arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 114 #define KVM_VM_CR0_ALWAYS_ON                                            \
 115         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 116 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 117         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 118          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 119
 120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 122
 123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 124
 125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 126
 127 /*
 128  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 129  * ple_gap:    upper bound on the amount of time between two successive
 130  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 131  *             According to test, this time is usually smaller than 128 cycles.
 132  * ple_window: upper bound on the amount of time a guest is allowed to execute
 133  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 134  *             less than 2^12 cycles
 135  * Time is measured based on a counter that runs at the same rate as the TSC,
 136  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 137  */
 138 #define KVM_VMX_DEFAULT_PLE_GAP           128
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 143                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 144
 145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 146 module_param(ple_gap, int, S_IRUGO);
 147
 148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 149 module_param(ple_window, int, S_IRUGO);
 150
 151 /* Default doubles per-vcpu window every exit. */
 152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 153 module_param(ple_window_grow, int, S_IRUGO);
 154
 155 /* Default resets per-vcpu window every exit to ple_window. */
 156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 157 module_param(ple_window_shrink, int, S_IRUGO);
 158
 159 /* Default is to compute the maximum so we can never overflow. */
 160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 161 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 module_param(ple_window_max, int, S_IRUGO);
 163
 164 extern const ulong vmx_return;
 165
 166 #define NR_AUTOLOAD_MSRS 8
 167 #define VMCS02_POOL_SIZE 1
 168
 169 struct vmcs {
 170         u32 revision_id;
 171         u32 abort;
 172         char data[0];
 173 };
 174
 175 /*
 176  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 177  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 178  * loaded on this CPU (so we can clear them if the CPU goes down).
 179  */
 180 struct loaded_vmcs {
 181         struct vmcs *vmcs;
 182         int cpu;
 183         int launched;
 184         struct list_head loaded_vmcss_on_cpu_link;
 185 };
 186
 187 struct shared_msr_entry {
 188         unsigned index;
 189         u64 data;
 190         u64 mask;
 191 };
 192
 193 /*
 194  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 195  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 196  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 197  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 198  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 199  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 200  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 201  * underlying hardware which will be used to run L2.
 202  * This structure is packed to ensure that its layout is identical across
 203  * machines (necessary for live migration).
 204  * If there are changes in this struct, VMCS12_REVISION must be changed.
 205  */
 206 typedef u64 natural_width;
 207 struct __packed vmcs12 {
 208         /* According to the Intel spec, a VMCS region must start with the
 209          * following two fields. Then follow implementation-specific data.
 210          */
 211         u32 revision_id;
 212         u32 abort;
 213
 214         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 215         u32 padding[7]; /* room for future expansion */
 216
 217         u64 io_bitmap_a;
 218         u64 io_bitmap_b;
 219         u64 msr_bitmap;
 220         u64 vm_exit_msr_store_addr;
 221         u64 vm_exit_msr_load_addr;
 222         u64 vm_entry_msr_load_addr;
 223         u64 tsc_offset;
 224         u64 virtual_apic_page_addr;
 225         u64 apic_access_addr;
 226         u64 posted_intr_desc_addr;
 227         u64 ept_pointer;
 228         u64 eoi_exit_bitmap0;
 229         u64 eoi_exit_bitmap1;
 230         u64 eoi_exit_bitmap2;
 231         u64 eoi_exit_bitmap3;
 232         u64 xss_exit_bitmap;
 233         u64 guest_physical_address;
 234         u64 vmcs_link_pointer;
 235         u64 guest_ia32_debugctl;
 236         u64 guest_ia32_pat;
 237         u64 guest_ia32_efer;
 238         u64 guest_ia32_perf_global_ctrl;
 239         u64 guest_pdptr0;
 240         u64 guest_pdptr1;
 241         u64 guest_pdptr2;
 242         u64 guest_pdptr3;
 243         u64 guest_bndcfgs;
 244         u64 host_ia32_pat;
 245         u64 host_ia32_efer;
 246         u64 host_ia32_perf_global_ctrl;
 247         u64 padding64[8]; /* room for future expansion */
 248         /*
 249          * To allow migration of L1 (complete with its L2 guests) between
 250          * machines of different natural widths (32 or 64 bit), we cannot have
 251          * unsigned long fields with no explict size. We use u64 (aliased
 252          * natural_width) instead. Luckily, x86 is little-endian.
 253          */
 254         natural_width cr0_guest_host_mask;
 255         natural_width cr4_guest_host_mask;
 256         natural_width cr0_read_shadow;
 257         natural_width cr4_read_shadow;
 258         natural_width cr3_target_value0;
 259         natural_width cr3_target_value1;
 260         natural_width cr3_target_value2;
 261         natural_width cr3_target_value3;
 262         natural_width exit_qualification;
 263         natural_width guest_linear_address;
 264         natural_width guest_cr0;
 265         natural_width guest_cr3;
 266         natural_width guest_cr4;
 267         natural_width guest_es_base;
 268         natural_width guest_cs_base;
 269         natural_width guest_ss_base;
 270         natural_width guest_ds_base;
 271         natural_width guest_fs_base;
 272         natural_width guest_gs_base;
 273         natural_width guest_ldtr_base;
 274         natural_width guest_tr_base;
 275         natural_width guest_gdtr_base;
 276         natural_width guest_idtr_base;
 277         natural_width guest_dr7;
 278         natural_width guest_rsp;
 279         natural_width guest_rip;
 280         natural_width guest_rflags;
 281         natural_width guest_pending_dbg_exceptions;
 282         natural_width guest_sysenter_esp;
 283         natural_width guest_sysenter_eip;
 284         natural_width host_cr0;
 285         natural_width host_cr3;
 286         natural_width host_cr4;
 287         natural_width host_fs_base;
 288         natural_width host_gs_base;
 289         natural_width host_tr_base;
 290         natural_width host_gdtr_base;
 291         natural_width host_idtr_base;
 292         natural_width host_ia32_sysenter_esp;
 293         natural_width host_ia32_sysenter_eip;
 294         natural_width host_rsp;
 295         natural_width host_rip;
 296         natural_width paddingl[8]; /* room for future expansion */
 297         u32 pin_based_vm_exec_control;
 298         u32 cpu_based_vm_exec_control;
 299         u32 exception_bitmap;
 300         u32 page_fault_error_code_mask;
 301         u32 page_fault_error_code_match;
 302         u32 cr3_target_count;
 303         u32 vm_exit_controls;
 304         u32 vm_exit_msr_store_count;
 305         u32 vm_exit_msr_load_count;
 306         u32 vm_entry_controls;
 307         u32 vm_entry_msr_load_count;
 308         u32 vm_entry_intr_info_field;
 309         u32 vm_entry_exception_error_code;
 310         u32 vm_entry_instruction_len;
 311         u32 tpr_threshold;
 312         u32 secondary_vm_exec_control;
 313         u32 vm_instruction_error;
 314         u32 vm_exit_reason;
 315         u32 vm_exit_intr_info;
 316         u32 vm_exit_intr_error_code;
 317         u32 idt_vectoring_info_field;
 318         u32 idt_vectoring_error_code;
 319         u32 vm_exit_instruction_len;
 320         u32 vmx_instruction_info;
 321         u32 guest_es_limit;
 322         u32 guest_cs_limit;
 323         u32 guest_ss_limit;
 324         u32 guest_ds_limit;
 325         u32 guest_fs_limit;
 326         u32 guest_gs_limit;
 327         u32 guest_ldtr_limit;
 328         u32 guest_tr_limit;
 329         u32 guest_gdtr_limit;
 330         u32 guest_idtr_limit;
 331         u32 guest_es_ar_bytes;
 332         u32 guest_cs_ar_bytes;
 333         u32 guest_ss_ar_bytes;
 334         u32 guest_ds_ar_bytes;
 335         u32 guest_fs_ar_bytes;
 336         u32 guest_gs_ar_bytes;
 337         u32 guest_ldtr_ar_bytes;
 338         u32 guest_tr_ar_bytes;
 339         u32 guest_interruptibility_info;
 340         u32 guest_activity_state;
 341         u32 guest_sysenter_cs;
 342         u32 host_ia32_sysenter_cs;
 343         u32 vmx_preemption_timer_value;
 344         u32 padding32[7]; /* room for future expansion */
 345         u16 virtual_processor_id;
 346         u16 posted_intr_nv;
 347         u16 guest_es_selector;
 348         u16 guest_cs_selector;
 349         u16 guest_ss_selector;
 350         u16 guest_ds_selector;
 351         u16 guest_fs_selector;
 352         u16 guest_gs_selector;
 353         u16 guest_ldtr_selector;
 354         u16 guest_tr_selector;
 355         u16 guest_intr_status;
 356         u16 host_es_selector;
 357         u16 host_cs_selector;
 358         u16 host_ss_selector;
 359         u16 host_ds_selector;
 360         u16 host_fs_selector;
 361         u16 host_gs_selector;
 362         u16 host_tr_selector;
 363 };
 364
 365 /*
 366  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 367  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 368  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 369  */
 370 #define VMCS12_REVISION 0x11e57ed0
 371
 372 /*
 373  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 374  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 375  * current implementation, 4K are reserved to avoid future complications.
 376  */
 377 #define VMCS12_SIZE 0x1000
 378
 379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 380 struct vmcs02_list {
 381         struct list_head list;
 382         gpa_t vmptr;
 383         struct loaded_vmcs vmcs02;
 384 };
 385
 386 /*
 387  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 388  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 389  */
 390 struct nested_vmx {
 391         /* Has the level1 guest done vmxon? */
 392         bool vmxon;
 393         gpa_t vmxon_ptr;
 394
 395         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 396         gpa_t current_vmptr;
 397         /* The host-usable pointer to the above */
 398         struct page *current_vmcs12_page;
 399         struct vmcs12 *current_vmcs12;
 400         struct vmcs *current_shadow_vmcs;
 401         /*
 402          * Indicates if the shadow vmcs must be updated with the
 403          * data hold by vmcs12
 404          */
 405         bool sync_shadow_vmcs;
 406
 407         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 408         struct list_head vmcs02_pool;
 409         int vmcs02_num;
 410         u64 vmcs01_tsc_offset;
 411         bool change_vmcs01_virtual_x2apic_mode;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601 };
 602
 603 enum segment_cache_field {
 604         SEG_FIELD_SEL = 0,
 605         SEG_FIELD_BASE = 1,
 606         SEG_FIELD_LIMIT = 2,
 607         SEG_FIELD_AR = 3,
 608
 609         SEG_FIELD_NR = 4
 610 };
 611
 612 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 613 {
 614         return container_of(vcpu, struct vcpu_vmx, vcpu);
 615 }
 616
 617 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 618 {
 619         return &(to_vmx(vcpu)->pi_desc);
 620 }
 621
 622 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 623 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 624 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 625                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 626
 627
 628 static unsigned long shadow_read_only_fields[] = {
 629         /*
 630          * We do NOT shadow fields that are modified when L0
 631          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 632          * VMXON...) executed by L1.
 633          * For example, VM_INSTRUCTION_ERROR is read
 634          * by L1 if a vmx instruction fails (part of the error path).
 635          * Note the code assumes this logic. If for some reason
 636          * we start shadowing these fields then we need to
 637          * force a shadow sync when L0 emulates vmx instructions
 638          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 639          * by nested_vmx_failValid)
 640          */
 641         VM_EXIT_REASON,
 642         VM_EXIT_INTR_INFO,
 643         VM_EXIT_INSTRUCTION_LEN,
 644         IDT_VECTORING_INFO_FIELD,
 645         IDT_VECTORING_ERROR_CODE,
 646         VM_EXIT_INTR_ERROR_CODE,
 647         EXIT_QUALIFICATION,
 648         GUEST_LINEAR_ADDRESS,
 649         GUEST_PHYSICAL_ADDRESS
 650 };
 651 static int max_shadow_read_only_fields =
 652         ARRAY_SIZE(shadow_read_only_fields);
 653
 654 static unsigned long shadow_read_write_fields[] = {
 655         TPR_THRESHOLD,
 656         GUEST_RIP,
 657         GUEST_RSP,
 658         GUEST_CR0,
 659         GUEST_CR3,
 660         GUEST_CR4,
 661         GUEST_INTERRUPTIBILITY_INFO,
 662         GUEST_RFLAGS,
 663         GUEST_CS_SELECTOR,
 664         GUEST_CS_AR_BYTES,
 665         GUEST_CS_LIMIT,
 666         GUEST_CS_BASE,
 667         GUEST_ES_BASE,
 668         GUEST_BNDCFGS,
 669         CR0_GUEST_HOST_MASK,
 670         CR0_READ_SHADOW,
 671         CR4_READ_SHADOW,
 672         TSC_OFFSET,
 673         EXCEPTION_BITMAP,
 674         CPU_BASED_VM_EXEC_CONTROL,
 675         VM_ENTRY_EXCEPTION_ERROR_CODE,
 676         VM_ENTRY_INTR_INFO_FIELD,
 677         VM_ENTRY_INSTRUCTION_LEN,
 678         VM_ENTRY_EXCEPTION_ERROR_CODE,
 679         HOST_FS_BASE,
 680         HOST_GS_BASE,
 681         HOST_FS_SELECTOR,
 682         HOST_GS_SELECTOR
 683 };
 684 static int max_shadow_read_write_fields =
 685         ARRAY_SIZE(shadow_read_write_fields);
 686
 687 static const unsigned short vmcs_field_to_offset_table[] = {
 688         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 689         FIELD(POSTED_INTR_NV, posted_intr_nv),
 690         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 691         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 692         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 693         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 694         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 695         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 696         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 697         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 698         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 699         FIELD(HOST_ES_SELECTOR, host_es_selector),
 700         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 701         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 702         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 703         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 704         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 705         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 706         FIELD64(IO_BITMAP_A, io_bitmap_a),
 707         FIELD64(IO_BITMAP_B, io_bitmap_b),
 708         FIELD64(MSR_BITMAP, msr_bitmap),
 709         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 710         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 711         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 712         FIELD64(TSC_OFFSET, tsc_offset),
 713         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 714         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 715         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 716         FIELD64(EPT_POINTER, ept_pointer),
 717         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 718         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 719         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 720         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 721         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 722         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 723         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 724         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 725         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 726         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 727         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 728         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 729         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 730         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 731         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 732         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 733         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 734         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 735         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 736         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 737         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 738         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 740         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 741         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 742         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 743         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 744         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 745         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 746         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 747         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 748         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 749         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 750         FIELD(TPR_THRESHOLD, tpr_threshold),
 751         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 752         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 753         FIELD(VM_EXIT_REASON, vm_exit_reason),
 754         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 755         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 756         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 757         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 758         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 759         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 760         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 761         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 762         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 763         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 764         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 765         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 766         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 767         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 768         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 769         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 770         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 771         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 772         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 773         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 774         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 775         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 776         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 777         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 778         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 779         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 780         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 781         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 782         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 783         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 784         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 785         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 786         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 787         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 788         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 789         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 790         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 791         FIELD(EXIT_QUALIFICATION, exit_qualification),
 792         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 793         FIELD(GUEST_CR0, guest_cr0),
 794         FIELD(GUEST_CR3, guest_cr3),
 795         FIELD(GUEST_CR4, guest_cr4),
 796         FIELD(GUEST_ES_BASE, guest_es_base),
 797         FIELD(GUEST_CS_BASE, guest_cs_base),
 798         FIELD(GUEST_SS_BASE, guest_ss_base),
 799         FIELD(GUEST_DS_BASE, guest_ds_base),
 800         FIELD(GUEST_FS_BASE, guest_fs_base),
 801         FIELD(GUEST_GS_BASE, guest_gs_base),
 802         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 803         FIELD(GUEST_TR_BASE, guest_tr_base),
 804         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 805         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 806         FIELD(GUEST_DR7, guest_dr7),
 807         FIELD(GUEST_RSP, guest_rsp),
 808         FIELD(GUEST_RIP, guest_rip),
 809         FIELD(GUEST_RFLAGS, guest_rflags),
 810         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 811         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 812         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 813         FIELD(HOST_CR0, host_cr0),
 814         FIELD(HOST_CR3, host_cr3),
 815         FIELD(HOST_CR4, host_cr4),
 816         FIELD(HOST_FS_BASE, host_fs_base),
 817         FIELD(HOST_GS_BASE, host_gs_base),
 818         FIELD(HOST_TR_BASE, host_tr_base),
 819         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 820         FIELD(HOST_IDTR_BASE, host_idtr_base),
 821         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 822         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 823         FIELD(HOST_RSP, host_rsp),
 824         FIELD(HOST_RIP, host_rip),
 825 };
 826
 827 static inline short vmcs_field_to_offset(unsigned long field)
 828 {
 829         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 830
 831         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 832             vmcs_field_to_offset_table[field] == 0)
 833                 return -ENOENT;
 834
 835         return vmcs_field_to_offset_table[field];
 836 }
 837
 838 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 839 {
 840         return to_vmx(vcpu)->nested.current_vmcs12;
 841 }
 842
 843 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 844 {
 845         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 846         if (is_error_page(page))
 847                 return NULL;
 848
 849         return page;
 850 }
 851
 852 static void nested_release_page(struct page *page)
 853 {
 854         kvm_release_page_dirty(page);
 855 }
 856
 857 static void nested_release_page_clean(struct page *page)
 858 {
 859         kvm_release_page_clean(page);
 860 }
 861
 862 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 863 static u64 construct_eptp(unsigned long root_hpa);
 864 static void kvm_cpu_vmxon(u64 addr);
 865 static void kvm_cpu_vmxoff(void);
 866 static bool vmx_mpx_supported(void);
 867 static bool vmx_xsaves_supported(void);
 868 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 869 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 870 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 871                             struct kvm_segment *var, int seg);
 872 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 873                             struct kvm_segment *var, int seg);
 874 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 875 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 876 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 877 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 878 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 879 static int alloc_identity_pagetable(struct kvm *kvm);
 880
 881 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 882 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 883 /*
 884  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 885  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 886  */
 887 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 888 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 889
 890 /*
 891  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 892  * can find which vCPU should be waken up.
 893  */
 894 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 895 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 896
 897 static unsigned long *vmx_io_bitmap_a;
 898 static unsigned long *vmx_io_bitmap_b;
 899 static unsigned long *vmx_msr_bitmap_legacy;
 900 static unsigned long *vmx_msr_bitmap_longmode;
 901 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 902 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 903 static unsigned long *vmx_msr_bitmap_nested;
 904 static unsigned long *vmx_vmread_bitmap;
 905 static unsigned long *vmx_vmwrite_bitmap;
 906
 907 static bool cpu_has_load_ia32_efer;
 908 static bool cpu_has_load_perf_global_ctrl;
 909
 910 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 911 static DEFINE_SPINLOCK(vmx_vpid_lock);
 912
 913 static struct vmcs_config {
 914         int size;
 915         int order;
 916         u32 revision_id;
 917         u32 pin_based_exec_ctrl;
 918         u32 cpu_based_exec_ctrl;
 919         u32 cpu_based_2nd_exec_ctrl;
 920         u32 vmexit_ctrl;
 921         u32 vmentry_ctrl;
 922 } vmcs_config;
 923
 924 static struct vmx_capability {
 925         u32 ept;
 926         u32 vpid;
 927 } vmx_capability;
 928
 929 #define VMX_SEGMENT_FIELD(seg)                                  \
 930         [VCPU_SREG_##seg] = {                                   \
 931                 .selector = GUEST_##seg##_SELECTOR,             \
 932                 .base = GUEST_##seg##_BASE,                     \
 933                 .limit = GUEST_##seg##_LIMIT,                   \
 934                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 935         }
 936
 937 static const struct kvm_vmx_segment_field {
 938         unsigned selector;
 939         unsigned base;
 940         unsigned limit;
 941         unsigned ar_bytes;
 942 } kvm_vmx_segment_fields[] = {
 943         VMX_SEGMENT_FIELD(CS),
 944         VMX_SEGMENT_FIELD(DS),
 945         VMX_SEGMENT_FIELD(ES),
 946         VMX_SEGMENT_FIELD(FS),
 947         VMX_SEGMENT_FIELD(GS),
 948         VMX_SEGMENT_FIELD(SS),
 949         VMX_SEGMENT_FIELD(TR),
 950         VMX_SEGMENT_FIELD(LDTR),
 951 };
 952
 953 static u64 host_efer;
 954
 955 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 956
 957 /*
 958  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 959  * away by decrementing the array size.
 960  */
 961 static const u32 vmx_msr_index[] = {
 962 #ifdef CONFIG_X86_64
 963         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 964 #endif
 965         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 966 };
 967
 968 static inline bool is_page_fault(u32 intr_info)
 969 {
 970         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 971                              INTR_INFO_VALID_MASK)) ==
 972                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 973 }
 974
 975 static inline bool is_no_device(u32 intr_info)
 976 {
 977         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 978                              INTR_INFO_VALID_MASK)) ==
 979                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 980 }
 981
 982 static inline bool is_invalid_opcode(u32 intr_info)
 983 {
 984         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 985                              INTR_INFO_VALID_MASK)) ==
 986                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 987 }
 988
 989 static inline bool is_external_interrupt(u32 intr_info)
 990 {
 991         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 992                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 993 }
 994
 995 static inline bool is_machine_check(u32 intr_info)
 996 {
 997         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 998                              INTR_INFO_VALID_MASK)) ==
 999                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1000 }
1001
1002 static inline bool cpu_has_vmx_msr_bitmap(void)
1003 {
1004         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1005 }
1006
1007 static inline bool cpu_has_vmx_tpr_shadow(void)
1008 {
1009         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1010 }
1011
1012 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1013 {
1014         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1015 }
1016
1017 static inline bool cpu_has_secondary_exec_ctrls(void)
1018 {
1019         return vmcs_config.cpu_based_exec_ctrl &
1020                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1021 }
1022
1023 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1024 {
1025         return vmcs_config.cpu_based_2nd_exec_ctrl &
1026                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1027 }
1028
1029 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1030 {
1031         return vmcs_config.cpu_based_2nd_exec_ctrl &
1032                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1033 }
1034
1035 static inline bool cpu_has_vmx_apic_register_virt(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1039 }
1040
1041 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1042 {
1043         return vmcs_config.cpu_based_2nd_exec_ctrl &
1044                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1045 }
1046
1047 static inline bool cpu_has_vmx_posted_intr(void)
1048 {
1049         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1050                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1051 }
1052
1053 static inline bool cpu_has_vmx_apicv(void)
1054 {
1055         return cpu_has_vmx_apic_register_virt() &&
1056                 cpu_has_vmx_virtual_intr_delivery() &&
1057                 cpu_has_vmx_posted_intr();
1058 }
1059
1060 static inline bool cpu_has_vmx_flexpriority(void)
1061 {
1062         return cpu_has_vmx_tpr_shadow() &&
1063                 cpu_has_vmx_virtualize_apic_accesses();
1064 }
1065
1066 static inline bool cpu_has_vmx_ept_execute_only(void)
1067 {
1068         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1069 }
1070
1071 static inline bool cpu_has_vmx_ept_2m_page(void)
1072 {
1073         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1074 }
1075
1076 static inline bool cpu_has_vmx_ept_1g_page(void)
1077 {
1078         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1079 }
1080
1081 static inline bool cpu_has_vmx_ept_4levels(void)
1082 {
1083         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1084 }
1085
1086 static inline bool cpu_has_vmx_ept_ad_bits(void)
1087 {
1088         return vmx_capability.ept & VMX_EPT_AD_BIT;
1089 }
1090
1091 static inline bool cpu_has_vmx_invept_context(void)
1092 {
1093         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1094 }
1095
1096 static inline bool cpu_has_vmx_invept_global(void)
1097 {
1098         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1099 }
1100
1101 static inline bool cpu_has_vmx_invvpid_single(void)
1102 {
1103         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1104 }
1105
1106 static inline bool cpu_has_vmx_invvpid_global(void)
1107 {
1108         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1109 }
1110
1111 static inline bool cpu_has_vmx_ept(void)
1112 {
1113         return vmcs_config.cpu_based_2nd_exec_ctrl &
1114                 SECONDARY_EXEC_ENABLE_EPT;
1115 }
1116
1117 static inline bool cpu_has_vmx_unrestricted_guest(void)
1118 {
1119         return vmcs_config.cpu_based_2nd_exec_ctrl &
1120                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1121 }
1122
1123 static inline bool cpu_has_vmx_ple(void)
1124 {
1125         return vmcs_config.cpu_based_2nd_exec_ctrl &
1126                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1127 }
1128
1129 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1130 {
1131         return flexpriority_enabled && lapic_in_kernel(vcpu);
1132 }
1133
1134 static inline bool cpu_has_vmx_vpid(void)
1135 {
1136         return vmcs_config.cpu_based_2nd_exec_ctrl &
1137                 SECONDARY_EXEC_ENABLE_VPID;
1138 }
1139
1140 static inline bool cpu_has_vmx_rdtscp(void)
1141 {
1142         return vmcs_config.cpu_based_2nd_exec_ctrl &
1143                 SECONDARY_EXEC_RDTSCP;
1144 }
1145
1146 static inline bool cpu_has_vmx_invpcid(void)
1147 {
1148         return vmcs_config.cpu_based_2nd_exec_ctrl &
1149                 SECONDARY_EXEC_ENABLE_INVPCID;
1150 }
1151
1152 static inline bool cpu_has_virtual_nmis(void)
1153 {
1154         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1155 }
1156
1157 static inline bool cpu_has_vmx_wbinvd_exit(void)
1158 {
1159         return vmcs_config.cpu_based_2nd_exec_ctrl &
1160                 SECONDARY_EXEC_WBINVD_EXITING;
1161 }
1162
1163 static inline bool cpu_has_vmx_shadow_vmcs(void)
1164 {
1165         u64 vmx_msr;
1166         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1167         /* check if the cpu supports writing r/o exit information fields */
1168         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1169                 return false;
1170
1171         return vmcs_config.cpu_based_2nd_exec_ctrl &
1172                 SECONDARY_EXEC_SHADOW_VMCS;
1173 }
1174
1175 static inline bool cpu_has_vmx_pml(void)
1176 {
1177         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1178 }
1179
1180 static inline bool cpu_has_vmx_tsc_scaling(void)
1181 {
1182         return vmcs_config.cpu_based_2nd_exec_ctrl &
1183                 SECONDARY_EXEC_TSC_SCALING;
1184 }
1185
1186 static inline bool report_flexpriority(void)
1187 {
1188         return flexpriority_enabled;
1189 }
1190
1191 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1192 {
1193         return vmcs12->cpu_based_vm_exec_control & bit;
1194 }
1195
1196 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1197 {
1198         return (vmcs12->cpu_based_vm_exec_control &
1199                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1200                 (vmcs12->secondary_vm_exec_control & bit);
1201 }
1202
1203 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1204 {
1205         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1206 }
1207
1208 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1209 {
1210         return vmcs12->pin_based_vm_exec_control &
1211                 PIN_BASED_VMX_PREEMPTION_TIMER;
1212 }
1213
1214 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1215 {
1216         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1217 }
1218
1219 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1220 {
1221         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1222                 vmx_xsaves_supported();
1223 }
1224
1225 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1226 {
1227         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1228 }
1229
1230 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1231 {
1232         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1233 }
1234
1235 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1236 {
1237         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1238 }
1239
1240 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1241 {
1242         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1243 }
1244
1245 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1246 {
1247         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1248 }
1249
1250 static inline bool is_nmi(u32 intr_info)
1251 {
1252         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1253                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1254 }
1255
1256 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1257                               u32 exit_intr_info,
1258                               unsigned long exit_qualification);
1259 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1260                         struct vmcs12 *vmcs12,
1261                         u32 reason, unsigned long qualification);
1262
1263 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1264 {
1265         int i;
1266
1267         for (i = 0; i < vmx->nmsrs; ++i)
1268                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1269                         return i;
1270         return -1;
1271 }
1272
1273 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1274 {
1275     struct {
1276         u64 vpid : 16;
1277         u64 rsvd : 48;
1278         u64 gva;
1279     } operand = { vpid, 0, gva };
1280
1281     asm volatile (__ex(ASM_VMX_INVVPID)
1282                   /* CF==1 or ZF==1 --> rc = -1 */
1283                   "; ja 1f ; ud2 ; 1:"
1284                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1285 }
1286
1287 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1288 {
1289         struct {
1290                 u64 eptp, gpa;
1291         } operand = {eptp, gpa};
1292
1293         asm volatile (__ex(ASM_VMX_INVEPT)
1294                         /* CF==1 or ZF==1 --> rc = -1 */
1295                         "; ja 1f ; ud2 ; 1:\n"
1296                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1297 }
1298
1299 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1300 {
1301         int i;
1302
1303         i = __find_msr_index(vmx, msr);
1304         if (i >= 0)
1305                 return &vmx->guest_msrs[i];
1306         return NULL;
1307 }
1308
1309 static void vmcs_clear(struct vmcs *vmcs)
1310 {
1311         u64 phys_addr = __pa(vmcs);
1312         u8 error;
1313
1314         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1315                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1316                       : "cc", "memory");
1317         if (error)
1318                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1319                        vmcs, phys_addr);
1320 }
1321
1322 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1323 {
1324         vmcs_clear(loaded_vmcs->vmcs);
1325         loaded_vmcs->cpu = -1;
1326         loaded_vmcs->launched = 0;
1327 }
1328
1329 static void vmcs_load(struct vmcs *vmcs)
1330 {
1331         u64 phys_addr = __pa(vmcs);
1332         u8 error;
1333
1334         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1335                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1336                         : "cc", "memory");
1337         if (error)
1338                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1339                        vmcs, phys_addr);
1340 }
1341
1342 #ifdef CONFIG_KEXEC_CORE
1343 /*
1344  * This bitmap is used to indicate whether the vmclear
1345  * operation is enabled on all cpus. All disabled by
1346  * default.
1347  */
1348 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1349
1350 static inline void crash_enable_local_vmclear(int cpu)
1351 {
1352         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1353 }
1354
1355 static inline void crash_disable_local_vmclear(int cpu)
1356 {
1357         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1358 }
1359
1360 static inline int crash_local_vmclear_enabled(int cpu)
1361 {
1362         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1363 }
1364
1365 static void crash_vmclear_local_loaded_vmcss(void)
1366 {
1367         int cpu = raw_smp_processor_id();
1368         struct loaded_vmcs *v;
1369
1370         if (!crash_local_vmclear_enabled(cpu))
1371                 return;
1372
1373         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1374                             loaded_vmcss_on_cpu_link)
1375                 vmcs_clear(v->vmcs);
1376 }
1377 #else
1378 static inline void crash_enable_local_vmclear(int cpu) { }
1379 static inline void crash_disable_local_vmclear(int cpu) { }
1380 #endif /* CONFIG_KEXEC_CORE */
1381
1382 static void __loaded_vmcs_clear(void *arg)
1383 {
1384         struct loaded_vmcs *loaded_vmcs = arg;
1385         int cpu = raw_smp_processor_id();
1386
1387         if (loaded_vmcs->cpu != cpu)
1388                 return; /* vcpu migration can race with cpu offline */
1389         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1390                 per_cpu(current_vmcs, cpu) = NULL;
1391         crash_disable_local_vmclear(cpu);
1392         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1393
1394         /*
1395          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1396          * is before setting loaded_vmcs->vcpu to -1 which is done in
1397          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1398          * then adds the vmcs into percpu list before it is deleted.
1399          */
1400         smp_wmb();
1401
1402         loaded_vmcs_init(loaded_vmcs);
1403         crash_enable_local_vmclear(cpu);
1404 }
1405
1406 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1407 {
1408         int cpu = loaded_vmcs->cpu;
1409
1410         if (cpu != -1)
1411                 smp_call_function_single(cpu,
1412                          __loaded_vmcs_clear, loaded_vmcs, 1);
1413 }
1414
1415 static inline void vpid_sync_vcpu_single(int vpid)
1416 {
1417         if (vpid == 0)
1418                 return;
1419
1420         if (cpu_has_vmx_invvpid_single())
1421                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1422 }
1423
1424 static inline void vpid_sync_vcpu_global(void)
1425 {
1426         if (cpu_has_vmx_invvpid_global())
1427                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1428 }
1429
1430 static inline void vpid_sync_context(int vpid)
1431 {
1432         if (cpu_has_vmx_invvpid_single())
1433                 vpid_sync_vcpu_single(vpid);
1434         else
1435                 vpid_sync_vcpu_global();
1436 }
1437
1438 static inline void ept_sync_global(void)
1439 {
1440         if (cpu_has_vmx_invept_global())
1441                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1442 }
1443
1444 static inline void ept_sync_context(u64 eptp)
1445 {
1446         if (enable_ept) {
1447                 if (cpu_has_vmx_invept_context())
1448                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1449                 else
1450                         ept_sync_global();
1451         }
1452 }
1453
1454 static __always_inline unsigned long vmcs_readl(unsigned long field)
1455 {
1456         unsigned long value;
1457
1458         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1459                       : "=a"(value) : "d"(field) : "cc");
1460         return value;
1461 }
1462
1463 static __always_inline u16 vmcs_read16(unsigned long field)
1464 {
1465         return vmcs_readl(field);
1466 }
1467
1468 static __always_inline u32 vmcs_read32(unsigned long field)
1469 {
1470         return vmcs_readl(field);
1471 }
1472
1473 static __always_inline u64 vmcs_read64(unsigned long field)
1474 {
1475 #ifdef CONFIG_X86_64
1476         return vmcs_readl(field);
1477 #else
1478         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1479 #endif
1480 }
1481
1482 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1483 {
1484         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1485                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1486         dump_stack();
1487 }
1488
1489 static void vmcs_writel(unsigned long field, unsigned long value)
1490 {
1491         u8 error;
1492
1493         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1494                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1495         if (unlikely(error))
1496                 vmwrite_error(field, value);
1497 }
1498
1499 static void vmcs_write16(unsigned long field, u16 value)
1500 {
1501         vmcs_writel(field, value);
1502 }
1503
1504 static void vmcs_write32(unsigned long field, u32 value)
1505 {
1506         vmcs_writel(field, value);
1507 }
1508
1509 static void vmcs_write64(unsigned long field, u64 value)
1510 {
1511         vmcs_writel(field, value);
1512 #ifndef CONFIG_X86_64
1513         asm volatile ("");
1514         vmcs_writel(field+1, value >> 32);
1515 #endif
1516 }
1517
1518 static void vmcs_clear_bits(unsigned long field, u32 mask)
1519 {
1520         vmcs_writel(field, vmcs_readl(field) & ~mask);
1521 }
1522
1523 static void vmcs_set_bits(unsigned long field, u32 mask)
1524 {
1525         vmcs_writel(field, vmcs_readl(field) | mask);
1526 }
1527
1528 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1529 {
1530         vmcs_write32(VM_ENTRY_CONTROLS, val);
1531         vmx->vm_entry_controls_shadow = val;
1532 }
1533
1534 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1535 {
1536         if (vmx->vm_entry_controls_shadow != val)
1537                 vm_entry_controls_init(vmx, val);
1538 }
1539
1540 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1541 {
1542         return vmx->vm_entry_controls_shadow;
1543 }
1544
1545
1546 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1547 {
1548         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1549 }
1550
1551 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1552 {
1553         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1554 }
1555
1556 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1557 {
1558         vmcs_write32(VM_EXIT_CONTROLS, val);
1559         vmx->vm_exit_controls_shadow = val;
1560 }
1561
1562 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1563 {
1564         if (vmx->vm_exit_controls_shadow != val)
1565                 vm_exit_controls_init(vmx, val);
1566 }
1567
1568 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1569 {
1570         return vmx->vm_exit_controls_shadow;
1571 }
1572
1573
1574 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1575 {
1576         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1577 }
1578
1579 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1580 {
1581         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1582 }
1583
1584 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1585 {
1586         vmx->segment_cache.bitmask = 0;
1587 }
1588
1589 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1590                                        unsigned field)
1591 {
1592         bool ret;
1593         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1594
1595         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1596                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1597                 vmx->segment_cache.bitmask = 0;
1598         }
1599         ret = vmx->segment_cache.bitmask & mask;
1600         vmx->segment_cache.bitmask |= mask;
1601         return ret;
1602 }
1603
1604 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1605 {
1606         u16 *p = &vmx->segment_cache.seg[seg].selector;
1607
1608         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1609                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1610         return *p;
1611 }
1612
1613 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1614 {
1615         ulong *p = &vmx->segment_cache.seg[seg].base;
1616
1617         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1618                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1619         return *p;
1620 }
1621
1622 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1623 {
1624         u32 *p = &vmx->segment_cache.seg[seg].limit;
1625
1626         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1627                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1628         return *p;
1629 }
1630
1631 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1632 {
1633         u32 *p = &vmx->segment_cache.seg[seg].ar;
1634
1635         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1636                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1637         return *p;
1638 }
1639
1640 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1641 {
1642         u32 eb;
1643
1644         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1645              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1646         if ((vcpu->guest_debug &
1647              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1648             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1649                 eb |= 1u << BP_VECTOR;
1650         if (to_vmx(vcpu)->rmode.vm86_active)
1651                 eb = ~0;
1652         if (enable_ept)
1653                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1654         if (vcpu->fpu_active)
1655                 eb &= ~(1u << NM_VECTOR);
1656
1657         /* When we are running a nested L2 guest and L1 specified for it a
1658          * certain exception bitmap, we must trap the same exceptions and pass
1659          * them to L1. When running L2, we will only handle the exceptions
1660          * specified above if L1 did not want them.
1661          */
1662         if (is_guest_mode(vcpu))
1663                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1664
1665         vmcs_write32(EXCEPTION_BITMAP, eb);
1666 }
1667
1668 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1669                 unsigned long entry, unsigned long exit)
1670 {
1671         vm_entry_controls_clearbit(vmx, entry);
1672         vm_exit_controls_clearbit(vmx, exit);
1673 }
1674
1675 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1676 {
1677         unsigned i;
1678         struct msr_autoload *m = &vmx->msr_autoload;
1679
1680         switch (msr) {
1681         case MSR_EFER:
1682                 if (cpu_has_load_ia32_efer) {
1683                         clear_atomic_switch_msr_special(vmx,
1684                                         VM_ENTRY_LOAD_IA32_EFER,
1685                                         VM_EXIT_LOAD_IA32_EFER);
1686                         return;
1687                 }
1688                 break;
1689         case MSR_CORE_PERF_GLOBAL_CTRL:
1690                 if (cpu_has_load_perf_global_ctrl) {
1691                         clear_atomic_switch_msr_special(vmx,
1692                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1693                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1694                         return;
1695                 }
1696                 break;
1697         }
1698
1699         for (i = 0; i < m->nr; ++i)
1700                 if (m->guest[i].index == msr)
1701                         break;
1702
1703         if (i == m->nr)
1704                 return;
1705         --m->nr;
1706         m->guest[i] = m->guest[m->nr];
1707         m->host[i] = m->host[m->nr];
1708         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1709         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1710 }
1711
1712 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1713                 unsigned long entry, unsigned long exit,
1714                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1715                 u64 guest_val, u64 host_val)
1716 {
1717         vmcs_write64(guest_val_vmcs, guest_val);
1718         vmcs_write64(host_val_vmcs, host_val);
1719         vm_entry_controls_setbit(vmx, entry);
1720         vm_exit_controls_setbit(vmx, exit);
1721 }
1722
1723 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1724                                   u64 guest_val, u64 host_val)
1725 {
1726         unsigned i;
1727         struct msr_autoload *m = &vmx->msr_autoload;
1728
1729         switch (msr) {
1730         case MSR_EFER:
1731                 if (cpu_has_load_ia32_efer) {
1732                         add_atomic_switch_msr_special(vmx,
1733                                         VM_ENTRY_LOAD_IA32_EFER,
1734                                         VM_EXIT_LOAD_IA32_EFER,
1735                                         GUEST_IA32_EFER,
1736                                         HOST_IA32_EFER,
1737                                         guest_val, host_val);
1738                         return;
1739                 }
1740                 break;
1741         case MSR_CORE_PERF_GLOBAL_CTRL:
1742                 if (cpu_has_load_perf_global_ctrl) {
1743                         add_atomic_switch_msr_special(vmx,
1744                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1745                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1746                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1747                                         HOST_IA32_PERF_GLOBAL_CTRL,
1748                                         guest_val, host_val);
1749                         return;
1750                 }
1751                 break;
1752         case MSR_IA32_PEBS_ENABLE:
1753                 /* PEBS needs a quiescent period after being disabled (to write
1754                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1755                  * provide that period, so a CPU could write host's record into
1756                  * guest's memory.
1757                  */
1758                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1759         }
1760
1761         for (i = 0; i < m->nr; ++i)
1762                 if (m->guest[i].index == msr)
1763                         break;
1764
1765         if (i == NR_AUTOLOAD_MSRS) {
1766                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1767                                 "Can't add msr %x\n", msr);
1768                 return;
1769         } else if (i == m->nr) {
1770                 ++m->nr;
1771                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1772                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1773         }
1774
1775         m->guest[i].index = msr;
1776         m->guest[i].value = guest_val;
1777         m->host[i].index = msr;
1778         m->host[i].value = host_val;
1779 }
1780
1781 static void reload_tss(void)
1782 {
1783         /*
1784          * VT restores TR but not its size.  Useless.
1785          */
1786         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1787         struct desc_struct *descs;
1788
1789         descs = (void *)gdt->address;
1790         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1791         load_TR_desc();
1792 }
1793
1794 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1795 {
1796         u64 guest_efer = vmx->vcpu.arch.efer;
1797         u64 ignore_bits = 0;
1798
1799         if (!enable_ept) {
1800                 /*
1801                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1802                  * host CPUID is more efficient than testing guest CPUID
1803                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1804                  */
1805                 if (boot_cpu_has(X86_FEATURE_SMEP))
1806                         guest_efer |= EFER_NX;
1807                 else if (!(guest_efer & EFER_NX))
1808                         ignore_bits |= EFER_NX;
1809         }
1810
1811         /*
1812          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1813          */
1814         ignore_bits |= EFER_SCE;
1815 #ifdef CONFIG_X86_64
1816         ignore_bits |= EFER_LMA | EFER_LME;
1817         /* SCE is meaningful only in long mode on Intel */
1818         if (guest_efer & EFER_LMA)
1819                 ignore_bits &= ~(u64)EFER_SCE;
1820 #endif
1821
1822         clear_atomic_switch_msr(vmx, MSR_EFER);
1823
1824         /*
1825          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1826          * On CPUs that support "load IA32_EFER", always switch EFER
1827          * atomically, since it's faster than switching it manually.
1828          */
1829         if (cpu_has_load_ia32_efer ||
1830             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1831                 if (!(guest_efer & EFER_LMA))
1832                         guest_efer &= ~EFER_LME;
1833                 if (guest_efer != host_efer)
1834                         add_atomic_switch_msr(vmx, MSR_EFER,
1835                                               guest_efer, host_efer);
1836                 return false;
1837         } else {
1838                 guest_efer &= ~ignore_bits;
1839                 guest_efer |= host_efer & ignore_bits;
1840
1841                 vmx->guest_msrs[efer_offset].data = guest_efer;
1842                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1843
1844                 return true;
1845         }
1846 }
1847
1848 static unsigned long segment_base(u16 selector)
1849 {
1850         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1851         struct desc_struct *d;
1852         unsigned long table_base;
1853         unsigned long v;
1854
1855         if (!(selector & ~3))
1856                 return 0;
1857
1858         table_base = gdt->address;
1859
1860         if (selector & 4) {           /* from ldt */
1861                 u16 ldt_selector = kvm_read_ldt();
1862
1863                 if (!(ldt_selector & ~3))
1864                         return 0;
1865
1866                 table_base = segment_base(ldt_selector);
1867         }
1868         d = (struct desc_struct *)(table_base + (selector & ~7));
1869         v = get_desc_base(d);
1870 #ifdef CONFIG_X86_64
1871        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1872                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1873 #endif
1874         return v;
1875 }
1876
1877 static inline unsigned long kvm_read_tr_base(void)
1878 {
1879         u16 tr;
1880         asm("str %0" : "=g"(tr));
1881         return segment_base(tr);
1882 }
1883
1884 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1885 {
1886         struct vcpu_vmx *vmx = to_vmx(vcpu);
1887         int i;
1888
1889         if (vmx->host_state.loaded)
1890                 return;
1891
1892         vmx->host_state.loaded = 1;
1893         /*
1894          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1895          * allow segment selectors with cpl > 0 or ti == 1.
1896          */
1897         vmx->host_state.ldt_sel = kvm_read_ldt();
1898         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1899         savesegment(fs, vmx->host_state.fs_sel);
1900         if (!(vmx->host_state.fs_sel & 7)) {
1901                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1902                 vmx->host_state.fs_reload_needed = 0;
1903         } else {
1904                 vmcs_write16(HOST_FS_SELECTOR, 0);
1905                 vmx->host_state.fs_reload_needed = 1;
1906         }
1907         savesegment(gs, vmx->host_state.gs_sel);
1908         if (!(vmx->host_state.gs_sel & 7))
1909                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1910         else {
1911                 vmcs_write16(HOST_GS_SELECTOR, 0);
1912                 vmx->host_state.gs_ldt_reload_needed = 1;
1913         }
1914
1915 #ifdef CONFIG_X86_64
1916         savesegment(ds, vmx->host_state.ds_sel);
1917         savesegment(es, vmx->host_state.es_sel);
1918 #endif
1919
1920 #ifdef CONFIG_X86_64
1921         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1922         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1923 #else
1924         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1925         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1926 #endif
1927
1928 #ifdef CONFIG_X86_64
1929         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1930         if (is_long_mode(&vmx->vcpu))
1931                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1932 #endif
1933         if (boot_cpu_has(X86_FEATURE_MPX))
1934                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1935         for (i = 0; i < vmx->save_nmsrs; ++i)
1936                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1937                                    vmx->guest_msrs[i].data,
1938                                    vmx->guest_msrs[i].mask);
1939 }
1940
1941 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1942 {
1943         if (!vmx->host_state.loaded)
1944                 return;
1945
1946         ++vmx->vcpu.stat.host_state_reload;
1947         vmx->host_state.loaded = 0;
1948 #ifdef CONFIG_X86_64
1949         if (is_long_mode(&vmx->vcpu))
1950                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1951 #endif
1952         if (vmx->host_state.gs_ldt_reload_needed) {
1953                 kvm_load_ldt(vmx->host_state.ldt_sel);
1954 #ifdef CONFIG_X86_64
1955                 load_gs_index(vmx->host_state.gs_sel);
1956 #else
1957                 loadsegment(gs, vmx->host_state.gs_sel);
1958 #endif
1959         }
1960         if (vmx->host_state.fs_reload_needed)
1961                 loadsegment(fs, vmx->host_state.fs_sel);
1962 #ifdef CONFIG_X86_64
1963         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1964                 loadsegment(ds, vmx->host_state.ds_sel);
1965                 loadsegment(es, vmx->host_state.es_sel);
1966         }
1967 #endif
1968         reload_tss();
1969 #ifdef CONFIG_X86_64
1970         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1971 #endif
1972         if (vmx->host_state.msr_host_bndcfgs)
1973                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1974         /*
1975          * If the FPU is not active (through the host task or
1976          * the guest vcpu), then restore the cr0.TS bit.
1977          */
1978         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1979                 stts();
1980         load_gdt(this_cpu_ptr(&host_gdt));
1981 }
1982
1983 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1984 {
1985         preempt_disable();
1986         __vmx_load_host_state(vmx);
1987         preempt_enable();
1988 }
1989
1990 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1991 {
1992         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1993         struct pi_desc old, new;
1994         unsigned int dest;
1995
1996         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1997                 !irq_remapping_cap(IRQ_POSTING_CAP))
1998                 return;
1999
2000         do {
2001                 old.control = new.control = pi_desc->control;
2002
2003                 /*
2004                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2005                  * are two possible cases:
2006                  * 1. After running 'pre_block', context switch
2007                  *    happened. For this case, 'sn' was set in
2008                  *    vmx_vcpu_put(), so we need to clear it here.
2009                  * 2. After running 'pre_block', we were blocked,
2010                  *    and woken up by some other guy. For this case,
2011                  *    we don't need to do anything, 'pi_post_block'
2012                  *    will do everything for us. However, we cannot
2013                  *    check whether it is case #1 or case #2 here
2014                  *    (maybe, not needed), so we also clear sn here,
2015                  *    I think it is not a big deal.
2016                  */
2017                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2018                         if (vcpu->cpu != cpu) {
2019                                 dest = cpu_physical_id(cpu);
2020
2021                                 if (x2apic_enabled())
2022                                         new.ndst = dest;
2023                                 else
2024                                         new.ndst = (dest << 8) & 0xFF00;
2025                         }
2026
2027                         /* set 'NV' to 'notification vector' */
2028                         new.nv = POSTED_INTR_VECTOR;
2029                 }
2030
2031                 /* Allow posting non-urgent interrupts */
2032                 new.sn = 0;
2033         } while (cmpxchg(&pi_desc->control, old.control,
2034                         new.control) != old.control);
2035 }
2036 /*
2037  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2038  * vcpu mutex is already taken.
2039  */
2040 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2041 {
2042         struct vcpu_vmx *vmx = to_vmx(vcpu);
2043         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2044
2045         if (!vmm_exclusive)
2046                 kvm_cpu_vmxon(phys_addr);
2047         else if (vmx->loaded_vmcs->cpu != cpu)
2048                 loaded_vmcs_clear(vmx->loaded_vmcs);
2049
2050         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2051                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2052                 vmcs_load(vmx->loaded_vmcs->vmcs);
2053         }
2054
2055         if (vmx->loaded_vmcs->cpu != cpu) {
2056                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2057                 unsigned long sysenter_esp;
2058
2059                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2060                 local_irq_disable();
2061                 crash_disable_local_vmclear(cpu);
2062
2063                 /*
2064                  * Read loaded_vmcs->cpu should be before fetching
2065                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2066                  * See the comments in __loaded_vmcs_clear().
2067                  */
2068                 smp_rmb();
2069
2070                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2071                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2072                 crash_enable_local_vmclear(cpu);
2073                 local_irq_enable();
2074
2075                 /*
2076                  * Linux uses per-cpu TSS and GDT, so set these when switching
2077                  * processors.
2078                  */
2079                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2080                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2081
2082                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2083                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2084
2085                 vmx->loaded_vmcs->cpu = cpu;
2086         }
2087
2088         /* Setup TSC multiplier */
2089         if (kvm_has_tsc_control &&
2090             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2091                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2092                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2093         }
2094
2095         vmx_vcpu_pi_load(vcpu, cpu);
2096 }
2097
2098 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2099 {
2100         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2101
2102         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2103                 !irq_remapping_cap(IRQ_POSTING_CAP))
2104                 return;
2105
2106         /* Set SN when the vCPU is preempted */
2107         if (vcpu->preempted)
2108                 pi_set_sn(pi_desc);
2109 }
2110
2111 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2112 {
2113         vmx_vcpu_pi_put(vcpu);
2114
2115         __vmx_load_host_state(to_vmx(vcpu));
2116         if (!vmm_exclusive) {
2117                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2118                 vcpu->cpu = -1;
2119                 kvm_cpu_vmxoff();
2120         }
2121 }
2122
2123 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2124 {
2125         ulong cr0;
2126
2127         if (vcpu->fpu_active)
2128                 return;
2129         vcpu->fpu_active = 1;
2130         cr0 = vmcs_readl(GUEST_CR0);
2131         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2132         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2133         vmcs_writel(GUEST_CR0, cr0);
2134         update_exception_bitmap(vcpu);
2135         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2136         if (is_guest_mode(vcpu))
2137                 vcpu->arch.cr0_guest_owned_bits &=
2138                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2139         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2140 }
2141
2142 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2143
2144 /*
2145  * Return the cr0 value that a nested guest would read. This is a combination
2146  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2147  * its hypervisor (cr0_read_shadow).
2148  */
2149 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2150 {
2151         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2152                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2153 }
2154 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2155 {
2156         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2157                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2158 }
2159
2160 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2161 {
2162         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2163          * set this *before* calling this function.
2164          */
2165         vmx_decache_cr0_guest_bits(vcpu);
2166         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2167         update_exception_bitmap(vcpu);
2168         vcpu->arch.cr0_guest_owned_bits = 0;
2169         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2170         if (is_guest_mode(vcpu)) {
2171                 /*
2172                  * L1's specified read shadow might not contain the TS bit,
2173                  * so now that we turned on shadowing of this bit, we need to
2174                  * set this bit of the shadow. Like in nested_vmx_run we need
2175                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2176                  * up-to-date here because we just decached cr0.TS (and we'll
2177                  * only update vmcs12->guest_cr0 on nested exit).
2178                  */
2179                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2180                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2181                         (vcpu->arch.cr0 & X86_CR0_TS);
2182                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2183         } else
2184                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2185 }
2186
2187 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2188 {
2189         unsigned long rflags, save_rflags;
2190
2191         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2192                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2193                 rflags = vmcs_readl(GUEST_RFLAGS);
2194                 if (to_vmx(vcpu)->rmode.vm86_active) {
2195                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2196                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2197                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2198                 }
2199                 to_vmx(vcpu)->rflags = rflags;
2200         }
2201         return to_vmx(vcpu)->rflags;
2202 }
2203
2204 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2205 {
2206         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2207         to_vmx(vcpu)->rflags = rflags;
2208         if (to_vmx(vcpu)->rmode.vm86_active) {
2209                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2210                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2211         }
2212         vmcs_writel(GUEST_RFLAGS, rflags);
2213 }
2214
2215 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2216 {
2217         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2218         int ret = 0;
2219
2220         if (interruptibility & GUEST_INTR_STATE_STI)
2221                 ret |= KVM_X86_SHADOW_INT_STI;
2222         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2223                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2224
2225         return ret;
2226 }
2227
2228 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2229 {
2230         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2231         u32 interruptibility = interruptibility_old;
2232
2233         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2234
2235         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2236                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2237         else if (mask & KVM_X86_SHADOW_INT_STI)
2238                 interruptibility |= GUEST_INTR_STATE_STI;
2239
2240         if ((interruptibility != interruptibility_old))
2241                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2242 }
2243
2244 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2245 {
2246         unsigned long rip;
2247
2248         rip = kvm_rip_read(vcpu);
2249         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2250         kvm_rip_write(vcpu, rip);
2251
2252         /* skipping an emulated instruction also counts */
2253         vmx_set_interrupt_shadow(vcpu, 0);
2254 }
2255
2256 /*
2257  * KVM wants to inject page-faults which it got to the guest. This function
2258  * checks whether in a nested guest, we need to inject them to L1 or L2.
2259  */
2260 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2261 {
2262         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2263
2264         if (!(vmcs12->exception_bitmap & (1u << nr)))
2265                 return 0;
2266
2267         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2268                           vmcs_read32(VM_EXIT_INTR_INFO),
2269                           vmcs_readl(EXIT_QUALIFICATION));
2270         return 1;
2271 }
2272
2273 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2274                                 bool has_error_code, u32 error_code,
2275                                 bool reinject)
2276 {
2277         struct vcpu_vmx *vmx = to_vmx(vcpu);
2278         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2279
2280         if (!reinject && is_guest_mode(vcpu) &&
2281             nested_vmx_check_exception(vcpu, nr))
2282                 return;
2283
2284         if (has_error_code) {
2285                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2286                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2287         }
2288
2289         if (vmx->rmode.vm86_active) {
2290                 int inc_eip = 0;
2291                 if (kvm_exception_is_soft(nr))
2292                         inc_eip = vcpu->arch.event_exit_inst_len;
2293                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2294                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2295                 return;
2296         }
2297
2298         if (kvm_exception_is_soft(nr)) {
2299                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2300                              vmx->vcpu.arch.event_exit_inst_len);
2301                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2302         } else
2303                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2304
2305         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2306 }
2307
2308 static bool vmx_rdtscp_supported(void)
2309 {
2310         return cpu_has_vmx_rdtscp();
2311 }
2312
2313 static bool vmx_invpcid_supported(void)
2314 {
2315         return cpu_has_vmx_invpcid() && enable_ept;
2316 }
2317
2318 /*
2319  * Swap MSR entry in host/guest MSR entry array.
2320  */
2321 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2322 {
2323         struct shared_msr_entry tmp;
2324
2325         tmp = vmx->guest_msrs[to];
2326         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2327         vmx->guest_msrs[from] = tmp;
2328 }
2329
2330 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2331 {
2332         unsigned long *msr_bitmap;
2333
2334         if (is_guest_mode(vcpu))
2335                 msr_bitmap = vmx_msr_bitmap_nested;
2336         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2337                 if (is_long_mode(vcpu))
2338                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2339                 else
2340                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2341         } else {
2342                 if (is_long_mode(vcpu))
2343                         msr_bitmap = vmx_msr_bitmap_longmode;
2344                 else
2345                         msr_bitmap = vmx_msr_bitmap_legacy;
2346         }
2347
2348         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2349 }
2350
2351 /*
2352  * Set up the vmcs to automatically save and restore system
2353  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2354  * mode, as fiddling with msrs is very expensive.
2355  */
2356 static void setup_msrs(struct vcpu_vmx *vmx)
2357 {
2358         int save_nmsrs, index;
2359
2360         save_nmsrs = 0;
2361 #ifdef CONFIG_X86_64
2362         if (is_long_mode(&vmx->vcpu)) {
2363                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2364                 if (index >= 0)
2365                         move_msr_up(vmx, index, save_nmsrs++);
2366                 index = __find_msr_index(vmx, MSR_LSTAR);
2367                 if (index >= 0)
2368                         move_msr_up(vmx, index, save_nmsrs++);
2369                 index = __find_msr_index(vmx, MSR_CSTAR);
2370                 if (index >= 0)
2371                         move_msr_up(vmx, index, save_nmsrs++);
2372                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2373                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2374                         move_msr_up(vmx, index, save_nmsrs++);
2375                 /*
2376                  * MSR_STAR is only needed on long mode guests, and only
2377                  * if efer.sce is enabled.
2378                  */
2379                 index = __find_msr_index(vmx, MSR_STAR);
2380                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2381                         move_msr_up(vmx, index, save_nmsrs++);
2382         }
2383 #endif
2384         index = __find_msr_index(vmx, MSR_EFER);
2385         if (index >= 0 && update_transition_efer(vmx, index))
2386                 move_msr_up(vmx, index, save_nmsrs++);
2387
2388         vmx->save_nmsrs = save_nmsrs;
2389
2390         if (cpu_has_vmx_msr_bitmap())
2391                 vmx_set_msr_bitmap(&vmx->vcpu);
2392 }
2393
2394 /*
2395  * reads and returns guest's timestamp counter "register"
2396  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2397  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2398  */
2399 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2400 {
2401         u64 host_tsc, tsc_offset;
2402
2403         host_tsc = rdtsc();
2404         tsc_offset = vmcs_read64(TSC_OFFSET);
2405         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2406 }
2407
2408 /*
2409  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2410  * counter, even if a nested guest (L2) is currently running.
2411  */
2412 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2413 {
2414         u64 tsc_offset;
2415
2416         tsc_offset = is_guest_mode(vcpu) ?
2417                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2418                 vmcs_read64(TSC_OFFSET);
2419         return host_tsc + tsc_offset;
2420 }
2421
2422 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2423 {
2424         return vmcs_read64(TSC_OFFSET);
2425 }
2426
2427 /*
2428  * writes 'offset' into guest's timestamp counter offset register
2429  */
2430 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2431 {
2432         if (is_guest_mode(vcpu)) {
2433                 /*
2434                  * We're here if L1 chose not to trap WRMSR to TSC. According
2435                  * to the spec, this should set L1's TSC; The offset that L1
2436                  * set for L2 remains unchanged, and still needs to be added
2437                  * to the newly set TSC to get L2's TSC.
2438                  */
2439                 struct vmcs12 *vmcs12;
2440                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2441                 /* recalculate vmcs02.TSC_OFFSET: */
2442                 vmcs12 = get_vmcs12(vcpu);
2443                 vmcs_write64(TSC_OFFSET, offset +
2444                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2445                          vmcs12->tsc_offset : 0));
2446         } else {
2447                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2448                                            vmcs_read64(TSC_OFFSET), offset);
2449                 vmcs_write64(TSC_OFFSET, offset);
2450         }
2451 }
2452
2453 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2454 {
2455         u64 offset = vmcs_read64(TSC_OFFSET);
2456
2457         vmcs_write64(TSC_OFFSET, offset + adjustment);
2458         if (is_guest_mode(vcpu)) {
2459                 /* Even when running L2, the adjustment needs to apply to L1 */
2460                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2461         } else
2462                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2463                                            offset + adjustment);
2464 }
2465
2466 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2467 {
2468         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2469         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2470 }
2471
2472 /*
2473  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2474  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2475  * all guests if the "nested" module option is off, and can also be disabled
2476  * for a single guest by disabling its VMX cpuid bit.
2477  */
2478 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2479 {
2480         return nested && guest_cpuid_has_vmx(vcpu);
2481 }
2482
2483 /*
2484  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2485  * returned for the various VMX controls MSRs when nested VMX is enabled.
2486  * The same values should also be used to verify that vmcs12 control fields are
2487  * valid during nested entry from L1 to L2.
2488  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2489  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2490  * bit in the high half is on if the corresponding bit in the control field
2491  * may be on. See also vmx_control_verify().
2492  */
2493 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2494 {
2495         /*
2496          * Note that as a general rule, the high half of the MSRs (bits in
2497          * the control fields which may be 1) should be initialized by the
2498          * intersection of the underlying hardware's MSR (i.e., features which
2499          * can be supported) and the list of features we want to expose -
2500          * because they are known to be properly supported in our code.
2501          * Also, usually, the low half of the MSRs (bits which must be 1) can
2502          * be set to 0, meaning that L1 may turn off any of these bits. The
2503          * reason is that if one of these bits is necessary, it will appear
2504          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2505          * fields of vmcs01 and vmcs02, will turn these bits off - and
2506          * nested_vmx_exit_handled() will not pass related exits to L1.
2507          * These rules have exceptions below.
2508          */
2509
2510         /* pin-based controls */
2511         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2512                 vmx->nested.nested_vmx_pinbased_ctls_low,
2513                 vmx->nested.nested_vmx_pinbased_ctls_high);
2514         vmx->nested.nested_vmx_pinbased_ctls_low |=
2515                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2516         vmx->nested.nested_vmx_pinbased_ctls_high &=
2517                 PIN_BASED_EXT_INTR_MASK |
2518                 PIN_BASED_NMI_EXITING |
2519                 PIN_BASED_VIRTUAL_NMIS;
2520         vmx->nested.nested_vmx_pinbased_ctls_high |=
2521                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2522                 PIN_BASED_VMX_PREEMPTION_TIMER;
2523         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2524                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2525                         PIN_BASED_POSTED_INTR;
2526
2527         /* exit controls */
2528         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2529                 vmx->nested.nested_vmx_exit_ctls_low,
2530                 vmx->nested.nested_vmx_exit_ctls_high);
2531         vmx->nested.nested_vmx_exit_ctls_low =
2532                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2533
2534         vmx->nested.nested_vmx_exit_ctls_high &=
2535 #ifdef CONFIG_X86_64
2536                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2537 #endif
2538                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2539         vmx->nested.nested_vmx_exit_ctls_high |=
2540                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2541                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2542                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2543
2544         if (vmx_mpx_supported())
2545                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2546
2547         /* We support free control of debug control saving. */
2548         vmx->nested.nested_vmx_true_exit_ctls_low =
2549                 vmx->nested.nested_vmx_exit_ctls_low &
2550                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2551
2552         /* entry controls */
2553         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2554                 vmx->nested.nested_vmx_entry_ctls_low,
2555                 vmx->nested.nested_vmx_entry_ctls_high);
2556         vmx->nested.nested_vmx_entry_ctls_low =
2557                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2558         vmx->nested.nested_vmx_entry_ctls_high &=
2559 #ifdef CONFIG_X86_64
2560                 VM_ENTRY_IA32E_MODE |
2561 #endif
2562                 VM_ENTRY_LOAD_IA32_PAT;
2563         vmx->nested.nested_vmx_entry_ctls_high |=
2564                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2565         if (vmx_mpx_supported())
2566                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2567
2568         /* We support free control of debug control loading. */
2569         vmx->nested.nested_vmx_true_entry_ctls_low =
2570                 vmx->nested.nested_vmx_entry_ctls_low &
2571                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2572
2573         /* cpu-based controls */
2574         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2575                 vmx->nested.nested_vmx_procbased_ctls_low,
2576                 vmx->nested.nested_vmx_procbased_ctls_high);
2577         vmx->nested.nested_vmx_procbased_ctls_low =
2578                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2579         vmx->nested.nested_vmx_procbased_ctls_high &=
2580                 CPU_BASED_VIRTUAL_INTR_PENDING |
2581                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2582                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2583                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2584                 CPU_BASED_CR3_STORE_EXITING |
2585 #ifdef CONFIG_X86_64
2586                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2587 #endif
2588                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2589                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2590                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2591                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2592                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2593         /*
2594          * We can allow some features even when not supported by the
2595          * hardware. For example, L1 can specify an MSR bitmap - and we
2596          * can use it to avoid exits to L1 - even when L0 runs L2
2597          * without MSR bitmaps.
2598          */
2599         vmx->nested.nested_vmx_procbased_ctls_high |=
2600                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2601                 CPU_BASED_USE_MSR_BITMAPS;
2602
2603         /* We support free control of CR3 access interception. */
2604         vmx->nested.nested_vmx_true_procbased_ctls_low =
2605                 vmx->nested.nested_vmx_procbased_ctls_low &
2606                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2607
2608         /* secondary cpu-based controls */
2609         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2610                 vmx->nested.nested_vmx_secondary_ctls_low,
2611                 vmx->nested.nested_vmx_secondary_ctls_high);
2612         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2613         vmx->nested.nested_vmx_secondary_ctls_high &=
2614                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2615                 SECONDARY_EXEC_RDTSCP |
2616                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2617                 SECONDARY_EXEC_ENABLE_VPID |
2618                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2619                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2620                 SECONDARY_EXEC_WBINVD_EXITING |
2621                 SECONDARY_EXEC_XSAVES |
2622                 SECONDARY_EXEC_PCOMMIT;
2623
2624         if (enable_ept) {
2625                 /* nested EPT: emulate EPT also to L1 */
2626                 vmx->nested.nested_vmx_secondary_ctls_high |=
2627                         SECONDARY_EXEC_ENABLE_EPT;
2628                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2629                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2630                          VMX_EPT_INVEPT_BIT;
2631                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2632                 /*
2633                  * For nested guests, we don't do anything specific
2634                  * for single context invalidation. Hence, only advertise
2635                  * support for global context invalidation.
2636                  */
2637                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2638         } else
2639                 vmx->nested.nested_vmx_ept_caps = 0;
2640
2641         /*
2642          * Old versions of KVM use the single-context version without
2643          * checking for support, so declare that it is supported even
2644          * though it is treated as global context.  The alternative is
2645          * not failing the single-context invvpid, and it is worse.
2646          */
2647         if (enable_vpid)
2648                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2649                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2650                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2651         else
2652                 vmx->nested.nested_vmx_vpid_caps = 0;
2653
2654         if (enable_unrestricted_guest)
2655                 vmx->nested.nested_vmx_secondary_ctls_high |=
2656                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2657
2658         /* miscellaneous data */
2659         rdmsr(MSR_IA32_VMX_MISC,
2660                 vmx->nested.nested_vmx_misc_low,
2661                 vmx->nested.nested_vmx_misc_high);
2662         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2663         vmx->nested.nested_vmx_misc_low |=
2664                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2665                 VMX_MISC_ACTIVITY_HLT;
2666         vmx->nested.nested_vmx_misc_high = 0;
2667 }
2668
2669 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2670 {
2671         /*
2672          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2673          */
2674         return ((control & high) | low) == control;
2675 }
2676
2677 static inline u64 vmx_control_msr(u32 low, u32 high)
2678 {
2679         return low | ((u64)high << 32);
2680 }
2681
2682 /* Returns 0 on success, non-0 otherwise. */
2683 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2684 {
2685         struct vcpu_vmx *vmx = to_vmx(vcpu);
2686
2687         switch (msr_index) {
2688         case MSR_IA32_VMX_BASIC:
2689                 /*
2690                  * This MSR reports some information about VMX support. We
2691                  * should return information about the VMX we emulate for the
2692                  * guest, and the VMCS structure we give it - not about the
2693                  * VMX support of the underlying hardware.
2694                  */
2695                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2696                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2697                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2698                 break;
2699         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2700         case MSR_IA32_VMX_PINBASED_CTLS:
2701                 *pdata = vmx_control_msr(
2702                         vmx->nested.nested_vmx_pinbased_ctls_low,
2703                         vmx->nested.nested_vmx_pinbased_ctls_high);
2704                 break;
2705         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2706                 *pdata = vmx_control_msr(
2707                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2708                         vmx->nested.nested_vmx_procbased_ctls_high);
2709                 break;
2710         case MSR_IA32_VMX_PROCBASED_CTLS:
2711                 *pdata = vmx_control_msr(
2712                         vmx->nested.nested_vmx_procbased_ctls_low,
2713                         vmx->nested.nested_vmx_procbased_ctls_high);
2714                 break;
2715         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2716                 *pdata = vmx_control_msr(
2717                         vmx->nested.nested_vmx_true_exit_ctls_low,
2718                         vmx->nested.nested_vmx_exit_ctls_high);
2719                 break;
2720         case MSR_IA32_VMX_EXIT_CTLS:
2721                 *pdata = vmx_control_msr(
2722                         vmx->nested.nested_vmx_exit_ctls_low,
2723                         vmx->nested.nested_vmx_exit_ctls_high);
2724                 break;
2725         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2726                 *pdata = vmx_control_msr(
2727                         vmx->nested.nested_vmx_true_entry_ctls_low,
2728                         vmx->nested.nested_vmx_entry_ctls_high);
2729                 break;
2730         case MSR_IA32_VMX_ENTRY_CTLS:
2731                 *pdata = vmx_control_msr(
2732                         vmx->nested.nested_vmx_entry_ctls_low,
2733                         vmx->nested.nested_vmx_entry_ctls_high);
2734                 break;
2735         case MSR_IA32_VMX_MISC:
2736                 *pdata = vmx_control_msr(
2737                         vmx->nested.nested_vmx_misc_low,
2738                         vmx->nested.nested_vmx_misc_high);
2739                 break;
2740         /*
2741          * These MSRs specify bits which the guest must keep fixed (on or off)
2742          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2743          * We picked the standard core2 setting.
2744          */
2745 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2746 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2747         case MSR_IA32_VMX_CR0_FIXED0:
2748                 *pdata = VMXON_CR0_ALWAYSON;
2749                 break;
2750         case MSR_IA32_VMX_CR0_FIXED1:
2751                 *pdata = -1ULL;
2752                 break;
2753         case MSR_IA32_VMX_CR4_FIXED0:
2754                 *pdata = VMXON_CR4_ALWAYSON;
2755                 break;
2756         case MSR_IA32_VMX_CR4_FIXED1:
2757                 *pdata = -1ULL;
2758                 break;
2759         case MSR_IA32_VMX_VMCS_ENUM:
2760                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2761                 break;
2762         case MSR_IA32_VMX_PROCBASED_CTLS2:
2763                 *pdata = vmx_control_msr(
2764                         vmx->nested.nested_vmx_secondary_ctls_low,
2765                         vmx->nested.nested_vmx_secondary_ctls_high);
2766                 break;
2767         case MSR_IA32_VMX_EPT_VPID_CAP:
2768                 /* Currently, no nested vpid support */
2769                 *pdata = vmx->nested.nested_vmx_ept_caps |
2770                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2771                 break;
2772         default:
2773                 return 1;
2774         }
2775
2776         return 0;
2777 }
2778
2779 /*
2780  * Reads an msr value (of 'msr_index') into 'pdata'.
2781  * Returns 0 on success, non-0 otherwise.
2782  * Assumes vcpu_load() was already called.
2783  */
2784 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2785 {
2786         struct shared_msr_entry *msr;
2787
2788         switch (msr_info->index) {
2789 #ifdef CONFIG_X86_64
2790         case MSR_FS_BASE:
2791                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2792                 break;
2793         case MSR_GS_BASE:
2794                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2795                 break;
2796         case MSR_KERNEL_GS_BASE:
2797                 vmx_load_host_state(to_vmx(vcpu));
2798                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2799                 break;
2800 #endif
2801         case MSR_EFER:
2802                 return kvm_get_msr_common(vcpu, msr_info);
2803         case MSR_IA32_TSC:
2804                 msr_info->data = guest_read_tsc(vcpu);
2805                 break;
2806         case MSR_IA32_SYSENTER_CS:
2807                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2808                 break;
2809         case MSR_IA32_SYSENTER_EIP:
2810                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2811                 break;
2812         case MSR_IA32_SYSENTER_ESP:
2813                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2814                 break;
2815         case MSR_IA32_BNDCFGS:
2816                 if (!vmx_mpx_supported())
2817                         return 1;
2818                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2819                 break;
2820         case MSR_IA32_FEATURE_CONTROL:
2821                 if (!nested_vmx_allowed(vcpu))
2822                         return 1;
2823                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2824                 break;
2825         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2826                 if (!nested_vmx_allowed(vcpu))
2827                         return 1;
2828                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2829         case MSR_IA32_XSS:
2830                 if (!vmx_xsaves_supported())
2831                         return 1;
2832                 msr_info->data = vcpu->arch.ia32_xss;
2833                 break;
2834         case MSR_TSC_AUX:
2835                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2836                         return 1;
2837                 /* Otherwise falls through */
2838         default:
2839                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2840                 if (msr) {
2841                         msr_info->data = msr->data;
2842                         break;
2843                 }
2844                 return kvm_get_msr_common(vcpu, msr_info);
2845         }
2846
2847         return 0;
2848 }
2849
2850 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2851
2852 /*
2853  * Writes msr value into into the appropriate "register".
2854  * Returns 0 on success, non-0 otherwise.
2855  * Assumes vcpu_load() was already called.
2856  */
2857 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2858 {
2859         struct vcpu_vmx *vmx = to_vmx(vcpu);
2860         struct shared_msr_entry *msr;
2861         int ret = 0;
2862         u32 msr_index = msr_info->index;
2863         u64 data = msr_info->data;
2864
2865         switch (msr_index) {
2866         case MSR_EFER:
2867                 ret = kvm_set_msr_common(vcpu, msr_info);
2868                 break;
2869 #ifdef CONFIG_X86_64
2870         case MSR_FS_BASE:
2871                 vmx_segment_cache_clear(vmx);
2872                 vmcs_writel(GUEST_FS_BASE, data);
2873                 break;
2874         case MSR_GS_BASE:
2875                 vmx_segment_cache_clear(vmx);
2876                 vmcs_writel(GUEST_GS_BASE, data);
2877                 break;
2878         case MSR_KERNEL_GS_BASE:
2879                 vmx_load_host_state(vmx);
2880                 vmx->msr_guest_kernel_gs_base = data;
2881                 break;
2882 #endif
2883         case MSR_IA32_SYSENTER_CS:
2884                 vmcs_write32(GUEST_SYSENTER_CS, data);
2885                 break;
2886         case MSR_IA32_SYSENTER_EIP:
2887                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2888                 break;
2889         case MSR_IA32_SYSENTER_ESP:
2890                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2891                 break;
2892         case MSR_IA32_BNDCFGS:
2893                 if (!vmx_mpx_supported())
2894                         return 1;
2895                 vmcs_write64(GUEST_BNDCFGS, data);
2896                 break;
2897         case MSR_IA32_TSC:
2898                 kvm_write_tsc(vcpu, msr_info);
2899                 break;
2900         case MSR_IA32_CR_PAT:
2901                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2902                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2903                                 return 1;
2904                         vmcs_write64(GUEST_IA32_PAT, data);
2905                         vcpu->arch.pat = data;
2906                         break;
2907                 }
2908                 ret = kvm_set_msr_common(vcpu, msr_info);
2909                 break;
2910         case MSR_IA32_TSC_ADJUST:
2911                 ret = kvm_set_msr_common(vcpu, msr_info);
2912                 break;
2913         case MSR_IA32_FEATURE_CONTROL:
2914                 if (!nested_vmx_allowed(vcpu) ||
2915                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2916                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2917                         return 1;
2918                 vmx->nested.msr_ia32_feature_control = data;
2919                 if (msr_info->host_initiated && data == 0)
2920                         vmx_leave_nested(vcpu);
2921                 break;
2922         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2923                 return 1; /* they are read-only */
2924         case MSR_IA32_XSS:
2925                 if (!vmx_xsaves_supported())
2926                         return 1;
2927                 /*
2928                  * The only supported bit as of Skylake is bit 8, but
2929                  * it is not supported on KVM.
2930                  */
2931                 if (data != 0)
2932                         return 1;
2933                 vcpu->arch.ia32_xss = data;
2934                 if (vcpu->arch.ia32_xss != host_xss)
2935                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2936                                 vcpu->arch.ia32_xss, host_xss);
2937                 else
2938                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2939                 break;
2940         case MSR_TSC_AUX:
2941                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2942                         return 1;
2943                 /* Check reserved bit, higher 32 bits should be zero */
2944                 if ((data >> 32) != 0)
2945                         return 1;
2946                 /* Otherwise falls through */
2947         default:
2948                 msr = find_msr_entry(vmx, msr_index);
2949                 if (msr) {
2950                         u64 old_msr_data = msr->data;
2951                         msr->data = data;
2952                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2953                                 preempt_disable();
2954                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2955                                                          msr->mask);
2956                                 preempt_enable();
2957                                 if (ret)
2958                                         msr->data = old_msr_data;
2959                         }
2960                         break;
2961                 }
2962                 ret = kvm_set_msr_common(vcpu, msr_info);
2963         }
2964
2965         return ret;
2966 }
2967
2968 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2969 {
2970         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2971         switch (reg) {
2972         case VCPU_REGS_RSP:
2973                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2974                 break;
2975         case VCPU_REGS_RIP:
2976                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2977                 break;
2978         case VCPU_EXREG_PDPTR:
2979                 if (enable_ept)
2980                         ept_save_pdptrs(vcpu);
2981                 break;
2982         default:
2983                 break;
2984         }
2985 }
2986
2987 static __init int cpu_has_kvm_support(void)
2988 {
2989         return cpu_has_vmx();
2990 }
2991
2992 static __init int vmx_disabled_by_bios(void)
2993 {
2994         u64 msr;
2995
2996         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2997         if (msr & FEATURE_CONTROL_LOCKED) {
2998                 /* launched w/ TXT and VMX disabled */
2999                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3000                         && tboot_enabled())
3001                         return 1;
3002                 /* launched w/o TXT and VMX only enabled w/ TXT */
3003                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3004                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3005                         && !tboot_enabled()) {
3006                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3007                                 "activate TXT before enabling KVM\n");
3008                         return 1;
3009                 }
3010                 /* launched w/o TXT and VMX disabled */
3011                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3012                         && !tboot_enabled())
3013                         return 1;
3014         }
3015
3016         return 0;
3017 }
3018
3019 static void kvm_cpu_vmxon(u64 addr)
3020 {
3021         asm volatile (ASM_VMX_VMXON_RAX
3022                         : : "a"(&addr), "m"(addr)
3023                         : "memory", "cc");
3024 }
3025
3026 static int hardware_enable(void)
3027 {
3028         int cpu = raw_smp_processor_id();
3029         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3030         u64 old, test_bits;
3031
3032         if (cr4_read_shadow() & X86_CR4_VMXE)
3033                 return -EBUSY;
3034
3035         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3036         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3037         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3038
3039         /*
3040          * Now we can enable the vmclear operation in kdump
3041          * since the loaded_vmcss_on_cpu list on this cpu
3042          * has been initialized.
3043          *
3044          * Though the cpu is not in VMX operation now, there
3045          * is no problem to enable the vmclear operation
3046          * for the loaded_vmcss_on_cpu list is empty!
3047          */
3048         crash_enable_local_vmclear(cpu);
3049
3050         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3051
3052         test_bits = FEATURE_CONTROL_LOCKED;
3053         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3054         if (tboot_enabled())
3055                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3056
3057         if ((old & test_bits) != test_bits) {
3058                 /* enable and lock */
3059                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3060         }
3061         cr4_set_bits(X86_CR4_VMXE);
3062
3063         if (vmm_exclusive) {
3064                 kvm_cpu_vmxon(phys_addr);
3065                 ept_sync_global();
3066         }
3067
3068         native_store_gdt(this_cpu_ptr(&host_gdt));
3069
3070         return 0;
3071 }
3072
3073 static void vmclear_local_loaded_vmcss(void)
3074 {
3075         int cpu = raw_smp_processor_id();
3076         struct loaded_vmcs *v, *n;
3077
3078         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3079                                  loaded_vmcss_on_cpu_link)
3080                 __loaded_vmcs_clear(v);
3081 }
3082
3083
3084 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3085  * tricks.
3086  */
3087 static void kvm_cpu_vmxoff(void)
3088 {
3089         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3090 }
3091
3092 static void hardware_disable(void)
3093 {
3094         if (vmm_exclusive) {
3095                 vmclear_local_loaded_vmcss();
3096                 kvm_cpu_vmxoff();
3097         }
3098         cr4_clear_bits(X86_CR4_VMXE);
3099 }
3100
3101 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3102                                       u32 msr, u32 *result)
3103 {
3104         u32 vmx_msr_low, vmx_msr_high;
3105         u32 ctl = ctl_min | ctl_opt;
3106
3107         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3108
3109         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3110         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3111
3112         /* Ensure minimum (required) set of control bits are supported. */
3113         if (ctl_min & ~ctl)
3114                 return -EIO;
3115
3116         *result = ctl;
3117         return 0;
3118 }
3119
3120 static __init bool allow_1_setting(u32 msr, u32 ctl)
3121 {
3122         u32 vmx_msr_low, vmx_msr_high;
3123
3124         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3125         return vmx_msr_high & ctl;
3126 }
3127
3128 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3129 {
3130         u32 vmx_msr_low, vmx_msr_high;
3131         u32 min, opt, min2, opt2;
3132         u32 _pin_based_exec_control = 0;
3133         u32 _cpu_based_exec_control = 0;
3134         u32 _cpu_based_2nd_exec_control = 0;
3135         u32 _vmexit_control = 0;
3136         u32 _vmentry_control = 0;
3137
3138         min = CPU_BASED_HLT_EXITING |
3139 #ifdef CONFIG_X86_64
3140               CPU_BASED_CR8_LOAD_EXITING |
3141               CPU_BASED_CR8_STORE_EXITING |
3142 #endif
3143               CPU_BASED_CR3_LOAD_EXITING |
3144               CPU_BASED_CR3_STORE_EXITING |
3145               CPU_BASED_USE_IO_BITMAPS |
3146               CPU_BASED_MOV_DR_EXITING |
3147               CPU_BASED_USE_TSC_OFFSETING |
3148               CPU_BASED_MWAIT_EXITING |
3149               CPU_BASED_MONITOR_EXITING |
3150               CPU_BASED_INVLPG_EXITING |
3151               CPU_BASED_RDPMC_EXITING;
3152
3153         opt = CPU_BASED_TPR_SHADOW |
3154               CPU_BASED_USE_MSR_BITMAPS |
3155               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3156         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3157                                 &_cpu_based_exec_control) < 0)
3158                 return -EIO;
3159 #ifdef CONFIG_X86_64
3160         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3161                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3162                                            ~CPU_BASED_CR8_STORE_EXITING;
3163 #endif
3164         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3165                 min2 = 0;
3166                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3167                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3168                         SECONDARY_EXEC_WBINVD_EXITING |
3169                         SECONDARY_EXEC_ENABLE_VPID |
3170                         SECONDARY_EXEC_ENABLE_EPT |
3171                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3172                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3173                         SECONDARY_EXEC_RDTSCP |
3174                         SECONDARY_EXEC_ENABLE_INVPCID |
3175                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3176                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3177                         SECONDARY_EXEC_SHADOW_VMCS |
3178                         SECONDARY_EXEC_XSAVES |
3179                         SECONDARY_EXEC_ENABLE_PML |
3180                         SECONDARY_EXEC_PCOMMIT |
3181                         SECONDARY_EXEC_TSC_SCALING;
3182                 if (adjust_vmx_controls(min2, opt2,
3183                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3184                                         &_cpu_based_2nd_exec_control) < 0)
3185                         return -EIO;
3186         }
3187 #ifndef CONFIG_X86_64
3188         if (!(_cpu_based_2nd_exec_control &
3189                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3190                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3191 #endif
3192
3193         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3194                 _cpu_based_2nd_exec_control &= ~(
3195                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3196                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3197                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3198
3199         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3200                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3201                    enabled */
3202                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3203                                              CPU_BASED_CR3_STORE_EXITING |
3204                                              CPU_BASED_INVLPG_EXITING);
3205                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3206                       vmx_capability.ept, vmx_capability.vpid);
3207         }
3208
3209         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3210 #ifdef CONFIG_X86_64
3211         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3212 #endif
3213         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3214                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3215         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3216                                 &_vmexit_control) < 0)
3217                 return -EIO;
3218
3219         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3220         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3221         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3222                                 &_pin_based_exec_control) < 0)
3223                 return -EIO;
3224
3225         if (!(_cpu_based_2nd_exec_control &
3226                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3227                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3228                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3229
3230         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3231         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3232         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3233                                 &_vmentry_control) < 0)
3234                 return -EIO;
3235
3236         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3237
3238         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3239         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3240                 return -EIO;
3241
3242 #ifdef CONFIG_X86_64
3243         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3244         if (vmx_msr_high & (1u<<16))
3245                 return -EIO;
3246 #endif
3247
3248         /* Require Write-Back (WB) memory type for VMCS accesses. */
3249         if (((vmx_msr_high >> 18) & 15) != 6)
3250                 return -EIO;
3251
3252         vmcs_conf->size = vmx_msr_high & 0x1fff;
3253         vmcs_conf->order = get_order(vmcs_config.size);
3254         vmcs_conf->revision_id = vmx_msr_low;
3255
3256         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3257         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3258         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3259         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3260         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3261
3262         cpu_has_load_ia32_efer =
3263                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3264                                 VM_ENTRY_LOAD_IA32_EFER)
3265                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3266                                    VM_EXIT_LOAD_IA32_EFER);
3267
3268         cpu_has_load_perf_global_ctrl =
3269                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3270                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3271                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3272                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3273
3274         /*
3275          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3276          * but due to arrata below it can't be used. Workaround is to use
3277          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3278          *
3279          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3280          *
3281          * AAK155             (model 26)
3282          * AAP115             (model 30)
3283          * AAT100             (model 37)
3284          * BC86,AAY89,BD102   (model 44)
3285          * BA97               (model 46)
3286          *
3287          */
3288         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3289                 switch (boot_cpu_data.x86_model) {
3290                 case 26:
3291                 case 30:
3292                 case 37:
3293                 case 44:
3294                 case 46:
3295                         cpu_has_load_perf_global_ctrl = false;
3296                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3297                                         "does not work properly. Using workaround\n");
3298                         break;
3299                 default:
3300                         break;
3301                 }
3302         }
3303
3304         if (cpu_has_xsaves)
3305                 rdmsrl(MSR_IA32_XSS, host_xss);
3306
3307         return 0;
3308 }
3309
3310 static struct vmcs *alloc_vmcs_cpu(int cpu)
3311 {
3312         int node = cpu_to_node(cpu);
3313         struct page *pages;
3314         struct vmcs *vmcs;
3315
3316         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3317         if (!pages)
3318                 return NULL;
3319         vmcs = page_address(pages);
3320         memset(vmcs, 0, vmcs_config.size);
3321         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3322         return vmcs;
3323 }
3324
3325 static struct vmcs *alloc_vmcs(void)
3326 {
3327         return alloc_vmcs_cpu(raw_smp_processor_id());
3328 }
3329
3330 static void free_vmcs(struct vmcs *vmcs)
3331 {
3332         free_pages((unsigned long)vmcs, vmcs_config.order);
3333 }
3334
3335 /*
3336  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3337  */
3338 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3339 {
3340         if (!loaded_vmcs->vmcs)
3341                 return;
3342         loaded_vmcs_clear(loaded_vmcs);
3343         free_vmcs(loaded_vmcs->vmcs);
3344         loaded_vmcs->vmcs = NULL;
3345 }
3346
3347 static void free_kvm_area(void)
3348 {
3349         int cpu;
3350
3351         for_each_possible_cpu(cpu) {
3352                 free_vmcs(per_cpu(vmxarea, cpu));
3353                 per_cpu(vmxarea, cpu) = NULL;
3354         }
3355 }
3356
3357 static void init_vmcs_shadow_fields(void)
3358 {
3359         int i, j;
3360
3361         /* No checks for read only fields yet */
3362
3363         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3364                 switch (shadow_read_write_fields[i]) {
3365                 case GUEST_BNDCFGS:
3366                         if (!vmx_mpx_supported())
3367                                 continue;
3368                         break;
3369                 default:
3370                         break;
3371                 }
3372
3373                 if (j < i)
3374                         shadow_read_write_fields[j] =
3375                                 shadow_read_write_fields[i];
3376                 j++;
3377         }
3378         max_shadow_read_write_fields = j;
3379
3380         /* shadowed fields guest access without vmexit */
3381         for (i = 0; i < max_shadow_read_write_fields; i++) {
3382                 clear_bit(shadow_read_write_fields[i],
3383                           vmx_vmwrite_bitmap);
3384                 clear_bit(shadow_read_write_fields[i],
3385                           vmx_vmread_bitmap);
3386         }
3387         for (i = 0; i < max_shadow_read_only_fields; i++)
3388                 clear_bit(shadow_read_only_fields[i],
3389                           vmx_vmread_bitmap);
3390 }
3391
3392 static __init int alloc_kvm_area(void)
3393 {
3394         int cpu;
3395
3396         for_each_possible_cpu(cpu) {
3397                 struct vmcs *vmcs;
3398
3399                 vmcs = alloc_vmcs_cpu(cpu);
3400                 if (!vmcs) {
3401                         free_kvm_area();
3402                         return -ENOMEM;
3403                 }
3404
3405                 per_cpu(vmxarea, cpu) = vmcs;
3406         }
3407         return 0;
3408 }
3409
3410 static bool emulation_required(struct kvm_vcpu *vcpu)
3411 {
3412         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3413 }
3414
3415 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3416                 struct kvm_segment *save)
3417 {
3418         if (!emulate_invalid_guest_state) {
3419                 /*
3420                  * CS and SS RPL should be equal during guest entry according
3421                  * to VMX spec, but in reality it is not always so. Since vcpu
3422                  * is in the middle of the transition from real mode to
3423                  * protected mode it is safe to assume that RPL 0 is a good
3424                  * default value.
3425                  */
3426                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3427                         save->selector &= ~SEGMENT_RPL_MASK;
3428                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3429                 save->s = 1;
3430         }
3431         vmx_set_segment(vcpu, save, seg);
3432 }
3433
3434 static void enter_pmode(struct kvm_vcpu *vcpu)
3435 {
3436         unsigned long flags;
3437         struct vcpu_vmx *vmx = to_vmx(vcpu);
3438
3439         /*
3440          * Update real mode segment cache. It may be not up-to-date if sement
3441          * register was written while vcpu was in a guest mode.
3442          */
3443         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3444         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3445         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3446         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3447         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3448         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3449
3450         vmx->rmode.vm86_active = 0;
3451
3452         vmx_segment_cache_clear(vmx);
3453
3454         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3455
3456         flags = vmcs_readl(GUEST_RFLAGS);
3457         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3458         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3459         vmcs_writel(GUEST_RFLAGS, flags);
3460
3461         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3462                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3463
3464         update_exception_bitmap(vcpu);
3465
3466         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3467         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3468         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3469         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3470         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3471         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3472 }
3473
3474 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3475 {
3476         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3477         struct kvm_segment var = *save;
3478
3479         var.dpl = 0x3;
3480         if (seg == VCPU_SREG_CS)
3481                 var.type = 0x3;
3482
3483         if (!emulate_invalid_guest_state) {
3484                 var.selector = var.base >> 4;
3485                 var.base = var.base & 0xffff0;
3486                 var.limit = 0xffff;
3487                 var.g = 0;
3488                 var.db = 0;
3489                 var.present = 1;
3490                 var.s = 1;
3491                 var.l = 0;
3492                 var.unusable = 0;
3493                 var.type = 0x3;
3494                 var.avl = 0;
3495                 if (save->base & 0xf)
3496                         printk_once(KERN_WARNING "kvm: segment base is not "
3497                                         "paragraph aligned when entering "
3498                                         "protected mode (seg=%d)", seg);
3499         }
3500
3501         vmcs_write16(sf->selector, var.selector);
3502         vmcs_writel(sf->base, var.base);
3503         vmcs_write32(sf->limit, var.limit);
3504         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3505 }
3506
3507 static void enter_rmode(struct kvm_vcpu *vcpu)
3508 {
3509         unsigned long flags;
3510         struct vcpu_vmx *vmx = to_vmx(vcpu);
3511
3512         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3513         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3514         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3515         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3516         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3517         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3518         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3519
3520         vmx->rmode.vm86_active = 1;
3521
3522         /*
3523          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3524          * vcpu. Warn the user that an update is overdue.
3525          */
3526         if (!vcpu->kvm->arch.tss_addr)
3527                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3528                              "called before entering vcpu\n");
3529
3530         vmx_segment_cache_clear(vmx);
3531
3532         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3533         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3534         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3535
3536         flags = vmcs_readl(GUEST_RFLAGS);
3537         vmx->rmode.save_rflags = flags;
3538
3539         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3540
3541         vmcs_writel(GUEST_RFLAGS, flags);
3542         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3543         update_exception_bitmap(vcpu);
3544
3545         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3546         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3547         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3548         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3549         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3550         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3551
3552         kvm_mmu_reset_context(vcpu);
3553 }
3554
3555 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3556 {
3557         struct vcpu_vmx *vmx = to_vmx(vcpu);
3558         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3559
3560         if (!msr)
3561                 return;
3562
3563         /*
3564          * Force kernel_gs_base reloading before EFER changes, as control
3565          * of this msr depends on is_long_mode().
3566          */
3567         vmx_load_host_state(to_vmx(vcpu));
3568         vcpu->arch.efer = efer;
3569         if (efer & EFER_LMA) {
3570                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3571                 msr->data = efer;
3572         } else {
3573                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3574
3575                 msr->data = efer & ~EFER_LME;
3576         }
3577         setup_msrs(vmx);
3578 }
3579
3580 #ifdef CONFIG_X86_64
3581
3582 static void enter_lmode(struct kvm_vcpu *vcpu)
3583 {
3584         u32 guest_tr_ar;
3585
3586         vmx_segment_cache_clear(to_vmx(vcpu));
3587
3588         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3589         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3590                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3591                                      __func__);
3592                 vmcs_write32(GUEST_TR_AR_BYTES,
3593                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3594                              | VMX_AR_TYPE_BUSY_64_TSS);
3595         }
3596         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3597 }
3598
3599 static void exit_lmode(struct kvm_vcpu *vcpu)
3600 {
3601         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3602         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3603 }
3604
3605 #endif
3606
3607 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3608 {
3609         vpid_sync_context(vpid);
3610         if (enable_ept) {
3611                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3612                         return;
3613                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3614         }
3615 }
3616
3617 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3618 {
3619         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3620 }
3621
3622 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3623 {
3624         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3625
3626         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3627         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3628 }
3629
3630 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3631 {
3632         if (enable_ept && is_paging(vcpu))
3633                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3634         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3635 }
3636
3637 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3638 {
3639         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3640
3641         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3642         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3643 }
3644
3645 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3646 {
3647         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3648
3649         if (!test_bit(VCPU_EXREG_PDPTR,
3650                       (unsigned long *)&vcpu->arch.regs_dirty))
3651                 return;
3652
3653         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3654                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3655                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3656                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3657                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3658         }
3659 }
3660
3661 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3662 {
3663         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3664
3665         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3666                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3667                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3668                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3669                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3670         }
3671
3672         __set_bit(VCPU_EXREG_PDPTR,
3673                   (unsigned long *)&vcpu->arch.regs_avail);
3674         __set_bit(VCPU_EXREG_PDPTR,
3675                   (unsigned long *)&vcpu->arch.regs_dirty);
3676 }
3677
3678 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3679
3680 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3681                                         unsigned long cr0,
3682                                         struct kvm_vcpu *vcpu)
3683 {
3684         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3685                 vmx_decache_cr3(vcpu);
3686         if (!(cr0 & X86_CR0_PG)) {
3687                 /* From paging/starting to nonpaging */
3688                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3689                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3690                              (CPU_BASED_CR3_LOAD_EXITING |
3691                               CPU_BASED_CR3_STORE_EXITING));
3692                 vcpu->arch.cr0 = cr0;
3693                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3694         } else if (!is_paging(vcpu)) {
3695                 /* From nonpaging to paging */
3696                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3697                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3698                              ~(CPU_BASED_CR3_LOAD_EXITING |
3699                                CPU_BASED_CR3_STORE_EXITING));
3700                 vcpu->arch.cr0 = cr0;
3701                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3702         }
3703
3704         if (!(cr0 & X86_CR0_WP))
3705                 *hw_cr0 &= ~X86_CR0_WP;
3706 }
3707
3708 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3709 {
3710         struct vcpu_vmx *vmx = to_vmx(vcpu);
3711         unsigned long hw_cr0;
3712
3713         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3714         if (enable_unrestricted_guest)
3715                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3716         else {
3717                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3718
3719                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3720                         enter_pmode(vcpu);
3721
3722                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3723                         enter_rmode(vcpu);
3724         }
3725
3726 #ifdef CONFIG_X86_64
3727         if (vcpu->arch.efer & EFER_LME) {
3728                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3729                         enter_lmode(vcpu);
3730                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3731                         exit_lmode(vcpu);
3732         }
3733 #endif
3734
3735         if (enable_ept)
3736                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3737
3738         if (!vcpu->fpu_active)
3739                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3740
3741         vmcs_writel(CR0_READ_SHADOW, cr0);
3742         vmcs_writel(GUEST_CR0, hw_cr0);
3743         vcpu->arch.cr0 = cr0;
3744
3745         /* depends on vcpu->arch.cr0 to be set to a new value */
3746         vmx->emulation_required = emulation_required(vcpu);
3747 }
3748
3749 static u64 construct_eptp(unsigned long root_hpa)
3750 {
3751         u64 eptp;
3752
3753         /* TODO write the value reading from MSR */
3754         eptp = VMX_EPT_DEFAULT_MT |
3755                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3756         if (enable_ept_ad_bits)
3757                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3758         eptp |= (root_hpa & PAGE_MASK);
3759
3760         return eptp;
3761 }
3762
3763 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3764 {
3765         unsigned long guest_cr3;
3766         u64 eptp;
3767
3768         guest_cr3 = cr3;
3769         if (enable_ept) {
3770                 eptp = construct_eptp(cr3);
3771                 vmcs_write64(EPT_POINTER, eptp);
3772                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3773                         guest_cr3 = kvm_read_cr3(vcpu);
3774                 else
3775                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3776                 ept_load_pdptrs(vcpu);
3777         }
3778
3779         vmx_flush_tlb(vcpu);
3780         vmcs_writel(GUEST_CR3, guest_cr3);
3781 }
3782
3783 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3784 {
3785         /*
3786          * Pass through host's Machine Check Enable value to hw_cr4, which
3787          * is in force while we are in guest mode.  Do not let guests control
3788          * this bit, even if host CR4.MCE == 0.
3789          */
3790         unsigned long hw_cr4 =
3791                 (cr4_read_shadow() & X86_CR4_MCE) |
3792                 (cr4 & ~X86_CR4_MCE) |
3793                 (to_vmx(vcpu)->rmode.vm86_active ?
3794                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3795
3796         if (cr4 & X86_CR4_VMXE) {
3797                 /*
3798                  * To use VMXON (and later other VMX instructions), a guest
3799                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3800                  * So basically the check on whether to allow nested VMX
3801                  * is here.
3802                  */
3803                 if (!nested_vmx_allowed(vcpu))
3804                         return 1;
3805         }
3806         if (to_vmx(vcpu)->nested.vmxon &&
3807             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3808                 return 1;
3809
3810         vcpu->arch.cr4 = cr4;
3811         if (enable_ept) {
3812                 if (!is_paging(vcpu)) {
3813                         hw_cr4 &= ~X86_CR4_PAE;
3814                         hw_cr4 |= X86_CR4_PSE;
3815                 } else if (!(cr4 & X86_CR4_PAE)) {
3816                         hw_cr4 &= ~X86_CR4_PAE;
3817                 }
3818         }
3819
3820         if (!enable_unrestricted_guest && !is_paging(vcpu))
3821                 /*
3822                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3823                  * hardware.  However KVM always uses paging mode without
3824                  * unrestricted guest.
3825                  * To emulate this behavior, SMEP/SMAP needs to be manually
3826                  * disabled when guest switches to non-paging mode.
3827                  */
3828                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3829
3830         vmcs_writel(CR4_READ_SHADOW, cr4);
3831         vmcs_writel(GUEST_CR4, hw_cr4);
3832         return 0;
3833 }
3834
3835 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3836                             struct kvm_segment *var, int seg)
3837 {
3838         struct vcpu_vmx *vmx = to_vmx(vcpu);
3839         u32 ar;
3840
3841         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3842                 *var = vmx->rmode.segs[seg];
3843                 if (seg == VCPU_SREG_TR
3844                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3845                         return;
3846                 var->base = vmx_read_guest_seg_base(vmx, seg);
3847                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3848                 return;
3849         }
3850         var->base = vmx_read_guest_seg_base(vmx, seg);
3851         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3852         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3853         ar = vmx_read_guest_seg_ar(vmx, seg);
3854         var->unusable = (ar >> 16) & 1;
3855         var->type = ar & 15;
3856         var->s = (ar >> 4) & 1;
3857         var->dpl = (ar >> 5) & 3;
3858         /*
3859          * Some userspaces do not preserve unusable property. Since usable
3860          * segment has to be present according to VMX spec we can use present
3861          * property to amend userspace bug by making unusable segment always
3862          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3863          * segment as unusable.
3864          */
3865         var->present = !var->unusable;
3866         var->avl = (ar >> 12) & 1;
3867         var->l = (ar >> 13) & 1;
3868         var->db = (ar >> 14) & 1;
3869         var->g = (ar >> 15) & 1;
3870 }
3871
3872 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3873 {
3874         struct kvm_segment s;
3875
3876         if (to_vmx(vcpu)->rmode.vm86_active) {
3877                 vmx_get_segment(vcpu, &s, seg);
3878                 return s.base;
3879         }
3880         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3881 }
3882
3883 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3884 {
3885         struct vcpu_vmx *vmx = to_vmx(vcpu);
3886
3887         if (unlikely(vmx->rmode.vm86_active))
3888                 return 0;
3889         else {
3890                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3891                 return VMX_AR_DPL(ar);
3892         }
3893 }
3894
3895 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3896 {
3897         u32 ar;
3898
3899         if (var->unusable || !var->present)
3900                 ar = 1 << 16;
3901         else {
3902                 ar = var->type & 15;
3903                 ar |= (var->s & 1) << 4;
3904                 ar |= (var->dpl & 3) << 5;
3905                 ar |= (var->present & 1) << 7;
3906                 ar |= (var->avl & 1) << 12;
3907                 ar |= (var->l & 1) << 13;
3908                 ar |= (var->db & 1) << 14;
3909                 ar |= (var->g & 1) << 15;
3910         }
3911
3912         return ar;
3913 }
3914
3915 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3916                             struct kvm_segment *var, int seg)
3917 {
3918         struct vcpu_vmx *vmx = to_vmx(vcpu);
3919         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3920
3921         vmx_segment_cache_clear(vmx);
3922
3923         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3924                 vmx->rmode.segs[seg] = *var;
3925                 if (seg == VCPU_SREG_TR)
3926                         vmcs_write16(sf->selector, var->selector);
3927                 else if (var->s)
3928                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3929                 goto out;
3930         }
3931
3932         vmcs_writel(sf->base, var->base);
3933         vmcs_write32(sf->limit, var->limit);
3934         vmcs_write16(sf->selector, var->selector);
3935
3936         /*
3937          *   Fix the "Accessed" bit in AR field of segment registers for older
3938          * qemu binaries.
3939          *   IA32 arch specifies that at the time of processor reset the
3940          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3941          * is setting it to 0 in the userland code. This causes invalid guest
3942          * state vmexit when "unrestricted guest" mode is turned on.
3943          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3944          * tree. Newer qemu binaries with that qemu fix would not need this
3945          * kvm hack.
3946          */
3947         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3948                 var->type |= 0x1; /* Accessed */
3949
3950         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3951
3952 out:
3953         vmx->emulation_required = emulation_required(vcpu);
3954 }
3955
3956 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3957 {
3958         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3959
3960         *db = (ar >> 14) & 1;
3961         *l = (ar >> 13) & 1;
3962 }
3963
3964 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3965 {
3966         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3967         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3968 }
3969
3970 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3971 {
3972         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3973         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3974 }
3975
3976 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3977 {
3978         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3979         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3980 }
3981
3982 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3983 {
3984         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3985         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3986 }
3987
3988 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3989 {
3990         struct kvm_segment var;
3991         u32 ar;
3992
3993         vmx_get_segment(vcpu, &var, seg);
3994         var.dpl = 0x3;
3995         if (seg == VCPU_SREG_CS)
3996                 var.type = 0x3;
3997         ar = vmx_segment_access_rights(&var);
3998
3999         if (var.base != (var.selector << 4))
4000                 return false;
4001         if (var.limit != 0xffff)
4002                 return false;
4003         if (ar != 0xf3)
4004                 return false;
4005
4006         return true;
4007 }
4008
4009 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4010 {
4011         struct kvm_segment cs;
4012         unsigned int cs_rpl;
4013
4014         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4015         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4016
4017         if (cs.unusable)
4018                 return false;
4019         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4020                 return false;
4021         if (!cs.s)
4022                 return false;
4023         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4024                 if (cs.dpl > cs_rpl)
4025                         return false;
4026         } else {
4027                 if (cs.dpl != cs_rpl)
4028                         return false;
4029         }
4030         if (!cs.present)
4031                 return false;
4032
4033         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4034         return true;
4035 }
4036
4037 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4038 {
4039         struct kvm_segment ss;
4040         unsigned int ss_rpl;
4041
4042         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4043         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4044
4045         if (ss.unusable)
4046                 return true;
4047         if (ss.type != 3 && ss.type != 7)
4048                 return false;
4049         if (!ss.s)
4050                 return false;
4051         if (ss.dpl != ss_rpl) /* DPL != RPL */
4052                 return false;
4053         if (!ss.present)
4054                 return false;
4055
4056         return true;
4057 }
4058
4059 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4060 {
4061         struct kvm_segment var;
4062         unsigned int rpl;
4063
4064         vmx_get_segment(vcpu, &var, seg);
4065         rpl = var.selector & SEGMENT_RPL_MASK;
4066
4067         if (var.unusable)
4068                 return true;
4069         if (!var.s)
4070                 return false;
4071         if (!var.present)
4072                 return false;
4073         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4074                 if (var.dpl < rpl) /* DPL < RPL */
4075                         return false;
4076         }
4077
4078         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4079          * rights flags
4080          */
4081         return true;
4082 }
4083
4084 static bool tr_valid(struct kvm_vcpu *vcpu)
4085 {
4086         struct kvm_segment tr;
4087
4088         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4089
4090         if (tr.unusable)
4091                 return false;
4092         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4093                 return false;
4094         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4095                 return false;
4096         if (!tr.present)
4097                 return false;
4098
4099         return true;
4100 }
4101
4102 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4103 {
4104         struct kvm_segment ldtr;
4105
4106         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4107
4108         if (ldtr.unusable)
4109                 return true;
4110         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4111                 return false;
4112         if (ldtr.type != 2)
4113                 return false;
4114         if (!ldtr.present)
4115                 return false;
4116
4117         return true;
4118 }
4119
4120 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4121 {
4122         struct kvm_segment cs, ss;
4123
4124         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4125         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4126
4127         return ((cs.selector & SEGMENT_RPL_MASK) ==
4128                  (ss.selector & SEGMENT_RPL_MASK));
4129 }
4130
4131 /*
4132  * Check if guest state is valid. Returns true if valid, false if
4133  * not.
4134  * We assume that registers are always usable
4135  */
4136 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4137 {
4138         if (enable_unrestricted_guest)
4139                 return true;
4140
4141         /* real mode guest state checks */
4142         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4143                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4144                         return false;
4145                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4146                         return false;
4147                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4148                         return false;
4149                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4150                         return false;
4151                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4152                         return false;
4153                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4154                         return false;
4155         } else {
4156         /* protected mode guest state checks */
4157                 if (!cs_ss_rpl_check(vcpu))
4158                         return false;
4159                 if (!code_segment_valid(vcpu))
4160                         return false;
4161                 if (!stack_segment_valid(vcpu))
4162                         return false;
4163                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4164                         return false;
4165                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4166                         return false;
4167                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4168                         return false;
4169                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4170                         return false;
4171                 if (!tr_valid(vcpu))
4172                         return false;
4173                 if (!ldtr_valid(vcpu))
4174                         return false;
4175         }
4176         /* TODO:
4177          * - Add checks on RIP
4178          * - Add checks on RFLAGS
4179          */
4180
4181         return true;
4182 }
4183
4184 static int init_rmode_tss(struct kvm *kvm)
4185 {
4186         gfn_t fn;
4187         u16 data = 0;
4188         int idx, r;
4189
4190         idx = srcu_read_lock(&kvm->srcu);
4191         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4192         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4193         if (r < 0)
4194                 goto out;
4195         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4196         r = kvm_write_guest_page(kvm, fn++, &data,
4197                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4198         if (r < 0)
4199                 goto out;
4200         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4201         if (r < 0)
4202                 goto out;
4203         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4204         if (r < 0)
4205                 goto out;
4206         data = ~0;
4207         r = kvm_write_guest_page(kvm, fn, &data,
4208                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4209                                  sizeof(u8));
4210 out:
4211         srcu_read_unlock(&kvm->srcu, idx);
4212         return r;
4213 }
4214
4215 static int init_rmode_identity_map(struct kvm *kvm)
4216 {
4217         int i, idx, r = 0;
4218         pfn_t identity_map_pfn;
4219         u32 tmp;
4220
4221         if (!enable_ept)
4222                 return 0;
4223
4224         /* Protect kvm->arch.ept_identity_pagetable_done. */
4225         mutex_lock(&kvm->slots_lock);
4226
4227         if (likely(kvm->arch.ept_identity_pagetable_done))
4228                 goto out2;
4229
4230         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4231
4232         r = alloc_identity_pagetable(kvm);
4233         if (r < 0)
4234                 goto out2;
4235
4236         idx = srcu_read_lock(&kvm->srcu);
4237         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4238         if (r < 0)
4239                 goto out;
4240         /* Set up identity-mapping pagetable for EPT in real mode */
4241         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4242                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4243                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4244                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4245                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4246                 if (r < 0)
4247                         goto out;
4248         }
4249         kvm->arch.ept_identity_pagetable_done = true;
4250
4251 out:
4252         srcu_read_unlock(&kvm->srcu, idx);
4253
4254 out2:
4255         mutex_unlock(&kvm->slots_lock);
4256         return r;
4257 }
4258
4259 static void seg_setup(int seg)
4260 {
4261         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4262         unsigned int ar;
4263
4264         vmcs_write16(sf->selector, 0);
4265         vmcs_writel(sf->base, 0);
4266         vmcs_write32(sf->limit, 0xffff);
4267         ar = 0x93;
4268         if (seg == VCPU_SREG_CS)
4269                 ar |= 0x08; /* code segment */
4270
4271         vmcs_write32(sf->ar_bytes, ar);
4272 }
4273
4274 static int alloc_apic_access_page(struct kvm *kvm)
4275 {
4276         struct page *page;
4277         int r = 0;
4278
4279         mutex_lock(&kvm->slots_lock);
4280         if (kvm->arch.apic_access_page_done)
4281                 goto out;
4282         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4283                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4284         if (r)
4285                 goto out;
4286
4287         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4288         if (is_error_page(page)) {
4289                 r = -EFAULT;
4290                 goto out;
4291         }
4292
4293         /*
4294          * Do not pin the page in memory, so that memory hot-unplug
4295          * is able to migrate it.
4296          */
4297         put_page(page);
4298         kvm->arch.apic_access_page_done = true;
4299 out:
4300         mutex_unlock(&kvm->slots_lock);
4301         return r;
4302 }
4303
4304 static int alloc_identity_pagetable(struct kvm *kvm)
4305 {
4306         /* Called with kvm->slots_lock held. */
4307
4308         int r = 0;
4309
4310         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4311
4312         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4313                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4314
4315         return r;
4316 }
4317
4318 static int allocate_vpid(void)
4319 {
4320         int vpid;
4321
4322         if (!enable_vpid)
4323                 return 0;
4324         spin_lock(&vmx_vpid_lock);
4325         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4326         if (vpid < VMX_NR_VPIDS)
4327                 __set_bit(vpid, vmx_vpid_bitmap);
4328         else
4329                 vpid = 0;
4330         spin_unlock(&vmx_vpid_lock);
4331         return vpid;
4332 }
4333
4334 static void free_vpid(int vpid)
4335 {
4336         if (!enable_vpid || vpid == 0)
4337                 return;
4338         spin_lock(&vmx_vpid_lock);
4339         __clear_bit(vpid, vmx_vpid_bitmap);
4340         spin_unlock(&vmx_vpid_lock);
4341 }
4342
4343 #define MSR_TYPE_R      1
4344 #define MSR_TYPE_W      2
4345 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4346                                                 u32 msr, int type)
4347 {
4348         int f = sizeof(unsigned long);
4349
4350         if (!cpu_has_vmx_msr_bitmap())
4351                 return;
4352
4353         /*
4354          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4355          * have the write-low and read-high bitmap offsets the wrong way round.
4356          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4357          */
4358         if (msr <= 0x1fff) {
4359                 if (type & MSR_TYPE_R)
4360                         /* read-low */
4361                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4362
4363                 if (type & MSR_TYPE_W)
4364                         /* write-low */
4365                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4366
4367         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4368                 msr &= 0x1fff;
4369                 if (type & MSR_TYPE_R)
4370                         /* read-high */
4371                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4372
4373                 if (type & MSR_TYPE_W)
4374                         /* write-high */
4375                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4376
4377         }
4378 }
4379
4380 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4381                                                 u32 msr, int type)
4382 {
4383         int f = sizeof(unsigned long);
4384
4385         if (!cpu_has_vmx_msr_bitmap())
4386                 return;
4387
4388         /*
4389          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4390          * have the write-low and read-high bitmap offsets the wrong way round.
4391          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4392          */
4393         if (msr <= 0x1fff) {
4394                 if (type & MSR_TYPE_R)
4395                         /* read-low */
4396                         __set_bit(msr, msr_bitmap + 0x000 / f);
4397
4398                 if (type & MSR_TYPE_W)
4399                         /* write-low */
4400                         __set_bit(msr, msr_bitmap + 0x800 / f);
4401
4402         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4403                 msr &= 0x1fff;
4404                 if (type & MSR_TYPE_R)
4405                         /* read-high */
4406                         __set_bit(msr, msr_bitmap + 0x400 / f);
4407
4408                 if (type & MSR_TYPE_W)
4409                         /* write-high */
4410                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4411
4412         }
4413 }
4414
4415 /*
4416  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4417  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4418  */
4419 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4420                                                unsigned long *msr_bitmap_nested,
4421                                                u32 msr, int type)
4422 {
4423         int f = sizeof(unsigned long);
4424
4425         if (!cpu_has_vmx_msr_bitmap()) {
4426                 WARN_ON(1);
4427                 return;
4428         }
4429
4430         /*
4431          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4432          * have the write-low and read-high bitmap offsets the wrong way round.
4433          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4434          */
4435         if (msr <= 0x1fff) {
4436                 if (type & MSR_TYPE_R &&
4437                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4438                         /* read-low */
4439                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4440
4441                 if (type & MSR_TYPE_W &&
4442                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4443                         /* write-low */
4444                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4445
4446         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4447                 msr &= 0x1fff;
4448                 if (type & MSR_TYPE_R &&
4449                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4450                         /* read-high */
4451                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4452
4453                 if (type & MSR_TYPE_W &&
4454                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4455                         /* write-high */
4456                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4457
4458         }
4459 }
4460
4461 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4462 {
4463         if (!longmode_only)
4464                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4465                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4466         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4467                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4468 }
4469
4470 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4471 {
4472         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4473                         msr, MSR_TYPE_R);
4474         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4475                         msr, MSR_TYPE_R);
4476 }
4477
4478 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4479 {
4480         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4481                         msr, MSR_TYPE_R);
4482         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4483                         msr, MSR_TYPE_R);
4484 }
4485
4486 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4487 {
4488         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4489                         msr, MSR_TYPE_W);
4490         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4491                         msr, MSR_TYPE_W);
4492 }
4493
4494 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4495 {
4496         return enable_apicv && lapic_in_kernel(vcpu);
4497 }
4498
4499 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4500 {
4501         struct vcpu_vmx *vmx = to_vmx(vcpu);
4502         int max_irr;
4503         void *vapic_page;
4504         u16 status;
4505
4506         if (vmx->nested.pi_desc &&
4507             vmx->nested.pi_pending) {
4508                 vmx->nested.pi_pending = false;
4509                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4510                         return 0;
4511
4512                 max_irr = find_last_bit(
4513                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4514
4515                 if (max_irr == 256)
4516                         return 0;
4517
4518                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4519                 if (!vapic_page) {
4520                         WARN_ON(1);
4521                         return -ENOMEM;
4522                 }
4523                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4524                 kunmap(vmx->nested.virtual_apic_page);
4525
4526                 status = vmcs_read16(GUEST_INTR_STATUS);
4527                 if ((u8)max_irr > ((u8)status & 0xff)) {
4528                         status &= ~0xff;
4529                         status |= (u8)max_irr;
4530                         vmcs_write16(GUEST_INTR_STATUS, status);
4531                 }
4532         }
4533         return 0;
4534 }
4535
4536 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4537 {
4538 #ifdef CONFIG_SMP
4539         if (vcpu->mode == IN_GUEST_MODE) {
4540                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4541
4542                 /*
4543                  * Currently, we don't support urgent interrupt,
4544                  * all interrupts are recognized as non-urgent
4545                  * interrupt, so we cannot post interrupts when
4546                  * 'SN' is set.
4547                  *
4548                  * If the vcpu is in guest mode, it means it is
4549                  * running instead of being scheduled out and
4550                  * waiting in the run queue, and that's the only
4551                  * case when 'SN' is set currently, warning if
4552                  * 'SN' is set.
4553                  */
4554                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4555
4556                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4557                                 POSTED_INTR_VECTOR);
4558                 return true;
4559         }
4560 #endif
4561         return false;
4562 }
4563
4564 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4565                                                 int vector)
4566 {
4567         struct vcpu_vmx *vmx = to_vmx(vcpu);
4568
4569         if (is_guest_mode(vcpu) &&
4570             vector == vmx->nested.posted_intr_nv) {
4571                 /* the PIR and ON have been set by L1. */
4572                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4573                 /*
4574                  * If a posted intr is not recognized by hardware,
4575                  * we will accomplish it in the next vmentry.
4576                  */
4577                 vmx->nested.pi_pending = true;
4578                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4579                 return 0;
4580         }
4581         return -1;
4582 }
4583 /*
4584  * Send interrupt to vcpu via posted interrupt way.
4585  * 1. If target vcpu is running(non-root mode), send posted interrupt
4586  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4587  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4588  * interrupt from PIR in next vmentry.
4589  */
4590 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4591 {
4592         struct vcpu_vmx *vmx = to_vmx(vcpu);
4593         int r;
4594
4595         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4596         if (!r)
4597                 return;
4598
4599         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4600                 return;
4601
4602         r = pi_test_and_set_on(&vmx->pi_desc);
4603         kvm_make_request(KVM_REQ_EVENT, vcpu);
4604         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4605                 kvm_vcpu_kick(vcpu);
4606 }
4607
4608 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4609 {
4610         struct vcpu_vmx *vmx = to_vmx(vcpu);
4611
4612         if (!pi_test_and_clear_on(&vmx->pi_desc))
4613                 return;
4614
4615         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4616 }
4617
4618 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4619 {
4620         return;
4621 }
4622
4623 /*
4624  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4625  * will not change in the lifetime of the guest.
4626  * Note that host-state that does change is set elsewhere. E.g., host-state
4627  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4628  */
4629 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4630 {
4631         u32 low32, high32;
4632         unsigned long tmpl;
4633         struct desc_ptr dt;
4634         unsigned long cr4;
4635
4636         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4637         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4638
4639         /* Save the most likely value for this task's CR4 in the VMCS. */
4640         cr4 = cr4_read_shadow();
4641         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4642         vmx->host_state.vmcs_host_cr4 = cr4;
4643
4644         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4645 #ifdef CONFIG_X86_64
4646         /*
4647          * Load null selectors, so we can avoid reloading them in
4648          * __vmx_load_host_state(), in case userspace uses the null selectors
4649          * too (the expected case).
4650          */
4651         vmcs_write16(HOST_DS_SELECTOR, 0);
4652         vmcs_write16(HOST_ES_SELECTOR, 0);
4653 #else
4654         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4655         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4656 #endif
4657         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4658         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4659
4660         native_store_idt(&dt);
4661         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4662         vmx->host_idt_base = dt.address;
4663
4664         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4665
4666         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4667         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4668         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4669         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4670
4671         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4672                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4673                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4674         }
4675 }
4676
4677 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4678 {
4679         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4680         if (enable_ept)
4681                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4682         if (is_guest_mode(&vmx->vcpu))
4683                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4684                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4685         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4686 }
4687
4688 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4689 {
4690         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4691
4692         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4693                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4694         return pin_based_exec_ctrl;
4695 }
4696
4697 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4698 {
4699         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4700
4701         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4702                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4703
4704         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4705                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4706 #ifdef CONFIG_X86_64
4707                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4708                                 CPU_BASED_CR8_LOAD_EXITING;
4709 #endif
4710         }
4711         if (!enable_ept)
4712                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4713                                 CPU_BASED_CR3_LOAD_EXITING  |
4714                                 CPU_BASED_INVLPG_EXITING;
4715         return exec_control;
4716 }
4717
4718 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4719 {
4720         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4721         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4722                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4723         if (vmx->vpid == 0)
4724                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4725         if (!enable_ept) {
4726                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4727                 enable_unrestricted_guest = 0;
4728                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4729                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4730         }
4731         if (!enable_unrestricted_guest)
4732                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4733         if (!ple_gap)
4734                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4735         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4736                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4737                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4738         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4739         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4740            (handle_vmptrld).
4741            We can NOT enable shadow_vmcs here because we don't have yet
4742            a current VMCS12
4743         */
4744         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4745
4746         if (!enable_pml)
4747                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4748
4749         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4750         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4751
4752         return exec_control;
4753 }
4754
4755 static void ept_set_mmio_spte_mask(void)
4756 {
4757         /*
4758          * EPT Misconfigurations can be generated if the value of bits 2:0
4759          * of an EPT paging-structure entry is 110b (write/execute).
4760          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4761          * spte.
4762          */
4763         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4764 }
4765
4766 #define VMX_XSS_EXIT_BITMAP 0
4767 /*
4768  * Sets up the vmcs for emulated real mode.
4769  */
4770 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4771 {
4772 #ifdef CONFIG_X86_64
4773         unsigned long a;
4774 #endif
4775         int i;
4776
4777         /* I/O */
4778         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4779         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4780
4781         if (enable_shadow_vmcs) {
4782                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4783                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4784         }
4785         if (cpu_has_vmx_msr_bitmap())
4786                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4787
4788         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4789
4790         /* Control */
4791         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4792
4793         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4794
4795         if (cpu_has_secondary_exec_ctrls())
4796                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4797                                 vmx_secondary_exec_control(vmx));
4798
4799         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4800                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4801                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4802                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4803                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4804
4805                 vmcs_write16(GUEST_INTR_STATUS, 0);
4806
4807                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4808                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4809         }
4810
4811         if (ple_gap) {
4812                 vmcs_write32(PLE_GAP, ple_gap);
4813                 vmx->ple_window = ple_window;
4814                 vmx->ple_window_dirty = true;
4815         }
4816
4817         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4818         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4819         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4820
4821         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4822         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4823         vmx_set_constant_host_state(vmx);
4824 #ifdef CONFIG_X86_64
4825         rdmsrl(MSR_FS_BASE, a);
4826         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4827         rdmsrl(MSR_GS_BASE, a);
4828         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4829 #else
4830         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4831         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4832 #endif
4833
4834         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4835         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4836         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4837         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4838         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4839
4840         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4841                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4842
4843         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4844                 u32 index = vmx_msr_index[i];
4845                 u32 data_low, data_high;
4846                 int j = vmx->nmsrs;
4847
4848                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4849                         continue;
4850                 if (wrmsr_safe(index, data_low, data_high) < 0)
4851                         continue;
4852                 vmx->guest_msrs[j].index = i;
4853                 vmx->guest_msrs[j].data = 0;
4854                 vmx->guest_msrs[j].mask = -1ull;
4855                 ++vmx->nmsrs;
4856         }
4857
4858
4859         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4860
4861         /* 22.2.1, 20.8.1 */
4862         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4863
4864         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4865         set_cr4_guest_host_mask(vmx);
4866
4867         if (vmx_xsaves_supported())
4868                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4869
4870         if (enable_pml) {
4871                 ASSERT(vmx->pml_pg);
4872                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4873                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4874         }
4875
4876         return 0;
4877 }
4878
4879 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4880 {
4881         struct vcpu_vmx *vmx = to_vmx(vcpu);
4882         struct msr_data apic_base_msr;
4883         u64 cr0;
4884
4885         vmx->rmode.vm86_active = 0;
4886
4887         vmx->soft_vnmi_blocked = 0;
4888
4889         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4890         kvm_set_cr8(vcpu, 0);
4891
4892         if (!init_event) {
4893                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4894                                      MSR_IA32_APICBASE_ENABLE;
4895                 if (kvm_vcpu_is_reset_bsp(vcpu))
4896                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4897                 apic_base_msr.host_initiated = true;
4898                 kvm_set_apic_base(vcpu, &apic_base_msr);
4899         }
4900
4901         vmx_segment_cache_clear(vmx);
4902
4903         seg_setup(VCPU_SREG_CS);
4904         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4905         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4906
4907         seg_setup(VCPU_SREG_DS);
4908         seg_setup(VCPU_SREG_ES);
4909         seg_setup(VCPU_SREG_FS);
4910         seg_setup(VCPU_SREG_GS);
4911         seg_setup(VCPU_SREG_SS);
4912
4913         vmcs_write16(GUEST_TR_SELECTOR, 0);
4914         vmcs_writel(GUEST_TR_BASE, 0);
4915         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4916         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4917
4918         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4919         vmcs_writel(GUEST_LDTR_BASE, 0);
4920         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4921         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4922
4923         if (!init_event) {
4924                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4925                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4926                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4927                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4928         }
4929
4930         vmcs_writel(GUEST_RFLAGS, 0x02);
4931         kvm_rip_write(vcpu, 0xfff0);
4932
4933         vmcs_writel(GUEST_GDTR_BASE, 0);
4934         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4935
4936         vmcs_writel(GUEST_IDTR_BASE, 0);
4937         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4938
4939         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4940         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4941         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4942
4943         setup_msrs(vmx);
4944
4945         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4946
4947         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4948                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4949                 if (cpu_need_tpr_shadow(vcpu))
4950                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4951                                      __pa(vcpu->arch.apic->regs));
4952                 vmcs_write32(TPR_THRESHOLD, 0);
4953         }
4954
4955         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4956
4957         if (vmx_cpu_uses_apicv(vcpu))
4958                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4959
4960         if (vmx->vpid != 0)
4961                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4962
4963         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4964         vmx->vcpu.arch.cr0 = cr0;
4965         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4966         vmx_set_cr4(vcpu, 0);
4967         vmx_set_efer(vcpu, 0);
4968         vmx_fpu_activate(vcpu);
4969         update_exception_bitmap(vcpu);
4970
4971         vpid_sync_context(vmx->vpid);
4972 }
4973
4974 /*
4975  * In nested virtualization, check if L1 asked to exit on external interrupts.
4976  * For most existing hypervisors, this will always return true.
4977  */
4978 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4979 {
4980         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4981                 PIN_BASED_EXT_INTR_MASK;
4982 }
4983
4984 /*
4985  * In nested virtualization, check if L1 has set
4986  * VM_EXIT_ACK_INTR_ON_EXIT
4987  */
4988 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4989 {
4990         return get_vmcs12(vcpu)->vm_exit_controls &
4991                 VM_EXIT_ACK_INTR_ON_EXIT;
4992 }
4993
4994 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4995 {
4996         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4997                 PIN_BASED_NMI_EXITING;
4998 }
4999
5000 static void enable_irq_window(struct kvm_vcpu *vcpu)
5001 {
5002         u32 cpu_based_vm_exec_control;
5003
5004         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5005         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5006         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5007 }
5008
5009 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5010 {
5011         u32 cpu_based_vm_exec_control;
5012
5013         if (!cpu_has_virtual_nmis() ||
5014             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5015                 enable_irq_window(vcpu);
5016                 return;
5017         }
5018
5019         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5020         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5021         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5022 }
5023
5024 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5025 {
5026         struct vcpu_vmx *vmx = to_vmx(vcpu);
5027         uint32_t intr;
5028         int irq = vcpu->arch.interrupt.nr;
5029
5030         trace_kvm_inj_virq(irq);
5031
5032         ++vcpu->stat.irq_injections;
5033         if (vmx->rmode.vm86_active) {
5034                 int inc_eip = 0;
5035                 if (vcpu->arch.interrupt.soft)
5036                         inc_eip = vcpu->arch.event_exit_inst_len;
5037                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5038                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5039                 return;
5040         }
5041         intr = irq | INTR_INFO_VALID_MASK;
5042         if (vcpu->arch.interrupt.soft) {
5043                 intr |= INTR_TYPE_SOFT_INTR;
5044                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5045                              vmx->vcpu.arch.event_exit_inst_len);
5046         } else
5047                 intr |= INTR_TYPE_EXT_INTR;
5048         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5049 }
5050
5051 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5052 {
5053         struct vcpu_vmx *vmx = to_vmx(vcpu);
5054
5055         if (is_guest_mode(vcpu))
5056                 return;
5057
5058         if (!cpu_has_virtual_nmis()) {
5059                 /*
5060                  * Tracking the NMI-blocked state in software is built upon
5061                  * finding the next open IRQ window. This, in turn, depends on
5062                  * well-behaving guests: They have to keep IRQs disabled at
5063                  * least as long as the NMI handler runs. Otherwise we may
5064                  * cause NMI nesting, maybe breaking the guest. But as this is
5065                  * highly unlikely, we can live with the residual risk.
5066                  */
5067                 vmx->soft_vnmi_blocked = 1;
5068                 vmx->vnmi_blocked_time = 0;
5069         }
5070
5071         ++vcpu->stat.nmi_injections;
5072         vmx->nmi_known_unmasked = false;
5073         if (vmx->rmode.vm86_active) {
5074                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5075                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5076                 return;
5077         }
5078         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5079                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5080 }
5081
5082 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5083 {
5084         if (!cpu_has_virtual_nmis())
5085                 return to_vmx(vcpu)->soft_vnmi_blocked;
5086         if (to_vmx(vcpu)->nmi_known_unmasked)
5087                 return false;
5088         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5089 }
5090
5091 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5092 {
5093         struct vcpu_vmx *vmx = to_vmx(vcpu);
5094
5095         if (!cpu_has_virtual_nmis()) {
5096                 if (vmx->soft_vnmi_blocked != masked) {
5097                         vmx->soft_vnmi_blocked = masked;
5098                         vmx->vnmi_blocked_time = 0;
5099                 }
5100         } else {
5101                 vmx->nmi_known_unmasked = !masked;
5102                 if (masked)
5103                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5104                                       GUEST_INTR_STATE_NMI);
5105                 else
5106                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5107                                         GUEST_INTR_STATE_NMI);
5108         }
5109 }
5110
5111 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5112 {
5113         if (to_vmx(vcpu)->nested.nested_run_pending)
5114                 return 0;
5115
5116         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5117                 return 0;
5118
5119         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5120                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5121                    | GUEST_INTR_STATE_NMI));
5122 }
5123
5124 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5125 {
5126         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5127                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5128                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5129                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5130 }
5131
5132 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5133 {
5134         int ret;
5135
5136         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5137                                     PAGE_SIZE * 3);
5138         if (ret)
5139                 return ret;
5140         kvm->arch.tss_addr = addr;
5141         return init_rmode_tss(kvm);
5142 }
5143
5144 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5145 {
5146         switch (vec) {
5147         case BP_VECTOR:
5148                 /*
5149                  * Update instruction length as we may reinject the exception
5150                  * from user space while in guest debugging mode.
5151                  */
5152                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5153                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5154                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5155                         return false;
5156                 /* fall through */
5157         case DB_VECTOR:
5158                 if (vcpu->guest_debug &
5159                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5160                         return false;
5161                 /* fall through */
5162         case DE_VECTOR:
5163         case OF_VECTOR:
5164         case BR_VECTOR:
5165         case UD_VECTOR:
5166         case DF_VECTOR:
5167         case SS_VECTOR:
5168         case GP_VECTOR:
5169         case MF_VECTOR:
5170                 return true;
5171         break;
5172         }
5173         return false;
5174 }
5175
5176 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5177                                   int vec, u32 err_code)
5178 {
5179         /*
5180          * Instruction with address size override prefix opcode 0x67
5181          * Cause the #SS fault with 0 error code in VM86 mode.
5182          */
5183         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5184                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5185                         if (vcpu->arch.halt_request) {
5186                                 vcpu->arch.halt_request = 0;
5187                                 return kvm_vcpu_halt(vcpu);
5188                         }
5189                         return 1;
5190                 }
5191                 return 0;
5192         }
5193
5194         /*
5195          * Forward all other exceptions that are valid in real mode.
5196          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5197          *        the required debugging infrastructure rework.
5198          */
5199         kvm_queue_exception(vcpu, vec);
5200         return 1;
5201 }
5202
5203 /*
5204  * Trigger machine check on the host. We assume all the MSRs are already set up
5205  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5206  * We pass a fake environment to the machine check handler because we want
5207  * the guest to be always treated like user space, no matter what context
5208  * it used internally.
5209  */
5210 static void kvm_machine_check(void)
5211 {
5212 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5213         struct pt_regs regs = {
5214                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5215                 .flags = X86_EFLAGS_IF,
5216         };
5217
5218         do_machine_check(&regs, 0);
5219 #endif
5220 }
5221
5222 static int handle_machine_check(struct kvm_vcpu *vcpu)
5223 {
5224         /* already handled by vcpu_run */
5225         return 1;
5226 }
5227
5228 static int handle_exception(struct kvm_vcpu *vcpu)
5229 {
5230         struct vcpu_vmx *vmx = to_vmx(vcpu);
5231         struct kvm_run *kvm_run = vcpu->run;
5232         u32 intr_info, ex_no, error_code;
5233         unsigned long cr2, rip, dr6;
5234         u32 vect_info;
5235         enum emulation_result er;
5236
5237         vect_info = vmx->idt_vectoring_info;
5238         intr_info = vmx->exit_intr_info;
5239
5240         if (is_machine_check(intr_info))
5241                 return handle_machine_check(vcpu);
5242
5243         if (is_nmi(intr_info))
5244                 return 1;  /* already handled by vmx_vcpu_run() */
5245
5246         if (is_no_device(intr_info)) {
5247                 vmx_fpu_activate(vcpu);
5248                 return 1;
5249         }
5250
5251         if (is_invalid_opcode(intr_info)) {
5252                 if (is_guest_mode(vcpu)) {
5253                         kvm_queue_exception(vcpu, UD_VECTOR);
5254                         return 1;
5255                 }
5256                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5257                 if (er != EMULATE_DONE)
5258                         kvm_queue_exception(vcpu, UD_VECTOR);
5259                 return 1;
5260         }
5261
5262         error_code = 0;
5263         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5264                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5265
5266         /*
5267          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5268          * MMIO, it is better to report an internal error.
5269          * See the comments in vmx_handle_exit.
5270          */
5271         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5272             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5273                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5274                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5275                 vcpu->run->internal.ndata = 3;
5276                 vcpu->run->internal.data[0] = vect_info;
5277                 vcpu->run->internal.data[1] = intr_info;
5278                 vcpu->run->internal.data[2] = error_code;
5279                 return 0;
5280         }
5281
5282         if (is_page_fault(intr_info)) {
5283                 /* EPT won't cause page fault directly */
5284                 BUG_ON(enable_ept);
5285                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5286                 trace_kvm_page_fault(cr2, error_code);
5287
5288                 if (kvm_event_needs_reinjection(vcpu))
5289                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5290                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5291         }
5292
5293         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5294
5295         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5296                 return handle_rmode_exception(vcpu, ex_no, error_code);
5297
5298         switch (ex_no) {
5299         case AC_VECTOR:
5300                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5301                 return 1;
5302         case DB_VECTOR:
5303                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5304                 if (!(vcpu->guest_debug &
5305                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5306                         vcpu->arch.dr6 &= ~15;
5307                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5308                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5309                                 skip_emulated_instruction(vcpu);
5310
5311                         kvm_queue_exception(vcpu, DB_VECTOR);
5312                         return 1;
5313                 }
5314                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5315                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5316                 /* fall through */
5317         case BP_VECTOR:
5318                 /*
5319                  * Update instruction length as we may reinject #BP from
5320                  * user space while in guest debugging mode. Reading it for
5321                  * #DB as well causes no harm, it is not used in that case.
5322                  */
5323                 vmx->vcpu.arch.event_exit_inst_len =
5324                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5325                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5326                 rip = kvm_rip_read(vcpu);
5327                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5328                 kvm_run->debug.arch.exception = ex_no;
5329                 break;
5330         default:
5331                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5332                 kvm_run->ex.exception = ex_no;
5333                 kvm_run->ex.error_code = error_code;
5334                 break;
5335         }
5336         return 0;
5337 }
5338
5339 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5340 {
5341         ++vcpu->stat.irq_exits;
5342         return 1;
5343 }
5344
5345 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5346 {
5347         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5348         return 0;
5349 }
5350
5351 static int handle_io(struct kvm_vcpu *vcpu)
5352 {
5353         unsigned long exit_qualification;
5354         int size, in, string;
5355         unsigned port;
5356
5357         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5358         string = (exit_qualification & 16) != 0;
5359         in = (exit_qualification & 8) != 0;
5360
5361         ++vcpu->stat.io_exits;
5362
5363         if (string || in)
5364                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5365
5366         port = exit_qualification >> 16;
5367         size = (exit_qualification & 7) + 1;
5368         skip_emulated_instruction(vcpu);
5369
5370         return kvm_fast_pio_out(vcpu, size, port);
5371 }
5372
5373 static void
5374 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5375 {
5376         /*
5377          * Patch in the VMCALL instruction:
5378          */
5379         hypercall[0] = 0x0f;
5380         hypercall[1] = 0x01;
5381         hypercall[2] = 0xc1;
5382 }
5383
5384 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5385 {
5386         unsigned long always_on = VMXON_CR0_ALWAYSON;
5387         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5388
5389         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5390                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5391             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5392                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5393         return (val & always_on) == always_on;
5394 }
5395
5396 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5397 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5398 {
5399         if (is_guest_mode(vcpu)) {
5400                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5401                 unsigned long orig_val = val;
5402
5403                 /*
5404                  * We get here when L2 changed cr0 in a way that did not change
5405                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5406                  * but did change L0 shadowed bits. So we first calculate the
5407                  * effective cr0 value that L1 would like to write into the
5408                  * hardware. It consists of the L2-owned bits from the new
5409                  * value combined with the L1-owned bits from L1's guest_cr0.
5410                  */
5411                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5412                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5413
5414                 if (!nested_cr0_valid(vcpu, val))
5415                         return 1;
5416
5417                 if (kvm_set_cr0(vcpu, val))
5418                         return 1;
5419                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5420                 return 0;
5421         } else {
5422                 if (to_vmx(vcpu)->nested.vmxon &&
5423                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5424                         return 1;
5425                 return kvm_set_cr0(vcpu, val);
5426         }
5427 }
5428
5429 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5430 {
5431         if (is_guest_mode(vcpu)) {
5432                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5433                 unsigned long orig_val = val;
5434
5435                 /* analogously to handle_set_cr0 */
5436                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5437                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5438                 if (kvm_set_cr4(vcpu, val))
5439                         return 1;
5440                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5441                 return 0;
5442         } else
5443                 return kvm_set_cr4(vcpu, val);
5444 }
5445
5446 /* called to set cr0 as approriate for clts instruction exit. */
5447 static void handle_clts(struct kvm_vcpu *vcpu)
5448 {
5449         if (is_guest_mode(vcpu)) {
5450                 /*
5451                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5452                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5453                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5454                  */
5455                 vmcs_writel(CR0_READ_SHADOW,
5456                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5457                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5458         } else
5459                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5460 }
5461
5462 static int handle_cr(struct kvm_vcpu *vcpu)
5463 {
5464         unsigned long exit_qualification, val;
5465         int cr;
5466         int reg;
5467         int err;
5468
5469         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5470         cr = exit_qualification & 15;
5471         reg = (exit_qualification >> 8) & 15;
5472         switch ((exit_qualification >> 4) & 3) {
5473         case 0: /* mov to cr */
5474                 val = kvm_register_readl(vcpu, reg);
5475                 trace_kvm_cr_write(cr, val);
5476                 switch (cr) {
5477                 case 0:
5478                         err = handle_set_cr0(vcpu, val);
5479                         kvm_complete_insn_gp(vcpu, err);
5480                         return 1;
5481                 case 3:
5482                         err = kvm_set_cr3(vcpu, val);
5483                         kvm_complete_insn_gp(vcpu, err);
5484                         return 1;
5485                 case 4:
5486                         err = handle_set_cr4(vcpu, val);
5487                         kvm_complete_insn_gp(vcpu, err);
5488                         return 1;
5489                 case 8: {
5490                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5491                                 u8 cr8 = (u8)val;
5492                                 err = kvm_set_cr8(vcpu, cr8);
5493                                 kvm_complete_insn_gp(vcpu, err);
5494                                 if (lapic_in_kernel(vcpu))
5495                                         return 1;
5496                                 if (cr8_prev <= cr8)
5497                                         return 1;
5498                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5499                                 return 0;
5500                         }
5501                 }
5502                 break;
5503         case 2: /* clts */
5504                 handle_clts(vcpu);
5505                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5506                 skip_emulated_instruction(vcpu);
5507                 vmx_fpu_activate(vcpu);
5508                 return 1;
5509         case 1: /*mov from cr*/
5510                 switch (cr) {
5511                 case 3:
5512                         val = kvm_read_cr3(vcpu);
5513                         kvm_register_write(vcpu, reg, val);
5514                         trace_kvm_cr_read(cr, val);
5515                         skip_emulated_instruction(vcpu);
5516                         return 1;
5517                 case 8:
5518                         val = kvm_get_cr8(vcpu);
5519                         kvm_register_write(vcpu, reg, val);
5520                         trace_kvm_cr_read(cr, val);
5521                         skip_emulated_instruction(vcpu);
5522                         return 1;
5523                 }
5524                 break;
5525         case 3: /* lmsw */
5526                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5527                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5528                 kvm_lmsw(vcpu, val);
5529
5530                 skip_emulated_instruction(vcpu);
5531                 return 1;
5532         default:
5533                 break;
5534         }
5535         vcpu->run->exit_reason = 0;
5536         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5537                (int)(exit_qualification >> 4) & 3, cr);
5538         return 0;
5539 }
5540
5541 static int handle_dr(struct kvm_vcpu *vcpu)
5542 {
5543         unsigned long exit_qualification;
5544         int dr, dr7, reg;
5545
5546         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5547         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5548
5549         /* First, if DR does not exist, trigger UD */
5550         if (!kvm_require_dr(vcpu, dr))
5551                 return 1;
5552
5553         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5554         if (!kvm_require_cpl(vcpu, 0))
5555                 return 1;
5556         dr7 = vmcs_readl(GUEST_DR7);
5557         if (dr7 & DR7_GD) {
5558                 /*
5559                  * As the vm-exit takes precedence over the debug trap, we
5560                  * need to emulate the latter, either for the host or the
5561                  * guest debugging itself.
5562                  */
5563                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5564                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5565                         vcpu->run->debug.arch.dr7 = dr7;
5566                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5567                         vcpu->run->debug.arch.exception = DB_VECTOR;
5568                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5569                         return 0;
5570                 } else {
5571                         vcpu->arch.dr6 &= ~15;
5572                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5573                         kvm_queue_exception(vcpu, DB_VECTOR);
5574                         return 1;
5575                 }
5576         }
5577
5578         if (vcpu->guest_debug == 0) {
5579                 u32 cpu_based_vm_exec_control;
5580
5581                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5582                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5583                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5584
5585                 /*
5586                  * No more DR vmexits; force a reload of the debug registers
5587                  * and reenter on this instruction.  The next vmexit will
5588                  * retrieve the full state of the debug registers.
5589                  */
5590                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5591                 return 1;
5592         }
5593
5594         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5595         if (exit_qualification & TYPE_MOV_FROM_DR) {
5596                 unsigned long val;
5597
5598                 if (kvm_get_dr(vcpu, dr, &val))
5599                         return 1;
5600                 kvm_register_write(vcpu, reg, val);
5601         } else
5602                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5603                         return 1;
5604
5605         skip_emulated_instruction(vcpu);
5606         return 1;
5607 }
5608
5609 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5610 {
5611         return vcpu->arch.dr6;
5612 }
5613
5614 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5615 {
5616 }
5617
5618 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5619 {
5620         u32 cpu_based_vm_exec_control;
5621
5622         get_debugreg(vcpu->arch.db[0], 0);
5623         get_debugreg(vcpu->arch.db[1], 1);
5624         get_debugreg(vcpu->arch.db[2], 2);
5625         get_debugreg(vcpu->arch.db[3], 3);
5626         get_debugreg(vcpu->arch.dr6, 6);
5627         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5628
5629         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5630
5631         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5632         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5633         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5634 }
5635
5636 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5637 {
5638         vmcs_writel(GUEST_DR7, val);
5639 }
5640
5641 static int handle_cpuid(struct kvm_vcpu *vcpu)
5642 {
5643         kvm_emulate_cpuid(vcpu);
5644         return 1;
5645 }
5646
5647 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5648 {
5649         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5650         struct msr_data msr_info;
5651
5652         msr_info.index = ecx;
5653         msr_info.host_initiated = false;
5654         if (vmx_get_msr(vcpu, &msr_info)) {
5655                 trace_kvm_msr_read_ex(ecx);
5656                 kvm_inject_gp(vcpu, 0);
5657                 return 1;
5658         }
5659
5660         trace_kvm_msr_read(ecx, msr_info.data);
5661
5662         /* FIXME: handling of bits 32:63 of rax, rdx */
5663         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5664         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5665         skip_emulated_instruction(vcpu);
5666         return 1;
5667 }
5668
5669 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5670 {
5671         struct msr_data msr;
5672         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5673         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5674                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5675
5676         msr.data = data;
5677         msr.index = ecx;
5678         msr.host_initiated = false;
5679         if (kvm_set_msr(vcpu, &msr) != 0) {
5680                 trace_kvm_msr_write_ex(ecx, data);
5681                 kvm_inject_gp(vcpu, 0);
5682                 return 1;
5683         }
5684
5685         trace_kvm_msr_write(ecx, data);
5686         skip_emulated_instruction(vcpu);
5687         return 1;
5688 }
5689
5690 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5691 {
5692         kvm_make_request(KVM_REQ_EVENT, vcpu);
5693         return 1;
5694 }
5695
5696 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5697 {
5698         u32 cpu_based_vm_exec_control;
5699
5700         /* clear pending irq */
5701         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5702         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5703         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5704
5705         kvm_make_request(KVM_REQ_EVENT, vcpu);
5706
5707         ++vcpu->stat.irq_window_exits;
5708         return 1;
5709 }
5710
5711 static int handle_halt(struct kvm_vcpu *vcpu)
5712 {
5713         return kvm_emulate_halt(vcpu);
5714 }
5715
5716 static int handle_vmcall(struct kvm_vcpu *vcpu)
5717 {
5718         kvm_emulate_hypercall(vcpu);
5719         return 1;
5720 }
5721
5722 static int handle_invd(struct kvm_vcpu *vcpu)
5723 {
5724         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5725 }
5726
5727 static int handle_invlpg(struct kvm_vcpu *vcpu)
5728 {
5729         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5730
5731         kvm_mmu_invlpg(vcpu, exit_qualification);
5732         skip_emulated_instruction(vcpu);
5733         return 1;
5734 }
5735
5736 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5737 {
5738         int err;
5739
5740         err = kvm_rdpmc(vcpu);
5741         kvm_complete_insn_gp(vcpu, err);
5742
5743         return 1;
5744 }
5745
5746 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5747 {
5748         kvm_emulate_wbinvd(vcpu);
5749         return 1;
5750 }
5751
5752 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5753 {
5754         u64 new_bv = kvm_read_edx_eax(vcpu);
5755         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5756
5757         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5758                 skip_emulated_instruction(vcpu);
5759         return 1;
5760 }
5761
5762 static int handle_xsaves(struct kvm_vcpu *vcpu)
5763 {
5764         skip_emulated_instruction(vcpu);
5765         WARN(1, "this should never happen\n");
5766         return 1;
5767 }
5768
5769 static int handle_xrstors(struct kvm_vcpu *vcpu)
5770 {
5771         skip_emulated_instruction(vcpu);
5772         WARN(1, "this should never happen\n");
5773         return 1;
5774 }
5775
5776 static int handle_apic_access(struct kvm_vcpu *vcpu)
5777 {
5778         if (likely(fasteoi)) {
5779                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5780                 int access_type, offset;
5781
5782                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5783                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5784                 /*
5785                  * Sane guest uses MOV to write EOI, with written value
5786                  * not cared. So make a short-circuit here by avoiding
5787                  * heavy instruction emulation.
5788                  */
5789                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5790                     (offset == APIC_EOI)) {
5791                         kvm_lapic_set_eoi(vcpu);
5792                         skip_emulated_instruction(vcpu);
5793                         return 1;
5794                 }
5795         }
5796         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5797 }
5798
5799 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5800 {
5801         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5802         int vector = exit_qualification & 0xff;
5803
5804         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5805         kvm_apic_set_eoi_accelerated(vcpu, vector);
5806         return 1;
5807 }
5808
5809 static int handle_apic_write(struct kvm_vcpu *vcpu)
5810 {
5811         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5812         u32 offset = exit_qualification & 0xfff;
5813
5814         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5815         kvm_apic_write_nodecode(vcpu, offset);
5816         return 1;
5817 }
5818
5819 static int handle_task_switch(struct kvm_vcpu *vcpu)
5820 {
5821         struct vcpu_vmx *vmx = to_vmx(vcpu);
5822         unsigned long exit_qualification;
5823         bool has_error_code = false;
5824         u32 error_code = 0;
5825         u16 tss_selector;
5826         int reason, type, idt_v, idt_index;
5827
5828         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5829         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5830         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5831
5832         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5833
5834         reason = (u32)exit_qualification >> 30;
5835         if (reason == TASK_SWITCH_GATE && idt_v) {
5836                 switch (type) {
5837                 case INTR_TYPE_NMI_INTR:
5838                         vcpu->arch.nmi_injected = false;
5839                         vmx_set_nmi_mask(vcpu, true);
5840                         break;
5841                 case INTR_TYPE_EXT_INTR:
5842                 case INTR_TYPE_SOFT_INTR:
5843                         kvm_clear_interrupt_queue(vcpu);
5844                         break;
5845                 case INTR_TYPE_HARD_EXCEPTION:
5846                         if (vmx->idt_vectoring_info &
5847                             VECTORING_INFO_DELIVER_CODE_MASK) {
5848                                 has_error_code = true;
5849                                 error_code =
5850                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5851                         }
5852                         /* fall through */
5853                 case INTR_TYPE_SOFT_EXCEPTION:
5854                         kvm_clear_exception_queue(vcpu);
5855                         break;
5856                 default:
5857                         break;
5858                 }
5859         }
5860         tss_selector = exit_qualification;
5861
5862         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5863                        type != INTR_TYPE_EXT_INTR &&
5864                        type != INTR_TYPE_NMI_INTR))
5865                 skip_emulated_instruction(vcpu);
5866
5867         if (kvm_task_switch(vcpu, tss_selector,
5868                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5869                             has_error_code, error_code) == EMULATE_FAIL) {
5870                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5871                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5872                 vcpu->run->internal.ndata = 0;
5873                 return 0;
5874         }
5875
5876         /*
5877          * TODO: What about debug traps on tss switch?
5878          *       Are we supposed to inject them and update dr6?
5879          */
5880
5881         return 1;
5882 }
5883
5884 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5885 {
5886         unsigned long exit_qualification;
5887         gpa_t gpa;
5888         u32 error_code;
5889         int gla_validity;
5890
5891         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5892
5893         gla_validity = (exit_qualification >> 7) & 0x3;
5894         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5895                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5896                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5897                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5898                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5899                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5900                         (long unsigned int)exit_qualification);
5901                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5902                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5903                 return 0;
5904         }
5905
5906         /*
5907          * EPT violation happened while executing iret from NMI,
5908          * "blocked by NMI" bit has to be set before next VM entry.
5909          * There are errata that may cause this bit to not be set:
5910          * AAK134, BY25.
5911          */
5912         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5913                         cpu_has_virtual_nmis() &&
5914                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5915                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5916
5917         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5918         trace_kvm_page_fault(gpa, exit_qualification);
5919
5920         /* It is a write fault? */
5921         error_code = exit_qualification & PFERR_WRITE_MASK;
5922         /* It is a fetch fault? */
5923         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5924         /* ept page table is present? */
5925         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5926
5927         vcpu->arch.exit_qualification = exit_qualification;
5928
5929         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5930 }
5931
5932 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5933 {
5934         int ret;
5935         gpa_t gpa;
5936
5937         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5938         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5939                 skip_emulated_instruction(vcpu);
5940                 trace_kvm_fast_mmio(gpa);
5941                 return 1;
5942         }
5943
5944         ret = handle_mmio_page_fault(vcpu, gpa, true);
5945         if (likely(ret == RET_MMIO_PF_EMULATE))
5946                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5947                                               EMULATE_DONE;
5948
5949         if (unlikely(ret == RET_MMIO_PF_INVALID))
5950                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5951
5952         if (unlikely(ret == RET_MMIO_PF_RETRY))
5953                 return 1;
5954
5955         /* It is the real ept misconfig */
5956         WARN_ON(1);
5957
5958         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5959         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5960
5961         return 0;
5962 }
5963
5964 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5965 {
5966         u32 cpu_based_vm_exec_control;
5967
5968         /* clear pending NMI */
5969         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5970         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5971         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5972         ++vcpu->stat.nmi_window_exits;
5973         kvm_make_request(KVM_REQ_EVENT, vcpu);
5974
5975         return 1;
5976 }
5977
5978 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5979 {
5980         struct vcpu_vmx *vmx = to_vmx(vcpu);
5981         enum emulation_result err = EMULATE_DONE;
5982         int ret = 1;
5983         u32 cpu_exec_ctrl;
5984         bool intr_window_requested;
5985         unsigned count = 130;
5986
5987         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5988         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5989
5990         while (vmx->emulation_required && count-- != 0) {
5991                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5992                         return handle_interrupt_window(&vmx->vcpu);
5993
5994                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5995                         return 1;
5996
5997                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5998
5999                 if (err == EMULATE_USER_EXIT) {
6000                         ++vcpu->stat.mmio_exits;
6001                         ret = 0;
6002                         goto out;
6003                 }
6004
6005                 if (err != EMULATE_DONE) {
6006                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6007                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6008                         vcpu->run->internal.ndata = 0;
6009                         return 0;
6010                 }
6011
6012                 if (vcpu->arch.halt_request) {
6013                         vcpu->arch.halt_request = 0;
6014                         ret = kvm_vcpu_halt(vcpu);
6015                         goto out;
6016                 }
6017
6018                 if (signal_pending(current))
6019                         goto out;
6020                 if (need_resched())
6021                         schedule();
6022         }
6023
6024 out:
6025         return ret;
6026 }
6027
6028 static int __grow_ple_window(int val)
6029 {
6030         if (ple_window_grow < 1)
6031                 return ple_window;
6032
6033         val = min(val, ple_window_actual_max);
6034
6035         if (ple_window_grow < ple_window)
6036                 val *= ple_window_grow;
6037         else
6038                 val += ple_window_grow;
6039
6040         return val;
6041 }
6042
6043 static int __shrink_ple_window(int val, int modifier, int minimum)
6044 {
6045         if (modifier < 1)
6046                 return ple_window;
6047
6048         if (modifier < ple_window)
6049                 val /= modifier;
6050         else
6051                 val -= modifier;
6052
6053         return max(val, minimum);
6054 }
6055
6056 static void grow_ple_window(struct kvm_vcpu *vcpu)
6057 {
6058         struct vcpu_vmx *vmx = to_vmx(vcpu);
6059         int old = vmx->ple_window;
6060
6061         vmx->ple_window = __grow_ple_window(old);
6062
6063         if (vmx->ple_window != old)
6064                 vmx->ple_window_dirty = true;
6065
6066         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6067 }
6068
6069 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6070 {
6071         struct vcpu_vmx *vmx = to_vmx(vcpu);
6072         int old = vmx->ple_window;
6073
6074         vmx->ple_window = __shrink_ple_window(old,
6075                                               ple_window_shrink, ple_window);
6076
6077         if (vmx->ple_window != old)
6078                 vmx->ple_window_dirty = true;
6079
6080         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6081 }
6082
6083 /*
6084  * ple_window_actual_max is computed to be one grow_ple_window() below
6085  * ple_window_max. (See __grow_ple_window for the reason.)
6086  * This prevents overflows, because ple_window_max is int.
6087  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6088  * this process.
6089  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6090  */
6091 static void update_ple_window_actual_max(void)
6092 {
6093         ple_window_actual_max =
6094                         __shrink_ple_window(max(ple_window_max, ple_window),
6095                                             ple_window_grow, INT_MIN);
6096 }
6097
6098 /*
6099  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6100  */
6101 static void wakeup_handler(void)
6102 {
6103         struct kvm_vcpu *vcpu;
6104         int cpu = smp_processor_id();
6105
6106         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6107         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6108                         blocked_vcpu_list) {
6109                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6110
6111                 if (pi_test_on(pi_desc) == 1)
6112                         kvm_vcpu_kick(vcpu);
6113         }
6114         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6115 }
6116
6117 static __init int hardware_setup(void)
6118 {
6119         int r = -ENOMEM, i, msr;
6120
6121         rdmsrl_safe(MSR_EFER, &host_efer);
6122
6123         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6124                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6125
6126         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6127         if (!vmx_io_bitmap_a)
6128                 return r;
6129
6130         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6131         if (!vmx_io_bitmap_b)
6132                 goto out;
6133
6134         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6135         if (!vmx_msr_bitmap_legacy)
6136                 goto out1;
6137
6138         vmx_msr_bitmap_legacy_x2apic =
6139                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6140         if (!vmx_msr_bitmap_legacy_x2apic)
6141                 goto out2;
6142
6143         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6144         if (!vmx_msr_bitmap_longmode)
6145                 goto out3;
6146
6147         vmx_msr_bitmap_longmode_x2apic =
6148                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6149         if (!vmx_msr_bitmap_longmode_x2apic)
6150                 goto out4;
6151
6152         if (nested) {
6153                 vmx_msr_bitmap_nested =
6154                         (unsigned long *)__get_free_page(GFP_KERNEL);
6155                 if (!vmx_msr_bitmap_nested)
6156                         goto out5;
6157         }
6158
6159         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6160         if (!vmx_vmread_bitmap)
6161                 goto out6;
6162
6163         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6164         if (!vmx_vmwrite_bitmap)
6165                 goto out7;
6166
6167         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6168         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6169
6170         /*
6171          * Allow direct access to the PC debug port (it is often used for I/O
6172          * delays, but the vmexits simply slow things down).
6173          */
6174         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6175         clear_bit(0x80, vmx_io_bitmap_a);
6176
6177         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6178
6179         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6180         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6181         if (nested)
6182                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6183
6184         if (setup_vmcs_config(&vmcs_config) < 0) {
6185                 r = -EIO;
6186                 goto out8;
6187         }
6188
6189         if (boot_cpu_has(X86_FEATURE_NX))
6190                 kvm_enable_efer_bits(EFER_NX);
6191
6192         if (!cpu_has_vmx_vpid())
6193                 enable_vpid = 0;
6194         if (!cpu_has_vmx_shadow_vmcs())
6195                 enable_shadow_vmcs = 0;
6196         if (enable_shadow_vmcs)
6197                 init_vmcs_shadow_fields();
6198
6199         if (!cpu_has_vmx_ept() ||
6200             !cpu_has_vmx_ept_4levels()) {
6201                 enable_ept = 0;
6202                 enable_unrestricted_guest = 0;
6203                 enable_ept_ad_bits = 0;
6204         }
6205
6206         if (!cpu_has_vmx_ept_ad_bits())
6207                 enable_ept_ad_bits = 0;
6208
6209         if (!cpu_has_vmx_unrestricted_guest())
6210                 enable_unrestricted_guest = 0;
6211
6212         if (!cpu_has_vmx_flexpriority())
6213                 flexpriority_enabled = 0;
6214
6215         /*
6216          * set_apic_access_page_addr() is used to reload apic access
6217          * page upon invalidation.  No need to do anything if not
6218          * using the APIC_ACCESS_ADDR VMCS field.
6219          */
6220         if (!flexpriority_enabled)
6221                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6222
6223         if (!cpu_has_vmx_tpr_shadow())
6224                 kvm_x86_ops->update_cr8_intercept = NULL;
6225
6226         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6227                 kvm_disable_largepages();
6228
6229         if (!cpu_has_vmx_ple())
6230                 ple_gap = 0;
6231
6232         if (!cpu_has_vmx_apicv())
6233                 enable_apicv = 0;
6234
6235         if (cpu_has_vmx_tsc_scaling()) {
6236                 kvm_has_tsc_control = true;
6237                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6238                 kvm_tsc_scaling_ratio_frac_bits = 48;
6239         }
6240
6241         if (enable_apicv)
6242                 kvm_x86_ops->update_cr8_intercept = NULL;
6243         else {
6244                 kvm_x86_ops->hwapic_irr_update = NULL;
6245                 kvm_x86_ops->hwapic_isr_update = NULL;
6246                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6247                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6248         }
6249
6250         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6251         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6252         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6253         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6254         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6255         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6256         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6257
6258         memcpy(vmx_msr_bitmap_legacy_x2apic,
6259                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6260         memcpy(vmx_msr_bitmap_longmode_x2apic,
6261                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6262
6263         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6264
6265         if (enable_apicv) {
6266                 for (msr = 0x800; msr <= 0x8ff; msr++)
6267                         vmx_disable_intercept_msr_read_x2apic(msr);
6268
6269                 /* According SDM, in x2apic mode, the whole id reg is used.
6270                  * But in KVM, it only use the highest eight bits. Need to
6271                  * intercept it */
6272                 vmx_enable_intercept_msr_read_x2apic(0x802);
6273                 /* TMCCT */
6274                 vmx_enable_intercept_msr_read_x2apic(0x839);
6275                 /* TPR */
6276                 vmx_disable_intercept_msr_write_x2apic(0x808);
6277                 /* EOI */
6278                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6279                 /* SELF-IPI */
6280                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6281         }
6282
6283         if (enable_ept) {
6284                 kvm_mmu_set_mask_ptes(0ull,
6285                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6286                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6287                         0ull, VMX_EPT_EXECUTABLE_MASK);
6288                 ept_set_mmio_spte_mask();
6289                 kvm_enable_tdp();
6290         } else
6291                 kvm_disable_tdp();
6292
6293         update_ple_window_actual_max();
6294
6295         /*
6296          * Only enable PML when hardware supports PML feature, and both EPT
6297          * and EPT A/D bit features are enabled -- PML depends on them to work.
6298          */
6299         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6300                 enable_pml = 0;
6301
6302         if (!enable_pml) {
6303                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6304                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6305                 kvm_x86_ops->flush_log_dirty = NULL;
6306                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6307         }
6308
6309         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6310
6311         return alloc_kvm_area();
6312
6313 out8:
6314         free_page((unsigned long)vmx_vmwrite_bitmap);
6315 out7:
6316         free_page((unsigned long)vmx_vmread_bitmap);
6317 out6:
6318         if (nested)
6319                 free_page((unsigned long)vmx_msr_bitmap_nested);
6320 out5:
6321         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6322 out4:
6323         free_page((unsigned long)vmx_msr_bitmap_longmode);
6324 out3:
6325         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6326 out2:
6327         free_page((unsigned long)vmx_msr_bitmap_legacy);
6328 out1:
6329         free_page((unsigned long)vmx_io_bitmap_b);
6330 out:
6331         free_page((unsigned long)vmx_io_bitmap_a);
6332
6333     return r;
6334 }
6335
6336 static __exit void hardware_unsetup(void)
6337 {
6338         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6339         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6340         free_page((unsigned long)vmx_msr_bitmap_legacy);
6341         free_page((unsigned long)vmx_msr_bitmap_longmode);
6342         free_page((unsigned long)vmx_io_bitmap_b);
6343         free_page((unsigned long)vmx_io_bitmap_a);
6344         free_page((unsigned long)vmx_vmwrite_bitmap);
6345         free_page((unsigned long)vmx_vmread_bitmap);
6346         if (nested)
6347                 free_page((unsigned long)vmx_msr_bitmap_nested);
6348
6349         free_kvm_area();
6350 }
6351
6352 /*
6353  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6354  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6355  */
6356 static int handle_pause(struct kvm_vcpu *vcpu)
6357 {
6358         if (ple_gap)
6359                 grow_ple_window(vcpu);
6360
6361         skip_emulated_instruction(vcpu);
6362         kvm_vcpu_on_spin(vcpu);
6363
6364         return 1;
6365 }
6366
6367 static int handle_nop(struct kvm_vcpu *vcpu)
6368 {
6369         skip_emulated_instruction(vcpu);
6370         return 1;
6371 }
6372
6373 static int handle_mwait(struct kvm_vcpu *vcpu)
6374 {
6375         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6376         return handle_nop(vcpu);
6377 }
6378
6379 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6380 {
6381         return 1;
6382 }
6383
6384 static int handle_monitor(struct kvm_vcpu *vcpu)
6385 {
6386         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6387         return handle_nop(vcpu);
6388 }
6389
6390 /*
6391  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6392  * We could reuse a single VMCS for all the L2 guests, but we also want the
6393  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6394  * allows keeping them loaded on the processor, and in the future will allow
6395  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6396  * every entry if they never change.
6397  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6398  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6399  *
6400  * The following functions allocate and free a vmcs02 in this pool.
6401  */
6402
6403 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6404 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6405 {
6406         struct vmcs02_list *item;
6407         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6408                 if (item->vmptr == vmx->nested.current_vmptr) {
6409                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6410                         return &item->vmcs02;
6411                 }
6412
6413         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6414                 /* Recycle the least recently used VMCS. */
6415                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6416                         struct vmcs02_list, list);
6417                 item->vmptr = vmx->nested.current_vmptr;
6418                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6419                 return &item->vmcs02;
6420         }
6421
6422         /* Create a new VMCS */
6423         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6424         if (!item)
6425                 return NULL;
6426         item->vmcs02.vmcs = alloc_vmcs();
6427         if (!item->vmcs02.vmcs) {
6428                 kfree(item);
6429                 return NULL;
6430         }
6431         loaded_vmcs_init(&item->vmcs02);
6432         item->vmptr = vmx->nested.current_vmptr;
6433         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6434         vmx->nested.vmcs02_num++;
6435         return &item->vmcs02;
6436 }
6437
6438 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6439 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6440 {
6441         struct vmcs02_list *item;
6442         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6443                 if (item->vmptr == vmptr) {
6444                         free_loaded_vmcs(&item->vmcs02);
6445                         list_del(&item->list);
6446                         kfree(item);
6447                         vmx->nested.vmcs02_num--;
6448                         return;
6449                 }
6450 }
6451
6452 /*
6453  * Free all VMCSs saved for this vcpu, except the one pointed by
6454  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6455  * must be &vmx->vmcs01.
6456  */
6457 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6458 {
6459         struct vmcs02_list *item, *n;
6460
6461         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6462         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6463                 /*
6464                  * Something will leak if the above WARN triggers.  Better than
6465                  * a use-after-free.
6466                  */
6467                 if (vmx->loaded_vmcs == &item->vmcs02)
6468                         continue;
6469
6470                 free_loaded_vmcs(&item->vmcs02);
6471                 list_del(&item->list);
6472                 kfree(item);
6473                 vmx->nested.vmcs02_num--;
6474         }
6475 }
6476
6477 /*
6478  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6479  * set the success or error code of an emulated VMX instruction, as specified
6480  * by Vol 2B, VMX Instruction Reference, "Conventions".
6481  */
6482 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6483 {
6484         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6485                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6486                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6487 }
6488
6489 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6490 {
6491         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6492                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6493                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6494                         | X86_EFLAGS_CF);
6495 }
6496
6497 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6498                                         u32 vm_instruction_error)
6499 {
6500         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6501                 /*
6502                  * failValid writes the error number to the current VMCS, which
6503                  * can't be done there isn't a current VMCS.
6504                  */
6505                 nested_vmx_failInvalid(vcpu);
6506                 return;
6507         }
6508         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6509                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6510                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6511                         | X86_EFLAGS_ZF);
6512         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6513         /*
6514          * We don't need to force a shadow sync because
6515          * VM_INSTRUCTION_ERROR is not shadowed
6516          */
6517 }
6518
6519 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6520 {
6521         /* TODO: not to reset guest simply here. */
6522         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6523         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6524 }
6525
6526 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6527 {
6528         struct vcpu_vmx *vmx =
6529                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6530
6531         vmx->nested.preemption_timer_expired = true;
6532         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6533         kvm_vcpu_kick(&vmx->vcpu);
6534
6535         return HRTIMER_NORESTART;
6536 }
6537
6538 /*
6539  * Decode the memory-address operand of a vmx instruction, as recorded on an
6540  * exit caused by such an instruction (run by a guest hypervisor).
6541  * On success, returns 0. When the operand is invalid, returns 1 and throws
6542  * #UD or #GP.
6543  */
6544 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6545                                  unsigned long exit_qualification,
6546                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6547 {
6548         gva_t off;
6549         bool exn;
6550         struct kvm_segment s;
6551
6552         /*
6553          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6554          * Execution", on an exit, vmx_instruction_info holds most of the
6555          * addressing components of the operand. Only the displacement part
6556          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6557          * For how an actual address is calculated from all these components,
6558          * refer to Vol. 1, "Operand Addressing".
6559          */
6560         int  scaling = vmx_instruction_info & 3;
6561         int  addr_size = (vmx_instruction_info >> 7) & 7;
6562         bool is_reg = vmx_instruction_info & (1u << 10);
6563         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6564         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6565         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6566         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6567         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6568
6569         if (is_reg) {
6570                 kvm_queue_exception(vcpu, UD_VECTOR);
6571                 return 1;
6572         }
6573
6574         /* Addr = segment_base + offset */
6575         /* offset = base + [index * scale] + displacement */
6576         off = exit_qualification; /* holds the displacement */
6577         if (base_is_valid)
6578                 off += kvm_register_read(vcpu, base_reg);
6579         if (index_is_valid)
6580                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6581         vmx_get_segment(vcpu, &s, seg_reg);
6582         *ret = s.base + off;
6583
6584         if (addr_size == 1) /* 32 bit */
6585                 *ret &= 0xffffffff;
6586
6587         /* Checks for #GP/#SS exceptions. */
6588         exn = false;
6589         if (is_long_mode(vcpu)) {
6590                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6591                  * non-canonical form. This is the only check on the memory
6592                  * destination for long mode!
6593                  */
6594                 exn = is_noncanonical_address(*ret);
6595         } else if (is_protmode(vcpu)) {
6596                 /* Protected mode: apply checks for segment validity in the
6597                  * following order:
6598                  * - segment type check (#GP(0) may be thrown)
6599                  * - usability check (#GP(0)/#SS(0))
6600                  * - limit check (#GP(0)/#SS(0))
6601                  */
6602                 if (wr)
6603                         /* #GP(0) if the destination operand is located in a
6604                          * read-only data segment or any code segment.
6605                          */
6606                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6607                 else
6608                         /* #GP(0) if the source operand is located in an
6609                          * execute-only code segment
6610                          */
6611                         exn = ((s.type & 0xa) == 8);
6612                 if (exn) {
6613                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6614                         return 1;
6615                 }
6616                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6617                  */
6618                 exn = (s.unusable != 0);
6619                 /* Protected mode: #GP(0)/#SS(0) if the memory
6620                  * operand is outside the segment limit.
6621                  */
6622                 exn = exn || (off + sizeof(u64) > s.limit);
6623         }
6624         if (exn) {
6625                 kvm_queue_exception_e(vcpu,
6626                                       seg_reg == VCPU_SREG_SS ?
6627                                                 SS_VECTOR : GP_VECTOR,
6628                                       0);
6629                 return 1;
6630         }
6631
6632         return 0;
6633 }
6634
6635 /*
6636  * This function performs the various checks including
6637  * - if it's 4KB aligned
6638  * - No bits beyond the physical address width are set
6639  * - Returns 0 on success or else 1
6640  * (Intel SDM Section 30.3)
6641  */
6642 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6643                                   gpa_t *vmpointer)
6644 {
6645         gva_t gva;
6646         gpa_t vmptr;
6647         struct x86_exception e;
6648         struct page *page;
6649         struct vcpu_vmx *vmx = to_vmx(vcpu);
6650         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6651
6652         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6653                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6654                 return 1;
6655
6656         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6657                                 sizeof(vmptr), &e)) {
6658                 kvm_inject_page_fault(vcpu, &e);
6659                 return 1;
6660         }
6661
6662         switch (exit_reason) {
6663         case EXIT_REASON_VMON:
6664                 /*
6665                  * SDM 3: 24.11.5
6666                  * The first 4 bytes of VMXON region contain the supported
6667                  * VMCS revision identifier
6668                  *
6669                  * Note - IA32_VMX_BASIC[48] will never be 1
6670                  * for the nested case;
6671                  * which replaces physical address width with 32
6672                  *
6673                  */
6674                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6675                         nested_vmx_failInvalid(vcpu);
6676                         skip_emulated_instruction(vcpu);
6677                         return 1;
6678                 }
6679
6680                 page = nested_get_page(vcpu, vmptr);
6681                 if (page == NULL) {
6682                         nested_vmx_failInvalid(vcpu);
6683                         skip_emulated_instruction(vcpu);
6684                         return 1;
6685                 }
6686                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6687                         kunmap(page);
6688                         nested_release_page_clean(page);
6689                         nested_vmx_failInvalid(vcpu);
6690                         skip_emulated_instruction(vcpu);
6691                         return 1;
6692                 }
6693                 kunmap(page);
6694                 nested_release_page_clean(page);
6695                 vmx->nested.vmxon_ptr = vmptr;
6696                 break;
6697         case EXIT_REASON_VMCLEAR:
6698                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6699                         nested_vmx_failValid(vcpu,
6700                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6701                         skip_emulated_instruction(vcpu);
6702                         return 1;
6703                 }
6704
6705                 if (vmptr == vmx->nested.vmxon_ptr) {
6706                         nested_vmx_failValid(vcpu,
6707                                              VMXERR_VMCLEAR_VMXON_POINTER);
6708                         skip_emulated_instruction(vcpu);
6709                         return 1;
6710                 }
6711                 break;
6712         case EXIT_REASON_VMPTRLD:
6713                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6714                         nested_vmx_failValid(vcpu,
6715                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6716                         skip_emulated_instruction(vcpu);
6717                         return 1;
6718                 }
6719
6720                 if (vmptr == vmx->nested.vmxon_ptr) {
6721                         nested_vmx_failValid(vcpu,
6722                                              VMXERR_VMCLEAR_VMXON_POINTER);
6723                         skip_emulated_instruction(vcpu);
6724                         return 1;
6725                 }
6726                 break;
6727         default:
6728                 return 1; /* shouldn't happen */
6729         }
6730
6731         if (vmpointer)
6732                 *vmpointer = vmptr;
6733         return 0;
6734 }
6735
6736 /*
6737  * Emulate the VMXON instruction.
6738  * Currently, we just remember that VMX is active, and do not save or even
6739  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6740  * do not currently need to store anything in that guest-allocated memory
6741  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6742  * argument is different from the VMXON pointer (which the spec says they do).
6743  */
6744 static int handle_vmon(struct kvm_vcpu *vcpu)
6745 {
6746         struct kvm_segment cs;
6747         struct vcpu_vmx *vmx = to_vmx(vcpu);
6748         struct vmcs *shadow_vmcs;
6749         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6750                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6751
6752         /* The Intel VMX Instruction Reference lists a bunch of bits that
6753          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6754          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6755          * Otherwise, we should fail with #UD. We test these now:
6756          */
6757         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6758             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6759             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6760                 kvm_queue_exception(vcpu, UD_VECTOR);
6761                 return 1;
6762         }
6763
6764         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6765         if (is_long_mode(vcpu) && !cs.l) {
6766                 kvm_queue_exception(vcpu, UD_VECTOR);
6767                 return 1;
6768         }
6769
6770         if (vmx_get_cpl(vcpu)) {
6771                 kvm_inject_gp(vcpu, 0);
6772                 return 1;
6773         }
6774
6775         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6776                 return 1;
6777
6778         if (vmx->nested.vmxon) {
6779                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6780                 skip_emulated_instruction(vcpu);
6781                 return 1;
6782         }
6783
6784         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6785                         != VMXON_NEEDED_FEATURES) {
6786                 kvm_inject_gp(vcpu, 0);
6787                 return 1;
6788         }
6789
6790         if (enable_shadow_vmcs) {
6791                 shadow_vmcs = alloc_vmcs();
6792                 if (!shadow_vmcs)
6793                         return -ENOMEM;
6794                 /* mark vmcs as shadow */
6795                 shadow_vmcs->revision_id |= (1u << 31);
6796                 /* init shadow vmcs */
6797                 vmcs_clear(shadow_vmcs);
6798                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6799         }
6800
6801         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6802         vmx->nested.vmcs02_num = 0;
6803
6804         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6805                      HRTIMER_MODE_REL);
6806         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6807
6808         vmx->nested.vmxon = true;
6809
6810         skip_emulated_instruction(vcpu);
6811         nested_vmx_succeed(vcpu);
6812         return 1;
6813 }
6814
6815 /*
6816  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6817  * for running VMX instructions (except VMXON, whose prerequisites are
6818  * slightly different). It also specifies what exception to inject otherwise.
6819  */
6820 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6821 {
6822         struct kvm_segment cs;
6823         struct vcpu_vmx *vmx = to_vmx(vcpu);
6824
6825         if (!vmx->nested.vmxon) {
6826                 kvm_queue_exception(vcpu, UD_VECTOR);
6827                 return 0;
6828         }
6829
6830         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6831         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6832             (is_long_mode(vcpu) && !cs.l)) {
6833                 kvm_queue_exception(vcpu, UD_VECTOR);
6834                 return 0;
6835         }
6836
6837         if (vmx_get_cpl(vcpu)) {
6838                 kvm_inject_gp(vcpu, 0);
6839                 return 0;
6840         }
6841
6842         return 1;
6843 }
6844
6845 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6846 {
6847         if (vmx->nested.current_vmptr == -1ull)
6848                 return;
6849
6850         /* current_vmptr and current_vmcs12 are always set/reset together */
6851         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6852                 return;
6853
6854         if (enable_shadow_vmcs) {
6855                 /* copy to memory all shadowed fields in case
6856                    they were modified */
6857                 copy_shadow_to_vmcs12(vmx);
6858                 vmx->nested.sync_shadow_vmcs = false;
6859                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6860                                 SECONDARY_EXEC_SHADOW_VMCS);
6861                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6862         }
6863         vmx->nested.posted_intr_nv = -1;
6864         kunmap(vmx->nested.current_vmcs12_page);
6865         nested_release_page(vmx->nested.current_vmcs12_page);
6866         vmx->nested.current_vmptr = -1ull;
6867         vmx->nested.current_vmcs12 = NULL;
6868 }
6869
6870 /*
6871  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6872  * just stops using VMX.
6873  */
6874 static void free_nested(struct vcpu_vmx *vmx)
6875 {
6876         if (!vmx->nested.vmxon)
6877                 return;
6878
6879         vmx->nested.vmxon = false;
6880         free_vpid(vmx->nested.vpid02);
6881         nested_release_vmcs12(vmx);
6882         if (enable_shadow_vmcs)
6883                 free_vmcs(vmx->nested.current_shadow_vmcs);
6884         /* Unpin physical memory we referred to in current vmcs02 */
6885         if (vmx->nested.apic_access_page) {
6886                 nested_release_page(vmx->nested.apic_access_page);
6887                 vmx->nested.apic_access_page = NULL;
6888         }
6889         if (vmx->nested.virtual_apic_page) {
6890                 nested_release_page(vmx->nested.virtual_apic_page);
6891                 vmx->nested.virtual_apic_page = NULL;
6892         }
6893         if (vmx->nested.pi_desc_page) {
6894                 kunmap(vmx->nested.pi_desc_page);
6895                 nested_release_page(vmx->nested.pi_desc_page);
6896                 vmx->nested.pi_desc_page = NULL;
6897                 vmx->nested.pi_desc = NULL;
6898         }
6899
6900         nested_free_all_saved_vmcss(vmx);
6901 }
6902
6903 /* Emulate the VMXOFF instruction */
6904 static int handle_vmoff(struct kvm_vcpu *vcpu)
6905 {
6906         if (!nested_vmx_check_permission(vcpu))
6907                 return 1;
6908         free_nested(to_vmx(vcpu));
6909         skip_emulated_instruction(vcpu);
6910         nested_vmx_succeed(vcpu);
6911         return 1;
6912 }
6913
6914 /* Emulate the VMCLEAR instruction */
6915 static int handle_vmclear(struct kvm_vcpu *vcpu)
6916 {
6917         struct vcpu_vmx *vmx = to_vmx(vcpu);
6918         gpa_t vmptr;
6919         struct vmcs12 *vmcs12;
6920         struct page *page;
6921
6922         if (!nested_vmx_check_permission(vcpu))
6923                 return 1;
6924
6925         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6926                 return 1;
6927
6928         if (vmptr == vmx->nested.current_vmptr)
6929                 nested_release_vmcs12(vmx);
6930
6931         page = nested_get_page(vcpu, vmptr);
6932         if (page == NULL) {
6933                 /*
6934                  * For accurate processor emulation, VMCLEAR beyond available
6935                  * physical memory should do nothing at all. However, it is
6936                  * possible that a nested vmx bug, not a guest hypervisor bug,
6937                  * resulted in this case, so let's shut down before doing any
6938                  * more damage:
6939                  */
6940                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6941                 return 1;
6942         }
6943         vmcs12 = kmap(page);
6944         vmcs12->launch_state = 0;
6945         kunmap(page);
6946         nested_release_page(page);
6947
6948         nested_free_vmcs02(vmx, vmptr);
6949
6950         skip_emulated_instruction(vcpu);
6951         nested_vmx_succeed(vcpu);
6952         return 1;
6953 }
6954
6955 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6956
6957 /* Emulate the VMLAUNCH instruction */
6958 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6959 {
6960         return nested_vmx_run(vcpu, true);
6961 }
6962
6963 /* Emulate the VMRESUME instruction */
6964 static int handle_vmresume(struct kvm_vcpu *vcpu)
6965 {
6966
6967         return nested_vmx_run(vcpu, false);
6968 }
6969
6970 enum vmcs_field_type {
6971         VMCS_FIELD_TYPE_U16 = 0,
6972         VMCS_FIELD_TYPE_U64 = 1,
6973         VMCS_FIELD_TYPE_U32 = 2,
6974         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6975 };
6976
6977 static inline int vmcs_field_type(unsigned long field)
6978 {
6979         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6980                 return VMCS_FIELD_TYPE_U32;
6981         return (field >> 13) & 0x3 ;
6982 }
6983
6984 static inline int vmcs_field_readonly(unsigned long field)
6985 {
6986         return (((field >> 10) & 0x3) == 1);
6987 }
6988
6989 /*
6990  * Read a vmcs12 field. Since these can have varying lengths and we return
6991  * one type, we chose the biggest type (u64) and zero-extend the return value
6992  * to that size. Note that the caller, handle_vmread, might need to use only
6993  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6994  * 64-bit fields are to be returned).
6995  */
6996 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6997                                   unsigned long field, u64 *ret)
6998 {
6999         short offset = vmcs_field_to_offset(field);
7000         char *p;
7001
7002         if (offset < 0)
7003                 return offset;
7004
7005         p = ((char *)(get_vmcs12(vcpu))) + offset;
7006
7007         switch (vmcs_field_type(field)) {
7008         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7009                 *ret = *((natural_width *)p);
7010                 return 0;
7011         case VMCS_FIELD_TYPE_U16:
7012                 *ret = *((u16 *)p);
7013                 return 0;
7014         case VMCS_FIELD_TYPE_U32:
7015                 *ret = *((u32 *)p);
7016                 return 0;
7017         case VMCS_FIELD_TYPE_U64:
7018                 *ret = *((u64 *)p);
7019                 return 0;
7020         default:
7021                 WARN_ON(1);
7022                 return -ENOENT;
7023         }
7024 }
7025
7026
7027 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7028                                    unsigned long field, u64 field_value){
7029         short offset = vmcs_field_to_offset(field);
7030         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7031         if (offset < 0)
7032                 return offset;
7033
7034         switch (vmcs_field_type(field)) {
7035         case VMCS_FIELD_TYPE_U16:
7036                 *(u16 *)p = field_value;
7037                 return 0;
7038         case VMCS_FIELD_TYPE_U32:
7039                 *(u32 *)p = field_value;
7040                 return 0;
7041         case VMCS_FIELD_TYPE_U64:
7042                 *(u64 *)p = field_value;
7043                 return 0;
7044         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7045                 *(natural_width *)p = field_value;
7046                 return 0;
7047         default:
7048                 WARN_ON(1);
7049                 return -ENOENT;
7050         }
7051
7052 }
7053
7054 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7055 {
7056         int i;
7057         unsigned long field;
7058         u64 field_value;
7059         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7060         const unsigned long *fields = shadow_read_write_fields;
7061         const int num_fields = max_shadow_read_write_fields;
7062
7063         preempt_disable();
7064
7065         vmcs_load(shadow_vmcs);
7066
7067         for (i = 0; i < num_fields; i++) {
7068                 field = fields[i];
7069                 switch (vmcs_field_type(field)) {
7070                 case VMCS_FIELD_TYPE_U16:
7071                         field_value = vmcs_read16(field);
7072                         break;
7073                 case VMCS_FIELD_TYPE_U32:
7074                         field_value = vmcs_read32(field);
7075                         break;
7076                 case VMCS_FIELD_TYPE_U64:
7077                         field_value = vmcs_read64(field);
7078                         break;
7079                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7080                         field_value = vmcs_readl(field);
7081                         break;
7082                 default:
7083                         WARN_ON(1);
7084                         continue;
7085                 }
7086                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7087         }
7088
7089         vmcs_clear(shadow_vmcs);
7090         vmcs_load(vmx->loaded_vmcs->vmcs);
7091
7092         preempt_enable();
7093 }
7094
7095 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7096 {
7097         const unsigned long *fields[] = {
7098                 shadow_read_write_fields,
7099                 shadow_read_only_fields
7100         };
7101         const int max_fields[] = {
7102                 max_shadow_read_write_fields,
7103                 max_shadow_read_only_fields
7104         };
7105         int i, q;
7106         unsigned long field;
7107         u64 field_value = 0;
7108         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7109
7110         vmcs_load(shadow_vmcs);
7111
7112         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7113                 for (i = 0; i < max_fields[q]; i++) {
7114                         field = fields[q][i];
7115                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7116
7117                         switch (vmcs_field_type(field)) {
7118                         case VMCS_FIELD_TYPE_U16:
7119                                 vmcs_write16(field, (u16)field_value);
7120                                 break;
7121                         case VMCS_FIELD_TYPE_U32:
7122                                 vmcs_write32(field, (u32)field_value);
7123                                 break;
7124                         case VMCS_FIELD_TYPE_U64:
7125                                 vmcs_write64(field, (u64)field_value);
7126                                 break;
7127                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7128                                 vmcs_writel(field, (long)field_value);
7129                                 break;
7130                         default:
7131                                 WARN_ON(1);
7132                                 break;
7133                         }
7134                 }
7135         }
7136
7137         vmcs_clear(shadow_vmcs);
7138         vmcs_load(vmx->loaded_vmcs->vmcs);
7139 }
7140
7141 /*
7142  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7143  * used before) all generate the same failure when it is missing.
7144  */
7145 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7146 {
7147         struct vcpu_vmx *vmx = to_vmx(vcpu);
7148         if (vmx->nested.current_vmptr == -1ull) {
7149                 nested_vmx_failInvalid(vcpu);
7150                 skip_emulated_instruction(vcpu);
7151                 return 0;
7152         }
7153         return 1;
7154 }
7155
7156 static int handle_vmread(struct kvm_vcpu *vcpu)
7157 {
7158         unsigned long field;
7159         u64 field_value;
7160         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7161         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7162         gva_t gva = 0;
7163
7164         if (!nested_vmx_check_permission(vcpu) ||
7165             !nested_vmx_check_vmcs12(vcpu))
7166                 return 1;
7167
7168         /* Decode instruction info and find the field to read */
7169         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7170         /* Read the field, zero-extended to a u64 field_value */
7171         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7172                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7173                 skip_emulated_instruction(vcpu);
7174                 return 1;
7175         }
7176         /*
7177          * Now copy part of this value to register or memory, as requested.
7178          * Note that the number of bits actually copied is 32 or 64 depending
7179          * on the guest's mode (32 or 64 bit), not on the given field's length.
7180          */
7181         if (vmx_instruction_info & (1u << 10)) {
7182                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7183                         field_value);
7184         } else {
7185                 if (get_vmx_mem_address(vcpu, exit_qualification,
7186                                 vmx_instruction_info, true, &gva))
7187                         return 1;
7188                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7189                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7190                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7191         }
7192
7193         nested_vmx_succeed(vcpu);
7194         skip_emulated_instruction(vcpu);
7195         return 1;
7196 }
7197
7198
7199 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7200 {
7201         unsigned long field;
7202         gva_t gva;
7203         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7204         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7205         /* The value to write might be 32 or 64 bits, depending on L1's long
7206          * mode, and eventually we need to write that into a field of several
7207          * possible lengths. The code below first zero-extends the value to 64
7208          * bit (field_value), and then copies only the approriate number of
7209          * bits into the vmcs12 field.
7210          */
7211         u64 field_value = 0;
7212         struct x86_exception e;
7213
7214         if (!nested_vmx_check_permission(vcpu) ||
7215             !nested_vmx_check_vmcs12(vcpu))
7216                 return 1;
7217
7218         if (vmx_instruction_info & (1u << 10))
7219                 field_value = kvm_register_readl(vcpu,
7220                         (((vmx_instruction_info) >> 3) & 0xf));
7221         else {
7222                 if (get_vmx_mem_address(vcpu, exit_qualification,
7223                                 vmx_instruction_info, false, &gva))
7224                         return 1;
7225                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7226                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7227                         kvm_inject_page_fault(vcpu, &e);
7228                         return 1;
7229                 }
7230         }
7231
7232
7233         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7234         if (vmcs_field_readonly(field)) {
7235                 nested_vmx_failValid(vcpu,
7236                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7237                 skip_emulated_instruction(vcpu);
7238                 return 1;
7239         }
7240
7241         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7242                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7243                 skip_emulated_instruction(vcpu);
7244                 return 1;
7245         }
7246
7247         nested_vmx_succeed(vcpu);
7248         skip_emulated_instruction(vcpu);
7249         return 1;
7250 }
7251
7252 /* Emulate the VMPTRLD instruction */
7253 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7254 {
7255         struct vcpu_vmx *vmx = to_vmx(vcpu);
7256         gpa_t vmptr;
7257
7258         if (!nested_vmx_check_permission(vcpu))
7259                 return 1;
7260
7261         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7262                 return 1;
7263
7264         if (vmx->nested.current_vmptr != vmptr) {
7265                 struct vmcs12 *new_vmcs12;
7266                 struct page *page;
7267                 page = nested_get_page(vcpu, vmptr);
7268                 if (page == NULL) {
7269                         nested_vmx_failInvalid(vcpu);
7270                         skip_emulated_instruction(vcpu);
7271                         return 1;
7272                 }
7273                 new_vmcs12 = kmap(page);
7274                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7275                         kunmap(page);
7276                         nested_release_page_clean(page);
7277                         nested_vmx_failValid(vcpu,
7278                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7279                         skip_emulated_instruction(vcpu);
7280                         return 1;
7281                 }
7282
7283                 nested_release_vmcs12(vmx);
7284                 vmx->nested.current_vmptr = vmptr;
7285                 vmx->nested.current_vmcs12 = new_vmcs12;
7286                 vmx->nested.current_vmcs12_page = page;
7287                 if (enable_shadow_vmcs) {
7288                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7289                                       SECONDARY_EXEC_SHADOW_VMCS);
7290                         vmcs_write64(VMCS_LINK_POINTER,
7291                                      __pa(vmx->nested.current_shadow_vmcs));
7292                         vmx->nested.sync_shadow_vmcs = true;
7293                 }
7294         }
7295
7296         nested_vmx_succeed(vcpu);
7297         skip_emulated_instruction(vcpu);
7298         return 1;
7299 }
7300
7301 /* Emulate the VMPTRST instruction */
7302 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7303 {
7304         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7305         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7306         gva_t vmcs_gva;
7307         struct x86_exception e;
7308
7309         if (!nested_vmx_check_permission(vcpu))
7310                 return 1;
7311
7312         if (get_vmx_mem_address(vcpu, exit_qualification,
7313                         vmx_instruction_info, true, &vmcs_gva))
7314                 return 1;
7315         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7316         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7317                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7318                                  sizeof(u64), &e)) {
7319                 kvm_inject_page_fault(vcpu, &e);
7320                 return 1;
7321         }
7322         nested_vmx_succeed(vcpu);
7323         skip_emulated_instruction(vcpu);
7324         return 1;
7325 }
7326
7327 /* Emulate the INVEPT instruction */
7328 static int handle_invept(struct kvm_vcpu *vcpu)
7329 {
7330         struct vcpu_vmx *vmx = to_vmx(vcpu);
7331         u32 vmx_instruction_info, types;
7332         unsigned long type;
7333         gva_t gva;
7334         struct x86_exception e;
7335         struct {
7336                 u64 eptp, gpa;
7337         } operand;
7338
7339         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7340               SECONDARY_EXEC_ENABLE_EPT) ||
7341             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7342                 kvm_queue_exception(vcpu, UD_VECTOR);
7343                 return 1;
7344         }
7345
7346         if (!nested_vmx_check_permission(vcpu))
7347                 return 1;
7348
7349         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7350                 kvm_queue_exception(vcpu, UD_VECTOR);
7351                 return 1;
7352         }
7353
7354         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7355         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7356
7357         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7358
7359         if (!(types & (1UL << type))) {
7360                 nested_vmx_failValid(vcpu,
7361                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7362                 skip_emulated_instruction(vcpu);
7363                 return 1;
7364         }
7365
7366         /* According to the Intel VMX instruction reference, the memory
7367          * operand is read even if it isn't needed (e.g., for type==global)
7368          */
7369         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7370                         vmx_instruction_info, false, &gva))
7371                 return 1;
7372         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7373                                 sizeof(operand), &e)) {
7374                 kvm_inject_page_fault(vcpu, &e);
7375                 return 1;
7376         }
7377
7378         switch (type) {
7379         case VMX_EPT_EXTENT_GLOBAL:
7380                 kvm_mmu_sync_roots(vcpu);
7381                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7382                 nested_vmx_succeed(vcpu);
7383                 break;
7384         default:
7385                 /* Trap single context invalidation invept calls */
7386                 BUG_ON(1);
7387                 break;
7388         }
7389
7390         skip_emulated_instruction(vcpu);
7391         return 1;
7392 }
7393
7394 static int handle_invvpid(struct kvm_vcpu *vcpu)
7395 {
7396         struct vcpu_vmx *vmx = to_vmx(vcpu);
7397         u32 vmx_instruction_info;
7398         unsigned long type, types;
7399         gva_t gva;
7400         struct x86_exception e;
7401         int vpid;
7402
7403         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7404               SECONDARY_EXEC_ENABLE_VPID) ||
7405                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7406                 kvm_queue_exception(vcpu, UD_VECTOR);
7407                 return 1;
7408         }
7409
7410         if (!nested_vmx_check_permission(vcpu))
7411                 return 1;
7412
7413         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7414         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7415
7416         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7417
7418         if (!(types & (1UL << type))) {
7419                 nested_vmx_failValid(vcpu,
7420                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7421                 skip_emulated_instruction(vcpu);
7422                 return 1;
7423         }
7424
7425         /* according to the intel vmx instruction reference, the memory
7426          * operand is read even if it isn't needed (e.g., for type==global)
7427          */
7428         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7429                         vmx_instruction_info, false, &gva))
7430                 return 1;
7431         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7432                                 sizeof(u32), &e)) {
7433                 kvm_inject_page_fault(vcpu, &e);
7434                 return 1;
7435         }
7436
7437         switch (type) {
7438         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7439                 /*
7440                  * Old versions of KVM use the single-context version so we
7441                  * have to support it; just treat it the same as all-context.
7442                  */
7443         case VMX_VPID_EXTENT_ALL_CONTEXT:
7444                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7445                 nested_vmx_succeed(vcpu);
7446                 break;
7447         default:
7448                 /* Trap individual address invalidation invvpid calls */
7449                 BUG_ON(1);
7450                 break;
7451         }
7452
7453         skip_emulated_instruction(vcpu);
7454         return 1;
7455 }
7456
7457 static int handle_pml_full(struct kvm_vcpu *vcpu)
7458 {
7459         unsigned long exit_qualification;
7460
7461         trace_kvm_pml_full(vcpu->vcpu_id);
7462
7463         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7464
7465         /*
7466          * PML buffer FULL happened while executing iret from NMI,
7467          * "blocked by NMI" bit has to be set before next VM entry.
7468          */
7469         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7470                         cpu_has_virtual_nmis() &&
7471                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7472                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7473                                 GUEST_INTR_STATE_NMI);
7474
7475         /*
7476          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7477          * here.., and there's no userspace involvement needed for PML.
7478          */
7479         return 1;
7480 }
7481
7482 static int handle_pcommit(struct kvm_vcpu *vcpu)
7483 {
7484         /* we never catch pcommit instruct for L1 guest. */
7485         WARN_ON(1);
7486         return 1;
7487 }
7488
7489 /*
7490  * The exit handlers return 1 if the exit was handled fully and guest execution
7491  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7492  * to be done to userspace and return 0.
7493  */
7494 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7495         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7496         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7497         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7498         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7499         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7500         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7501         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7502         [EXIT_REASON_CPUID]                   = handle_cpuid,
7503         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7504         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7505         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7506         [EXIT_REASON_HLT]                     = handle_halt,
7507         [EXIT_REASON_INVD]                    = handle_invd,
7508         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7509         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7510         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7511         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7512         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7513         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7514         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7515         [EXIT_REASON_VMREAD]                  = handle_vmread,
7516         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7517         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7518         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7519         [EXIT_REASON_VMON]                    = handle_vmon,
7520         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7521         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7522         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7523         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7524         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7525         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7526         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7527         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7528         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7529         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7530         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7531         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7532         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7533         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7534         [EXIT_REASON_INVEPT]                  = handle_invept,
7535         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7536         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7537         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7538         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7539         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7540 };
7541
7542 static const int kvm_vmx_max_exit_handlers =
7543         ARRAY_SIZE(kvm_vmx_exit_handlers);
7544
7545 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7546                                        struct vmcs12 *vmcs12)
7547 {
7548         unsigned long exit_qualification;
7549         gpa_t bitmap, last_bitmap;
7550         unsigned int port;
7551         int size;
7552         u8 b;
7553
7554         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7555                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7556
7557         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7558
7559         port = exit_qualification >> 16;
7560         size = (exit_qualification & 7) + 1;
7561
7562         last_bitmap = (gpa_t)-1;
7563         b = -1;
7564
7565         while (size > 0) {
7566                 if (port < 0x8000)
7567                         bitmap = vmcs12->io_bitmap_a;
7568                 else if (port < 0x10000)
7569                         bitmap = vmcs12->io_bitmap_b;
7570                 else
7571                         return true;
7572                 bitmap += (port & 0x7fff) / 8;
7573
7574                 if (last_bitmap != bitmap)
7575                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7576                                 return true;
7577                 if (b & (1 << (port & 7)))
7578                         return true;
7579
7580                 port++;
7581                 size--;
7582                 last_bitmap = bitmap;
7583         }
7584
7585         return false;
7586 }
7587
7588 /*
7589  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7590  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7591  * disinterest in the current event (read or write a specific MSR) by using an
7592  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7593  */
7594 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7595         struct vmcs12 *vmcs12, u32 exit_reason)
7596 {
7597         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7598         gpa_t bitmap;
7599
7600         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7601                 return true;
7602
7603         /*
7604          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7605          * for the four combinations of read/write and low/high MSR numbers.
7606          * First we need to figure out which of the four to use:
7607          */
7608         bitmap = vmcs12->msr_bitmap;
7609         if (exit_reason == EXIT_REASON_MSR_WRITE)
7610                 bitmap += 2048;
7611         if (msr_index >= 0xc0000000) {
7612                 msr_index -= 0xc0000000;
7613                 bitmap += 1024;
7614         }
7615
7616         /* Then read the msr_index'th bit from this bitmap: */
7617         if (msr_index < 1024*8) {
7618                 unsigned char b;
7619                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7620                         return true;
7621                 return 1 & (b >> (msr_index & 7));
7622         } else
7623                 return true; /* let L1 handle the wrong parameter */
7624 }
7625
7626 /*
7627  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7628  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7629  * intercept (via guest_host_mask etc.) the current event.
7630  */
7631 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7632         struct vmcs12 *vmcs12)
7633 {
7634         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7635         int cr = exit_qualification & 15;
7636         int reg = (exit_qualification >> 8) & 15;
7637         unsigned long val = kvm_register_readl(vcpu, reg);
7638
7639         switch ((exit_qualification >> 4) & 3) {
7640         case 0: /* mov to cr */
7641                 switch (cr) {
7642                 case 0:
7643                         if (vmcs12->cr0_guest_host_mask &
7644                             (val ^ vmcs12->cr0_read_shadow))
7645                                 return true;
7646                         break;
7647                 case 3:
7648                         if ((vmcs12->cr3_target_count >= 1 &&
7649                                         vmcs12->cr3_target_value0 == val) ||
7650                                 (vmcs12->cr3_target_count >= 2 &&
7651                                         vmcs12->cr3_target_value1 == val) ||
7652                                 (vmcs12->cr3_target_count >= 3 &&
7653                                         vmcs12->cr3_target_value2 == val) ||
7654                                 (vmcs12->cr3_target_count >= 4 &&
7655                                         vmcs12->cr3_target_value3 == val))
7656                                 return false;
7657                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7658                                 return true;
7659                         break;
7660                 case 4:
7661                         if (vmcs12->cr4_guest_host_mask &
7662                             (vmcs12->cr4_read_shadow ^ val))
7663                                 return true;
7664                         break;
7665                 case 8:
7666                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7667                                 return true;
7668                         break;
7669                 }
7670                 break;
7671         case 2: /* clts */
7672                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7673                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7674                         return true;
7675                 break;
7676         case 1: /* mov from cr */
7677                 switch (cr) {
7678                 case 3:
7679                         if (vmcs12->cpu_based_vm_exec_control &
7680                             CPU_BASED_CR3_STORE_EXITING)
7681                                 return true;
7682                         break;
7683                 case 8:
7684                         if (vmcs12->cpu_based_vm_exec_control &
7685                             CPU_BASED_CR8_STORE_EXITING)
7686                                 return true;
7687                         break;
7688                 }
7689                 break;
7690         case 3: /* lmsw */
7691                 /*
7692                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7693                  * cr0. Other attempted changes are ignored, with no exit.
7694                  */
7695                 if (vmcs12->cr0_guest_host_mask & 0xe &
7696                     (val ^ vmcs12->cr0_read_shadow))
7697                         return true;
7698                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7699                     !(vmcs12->cr0_read_shadow & 0x1) &&
7700                     (val & 0x1))
7701                         return true;
7702                 break;
7703         }
7704         return false;
7705 }
7706
7707 /*
7708  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7709  * should handle it ourselves in L0 (and then continue L2). Only call this
7710  * when in is_guest_mode (L2).
7711  */
7712 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7713 {
7714         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7715         struct vcpu_vmx *vmx = to_vmx(vcpu);
7716         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7717         u32 exit_reason = vmx->exit_reason;
7718
7719         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7720                                 vmcs_readl(EXIT_QUALIFICATION),
7721                                 vmx->idt_vectoring_info,
7722                                 intr_info,
7723                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7724                                 KVM_ISA_VMX);
7725
7726         if (vmx->nested.nested_run_pending)
7727                 return false;
7728
7729         if (unlikely(vmx->fail)) {
7730                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7731                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7732                 return true;
7733         }
7734
7735         switch (exit_reason) {
7736         case EXIT_REASON_EXCEPTION_NMI:
7737                 if (is_nmi(intr_info))
7738                         return false;
7739                 else if (is_page_fault(intr_info))
7740                         return enable_ept;
7741                 else if (is_no_device(intr_info) &&
7742                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7743                         return false;
7744                 return vmcs12->exception_bitmap &
7745                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7746         case EXIT_REASON_EXTERNAL_INTERRUPT:
7747                 return false;
7748         case EXIT_REASON_TRIPLE_FAULT:
7749                 return true;
7750         case EXIT_REASON_PENDING_INTERRUPT:
7751                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7752         case EXIT_REASON_NMI_WINDOW:
7753                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7754         case EXIT_REASON_TASK_SWITCH:
7755                 return true;
7756         case EXIT_REASON_CPUID:
7757                 return true;
7758         case EXIT_REASON_HLT:
7759                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7760         case EXIT_REASON_INVD:
7761                 return true;
7762         case EXIT_REASON_INVLPG:
7763                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7764         case EXIT_REASON_RDPMC:
7765                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7766         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7767                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7768         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7769         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7770         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7771         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7772         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7773         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7774                 /*
7775                  * VMX instructions trap unconditionally. This allows L1 to
7776                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7777                  */
7778                 return true;
7779         case EXIT_REASON_CR_ACCESS:
7780                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7781         case EXIT_REASON_DR_ACCESS:
7782                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7783         case EXIT_REASON_IO_INSTRUCTION:
7784                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7785         case EXIT_REASON_MSR_READ:
7786         case EXIT_REASON_MSR_WRITE:
7787                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7788         case EXIT_REASON_INVALID_STATE:
7789                 return true;
7790         case EXIT_REASON_MWAIT_INSTRUCTION:
7791                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7792         case EXIT_REASON_MONITOR_TRAP_FLAG:
7793                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7794         case EXIT_REASON_MONITOR_INSTRUCTION:
7795                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7796         case EXIT_REASON_PAUSE_INSTRUCTION:
7797                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7798                         nested_cpu_has2(vmcs12,
7799                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7800         case EXIT_REASON_MCE_DURING_VMENTRY:
7801                 return false;
7802         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7803                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7804         case EXIT_REASON_APIC_ACCESS:
7805                 return nested_cpu_has2(vmcs12,
7806                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7807         case EXIT_REASON_APIC_WRITE:
7808         case EXIT_REASON_EOI_INDUCED:
7809                 /* apic_write and eoi_induced should exit unconditionally. */
7810                 return true;
7811         case EXIT_REASON_EPT_VIOLATION:
7812                 /*
7813                  * L0 always deals with the EPT violation. If nested EPT is
7814                  * used, and the nested mmu code discovers that the address is
7815                  * missing in the guest EPT table (EPT12), the EPT violation
7816                  * will be injected with nested_ept_inject_page_fault()
7817                  */
7818                 return false;
7819         case EXIT_REASON_EPT_MISCONFIG:
7820                 /*
7821                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7822                  * table (shadow on EPT) or a merged EPT table that L0 built
7823                  * (EPT on EPT). So any problems with the structure of the
7824                  * table is L0's fault.
7825                  */
7826                 return false;
7827         case EXIT_REASON_WBINVD:
7828                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7829         case EXIT_REASON_XSETBV:
7830                 return true;
7831         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7832                 /*
7833                  * This should never happen, since it is not possible to
7834                  * set XSS to a non-zero value---neither in L1 nor in L2.
7835                  * If if it were, XSS would have to be checked against
7836                  * the XSS exit bitmap in vmcs12.
7837                  */
7838                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7839         case EXIT_REASON_PCOMMIT:
7840                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7841         default:
7842                 return true;
7843         }
7844 }
7845
7846 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7847 {
7848         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7849         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7850 }
7851
7852 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7853 {
7854         if (vmx->pml_pg) {
7855                 __free_page(vmx->pml_pg);
7856                 vmx->pml_pg = NULL;
7857         }
7858 }
7859
7860 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7861 {
7862         struct vcpu_vmx *vmx = to_vmx(vcpu);
7863         u64 *pml_buf;
7864         u16 pml_idx;
7865
7866         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7867
7868         /* Do nothing if PML buffer is empty */
7869         if (pml_idx == (PML_ENTITY_NUM - 1))
7870                 return;
7871
7872         /* PML index always points to next available PML buffer entity */
7873         if (pml_idx >= PML_ENTITY_NUM)
7874                 pml_idx = 0;
7875         else
7876                 pml_idx++;
7877
7878         pml_buf = page_address(vmx->pml_pg);
7879         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7880                 u64 gpa;
7881
7882                 gpa = pml_buf[pml_idx];
7883                 WARN_ON(gpa & (PAGE_SIZE - 1));
7884                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7885         }
7886
7887         /* reset PML index */
7888         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7889 }
7890
7891 /*
7892  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7893  * Called before reporting dirty_bitmap to userspace.
7894  */
7895 static void kvm_flush_pml_buffers(struct kvm *kvm)
7896 {
7897         int i;
7898         struct kvm_vcpu *vcpu;
7899         /*
7900          * We only need to kick vcpu out of guest mode here, as PML buffer
7901          * is flushed at beginning of all VMEXITs, and it's obvious that only
7902          * vcpus running in guest are possible to have unflushed GPAs in PML
7903          * buffer.
7904          */
7905         kvm_for_each_vcpu(i, vcpu, kvm)
7906                 kvm_vcpu_kick(vcpu);
7907 }
7908
7909 static void vmx_dump_sel(char *name, uint32_t sel)
7910 {
7911         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7912                name, vmcs_read16(sel),
7913                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7914                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7915                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7916 }
7917
7918 static void vmx_dump_dtsel(char *name, uint32_t limit)
7919 {
7920         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7921                name, vmcs_read32(limit),
7922                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7923 }
7924
7925 static void dump_vmcs(void)
7926 {
7927         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7928         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7929         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7930         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7931         u32 secondary_exec_control = 0;
7932         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7933         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7934         int i, n;
7935
7936         if (cpu_has_secondary_exec_ctrls())
7937                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7938
7939         pr_err("*** Guest State ***\n");
7940         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7941                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7942                vmcs_readl(CR0_GUEST_HOST_MASK));
7943         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7944                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7945         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7946         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7947             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7948         {
7949                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7950                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7951                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7952                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7953         }
7954         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7955                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7956         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7957                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7958         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7959                vmcs_readl(GUEST_SYSENTER_ESP),
7960                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7961         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7962         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7963         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7964         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7965         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7966         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7967         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7968         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7969         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7970         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7971         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7972             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7973                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7974                        efer, vmcs_readl(GUEST_IA32_PAT));
7975         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7976                vmcs_readl(GUEST_IA32_DEBUGCTL),
7977                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7978         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7979                 pr_err("PerfGlobCtl = 0x%016lx\n",
7980                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7981         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7982                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7983         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7984                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7985                vmcs_read32(GUEST_ACTIVITY_STATE));
7986         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7987                 pr_err("InterruptStatus = %04x\n",
7988                        vmcs_read16(GUEST_INTR_STATUS));
7989
7990         pr_err("*** Host State ***\n");
7991         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7992                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7993         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7994                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7995                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7996                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7997                vmcs_read16(HOST_TR_SELECTOR));
7998         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7999                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8000                vmcs_readl(HOST_TR_BASE));
8001         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8002                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8003         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8004                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8005                vmcs_readl(HOST_CR4));
8006         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8007                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8008                vmcs_read32(HOST_IA32_SYSENTER_CS),
8009                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8010         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8011                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
8012                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
8013         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8014                 pr_err("PerfGlobCtl = 0x%016lx\n",
8015                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
8016
8017         pr_err("*** Control State ***\n");
8018         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8019                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8020         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8021         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8022                vmcs_read32(EXCEPTION_BITMAP),
8023                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8024                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8025         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8026                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8027                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8028                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8029         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8030                vmcs_read32(VM_EXIT_INTR_INFO),
8031                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8032                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8033         pr_err("        reason=%08x qualification=%016lx\n",
8034                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8035         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8036                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8037                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8038         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8039         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8040                 pr_err("TSC Multiplier = 0x%016lx\n",
8041                        vmcs_readl(TSC_MULTIPLIER));
8042         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8043                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8044         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8045                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8046         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8047                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8048         n = vmcs_read32(CR3_TARGET_COUNT);
8049         for (i = 0; i + 1 < n; i += 4)
8050                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8051                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8052                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8053         if (i < n)
8054                 pr_err("CR3 target%u=%016lx\n",
8055                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8056         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8057                 pr_err("PLE Gap=%08x Window=%08x\n",
8058                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8059         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8060                 pr_err("Virtual processor ID = 0x%04x\n",
8061                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8062 }
8063
8064 /*
8065  * The guest has exited.  See if we can fix it or if we need userspace
8066  * assistance.
8067  */
8068 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8069 {
8070         struct vcpu_vmx *vmx = to_vmx(vcpu);
8071         u32 exit_reason = vmx->exit_reason;
8072         u32 vectoring_info = vmx->idt_vectoring_info;
8073
8074         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8075
8076         /*
8077          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8078          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8079          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8080          * mode as if vcpus is in root mode, the PML buffer must has been
8081          * flushed already.
8082          */
8083         if (enable_pml)
8084                 vmx_flush_pml_buffer(vcpu);
8085
8086         /* If guest state is invalid, start emulating */
8087         if (vmx->emulation_required)
8088                 return handle_invalid_guest_state(vcpu);
8089
8090         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8091                 nested_vmx_vmexit(vcpu, exit_reason,
8092                                   vmcs_read32(VM_EXIT_INTR_INFO),
8093                                   vmcs_readl(EXIT_QUALIFICATION));
8094                 return 1;
8095         }
8096
8097         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8098                 dump_vmcs();
8099                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8100                 vcpu->run->fail_entry.hardware_entry_failure_reason
8101                         = exit_reason;
8102                 return 0;
8103         }
8104
8105         if (unlikely(vmx->fail)) {
8106                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8107                 vcpu->run->fail_entry.hardware_entry_failure_reason
8108                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8109                 return 0;
8110         }
8111
8112         /*
8113          * Note:
8114          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8115          * delivery event since it indicates guest is accessing MMIO.
8116          * The vm-exit can be triggered again after return to guest that
8117          * will cause infinite loop.
8118          */
8119         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8120                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8121                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8122                         exit_reason != EXIT_REASON_PML_FULL &&
8123                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8124                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8125                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8126                 vcpu->run->internal.ndata = 2;
8127                 vcpu->run->internal.data[0] = vectoring_info;
8128                 vcpu->run->internal.data[1] = exit_reason;
8129                 return 0;
8130         }
8131
8132         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8133             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8134                                         get_vmcs12(vcpu))))) {
8135                 if (vmx_interrupt_allowed(vcpu)) {
8136                         vmx->soft_vnmi_blocked = 0;
8137                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8138                            vcpu->arch.nmi_pending) {
8139                         /*
8140                          * This CPU don't support us in finding the end of an
8141                          * NMI-blocked window if the guest runs with IRQs
8142                          * disabled. So we pull the trigger after 1 s of
8143                          * futile waiting, but inform the user about this.
8144                          */
8145                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8146                                "state on VCPU %d after 1 s timeout\n",
8147                                __func__, vcpu->vcpu_id);
8148                         vmx->soft_vnmi_blocked = 0;
8149                 }
8150         }
8151
8152         if (exit_reason < kvm_vmx_max_exit_handlers
8153             && kvm_vmx_exit_handlers[exit_reason])
8154                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8155         else {
8156                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8157                 kvm_queue_exception(vcpu, UD_VECTOR);
8158                 return 1;
8159         }
8160 }
8161
8162 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8163 {
8164         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8165
8166         if (is_guest_mode(vcpu) &&
8167                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8168                 return;
8169
8170         if (irr == -1 || tpr < irr) {
8171                 vmcs_write32(TPR_THRESHOLD, 0);
8172                 return;
8173         }
8174
8175         vmcs_write32(TPR_THRESHOLD, irr);
8176 }
8177
8178 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8179 {
8180         u32 sec_exec_control;
8181
8182         /* Postpone execution until vmcs01 is the current VMCS. */
8183         if (is_guest_mode(vcpu)) {
8184                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8185                 return;
8186         }
8187
8188         /*
8189          * There is not point to enable virtualize x2apic without enable
8190          * apicv
8191          */
8192         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8193                                 !vmx_cpu_uses_apicv(vcpu))
8194                 return;
8195
8196         if (!cpu_need_tpr_shadow(vcpu))
8197                 return;
8198
8199         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8200
8201         if (set) {
8202                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8203                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8204         } else {
8205                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8206                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8207         }
8208         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8209
8210         vmx_set_msr_bitmap(vcpu);
8211 }
8212
8213 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8214 {
8215         struct vcpu_vmx *vmx = to_vmx(vcpu);
8216
8217         /*
8218          * Currently we do not handle the nested case where L2 has an
8219          * APIC access page of its own; that page is still pinned.
8220          * Hence, we skip the case where the VCPU is in guest mode _and_
8221          * L1 prepared an APIC access page for L2.
8222          *
8223          * For the case where L1 and L2 share the same APIC access page
8224          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8225          * in the vmcs12), this function will only update either the vmcs01
8226          * or the vmcs02.  If the former, the vmcs02 will be updated by
8227          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8228          * the next L2->L1 exit.
8229          */
8230         if (!is_guest_mode(vcpu) ||
8231             !nested_cpu_has2(vmx->nested.current_vmcs12,
8232                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8233                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8234 }
8235
8236 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8237 {
8238         u16 status;
8239         u8 old;
8240
8241         if (isr == -1)
8242                 isr = 0;
8243
8244         status = vmcs_read16(GUEST_INTR_STATUS);
8245         old = status >> 8;
8246         if (isr != old) {
8247                 status &= 0xff;
8248                 status |= isr << 8;
8249                 vmcs_write16(GUEST_INTR_STATUS, status);
8250         }
8251 }
8252
8253 static void vmx_set_rvi(int vector)
8254 {
8255         u16 status;
8256         u8 old;
8257
8258         if (vector == -1)
8259                 vector = 0;
8260
8261         status = vmcs_read16(GUEST_INTR_STATUS);
8262         old = (u8)status & 0xff;
8263         if ((u8)vector != old) {
8264                 status &= ~0xff;
8265                 status |= (u8)vector;
8266                 vmcs_write16(GUEST_INTR_STATUS, status);
8267         }
8268 }
8269
8270 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8271 {
8272         if (!is_guest_mode(vcpu)) {
8273                 vmx_set_rvi(max_irr);
8274                 return;
8275         }
8276
8277         if (max_irr == -1)
8278                 return;
8279
8280         /*
8281          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8282          * handles it.
8283          */
8284         if (nested_exit_on_intr(vcpu))
8285                 return;
8286
8287         /*
8288          * Else, fall back to pre-APICv interrupt injection since L2
8289          * is run without virtual interrupt delivery.
8290          */
8291         if (!kvm_event_needs_reinjection(vcpu) &&
8292             vmx_interrupt_allowed(vcpu)) {
8293                 kvm_queue_interrupt(vcpu, max_irr, false);
8294                 vmx_inject_irq(vcpu);
8295         }
8296 }
8297
8298 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8299 {
8300         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8301         if (!vmx_cpu_uses_apicv(vcpu))
8302                 return;
8303
8304         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8305         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8306         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8307         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8308 }
8309
8310 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8311 {
8312         u32 exit_intr_info;
8313
8314         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8315               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8316                 return;
8317
8318         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8319         exit_intr_info = vmx->exit_intr_info;
8320
8321         /* Handle machine checks before interrupts are enabled */
8322         if (is_machine_check(exit_intr_info))
8323                 kvm_machine_check();
8324
8325         /* We need to handle NMIs before interrupts are enabled */
8326         if (is_nmi(exit_intr_info)) {
8327                 kvm_before_handle_nmi(&vmx->vcpu);
8328                 asm("int $2");
8329                 kvm_after_handle_nmi(&vmx->vcpu);
8330         }
8331 }
8332
8333 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8334 {
8335         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8336
8337         /*
8338          * If external interrupt exists, IF bit is set in rflags/eflags on the
8339          * interrupt stack frame, and interrupt will be enabled on a return
8340          * from interrupt handler.
8341          */
8342         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8343                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8344                 unsigned int vector;
8345                 unsigned long entry;
8346                 gate_desc *desc;
8347                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8348 #ifdef CONFIG_X86_64
8349                 unsigned long tmp;
8350 #endif
8351
8352                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8353                 desc = (gate_desc *)vmx->host_idt_base + vector;
8354                 entry = gate_offset(*desc);
8355                 asm volatile(
8356 #ifdef CONFIG_X86_64
8357                         "mov %%" _ASM_SP ", %[sp]\n\t"
8358                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8359                         "push $%c[ss]\n\t"
8360                         "push %[sp]\n\t"
8361 #endif
8362                         "pushf\n\t"
8363                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8364                         __ASM_SIZE(push) " $%c[cs]\n\t"
8365                         "call *%[entry]\n\t"
8366                         :
8367 #ifdef CONFIG_X86_64
8368                         [sp]"=&r"(tmp)
8369 #endif
8370                         :
8371                         [entry]"r"(entry),
8372                         [ss]"i"(__KERNEL_DS),
8373                         [cs]"i"(__KERNEL_CS)
8374                         );
8375         } else
8376                 local_irq_enable();
8377 }
8378
8379 static bool vmx_has_high_real_mode_segbase(void)
8380 {
8381         return enable_unrestricted_guest || emulate_invalid_guest_state;
8382 }
8383
8384 static bool vmx_mpx_supported(void)
8385 {
8386         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8387                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8388 }
8389
8390 static bool vmx_xsaves_supported(void)
8391 {
8392         return vmcs_config.cpu_based_2nd_exec_ctrl &
8393                 SECONDARY_EXEC_XSAVES;
8394 }
8395
8396 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8397 {
8398         u32 exit_intr_info;
8399         bool unblock_nmi;
8400         u8 vector;
8401         bool idtv_info_valid;
8402
8403         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8404
8405         if (cpu_has_virtual_nmis()) {
8406                 if (vmx->nmi_known_unmasked)
8407                         return;
8408                 /*
8409                  * Can't use vmx->exit_intr_info since we're not sure what
8410                  * the exit reason is.
8411                  */
8412                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8413                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8414                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8415                 /*
8416                  * SDM 3: 27.7.1.2 (September 2008)
8417                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8418                  * a guest IRET fault.
8419                  * SDM 3: 23.2.2 (September 2008)
8420                  * Bit 12 is undefined in any of the following cases:
8421                  *  If the VM exit sets the valid bit in the IDT-vectoring
8422                  *   information field.
8423                  *  If the VM exit is due to a double fault.
8424                  */
8425                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8426                     vector != DF_VECTOR && !idtv_info_valid)
8427                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8428                                       GUEST_INTR_STATE_NMI);
8429                 else
8430                         vmx->nmi_known_unmasked =
8431                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8432                                   & GUEST_INTR_STATE_NMI);
8433         } else if (unlikely(vmx->soft_vnmi_blocked))
8434                 vmx->vnmi_blocked_time +=
8435                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8436 }
8437
8438 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8439                                       u32 idt_vectoring_info,
8440                                       int instr_len_field,
8441                                       int error_code_field)
8442 {
8443         u8 vector;
8444         int type;
8445         bool idtv_info_valid;
8446
8447         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8448
8449         vcpu->arch.nmi_injected = false;
8450         kvm_clear_exception_queue(vcpu);
8451         kvm_clear_interrupt_queue(vcpu);
8452
8453         if (!idtv_info_valid)
8454                 return;
8455
8456         kvm_make_request(KVM_REQ_EVENT, vcpu);
8457
8458         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8459         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8460
8461         switch (type) {
8462         case INTR_TYPE_NMI_INTR:
8463                 vcpu->arch.nmi_injected = true;
8464                 /*
8465                  * SDM 3: 27.7.1.2 (September 2008)
8466                  * Clear bit "block by NMI" before VM entry if a NMI
8467                  * delivery faulted.
8468                  */
8469                 vmx_set_nmi_mask(vcpu, false);
8470                 break;
8471         case INTR_TYPE_SOFT_EXCEPTION:
8472                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8473                 /* fall through */
8474         case INTR_TYPE_HARD_EXCEPTION:
8475                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8476                         u32 err = vmcs_read32(error_code_field);
8477                         kvm_requeue_exception_e(vcpu, vector, err);
8478                 } else
8479                         kvm_requeue_exception(vcpu, vector);
8480                 break;
8481         case INTR_TYPE_SOFT_INTR:
8482                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8483                 /* fall through */
8484         case INTR_TYPE_EXT_INTR:
8485                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8486                 break;
8487         default:
8488                 break;
8489         }
8490 }
8491
8492 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8493 {
8494         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8495                                   VM_EXIT_INSTRUCTION_LEN,
8496                                   IDT_VECTORING_ERROR_CODE);
8497 }
8498
8499 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8500 {
8501         __vmx_complete_interrupts(vcpu,
8502                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8503                                   VM_ENTRY_INSTRUCTION_LEN,
8504                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8505
8506         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8507 }
8508
8509 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8510 {
8511         int i, nr_msrs;
8512         struct perf_guest_switch_msr *msrs;
8513
8514         msrs = perf_guest_get_msrs(&nr_msrs);
8515
8516         if (!msrs)
8517                 return;
8518
8519         for (i = 0; i < nr_msrs; i++)
8520                 if (msrs[i].host == msrs[i].guest)
8521                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8522                 else
8523                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8524                                         msrs[i].host);
8525 }
8526
8527 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8528 {
8529         struct vcpu_vmx *vmx = to_vmx(vcpu);
8530         unsigned long debugctlmsr, cr4;
8531
8532         /* Record the guest's net vcpu time for enforced NMI injections. */
8533         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8534                 vmx->entry_time = ktime_get();
8535
8536         /* Don't enter VMX if guest state is invalid, let the exit handler
8537            start emulation until we arrive back to a valid state */
8538         if (vmx->emulation_required)
8539                 return;
8540
8541         if (vmx->ple_window_dirty) {
8542                 vmx->ple_window_dirty = false;
8543                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8544         }
8545
8546         if (vmx->nested.sync_shadow_vmcs) {
8547                 copy_vmcs12_to_shadow(vmx);
8548                 vmx->nested.sync_shadow_vmcs = false;
8549         }
8550
8551         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8552                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8553         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8554                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8555
8556         cr4 = cr4_read_shadow();
8557         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8558                 vmcs_writel(HOST_CR4, cr4);
8559                 vmx->host_state.vmcs_host_cr4 = cr4;
8560         }
8561
8562         /* When single-stepping over STI and MOV SS, we must clear the
8563          * corresponding interruptibility bits in the guest state. Otherwise
8564          * vmentry fails as it then expects bit 14 (BS) in pending debug
8565          * exceptions being set, but that's not correct for the guest debugging
8566          * case. */
8567         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8568                 vmx_set_interrupt_shadow(vcpu, 0);
8569
8570         atomic_switch_perf_msrs(vmx);
8571         debugctlmsr = get_debugctlmsr();
8572
8573         vmx->__launched = vmx->loaded_vmcs->launched;
8574         asm(
8575                 /* Store host registers */
8576                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8577                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8578                 "push %%" _ASM_CX " \n\t"
8579                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8580                 "je 1f \n\t"
8581                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8582                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8583                 "1: \n\t"
8584                 /* Reload cr2 if changed */
8585                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8586                 "mov %%cr2, %%" _ASM_DX " \n\t"
8587                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8588                 "je 2f \n\t"
8589                 "mov %%" _ASM_AX", %%cr2 \n\t"
8590                 "2: \n\t"
8591                 /* Check if vmlaunch of vmresume is needed */
8592                 "cmpl $0, %c[launched](%0) \n\t"
8593                 /* Load guest registers.  Don't clobber flags. */
8594                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8595                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8596                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8597                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8598                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8599                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8600 #ifdef CONFIG_X86_64
8601                 "mov %c[r8](%0),  %%r8  \n\t"
8602                 "mov %c[r9](%0),  %%r9  \n\t"
8603                 "mov %c[r10](%0), %%r10 \n\t"
8604                 "mov %c[r11](%0), %%r11 \n\t"
8605                 "mov %c[r12](%0), %%r12 \n\t"
8606                 "mov %c[r13](%0), %%r13 \n\t"
8607                 "mov %c[r14](%0), %%r14 \n\t"
8608                 "mov %c[r15](%0), %%r15 \n\t"
8609 #endif
8610                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8611
8612                 /* Enter guest mode */
8613                 "jne 1f \n\t"
8614                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8615                 "jmp 2f \n\t"
8616                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8617                 "2: "
8618                 /* Save guest registers, load host registers, keep flags */
8619                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8620                 "pop %0 \n\t"
8621                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8622                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8623                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8624                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8625                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8626                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8627                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8628 #ifdef CONFIG_X86_64
8629                 "mov %%r8,  %c[r8](%0) \n\t"
8630                 "mov %%r9,  %c[r9](%0) \n\t"
8631                 "mov %%r10, %c[r10](%0) \n\t"
8632                 "mov %%r11, %c[r11](%0) \n\t"
8633                 "mov %%r12, %c[r12](%0) \n\t"
8634                 "mov %%r13, %c[r13](%0) \n\t"
8635                 "mov %%r14, %c[r14](%0) \n\t"
8636                 "mov %%r15, %c[r15](%0) \n\t"
8637 #endif
8638                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8639                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8640
8641                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8642                 "setbe %c[fail](%0) \n\t"
8643                 ".pushsection .rodata \n\t"
8644                 ".global vmx_return \n\t"
8645                 "vmx_return: " _ASM_PTR " 2b \n\t"
8646                 ".popsection"
8647               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8648                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8649                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8650                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8651                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8652                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8653                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8654                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8655                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8656                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8657                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8658 #ifdef CONFIG_X86_64
8659                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8660                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8661                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8662                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8663                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8664                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8665                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8666                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8667 #endif
8668                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8669                 [wordsize]"i"(sizeof(ulong))
8670               : "cc", "memory"
8671 #ifdef CONFIG_X86_64
8672                 , "rax", "rbx", "rdi", "rsi"
8673                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8674 #else
8675                 , "eax", "ebx", "edi", "esi"
8676 #endif
8677               );
8678
8679         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8680         if (debugctlmsr)
8681                 update_debugctlmsr(debugctlmsr);
8682
8683 #ifndef CONFIG_X86_64
8684         /*
8685          * The sysexit path does not restore ds/es, so we must set them to
8686          * a reasonable value ourselves.
8687          *
8688          * We can't defer this to vmx_load_host_state() since that function
8689          * may be executed in interrupt context, which saves and restore segments
8690          * around it, nullifying its effect.
8691          */
8692         loadsegment(ds, __USER_DS);
8693         loadsegment(es, __USER_DS);
8694 #endif
8695
8696         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8697                                   | (1 << VCPU_EXREG_RFLAGS)
8698                                   | (1 << VCPU_EXREG_PDPTR)
8699                                   | (1 << VCPU_EXREG_SEGMENTS)
8700                                   | (1 << VCPU_EXREG_CR3));
8701         vcpu->arch.regs_dirty = 0;
8702
8703         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8704
8705         vmx->loaded_vmcs->launched = 1;
8706
8707         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8708
8709         /*
8710          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8711          * we did not inject a still-pending event to L1 now because of
8712          * nested_run_pending, we need to re-enable this bit.
8713          */
8714         if (vmx->nested.nested_run_pending)
8715                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8716
8717         vmx->nested.nested_run_pending = 0;
8718
8719         vmx_complete_atomic_exit(vmx);
8720         vmx_recover_nmi_blocking(vmx);
8721         vmx_complete_interrupts(vmx);
8722 }
8723
8724 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8725 {
8726         struct vcpu_vmx *vmx = to_vmx(vcpu);
8727         int cpu;
8728
8729         if (vmx->loaded_vmcs == &vmx->vmcs01)
8730                 return;
8731
8732         cpu = get_cpu();
8733         vmx->loaded_vmcs = &vmx->vmcs01;
8734         vmx_vcpu_put(vcpu);
8735         vmx_vcpu_load(vcpu, cpu);
8736         vcpu->cpu = cpu;
8737         put_cpu();
8738 }
8739
8740 /*
8741  * Ensure that the current vmcs of the logical processor is the
8742  * vmcs01 of the vcpu before calling free_nested().
8743  */
8744 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
8745 {
8746        struct vcpu_vmx *vmx = to_vmx(vcpu);
8747        int r;
8748
8749        r = vcpu_load(vcpu);
8750        BUG_ON(r);
8751        vmx_load_vmcs01(vcpu);
8752        free_nested(vmx);
8753        vcpu_put(vcpu);
8754 }
8755
8756 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8757 {
8758         struct vcpu_vmx *vmx = to_vmx(vcpu);
8759
8760         if (enable_pml)
8761                 vmx_destroy_pml_buffer(vmx);
8762         free_vpid(vmx->vpid);
8763         leave_guest_mode(vcpu);
8764         vmx_free_vcpu_nested(vcpu);
8765         free_loaded_vmcs(vmx->loaded_vmcs);
8766         kfree(vmx->guest_msrs);
8767         kvm_vcpu_uninit(vcpu);
8768         kmem_cache_free(kvm_vcpu_cache, vmx);
8769 }
8770
8771 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8772 {
8773         int err;
8774         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8775         int cpu;
8776
8777         if (!vmx)
8778                 return ERR_PTR(-ENOMEM);
8779
8780         vmx->vpid = allocate_vpid();
8781
8782         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8783         if (err)
8784                 goto free_vcpu;
8785
8786         err = -ENOMEM;
8787
8788         /*
8789          * If PML is turned on, failure on enabling PML just results in failure
8790          * of creating the vcpu, therefore we can simplify PML logic (by
8791          * avoiding dealing with cases, such as enabling PML partially on vcpus
8792          * for the guest, etc.
8793          */
8794         if (enable_pml) {
8795                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
8796                 if (!vmx->pml_pg)
8797                         goto uninit_vcpu;
8798         }
8799
8800         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8801         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8802                      > PAGE_SIZE);
8803
8804         if (!vmx->guest_msrs)
8805                 goto free_pml;
8806
8807         vmx->loaded_vmcs = &vmx->vmcs01;
8808         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8809         if (!vmx->loaded_vmcs->vmcs)
8810                 goto free_msrs;
8811         if (!vmm_exclusive)
8812                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8813         loaded_vmcs_init(vmx->loaded_vmcs);
8814         if (!vmm_exclusive)
8815                 kvm_cpu_vmxoff();
8816
8817         cpu = get_cpu();
8818         vmx_vcpu_load(&vmx->vcpu, cpu);
8819         vmx->vcpu.cpu = cpu;
8820         err = vmx_vcpu_setup(vmx);
8821         vmx_vcpu_put(&vmx->vcpu);
8822         put_cpu();
8823         if (err)
8824                 goto free_vmcs;
8825         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8826                 err = alloc_apic_access_page(kvm);
8827                 if (err)
8828                         goto free_vmcs;
8829         }
8830
8831         if (enable_ept) {
8832                 if (!kvm->arch.ept_identity_map_addr)
8833                         kvm->arch.ept_identity_map_addr =
8834                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8835                 err = init_rmode_identity_map(kvm);
8836                 if (err)
8837                         goto free_vmcs;
8838         }
8839
8840         if (nested) {
8841                 nested_vmx_setup_ctls_msrs(vmx);
8842                 vmx->nested.vpid02 = allocate_vpid();
8843         }
8844
8845         vmx->nested.posted_intr_nv = -1;
8846         vmx->nested.current_vmptr = -1ull;
8847         vmx->nested.current_vmcs12 = NULL;
8848
8849         return &vmx->vcpu;
8850
8851 free_vmcs:
8852         free_vpid(vmx->nested.vpid02);
8853         free_loaded_vmcs(vmx->loaded_vmcs);
8854 free_msrs:
8855         kfree(vmx->guest_msrs);
8856 free_pml:
8857         vmx_destroy_pml_buffer(vmx);
8858 uninit_vcpu:
8859         kvm_vcpu_uninit(&vmx->vcpu);
8860 free_vcpu:
8861         free_vpid(vmx->vpid);
8862         kmem_cache_free(kvm_vcpu_cache, vmx);
8863         return ERR_PTR(err);
8864 }
8865
8866 static void __init vmx_check_processor_compat(void *rtn)
8867 {
8868         struct vmcs_config vmcs_conf;
8869
8870         *(int *)rtn = 0;
8871         if (setup_vmcs_config(&vmcs_conf) < 0)
8872                 *(int *)rtn = -EIO;
8873         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8874                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8875                                 smp_processor_id());
8876                 *(int *)rtn = -EIO;
8877         }
8878 }
8879
8880 static int get_ept_level(void)
8881 {
8882         return VMX_EPT_DEFAULT_GAW + 1;
8883 }
8884
8885 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8886 {
8887         u8 cache;
8888         u64 ipat = 0;
8889
8890         /* For VT-d and EPT combination
8891          * 1. MMIO: always map as UC
8892          * 2. EPT with VT-d:
8893          *   a. VT-d without snooping control feature: can't guarantee the
8894          *      result, try to trust guest.
8895          *   b. VT-d with snooping control feature: snooping control feature of
8896          *      VT-d engine can guarantee the cache correctness. Just set it
8897          *      to WB to keep consistent with host. So the same as item 3.
8898          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8899          *    consistent with host MTRR
8900          */
8901         if (is_mmio) {
8902                 cache = MTRR_TYPE_UNCACHABLE;
8903                 goto exit;
8904         }
8905
8906         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8907                 ipat = VMX_EPT_IPAT_BIT;
8908                 cache = MTRR_TYPE_WRBACK;
8909                 goto exit;
8910         }
8911
8912         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8913                 ipat = VMX_EPT_IPAT_BIT;
8914                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8915                         cache = MTRR_TYPE_WRBACK;
8916                 else
8917                         cache = MTRR_TYPE_UNCACHABLE;
8918                 goto exit;
8919         }
8920
8921         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8922
8923 exit:
8924         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8925 }
8926
8927 static int vmx_get_lpage_level(void)
8928 {
8929         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8930                 return PT_DIRECTORY_LEVEL;
8931         else
8932                 /* For shadow and EPT supported 1GB page */
8933                 return PT_PDPE_LEVEL;
8934 }
8935
8936 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8937 {
8938         /*
8939          * These bits in the secondary execution controls field
8940          * are dynamic, the others are mostly based on the hypervisor
8941          * architecture and the guest's CPUID.  Do not touch the
8942          * dynamic bits.
8943          */
8944         u32 mask =
8945                 SECONDARY_EXEC_SHADOW_VMCS |
8946                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8947                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8948
8949         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8950
8951         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8952                      (new_ctl & ~mask) | (cur_ctl & mask));
8953 }
8954
8955 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8956 {
8957         struct kvm_cpuid_entry2 *best;
8958         struct vcpu_vmx *vmx = to_vmx(vcpu);
8959         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8960
8961         if (vmx_rdtscp_supported()) {
8962                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8963                 if (!rdtscp_enabled)
8964                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8965
8966                 if (nested) {
8967                         if (rdtscp_enabled)
8968                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8969                                         SECONDARY_EXEC_RDTSCP;
8970                         else
8971                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8972                                         ~SECONDARY_EXEC_RDTSCP;
8973                 }
8974         }
8975
8976         /* Exposing INVPCID only when PCID is exposed */
8977         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8978         if (vmx_invpcid_supported() &&
8979             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8980             !guest_cpuid_has_pcid(vcpu))) {
8981                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8982
8983                 if (best)
8984                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8985         }
8986
8987         if (cpu_has_secondary_exec_ctrls())
8988                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8989
8990         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8991                 if (guest_cpuid_has_pcommit(vcpu))
8992                         vmx->nested.nested_vmx_secondary_ctls_high |=
8993                                 SECONDARY_EXEC_PCOMMIT;
8994                 else
8995                         vmx->nested.nested_vmx_secondary_ctls_high &=
8996                                 ~SECONDARY_EXEC_PCOMMIT;
8997         }
8998 }
8999
9000 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9001 {
9002         if (func == 1 && nested)
9003                 entry->ecx |= bit(X86_FEATURE_VMX);
9004 }
9005
9006 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9007                 struct x86_exception *fault)
9008 {
9009         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9010         u32 exit_reason;
9011
9012         if (fault->error_code & PFERR_RSVD_MASK)
9013                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9014         else
9015                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9016         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9017         vmcs12->guest_physical_address = fault->address;
9018 }
9019
9020 /* Callbacks for nested_ept_init_mmu_context: */
9021
9022 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9023 {
9024         /* return the page table to be shadowed - in our case, EPT12 */
9025         return get_vmcs12(vcpu)->ept_pointer;
9026 }
9027
9028 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9029 {
9030         WARN_ON(mmu_is_nested(vcpu));
9031         kvm_init_shadow_ept_mmu(vcpu,
9032                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9033                         VMX_EPT_EXECUTE_ONLY_BIT);
9034         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9035         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9036         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9037
9038         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9039 }
9040
9041 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9042 {
9043         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9044 }
9045
9046 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9047                                             u16 error_code)
9048 {
9049         bool inequality, bit;
9050
9051         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9052         inequality =
9053                 (error_code & vmcs12->page_fault_error_code_mask) !=
9054                  vmcs12->page_fault_error_code_match;
9055         return inequality ^ bit;
9056 }
9057
9058 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9059                 struct x86_exception *fault)
9060 {
9061         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9062
9063         WARN_ON(!is_guest_mode(vcpu));
9064
9065         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9066                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9067                                   vmcs_read32(VM_EXIT_INTR_INFO),
9068                                   vmcs_readl(EXIT_QUALIFICATION));
9069         else
9070                 kvm_inject_page_fault(vcpu, fault);
9071 }
9072
9073 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9074                                         struct vmcs12 *vmcs12)
9075 {
9076         struct vcpu_vmx *vmx = to_vmx(vcpu);
9077         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9078
9079         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9080                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9081                     vmcs12->apic_access_addr >> maxphyaddr)
9082                         return false;
9083
9084                 /*
9085                  * Translate L1 physical address to host physical
9086                  * address for vmcs02. Keep the page pinned, so this
9087                  * physical address remains valid. We keep a reference
9088                  * to it so we can release it later.
9089                  */
9090                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9091                         nested_release_page(vmx->nested.apic_access_page);
9092                 vmx->nested.apic_access_page =
9093                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9094         }
9095
9096         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9097                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9098                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9099                         return false;
9100
9101                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9102                         nested_release_page(vmx->nested.virtual_apic_page);
9103                 vmx->nested.virtual_apic_page =
9104                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9105
9106                 /*
9107                  * Failing the vm entry is _not_ what the processor does
9108                  * but it's basically the only possibility we have.
9109                  * We could still enter the guest if CR8 load exits are
9110                  * enabled, CR8 store exits are enabled, and virtualize APIC
9111                  * access is disabled; in this case the processor would never
9112                  * use the TPR shadow and we could simply clear the bit from
9113                  * the execution control.  But such a configuration is useless,
9114                  * so let's keep the code simple.
9115                  */
9116                 if (!vmx->nested.virtual_apic_page)
9117                         return false;
9118         }
9119
9120         if (nested_cpu_has_posted_intr(vmcs12)) {
9121                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9122                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9123                         return false;
9124
9125                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9126                         kunmap(vmx->nested.pi_desc_page);
9127                         nested_release_page(vmx->nested.pi_desc_page);
9128                 }
9129                 vmx->nested.pi_desc_page =
9130                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9131                 if (!vmx->nested.pi_desc_page)
9132                         return false;
9133
9134                 vmx->nested.pi_desc =
9135                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9136                 if (!vmx->nested.pi_desc) {
9137                         nested_release_page_clean(vmx->nested.pi_desc_page);
9138                         return false;
9139                 }
9140                 vmx->nested.pi_desc =
9141                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9142                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9143                         (PAGE_SIZE - 1)));
9144         }
9145
9146         return true;
9147 }
9148
9149 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9150 {
9151         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9152         struct vcpu_vmx *vmx = to_vmx(vcpu);
9153
9154         if (vcpu->arch.virtual_tsc_khz == 0)
9155                 return;
9156
9157         /* Make sure short timeouts reliably trigger an immediate vmexit.
9158          * hrtimer_start does not guarantee this. */
9159         if (preemption_timeout <= 1) {
9160                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9161                 return;
9162         }
9163
9164         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9165         preemption_timeout *= 1000000;
9166         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9167         hrtimer_start(&vmx->nested.preemption_timer,
9168                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9169 }
9170
9171 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9172                                                 struct vmcs12 *vmcs12)
9173 {
9174         int maxphyaddr;
9175         u64 addr;
9176
9177         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9178                 return 0;
9179
9180         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9181                 WARN_ON(1);
9182                 return -EINVAL;
9183         }
9184         maxphyaddr = cpuid_maxphyaddr(vcpu);
9185
9186         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9187            ((addr + PAGE_SIZE) >> maxphyaddr))
9188                 return -EINVAL;
9189
9190         return 0;
9191 }
9192
9193 /*
9194  * Merge L0's and L1's MSR bitmap, return false to indicate that
9195  * we do not use the hardware.
9196  */
9197 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9198                                                struct vmcs12 *vmcs12)
9199 {
9200         int msr;
9201         struct page *page;
9202         unsigned long *msr_bitmap;
9203
9204         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9205                 return false;
9206
9207         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9208         if (!page) {
9209                 WARN_ON(1);
9210                 return false;
9211         }
9212         msr_bitmap = (unsigned long *)kmap(page);
9213         if (!msr_bitmap) {
9214                 nested_release_page_clean(page);
9215                 WARN_ON(1);
9216                 return false;
9217         }
9218
9219         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9220                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9221                         for (msr = 0x800; msr <= 0x8ff; msr++)
9222                                 nested_vmx_disable_intercept_for_msr(
9223                                         msr_bitmap,
9224                                         vmx_msr_bitmap_nested,
9225                                         msr, MSR_TYPE_R);
9226                 /* TPR is allowed */
9227                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9228                                 vmx_msr_bitmap_nested,
9229                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9230                                 MSR_TYPE_R | MSR_TYPE_W);
9231                 if (nested_cpu_has_vid(vmcs12)) {
9232                         /* EOI and self-IPI are allowed */
9233                         nested_vmx_disable_intercept_for_msr(
9234                                 msr_bitmap,
9235                                 vmx_msr_bitmap_nested,
9236                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9237                                 MSR_TYPE_W);
9238                         nested_vmx_disable_intercept_for_msr(
9239                                 msr_bitmap,
9240                                 vmx_msr_bitmap_nested,
9241                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9242                                 MSR_TYPE_W);
9243                 }
9244         } else {
9245                 /*
9246                  * Enable reading intercept of all the x2apic
9247                  * MSRs. We should not rely on vmcs12 to do any
9248                  * optimizations here, it may have been modified
9249                  * by L1.
9250                  */
9251                 for (msr = 0x800; msr <= 0x8ff; msr++)
9252                         __vmx_enable_intercept_for_msr(
9253                                 vmx_msr_bitmap_nested,
9254                                 msr,
9255                                 MSR_TYPE_R);
9256
9257                 __vmx_enable_intercept_for_msr(
9258                                 vmx_msr_bitmap_nested,
9259                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9260                                 MSR_TYPE_W);
9261                 __vmx_enable_intercept_for_msr(
9262                                 vmx_msr_bitmap_nested,
9263                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9264                                 MSR_TYPE_W);
9265                 __vmx_enable_intercept_for_msr(
9266                                 vmx_msr_bitmap_nested,
9267                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9268                                 MSR_TYPE_W);
9269         }
9270         kunmap(page);
9271         nested_release_page_clean(page);
9272
9273         return true;
9274 }
9275
9276 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9277                                            struct vmcs12 *vmcs12)
9278 {
9279         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9280             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9281             !nested_cpu_has_vid(vmcs12) &&
9282             !nested_cpu_has_posted_intr(vmcs12))
9283                 return 0;
9284
9285         /*
9286          * If virtualize x2apic mode is enabled,
9287          * virtualize apic access must be disabled.
9288          */
9289         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9290             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9291                 return -EINVAL;
9292
9293         /*
9294          * If virtual interrupt delivery is enabled,
9295          * we must exit on external interrupts.
9296          */
9297         if (nested_cpu_has_vid(vmcs12) &&
9298            !nested_exit_on_intr(vcpu))
9299                 return -EINVAL;
9300
9301         /*
9302          * bits 15:8 should be zero in posted_intr_nv,
9303          * the descriptor address has been already checked
9304          * in nested_get_vmcs12_pages.
9305          */
9306         if (nested_cpu_has_posted_intr(vmcs12) &&
9307            (!nested_cpu_has_vid(vmcs12) ||
9308             !nested_exit_intr_ack_set(vcpu) ||
9309             vmcs12->posted_intr_nv & 0xff00))
9310                 return -EINVAL;
9311
9312         /* tpr shadow is needed by all apicv features. */
9313         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9314                 return -EINVAL;
9315
9316         return 0;
9317 }
9318
9319 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9320                                        unsigned long count_field,
9321                                        unsigned long addr_field)
9322 {
9323         int maxphyaddr;
9324         u64 count, addr;
9325
9326         if (vmcs12_read_any(vcpu, count_field, &count) ||
9327             vmcs12_read_any(vcpu, addr_field, &addr)) {
9328                 WARN_ON(1);
9329                 return -EINVAL;
9330         }
9331         if (count == 0)
9332                 return 0;
9333         maxphyaddr = cpuid_maxphyaddr(vcpu);
9334         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9335             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9336                 pr_warn_ratelimited(
9337                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9338                         addr_field, maxphyaddr, count, addr);
9339                 return -EINVAL;
9340         }
9341         return 0;
9342 }
9343
9344 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9345                                                 struct vmcs12 *vmcs12)
9346 {
9347         if (vmcs12->vm_exit_msr_load_count == 0 &&
9348             vmcs12->vm_exit_msr_store_count == 0 &&
9349             vmcs12->vm_entry_msr_load_count == 0)
9350                 return 0; /* Fast path */
9351         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9352                                         VM_EXIT_MSR_LOAD_ADDR) ||
9353             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9354                                         VM_EXIT_MSR_STORE_ADDR) ||
9355             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9356                                         VM_ENTRY_MSR_LOAD_ADDR))
9357                 return -EINVAL;
9358         return 0;
9359 }
9360
9361 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9362                                        struct vmx_msr_entry *e)
9363 {
9364         /* x2APIC MSR accesses are not allowed */
9365         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9366                 return -EINVAL;
9367         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9368             e->index == MSR_IA32_UCODE_REV)
9369                 return -EINVAL;
9370         if (e->reserved != 0)
9371                 return -EINVAL;
9372         return 0;
9373 }
9374
9375 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9376                                      struct vmx_msr_entry *e)
9377 {
9378         if (e->index == MSR_FS_BASE ||
9379             e->index == MSR_GS_BASE ||
9380             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9381             nested_vmx_msr_check_common(vcpu, e))
9382                 return -EINVAL;
9383         return 0;
9384 }
9385
9386 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9387                                       struct vmx_msr_entry *e)
9388 {
9389         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9390             nested_vmx_msr_check_common(vcpu, e))
9391                 return -EINVAL;
9392         return 0;
9393 }
9394
9395 /*
9396  * Load guest's/host's msr at nested entry/exit.
9397  * return 0 for success, entry index for failure.
9398  */
9399 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9400 {
9401         u32 i;
9402         struct vmx_msr_entry e;
9403         struct msr_data msr;
9404
9405         msr.host_initiated = false;
9406         for (i = 0; i < count; i++) {
9407                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9408                                         &e, sizeof(e))) {
9409                         pr_warn_ratelimited(
9410                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9411                                 __func__, i, gpa + i * sizeof(e));
9412                         goto fail;
9413                 }
9414                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9415                         pr_warn_ratelimited(
9416                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9417                                 __func__, i, e.index, e.reserved);
9418                         goto fail;
9419                 }
9420                 msr.index = e.index;
9421                 msr.data = e.value;
9422                 if (kvm_set_msr(vcpu, &msr)) {
9423                         pr_warn_ratelimited(
9424                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9425                                 __func__, i, e.index, e.value);
9426                         goto fail;
9427                 }
9428         }
9429         return 0;
9430 fail:
9431         return i + 1;
9432 }
9433
9434 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9435 {
9436         u32 i;
9437         struct vmx_msr_entry e;
9438
9439         for (i = 0; i < count; i++) {
9440                 struct msr_data msr_info;
9441                 if (kvm_vcpu_read_guest(vcpu,
9442                                         gpa + i * sizeof(e),
9443                                         &e, 2 * sizeof(u32))) {
9444                         pr_warn_ratelimited(
9445                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9446                                 __func__, i, gpa + i * sizeof(e));
9447                         return -EINVAL;
9448                 }
9449                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9450                         pr_warn_ratelimited(
9451                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9452                                 __func__, i, e.index, e.reserved);
9453                         return -EINVAL;
9454                 }
9455                 msr_info.host_initiated = false;
9456                 msr_info.index = e.index;
9457                 if (kvm_get_msr(vcpu, &msr_info)) {
9458                         pr_warn_ratelimited(
9459                                 "%s cannot read MSR (%u, 0x%x)\n",
9460                                 __func__, i, e.index);
9461                         return -EINVAL;
9462                 }
9463                 if (kvm_vcpu_write_guest(vcpu,
9464                                          gpa + i * sizeof(e) +
9465                                              offsetof(struct vmx_msr_entry, value),
9466                                          &msr_info.data, sizeof(msr_info.data))) {
9467                         pr_warn_ratelimited(
9468                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9469                                 __func__, i, e.index, msr_info.data);
9470                         return -EINVAL;
9471                 }
9472         }
9473         return 0;
9474 }
9475
9476 /*
9477  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9478  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9479  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9480  * guest in a way that will both be appropriate to L1's requests, and our
9481  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9482  * function also has additional necessary side-effects, like setting various
9483  * vcpu->arch fields.
9484  */
9485 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9486 {
9487         struct vcpu_vmx *vmx = to_vmx(vcpu);
9488         u32 exec_control;
9489
9490         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9491         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9492         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9493         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9494         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9495         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9496         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9497         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9498         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9499         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9500         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9501         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9502         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9503         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9504         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9505         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9506         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9507         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9508         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9509         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9510         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9511         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9512         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9513         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9514         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9515         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9516         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9517         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9518         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9519         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9520         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9521         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9522         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9523         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9524         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9525         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9526
9527         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9528                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9529                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9530         } else {
9531                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9532                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9533         }
9534         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9535                 vmcs12->vm_entry_intr_info_field);
9536         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9537                 vmcs12->vm_entry_exception_error_code);
9538         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9539                 vmcs12->vm_entry_instruction_len);
9540         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9541                 vmcs12->guest_interruptibility_info);
9542         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9543         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9544         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9545                 vmcs12->guest_pending_dbg_exceptions);
9546         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9547         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9548
9549         if (nested_cpu_has_xsaves(vmcs12))
9550                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9551         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9552
9553         exec_control = vmcs12->pin_based_vm_exec_control;
9554         exec_control |= vmcs_config.pin_based_exec_ctrl;
9555         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9556
9557         if (nested_cpu_has_posted_intr(vmcs12)) {
9558                 /*
9559                  * Note that we use L0's vector here and in
9560                  * vmx_deliver_nested_posted_interrupt.
9561                  */
9562                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9563                 vmx->nested.pi_pending = false;
9564                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9565                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9566                         page_to_phys(vmx->nested.pi_desc_page) +
9567                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9568                         (PAGE_SIZE - 1)));
9569         } else
9570                 exec_control &= ~PIN_BASED_POSTED_INTR;
9571
9572         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9573
9574         vmx->nested.preemption_timer_expired = false;
9575         if (nested_cpu_has_preemption_timer(vmcs12))
9576                 vmx_start_preemption_timer(vcpu);
9577
9578         /*
9579          * Whether page-faults are trapped is determined by a combination of
9580          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9581          * If enable_ept, L0 doesn't care about page faults and we should
9582          * set all of these to L1's desires. However, if !enable_ept, L0 does
9583          * care about (at least some) page faults, and because it is not easy
9584          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9585          * to exit on each and every L2 page fault. This is done by setting
9586          * MASK=MATCH=0 and (see below) EB.PF=1.
9587          * Note that below we don't need special code to set EB.PF beyond the
9588          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9589          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9590          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9591          *
9592          * A problem with this approach (when !enable_ept) is that L1 may be
9593          * injected with more page faults than it asked for. This could have
9594          * caused problems, but in practice existing hypervisors don't care.
9595          * To fix this, we will need to emulate the PFEC checking (on the L1
9596          * page tables), using walk_addr(), when injecting PFs to L1.
9597          */
9598         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9599                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9600         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9601                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9602
9603         if (cpu_has_secondary_exec_ctrls()) {
9604                 exec_control = vmx_secondary_exec_control(vmx);
9605
9606                 /* Take the following fields only from vmcs12 */
9607                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9608                                   SECONDARY_EXEC_RDTSCP |
9609                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9610                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9611                                   SECONDARY_EXEC_PCOMMIT);
9612                 if (nested_cpu_has(vmcs12,
9613                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9614                         exec_control |= vmcs12->secondary_vm_exec_control;
9615
9616                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9617                         /*
9618                          * If translation failed, no matter: This feature asks
9619                          * to exit when accessing the given address, and if it
9620                          * can never be accessed, this feature won't do
9621                          * anything anyway.
9622                          */
9623                         if (!vmx->nested.apic_access_page)
9624                                 exec_control &=
9625                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9626                         else
9627                                 vmcs_write64(APIC_ACCESS_ADDR,
9628                                   page_to_phys(vmx->nested.apic_access_page));
9629                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9630                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9631                         exec_control |=
9632                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9633                         kvm_vcpu_reload_apic_access_page(vcpu);
9634                 }
9635
9636                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9637                         vmcs_write64(EOI_EXIT_BITMAP0,
9638                                 vmcs12->eoi_exit_bitmap0);
9639                         vmcs_write64(EOI_EXIT_BITMAP1,
9640                                 vmcs12->eoi_exit_bitmap1);
9641                         vmcs_write64(EOI_EXIT_BITMAP2,
9642                                 vmcs12->eoi_exit_bitmap2);
9643                         vmcs_write64(EOI_EXIT_BITMAP3,
9644                                 vmcs12->eoi_exit_bitmap3);
9645                         vmcs_write16(GUEST_INTR_STATUS,
9646                                 vmcs12->guest_intr_status);
9647                 }
9648
9649                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9650         }
9651
9652
9653         /*
9654          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9655          * Some constant fields are set here by vmx_set_constant_host_state().
9656          * Other fields are different per CPU, and will be set later when
9657          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9658          */
9659         vmx_set_constant_host_state(vmx);
9660
9661         /*
9662          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9663          * entry, but only if the current (host) sp changed from the value
9664          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9665          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9666          * here we just force the write to happen on entry.
9667          */
9668         vmx->host_rsp = 0;
9669
9670         exec_control = vmx_exec_control(vmx); /* L0's desires */
9671         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9672         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9673         exec_control &= ~CPU_BASED_TPR_SHADOW;
9674         exec_control |= vmcs12->cpu_based_vm_exec_control;
9675
9676         if (exec_control & CPU_BASED_TPR_SHADOW) {
9677                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9678                                 page_to_phys(vmx->nested.virtual_apic_page));
9679                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9680         }
9681
9682         if (cpu_has_vmx_msr_bitmap() &&
9683             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9684                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9685                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9686         } else
9687                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9688
9689         /*
9690          * Merging of IO bitmap not currently supported.
9691          * Rather, exit every time.
9692          */
9693         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9694         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9695
9696         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9697
9698         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9699          * bitwise-or of what L1 wants to trap for L2, and what we want to
9700          * trap. Note that CR0.TS also needs updating - we do this later.
9701          */
9702         update_exception_bitmap(vcpu);
9703         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9704         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9705
9706         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9707          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9708          * bits are further modified by vmx_set_efer() below.
9709          */
9710         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9711
9712         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9713          * emulated by vmx_set_efer(), below.
9714          */
9715         vm_entry_controls_init(vmx,
9716                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9717                         ~VM_ENTRY_IA32E_MODE) |
9718                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9719
9720         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9721                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9722                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9723         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9724                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9725
9726
9727         set_cr4_guest_host_mask(vmx);
9728
9729         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9730                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9731
9732         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9733                 vmcs_write64(TSC_OFFSET,
9734                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9735         else
9736                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9737
9738         if (enable_vpid) {
9739                 /*
9740                  * There is no direct mapping between vpid02 and vpid12, the
9741                  * vpid02 is per-vCPU for L0 and reused while the value of
9742                  * vpid12 is changed w/ one invvpid during nested vmentry.
9743                  * The vpid12 is allocated by L1 for L2, so it will not
9744                  * influence global bitmap(for vpid01 and vpid02 allocation)
9745                  * even if spawn a lot of nested vCPUs.
9746                  */
9747                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9748                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9749                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9750                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9751                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9752                         }
9753                 } else {
9754                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9755                         vmx_flush_tlb(vcpu);
9756                 }
9757
9758         }
9759
9760         if (nested_cpu_has_ept(vmcs12)) {
9761                 kvm_mmu_unload(vcpu);
9762                 nested_ept_init_mmu_context(vcpu);
9763         }
9764
9765         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9766                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9767         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9768                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9769         else
9770                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9771         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9772         vmx_set_efer(vcpu, vcpu->arch.efer);
9773
9774         /*
9775          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9776          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9777          * The CR0_READ_SHADOW is what L2 should have expected to read given
9778          * the specifications by L1; It's not enough to take
9779          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9780          * have more bits than L1 expected.
9781          */
9782         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9783         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9784
9785         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9786         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9787
9788         /* shadow page tables on either EPT or shadow page tables */
9789         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9790         kvm_mmu_reset_context(vcpu);
9791
9792         if (!enable_ept)
9793                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9794
9795         /*
9796          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9797          */
9798         if (enable_ept) {
9799                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9800                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9801                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9802                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9803         }
9804
9805         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9806         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9807 }
9808
9809 /*
9810  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9811  * for running an L2 nested guest.
9812  */
9813 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9814 {
9815         struct vmcs12 *vmcs12;
9816         struct vcpu_vmx *vmx = to_vmx(vcpu);
9817         int cpu;
9818         struct loaded_vmcs *vmcs02;
9819         bool ia32e;
9820         u32 msr_entry_idx;
9821
9822         if (!nested_vmx_check_permission(vcpu) ||
9823             !nested_vmx_check_vmcs12(vcpu))
9824                 return 1;
9825
9826         skip_emulated_instruction(vcpu);
9827         vmcs12 = get_vmcs12(vcpu);
9828
9829         if (enable_shadow_vmcs)
9830                 copy_shadow_to_vmcs12(vmx);
9831
9832         /*
9833          * The nested entry process starts with enforcing various prerequisites
9834          * on vmcs12 as required by the Intel SDM, and act appropriately when
9835          * they fail: As the SDM explains, some conditions should cause the
9836          * instruction to fail, while others will cause the instruction to seem
9837          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9838          * To speed up the normal (success) code path, we should avoid checking
9839          * for misconfigurations which will anyway be caught by the processor
9840          * when using the merged vmcs02.
9841          */
9842         if (vmcs12->launch_state == launch) {
9843                 nested_vmx_failValid(vcpu,
9844                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9845                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9846                 return 1;
9847         }
9848
9849         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9850             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9851                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9852                 return 1;
9853         }
9854
9855         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9856                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9857                 return 1;
9858         }
9859
9860         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9861                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9862                 return 1;
9863         }
9864
9865         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9866                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9867                 return 1;
9868         }
9869
9870         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9871                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9872                 return 1;
9873         }
9874
9875         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9876                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9877                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9878             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9879                                 vmx->nested.nested_vmx_secondary_ctls_low,
9880                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9881             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9882                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9883                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9884             !vmx_control_verify(vmcs12->vm_exit_controls,
9885                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9886                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9887             !vmx_control_verify(vmcs12->vm_entry_controls,
9888                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9889                                 vmx->nested.nested_vmx_entry_ctls_high))
9890         {
9891                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9892                 return 1;
9893         }
9894
9895         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9896             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9897                 nested_vmx_failValid(vcpu,
9898                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9899                 return 1;
9900         }
9901
9902         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9903             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9904                 nested_vmx_entry_failure(vcpu, vmcs12,
9905                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9906                 return 1;
9907         }
9908         if (vmcs12->vmcs_link_pointer != -1ull) {
9909                 nested_vmx_entry_failure(vcpu, vmcs12,
9910                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9911                 return 1;
9912         }
9913
9914         /*
9915          * If the load IA32_EFER VM-entry control is 1, the following checks
9916          * are performed on the field for the IA32_EFER MSR:
9917          * - Bits reserved in the IA32_EFER MSR must be 0.
9918          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9919          *   the IA-32e mode guest VM-exit control. It must also be identical
9920          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9921          *   CR0.PG) is 1.
9922          */
9923         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9924                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9925                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9926                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9927                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9928                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9929                         nested_vmx_entry_failure(vcpu, vmcs12,
9930                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9931                         return 1;
9932                 }
9933         }
9934
9935         /*
9936          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9937          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9938          * the values of the LMA and LME bits in the field must each be that of
9939          * the host address-space size VM-exit control.
9940          */
9941         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9942                 ia32e = (vmcs12->vm_exit_controls &
9943                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9944                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9945                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9946                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9947                         nested_vmx_entry_failure(vcpu, vmcs12,
9948                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9949                         return 1;
9950                 }
9951         }
9952
9953         /*
9954          * We're finally done with prerequisite checking, and can start with
9955          * the nested entry.
9956          */
9957
9958         vmcs02 = nested_get_current_vmcs02(vmx);
9959         if (!vmcs02)
9960                 return -ENOMEM;
9961
9962         enter_guest_mode(vcpu);
9963
9964         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9965
9966         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9967                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9968
9969         cpu = get_cpu();
9970         vmx->loaded_vmcs = vmcs02;
9971         vmx_vcpu_put(vcpu);
9972         vmx_vcpu_load(vcpu, cpu);
9973         vcpu->cpu = cpu;
9974         put_cpu();
9975
9976         vmx_segment_cache_clear(vmx);
9977
9978         prepare_vmcs02(vcpu, vmcs12);
9979
9980         msr_entry_idx = nested_vmx_load_msr(vcpu,
9981                                             vmcs12->vm_entry_msr_load_addr,
9982                                             vmcs12->vm_entry_msr_load_count);
9983         if (msr_entry_idx) {
9984                 leave_guest_mode(vcpu);
9985                 vmx_load_vmcs01(vcpu);
9986                 nested_vmx_entry_failure(vcpu, vmcs12,
9987                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9988                 return 1;
9989         }
9990
9991         vmcs12->launch_state = 1;
9992
9993         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9994                 return kvm_vcpu_halt(vcpu);
9995
9996         vmx->nested.nested_run_pending = 1;
9997
9998         /*
9999          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10000          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10001          * returned as far as L1 is concerned. It will only return (and set
10002          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10003          */
10004         return 1;
10005 }
10006
10007 /*
10008  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10009  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10010  * This function returns the new value we should put in vmcs12.guest_cr0.
10011  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10012  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10013  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10014  *     didn't trap the bit, because if L1 did, so would L0).
10015  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10016  *     been modified by L2, and L1 knows it. So just leave the old value of
10017  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10018  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10019  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10020  *     changed these bits, and therefore they need to be updated, but L0
10021  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10022  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10023  */
10024 static inline unsigned long
10025 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10026 {
10027         return
10028         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10029         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10030         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10031                         vcpu->arch.cr0_guest_owned_bits));
10032 }
10033
10034 static inline unsigned long
10035 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10036 {
10037         return
10038         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10039         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10040         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10041                         vcpu->arch.cr4_guest_owned_bits));
10042 }
10043
10044 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10045                                        struct vmcs12 *vmcs12)
10046 {
10047         u32 idt_vectoring;
10048         unsigned int nr;
10049
10050         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10051                 nr = vcpu->arch.exception.nr;
10052                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10053
10054                 if (kvm_exception_is_soft(nr)) {
10055                         vmcs12->vm_exit_instruction_len =
10056                                 vcpu->arch.event_exit_inst_len;
10057                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10058                 } else
10059                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10060
10061                 if (vcpu->arch.exception.has_error_code) {
10062                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10063                         vmcs12->idt_vectoring_error_code =
10064                                 vcpu->arch.exception.error_code;
10065                 }
10066
10067                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10068         } else if (vcpu->arch.nmi_injected) {
10069                 vmcs12->idt_vectoring_info_field =
10070                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10071         } else if (vcpu->arch.interrupt.pending) {
10072                 nr = vcpu->arch.interrupt.nr;
10073                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10074
10075                 if (vcpu->arch.interrupt.soft) {
10076                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10077                         vmcs12->vm_entry_instruction_len =
10078                                 vcpu->arch.event_exit_inst_len;
10079                 } else
10080                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10081
10082                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10083         }
10084 }
10085
10086 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10087 {
10088         struct vcpu_vmx *vmx = to_vmx(vcpu);
10089
10090         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10091             vmx->nested.preemption_timer_expired) {
10092                 if (vmx->nested.nested_run_pending)
10093                         return -EBUSY;
10094                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10095                 return 0;
10096         }
10097
10098         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10099                 if (vmx->nested.nested_run_pending ||
10100                     vcpu->arch.interrupt.pending)
10101                         return -EBUSY;
10102                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10103                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10104                                   INTR_INFO_VALID_MASK, 0);
10105                 /*
10106                  * The NMI-triggered VM exit counts as injection:
10107                  * clear this one and block further NMIs.
10108                  */
10109                 vcpu->arch.nmi_pending = 0;
10110                 vmx_set_nmi_mask(vcpu, true);
10111                 return 0;
10112         }
10113
10114         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10115             nested_exit_on_intr(vcpu)) {
10116                 if (vmx->nested.nested_run_pending)
10117                         return -EBUSY;
10118                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10119                 return 0;
10120         }
10121
10122         return vmx_complete_nested_posted_interrupt(vcpu);
10123 }
10124
10125 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10126 {
10127         ktime_t remaining =
10128                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10129         u64 value;
10130
10131         if (ktime_to_ns(remaining) <= 0)
10132                 return 0;
10133
10134         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10135         do_div(value, 1000000);
10136         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10137 }
10138
10139 /*
10140  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10141  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10142  * and this function updates it to reflect the changes to the guest state while
10143  * L2 was running (and perhaps made some exits which were handled directly by L0
10144  * without going back to L1), and to reflect the exit reason.
10145  * Note that we do not have to copy here all VMCS fields, just those that
10146  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10147  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10148  * which already writes to vmcs12 directly.
10149  */
10150 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10151                            u32 exit_reason, u32 exit_intr_info,
10152                            unsigned long exit_qualification)
10153 {
10154         /* update guest state fields: */
10155         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10156         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10157
10158         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10159         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10160         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10161
10162         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10163         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10164         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10165         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10166         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10167         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10168         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10169         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10170         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10171         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10172         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10173         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10174         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10175         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10176         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10177         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10178         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10179         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10180         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10181         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10182         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10183         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10184         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10185         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10186         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10187         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10188         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10189         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10190         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10191         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10192         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10193         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10194         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10195         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10196         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10197         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10198
10199         vmcs12->guest_interruptibility_info =
10200                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10201         vmcs12->guest_pending_dbg_exceptions =
10202                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10203         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10204                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10205         else
10206                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10207
10208         if (nested_cpu_has_preemption_timer(vmcs12)) {
10209                 if (vmcs12->vm_exit_controls &
10210                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10211                         vmcs12->vmx_preemption_timer_value =
10212                                 vmx_get_preemption_timer_value(vcpu);
10213                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10214         }
10215
10216         /*
10217          * In some cases (usually, nested EPT), L2 is allowed to change its
10218          * own CR3 without exiting. If it has changed it, we must keep it.
10219          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10220          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10221          *
10222          * Additionally, restore L2's PDPTR to vmcs12.
10223          */
10224         if (enable_ept) {
10225                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10226                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10227                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10228                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10229                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10230         }
10231
10232         if (nested_cpu_has_vid(vmcs12))
10233                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10234
10235         vmcs12->vm_entry_controls =
10236                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10237                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10238
10239         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10240                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10241                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10242         }
10243
10244         /* TODO: These cannot have changed unless we have MSR bitmaps and
10245          * the relevant bit asks not to trap the change */
10246         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10247                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10248         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10249                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10250         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10251         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10252         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10253         if (vmx_mpx_supported())
10254                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10255         if (nested_cpu_has_xsaves(vmcs12))
10256                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10257
10258         /* update exit information fields: */
10259
10260         vmcs12->vm_exit_reason = exit_reason;
10261         vmcs12->exit_qualification = exit_qualification;
10262
10263         vmcs12->vm_exit_intr_info = exit_intr_info;
10264         if ((vmcs12->vm_exit_intr_info &
10265              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10266             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10267                 vmcs12->vm_exit_intr_error_code =
10268                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10269         vmcs12->idt_vectoring_info_field = 0;
10270         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10271         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10272
10273         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10274                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10275                  * instead of reading the real value. */
10276                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10277
10278                 /*
10279                  * Transfer the event that L0 or L1 may wanted to inject into
10280                  * L2 to IDT_VECTORING_INFO_FIELD.
10281                  */
10282                 vmcs12_save_pending_event(vcpu, vmcs12);
10283         }
10284
10285         /*
10286          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10287          * preserved above and would only end up incorrectly in L1.
10288          */
10289         vcpu->arch.nmi_injected = false;
10290         kvm_clear_exception_queue(vcpu);
10291         kvm_clear_interrupt_queue(vcpu);
10292 }
10293
10294 /*
10295  * A part of what we need to when the nested L2 guest exits and we want to
10296  * run its L1 parent, is to reset L1's guest state to the host state specified
10297  * in vmcs12.
10298  * This function is to be called not only on normal nested exit, but also on
10299  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10300  * Failures During or After Loading Guest State").
10301  * This function should be called when the active VMCS is L1's (vmcs01).
10302  */
10303 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10304                                    struct vmcs12 *vmcs12)
10305 {
10306         struct kvm_segment seg;
10307
10308         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10309                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10310         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10311                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10312         else
10313                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10314         vmx_set_efer(vcpu, vcpu->arch.efer);
10315
10316         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10317         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10318         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10319         /*
10320          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10321          * actually changed, because it depends on the current state of
10322          * fpu_active (which may have changed).
10323          * Note that vmx_set_cr0 refers to efer set above.
10324          */
10325         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10326         /*
10327          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10328          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10329          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10330          */
10331         update_exception_bitmap(vcpu);
10332         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10333         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10334
10335         /*
10336          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10337          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10338          */
10339         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10340         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10341
10342         nested_ept_uninit_mmu_context(vcpu);
10343
10344         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10345         kvm_mmu_reset_context(vcpu);
10346
10347         if (!enable_ept)
10348                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10349
10350         if (enable_vpid) {
10351                 /*
10352                  * Trivially support vpid by letting L2s share their parent
10353                  * L1's vpid. TODO: move to a more elaborate solution, giving
10354                  * each L2 its own vpid and exposing the vpid feature to L1.
10355                  */
10356                 vmx_flush_tlb(vcpu);
10357         }
10358
10359
10360         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10361         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10362         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10363         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10364         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10365
10366         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10367         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10368                 vmcs_write64(GUEST_BNDCFGS, 0);
10369
10370         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10371                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10372                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10373         }
10374         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10375                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10376                         vmcs12->host_ia32_perf_global_ctrl);
10377
10378         /* Set L1 segment info according to Intel SDM
10379             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10380         seg = (struct kvm_segment) {
10381                 .base = 0,
10382                 .limit = 0xFFFFFFFF,
10383                 .selector = vmcs12->host_cs_selector,
10384                 .type = 11,
10385                 .present = 1,
10386                 .s = 1,
10387                 .g = 1
10388         };
10389         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10390                 seg.l = 1;
10391         else
10392                 seg.db = 1;
10393         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10394         seg = (struct kvm_segment) {
10395                 .base = 0,
10396                 .limit = 0xFFFFFFFF,
10397                 .type = 3,
10398                 .present = 1,
10399                 .s = 1,
10400                 .db = 1,
10401                 .g = 1
10402         };
10403         seg.selector = vmcs12->host_ds_selector;
10404         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10405         seg.selector = vmcs12->host_es_selector;
10406         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10407         seg.selector = vmcs12->host_ss_selector;
10408         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10409         seg.selector = vmcs12->host_fs_selector;
10410         seg.base = vmcs12->host_fs_base;
10411         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10412         seg.selector = vmcs12->host_gs_selector;
10413         seg.base = vmcs12->host_gs_base;
10414         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10415         seg = (struct kvm_segment) {
10416                 .base = vmcs12->host_tr_base,
10417                 .limit = 0x67,
10418                 .selector = vmcs12->host_tr_selector,
10419                 .type = 11,
10420                 .present = 1
10421         };
10422         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10423
10424         kvm_set_dr(vcpu, 7, 0x400);
10425         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10426
10427         if (cpu_has_vmx_msr_bitmap())
10428                 vmx_set_msr_bitmap(vcpu);
10429
10430         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10431                                 vmcs12->vm_exit_msr_load_count))
10432                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10433 }
10434
10435 /*
10436  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10437  * and modify vmcs12 to make it see what it would expect to see there if
10438  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10439  */
10440 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10441                               u32 exit_intr_info,
10442                               unsigned long exit_qualification)
10443 {
10444         struct vcpu_vmx *vmx = to_vmx(vcpu);
10445         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10446
10447         /* trying to cancel vmlaunch/vmresume is a bug */
10448         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10449
10450         leave_guest_mode(vcpu);
10451         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10452                        exit_qualification);
10453
10454         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10455                                  vmcs12->vm_exit_msr_store_count))
10456                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10457
10458         vmx_load_vmcs01(vcpu);
10459
10460         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10461             && nested_exit_intr_ack_set(vcpu)) {
10462                 int irq = kvm_cpu_get_interrupt(vcpu);
10463                 WARN_ON(irq < 0);
10464                 vmcs12->vm_exit_intr_info = irq |
10465                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10466         }
10467
10468         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10469                                        vmcs12->exit_qualification,
10470                                        vmcs12->idt_vectoring_info_field,
10471                                        vmcs12->vm_exit_intr_info,
10472                                        vmcs12->vm_exit_intr_error_code,
10473                                        KVM_ISA_VMX);
10474
10475         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10476         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10477         vmx_segment_cache_clear(vmx);
10478
10479         /* if no vmcs02 cache requested, remove the one we used */
10480         if (VMCS02_POOL_SIZE == 0)
10481                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10482
10483         load_vmcs12_host_state(vcpu, vmcs12);
10484
10485         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10486         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10487
10488         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10489                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10490                 vmx_set_virtual_x2apic_mode(vcpu,
10491                                 vcpu->arch.apic_base & X2APIC_ENABLE);
10492         }
10493
10494         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10495         vmx->host_rsp = 0;
10496
10497         /* Unpin physical memory we referred to in vmcs02 */
10498         if (vmx->nested.apic_access_page) {
10499                 nested_release_page(vmx->nested.apic_access_page);
10500                 vmx->nested.apic_access_page = NULL;
10501         }
10502         if (vmx->nested.virtual_apic_page) {
10503                 nested_release_page(vmx->nested.virtual_apic_page);
10504                 vmx->nested.virtual_apic_page = NULL;
10505         }
10506         if (vmx->nested.pi_desc_page) {
10507                 kunmap(vmx->nested.pi_desc_page);
10508                 nested_release_page(vmx->nested.pi_desc_page);
10509                 vmx->nested.pi_desc_page = NULL;
10510                 vmx->nested.pi_desc = NULL;
10511         }
10512
10513         /*
10514          * We are now running in L2, mmu_notifier will force to reload the
10515          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10516          */
10517         kvm_vcpu_reload_apic_access_page(vcpu);
10518
10519         /*
10520          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10521          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10522          * success or failure flag accordingly.
10523          */
10524         if (unlikely(vmx->fail)) {
10525                 vmx->fail = 0;
10526                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10527         } else
10528                 nested_vmx_succeed(vcpu);
10529         if (enable_shadow_vmcs)
10530                 vmx->nested.sync_shadow_vmcs = true;
10531
10532         /* in case we halted in L2 */
10533         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10534 }
10535
10536 /*
10537  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10538  */
10539 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10540 {
10541         if (is_guest_mode(vcpu))
10542                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10543         free_nested(to_vmx(vcpu));
10544 }
10545
10546 /*
10547  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10548  * 23.7 "VM-entry failures during or after loading guest state" (this also
10549  * lists the acceptable exit-reason and exit-qualification parameters).
10550  * It should only be called before L2 actually succeeded to run, and when
10551  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10552  */
10553 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10554                         struct vmcs12 *vmcs12,
10555                         u32 reason, unsigned long qualification)
10556 {
10557         load_vmcs12_host_state(vcpu, vmcs12);
10558         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10559         vmcs12->exit_qualification = qualification;
10560         nested_vmx_succeed(vcpu);
10561         if (enable_shadow_vmcs)
10562                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10563 }
10564
10565 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10566                                struct x86_instruction_info *info,
10567                                enum x86_intercept_stage stage)
10568 {
10569         return X86EMUL_CONTINUE;
10570 }
10571
10572 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10573 {
10574         if (ple_gap)
10575                 shrink_ple_window(vcpu);
10576 }
10577
10578 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10579                                      struct kvm_memory_slot *slot)
10580 {
10581         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10582         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10583 }
10584
10585 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10586                                        struct kvm_memory_slot *slot)
10587 {
10588         kvm_mmu_slot_set_dirty(kvm, slot);
10589 }
10590
10591 static void vmx_flush_log_dirty(struct kvm *kvm)
10592 {
10593         kvm_flush_pml_buffers(kvm);
10594 }
10595
10596 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10597                                            struct kvm_memory_slot *memslot,
10598                                            gfn_t offset, unsigned long mask)
10599 {
10600         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10601 }
10602
10603 /*
10604  * This routine does the following things for vCPU which is going
10605  * to be blocked if VT-d PI is enabled.
10606  * - Store the vCPU to the wakeup list, so when interrupts happen
10607  *   we can find the right vCPU to wake up.
10608  * - Change the Posted-interrupt descriptor as below:
10609  *      'NDST' <-- vcpu->pre_pcpu
10610  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10611  * - If 'ON' is set during this process, which means at least one
10612  *   interrupt is posted for this vCPU, we cannot block it, in
10613  *   this case, return 1, otherwise, return 0.
10614  *
10615  */
10616 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10617 {
10618         unsigned long flags;
10619         unsigned int dest;
10620         struct pi_desc old, new;
10621         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10622
10623         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10624                 !irq_remapping_cap(IRQ_POSTING_CAP))
10625                 return 0;
10626
10627         vcpu->pre_pcpu = vcpu->cpu;
10628         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10629                           vcpu->pre_pcpu), flags);
10630         list_add_tail(&vcpu->blocked_vcpu_list,
10631                       &per_cpu(blocked_vcpu_on_cpu,
10632                       vcpu->pre_pcpu));
10633         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10634                                vcpu->pre_pcpu), flags);
10635
10636         do {
10637                 old.control = new.control = pi_desc->control;
10638
10639                 /*
10640                  * We should not block the vCPU if
10641                  * an interrupt is posted for it.
10642                  */
10643                 if (pi_test_on(pi_desc) == 1) {
10644                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10645                                           vcpu->pre_pcpu), flags);
10646                         list_del(&vcpu->blocked_vcpu_list);
10647                         spin_unlock_irqrestore(
10648                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10649                                         vcpu->pre_pcpu), flags);
10650                         vcpu->pre_pcpu = -1;
10651
10652                         return 1;
10653                 }
10654
10655                 WARN((pi_desc->sn == 1),
10656                      "Warning: SN field of posted-interrupts "
10657                      "is set before blocking\n");
10658
10659                 /*
10660                  * Since vCPU can be preempted during this process,
10661                  * vcpu->cpu could be different with pre_pcpu, we
10662                  * need to set pre_pcpu as the destination of wakeup
10663                  * notification event, then we can find the right vCPU
10664                  * to wakeup in wakeup handler if interrupts happen
10665                  * when the vCPU is in blocked state.
10666                  */
10667                 dest = cpu_physical_id(vcpu->pre_pcpu);
10668
10669                 if (x2apic_enabled())
10670                         new.ndst = dest;
10671                 else
10672                         new.ndst = (dest << 8) & 0xFF00;
10673
10674                 /* set 'NV' to 'wakeup vector' */
10675                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10676         } while (cmpxchg(&pi_desc->control, old.control,
10677                         new.control) != old.control);
10678
10679         return 0;
10680 }
10681
10682 static void vmx_post_block(struct kvm_vcpu *vcpu)
10683 {
10684         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10685         struct pi_desc old, new;
10686         unsigned int dest;
10687         unsigned long flags;
10688
10689         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10690                 !irq_remapping_cap(IRQ_POSTING_CAP))
10691                 return;
10692
10693         do {
10694                 old.control = new.control = pi_desc->control;
10695
10696                 dest = cpu_physical_id(vcpu->cpu);
10697
10698                 if (x2apic_enabled())
10699                         new.ndst = dest;
10700                 else
10701                         new.ndst = (dest << 8) & 0xFF00;
10702
10703                 /* Allow posting non-urgent interrupts */
10704                 new.sn = 0;
10705
10706                 /* set 'NV' to 'notification vector' */
10707                 new.nv = POSTED_INTR_VECTOR;
10708         } while (cmpxchg(&pi_desc->control, old.control,
10709                         new.control) != old.control);
10710
10711         if(vcpu->pre_pcpu != -1) {
10712                 spin_lock_irqsave(
10713                         &per_cpu(blocked_vcpu_on_cpu_lock,
10714                         vcpu->pre_pcpu), flags);
10715                 list_del(&vcpu->blocked_vcpu_list);
10716                 spin_unlock_irqrestore(
10717                         &per_cpu(blocked_vcpu_on_cpu_lock,
10718                         vcpu->pre_pcpu), flags);
10719                 vcpu->pre_pcpu = -1;
10720         }
10721 }
10722
10723 /*
10724  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10725  *
10726  * @kvm: kvm
10727  * @host_irq: host irq of the interrupt
10728  * @guest_irq: gsi of the interrupt
10729  * @set: set or unset PI
10730  * returns 0 on success, < 0 on failure
10731  */
10732 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10733                               uint32_t guest_irq, bool set)
10734 {
10735         struct kvm_kernel_irq_routing_entry *e;
10736         struct kvm_irq_routing_table *irq_rt;
10737         struct kvm_lapic_irq irq;
10738         struct kvm_vcpu *vcpu;
10739         struct vcpu_data vcpu_info;
10740         int idx, ret = -EINVAL;
10741
10742         if (!kvm_arch_has_assigned_device(kvm) ||
10743                 !irq_remapping_cap(IRQ_POSTING_CAP))
10744                 return 0;
10745
10746         idx = srcu_read_lock(&kvm->irq_srcu);
10747         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10748         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10749
10750         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10751                 if (e->type != KVM_IRQ_ROUTING_MSI)
10752                         continue;
10753                 /*
10754                  * VT-d PI cannot support posting multicast/broadcast
10755                  * interrupts to a vCPU, we still use interrupt remapping
10756                  * for these kind of interrupts.
10757                  *
10758                  * For lowest-priority interrupts, we only support
10759                  * those with single CPU as the destination, e.g. user
10760                  * configures the interrupts via /proc/irq or uses
10761                  * irqbalance to make the interrupts single-CPU.
10762                  *
10763                  * We will support full lowest-priority interrupt later.
10764                  */
10765
10766                 kvm_set_msi_irq(e, &irq);
10767                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10768                         continue;
10769
10770                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10771                 vcpu_info.vector = irq.vector;
10772
10773                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10774                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10775
10776                 if (set)
10777                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10778                 else {
10779                         /* suppress notification event before unposting */
10780                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10781                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10782                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10783                 }
10784
10785                 if (ret < 0) {
10786                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10787                                         __func__);
10788                         goto out;
10789                 }
10790         }
10791
10792         ret = 0;
10793 out:
10794         srcu_read_unlock(&kvm->irq_srcu, idx);
10795         return ret;
10796 }
10797
10798 static struct kvm_x86_ops vmx_x86_ops = {
10799         .cpu_has_kvm_support = cpu_has_kvm_support,
10800         .disabled_by_bios = vmx_disabled_by_bios,
10801         .hardware_setup = hardware_setup,
10802         .hardware_unsetup = hardware_unsetup,
10803         .check_processor_compatibility = vmx_check_processor_compat,
10804         .hardware_enable = hardware_enable,
10805         .hardware_disable = hardware_disable,
10806         .cpu_has_accelerated_tpr = report_flexpriority,
10807         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10808
10809         .vcpu_create = vmx_create_vcpu,
10810         .vcpu_free = vmx_free_vcpu,
10811         .vcpu_reset = vmx_vcpu_reset,
10812
10813         .prepare_guest_switch = vmx_save_host_state,
10814         .vcpu_load = vmx_vcpu_load,
10815         .vcpu_put = vmx_vcpu_put,
10816
10817         .update_bp_intercept = update_exception_bitmap,
10818         .get_msr = vmx_get_msr,
10819         .set_msr = vmx_set_msr,
10820         .get_segment_base = vmx_get_segment_base,
10821         .get_segment = vmx_get_segment,
10822         .set_segment = vmx_set_segment,
10823         .get_cpl = vmx_get_cpl,
10824         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10825         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10826         .decache_cr3 = vmx_decache_cr3,
10827         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10828         .set_cr0 = vmx_set_cr0,
10829         .set_cr3 = vmx_set_cr3,
10830         .set_cr4 = vmx_set_cr4,
10831         .set_efer = vmx_set_efer,
10832         .get_idt = vmx_get_idt,
10833         .set_idt = vmx_set_idt,
10834         .get_gdt = vmx_get_gdt,
10835         .set_gdt = vmx_set_gdt,
10836         .get_dr6 = vmx_get_dr6,
10837         .set_dr6 = vmx_set_dr6,
10838         .set_dr7 = vmx_set_dr7,
10839         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10840         .cache_reg = vmx_cache_reg,
10841         .get_rflags = vmx_get_rflags,
10842         .set_rflags = vmx_set_rflags,
10843         .fpu_activate = vmx_fpu_activate,
10844         .fpu_deactivate = vmx_fpu_deactivate,
10845
10846         .tlb_flush = vmx_flush_tlb,
10847
10848         .run = vmx_vcpu_run,
10849         .handle_exit = vmx_handle_exit,
10850         .skip_emulated_instruction = skip_emulated_instruction,
10851         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10852         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10853         .patch_hypercall = vmx_patch_hypercall,
10854         .set_irq = vmx_inject_irq,
10855         .set_nmi = vmx_inject_nmi,
10856         .queue_exception = vmx_queue_exception,
10857         .cancel_injection = vmx_cancel_injection,
10858         .interrupt_allowed = vmx_interrupt_allowed,
10859         .nmi_allowed = vmx_nmi_allowed,
10860         .get_nmi_mask = vmx_get_nmi_mask,
10861         .set_nmi_mask = vmx_set_nmi_mask,
10862         .enable_nmi_window = enable_nmi_window,
10863         .enable_irq_window = enable_irq_window,
10864         .update_cr8_intercept = update_cr8_intercept,
10865         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10866         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10867         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10868         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10869         .hwapic_irr_update = vmx_hwapic_irr_update,
10870         .hwapic_isr_update = vmx_hwapic_isr_update,
10871         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10872         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10873
10874         .set_tss_addr = vmx_set_tss_addr,
10875         .get_tdp_level = get_ept_level,
10876         .get_mt_mask = vmx_get_mt_mask,
10877
10878         .get_exit_info = vmx_get_exit_info,
10879
10880         .get_lpage_level = vmx_get_lpage_level,
10881
10882         .cpuid_update = vmx_cpuid_update,
10883
10884         .rdtscp_supported = vmx_rdtscp_supported,
10885         .invpcid_supported = vmx_invpcid_supported,
10886
10887         .set_supported_cpuid = vmx_set_supported_cpuid,
10888
10889         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10890
10891         .read_tsc_offset = vmx_read_tsc_offset,
10892         .write_tsc_offset = vmx_write_tsc_offset,
10893         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10894         .read_l1_tsc = vmx_read_l1_tsc,
10895
10896         .set_tdp_cr3 = vmx_set_cr3,
10897
10898         .check_intercept = vmx_check_intercept,
10899         .handle_external_intr = vmx_handle_external_intr,
10900         .mpx_supported = vmx_mpx_supported,
10901         .xsaves_supported = vmx_xsaves_supported,
10902
10903         .check_nested_events = vmx_check_nested_events,
10904
10905         .sched_in = vmx_sched_in,
10906
10907         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10908         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10909         .flush_log_dirty = vmx_flush_log_dirty,
10910         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10911
10912         .pre_block = vmx_pre_block,
10913         .post_block = vmx_post_block,
10914
10915         .pmu_ops = &intel_pmu_ops,
10916
10917         .update_pi_irte = vmx_update_pi_irte,
10918 };
10919
10920 static int __init vmx_init(void)
10921 {
10922         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10923                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10924         if (r)
10925                 return r;
10926
10927 #ifdef CONFIG_KEXEC_CORE
10928         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10929                            crash_vmclear_local_loaded_vmcss);
10930 #endif
10931
10932         return 0;
10933 }
10934
10935 static void __exit vmx_exit(void)
10936 {
10937 #ifdef CONFIG_KEXEC_CORE
10938         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10939         synchronize_rcu();
10940 #endif
10941
10942         kvm_exit();
10943 }
10944
10945 module_init(vmx_init)
10946 module_exit(vmx_exit)