arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 114 #define KVM_VM_CR0_ALWAYS_ON                                            \
 115         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 116 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 117         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 118          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 119
 120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 122
 123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 124
 125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 126
 127 /*
 128  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 129  * ple_gap:    upper bound on the amount of time between two successive
 130  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 131  *             According to test, this time is usually smaller than 128 cycles.
 132  * ple_window: upper bound on the amount of time a guest is allowed to execute
 133  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 134  *             less than 2^12 cycles
 135  * Time is measured based on a counter that runs at the same rate as the TSC,
 136  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 137  */
 138 #define KVM_VMX_DEFAULT_PLE_GAP           128
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 143                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 144
 145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 146 module_param(ple_gap, int, S_IRUGO);
 147
 148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 149 module_param(ple_window, int, S_IRUGO);
 150
 151 /* Default doubles per-vcpu window every exit. */
 152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 153 module_param(ple_window_grow, int, S_IRUGO);
 154
 155 /* Default resets per-vcpu window every exit to ple_window. */
 156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 157 module_param(ple_window_shrink, int, S_IRUGO);
 158
 159 /* Default is to compute the maximum so we can never overflow. */
 160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 161 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 module_param(ple_window_max, int, S_IRUGO);
 163
 164 extern const ulong vmx_return;
 165
 166 #define NR_AUTOLOAD_MSRS 8
 167 #define VMCS02_POOL_SIZE 1
 168
 169 struct vmcs {
 170         u32 revision_id;
 171         u32 abort;
 172         char data[0];
 173 };
 174
 175 /*
 176  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 177  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 178  * loaded on this CPU (so we can clear them if the CPU goes down).
 179  */
 180 struct loaded_vmcs {
 181         struct vmcs *vmcs;
 182         int cpu;
 183         int launched;
 184         struct list_head loaded_vmcss_on_cpu_link;
 185 };
 186
 187 struct shared_msr_entry {
 188         unsigned index;
 189         u64 data;
 190         u64 mask;
 191 };
 192
 193 /*
 194  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 195  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 196  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 197  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 198  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 199  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 200  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 201  * underlying hardware which will be used to run L2.
 202  * This structure is packed to ensure that its layout is identical across
 203  * machines (necessary for live migration).
 204  * If there are changes in this struct, VMCS12_REVISION must be changed.
 205  */
 206 typedef u64 natural_width;
 207 struct __packed vmcs12 {
 208         /* According to the Intel spec, a VMCS region must start with the
 209          * following two fields. Then follow implementation-specific data.
 210          */
 211         u32 revision_id;
 212         u32 abort;
 213
 214         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 215         u32 padding[7]; /* room for future expansion */
 216
 217         u64 io_bitmap_a;
 218         u64 io_bitmap_b;
 219         u64 msr_bitmap;
 220         u64 vm_exit_msr_store_addr;
 221         u64 vm_exit_msr_load_addr;
 222         u64 vm_entry_msr_load_addr;
 223         u64 tsc_offset;
 224         u64 virtual_apic_page_addr;
 225         u64 apic_access_addr;
 226         u64 posted_intr_desc_addr;
 227         u64 ept_pointer;
 228         u64 eoi_exit_bitmap0;
 229         u64 eoi_exit_bitmap1;
 230         u64 eoi_exit_bitmap2;
 231         u64 eoi_exit_bitmap3;
 232         u64 xss_exit_bitmap;
 233         u64 guest_physical_address;
 234         u64 vmcs_link_pointer;
 235         u64 guest_ia32_debugctl;
 236         u64 guest_ia32_pat;
 237         u64 guest_ia32_efer;
 238         u64 guest_ia32_perf_global_ctrl;
 239         u64 guest_pdptr0;
 240         u64 guest_pdptr1;
 241         u64 guest_pdptr2;
 242         u64 guest_pdptr3;
 243         u64 guest_bndcfgs;
 244         u64 host_ia32_pat;
 245         u64 host_ia32_efer;
 246         u64 host_ia32_perf_global_ctrl;
 247         u64 padding64[8]; /* room for future expansion */
 248         /*
 249          * To allow migration of L1 (complete with its L2 guests) between
 250          * machines of different natural widths (32 or 64 bit), we cannot have
 251          * unsigned long fields with no explict size. We use u64 (aliased
 252          * natural_width) instead. Luckily, x86 is little-endian.
 253          */
 254         natural_width cr0_guest_host_mask;
 255         natural_width cr4_guest_host_mask;
 256         natural_width cr0_read_shadow;
 257         natural_width cr4_read_shadow;
 258         natural_width cr3_target_value0;
 259         natural_width cr3_target_value1;
 260         natural_width cr3_target_value2;
 261         natural_width cr3_target_value3;
 262         natural_width exit_qualification;
 263         natural_width guest_linear_address;
 264         natural_width guest_cr0;
 265         natural_width guest_cr3;
 266         natural_width guest_cr4;
 267         natural_width guest_es_base;
 268         natural_width guest_cs_base;
 269         natural_width guest_ss_base;
 270         natural_width guest_ds_base;
 271         natural_width guest_fs_base;
 272         natural_width guest_gs_base;
 273         natural_width guest_ldtr_base;
 274         natural_width guest_tr_base;
 275         natural_width guest_gdtr_base;
 276         natural_width guest_idtr_base;
 277         natural_width guest_dr7;
 278         natural_width guest_rsp;
 279         natural_width guest_rip;
 280         natural_width guest_rflags;
 281         natural_width guest_pending_dbg_exceptions;
 282         natural_width guest_sysenter_esp;
 283         natural_width guest_sysenter_eip;
 284         natural_width host_cr0;
 285         natural_width host_cr3;
 286         natural_width host_cr4;
 287         natural_width host_fs_base;
 288         natural_width host_gs_base;
 289         natural_width host_tr_base;
 290         natural_width host_gdtr_base;
 291         natural_width host_idtr_base;
 292         natural_width host_ia32_sysenter_esp;
 293         natural_width host_ia32_sysenter_eip;
 294         natural_width host_rsp;
 295         natural_width host_rip;
 296         natural_width paddingl[8]; /* room for future expansion */
 297         u32 pin_based_vm_exec_control;
 298         u32 cpu_based_vm_exec_control;
 299         u32 exception_bitmap;
 300         u32 page_fault_error_code_mask;
 301         u32 page_fault_error_code_match;
 302         u32 cr3_target_count;
 303         u32 vm_exit_controls;
 304         u32 vm_exit_msr_store_count;
 305         u32 vm_exit_msr_load_count;
 306         u32 vm_entry_controls;
 307         u32 vm_entry_msr_load_count;
 308         u32 vm_entry_intr_info_field;
 309         u32 vm_entry_exception_error_code;
 310         u32 vm_entry_instruction_len;
 311         u32 tpr_threshold;
 312         u32 secondary_vm_exec_control;
 313         u32 vm_instruction_error;
 314         u32 vm_exit_reason;
 315         u32 vm_exit_intr_info;
 316         u32 vm_exit_intr_error_code;
 317         u32 idt_vectoring_info_field;
 318         u32 idt_vectoring_error_code;
 319         u32 vm_exit_instruction_len;
 320         u32 vmx_instruction_info;
 321         u32 guest_es_limit;
 322         u32 guest_cs_limit;
 323         u32 guest_ss_limit;
 324         u32 guest_ds_limit;
 325         u32 guest_fs_limit;
 326         u32 guest_gs_limit;
 327         u32 guest_ldtr_limit;
 328         u32 guest_tr_limit;
 329         u32 guest_gdtr_limit;
 330         u32 guest_idtr_limit;
 331         u32 guest_es_ar_bytes;
 332         u32 guest_cs_ar_bytes;
 333         u32 guest_ss_ar_bytes;
 334         u32 guest_ds_ar_bytes;
 335         u32 guest_fs_ar_bytes;
 336         u32 guest_gs_ar_bytes;
 337         u32 guest_ldtr_ar_bytes;
 338         u32 guest_tr_ar_bytes;
 339         u32 guest_interruptibility_info;
 340         u32 guest_activity_state;
 341         u32 guest_sysenter_cs;
 342         u32 host_ia32_sysenter_cs;
 343         u32 vmx_preemption_timer_value;
 344         u32 padding32[7]; /* room for future expansion */
 345         u16 virtual_processor_id;
 346         u16 posted_intr_nv;
 347         u16 guest_es_selector;
 348         u16 guest_cs_selector;
 349         u16 guest_ss_selector;
 350         u16 guest_ds_selector;
 351         u16 guest_fs_selector;
 352         u16 guest_gs_selector;
 353         u16 guest_ldtr_selector;
 354         u16 guest_tr_selector;
 355         u16 guest_intr_status;
 356         u16 host_es_selector;
 357         u16 host_cs_selector;
 358         u16 host_ss_selector;
 359         u16 host_ds_selector;
 360         u16 host_fs_selector;
 361         u16 host_gs_selector;
 362         u16 host_tr_selector;
 363 };
 364
 365 /*
 366  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 367  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 368  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 369  */
 370 #define VMCS12_REVISION 0x11e57ed0
 371
 372 /*
 373  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 374  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 375  * current implementation, 4K are reserved to avoid future complications.
 376  */
 377 #define VMCS12_SIZE 0x1000
 378
 379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 380 struct vmcs02_list {
 381         struct list_head list;
 382         gpa_t vmptr;
 383         struct loaded_vmcs vmcs02;
 384 };
 385
 386 /*
 387  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 388  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 389  */
 390 struct nested_vmx {
 391         /* Has the level1 guest done vmxon? */
 392         bool vmxon;
 393         gpa_t vmxon_ptr;
 394
 395         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 396         gpa_t current_vmptr;
 397         /* The host-usable pointer to the above */
 398         struct page *current_vmcs12_page;
 399         struct vmcs12 *current_vmcs12;
 400         struct vmcs *current_shadow_vmcs;
 401         /*
 402          * Indicates if the shadow vmcs must be updated with the
 403          * data hold by vmcs12
 404          */
 405         bool sync_shadow_vmcs;
 406
 407         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 408         struct list_head vmcs02_pool;
 409         int vmcs02_num;
 410         u64 vmcs01_tsc_offset;
 411         bool change_vmcs01_virtual_x2apic_mode;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601 };
 602
 603 enum segment_cache_field {
 604         SEG_FIELD_SEL = 0,
 605         SEG_FIELD_BASE = 1,
 606         SEG_FIELD_LIMIT = 2,
 607         SEG_FIELD_AR = 3,
 608
 609         SEG_FIELD_NR = 4
 610 };
 611
 612 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 613 {
 614         return container_of(vcpu, struct vcpu_vmx, vcpu);
 615 }
 616
 617 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 618 {
 619         return &(to_vmx(vcpu)->pi_desc);
 620 }
 621
 622 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 623 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 624 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 625                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 626
 627
 628 static unsigned long shadow_read_only_fields[] = {
 629         /*
 630          * We do NOT shadow fields that are modified when L0
 631          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 632          * VMXON...) executed by L1.
 633          * For example, VM_INSTRUCTION_ERROR is read
 634          * by L1 if a vmx instruction fails (part of the error path).
 635          * Note the code assumes this logic. If for some reason
 636          * we start shadowing these fields then we need to
 637          * force a shadow sync when L0 emulates vmx instructions
 638          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 639          * by nested_vmx_failValid)
 640          */
 641         VM_EXIT_REASON,
 642         VM_EXIT_INTR_INFO,
 643         VM_EXIT_INSTRUCTION_LEN,
 644         IDT_VECTORING_INFO_FIELD,
 645         IDT_VECTORING_ERROR_CODE,
 646         VM_EXIT_INTR_ERROR_CODE,
 647         EXIT_QUALIFICATION,
 648         GUEST_LINEAR_ADDRESS,
 649         GUEST_PHYSICAL_ADDRESS
 650 };
 651 static int max_shadow_read_only_fields =
 652         ARRAY_SIZE(shadow_read_only_fields);
 653
 654 static unsigned long shadow_read_write_fields[] = {
 655         TPR_THRESHOLD,
 656         GUEST_RIP,
 657         GUEST_RSP,
 658         GUEST_CR0,
 659         GUEST_CR3,
 660         GUEST_CR4,
 661         GUEST_INTERRUPTIBILITY_INFO,
 662         GUEST_RFLAGS,
 663         GUEST_CS_SELECTOR,
 664         GUEST_CS_AR_BYTES,
 665         GUEST_CS_LIMIT,
 666         GUEST_CS_BASE,
 667         GUEST_ES_BASE,
 668         GUEST_BNDCFGS,
 669         CR0_GUEST_HOST_MASK,
 670         CR0_READ_SHADOW,
 671         CR4_READ_SHADOW,
 672         TSC_OFFSET,
 673         EXCEPTION_BITMAP,
 674         CPU_BASED_VM_EXEC_CONTROL,
 675         VM_ENTRY_EXCEPTION_ERROR_CODE,
 676         VM_ENTRY_INTR_INFO_FIELD,
 677         VM_ENTRY_INSTRUCTION_LEN,
 678         VM_ENTRY_EXCEPTION_ERROR_CODE,
 679         HOST_FS_BASE,
 680         HOST_GS_BASE,
 681         HOST_FS_SELECTOR,
 682         HOST_GS_SELECTOR
 683 };
 684 static int max_shadow_read_write_fields =
 685         ARRAY_SIZE(shadow_read_write_fields);
 686
 687 static const unsigned short vmcs_field_to_offset_table[] = {
 688         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 689         FIELD(POSTED_INTR_NV, posted_intr_nv),
 690         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 691         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 692         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 693         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 694         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 695         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 696         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 697         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 698         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 699         FIELD(HOST_ES_SELECTOR, host_es_selector),
 700         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 701         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 702         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 703         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 704         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 705         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 706         FIELD64(IO_BITMAP_A, io_bitmap_a),
 707         FIELD64(IO_BITMAP_B, io_bitmap_b),
 708         FIELD64(MSR_BITMAP, msr_bitmap),
 709         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 710         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 711         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 712         FIELD64(TSC_OFFSET, tsc_offset),
 713         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 714         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 715         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 716         FIELD64(EPT_POINTER, ept_pointer),
 717         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 718         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 719         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 720         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 721         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 722         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 723         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 724         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 725         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 726         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 727         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 728         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 729         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 730         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 731         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 732         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 733         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 734         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 735         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 736         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 737         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 738         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 740         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 741         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 742         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 743         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 744         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 745         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 746         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 747         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 748         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 749         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 750         FIELD(TPR_THRESHOLD, tpr_threshold),
 751         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 752         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 753         FIELD(VM_EXIT_REASON, vm_exit_reason),
 754         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 755         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 756         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 757         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 758         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 759         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 760         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 761         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 762         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 763         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 764         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 765         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 766         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 767         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 768         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 769         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 770         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 771         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 772         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 773         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 774         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 775         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 776         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 777         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 778         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 779         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 780         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 781         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 782         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 783         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 784         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 785         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 786         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 787         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 788         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 789         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 790         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 791         FIELD(EXIT_QUALIFICATION, exit_qualification),
 792         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 793         FIELD(GUEST_CR0, guest_cr0),
 794         FIELD(GUEST_CR3, guest_cr3),
 795         FIELD(GUEST_CR4, guest_cr4),
 796         FIELD(GUEST_ES_BASE, guest_es_base),
 797         FIELD(GUEST_CS_BASE, guest_cs_base),
 798         FIELD(GUEST_SS_BASE, guest_ss_base),
 799         FIELD(GUEST_DS_BASE, guest_ds_base),
 800         FIELD(GUEST_FS_BASE, guest_fs_base),
 801         FIELD(GUEST_GS_BASE, guest_gs_base),
 802         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 803         FIELD(GUEST_TR_BASE, guest_tr_base),
 804         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 805         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 806         FIELD(GUEST_DR7, guest_dr7),
 807         FIELD(GUEST_RSP, guest_rsp),
 808         FIELD(GUEST_RIP, guest_rip),
 809         FIELD(GUEST_RFLAGS, guest_rflags),
 810         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 811         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 812         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 813         FIELD(HOST_CR0, host_cr0),
 814         FIELD(HOST_CR3, host_cr3),
 815         FIELD(HOST_CR4, host_cr4),
 816         FIELD(HOST_FS_BASE, host_fs_base),
 817         FIELD(HOST_GS_BASE, host_gs_base),
 818         FIELD(HOST_TR_BASE, host_tr_base),
 819         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 820         FIELD(HOST_IDTR_BASE, host_idtr_base),
 821         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 822         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 823         FIELD(HOST_RSP, host_rsp),
 824         FIELD(HOST_RIP, host_rip),
 825 };
 826
 827 static inline short vmcs_field_to_offset(unsigned long field)
 828 {
 829         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 830
 831         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 832             vmcs_field_to_offset_table[field] == 0)
 833                 return -ENOENT;
 834
 835         return vmcs_field_to_offset_table[field];
 836 }
 837
 838 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 839 {
 840         return to_vmx(vcpu)->nested.current_vmcs12;
 841 }
 842
 843 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 844 {
 845         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 846         if (is_error_page(page))
 847                 return NULL;
 848
 849         return page;
 850 }
 851
 852 static void nested_release_page(struct page *page)
 853 {
 854         kvm_release_page_dirty(page);
 855 }
 856
 857 static void nested_release_page_clean(struct page *page)
 858 {
 859         kvm_release_page_clean(page);
 860 }
 861
 862 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 863 static u64 construct_eptp(unsigned long root_hpa);
 864 static void kvm_cpu_vmxon(u64 addr);
 865 static void kvm_cpu_vmxoff(void);
 866 static bool vmx_xsaves_supported(void);
 867 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 869 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 872                             struct kvm_segment *var, int seg);
 873 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 874 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 875 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 876 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 877 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 878 static int alloc_identity_pagetable(struct kvm *kvm);
 879
 880 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 881 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 882 /*
 883  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 884  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 885  */
 886 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 887 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 888
 889 /*
 890  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 891  * can find which vCPU should be waken up.
 892  */
 893 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 894 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 895
 896 static unsigned long *vmx_io_bitmap_a;
 897 static unsigned long *vmx_io_bitmap_b;
 898 static unsigned long *vmx_msr_bitmap_legacy;
 899 static unsigned long *vmx_msr_bitmap_longmode;
 900 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 901 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 902 static unsigned long *vmx_msr_bitmap_nested;
 903 static unsigned long *vmx_vmread_bitmap;
 904 static unsigned long *vmx_vmwrite_bitmap;
 905
 906 static bool cpu_has_load_ia32_efer;
 907 static bool cpu_has_load_perf_global_ctrl;
 908
 909 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 910 static DEFINE_SPINLOCK(vmx_vpid_lock);
 911
 912 static struct vmcs_config {
 913         int size;
 914         int order;
 915         u32 revision_id;
 916         u32 pin_based_exec_ctrl;
 917         u32 cpu_based_exec_ctrl;
 918         u32 cpu_based_2nd_exec_ctrl;
 919         u32 vmexit_ctrl;
 920         u32 vmentry_ctrl;
 921 } vmcs_config;
 922
 923 static struct vmx_capability {
 924         u32 ept;
 925         u32 vpid;
 926 } vmx_capability;
 927
 928 #define VMX_SEGMENT_FIELD(seg)                                  \
 929         [VCPU_SREG_##seg] = {                                   \
 930                 .selector = GUEST_##seg##_SELECTOR,             \
 931                 .base = GUEST_##seg##_BASE,                     \
 932                 .limit = GUEST_##seg##_LIMIT,                   \
 933                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 934         }
 935
 936 static const struct kvm_vmx_segment_field {
 937         unsigned selector;
 938         unsigned base;
 939         unsigned limit;
 940         unsigned ar_bytes;
 941 } kvm_vmx_segment_fields[] = {
 942         VMX_SEGMENT_FIELD(CS),
 943         VMX_SEGMENT_FIELD(DS),
 944         VMX_SEGMENT_FIELD(ES),
 945         VMX_SEGMENT_FIELD(FS),
 946         VMX_SEGMENT_FIELD(GS),
 947         VMX_SEGMENT_FIELD(SS),
 948         VMX_SEGMENT_FIELD(TR),
 949         VMX_SEGMENT_FIELD(LDTR),
 950 };
 951
 952 static u64 host_efer;
 953
 954 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 955
 956 /*
 957  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 958  * away by decrementing the array size.
 959  */
 960 static const u32 vmx_msr_index[] = {
 961 #ifdef CONFIG_X86_64
 962         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 963 #endif
 964         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 965 };
 966
 967 static inline bool is_page_fault(u32 intr_info)
 968 {
 969         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 970                              INTR_INFO_VALID_MASK)) ==
 971                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 972 }
 973
 974 static inline bool is_no_device(u32 intr_info)
 975 {
 976         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 977                              INTR_INFO_VALID_MASK)) ==
 978                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 979 }
 980
 981 static inline bool is_invalid_opcode(u32 intr_info)
 982 {
 983         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 984                              INTR_INFO_VALID_MASK)) ==
 985                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 986 }
 987
 988 static inline bool is_external_interrupt(u32 intr_info)
 989 {
 990         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 991                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 992 }
 993
 994 static inline bool is_machine_check(u32 intr_info)
 995 {
 996         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 997                              INTR_INFO_VALID_MASK)) ==
 998                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 999 }
1000
1001 static inline bool cpu_has_vmx_msr_bitmap(void)
1002 {
1003         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1004 }
1005
1006 static inline bool cpu_has_vmx_tpr_shadow(void)
1007 {
1008         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1009 }
1010
1011 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1012 {
1013         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1014 }
1015
1016 static inline bool cpu_has_secondary_exec_ctrls(void)
1017 {
1018         return vmcs_config.cpu_based_exec_ctrl &
1019                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1020 }
1021
1022 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1023 {
1024         return vmcs_config.cpu_based_2nd_exec_ctrl &
1025                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1026 }
1027
1028 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1029 {
1030         return vmcs_config.cpu_based_2nd_exec_ctrl &
1031                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1032 }
1033
1034 static inline bool cpu_has_vmx_apic_register_virt(void)
1035 {
1036         return vmcs_config.cpu_based_2nd_exec_ctrl &
1037                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1038 }
1039
1040 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1041 {
1042         return vmcs_config.cpu_based_2nd_exec_ctrl &
1043                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1044 }
1045
1046 static inline bool cpu_has_vmx_posted_intr(void)
1047 {
1048         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1049                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1050 }
1051
1052 static inline bool cpu_has_vmx_apicv(void)
1053 {
1054         return cpu_has_vmx_apic_register_virt() &&
1055                 cpu_has_vmx_virtual_intr_delivery() &&
1056                 cpu_has_vmx_posted_intr();
1057 }
1058
1059 static inline bool cpu_has_vmx_flexpriority(void)
1060 {
1061         return cpu_has_vmx_tpr_shadow() &&
1062                 cpu_has_vmx_virtualize_apic_accesses();
1063 }
1064
1065 static inline bool cpu_has_vmx_ept_execute_only(void)
1066 {
1067         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1068 }
1069
1070 static inline bool cpu_has_vmx_ept_2m_page(void)
1071 {
1072         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1073 }
1074
1075 static inline bool cpu_has_vmx_ept_1g_page(void)
1076 {
1077         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1078 }
1079
1080 static inline bool cpu_has_vmx_ept_4levels(void)
1081 {
1082         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1083 }
1084
1085 static inline bool cpu_has_vmx_ept_ad_bits(void)
1086 {
1087         return vmx_capability.ept & VMX_EPT_AD_BIT;
1088 }
1089
1090 static inline bool cpu_has_vmx_invept_context(void)
1091 {
1092         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1093 }
1094
1095 static inline bool cpu_has_vmx_invept_global(void)
1096 {
1097         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1098 }
1099
1100 static inline bool cpu_has_vmx_invvpid_single(void)
1101 {
1102         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1103 }
1104
1105 static inline bool cpu_has_vmx_invvpid_global(void)
1106 {
1107         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1108 }
1109
1110 static inline bool cpu_has_vmx_ept(void)
1111 {
1112         return vmcs_config.cpu_based_2nd_exec_ctrl &
1113                 SECONDARY_EXEC_ENABLE_EPT;
1114 }
1115
1116 static inline bool cpu_has_vmx_unrestricted_guest(void)
1117 {
1118         return vmcs_config.cpu_based_2nd_exec_ctrl &
1119                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1120 }
1121
1122 static inline bool cpu_has_vmx_ple(void)
1123 {
1124         return vmcs_config.cpu_based_2nd_exec_ctrl &
1125                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1126 }
1127
1128 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1129 {
1130         return flexpriority_enabled && lapic_in_kernel(vcpu);
1131 }
1132
1133 static inline bool cpu_has_vmx_vpid(void)
1134 {
1135         return vmcs_config.cpu_based_2nd_exec_ctrl &
1136                 SECONDARY_EXEC_ENABLE_VPID;
1137 }
1138
1139 static inline bool cpu_has_vmx_rdtscp(void)
1140 {
1141         return vmcs_config.cpu_based_2nd_exec_ctrl &
1142                 SECONDARY_EXEC_RDTSCP;
1143 }
1144
1145 static inline bool cpu_has_vmx_invpcid(void)
1146 {
1147         return vmcs_config.cpu_based_2nd_exec_ctrl &
1148                 SECONDARY_EXEC_ENABLE_INVPCID;
1149 }
1150
1151 static inline bool cpu_has_virtual_nmis(void)
1152 {
1153         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1154 }
1155
1156 static inline bool cpu_has_vmx_wbinvd_exit(void)
1157 {
1158         return vmcs_config.cpu_based_2nd_exec_ctrl &
1159                 SECONDARY_EXEC_WBINVD_EXITING;
1160 }
1161
1162 static inline bool cpu_has_vmx_shadow_vmcs(void)
1163 {
1164         u64 vmx_msr;
1165         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1166         /* check if the cpu supports writing r/o exit information fields */
1167         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1168                 return false;
1169
1170         return vmcs_config.cpu_based_2nd_exec_ctrl &
1171                 SECONDARY_EXEC_SHADOW_VMCS;
1172 }
1173
1174 static inline bool cpu_has_vmx_pml(void)
1175 {
1176         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1177 }
1178
1179 static inline bool cpu_has_vmx_tsc_scaling(void)
1180 {
1181         return vmcs_config.cpu_based_2nd_exec_ctrl &
1182                 SECONDARY_EXEC_TSC_SCALING;
1183 }
1184
1185 static inline bool report_flexpriority(void)
1186 {
1187         return flexpriority_enabled;
1188 }
1189
1190 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1191 {
1192         return vmcs12->cpu_based_vm_exec_control & bit;
1193 }
1194
1195 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1196 {
1197         return (vmcs12->cpu_based_vm_exec_control &
1198                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1199                 (vmcs12->secondary_vm_exec_control & bit);
1200 }
1201
1202 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1203 {
1204         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1205 }
1206
1207 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1208 {
1209         return vmcs12->pin_based_vm_exec_control &
1210                 PIN_BASED_VMX_PREEMPTION_TIMER;
1211 }
1212
1213 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1214 {
1215         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1216 }
1217
1218 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1219 {
1220         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1221                 vmx_xsaves_supported();
1222 }
1223
1224 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1225 {
1226         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1227 }
1228
1229 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1230 {
1231         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1232 }
1233
1234 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1235 {
1236         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1237 }
1238
1239 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1240 {
1241         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1242 }
1243
1244 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1245 {
1246         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1247 }
1248
1249 static inline bool is_nmi(u32 intr_info)
1250 {
1251         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1252                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1253 }
1254
1255 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1256                               u32 exit_intr_info,
1257                               unsigned long exit_qualification);
1258 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1259                         struct vmcs12 *vmcs12,
1260                         u32 reason, unsigned long qualification);
1261
1262 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1263 {
1264         int i;
1265
1266         for (i = 0; i < vmx->nmsrs; ++i)
1267                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1268                         return i;
1269         return -1;
1270 }
1271
1272 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1273 {
1274     struct {
1275         u64 vpid : 16;
1276         u64 rsvd : 48;
1277         u64 gva;
1278     } operand = { vpid, 0, gva };
1279
1280     asm volatile (__ex(ASM_VMX_INVVPID)
1281                   /* CF==1 or ZF==1 --> rc = -1 */
1282                   "; ja 1f ; ud2 ; 1:"
1283                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1284 }
1285
1286 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1287 {
1288         struct {
1289                 u64 eptp, gpa;
1290         } operand = {eptp, gpa};
1291
1292         asm volatile (__ex(ASM_VMX_INVEPT)
1293                         /* CF==1 or ZF==1 --> rc = -1 */
1294                         "; ja 1f ; ud2 ; 1:\n"
1295                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1296 }
1297
1298 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1299 {
1300         int i;
1301
1302         i = __find_msr_index(vmx, msr);
1303         if (i >= 0)
1304                 return &vmx->guest_msrs[i];
1305         return NULL;
1306 }
1307
1308 static void vmcs_clear(struct vmcs *vmcs)
1309 {
1310         u64 phys_addr = __pa(vmcs);
1311         u8 error;
1312
1313         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1314                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1315                       : "cc", "memory");
1316         if (error)
1317                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1318                        vmcs, phys_addr);
1319 }
1320
1321 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1322 {
1323         vmcs_clear(loaded_vmcs->vmcs);
1324         loaded_vmcs->cpu = -1;
1325         loaded_vmcs->launched = 0;
1326 }
1327
1328 static void vmcs_load(struct vmcs *vmcs)
1329 {
1330         u64 phys_addr = __pa(vmcs);
1331         u8 error;
1332
1333         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1334                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1335                         : "cc", "memory");
1336         if (error)
1337                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1338                        vmcs, phys_addr);
1339 }
1340
1341 #ifdef CONFIG_KEXEC_CORE
1342 /*
1343  * This bitmap is used to indicate whether the vmclear
1344  * operation is enabled on all cpus. All disabled by
1345  * default.
1346  */
1347 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1348
1349 static inline void crash_enable_local_vmclear(int cpu)
1350 {
1351         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1352 }
1353
1354 static inline void crash_disable_local_vmclear(int cpu)
1355 {
1356         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1357 }
1358
1359 static inline int crash_local_vmclear_enabled(int cpu)
1360 {
1361         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1362 }
1363
1364 static void crash_vmclear_local_loaded_vmcss(void)
1365 {
1366         int cpu = raw_smp_processor_id();
1367         struct loaded_vmcs *v;
1368
1369         if (!crash_local_vmclear_enabled(cpu))
1370                 return;
1371
1372         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1373                             loaded_vmcss_on_cpu_link)
1374                 vmcs_clear(v->vmcs);
1375 }
1376 #else
1377 static inline void crash_enable_local_vmclear(int cpu) { }
1378 static inline void crash_disable_local_vmclear(int cpu) { }
1379 #endif /* CONFIG_KEXEC_CORE */
1380
1381 static void __loaded_vmcs_clear(void *arg)
1382 {
1383         struct loaded_vmcs *loaded_vmcs = arg;
1384         int cpu = raw_smp_processor_id();
1385
1386         if (loaded_vmcs->cpu != cpu)
1387                 return; /* vcpu migration can race with cpu offline */
1388         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1389                 per_cpu(current_vmcs, cpu) = NULL;
1390         crash_disable_local_vmclear(cpu);
1391         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1392
1393         /*
1394          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1395          * is before setting loaded_vmcs->vcpu to -1 which is done in
1396          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1397          * then adds the vmcs into percpu list before it is deleted.
1398          */
1399         smp_wmb();
1400
1401         loaded_vmcs_init(loaded_vmcs);
1402         crash_enable_local_vmclear(cpu);
1403 }
1404
1405 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1406 {
1407         int cpu = loaded_vmcs->cpu;
1408
1409         if (cpu != -1)
1410                 smp_call_function_single(cpu,
1411                          __loaded_vmcs_clear, loaded_vmcs, 1);
1412 }
1413
1414 static inline void vpid_sync_vcpu_single(int vpid)
1415 {
1416         if (vpid == 0)
1417                 return;
1418
1419         if (cpu_has_vmx_invvpid_single())
1420                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1421 }
1422
1423 static inline void vpid_sync_vcpu_global(void)
1424 {
1425         if (cpu_has_vmx_invvpid_global())
1426                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1427 }
1428
1429 static inline void vpid_sync_context(int vpid)
1430 {
1431         if (cpu_has_vmx_invvpid_single())
1432                 vpid_sync_vcpu_single(vpid);
1433         else
1434                 vpid_sync_vcpu_global();
1435 }
1436
1437 static inline void ept_sync_global(void)
1438 {
1439         if (cpu_has_vmx_invept_global())
1440                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1441 }
1442
1443 static inline void ept_sync_context(u64 eptp)
1444 {
1445         if (enable_ept) {
1446                 if (cpu_has_vmx_invept_context())
1447                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1448                 else
1449                         ept_sync_global();
1450         }
1451 }
1452
1453 static __always_inline unsigned long vmcs_readl(unsigned long field)
1454 {
1455         unsigned long value;
1456
1457         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1458                       : "=a"(value) : "d"(field) : "cc");
1459         return value;
1460 }
1461
1462 static __always_inline u16 vmcs_read16(unsigned long field)
1463 {
1464         return vmcs_readl(field);
1465 }
1466
1467 static __always_inline u32 vmcs_read32(unsigned long field)
1468 {
1469         return vmcs_readl(field);
1470 }
1471
1472 static __always_inline u64 vmcs_read64(unsigned long field)
1473 {
1474 #ifdef CONFIG_X86_64
1475         return vmcs_readl(field);
1476 #else
1477         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1478 #endif
1479 }
1480
1481 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1482 {
1483         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1484                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1485         dump_stack();
1486 }
1487
1488 static void vmcs_writel(unsigned long field, unsigned long value)
1489 {
1490         u8 error;
1491
1492         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1493                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1494         if (unlikely(error))
1495                 vmwrite_error(field, value);
1496 }
1497
1498 static void vmcs_write16(unsigned long field, u16 value)
1499 {
1500         vmcs_writel(field, value);
1501 }
1502
1503 static void vmcs_write32(unsigned long field, u32 value)
1504 {
1505         vmcs_writel(field, value);
1506 }
1507
1508 static void vmcs_write64(unsigned long field, u64 value)
1509 {
1510         vmcs_writel(field, value);
1511 #ifndef CONFIG_X86_64
1512         asm volatile ("");
1513         vmcs_writel(field+1, value >> 32);
1514 #endif
1515 }
1516
1517 static void vmcs_clear_bits(unsigned long field, u32 mask)
1518 {
1519         vmcs_writel(field, vmcs_readl(field) & ~mask);
1520 }
1521
1522 static void vmcs_set_bits(unsigned long field, u32 mask)
1523 {
1524         vmcs_writel(field, vmcs_readl(field) | mask);
1525 }
1526
1527 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1528 {
1529         vmcs_write32(VM_ENTRY_CONTROLS, val);
1530         vmx->vm_entry_controls_shadow = val;
1531 }
1532
1533 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1534 {
1535         if (vmx->vm_entry_controls_shadow != val)
1536                 vm_entry_controls_init(vmx, val);
1537 }
1538
1539 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1540 {
1541         return vmx->vm_entry_controls_shadow;
1542 }
1543
1544
1545 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1546 {
1547         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1548 }
1549
1550 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1551 {
1552         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1553 }
1554
1555 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1556 {
1557         vmcs_write32(VM_EXIT_CONTROLS, val);
1558         vmx->vm_exit_controls_shadow = val;
1559 }
1560
1561 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1562 {
1563         if (vmx->vm_exit_controls_shadow != val)
1564                 vm_exit_controls_init(vmx, val);
1565 }
1566
1567 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1568 {
1569         return vmx->vm_exit_controls_shadow;
1570 }
1571
1572
1573 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1574 {
1575         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1576 }
1577
1578 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1579 {
1580         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1581 }
1582
1583 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1584 {
1585         vmx->segment_cache.bitmask = 0;
1586 }
1587
1588 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1589                                        unsigned field)
1590 {
1591         bool ret;
1592         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1593
1594         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1595                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1596                 vmx->segment_cache.bitmask = 0;
1597         }
1598         ret = vmx->segment_cache.bitmask & mask;
1599         vmx->segment_cache.bitmask |= mask;
1600         return ret;
1601 }
1602
1603 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1604 {
1605         u16 *p = &vmx->segment_cache.seg[seg].selector;
1606
1607         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1608                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1609         return *p;
1610 }
1611
1612 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1613 {
1614         ulong *p = &vmx->segment_cache.seg[seg].base;
1615
1616         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1617                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1618         return *p;
1619 }
1620
1621 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1622 {
1623         u32 *p = &vmx->segment_cache.seg[seg].limit;
1624
1625         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1626                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1627         return *p;
1628 }
1629
1630 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1631 {
1632         u32 *p = &vmx->segment_cache.seg[seg].ar;
1633
1634         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1635                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1636         return *p;
1637 }
1638
1639 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1640 {
1641         u32 eb;
1642
1643         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1644              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1645         if ((vcpu->guest_debug &
1646              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1647             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1648                 eb |= 1u << BP_VECTOR;
1649         if (to_vmx(vcpu)->rmode.vm86_active)
1650                 eb = ~0;
1651         if (enable_ept)
1652                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1653         if (vcpu->fpu_active)
1654                 eb &= ~(1u << NM_VECTOR);
1655
1656         /* When we are running a nested L2 guest and L1 specified for it a
1657          * certain exception bitmap, we must trap the same exceptions and pass
1658          * them to L1. When running L2, we will only handle the exceptions
1659          * specified above if L1 did not want them.
1660          */
1661         if (is_guest_mode(vcpu))
1662                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1663
1664         vmcs_write32(EXCEPTION_BITMAP, eb);
1665 }
1666
1667 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1668                 unsigned long entry, unsigned long exit)
1669 {
1670         vm_entry_controls_clearbit(vmx, entry);
1671         vm_exit_controls_clearbit(vmx, exit);
1672 }
1673
1674 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1675 {
1676         unsigned i;
1677         struct msr_autoload *m = &vmx->msr_autoload;
1678
1679         switch (msr) {
1680         case MSR_EFER:
1681                 if (cpu_has_load_ia32_efer) {
1682                         clear_atomic_switch_msr_special(vmx,
1683                                         VM_ENTRY_LOAD_IA32_EFER,
1684                                         VM_EXIT_LOAD_IA32_EFER);
1685                         return;
1686                 }
1687                 break;
1688         case MSR_CORE_PERF_GLOBAL_CTRL:
1689                 if (cpu_has_load_perf_global_ctrl) {
1690                         clear_atomic_switch_msr_special(vmx,
1691                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1692                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1693                         return;
1694                 }
1695                 break;
1696         }
1697
1698         for (i = 0; i < m->nr; ++i)
1699                 if (m->guest[i].index == msr)
1700                         break;
1701
1702         if (i == m->nr)
1703                 return;
1704         --m->nr;
1705         m->guest[i] = m->guest[m->nr];
1706         m->host[i] = m->host[m->nr];
1707         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1708         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1709 }
1710
1711 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1712                 unsigned long entry, unsigned long exit,
1713                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1714                 u64 guest_val, u64 host_val)
1715 {
1716         vmcs_write64(guest_val_vmcs, guest_val);
1717         vmcs_write64(host_val_vmcs, host_val);
1718         vm_entry_controls_setbit(vmx, entry);
1719         vm_exit_controls_setbit(vmx, exit);
1720 }
1721
1722 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1723                                   u64 guest_val, u64 host_val)
1724 {
1725         unsigned i;
1726         struct msr_autoload *m = &vmx->msr_autoload;
1727
1728         switch (msr) {
1729         case MSR_EFER:
1730                 if (cpu_has_load_ia32_efer) {
1731                         add_atomic_switch_msr_special(vmx,
1732                                         VM_ENTRY_LOAD_IA32_EFER,
1733                                         VM_EXIT_LOAD_IA32_EFER,
1734                                         GUEST_IA32_EFER,
1735                                         HOST_IA32_EFER,
1736                                         guest_val, host_val);
1737                         return;
1738                 }
1739                 break;
1740         case MSR_CORE_PERF_GLOBAL_CTRL:
1741                 if (cpu_has_load_perf_global_ctrl) {
1742                         add_atomic_switch_msr_special(vmx,
1743                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1744                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1745                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1746                                         HOST_IA32_PERF_GLOBAL_CTRL,
1747                                         guest_val, host_val);
1748                         return;
1749                 }
1750                 break;
1751         case MSR_IA32_PEBS_ENABLE:
1752                 /* PEBS needs a quiescent period after being disabled (to write
1753                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1754                  * provide that period, so a CPU could write host's record into
1755                  * guest's memory.
1756                  */
1757                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1758         }
1759
1760         for (i = 0; i < m->nr; ++i)
1761                 if (m->guest[i].index == msr)
1762                         break;
1763
1764         if (i == NR_AUTOLOAD_MSRS) {
1765                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1766                                 "Can't add msr %x\n", msr);
1767                 return;
1768         } else if (i == m->nr) {
1769                 ++m->nr;
1770                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1771                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1772         }
1773
1774         m->guest[i].index = msr;
1775         m->guest[i].value = guest_val;
1776         m->host[i].index = msr;
1777         m->host[i].value = host_val;
1778 }
1779
1780 static void reload_tss(void)
1781 {
1782         /*
1783          * VT restores TR but not its size.  Useless.
1784          */
1785         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1786         struct desc_struct *descs;
1787
1788         descs = (void *)gdt->address;
1789         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1790         load_TR_desc();
1791 }
1792
1793 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1794 {
1795         u64 guest_efer = vmx->vcpu.arch.efer;
1796         u64 ignore_bits = 0;
1797
1798         if (!enable_ept) {
1799                 /*
1800                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1801                  * host CPUID is more efficient than testing guest CPUID
1802                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1803                  */
1804                 if (boot_cpu_has(X86_FEATURE_SMEP))
1805                         guest_efer |= EFER_NX;
1806                 else if (!(guest_efer & EFER_NX))
1807                         ignore_bits |= EFER_NX;
1808         }
1809
1810         /*
1811          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1812          */
1813         ignore_bits |= EFER_SCE;
1814 #ifdef CONFIG_X86_64
1815         ignore_bits |= EFER_LMA | EFER_LME;
1816         /* SCE is meaningful only in long mode on Intel */
1817         if (guest_efer & EFER_LMA)
1818                 ignore_bits &= ~(u64)EFER_SCE;
1819 #endif
1820
1821         clear_atomic_switch_msr(vmx, MSR_EFER);
1822
1823         /*
1824          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1825          * On CPUs that support "load IA32_EFER", always switch EFER
1826          * atomically, since it's faster than switching it manually.
1827          */
1828         if (cpu_has_load_ia32_efer ||
1829             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1830                 if (!(guest_efer & EFER_LMA))
1831                         guest_efer &= ~EFER_LME;
1832                 if (guest_efer != host_efer)
1833                         add_atomic_switch_msr(vmx, MSR_EFER,
1834                                               guest_efer, host_efer);
1835                 return false;
1836         } else {
1837                 guest_efer &= ~ignore_bits;
1838                 guest_efer |= host_efer & ignore_bits;
1839
1840                 vmx->guest_msrs[efer_offset].data = guest_efer;
1841                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1842
1843                 return true;
1844         }
1845 }
1846
1847 static unsigned long segment_base(u16 selector)
1848 {
1849         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1850         struct desc_struct *d;
1851         unsigned long table_base;
1852         unsigned long v;
1853
1854         if (!(selector & ~3))
1855                 return 0;
1856
1857         table_base = gdt->address;
1858
1859         if (selector & 4) {           /* from ldt */
1860                 u16 ldt_selector = kvm_read_ldt();
1861
1862                 if (!(ldt_selector & ~3))
1863                         return 0;
1864
1865                 table_base = segment_base(ldt_selector);
1866         }
1867         d = (struct desc_struct *)(table_base + (selector & ~7));
1868         v = get_desc_base(d);
1869 #ifdef CONFIG_X86_64
1870        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1871                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1872 #endif
1873         return v;
1874 }
1875
1876 static inline unsigned long kvm_read_tr_base(void)
1877 {
1878         u16 tr;
1879         asm("str %0" : "=g"(tr));
1880         return segment_base(tr);
1881 }
1882
1883 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1884 {
1885         struct vcpu_vmx *vmx = to_vmx(vcpu);
1886         int i;
1887
1888         if (vmx->host_state.loaded)
1889                 return;
1890
1891         vmx->host_state.loaded = 1;
1892         /*
1893          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1894          * allow segment selectors with cpl > 0 or ti == 1.
1895          */
1896         vmx->host_state.ldt_sel = kvm_read_ldt();
1897         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1898         savesegment(fs, vmx->host_state.fs_sel);
1899         if (!(vmx->host_state.fs_sel & 7)) {
1900                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1901                 vmx->host_state.fs_reload_needed = 0;
1902         } else {
1903                 vmcs_write16(HOST_FS_SELECTOR, 0);
1904                 vmx->host_state.fs_reload_needed = 1;
1905         }
1906         savesegment(gs, vmx->host_state.gs_sel);
1907         if (!(vmx->host_state.gs_sel & 7))
1908                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1909         else {
1910                 vmcs_write16(HOST_GS_SELECTOR, 0);
1911                 vmx->host_state.gs_ldt_reload_needed = 1;
1912         }
1913
1914 #ifdef CONFIG_X86_64
1915         savesegment(ds, vmx->host_state.ds_sel);
1916         savesegment(es, vmx->host_state.es_sel);
1917 #endif
1918
1919 #ifdef CONFIG_X86_64
1920         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1921         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1922 #else
1923         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1924         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1925 #endif
1926
1927 #ifdef CONFIG_X86_64
1928         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1929         if (is_long_mode(&vmx->vcpu))
1930                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1931 #endif
1932         if (boot_cpu_has(X86_FEATURE_MPX))
1933                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1934         for (i = 0; i < vmx->save_nmsrs; ++i)
1935                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1936                                    vmx->guest_msrs[i].data,
1937                                    vmx->guest_msrs[i].mask);
1938 }
1939
1940 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1941 {
1942         if (!vmx->host_state.loaded)
1943                 return;
1944
1945         ++vmx->vcpu.stat.host_state_reload;
1946         vmx->host_state.loaded = 0;
1947 #ifdef CONFIG_X86_64
1948         if (is_long_mode(&vmx->vcpu))
1949                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1950 #endif
1951         if (vmx->host_state.gs_ldt_reload_needed) {
1952                 kvm_load_ldt(vmx->host_state.ldt_sel);
1953 #ifdef CONFIG_X86_64
1954                 load_gs_index(vmx->host_state.gs_sel);
1955 #else
1956                 loadsegment(gs, vmx->host_state.gs_sel);
1957 #endif
1958         }
1959         if (vmx->host_state.fs_reload_needed)
1960                 loadsegment(fs, vmx->host_state.fs_sel);
1961 #ifdef CONFIG_X86_64
1962         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1963                 loadsegment(ds, vmx->host_state.ds_sel);
1964                 loadsegment(es, vmx->host_state.es_sel);
1965         }
1966 #endif
1967         reload_tss();
1968 #ifdef CONFIG_X86_64
1969         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1970 #endif
1971         if (vmx->host_state.msr_host_bndcfgs)
1972                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1973         /*
1974          * If the FPU is not active (through the host task or
1975          * the guest vcpu), then restore the cr0.TS bit.
1976          */
1977         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1978                 stts();
1979         load_gdt(this_cpu_ptr(&host_gdt));
1980 }
1981
1982 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1983 {
1984         preempt_disable();
1985         __vmx_load_host_state(vmx);
1986         preempt_enable();
1987 }
1988
1989 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1990 {
1991         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1992         struct pi_desc old, new;
1993         unsigned int dest;
1994
1995         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1996                 !irq_remapping_cap(IRQ_POSTING_CAP))
1997                 return;
1998
1999         do {
2000                 old.control = new.control = pi_desc->control;
2001
2002                 /*
2003                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2004                  * are two possible cases:
2005                  * 1. After running 'pre_block', context switch
2006                  *    happened. For this case, 'sn' was set in
2007                  *    vmx_vcpu_put(), so we need to clear it here.
2008                  * 2. After running 'pre_block', we were blocked,
2009                  *    and woken up by some other guy. For this case,
2010                  *    we don't need to do anything, 'pi_post_block'
2011                  *    will do everything for us. However, we cannot
2012                  *    check whether it is case #1 or case #2 here
2013                  *    (maybe, not needed), so we also clear sn here,
2014                  *    I think it is not a big deal.
2015                  */
2016                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2017                         if (vcpu->cpu != cpu) {
2018                                 dest = cpu_physical_id(cpu);
2019
2020                                 if (x2apic_enabled())
2021                                         new.ndst = dest;
2022                                 else
2023                                         new.ndst = (dest << 8) & 0xFF00;
2024                         }
2025
2026                         /* set 'NV' to 'notification vector' */
2027                         new.nv = POSTED_INTR_VECTOR;
2028                 }
2029
2030                 /* Allow posting non-urgent interrupts */
2031                 new.sn = 0;
2032         } while (cmpxchg64(&pi_desc->control, old.control,
2033                            new.control) != old.control);
2034 }
2035 /*
2036  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2037  * vcpu mutex is already taken.
2038  */
2039 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2040 {
2041         struct vcpu_vmx *vmx = to_vmx(vcpu);
2042         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2043
2044         if (!vmm_exclusive)
2045                 kvm_cpu_vmxon(phys_addr);
2046         else if (vmx->loaded_vmcs->cpu != cpu)
2047                 loaded_vmcs_clear(vmx->loaded_vmcs);
2048
2049         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2050                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2051                 vmcs_load(vmx->loaded_vmcs->vmcs);
2052         }
2053
2054         if (vmx->loaded_vmcs->cpu != cpu) {
2055                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2056                 unsigned long sysenter_esp;
2057
2058                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2059                 local_irq_disable();
2060                 crash_disable_local_vmclear(cpu);
2061
2062                 /*
2063                  * Read loaded_vmcs->cpu should be before fetching
2064                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2065                  * See the comments in __loaded_vmcs_clear().
2066                  */
2067                 smp_rmb();
2068
2069                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2070                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2071                 crash_enable_local_vmclear(cpu);
2072                 local_irq_enable();
2073
2074                 /*
2075                  * Linux uses per-cpu TSS and GDT, so set these when switching
2076                  * processors.
2077                  */
2078                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2079                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2080
2081                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2082                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2083
2084                 vmx->loaded_vmcs->cpu = cpu;
2085         }
2086
2087         /* Setup TSC multiplier */
2088         if (kvm_has_tsc_control &&
2089             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2090                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2091                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2092         }
2093
2094         vmx_vcpu_pi_load(vcpu, cpu);
2095 }
2096
2097 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2098 {
2099         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2100
2101         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2102                 !irq_remapping_cap(IRQ_POSTING_CAP))
2103                 return;
2104
2105         /* Set SN when the vCPU is preempted */
2106         if (vcpu->preempted)
2107                 pi_set_sn(pi_desc);
2108 }
2109
2110 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2111 {
2112         vmx_vcpu_pi_put(vcpu);
2113
2114         __vmx_load_host_state(to_vmx(vcpu));
2115         if (!vmm_exclusive) {
2116                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2117                 vcpu->cpu = -1;
2118                 kvm_cpu_vmxoff();
2119         }
2120 }
2121
2122 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2123 {
2124         ulong cr0;
2125
2126         if (vcpu->fpu_active)
2127                 return;
2128         vcpu->fpu_active = 1;
2129         cr0 = vmcs_readl(GUEST_CR0);
2130         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2131         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2132         vmcs_writel(GUEST_CR0, cr0);
2133         update_exception_bitmap(vcpu);
2134         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2135         if (is_guest_mode(vcpu))
2136                 vcpu->arch.cr0_guest_owned_bits &=
2137                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2138         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2139 }
2140
2141 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2142
2143 /*
2144  * Return the cr0 value that a nested guest would read. This is a combination
2145  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2146  * its hypervisor (cr0_read_shadow).
2147  */
2148 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2149 {
2150         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2151                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2152 }
2153 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2154 {
2155         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2156                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2157 }
2158
2159 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2160 {
2161         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2162          * set this *before* calling this function.
2163          */
2164         vmx_decache_cr0_guest_bits(vcpu);
2165         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2166         update_exception_bitmap(vcpu);
2167         vcpu->arch.cr0_guest_owned_bits = 0;
2168         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2169         if (is_guest_mode(vcpu)) {
2170                 /*
2171                  * L1's specified read shadow might not contain the TS bit,
2172                  * so now that we turned on shadowing of this bit, we need to
2173                  * set this bit of the shadow. Like in nested_vmx_run we need
2174                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2175                  * up-to-date here because we just decached cr0.TS (and we'll
2176                  * only update vmcs12->guest_cr0 on nested exit).
2177                  */
2178                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2179                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2180                         (vcpu->arch.cr0 & X86_CR0_TS);
2181                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2182         } else
2183                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2184 }
2185
2186 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2187 {
2188         unsigned long rflags, save_rflags;
2189
2190         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2191                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2192                 rflags = vmcs_readl(GUEST_RFLAGS);
2193                 if (to_vmx(vcpu)->rmode.vm86_active) {
2194                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2195                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2196                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2197                 }
2198                 to_vmx(vcpu)->rflags = rflags;
2199         }
2200         return to_vmx(vcpu)->rflags;
2201 }
2202
2203 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2204 {
2205         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2206         to_vmx(vcpu)->rflags = rflags;
2207         if (to_vmx(vcpu)->rmode.vm86_active) {
2208                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2209                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2210         }
2211         vmcs_writel(GUEST_RFLAGS, rflags);
2212 }
2213
2214 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2215 {
2216         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2217         int ret = 0;
2218
2219         if (interruptibility & GUEST_INTR_STATE_STI)
2220                 ret |= KVM_X86_SHADOW_INT_STI;
2221         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2222                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2223
2224         return ret;
2225 }
2226
2227 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2228 {
2229         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2230         u32 interruptibility = interruptibility_old;
2231
2232         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2233
2234         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2235                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2236         else if (mask & KVM_X86_SHADOW_INT_STI)
2237                 interruptibility |= GUEST_INTR_STATE_STI;
2238
2239         if ((interruptibility != interruptibility_old))
2240                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2241 }
2242
2243 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2244 {
2245         unsigned long rip;
2246
2247         rip = kvm_rip_read(vcpu);
2248         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2249         kvm_rip_write(vcpu, rip);
2250
2251         /* skipping an emulated instruction also counts */
2252         vmx_set_interrupt_shadow(vcpu, 0);
2253 }
2254
2255 /*
2256  * KVM wants to inject page-faults which it got to the guest. This function
2257  * checks whether in a nested guest, we need to inject them to L1 or L2.
2258  */
2259 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2260 {
2261         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2262
2263         if (!(vmcs12->exception_bitmap & (1u << nr)))
2264                 return 0;
2265
2266         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2267                           vmcs_read32(VM_EXIT_INTR_INFO),
2268                           vmcs_readl(EXIT_QUALIFICATION));
2269         return 1;
2270 }
2271
2272 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2273                                 bool has_error_code, u32 error_code,
2274                                 bool reinject)
2275 {
2276         struct vcpu_vmx *vmx = to_vmx(vcpu);
2277         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2278
2279         if (!reinject && is_guest_mode(vcpu) &&
2280             nested_vmx_check_exception(vcpu, nr))
2281                 return;
2282
2283         if (has_error_code) {
2284                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2285                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2286         }
2287
2288         if (vmx->rmode.vm86_active) {
2289                 int inc_eip = 0;
2290                 if (kvm_exception_is_soft(nr))
2291                         inc_eip = vcpu->arch.event_exit_inst_len;
2292                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2293                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2294                 return;
2295         }
2296
2297         if (kvm_exception_is_soft(nr)) {
2298                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2299                              vmx->vcpu.arch.event_exit_inst_len);
2300                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2301         } else
2302                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2303
2304         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2305 }
2306
2307 static bool vmx_rdtscp_supported(void)
2308 {
2309         return cpu_has_vmx_rdtscp();
2310 }
2311
2312 static bool vmx_invpcid_supported(void)
2313 {
2314         return cpu_has_vmx_invpcid() && enable_ept;
2315 }
2316
2317 /*
2318  * Swap MSR entry in host/guest MSR entry array.
2319  */
2320 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2321 {
2322         struct shared_msr_entry tmp;
2323
2324         tmp = vmx->guest_msrs[to];
2325         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2326         vmx->guest_msrs[from] = tmp;
2327 }
2328
2329 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2330 {
2331         unsigned long *msr_bitmap;
2332
2333         if (is_guest_mode(vcpu))
2334                 msr_bitmap = vmx_msr_bitmap_nested;
2335         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2336                 if (is_long_mode(vcpu))
2337                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2338                 else
2339                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2340         } else {
2341                 if (is_long_mode(vcpu))
2342                         msr_bitmap = vmx_msr_bitmap_longmode;
2343                 else
2344                         msr_bitmap = vmx_msr_bitmap_legacy;
2345         }
2346
2347         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2348 }
2349
2350 /*
2351  * Set up the vmcs to automatically save and restore system
2352  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2353  * mode, as fiddling with msrs is very expensive.
2354  */
2355 static void setup_msrs(struct vcpu_vmx *vmx)
2356 {
2357         int save_nmsrs, index;
2358
2359         save_nmsrs = 0;
2360 #ifdef CONFIG_X86_64
2361         if (is_long_mode(&vmx->vcpu)) {
2362                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2363                 if (index >= 0)
2364                         move_msr_up(vmx, index, save_nmsrs++);
2365                 index = __find_msr_index(vmx, MSR_LSTAR);
2366                 if (index >= 0)
2367                         move_msr_up(vmx, index, save_nmsrs++);
2368                 index = __find_msr_index(vmx, MSR_CSTAR);
2369                 if (index >= 0)
2370                         move_msr_up(vmx, index, save_nmsrs++);
2371                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2372                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2373                         move_msr_up(vmx, index, save_nmsrs++);
2374                 /*
2375                  * MSR_STAR is only needed on long mode guests, and only
2376                  * if efer.sce is enabled.
2377                  */
2378                 index = __find_msr_index(vmx, MSR_STAR);
2379                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2380                         move_msr_up(vmx, index, save_nmsrs++);
2381         }
2382 #endif
2383         index = __find_msr_index(vmx, MSR_EFER);
2384         if (index >= 0 && update_transition_efer(vmx, index))
2385                 move_msr_up(vmx, index, save_nmsrs++);
2386
2387         vmx->save_nmsrs = save_nmsrs;
2388
2389         if (cpu_has_vmx_msr_bitmap())
2390                 vmx_set_msr_bitmap(&vmx->vcpu);
2391 }
2392
2393 /*
2394  * reads and returns guest's timestamp counter "register"
2395  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2396  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2397  */
2398 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2399 {
2400         u64 host_tsc, tsc_offset;
2401
2402         host_tsc = rdtsc();
2403         tsc_offset = vmcs_read64(TSC_OFFSET);
2404         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2405 }
2406
2407 /*
2408  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2409  * counter, even if a nested guest (L2) is currently running.
2410  */
2411 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2412 {
2413         u64 tsc_offset;
2414
2415         tsc_offset = is_guest_mode(vcpu) ?
2416                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2417                 vmcs_read64(TSC_OFFSET);
2418         return host_tsc + tsc_offset;
2419 }
2420
2421 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2422 {
2423         return vmcs_read64(TSC_OFFSET);
2424 }
2425
2426 /*
2427  * writes 'offset' into guest's timestamp counter offset register
2428  */
2429 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2430 {
2431         if (is_guest_mode(vcpu)) {
2432                 /*
2433                  * We're here if L1 chose not to trap WRMSR to TSC. According
2434                  * to the spec, this should set L1's TSC; The offset that L1
2435                  * set for L2 remains unchanged, and still needs to be added
2436                  * to the newly set TSC to get L2's TSC.
2437                  */
2438                 struct vmcs12 *vmcs12;
2439                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2440                 /* recalculate vmcs02.TSC_OFFSET: */
2441                 vmcs12 = get_vmcs12(vcpu);
2442                 vmcs_write64(TSC_OFFSET, offset +
2443                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2444                          vmcs12->tsc_offset : 0));
2445         } else {
2446                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2447                                            vmcs_read64(TSC_OFFSET), offset);
2448                 vmcs_write64(TSC_OFFSET, offset);
2449         }
2450 }
2451
2452 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2453 {
2454         u64 offset = vmcs_read64(TSC_OFFSET);
2455
2456         vmcs_write64(TSC_OFFSET, offset + adjustment);
2457         if (is_guest_mode(vcpu)) {
2458                 /* Even when running L2, the adjustment needs to apply to L1 */
2459                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2460         } else
2461                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2462                                            offset + adjustment);
2463 }
2464
2465 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2466 {
2467         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2468         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2469 }
2470
2471 /*
2472  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2473  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2474  * all guests if the "nested" module option is off, and can also be disabled
2475  * for a single guest by disabling its VMX cpuid bit.
2476  */
2477 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2478 {
2479         return nested && guest_cpuid_has_vmx(vcpu);
2480 }
2481
2482 /*
2483  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2484  * returned for the various VMX controls MSRs when nested VMX is enabled.
2485  * The same values should also be used to verify that vmcs12 control fields are
2486  * valid during nested entry from L1 to L2.
2487  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2488  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2489  * bit in the high half is on if the corresponding bit in the control field
2490  * may be on. See also vmx_control_verify().
2491  */
2492 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2493 {
2494         /*
2495          * Note that as a general rule, the high half of the MSRs (bits in
2496          * the control fields which may be 1) should be initialized by the
2497          * intersection of the underlying hardware's MSR (i.e., features which
2498          * can be supported) and the list of features we want to expose -
2499          * because they are known to be properly supported in our code.
2500          * Also, usually, the low half of the MSRs (bits which must be 1) can
2501          * be set to 0, meaning that L1 may turn off any of these bits. The
2502          * reason is that if one of these bits is necessary, it will appear
2503          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2504          * fields of vmcs01 and vmcs02, will turn these bits off - and
2505          * nested_vmx_exit_handled() will not pass related exits to L1.
2506          * These rules have exceptions below.
2507          */
2508
2509         /* pin-based controls */
2510         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2511                 vmx->nested.nested_vmx_pinbased_ctls_low,
2512                 vmx->nested.nested_vmx_pinbased_ctls_high);
2513         vmx->nested.nested_vmx_pinbased_ctls_low |=
2514                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2515         vmx->nested.nested_vmx_pinbased_ctls_high &=
2516                 PIN_BASED_EXT_INTR_MASK |
2517                 PIN_BASED_NMI_EXITING |
2518                 PIN_BASED_VIRTUAL_NMIS;
2519         vmx->nested.nested_vmx_pinbased_ctls_high |=
2520                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2521                 PIN_BASED_VMX_PREEMPTION_TIMER;
2522         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2523                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2524                         PIN_BASED_POSTED_INTR;
2525
2526         /* exit controls */
2527         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2528                 vmx->nested.nested_vmx_exit_ctls_low,
2529                 vmx->nested.nested_vmx_exit_ctls_high);
2530         vmx->nested.nested_vmx_exit_ctls_low =
2531                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2532
2533         vmx->nested.nested_vmx_exit_ctls_high &=
2534 #ifdef CONFIG_X86_64
2535                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2536 #endif
2537                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2538         vmx->nested.nested_vmx_exit_ctls_high |=
2539                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2540                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2541                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2542
2543         if (kvm_mpx_supported())
2544                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2545
2546         /* We support free control of debug control saving. */
2547         vmx->nested.nested_vmx_true_exit_ctls_low =
2548                 vmx->nested.nested_vmx_exit_ctls_low &
2549                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2550
2551         /* entry controls */
2552         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2553                 vmx->nested.nested_vmx_entry_ctls_low,
2554                 vmx->nested.nested_vmx_entry_ctls_high);
2555         vmx->nested.nested_vmx_entry_ctls_low =
2556                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2557         vmx->nested.nested_vmx_entry_ctls_high &=
2558 #ifdef CONFIG_X86_64
2559                 VM_ENTRY_IA32E_MODE |
2560 #endif
2561                 VM_ENTRY_LOAD_IA32_PAT;
2562         vmx->nested.nested_vmx_entry_ctls_high |=
2563                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2564         if (kvm_mpx_supported())
2565                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2566
2567         /* We support free control of debug control loading. */
2568         vmx->nested.nested_vmx_true_entry_ctls_low =
2569                 vmx->nested.nested_vmx_entry_ctls_low &
2570                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2571
2572         /* cpu-based controls */
2573         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2574                 vmx->nested.nested_vmx_procbased_ctls_low,
2575                 vmx->nested.nested_vmx_procbased_ctls_high);
2576         vmx->nested.nested_vmx_procbased_ctls_low =
2577                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2578         vmx->nested.nested_vmx_procbased_ctls_high &=
2579                 CPU_BASED_VIRTUAL_INTR_PENDING |
2580                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2581                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2582                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2583                 CPU_BASED_CR3_STORE_EXITING |
2584 #ifdef CONFIG_X86_64
2585                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2586 #endif
2587                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2588                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2589                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2590                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2591                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2592         /*
2593          * We can allow some features even when not supported by the
2594          * hardware. For example, L1 can specify an MSR bitmap - and we
2595          * can use it to avoid exits to L1 - even when L0 runs L2
2596          * without MSR bitmaps.
2597          */
2598         vmx->nested.nested_vmx_procbased_ctls_high |=
2599                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2600                 CPU_BASED_USE_MSR_BITMAPS;
2601
2602         /* We support free control of CR3 access interception. */
2603         vmx->nested.nested_vmx_true_procbased_ctls_low =
2604                 vmx->nested.nested_vmx_procbased_ctls_low &
2605                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2606
2607         /* secondary cpu-based controls */
2608         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2609                 vmx->nested.nested_vmx_secondary_ctls_low,
2610                 vmx->nested.nested_vmx_secondary_ctls_high);
2611         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2612         vmx->nested.nested_vmx_secondary_ctls_high &=
2613                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2614                 SECONDARY_EXEC_RDTSCP |
2615                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2616                 SECONDARY_EXEC_ENABLE_VPID |
2617                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2618                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2619                 SECONDARY_EXEC_WBINVD_EXITING |
2620                 SECONDARY_EXEC_XSAVES |
2621                 SECONDARY_EXEC_PCOMMIT;
2622
2623         if (enable_ept) {
2624                 /* nested EPT: emulate EPT also to L1 */
2625                 vmx->nested.nested_vmx_secondary_ctls_high |=
2626                         SECONDARY_EXEC_ENABLE_EPT;
2627                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2628                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2629                          VMX_EPT_INVEPT_BIT;
2630                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2631                 /*
2632                  * For nested guests, we don't do anything specific
2633                  * for single context invalidation. Hence, only advertise
2634                  * support for global context invalidation.
2635                  */
2636                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2637         } else
2638                 vmx->nested.nested_vmx_ept_caps = 0;
2639
2640         /*
2641          * Old versions of KVM use the single-context version without
2642          * checking for support, so declare that it is supported even
2643          * though it is treated as global context.  The alternative is
2644          * not failing the single-context invvpid, and it is worse.
2645          */
2646         if (enable_vpid)
2647                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2648                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2649                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2650         else
2651                 vmx->nested.nested_vmx_vpid_caps = 0;
2652
2653         if (enable_unrestricted_guest)
2654                 vmx->nested.nested_vmx_secondary_ctls_high |=
2655                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2656
2657         /* miscellaneous data */
2658         rdmsr(MSR_IA32_VMX_MISC,
2659                 vmx->nested.nested_vmx_misc_low,
2660                 vmx->nested.nested_vmx_misc_high);
2661         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2662         vmx->nested.nested_vmx_misc_low |=
2663                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2664                 VMX_MISC_ACTIVITY_HLT;
2665         vmx->nested.nested_vmx_misc_high = 0;
2666 }
2667
2668 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2669 {
2670         /*
2671          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2672          */
2673         return ((control & high) | low) == control;
2674 }
2675
2676 static inline u64 vmx_control_msr(u32 low, u32 high)
2677 {
2678         return low | ((u64)high << 32);
2679 }
2680
2681 /* Returns 0 on success, non-0 otherwise. */
2682 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2683 {
2684         struct vcpu_vmx *vmx = to_vmx(vcpu);
2685
2686         switch (msr_index) {
2687         case MSR_IA32_VMX_BASIC:
2688                 /*
2689                  * This MSR reports some information about VMX support. We
2690                  * should return information about the VMX we emulate for the
2691                  * guest, and the VMCS structure we give it - not about the
2692                  * VMX support of the underlying hardware.
2693                  */
2694                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2695                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2696                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2697                 break;
2698         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2699         case MSR_IA32_VMX_PINBASED_CTLS:
2700                 *pdata = vmx_control_msr(
2701                         vmx->nested.nested_vmx_pinbased_ctls_low,
2702                         vmx->nested.nested_vmx_pinbased_ctls_high);
2703                 break;
2704         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2705                 *pdata = vmx_control_msr(
2706                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2707                         vmx->nested.nested_vmx_procbased_ctls_high);
2708                 break;
2709         case MSR_IA32_VMX_PROCBASED_CTLS:
2710                 *pdata = vmx_control_msr(
2711                         vmx->nested.nested_vmx_procbased_ctls_low,
2712                         vmx->nested.nested_vmx_procbased_ctls_high);
2713                 break;
2714         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2715                 *pdata = vmx_control_msr(
2716                         vmx->nested.nested_vmx_true_exit_ctls_low,
2717                         vmx->nested.nested_vmx_exit_ctls_high);
2718                 break;
2719         case MSR_IA32_VMX_EXIT_CTLS:
2720                 *pdata = vmx_control_msr(
2721                         vmx->nested.nested_vmx_exit_ctls_low,
2722                         vmx->nested.nested_vmx_exit_ctls_high);
2723                 break;
2724         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2725                 *pdata = vmx_control_msr(
2726                         vmx->nested.nested_vmx_true_entry_ctls_low,
2727                         vmx->nested.nested_vmx_entry_ctls_high);
2728                 break;
2729         case MSR_IA32_VMX_ENTRY_CTLS:
2730                 *pdata = vmx_control_msr(
2731                         vmx->nested.nested_vmx_entry_ctls_low,
2732                         vmx->nested.nested_vmx_entry_ctls_high);
2733                 break;
2734         case MSR_IA32_VMX_MISC:
2735                 *pdata = vmx_control_msr(
2736                         vmx->nested.nested_vmx_misc_low,
2737                         vmx->nested.nested_vmx_misc_high);
2738                 break;
2739         /*
2740          * These MSRs specify bits which the guest must keep fixed (on or off)
2741          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2742          * We picked the standard core2 setting.
2743          */
2744 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2745 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2746         case MSR_IA32_VMX_CR0_FIXED0:
2747                 *pdata = VMXON_CR0_ALWAYSON;
2748                 break;
2749         case MSR_IA32_VMX_CR0_FIXED1:
2750                 *pdata = -1ULL;
2751                 break;
2752         case MSR_IA32_VMX_CR4_FIXED0:
2753                 *pdata = VMXON_CR4_ALWAYSON;
2754                 break;
2755         case MSR_IA32_VMX_CR4_FIXED1:
2756                 *pdata = -1ULL;
2757                 break;
2758         case MSR_IA32_VMX_VMCS_ENUM:
2759                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2760                 break;
2761         case MSR_IA32_VMX_PROCBASED_CTLS2:
2762                 *pdata = vmx_control_msr(
2763                         vmx->nested.nested_vmx_secondary_ctls_low,
2764                         vmx->nested.nested_vmx_secondary_ctls_high);
2765                 break;
2766         case MSR_IA32_VMX_EPT_VPID_CAP:
2767                 /* Currently, no nested vpid support */
2768                 *pdata = vmx->nested.nested_vmx_ept_caps |
2769                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2770                 break;
2771         default:
2772                 return 1;
2773         }
2774
2775         return 0;
2776 }
2777
2778 /*
2779  * Reads an msr value (of 'msr_index') into 'pdata'.
2780  * Returns 0 on success, non-0 otherwise.
2781  * Assumes vcpu_load() was already called.
2782  */
2783 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2784 {
2785         struct shared_msr_entry *msr;
2786
2787         switch (msr_info->index) {
2788 #ifdef CONFIG_X86_64
2789         case MSR_FS_BASE:
2790                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2791                 break;
2792         case MSR_GS_BASE:
2793                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2794                 break;
2795         case MSR_KERNEL_GS_BASE:
2796                 vmx_load_host_state(to_vmx(vcpu));
2797                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2798                 break;
2799 #endif
2800         case MSR_EFER:
2801                 return kvm_get_msr_common(vcpu, msr_info);
2802         case MSR_IA32_TSC:
2803                 msr_info->data = guest_read_tsc(vcpu);
2804                 break;
2805         case MSR_IA32_SYSENTER_CS:
2806                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2807                 break;
2808         case MSR_IA32_SYSENTER_EIP:
2809                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2810                 break;
2811         case MSR_IA32_SYSENTER_ESP:
2812                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2813                 break;
2814         case MSR_IA32_BNDCFGS:
2815                 if (!kvm_mpx_supported() ||
2816                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
2817                         return 1;
2818                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2819                 break;
2820         case MSR_IA32_FEATURE_CONTROL:
2821                 if (!nested_vmx_allowed(vcpu))
2822                         return 1;
2823                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2824                 break;
2825         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2826                 if (!nested_vmx_allowed(vcpu))
2827                         return 1;
2828                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2829         case MSR_IA32_XSS:
2830                 if (!vmx_xsaves_supported())
2831                         return 1;
2832                 msr_info->data = vcpu->arch.ia32_xss;
2833                 break;
2834         case MSR_TSC_AUX:
2835                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2836                         return 1;
2837                 /* Otherwise falls through */
2838         default:
2839                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2840                 if (msr) {
2841                         msr_info->data = msr->data;
2842                         break;
2843                 }
2844                 return kvm_get_msr_common(vcpu, msr_info);
2845         }
2846
2847         return 0;
2848 }
2849
2850 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2851
2852 /*
2853  * Writes msr value into into the appropriate "register".
2854  * Returns 0 on success, non-0 otherwise.
2855  * Assumes vcpu_load() was already called.
2856  */
2857 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2858 {
2859         struct vcpu_vmx *vmx = to_vmx(vcpu);
2860         struct shared_msr_entry *msr;
2861         int ret = 0;
2862         u32 msr_index = msr_info->index;
2863         u64 data = msr_info->data;
2864
2865         switch (msr_index) {
2866         case MSR_EFER:
2867                 ret = kvm_set_msr_common(vcpu, msr_info);
2868                 break;
2869 #ifdef CONFIG_X86_64
2870         case MSR_FS_BASE:
2871                 vmx_segment_cache_clear(vmx);
2872                 vmcs_writel(GUEST_FS_BASE, data);
2873                 break;
2874         case MSR_GS_BASE:
2875                 vmx_segment_cache_clear(vmx);
2876                 vmcs_writel(GUEST_GS_BASE, data);
2877                 break;
2878         case MSR_KERNEL_GS_BASE:
2879                 vmx_load_host_state(vmx);
2880                 vmx->msr_guest_kernel_gs_base = data;
2881                 break;
2882 #endif
2883         case MSR_IA32_SYSENTER_CS:
2884                 vmcs_write32(GUEST_SYSENTER_CS, data);
2885                 break;
2886         case MSR_IA32_SYSENTER_EIP:
2887                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2888                 break;
2889         case MSR_IA32_SYSENTER_ESP:
2890                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2891                 break;
2892         case MSR_IA32_BNDCFGS:
2893                 if (!kvm_mpx_supported() ||
2894                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
2895                         return 1;
2896                 if (is_noncanonical_address(data & PAGE_MASK) ||
2897                     (data & MSR_IA32_BNDCFGS_RSVD))
2898                         return 1;
2899                 vmcs_write64(GUEST_BNDCFGS, data);
2900                 break;
2901         case MSR_IA32_TSC:
2902                 kvm_write_tsc(vcpu, msr_info);
2903                 break;
2904         case MSR_IA32_CR_PAT:
2905                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2906                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2907                                 return 1;
2908                         vmcs_write64(GUEST_IA32_PAT, data);
2909                         vcpu->arch.pat = data;
2910                         break;
2911                 }
2912                 ret = kvm_set_msr_common(vcpu, msr_info);
2913                 break;
2914         case MSR_IA32_TSC_ADJUST:
2915                 ret = kvm_set_msr_common(vcpu, msr_info);
2916                 break;
2917         case MSR_IA32_FEATURE_CONTROL:
2918                 if (!nested_vmx_allowed(vcpu) ||
2919                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2920                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2921                         return 1;
2922                 vmx->nested.msr_ia32_feature_control = data;
2923                 if (msr_info->host_initiated && data == 0)
2924                         vmx_leave_nested(vcpu);
2925                 break;
2926         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2927                 return 1; /* they are read-only */
2928         case MSR_IA32_XSS:
2929                 if (!vmx_xsaves_supported())
2930                         return 1;
2931                 /*
2932                  * The only supported bit as of Skylake is bit 8, but
2933                  * it is not supported on KVM.
2934                  */
2935                 if (data != 0)
2936                         return 1;
2937                 vcpu->arch.ia32_xss = data;
2938                 if (vcpu->arch.ia32_xss != host_xss)
2939                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2940                                 vcpu->arch.ia32_xss, host_xss);
2941                 else
2942                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2943                 break;
2944         case MSR_TSC_AUX:
2945                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2946                         return 1;
2947                 /* Check reserved bit, higher 32 bits should be zero */
2948                 if ((data >> 32) != 0)
2949                         return 1;
2950                 /* Otherwise falls through */
2951         default:
2952                 msr = find_msr_entry(vmx, msr_index);
2953                 if (msr) {
2954                         u64 old_msr_data = msr->data;
2955                         msr->data = data;
2956                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2957                                 preempt_disable();
2958                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2959                                                          msr->mask);
2960                                 preempt_enable();
2961                                 if (ret)
2962                                         msr->data = old_msr_data;
2963                         }
2964                         break;
2965                 }
2966                 ret = kvm_set_msr_common(vcpu, msr_info);
2967         }
2968
2969         return ret;
2970 }
2971
2972 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2973 {
2974         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2975         switch (reg) {
2976         case VCPU_REGS_RSP:
2977                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2978                 break;
2979         case VCPU_REGS_RIP:
2980                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2981                 break;
2982         case VCPU_EXREG_PDPTR:
2983                 if (enable_ept)
2984                         ept_save_pdptrs(vcpu);
2985                 break;
2986         default:
2987                 break;
2988         }
2989 }
2990
2991 static __init int cpu_has_kvm_support(void)
2992 {
2993         return cpu_has_vmx();
2994 }
2995
2996 static __init int vmx_disabled_by_bios(void)
2997 {
2998         u64 msr;
2999
3000         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3001         if (msr & FEATURE_CONTROL_LOCKED) {
3002                 /* launched w/ TXT and VMX disabled */
3003                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3004                         && tboot_enabled())
3005                         return 1;
3006                 /* launched w/o TXT and VMX only enabled w/ TXT */
3007                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3008                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3009                         && !tboot_enabled()) {
3010                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3011                                 "activate TXT before enabling KVM\n");
3012                         return 1;
3013                 }
3014                 /* launched w/o TXT and VMX disabled */
3015                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3016                         && !tboot_enabled())
3017                         return 1;
3018         }
3019
3020         return 0;
3021 }
3022
3023 static void kvm_cpu_vmxon(u64 addr)
3024 {
3025         asm volatile (ASM_VMX_VMXON_RAX
3026                         : : "a"(&addr), "m"(addr)
3027                         : "memory", "cc");
3028 }
3029
3030 static int hardware_enable(void)
3031 {
3032         int cpu = raw_smp_processor_id();
3033         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3034         u64 old, test_bits;
3035
3036         if (cr4_read_shadow() & X86_CR4_VMXE)
3037                 return -EBUSY;
3038
3039         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3040         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3041         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3042
3043         /*
3044          * Now we can enable the vmclear operation in kdump
3045          * since the loaded_vmcss_on_cpu list on this cpu
3046          * has been initialized.
3047          *
3048          * Though the cpu is not in VMX operation now, there
3049          * is no problem to enable the vmclear operation
3050          * for the loaded_vmcss_on_cpu list is empty!
3051          */
3052         crash_enable_local_vmclear(cpu);
3053
3054         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3055
3056         test_bits = FEATURE_CONTROL_LOCKED;
3057         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3058         if (tboot_enabled())
3059                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3060
3061         if ((old & test_bits) != test_bits) {
3062                 /* enable and lock */
3063                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3064         }
3065         cr4_set_bits(X86_CR4_VMXE);
3066
3067         if (vmm_exclusive) {
3068                 kvm_cpu_vmxon(phys_addr);
3069                 ept_sync_global();
3070         }
3071
3072         native_store_gdt(this_cpu_ptr(&host_gdt));
3073
3074         return 0;
3075 }
3076
3077 static void vmclear_local_loaded_vmcss(void)
3078 {
3079         int cpu = raw_smp_processor_id();
3080         struct loaded_vmcs *v, *n;
3081
3082         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3083                                  loaded_vmcss_on_cpu_link)
3084                 __loaded_vmcs_clear(v);
3085 }
3086
3087
3088 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3089  * tricks.
3090  */
3091 static void kvm_cpu_vmxoff(void)
3092 {
3093         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3094 }
3095
3096 static void hardware_disable(void)
3097 {
3098         if (vmm_exclusive) {
3099                 vmclear_local_loaded_vmcss();
3100                 kvm_cpu_vmxoff();
3101         }
3102         cr4_clear_bits(X86_CR4_VMXE);
3103 }
3104
3105 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3106                                       u32 msr, u32 *result)
3107 {
3108         u32 vmx_msr_low, vmx_msr_high;
3109         u32 ctl = ctl_min | ctl_opt;
3110
3111         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3112
3113         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3114         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3115
3116         /* Ensure minimum (required) set of control bits are supported. */
3117         if (ctl_min & ~ctl)
3118                 return -EIO;
3119
3120         *result = ctl;
3121         return 0;
3122 }
3123
3124 static __init bool allow_1_setting(u32 msr, u32 ctl)
3125 {
3126         u32 vmx_msr_low, vmx_msr_high;
3127
3128         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3129         return vmx_msr_high & ctl;
3130 }
3131
3132 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3133 {
3134         u32 vmx_msr_low, vmx_msr_high;
3135         u32 min, opt, min2, opt2;
3136         u32 _pin_based_exec_control = 0;
3137         u32 _cpu_based_exec_control = 0;
3138         u32 _cpu_based_2nd_exec_control = 0;
3139         u32 _vmexit_control = 0;
3140         u32 _vmentry_control = 0;
3141
3142         min = CPU_BASED_HLT_EXITING |
3143 #ifdef CONFIG_X86_64
3144               CPU_BASED_CR8_LOAD_EXITING |
3145               CPU_BASED_CR8_STORE_EXITING |
3146 #endif
3147               CPU_BASED_CR3_LOAD_EXITING |
3148               CPU_BASED_CR3_STORE_EXITING |
3149               CPU_BASED_USE_IO_BITMAPS |
3150               CPU_BASED_MOV_DR_EXITING |
3151               CPU_BASED_USE_TSC_OFFSETING |
3152               CPU_BASED_MWAIT_EXITING |
3153               CPU_BASED_MONITOR_EXITING |
3154               CPU_BASED_INVLPG_EXITING |
3155               CPU_BASED_RDPMC_EXITING;
3156
3157         opt = CPU_BASED_TPR_SHADOW |
3158               CPU_BASED_USE_MSR_BITMAPS |
3159               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3160         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3161                                 &_cpu_based_exec_control) < 0)
3162                 return -EIO;
3163 #ifdef CONFIG_X86_64
3164         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3165                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3166                                            ~CPU_BASED_CR8_STORE_EXITING;
3167 #endif
3168         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3169                 min2 = 0;
3170                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3171                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3172                         SECONDARY_EXEC_WBINVD_EXITING |
3173                         SECONDARY_EXEC_ENABLE_VPID |
3174                         SECONDARY_EXEC_ENABLE_EPT |
3175                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3176                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3177                         SECONDARY_EXEC_RDTSCP |
3178                         SECONDARY_EXEC_ENABLE_INVPCID |
3179                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3180                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3181                         SECONDARY_EXEC_SHADOW_VMCS |
3182                         SECONDARY_EXEC_XSAVES |
3183                         SECONDARY_EXEC_ENABLE_PML |
3184                         SECONDARY_EXEC_PCOMMIT |
3185                         SECONDARY_EXEC_TSC_SCALING;
3186                 if (adjust_vmx_controls(min2, opt2,
3187                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3188                                         &_cpu_based_2nd_exec_control) < 0)
3189                         return -EIO;
3190         }
3191 #ifndef CONFIG_X86_64
3192         if (!(_cpu_based_2nd_exec_control &
3193                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3194                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3195 #endif
3196
3197         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3198                 _cpu_based_2nd_exec_control &= ~(
3199                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3200                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3201                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3202
3203         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3204                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3205                    enabled */
3206                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3207                                              CPU_BASED_CR3_STORE_EXITING |
3208                                              CPU_BASED_INVLPG_EXITING);
3209                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3210                       vmx_capability.ept, vmx_capability.vpid);
3211         }
3212
3213         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3214 #ifdef CONFIG_X86_64
3215         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3216 #endif
3217         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3218                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3219         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3220                                 &_vmexit_control) < 0)
3221                 return -EIO;
3222
3223         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3224         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3225         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3226                                 &_pin_based_exec_control) < 0)
3227                 return -EIO;
3228
3229         if (!(_cpu_based_2nd_exec_control &
3230                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3231                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3232                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3233
3234         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3235         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3236         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3237                                 &_vmentry_control) < 0)
3238                 return -EIO;
3239
3240         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3241
3242         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3243         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3244                 return -EIO;
3245
3246 #ifdef CONFIG_X86_64
3247         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3248         if (vmx_msr_high & (1u<<16))
3249                 return -EIO;
3250 #endif
3251
3252         /* Require Write-Back (WB) memory type for VMCS accesses. */
3253         if (((vmx_msr_high >> 18) & 15) != 6)
3254                 return -EIO;
3255
3256         vmcs_conf->size = vmx_msr_high & 0x1fff;
3257         vmcs_conf->order = get_order(vmcs_config.size);
3258         vmcs_conf->revision_id = vmx_msr_low;
3259
3260         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3261         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3262         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3263         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3264         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3265
3266         cpu_has_load_ia32_efer =
3267                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3268                                 VM_ENTRY_LOAD_IA32_EFER)
3269                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3270                                    VM_EXIT_LOAD_IA32_EFER);
3271
3272         cpu_has_load_perf_global_ctrl =
3273                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3274                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3275                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3276                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3277
3278         /*
3279          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3280          * but due to arrata below it can't be used. Workaround is to use
3281          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3282          *
3283          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3284          *
3285          * AAK155             (model 26)
3286          * AAP115             (model 30)
3287          * AAT100             (model 37)
3288          * BC86,AAY89,BD102   (model 44)
3289          * BA97               (model 46)
3290          *
3291          */
3292         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3293                 switch (boot_cpu_data.x86_model) {
3294                 case 26:
3295                 case 30:
3296                 case 37:
3297                 case 44:
3298                 case 46:
3299                         cpu_has_load_perf_global_ctrl = false;
3300                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3301                                         "does not work properly. Using workaround\n");
3302                         break;
3303                 default:
3304                         break;
3305                 }
3306         }
3307
3308         if (cpu_has_xsaves)
3309                 rdmsrl(MSR_IA32_XSS, host_xss);
3310
3311         return 0;
3312 }
3313
3314 static struct vmcs *alloc_vmcs_cpu(int cpu)
3315 {
3316         int node = cpu_to_node(cpu);
3317         struct page *pages;
3318         struct vmcs *vmcs;
3319
3320         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3321         if (!pages)
3322                 return NULL;
3323         vmcs = page_address(pages);
3324         memset(vmcs, 0, vmcs_config.size);
3325         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3326         return vmcs;
3327 }
3328
3329 static struct vmcs *alloc_vmcs(void)
3330 {
3331         return alloc_vmcs_cpu(raw_smp_processor_id());
3332 }
3333
3334 static void free_vmcs(struct vmcs *vmcs)
3335 {
3336         free_pages((unsigned long)vmcs, vmcs_config.order);
3337 }
3338
3339 /*
3340  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3341  */
3342 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3343 {
3344         if (!loaded_vmcs->vmcs)
3345                 return;
3346         loaded_vmcs_clear(loaded_vmcs);
3347         free_vmcs(loaded_vmcs->vmcs);
3348         loaded_vmcs->vmcs = NULL;
3349 }
3350
3351 static void free_kvm_area(void)
3352 {
3353         int cpu;
3354
3355         for_each_possible_cpu(cpu) {
3356                 free_vmcs(per_cpu(vmxarea, cpu));
3357                 per_cpu(vmxarea, cpu) = NULL;
3358         }
3359 }
3360
3361 static void init_vmcs_shadow_fields(void)
3362 {
3363         int i, j;
3364
3365         /* No checks for read only fields yet */
3366
3367         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3368                 switch (shadow_read_write_fields[i]) {
3369                 case GUEST_BNDCFGS:
3370                         if (!kvm_mpx_supported())
3371                                 continue;
3372                         break;
3373                 default:
3374                         break;
3375                 }
3376
3377                 if (j < i)
3378                         shadow_read_write_fields[j] =
3379                                 shadow_read_write_fields[i];
3380                 j++;
3381         }
3382         max_shadow_read_write_fields = j;
3383
3384         /* shadowed fields guest access without vmexit */
3385         for (i = 0; i < max_shadow_read_write_fields; i++) {
3386                 clear_bit(shadow_read_write_fields[i],
3387                           vmx_vmwrite_bitmap);
3388                 clear_bit(shadow_read_write_fields[i],
3389                           vmx_vmread_bitmap);
3390         }
3391         for (i = 0; i < max_shadow_read_only_fields; i++)
3392                 clear_bit(shadow_read_only_fields[i],
3393                           vmx_vmread_bitmap);
3394 }
3395
3396 static __init int alloc_kvm_area(void)
3397 {
3398         int cpu;
3399
3400         for_each_possible_cpu(cpu) {
3401                 struct vmcs *vmcs;
3402
3403                 vmcs = alloc_vmcs_cpu(cpu);
3404                 if (!vmcs) {
3405                         free_kvm_area();
3406                         return -ENOMEM;
3407                 }
3408
3409                 per_cpu(vmxarea, cpu) = vmcs;
3410         }
3411         return 0;
3412 }
3413
3414 static bool emulation_required(struct kvm_vcpu *vcpu)
3415 {
3416         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3417 }
3418
3419 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3420                 struct kvm_segment *save)
3421 {
3422         if (!emulate_invalid_guest_state) {
3423                 /*
3424                  * CS and SS RPL should be equal during guest entry according
3425                  * to VMX spec, but in reality it is not always so. Since vcpu
3426                  * is in the middle of the transition from real mode to
3427                  * protected mode it is safe to assume that RPL 0 is a good
3428                  * default value.
3429                  */
3430                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3431                         save->selector &= ~SEGMENT_RPL_MASK;
3432                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3433                 save->s = 1;
3434         }
3435         vmx_set_segment(vcpu, save, seg);
3436 }
3437
3438 static void enter_pmode(struct kvm_vcpu *vcpu)
3439 {
3440         unsigned long flags;
3441         struct vcpu_vmx *vmx = to_vmx(vcpu);
3442
3443         /*
3444          * Update real mode segment cache. It may be not up-to-date if sement
3445          * register was written while vcpu was in a guest mode.
3446          */
3447         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3448         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3449         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3450         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3451         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3452         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3453
3454         vmx->rmode.vm86_active = 0;
3455
3456         vmx_segment_cache_clear(vmx);
3457
3458         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3459
3460         flags = vmcs_readl(GUEST_RFLAGS);
3461         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3462         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3463         vmcs_writel(GUEST_RFLAGS, flags);
3464
3465         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3466                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3467
3468         update_exception_bitmap(vcpu);
3469
3470         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3471         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3472         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3473         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3474         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3475         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3476 }
3477
3478 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3479 {
3480         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3481         struct kvm_segment var = *save;
3482
3483         var.dpl = 0x3;
3484         if (seg == VCPU_SREG_CS)
3485                 var.type = 0x3;
3486
3487         if (!emulate_invalid_guest_state) {
3488                 var.selector = var.base >> 4;
3489                 var.base = var.base & 0xffff0;
3490                 var.limit = 0xffff;
3491                 var.g = 0;
3492                 var.db = 0;
3493                 var.present = 1;
3494                 var.s = 1;
3495                 var.l = 0;
3496                 var.unusable = 0;
3497                 var.type = 0x3;
3498                 var.avl = 0;
3499                 if (save->base & 0xf)
3500                         printk_once(KERN_WARNING "kvm: segment base is not "
3501                                         "paragraph aligned when entering "
3502                                         "protected mode (seg=%d)", seg);
3503         }
3504
3505         vmcs_write16(sf->selector, var.selector);
3506         vmcs_writel(sf->base, var.base);
3507         vmcs_write32(sf->limit, var.limit);
3508         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3509 }
3510
3511 static void enter_rmode(struct kvm_vcpu *vcpu)
3512 {
3513         unsigned long flags;
3514         struct vcpu_vmx *vmx = to_vmx(vcpu);
3515
3516         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3517         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3518         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3519         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3520         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3521         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3522         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3523
3524         vmx->rmode.vm86_active = 1;
3525
3526         /*
3527          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3528          * vcpu. Warn the user that an update is overdue.
3529          */
3530         if (!vcpu->kvm->arch.tss_addr)
3531                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3532                              "called before entering vcpu\n");
3533
3534         vmx_segment_cache_clear(vmx);
3535
3536         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3537         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3538         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3539
3540         flags = vmcs_readl(GUEST_RFLAGS);
3541         vmx->rmode.save_rflags = flags;
3542
3543         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3544
3545         vmcs_writel(GUEST_RFLAGS, flags);
3546         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3547         update_exception_bitmap(vcpu);
3548
3549         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3550         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3551         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3552         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3553         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3554         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3555
3556         kvm_mmu_reset_context(vcpu);
3557 }
3558
3559 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3560 {
3561         struct vcpu_vmx *vmx = to_vmx(vcpu);
3562         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3563
3564         if (!msr)
3565                 return;
3566
3567         /*
3568          * Force kernel_gs_base reloading before EFER changes, as control
3569          * of this msr depends on is_long_mode().
3570          */
3571         vmx_load_host_state(to_vmx(vcpu));
3572         vcpu->arch.efer = efer;
3573         if (efer & EFER_LMA) {
3574                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3575                 msr->data = efer;
3576         } else {
3577                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3578
3579                 msr->data = efer & ~EFER_LME;
3580         }
3581         setup_msrs(vmx);
3582 }
3583
3584 #ifdef CONFIG_X86_64
3585
3586 static void enter_lmode(struct kvm_vcpu *vcpu)
3587 {
3588         u32 guest_tr_ar;
3589
3590         vmx_segment_cache_clear(to_vmx(vcpu));
3591
3592         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3593         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3594                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3595                                      __func__);
3596                 vmcs_write32(GUEST_TR_AR_BYTES,
3597                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3598                              | VMX_AR_TYPE_BUSY_64_TSS);
3599         }
3600         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3601 }
3602
3603 static void exit_lmode(struct kvm_vcpu *vcpu)
3604 {
3605         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3606         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3607 }
3608
3609 #endif
3610
3611 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3612 {
3613         vpid_sync_context(vpid);
3614         if (enable_ept) {
3615                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3616                         return;
3617                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3618         }
3619 }
3620
3621 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3622 {
3623         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3624 }
3625
3626 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3627 {
3628         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3629
3630         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3631         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3632 }
3633
3634 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3635 {
3636         if (enable_ept && is_paging(vcpu))
3637                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3638         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3639 }
3640
3641 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3642 {
3643         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3644
3645         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3646         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3647 }
3648
3649 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3650 {
3651         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3652
3653         if (!test_bit(VCPU_EXREG_PDPTR,
3654                       (unsigned long *)&vcpu->arch.regs_dirty))
3655                 return;
3656
3657         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3658                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3659                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3660                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3661                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3662         }
3663 }
3664
3665 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3666 {
3667         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3668
3669         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3670                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3671                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3672                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3673                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3674         }
3675
3676         __set_bit(VCPU_EXREG_PDPTR,
3677                   (unsigned long *)&vcpu->arch.regs_avail);
3678         __set_bit(VCPU_EXREG_PDPTR,
3679                   (unsigned long *)&vcpu->arch.regs_dirty);
3680 }
3681
3682 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3683
3684 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3685                                         unsigned long cr0,
3686                                         struct kvm_vcpu *vcpu)
3687 {
3688         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3689                 vmx_decache_cr3(vcpu);
3690         if (!(cr0 & X86_CR0_PG)) {
3691                 /* From paging/starting to nonpaging */
3692                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3693                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3694                              (CPU_BASED_CR3_LOAD_EXITING |
3695                               CPU_BASED_CR3_STORE_EXITING));
3696                 vcpu->arch.cr0 = cr0;
3697                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3698         } else if (!is_paging(vcpu)) {
3699                 /* From nonpaging to paging */
3700                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3701                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3702                              ~(CPU_BASED_CR3_LOAD_EXITING |
3703                                CPU_BASED_CR3_STORE_EXITING));
3704                 vcpu->arch.cr0 = cr0;
3705                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3706         }
3707
3708         if (!(cr0 & X86_CR0_WP))
3709                 *hw_cr0 &= ~X86_CR0_WP;
3710 }
3711
3712 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3713 {
3714         struct vcpu_vmx *vmx = to_vmx(vcpu);
3715         unsigned long hw_cr0;
3716
3717         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3718         if (enable_unrestricted_guest)
3719                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3720         else {
3721                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3722
3723                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3724                         enter_pmode(vcpu);
3725
3726                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3727                         enter_rmode(vcpu);
3728         }
3729
3730 #ifdef CONFIG_X86_64
3731         if (vcpu->arch.efer & EFER_LME) {
3732                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3733                         enter_lmode(vcpu);
3734                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3735                         exit_lmode(vcpu);
3736         }
3737 #endif
3738
3739         if (enable_ept)
3740                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3741
3742         if (!vcpu->fpu_active)
3743                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3744
3745         vmcs_writel(CR0_READ_SHADOW, cr0);
3746         vmcs_writel(GUEST_CR0, hw_cr0);
3747         vcpu->arch.cr0 = cr0;
3748
3749         /* depends on vcpu->arch.cr0 to be set to a new value */
3750         vmx->emulation_required = emulation_required(vcpu);
3751 }
3752
3753 static u64 construct_eptp(unsigned long root_hpa)
3754 {
3755         u64 eptp;
3756
3757         /* TODO write the value reading from MSR */
3758         eptp = VMX_EPT_DEFAULT_MT |
3759                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3760         if (enable_ept_ad_bits)
3761                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3762         eptp |= (root_hpa & PAGE_MASK);
3763
3764         return eptp;
3765 }
3766
3767 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3768 {
3769         unsigned long guest_cr3;
3770         u64 eptp;
3771
3772         guest_cr3 = cr3;
3773         if (enable_ept) {
3774                 eptp = construct_eptp(cr3);
3775                 vmcs_write64(EPT_POINTER, eptp);
3776                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3777                         guest_cr3 = kvm_read_cr3(vcpu);
3778                 else
3779                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3780                 ept_load_pdptrs(vcpu);
3781         }
3782
3783         vmx_flush_tlb(vcpu);
3784         vmcs_writel(GUEST_CR3, guest_cr3);
3785 }
3786
3787 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3788 {
3789         /*
3790          * Pass through host's Machine Check Enable value to hw_cr4, which
3791          * is in force while we are in guest mode.  Do not let guests control
3792          * this bit, even if host CR4.MCE == 0.
3793          */
3794         unsigned long hw_cr4 =
3795                 (cr4_read_shadow() & X86_CR4_MCE) |
3796                 (cr4 & ~X86_CR4_MCE) |
3797                 (to_vmx(vcpu)->rmode.vm86_active ?
3798                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3799
3800         if (cr4 & X86_CR4_VMXE) {
3801                 /*
3802                  * To use VMXON (and later other VMX instructions), a guest
3803                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3804                  * So basically the check on whether to allow nested VMX
3805                  * is here.
3806                  */
3807                 if (!nested_vmx_allowed(vcpu))
3808                         return 1;
3809         }
3810         if (to_vmx(vcpu)->nested.vmxon &&
3811             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3812                 return 1;
3813
3814         vcpu->arch.cr4 = cr4;
3815         if (enable_ept) {
3816                 if (!is_paging(vcpu)) {
3817                         hw_cr4 &= ~X86_CR4_PAE;
3818                         hw_cr4 |= X86_CR4_PSE;
3819                 } else if (!(cr4 & X86_CR4_PAE)) {
3820                         hw_cr4 &= ~X86_CR4_PAE;
3821                 }
3822         }
3823
3824         if (!enable_unrestricted_guest && !is_paging(vcpu))
3825                 /*
3826                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3827                  * hardware.  However KVM always uses paging mode without
3828                  * unrestricted guest.
3829                  * To emulate this behavior, SMEP/SMAP needs to be manually
3830                  * disabled when guest switches to non-paging mode.
3831                  */
3832                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3833
3834         vmcs_writel(CR4_READ_SHADOW, cr4);
3835         vmcs_writel(GUEST_CR4, hw_cr4);
3836         return 0;
3837 }
3838
3839 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3840                             struct kvm_segment *var, int seg)
3841 {
3842         struct vcpu_vmx *vmx = to_vmx(vcpu);
3843         u32 ar;
3844
3845         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3846                 *var = vmx->rmode.segs[seg];
3847                 if (seg == VCPU_SREG_TR
3848                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3849                         return;
3850                 var->base = vmx_read_guest_seg_base(vmx, seg);
3851                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3852                 return;
3853         }
3854         var->base = vmx_read_guest_seg_base(vmx, seg);
3855         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3856         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3857         ar = vmx_read_guest_seg_ar(vmx, seg);
3858         var->unusable = (ar >> 16) & 1;
3859         var->type = ar & 15;
3860         var->s = (ar >> 4) & 1;
3861         var->dpl = (ar >> 5) & 3;
3862         /*
3863          * Some userspaces do not preserve unusable property. Since usable
3864          * segment has to be present according to VMX spec we can use present
3865          * property to amend userspace bug by making unusable segment always
3866          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3867          * segment as unusable.
3868          */
3869         var->present = !var->unusable;
3870         var->avl = (ar >> 12) & 1;
3871         var->l = (ar >> 13) & 1;
3872         var->db = (ar >> 14) & 1;
3873         var->g = (ar >> 15) & 1;
3874 }
3875
3876 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3877 {
3878         struct kvm_segment s;
3879
3880         if (to_vmx(vcpu)->rmode.vm86_active) {
3881                 vmx_get_segment(vcpu, &s, seg);
3882                 return s.base;
3883         }
3884         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3885 }
3886
3887 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3888 {
3889         struct vcpu_vmx *vmx = to_vmx(vcpu);
3890
3891         if (unlikely(vmx->rmode.vm86_active))
3892                 return 0;
3893         else {
3894                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3895                 return VMX_AR_DPL(ar);
3896         }
3897 }
3898
3899 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3900 {
3901         u32 ar;
3902
3903         if (var->unusable || !var->present)
3904                 ar = 1 << 16;
3905         else {
3906                 ar = var->type & 15;
3907                 ar |= (var->s & 1) << 4;
3908                 ar |= (var->dpl & 3) << 5;
3909                 ar |= (var->present & 1) << 7;
3910                 ar |= (var->avl & 1) << 12;
3911                 ar |= (var->l & 1) << 13;
3912                 ar |= (var->db & 1) << 14;
3913                 ar |= (var->g & 1) << 15;
3914         }
3915
3916         return ar;
3917 }
3918
3919 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3920                             struct kvm_segment *var, int seg)
3921 {
3922         struct vcpu_vmx *vmx = to_vmx(vcpu);
3923         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3924
3925         vmx_segment_cache_clear(vmx);
3926
3927         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3928                 vmx->rmode.segs[seg] = *var;
3929                 if (seg == VCPU_SREG_TR)
3930                         vmcs_write16(sf->selector, var->selector);
3931                 else if (var->s)
3932                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3933                 goto out;
3934         }
3935
3936         vmcs_writel(sf->base, var->base);
3937         vmcs_write32(sf->limit, var->limit);
3938         vmcs_write16(sf->selector, var->selector);
3939
3940         /*
3941          *   Fix the "Accessed" bit in AR field of segment registers for older
3942          * qemu binaries.
3943          *   IA32 arch specifies that at the time of processor reset the
3944          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3945          * is setting it to 0 in the userland code. This causes invalid guest
3946          * state vmexit when "unrestricted guest" mode is turned on.
3947          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3948          * tree. Newer qemu binaries with that qemu fix would not need this
3949          * kvm hack.
3950          */
3951         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3952                 var->type |= 0x1; /* Accessed */
3953
3954         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3955
3956 out:
3957         vmx->emulation_required = emulation_required(vcpu);
3958 }
3959
3960 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3961 {
3962         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3963
3964         *db = (ar >> 14) & 1;
3965         *l = (ar >> 13) & 1;
3966 }
3967
3968 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3969 {
3970         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3971         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3972 }
3973
3974 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3975 {
3976         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3977         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3978 }
3979
3980 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3981 {
3982         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3983         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3984 }
3985
3986 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3987 {
3988         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3989         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3990 }
3991
3992 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3993 {
3994         struct kvm_segment var;
3995         u32 ar;
3996
3997         vmx_get_segment(vcpu, &var, seg);
3998         var.dpl = 0x3;
3999         if (seg == VCPU_SREG_CS)
4000                 var.type = 0x3;
4001         ar = vmx_segment_access_rights(&var);
4002
4003         if (var.base != (var.selector << 4))
4004                 return false;
4005         if (var.limit != 0xffff)
4006                 return false;
4007         if (ar != 0xf3)
4008                 return false;
4009
4010         return true;
4011 }
4012
4013 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4014 {
4015         struct kvm_segment cs;
4016         unsigned int cs_rpl;
4017
4018         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4019         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4020
4021         if (cs.unusable)
4022                 return false;
4023         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4024                 return false;
4025         if (!cs.s)
4026                 return false;
4027         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4028                 if (cs.dpl > cs_rpl)
4029                         return false;
4030         } else {
4031                 if (cs.dpl != cs_rpl)
4032                         return false;
4033         }
4034         if (!cs.present)
4035                 return false;
4036
4037         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4038         return true;
4039 }
4040
4041 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4042 {
4043         struct kvm_segment ss;
4044         unsigned int ss_rpl;
4045
4046         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4047         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4048
4049         if (ss.unusable)
4050                 return true;
4051         if (ss.type != 3 && ss.type != 7)
4052                 return false;
4053         if (!ss.s)
4054                 return false;
4055         if (ss.dpl != ss_rpl) /* DPL != RPL */
4056                 return false;
4057         if (!ss.present)
4058                 return false;
4059
4060         return true;
4061 }
4062
4063 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4064 {
4065         struct kvm_segment var;
4066         unsigned int rpl;
4067
4068         vmx_get_segment(vcpu, &var, seg);
4069         rpl = var.selector & SEGMENT_RPL_MASK;
4070
4071         if (var.unusable)
4072                 return true;
4073         if (!var.s)
4074                 return false;
4075         if (!var.present)
4076                 return false;
4077         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4078                 if (var.dpl < rpl) /* DPL < RPL */
4079                         return false;
4080         }
4081
4082         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4083          * rights flags
4084          */
4085         return true;
4086 }
4087
4088 static bool tr_valid(struct kvm_vcpu *vcpu)
4089 {
4090         struct kvm_segment tr;
4091
4092         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4093
4094         if (tr.unusable)
4095                 return false;
4096         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4097                 return false;
4098         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4099                 return false;
4100         if (!tr.present)
4101                 return false;
4102
4103         return true;
4104 }
4105
4106 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4107 {
4108         struct kvm_segment ldtr;
4109
4110         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4111
4112         if (ldtr.unusable)
4113                 return true;
4114         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4115                 return false;
4116         if (ldtr.type != 2)
4117                 return false;
4118         if (!ldtr.present)
4119                 return false;
4120
4121         return true;
4122 }
4123
4124 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4125 {
4126         struct kvm_segment cs, ss;
4127
4128         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4129         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4130
4131         return ((cs.selector & SEGMENT_RPL_MASK) ==
4132                  (ss.selector & SEGMENT_RPL_MASK));
4133 }
4134
4135 /*
4136  * Check if guest state is valid. Returns true if valid, false if
4137  * not.
4138  * We assume that registers are always usable
4139  */
4140 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4141 {
4142         if (enable_unrestricted_guest)
4143                 return true;
4144
4145         /* real mode guest state checks */
4146         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4147                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4148                         return false;
4149                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4150                         return false;
4151                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4152                         return false;
4153                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4154                         return false;
4155                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4156                         return false;
4157                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4158                         return false;
4159         } else {
4160         /* protected mode guest state checks */
4161                 if (!cs_ss_rpl_check(vcpu))
4162                         return false;
4163                 if (!code_segment_valid(vcpu))
4164                         return false;
4165                 if (!stack_segment_valid(vcpu))
4166                         return false;
4167                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4168                         return false;
4169                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4170                         return false;
4171                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4172                         return false;
4173                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4174                         return false;
4175                 if (!tr_valid(vcpu))
4176                         return false;
4177                 if (!ldtr_valid(vcpu))
4178                         return false;
4179         }
4180         /* TODO:
4181          * - Add checks on RIP
4182          * - Add checks on RFLAGS
4183          */
4184
4185         return true;
4186 }
4187
4188 static int init_rmode_tss(struct kvm *kvm)
4189 {
4190         gfn_t fn;
4191         u16 data = 0;
4192         int idx, r;
4193
4194         idx = srcu_read_lock(&kvm->srcu);
4195         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4196         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4197         if (r < 0)
4198                 goto out;
4199         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4200         r = kvm_write_guest_page(kvm, fn++, &data,
4201                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4202         if (r < 0)
4203                 goto out;
4204         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4205         if (r < 0)
4206                 goto out;
4207         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4208         if (r < 0)
4209                 goto out;
4210         data = ~0;
4211         r = kvm_write_guest_page(kvm, fn, &data,
4212                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4213                                  sizeof(u8));
4214 out:
4215         srcu_read_unlock(&kvm->srcu, idx);
4216         return r;
4217 }
4218
4219 static int init_rmode_identity_map(struct kvm *kvm)
4220 {
4221         int i, idx, r = 0;
4222         pfn_t identity_map_pfn;
4223         u32 tmp;
4224
4225         if (!enable_ept)
4226                 return 0;
4227
4228         /* Protect kvm->arch.ept_identity_pagetable_done. */
4229         mutex_lock(&kvm->slots_lock);
4230
4231         if (likely(kvm->arch.ept_identity_pagetable_done))
4232                 goto out2;
4233
4234         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4235
4236         r = alloc_identity_pagetable(kvm);
4237         if (r < 0)
4238                 goto out2;
4239
4240         idx = srcu_read_lock(&kvm->srcu);
4241         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4242         if (r < 0)
4243                 goto out;
4244         /* Set up identity-mapping pagetable for EPT in real mode */
4245         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4246                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4247                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4248                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4249                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4250                 if (r < 0)
4251                         goto out;
4252         }
4253         kvm->arch.ept_identity_pagetable_done = true;
4254
4255 out:
4256         srcu_read_unlock(&kvm->srcu, idx);
4257
4258 out2:
4259         mutex_unlock(&kvm->slots_lock);
4260         return r;
4261 }
4262
4263 static void seg_setup(int seg)
4264 {
4265         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4266         unsigned int ar;
4267
4268         vmcs_write16(sf->selector, 0);
4269         vmcs_writel(sf->base, 0);
4270         vmcs_write32(sf->limit, 0xffff);
4271         ar = 0x93;
4272         if (seg == VCPU_SREG_CS)
4273                 ar |= 0x08; /* code segment */
4274
4275         vmcs_write32(sf->ar_bytes, ar);
4276 }
4277
4278 static int alloc_apic_access_page(struct kvm *kvm)
4279 {
4280         struct page *page;
4281         int r = 0;
4282
4283         mutex_lock(&kvm->slots_lock);
4284         if (kvm->arch.apic_access_page_done)
4285                 goto out;
4286         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4287                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4288         if (r)
4289                 goto out;
4290
4291         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4292         if (is_error_page(page)) {
4293                 r = -EFAULT;
4294                 goto out;
4295         }
4296
4297         /*
4298          * Do not pin the page in memory, so that memory hot-unplug
4299          * is able to migrate it.
4300          */
4301         put_page(page);
4302         kvm->arch.apic_access_page_done = true;
4303 out:
4304         mutex_unlock(&kvm->slots_lock);
4305         return r;
4306 }
4307
4308 static int alloc_identity_pagetable(struct kvm *kvm)
4309 {
4310         /* Called with kvm->slots_lock held. */
4311
4312         int r = 0;
4313
4314         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4315
4316         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4317                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4318
4319         return r;
4320 }
4321
4322 static int allocate_vpid(void)
4323 {
4324         int vpid;
4325
4326         if (!enable_vpid)
4327                 return 0;
4328         spin_lock(&vmx_vpid_lock);
4329         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4330         if (vpid < VMX_NR_VPIDS)
4331                 __set_bit(vpid, vmx_vpid_bitmap);
4332         else
4333                 vpid = 0;
4334         spin_unlock(&vmx_vpid_lock);
4335         return vpid;
4336 }
4337
4338 static void free_vpid(int vpid)
4339 {
4340         if (!enable_vpid || vpid == 0)
4341                 return;
4342         spin_lock(&vmx_vpid_lock);
4343         __clear_bit(vpid, vmx_vpid_bitmap);
4344         spin_unlock(&vmx_vpid_lock);
4345 }
4346
4347 #define MSR_TYPE_R      1
4348 #define MSR_TYPE_W      2
4349 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4350                                                 u32 msr, int type)
4351 {
4352         int f = sizeof(unsigned long);
4353
4354         if (!cpu_has_vmx_msr_bitmap())
4355                 return;
4356
4357         /*
4358          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4359          * have the write-low and read-high bitmap offsets the wrong way round.
4360          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4361          */
4362         if (msr <= 0x1fff) {
4363                 if (type & MSR_TYPE_R)
4364                         /* read-low */
4365                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4366
4367                 if (type & MSR_TYPE_W)
4368                         /* write-low */
4369                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4370
4371         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4372                 msr &= 0x1fff;
4373                 if (type & MSR_TYPE_R)
4374                         /* read-high */
4375                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4376
4377                 if (type & MSR_TYPE_W)
4378                         /* write-high */
4379                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4380
4381         }
4382 }
4383
4384 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4385                                                 u32 msr, int type)
4386 {
4387         int f = sizeof(unsigned long);
4388
4389         if (!cpu_has_vmx_msr_bitmap())
4390                 return;
4391
4392         /*
4393          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4394          * have the write-low and read-high bitmap offsets the wrong way round.
4395          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4396          */
4397         if (msr <= 0x1fff) {
4398                 if (type & MSR_TYPE_R)
4399                         /* read-low */
4400                         __set_bit(msr, msr_bitmap + 0x000 / f);
4401
4402                 if (type & MSR_TYPE_W)
4403                         /* write-low */
4404                         __set_bit(msr, msr_bitmap + 0x800 / f);
4405
4406         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4407                 msr &= 0x1fff;
4408                 if (type & MSR_TYPE_R)
4409                         /* read-high */
4410                         __set_bit(msr, msr_bitmap + 0x400 / f);
4411
4412                 if (type & MSR_TYPE_W)
4413                         /* write-high */
4414                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4415
4416         }
4417 }
4418
4419 /*
4420  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4421  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4422  */
4423 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4424                                                unsigned long *msr_bitmap_nested,
4425                                                u32 msr, int type)
4426 {
4427         int f = sizeof(unsigned long);
4428
4429         if (!cpu_has_vmx_msr_bitmap()) {
4430                 WARN_ON(1);
4431                 return;
4432         }
4433
4434         /*
4435          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4436          * have the write-low and read-high bitmap offsets the wrong way round.
4437          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4438          */
4439         if (msr <= 0x1fff) {
4440                 if (type & MSR_TYPE_R &&
4441                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4442                         /* read-low */
4443                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4444
4445                 if (type & MSR_TYPE_W &&
4446                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4447                         /* write-low */
4448                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4449
4450         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4451                 msr &= 0x1fff;
4452                 if (type & MSR_TYPE_R &&
4453                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4454                         /* read-high */
4455                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4456
4457                 if (type & MSR_TYPE_W &&
4458                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4459                         /* write-high */
4460                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4461
4462         }
4463 }
4464
4465 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4466 {
4467         if (!longmode_only)
4468                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4469                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4470         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4471                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4472 }
4473
4474 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4475 {
4476         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4477                         msr, MSR_TYPE_R);
4478         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4479                         msr, MSR_TYPE_R);
4480 }
4481
4482 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4483 {
4484         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4485                         msr, MSR_TYPE_R);
4486         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4487                         msr, MSR_TYPE_R);
4488 }
4489
4490 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4491 {
4492         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4493                         msr, MSR_TYPE_W);
4494         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4495                         msr, MSR_TYPE_W);
4496 }
4497
4498 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4499 {
4500         return enable_apicv && lapic_in_kernel(vcpu);
4501 }
4502
4503 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4504 {
4505         struct vcpu_vmx *vmx = to_vmx(vcpu);
4506         int max_irr;
4507         void *vapic_page;
4508         u16 status;
4509
4510         if (vmx->nested.pi_desc &&
4511             vmx->nested.pi_pending) {
4512                 vmx->nested.pi_pending = false;
4513                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4514                         return 0;
4515
4516                 max_irr = find_last_bit(
4517                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4518
4519                 if (max_irr == 256)
4520                         return 0;
4521
4522                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4523                 if (!vapic_page) {
4524                         WARN_ON(1);
4525                         return -ENOMEM;
4526                 }
4527                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4528                 kunmap(vmx->nested.virtual_apic_page);
4529
4530                 status = vmcs_read16(GUEST_INTR_STATUS);
4531                 if ((u8)max_irr > ((u8)status & 0xff)) {
4532                         status &= ~0xff;
4533                         status |= (u8)max_irr;
4534                         vmcs_write16(GUEST_INTR_STATUS, status);
4535                 }
4536         }
4537         return 0;
4538 }
4539
4540 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4541 {
4542 #ifdef CONFIG_SMP
4543         if (vcpu->mode == IN_GUEST_MODE) {
4544                 /*
4545                  * The vector of interrupt to be delivered to vcpu had
4546                  * been set in PIR before this function.
4547                  *
4548                  * Following cases will be reached in this block, and
4549                  * we always send a notification event in all cases as
4550                  * explained below.
4551                  *
4552                  * Case 1: vcpu keeps in non-root mode. Sending a
4553                  * notification event posts the interrupt to vcpu.
4554                  *
4555                  * Case 2: vcpu exits to root mode and is still
4556                  * runnable. PIR will be synced to vIRR before the
4557                  * next vcpu entry. Sending a notification event in
4558                  * this case has no effect, as vcpu is not in root
4559                  * mode.
4560                  *
4561                  * Case 3: vcpu exits to root mode and is blocked.
4562                  * vcpu_block() has already synced PIR to vIRR and
4563                  * never blocks vcpu if vIRR is not cleared. Therefore,
4564                  * a blocked vcpu here does not wait for any requested
4565                  * interrupts in PIR, and sending a notification event
4566                  * which has no effect is safe here.
4567                  */
4568
4569                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4570                                 POSTED_INTR_VECTOR);
4571                 return true;
4572         }
4573 #endif
4574         return false;
4575 }
4576
4577 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4578                                                 int vector)
4579 {
4580         struct vcpu_vmx *vmx = to_vmx(vcpu);
4581
4582         if (is_guest_mode(vcpu) &&
4583             vector == vmx->nested.posted_intr_nv) {
4584                 /* the PIR and ON have been set by L1. */
4585                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4586                 /*
4587                  * If a posted intr is not recognized by hardware,
4588                  * we will accomplish it in the next vmentry.
4589                  */
4590                 vmx->nested.pi_pending = true;
4591                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4592                 return 0;
4593         }
4594         return -1;
4595 }
4596 /*
4597  * Send interrupt to vcpu via posted interrupt way.
4598  * 1. If target vcpu is running(non-root mode), send posted interrupt
4599  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4600  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4601  * interrupt from PIR in next vmentry.
4602  */
4603 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4604 {
4605         struct vcpu_vmx *vmx = to_vmx(vcpu);
4606         int r;
4607
4608         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4609         if (!r)
4610                 return;
4611
4612         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4613                 return;
4614
4615         r = pi_test_and_set_on(&vmx->pi_desc);
4616         kvm_make_request(KVM_REQ_EVENT, vcpu);
4617         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4618                 kvm_vcpu_kick(vcpu);
4619 }
4620
4621 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4622 {
4623         struct vcpu_vmx *vmx = to_vmx(vcpu);
4624
4625         if (!pi_test_and_clear_on(&vmx->pi_desc))
4626                 return;
4627
4628         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4629 }
4630
4631 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4632 {
4633         return;
4634 }
4635
4636 /*
4637  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4638  * will not change in the lifetime of the guest.
4639  * Note that host-state that does change is set elsewhere. E.g., host-state
4640  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4641  */
4642 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4643 {
4644         u32 low32, high32;
4645         unsigned long tmpl;
4646         struct desc_ptr dt;
4647         unsigned long cr4;
4648
4649         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4650         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4651
4652         /* Save the most likely value for this task's CR4 in the VMCS. */
4653         cr4 = cr4_read_shadow();
4654         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4655         vmx->host_state.vmcs_host_cr4 = cr4;
4656
4657         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4658 #ifdef CONFIG_X86_64
4659         /*
4660          * Load null selectors, so we can avoid reloading them in
4661          * __vmx_load_host_state(), in case userspace uses the null selectors
4662          * too (the expected case).
4663          */
4664         vmcs_write16(HOST_DS_SELECTOR, 0);
4665         vmcs_write16(HOST_ES_SELECTOR, 0);
4666 #else
4667         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4668         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4669 #endif
4670         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4671         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4672
4673         native_store_idt(&dt);
4674         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4675         vmx->host_idt_base = dt.address;
4676
4677         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4678
4679         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4680         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4681         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4682         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4683
4684         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4685                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4686                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4687         }
4688 }
4689
4690 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4691 {
4692         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4693         if (enable_ept)
4694                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4695         if (is_guest_mode(&vmx->vcpu))
4696                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4697                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4698         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4699 }
4700
4701 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4702 {
4703         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4704
4705         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4706                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4707         return pin_based_exec_ctrl;
4708 }
4709
4710 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4711 {
4712         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4713
4714         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4715                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4716
4717         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4718                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4719 #ifdef CONFIG_X86_64
4720                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4721                                 CPU_BASED_CR8_LOAD_EXITING;
4722 #endif
4723         }
4724         if (!enable_ept)
4725                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4726                                 CPU_BASED_CR3_LOAD_EXITING  |
4727                                 CPU_BASED_INVLPG_EXITING;
4728         return exec_control;
4729 }
4730
4731 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4732 {
4733         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4734         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4735                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4736         if (vmx->vpid == 0)
4737                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4738         if (!enable_ept) {
4739                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4740                 enable_unrestricted_guest = 0;
4741                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4742                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4743         }
4744         if (!enable_unrestricted_guest)
4745                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4746         if (!ple_gap)
4747                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4748         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4749                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4750                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4751         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4752         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4753            (handle_vmptrld).
4754            We can NOT enable shadow_vmcs here because we don't have yet
4755            a current VMCS12
4756         */
4757         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4758
4759         if (!enable_pml)
4760                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4761
4762         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4763         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4764
4765         return exec_control;
4766 }
4767
4768 static void ept_set_mmio_spte_mask(void)
4769 {
4770         /*
4771          * EPT Misconfigurations can be generated if the value of bits 2:0
4772          * of an EPT paging-structure entry is 110b (write/execute).
4773          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4774          * spte.
4775          */
4776         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4777 }
4778
4779 #define VMX_XSS_EXIT_BITMAP 0
4780 /*
4781  * Sets up the vmcs for emulated real mode.
4782  */
4783 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4784 {
4785 #ifdef CONFIG_X86_64
4786         unsigned long a;
4787 #endif
4788         int i;
4789
4790         /* I/O */
4791         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4792         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4793
4794         if (enable_shadow_vmcs) {
4795                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4796                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4797         }
4798         if (cpu_has_vmx_msr_bitmap())
4799                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4800
4801         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4802
4803         /* Control */
4804         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4805
4806         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4807
4808         if (cpu_has_secondary_exec_ctrls())
4809                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4810                                 vmx_secondary_exec_control(vmx));
4811
4812         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4813                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4814                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4815                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4816                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4817
4818                 vmcs_write16(GUEST_INTR_STATUS, 0);
4819
4820                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4821                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4822         }
4823
4824         if (ple_gap) {
4825                 vmcs_write32(PLE_GAP, ple_gap);
4826                 vmx->ple_window = ple_window;
4827                 vmx->ple_window_dirty = true;
4828         }
4829
4830         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4831         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4832         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4833
4834         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4835         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4836         vmx_set_constant_host_state(vmx);
4837 #ifdef CONFIG_X86_64
4838         rdmsrl(MSR_FS_BASE, a);
4839         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4840         rdmsrl(MSR_GS_BASE, a);
4841         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4842 #else
4843         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4844         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4845 #endif
4846
4847         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4848         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4849         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4850         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4851         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4852
4853         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4854                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4855
4856         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4857                 u32 index = vmx_msr_index[i];
4858                 u32 data_low, data_high;
4859                 int j = vmx->nmsrs;
4860
4861                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4862                         continue;
4863                 if (wrmsr_safe(index, data_low, data_high) < 0)
4864                         continue;
4865                 vmx->guest_msrs[j].index = i;
4866                 vmx->guest_msrs[j].data = 0;
4867                 vmx->guest_msrs[j].mask = -1ull;
4868                 ++vmx->nmsrs;
4869         }
4870
4871
4872         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4873
4874         /* 22.2.1, 20.8.1 */
4875         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4876
4877         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4878         set_cr4_guest_host_mask(vmx);
4879
4880         if (vmx_xsaves_supported())
4881                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4882
4883         if (enable_pml) {
4884                 ASSERT(vmx->pml_pg);
4885                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4886                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4887         }
4888
4889         return 0;
4890 }
4891
4892 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4893 {
4894         struct vcpu_vmx *vmx = to_vmx(vcpu);
4895         struct msr_data apic_base_msr;
4896         u64 cr0;
4897
4898         vmx->rmode.vm86_active = 0;
4899
4900         vmx->soft_vnmi_blocked = 0;
4901
4902         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4903         kvm_set_cr8(vcpu, 0);
4904
4905         if (!init_event) {
4906                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4907                                      MSR_IA32_APICBASE_ENABLE;
4908                 if (kvm_vcpu_is_reset_bsp(vcpu))
4909                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4910                 apic_base_msr.host_initiated = true;
4911                 kvm_set_apic_base(vcpu, &apic_base_msr);
4912         }
4913
4914         vmx_segment_cache_clear(vmx);
4915
4916         seg_setup(VCPU_SREG_CS);
4917         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4918         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4919
4920         seg_setup(VCPU_SREG_DS);
4921         seg_setup(VCPU_SREG_ES);
4922         seg_setup(VCPU_SREG_FS);
4923         seg_setup(VCPU_SREG_GS);
4924         seg_setup(VCPU_SREG_SS);
4925
4926         vmcs_write16(GUEST_TR_SELECTOR, 0);
4927         vmcs_writel(GUEST_TR_BASE, 0);
4928         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4929         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4930
4931         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4932         vmcs_writel(GUEST_LDTR_BASE, 0);
4933         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4934         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4935
4936         if (!init_event) {
4937                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4938                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4939                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4940                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4941         }
4942
4943         vmcs_writel(GUEST_RFLAGS, 0x02);
4944         kvm_rip_write(vcpu, 0xfff0);
4945
4946         vmcs_writel(GUEST_GDTR_BASE, 0);
4947         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4948
4949         vmcs_writel(GUEST_IDTR_BASE, 0);
4950         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4951
4952         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4953         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4954         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4955
4956         setup_msrs(vmx);
4957
4958         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4959
4960         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4961                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4962                 if (cpu_need_tpr_shadow(vcpu))
4963                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4964                                      __pa(vcpu->arch.apic->regs));
4965                 vmcs_write32(TPR_THRESHOLD, 0);
4966         }
4967
4968         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4969
4970         if (vmx_cpu_uses_apicv(vcpu))
4971                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4972
4973         if (vmx->vpid != 0)
4974                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4975
4976         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4977         vmx->vcpu.arch.cr0 = cr0;
4978         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4979         vmx_set_cr4(vcpu, 0);
4980         vmx_set_efer(vcpu, 0);
4981         vmx_fpu_activate(vcpu);
4982         update_exception_bitmap(vcpu);
4983
4984         vpid_sync_context(vmx->vpid);
4985 }
4986
4987 /*
4988  * In nested virtualization, check if L1 asked to exit on external interrupts.
4989  * For most existing hypervisors, this will always return true.
4990  */
4991 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4992 {
4993         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4994                 PIN_BASED_EXT_INTR_MASK;
4995 }
4996
4997 /*
4998  * In nested virtualization, check if L1 has set
4999  * VM_EXIT_ACK_INTR_ON_EXIT
5000  */
5001 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5002 {
5003         return get_vmcs12(vcpu)->vm_exit_controls &
5004                 VM_EXIT_ACK_INTR_ON_EXIT;
5005 }
5006
5007 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5008 {
5009         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5010                 PIN_BASED_NMI_EXITING;
5011 }
5012
5013 static void enable_irq_window(struct kvm_vcpu *vcpu)
5014 {
5015         u32 cpu_based_vm_exec_control;
5016
5017         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5018         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5019         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5020 }
5021
5022 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5023 {
5024         u32 cpu_based_vm_exec_control;
5025
5026         if (!cpu_has_virtual_nmis() ||
5027             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5028                 enable_irq_window(vcpu);
5029                 return;
5030         }
5031
5032         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5033         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5034         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5035 }
5036
5037 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5038 {
5039         struct vcpu_vmx *vmx = to_vmx(vcpu);
5040         uint32_t intr;
5041         int irq = vcpu->arch.interrupt.nr;
5042
5043         trace_kvm_inj_virq(irq);
5044
5045         ++vcpu->stat.irq_injections;
5046         if (vmx->rmode.vm86_active) {
5047                 int inc_eip = 0;
5048                 if (vcpu->arch.interrupt.soft)
5049                         inc_eip = vcpu->arch.event_exit_inst_len;
5050                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5051                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5052                 return;
5053         }
5054         intr = irq | INTR_INFO_VALID_MASK;
5055         if (vcpu->arch.interrupt.soft) {
5056                 intr |= INTR_TYPE_SOFT_INTR;
5057                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5058                              vmx->vcpu.arch.event_exit_inst_len);
5059         } else
5060                 intr |= INTR_TYPE_EXT_INTR;
5061         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5062 }
5063
5064 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5065 {
5066         struct vcpu_vmx *vmx = to_vmx(vcpu);
5067
5068         if (is_guest_mode(vcpu))
5069                 return;
5070
5071         if (!cpu_has_virtual_nmis()) {
5072                 /*
5073                  * Tracking the NMI-blocked state in software is built upon
5074                  * finding the next open IRQ window. This, in turn, depends on
5075                  * well-behaving guests: They have to keep IRQs disabled at
5076                  * least as long as the NMI handler runs. Otherwise we may
5077                  * cause NMI nesting, maybe breaking the guest. But as this is
5078                  * highly unlikely, we can live with the residual risk.
5079                  */
5080                 vmx->soft_vnmi_blocked = 1;
5081                 vmx->vnmi_blocked_time = 0;
5082         }
5083
5084         ++vcpu->stat.nmi_injections;
5085         vmx->nmi_known_unmasked = false;
5086         if (vmx->rmode.vm86_active) {
5087                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5088                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5089                 return;
5090         }
5091         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5092                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5093 }
5094
5095 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5096 {
5097         if (!cpu_has_virtual_nmis())
5098                 return to_vmx(vcpu)->soft_vnmi_blocked;
5099         if (to_vmx(vcpu)->nmi_known_unmasked)
5100                 return false;
5101         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5102 }
5103
5104 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5105 {
5106         struct vcpu_vmx *vmx = to_vmx(vcpu);
5107
5108         if (!cpu_has_virtual_nmis()) {
5109                 if (vmx->soft_vnmi_blocked != masked) {
5110                         vmx->soft_vnmi_blocked = masked;
5111                         vmx->vnmi_blocked_time = 0;
5112                 }
5113         } else {
5114                 vmx->nmi_known_unmasked = !masked;
5115                 if (masked)
5116                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5117                                       GUEST_INTR_STATE_NMI);
5118                 else
5119                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5120                                         GUEST_INTR_STATE_NMI);
5121         }
5122 }
5123
5124 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5125 {
5126         if (to_vmx(vcpu)->nested.nested_run_pending)
5127                 return 0;
5128
5129         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5130                 return 0;
5131
5132         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5133                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5134                    | GUEST_INTR_STATE_NMI));
5135 }
5136
5137 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5138 {
5139         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5140                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5141                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5142                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5143 }
5144
5145 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5146 {
5147         int ret;
5148
5149         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5150                                     PAGE_SIZE * 3);
5151         if (ret)
5152                 return ret;
5153         kvm->arch.tss_addr = addr;
5154         return init_rmode_tss(kvm);
5155 }
5156
5157 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5158 {
5159         switch (vec) {
5160         case BP_VECTOR:
5161                 /*
5162                  * Update instruction length as we may reinject the exception
5163                  * from user space while in guest debugging mode.
5164                  */
5165                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5166                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5167                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5168                         return false;
5169                 /* fall through */
5170         case DB_VECTOR:
5171                 if (vcpu->guest_debug &
5172                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5173                         return false;
5174                 /* fall through */
5175         case DE_VECTOR:
5176         case OF_VECTOR:
5177         case BR_VECTOR:
5178         case UD_VECTOR:
5179         case DF_VECTOR:
5180         case SS_VECTOR:
5181         case GP_VECTOR:
5182         case MF_VECTOR:
5183                 return true;
5184         break;
5185         }
5186         return false;
5187 }
5188
5189 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5190                                   int vec, u32 err_code)
5191 {
5192         /*
5193          * Instruction with address size override prefix opcode 0x67
5194          * Cause the #SS fault with 0 error code in VM86 mode.
5195          */
5196         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5197                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5198                         if (vcpu->arch.halt_request) {
5199                                 vcpu->arch.halt_request = 0;
5200                                 return kvm_vcpu_halt(vcpu);
5201                         }
5202                         return 1;
5203                 }
5204                 return 0;
5205         }
5206
5207         /*
5208          * Forward all other exceptions that are valid in real mode.
5209          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5210          *        the required debugging infrastructure rework.
5211          */
5212         kvm_queue_exception(vcpu, vec);
5213         return 1;
5214 }
5215
5216 /*
5217  * Trigger machine check on the host. We assume all the MSRs are already set up
5218  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5219  * We pass a fake environment to the machine check handler because we want
5220  * the guest to be always treated like user space, no matter what context
5221  * it used internally.
5222  */
5223 static void kvm_machine_check(void)
5224 {
5225 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5226         struct pt_regs regs = {
5227                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5228                 .flags = X86_EFLAGS_IF,
5229         };
5230
5231         do_machine_check(&regs, 0);
5232 #endif
5233 }
5234
5235 static int handle_machine_check(struct kvm_vcpu *vcpu)
5236 {
5237         /* already handled by vcpu_run */
5238         return 1;
5239 }
5240
5241 static int handle_exception(struct kvm_vcpu *vcpu)
5242 {
5243         struct vcpu_vmx *vmx = to_vmx(vcpu);
5244         struct kvm_run *kvm_run = vcpu->run;
5245         u32 intr_info, ex_no, error_code;
5246         unsigned long cr2, rip, dr6;
5247         u32 vect_info;
5248         enum emulation_result er;
5249
5250         vect_info = vmx->idt_vectoring_info;
5251         intr_info = vmx->exit_intr_info;
5252
5253         if (is_machine_check(intr_info))
5254                 return handle_machine_check(vcpu);
5255
5256         if (is_nmi(intr_info))
5257                 return 1;  /* already handled by vmx_vcpu_run() */
5258
5259         if (is_no_device(intr_info)) {
5260                 vmx_fpu_activate(vcpu);
5261                 return 1;
5262         }
5263
5264         if (is_invalid_opcode(intr_info)) {
5265                 if (is_guest_mode(vcpu)) {
5266                         kvm_queue_exception(vcpu, UD_VECTOR);
5267                         return 1;
5268                 }
5269                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5270                 if (er == EMULATE_USER_EXIT)
5271                         return 0;
5272                 if (er != EMULATE_DONE)
5273                         kvm_queue_exception(vcpu, UD_VECTOR);
5274                 return 1;
5275         }
5276
5277         error_code = 0;
5278         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5279                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5280
5281         /*
5282          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5283          * MMIO, it is better to report an internal error.
5284          * See the comments in vmx_handle_exit.
5285          */
5286         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5287             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5288                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5289                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5290                 vcpu->run->internal.ndata = 3;
5291                 vcpu->run->internal.data[0] = vect_info;
5292                 vcpu->run->internal.data[1] = intr_info;
5293                 vcpu->run->internal.data[2] = error_code;
5294                 return 0;
5295         }
5296
5297         if (is_page_fault(intr_info)) {
5298                 /* EPT won't cause page fault directly */
5299                 BUG_ON(enable_ept);
5300                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5301                 trace_kvm_page_fault(cr2, error_code);
5302
5303                 if (kvm_event_needs_reinjection(vcpu))
5304                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5305                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5306         }
5307
5308         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5309
5310         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5311                 return handle_rmode_exception(vcpu, ex_no, error_code);
5312
5313         switch (ex_no) {
5314         case AC_VECTOR:
5315                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5316                 return 1;
5317         case DB_VECTOR:
5318                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5319                 if (!(vcpu->guest_debug &
5320                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5321                         vcpu->arch.dr6 &= ~15;
5322                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5323                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5324                                 skip_emulated_instruction(vcpu);
5325
5326                         kvm_queue_exception(vcpu, DB_VECTOR);
5327                         return 1;
5328                 }
5329                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5330                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5331                 /* fall through */
5332         case BP_VECTOR:
5333                 /*
5334                  * Update instruction length as we may reinject #BP from
5335                  * user space while in guest debugging mode. Reading it for
5336                  * #DB as well causes no harm, it is not used in that case.
5337                  */
5338                 vmx->vcpu.arch.event_exit_inst_len =
5339                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5340                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5341                 rip = kvm_rip_read(vcpu);
5342                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5343                 kvm_run->debug.arch.exception = ex_no;
5344                 break;
5345         default:
5346                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5347                 kvm_run->ex.exception = ex_no;
5348                 kvm_run->ex.error_code = error_code;
5349                 break;
5350         }
5351         return 0;
5352 }
5353
5354 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5355 {
5356         ++vcpu->stat.irq_exits;
5357         return 1;
5358 }
5359
5360 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5361 {
5362         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5363         return 0;
5364 }
5365
5366 static int handle_io(struct kvm_vcpu *vcpu)
5367 {
5368         unsigned long exit_qualification;
5369         int size, in, string;
5370         unsigned port;
5371
5372         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5373         string = (exit_qualification & 16) != 0;
5374         in = (exit_qualification & 8) != 0;
5375
5376         ++vcpu->stat.io_exits;
5377
5378         if (string || in)
5379                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5380
5381         port = exit_qualification >> 16;
5382         size = (exit_qualification & 7) + 1;
5383         skip_emulated_instruction(vcpu);
5384
5385         return kvm_fast_pio_out(vcpu, size, port);
5386 }
5387
5388 static void
5389 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5390 {
5391         /*
5392          * Patch in the VMCALL instruction:
5393          */
5394         hypercall[0] = 0x0f;
5395         hypercall[1] = 0x01;
5396         hypercall[2] = 0xc1;
5397 }
5398
5399 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5400 {
5401         unsigned long always_on = VMXON_CR0_ALWAYSON;
5402         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5403
5404         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5405                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5406             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5407                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5408         return (val & always_on) == always_on;
5409 }
5410
5411 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5412 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5413 {
5414         if (is_guest_mode(vcpu)) {
5415                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5416                 unsigned long orig_val = val;
5417
5418                 /*
5419                  * We get here when L2 changed cr0 in a way that did not change
5420                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5421                  * but did change L0 shadowed bits. So we first calculate the
5422                  * effective cr0 value that L1 would like to write into the
5423                  * hardware. It consists of the L2-owned bits from the new
5424                  * value combined with the L1-owned bits from L1's guest_cr0.
5425                  */
5426                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5427                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5428
5429                 if (!nested_cr0_valid(vcpu, val))
5430                         return 1;
5431
5432                 if (kvm_set_cr0(vcpu, val))
5433                         return 1;
5434                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5435                 return 0;
5436         } else {
5437                 if (to_vmx(vcpu)->nested.vmxon &&
5438                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5439                         return 1;
5440                 return kvm_set_cr0(vcpu, val);
5441         }
5442 }
5443
5444 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5445 {
5446         if (is_guest_mode(vcpu)) {
5447                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5448                 unsigned long orig_val = val;
5449
5450                 /* analogously to handle_set_cr0 */
5451                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5452                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5453                 if (kvm_set_cr4(vcpu, val))
5454                         return 1;
5455                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5456                 return 0;
5457         } else
5458                 return kvm_set_cr4(vcpu, val);
5459 }
5460
5461 /* called to set cr0 as approriate for clts instruction exit. */
5462 static void handle_clts(struct kvm_vcpu *vcpu)
5463 {
5464         if (is_guest_mode(vcpu)) {
5465                 /*
5466                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5467                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5468                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5469                  */
5470                 vmcs_writel(CR0_READ_SHADOW,
5471                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5472                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5473         } else
5474                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5475 }
5476
5477 static int handle_cr(struct kvm_vcpu *vcpu)
5478 {
5479         unsigned long exit_qualification, val;
5480         int cr;
5481         int reg;
5482         int err;
5483
5484         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5485         cr = exit_qualification & 15;
5486         reg = (exit_qualification >> 8) & 15;
5487         switch ((exit_qualification >> 4) & 3) {
5488         case 0: /* mov to cr */
5489                 val = kvm_register_readl(vcpu, reg);
5490                 trace_kvm_cr_write(cr, val);
5491                 switch (cr) {
5492                 case 0:
5493                         err = handle_set_cr0(vcpu, val);
5494                         kvm_complete_insn_gp(vcpu, err);
5495                         return 1;
5496                 case 3:
5497                         err = kvm_set_cr3(vcpu, val);
5498                         kvm_complete_insn_gp(vcpu, err);
5499                         return 1;
5500                 case 4:
5501                         err = handle_set_cr4(vcpu, val);
5502                         kvm_complete_insn_gp(vcpu, err);
5503                         return 1;
5504                 case 8: {
5505                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5506                                 u8 cr8 = (u8)val;
5507                                 err = kvm_set_cr8(vcpu, cr8);
5508                                 kvm_complete_insn_gp(vcpu, err);
5509                                 if (lapic_in_kernel(vcpu))
5510                                         return 1;
5511                                 if (cr8_prev <= cr8)
5512                                         return 1;
5513                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5514                                 return 0;
5515                         }
5516                 }
5517                 break;
5518         case 2: /* clts */
5519                 handle_clts(vcpu);
5520                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5521                 skip_emulated_instruction(vcpu);
5522                 vmx_fpu_activate(vcpu);
5523                 return 1;
5524         case 1: /*mov from cr*/
5525                 switch (cr) {
5526                 case 3:
5527                         val = kvm_read_cr3(vcpu);
5528                         kvm_register_write(vcpu, reg, val);
5529                         trace_kvm_cr_read(cr, val);
5530                         skip_emulated_instruction(vcpu);
5531                         return 1;
5532                 case 8:
5533                         val = kvm_get_cr8(vcpu);
5534                         kvm_register_write(vcpu, reg, val);
5535                         trace_kvm_cr_read(cr, val);
5536                         skip_emulated_instruction(vcpu);
5537                         return 1;
5538                 }
5539                 break;
5540         case 3: /* lmsw */
5541                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5542                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5543                 kvm_lmsw(vcpu, val);
5544
5545                 skip_emulated_instruction(vcpu);
5546                 return 1;
5547         default:
5548                 break;
5549         }
5550         vcpu->run->exit_reason = 0;
5551         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5552                (int)(exit_qualification >> 4) & 3, cr);
5553         return 0;
5554 }
5555
5556 static int handle_dr(struct kvm_vcpu *vcpu)
5557 {
5558         unsigned long exit_qualification;
5559         int dr, dr7, reg;
5560
5561         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5562         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5563
5564         /* First, if DR does not exist, trigger UD */
5565         if (!kvm_require_dr(vcpu, dr))
5566                 return 1;
5567
5568         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5569         if (!kvm_require_cpl(vcpu, 0))
5570                 return 1;
5571         dr7 = vmcs_readl(GUEST_DR7);
5572         if (dr7 & DR7_GD) {
5573                 /*
5574                  * As the vm-exit takes precedence over the debug trap, we
5575                  * need to emulate the latter, either for the host or the
5576                  * guest debugging itself.
5577                  */
5578                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5579                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5580                         vcpu->run->debug.arch.dr7 = dr7;
5581                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5582                         vcpu->run->debug.arch.exception = DB_VECTOR;
5583                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5584                         return 0;
5585                 } else {
5586                         vcpu->arch.dr6 &= ~15;
5587                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5588                         kvm_queue_exception(vcpu, DB_VECTOR);
5589                         return 1;
5590                 }
5591         }
5592
5593         if (vcpu->guest_debug == 0) {
5594                 u32 cpu_based_vm_exec_control;
5595
5596                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5597                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5598                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5599
5600                 /*
5601                  * No more DR vmexits; force a reload of the debug registers
5602                  * and reenter on this instruction.  The next vmexit will
5603                  * retrieve the full state of the debug registers.
5604                  */
5605                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5606                 return 1;
5607         }
5608
5609         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5610         if (exit_qualification & TYPE_MOV_FROM_DR) {
5611                 unsigned long val;
5612
5613                 if (kvm_get_dr(vcpu, dr, &val))
5614                         return 1;
5615                 kvm_register_write(vcpu, reg, val);
5616         } else
5617                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5618                         return 1;
5619
5620         skip_emulated_instruction(vcpu);
5621         return 1;
5622 }
5623
5624 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5625 {
5626         return vcpu->arch.dr6;
5627 }
5628
5629 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5630 {
5631 }
5632
5633 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5634 {
5635         u32 cpu_based_vm_exec_control;
5636
5637         get_debugreg(vcpu->arch.db[0], 0);
5638         get_debugreg(vcpu->arch.db[1], 1);
5639         get_debugreg(vcpu->arch.db[2], 2);
5640         get_debugreg(vcpu->arch.db[3], 3);
5641         get_debugreg(vcpu->arch.dr6, 6);
5642         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5643
5644         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5645
5646         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5647         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5648         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5649 }
5650
5651 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5652 {
5653         vmcs_writel(GUEST_DR7, val);
5654 }
5655
5656 static int handle_cpuid(struct kvm_vcpu *vcpu)
5657 {
5658         kvm_emulate_cpuid(vcpu);
5659         return 1;
5660 }
5661
5662 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5663 {
5664         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5665         struct msr_data msr_info;
5666
5667         msr_info.index = ecx;
5668         msr_info.host_initiated = false;
5669         if (vmx_get_msr(vcpu, &msr_info)) {
5670                 trace_kvm_msr_read_ex(ecx);
5671                 kvm_inject_gp(vcpu, 0);
5672                 return 1;
5673         }
5674
5675         trace_kvm_msr_read(ecx, msr_info.data);
5676
5677         /* FIXME: handling of bits 32:63 of rax, rdx */
5678         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5679         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5680         skip_emulated_instruction(vcpu);
5681         return 1;
5682 }
5683
5684 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5685 {
5686         struct msr_data msr;
5687         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5688         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5689                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5690
5691         msr.data = data;
5692         msr.index = ecx;
5693         msr.host_initiated = false;
5694         if (kvm_set_msr(vcpu, &msr) != 0) {
5695                 trace_kvm_msr_write_ex(ecx, data);
5696                 kvm_inject_gp(vcpu, 0);
5697                 return 1;
5698         }
5699
5700         trace_kvm_msr_write(ecx, data);
5701         skip_emulated_instruction(vcpu);
5702         return 1;
5703 }
5704
5705 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5706 {
5707         kvm_make_request(KVM_REQ_EVENT, vcpu);
5708         return 1;
5709 }
5710
5711 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5712 {
5713         u32 cpu_based_vm_exec_control;
5714
5715         /* clear pending irq */
5716         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5717         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5718         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5719
5720         kvm_make_request(KVM_REQ_EVENT, vcpu);
5721
5722         ++vcpu->stat.irq_window_exits;
5723         return 1;
5724 }
5725
5726 static int handle_halt(struct kvm_vcpu *vcpu)
5727 {
5728         return kvm_emulate_halt(vcpu);
5729 }
5730
5731 static int handle_vmcall(struct kvm_vcpu *vcpu)
5732 {
5733         kvm_emulate_hypercall(vcpu);
5734         return 1;
5735 }
5736
5737 static int handle_invd(struct kvm_vcpu *vcpu)
5738 {
5739         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5740 }
5741
5742 static int handle_invlpg(struct kvm_vcpu *vcpu)
5743 {
5744         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5745
5746         kvm_mmu_invlpg(vcpu, exit_qualification);
5747         skip_emulated_instruction(vcpu);
5748         return 1;
5749 }
5750
5751 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5752 {
5753         int err;
5754
5755         err = kvm_rdpmc(vcpu);
5756         kvm_complete_insn_gp(vcpu, err);
5757
5758         return 1;
5759 }
5760
5761 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5762 {
5763         kvm_emulate_wbinvd(vcpu);
5764         return 1;
5765 }
5766
5767 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5768 {
5769         u64 new_bv = kvm_read_edx_eax(vcpu);
5770         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5771
5772         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5773                 skip_emulated_instruction(vcpu);
5774         return 1;
5775 }
5776
5777 static int handle_xsaves(struct kvm_vcpu *vcpu)
5778 {
5779         skip_emulated_instruction(vcpu);
5780         WARN(1, "this should never happen\n");
5781         return 1;
5782 }
5783
5784 static int handle_xrstors(struct kvm_vcpu *vcpu)
5785 {
5786         skip_emulated_instruction(vcpu);
5787         WARN(1, "this should never happen\n");
5788         return 1;
5789 }
5790
5791 static int handle_apic_access(struct kvm_vcpu *vcpu)
5792 {
5793         if (likely(fasteoi)) {
5794                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5795                 int access_type, offset;
5796
5797                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5798                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5799                 /*
5800                  * Sane guest uses MOV to write EOI, with written value
5801                  * not cared. So make a short-circuit here by avoiding
5802                  * heavy instruction emulation.
5803                  */
5804                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5805                     (offset == APIC_EOI)) {
5806                         kvm_lapic_set_eoi(vcpu);
5807                         skip_emulated_instruction(vcpu);
5808                         return 1;
5809                 }
5810         }
5811         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5812 }
5813
5814 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5815 {
5816         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5817         int vector = exit_qualification & 0xff;
5818
5819         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5820         kvm_apic_set_eoi_accelerated(vcpu, vector);
5821         return 1;
5822 }
5823
5824 static int handle_apic_write(struct kvm_vcpu *vcpu)
5825 {
5826         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5827         u32 offset = exit_qualification & 0xfff;
5828
5829         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5830         kvm_apic_write_nodecode(vcpu, offset);
5831         return 1;
5832 }
5833
5834 static int handle_task_switch(struct kvm_vcpu *vcpu)
5835 {
5836         struct vcpu_vmx *vmx = to_vmx(vcpu);
5837         unsigned long exit_qualification;
5838         bool has_error_code = false;
5839         u32 error_code = 0;
5840         u16 tss_selector;
5841         int reason, type, idt_v, idt_index;
5842
5843         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5844         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5845         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5846
5847         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5848
5849         reason = (u32)exit_qualification >> 30;
5850         if (reason == TASK_SWITCH_GATE && idt_v) {
5851                 switch (type) {
5852                 case INTR_TYPE_NMI_INTR:
5853                         vcpu->arch.nmi_injected = false;
5854                         vmx_set_nmi_mask(vcpu, true);
5855                         break;
5856                 case INTR_TYPE_EXT_INTR:
5857                 case INTR_TYPE_SOFT_INTR:
5858                         kvm_clear_interrupt_queue(vcpu);
5859                         break;
5860                 case INTR_TYPE_HARD_EXCEPTION:
5861                         if (vmx->idt_vectoring_info &
5862                             VECTORING_INFO_DELIVER_CODE_MASK) {
5863                                 has_error_code = true;
5864                                 error_code =
5865                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5866                         }
5867                         /* fall through */
5868                 case INTR_TYPE_SOFT_EXCEPTION:
5869                         kvm_clear_exception_queue(vcpu);
5870                         break;
5871                 default:
5872                         break;
5873                 }
5874         }
5875         tss_selector = exit_qualification;
5876
5877         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5878                        type != INTR_TYPE_EXT_INTR &&
5879                        type != INTR_TYPE_NMI_INTR))
5880                 skip_emulated_instruction(vcpu);
5881
5882         if (kvm_task_switch(vcpu, tss_selector,
5883                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5884                             has_error_code, error_code) == EMULATE_FAIL) {
5885                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5886                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5887                 vcpu->run->internal.ndata = 0;
5888                 return 0;
5889         }
5890
5891         /*
5892          * TODO: What about debug traps on tss switch?
5893          *       Are we supposed to inject them and update dr6?
5894          */
5895
5896         return 1;
5897 }
5898
5899 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5900 {
5901         unsigned long exit_qualification;
5902         gpa_t gpa;
5903         u32 error_code;
5904         int gla_validity;
5905
5906         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5907
5908         gla_validity = (exit_qualification >> 7) & 0x3;
5909         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5910                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5911                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5912                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5913                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5914                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5915                         (long unsigned int)exit_qualification);
5916                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5917                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5918                 return 0;
5919         }
5920
5921         /*
5922          * EPT violation happened while executing iret from NMI,
5923          * "blocked by NMI" bit has to be set before next VM entry.
5924          * There are errata that may cause this bit to not be set:
5925          * AAK134, BY25.
5926          */
5927         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5928                         cpu_has_virtual_nmis() &&
5929                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5930                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5931
5932         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5933         trace_kvm_page_fault(gpa, exit_qualification);
5934
5935         /* It is a write fault? */
5936         error_code = exit_qualification & PFERR_WRITE_MASK;
5937         /* It is a fetch fault? */
5938         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5939         /* ept page table is present? */
5940         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5941
5942         vcpu->arch.exit_qualification = exit_qualification;
5943
5944         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5945 }
5946
5947 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5948 {
5949         int ret;
5950         gpa_t gpa;
5951
5952         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5953         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5954                 skip_emulated_instruction(vcpu);
5955                 trace_kvm_fast_mmio(gpa);
5956                 return 1;
5957         }
5958
5959         ret = handle_mmio_page_fault(vcpu, gpa, true);
5960         if (likely(ret == RET_MMIO_PF_EMULATE))
5961                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5962                                               EMULATE_DONE;
5963
5964         if (unlikely(ret == RET_MMIO_PF_INVALID))
5965                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5966
5967         if (unlikely(ret == RET_MMIO_PF_RETRY))
5968                 return 1;
5969
5970         /* It is the real ept misconfig */
5971         WARN_ON(1);
5972
5973         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5974         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5975
5976         return 0;
5977 }
5978
5979 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5980 {
5981         u32 cpu_based_vm_exec_control;
5982
5983         /* clear pending NMI */
5984         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5985         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5986         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5987         ++vcpu->stat.nmi_window_exits;
5988         kvm_make_request(KVM_REQ_EVENT, vcpu);
5989
5990         return 1;
5991 }
5992
5993 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5994 {
5995         struct vcpu_vmx *vmx = to_vmx(vcpu);
5996         enum emulation_result err = EMULATE_DONE;
5997         int ret = 1;
5998         u32 cpu_exec_ctrl;
5999         bool intr_window_requested;
6000         unsigned count = 130;
6001
6002         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6003         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6004
6005         while (vmx->emulation_required && count-- != 0) {
6006                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6007                         return handle_interrupt_window(&vmx->vcpu);
6008
6009                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6010                         return 1;
6011
6012                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6013
6014                 if (err == EMULATE_USER_EXIT) {
6015                         ++vcpu->stat.mmio_exits;
6016                         ret = 0;
6017                         goto out;
6018                 }
6019
6020                 if (err != EMULATE_DONE) {
6021                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6022                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6023                         vcpu->run->internal.ndata = 0;
6024                         return 0;
6025                 }
6026
6027                 if (vcpu->arch.halt_request) {
6028                         vcpu->arch.halt_request = 0;
6029                         ret = kvm_vcpu_halt(vcpu);
6030                         goto out;
6031                 }
6032
6033                 if (signal_pending(current))
6034                         goto out;
6035                 if (need_resched())
6036                         schedule();
6037         }
6038
6039 out:
6040         return ret;
6041 }
6042
6043 static int __grow_ple_window(int val)
6044 {
6045         if (ple_window_grow < 1)
6046                 return ple_window;
6047
6048         val = min(val, ple_window_actual_max);
6049
6050         if (ple_window_grow < ple_window)
6051                 val *= ple_window_grow;
6052         else
6053                 val += ple_window_grow;
6054
6055         return val;
6056 }
6057
6058 static int __shrink_ple_window(int val, int modifier, int minimum)
6059 {
6060         if (modifier < 1)
6061                 return ple_window;
6062
6063         if (modifier < ple_window)
6064                 val /= modifier;
6065         else
6066                 val -= modifier;
6067
6068         return max(val, minimum);
6069 }
6070
6071 static void grow_ple_window(struct kvm_vcpu *vcpu)
6072 {
6073         struct vcpu_vmx *vmx = to_vmx(vcpu);
6074         int old = vmx->ple_window;
6075
6076         vmx->ple_window = __grow_ple_window(old);
6077
6078         if (vmx->ple_window != old)
6079                 vmx->ple_window_dirty = true;
6080
6081         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6082 }
6083
6084 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6085 {
6086         struct vcpu_vmx *vmx = to_vmx(vcpu);
6087         int old = vmx->ple_window;
6088
6089         vmx->ple_window = __shrink_ple_window(old,
6090                                               ple_window_shrink, ple_window);
6091
6092         if (vmx->ple_window != old)
6093                 vmx->ple_window_dirty = true;
6094
6095         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6096 }
6097
6098 /*
6099  * ple_window_actual_max is computed to be one grow_ple_window() below
6100  * ple_window_max. (See __grow_ple_window for the reason.)
6101  * This prevents overflows, because ple_window_max is int.
6102  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6103  * this process.
6104  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6105  */
6106 static void update_ple_window_actual_max(void)
6107 {
6108         ple_window_actual_max =
6109                         __shrink_ple_window(max(ple_window_max, ple_window),
6110                                             ple_window_grow, INT_MIN);
6111 }
6112
6113 /*
6114  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6115  */
6116 static void wakeup_handler(void)
6117 {
6118         struct kvm_vcpu *vcpu;
6119         int cpu = smp_processor_id();
6120
6121         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6122         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6123                         blocked_vcpu_list) {
6124                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6125
6126                 if (pi_test_on(pi_desc) == 1)
6127                         kvm_vcpu_kick(vcpu);
6128         }
6129         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6130 }
6131
6132 static __init int hardware_setup(void)
6133 {
6134         int r = -ENOMEM, i, msr;
6135
6136         rdmsrl_safe(MSR_EFER, &host_efer);
6137
6138         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6139                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6140
6141         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6142         if (!vmx_io_bitmap_a)
6143                 return r;
6144
6145         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6146         if (!vmx_io_bitmap_b)
6147                 goto out;
6148
6149         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6150         if (!vmx_msr_bitmap_legacy)
6151                 goto out1;
6152
6153         vmx_msr_bitmap_legacy_x2apic =
6154                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6155         if (!vmx_msr_bitmap_legacy_x2apic)
6156                 goto out2;
6157
6158         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6159         if (!vmx_msr_bitmap_longmode)
6160                 goto out3;
6161
6162         vmx_msr_bitmap_longmode_x2apic =
6163                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6164         if (!vmx_msr_bitmap_longmode_x2apic)
6165                 goto out4;
6166
6167         if (nested) {
6168                 vmx_msr_bitmap_nested =
6169                         (unsigned long *)__get_free_page(GFP_KERNEL);
6170                 if (!vmx_msr_bitmap_nested)
6171                         goto out5;
6172         }
6173
6174         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6175         if (!vmx_vmread_bitmap)
6176                 goto out6;
6177
6178         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6179         if (!vmx_vmwrite_bitmap)
6180                 goto out7;
6181
6182         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6183         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6184
6185         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6186
6187         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6188
6189         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6190         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6191         if (nested)
6192                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6193
6194         if (setup_vmcs_config(&vmcs_config) < 0) {
6195                 r = -EIO;
6196                 goto out8;
6197         }
6198
6199         if (boot_cpu_has(X86_FEATURE_NX))
6200                 kvm_enable_efer_bits(EFER_NX);
6201
6202         if (!cpu_has_vmx_vpid())
6203                 enable_vpid = 0;
6204         if (!cpu_has_vmx_shadow_vmcs())
6205                 enable_shadow_vmcs = 0;
6206         if (enable_shadow_vmcs)
6207                 init_vmcs_shadow_fields();
6208
6209         if (!cpu_has_vmx_ept() ||
6210             !cpu_has_vmx_ept_4levels()) {
6211                 enable_ept = 0;
6212                 enable_unrestricted_guest = 0;
6213                 enable_ept_ad_bits = 0;
6214         }
6215
6216         if (!cpu_has_vmx_ept_ad_bits())
6217                 enable_ept_ad_bits = 0;
6218
6219         if (!cpu_has_vmx_unrestricted_guest())
6220                 enable_unrestricted_guest = 0;
6221
6222         if (!cpu_has_vmx_flexpriority())
6223                 flexpriority_enabled = 0;
6224
6225         /*
6226          * set_apic_access_page_addr() is used to reload apic access
6227          * page upon invalidation.  No need to do anything if not
6228          * using the APIC_ACCESS_ADDR VMCS field.
6229          */
6230         if (!flexpriority_enabled)
6231                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6232
6233         if (!cpu_has_vmx_tpr_shadow())
6234                 kvm_x86_ops->update_cr8_intercept = NULL;
6235
6236         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6237                 kvm_disable_largepages();
6238
6239         if (!cpu_has_vmx_ple())
6240                 ple_gap = 0;
6241
6242         if (!cpu_has_vmx_apicv())
6243                 enable_apicv = 0;
6244
6245         if (cpu_has_vmx_tsc_scaling()) {
6246                 kvm_has_tsc_control = true;
6247                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6248                 kvm_tsc_scaling_ratio_frac_bits = 48;
6249         }
6250
6251         if (enable_apicv)
6252                 kvm_x86_ops->update_cr8_intercept = NULL;
6253         else {
6254                 kvm_x86_ops->hwapic_irr_update = NULL;
6255                 kvm_x86_ops->hwapic_isr_update = NULL;
6256                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6257                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6258         }
6259
6260         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6261         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6262         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6263         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6264         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6265         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6266
6267         memcpy(vmx_msr_bitmap_legacy_x2apic,
6268                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6269         memcpy(vmx_msr_bitmap_longmode_x2apic,
6270                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6271
6272         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6273
6274         if (enable_apicv) {
6275                 for (msr = 0x800; msr <= 0x8ff; msr++)
6276                         vmx_disable_intercept_msr_read_x2apic(msr);
6277
6278                 /* According SDM, in x2apic mode, the whole id reg is used.
6279                  * But in KVM, it only use the highest eight bits. Need to
6280                  * intercept it */
6281                 vmx_enable_intercept_msr_read_x2apic(0x802);
6282                 /* TMCCT */
6283                 vmx_enable_intercept_msr_read_x2apic(0x839);
6284                 /* TPR */
6285                 vmx_disable_intercept_msr_write_x2apic(0x808);
6286                 /* EOI */
6287                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6288                 /* SELF-IPI */
6289                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6290         }
6291
6292         if (enable_ept) {
6293                 kvm_mmu_set_mask_ptes(0ull,
6294                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6295                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6296                         0ull, VMX_EPT_EXECUTABLE_MASK);
6297                 ept_set_mmio_spte_mask();
6298                 kvm_enable_tdp();
6299         } else
6300                 kvm_disable_tdp();
6301
6302         update_ple_window_actual_max();
6303
6304         /*
6305          * Only enable PML when hardware supports PML feature, and both EPT
6306          * and EPT A/D bit features are enabled -- PML depends on them to work.
6307          */
6308         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6309                 enable_pml = 0;
6310
6311         if (!enable_pml) {
6312                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6313                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6314                 kvm_x86_ops->flush_log_dirty = NULL;
6315                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6316         }
6317
6318         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6319
6320         return alloc_kvm_area();
6321
6322 out8:
6323         free_page((unsigned long)vmx_vmwrite_bitmap);
6324 out7:
6325         free_page((unsigned long)vmx_vmread_bitmap);
6326 out6:
6327         if (nested)
6328                 free_page((unsigned long)vmx_msr_bitmap_nested);
6329 out5:
6330         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6331 out4:
6332         free_page((unsigned long)vmx_msr_bitmap_longmode);
6333 out3:
6334         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6335 out2:
6336         free_page((unsigned long)vmx_msr_bitmap_legacy);
6337 out1:
6338         free_page((unsigned long)vmx_io_bitmap_b);
6339 out:
6340         free_page((unsigned long)vmx_io_bitmap_a);
6341
6342     return r;
6343 }
6344
6345 static __exit void hardware_unsetup(void)
6346 {
6347         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6348         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6349         free_page((unsigned long)vmx_msr_bitmap_legacy);
6350         free_page((unsigned long)vmx_msr_bitmap_longmode);
6351         free_page((unsigned long)vmx_io_bitmap_b);
6352         free_page((unsigned long)vmx_io_bitmap_a);
6353         free_page((unsigned long)vmx_vmwrite_bitmap);
6354         free_page((unsigned long)vmx_vmread_bitmap);
6355         if (nested)
6356                 free_page((unsigned long)vmx_msr_bitmap_nested);
6357
6358         free_kvm_area();
6359 }
6360
6361 /*
6362  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6363  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6364  */
6365 static int handle_pause(struct kvm_vcpu *vcpu)
6366 {
6367         if (ple_gap)
6368                 grow_ple_window(vcpu);
6369
6370         skip_emulated_instruction(vcpu);
6371         kvm_vcpu_on_spin(vcpu);
6372
6373         return 1;
6374 }
6375
6376 static int handle_nop(struct kvm_vcpu *vcpu)
6377 {
6378         skip_emulated_instruction(vcpu);
6379         return 1;
6380 }
6381
6382 static int handle_mwait(struct kvm_vcpu *vcpu)
6383 {
6384         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6385         return handle_nop(vcpu);
6386 }
6387
6388 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6389 {
6390         return 1;
6391 }
6392
6393 static int handle_monitor(struct kvm_vcpu *vcpu)
6394 {
6395         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6396         return handle_nop(vcpu);
6397 }
6398
6399 /*
6400  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6401  * We could reuse a single VMCS for all the L2 guests, but we also want the
6402  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6403  * allows keeping them loaded on the processor, and in the future will allow
6404  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6405  * every entry if they never change.
6406  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6407  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6408  *
6409  * The following functions allocate and free a vmcs02 in this pool.
6410  */
6411
6412 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6413 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6414 {
6415         struct vmcs02_list *item;
6416         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6417                 if (item->vmptr == vmx->nested.current_vmptr) {
6418                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6419                         return &item->vmcs02;
6420                 }
6421
6422         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6423                 /* Recycle the least recently used VMCS. */
6424                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6425                         struct vmcs02_list, list);
6426                 item->vmptr = vmx->nested.current_vmptr;
6427                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6428                 return &item->vmcs02;
6429         }
6430
6431         /* Create a new VMCS */
6432         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6433         if (!item)
6434                 return NULL;
6435         item->vmcs02.vmcs = alloc_vmcs();
6436         if (!item->vmcs02.vmcs) {
6437                 kfree(item);
6438                 return NULL;
6439         }
6440         loaded_vmcs_init(&item->vmcs02);
6441         item->vmptr = vmx->nested.current_vmptr;
6442         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6443         vmx->nested.vmcs02_num++;
6444         return &item->vmcs02;
6445 }
6446
6447 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6448 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6449 {
6450         struct vmcs02_list *item;
6451         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6452                 if (item->vmptr == vmptr) {
6453                         free_loaded_vmcs(&item->vmcs02);
6454                         list_del(&item->list);
6455                         kfree(item);
6456                         vmx->nested.vmcs02_num--;
6457                         return;
6458                 }
6459 }
6460
6461 /*
6462  * Free all VMCSs saved for this vcpu, except the one pointed by
6463  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6464  * must be &vmx->vmcs01.
6465  */
6466 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6467 {
6468         struct vmcs02_list *item, *n;
6469
6470         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6471         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6472                 /*
6473                  * Something will leak if the above WARN triggers.  Better than
6474                  * a use-after-free.
6475                  */
6476                 if (vmx->loaded_vmcs == &item->vmcs02)
6477                         continue;
6478
6479                 free_loaded_vmcs(&item->vmcs02);
6480                 list_del(&item->list);
6481                 kfree(item);
6482                 vmx->nested.vmcs02_num--;
6483         }
6484 }
6485
6486 /*
6487  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6488  * set the success or error code of an emulated VMX instruction, as specified
6489  * by Vol 2B, VMX Instruction Reference, "Conventions".
6490  */
6491 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6492 {
6493         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6494                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6495                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6496 }
6497
6498 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6499 {
6500         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6501                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6502                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6503                         | X86_EFLAGS_CF);
6504 }
6505
6506 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6507                                         u32 vm_instruction_error)
6508 {
6509         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6510                 /*
6511                  * failValid writes the error number to the current VMCS, which
6512                  * can't be done there isn't a current VMCS.
6513                  */
6514                 nested_vmx_failInvalid(vcpu);
6515                 return;
6516         }
6517         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6518                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6519                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6520                         | X86_EFLAGS_ZF);
6521         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6522         /*
6523          * We don't need to force a shadow sync because
6524          * VM_INSTRUCTION_ERROR is not shadowed
6525          */
6526 }
6527
6528 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6529 {
6530         /* TODO: not to reset guest simply here. */
6531         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6532         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6533 }
6534
6535 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6536 {
6537         struct vcpu_vmx *vmx =
6538                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6539
6540         vmx->nested.preemption_timer_expired = true;
6541         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6542         kvm_vcpu_kick(&vmx->vcpu);
6543
6544         return HRTIMER_NORESTART;
6545 }
6546
6547 /*
6548  * Decode the memory-address operand of a vmx instruction, as recorded on an
6549  * exit caused by such an instruction (run by a guest hypervisor).
6550  * On success, returns 0. When the operand is invalid, returns 1 and throws
6551  * #UD or #GP.
6552  */
6553 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6554                                  unsigned long exit_qualification,
6555                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6556 {
6557         gva_t off;
6558         bool exn;
6559         struct kvm_segment s;
6560
6561         /*
6562          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6563          * Execution", on an exit, vmx_instruction_info holds most of the
6564          * addressing components of the operand. Only the displacement part
6565          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6566          * For how an actual address is calculated from all these components,
6567          * refer to Vol. 1, "Operand Addressing".
6568          */
6569         int  scaling = vmx_instruction_info & 3;
6570         int  addr_size = (vmx_instruction_info >> 7) & 7;
6571         bool is_reg = vmx_instruction_info & (1u << 10);
6572         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6573         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6574         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6575         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6576         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6577
6578         if (is_reg) {
6579                 kvm_queue_exception(vcpu, UD_VECTOR);
6580                 return 1;
6581         }
6582
6583         /* Addr = segment_base + offset */
6584         /* offset = base + [index * scale] + displacement */
6585         off = exit_qualification; /* holds the displacement */
6586         if (base_is_valid)
6587                 off += kvm_register_read(vcpu, base_reg);
6588         if (index_is_valid)
6589                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6590         vmx_get_segment(vcpu, &s, seg_reg);
6591         *ret = s.base + off;
6592
6593         if (addr_size == 1) /* 32 bit */
6594                 *ret &= 0xffffffff;
6595
6596         /* Checks for #GP/#SS exceptions. */
6597         exn = false;
6598         if (is_long_mode(vcpu)) {
6599                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6600                  * non-canonical form. This is the only check on the memory
6601                  * destination for long mode!
6602                  */
6603                 exn = is_noncanonical_address(*ret);
6604         } else if (is_protmode(vcpu)) {
6605                 /* Protected mode: apply checks for segment validity in the
6606                  * following order:
6607                  * - segment type check (#GP(0) may be thrown)
6608                  * - usability check (#GP(0)/#SS(0))
6609                  * - limit check (#GP(0)/#SS(0))
6610                  */
6611                 if (wr)
6612                         /* #GP(0) if the destination operand is located in a
6613                          * read-only data segment or any code segment.
6614                          */
6615                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6616                 else
6617                         /* #GP(0) if the source operand is located in an
6618                          * execute-only code segment
6619                          */
6620                         exn = ((s.type & 0xa) == 8);
6621                 if (exn) {
6622                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6623                         return 1;
6624                 }
6625                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6626                  */
6627                 exn = (s.unusable != 0);
6628                 /* Protected mode: #GP(0)/#SS(0) if the memory
6629                  * operand is outside the segment limit.
6630                  */
6631                 exn = exn || (off + sizeof(u64) > s.limit);
6632         }
6633         if (exn) {
6634                 kvm_queue_exception_e(vcpu,
6635                                       seg_reg == VCPU_SREG_SS ?
6636                                                 SS_VECTOR : GP_VECTOR,
6637                                       0);
6638                 return 1;
6639         }
6640
6641         return 0;
6642 }
6643
6644 /*
6645  * This function performs the various checks including
6646  * - if it's 4KB aligned
6647  * - No bits beyond the physical address width are set
6648  * - Returns 0 on success or else 1
6649  * (Intel SDM Section 30.3)
6650  */
6651 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6652                                   gpa_t *vmpointer)
6653 {
6654         gva_t gva;
6655         gpa_t vmptr;
6656         struct x86_exception e;
6657         struct page *page;
6658         struct vcpu_vmx *vmx = to_vmx(vcpu);
6659         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6660
6661         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6662                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6663                 return 1;
6664
6665         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6666                                 sizeof(vmptr), &e)) {
6667                 kvm_inject_page_fault(vcpu, &e);
6668                 return 1;
6669         }
6670
6671         switch (exit_reason) {
6672         case EXIT_REASON_VMON:
6673                 /*
6674                  * SDM 3: 24.11.5
6675                  * The first 4 bytes of VMXON region contain the supported
6676                  * VMCS revision identifier
6677                  *
6678                  * Note - IA32_VMX_BASIC[48] will never be 1
6679                  * for the nested case;
6680                  * which replaces physical address width with 32
6681                  *
6682                  */
6683                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6684                         nested_vmx_failInvalid(vcpu);
6685                         skip_emulated_instruction(vcpu);
6686                         return 1;
6687                 }
6688
6689                 page = nested_get_page(vcpu, vmptr);
6690                 if (page == NULL) {
6691                         nested_vmx_failInvalid(vcpu);
6692                         skip_emulated_instruction(vcpu);
6693                         return 1;
6694                 }
6695                 if (*(u32 *)kmap(page) != VMCS12_REVISION) {
6696                         kunmap(page);
6697                         nested_release_page_clean(page);
6698                         nested_vmx_failInvalid(vcpu);
6699                         skip_emulated_instruction(vcpu);
6700                         return 1;
6701                 }
6702                 kunmap(page);
6703                 nested_release_page_clean(page);
6704                 vmx->nested.vmxon_ptr = vmptr;
6705                 break;
6706         case EXIT_REASON_VMCLEAR:
6707                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6708                         nested_vmx_failValid(vcpu,
6709                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6710                         skip_emulated_instruction(vcpu);
6711                         return 1;
6712                 }
6713
6714                 if (vmptr == vmx->nested.vmxon_ptr) {
6715                         nested_vmx_failValid(vcpu,
6716                                              VMXERR_VMCLEAR_VMXON_POINTER);
6717                         skip_emulated_instruction(vcpu);
6718                         return 1;
6719                 }
6720                 break;
6721         case EXIT_REASON_VMPTRLD:
6722                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6723                         nested_vmx_failValid(vcpu,
6724                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6725                         skip_emulated_instruction(vcpu);
6726                         return 1;
6727                 }
6728
6729                 if (vmptr == vmx->nested.vmxon_ptr) {
6730                         nested_vmx_failValid(vcpu,
6731                                              VMXERR_VMCLEAR_VMXON_POINTER);
6732                         skip_emulated_instruction(vcpu);
6733                         return 1;
6734                 }
6735                 break;
6736         default:
6737                 return 1; /* shouldn't happen */
6738         }
6739
6740         if (vmpointer)
6741                 *vmpointer = vmptr;
6742         return 0;
6743 }
6744
6745 /*
6746  * Emulate the VMXON instruction.
6747  * Currently, we just remember that VMX is active, and do not save or even
6748  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6749  * do not currently need to store anything in that guest-allocated memory
6750  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6751  * argument is different from the VMXON pointer (which the spec says they do).
6752  */
6753 static int handle_vmon(struct kvm_vcpu *vcpu)
6754 {
6755         struct kvm_segment cs;
6756         struct vcpu_vmx *vmx = to_vmx(vcpu);
6757         struct vmcs *shadow_vmcs;
6758         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6759                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6760
6761         /* The Intel VMX Instruction Reference lists a bunch of bits that
6762          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6763          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6764          * Otherwise, we should fail with #UD. We test these now:
6765          */
6766         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6767             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6768             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6769                 kvm_queue_exception(vcpu, UD_VECTOR);
6770                 return 1;
6771         }
6772
6773         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6774         if (is_long_mode(vcpu) && !cs.l) {
6775                 kvm_queue_exception(vcpu, UD_VECTOR);
6776                 return 1;
6777         }
6778
6779         if (vmx_get_cpl(vcpu)) {
6780                 kvm_inject_gp(vcpu, 0);
6781                 return 1;
6782         }
6783
6784         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6785                 return 1;
6786
6787         if (vmx->nested.vmxon) {
6788                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6789                 skip_emulated_instruction(vcpu);
6790                 return 1;
6791         }
6792
6793         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6794                         != VMXON_NEEDED_FEATURES) {
6795                 kvm_inject_gp(vcpu, 0);
6796                 return 1;
6797         }
6798
6799         if (enable_shadow_vmcs) {
6800                 shadow_vmcs = alloc_vmcs();
6801                 if (!shadow_vmcs)
6802                         return -ENOMEM;
6803                 /* mark vmcs as shadow */
6804                 shadow_vmcs->revision_id |= (1u << 31);
6805                 /* init shadow vmcs */
6806                 vmcs_clear(shadow_vmcs);
6807                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6808         }
6809
6810         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6811         vmx->nested.vmcs02_num = 0;
6812
6813         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6814                      HRTIMER_MODE_REL);
6815         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6816
6817         vmx->nested.vmxon = true;
6818
6819         skip_emulated_instruction(vcpu);
6820         nested_vmx_succeed(vcpu);
6821         return 1;
6822 }
6823
6824 /*
6825  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6826  * for running VMX instructions (except VMXON, whose prerequisites are
6827  * slightly different). It also specifies what exception to inject otherwise.
6828  */
6829 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6830 {
6831         struct kvm_segment cs;
6832         struct vcpu_vmx *vmx = to_vmx(vcpu);
6833
6834         if (!vmx->nested.vmxon) {
6835                 kvm_queue_exception(vcpu, UD_VECTOR);
6836                 return 0;
6837         }
6838
6839         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6840         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6841             (is_long_mode(vcpu) && !cs.l)) {
6842                 kvm_queue_exception(vcpu, UD_VECTOR);
6843                 return 0;
6844         }
6845
6846         if (vmx_get_cpl(vcpu)) {
6847                 kvm_inject_gp(vcpu, 0);
6848                 return 0;
6849         }
6850
6851         return 1;
6852 }
6853
6854 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6855 {
6856         if (vmx->nested.current_vmptr == -1ull)
6857                 return;
6858
6859         /* current_vmptr and current_vmcs12 are always set/reset together */
6860         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6861                 return;
6862
6863         if (enable_shadow_vmcs) {
6864                 /* copy to memory all shadowed fields in case
6865                    they were modified */
6866                 copy_shadow_to_vmcs12(vmx);
6867                 vmx->nested.sync_shadow_vmcs = false;
6868                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6869                                 SECONDARY_EXEC_SHADOW_VMCS);
6870                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6871         }
6872         vmx->nested.posted_intr_nv = -1;
6873         kunmap(vmx->nested.current_vmcs12_page);
6874         nested_release_page(vmx->nested.current_vmcs12_page);
6875         vmx->nested.current_vmptr = -1ull;
6876         vmx->nested.current_vmcs12 = NULL;
6877 }
6878
6879 /*
6880  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6881  * just stops using VMX.
6882  */
6883 static void free_nested(struct vcpu_vmx *vmx)
6884 {
6885         if (!vmx->nested.vmxon)
6886                 return;
6887
6888         vmx->nested.vmxon = false;
6889         free_vpid(vmx->nested.vpid02);
6890         nested_release_vmcs12(vmx);
6891         if (enable_shadow_vmcs)
6892                 free_vmcs(vmx->nested.current_shadow_vmcs);
6893         /* Unpin physical memory we referred to in current vmcs02 */
6894         if (vmx->nested.apic_access_page) {
6895                 nested_release_page(vmx->nested.apic_access_page);
6896                 vmx->nested.apic_access_page = NULL;
6897         }
6898         if (vmx->nested.virtual_apic_page) {
6899                 nested_release_page(vmx->nested.virtual_apic_page);
6900                 vmx->nested.virtual_apic_page = NULL;
6901         }
6902         if (vmx->nested.pi_desc_page) {
6903                 kunmap(vmx->nested.pi_desc_page);
6904                 nested_release_page(vmx->nested.pi_desc_page);
6905                 vmx->nested.pi_desc_page = NULL;
6906                 vmx->nested.pi_desc = NULL;
6907         }
6908
6909         nested_free_all_saved_vmcss(vmx);
6910 }
6911
6912 /* Emulate the VMXOFF instruction */
6913 static int handle_vmoff(struct kvm_vcpu *vcpu)
6914 {
6915         if (!nested_vmx_check_permission(vcpu))
6916                 return 1;
6917         free_nested(to_vmx(vcpu));
6918         skip_emulated_instruction(vcpu);
6919         nested_vmx_succeed(vcpu);
6920         return 1;
6921 }
6922
6923 /* Emulate the VMCLEAR instruction */
6924 static int handle_vmclear(struct kvm_vcpu *vcpu)
6925 {
6926         struct vcpu_vmx *vmx = to_vmx(vcpu);
6927         gpa_t vmptr;
6928         struct vmcs12 *vmcs12;
6929         struct page *page;
6930
6931         if (!nested_vmx_check_permission(vcpu))
6932                 return 1;
6933
6934         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6935                 return 1;
6936
6937         if (vmptr == vmx->nested.current_vmptr)
6938                 nested_release_vmcs12(vmx);
6939
6940         page = nested_get_page(vcpu, vmptr);
6941         if (page == NULL) {
6942                 /*
6943                  * For accurate processor emulation, VMCLEAR beyond available
6944                  * physical memory should do nothing at all. However, it is
6945                  * possible that a nested vmx bug, not a guest hypervisor bug,
6946                  * resulted in this case, so let's shut down before doing any
6947                  * more damage:
6948                  */
6949                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6950                 return 1;
6951         }
6952         vmcs12 = kmap(page);
6953         vmcs12->launch_state = 0;
6954         kunmap(page);
6955         nested_release_page(page);
6956
6957         nested_free_vmcs02(vmx, vmptr);
6958
6959         skip_emulated_instruction(vcpu);
6960         nested_vmx_succeed(vcpu);
6961         return 1;
6962 }
6963
6964 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6965
6966 /* Emulate the VMLAUNCH instruction */
6967 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6968 {
6969         return nested_vmx_run(vcpu, true);
6970 }
6971
6972 /* Emulate the VMRESUME instruction */
6973 static int handle_vmresume(struct kvm_vcpu *vcpu)
6974 {
6975
6976         return nested_vmx_run(vcpu, false);
6977 }
6978
6979 enum vmcs_field_type {
6980         VMCS_FIELD_TYPE_U16 = 0,
6981         VMCS_FIELD_TYPE_U64 = 1,
6982         VMCS_FIELD_TYPE_U32 = 2,
6983         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6984 };
6985
6986 static inline int vmcs_field_type(unsigned long field)
6987 {
6988         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6989                 return VMCS_FIELD_TYPE_U32;
6990         return (field >> 13) & 0x3 ;
6991 }
6992
6993 static inline int vmcs_field_readonly(unsigned long field)
6994 {
6995         return (((field >> 10) & 0x3) == 1);
6996 }
6997
6998 /*
6999  * Read a vmcs12 field. Since these can have varying lengths and we return
7000  * one type, we chose the biggest type (u64) and zero-extend the return value
7001  * to that size. Note that the caller, handle_vmread, might need to use only
7002  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7003  * 64-bit fields are to be returned).
7004  */
7005 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7006                                   unsigned long field, u64 *ret)
7007 {
7008         short offset = vmcs_field_to_offset(field);
7009         char *p;
7010
7011         if (offset < 0)
7012                 return offset;
7013
7014         p = ((char *)(get_vmcs12(vcpu))) + offset;
7015
7016         switch (vmcs_field_type(field)) {
7017         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7018                 *ret = *((natural_width *)p);
7019                 return 0;
7020         case VMCS_FIELD_TYPE_U16:
7021                 *ret = *((u16 *)p);
7022                 return 0;
7023         case VMCS_FIELD_TYPE_U32:
7024                 *ret = *((u32 *)p);
7025                 return 0;
7026         case VMCS_FIELD_TYPE_U64:
7027                 *ret = *((u64 *)p);
7028                 return 0;
7029         default:
7030                 WARN_ON(1);
7031                 return -ENOENT;
7032         }
7033 }
7034
7035
7036 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7037                                    unsigned long field, u64 field_value){
7038         short offset = vmcs_field_to_offset(field);
7039         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7040         if (offset < 0)
7041                 return offset;
7042
7043         switch (vmcs_field_type(field)) {
7044         case VMCS_FIELD_TYPE_U16:
7045                 *(u16 *)p = field_value;
7046                 return 0;
7047         case VMCS_FIELD_TYPE_U32:
7048                 *(u32 *)p = field_value;
7049                 return 0;
7050         case VMCS_FIELD_TYPE_U64:
7051                 *(u64 *)p = field_value;
7052                 return 0;
7053         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7054                 *(natural_width *)p = field_value;
7055                 return 0;
7056         default:
7057                 WARN_ON(1);
7058                 return -ENOENT;
7059         }
7060
7061 }
7062
7063 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7064 {
7065         int i;
7066         unsigned long field;
7067         u64 field_value;
7068         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7069         const unsigned long *fields = shadow_read_write_fields;
7070         const int num_fields = max_shadow_read_write_fields;
7071
7072         preempt_disable();
7073
7074         vmcs_load(shadow_vmcs);
7075
7076         for (i = 0; i < num_fields; i++) {
7077                 field = fields[i];
7078                 switch (vmcs_field_type(field)) {
7079                 case VMCS_FIELD_TYPE_U16:
7080                         field_value = vmcs_read16(field);
7081                         break;
7082                 case VMCS_FIELD_TYPE_U32:
7083                         field_value = vmcs_read32(field);
7084                         break;
7085                 case VMCS_FIELD_TYPE_U64:
7086                         field_value = vmcs_read64(field);
7087                         break;
7088                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7089                         field_value = vmcs_readl(field);
7090                         break;
7091                 default:
7092                         WARN_ON(1);
7093                         continue;
7094                 }
7095                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7096         }
7097
7098         vmcs_clear(shadow_vmcs);
7099         vmcs_load(vmx->loaded_vmcs->vmcs);
7100
7101         preempt_enable();
7102 }
7103
7104 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7105 {
7106         const unsigned long *fields[] = {
7107                 shadow_read_write_fields,
7108                 shadow_read_only_fields
7109         };
7110         const int max_fields[] = {
7111                 max_shadow_read_write_fields,
7112                 max_shadow_read_only_fields
7113         };
7114         int i, q;
7115         unsigned long field;
7116         u64 field_value = 0;
7117         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7118
7119         vmcs_load(shadow_vmcs);
7120
7121         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7122                 for (i = 0; i < max_fields[q]; i++) {
7123                         field = fields[q][i];
7124                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7125
7126                         switch (vmcs_field_type(field)) {
7127                         case VMCS_FIELD_TYPE_U16:
7128                                 vmcs_write16(field, (u16)field_value);
7129                                 break;
7130                         case VMCS_FIELD_TYPE_U32:
7131                                 vmcs_write32(field, (u32)field_value);
7132                                 break;
7133                         case VMCS_FIELD_TYPE_U64:
7134                                 vmcs_write64(field, (u64)field_value);
7135                                 break;
7136                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7137                                 vmcs_writel(field, (long)field_value);
7138                                 break;
7139                         default:
7140                                 WARN_ON(1);
7141                                 break;
7142                         }
7143                 }
7144         }
7145
7146         vmcs_clear(shadow_vmcs);
7147         vmcs_load(vmx->loaded_vmcs->vmcs);
7148 }
7149
7150 /*
7151  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7152  * used before) all generate the same failure when it is missing.
7153  */
7154 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7155 {
7156         struct vcpu_vmx *vmx = to_vmx(vcpu);
7157         if (vmx->nested.current_vmptr == -1ull) {
7158                 nested_vmx_failInvalid(vcpu);
7159                 skip_emulated_instruction(vcpu);
7160                 return 0;
7161         }
7162         return 1;
7163 }
7164
7165 static int handle_vmread(struct kvm_vcpu *vcpu)
7166 {
7167         unsigned long field;
7168         u64 field_value;
7169         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7170         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7171         gva_t gva = 0;
7172
7173         if (!nested_vmx_check_permission(vcpu) ||
7174             !nested_vmx_check_vmcs12(vcpu))
7175                 return 1;
7176
7177         /* Decode instruction info and find the field to read */
7178         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7179         /* Read the field, zero-extended to a u64 field_value */
7180         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7181                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7182                 skip_emulated_instruction(vcpu);
7183                 return 1;
7184         }
7185         /*
7186          * Now copy part of this value to register or memory, as requested.
7187          * Note that the number of bits actually copied is 32 or 64 depending
7188          * on the guest's mode (32 or 64 bit), not on the given field's length.
7189          */
7190         if (vmx_instruction_info & (1u << 10)) {
7191                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7192                         field_value);
7193         } else {
7194                 if (get_vmx_mem_address(vcpu, exit_qualification,
7195                                 vmx_instruction_info, true, &gva))
7196                         return 1;
7197                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7198                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7199                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7200         }
7201
7202         nested_vmx_succeed(vcpu);
7203         skip_emulated_instruction(vcpu);
7204         return 1;
7205 }
7206
7207
7208 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7209 {
7210         unsigned long field;
7211         gva_t gva;
7212         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7213         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7214         /* The value to write might be 32 or 64 bits, depending on L1's long
7215          * mode, and eventually we need to write that into a field of several
7216          * possible lengths. The code below first zero-extends the value to 64
7217          * bit (field_value), and then copies only the approriate number of
7218          * bits into the vmcs12 field.
7219          */
7220         u64 field_value = 0;
7221         struct x86_exception e;
7222
7223         if (!nested_vmx_check_permission(vcpu) ||
7224             !nested_vmx_check_vmcs12(vcpu))
7225                 return 1;
7226
7227         if (vmx_instruction_info & (1u << 10))
7228                 field_value = kvm_register_readl(vcpu,
7229                         (((vmx_instruction_info) >> 3) & 0xf));
7230         else {
7231                 if (get_vmx_mem_address(vcpu, exit_qualification,
7232                                 vmx_instruction_info, false, &gva))
7233                         return 1;
7234                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7235                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7236                         kvm_inject_page_fault(vcpu, &e);
7237                         return 1;
7238                 }
7239         }
7240
7241
7242         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7243         if (vmcs_field_readonly(field)) {
7244                 nested_vmx_failValid(vcpu,
7245                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7246                 skip_emulated_instruction(vcpu);
7247                 return 1;
7248         }
7249
7250         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7251                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7252                 skip_emulated_instruction(vcpu);
7253                 return 1;
7254         }
7255
7256         nested_vmx_succeed(vcpu);
7257         skip_emulated_instruction(vcpu);
7258         return 1;
7259 }
7260
7261 /* Emulate the VMPTRLD instruction */
7262 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7263 {
7264         struct vcpu_vmx *vmx = to_vmx(vcpu);
7265         gpa_t vmptr;
7266
7267         if (!nested_vmx_check_permission(vcpu))
7268                 return 1;
7269
7270         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7271                 return 1;
7272
7273         if (vmx->nested.current_vmptr != vmptr) {
7274                 struct vmcs12 *new_vmcs12;
7275                 struct page *page;
7276                 page = nested_get_page(vcpu, vmptr);
7277                 if (page == NULL) {
7278                         nested_vmx_failInvalid(vcpu);
7279                         skip_emulated_instruction(vcpu);
7280                         return 1;
7281                 }
7282                 new_vmcs12 = kmap(page);
7283                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7284                         kunmap(page);
7285                         nested_release_page_clean(page);
7286                         nested_vmx_failValid(vcpu,
7287                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7288                         skip_emulated_instruction(vcpu);
7289                         return 1;
7290                 }
7291
7292                 nested_release_vmcs12(vmx);
7293                 vmx->nested.current_vmptr = vmptr;
7294                 vmx->nested.current_vmcs12 = new_vmcs12;
7295                 vmx->nested.current_vmcs12_page = page;
7296                 if (enable_shadow_vmcs) {
7297                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7298                                       SECONDARY_EXEC_SHADOW_VMCS);
7299                         vmcs_write64(VMCS_LINK_POINTER,
7300                                      __pa(vmx->nested.current_shadow_vmcs));
7301                         vmx->nested.sync_shadow_vmcs = true;
7302                 }
7303         }
7304
7305         nested_vmx_succeed(vcpu);
7306         skip_emulated_instruction(vcpu);
7307         return 1;
7308 }
7309
7310 /* Emulate the VMPTRST instruction */
7311 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7312 {
7313         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7314         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7315         gva_t vmcs_gva;
7316         struct x86_exception e;
7317
7318         if (!nested_vmx_check_permission(vcpu))
7319                 return 1;
7320
7321         if (get_vmx_mem_address(vcpu, exit_qualification,
7322                         vmx_instruction_info, true, &vmcs_gva))
7323                 return 1;
7324         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7325         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7326                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7327                                  sizeof(u64), &e)) {
7328                 kvm_inject_page_fault(vcpu, &e);
7329                 return 1;
7330         }
7331         nested_vmx_succeed(vcpu);
7332         skip_emulated_instruction(vcpu);
7333         return 1;
7334 }
7335
7336 /* Emulate the INVEPT instruction */
7337 static int handle_invept(struct kvm_vcpu *vcpu)
7338 {
7339         struct vcpu_vmx *vmx = to_vmx(vcpu);
7340         u32 vmx_instruction_info, types;
7341         unsigned long type;
7342         gva_t gva;
7343         struct x86_exception e;
7344         struct {
7345                 u64 eptp, gpa;
7346         } operand;
7347
7348         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7349               SECONDARY_EXEC_ENABLE_EPT) ||
7350             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7351                 kvm_queue_exception(vcpu, UD_VECTOR);
7352                 return 1;
7353         }
7354
7355         if (!nested_vmx_check_permission(vcpu))
7356                 return 1;
7357
7358         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7359                 kvm_queue_exception(vcpu, UD_VECTOR);
7360                 return 1;
7361         }
7362
7363         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7364         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7365
7366         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7367
7368         if (!(types & (1UL << type))) {
7369                 nested_vmx_failValid(vcpu,
7370                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7371                 skip_emulated_instruction(vcpu);
7372                 return 1;
7373         }
7374
7375         /* According to the Intel VMX instruction reference, the memory
7376          * operand is read even if it isn't needed (e.g., for type==global)
7377          */
7378         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7379                         vmx_instruction_info, false, &gva))
7380                 return 1;
7381         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7382                                 sizeof(operand), &e)) {
7383                 kvm_inject_page_fault(vcpu, &e);
7384                 return 1;
7385         }
7386
7387         switch (type) {
7388         case VMX_EPT_EXTENT_GLOBAL:
7389                 kvm_mmu_sync_roots(vcpu);
7390                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7391                 nested_vmx_succeed(vcpu);
7392                 break;
7393         default:
7394                 /* Trap single context invalidation invept calls */
7395                 BUG_ON(1);
7396                 break;
7397         }
7398
7399         skip_emulated_instruction(vcpu);
7400         return 1;
7401 }
7402
7403 static int handle_invvpid(struct kvm_vcpu *vcpu)
7404 {
7405         struct vcpu_vmx *vmx = to_vmx(vcpu);
7406         u32 vmx_instruction_info;
7407         unsigned long type, types;
7408         gva_t gva;
7409         struct x86_exception e;
7410         int vpid;
7411
7412         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7413               SECONDARY_EXEC_ENABLE_VPID) ||
7414                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7415                 kvm_queue_exception(vcpu, UD_VECTOR);
7416                 return 1;
7417         }
7418
7419         if (!nested_vmx_check_permission(vcpu))
7420                 return 1;
7421
7422         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7423         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7424
7425         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7426
7427         if (!(types & (1UL << type))) {
7428                 nested_vmx_failValid(vcpu,
7429                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7430                 skip_emulated_instruction(vcpu);
7431                 return 1;
7432         }
7433
7434         /* according to the intel vmx instruction reference, the memory
7435          * operand is read even if it isn't needed (e.g., for type==global)
7436          */
7437         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7438                         vmx_instruction_info, false, &gva))
7439                 return 1;
7440         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7441                                 sizeof(u32), &e)) {
7442                 kvm_inject_page_fault(vcpu, &e);
7443                 return 1;
7444         }
7445
7446         switch (type) {
7447         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7448                 /*
7449                  * Old versions of KVM use the single-context version so we
7450                  * have to support it; just treat it the same as all-context.
7451                  */
7452         case VMX_VPID_EXTENT_ALL_CONTEXT:
7453                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7454                 nested_vmx_succeed(vcpu);
7455                 break;
7456         default:
7457                 /* Trap individual address invalidation invvpid calls */
7458                 BUG_ON(1);
7459                 break;
7460         }
7461
7462         skip_emulated_instruction(vcpu);
7463         return 1;
7464 }
7465
7466 static int handle_pml_full(struct kvm_vcpu *vcpu)
7467 {
7468         unsigned long exit_qualification;
7469
7470         trace_kvm_pml_full(vcpu->vcpu_id);
7471
7472         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7473
7474         /*
7475          * PML buffer FULL happened while executing iret from NMI,
7476          * "blocked by NMI" bit has to be set before next VM entry.
7477          */
7478         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7479                         cpu_has_virtual_nmis() &&
7480                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7481                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7482                                 GUEST_INTR_STATE_NMI);
7483
7484         /*
7485          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7486          * here.., and there's no userspace involvement needed for PML.
7487          */
7488         return 1;
7489 }
7490
7491 static int handle_pcommit(struct kvm_vcpu *vcpu)
7492 {
7493         /* we never catch pcommit instruct for L1 guest. */
7494         WARN_ON(1);
7495         return 1;
7496 }
7497
7498 /*
7499  * The exit handlers return 1 if the exit was handled fully and guest execution
7500  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7501  * to be done to userspace and return 0.
7502  */
7503 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7504         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7505         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7506         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7507         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7508         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7509         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7510         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7511         [EXIT_REASON_CPUID]                   = handle_cpuid,
7512         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7513         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7514         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7515         [EXIT_REASON_HLT]                     = handle_halt,
7516         [EXIT_REASON_INVD]                    = handle_invd,
7517         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7518         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7519         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7520         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7521         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7522         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7523         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7524         [EXIT_REASON_VMREAD]                  = handle_vmread,
7525         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7526         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7527         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7528         [EXIT_REASON_VMON]                    = handle_vmon,
7529         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7530         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7531         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7532         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7533         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7534         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7535         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7536         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7537         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7538         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7539         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7540         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7541         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7542         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7543         [EXIT_REASON_INVEPT]                  = handle_invept,
7544         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7545         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7546         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7547         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7548         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7549 };
7550
7551 static const int kvm_vmx_max_exit_handlers =
7552         ARRAY_SIZE(kvm_vmx_exit_handlers);
7553
7554 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7555                                        struct vmcs12 *vmcs12)
7556 {
7557         unsigned long exit_qualification;
7558         gpa_t bitmap, last_bitmap;
7559         unsigned int port;
7560         int size;
7561         u8 b;
7562
7563         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7564                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7565
7566         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7567
7568         port = exit_qualification >> 16;
7569         size = (exit_qualification & 7) + 1;
7570
7571         last_bitmap = (gpa_t)-1;
7572         b = -1;
7573
7574         while (size > 0) {
7575                 if (port < 0x8000)
7576                         bitmap = vmcs12->io_bitmap_a;
7577                 else if (port < 0x10000)
7578                         bitmap = vmcs12->io_bitmap_b;
7579                 else
7580                         return true;
7581                 bitmap += (port & 0x7fff) / 8;
7582
7583                 if (last_bitmap != bitmap)
7584                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7585                                 return true;
7586                 if (b & (1 << (port & 7)))
7587                         return true;
7588
7589                 port++;
7590                 size--;
7591                 last_bitmap = bitmap;
7592         }
7593
7594         return false;
7595 }
7596
7597 /*
7598  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7599  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7600  * disinterest in the current event (read or write a specific MSR) by using an
7601  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7602  */
7603 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7604         struct vmcs12 *vmcs12, u32 exit_reason)
7605 {
7606         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7607         gpa_t bitmap;
7608
7609         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7610                 return true;
7611
7612         /*
7613          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7614          * for the four combinations of read/write and low/high MSR numbers.
7615          * First we need to figure out which of the four to use:
7616          */
7617         bitmap = vmcs12->msr_bitmap;
7618         if (exit_reason == EXIT_REASON_MSR_WRITE)
7619                 bitmap += 2048;
7620         if (msr_index >= 0xc0000000) {
7621                 msr_index -= 0xc0000000;
7622                 bitmap += 1024;
7623         }
7624
7625         /* Then read the msr_index'th bit from this bitmap: */
7626         if (msr_index < 1024*8) {
7627                 unsigned char b;
7628                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7629                         return true;
7630                 return 1 & (b >> (msr_index & 7));
7631         } else
7632                 return true; /* let L1 handle the wrong parameter */
7633 }
7634
7635 /*
7636  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7637  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7638  * intercept (via guest_host_mask etc.) the current event.
7639  */
7640 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7641         struct vmcs12 *vmcs12)
7642 {
7643         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7644         int cr = exit_qualification & 15;
7645         int reg = (exit_qualification >> 8) & 15;
7646         unsigned long val = kvm_register_readl(vcpu, reg);
7647
7648         switch ((exit_qualification >> 4) & 3) {
7649         case 0: /* mov to cr */
7650                 switch (cr) {
7651                 case 0:
7652                         if (vmcs12->cr0_guest_host_mask &
7653                             (val ^ vmcs12->cr0_read_shadow))
7654                                 return true;
7655                         break;
7656                 case 3:
7657                         if ((vmcs12->cr3_target_count >= 1 &&
7658                                         vmcs12->cr3_target_value0 == val) ||
7659                                 (vmcs12->cr3_target_count >= 2 &&
7660                                         vmcs12->cr3_target_value1 == val) ||
7661                                 (vmcs12->cr3_target_count >= 3 &&
7662                                         vmcs12->cr3_target_value2 == val) ||
7663                                 (vmcs12->cr3_target_count >= 4 &&
7664                                         vmcs12->cr3_target_value3 == val))
7665                                 return false;
7666                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7667                                 return true;
7668                         break;
7669                 case 4:
7670                         if (vmcs12->cr4_guest_host_mask &
7671                             (vmcs12->cr4_read_shadow ^ val))
7672                                 return true;
7673                         break;
7674                 case 8:
7675                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7676                                 return true;
7677                         break;
7678                 }
7679                 break;
7680         case 2: /* clts */
7681                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7682                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7683                         return true;
7684                 break;
7685         case 1: /* mov from cr */
7686                 switch (cr) {
7687                 case 3:
7688                         if (vmcs12->cpu_based_vm_exec_control &
7689                             CPU_BASED_CR3_STORE_EXITING)
7690                                 return true;
7691                         break;
7692                 case 8:
7693                         if (vmcs12->cpu_based_vm_exec_control &
7694                             CPU_BASED_CR8_STORE_EXITING)
7695                                 return true;
7696                         break;
7697                 }
7698                 break;
7699         case 3: /* lmsw */
7700                 /*
7701                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7702                  * cr0. Other attempted changes are ignored, with no exit.
7703                  */
7704                 if (vmcs12->cr0_guest_host_mask & 0xe &
7705                     (val ^ vmcs12->cr0_read_shadow))
7706                         return true;
7707                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7708                     !(vmcs12->cr0_read_shadow & 0x1) &&
7709                     (val & 0x1))
7710                         return true;
7711                 break;
7712         }
7713         return false;
7714 }
7715
7716 /*
7717  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7718  * should handle it ourselves in L0 (and then continue L2). Only call this
7719  * when in is_guest_mode (L2).
7720  */
7721 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7722 {
7723         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7724         struct vcpu_vmx *vmx = to_vmx(vcpu);
7725         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7726         u32 exit_reason = vmx->exit_reason;
7727
7728         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7729                                 vmcs_readl(EXIT_QUALIFICATION),
7730                                 vmx->idt_vectoring_info,
7731                                 intr_info,
7732                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7733                                 KVM_ISA_VMX);
7734
7735         if (vmx->nested.nested_run_pending)
7736                 return false;
7737
7738         if (unlikely(vmx->fail)) {
7739                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7740                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7741                 return true;
7742         }
7743
7744         switch (exit_reason) {
7745         case EXIT_REASON_EXCEPTION_NMI:
7746                 if (is_nmi(intr_info))
7747                         return false;
7748                 else if (is_page_fault(intr_info))
7749                         return enable_ept;
7750                 else if (is_no_device(intr_info) &&
7751                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7752                         return false;
7753                 return vmcs12->exception_bitmap &
7754                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7755         case EXIT_REASON_EXTERNAL_INTERRUPT:
7756                 return false;
7757         case EXIT_REASON_TRIPLE_FAULT:
7758                 return true;
7759         case EXIT_REASON_PENDING_INTERRUPT:
7760                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7761         case EXIT_REASON_NMI_WINDOW:
7762                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7763         case EXIT_REASON_TASK_SWITCH:
7764                 return true;
7765         case EXIT_REASON_CPUID:
7766                 return true;
7767         case EXIT_REASON_HLT:
7768                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7769         case EXIT_REASON_INVD:
7770                 return true;
7771         case EXIT_REASON_INVLPG:
7772                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7773         case EXIT_REASON_RDPMC:
7774                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7775         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7776                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7777         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7778         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7779         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7780         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7781         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7782         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7783                 /*
7784                  * VMX instructions trap unconditionally. This allows L1 to
7785                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7786                  */
7787                 return true;
7788         case EXIT_REASON_CR_ACCESS:
7789                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7790         case EXIT_REASON_DR_ACCESS:
7791                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7792         case EXIT_REASON_IO_INSTRUCTION:
7793                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7794         case EXIT_REASON_MSR_READ:
7795         case EXIT_REASON_MSR_WRITE:
7796                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7797         case EXIT_REASON_INVALID_STATE:
7798                 return true;
7799         case EXIT_REASON_MWAIT_INSTRUCTION:
7800                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7801         case EXIT_REASON_MONITOR_TRAP_FLAG:
7802                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7803         case EXIT_REASON_MONITOR_INSTRUCTION:
7804                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7805         case EXIT_REASON_PAUSE_INSTRUCTION:
7806                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7807                         nested_cpu_has2(vmcs12,
7808                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7809         case EXIT_REASON_MCE_DURING_VMENTRY:
7810                 return false;
7811         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7812                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7813         case EXIT_REASON_APIC_ACCESS:
7814                 return nested_cpu_has2(vmcs12,
7815                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7816         case EXIT_REASON_APIC_WRITE:
7817         case EXIT_REASON_EOI_INDUCED:
7818                 /* apic_write and eoi_induced should exit unconditionally. */
7819                 return true;
7820         case EXIT_REASON_EPT_VIOLATION:
7821                 /*
7822                  * L0 always deals with the EPT violation. If nested EPT is
7823                  * used, and the nested mmu code discovers that the address is
7824                  * missing in the guest EPT table (EPT12), the EPT violation
7825                  * will be injected with nested_ept_inject_page_fault()
7826                  */
7827                 return false;
7828         case EXIT_REASON_EPT_MISCONFIG:
7829                 /*
7830                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7831                  * table (shadow on EPT) or a merged EPT table that L0 built
7832                  * (EPT on EPT). So any problems with the structure of the
7833                  * table is L0's fault.
7834                  */
7835                 return false;
7836         case EXIT_REASON_WBINVD:
7837                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7838         case EXIT_REASON_XSETBV:
7839                 return true;
7840         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7841                 /*
7842                  * This should never happen, since it is not possible to
7843                  * set XSS to a non-zero value---neither in L1 nor in L2.
7844                  * If if it were, XSS would have to be checked against
7845                  * the XSS exit bitmap in vmcs12.
7846                  */
7847                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7848         case EXIT_REASON_PCOMMIT:
7849                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7850         case EXIT_REASON_PML_FULL:
7851                 /* We don't expose PML support to L1. */
7852                 return false;
7853         default:
7854                 return true;
7855         }
7856 }
7857
7858 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7859 {
7860         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7861         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7862 }
7863
7864 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7865 {
7866         if (vmx->pml_pg) {
7867                 __free_page(vmx->pml_pg);
7868                 vmx->pml_pg = NULL;
7869         }
7870 }
7871
7872 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7873 {
7874         struct vcpu_vmx *vmx = to_vmx(vcpu);
7875         u64 *pml_buf;
7876         u16 pml_idx;
7877
7878         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7879
7880         /* Do nothing if PML buffer is empty */
7881         if (pml_idx == (PML_ENTITY_NUM - 1))
7882                 return;
7883
7884         /* PML index always points to next available PML buffer entity */
7885         if (pml_idx >= PML_ENTITY_NUM)
7886                 pml_idx = 0;
7887         else
7888                 pml_idx++;
7889
7890         pml_buf = page_address(vmx->pml_pg);
7891         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7892                 u64 gpa;
7893
7894                 gpa = pml_buf[pml_idx];
7895                 WARN_ON(gpa & (PAGE_SIZE - 1));
7896                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7897         }
7898
7899         /* reset PML index */
7900         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7901 }
7902
7903 /*
7904  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7905  * Called before reporting dirty_bitmap to userspace.
7906  */
7907 static void kvm_flush_pml_buffers(struct kvm *kvm)
7908 {
7909         int i;
7910         struct kvm_vcpu *vcpu;
7911         /*
7912          * We only need to kick vcpu out of guest mode here, as PML buffer
7913          * is flushed at beginning of all VMEXITs, and it's obvious that only
7914          * vcpus running in guest are possible to have unflushed GPAs in PML
7915          * buffer.
7916          */
7917         kvm_for_each_vcpu(i, vcpu, kvm)
7918                 kvm_vcpu_kick(vcpu);
7919 }
7920
7921 static void vmx_dump_sel(char *name, uint32_t sel)
7922 {
7923         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7924                name, vmcs_read16(sel),
7925                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7926                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7927                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7928 }
7929
7930 static void vmx_dump_dtsel(char *name, uint32_t limit)
7931 {
7932         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7933                name, vmcs_read32(limit),
7934                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7935 }
7936
7937 static void dump_vmcs(void)
7938 {
7939         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7940         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7941         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7942         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7943         u32 secondary_exec_control = 0;
7944         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7945         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7946         int i, n;
7947
7948         if (cpu_has_secondary_exec_ctrls())
7949                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7950
7951         pr_err("*** Guest State ***\n");
7952         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7953                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7954                vmcs_readl(CR0_GUEST_HOST_MASK));
7955         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7956                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7957         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7958         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7959             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7960         {
7961                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7962                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7963                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7964                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7965         }
7966         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7967                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7968         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7969                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7970         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7971                vmcs_readl(GUEST_SYSENTER_ESP),
7972                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7973         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7974         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7975         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7976         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7977         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7978         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7979         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7980         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7981         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7982         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7983         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7984             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7985                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7986                        efer, vmcs_readl(GUEST_IA32_PAT));
7987         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7988                vmcs_readl(GUEST_IA32_DEBUGCTL),
7989                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7990         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7991                 pr_err("PerfGlobCtl = 0x%016lx\n",
7992                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7993         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7994                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7995         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7996                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7997                vmcs_read32(GUEST_ACTIVITY_STATE));
7998         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7999                 pr_err("InterruptStatus = %04x\n",
8000                        vmcs_read16(GUEST_INTR_STATUS));
8001
8002         pr_err("*** Host State ***\n");
8003         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8004                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8005         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8006                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8007                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8008                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8009                vmcs_read16(HOST_TR_SELECTOR));
8010         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8011                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8012                vmcs_readl(HOST_TR_BASE));
8013         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8014                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8015         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8016                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8017                vmcs_readl(HOST_CR4));
8018         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8019                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8020                vmcs_read32(HOST_IA32_SYSENTER_CS),
8021                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8022         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8023                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
8024                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
8025         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8026                 pr_err("PerfGlobCtl = 0x%016lx\n",
8027                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
8028
8029         pr_err("*** Control State ***\n");
8030         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8031                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8032         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8033         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8034                vmcs_read32(EXCEPTION_BITMAP),
8035                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8036                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8037         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8038                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8039                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8040                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8041         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8042                vmcs_read32(VM_EXIT_INTR_INFO),
8043                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8044                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8045         pr_err("        reason=%08x qualification=%016lx\n",
8046                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8047         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8048                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8049                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8050         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8051         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8052                 pr_err("TSC Multiplier = 0x%016lx\n",
8053                        vmcs_readl(TSC_MULTIPLIER));
8054         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8055                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8056         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8057                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8058         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8059                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8060         n = vmcs_read32(CR3_TARGET_COUNT);
8061         for (i = 0; i + 1 < n; i += 4)
8062                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8063                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8064                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8065         if (i < n)
8066                 pr_err("CR3 target%u=%016lx\n",
8067                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8068         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8069                 pr_err("PLE Gap=%08x Window=%08x\n",
8070                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8071         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8072                 pr_err("Virtual processor ID = 0x%04x\n",
8073                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8074 }
8075
8076 /*
8077  * The guest has exited.  See if we can fix it or if we need userspace
8078  * assistance.
8079  */
8080 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8081 {
8082         struct vcpu_vmx *vmx = to_vmx(vcpu);
8083         u32 exit_reason = vmx->exit_reason;
8084         u32 vectoring_info = vmx->idt_vectoring_info;
8085
8086         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8087
8088         /*
8089          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8090          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8091          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8092          * mode as if vcpus is in root mode, the PML buffer must has been
8093          * flushed already.
8094          */
8095         if (enable_pml)
8096                 vmx_flush_pml_buffer(vcpu);
8097
8098         /* If guest state is invalid, start emulating */
8099         if (vmx->emulation_required)
8100                 return handle_invalid_guest_state(vcpu);
8101
8102         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8103                 nested_vmx_vmexit(vcpu, exit_reason,
8104                                   vmcs_read32(VM_EXIT_INTR_INFO),
8105                                   vmcs_readl(EXIT_QUALIFICATION));
8106                 return 1;
8107         }
8108
8109         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8110                 dump_vmcs();
8111                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8112                 vcpu->run->fail_entry.hardware_entry_failure_reason
8113                         = exit_reason;
8114                 return 0;
8115         }
8116
8117         if (unlikely(vmx->fail)) {
8118                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8119                 vcpu->run->fail_entry.hardware_entry_failure_reason
8120                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8121                 return 0;
8122         }
8123
8124         /*
8125          * Note:
8126          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8127          * delivery event since it indicates guest is accessing MMIO.
8128          * The vm-exit can be triggered again after return to guest that
8129          * will cause infinite loop.
8130          */
8131         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8132                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8133                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8134                         exit_reason != EXIT_REASON_PML_FULL &&
8135                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8136                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8137                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8138                 vcpu->run->internal.ndata = 2;
8139                 vcpu->run->internal.data[0] = vectoring_info;
8140                 vcpu->run->internal.data[1] = exit_reason;
8141                 return 0;
8142         }
8143
8144         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8145             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8146                                         get_vmcs12(vcpu))))) {
8147                 if (vmx_interrupt_allowed(vcpu)) {
8148                         vmx->soft_vnmi_blocked = 0;
8149                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8150                            vcpu->arch.nmi_pending) {
8151                         /*
8152                          * This CPU don't support us in finding the end of an
8153                          * NMI-blocked window if the guest runs with IRQs
8154                          * disabled. So we pull the trigger after 1 s of
8155                          * futile waiting, but inform the user about this.
8156                          */
8157                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8158                                "state on VCPU %d after 1 s timeout\n",
8159                                __func__, vcpu->vcpu_id);
8160                         vmx->soft_vnmi_blocked = 0;
8161                 }
8162         }
8163
8164         if (exit_reason < kvm_vmx_max_exit_handlers
8165             && kvm_vmx_exit_handlers[exit_reason])
8166                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8167         else {
8168                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8169                 kvm_queue_exception(vcpu, UD_VECTOR);
8170                 return 1;
8171         }
8172 }
8173
8174 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8175 {
8176         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8177
8178         if (is_guest_mode(vcpu) &&
8179                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8180                 return;
8181
8182         if (irr == -1 || tpr < irr) {
8183                 vmcs_write32(TPR_THRESHOLD, 0);
8184                 return;
8185         }
8186
8187         vmcs_write32(TPR_THRESHOLD, irr);
8188 }
8189
8190 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8191 {
8192         u32 sec_exec_control;
8193
8194         /* Postpone execution until vmcs01 is the current VMCS. */
8195         if (is_guest_mode(vcpu)) {
8196                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8197                 return;
8198         }
8199
8200         /*
8201          * There is not point to enable virtualize x2apic without enable
8202          * apicv
8203          */
8204         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8205                                 !vmx_cpu_uses_apicv(vcpu))
8206                 return;
8207
8208         if (!cpu_need_tpr_shadow(vcpu))
8209                 return;
8210
8211         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8212
8213         if (set) {
8214                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8215                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8216         } else {
8217                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8218                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8219         }
8220         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8221
8222         vmx_set_msr_bitmap(vcpu);
8223 }
8224
8225 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8226 {
8227         struct vcpu_vmx *vmx = to_vmx(vcpu);
8228
8229         /*
8230          * Currently we do not handle the nested case where L2 has an
8231          * APIC access page of its own; that page is still pinned.
8232          * Hence, we skip the case where the VCPU is in guest mode _and_
8233          * L1 prepared an APIC access page for L2.
8234          *
8235          * For the case where L1 and L2 share the same APIC access page
8236          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8237          * in the vmcs12), this function will only update either the vmcs01
8238          * or the vmcs02.  If the former, the vmcs02 will be updated by
8239          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8240          * the next L2->L1 exit.
8241          */
8242         if (!is_guest_mode(vcpu) ||
8243             !nested_cpu_has2(vmx->nested.current_vmcs12,
8244                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8245                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8246 }
8247
8248 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8249 {
8250         u16 status;
8251         u8 old;
8252
8253         if (isr == -1)
8254                 isr = 0;
8255
8256         status = vmcs_read16(GUEST_INTR_STATUS);
8257         old = status >> 8;
8258         if (isr != old) {
8259                 status &= 0xff;
8260                 status |= isr << 8;
8261                 vmcs_write16(GUEST_INTR_STATUS, status);
8262         }
8263 }
8264
8265 static void vmx_set_rvi(int vector)
8266 {
8267         u16 status;
8268         u8 old;
8269
8270         if (vector == -1)
8271                 vector = 0;
8272
8273         status = vmcs_read16(GUEST_INTR_STATUS);
8274         old = (u8)status & 0xff;
8275         if ((u8)vector != old) {
8276                 status &= ~0xff;
8277                 status |= (u8)vector;
8278                 vmcs_write16(GUEST_INTR_STATUS, status);
8279         }
8280 }
8281
8282 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8283 {
8284         if (!is_guest_mode(vcpu)) {
8285                 vmx_set_rvi(max_irr);
8286                 return;
8287         }
8288
8289         if (max_irr == -1)
8290                 return;
8291
8292         /*
8293          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8294          * handles it.
8295          */
8296         if (nested_exit_on_intr(vcpu))
8297                 return;
8298
8299         /*
8300          * Else, fall back to pre-APICv interrupt injection since L2
8301          * is run without virtual interrupt delivery.
8302          */
8303         if (!kvm_event_needs_reinjection(vcpu) &&
8304             vmx_interrupt_allowed(vcpu)) {
8305                 kvm_queue_interrupt(vcpu, max_irr, false);
8306                 vmx_inject_irq(vcpu);
8307         }
8308 }
8309
8310 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8311 {
8312         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8313         if (!vmx_cpu_uses_apicv(vcpu))
8314                 return;
8315
8316         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8317         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8318         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8319         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8320 }
8321
8322 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8323 {
8324         u32 exit_intr_info;
8325
8326         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8327               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8328                 return;
8329
8330         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8331         exit_intr_info = vmx->exit_intr_info;
8332
8333         /* Handle machine checks before interrupts are enabled */
8334         if (is_machine_check(exit_intr_info))
8335                 kvm_machine_check();
8336
8337         /* We need to handle NMIs before interrupts are enabled */
8338         if (is_nmi(exit_intr_info)) {
8339                 kvm_before_handle_nmi(&vmx->vcpu);
8340                 asm("int $2");
8341                 kvm_after_handle_nmi(&vmx->vcpu);
8342         }
8343 }
8344
8345 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8346 {
8347         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8348
8349         /*
8350          * If external interrupt exists, IF bit is set in rflags/eflags on the
8351          * interrupt stack frame, and interrupt will be enabled on a return
8352          * from interrupt handler.
8353          */
8354         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8355                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8356                 unsigned int vector;
8357                 unsigned long entry;
8358                 gate_desc *desc;
8359                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8360 #ifdef CONFIG_X86_64
8361                 unsigned long tmp;
8362 #endif
8363
8364                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8365                 desc = (gate_desc *)vmx->host_idt_base + vector;
8366                 entry = gate_offset(*desc);
8367                 asm volatile(
8368 #ifdef CONFIG_X86_64
8369                         "mov %%" _ASM_SP ", %[sp]\n\t"
8370                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8371                         "push $%c[ss]\n\t"
8372                         "push %[sp]\n\t"
8373 #endif
8374                         "pushf\n\t"
8375                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8376                         __ASM_SIZE(push) " $%c[cs]\n\t"
8377                         "call *%[entry]\n\t"
8378                         :
8379 #ifdef CONFIG_X86_64
8380                         [sp]"=&r"(tmp)
8381 #endif
8382                         :
8383                         [entry]"r"(entry),
8384                         [ss]"i"(__KERNEL_DS),
8385                         [cs]"i"(__KERNEL_CS)
8386                         );
8387         } else
8388                 local_irq_enable();
8389 }
8390
8391 static bool vmx_has_high_real_mode_segbase(void)
8392 {
8393         return enable_unrestricted_guest || emulate_invalid_guest_state;
8394 }
8395
8396 static bool vmx_mpx_supported(void)
8397 {
8398         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8399                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8400 }
8401
8402 static bool vmx_xsaves_supported(void)
8403 {
8404         return vmcs_config.cpu_based_2nd_exec_ctrl &
8405                 SECONDARY_EXEC_XSAVES;
8406 }
8407
8408 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8409 {
8410         u32 exit_intr_info;
8411         bool unblock_nmi;
8412         u8 vector;
8413         bool idtv_info_valid;
8414
8415         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8416
8417         if (cpu_has_virtual_nmis()) {
8418                 if (vmx->nmi_known_unmasked)
8419                         return;
8420                 /*
8421                  * Can't use vmx->exit_intr_info since we're not sure what
8422                  * the exit reason is.
8423                  */
8424                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8425                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8426                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8427                 /*
8428                  * SDM 3: 27.7.1.2 (September 2008)
8429                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8430                  * a guest IRET fault.
8431                  * SDM 3: 23.2.2 (September 2008)
8432                  * Bit 12 is undefined in any of the following cases:
8433                  *  If the VM exit sets the valid bit in the IDT-vectoring
8434                  *   information field.
8435                  *  If the VM exit is due to a double fault.
8436                  */
8437                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8438                     vector != DF_VECTOR && !idtv_info_valid)
8439                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8440                                       GUEST_INTR_STATE_NMI);
8441                 else
8442                         vmx->nmi_known_unmasked =
8443                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8444                                   & GUEST_INTR_STATE_NMI);
8445         } else if (unlikely(vmx->soft_vnmi_blocked))
8446                 vmx->vnmi_blocked_time +=
8447                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8448 }
8449
8450 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8451                                       u32 idt_vectoring_info,
8452                                       int instr_len_field,
8453                                       int error_code_field)
8454 {
8455         u8 vector;
8456         int type;
8457         bool idtv_info_valid;
8458
8459         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8460
8461         vcpu->arch.nmi_injected = false;
8462         kvm_clear_exception_queue(vcpu);
8463         kvm_clear_interrupt_queue(vcpu);
8464
8465         if (!idtv_info_valid)
8466                 return;
8467
8468         kvm_make_request(KVM_REQ_EVENT, vcpu);
8469
8470         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8471         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8472
8473         switch (type) {
8474         case INTR_TYPE_NMI_INTR:
8475                 vcpu->arch.nmi_injected = true;
8476                 /*
8477                  * SDM 3: 27.7.1.2 (September 2008)
8478                  * Clear bit "block by NMI" before VM entry if a NMI
8479                  * delivery faulted.
8480                  */
8481                 vmx_set_nmi_mask(vcpu, false);
8482                 break;
8483         case INTR_TYPE_SOFT_EXCEPTION:
8484                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8485                 /* fall through */
8486         case INTR_TYPE_HARD_EXCEPTION:
8487                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8488                         u32 err = vmcs_read32(error_code_field);
8489                         kvm_requeue_exception_e(vcpu, vector, err);
8490                 } else
8491                         kvm_requeue_exception(vcpu, vector);
8492                 break;
8493         case INTR_TYPE_SOFT_INTR:
8494                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8495                 /* fall through */
8496         case INTR_TYPE_EXT_INTR:
8497                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8498                 break;
8499         default:
8500                 break;
8501         }
8502 }
8503
8504 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8505 {
8506         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8507                                   VM_EXIT_INSTRUCTION_LEN,
8508                                   IDT_VECTORING_ERROR_CODE);
8509 }
8510
8511 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8512 {
8513         __vmx_complete_interrupts(vcpu,
8514                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8515                                   VM_ENTRY_INSTRUCTION_LEN,
8516                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8517
8518         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8519 }
8520
8521 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8522 {
8523         int i, nr_msrs;
8524         struct perf_guest_switch_msr *msrs;
8525
8526         msrs = perf_guest_get_msrs(&nr_msrs);
8527
8528         if (!msrs)
8529                 return;
8530
8531         for (i = 0; i < nr_msrs; i++)
8532                 if (msrs[i].host == msrs[i].guest)
8533                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8534                 else
8535                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8536                                         msrs[i].host);
8537 }
8538
8539 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8540 {
8541         struct vcpu_vmx *vmx = to_vmx(vcpu);
8542         unsigned long debugctlmsr, cr4;
8543
8544         /* Record the guest's net vcpu time for enforced NMI injections. */
8545         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8546                 vmx->entry_time = ktime_get();
8547
8548         /* Don't enter VMX if guest state is invalid, let the exit handler
8549            start emulation until we arrive back to a valid state */
8550         if (vmx->emulation_required)
8551                 return;
8552
8553         if (vmx->ple_window_dirty) {
8554                 vmx->ple_window_dirty = false;
8555                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8556         }
8557
8558         if (vmx->nested.sync_shadow_vmcs) {
8559                 copy_vmcs12_to_shadow(vmx);
8560                 vmx->nested.sync_shadow_vmcs = false;
8561         }
8562
8563         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8564                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8565         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8566                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8567
8568         cr4 = cr4_read_shadow();
8569         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8570                 vmcs_writel(HOST_CR4, cr4);
8571                 vmx->host_state.vmcs_host_cr4 = cr4;
8572         }
8573
8574         /* When single-stepping over STI and MOV SS, we must clear the
8575          * corresponding interruptibility bits in the guest state. Otherwise
8576          * vmentry fails as it then expects bit 14 (BS) in pending debug
8577          * exceptions being set, but that's not correct for the guest debugging
8578          * case. */
8579         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8580                 vmx_set_interrupt_shadow(vcpu, 0);
8581
8582         atomic_switch_perf_msrs(vmx);
8583         debugctlmsr = get_debugctlmsr();
8584
8585         vmx->__launched = vmx->loaded_vmcs->launched;
8586         asm(
8587                 /* Store host registers */
8588                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8589                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8590                 "push %%" _ASM_CX " \n\t"
8591                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8592                 "je 1f \n\t"
8593                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8594                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8595                 "1: \n\t"
8596                 /* Reload cr2 if changed */
8597                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8598                 "mov %%cr2, %%" _ASM_DX " \n\t"
8599                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8600                 "je 2f \n\t"
8601                 "mov %%" _ASM_AX", %%cr2 \n\t"
8602                 "2: \n\t"
8603                 /* Check if vmlaunch of vmresume is needed */
8604                 "cmpl $0, %c[launched](%0) \n\t"
8605                 /* Load guest registers.  Don't clobber flags. */
8606                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8607                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8608                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8609                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8610                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8611                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8612 #ifdef CONFIG_X86_64
8613                 "mov %c[r8](%0),  %%r8  \n\t"
8614                 "mov %c[r9](%0),  %%r9  \n\t"
8615                 "mov %c[r10](%0), %%r10 \n\t"
8616                 "mov %c[r11](%0), %%r11 \n\t"
8617                 "mov %c[r12](%0), %%r12 \n\t"
8618                 "mov %c[r13](%0), %%r13 \n\t"
8619                 "mov %c[r14](%0), %%r14 \n\t"
8620                 "mov %c[r15](%0), %%r15 \n\t"
8621 #endif
8622                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8623
8624                 /* Enter guest mode */
8625                 "jne 1f \n\t"
8626                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8627                 "jmp 2f \n\t"
8628                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8629                 "2: "
8630                 /* Save guest registers, load host registers, keep flags */
8631                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8632                 "pop %0 \n\t"
8633                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8634                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8635                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8636                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8637                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8638                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8639                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8640 #ifdef CONFIG_X86_64
8641                 "mov %%r8,  %c[r8](%0) \n\t"
8642                 "mov %%r9,  %c[r9](%0) \n\t"
8643                 "mov %%r10, %c[r10](%0) \n\t"
8644                 "mov %%r11, %c[r11](%0) \n\t"
8645                 "mov %%r12, %c[r12](%0) \n\t"
8646                 "mov %%r13, %c[r13](%0) \n\t"
8647                 "mov %%r14, %c[r14](%0) \n\t"
8648                 "mov %%r15, %c[r15](%0) \n\t"
8649 #endif
8650                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8651                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8652
8653                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8654                 "setbe %c[fail](%0) \n\t"
8655                 ".pushsection .rodata \n\t"
8656                 ".global vmx_return \n\t"
8657                 "vmx_return: " _ASM_PTR " 2b \n\t"
8658                 ".popsection"
8659               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8660                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8661                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8662                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8663                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8664                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8665                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8666                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8667                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8668                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8669                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8670 #ifdef CONFIG_X86_64
8671                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8672                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8673                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8674                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8675                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8676                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8677                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8678                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8679 #endif
8680                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8681                 [wordsize]"i"(sizeof(ulong))
8682               : "cc", "memory"
8683 #ifdef CONFIG_X86_64
8684                 , "rax", "rbx", "rdi", "rsi"
8685                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8686 #else
8687                 , "eax", "ebx", "edi", "esi"
8688 #endif
8689               );
8690
8691         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8692         if (debugctlmsr)
8693                 update_debugctlmsr(debugctlmsr);
8694
8695 #ifndef CONFIG_X86_64
8696         /*
8697          * The sysexit path does not restore ds/es, so we must set them to
8698          * a reasonable value ourselves.
8699          *
8700          * We can't defer this to vmx_load_host_state() since that function
8701          * may be executed in interrupt context, which saves and restore segments
8702          * around it, nullifying its effect.
8703          */
8704         loadsegment(ds, __USER_DS);
8705         loadsegment(es, __USER_DS);
8706 #endif
8707
8708         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8709                                   | (1 << VCPU_EXREG_RFLAGS)
8710                                   | (1 << VCPU_EXREG_PDPTR)
8711                                   | (1 << VCPU_EXREG_SEGMENTS)
8712                                   | (1 << VCPU_EXREG_CR3));
8713         vcpu->arch.regs_dirty = 0;
8714
8715         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8716
8717         vmx->loaded_vmcs->launched = 1;
8718
8719         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8720
8721         /*
8722          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8723          * we did not inject a still-pending event to L1 now because of
8724          * nested_run_pending, we need to re-enable this bit.
8725          */
8726         if (vmx->nested.nested_run_pending)
8727                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8728
8729         vmx->nested.nested_run_pending = 0;
8730
8731         vmx_complete_atomic_exit(vmx);
8732         vmx_recover_nmi_blocking(vmx);
8733         vmx_complete_interrupts(vmx);
8734 }
8735
8736 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8737 {
8738         struct vcpu_vmx *vmx = to_vmx(vcpu);
8739         int cpu;
8740
8741         if (vmx->loaded_vmcs == &vmx->vmcs01)
8742                 return;
8743
8744         cpu = get_cpu();
8745         vmx->loaded_vmcs = &vmx->vmcs01;
8746         vmx_vcpu_put(vcpu);
8747         vmx_vcpu_load(vcpu, cpu);
8748         vcpu->cpu = cpu;
8749         put_cpu();
8750 }
8751
8752 /*
8753  * Ensure that the current vmcs of the logical processor is the
8754  * vmcs01 of the vcpu before calling free_nested().
8755  */
8756 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
8757 {
8758        struct vcpu_vmx *vmx = to_vmx(vcpu);
8759        int r;
8760
8761        r = vcpu_load(vcpu);
8762        BUG_ON(r);
8763        vmx_load_vmcs01(vcpu);
8764        free_nested(vmx);
8765        vcpu_put(vcpu);
8766 }
8767
8768 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8769 {
8770         struct vcpu_vmx *vmx = to_vmx(vcpu);
8771
8772         if (enable_pml)
8773                 vmx_destroy_pml_buffer(vmx);
8774         free_vpid(vmx->vpid);
8775         leave_guest_mode(vcpu);
8776         vmx_free_vcpu_nested(vcpu);
8777         free_loaded_vmcs(vmx->loaded_vmcs);
8778         kfree(vmx->guest_msrs);
8779         kvm_vcpu_uninit(vcpu);
8780         kmem_cache_free(kvm_vcpu_cache, vmx);
8781 }
8782
8783 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8784 {
8785         int err;
8786         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8787         int cpu;
8788
8789         if (!vmx)
8790                 return ERR_PTR(-ENOMEM);
8791
8792         vmx->vpid = allocate_vpid();
8793
8794         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8795         if (err)
8796                 goto free_vcpu;
8797
8798         err = -ENOMEM;
8799
8800         /*
8801          * If PML is turned on, failure on enabling PML just results in failure
8802          * of creating the vcpu, therefore we can simplify PML logic (by
8803          * avoiding dealing with cases, such as enabling PML partially on vcpus
8804          * for the guest, etc.
8805          */
8806         if (enable_pml) {
8807                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
8808                 if (!vmx->pml_pg)
8809                         goto uninit_vcpu;
8810         }
8811
8812         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8813         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8814                      > PAGE_SIZE);
8815
8816         if (!vmx->guest_msrs)
8817                 goto free_pml;
8818
8819         vmx->loaded_vmcs = &vmx->vmcs01;
8820         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8821         if (!vmx->loaded_vmcs->vmcs)
8822                 goto free_msrs;
8823         if (!vmm_exclusive)
8824                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8825         loaded_vmcs_init(vmx->loaded_vmcs);
8826         if (!vmm_exclusive)
8827                 kvm_cpu_vmxoff();
8828
8829         cpu = get_cpu();
8830         vmx_vcpu_load(&vmx->vcpu, cpu);
8831         vmx->vcpu.cpu = cpu;
8832         err = vmx_vcpu_setup(vmx);
8833         vmx_vcpu_put(&vmx->vcpu);
8834         put_cpu();
8835         if (err)
8836                 goto free_vmcs;
8837         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8838                 err = alloc_apic_access_page(kvm);
8839                 if (err)
8840                         goto free_vmcs;
8841         }
8842
8843         if (enable_ept) {
8844                 if (!kvm->arch.ept_identity_map_addr)
8845                         kvm->arch.ept_identity_map_addr =
8846                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8847                 err = init_rmode_identity_map(kvm);
8848                 if (err)
8849                         goto free_vmcs;
8850         }
8851
8852         if (nested) {
8853                 nested_vmx_setup_ctls_msrs(vmx);
8854                 vmx->nested.vpid02 = allocate_vpid();
8855         }
8856
8857         vmx->nested.posted_intr_nv = -1;
8858         vmx->nested.current_vmptr = -1ull;
8859         vmx->nested.current_vmcs12 = NULL;
8860
8861         return &vmx->vcpu;
8862
8863 free_vmcs:
8864         free_vpid(vmx->nested.vpid02);
8865         free_loaded_vmcs(vmx->loaded_vmcs);
8866 free_msrs:
8867         kfree(vmx->guest_msrs);
8868 free_pml:
8869         vmx_destroy_pml_buffer(vmx);
8870 uninit_vcpu:
8871         kvm_vcpu_uninit(&vmx->vcpu);
8872 free_vcpu:
8873         free_vpid(vmx->vpid);
8874         kmem_cache_free(kvm_vcpu_cache, vmx);
8875         return ERR_PTR(err);
8876 }
8877
8878 static void __init vmx_check_processor_compat(void *rtn)
8879 {
8880         struct vmcs_config vmcs_conf;
8881
8882         *(int *)rtn = 0;
8883         if (setup_vmcs_config(&vmcs_conf) < 0)
8884                 *(int *)rtn = -EIO;
8885         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8886                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8887                                 smp_processor_id());
8888                 *(int *)rtn = -EIO;
8889         }
8890 }
8891
8892 static int get_ept_level(void)
8893 {
8894         return VMX_EPT_DEFAULT_GAW + 1;
8895 }
8896
8897 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8898 {
8899         u8 cache;
8900         u64 ipat = 0;
8901
8902         /* For VT-d and EPT combination
8903          * 1. MMIO: always map as UC
8904          * 2. EPT with VT-d:
8905          *   a. VT-d without snooping control feature: can't guarantee the
8906          *      result, try to trust guest.
8907          *   b. VT-d with snooping control feature: snooping control feature of
8908          *      VT-d engine can guarantee the cache correctness. Just set it
8909          *      to WB to keep consistent with host. So the same as item 3.
8910          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8911          *    consistent with host MTRR
8912          */
8913         if (is_mmio) {
8914                 cache = MTRR_TYPE_UNCACHABLE;
8915                 goto exit;
8916         }
8917
8918         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8919                 ipat = VMX_EPT_IPAT_BIT;
8920                 cache = MTRR_TYPE_WRBACK;
8921                 goto exit;
8922         }
8923
8924         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8925                 ipat = VMX_EPT_IPAT_BIT;
8926                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8927                         cache = MTRR_TYPE_WRBACK;
8928                 else
8929                         cache = MTRR_TYPE_UNCACHABLE;
8930                 goto exit;
8931         }
8932
8933         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8934
8935 exit:
8936         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8937 }
8938
8939 static int vmx_get_lpage_level(void)
8940 {
8941         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8942                 return PT_DIRECTORY_LEVEL;
8943         else
8944                 /* For shadow and EPT supported 1GB page */
8945                 return PT_PDPE_LEVEL;
8946 }
8947
8948 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8949 {
8950         /*
8951          * These bits in the secondary execution controls field
8952          * are dynamic, the others are mostly based on the hypervisor
8953          * architecture and the guest's CPUID.  Do not touch the
8954          * dynamic bits.
8955          */
8956         u32 mask =
8957                 SECONDARY_EXEC_SHADOW_VMCS |
8958                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8959                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8960
8961         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8962
8963         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8964                      (new_ctl & ~mask) | (cur_ctl & mask));
8965 }
8966
8967 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8968 {
8969         struct kvm_cpuid_entry2 *best;
8970         struct vcpu_vmx *vmx = to_vmx(vcpu);
8971         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8972
8973         if (vmx_rdtscp_supported()) {
8974                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8975                 if (!rdtscp_enabled)
8976                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8977
8978                 if (nested) {
8979                         if (rdtscp_enabled)
8980                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8981                                         SECONDARY_EXEC_RDTSCP;
8982                         else
8983                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8984                                         ~SECONDARY_EXEC_RDTSCP;
8985                 }
8986         }
8987
8988         /* Exposing INVPCID only when PCID is exposed */
8989         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8990         if (vmx_invpcid_supported() &&
8991             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8992             !guest_cpuid_has_pcid(vcpu))) {
8993                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8994
8995                 if (best)
8996                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8997         }
8998
8999         if (cpu_has_secondary_exec_ctrls())
9000                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9001
9002         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9003                 if (guest_cpuid_has_pcommit(vcpu))
9004                         vmx->nested.nested_vmx_secondary_ctls_high |=
9005                                 SECONDARY_EXEC_PCOMMIT;
9006                 else
9007                         vmx->nested.nested_vmx_secondary_ctls_high &=
9008                                 ~SECONDARY_EXEC_PCOMMIT;
9009         }
9010 }
9011
9012 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9013 {
9014         if (func == 1 && nested)
9015                 entry->ecx |= bit(X86_FEATURE_VMX);
9016 }
9017
9018 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9019                 struct x86_exception *fault)
9020 {
9021         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9022         u32 exit_reason;
9023
9024         if (fault->error_code & PFERR_RSVD_MASK)
9025                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9026         else
9027                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9028         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9029         vmcs12->guest_physical_address = fault->address;
9030 }
9031
9032 /* Callbacks for nested_ept_init_mmu_context: */
9033
9034 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9035 {
9036         /* return the page table to be shadowed - in our case, EPT12 */
9037         return get_vmcs12(vcpu)->ept_pointer;
9038 }
9039
9040 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9041 {
9042         WARN_ON(mmu_is_nested(vcpu));
9043         kvm_init_shadow_ept_mmu(vcpu,
9044                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9045                         VMX_EPT_EXECUTE_ONLY_BIT);
9046         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9047         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9048         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9049
9050         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9051 }
9052
9053 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9054 {
9055         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9056 }
9057
9058 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9059                                             u16 error_code)
9060 {
9061         bool inequality, bit;
9062
9063         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9064         inequality =
9065                 (error_code & vmcs12->page_fault_error_code_mask) !=
9066                  vmcs12->page_fault_error_code_match;
9067         return inequality ^ bit;
9068 }
9069
9070 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9071                 struct x86_exception *fault)
9072 {
9073         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9074
9075         WARN_ON(!is_guest_mode(vcpu));
9076
9077         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9078                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9079                                   vmcs_read32(VM_EXIT_INTR_INFO),
9080                                   vmcs_readl(EXIT_QUALIFICATION));
9081         else
9082                 kvm_inject_page_fault(vcpu, fault);
9083 }
9084
9085 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9086                                         struct vmcs12 *vmcs12)
9087 {
9088         struct vcpu_vmx *vmx = to_vmx(vcpu);
9089         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9090
9091         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9092                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9093                     vmcs12->apic_access_addr >> maxphyaddr)
9094                         return false;
9095
9096                 /*
9097                  * Translate L1 physical address to host physical
9098                  * address for vmcs02. Keep the page pinned, so this
9099                  * physical address remains valid. We keep a reference
9100                  * to it so we can release it later.
9101                  */
9102                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9103                         nested_release_page(vmx->nested.apic_access_page);
9104                 vmx->nested.apic_access_page =
9105                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9106         }
9107
9108         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9109                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9110                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9111                         return false;
9112
9113                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9114                         nested_release_page(vmx->nested.virtual_apic_page);
9115                 vmx->nested.virtual_apic_page =
9116                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9117
9118                 /*
9119                  * Failing the vm entry is _not_ what the processor does
9120                  * but it's basically the only possibility we have.
9121                  * We could still enter the guest if CR8 load exits are
9122                  * enabled, CR8 store exits are enabled, and virtualize APIC
9123                  * access is disabled; in this case the processor would never
9124                  * use the TPR shadow and we could simply clear the bit from
9125                  * the execution control.  But such a configuration is useless,
9126                  * so let's keep the code simple.
9127                  */
9128                 if (!vmx->nested.virtual_apic_page)
9129                         return false;
9130         }
9131
9132         if (nested_cpu_has_posted_intr(vmcs12)) {
9133                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9134                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9135                         return false;
9136
9137                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9138                         kunmap(vmx->nested.pi_desc_page);
9139                         nested_release_page(vmx->nested.pi_desc_page);
9140                 }
9141                 vmx->nested.pi_desc_page =
9142                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9143                 if (!vmx->nested.pi_desc_page)
9144                         return false;
9145
9146                 vmx->nested.pi_desc =
9147                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9148                 if (!vmx->nested.pi_desc) {
9149                         nested_release_page_clean(vmx->nested.pi_desc_page);
9150                         return false;
9151                 }
9152                 vmx->nested.pi_desc =
9153                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9154                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9155                         (PAGE_SIZE - 1)));
9156         }
9157
9158         return true;
9159 }
9160
9161 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9162 {
9163         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9164         struct vcpu_vmx *vmx = to_vmx(vcpu);
9165
9166         if (vcpu->arch.virtual_tsc_khz == 0)
9167                 return;
9168
9169         /* Make sure short timeouts reliably trigger an immediate vmexit.
9170          * hrtimer_start does not guarantee this. */
9171         if (preemption_timeout <= 1) {
9172                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9173                 return;
9174         }
9175
9176         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9177         preemption_timeout *= 1000000;
9178         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9179         hrtimer_start(&vmx->nested.preemption_timer,
9180                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9181 }
9182
9183 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9184                                                 struct vmcs12 *vmcs12)
9185 {
9186         int maxphyaddr;
9187         u64 addr;
9188
9189         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9190                 return 0;
9191
9192         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9193                 WARN_ON(1);
9194                 return -EINVAL;
9195         }
9196         maxphyaddr = cpuid_maxphyaddr(vcpu);
9197
9198         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9199            ((addr + PAGE_SIZE) >> maxphyaddr))
9200                 return -EINVAL;
9201
9202         return 0;
9203 }
9204
9205 /*
9206  * Merge L0's and L1's MSR bitmap, return false to indicate that
9207  * we do not use the hardware.
9208  */
9209 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9210                                                struct vmcs12 *vmcs12)
9211 {
9212         int msr;
9213         struct page *page;
9214         unsigned long *msr_bitmap;
9215
9216         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9217                 return false;
9218
9219         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9220         if (!page) {
9221                 WARN_ON(1);
9222                 return false;
9223         }
9224         msr_bitmap = (unsigned long *)kmap(page);
9225         if (!msr_bitmap) {
9226                 nested_release_page_clean(page);
9227                 WARN_ON(1);
9228                 return false;
9229         }
9230
9231         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9232                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9233                         for (msr = 0x800; msr <= 0x8ff; msr++)
9234                                 nested_vmx_disable_intercept_for_msr(
9235                                         msr_bitmap,
9236                                         vmx_msr_bitmap_nested,
9237                                         msr, MSR_TYPE_R);
9238                 /* TPR is allowed */
9239                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9240                                 vmx_msr_bitmap_nested,
9241                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9242                                 MSR_TYPE_R | MSR_TYPE_W);
9243                 if (nested_cpu_has_vid(vmcs12)) {
9244                         /* EOI and self-IPI are allowed */
9245                         nested_vmx_disable_intercept_for_msr(
9246                                 msr_bitmap,
9247                                 vmx_msr_bitmap_nested,
9248                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9249                                 MSR_TYPE_W);
9250                         nested_vmx_disable_intercept_for_msr(
9251                                 msr_bitmap,
9252                                 vmx_msr_bitmap_nested,
9253                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9254                                 MSR_TYPE_W);
9255                 }
9256         } else {
9257                 /*
9258                  * Enable reading intercept of all the x2apic
9259                  * MSRs. We should not rely on vmcs12 to do any
9260                  * optimizations here, it may have been modified
9261                  * by L1.
9262                  */
9263                 for (msr = 0x800; msr <= 0x8ff; msr++)
9264                         __vmx_enable_intercept_for_msr(
9265                                 vmx_msr_bitmap_nested,
9266                                 msr,
9267                                 MSR_TYPE_R);
9268
9269                 __vmx_enable_intercept_for_msr(
9270                                 vmx_msr_bitmap_nested,
9271                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9272                                 MSR_TYPE_W);
9273                 __vmx_enable_intercept_for_msr(
9274                                 vmx_msr_bitmap_nested,
9275                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9276                                 MSR_TYPE_W);
9277                 __vmx_enable_intercept_for_msr(
9278                                 vmx_msr_bitmap_nested,
9279                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9280                                 MSR_TYPE_W);
9281         }
9282         kunmap(page);
9283         nested_release_page_clean(page);
9284
9285         return true;
9286 }
9287
9288 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9289                                            struct vmcs12 *vmcs12)
9290 {
9291         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9292             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9293             !nested_cpu_has_vid(vmcs12) &&
9294             !nested_cpu_has_posted_intr(vmcs12))
9295                 return 0;
9296
9297         /*
9298          * If virtualize x2apic mode is enabled,
9299          * virtualize apic access must be disabled.
9300          */
9301         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9302             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9303                 return -EINVAL;
9304
9305         /*
9306          * If virtual interrupt delivery is enabled,
9307          * we must exit on external interrupts.
9308          */
9309         if (nested_cpu_has_vid(vmcs12) &&
9310            !nested_exit_on_intr(vcpu))
9311                 return -EINVAL;
9312
9313         /*
9314          * bits 15:8 should be zero in posted_intr_nv,
9315          * the descriptor address has been already checked
9316          * in nested_get_vmcs12_pages.
9317          */
9318         if (nested_cpu_has_posted_intr(vmcs12) &&
9319            (!nested_cpu_has_vid(vmcs12) ||
9320             !nested_exit_intr_ack_set(vcpu) ||
9321             vmcs12->posted_intr_nv & 0xff00))
9322                 return -EINVAL;
9323
9324         /* tpr shadow is needed by all apicv features. */
9325         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9326                 return -EINVAL;
9327
9328         return 0;
9329 }
9330
9331 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9332                                        unsigned long count_field,
9333                                        unsigned long addr_field)
9334 {
9335         int maxphyaddr;
9336         u64 count, addr;
9337
9338         if (vmcs12_read_any(vcpu, count_field, &count) ||
9339             vmcs12_read_any(vcpu, addr_field, &addr)) {
9340                 WARN_ON(1);
9341                 return -EINVAL;
9342         }
9343         if (count == 0)
9344                 return 0;
9345         maxphyaddr = cpuid_maxphyaddr(vcpu);
9346         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9347             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9348                 pr_warn_ratelimited(
9349                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9350                         addr_field, maxphyaddr, count, addr);
9351                 return -EINVAL;
9352         }
9353         return 0;
9354 }
9355
9356 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9357                                                 struct vmcs12 *vmcs12)
9358 {
9359         if (vmcs12->vm_exit_msr_load_count == 0 &&
9360             vmcs12->vm_exit_msr_store_count == 0 &&
9361             vmcs12->vm_entry_msr_load_count == 0)
9362                 return 0; /* Fast path */
9363         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9364                                         VM_EXIT_MSR_LOAD_ADDR) ||
9365             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9366                                         VM_EXIT_MSR_STORE_ADDR) ||
9367             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9368                                         VM_ENTRY_MSR_LOAD_ADDR))
9369                 return -EINVAL;
9370         return 0;
9371 }
9372
9373 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9374                                        struct vmx_msr_entry *e)
9375 {
9376         /* x2APIC MSR accesses are not allowed */
9377         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9378                 return -EINVAL;
9379         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9380             e->index == MSR_IA32_UCODE_REV)
9381                 return -EINVAL;
9382         if (e->reserved != 0)
9383                 return -EINVAL;
9384         return 0;
9385 }
9386
9387 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9388                                      struct vmx_msr_entry *e)
9389 {
9390         if (e->index == MSR_FS_BASE ||
9391             e->index == MSR_GS_BASE ||
9392             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9393             nested_vmx_msr_check_common(vcpu, e))
9394                 return -EINVAL;
9395         return 0;
9396 }
9397
9398 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9399                                       struct vmx_msr_entry *e)
9400 {
9401         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9402             nested_vmx_msr_check_common(vcpu, e))
9403                 return -EINVAL;
9404         return 0;
9405 }
9406
9407 /*
9408  * Load guest's/host's msr at nested entry/exit.
9409  * return 0 for success, entry index for failure.
9410  */
9411 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9412 {
9413         u32 i;
9414         struct vmx_msr_entry e;
9415         struct msr_data msr;
9416
9417         msr.host_initiated = false;
9418         for (i = 0; i < count; i++) {
9419                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9420                                         &e, sizeof(e))) {
9421                         pr_warn_ratelimited(
9422                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9423                                 __func__, i, gpa + i * sizeof(e));
9424                         goto fail;
9425                 }
9426                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9427                         pr_warn_ratelimited(
9428                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9429                                 __func__, i, e.index, e.reserved);
9430                         goto fail;
9431                 }
9432                 msr.index = e.index;
9433                 msr.data = e.value;
9434                 if (kvm_set_msr(vcpu, &msr)) {
9435                         pr_warn_ratelimited(
9436                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9437                                 __func__, i, e.index, e.value);
9438                         goto fail;
9439                 }
9440         }
9441         return 0;
9442 fail:
9443         return i + 1;
9444 }
9445
9446 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9447 {
9448         u32 i;
9449         struct vmx_msr_entry e;
9450
9451         for (i = 0; i < count; i++) {
9452                 struct msr_data msr_info;
9453                 if (kvm_vcpu_read_guest(vcpu,
9454                                         gpa + i * sizeof(e),
9455                                         &e, 2 * sizeof(u32))) {
9456                         pr_warn_ratelimited(
9457                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9458                                 __func__, i, gpa + i * sizeof(e));
9459                         return -EINVAL;
9460                 }
9461                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9462                         pr_warn_ratelimited(
9463                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9464                                 __func__, i, e.index, e.reserved);
9465                         return -EINVAL;
9466                 }
9467                 msr_info.host_initiated = false;
9468                 msr_info.index = e.index;
9469                 if (kvm_get_msr(vcpu, &msr_info)) {
9470                         pr_warn_ratelimited(
9471                                 "%s cannot read MSR (%u, 0x%x)\n",
9472                                 __func__, i, e.index);
9473                         return -EINVAL;
9474                 }
9475                 if (kvm_vcpu_write_guest(vcpu,
9476                                          gpa + i * sizeof(e) +
9477                                              offsetof(struct vmx_msr_entry, value),
9478                                          &msr_info.data, sizeof(msr_info.data))) {
9479                         pr_warn_ratelimited(
9480                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9481                                 __func__, i, e.index, msr_info.data);
9482                         return -EINVAL;
9483                 }
9484         }
9485         return 0;
9486 }
9487
9488 /*
9489  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9490  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9491  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9492  * guest in a way that will both be appropriate to L1's requests, and our
9493  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9494  * function also has additional necessary side-effects, like setting various
9495  * vcpu->arch fields.
9496  */
9497 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9498 {
9499         struct vcpu_vmx *vmx = to_vmx(vcpu);
9500         u32 exec_control;
9501
9502         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9503         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9504         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9505         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9506         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9507         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9508         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9509         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9510         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9511         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9512         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9513         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9514         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9515         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9516         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9517         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9518         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9519         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9520         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9521         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9522         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9523         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9524         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9525         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9526         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9527         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9528         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9529         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9530         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9531         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9532         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9533         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9534         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9535         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9536         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9537         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9538
9539         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9540                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9541                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9542         } else {
9543                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9544                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9545         }
9546         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9547                 vmcs12->vm_entry_intr_info_field);
9548         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9549                 vmcs12->vm_entry_exception_error_code);
9550         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9551                 vmcs12->vm_entry_instruction_len);
9552         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9553                 vmcs12->guest_interruptibility_info);
9554         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9555         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9556         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9557                 vmcs12->guest_pending_dbg_exceptions);
9558         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9559         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9560
9561         if (nested_cpu_has_xsaves(vmcs12))
9562                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9563         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9564
9565         exec_control = vmcs12->pin_based_vm_exec_control;
9566         exec_control |= vmcs_config.pin_based_exec_ctrl;
9567         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9568
9569         if (nested_cpu_has_posted_intr(vmcs12)) {
9570                 /*
9571                  * Note that we use L0's vector here and in
9572                  * vmx_deliver_nested_posted_interrupt.
9573                  */
9574                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9575                 vmx->nested.pi_pending = false;
9576                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9577                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9578                         page_to_phys(vmx->nested.pi_desc_page) +
9579                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9580                         (PAGE_SIZE - 1)));
9581         } else
9582                 exec_control &= ~PIN_BASED_POSTED_INTR;
9583
9584         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9585
9586         vmx->nested.preemption_timer_expired = false;
9587         if (nested_cpu_has_preemption_timer(vmcs12))
9588                 vmx_start_preemption_timer(vcpu);
9589
9590         /*
9591          * Whether page-faults are trapped is determined by a combination of
9592          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9593          * If enable_ept, L0 doesn't care about page faults and we should
9594          * set all of these to L1's desires. However, if !enable_ept, L0 does
9595          * care about (at least some) page faults, and because it is not easy
9596          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9597          * to exit on each and every L2 page fault. This is done by setting
9598          * MASK=MATCH=0 and (see below) EB.PF=1.
9599          * Note that below we don't need special code to set EB.PF beyond the
9600          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9601          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9602          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9603          *
9604          * A problem with this approach (when !enable_ept) is that L1 may be
9605          * injected with more page faults than it asked for. This could have
9606          * caused problems, but in practice existing hypervisors don't care.
9607          * To fix this, we will need to emulate the PFEC checking (on the L1
9608          * page tables), using walk_addr(), when injecting PFs to L1.
9609          */
9610         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9611                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9612         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9613                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9614
9615         if (cpu_has_secondary_exec_ctrls()) {
9616                 exec_control = vmx_secondary_exec_control(vmx);
9617
9618                 /* Take the following fields only from vmcs12 */
9619                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9620                                   SECONDARY_EXEC_RDTSCP |
9621                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9622                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9623                                   SECONDARY_EXEC_PCOMMIT);
9624                 if (nested_cpu_has(vmcs12,
9625                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9626                         exec_control |= vmcs12->secondary_vm_exec_control;
9627
9628                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9629                         /*
9630                          * If translation failed, no matter: This feature asks
9631                          * to exit when accessing the given address, and if it
9632                          * can never be accessed, this feature won't do
9633                          * anything anyway.
9634                          */
9635                         if (!vmx->nested.apic_access_page)
9636                                 exec_control &=
9637                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9638                         else
9639                                 vmcs_write64(APIC_ACCESS_ADDR,
9640                                   page_to_phys(vmx->nested.apic_access_page));
9641                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9642                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9643                         exec_control |=
9644                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9645                         kvm_vcpu_reload_apic_access_page(vcpu);
9646                 }
9647
9648                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9649                         vmcs_write64(EOI_EXIT_BITMAP0,
9650                                 vmcs12->eoi_exit_bitmap0);
9651                         vmcs_write64(EOI_EXIT_BITMAP1,
9652                                 vmcs12->eoi_exit_bitmap1);
9653                         vmcs_write64(EOI_EXIT_BITMAP2,
9654                                 vmcs12->eoi_exit_bitmap2);
9655                         vmcs_write64(EOI_EXIT_BITMAP3,
9656                                 vmcs12->eoi_exit_bitmap3);
9657                         vmcs_write16(GUEST_INTR_STATUS,
9658                                 vmcs12->guest_intr_status);
9659                 }
9660
9661                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9662         }
9663
9664
9665         /*
9666          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9667          * Some constant fields are set here by vmx_set_constant_host_state().
9668          * Other fields are different per CPU, and will be set later when
9669          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9670          */
9671         vmx_set_constant_host_state(vmx);
9672
9673         /*
9674          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9675          * entry, but only if the current (host) sp changed from the value
9676          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9677          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9678          * here we just force the write to happen on entry.
9679          */
9680         vmx->host_rsp = 0;
9681
9682         exec_control = vmx_exec_control(vmx); /* L0's desires */
9683         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9684         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9685         exec_control &= ~CPU_BASED_TPR_SHADOW;
9686         exec_control |= vmcs12->cpu_based_vm_exec_control;
9687
9688         if (exec_control & CPU_BASED_TPR_SHADOW) {
9689                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9690                                 page_to_phys(vmx->nested.virtual_apic_page));
9691                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9692         } else {
9693 #ifdef CONFIG_X86_64
9694                 exec_control |= CPU_BASED_CR8_LOAD_EXITING |
9695                                 CPU_BASED_CR8_STORE_EXITING;
9696 #endif
9697         }
9698
9699         if (cpu_has_vmx_msr_bitmap() &&
9700             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9701                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9702                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9703         } else
9704                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9705
9706         /*
9707          * Merging of IO bitmap not currently supported.
9708          * Rather, exit every time.
9709          */
9710         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9711         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9712
9713         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9714
9715         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9716          * bitwise-or of what L1 wants to trap for L2, and what we want to
9717          * trap. Note that CR0.TS also needs updating - we do this later.
9718          */
9719         update_exception_bitmap(vcpu);
9720         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9721         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9722
9723         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9724          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9725          * bits are further modified by vmx_set_efer() below.
9726          */
9727         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9728
9729         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9730          * emulated by vmx_set_efer(), below.
9731          */
9732         vm_entry_controls_init(vmx,
9733                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9734                         ~VM_ENTRY_IA32E_MODE) |
9735                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9736
9737         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9738                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9739                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9740         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9741                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9742
9743
9744         set_cr4_guest_host_mask(vmx);
9745
9746         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9747                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9748
9749         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9750                 vmcs_write64(TSC_OFFSET,
9751                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9752         else
9753                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9754
9755         if (enable_vpid) {
9756                 /*
9757                  * There is no direct mapping between vpid02 and vpid12, the
9758                  * vpid02 is per-vCPU for L0 and reused while the value of
9759                  * vpid12 is changed w/ one invvpid during nested vmentry.
9760                  * The vpid12 is allocated by L1 for L2, so it will not
9761                  * influence global bitmap(for vpid01 and vpid02 allocation)
9762                  * even if spawn a lot of nested vCPUs.
9763                  */
9764                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9765                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9766                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9767                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9768                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9769                         }
9770                 } else {
9771                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9772                         vmx_flush_tlb(vcpu);
9773                 }
9774
9775         }
9776
9777         if (enable_pml) {
9778                 /*
9779                  * Conceptually we want to copy the PML address and index from
9780                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
9781                  * since we always flush the log on each vmexit, this happens
9782                  * to be equivalent to simply resetting the fields in vmcs02.
9783                  */
9784                 ASSERT(vmx->pml_pg);
9785                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
9786                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
9787         }
9788
9789         if (nested_cpu_has_ept(vmcs12)) {
9790                 kvm_mmu_unload(vcpu);
9791                 nested_ept_init_mmu_context(vcpu);
9792         }
9793
9794         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9795                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9796         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9797                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9798         else
9799                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9800         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9801         vmx_set_efer(vcpu, vcpu->arch.efer);
9802
9803         /*
9804          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9805          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9806          * The CR0_READ_SHADOW is what L2 should have expected to read given
9807          * the specifications by L1; It's not enough to take
9808          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9809          * have more bits than L1 expected.
9810          */
9811         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9812         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9813
9814         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9815         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9816
9817         /* shadow page tables on either EPT or shadow page tables */
9818         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9819         kvm_mmu_reset_context(vcpu);
9820
9821         if (!enable_ept)
9822                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9823
9824         /*
9825          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9826          */
9827         if (enable_ept) {
9828                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9829                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9830                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9831                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9832         }
9833
9834         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9835         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9836 }
9837
9838 /*
9839  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9840  * for running an L2 nested guest.
9841  */
9842 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9843 {
9844         struct vmcs12 *vmcs12;
9845         struct vcpu_vmx *vmx = to_vmx(vcpu);
9846         int cpu;
9847         struct loaded_vmcs *vmcs02;
9848         bool ia32e;
9849         u32 msr_entry_idx;
9850
9851         if (!nested_vmx_check_permission(vcpu) ||
9852             !nested_vmx_check_vmcs12(vcpu))
9853                 return 1;
9854
9855         skip_emulated_instruction(vcpu);
9856         vmcs12 = get_vmcs12(vcpu);
9857
9858         if (enable_shadow_vmcs)
9859                 copy_shadow_to_vmcs12(vmx);
9860
9861         /*
9862          * The nested entry process starts with enforcing various prerequisites
9863          * on vmcs12 as required by the Intel SDM, and act appropriately when
9864          * they fail: As the SDM explains, some conditions should cause the
9865          * instruction to fail, while others will cause the instruction to seem
9866          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9867          * To speed up the normal (success) code path, we should avoid checking
9868          * for misconfigurations which will anyway be caught by the processor
9869          * when using the merged vmcs02.
9870          */
9871         if (vmcs12->launch_state == launch) {
9872                 nested_vmx_failValid(vcpu,
9873                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9874                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9875                 return 1;
9876         }
9877
9878         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9879             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9880                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9881                 return 1;
9882         }
9883
9884         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9885                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9886                 return 1;
9887         }
9888
9889         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9890                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9891                 return 1;
9892         }
9893
9894         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9895                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9896                 return 1;
9897         }
9898
9899         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9900                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9901                 return 1;
9902         }
9903
9904         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9905                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9906                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9907             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9908                                 vmx->nested.nested_vmx_secondary_ctls_low,
9909                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9910             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9911                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9912                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9913             !vmx_control_verify(vmcs12->vm_exit_controls,
9914                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9915                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9916             !vmx_control_verify(vmcs12->vm_entry_controls,
9917                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9918                                 vmx->nested.nested_vmx_entry_ctls_high))
9919         {
9920                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9921                 return 1;
9922         }
9923
9924         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9925             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9926                 nested_vmx_failValid(vcpu,
9927                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9928                 return 1;
9929         }
9930
9931         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9932             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9933                 nested_vmx_entry_failure(vcpu, vmcs12,
9934                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9935                 return 1;
9936         }
9937         if (vmcs12->vmcs_link_pointer != -1ull) {
9938                 nested_vmx_entry_failure(vcpu, vmcs12,
9939                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9940                 return 1;
9941         }
9942
9943         /*
9944          * If the load IA32_EFER VM-entry control is 1, the following checks
9945          * are performed on the field for the IA32_EFER MSR:
9946          * - Bits reserved in the IA32_EFER MSR must be 0.
9947          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9948          *   the IA-32e mode guest VM-exit control. It must also be identical
9949          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9950          *   CR0.PG) is 1.
9951          */
9952         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9953                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9954                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9955                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9956                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9957                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9958                         nested_vmx_entry_failure(vcpu, vmcs12,
9959                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9960                         return 1;
9961                 }
9962         }
9963
9964         /*
9965          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9966          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9967          * the values of the LMA and LME bits in the field must each be that of
9968          * the host address-space size VM-exit control.
9969          */
9970         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9971                 ia32e = (vmcs12->vm_exit_controls &
9972                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9973                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9974                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9975                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9976                         nested_vmx_entry_failure(vcpu, vmcs12,
9977                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9978                         return 1;
9979                 }
9980         }
9981
9982         /*
9983          * We're finally done with prerequisite checking, and can start with
9984          * the nested entry.
9985          */
9986
9987         vmcs02 = nested_get_current_vmcs02(vmx);
9988         if (!vmcs02)
9989                 return -ENOMEM;
9990
9991         enter_guest_mode(vcpu);
9992
9993         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9994
9995         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9996                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9997
9998         cpu = get_cpu();
9999         vmx->loaded_vmcs = vmcs02;
10000         vmx_vcpu_put(vcpu);
10001         vmx_vcpu_load(vcpu, cpu);
10002         vcpu->cpu = cpu;
10003         put_cpu();
10004
10005         vmx_segment_cache_clear(vmx);
10006
10007         prepare_vmcs02(vcpu, vmcs12);
10008
10009         msr_entry_idx = nested_vmx_load_msr(vcpu,
10010                                             vmcs12->vm_entry_msr_load_addr,
10011                                             vmcs12->vm_entry_msr_load_count);
10012         if (msr_entry_idx) {
10013                 leave_guest_mode(vcpu);
10014                 vmx_load_vmcs01(vcpu);
10015                 nested_vmx_entry_failure(vcpu, vmcs12,
10016                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10017                 return 1;
10018         }
10019
10020         vmcs12->launch_state = 1;
10021
10022         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10023                 return kvm_vcpu_halt(vcpu);
10024
10025         vmx->nested.nested_run_pending = 1;
10026
10027         /*
10028          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10029          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10030          * returned as far as L1 is concerned. It will only return (and set
10031          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10032          */
10033         return 1;
10034 }
10035
10036 /*
10037  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10038  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10039  * This function returns the new value we should put in vmcs12.guest_cr0.
10040  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10041  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10042  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10043  *     didn't trap the bit, because if L1 did, so would L0).
10044  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10045  *     been modified by L2, and L1 knows it. So just leave the old value of
10046  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10047  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10048  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10049  *     changed these bits, and therefore they need to be updated, but L0
10050  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10051  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10052  */
10053 static inline unsigned long
10054 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10055 {
10056         return
10057         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10058         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10059         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10060                         vcpu->arch.cr0_guest_owned_bits));
10061 }
10062
10063 static inline unsigned long
10064 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10065 {
10066         return
10067         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10068         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10069         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10070                         vcpu->arch.cr4_guest_owned_bits));
10071 }
10072
10073 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10074                                        struct vmcs12 *vmcs12)
10075 {
10076         u32 idt_vectoring;
10077         unsigned int nr;
10078
10079         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10080                 nr = vcpu->arch.exception.nr;
10081                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10082
10083                 if (kvm_exception_is_soft(nr)) {
10084                         vmcs12->vm_exit_instruction_len =
10085                                 vcpu->arch.event_exit_inst_len;
10086                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10087                 } else
10088                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10089
10090                 if (vcpu->arch.exception.has_error_code) {
10091                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10092                         vmcs12->idt_vectoring_error_code =
10093                                 vcpu->arch.exception.error_code;
10094                 }
10095
10096                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10097         } else if (vcpu->arch.nmi_injected) {
10098                 vmcs12->idt_vectoring_info_field =
10099                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10100         } else if (vcpu->arch.interrupt.pending) {
10101                 nr = vcpu->arch.interrupt.nr;
10102                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10103
10104                 if (vcpu->arch.interrupt.soft) {
10105                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10106                         vmcs12->vm_entry_instruction_len =
10107                                 vcpu->arch.event_exit_inst_len;
10108                 } else
10109                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10110
10111                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10112         }
10113 }
10114
10115 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10116 {
10117         struct vcpu_vmx *vmx = to_vmx(vcpu);
10118
10119         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10120             vmx->nested.preemption_timer_expired) {
10121                 if (vmx->nested.nested_run_pending)
10122                         return -EBUSY;
10123                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10124                 return 0;
10125         }
10126
10127         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10128                 if (vmx->nested.nested_run_pending ||
10129                     vcpu->arch.interrupt.pending)
10130                         return -EBUSY;
10131                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10132                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10133                                   INTR_INFO_VALID_MASK, 0);
10134                 /*
10135                  * The NMI-triggered VM exit counts as injection:
10136                  * clear this one and block further NMIs.
10137                  */
10138                 vcpu->arch.nmi_pending = 0;
10139                 vmx_set_nmi_mask(vcpu, true);
10140                 return 0;
10141         }
10142
10143         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10144             nested_exit_on_intr(vcpu)) {
10145                 if (vmx->nested.nested_run_pending)
10146                         return -EBUSY;
10147                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10148                 return 0;
10149         }
10150
10151         return vmx_complete_nested_posted_interrupt(vcpu);
10152 }
10153
10154 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10155 {
10156         ktime_t remaining =
10157                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10158         u64 value;
10159
10160         if (ktime_to_ns(remaining) <= 0)
10161                 return 0;
10162
10163         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10164         do_div(value, 1000000);
10165         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10166 }
10167
10168 /*
10169  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10170  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10171  * and this function updates it to reflect the changes to the guest state while
10172  * L2 was running (and perhaps made some exits which were handled directly by L0
10173  * without going back to L1), and to reflect the exit reason.
10174  * Note that we do not have to copy here all VMCS fields, just those that
10175  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10176  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10177  * which already writes to vmcs12 directly.
10178  */
10179 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10180                            u32 exit_reason, u32 exit_intr_info,
10181                            unsigned long exit_qualification)
10182 {
10183         /* update guest state fields: */
10184         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10185         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10186
10187         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10188         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10189         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10190
10191         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10192         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10193         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10194         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10195         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10196         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10197         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10198         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10199         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10200         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10201         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10202         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10203         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10204         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10205         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10206         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10207         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10208         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10209         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10210         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10211         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10212         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10213         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10214         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10215         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10216         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10217         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10218         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10219         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10220         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10221         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10222         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10223         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10224         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10225         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10226         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10227
10228         vmcs12->guest_interruptibility_info =
10229                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10230         vmcs12->guest_pending_dbg_exceptions =
10231                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10232         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10233                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10234         else
10235                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10236
10237         if (nested_cpu_has_preemption_timer(vmcs12)) {
10238                 if (vmcs12->vm_exit_controls &
10239                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10240                         vmcs12->vmx_preemption_timer_value =
10241                                 vmx_get_preemption_timer_value(vcpu);
10242                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10243         }
10244
10245         /*
10246          * In some cases (usually, nested EPT), L2 is allowed to change its
10247          * own CR3 without exiting. If it has changed it, we must keep it.
10248          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10249          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10250          *
10251          * Additionally, restore L2's PDPTR to vmcs12.
10252          */
10253         if (enable_ept) {
10254                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10255                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10256                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10257                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10258                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10259         }
10260
10261         if (nested_cpu_has_vid(vmcs12))
10262                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10263
10264         vmcs12->vm_entry_controls =
10265                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10266                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10267
10268         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10269                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10270                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10271         }
10272
10273         /* TODO: These cannot have changed unless we have MSR bitmaps and
10274          * the relevant bit asks not to trap the change */
10275         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10276                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10277         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10278                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10279         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10280         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10281         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10282         if (kvm_mpx_supported())
10283                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10284         if (nested_cpu_has_xsaves(vmcs12))
10285                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10286
10287         /* update exit information fields: */
10288
10289         vmcs12->vm_exit_reason = exit_reason;
10290         vmcs12->exit_qualification = exit_qualification;
10291
10292         vmcs12->vm_exit_intr_info = exit_intr_info;
10293         if ((vmcs12->vm_exit_intr_info &
10294              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10295             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10296                 vmcs12->vm_exit_intr_error_code =
10297                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10298         vmcs12->idt_vectoring_info_field = 0;
10299         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10300         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10301
10302         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10303                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10304                  * instead of reading the real value. */
10305                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10306
10307                 /*
10308                  * Transfer the event that L0 or L1 may wanted to inject into
10309                  * L2 to IDT_VECTORING_INFO_FIELD.
10310                  */
10311                 vmcs12_save_pending_event(vcpu, vmcs12);
10312         }
10313
10314         /*
10315          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10316          * preserved above and would only end up incorrectly in L1.
10317          */
10318         vcpu->arch.nmi_injected = false;
10319         kvm_clear_exception_queue(vcpu);
10320         kvm_clear_interrupt_queue(vcpu);
10321 }
10322
10323 /*
10324  * A part of what we need to when the nested L2 guest exits and we want to
10325  * run its L1 parent, is to reset L1's guest state to the host state specified
10326  * in vmcs12.
10327  * This function is to be called not only on normal nested exit, but also on
10328  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10329  * Failures During or After Loading Guest State").
10330  * This function should be called when the active VMCS is L1's (vmcs01).
10331  */
10332 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10333                                    struct vmcs12 *vmcs12)
10334 {
10335         struct kvm_segment seg;
10336
10337         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10338                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10339         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10340                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10341         else
10342                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10343         vmx_set_efer(vcpu, vcpu->arch.efer);
10344
10345         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10346         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10347         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10348         /*
10349          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10350          * actually changed, because it depends on the current state of
10351          * fpu_active (which may have changed).
10352          * Note that vmx_set_cr0 refers to efer set above.
10353          */
10354         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10355         /*
10356          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10357          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10358          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10359          */
10360         update_exception_bitmap(vcpu);
10361         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10362         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10363
10364         /*
10365          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10366          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10367          */
10368         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10369         vmx_set_cr4(vcpu, vmcs12->host_cr4);
10370
10371         nested_ept_uninit_mmu_context(vcpu);
10372
10373         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10374         kvm_mmu_reset_context(vcpu);
10375
10376         if (!enable_ept)
10377                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10378
10379         if (enable_vpid) {
10380                 /*
10381                  * Trivially support vpid by letting L2s share their parent
10382                  * L1's vpid. TODO: move to a more elaborate solution, giving
10383                  * each L2 its own vpid and exposing the vpid feature to L1.
10384                  */
10385                 vmx_flush_tlb(vcpu);
10386         }
10387
10388
10389         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10390         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10391         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10392         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10393         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10394         vmcs_write32(GUEST_IDTR_LIMIT, 0xFFFF);
10395         vmcs_write32(GUEST_GDTR_LIMIT, 0xFFFF);
10396
10397         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10398         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10399                 vmcs_write64(GUEST_BNDCFGS, 0);
10400
10401         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10402                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10403                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10404         }
10405         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10406                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10407                         vmcs12->host_ia32_perf_global_ctrl);
10408
10409         /* Set L1 segment info according to Intel SDM
10410             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10411         seg = (struct kvm_segment) {
10412                 .base = 0,
10413                 .limit = 0xFFFFFFFF,
10414                 .selector = vmcs12->host_cs_selector,
10415                 .type = 11,
10416                 .present = 1,
10417                 .s = 1,
10418                 .g = 1
10419         };
10420         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10421                 seg.l = 1;
10422         else
10423                 seg.db = 1;
10424         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10425         seg = (struct kvm_segment) {
10426                 .base = 0,
10427                 .limit = 0xFFFFFFFF,
10428                 .type = 3,
10429                 .present = 1,
10430                 .s = 1,
10431                 .db = 1,
10432                 .g = 1
10433         };
10434         seg.selector = vmcs12->host_ds_selector;
10435         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10436         seg.selector = vmcs12->host_es_selector;
10437         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10438         seg.selector = vmcs12->host_ss_selector;
10439         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10440         seg.selector = vmcs12->host_fs_selector;
10441         seg.base = vmcs12->host_fs_base;
10442         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10443         seg.selector = vmcs12->host_gs_selector;
10444         seg.base = vmcs12->host_gs_base;
10445         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10446         seg = (struct kvm_segment) {
10447                 .base = vmcs12->host_tr_base,
10448                 .limit = 0x67,
10449                 .selector = vmcs12->host_tr_selector,
10450                 .type = 11,
10451                 .present = 1
10452         };
10453         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10454
10455         kvm_set_dr(vcpu, 7, 0x400);
10456         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10457
10458         if (cpu_has_vmx_msr_bitmap())
10459                 vmx_set_msr_bitmap(vcpu);
10460
10461         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10462                                 vmcs12->vm_exit_msr_load_count))
10463                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10464 }
10465
10466 /*
10467  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10468  * and modify vmcs12 to make it see what it would expect to see there if
10469  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10470  */
10471 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10472                               u32 exit_intr_info,
10473                               unsigned long exit_qualification)
10474 {
10475         struct vcpu_vmx *vmx = to_vmx(vcpu);
10476         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10477
10478         /* trying to cancel vmlaunch/vmresume is a bug */
10479         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10480
10481         leave_guest_mode(vcpu);
10482         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10483                        exit_qualification);
10484
10485         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10486                                  vmcs12->vm_exit_msr_store_count))
10487                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10488
10489         vmx_load_vmcs01(vcpu);
10490
10491         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10492             && nested_exit_intr_ack_set(vcpu)) {
10493                 int irq = kvm_cpu_get_interrupt(vcpu);
10494                 WARN_ON(irq < 0);
10495                 vmcs12->vm_exit_intr_info = irq |
10496                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10497         }
10498
10499         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10500                                        vmcs12->exit_qualification,
10501                                        vmcs12->idt_vectoring_info_field,
10502                                        vmcs12->vm_exit_intr_info,
10503                                        vmcs12->vm_exit_intr_error_code,
10504                                        KVM_ISA_VMX);
10505
10506         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10507         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10508         vmx_segment_cache_clear(vmx);
10509
10510         /* if no vmcs02 cache requested, remove the one we used */
10511         if (VMCS02_POOL_SIZE == 0)
10512                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10513
10514         load_vmcs12_host_state(vcpu, vmcs12);
10515
10516         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10517         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10518
10519         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10520                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10521                 vmx_set_virtual_x2apic_mode(vcpu,
10522                                 vcpu->arch.apic_base & X2APIC_ENABLE);
10523         }
10524
10525         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10526         vmx->host_rsp = 0;
10527
10528         /* Unpin physical memory we referred to in vmcs02 */
10529         if (vmx->nested.apic_access_page) {
10530                 nested_release_page(vmx->nested.apic_access_page);
10531                 vmx->nested.apic_access_page = NULL;
10532         }
10533         if (vmx->nested.virtual_apic_page) {
10534                 nested_release_page(vmx->nested.virtual_apic_page);
10535                 vmx->nested.virtual_apic_page = NULL;
10536         }
10537         if (vmx->nested.pi_desc_page) {
10538                 kunmap(vmx->nested.pi_desc_page);
10539                 nested_release_page(vmx->nested.pi_desc_page);
10540                 vmx->nested.pi_desc_page = NULL;
10541                 vmx->nested.pi_desc = NULL;
10542         }
10543
10544         /*
10545          * We are now running in L2, mmu_notifier will force to reload the
10546          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10547          */
10548         kvm_vcpu_reload_apic_access_page(vcpu);
10549
10550         /*
10551          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10552          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10553          * success or failure flag accordingly.
10554          */
10555         if (unlikely(vmx->fail)) {
10556                 vmx->fail = 0;
10557                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10558         } else
10559                 nested_vmx_succeed(vcpu);
10560         if (enable_shadow_vmcs)
10561                 vmx->nested.sync_shadow_vmcs = true;
10562
10563         /* in case we halted in L2 */
10564         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10565 }
10566
10567 /*
10568  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10569  */
10570 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10571 {
10572         if (is_guest_mode(vcpu))
10573                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10574         free_nested(to_vmx(vcpu));
10575 }
10576
10577 /*
10578  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10579  * 23.7 "VM-entry failures during or after loading guest state" (this also
10580  * lists the acceptable exit-reason and exit-qualification parameters).
10581  * It should only be called before L2 actually succeeded to run, and when
10582  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10583  */
10584 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10585                         struct vmcs12 *vmcs12,
10586                         u32 reason, unsigned long qualification)
10587 {
10588         load_vmcs12_host_state(vcpu, vmcs12);
10589         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10590         vmcs12->exit_qualification = qualification;
10591         nested_vmx_succeed(vcpu);
10592         if (enable_shadow_vmcs)
10593                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10594 }
10595
10596 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10597                                struct x86_instruction_info *info,
10598                                enum x86_intercept_stage stage)
10599 {
10600         return X86EMUL_CONTINUE;
10601 }
10602
10603 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10604 {
10605         if (ple_gap)
10606                 shrink_ple_window(vcpu);
10607 }
10608
10609 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10610                                      struct kvm_memory_slot *slot)
10611 {
10612         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10613         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10614 }
10615
10616 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10617                                        struct kvm_memory_slot *slot)
10618 {
10619         kvm_mmu_slot_set_dirty(kvm, slot);
10620 }
10621
10622 static void vmx_flush_log_dirty(struct kvm *kvm)
10623 {
10624         kvm_flush_pml_buffers(kvm);
10625 }
10626
10627 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10628                                            struct kvm_memory_slot *memslot,
10629                                            gfn_t offset, unsigned long mask)
10630 {
10631         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10632 }
10633
10634 /*
10635  * This routine does the following things for vCPU which is going
10636  * to be blocked if VT-d PI is enabled.
10637  * - Store the vCPU to the wakeup list, so when interrupts happen
10638  *   we can find the right vCPU to wake up.
10639  * - Change the Posted-interrupt descriptor as below:
10640  *      'NDST' <-- vcpu->pre_pcpu
10641  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10642  * - If 'ON' is set during this process, which means at least one
10643  *   interrupt is posted for this vCPU, we cannot block it, in
10644  *   this case, return 1, otherwise, return 0.
10645  *
10646  */
10647 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10648 {
10649         unsigned long flags;
10650         unsigned int dest;
10651         struct pi_desc old, new;
10652         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10653
10654         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10655                 !irq_remapping_cap(IRQ_POSTING_CAP))
10656                 return 0;
10657
10658         vcpu->pre_pcpu = vcpu->cpu;
10659         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10660                           vcpu->pre_pcpu), flags);
10661         list_add_tail(&vcpu->blocked_vcpu_list,
10662                       &per_cpu(blocked_vcpu_on_cpu,
10663                       vcpu->pre_pcpu));
10664         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10665                                vcpu->pre_pcpu), flags);
10666
10667         do {
10668                 old.control = new.control = pi_desc->control;
10669
10670                 /*
10671                  * We should not block the vCPU if
10672                  * an interrupt is posted for it.
10673                  */
10674                 if (pi_test_on(pi_desc) == 1) {
10675                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10676                                           vcpu->pre_pcpu), flags);
10677                         list_del(&vcpu->blocked_vcpu_list);
10678                         spin_unlock_irqrestore(
10679                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10680                                         vcpu->pre_pcpu), flags);
10681                         vcpu->pre_pcpu = -1;
10682
10683                         return 1;
10684                 }
10685
10686                 WARN((pi_desc->sn == 1),
10687                      "Warning: SN field of posted-interrupts "
10688                      "is set before blocking\n");
10689
10690                 /*
10691                  * Since vCPU can be preempted during this process,
10692                  * vcpu->cpu could be different with pre_pcpu, we
10693                  * need to set pre_pcpu as the destination of wakeup
10694                  * notification event, then we can find the right vCPU
10695                  * to wakeup in wakeup handler if interrupts happen
10696                  * when the vCPU is in blocked state.
10697                  */
10698                 dest = cpu_physical_id(vcpu->pre_pcpu);
10699
10700                 if (x2apic_enabled())
10701                         new.ndst = dest;
10702                 else
10703                         new.ndst = (dest << 8) & 0xFF00;
10704
10705                 /* set 'NV' to 'wakeup vector' */
10706                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10707         } while (cmpxchg64(&pi_desc->control, old.control,
10708                            new.control) != old.control);
10709
10710         return 0;
10711 }
10712
10713 static void vmx_post_block(struct kvm_vcpu *vcpu)
10714 {
10715         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10716         struct pi_desc old, new;
10717         unsigned int dest;
10718         unsigned long flags;
10719
10720         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10721                 !irq_remapping_cap(IRQ_POSTING_CAP))
10722                 return;
10723
10724         do {
10725                 old.control = new.control = pi_desc->control;
10726
10727                 dest = cpu_physical_id(vcpu->cpu);
10728
10729                 if (x2apic_enabled())
10730                         new.ndst = dest;
10731                 else
10732                         new.ndst = (dest << 8) & 0xFF00;
10733
10734                 /* Allow posting non-urgent interrupts */
10735                 new.sn = 0;
10736
10737                 /* set 'NV' to 'notification vector' */
10738                 new.nv = POSTED_INTR_VECTOR;
10739         } while (cmpxchg64(&pi_desc->control, old.control,
10740                            new.control) != old.control);
10741
10742         if(vcpu->pre_pcpu != -1) {
10743                 spin_lock_irqsave(
10744                         &per_cpu(blocked_vcpu_on_cpu_lock,
10745                         vcpu->pre_pcpu), flags);
10746                 list_del(&vcpu->blocked_vcpu_list);
10747                 spin_unlock_irqrestore(
10748                         &per_cpu(blocked_vcpu_on_cpu_lock,
10749                         vcpu->pre_pcpu), flags);
10750                 vcpu->pre_pcpu = -1;
10751         }
10752 }
10753
10754 /*
10755  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10756  *
10757  * @kvm: kvm
10758  * @host_irq: host irq of the interrupt
10759  * @guest_irq: gsi of the interrupt
10760  * @set: set or unset PI
10761  * returns 0 on success, < 0 on failure
10762  */
10763 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10764                               uint32_t guest_irq, bool set)
10765 {
10766         struct kvm_kernel_irq_routing_entry *e;
10767         struct kvm_irq_routing_table *irq_rt;
10768         struct kvm_lapic_irq irq;
10769         struct kvm_vcpu *vcpu;
10770         struct vcpu_data vcpu_info;
10771         int idx, ret = 0;
10772
10773         if (!kvm_arch_has_assigned_device(kvm) ||
10774                 !irq_remapping_cap(IRQ_POSTING_CAP))
10775                 return 0;
10776
10777         idx = srcu_read_lock(&kvm->irq_srcu);
10778         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10779         if (guest_irq >= irq_rt->nr_rt_entries ||
10780             hlist_empty(&irq_rt->map[guest_irq])) {
10781                 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
10782                              guest_irq, irq_rt->nr_rt_entries);
10783                 goto out;
10784         }
10785
10786         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10787                 if (e->type != KVM_IRQ_ROUTING_MSI)
10788                         continue;
10789                 /*
10790                  * VT-d PI cannot support posting multicast/broadcast
10791                  * interrupts to a vCPU, we still use interrupt remapping
10792                  * for these kind of interrupts.
10793                  *
10794                  * For lowest-priority interrupts, we only support
10795                  * those with single CPU as the destination, e.g. user
10796                  * configures the interrupts via /proc/irq or uses
10797                  * irqbalance to make the interrupts single-CPU.
10798                  *
10799                  * We will support full lowest-priority interrupt later.
10800                  */
10801
10802                 kvm_set_msi_irq(e, &irq);
10803                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10804                         continue;
10805
10806                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10807                 vcpu_info.vector = irq.vector;
10808
10809                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10810                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10811
10812                 if (set)
10813                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10814                 else
10815                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10816
10817                 if (ret < 0) {
10818                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10819                                         __func__);
10820                         goto out;
10821                 }
10822         }
10823
10824         ret = 0;
10825 out:
10826         srcu_read_unlock(&kvm->irq_srcu, idx);
10827         return ret;
10828 }
10829
10830 static struct kvm_x86_ops vmx_x86_ops = {
10831         .cpu_has_kvm_support = cpu_has_kvm_support,
10832         .disabled_by_bios = vmx_disabled_by_bios,
10833         .hardware_setup = hardware_setup,
10834         .hardware_unsetup = hardware_unsetup,
10835         .check_processor_compatibility = vmx_check_processor_compat,
10836         .hardware_enable = hardware_enable,
10837         .hardware_disable = hardware_disable,
10838         .cpu_has_accelerated_tpr = report_flexpriority,
10839         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10840
10841         .vcpu_create = vmx_create_vcpu,
10842         .vcpu_free = vmx_free_vcpu,
10843         .vcpu_reset = vmx_vcpu_reset,
10844
10845         .prepare_guest_switch = vmx_save_host_state,
10846         .vcpu_load = vmx_vcpu_load,
10847         .vcpu_put = vmx_vcpu_put,
10848
10849         .update_bp_intercept = update_exception_bitmap,
10850         .get_msr = vmx_get_msr,
10851         .set_msr = vmx_set_msr,
10852         .get_segment_base = vmx_get_segment_base,
10853         .get_segment = vmx_get_segment,
10854         .set_segment = vmx_set_segment,
10855         .get_cpl = vmx_get_cpl,
10856         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10857         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10858         .decache_cr3 = vmx_decache_cr3,
10859         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10860         .set_cr0 = vmx_set_cr0,
10861         .set_cr3 = vmx_set_cr3,
10862         .set_cr4 = vmx_set_cr4,
10863         .set_efer = vmx_set_efer,
10864         .get_idt = vmx_get_idt,
10865         .set_idt = vmx_set_idt,
10866         .get_gdt = vmx_get_gdt,
10867         .set_gdt = vmx_set_gdt,
10868         .get_dr6 = vmx_get_dr6,
10869         .set_dr6 = vmx_set_dr6,
10870         .set_dr7 = vmx_set_dr7,
10871         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10872         .cache_reg = vmx_cache_reg,
10873         .get_rflags = vmx_get_rflags,
10874         .set_rflags = vmx_set_rflags,
10875         .fpu_activate = vmx_fpu_activate,
10876         .fpu_deactivate = vmx_fpu_deactivate,
10877
10878         .tlb_flush = vmx_flush_tlb,
10879
10880         .run = vmx_vcpu_run,
10881         .handle_exit = vmx_handle_exit,
10882         .skip_emulated_instruction = skip_emulated_instruction,
10883         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10884         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10885         .patch_hypercall = vmx_patch_hypercall,
10886         .set_irq = vmx_inject_irq,
10887         .set_nmi = vmx_inject_nmi,
10888         .queue_exception = vmx_queue_exception,
10889         .cancel_injection = vmx_cancel_injection,
10890         .interrupt_allowed = vmx_interrupt_allowed,
10891         .nmi_allowed = vmx_nmi_allowed,
10892         .get_nmi_mask = vmx_get_nmi_mask,
10893         .set_nmi_mask = vmx_set_nmi_mask,
10894         .enable_nmi_window = enable_nmi_window,
10895         .enable_irq_window = enable_irq_window,
10896         .update_cr8_intercept = update_cr8_intercept,
10897         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10898         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10899         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10900         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10901         .hwapic_irr_update = vmx_hwapic_irr_update,
10902         .hwapic_isr_update = vmx_hwapic_isr_update,
10903         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10904         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10905
10906         .set_tss_addr = vmx_set_tss_addr,
10907         .get_tdp_level = get_ept_level,
10908         .get_mt_mask = vmx_get_mt_mask,
10909
10910         .get_exit_info = vmx_get_exit_info,
10911
10912         .get_lpage_level = vmx_get_lpage_level,
10913
10914         .cpuid_update = vmx_cpuid_update,
10915
10916         .rdtscp_supported = vmx_rdtscp_supported,
10917         .invpcid_supported = vmx_invpcid_supported,
10918
10919         .set_supported_cpuid = vmx_set_supported_cpuid,
10920
10921         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10922
10923         .read_tsc_offset = vmx_read_tsc_offset,
10924         .write_tsc_offset = vmx_write_tsc_offset,
10925         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10926         .read_l1_tsc = vmx_read_l1_tsc,
10927
10928         .set_tdp_cr3 = vmx_set_cr3,
10929
10930         .check_intercept = vmx_check_intercept,
10931         .handle_external_intr = vmx_handle_external_intr,
10932         .mpx_supported = vmx_mpx_supported,
10933         .xsaves_supported = vmx_xsaves_supported,
10934
10935         .check_nested_events = vmx_check_nested_events,
10936
10937         .sched_in = vmx_sched_in,
10938
10939         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10940         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10941         .flush_log_dirty = vmx_flush_log_dirty,
10942         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10943
10944         .pre_block = vmx_pre_block,
10945         .post_block = vmx_post_block,
10946
10947         .pmu_ops = &intel_pmu_ops,
10948
10949         .update_pi_irte = vmx_update_pi_irte,
10950 };
10951
10952 static int __init vmx_init(void)
10953 {
10954         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10955                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10956         if (r)
10957                 return r;
10958
10959 #ifdef CONFIG_KEXEC_CORE
10960         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10961                            crash_vmclear_local_loaded_vmcss);
10962 #endif
10963
10964         return 0;
10965 }
10966
10967 static void __exit vmx_exit(void)
10968 {
10969 #ifdef CONFIG_KEXEC_CORE
10970         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10971         synchronize_rcu();
10972 #endif
10973
10974         kvm_exit();
10975 }
10976
10977 module_init(vmx_init)
10978 module_exit(vmx_exit)