arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 114 #define KVM_VM_CR0_ALWAYS_ON                                            \
 115         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 116 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 117         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 118          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 119
 120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 122
 123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 124
 125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 126
 127 /*
 128  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 129  * ple_gap:    upper bound on the amount of time between two successive
 130  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 131  *             According to test, this time is usually smaller than 128 cycles.
 132  * ple_window: upper bound on the amount of time a guest is allowed to execute
 133  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 134  *             less than 2^12 cycles
 135  * Time is measured based on a counter that runs at the same rate as the TSC,
 136  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 137  */
 138 #define KVM_VMX_DEFAULT_PLE_GAP           128
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 143                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 144
 145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 146 module_param(ple_gap, int, S_IRUGO);
 147
 148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 149 module_param(ple_window, int, S_IRUGO);
 150
 151 /* Default doubles per-vcpu window every exit. */
 152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 153 module_param(ple_window_grow, int, S_IRUGO);
 154
 155 /* Default resets per-vcpu window every exit to ple_window. */
 156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 157 module_param(ple_window_shrink, int, S_IRUGO);
 158
 159 /* Default is to compute the maximum so we can never overflow. */
 160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 161 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 module_param(ple_window_max, int, S_IRUGO);
 163
 164 extern const ulong vmx_return;
 165
 166 #define NR_AUTOLOAD_MSRS 8
 167 #define VMCS02_POOL_SIZE 1
 168
 169 struct vmcs {
 170         u32 revision_id;
 171         u32 abort;
 172         char data[0];
 173 };
 174
 175 /*
 176  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 177  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 178  * loaded on this CPU (so we can clear them if the CPU goes down).
 179  */
 180 struct loaded_vmcs {
 181         struct vmcs *vmcs;
 182         int cpu;
 183         int launched;
 184         struct list_head loaded_vmcss_on_cpu_link;
 185 };
 186
 187 struct shared_msr_entry {
 188         unsigned index;
 189         u64 data;
 190         u64 mask;
 191 };
 192
 193 /*
 194  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 195  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 196  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 197  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 198  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 199  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 200  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 201  * underlying hardware which will be used to run L2.
 202  * This structure is packed to ensure that its layout is identical across
 203  * machines (necessary for live migration).
 204  * If there are changes in this struct, VMCS12_REVISION must be changed.
 205  */
 206 typedef u64 natural_width;
 207 struct __packed vmcs12 {
 208         /* According to the Intel spec, a VMCS region must start with the
 209          * following two fields. Then follow implementation-specific data.
 210          */
 211         u32 revision_id;
 212         u32 abort;
 213
 214         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 215         u32 padding[7]; /* room for future expansion */
 216
 217         u64 io_bitmap_a;
 218         u64 io_bitmap_b;
 219         u64 msr_bitmap;
 220         u64 vm_exit_msr_store_addr;
 221         u64 vm_exit_msr_load_addr;
 222         u64 vm_entry_msr_load_addr;
 223         u64 tsc_offset;
 224         u64 virtual_apic_page_addr;
 225         u64 apic_access_addr;
 226         u64 posted_intr_desc_addr;
 227         u64 ept_pointer;
 228         u64 eoi_exit_bitmap0;
 229         u64 eoi_exit_bitmap1;
 230         u64 eoi_exit_bitmap2;
 231         u64 eoi_exit_bitmap3;
 232         u64 xss_exit_bitmap;
 233         u64 guest_physical_address;
 234         u64 vmcs_link_pointer;
 235         u64 guest_ia32_debugctl;
 236         u64 guest_ia32_pat;
 237         u64 guest_ia32_efer;
 238         u64 guest_ia32_perf_global_ctrl;
 239         u64 guest_pdptr0;
 240         u64 guest_pdptr1;
 241         u64 guest_pdptr2;
 242         u64 guest_pdptr3;
 243         u64 guest_bndcfgs;
 244         u64 host_ia32_pat;
 245         u64 host_ia32_efer;
 246         u64 host_ia32_perf_global_ctrl;
 247         u64 padding64[8]; /* room for future expansion */
 248         /*
 249          * To allow migration of L1 (complete with its L2 guests) between
 250          * machines of different natural widths (32 or 64 bit), we cannot have
 251          * unsigned long fields with no explict size. We use u64 (aliased
 252          * natural_width) instead. Luckily, x86 is little-endian.
 253          */
 254         natural_width cr0_guest_host_mask;
 255         natural_width cr4_guest_host_mask;
 256         natural_width cr0_read_shadow;
 257         natural_width cr4_read_shadow;
 258         natural_width cr3_target_value0;
 259         natural_width cr3_target_value1;
 260         natural_width cr3_target_value2;
 261         natural_width cr3_target_value3;
 262         natural_width exit_qualification;
 263         natural_width guest_linear_address;
 264         natural_width guest_cr0;
 265         natural_width guest_cr3;
 266         natural_width guest_cr4;
 267         natural_width guest_es_base;
 268         natural_width guest_cs_base;
 269         natural_width guest_ss_base;
 270         natural_width guest_ds_base;
 271         natural_width guest_fs_base;
 272         natural_width guest_gs_base;
 273         natural_width guest_ldtr_base;
 274         natural_width guest_tr_base;
 275         natural_width guest_gdtr_base;
 276         natural_width guest_idtr_base;
 277         natural_width guest_dr7;
 278         natural_width guest_rsp;
 279         natural_width guest_rip;
 280         natural_width guest_rflags;
 281         natural_width guest_pending_dbg_exceptions;
 282         natural_width guest_sysenter_esp;
 283         natural_width guest_sysenter_eip;
 284         natural_width host_cr0;
 285         natural_width host_cr3;
 286         natural_width host_cr4;
 287         natural_width host_fs_base;
 288         natural_width host_gs_base;
 289         natural_width host_tr_base;
 290         natural_width host_gdtr_base;
 291         natural_width host_idtr_base;
 292         natural_width host_ia32_sysenter_esp;
 293         natural_width host_ia32_sysenter_eip;
 294         natural_width host_rsp;
 295         natural_width host_rip;
 296         natural_width paddingl[8]; /* room for future expansion */
 297         u32 pin_based_vm_exec_control;
 298         u32 cpu_based_vm_exec_control;
 299         u32 exception_bitmap;
 300         u32 page_fault_error_code_mask;
 301         u32 page_fault_error_code_match;
 302         u32 cr3_target_count;
 303         u32 vm_exit_controls;
 304         u32 vm_exit_msr_store_count;
 305         u32 vm_exit_msr_load_count;
 306         u32 vm_entry_controls;
 307         u32 vm_entry_msr_load_count;
 308         u32 vm_entry_intr_info_field;
 309         u32 vm_entry_exception_error_code;
 310         u32 vm_entry_instruction_len;
 311         u32 tpr_threshold;
 312         u32 secondary_vm_exec_control;
 313         u32 vm_instruction_error;
 314         u32 vm_exit_reason;
 315         u32 vm_exit_intr_info;
 316         u32 vm_exit_intr_error_code;
 317         u32 idt_vectoring_info_field;
 318         u32 idt_vectoring_error_code;
 319         u32 vm_exit_instruction_len;
 320         u32 vmx_instruction_info;
 321         u32 guest_es_limit;
 322         u32 guest_cs_limit;
 323         u32 guest_ss_limit;
 324         u32 guest_ds_limit;
 325         u32 guest_fs_limit;
 326         u32 guest_gs_limit;
 327         u32 guest_ldtr_limit;
 328         u32 guest_tr_limit;
 329         u32 guest_gdtr_limit;
 330         u32 guest_idtr_limit;
 331         u32 guest_es_ar_bytes;
 332         u32 guest_cs_ar_bytes;
 333         u32 guest_ss_ar_bytes;
 334         u32 guest_ds_ar_bytes;
 335         u32 guest_fs_ar_bytes;
 336         u32 guest_gs_ar_bytes;
 337         u32 guest_ldtr_ar_bytes;
 338         u32 guest_tr_ar_bytes;
 339         u32 guest_interruptibility_info;
 340         u32 guest_activity_state;
 341         u32 guest_sysenter_cs;
 342         u32 host_ia32_sysenter_cs;
 343         u32 vmx_preemption_timer_value;
 344         u32 padding32[7]; /* room for future expansion */
 345         u16 virtual_processor_id;
 346         u16 posted_intr_nv;
 347         u16 guest_es_selector;
 348         u16 guest_cs_selector;
 349         u16 guest_ss_selector;
 350         u16 guest_ds_selector;
 351         u16 guest_fs_selector;
 352         u16 guest_gs_selector;
 353         u16 guest_ldtr_selector;
 354         u16 guest_tr_selector;
 355         u16 guest_intr_status;
 356         u16 host_es_selector;
 357         u16 host_cs_selector;
 358         u16 host_ss_selector;
 359         u16 host_ds_selector;
 360         u16 host_fs_selector;
 361         u16 host_gs_selector;
 362         u16 host_tr_selector;
 363 };
 364
 365 /*
 366  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 367  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 368  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 369  */
 370 #define VMCS12_REVISION 0x11e57ed0
 371
 372 /*
 373  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 374  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 375  * current implementation, 4K are reserved to avoid future complications.
 376  */
 377 #define VMCS12_SIZE 0x1000
 378
 379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 380 struct vmcs02_list {
 381         struct list_head list;
 382         gpa_t vmptr;
 383         struct loaded_vmcs vmcs02;
 384 };
 385
 386 /*
 387  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 388  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 389  */
 390 struct nested_vmx {
 391         /* Has the level1 guest done vmxon? */
 392         bool vmxon;
 393         gpa_t vmxon_ptr;
 394
 395         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 396         gpa_t current_vmptr;
 397         /* The host-usable pointer to the above */
 398         struct page *current_vmcs12_page;
 399         struct vmcs12 *current_vmcs12;
 400         struct vmcs *current_shadow_vmcs;
 401         /*
 402          * Indicates if the shadow vmcs must be updated with the
 403          * data hold by vmcs12
 404          */
 405         bool sync_shadow_vmcs;
 406
 407         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 408         struct list_head vmcs02_pool;
 409         int vmcs02_num;
 410         u64 vmcs01_tsc_offset;
 411         /* L2 must run next, and mustn't decide to exit to L1. */
 412         bool nested_run_pending;
 413         /*
 414          * Guest pages referred to in vmcs02 with host-physical pointers, so
 415          * we must keep them pinned while L2 runs.
 416          */
 417         struct page *apic_access_page;
 418         struct page *virtual_apic_page;
 419         struct page *pi_desc_page;
 420         struct pi_desc *pi_desc;
 421         bool pi_pending;
 422         u16 posted_intr_nv;
 423         u64 msr_ia32_feature_control;
 424
 425         struct hrtimer preemption_timer;
 426         bool preemption_timer_expired;
 427
 428         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 429         u64 vmcs01_debugctl;
 430
 431         u16 vpid02;
 432         u16 last_vpid;
 433
 434         u32 nested_vmx_procbased_ctls_low;
 435         u32 nested_vmx_procbased_ctls_high;
 436         u32 nested_vmx_true_procbased_ctls_low;
 437         u32 nested_vmx_secondary_ctls_low;
 438         u32 nested_vmx_secondary_ctls_high;
 439         u32 nested_vmx_pinbased_ctls_low;
 440         u32 nested_vmx_pinbased_ctls_high;
 441         u32 nested_vmx_exit_ctls_low;
 442         u32 nested_vmx_exit_ctls_high;
 443         u32 nested_vmx_true_exit_ctls_low;
 444         u32 nested_vmx_entry_ctls_low;
 445         u32 nested_vmx_entry_ctls_high;
 446         u32 nested_vmx_true_entry_ctls_low;
 447         u32 nested_vmx_misc_low;
 448         u32 nested_vmx_misc_high;
 449         u32 nested_vmx_ept_caps;
 450         u32 nested_vmx_vpid_caps;
 451 };
 452
 453 #define POSTED_INTR_ON  0
 454 #define POSTED_INTR_SN  1
 455
 456 /* Posted-Interrupt Descriptor */
 457 struct pi_desc {
 458         u32 pir[8];     /* Posted interrupt requested */
 459         union {
 460                 struct {
 461                                 /* bit 256 - Outstanding Notification */
 462                         u16     on      : 1,
 463                                 /* bit 257 - Suppress Notification */
 464                                 sn      : 1,
 465                                 /* bit 271:258 - Reserved */
 466                                 rsvd_1  : 14;
 467                                 /* bit 279:272 - Notification Vector */
 468                         u8      nv;
 469                                 /* bit 287:280 - Reserved */
 470                         u8      rsvd_2;
 471                                 /* bit 319:288 - Notification Destination */
 472                         u32     ndst;
 473                 };
 474                 u64 control;
 475         };
 476         u32 rsvd[6];
 477 } __aligned(64);
 478
 479 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 480 {
 481         return test_and_set_bit(POSTED_INTR_ON,
 482                         (unsigned long *)&pi_desc->control);
 483 }
 484
 485 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 486 {
 487         return test_and_clear_bit(POSTED_INTR_ON,
 488                         (unsigned long *)&pi_desc->control);
 489 }
 490
 491 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 492 {
 493         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 494 }
 495
 496 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 497 {
 498         return clear_bit(POSTED_INTR_SN,
 499                         (unsigned long *)&pi_desc->control);
 500 }
 501
 502 static inline void pi_set_sn(struct pi_desc *pi_desc)
 503 {
 504         return set_bit(POSTED_INTR_SN,
 505                         (unsigned long *)&pi_desc->control);
 506 }
 507
 508 static inline int pi_test_on(struct pi_desc *pi_desc)
 509 {
 510         return test_bit(POSTED_INTR_ON,
 511                         (unsigned long *)&pi_desc->control);
 512 }
 513
 514 static inline int pi_test_sn(struct pi_desc *pi_desc)
 515 {
 516         return test_bit(POSTED_INTR_SN,
 517                         (unsigned long *)&pi_desc->control);
 518 }
 519
 520 struct vcpu_vmx {
 521         struct kvm_vcpu       vcpu;
 522         unsigned long         host_rsp;
 523         u8                    fail;
 524         bool                  nmi_known_unmasked;
 525         u32                   exit_intr_info;
 526         u32                   idt_vectoring_info;
 527         ulong                 rflags;
 528         struct shared_msr_entry *guest_msrs;
 529         int                   nmsrs;
 530         int                   save_nmsrs;
 531         unsigned long         host_idt_base;
 532 #ifdef CONFIG_X86_64
 533         u64                   msr_host_kernel_gs_base;
 534         u64                   msr_guest_kernel_gs_base;
 535 #endif
 536         u32 vm_entry_controls_shadow;
 537         u32 vm_exit_controls_shadow;
 538         /*
 539          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 540          * non-nested (L1) guest, it always points to vmcs01. For a nested
 541          * guest (L2), it points to a different VMCS.
 542          */
 543         struct loaded_vmcs    vmcs01;
 544         struct loaded_vmcs   *loaded_vmcs;
 545         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 546         struct msr_autoload {
 547                 unsigned nr;
 548                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 549                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 550         } msr_autoload;
 551         struct {
 552                 int           loaded;
 553                 u16           fs_sel, gs_sel, ldt_sel;
 554 #ifdef CONFIG_X86_64
 555                 u16           ds_sel, es_sel;
 556 #endif
 557                 int           gs_ldt_reload_needed;
 558                 int           fs_reload_needed;
 559                 u64           msr_host_bndcfgs;
 560                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 561         } host_state;
 562         struct {
 563                 int vm86_active;
 564                 ulong save_rflags;
 565                 struct kvm_segment segs[8];
 566         } rmode;
 567         struct {
 568                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 569                 struct kvm_save_segment {
 570                         u16 selector;
 571                         unsigned long base;
 572                         u32 limit;
 573                         u32 ar;
 574                 } seg[8];
 575         } segment_cache;
 576         int vpid;
 577         bool emulation_required;
 578
 579         /* Support for vnmi-less CPUs */
 580         int soft_vnmi_blocked;
 581         ktime_t entry_time;
 582         s64 vnmi_blocked_time;
 583         u32 exit_reason;
 584
 585         /* Posted interrupt descriptor */
 586         struct pi_desc pi_desc;
 587
 588         /* Support for a guest hypervisor (nested VMX) */
 589         struct nested_vmx nested;
 590
 591         /* Dynamic PLE window. */
 592         int ple_window;
 593         bool ple_window_dirty;
 594
 595         /* Support for PML */
 596 #define PML_ENTITY_NUM          512
 597         struct page *pml_pg;
 598 };
 599
 600 enum segment_cache_field {
 601         SEG_FIELD_SEL = 0,
 602         SEG_FIELD_BASE = 1,
 603         SEG_FIELD_LIMIT = 2,
 604         SEG_FIELD_AR = 3,
 605
 606         SEG_FIELD_NR = 4
 607 };
 608
 609 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 610 {
 611         return container_of(vcpu, struct vcpu_vmx, vcpu);
 612 }
 613
 614 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 615 {
 616         return &(to_vmx(vcpu)->pi_desc);
 617 }
 618
 619 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 620 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 621 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 622                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 623
 624
 625 static unsigned long shadow_read_only_fields[] = {
 626         /*
 627          * We do NOT shadow fields that are modified when L0
 628          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 629          * VMXON...) executed by L1.
 630          * For example, VM_INSTRUCTION_ERROR is read
 631          * by L1 if a vmx instruction fails (part of the error path).
 632          * Note the code assumes this logic. If for some reason
 633          * we start shadowing these fields then we need to
 634          * force a shadow sync when L0 emulates vmx instructions
 635          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 636          * by nested_vmx_failValid)
 637          */
 638         VM_EXIT_REASON,
 639         VM_EXIT_INTR_INFO,
 640         VM_EXIT_INSTRUCTION_LEN,
 641         IDT_VECTORING_INFO_FIELD,
 642         IDT_VECTORING_ERROR_CODE,
 643         VM_EXIT_INTR_ERROR_CODE,
 644         EXIT_QUALIFICATION,
 645         GUEST_LINEAR_ADDRESS,
 646         GUEST_PHYSICAL_ADDRESS
 647 };
 648 static int max_shadow_read_only_fields =
 649         ARRAY_SIZE(shadow_read_only_fields);
 650
 651 static unsigned long shadow_read_write_fields[] = {
 652         TPR_THRESHOLD,
 653         GUEST_RIP,
 654         GUEST_RSP,
 655         GUEST_CR0,
 656         GUEST_CR3,
 657         GUEST_CR4,
 658         GUEST_INTERRUPTIBILITY_INFO,
 659         GUEST_RFLAGS,
 660         GUEST_CS_SELECTOR,
 661         GUEST_CS_AR_BYTES,
 662         GUEST_CS_LIMIT,
 663         GUEST_CS_BASE,
 664         GUEST_ES_BASE,
 665         GUEST_BNDCFGS,
 666         CR0_GUEST_HOST_MASK,
 667         CR0_READ_SHADOW,
 668         CR4_READ_SHADOW,
 669         TSC_OFFSET,
 670         EXCEPTION_BITMAP,
 671         CPU_BASED_VM_EXEC_CONTROL,
 672         VM_ENTRY_EXCEPTION_ERROR_CODE,
 673         VM_ENTRY_INTR_INFO_FIELD,
 674         VM_ENTRY_INSTRUCTION_LEN,
 675         VM_ENTRY_EXCEPTION_ERROR_CODE,
 676         HOST_FS_BASE,
 677         HOST_GS_BASE,
 678         HOST_FS_SELECTOR,
 679         HOST_GS_SELECTOR
 680 };
 681 static int max_shadow_read_write_fields =
 682         ARRAY_SIZE(shadow_read_write_fields);
 683
 684 static const unsigned short vmcs_field_to_offset_table[] = {
 685         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 686         FIELD(POSTED_INTR_NV, posted_intr_nv),
 687         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 688         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 689         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 690         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 691         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 692         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 693         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 694         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 695         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 696         FIELD(HOST_ES_SELECTOR, host_es_selector),
 697         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 698         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 699         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 700         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 701         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 702         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 703         FIELD64(IO_BITMAP_A, io_bitmap_a),
 704         FIELD64(IO_BITMAP_B, io_bitmap_b),
 705         FIELD64(MSR_BITMAP, msr_bitmap),
 706         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 707         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 708         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 709         FIELD64(TSC_OFFSET, tsc_offset),
 710         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 711         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 712         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 713         FIELD64(EPT_POINTER, ept_pointer),
 714         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 715         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 716         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 717         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 718         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 719         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 720         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 721         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 722         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 723         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 724         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 725         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 726         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 727         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 728         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 729         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 730         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 731         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 732         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 733         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 734         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 735         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 736         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 737         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 738         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 739         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 740         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 741         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 742         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 743         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 744         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 745         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 746         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 747         FIELD(TPR_THRESHOLD, tpr_threshold),
 748         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 749         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 750         FIELD(VM_EXIT_REASON, vm_exit_reason),
 751         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 752         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 753         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 754         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 755         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 756         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 757         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 758         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 759         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 760         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 761         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 762         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 763         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 764         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 765         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 766         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 767         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 768         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 769         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 770         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 771         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 772         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 773         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 774         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 775         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 776         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 777         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 778         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 779         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 780         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 781         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 782         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 783         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 784         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 785         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 786         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 787         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 788         FIELD(EXIT_QUALIFICATION, exit_qualification),
 789         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 790         FIELD(GUEST_CR0, guest_cr0),
 791         FIELD(GUEST_CR3, guest_cr3),
 792         FIELD(GUEST_CR4, guest_cr4),
 793         FIELD(GUEST_ES_BASE, guest_es_base),
 794         FIELD(GUEST_CS_BASE, guest_cs_base),
 795         FIELD(GUEST_SS_BASE, guest_ss_base),
 796         FIELD(GUEST_DS_BASE, guest_ds_base),
 797         FIELD(GUEST_FS_BASE, guest_fs_base),
 798         FIELD(GUEST_GS_BASE, guest_gs_base),
 799         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 800         FIELD(GUEST_TR_BASE, guest_tr_base),
 801         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 802         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 803         FIELD(GUEST_DR7, guest_dr7),
 804         FIELD(GUEST_RSP, guest_rsp),
 805         FIELD(GUEST_RIP, guest_rip),
 806         FIELD(GUEST_RFLAGS, guest_rflags),
 807         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 808         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 809         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 810         FIELD(HOST_CR0, host_cr0),
 811         FIELD(HOST_CR3, host_cr3),
 812         FIELD(HOST_CR4, host_cr4),
 813         FIELD(HOST_FS_BASE, host_fs_base),
 814         FIELD(HOST_GS_BASE, host_gs_base),
 815         FIELD(HOST_TR_BASE, host_tr_base),
 816         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 817         FIELD(HOST_IDTR_BASE, host_idtr_base),
 818         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 819         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 820         FIELD(HOST_RSP, host_rsp),
 821         FIELD(HOST_RIP, host_rip),
 822 };
 823
 824 static inline short vmcs_field_to_offset(unsigned long field)
 825 {
 826         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 827
 828         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 829             vmcs_field_to_offset_table[field] == 0)
 830                 return -ENOENT;
 831
 832         return vmcs_field_to_offset_table[field];
 833 }
 834
 835 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 836 {
 837         return to_vmx(vcpu)->nested.current_vmcs12;
 838 }
 839
 840 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 841 {
 842         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 843         if (is_error_page(page))
 844                 return NULL;
 845
 846         return page;
 847 }
 848
 849 static void nested_release_page(struct page *page)
 850 {
 851         kvm_release_page_dirty(page);
 852 }
 853
 854 static void nested_release_page_clean(struct page *page)
 855 {
 856         kvm_release_page_clean(page);
 857 }
 858
 859 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 860 static u64 construct_eptp(unsigned long root_hpa);
 861 static void kvm_cpu_vmxon(u64 addr);
 862 static void kvm_cpu_vmxoff(void);
 863 static bool vmx_mpx_supported(void);
 864 static bool vmx_xsaves_supported(void);
 865 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 866 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 867 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 868                             struct kvm_segment *var, int seg);
 869 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 872 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 873 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 874 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 875 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 876 static int alloc_identity_pagetable(struct kvm *kvm);
 877
 878 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 879 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 880 /*
 881  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 882  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 883  */
 884 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 885 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 886
 887 /*
 888  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 889  * can find which vCPU should be waken up.
 890  */
 891 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 892 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 893
 894 static unsigned long *vmx_io_bitmap_a;
 895 static unsigned long *vmx_io_bitmap_b;
 896 static unsigned long *vmx_msr_bitmap_legacy;
 897 static unsigned long *vmx_msr_bitmap_longmode;
 898 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 899 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 900 static unsigned long *vmx_msr_bitmap_nested;
 901 static unsigned long *vmx_vmread_bitmap;
 902 static unsigned long *vmx_vmwrite_bitmap;
 903
 904 static bool cpu_has_load_ia32_efer;
 905 static bool cpu_has_load_perf_global_ctrl;
 906
 907 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 908 static DEFINE_SPINLOCK(vmx_vpid_lock);
 909
 910 static struct vmcs_config {
 911         int size;
 912         int order;
 913         u32 revision_id;
 914         u32 pin_based_exec_ctrl;
 915         u32 cpu_based_exec_ctrl;
 916         u32 cpu_based_2nd_exec_ctrl;
 917         u32 vmexit_ctrl;
 918         u32 vmentry_ctrl;
 919 } vmcs_config;
 920
 921 static struct vmx_capability {
 922         u32 ept;
 923         u32 vpid;
 924 } vmx_capability;
 925
 926 #define VMX_SEGMENT_FIELD(seg)                                  \
 927         [VCPU_SREG_##seg] = {                                   \
 928                 .selector = GUEST_##seg##_SELECTOR,             \
 929                 .base = GUEST_##seg##_BASE,                     \
 930                 .limit = GUEST_##seg##_LIMIT,                   \
 931                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 932         }
 933
 934 static const struct kvm_vmx_segment_field {
 935         unsigned selector;
 936         unsigned base;
 937         unsigned limit;
 938         unsigned ar_bytes;
 939 } kvm_vmx_segment_fields[] = {
 940         VMX_SEGMENT_FIELD(CS),
 941         VMX_SEGMENT_FIELD(DS),
 942         VMX_SEGMENT_FIELD(ES),
 943         VMX_SEGMENT_FIELD(FS),
 944         VMX_SEGMENT_FIELD(GS),
 945         VMX_SEGMENT_FIELD(SS),
 946         VMX_SEGMENT_FIELD(TR),
 947         VMX_SEGMENT_FIELD(LDTR),
 948 };
 949
 950 static u64 host_efer;
 951
 952 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 953
 954 /*
 955  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 956  * away by decrementing the array size.
 957  */
 958 static const u32 vmx_msr_index[] = {
 959 #ifdef CONFIG_X86_64
 960         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 961 #endif
 962         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 963 };
 964
 965 static inline bool is_page_fault(u32 intr_info)
 966 {
 967         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 968                              INTR_INFO_VALID_MASK)) ==
 969                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 970 }
 971
 972 static inline bool is_no_device(u32 intr_info)
 973 {
 974         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 975                              INTR_INFO_VALID_MASK)) ==
 976                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 977 }
 978
 979 static inline bool is_invalid_opcode(u32 intr_info)
 980 {
 981         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 982                              INTR_INFO_VALID_MASK)) ==
 983                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 984 }
 985
 986 static inline bool is_external_interrupt(u32 intr_info)
 987 {
 988         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 989                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 990 }
 991
 992 static inline bool is_machine_check(u32 intr_info)
 993 {
 994         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 995                              INTR_INFO_VALID_MASK)) ==
 996                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 997 }
 998
 999 static inline bool cpu_has_vmx_msr_bitmap(void)
1000 {
1001         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1002 }
1003
1004 static inline bool cpu_has_vmx_tpr_shadow(void)
1005 {
1006         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1007 }
1008
1009 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1010 {
1011         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1012 }
1013
1014 static inline bool cpu_has_secondary_exec_ctrls(void)
1015 {
1016         return vmcs_config.cpu_based_exec_ctrl &
1017                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1018 }
1019
1020 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1021 {
1022         return vmcs_config.cpu_based_2nd_exec_ctrl &
1023                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1024 }
1025
1026 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1027 {
1028         return vmcs_config.cpu_based_2nd_exec_ctrl &
1029                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1030 }
1031
1032 static inline bool cpu_has_vmx_apic_register_virt(void)
1033 {
1034         return vmcs_config.cpu_based_2nd_exec_ctrl &
1035                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1036 }
1037
1038 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1039 {
1040         return vmcs_config.cpu_based_2nd_exec_ctrl &
1041                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1042 }
1043
1044 static inline bool cpu_has_vmx_posted_intr(void)
1045 {
1046         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1047                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1048 }
1049
1050 static inline bool cpu_has_vmx_apicv(void)
1051 {
1052         return cpu_has_vmx_apic_register_virt() &&
1053                 cpu_has_vmx_virtual_intr_delivery() &&
1054                 cpu_has_vmx_posted_intr();
1055 }
1056
1057 static inline bool cpu_has_vmx_flexpriority(void)
1058 {
1059         return cpu_has_vmx_tpr_shadow() &&
1060                 cpu_has_vmx_virtualize_apic_accesses();
1061 }
1062
1063 static inline bool cpu_has_vmx_ept_execute_only(void)
1064 {
1065         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1066 }
1067
1068 static inline bool cpu_has_vmx_ept_2m_page(void)
1069 {
1070         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1071 }
1072
1073 static inline bool cpu_has_vmx_ept_1g_page(void)
1074 {
1075         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1076 }
1077
1078 static inline bool cpu_has_vmx_ept_4levels(void)
1079 {
1080         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1081 }
1082
1083 static inline bool cpu_has_vmx_ept_ad_bits(void)
1084 {
1085         return vmx_capability.ept & VMX_EPT_AD_BIT;
1086 }
1087
1088 static inline bool cpu_has_vmx_invept_context(void)
1089 {
1090         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1091 }
1092
1093 static inline bool cpu_has_vmx_invept_global(void)
1094 {
1095         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1096 }
1097
1098 static inline bool cpu_has_vmx_invvpid_single(void)
1099 {
1100         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1101 }
1102
1103 static inline bool cpu_has_vmx_invvpid_global(void)
1104 {
1105         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1106 }
1107
1108 static inline bool cpu_has_vmx_ept(void)
1109 {
1110         return vmcs_config.cpu_based_2nd_exec_ctrl &
1111                 SECONDARY_EXEC_ENABLE_EPT;
1112 }
1113
1114 static inline bool cpu_has_vmx_unrestricted_guest(void)
1115 {
1116         return vmcs_config.cpu_based_2nd_exec_ctrl &
1117                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1118 }
1119
1120 static inline bool cpu_has_vmx_ple(void)
1121 {
1122         return vmcs_config.cpu_based_2nd_exec_ctrl &
1123                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1124 }
1125
1126 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1127 {
1128         return flexpriority_enabled && lapic_in_kernel(vcpu);
1129 }
1130
1131 static inline bool cpu_has_vmx_vpid(void)
1132 {
1133         return vmcs_config.cpu_based_2nd_exec_ctrl &
1134                 SECONDARY_EXEC_ENABLE_VPID;
1135 }
1136
1137 static inline bool cpu_has_vmx_rdtscp(void)
1138 {
1139         return vmcs_config.cpu_based_2nd_exec_ctrl &
1140                 SECONDARY_EXEC_RDTSCP;
1141 }
1142
1143 static inline bool cpu_has_vmx_invpcid(void)
1144 {
1145         return vmcs_config.cpu_based_2nd_exec_ctrl &
1146                 SECONDARY_EXEC_ENABLE_INVPCID;
1147 }
1148
1149 static inline bool cpu_has_virtual_nmis(void)
1150 {
1151         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1152 }
1153
1154 static inline bool cpu_has_vmx_wbinvd_exit(void)
1155 {
1156         return vmcs_config.cpu_based_2nd_exec_ctrl &
1157                 SECONDARY_EXEC_WBINVD_EXITING;
1158 }
1159
1160 static inline bool cpu_has_vmx_shadow_vmcs(void)
1161 {
1162         u64 vmx_msr;
1163         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1164         /* check if the cpu supports writing r/o exit information fields */
1165         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1166                 return false;
1167
1168         return vmcs_config.cpu_based_2nd_exec_ctrl &
1169                 SECONDARY_EXEC_SHADOW_VMCS;
1170 }
1171
1172 static inline bool cpu_has_vmx_pml(void)
1173 {
1174         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1175 }
1176
1177 static inline bool cpu_has_vmx_tsc_scaling(void)
1178 {
1179         return vmcs_config.cpu_based_2nd_exec_ctrl &
1180                 SECONDARY_EXEC_TSC_SCALING;
1181 }
1182
1183 static inline bool report_flexpriority(void)
1184 {
1185         return flexpriority_enabled;
1186 }
1187
1188 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1189 {
1190         return vmcs12->cpu_based_vm_exec_control & bit;
1191 }
1192
1193 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1194 {
1195         return (vmcs12->cpu_based_vm_exec_control &
1196                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1197                 (vmcs12->secondary_vm_exec_control & bit);
1198 }
1199
1200 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1201 {
1202         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1203 }
1204
1205 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1206 {
1207         return vmcs12->pin_based_vm_exec_control &
1208                 PIN_BASED_VMX_PREEMPTION_TIMER;
1209 }
1210
1211 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1212 {
1213         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1214 }
1215
1216 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1217 {
1218         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1219                 vmx_xsaves_supported();
1220 }
1221
1222 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1223 {
1224         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1225 }
1226
1227 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1228 {
1229         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1230 }
1231
1232 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1233 {
1234         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1235 }
1236
1237 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1238 {
1239         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1240 }
1241
1242 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1243 {
1244         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1245 }
1246
1247 static inline bool is_exception(u32 intr_info)
1248 {
1249         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1250                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1251 }
1252
1253 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1254                               u32 exit_intr_info,
1255                               unsigned long exit_qualification);
1256 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1257                         struct vmcs12 *vmcs12,
1258                         u32 reason, unsigned long qualification);
1259
1260 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1261 {
1262         int i;
1263
1264         for (i = 0; i < vmx->nmsrs; ++i)
1265                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1266                         return i;
1267         return -1;
1268 }
1269
1270 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1271 {
1272     struct {
1273         u64 vpid : 16;
1274         u64 rsvd : 48;
1275         u64 gva;
1276     } operand = { vpid, 0, gva };
1277
1278     asm volatile (__ex(ASM_VMX_INVVPID)
1279                   /* CF==1 or ZF==1 --> rc = -1 */
1280                   "; ja 1f ; ud2 ; 1:"
1281                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1282 }
1283
1284 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1285 {
1286         struct {
1287                 u64 eptp, gpa;
1288         } operand = {eptp, gpa};
1289
1290         asm volatile (__ex(ASM_VMX_INVEPT)
1291                         /* CF==1 or ZF==1 --> rc = -1 */
1292                         "; ja 1f ; ud2 ; 1:\n"
1293                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1294 }
1295
1296 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1297 {
1298         int i;
1299
1300         i = __find_msr_index(vmx, msr);
1301         if (i >= 0)
1302                 return &vmx->guest_msrs[i];
1303         return NULL;
1304 }
1305
1306 static void vmcs_clear(struct vmcs *vmcs)
1307 {
1308         u64 phys_addr = __pa(vmcs);
1309         u8 error;
1310
1311         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1312                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1313                       : "cc", "memory");
1314         if (error)
1315                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1316                        vmcs, phys_addr);
1317 }
1318
1319 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1320 {
1321         vmcs_clear(loaded_vmcs->vmcs);
1322         loaded_vmcs->cpu = -1;
1323         loaded_vmcs->launched = 0;
1324 }
1325
1326 static void vmcs_load(struct vmcs *vmcs)
1327 {
1328         u64 phys_addr = __pa(vmcs);
1329         u8 error;
1330
1331         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1332                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1333                         : "cc", "memory");
1334         if (error)
1335                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1336                        vmcs, phys_addr);
1337 }
1338
1339 #ifdef CONFIG_KEXEC_CORE
1340 /*
1341  * This bitmap is used to indicate whether the vmclear
1342  * operation is enabled on all cpus. All disabled by
1343  * default.
1344  */
1345 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1346
1347 static inline void crash_enable_local_vmclear(int cpu)
1348 {
1349         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1350 }
1351
1352 static inline void crash_disable_local_vmclear(int cpu)
1353 {
1354         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1355 }
1356
1357 static inline int crash_local_vmclear_enabled(int cpu)
1358 {
1359         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1360 }
1361
1362 static void crash_vmclear_local_loaded_vmcss(void)
1363 {
1364         int cpu = raw_smp_processor_id();
1365         struct loaded_vmcs *v;
1366
1367         if (!crash_local_vmclear_enabled(cpu))
1368                 return;
1369
1370         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1371                             loaded_vmcss_on_cpu_link)
1372                 vmcs_clear(v->vmcs);
1373 }
1374 #else
1375 static inline void crash_enable_local_vmclear(int cpu) { }
1376 static inline void crash_disable_local_vmclear(int cpu) { }
1377 #endif /* CONFIG_KEXEC_CORE */
1378
1379 static void __loaded_vmcs_clear(void *arg)
1380 {
1381         struct loaded_vmcs *loaded_vmcs = arg;
1382         int cpu = raw_smp_processor_id();
1383
1384         if (loaded_vmcs->cpu != cpu)
1385                 return; /* vcpu migration can race with cpu offline */
1386         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1387                 per_cpu(current_vmcs, cpu) = NULL;
1388         crash_disable_local_vmclear(cpu);
1389         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1390
1391         /*
1392          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1393          * is before setting loaded_vmcs->vcpu to -1 which is done in
1394          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1395          * then adds the vmcs into percpu list before it is deleted.
1396          */
1397         smp_wmb();
1398
1399         loaded_vmcs_init(loaded_vmcs);
1400         crash_enable_local_vmclear(cpu);
1401 }
1402
1403 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1404 {
1405         int cpu = loaded_vmcs->cpu;
1406
1407         if (cpu != -1)
1408                 smp_call_function_single(cpu,
1409                          __loaded_vmcs_clear, loaded_vmcs, 1);
1410 }
1411
1412 static inline void vpid_sync_vcpu_single(int vpid)
1413 {
1414         if (vpid == 0)
1415                 return;
1416
1417         if (cpu_has_vmx_invvpid_single())
1418                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1419 }
1420
1421 static inline void vpid_sync_vcpu_global(void)
1422 {
1423         if (cpu_has_vmx_invvpid_global())
1424                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1425 }
1426
1427 static inline void vpid_sync_context(int vpid)
1428 {
1429         if (cpu_has_vmx_invvpid_single())
1430                 vpid_sync_vcpu_single(vpid);
1431         else
1432                 vpid_sync_vcpu_global();
1433 }
1434
1435 static inline void ept_sync_global(void)
1436 {
1437         if (cpu_has_vmx_invept_global())
1438                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1439 }
1440
1441 static inline void ept_sync_context(u64 eptp)
1442 {
1443         if (enable_ept) {
1444                 if (cpu_has_vmx_invept_context())
1445                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1446                 else
1447                         ept_sync_global();
1448         }
1449 }
1450
1451 static __always_inline unsigned long vmcs_readl(unsigned long field)
1452 {
1453         unsigned long value;
1454
1455         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1456                       : "=a"(value) : "d"(field) : "cc");
1457         return value;
1458 }
1459
1460 static __always_inline u16 vmcs_read16(unsigned long field)
1461 {
1462         return vmcs_readl(field);
1463 }
1464
1465 static __always_inline u32 vmcs_read32(unsigned long field)
1466 {
1467         return vmcs_readl(field);
1468 }
1469
1470 static __always_inline u64 vmcs_read64(unsigned long field)
1471 {
1472 #ifdef CONFIG_X86_64
1473         return vmcs_readl(field);
1474 #else
1475         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1476 #endif
1477 }
1478
1479 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1480 {
1481         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1482                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1483         dump_stack();
1484 }
1485
1486 static void vmcs_writel(unsigned long field, unsigned long value)
1487 {
1488         u8 error;
1489
1490         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1491                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1492         if (unlikely(error))
1493                 vmwrite_error(field, value);
1494 }
1495
1496 static void vmcs_write16(unsigned long field, u16 value)
1497 {
1498         vmcs_writel(field, value);
1499 }
1500
1501 static void vmcs_write32(unsigned long field, u32 value)
1502 {
1503         vmcs_writel(field, value);
1504 }
1505
1506 static void vmcs_write64(unsigned long field, u64 value)
1507 {
1508         vmcs_writel(field, value);
1509 #ifndef CONFIG_X86_64
1510         asm volatile ("");
1511         vmcs_writel(field+1, value >> 32);
1512 #endif
1513 }
1514
1515 static void vmcs_clear_bits(unsigned long field, u32 mask)
1516 {
1517         vmcs_writel(field, vmcs_readl(field) & ~mask);
1518 }
1519
1520 static void vmcs_set_bits(unsigned long field, u32 mask)
1521 {
1522         vmcs_writel(field, vmcs_readl(field) | mask);
1523 }
1524
1525 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1526 {
1527         vmcs_write32(VM_ENTRY_CONTROLS, val);
1528         vmx->vm_entry_controls_shadow = val;
1529 }
1530
1531 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1532 {
1533         if (vmx->vm_entry_controls_shadow != val)
1534                 vm_entry_controls_init(vmx, val);
1535 }
1536
1537 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1538 {
1539         return vmx->vm_entry_controls_shadow;
1540 }
1541
1542
1543 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1544 {
1545         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1546 }
1547
1548 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1549 {
1550         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1551 }
1552
1553 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1554 {
1555         vmcs_write32(VM_EXIT_CONTROLS, val);
1556         vmx->vm_exit_controls_shadow = val;
1557 }
1558
1559 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1560 {
1561         if (vmx->vm_exit_controls_shadow != val)
1562                 vm_exit_controls_init(vmx, val);
1563 }
1564
1565 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1566 {
1567         return vmx->vm_exit_controls_shadow;
1568 }
1569
1570
1571 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1572 {
1573         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1574 }
1575
1576 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1577 {
1578         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1579 }
1580
1581 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1582 {
1583         vmx->segment_cache.bitmask = 0;
1584 }
1585
1586 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1587                                        unsigned field)
1588 {
1589         bool ret;
1590         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1591
1592         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1593                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1594                 vmx->segment_cache.bitmask = 0;
1595         }
1596         ret = vmx->segment_cache.bitmask & mask;
1597         vmx->segment_cache.bitmask |= mask;
1598         return ret;
1599 }
1600
1601 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1602 {
1603         u16 *p = &vmx->segment_cache.seg[seg].selector;
1604
1605         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1606                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1607         return *p;
1608 }
1609
1610 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1611 {
1612         ulong *p = &vmx->segment_cache.seg[seg].base;
1613
1614         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1615                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1616         return *p;
1617 }
1618
1619 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1620 {
1621         u32 *p = &vmx->segment_cache.seg[seg].limit;
1622
1623         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1624                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1625         return *p;
1626 }
1627
1628 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1629 {
1630         u32 *p = &vmx->segment_cache.seg[seg].ar;
1631
1632         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1633                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1634         return *p;
1635 }
1636
1637 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1638 {
1639         u32 eb;
1640
1641         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1642              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1643         if ((vcpu->guest_debug &
1644              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1645             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1646                 eb |= 1u << BP_VECTOR;
1647         if (to_vmx(vcpu)->rmode.vm86_active)
1648                 eb = ~0;
1649         if (enable_ept)
1650                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1651         if (vcpu->fpu_active)
1652                 eb &= ~(1u << NM_VECTOR);
1653
1654         /* When we are running a nested L2 guest and L1 specified for it a
1655          * certain exception bitmap, we must trap the same exceptions and pass
1656          * them to L1. When running L2, we will only handle the exceptions
1657          * specified above if L1 did not want them.
1658          */
1659         if (is_guest_mode(vcpu))
1660                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1661
1662         vmcs_write32(EXCEPTION_BITMAP, eb);
1663 }
1664
1665 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1666                 unsigned long entry, unsigned long exit)
1667 {
1668         vm_entry_controls_clearbit(vmx, entry);
1669         vm_exit_controls_clearbit(vmx, exit);
1670 }
1671
1672 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1673 {
1674         unsigned i;
1675         struct msr_autoload *m = &vmx->msr_autoload;
1676
1677         switch (msr) {
1678         case MSR_EFER:
1679                 if (cpu_has_load_ia32_efer) {
1680                         clear_atomic_switch_msr_special(vmx,
1681                                         VM_ENTRY_LOAD_IA32_EFER,
1682                                         VM_EXIT_LOAD_IA32_EFER);
1683                         return;
1684                 }
1685                 break;
1686         case MSR_CORE_PERF_GLOBAL_CTRL:
1687                 if (cpu_has_load_perf_global_ctrl) {
1688                         clear_atomic_switch_msr_special(vmx,
1689                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1690                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1691                         return;
1692                 }
1693                 break;
1694         }
1695
1696         for (i = 0; i < m->nr; ++i)
1697                 if (m->guest[i].index == msr)
1698                         break;
1699
1700         if (i == m->nr)
1701                 return;
1702         --m->nr;
1703         m->guest[i] = m->guest[m->nr];
1704         m->host[i] = m->host[m->nr];
1705         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1706         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1707 }
1708
1709 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1710                 unsigned long entry, unsigned long exit,
1711                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1712                 u64 guest_val, u64 host_val)
1713 {
1714         vmcs_write64(guest_val_vmcs, guest_val);
1715         vmcs_write64(host_val_vmcs, host_val);
1716         vm_entry_controls_setbit(vmx, entry);
1717         vm_exit_controls_setbit(vmx, exit);
1718 }
1719
1720 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1721                                   u64 guest_val, u64 host_val)
1722 {
1723         unsigned i;
1724         struct msr_autoload *m = &vmx->msr_autoload;
1725
1726         switch (msr) {
1727         case MSR_EFER:
1728                 if (cpu_has_load_ia32_efer) {
1729                         add_atomic_switch_msr_special(vmx,
1730                                         VM_ENTRY_LOAD_IA32_EFER,
1731                                         VM_EXIT_LOAD_IA32_EFER,
1732                                         GUEST_IA32_EFER,
1733                                         HOST_IA32_EFER,
1734                                         guest_val, host_val);
1735                         return;
1736                 }
1737                 break;
1738         case MSR_CORE_PERF_GLOBAL_CTRL:
1739                 if (cpu_has_load_perf_global_ctrl) {
1740                         add_atomic_switch_msr_special(vmx,
1741                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1742                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1743                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1744                                         HOST_IA32_PERF_GLOBAL_CTRL,
1745                                         guest_val, host_val);
1746                         return;
1747                 }
1748                 break;
1749         }
1750
1751         for (i = 0; i < m->nr; ++i)
1752                 if (m->guest[i].index == msr)
1753                         break;
1754
1755         if (i == NR_AUTOLOAD_MSRS) {
1756                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1757                                 "Can't add msr %x\n", msr);
1758                 return;
1759         } else if (i == m->nr) {
1760                 ++m->nr;
1761                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1762                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1763         }
1764
1765         m->guest[i].index = msr;
1766         m->guest[i].value = guest_val;
1767         m->host[i].index = msr;
1768         m->host[i].value = host_val;
1769 }
1770
1771 static void reload_tss(void)
1772 {
1773         /*
1774          * VT restores TR but not its size.  Useless.
1775          */
1776         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1777         struct desc_struct *descs;
1778
1779         descs = (void *)gdt->address;
1780         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1781         load_TR_desc();
1782 }
1783
1784 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1785 {
1786         u64 guest_efer;
1787         u64 ignore_bits;
1788
1789         guest_efer = vmx->vcpu.arch.efer;
1790
1791         /*
1792          * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1793          * outside long mode
1794          */
1795         ignore_bits = EFER_NX | EFER_SCE;
1796 #ifdef CONFIG_X86_64
1797         ignore_bits |= EFER_LMA | EFER_LME;
1798         /* SCE is meaningful only in long mode on Intel */
1799         if (guest_efer & EFER_LMA)
1800                 ignore_bits &= ~(u64)EFER_SCE;
1801 #endif
1802         guest_efer &= ~ignore_bits;
1803         guest_efer |= host_efer & ignore_bits;
1804         vmx->guest_msrs[efer_offset].data = guest_efer;
1805         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1806
1807         clear_atomic_switch_msr(vmx, MSR_EFER);
1808
1809         /*
1810          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1811          * On CPUs that support "load IA32_EFER", always switch EFER
1812          * atomically, since it's faster than switching it manually.
1813          */
1814         if (cpu_has_load_ia32_efer ||
1815             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1816                 guest_efer = vmx->vcpu.arch.efer;
1817                 if (!(guest_efer & EFER_LMA))
1818                         guest_efer &= ~EFER_LME;
1819                 if (guest_efer != host_efer)
1820                         add_atomic_switch_msr(vmx, MSR_EFER,
1821                                               guest_efer, host_efer);
1822                 return false;
1823         }
1824
1825         return true;
1826 }
1827
1828 static unsigned long segment_base(u16 selector)
1829 {
1830         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1831         struct desc_struct *d;
1832         unsigned long table_base;
1833         unsigned long v;
1834
1835         if (!(selector & ~3))
1836                 return 0;
1837
1838         table_base = gdt->address;
1839
1840         if (selector & 4) {           /* from ldt */
1841                 u16 ldt_selector = kvm_read_ldt();
1842
1843                 if (!(ldt_selector & ~3))
1844                         return 0;
1845
1846                 table_base = segment_base(ldt_selector);
1847         }
1848         d = (struct desc_struct *)(table_base + (selector & ~7));
1849         v = get_desc_base(d);
1850 #ifdef CONFIG_X86_64
1851        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1852                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1853 #endif
1854         return v;
1855 }
1856
1857 static inline unsigned long kvm_read_tr_base(void)
1858 {
1859         u16 tr;
1860         asm("str %0" : "=g"(tr));
1861         return segment_base(tr);
1862 }
1863
1864 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1865 {
1866         struct vcpu_vmx *vmx = to_vmx(vcpu);
1867         int i;
1868
1869         if (vmx->host_state.loaded)
1870                 return;
1871
1872         vmx->host_state.loaded = 1;
1873         /*
1874          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1875          * allow segment selectors with cpl > 0 or ti == 1.
1876          */
1877         vmx->host_state.ldt_sel = kvm_read_ldt();
1878         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1879         savesegment(fs, vmx->host_state.fs_sel);
1880         if (!(vmx->host_state.fs_sel & 7)) {
1881                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1882                 vmx->host_state.fs_reload_needed = 0;
1883         } else {
1884                 vmcs_write16(HOST_FS_SELECTOR, 0);
1885                 vmx->host_state.fs_reload_needed = 1;
1886         }
1887         savesegment(gs, vmx->host_state.gs_sel);
1888         if (!(vmx->host_state.gs_sel & 7))
1889                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1890         else {
1891                 vmcs_write16(HOST_GS_SELECTOR, 0);
1892                 vmx->host_state.gs_ldt_reload_needed = 1;
1893         }
1894
1895 #ifdef CONFIG_X86_64
1896         savesegment(ds, vmx->host_state.ds_sel);
1897         savesegment(es, vmx->host_state.es_sel);
1898 #endif
1899
1900 #ifdef CONFIG_X86_64
1901         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1902         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1903 #else
1904         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1905         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1906 #endif
1907
1908 #ifdef CONFIG_X86_64
1909         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1910         if (is_long_mode(&vmx->vcpu))
1911                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1912 #endif
1913         if (boot_cpu_has(X86_FEATURE_MPX))
1914                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1915         for (i = 0; i < vmx->save_nmsrs; ++i)
1916                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1917                                    vmx->guest_msrs[i].data,
1918                                    vmx->guest_msrs[i].mask);
1919 }
1920
1921 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1922 {
1923         if (!vmx->host_state.loaded)
1924                 return;
1925
1926         ++vmx->vcpu.stat.host_state_reload;
1927         vmx->host_state.loaded = 0;
1928 #ifdef CONFIG_X86_64
1929         if (is_long_mode(&vmx->vcpu))
1930                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1931 #endif
1932         if (vmx->host_state.gs_ldt_reload_needed) {
1933                 kvm_load_ldt(vmx->host_state.ldt_sel);
1934 #ifdef CONFIG_X86_64
1935                 load_gs_index(vmx->host_state.gs_sel);
1936 #else
1937                 loadsegment(gs, vmx->host_state.gs_sel);
1938 #endif
1939         }
1940         if (vmx->host_state.fs_reload_needed)
1941                 loadsegment(fs, vmx->host_state.fs_sel);
1942 #ifdef CONFIG_X86_64
1943         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1944                 loadsegment(ds, vmx->host_state.ds_sel);
1945                 loadsegment(es, vmx->host_state.es_sel);
1946         }
1947 #endif
1948         reload_tss();
1949 #ifdef CONFIG_X86_64
1950         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1951 #endif
1952         if (vmx->host_state.msr_host_bndcfgs)
1953                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1954         /*
1955          * If the FPU is not active (through the host task or
1956          * the guest vcpu), then restore the cr0.TS bit.
1957          */
1958         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1959                 stts();
1960         load_gdt(this_cpu_ptr(&host_gdt));
1961 }
1962
1963 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1964 {
1965         preempt_disable();
1966         __vmx_load_host_state(vmx);
1967         preempt_enable();
1968 }
1969
1970 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1971 {
1972         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1973         struct pi_desc old, new;
1974         unsigned int dest;
1975
1976         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1977                 !irq_remapping_cap(IRQ_POSTING_CAP))
1978                 return;
1979
1980         do {
1981                 old.control = new.control = pi_desc->control;
1982
1983                 /*
1984                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1985                  * are two possible cases:
1986                  * 1. After running 'pre_block', context switch
1987                  *    happened. For this case, 'sn' was set in
1988                  *    vmx_vcpu_put(), so we need to clear it here.
1989                  * 2. After running 'pre_block', we were blocked,
1990                  *    and woken up by some other guy. For this case,
1991                  *    we don't need to do anything, 'pi_post_block'
1992                  *    will do everything for us. However, we cannot
1993                  *    check whether it is case #1 or case #2 here
1994                  *    (maybe, not needed), so we also clear sn here,
1995                  *    I think it is not a big deal.
1996                  */
1997                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
1998                         if (vcpu->cpu != cpu) {
1999                                 dest = cpu_physical_id(cpu);
2000
2001                                 if (x2apic_enabled())
2002                                         new.ndst = dest;
2003                                 else
2004                                         new.ndst = (dest << 8) & 0xFF00;
2005                         }
2006
2007                         /* set 'NV' to 'notification vector' */
2008                         new.nv = POSTED_INTR_VECTOR;
2009                 }
2010
2011                 /* Allow posting non-urgent interrupts */
2012                 new.sn = 0;
2013         } while (cmpxchg(&pi_desc->control, old.control,
2014                         new.control) != old.control);
2015 }
2016 /*
2017  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2018  * vcpu mutex is already taken.
2019  */
2020 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2021 {
2022         struct vcpu_vmx *vmx = to_vmx(vcpu);
2023         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2024
2025         if (!vmm_exclusive)
2026                 kvm_cpu_vmxon(phys_addr);
2027         else if (vmx->loaded_vmcs->cpu != cpu)
2028                 loaded_vmcs_clear(vmx->loaded_vmcs);
2029
2030         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2031                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2032                 vmcs_load(vmx->loaded_vmcs->vmcs);
2033         }
2034
2035         if (vmx->loaded_vmcs->cpu != cpu) {
2036                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2037                 unsigned long sysenter_esp;
2038
2039                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2040                 local_irq_disable();
2041                 crash_disable_local_vmclear(cpu);
2042
2043                 /*
2044                  * Read loaded_vmcs->cpu should be before fetching
2045                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2046                  * See the comments in __loaded_vmcs_clear().
2047                  */
2048                 smp_rmb();
2049
2050                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2051                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2052                 crash_enable_local_vmclear(cpu);
2053                 local_irq_enable();
2054
2055                 /*
2056                  * Linux uses per-cpu TSS and GDT, so set these when switching
2057                  * processors.
2058                  */
2059                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2060                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2061
2062                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2063                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2064
2065                 /* Setup TSC multiplier */
2066                 if (cpu_has_vmx_tsc_scaling())
2067                         vmcs_write64(TSC_MULTIPLIER,
2068                                      vcpu->arch.tsc_scaling_ratio);
2069
2070                 vmx->loaded_vmcs->cpu = cpu;
2071         }
2072
2073         vmx_vcpu_pi_load(vcpu, cpu);
2074 }
2075
2076 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2077 {
2078         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2079
2080         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2081                 !irq_remapping_cap(IRQ_POSTING_CAP))
2082                 return;
2083
2084         /* Set SN when the vCPU is preempted */
2085         if (vcpu->preempted)
2086                 pi_set_sn(pi_desc);
2087 }
2088
2089 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2090 {
2091         vmx_vcpu_pi_put(vcpu);
2092
2093         __vmx_load_host_state(to_vmx(vcpu));
2094         if (!vmm_exclusive) {
2095                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2096                 vcpu->cpu = -1;
2097                 kvm_cpu_vmxoff();
2098         }
2099 }
2100
2101 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2102 {
2103         ulong cr0;
2104
2105         if (vcpu->fpu_active)
2106                 return;
2107         vcpu->fpu_active = 1;
2108         cr0 = vmcs_readl(GUEST_CR0);
2109         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2110         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2111         vmcs_writel(GUEST_CR0, cr0);
2112         update_exception_bitmap(vcpu);
2113         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2114         if (is_guest_mode(vcpu))
2115                 vcpu->arch.cr0_guest_owned_bits &=
2116                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2117         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2118 }
2119
2120 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2121
2122 /*
2123  * Return the cr0 value that a nested guest would read. This is a combination
2124  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2125  * its hypervisor (cr0_read_shadow).
2126  */
2127 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2128 {
2129         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2130                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2131 }
2132 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2133 {
2134         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2135                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2136 }
2137
2138 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2139 {
2140         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2141          * set this *before* calling this function.
2142          */
2143         vmx_decache_cr0_guest_bits(vcpu);
2144         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2145         update_exception_bitmap(vcpu);
2146         vcpu->arch.cr0_guest_owned_bits = 0;
2147         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2148         if (is_guest_mode(vcpu)) {
2149                 /*
2150                  * L1's specified read shadow might not contain the TS bit,
2151                  * so now that we turned on shadowing of this bit, we need to
2152                  * set this bit of the shadow. Like in nested_vmx_run we need
2153                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2154                  * up-to-date here because we just decached cr0.TS (and we'll
2155                  * only update vmcs12->guest_cr0 on nested exit).
2156                  */
2157                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2158                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2159                         (vcpu->arch.cr0 & X86_CR0_TS);
2160                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2161         } else
2162                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2163 }
2164
2165 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2166 {
2167         unsigned long rflags, save_rflags;
2168
2169         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2170                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2171                 rflags = vmcs_readl(GUEST_RFLAGS);
2172                 if (to_vmx(vcpu)->rmode.vm86_active) {
2173                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2174                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2175                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2176                 }
2177                 to_vmx(vcpu)->rflags = rflags;
2178         }
2179         return to_vmx(vcpu)->rflags;
2180 }
2181
2182 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2183 {
2184         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2185         to_vmx(vcpu)->rflags = rflags;
2186         if (to_vmx(vcpu)->rmode.vm86_active) {
2187                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2188                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2189         }
2190         vmcs_writel(GUEST_RFLAGS, rflags);
2191 }
2192
2193 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2194 {
2195         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2196         int ret = 0;
2197
2198         if (interruptibility & GUEST_INTR_STATE_STI)
2199                 ret |= KVM_X86_SHADOW_INT_STI;
2200         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2201                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2202
2203         return ret;
2204 }
2205
2206 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2207 {
2208         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2209         u32 interruptibility = interruptibility_old;
2210
2211         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2212
2213         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2214                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2215         else if (mask & KVM_X86_SHADOW_INT_STI)
2216                 interruptibility |= GUEST_INTR_STATE_STI;
2217
2218         if ((interruptibility != interruptibility_old))
2219                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2220 }
2221
2222 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2223 {
2224         unsigned long rip;
2225
2226         rip = kvm_rip_read(vcpu);
2227         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2228         kvm_rip_write(vcpu, rip);
2229
2230         /* skipping an emulated instruction also counts */
2231         vmx_set_interrupt_shadow(vcpu, 0);
2232 }
2233
2234 /*
2235  * KVM wants to inject page-faults which it got to the guest. This function
2236  * checks whether in a nested guest, we need to inject them to L1 or L2.
2237  */
2238 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2239 {
2240         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2241
2242         if (!(vmcs12->exception_bitmap & (1u << nr)))
2243                 return 0;
2244
2245         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2246                           vmcs_read32(VM_EXIT_INTR_INFO),
2247                           vmcs_readl(EXIT_QUALIFICATION));
2248         return 1;
2249 }
2250
2251 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2252                                 bool has_error_code, u32 error_code,
2253                                 bool reinject)
2254 {
2255         struct vcpu_vmx *vmx = to_vmx(vcpu);
2256         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2257
2258         if (!reinject && is_guest_mode(vcpu) &&
2259             nested_vmx_check_exception(vcpu, nr))
2260                 return;
2261
2262         if (has_error_code) {
2263                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2264                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2265         }
2266
2267         if (vmx->rmode.vm86_active) {
2268                 int inc_eip = 0;
2269                 if (kvm_exception_is_soft(nr))
2270                         inc_eip = vcpu->arch.event_exit_inst_len;
2271                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2272                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2273                 return;
2274         }
2275
2276         if (kvm_exception_is_soft(nr)) {
2277                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2278                              vmx->vcpu.arch.event_exit_inst_len);
2279                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2280         } else
2281                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2282
2283         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2284 }
2285
2286 static bool vmx_rdtscp_supported(void)
2287 {
2288         return cpu_has_vmx_rdtscp();
2289 }
2290
2291 static bool vmx_invpcid_supported(void)
2292 {
2293         return cpu_has_vmx_invpcid() && enable_ept;
2294 }
2295
2296 /*
2297  * Swap MSR entry in host/guest MSR entry array.
2298  */
2299 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2300 {
2301         struct shared_msr_entry tmp;
2302
2303         tmp = vmx->guest_msrs[to];
2304         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2305         vmx->guest_msrs[from] = tmp;
2306 }
2307
2308 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2309 {
2310         unsigned long *msr_bitmap;
2311
2312         if (is_guest_mode(vcpu))
2313                 msr_bitmap = vmx_msr_bitmap_nested;
2314         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2315                 if (is_long_mode(vcpu))
2316                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2317                 else
2318                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2319         } else {
2320                 if (is_long_mode(vcpu))
2321                         msr_bitmap = vmx_msr_bitmap_longmode;
2322                 else
2323                         msr_bitmap = vmx_msr_bitmap_legacy;
2324         }
2325
2326         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2327 }
2328
2329 /*
2330  * Set up the vmcs to automatically save and restore system
2331  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2332  * mode, as fiddling with msrs is very expensive.
2333  */
2334 static void setup_msrs(struct vcpu_vmx *vmx)
2335 {
2336         int save_nmsrs, index;
2337
2338         save_nmsrs = 0;
2339 #ifdef CONFIG_X86_64
2340         if (is_long_mode(&vmx->vcpu)) {
2341                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2342                 if (index >= 0)
2343                         move_msr_up(vmx, index, save_nmsrs++);
2344                 index = __find_msr_index(vmx, MSR_LSTAR);
2345                 if (index >= 0)
2346                         move_msr_up(vmx, index, save_nmsrs++);
2347                 index = __find_msr_index(vmx, MSR_CSTAR);
2348                 if (index >= 0)
2349                         move_msr_up(vmx, index, save_nmsrs++);
2350                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2351                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2352                         move_msr_up(vmx, index, save_nmsrs++);
2353                 /*
2354                  * MSR_STAR is only needed on long mode guests, and only
2355                  * if efer.sce is enabled.
2356                  */
2357                 index = __find_msr_index(vmx, MSR_STAR);
2358                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2359                         move_msr_up(vmx, index, save_nmsrs++);
2360         }
2361 #endif
2362         index = __find_msr_index(vmx, MSR_EFER);
2363         if (index >= 0 && update_transition_efer(vmx, index))
2364                 move_msr_up(vmx, index, save_nmsrs++);
2365
2366         vmx->save_nmsrs = save_nmsrs;
2367
2368         if (cpu_has_vmx_msr_bitmap())
2369                 vmx_set_msr_bitmap(&vmx->vcpu);
2370 }
2371
2372 /*
2373  * reads and returns guest's timestamp counter "register"
2374  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2375  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2376  */
2377 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2378 {
2379         u64 host_tsc, tsc_offset;
2380
2381         host_tsc = rdtsc();
2382         tsc_offset = vmcs_read64(TSC_OFFSET);
2383         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2384 }
2385
2386 /*
2387  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2388  * counter, even if a nested guest (L2) is currently running.
2389  */
2390 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2391 {
2392         u64 tsc_offset;
2393
2394         tsc_offset = is_guest_mode(vcpu) ?
2395                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2396                 vmcs_read64(TSC_OFFSET);
2397         return host_tsc + tsc_offset;
2398 }
2399
2400 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2401 {
2402         return vmcs_read64(TSC_OFFSET);
2403 }
2404
2405 /*
2406  * writes 'offset' into guest's timestamp counter offset register
2407  */
2408 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2409 {
2410         if (is_guest_mode(vcpu)) {
2411                 /*
2412                  * We're here if L1 chose not to trap WRMSR to TSC. According
2413                  * to the spec, this should set L1's TSC; The offset that L1
2414                  * set for L2 remains unchanged, and still needs to be added
2415                  * to the newly set TSC to get L2's TSC.
2416                  */
2417                 struct vmcs12 *vmcs12;
2418                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2419                 /* recalculate vmcs02.TSC_OFFSET: */
2420                 vmcs12 = get_vmcs12(vcpu);
2421                 vmcs_write64(TSC_OFFSET, offset +
2422                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2423                          vmcs12->tsc_offset : 0));
2424         } else {
2425                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2426                                            vmcs_read64(TSC_OFFSET), offset);
2427                 vmcs_write64(TSC_OFFSET, offset);
2428         }
2429 }
2430
2431 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2432 {
2433         u64 offset = vmcs_read64(TSC_OFFSET);
2434
2435         vmcs_write64(TSC_OFFSET, offset + adjustment);
2436         if (is_guest_mode(vcpu)) {
2437                 /* Even when running L2, the adjustment needs to apply to L1 */
2438                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2439         } else
2440                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2441                                            offset + adjustment);
2442 }
2443
2444 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2445 {
2446         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2447         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2448 }
2449
2450 /*
2451  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2452  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2453  * all guests if the "nested" module option is off, and can also be disabled
2454  * for a single guest by disabling its VMX cpuid bit.
2455  */
2456 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2457 {
2458         return nested && guest_cpuid_has_vmx(vcpu);
2459 }
2460
2461 /*
2462  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2463  * returned for the various VMX controls MSRs when nested VMX is enabled.
2464  * The same values should also be used to verify that vmcs12 control fields are
2465  * valid during nested entry from L1 to L2.
2466  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2467  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2468  * bit in the high half is on if the corresponding bit in the control field
2469  * may be on. See also vmx_control_verify().
2470  */
2471 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2472 {
2473         /*
2474          * Note that as a general rule, the high half of the MSRs (bits in
2475          * the control fields which may be 1) should be initialized by the
2476          * intersection of the underlying hardware's MSR (i.e., features which
2477          * can be supported) and the list of features we want to expose -
2478          * because they are known to be properly supported in our code.
2479          * Also, usually, the low half of the MSRs (bits which must be 1) can
2480          * be set to 0, meaning that L1 may turn off any of these bits. The
2481          * reason is that if one of these bits is necessary, it will appear
2482          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2483          * fields of vmcs01 and vmcs02, will turn these bits off - and
2484          * nested_vmx_exit_handled() will not pass related exits to L1.
2485          * These rules have exceptions below.
2486          */
2487
2488         /* pin-based controls */
2489         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2490                 vmx->nested.nested_vmx_pinbased_ctls_low,
2491                 vmx->nested.nested_vmx_pinbased_ctls_high);
2492         vmx->nested.nested_vmx_pinbased_ctls_low |=
2493                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2494         vmx->nested.nested_vmx_pinbased_ctls_high &=
2495                 PIN_BASED_EXT_INTR_MASK |
2496                 PIN_BASED_NMI_EXITING |
2497                 PIN_BASED_VIRTUAL_NMIS;
2498         vmx->nested.nested_vmx_pinbased_ctls_high |=
2499                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2500                 PIN_BASED_VMX_PREEMPTION_TIMER;
2501         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2502                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2503                         PIN_BASED_POSTED_INTR;
2504
2505         /* exit controls */
2506         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2507                 vmx->nested.nested_vmx_exit_ctls_low,
2508                 vmx->nested.nested_vmx_exit_ctls_high);
2509         vmx->nested.nested_vmx_exit_ctls_low =
2510                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2511
2512         vmx->nested.nested_vmx_exit_ctls_high &=
2513 #ifdef CONFIG_X86_64
2514                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2515 #endif
2516                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2517         vmx->nested.nested_vmx_exit_ctls_high |=
2518                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2519                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2520                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2521
2522         if (vmx_mpx_supported())
2523                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2524
2525         /* We support free control of debug control saving. */
2526         vmx->nested.nested_vmx_true_exit_ctls_low =
2527                 vmx->nested.nested_vmx_exit_ctls_low &
2528                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2529
2530         /* entry controls */
2531         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2532                 vmx->nested.nested_vmx_entry_ctls_low,
2533                 vmx->nested.nested_vmx_entry_ctls_high);
2534         vmx->nested.nested_vmx_entry_ctls_low =
2535                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2536         vmx->nested.nested_vmx_entry_ctls_high &=
2537 #ifdef CONFIG_X86_64
2538                 VM_ENTRY_IA32E_MODE |
2539 #endif
2540                 VM_ENTRY_LOAD_IA32_PAT;
2541         vmx->nested.nested_vmx_entry_ctls_high |=
2542                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2543         if (vmx_mpx_supported())
2544                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2545
2546         /* We support free control of debug control loading. */
2547         vmx->nested.nested_vmx_true_entry_ctls_low =
2548                 vmx->nested.nested_vmx_entry_ctls_low &
2549                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2550
2551         /* cpu-based controls */
2552         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2553                 vmx->nested.nested_vmx_procbased_ctls_low,
2554                 vmx->nested.nested_vmx_procbased_ctls_high);
2555         vmx->nested.nested_vmx_procbased_ctls_low =
2556                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2557         vmx->nested.nested_vmx_procbased_ctls_high &=
2558                 CPU_BASED_VIRTUAL_INTR_PENDING |
2559                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2560                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2561                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2562                 CPU_BASED_CR3_STORE_EXITING |
2563 #ifdef CONFIG_X86_64
2564                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2565 #endif
2566                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2567                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2568                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2569                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2570                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2571         /*
2572          * We can allow some features even when not supported by the
2573          * hardware. For example, L1 can specify an MSR bitmap - and we
2574          * can use it to avoid exits to L1 - even when L0 runs L2
2575          * without MSR bitmaps.
2576          */
2577         vmx->nested.nested_vmx_procbased_ctls_high |=
2578                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2579                 CPU_BASED_USE_MSR_BITMAPS;
2580
2581         /* We support free control of CR3 access interception. */
2582         vmx->nested.nested_vmx_true_procbased_ctls_low =
2583                 vmx->nested.nested_vmx_procbased_ctls_low &
2584                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2585
2586         /* secondary cpu-based controls */
2587         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2588                 vmx->nested.nested_vmx_secondary_ctls_low,
2589                 vmx->nested.nested_vmx_secondary_ctls_high);
2590         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2591         vmx->nested.nested_vmx_secondary_ctls_high &=
2592                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2593                 SECONDARY_EXEC_RDTSCP |
2594                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2595                 SECONDARY_EXEC_ENABLE_VPID |
2596                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2597                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2598                 SECONDARY_EXEC_WBINVD_EXITING |
2599                 SECONDARY_EXEC_XSAVES |
2600                 SECONDARY_EXEC_PCOMMIT;
2601
2602         if (enable_ept) {
2603                 /* nested EPT: emulate EPT also to L1 */
2604                 vmx->nested.nested_vmx_secondary_ctls_high |=
2605                         SECONDARY_EXEC_ENABLE_EPT;
2606                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2607                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2608                          VMX_EPT_INVEPT_BIT;
2609                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2610                 /*
2611                  * For nested guests, we don't do anything specific
2612                  * for single context invalidation. Hence, only advertise
2613                  * support for global context invalidation.
2614                  */
2615                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2616         } else
2617                 vmx->nested.nested_vmx_ept_caps = 0;
2618
2619         if (enable_vpid)
2620                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2621                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2622         else
2623                 vmx->nested.nested_vmx_vpid_caps = 0;
2624
2625         if (enable_unrestricted_guest)
2626                 vmx->nested.nested_vmx_secondary_ctls_high |=
2627                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2628
2629         /* miscellaneous data */
2630         rdmsr(MSR_IA32_VMX_MISC,
2631                 vmx->nested.nested_vmx_misc_low,
2632                 vmx->nested.nested_vmx_misc_high);
2633         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2634         vmx->nested.nested_vmx_misc_low |=
2635                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2636                 VMX_MISC_ACTIVITY_HLT;
2637         vmx->nested.nested_vmx_misc_high = 0;
2638 }
2639
2640 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2641 {
2642         /*
2643          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2644          */
2645         return ((control & high) | low) == control;
2646 }
2647
2648 static inline u64 vmx_control_msr(u32 low, u32 high)
2649 {
2650         return low | ((u64)high << 32);
2651 }
2652
2653 /* Returns 0 on success, non-0 otherwise. */
2654 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2655 {
2656         struct vcpu_vmx *vmx = to_vmx(vcpu);
2657
2658         switch (msr_index) {
2659         case MSR_IA32_VMX_BASIC:
2660                 /*
2661                  * This MSR reports some information about VMX support. We
2662                  * should return information about the VMX we emulate for the
2663                  * guest, and the VMCS structure we give it - not about the
2664                  * VMX support of the underlying hardware.
2665                  */
2666                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2667                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2668                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2669                 break;
2670         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2671         case MSR_IA32_VMX_PINBASED_CTLS:
2672                 *pdata = vmx_control_msr(
2673                         vmx->nested.nested_vmx_pinbased_ctls_low,
2674                         vmx->nested.nested_vmx_pinbased_ctls_high);
2675                 break;
2676         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2677                 *pdata = vmx_control_msr(
2678                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2679                         vmx->nested.nested_vmx_procbased_ctls_high);
2680                 break;
2681         case MSR_IA32_VMX_PROCBASED_CTLS:
2682                 *pdata = vmx_control_msr(
2683                         vmx->nested.nested_vmx_procbased_ctls_low,
2684                         vmx->nested.nested_vmx_procbased_ctls_high);
2685                 break;
2686         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2687                 *pdata = vmx_control_msr(
2688                         vmx->nested.nested_vmx_true_exit_ctls_low,
2689                         vmx->nested.nested_vmx_exit_ctls_high);
2690                 break;
2691         case MSR_IA32_VMX_EXIT_CTLS:
2692                 *pdata = vmx_control_msr(
2693                         vmx->nested.nested_vmx_exit_ctls_low,
2694                         vmx->nested.nested_vmx_exit_ctls_high);
2695                 break;
2696         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2697                 *pdata = vmx_control_msr(
2698                         vmx->nested.nested_vmx_true_entry_ctls_low,
2699                         vmx->nested.nested_vmx_entry_ctls_high);
2700                 break;
2701         case MSR_IA32_VMX_ENTRY_CTLS:
2702                 *pdata = vmx_control_msr(
2703                         vmx->nested.nested_vmx_entry_ctls_low,
2704                         vmx->nested.nested_vmx_entry_ctls_high);
2705                 break;
2706         case MSR_IA32_VMX_MISC:
2707                 *pdata = vmx_control_msr(
2708                         vmx->nested.nested_vmx_misc_low,
2709                         vmx->nested.nested_vmx_misc_high);
2710                 break;
2711         /*
2712          * These MSRs specify bits which the guest must keep fixed (on or off)
2713          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2714          * We picked the standard core2 setting.
2715          */
2716 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2717 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2718         case MSR_IA32_VMX_CR0_FIXED0:
2719                 *pdata = VMXON_CR0_ALWAYSON;
2720                 break;
2721         case MSR_IA32_VMX_CR0_FIXED1:
2722                 *pdata = -1ULL;
2723                 break;
2724         case MSR_IA32_VMX_CR4_FIXED0:
2725                 *pdata = VMXON_CR4_ALWAYSON;
2726                 break;
2727         case MSR_IA32_VMX_CR4_FIXED1:
2728                 *pdata = -1ULL;
2729                 break;
2730         case MSR_IA32_VMX_VMCS_ENUM:
2731                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2732                 break;
2733         case MSR_IA32_VMX_PROCBASED_CTLS2:
2734                 *pdata = vmx_control_msr(
2735                         vmx->nested.nested_vmx_secondary_ctls_low,
2736                         vmx->nested.nested_vmx_secondary_ctls_high);
2737                 break;
2738         case MSR_IA32_VMX_EPT_VPID_CAP:
2739                 /* Currently, no nested vpid support */
2740                 *pdata = vmx->nested.nested_vmx_ept_caps |
2741                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2742                 break;
2743         default:
2744                 return 1;
2745         }
2746
2747         return 0;
2748 }
2749
2750 /*
2751  * Reads an msr value (of 'msr_index') into 'pdata'.
2752  * Returns 0 on success, non-0 otherwise.
2753  * Assumes vcpu_load() was already called.
2754  */
2755 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2756 {
2757         struct shared_msr_entry *msr;
2758
2759         switch (msr_info->index) {
2760 #ifdef CONFIG_X86_64
2761         case MSR_FS_BASE:
2762                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2763                 break;
2764         case MSR_GS_BASE:
2765                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2766                 break;
2767         case MSR_KERNEL_GS_BASE:
2768                 vmx_load_host_state(to_vmx(vcpu));
2769                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2770                 break;
2771 #endif
2772         case MSR_EFER:
2773                 return kvm_get_msr_common(vcpu, msr_info);
2774         case MSR_IA32_TSC:
2775                 msr_info->data = guest_read_tsc(vcpu);
2776                 break;
2777         case MSR_IA32_SYSENTER_CS:
2778                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2779                 break;
2780         case MSR_IA32_SYSENTER_EIP:
2781                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2782                 break;
2783         case MSR_IA32_SYSENTER_ESP:
2784                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2785                 break;
2786         case MSR_IA32_BNDCFGS:
2787                 if (!vmx_mpx_supported())
2788                         return 1;
2789                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2790                 break;
2791         case MSR_IA32_FEATURE_CONTROL:
2792                 if (!nested_vmx_allowed(vcpu))
2793                         return 1;
2794                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2795                 break;
2796         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2797                 if (!nested_vmx_allowed(vcpu))
2798                         return 1;
2799                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2800         case MSR_IA32_XSS:
2801                 if (!vmx_xsaves_supported())
2802                         return 1;
2803                 msr_info->data = vcpu->arch.ia32_xss;
2804                 break;
2805         case MSR_TSC_AUX:
2806                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2807                         return 1;
2808                 /* Otherwise falls through */
2809         default:
2810                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2811                 if (msr) {
2812                         msr_info->data = msr->data;
2813                         break;
2814                 }
2815                 return kvm_get_msr_common(vcpu, msr_info);
2816         }
2817
2818         return 0;
2819 }
2820
2821 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2822
2823 /*
2824  * Writes msr value into into the appropriate "register".
2825  * Returns 0 on success, non-0 otherwise.
2826  * Assumes vcpu_load() was already called.
2827  */
2828 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2829 {
2830         struct vcpu_vmx *vmx = to_vmx(vcpu);
2831         struct shared_msr_entry *msr;
2832         int ret = 0;
2833         u32 msr_index = msr_info->index;
2834         u64 data = msr_info->data;
2835
2836         switch (msr_index) {
2837         case MSR_EFER:
2838                 ret = kvm_set_msr_common(vcpu, msr_info);
2839                 break;
2840 #ifdef CONFIG_X86_64
2841         case MSR_FS_BASE:
2842                 vmx_segment_cache_clear(vmx);
2843                 vmcs_writel(GUEST_FS_BASE, data);
2844                 break;
2845         case MSR_GS_BASE:
2846                 vmx_segment_cache_clear(vmx);
2847                 vmcs_writel(GUEST_GS_BASE, data);
2848                 break;
2849         case MSR_KERNEL_GS_BASE:
2850                 vmx_load_host_state(vmx);
2851                 vmx->msr_guest_kernel_gs_base = data;
2852                 break;
2853 #endif
2854         case MSR_IA32_SYSENTER_CS:
2855                 vmcs_write32(GUEST_SYSENTER_CS, data);
2856                 break;
2857         case MSR_IA32_SYSENTER_EIP:
2858                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2859                 break;
2860         case MSR_IA32_SYSENTER_ESP:
2861                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2862                 break;
2863         case MSR_IA32_BNDCFGS:
2864                 if (!vmx_mpx_supported())
2865                         return 1;
2866                 vmcs_write64(GUEST_BNDCFGS, data);
2867                 break;
2868         case MSR_IA32_TSC:
2869                 kvm_write_tsc(vcpu, msr_info);
2870                 break;
2871         case MSR_IA32_CR_PAT:
2872                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2873                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2874                                 return 1;
2875                         vmcs_write64(GUEST_IA32_PAT, data);
2876                         vcpu->arch.pat = data;
2877                         break;
2878                 }
2879                 ret = kvm_set_msr_common(vcpu, msr_info);
2880                 break;
2881         case MSR_IA32_TSC_ADJUST:
2882                 ret = kvm_set_msr_common(vcpu, msr_info);
2883                 break;
2884         case MSR_IA32_FEATURE_CONTROL:
2885                 if (!nested_vmx_allowed(vcpu) ||
2886                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2887                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2888                         return 1;
2889                 vmx->nested.msr_ia32_feature_control = data;
2890                 if (msr_info->host_initiated && data == 0)
2891                         vmx_leave_nested(vcpu);
2892                 break;
2893         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2894                 return 1; /* they are read-only */
2895         case MSR_IA32_XSS:
2896                 if (!vmx_xsaves_supported())
2897                         return 1;
2898                 /*
2899                  * The only supported bit as of Skylake is bit 8, but
2900                  * it is not supported on KVM.
2901                  */
2902                 if (data != 0)
2903                         return 1;
2904                 vcpu->arch.ia32_xss = data;
2905                 if (vcpu->arch.ia32_xss != host_xss)
2906                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2907                                 vcpu->arch.ia32_xss, host_xss);
2908                 else
2909                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2910                 break;
2911         case MSR_TSC_AUX:
2912                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2913                         return 1;
2914                 /* Check reserved bit, higher 32 bits should be zero */
2915                 if ((data >> 32) != 0)
2916                         return 1;
2917                 /* Otherwise falls through */
2918         default:
2919                 msr = find_msr_entry(vmx, msr_index);
2920                 if (msr) {
2921                         u64 old_msr_data = msr->data;
2922                         msr->data = data;
2923                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2924                                 preempt_disable();
2925                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2926                                                          msr->mask);
2927                                 preempt_enable();
2928                                 if (ret)
2929                                         msr->data = old_msr_data;
2930                         }
2931                         break;
2932                 }
2933                 ret = kvm_set_msr_common(vcpu, msr_info);
2934         }
2935
2936         return ret;
2937 }
2938
2939 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2940 {
2941         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2942         switch (reg) {
2943         case VCPU_REGS_RSP:
2944                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2945                 break;
2946         case VCPU_REGS_RIP:
2947                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2948                 break;
2949         case VCPU_EXREG_PDPTR:
2950                 if (enable_ept)
2951                         ept_save_pdptrs(vcpu);
2952                 break;
2953         default:
2954                 break;
2955         }
2956 }
2957
2958 static __init int cpu_has_kvm_support(void)
2959 {
2960         return cpu_has_vmx();
2961 }
2962
2963 static __init int vmx_disabled_by_bios(void)
2964 {
2965         u64 msr;
2966
2967         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2968         if (msr & FEATURE_CONTROL_LOCKED) {
2969                 /* launched w/ TXT and VMX disabled */
2970                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2971                         && tboot_enabled())
2972                         return 1;
2973                 /* launched w/o TXT and VMX only enabled w/ TXT */
2974                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2975                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2976                         && !tboot_enabled()) {
2977                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2978                                 "activate TXT before enabling KVM\n");
2979                         return 1;
2980                 }
2981                 /* launched w/o TXT and VMX disabled */
2982                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2983                         && !tboot_enabled())
2984                         return 1;
2985         }
2986
2987         return 0;
2988 }
2989
2990 static void kvm_cpu_vmxon(u64 addr)
2991 {
2992         asm volatile (ASM_VMX_VMXON_RAX
2993                         : : "a"(&addr), "m"(addr)
2994                         : "memory", "cc");
2995 }
2996
2997 static int hardware_enable(void)
2998 {
2999         int cpu = raw_smp_processor_id();
3000         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3001         u64 old, test_bits;
3002
3003         if (cr4_read_shadow() & X86_CR4_VMXE)
3004                 return -EBUSY;
3005
3006         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3007         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3008         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3009
3010         /*
3011          * Now we can enable the vmclear operation in kdump
3012          * since the loaded_vmcss_on_cpu list on this cpu
3013          * has been initialized.
3014          *
3015          * Though the cpu is not in VMX operation now, there
3016          * is no problem to enable the vmclear operation
3017          * for the loaded_vmcss_on_cpu list is empty!
3018          */
3019         crash_enable_local_vmclear(cpu);
3020
3021         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3022
3023         test_bits = FEATURE_CONTROL_LOCKED;
3024         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3025         if (tboot_enabled())
3026                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3027
3028         if ((old & test_bits) != test_bits) {
3029                 /* enable and lock */
3030                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3031         }
3032         cr4_set_bits(X86_CR4_VMXE);
3033
3034         if (vmm_exclusive) {
3035                 kvm_cpu_vmxon(phys_addr);
3036                 ept_sync_global();
3037         }
3038
3039         native_store_gdt(this_cpu_ptr(&host_gdt));
3040
3041         return 0;
3042 }
3043
3044 static void vmclear_local_loaded_vmcss(void)
3045 {
3046         int cpu = raw_smp_processor_id();
3047         struct loaded_vmcs *v, *n;
3048
3049         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3050                                  loaded_vmcss_on_cpu_link)
3051                 __loaded_vmcs_clear(v);
3052 }
3053
3054
3055 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3056  * tricks.
3057  */
3058 static void kvm_cpu_vmxoff(void)
3059 {
3060         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3061 }
3062
3063 static void hardware_disable(void)
3064 {
3065         if (vmm_exclusive) {
3066                 vmclear_local_loaded_vmcss();
3067                 kvm_cpu_vmxoff();
3068         }
3069         cr4_clear_bits(X86_CR4_VMXE);
3070 }
3071
3072 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3073                                       u32 msr, u32 *result)
3074 {
3075         u32 vmx_msr_low, vmx_msr_high;
3076         u32 ctl = ctl_min | ctl_opt;
3077
3078         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3079
3080         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3081         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3082
3083         /* Ensure minimum (required) set of control bits are supported. */
3084         if (ctl_min & ~ctl)
3085                 return -EIO;
3086
3087         *result = ctl;
3088         return 0;
3089 }
3090
3091 static __init bool allow_1_setting(u32 msr, u32 ctl)
3092 {
3093         u32 vmx_msr_low, vmx_msr_high;
3094
3095         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3096         return vmx_msr_high & ctl;
3097 }
3098
3099 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3100 {
3101         u32 vmx_msr_low, vmx_msr_high;
3102         u32 min, opt, min2, opt2;
3103         u32 _pin_based_exec_control = 0;
3104         u32 _cpu_based_exec_control = 0;
3105         u32 _cpu_based_2nd_exec_control = 0;
3106         u32 _vmexit_control = 0;
3107         u32 _vmentry_control = 0;
3108
3109         min = CPU_BASED_HLT_EXITING |
3110 #ifdef CONFIG_X86_64
3111               CPU_BASED_CR8_LOAD_EXITING |
3112               CPU_BASED_CR8_STORE_EXITING |
3113 #endif
3114               CPU_BASED_CR3_LOAD_EXITING |
3115               CPU_BASED_CR3_STORE_EXITING |
3116               CPU_BASED_USE_IO_BITMAPS |
3117               CPU_BASED_MOV_DR_EXITING |
3118               CPU_BASED_USE_TSC_OFFSETING |
3119               CPU_BASED_MWAIT_EXITING |
3120               CPU_BASED_MONITOR_EXITING |
3121               CPU_BASED_INVLPG_EXITING |
3122               CPU_BASED_RDPMC_EXITING;
3123
3124         opt = CPU_BASED_TPR_SHADOW |
3125               CPU_BASED_USE_MSR_BITMAPS |
3126               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3127         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3128                                 &_cpu_based_exec_control) < 0)
3129                 return -EIO;
3130 #ifdef CONFIG_X86_64
3131         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3132                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3133                                            ~CPU_BASED_CR8_STORE_EXITING;
3134 #endif
3135         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3136                 min2 = 0;
3137                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3138                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3139                         SECONDARY_EXEC_WBINVD_EXITING |
3140                         SECONDARY_EXEC_ENABLE_VPID |
3141                         SECONDARY_EXEC_ENABLE_EPT |
3142                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3143                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3144                         SECONDARY_EXEC_RDTSCP |
3145                         SECONDARY_EXEC_ENABLE_INVPCID |
3146                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3147                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3148                         SECONDARY_EXEC_SHADOW_VMCS |
3149                         SECONDARY_EXEC_XSAVES |
3150                         SECONDARY_EXEC_ENABLE_PML |
3151                         SECONDARY_EXEC_PCOMMIT |
3152                         SECONDARY_EXEC_TSC_SCALING;
3153                 if (adjust_vmx_controls(min2, opt2,
3154                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3155                                         &_cpu_based_2nd_exec_control) < 0)
3156                         return -EIO;
3157         }
3158 #ifndef CONFIG_X86_64
3159         if (!(_cpu_based_2nd_exec_control &
3160                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3161                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3162 #endif
3163
3164         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3165                 _cpu_based_2nd_exec_control &= ~(
3166                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3167                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3168                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3169
3170         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3171                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3172                    enabled */
3173                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3174                                              CPU_BASED_CR3_STORE_EXITING |
3175                                              CPU_BASED_INVLPG_EXITING);
3176                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3177                       vmx_capability.ept, vmx_capability.vpid);
3178         }
3179
3180         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3181 #ifdef CONFIG_X86_64
3182         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3183 #endif
3184         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3185                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3186         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3187                                 &_vmexit_control) < 0)
3188                 return -EIO;
3189
3190         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3191         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3192         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3193                                 &_pin_based_exec_control) < 0)
3194                 return -EIO;
3195
3196         if (!(_cpu_based_2nd_exec_control &
3197                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3198                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3199                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3200
3201         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3202         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3203         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3204                                 &_vmentry_control) < 0)
3205                 return -EIO;
3206
3207         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3208
3209         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3210         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3211                 return -EIO;
3212
3213 #ifdef CONFIG_X86_64
3214         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3215         if (vmx_msr_high & (1u<<16))
3216                 return -EIO;
3217 #endif
3218
3219         /* Require Write-Back (WB) memory type for VMCS accesses. */
3220         if (((vmx_msr_high >> 18) & 15) != 6)
3221                 return -EIO;
3222
3223         vmcs_conf->size = vmx_msr_high & 0x1fff;
3224         vmcs_conf->order = get_order(vmcs_config.size);
3225         vmcs_conf->revision_id = vmx_msr_low;
3226
3227         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3228         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3229         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3230         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3231         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3232
3233         cpu_has_load_ia32_efer =
3234                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3235                                 VM_ENTRY_LOAD_IA32_EFER)
3236                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3237                                    VM_EXIT_LOAD_IA32_EFER);
3238
3239         cpu_has_load_perf_global_ctrl =
3240                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3241                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3242                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3243                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3244
3245         /*
3246          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3247          * but due to arrata below it can't be used. Workaround is to use
3248          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3249          *
3250          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3251          *
3252          * AAK155             (model 26)
3253          * AAP115             (model 30)
3254          * AAT100             (model 37)
3255          * BC86,AAY89,BD102   (model 44)
3256          * BA97               (model 46)
3257          *
3258          */
3259         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3260                 switch (boot_cpu_data.x86_model) {
3261                 case 26:
3262                 case 30:
3263                 case 37:
3264                 case 44:
3265                 case 46:
3266                         cpu_has_load_perf_global_ctrl = false;
3267                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3268                                         "does not work properly. Using workaround\n");
3269                         break;
3270                 default:
3271                         break;
3272                 }
3273         }
3274
3275         if (cpu_has_xsaves)
3276                 rdmsrl(MSR_IA32_XSS, host_xss);
3277
3278         return 0;
3279 }
3280
3281 static struct vmcs *alloc_vmcs_cpu(int cpu)
3282 {
3283         int node = cpu_to_node(cpu);
3284         struct page *pages;
3285         struct vmcs *vmcs;
3286
3287         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3288         if (!pages)
3289                 return NULL;
3290         vmcs = page_address(pages);
3291         memset(vmcs, 0, vmcs_config.size);
3292         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3293         return vmcs;
3294 }
3295
3296 static struct vmcs *alloc_vmcs(void)
3297 {
3298         return alloc_vmcs_cpu(raw_smp_processor_id());
3299 }
3300
3301 static void free_vmcs(struct vmcs *vmcs)
3302 {
3303         free_pages((unsigned long)vmcs, vmcs_config.order);
3304 }
3305
3306 /*
3307  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3308  */
3309 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3310 {
3311         if (!loaded_vmcs->vmcs)
3312                 return;
3313         loaded_vmcs_clear(loaded_vmcs);
3314         free_vmcs(loaded_vmcs->vmcs);
3315         loaded_vmcs->vmcs = NULL;
3316 }
3317
3318 static void free_kvm_area(void)
3319 {
3320         int cpu;
3321
3322         for_each_possible_cpu(cpu) {
3323                 free_vmcs(per_cpu(vmxarea, cpu));
3324                 per_cpu(vmxarea, cpu) = NULL;
3325         }
3326 }
3327
3328 static void init_vmcs_shadow_fields(void)
3329 {
3330         int i, j;
3331
3332         /* No checks for read only fields yet */
3333
3334         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3335                 switch (shadow_read_write_fields[i]) {
3336                 case GUEST_BNDCFGS:
3337                         if (!vmx_mpx_supported())
3338                                 continue;
3339                         break;
3340                 default:
3341                         break;
3342                 }
3343
3344                 if (j < i)
3345                         shadow_read_write_fields[j] =
3346                                 shadow_read_write_fields[i];
3347                 j++;
3348         }
3349         max_shadow_read_write_fields = j;
3350
3351         /* shadowed fields guest access without vmexit */
3352         for (i = 0; i < max_shadow_read_write_fields; i++) {
3353                 clear_bit(shadow_read_write_fields[i],
3354                           vmx_vmwrite_bitmap);
3355                 clear_bit(shadow_read_write_fields[i],
3356                           vmx_vmread_bitmap);
3357         }
3358         for (i = 0; i < max_shadow_read_only_fields; i++)
3359                 clear_bit(shadow_read_only_fields[i],
3360                           vmx_vmread_bitmap);
3361 }
3362
3363 static __init int alloc_kvm_area(void)
3364 {
3365         int cpu;
3366
3367         for_each_possible_cpu(cpu) {
3368                 struct vmcs *vmcs;
3369
3370                 vmcs = alloc_vmcs_cpu(cpu);
3371                 if (!vmcs) {
3372                         free_kvm_area();
3373                         return -ENOMEM;
3374                 }
3375
3376                 per_cpu(vmxarea, cpu) = vmcs;
3377         }
3378         return 0;
3379 }
3380
3381 static bool emulation_required(struct kvm_vcpu *vcpu)
3382 {
3383         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3384 }
3385
3386 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3387                 struct kvm_segment *save)
3388 {
3389         if (!emulate_invalid_guest_state) {
3390                 /*
3391                  * CS and SS RPL should be equal during guest entry according
3392                  * to VMX spec, but in reality it is not always so. Since vcpu
3393                  * is in the middle of the transition from real mode to
3394                  * protected mode it is safe to assume that RPL 0 is a good
3395                  * default value.
3396                  */
3397                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3398                         save->selector &= ~SEGMENT_RPL_MASK;
3399                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3400                 save->s = 1;
3401         }
3402         vmx_set_segment(vcpu, save, seg);
3403 }
3404
3405 static void enter_pmode(struct kvm_vcpu *vcpu)
3406 {
3407         unsigned long flags;
3408         struct vcpu_vmx *vmx = to_vmx(vcpu);
3409
3410         /*
3411          * Update real mode segment cache. It may be not up-to-date if sement
3412          * register was written while vcpu was in a guest mode.
3413          */
3414         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3415         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3416         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3417         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3418         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3419         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3420
3421         vmx->rmode.vm86_active = 0;
3422
3423         vmx_segment_cache_clear(vmx);
3424
3425         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3426
3427         flags = vmcs_readl(GUEST_RFLAGS);
3428         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3429         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3430         vmcs_writel(GUEST_RFLAGS, flags);
3431
3432         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3433                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3434
3435         update_exception_bitmap(vcpu);
3436
3437         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3438         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3439         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3440         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3441         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3442         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3443 }
3444
3445 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3446 {
3447         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3448         struct kvm_segment var = *save;
3449
3450         var.dpl = 0x3;
3451         if (seg == VCPU_SREG_CS)
3452                 var.type = 0x3;
3453
3454         if (!emulate_invalid_guest_state) {
3455                 var.selector = var.base >> 4;
3456                 var.base = var.base & 0xffff0;
3457                 var.limit = 0xffff;
3458                 var.g = 0;
3459                 var.db = 0;
3460                 var.present = 1;
3461                 var.s = 1;
3462                 var.l = 0;
3463                 var.unusable = 0;
3464                 var.type = 0x3;
3465                 var.avl = 0;
3466                 if (save->base & 0xf)
3467                         printk_once(KERN_WARNING "kvm: segment base is not "
3468                                         "paragraph aligned when entering "
3469                                         "protected mode (seg=%d)", seg);
3470         }
3471
3472         vmcs_write16(sf->selector, var.selector);
3473         vmcs_write32(sf->base, var.base);
3474         vmcs_write32(sf->limit, var.limit);
3475         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3476 }
3477
3478 static void enter_rmode(struct kvm_vcpu *vcpu)
3479 {
3480         unsigned long flags;
3481         struct vcpu_vmx *vmx = to_vmx(vcpu);
3482
3483         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3484         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3485         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3486         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3487         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3488         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3489         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3490
3491         vmx->rmode.vm86_active = 1;
3492
3493         /*
3494          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3495          * vcpu. Warn the user that an update is overdue.
3496          */
3497         if (!vcpu->kvm->arch.tss_addr)
3498                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3499                              "called before entering vcpu\n");
3500
3501         vmx_segment_cache_clear(vmx);
3502
3503         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3504         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3505         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3506
3507         flags = vmcs_readl(GUEST_RFLAGS);
3508         vmx->rmode.save_rflags = flags;
3509
3510         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3511
3512         vmcs_writel(GUEST_RFLAGS, flags);
3513         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3514         update_exception_bitmap(vcpu);
3515
3516         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3517         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3518         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3519         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3520         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3521         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3522
3523         kvm_mmu_reset_context(vcpu);
3524 }
3525
3526 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3527 {
3528         struct vcpu_vmx *vmx = to_vmx(vcpu);
3529         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3530
3531         if (!msr)
3532                 return;
3533
3534         /*
3535          * Force kernel_gs_base reloading before EFER changes, as control
3536          * of this msr depends on is_long_mode().
3537          */
3538         vmx_load_host_state(to_vmx(vcpu));
3539         vcpu->arch.efer = efer;
3540         if (efer & EFER_LMA) {
3541                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3542                 msr->data = efer;
3543         } else {
3544                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3545
3546                 msr->data = efer & ~EFER_LME;
3547         }
3548         setup_msrs(vmx);
3549 }
3550
3551 #ifdef CONFIG_X86_64
3552
3553 static void enter_lmode(struct kvm_vcpu *vcpu)
3554 {
3555         u32 guest_tr_ar;
3556
3557         vmx_segment_cache_clear(to_vmx(vcpu));
3558
3559         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3560         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3561                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3562                                      __func__);
3563                 vmcs_write32(GUEST_TR_AR_BYTES,
3564                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3565                              | VMX_AR_TYPE_BUSY_64_TSS);
3566         }
3567         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3568 }
3569
3570 static void exit_lmode(struct kvm_vcpu *vcpu)
3571 {
3572         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3573         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3574 }
3575
3576 #endif
3577
3578 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3579 {
3580         vpid_sync_context(vpid);
3581         if (enable_ept) {
3582                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3583                         return;
3584                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3585         }
3586 }
3587
3588 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3589 {
3590         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3591 }
3592
3593 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3594 {
3595         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3596
3597         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3598         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3599 }
3600
3601 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3602 {
3603         if (enable_ept && is_paging(vcpu))
3604                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3605         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3606 }
3607
3608 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3609 {
3610         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3611
3612         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3613         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3614 }
3615
3616 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3617 {
3618         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3619
3620         if (!test_bit(VCPU_EXREG_PDPTR,
3621                       (unsigned long *)&vcpu->arch.regs_dirty))
3622                 return;
3623
3624         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3625                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3626                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3627                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3628                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3629         }
3630 }
3631
3632 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3633 {
3634         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3635
3636         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3637                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3638                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3639                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3640                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3641         }
3642
3643         __set_bit(VCPU_EXREG_PDPTR,
3644                   (unsigned long *)&vcpu->arch.regs_avail);
3645         __set_bit(VCPU_EXREG_PDPTR,
3646                   (unsigned long *)&vcpu->arch.regs_dirty);
3647 }
3648
3649 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3650
3651 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3652                                         unsigned long cr0,
3653                                         struct kvm_vcpu *vcpu)
3654 {
3655         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3656                 vmx_decache_cr3(vcpu);
3657         if (!(cr0 & X86_CR0_PG)) {
3658                 /* From paging/starting to nonpaging */
3659                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3660                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3661                              (CPU_BASED_CR3_LOAD_EXITING |
3662                               CPU_BASED_CR3_STORE_EXITING));
3663                 vcpu->arch.cr0 = cr0;
3664                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3665         } else if (!is_paging(vcpu)) {
3666                 /* From nonpaging to paging */
3667                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3668                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3669                              ~(CPU_BASED_CR3_LOAD_EXITING |
3670                                CPU_BASED_CR3_STORE_EXITING));
3671                 vcpu->arch.cr0 = cr0;
3672                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3673         }
3674
3675         if (!(cr0 & X86_CR0_WP))
3676                 *hw_cr0 &= ~X86_CR0_WP;
3677 }
3678
3679 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3680 {
3681         struct vcpu_vmx *vmx = to_vmx(vcpu);
3682         unsigned long hw_cr0;
3683
3684         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3685         if (enable_unrestricted_guest)
3686                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3687         else {
3688                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3689
3690                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3691                         enter_pmode(vcpu);
3692
3693                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3694                         enter_rmode(vcpu);
3695         }
3696
3697 #ifdef CONFIG_X86_64
3698         if (vcpu->arch.efer & EFER_LME) {
3699                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3700                         enter_lmode(vcpu);
3701                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3702                         exit_lmode(vcpu);
3703         }
3704 #endif
3705
3706         if (enable_ept)
3707                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3708
3709         if (!vcpu->fpu_active)
3710                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3711
3712         vmcs_writel(CR0_READ_SHADOW, cr0);
3713         vmcs_writel(GUEST_CR0, hw_cr0);
3714         vcpu->arch.cr0 = cr0;
3715
3716         /* depends on vcpu->arch.cr0 to be set to a new value */
3717         vmx->emulation_required = emulation_required(vcpu);
3718 }
3719
3720 static u64 construct_eptp(unsigned long root_hpa)
3721 {
3722         u64 eptp;
3723
3724         /* TODO write the value reading from MSR */
3725         eptp = VMX_EPT_DEFAULT_MT |
3726                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3727         if (enable_ept_ad_bits)
3728                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3729         eptp |= (root_hpa & PAGE_MASK);
3730
3731         return eptp;
3732 }
3733
3734 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3735 {
3736         unsigned long guest_cr3;
3737         u64 eptp;
3738
3739         guest_cr3 = cr3;
3740         if (enable_ept) {
3741                 eptp = construct_eptp(cr3);
3742                 vmcs_write64(EPT_POINTER, eptp);
3743                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3744                         guest_cr3 = kvm_read_cr3(vcpu);
3745                 else
3746                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3747                 ept_load_pdptrs(vcpu);
3748         }
3749
3750         vmx_flush_tlb(vcpu);
3751         vmcs_writel(GUEST_CR3, guest_cr3);
3752 }
3753
3754 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3755 {
3756         /*
3757          * Pass through host's Machine Check Enable value to hw_cr4, which
3758          * is in force while we are in guest mode.  Do not let guests control
3759          * this bit, even if host CR4.MCE == 0.
3760          */
3761         unsigned long hw_cr4 =
3762                 (cr4_read_shadow() & X86_CR4_MCE) |
3763                 (cr4 & ~X86_CR4_MCE) |
3764                 (to_vmx(vcpu)->rmode.vm86_active ?
3765                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3766
3767         if (cr4 & X86_CR4_VMXE) {
3768                 /*
3769                  * To use VMXON (and later other VMX instructions), a guest
3770                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3771                  * So basically the check on whether to allow nested VMX
3772                  * is here.
3773                  */
3774                 if (!nested_vmx_allowed(vcpu))
3775                         return 1;
3776         }
3777         if (to_vmx(vcpu)->nested.vmxon &&
3778             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3779                 return 1;
3780
3781         vcpu->arch.cr4 = cr4;
3782         if (enable_ept) {
3783                 if (!is_paging(vcpu)) {
3784                         hw_cr4 &= ~X86_CR4_PAE;
3785                         hw_cr4 |= X86_CR4_PSE;
3786                 } else if (!(cr4 & X86_CR4_PAE)) {
3787                         hw_cr4 &= ~X86_CR4_PAE;
3788                 }
3789         }
3790
3791         if (!enable_unrestricted_guest && !is_paging(vcpu))
3792                 /*
3793                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3794                  * hardware.  However KVM always uses paging mode without
3795                  * unrestricted guest.
3796                  * To emulate this behavior, SMEP/SMAP needs to be manually
3797                  * disabled when guest switches to non-paging mode.
3798                  */
3799                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3800
3801         vmcs_writel(CR4_READ_SHADOW, cr4);
3802         vmcs_writel(GUEST_CR4, hw_cr4);
3803         return 0;
3804 }
3805
3806 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3807                             struct kvm_segment *var, int seg)
3808 {
3809         struct vcpu_vmx *vmx = to_vmx(vcpu);
3810         u32 ar;
3811
3812         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3813                 *var = vmx->rmode.segs[seg];
3814                 if (seg == VCPU_SREG_TR
3815                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3816                         return;
3817                 var->base = vmx_read_guest_seg_base(vmx, seg);
3818                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3819                 return;
3820         }
3821         var->base = vmx_read_guest_seg_base(vmx, seg);
3822         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3823         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3824         ar = vmx_read_guest_seg_ar(vmx, seg);
3825         var->unusable = (ar >> 16) & 1;
3826         var->type = ar & 15;
3827         var->s = (ar >> 4) & 1;
3828         var->dpl = (ar >> 5) & 3;
3829         /*
3830          * Some userspaces do not preserve unusable property. Since usable
3831          * segment has to be present according to VMX spec we can use present
3832          * property to amend userspace bug by making unusable segment always
3833          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3834          * segment as unusable.
3835          */
3836         var->present = !var->unusable;
3837         var->avl = (ar >> 12) & 1;
3838         var->l = (ar >> 13) & 1;
3839         var->db = (ar >> 14) & 1;
3840         var->g = (ar >> 15) & 1;
3841 }
3842
3843 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3844 {
3845         struct kvm_segment s;
3846
3847         if (to_vmx(vcpu)->rmode.vm86_active) {
3848                 vmx_get_segment(vcpu, &s, seg);
3849                 return s.base;
3850         }
3851         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3852 }
3853
3854 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3855 {
3856         struct vcpu_vmx *vmx = to_vmx(vcpu);
3857
3858         if (unlikely(vmx->rmode.vm86_active))
3859                 return 0;
3860         else {
3861                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3862                 return VMX_AR_DPL(ar);
3863         }
3864 }
3865
3866 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3867 {
3868         u32 ar;
3869
3870         if (var->unusable || !var->present)
3871                 ar = 1 << 16;
3872         else {
3873                 ar = var->type & 15;
3874                 ar |= (var->s & 1) << 4;
3875                 ar |= (var->dpl & 3) << 5;
3876                 ar |= (var->present & 1) << 7;
3877                 ar |= (var->avl & 1) << 12;
3878                 ar |= (var->l & 1) << 13;
3879                 ar |= (var->db & 1) << 14;
3880                 ar |= (var->g & 1) << 15;
3881         }
3882
3883         return ar;
3884 }
3885
3886 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3887                             struct kvm_segment *var, int seg)
3888 {
3889         struct vcpu_vmx *vmx = to_vmx(vcpu);
3890         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3891
3892         vmx_segment_cache_clear(vmx);
3893
3894         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3895                 vmx->rmode.segs[seg] = *var;
3896                 if (seg == VCPU_SREG_TR)
3897                         vmcs_write16(sf->selector, var->selector);
3898                 else if (var->s)
3899                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3900                 goto out;
3901         }
3902
3903         vmcs_writel(sf->base, var->base);
3904         vmcs_write32(sf->limit, var->limit);
3905         vmcs_write16(sf->selector, var->selector);
3906
3907         /*
3908          *   Fix the "Accessed" bit in AR field of segment registers for older
3909          * qemu binaries.
3910          *   IA32 arch specifies that at the time of processor reset the
3911          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3912          * is setting it to 0 in the userland code. This causes invalid guest
3913          * state vmexit when "unrestricted guest" mode is turned on.
3914          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3915          * tree. Newer qemu binaries with that qemu fix would not need this
3916          * kvm hack.
3917          */
3918         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3919                 var->type |= 0x1; /* Accessed */
3920
3921         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3922
3923 out:
3924         vmx->emulation_required = emulation_required(vcpu);
3925 }
3926
3927 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3928 {
3929         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3930
3931         *db = (ar >> 14) & 1;
3932         *l = (ar >> 13) & 1;
3933 }
3934
3935 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3936 {
3937         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3938         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3939 }
3940
3941 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3942 {
3943         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3944         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3945 }
3946
3947 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3948 {
3949         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3950         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3951 }
3952
3953 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3954 {
3955         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3956         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3957 }
3958
3959 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3960 {
3961         struct kvm_segment var;
3962         u32 ar;
3963
3964         vmx_get_segment(vcpu, &var, seg);
3965         var.dpl = 0x3;
3966         if (seg == VCPU_SREG_CS)
3967                 var.type = 0x3;
3968         ar = vmx_segment_access_rights(&var);
3969
3970         if (var.base != (var.selector << 4))
3971                 return false;
3972         if (var.limit != 0xffff)
3973                 return false;
3974         if (ar != 0xf3)
3975                 return false;
3976
3977         return true;
3978 }
3979
3980 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3981 {
3982         struct kvm_segment cs;
3983         unsigned int cs_rpl;
3984
3985         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3986         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
3987
3988         if (cs.unusable)
3989                 return false;
3990         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
3991                 return false;
3992         if (!cs.s)
3993                 return false;
3994         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
3995                 if (cs.dpl > cs_rpl)
3996                         return false;
3997         } else {
3998                 if (cs.dpl != cs_rpl)
3999                         return false;
4000         }
4001         if (!cs.present)
4002                 return false;
4003
4004         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4005         return true;
4006 }
4007
4008 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4009 {
4010         struct kvm_segment ss;
4011         unsigned int ss_rpl;
4012
4013         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4014         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4015
4016         if (ss.unusable)
4017                 return true;
4018         if (ss.type != 3 && ss.type != 7)
4019                 return false;
4020         if (!ss.s)
4021                 return false;
4022         if (ss.dpl != ss_rpl) /* DPL != RPL */
4023                 return false;
4024         if (!ss.present)
4025                 return false;
4026
4027         return true;
4028 }
4029
4030 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4031 {
4032         struct kvm_segment var;
4033         unsigned int rpl;
4034
4035         vmx_get_segment(vcpu, &var, seg);
4036         rpl = var.selector & SEGMENT_RPL_MASK;
4037
4038         if (var.unusable)
4039                 return true;
4040         if (!var.s)
4041                 return false;
4042         if (!var.present)
4043                 return false;
4044         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4045                 if (var.dpl < rpl) /* DPL < RPL */
4046                         return false;
4047         }
4048
4049         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4050          * rights flags
4051          */
4052         return true;
4053 }
4054
4055 static bool tr_valid(struct kvm_vcpu *vcpu)
4056 {
4057         struct kvm_segment tr;
4058
4059         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4060
4061         if (tr.unusable)
4062                 return false;
4063         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4064                 return false;
4065         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4066                 return false;
4067         if (!tr.present)
4068                 return false;
4069
4070         return true;
4071 }
4072
4073 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4074 {
4075         struct kvm_segment ldtr;
4076
4077         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4078
4079         if (ldtr.unusable)
4080                 return true;
4081         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4082                 return false;
4083         if (ldtr.type != 2)
4084                 return false;
4085         if (!ldtr.present)
4086                 return false;
4087
4088         return true;
4089 }
4090
4091 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4092 {
4093         struct kvm_segment cs, ss;
4094
4095         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4096         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4097
4098         return ((cs.selector & SEGMENT_RPL_MASK) ==
4099                  (ss.selector & SEGMENT_RPL_MASK));
4100 }
4101
4102 /*
4103  * Check if guest state is valid. Returns true if valid, false if
4104  * not.
4105  * We assume that registers are always usable
4106  */
4107 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4108 {
4109         if (enable_unrestricted_guest)
4110                 return true;
4111
4112         /* real mode guest state checks */
4113         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4114                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4115                         return false;
4116                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4117                         return false;
4118                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4119                         return false;
4120                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4121                         return false;
4122                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4123                         return false;
4124                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4125                         return false;
4126         } else {
4127         /* protected mode guest state checks */
4128                 if (!cs_ss_rpl_check(vcpu))
4129                         return false;
4130                 if (!code_segment_valid(vcpu))
4131                         return false;
4132                 if (!stack_segment_valid(vcpu))
4133                         return false;
4134                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4135                         return false;
4136                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4137                         return false;
4138                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4139                         return false;
4140                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4141                         return false;
4142                 if (!tr_valid(vcpu))
4143                         return false;
4144                 if (!ldtr_valid(vcpu))
4145                         return false;
4146         }
4147         /* TODO:
4148          * - Add checks on RIP
4149          * - Add checks on RFLAGS
4150          */
4151
4152         return true;
4153 }
4154
4155 static int init_rmode_tss(struct kvm *kvm)
4156 {
4157         gfn_t fn;
4158         u16 data = 0;
4159         int idx, r;
4160
4161         idx = srcu_read_lock(&kvm->srcu);
4162         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4163         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4164         if (r < 0)
4165                 goto out;
4166         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4167         r = kvm_write_guest_page(kvm, fn++, &data,
4168                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4169         if (r < 0)
4170                 goto out;
4171         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4172         if (r < 0)
4173                 goto out;
4174         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4175         if (r < 0)
4176                 goto out;
4177         data = ~0;
4178         r = kvm_write_guest_page(kvm, fn, &data,
4179                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4180                                  sizeof(u8));
4181 out:
4182         srcu_read_unlock(&kvm->srcu, idx);
4183         return r;
4184 }
4185
4186 static int init_rmode_identity_map(struct kvm *kvm)
4187 {
4188         int i, idx, r = 0;
4189         pfn_t identity_map_pfn;
4190         u32 tmp;
4191
4192         if (!enable_ept)
4193                 return 0;
4194
4195         /* Protect kvm->arch.ept_identity_pagetable_done. */
4196         mutex_lock(&kvm->slots_lock);
4197
4198         if (likely(kvm->arch.ept_identity_pagetable_done))
4199                 goto out2;
4200
4201         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4202
4203         r = alloc_identity_pagetable(kvm);
4204         if (r < 0)
4205                 goto out2;
4206
4207         idx = srcu_read_lock(&kvm->srcu);
4208         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4209         if (r < 0)
4210                 goto out;
4211         /* Set up identity-mapping pagetable for EPT in real mode */
4212         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4213                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4214                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4215                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4216                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4217                 if (r < 0)
4218                         goto out;
4219         }
4220         kvm->arch.ept_identity_pagetable_done = true;
4221
4222 out:
4223         srcu_read_unlock(&kvm->srcu, idx);
4224
4225 out2:
4226         mutex_unlock(&kvm->slots_lock);
4227         return r;
4228 }
4229
4230 static void seg_setup(int seg)
4231 {
4232         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4233         unsigned int ar;
4234
4235         vmcs_write16(sf->selector, 0);
4236         vmcs_writel(sf->base, 0);
4237         vmcs_write32(sf->limit, 0xffff);
4238         ar = 0x93;
4239         if (seg == VCPU_SREG_CS)
4240                 ar |= 0x08; /* code segment */
4241
4242         vmcs_write32(sf->ar_bytes, ar);
4243 }
4244
4245 static int alloc_apic_access_page(struct kvm *kvm)
4246 {
4247         struct page *page;
4248         int r = 0;
4249
4250         mutex_lock(&kvm->slots_lock);
4251         if (kvm->arch.apic_access_page_done)
4252                 goto out;
4253         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4254                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4255         if (r)
4256                 goto out;
4257
4258         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4259         if (is_error_page(page)) {
4260                 r = -EFAULT;
4261                 goto out;
4262         }
4263
4264         /*
4265          * Do not pin the page in memory, so that memory hot-unplug
4266          * is able to migrate it.
4267          */
4268         put_page(page);
4269         kvm->arch.apic_access_page_done = true;
4270 out:
4271         mutex_unlock(&kvm->slots_lock);
4272         return r;
4273 }
4274
4275 static int alloc_identity_pagetable(struct kvm *kvm)
4276 {
4277         /* Called with kvm->slots_lock held. */
4278
4279         int r = 0;
4280
4281         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4282
4283         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4284                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4285
4286         return r;
4287 }
4288
4289 static int allocate_vpid(void)
4290 {
4291         int vpid;
4292
4293         if (!enable_vpid)
4294                 return 0;
4295         spin_lock(&vmx_vpid_lock);
4296         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4297         if (vpid < VMX_NR_VPIDS)
4298                 __set_bit(vpid, vmx_vpid_bitmap);
4299         else
4300                 vpid = 0;
4301         spin_unlock(&vmx_vpid_lock);
4302         return vpid;
4303 }
4304
4305 static void free_vpid(int vpid)
4306 {
4307         if (!enable_vpid || vpid == 0)
4308                 return;
4309         spin_lock(&vmx_vpid_lock);
4310         __clear_bit(vpid, vmx_vpid_bitmap);
4311         spin_unlock(&vmx_vpid_lock);
4312 }
4313
4314 #define MSR_TYPE_R      1
4315 #define MSR_TYPE_W      2
4316 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4317                                                 u32 msr, int type)
4318 {
4319         int f = sizeof(unsigned long);
4320
4321         if (!cpu_has_vmx_msr_bitmap())
4322                 return;
4323
4324         /*
4325          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4326          * have the write-low and read-high bitmap offsets the wrong way round.
4327          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4328          */
4329         if (msr <= 0x1fff) {
4330                 if (type & MSR_TYPE_R)
4331                         /* read-low */
4332                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4333
4334                 if (type & MSR_TYPE_W)
4335                         /* write-low */
4336                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4337
4338         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4339                 msr &= 0x1fff;
4340                 if (type & MSR_TYPE_R)
4341                         /* read-high */
4342                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4343
4344                 if (type & MSR_TYPE_W)
4345                         /* write-high */
4346                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4347
4348         }
4349 }
4350
4351 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4352                                                 u32 msr, int type)
4353 {
4354         int f = sizeof(unsigned long);
4355
4356         if (!cpu_has_vmx_msr_bitmap())
4357                 return;
4358
4359         /*
4360          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4361          * have the write-low and read-high bitmap offsets the wrong way round.
4362          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4363          */
4364         if (msr <= 0x1fff) {
4365                 if (type & MSR_TYPE_R)
4366                         /* read-low */
4367                         __set_bit(msr, msr_bitmap + 0x000 / f);
4368
4369                 if (type & MSR_TYPE_W)
4370                         /* write-low */
4371                         __set_bit(msr, msr_bitmap + 0x800 / f);
4372
4373         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4374                 msr &= 0x1fff;
4375                 if (type & MSR_TYPE_R)
4376                         /* read-high */
4377                         __set_bit(msr, msr_bitmap + 0x400 / f);
4378
4379                 if (type & MSR_TYPE_W)
4380                         /* write-high */
4381                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4382
4383         }
4384 }
4385
4386 /*
4387  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4388  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4389  */
4390 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4391                                                unsigned long *msr_bitmap_nested,
4392                                                u32 msr, int type)
4393 {
4394         int f = sizeof(unsigned long);
4395
4396         if (!cpu_has_vmx_msr_bitmap()) {
4397                 WARN_ON(1);
4398                 return;
4399         }
4400
4401         /*
4402          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4403          * have the write-low and read-high bitmap offsets the wrong way round.
4404          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4405          */
4406         if (msr <= 0x1fff) {
4407                 if (type & MSR_TYPE_R &&
4408                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4409                         /* read-low */
4410                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4411
4412                 if (type & MSR_TYPE_W &&
4413                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4414                         /* write-low */
4415                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4416
4417         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4418                 msr &= 0x1fff;
4419                 if (type & MSR_TYPE_R &&
4420                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4421                         /* read-high */
4422                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4423
4424                 if (type & MSR_TYPE_W &&
4425                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4426                         /* write-high */
4427                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4428
4429         }
4430 }
4431
4432 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4433 {
4434         if (!longmode_only)
4435                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4436                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4437         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4438                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4439 }
4440
4441 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4442 {
4443         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4444                         msr, MSR_TYPE_R);
4445         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4446                         msr, MSR_TYPE_R);
4447 }
4448
4449 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4450 {
4451         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4452                         msr, MSR_TYPE_R);
4453         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4454                         msr, MSR_TYPE_R);
4455 }
4456
4457 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4458 {
4459         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4460                         msr, MSR_TYPE_W);
4461         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4462                         msr, MSR_TYPE_W);
4463 }
4464
4465 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4466 {
4467         return enable_apicv && lapic_in_kernel(vcpu);
4468 }
4469
4470 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4471 {
4472         struct vcpu_vmx *vmx = to_vmx(vcpu);
4473         int max_irr;
4474         void *vapic_page;
4475         u16 status;
4476
4477         if (vmx->nested.pi_desc &&
4478             vmx->nested.pi_pending) {
4479                 vmx->nested.pi_pending = false;
4480                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4481                         return 0;
4482
4483                 max_irr = find_last_bit(
4484                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4485
4486                 if (max_irr == 256)
4487                         return 0;
4488
4489                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4490                 if (!vapic_page) {
4491                         WARN_ON(1);
4492                         return -ENOMEM;
4493                 }
4494                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4495                 kunmap(vmx->nested.virtual_apic_page);
4496
4497                 status = vmcs_read16(GUEST_INTR_STATUS);
4498                 if ((u8)max_irr > ((u8)status & 0xff)) {
4499                         status &= ~0xff;
4500                         status |= (u8)max_irr;
4501                         vmcs_write16(GUEST_INTR_STATUS, status);
4502                 }
4503         }
4504         return 0;
4505 }
4506
4507 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4508 {
4509 #ifdef CONFIG_SMP
4510         if (vcpu->mode == IN_GUEST_MODE) {
4511                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4512
4513                 /*
4514                  * Currently, we don't support urgent interrupt,
4515                  * all interrupts are recognized as non-urgent
4516                  * interrupt, so we cannot post interrupts when
4517                  * 'SN' is set.
4518                  *
4519                  * If the vcpu is in guest mode, it means it is
4520                  * running instead of being scheduled out and
4521                  * waiting in the run queue, and that's the only
4522                  * case when 'SN' is set currently, warning if
4523                  * 'SN' is set.
4524                  */
4525                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4526
4527                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4528                                 POSTED_INTR_VECTOR);
4529                 return true;
4530         }
4531 #endif
4532         return false;
4533 }
4534
4535 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4536                                                 int vector)
4537 {
4538         struct vcpu_vmx *vmx = to_vmx(vcpu);
4539
4540         if (is_guest_mode(vcpu) &&
4541             vector == vmx->nested.posted_intr_nv) {
4542                 /* the PIR and ON have been set by L1. */
4543                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4544                 /*
4545                  * If a posted intr is not recognized by hardware,
4546                  * we will accomplish it in the next vmentry.
4547                  */
4548                 vmx->nested.pi_pending = true;
4549                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4550                 return 0;
4551         }
4552         return -1;
4553 }
4554 /*
4555  * Send interrupt to vcpu via posted interrupt way.
4556  * 1. If target vcpu is running(non-root mode), send posted interrupt
4557  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4558  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4559  * interrupt from PIR in next vmentry.
4560  */
4561 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4562 {
4563         struct vcpu_vmx *vmx = to_vmx(vcpu);
4564         int r;
4565
4566         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4567         if (!r)
4568                 return;
4569
4570         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4571                 return;
4572
4573         r = pi_test_and_set_on(&vmx->pi_desc);
4574         kvm_make_request(KVM_REQ_EVENT, vcpu);
4575         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4576                 kvm_vcpu_kick(vcpu);
4577 }
4578
4579 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4580 {
4581         struct vcpu_vmx *vmx = to_vmx(vcpu);
4582
4583         if (!pi_test_and_clear_on(&vmx->pi_desc))
4584                 return;
4585
4586         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4587 }
4588
4589 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4590 {
4591         return;
4592 }
4593
4594 /*
4595  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4596  * will not change in the lifetime of the guest.
4597  * Note that host-state that does change is set elsewhere. E.g., host-state
4598  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4599  */
4600 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4601 {
4602         u32 low32, high32;
4603         unsigned long tmpl;
4604         struct desc_ptr dt;
4605         unsigned long cr4;
4606
4607         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4608         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4609
4610         /* Save the most likely value for this task's CR4 in the VMCS. */
4611         cr4 = cr4_read_shadow();
4612         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4613         vmx->host_state.vmcs_host_cr4 = cr4;
4614
4615         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4616 #ifdef CONFIG_X86_64
4617         /*
4618          * Load null selectors, so we can avoid reloading them in
4619          * __vmx_load_host_state(), in case userspace uses the null selectors
4620          * too (the expected case).
4621          */
4622         vmcs_write16(HOST_DS_SELECTOR, 0);
4623         vmcs_write16(HOST_ES_SELECTOR, 0);
4624 #else
4625         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4626         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4627 #endif
4628         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4629         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4630
4631         native_store_idt(&dt);
4632         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4633         vmx->host_idt_base = dt.address;
4634
4635         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4636
4637         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4638         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4639         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4640         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4641
4642         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4643                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4644                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4645         }
4646 }
4647
4648 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4649 {
4650         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4651         if (enable_ept)
4652                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4653         if (is_guest_mode(&vmx->vcpu))
4654                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4655                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4656         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4657 }
4658
4659 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4660 {
4661         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4662
4663         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4664                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4665         return pin_based_exec_ctrl;
4666 }
4667
4668 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4669 {
4670         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4671
4672         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4673                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4674
4675         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4676                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4677 #ifdef CONFIG_X86_64
4678                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4679                                 CPU_BASED_CR8_LOAD_EXITING;
4680 #endif
4681         }
4682         if (!enable_ept)
4683                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4684                                 CPU_BASED_CR3_LOAD_EXITING  |
4685                                 CPU_BASED_INVLPG_EXITING;
4686         return exec_control;
4687 }
4688
4689 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4690 {
4691         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4692         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4693                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4694         if (vmx->vpid == 0)
4695                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4696         if (!enable_ept) {
4697                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4698                 enable_unrestricted_guest = 0;
4699                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4700                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4701         }
4702         if (!enable_unrestricted_guest)
4703                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4704         if (!ple_gap)
4705                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4706         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4707                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4708                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4709         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4710         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4711            (handle_vmptrld).
4712            We can NOT enable shadow_vmcs here because we don't have yet
4713            a current VMCS12
4714         */
4715         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4716
4717         if (!enable_pml)
4718                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4719
4720         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4721         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4722
4723         return exec_control;
4724 }
4725
4726 static void ept_set_mmio_spte_mask(void)
4727 {
4728         /*
4729          * EPT Misconfigurations can be generated if the value of bits 2:0
4730          * of an EPT paging-structure entry is 110b (write/execute).
4731          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4732          * spte.
4733          */
4734         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4735 }
4736
4737 #define VMX_XSS_EXIT_BITMAP 0
4738 /*
4739  * Sets up the vmcs for emulated real mode.
4740  */
4741 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4742 {
4743 #ifdef CONFIG_X86_64
4744         unsigned long a;
4745 #endif
4746         int i;
4747
4748         /* I/O */
4749         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4750         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4751
4752         if (enable_shadow_vmcs) {
4753                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4754                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4755         }
4756         if (cpu_has_vmx_msr_bitmap())
4757                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4758
4759         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4760
4761         /* Control */
4762         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4763
4764         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4765
4766         if (cpu_has_secondary_exec_ctrls())
4767                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4768                                 vmx_secondary_exec_control(vmx));
4769
4770         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4771                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4772                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4773                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4774                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4775
4776                 vmcs_write16(GUEST_INTR_STATUS, 0);
4777
4778                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4779                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4780         }
4781
4782         if (ple_gap) {
4783                 vmcs_write32(PLE_GAP, ple_gap);
4784                 vmx->ple_window = ple_window;
4785                 vmx->ple_window_dirty = true;
4786         }
4787
4788         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4789         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4790         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4791
4792         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4793         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4794         vmx_set_constant_host_state(vmx);
4795 #ifdef CONFIG_X86_64
4796         rdmsrl(MSR_FS_BASE, a);
4797         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4798         rdmsrl(MSR_GS_BASE, a);
4799         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4800 #else
4801         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4802         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4803 #endif
4804
4805         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4806         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4807         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4808         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4809         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4810
4811         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4812                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4813
4814         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4815                 u32 index = vmx_msr_index[i];
4816                 u32 data_low, data_high;
4817                 int j = vmx->nmsrs;
4818
4819                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4820                         continue;
4821                 if (wrmsr_safe(index, data_low, data_high) < 0)
4822                         continue;
4823                 vmx->guest_msrs[j].index = i;
4824                 vmx->guest_msrs[j].data = 0;
4825                 vmx->guest_msrs[j].mask = -1ull;
4826                 ++vmx->nmsrs;
4827         }
4828
4829
4830         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4831
4832         /* 22.2.1, 20.8.1 */
4833         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4834
4835         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4836         set_cr4_guest_host_mask(vmx);
4837
4838         if (vmx_xsaves_supported())
4839                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4840
4841         return 0;
4842 }
4843
4844 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4845 {
4846         struct vcpu_vmx *vmx = to_vmx(vcpu);
4847         struct msr_data apic_base_msr;
4848         u64 cr0;
4849
4850         vmx->rmode.vm86_active = 0;
4851
4852         vmx->soft_vnmi_blocked = 0;
4853
4854         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4855         kvm_set_cr8(vcpu, 0);
4856
4857         if (!init_event) {
4858                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4859                                      MSR_IA32_APICBASE_ENABLE;
4860                 if (kvm_vcpu_is_reset_bsp(vcpu))
4861                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4862                 apic_base_msr.host_initiated = true;
4863                 kvm_set_apic_base(vcpu, &apic_base_msr);
4864         }
4865
4866         vmx_segment_cache_clear(vmx);
4867
4868         seg_setup(VCPU_SREG_CS);
4869         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4870         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4871
4872         seg_setup(VCPU_SREG_DS);
4873         seg_setup(VCPU_SREG_ES);
4874         seg_setup(VCPU_SREG_FS);
4875         seg_setup(VCPU_SREG_GS);
4876         seg_setup(VCPU_SREG_SS);
4877
4878         vmcs_write16(GUEST_TR_SELECTOR, 0);
4879         vmcs_writel(GUEST_TR_BASE, 0);
4880         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4881         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4882
4883         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4884         vmcs_writel(GUEST_LDTR_BASE, 0);
4885         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4886         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4887
4888         if (!init_event) {
4889                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4890                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4891                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4892                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4893         }
4894
4895         vmcs_writel(GUEST_RFLAGS, 0x02);
4896         kvm_rip_write(vcpu, 0xfff0);
4897
4898         vmcs_writel(GUEST_GDTR_BASE, 0);
4899         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4900
4901         vmcs_writel(GUEST_IDTR_BASE, 0);
4902         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4903
4904         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4905         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4906         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4907
4908         setup_msrs(vmx);
4909
4910         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4911
4912         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4913                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4914                 if (cpu_need_tpr_shadow(vcpu))
4915                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4916                                      __pa(vcpu->arch.apic->regs));
4917                 vmcs_write32(TPR_THRESHOLD, 0);
4918         }
4919
4920         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4921
4922         if (vmx_cpu_uses_apicv(vcpu))
4923                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4924
4925         if (vmx->vpid != 0)
4926                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4927
4928         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4929         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4930         vmx->vcpu.arch.cr0 = cr0;
4931         vmx_set_cr4(vcpu, 0);
4932         vmx_set_efer(vcpu, 0);
4933         vmx_fpu_activate(vcpu);
4934         update_exception_bitmap(vcpu);
4935
4936         vpid_sync_context(vmx->vpid);
4937 }
4938
4939 /*
4940  * In nested virtualization, check if L1 asked to exit on external interrupts.
4941  * For most existing hypervisors, this will always return true.
4942  */
4943 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4944 {
4945         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4946                 PIN_BASED_EXT_INTR_MASK;
4947 }
4948
4949 /*
4950  * In nested virtualization, check if L1 has set
4951  * VM_EXIT_ACK_INTR_ON_EXIT
4952  */
4953 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4954 {
4955         return get_vmcs12(vcpu)->vm_exit_controls &
4956                 VM_EXIT_ACK_INTR_ON_EXIT;
4957 }
4958
4959 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4960 {
4961         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4962                 PIN_BASED_NMI_EXITING;
4963 }
4964
4965 static void enable_irq_window(struct kvm_vcpu *vcpu)
4966 {
4967         u32 cpu_based_vm_exec_control;
4968
4969         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4970         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4971         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4972 }
4973
4974 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4975 {
4976         u32 cpu_based_vm_exec_control;
4977
4978         if (!cpu_has_virtual_nmis() ||
4979             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4980                 enable_irq_window(vcpu);
4981                 return;
4982         }
4983
4984         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4985         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4986         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4987 }
4988
4989 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4990 {
4991         struct vcpu_vmx *vmx = to_vmx(vcpu);
4992         uint32_t intr;
4993         int irq = vcpu->arch.interrupt.nr;
4994
4995         trace_kvm_inj_virq(irq);
4996
4997         ++vcpu->stat.irq_injections;
4998         if (vmx->rmode.vm86_active) {
4999                 int inc_eip = 0;
5000                 if (vcpu->arch.interrupt.soft)
5001                         inc_eip = vcpu->arch.event_exit_inst_len;
5002                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5003                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5004                 return;
5005         }
5006         intr = irq | INTR_INFO_VALID_MASK;
5007         if (vcpu->arch.interrupt.soft) {
5008                 intr |= INTR_TYPE_SOFT_INTR;
5009                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5010                              vmx->vcpu.arch.event_exit_inst_len);
5011         } else
5012                 intr |= INTR_TYPE_EXT_INTR;
5013         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5014 }
5015
5016 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5017 {
5018         struct vcpu_vmx *vmx = to_vmx(vcpu);
5019
5020         if (is_guest_mode(vcpu))
5021                 return;
5022
5023         if (!cpu_has_virtual_nmis()) {
5024                 /*
5025                  * Tracking the NMI-blocked state in software is built upon
5026                  * finding the next open IRQ window. This, in turn, depends on
5027                  * well-behaving guests: They have to keep IRQs disabled at
5028                  * least as long as the NMI handler runs. Otherwise we may
5029                  * cause NMI nesting, maybe breaking the guest. But as this is
5030                  * highly unlikely, we can live with the residual risk.
5031                  */
5032                 vmx->soft_vnmi_blocked = 1;
5033                 vmx->vnmi_blocked_time = 0;
5034         }
5035
5036         ++vcpu->stat.nmi_injections;
5037         vmx->nmi_known_unmasked = false;
5038         if (vmx->rmode.vm86_active) {
5039                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5040                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5041                 return;
5042         }
5043         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5044                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5045 }
5046
5047 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5048 {
5049         if (!cpu_has_virtual_nmis())
5050                 return to_vmx(vcpu)->soft_vnmi_blocked;
5051         if (to_vmx(vcpu)->nmi_known_unmasked)
5052                 return false;
5053         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5054 }
5055
5056 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5057 {
5058         struct vcpu_vmx *vmx = to_vmx(vcpu);
5059
5060         if (!cpu_has_virtual_nmis()) {
5061                 if (vmx->soft_vnmi_blocked != masked) {
5062                         vmx->soft_vnmi_blocked = masked;
5063                         vmx->vnmi_blocked_time = 0;
5064                 }
5065         } else {
5066                 vmx->nmi_known_unmasked = !masked;
5067                 if (masked)
5068                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5069                                       GUEST_INTR_STATE_NMI);
5070                 else
5071                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5072                                         GUEST_INTR_STATE_NMI);
5073         }
5074 }
5075
5076 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5077 {
5078         if (to_vmx(vcpu)->nested.nested_run_pending)
5079                 return 0;
5080
5081         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5082                 return 0;
5083
5084         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5085                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5086                    | GUEST_INTR_STATE_NMI));
5087 }
5088
5089 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5090 {
5091         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5092                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5093                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5094                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5095 }
5096
5097 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5098 {
5099         int ret;
5100
5101         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5102                                     PAGE_SIZE * 3);
5103         if (ret)
5104                 return ret;
5105         kvm->arch.tss_addr = addr;
5106         return init_rmode_tss(kvm);
5107 }
5108
5109 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5110 {
5111         switch (vec) {
5112         case BP_VECTOR:
5113                 /*
5114                  * Update instruction length as we may reinject the exception
5115                  * from user space while in guest debugging mode.
5116                  */
5117                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5118                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5119                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5120                         return false;
5121                 /* fall through */
5122         case DB_VECTOR:
5123                 if (vcpu->guest_debug &
5124                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5125                         return false;
5126                 /* fall through */
5127         case DE_VECTOR:
5128         case OF_VECTOR:
5129         case BR_VECTOR:
5130         case UD_VECTOR:
5131         case DF_VECTOR:
5132         case SS_VECTOR:
5133         case GP_VECTOR:
5134         case MF_VECTOR:
5135                 return true;
5136         break;
5137         }
5138         return false;
5139 }
5140
5141 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5142                                   int vec, u32 err_code)
5143 {
5144         /*
5145          * Instruction with address size override prefix opcode 0x67
5146          * Cause the #SS fault with 0 error code in VM86 mode.
5147          */
5148         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5149                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5150                         if (vcpu->arch.halt_request) {
5151                                 vcpu->arch.halt_request = 0;
5152                                 return kvm_vcpu_halt(vcpu);
5153                         }
5154                         return 1;
5155                 }
5156                 return 0;
5157         }
5158
5159         /*
5160          * Forward all other exceptions that are valid in real mode.
5161          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5162          *        the required debugging infrastructure rework.
5163          */
5164         kvm_queue_exception(vcpu, vec);
5165         return 1;
5166 }
5167
5168 /*
5169  * Trigger machine check on the host. We assume all the MSRs are already set up
5170  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5171  * We pass a fake environment to the machine check handler because we want
5172  * the guest to be always treated like user space, no matter what context
5173  * it used internally.
5174  */
5175 static void kvm_machine_check(void)
5176 {
5177 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5178         struct pt_regs regs = {
5179                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5180                 .flags = X86_EFLAGS_IF,
5181         };
5182
5183         do_machine_check(&regs, 0);
5184 #endif
5185 }
5186
5187 static int handle_machine_check(struct kvm_vcpu *vcpu)
5188 {
5189         /* already handled by vcpu_run */
5190         return 1;
5191 }
5192
5193 static int handle_exception(struct kvm_vcpu *vcpu)
5194 {
5195         struct vcpu_vmx *vmx = to_vmx(vcpu);
5196         struct kvm_run *kvm_run = vcpu->run;
5197         u32 intr_info, ex_no, error_code;
5198         unsigned long cr2, rip, dr6;
5199         u32 vect_info;
5200         enum emulation_result er;
5201
5202         vect_info = vmx->idt_vectoring_info;
5203         intr_info = vmx->exit_intr_info;
5204
5205         if (is_machine_check(intr_info))
5206                 return handle_machine_check(vcpu);
5207
5208         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5209                 return 1;  /* already handled by vmx_vcpu_run() */
5210
5211         if (is_no_device(intr_info)) {
5212                 vmx_fpu_activate(vcpu);
5213                 return 1;
5214         }
5215
5216         if (is_invalid_opcode(intr_info)) {
5217                 if (is_guest_mode(vcpu)) {
5218                         kvm_queue_exception(vcpu, UD_VECTOR);
5219                         return 1;
5220                 }
5221                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5222                 if (er != EMULATE_DONE)
5223                         kvm_queue_exception(vcpu, UD_VECTOR);
5224                 return 1;
5225         }
5226
5227         error_code = 0;
5228         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5229                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5230
5231         /*
5232          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5233          * MMIO, it is better to report an internal error.
5234          * See the comments in vmx_handle_exit.
5235          */
5236         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5237             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5238                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5239                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5240                 vcpu->run->internal.ndata = 3;
5241                 vcpu->run->internal.data[0] = vect_info;
5242                 vcpu->run->internal.data[1] = intr_info;
5243                 vcpu->run->internal.data[2] = error_code;
5244                 return 0;
5245         }
5246
5247         if (is_page_fault(intr_info)) {
5248                 /* EPT won't cause page fault directly */
5249                 BUG_ON(enable_ept);
5250                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5251                 trace_kvm_page_fault(cr2, error_code);
5252
5253                 if (kvm_event_needs_reinjection(vcpu))
5254                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5255                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5256         }
5257
5258         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5259
5260         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5261                 return handle_rmode_exception(vcpu, ex_no, error_code);
5262
5263         switch (ex_no) {
5264         case AC_VECTOR:
5265                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5266                 return 1;
5267         case DB_VECTOR:
5268                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5269                 if (!(vcpu->guest_debug &
5270                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5271                         vcpu->arch.dr6 &= ~15;
5272                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5273                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5274                                 skip_emulated_instruction(vcpu);
5275
5276                         kvm_queue_exception(vcpu, DB_VECTOR);
5277                         return 1;
5278                 }
5279                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5280                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5281                 /* fall through */
5282         case BP_VECTOR:
5283                 /*
5284                  * Update instruction length as we may reinject #BP from
5285                  * user space while in guest debugging mode. Reading it for
5286                  * #DB as well causes no harm, it is not used in that case.
5287                  */
5288                 vmx->vcpu.arch.event_exit_inst_len =
5289                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5290                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5291                 rip = kvm_rip_read(vcpu);
5292                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5293                 kvm_run->debug.arch.exception = ex_no;
5294                 break;
5295         default:
5296                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5297                 kvm_run->ex.exception = ex_no;
5298                 kvm_run->ex.error_code = error_code;
5299                 break;
5300         }
5301         return 0;
5302 }
5303
5304 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5305 {
5306         ++vcpu->stat.irq_exits;
5307         return 1;
5308 }
5309
5310 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5311 {
5312         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5313         return 0;
5314 }
5315
5316 static int handle_io(struct kvm_vcpu *vcpu)
5317 {
5318         unsigned long exit_qualification;
5319         int size, in, string;
5320         unsigned port;
5321
5322         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5323         string = (exit_qualification & 16) != 0;
5324         in = (exit_qualification & 8) != 0;
5325
5326         ++vcpu->stat.io_exits;
5327
5328         if (string || in)
5329                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5330
5331         port = exit_qualification >> 16;
5332         size = (exit_qualification & 7) + 1;
5333         skip_emulated_instruction(vcpu);
5334
5335         return kvm_fast_pio_out(vcpu, size, port);
5336 }
5337
5338 static void
5339 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5340 {
5341         /*
5342          * Patch in the VMCALL instruction:
5343          */
5344         hypercall[0] = 0x0f;
5345         hypercall[1] = 0x01;
5346         hypercall[2] = 0xc1;
5347 }
5348
5349 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5350 {
5351         unsigned long always_on = VMXON_CR0_ALWAYSON;
5352         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5353
5354         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5355                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5356             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5357                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5358         return (val & always_on) == always_on;
5359 }
5360
5361 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5362 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5363 {
5364         if (is_guest_mode(vcpu)) {
5365                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5366                 unsigned long orig_val = val;
5367
5368                 /*
5369                  * We get here when L2 changed cr0 in a way that did not change
5370                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5371                  * but did change L0 shadowed bits. So we first calculate the
5372                  * effective cr0 value that L1 would like to write into the
5373                  * hardware. It consists of the L2-owned bits from the new
5374                  * value combined with the L1-owned bits from L1's guest_cr0.
5375                  */
5376                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5377                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5378
5379                 if (!nested_cr0_valid(vcpu, val))
5380                         return 1;
5381
5382                 if (kvm_set_cr0(vcpu, val))
5383                         return 1;
5384                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5385                 return 0;
5386         } else {
5387                 if (to_vmx(vcpu)->nested.vmxon &&
5388                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5389                         return 1;
5390                 return kvm_set_cr0(vcpu, val);
5391         }
5392 }
5393
5394 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5395 {
5396         if (is_guest_mode(vcpu)) {
5397                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5398                 unsigned long orig_val = val;
5399
5400                 /* analogously to handle_set_cr0 */
5401                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5402                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5403                 if (kvm_set_cr4(vcpu, val))
5404                         return 1;
5405                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5406                 return 0;
5407         } else
5408                 return kvm_set_cr4(vcpu, val);
5409 }
5410
5411 /* called to set cr0 as approriate for clts instruction exit. */
5412 static void handle_clts(struct kvm_vcpu *vcpu)
5413 {
5414         if (is_guest_mode(vcpu)) {
5415                 /*
5416                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5417                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5418                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5419                  */
5420                 vmcs_writel(CR0_READ_SHADOW,
5421                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5422                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5423         } else
5424                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5425 }
5426
5427 static int handle_cr(struct kvm_vcpu *vcpu)
5428 {
5429         unsigned long exit_qualification, val;
5430         int cr;
5431         int reg;
5432         int err;
5433
5434         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5435         cr = exit_qualification & 15;
5436         reg = (exit_qualification >> 8) & 15;
5437         switch ((exit_qualification >> 4) & 3) {
5438         case 0: /* mov to cr */
5439                 val = kvm_register_readl(vcpu, reg);
5440                 trace_kvm_cr_write(cr, val);
5441                 switch (cr) {
5442                 case 0:
5443                         err = handle_set_cr0(vcpu, val);
5444                         kvm_complete_insn_gp(vcpu, err);
5445                         return 1;
5446                 case 3:
5447                         err = kvm_set_cr3(vcpu, val);
5448                         kvm_complete_insn_gp(vcpu, err);
5449                         return 1;
5450                 case 4:
5451                         err = handle_set_cr4(vcpu, val);
5452                         kvm_complete_insn_gp(vcpu, err);
5453                         return 1;
5454                 case 8: {
5455                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5456                                 u8 cr8 = (u8)val;
5457                                 err = kvm_set_cr8(vcpu, cr8);
5458                                 kvm_complete_insn_gp(vcpu, err);
5459                                 if (lapic_in_kernel(vcpu))
5460                                         return 1;
5461                                 if (cr8_prev <= cr8)
5462                                         return 1;
5463                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5464                                 return 0;
5465                         }
5466                 }
5467                 break;
5468         case 2: /* clts */
5469                 handle_clts(vcpu);
5470                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5471                 skip_emulated_instruction(vcpu);
5472                 vmx_fpu_activate(vcpu);
5473                 return 1;
5474         case 1: /*mov from cr*/
5475                 switch (cr) {
5476                 case 3:
5477                         val = kvm_read_cr3(vcpu);
5478                         kvm_register_write(vcpu, reg, val);
5479                         trace_kvm_cr_read(cr, val);
5480                         skip_emulated_instruction(vcpu);
5481                         return 1;
5482                 case 8:
5483                         val = kvm_get_cr8(vcpu);
5484                         kvm_register_write(vcpu, reg, val);
5485                         trace_kvm_cr_read(cr, val);
5486                         skip_emulated_instruction(vcpu);
5487                         return 1;
5488                 }
5489                 break;
5490         case 3: /* lmsw */
5491                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5492                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5493                 kvm_lmsw(vcpu, val);
5494
5495                 skip_emulated_instruction(vcpu);
5496                 return 1;
5497         default:
5498                 break;
5499         }
5500         vcpu->run->exit_reason = 0;
5501         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5502                (int)(exit_qualification >> 4) & 3, cr);
5503         return 0;
5504 }
5505
5506 static int handle_dr(struct kvm_vcpu *vcpu)
5507 {
5508         unsigned long exit_qualification;
5509         int dr, dr7, reg;
5510
5511         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5512         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5513
5514         /* First, if DR does not exist, trigger UD */
5515         if (!kvm_require_dr(vcpu, dr))
5516                 return 1;
5517
5518         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5519         if (!kvm_require_cpl(vcpu, 0))
5520                 return 1;
5521         dr7 = vmcs_readl(GUEST_DR7);
5522         if (dr7 & DR7_GD) {
5523                 /*
5524                  * As the vm-exit takes precedence over the debug trap, we
5525                  * need to emulate the latter, either for the host or the
5526                  * guest debugging itself.
5527                  */
5528                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5529                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5530                         vcpu->run->debug.arch.dr7 = dr7;
5531                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5532                         vcpu->run->debug.arch.exception = DB_VECTOR;
5533                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5534                         return 0;
5535                 } else {
5536                         vcpu->arch.dr6 &= ~15;
5537                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5538                         kvm_queue_exception(vcpu, DB_VECTOR);
5539                         return 1;
5540                 }
5541         }
5542
5543         if (vcpu->guest_debug == 0) {
5544                 u32 cpu_based_vm_exec_control;
5545
5546                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5547                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5548                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5549
5550                 /*
5551                  * No more DR vmexits; force a reload of the debug registers
5552                  * and reenter on this instruction.  The next vmexit will
5553                  * retrieve the full state of the debug registers.
5554                  */
5555                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5556                 return 1;
5557         }
5558
5559         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5560         if (exit_qualification & TYPE_MOV_FROM_DR) {
5561                 unsigned long val;
5562
5563                 if (kvm_get_dr(vcpu, dr, &val))
5564                         return 1;
5565                 kvm_register_write(vcpu, reg, val);
5566         } else
5567                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5568                         return 1;
5569
5570         skip_emulated_instruction(vcpu);
5571         return 1;
5572 }
5573
5574 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5575 {
5576         return vcpu->arch.dr6;
5577 }
5578
5579 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5580 {
5581 }
5582
5583 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5584 {
5585         u32 cpu_based_vm_exec_control;
5586
5587         get_debugreg(vcpu->arch.db[0], 0);
5588         get_debugreg(vcpu->arch.db[1], 1);
5589         get_debugreg(vcpu->arch.db[2], 2);
5590         get_debugreg(vcpu->arch.db[3], 3);
5591         get_debugreg(vcpu->arch.dr6, 6);
5592         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5593
5594         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5595
5596         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5597         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5598         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5599 }
5600
5601 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5602 {
5603         vmcs_writel(GUEST_DR7, val);
5604 }
5605
5606 static int handle_cpuid(struct kvm_vcpu *vcpu)
5607 {
5608         kvm_emulate_cpuid(vcpu);
5609         return 1;
5610 }
5611
5612 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5613 {
5614         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5615         struct msr_data msr_info;
5616
5617         msr_info.index = ecx;
5618         msr_info.host_initiated = false;
5619         if (vmx_get_msr(vcpu, &msr_info)) {
5620                 trace_kvm_msr_read_ex(ecx);
5621                 kvm_inject_gp(vcpu, 0);
5622                 return 1;
5623         }
5624
5625         trace_kvm_msr_read(ecx, msr_info.data);
5626
5627         /* FIXME: handling of bits 32:63 of rax, rdx */
5628         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5629         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5630         skip_emulated_instruction(vcpu);
5631         return 1;
5632 }
5633
5634 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5635 {
5636         struct msr_data msr;
5637         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5638         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5639                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5640
5641         msr.data = data;
5642         msr.index = ecx;
5643         msr.host_initiated = false;
5644         if (kvm_set_msr(vcpu, &msr) != 0) {
5645                 trace_kvm_msr_write_ex(ecx, data);
5646                 kvm_inject_gp(vcpu, 0);
5647                 return 1;
5648         }
5649
5650         trace_kvm_msr_write(ecx, data);
5651         skip_emulated_instruction(vcpu);
5652         return 1;
5653 }
5654
5655 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5656 {
5657         kvm_make_request(KVM_REQ_EVENT, vcpu);
5658         return 1;
5659 }
5660
5661 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5662 {
5663         u32 cpu_based_vm_exec_control;
5664
5665         /* clear pending irq */
5666         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5667         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5668         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5669
5670         kvm_make_request(KVM_REQ_EVENT, vcpu);
5671
5672         ++vcpu->stat.irq_window_exits;
5673         return 1;
5674 }
5675
5676 static int handle_halt(struct kvm_vcpu *vcpu)
5677 {
5678         return kvm_emulate_halt(vcpu);
5679 }
5680
5681 static int handle_vmcall(struct kvm_vcpu *vcpu)
5682 {
5683         kvm_emulate_hypercall(vcpu);
5684         return 1;
5685 }
5686
5687 static int handle_invd(struct kvm_vcpu *vcpu)
5688 {
5689         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5690 }
5691
5692 static int handle_invlpg(struct kvm_vcpu *vcpu)
5693 {
5694         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5695
5696         kvm_mmu_invlpg(vcpu, exit_qualification);
5697         skip_emulated_instruction(vcpu);
5698         return 1;
5699 }
5700
5701 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5702 {
5703         int err;
5704
5705         err = kvm_rdpmc(vcpu);
5706         kvm_complete_insn_gp(vcpu, err);
5707
5708         return 1;
5709 }
5710
5711 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5712 {
5713         kvm_emulate_wbinvd(vcpu);
5714         return 1;
5715 }
5716
5717 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5718 {
5719         u64 new_bv = kvm_read_edx_eax(vcpu);
5720         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5721
5722         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5723                 skip_emulated_instruction(vcpu);
5724         return 1;
5725 }
5726
5727 static int handle_xsaves(struct kvm_vcpu *vcpu)
5728 {
5729         skip_emulated_instruction(vcpu);
5730         WARN(1, "this should never happen\n");
5731         return 1;
5732 }
5733
5734 static int handle_xrstors(struct kvm_vcpu *vcpu)
5735 {
5736         skip_emulated_instruction(vcpu);
5737         WARN(1, "this should never happen\n");
5738         return 1;
5739 }
5740
5741 static int handle_apic_access(struct kvm_vcpu *vcpu)
5742 {
5743         if (likely(fasteoi)) {
5744                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5745                 int access_type, offset;
5746
5747                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5748                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5749                 /*
5750                  * Sane guest uses MOV to write EOI, with written value
5751                  * not cared. So make a short-circuit here by avoiding
5752                  * heavy instruction emulation.
5753                  */
5754                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5755                     (offset == APIC_EOI)) {
5756                         kvm_lapic_set_eoi(vcpu);
5757                         skip_emulated_instruction(vcpu);
5758                         return 1;
5759                 }
5760         }
5761         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5762 }
5763
5764 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5765 {
5766         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5767         int vector = exit_qualification & 0xff;
5768
5769         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5770         kvm_apic_set_eoi_accelerated(vcpu, vector);
5771         return 1;
5772 }
5773
5774 static int handle_apic_write(struct kvm_vcpu *vcpu)
5775 {
5776         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5777         u32 offset = exit_qualification & 0xfff;
5778
5779         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5780         kvm_apic_write_nodecode(vcpu, offset);
5781         return 1;
5782 }
5783
5784 static int handle_task_switch(struct kvm_vcpu *vcpu)
5785 {
5786         struct vcpu_vmx *vmx = to_vmx(vcpu);
5787         unsigned long exit_qualification;
5788         bool has_error_code = false;
5789         u32 error_code = 0;
5790         u16 tss_selector;
5791         int reason, type, idt_v, idt_index;
5792
5793         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5794         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5795         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5796
5797         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5798
5799         reason = (u32)exit_qualification >> 30;
5800         if (reason == TASK_SWITCH_GATE && idt_v) {
5801                 switch (type) {
5802                 case INTR_TYPE_NMI_INTR:
5803                         vcpu->arch.nmi_injected = false;
5804                         vmx_set_nmi_mask(vcpu, true);
5805                         break;
5806                 case INTR_TYPE_EXT_INTR:
5807                 case INTR_TYPE_SOFT_INTR:
5808                         kvm_clear_interrupt_queue(vcpu);
5809                         break;
5810                 case INTR_TYPE_HARD_EXCEPTION:
5811                         if (vmx->idt_vectoring_info &
5812                             VECTORING_INFO_DELIVER_CODE_MASK) {
5813                                 has_error_code = true;
5814                                 error_code =
5815                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5816                         }
5817                         /* fall through */
5818                 case INTR_TYPE_SOFT_EXCEPTION:
5819                         kvm_clear_exception_queue(vcpu);
5820                         break;
5821                 default:
5822                         break;
5823                 }
5824         }
5825         tss_selector = exit_qualification;
5826
5827         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5828                        type != INTR_TYPE_EXT_INTR &&
5829                        type != INTR_TYPE_NMI_INTR))
5830                 skip_emulated_instruction(vcpu);
5831
5832         if (kvm_task_switch(vcpu, tss_selector,
5833                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5834                             has_error_code, error_code) == EMULATE_FAIL) {
5835                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5836                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5837                 vcpu->run->internal.ndata = 0;
5838                 return 0;
5839         }
5840
5841         /*
5842          * TODO: What about debug traps on tss switch?
5843          *       Are we supposed to inject them and update dr6?
5844          */
5845
5846         return 1;
5847 }
5848
5849 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5850 {
5851         unsigned long exit_qualification;
5852         gpa_t gpa;
5853         u32 error_code;
5854         int gla_validity;
5855
5856         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5857
5858         gla_validity = (exit_qualification >> 7) & 0x3;
5859         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5860                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5861                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5862                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5863                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5864                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5865                         (long unsigned int)exit_qualification);
5866                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5867                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5868                 return 0;
5869         }
5870
5871         /*
5872          * EPT violation happened while executing iret from NMI,
5873          * "blocked by NMI" bit has to be set before next VM entry.
5874          * There are errata that may cause this bit to not be set:
5875          * AAK134, BY25.
5876          */
5877         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5878                         cpu_has_virtual_nmis() &&
5879                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5880                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5881
5882         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5883         trace_kvm_page_fault(gpa, exit_qualification);
5884
5885         /* It is a write fault? */
5886         error_code = exit_qualification & PFERR_WRITE_MASK;
5887         /* It is a fetch fault? */
5888         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5889         /* ept page table is present? */
5890         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5891
5892         vcpu->arch.exit_qualification = exit_qualification;
5893
5894         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5895 }
5896
5897 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5898 {
5899         int ret;
5900         gpa_t gpa;
5901
5902         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5903         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5904                 skip_emulated_instruction(vcpu);
5905                 trace_kvm_fast_mmio(gpa);
5906                 return 1;
5907         }
5908
5909         ret = handle_mmio_page_fault(vcpu, gpa, true);
5910         if (likely(ret == RET_MMIO_PF_EMULATE))
5911                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5912                                               EMULATE_DONE;
5913
5914         if (unlikely(ret == RET_MMIO_PF_INVALID))
5915                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5916
5917         if (unlikely(ret == RET_MMIO_PF_RETRY))
5918                 return 1;
5919
5920         /* It is the real ept misconfig */
5921         WARN_ON(1);
5922
5923         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5924         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5925
5926         return 0;
5927 }
5928
5929 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5930 {
5931         u32 cpu_based_vm_exec_control;
5932
5933         /* clear pending NMI */
5934         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5935         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5936         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5937         ++vcpu->stat.nmi_window_exits;
5938         kvm_make_request(KVM_REQ_EVENT, vcpu);
5939
5940         return 1;
5941 }
5942
5943 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5944 {
5945         struct vcpu_vmx *vmx = to_vmx(vcpu);
5946         enum emulation_result err = EMULATE_DONE;
5947         int ret = 1;
5948         u32 cpu_exec_ctrl;
5949         bool intr_window_requested;
5950         unsigned count = 130;
5951
5952         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5953         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5954
5955         while (vmx->emulation_required && count-- != 0) {
5956                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5957                         return handle_interrupt_window(&vmx->vcpu);
5958
5959                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5960                         return 1;
5961
5962                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5963
5964                 if (err == EMULATE_USER_EXIT) {
5965                         ++vcpu->stat.mmio_exits;
5966                         ret = 0;
5967                         goto out;
5968                 }
5969
5970                 if (err != EMULATE_DONE) {
5971                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5972                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5973                         vcpu->run->internal.ndata = 0;
5974                         return 0;
5975                 }
5976
5977                 if (vcpu->arch.halt_request) {
5978                         vcpu->arch.halt_request = 0;
5979                         ret = kvm_vcpu_halt(vcpu);
5980                         goto out;
5981                 }
5982
5983                 if (signal_pending(current))
5984                         goto out;
5985                 if (need_resched())
5986                         schedule();
5987         }
5988
5989 out:
5990         return ret;
5991 }
5992
5993 static int __grow_ple_window(int val)
5994 {
5995         if (ple_window_grow < 1)
5996                 return ple_window;
5997
5998         val = min(val, ple_window_actual_max);
5999
6000         if (ple_window_grow < ple_window)
6001                 val *= ple_window_grow;
6002         else
6003                 val += ple_window_grow;
6004
6005         return val;
6006 }
6007
6008 static int __shrink_ple_window(int val, int modifier, int minimum)
6009 {
6010         if (modifier < 1)
6011                 return ple_window;
6012
6013         if (modifier < ple_window)
6014                 val /= modifier;
6015         else
6016                 val -= modifier;
6017
6018         return max(val, minimum);
6019 }
6020
6021 static void grow_ple_window(struct kvm_vcpu *vcpu)
6022 {
6023         struct vcpu_vmx *vmx = to_vmx(vcpu);
6024         int old = vmx->ple_window;
6025
6026         vmx->ple_window = __grow_ple_window(old);
6027
6028         if (vmx->ple_window != old)
6029                 vmx->ple_window_dirty = true;
6030
6031         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6032 }
6033
6034 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6035 {
6036         struct vcpu_vmx *vmx = to_vmx(vcpu);
6037         int old = vmx->ple_window;
6038
6039         vmx->ple_window = __shrink_ple_window(old,
6040                                               ple_window_shrink, ple_window);
6041
6042         if (vmx->ple_window != old)
6043                 vmx->ple_window_dirty = true;
6044
6045         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6046 }
6047
6048 /*
6049  * ple_window_actual_max is computed to be one grow_ple_window() below
6050  * ple_window_max. (See __grow_ple_window for the reason.)
6051  * This prevents overflows, because ple_window_max is int.
6052  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6053  * this process.
6054  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6055  */
6056 static void update_ple_window_actual_max(void)
6057 {
6058         ple_window_actual_max =
6059                         __shrink_ple_window(max(ple_window_max, ple_window),
6060                                             ple_window_grow, INT_MIN);
6061 }
6062
6063 /*
6064  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6065  */
6066 static void wakeup_handler(void)
6067 {
6068         struct kvm_vcpu *vcpu;
6069         int cpu = smp_processor_id();
6070
6071         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6072         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6073                         blocked_vcpu_list) {
6074                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6075
6076                 if (pi_test_on(pi_desc) == 1)
6077                         kvm_vcpu_kick(vcpu);
6078         }
6079         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6080 }
6081
6082 static __init int hardware_setup(void)
6083 {
6084         int r = -ENOMEM, i, msr;
6085
6086         rdmsrl_safe(MSR_EFER, &host_efer);
6087
6088         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6089                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6090
6091         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6092         if (!vmx_io_bitmap_a)
6093                 return r;
6094
6095         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6096         if (!vmx_io_bitmap_b)
6097                 goto out;
6098
6099         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6100         if (!vmx_msr_bitmap_legacy)
6101                 goto out1;
6102
6103         vmx_msr_bitmap_legacy_x2apic =
6104                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6105         if (!vmx_msr_bitmap_legacy_x2apic)
6106                 goto out2;
6107
6108         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6109         if (!vmx_msr_bitmap_longmode)
6110                 goto out3;
6111
6112         vmx_msr_bitmap_longmode_x2apic =
6113                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6114         if (!vmx_msr_bitmap_longmode_x2apic)
6115                 goto out4;
6116
6117         if (nested) {
6118                 vmx_msr_bitmap_nested =
6119                         (unsigned long *)__get_free_page(GFP_KERNEL);
6120                 if (!vmx_msr_bitmap_nested)
6121                         goto out5;
6122         }
6123
6124         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6125         if (!vmx_vmread_bitmap)
6126                 goto out6;
6127
6128         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6129         if (!vmx_vmwrite_bitmap)
6130                 goto out7;
6131
6132         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6133         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6134
6135         /*
6136          * Allow direct access to the PC debug port (it is often used for I/O
6137          * delays, but the vmexits simply slow things down).
6138          */
6139         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6140         clear_bit(0x80, vmx_io_bitmap_a);
6141
6142         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6143
6144         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6145         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6146         if (nested)
6147                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6148
6149         if (setup_vmcs_config(&vmcs_config) < 0) {
6150                 r = -EIO;
6151                 goto out8;
6152         }
6153
6154         if (boot_cpu_has(X86_FEATURE_NX))
6155                 kvm_enable_efer_bits(EFER_NX);
6156
6157         if (!cpu_has_vmx_vpid())
6158                 enable_vpid = 0;
6159         if (!cpu_has_vmx_shadow_vmcs())
6160                 enable_shadow_vmcs = 0;
6161         if (enable_shadow_vmcs)
6162                 init_vmcs_shadow_fields();
6163
6164         if (!cpu_has_vmx_ept() ||
6165             !cpu_has_vmx_ept_4levels()) {
6166                 enable_ept = 0;
6167                 enable_unrestricted_guest = 0;
6168                 enable_ept_ad_bits = 0;
6169         }
6170
6171         if (!cpu_has_vmx_ept_ad_bits())
6172                 enable_ept_ad_bits = 0;
6173
6174         if (!cpu_has_vmx_unrestricted_guest())
6175                 enable_unrestricted_guest = 0;
6176
6177         if (!cpu_has_vmx_flexpriority())
6178                 flexpriority_enabled = 0;
6179
6180         /*
6181          * set_apic_access_page_addr() is used to reload apic access
6182          * page upon invalidation.  No need to do anything if not
6183          * using the APIC_ACCESS_ADDR VMCS field.
6184          */
6185         if (!flexpriority_enabled)
6186                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6187
6188         if (!cpu_has_vmx_tpr_shadow())
6189                 kvm_x86_ops->update_cr8_intercept = NULL;
6190
6191         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6192                 kvm_disable_largepages();
6193
6194         if (!cpu_has_vmx_ple())
6195                 ple_gap = 0;
6196
6197         if (!cpu_has_vmx_apicv())
6198                 enable_apicv = 0;
6199
6200         if (cpu_has_vmx_tsc_scaling()) {
6201                 kvm_has_tsc_control = true;
6202                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6203                 kvm_tsc_scaling_ratio_frac_bits = 48;
6204         }
6205
6206         if (enable_apicv)
6207                 kvm_x86_ops->update_cr8_intercept = NULL;
6208         else {
6209                 kvm_x86_ops->hwapic_irr_update = NULL;
6210                 kvm_x86_ops->hwapic_isr_update = NULL;
6211                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6212                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6213         }
6214
6215         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6216         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6217         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6218         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6219         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6220         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6221         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6222
6223         memcpy(vmx_msr_bitmap_legacy_x2apic,
6224                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6225         memcpy(vmx_msr_bitmap_longmode_x2apic,
6226                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6227
6228         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6229
6230         if (enable_apicv) {
6231                 for (msr = 0x800; msr <= 0x8ff; msr++)
6232                         vmx_disable_intercept_msr_read_x2apic(msr);
6233
6234                 /* According SDM, in x2apic mode, the whole id reg is used.
6235                  * But in KVM, it only use the highest eight bits. Need to
6236                  * intercept it */
6237                 vmx_enable_intercept_msr_read_x2apic(0x802);
6238                 /* TMCCT */
6239                 vmx_enable_intercept_msr_read_x2apic(0x839);
6240                 /* TPR */
6241                 vmx_disable_intercept_msr_write_x2apic(0x808);
6242                 /* EOI */
6243                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6244                 /* SELF-IPI */
6245                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6246         }
6247
6248         if (enable_ept) {
6249                 kvm_mmu_set_mask_ptes(0ull,
6250                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6251                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6252                         0ull, VMX_EPT_EXECUTABLE_MASK);
6253                 ept_set_mmio_spte_mask();
6254                 kvm_enable_tdp();
6255         } else
6256                 kvm_disable_tdp();
6257
6258         update_ple_window_actual_max();
6259
6260         /*
6261          * Only enable PML when hardware supports PML feature, and both EPT
6262          * and EPT A/D bit features are enabled -- PML depends on them to work.
6263          */
6264         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6265                 enable_pml = 0;
6266
6267         if (!enable_pml) {
6268                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6269                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6270                 kvm_x86_ops->flush_log_dirty = NULL;
6271                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6272         }
6273
6274         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6275
6276         return alloc_kvm_area();
6277
6278 out8:
6279         free_page((unsigned long)vmx_vmwrite_bitmap);
6280 out7:
6281         free_page((unsigned long)vmx_vmread_bitmap);
6282 out6:
6283         if (nested)
6284                 free_page((unsigned long)vmx_msr_bitmap_nested);
6285 out5:
6286         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6287 out4:
6288         free_page((unsigned long)vmx_msr_bitmap_longmode);
6289 out3:
6290         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6291 out2:
6292         free_page((unsigned long)vmx_msr_bitmap_legacy);
6293 out1:
6294         free_page((unsigned long)vmx_io_bitmap_b);
6295 out:
6296         free_page((unsigned long)vmx_io_bitmap_a);
6297
6298     return r;
6299 }
6300
6301 static __exit void hardware_unsetup(void)
6302 {
6303         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6304         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6305         free_page((unsigned long)vmx_msr_bitmap_legacy);
6306         free_page((unsigned long)vmx_msr_bitmap_longmode);
6307         free_page((unsigned long)vmx_io_bitmap_b);
6308         free_page((unsigned long)vmx_io_bitmap_a);
6309         free_page((unsigned long)vmx_vmwrite_bitmap);
6310         free_page((unsigned long)vmx_vmread_bitmap);
6311         if (nested)
6312                 free_page((unsigned long)vmx_msr_bitmap_nested);
6313
6314         free_kvm_area();
6315 }
6316
6317 /*
6318  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6319  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6320  */
6321 static int handle_pause(struct kvm_vcpu *vcpu)
6322 {
6323         if (ple_gap)
6324                 grow_ple_window(vcpu);
6325
6326         skip_emulated_instruction(vcpu);
6327         kvm_vcpu_on_spin(vcpu);
6328
6329         return 1;
6330 }
6331
6332 static int handle_nop(struct kvm_vcpu *vcpu)
6333 {
6334         skip_emulated_instruction(vcpu);
6335         return 1;
6336 }
6337
6338 static int handle_mwait(struct kvm_vcpu *vcpu)
6339 {
6340         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6341         return handle_nop(vcpu);
6342 }
6343
6344 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6345 {
6346         return 1;
6347 }
6348
6349 static int handle_monitor(struct kvm_vcpu *vcpu)
6350 {
6351         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6352         return handle_nop(vcpu);
6353 }
6354
6355 /*
6356  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6357  * We could reuse a single VMCS for all the L2 guests, but we also want the
6358  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6359  * allows keeping them loaded on the processor, and in the future will allow
6360  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6361  * every entry if they never change.
6362  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6363  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6364  *
6365  * The following functions allocate and free a vmcs02 in this pool.
6366  */
6367
6368 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6369 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6370 {
6371         struct vmcs02_list *item;
6372         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6373                 if (item->vmptr == vmx->nested.current_vmptr) {
6374                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6375                         return &item->vmcs02;
6376                 }
6377
6378         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6379                 /* Recycle the least recently used VMCS. */
6380                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6381                         struct vmcs02_list, list);
6382                 item->vmptr = vmx->nested.current_vmptr;
6383                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6384                 return &item->vmcs02;
6385         }
6386
6387         /* Create a new VMCS */
6388         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6389         if (!item)
6390                 return NULL;
6391         item->vmcs02.vmcs = alloc_vmcs();
6392         if (!item->vmcs02.vmcs) {
6393                 kfree(item);
6394                 return NULL;
6395         }
6396         loaded_vmcs_init(&item->vmcs02);
6397         item->vmptr = vmx->nested.current_vmptr;
6398         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6399         vmx->nested.vmcs02_num++;
6400         return &item->vmcs02;
6401 }
6402
6403 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6404 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6405 {
6406         struct vmcs02_list *item;
6407         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6408                 if (item->vmptr == vmptr) {
6409                         free_loaded_vmcs(&item->vmcs02);
6410                         list_del(&item->list);
6411                         kfree(item);
6412                         vmx->nested.vmcs02_num--;
6413                         return;
6414                 }
6415 }
6416
6417 /*
6418  * Free all VMCSs saved for this vcpu, except the one pointed by
6419  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6420  * must be &vmx->vmcs01.
6421  */
6422 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6423 {
6424         struct vmcs02_list *item, *n;
6425
6426         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6427         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6428                 /*
6429                  * Something will leak if the above WARN triggers.  Better than
6430                  * a use-after-free.
6431                  */
6432                 if (vmx->loaded_vmcs == &item->vmcs02)
6433                         continue;
6434
6435                 free_loaded_vmcs(&item->vmcs02);
6436                 list_del(&item->list);
6437                 kfree(item);
6438                 vmx->nested.vmcs02_num--;
6439         }
6440 }
6441
6442 /*
6443  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6444  * set the success or error code of an emulated VMX instruction, as specified
6445  * by Vol 2B, VMX Instruction Reference, "Conventions".
6446  */
6447 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6448 {
6449         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6450                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6451                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6452 }
6453
6454 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6455 {
6456         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6457                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6458                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6459                         | X86_EFLAGS_CF);
6460 }
6461
6462 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6463                                         u32 vm_instruction_error)
6464 {
6465         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6466                 /*
6467                  * failValid writes the error number to the current VMCS, which
6468                  * can't be done there isn't a current VMCS.
6469                  */
6470                 nested_vmx_failInvalid(vcpu);
6471                 return;
6472         }
6473         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6474                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6475                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6476                         | X86_EFLAGS_ZF);
6477         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6478         /*
6479          * We don't need to force a shadow sync because
6480          * VM_INSTRUCTION_ERROR is not shadowed
6481          */
6482 }
6483
6484 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6485 {
6486         /* TODO: not to reset guest simply here. */
6487         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6488         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6489 }
6490
6491 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6492 {
6493         struct vcpu_vmx *vmx =
6494                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6495
6496         vmx->nested.preemption_timer_expired = true;
6497         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6498         kvm_vcpu_kick(&vmx->vcpu);
6499
6500         return HRTIMER_NORESTART;
6501 }
6502
6503 /*
6504  * Decode the memory-address operand of a vmx instruction, as recorded on an
6505  * exit caused by such an instruction (run by a guest hypervisor).
6506  * On success, returns 0. When the operand is invalid, returns 1 and throws
6507  * #UD or #GP.
6508  */
6509 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6510                                  unsigned long exit_qualification,
6511                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6512 {
6513         gva_t off;
6514         bool exn;
6515         struct kvm_segment s;
6516
6517         /*
6518          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6519          * Execution", on an exit, vmx_instruction_info holds most of the
6520          * addressing components of the operand. Only the displacement part
6521          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6522          * For how an actual address is calculated from all these components,
6523          * refer to Vol. 1, "Operand Addressing".
6524          */
6525         int  scaling = vmx_instruction_info & 3;
6526         int  addr_size = (vmx_instruction_info >> 7) & 7;
6527         bool is_reg = vmx_instruction_info & (1u << 10);
6528         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6529         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6530         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6531         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6532         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6533
6534         if (is_reg) {
6535                 kvm_queue_exception(vcpu, UD_VECTOR);
6536                 return 1;
6537         }
6538
6539         /* Addr = segment_base + offset */
6540         /* offset = base + [index * scale] + displacement */
6541         off = exit_qualification; /* holds the displacement */
6542         if (base_is_valid)
6543                 off += kvm_register_read(vcpu, base_reg);
6544         if (index_is_valid)
6545                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6546         vmx_get_segment(vcpu, &s, seg_reg);
6547         *ret = s.base + off;
6548
6549         if (addr_size == 1) /* 32 bit */
6550                 *ret &= 0xffffffff;
6551
6552         /* Checks for #GP/#SS exceptions. */
6553         exn = false;
6554         if (is_protmode(vcpu)) {
6555                 /* Protected mode: apply checks for segment validity in the
6556                  * following order:
6557                  * - segment type check (#GP(0) may be thrown)
6558                  * - usability check (#GP(0)/#SS(0))
6559                  * - limit check (#GP(0)/#SS(0))
6560                  */
6561                 if (wr)
6562                         /* #GP(0) if the destination operand is located in a
6563                          * read-only data segment or any code segment.
6564                          */
6565                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6566                 else
6567                         /* #GP(0) if the source operand is located in an
6568                          * execute-only code segment
6569                          */
6570                         exn = ((s.type & 0xa) == 8);
6571         }
6572         if (exn) {
6573                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6574                 return 1;
6575         }
6576         if (is_long_mode(vcpu)) {
6577                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6578                  * non-canonical form. This is an only check for long mode.
6579                  */
6580                 exn = is_noncanonical_address(*ret);
6581         } else if (is_protmode(vcpu)) {
6582                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6583                  */
6584                 exn = (s.unusable != 0);
6585                 /* Protected mode: #GP(0)/#SS(0) if the memory
6586                  * operand is outside the segment limit.
6587                  */
6588                 exn = exn || (off + sizeof(u64) > s.limit);
6589         }
6590         if (exn) {
6591                 kvm_queue_exception_e(vcpu,
6592                                       seg_reg == VCPU_SREG_SS ?
6593                                                 SS_VECTOR : GP_VECTOR,
6594                                       0);
6595                 return 1;
6596         }
6597
6598         return 0;
6599 }
6600
6601 /*
6602  * This function performs the various checks including
6603  * - if it's 4KB aligned
6604  * - No bits beyond the physical address width are set
6605  * - Returns 0 on success or else 1
6606  * (Intel SDM Section 30.3)
6607  */
6608 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6609                                   gpa_t *vmpointer)
6610 {
6611         gva_t gva;
6612         gpa_t vmptr;
6613         struct x86_exception e;
6614         struct page *page;
6615         struct vcpu_vmx *vmx = to_vmx(vcpu);
6616         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6617
6618         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6619                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6620                 return 1;
6621
6622         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6623                                 sizeof(vmptr), &e)) {
6624                 kvm_inject_page_fault(vcpu, &e);
6625                 return 1;
6626         }
6627
6628         switch (exit_reason) {
6629         case EXIT_REASON_VMON:
6630                 /*
6631                  * SDM 3: 24.11.5
6632                  * The first 4 bytes of VMXON region contain the supported
6633                  * VMCS revision identifier
6634                  *
6635                  * Note - IA32_VMX_BASIC[48] will never be 1
6636                  * for the nested case;
6637                  * which replaces physical address width with 32
6638                  *
6639                  */
6640                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6641                         nested_vmx_failInvalid(vcpu);
6642                         skip_emulated_instruction(vcpu);
6643                         return 1;
6644                 }
6645
6646                 page = nested_get_page(vcpu, vmptr);
6647                 if (page == NULL ||
6648                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6649                         nested_vmx_failInvalid(vcpu);
6650                         kunmap(page);
6651                         skip_emulated_instruction(vcpu);
6652                         return 1;
6653                 }
6654                 kunmap(page);
6655                 vmx->nested.vmxon_ptr = vmptr;
6656                 break;
6657         case EXIT_REASON_VMCLEAR:
6658                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6659                         nested_vmx_failValid(vcpu,
6660                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6661                         skip_emulated_instruction(vcpu);
6662                         return 1;
6663                 }
6664
6665                 if (vmptr == vmx->nested.vmxon_ptr) {
6666                         nested_vmx_failValid(vcpu,
6667                                              VMXERR_VMCLEAR_VMXON_POINTER);
6668                         skip_emulated_instruction(vcpu);
6669                         return 1;
6670                 }
6671                 break;
6672         case EXIT_REASON_VMPTRLD:
6673                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6674                         nested_vmx_failValid(vcpu,
6675                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6676                         skip_emulated_instruction(vcpu);
6677                         return 1;
6678                 }
6679
6680                 if (vmptr == vmx->nested.vmxon_ptr) {
6681                         nested_vmx_failValid(vcpu,
6682                                              VMXERR_VMCLEAR_VMXON_POINTER);
6683                         skip_emulated_instruction(vcpu);
6684                         return 1;
6685                 }
6686                 break;
6687         default:
6688                 return 1; /* shouldn't happen */
6689         }
6690
6691         if (vmpointer)
6692                 *vmpointer = vmptr;
6693         return 0;
6694 }
6695
6696 /*
6697  * Emulate the VMXON instruction.
6698  * Currently, we just remember that VMX is active, and do not save or even
6699  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6700  * do not currently need to store anything in that guest-allocated memory
6701  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6702  * argument is different from the VMXON pointer (which the spec says they do).
6703  */
6704 static int handle_vmon(struct kvm_vcpu *vcpu)
6705 {
6706         struct kvm_segment cs;
6707         struct vcpu_vmx *vmx = to_vmx(vcpu);
6708         struct vmcs *shadow_vmcs;
6709         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6710                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6711
6712         /* The Intel VMX Instruction Reference lists a bunch of bits that
6713          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6714          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6715          * Otherwise, we should fail with #UD. We test these now:
6716          */
6717         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6718             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6719             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6720                 kvm_queue_exception(vcpu, UD_VECTOR);
6721                 return 1;
6722         }
6723
6724         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6725         if (is_long_mode(vcpu) && !cs.l) {
6726                 kvm_queue_exception(vcpu, UD_VECTOR);
6727                 return 1;
6728         }
6729
6730         if (vmx_get_cpl(vcpu)) {
6731                 kvm_inject_gp(vcpu, 0);
6732                 return 1;
6733         }
6734
6735         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6736                 return 1;
6737
6738         if (vmx->nested.vmxon) {
6739                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6740                 skip_emulated_instruction(vcpu);
6741                 return 1;
6742         }
6743
6744         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6745                         != VMXON_NEEDED_FEATURES) {
6746                 kvm_inject_gp(vcpu, 0);
6747                 return 1;
6748         }
6749
6750         if (enable_shadow_vmcs) {
6751                 shadow_vmcs = alloc_vmcs();
6752                 if (!shadow_vmcs)
6753                         return -ENOMEM;
6754                 /* mark vmcs as shadow */
6755                 shadow_vmcs->revision_id |= (1u << 31);
6756                 /* init shadow vmcs */
6757                 vmcs_clear(shadow_vmcs);
6758                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6759         }
6760
6761         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6762         vmx->nested.vmcs02_num = 0;
6763
6764         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6765                      HRTIMER_MODE_REL);
6766         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6767
6768         vmx->nested.vmxon = true;
6769
6770         skip_emulated_instruction(vcpu);
6771         nested_vmx_succeed(vcpu);
6772         return 1;
6773 }
6774
6775 /*
6776  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6777  * for running VMX instructions (except VMXON, whose prerequisites are
6778  * slightly different). It also specifies what exception to inject otherwise.
6779  */
6780 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6781 {
6782         struct kvm_segment cs;
6783         struct vcpu_vmx *vmx = to_vmx(vcpu);
6784
6785         if (!vmx->nested.vmxon) {
6786                 kvm_queue_exception(vcpu, UD_VECTOR);
6787                 return 0;
6788         }
6789
6790         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6791         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6792             (is_long_mode(vcpu) && !cs.l)) {
6793                 kvm_queue_exception(vcpu, UD_VECTOR);
6794                 return 0;
6795         }
6796
6797         if (vmx_get_cpl(vcpu)) {
6798                 kvm_inject_gp(vcpu, 0);
6799                 return 0;
6800         }
6801
6802         return 1;
6803 }
6804
6805 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6806 {
6807         if (vmx->nested.current_vmptr == -1ull)
6808                 return;
6809
6810         /* current_vmptr and current_vmcs12 are always set/reset together */
6811         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6812                 return;
6813
6814         if (enable_shadow_vmcs) {
6815                 /* copy to memory all shadowed fields in case
6816                    they were modified */
6817                 copy_shadow_to_vmcs12(vmx);
6818                 vmx->nested.sync_shadow_vmcs = false;
6819                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6820                                 SECONDARY_EXEC_SHADOW_VMCS);
6821                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6822         }
6823         vmx->nested.posted_intr_nv = -1;
6824         kunmap(vmx->nested.current_vmcs12_page);
6825         nested_release_page(vmx->nested.current_vmcs12_page);
6826         vmx->nested.current_vmptr = -1ull;
6827         vmx->nested.current_vmcs12 = NULL;
6828 }
6829
6830 /*
6831  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6832  * just stops using VMX.
6833  */
6834 static void free_nested(struct vcpu_vmx *vmx)
6835 {
6836         if (!vmx->nested.vmxon)
6837                 return;
6838
6839         vmx->nested.vmxon = false;
6840         free_vpid(vmx->nested.vpid02);
6841         nested_release_vmcs12(vmx);
6842         if (enable_shadow_vmcs)
6843                 free_vmcs(vmx->nested.current_shadow_vmcs);
6844         /* Unpin physical memory we referred to in current vmcs02 */
6845         if (vmx->nested.apic_access_page) {
6846                 nested_release_page(vmx->nested.apic_access_page);
6847                 vmx->nested.apic_access_page = NULL;
6848         }
6849         if (vmx->nested.virtual_apic_page) {
6850                 nested_release_page(vmx->nested.virtual_apic_page);
6851                 vmx->nested.virtual_apic_page = NULL;
6852         }
6853         if (vmx->nested.pi_desc_page) {
6854                 kunmap(vmx->nested.pi_desc_page);
6855                 nested_release_page(vmx->nested.pi_desc_page);
6856                 vmx->nested.pi_desc_page = NULL;
6857                 vmx->nested.pi_desc = NULL;
6858         }
6859
6860         nested_free_all_saved_vmcss(vmx);
6861 }
6862
6863 /* Emulate the VMXOFF instruction */
6864 static int handle_vmoff(struct kvm_vcpu *vcpu)
6865 {
6866         if (!nested_vmx_check_permission(vcpu))
6867                 return 1;
6868         free_nested(to_vmx(vcpu));
6869         skip_emulated_instruction(vcpu);
6870         nested_vmx_succeed(vcpu);
6871         return 1;
6872 }
6873
6874 /* Emulate the VMCLEAR instruction */
6875 static int handle_vmclear(struct kvm_vcpu *vcpu)
6876 {
6877         struct vcpu_vmx *vmx = to_vmx(vcpu);
6878         gpa_t vmptr;
6879         struct vmcs12 *vmcs12;
6880         struct page *page;
6881
6882         if (!nested_vmx_check_permission(vcpu))
6883                 return 1;
6884
6885         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6886                 return 1;
6887
6888         if (vmptr == vmx->nested.current_vmptr)
6889                 nested_release_vmcs12(vmx);
6890
6891         page = nested_get_page(vcpu, vmptr);
6892         if (page == NULL) {
6893                 /*
6894                  * For accurate processor emulation, VMCLEAR beyond available
6895                  * physical memory should do nothing at all. However, it is
6896                  * possible that a nested vmx bug, not a guest hypervisor bug,
6897                  * resulted in this case, so let's shut down before doing any
6898                  * more damage:
6899                  */
6900                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6901                 return 1;
6902         }
6903         vmcs12 = kmap(page);
6904         vmcs12->launch_state = 0;
6905         kunmap(page);
6906         nested_release_page(page);
6907
6908         nested_free_vmcs02(vmx, vmptr);
6909
6910         skip_emulated_instruction(vcpu);
6911         nested_vmx_succeed(vcpu);
6912         return 1;
6913 }
6914
6915 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6916
6917 /* Emulate the VMLAUNCH instruction */
6918 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6919 {
6920         return nested_vmx_run(vcpu, true);
6921 }
6922
6923 /* Emulate the VMRESUME instruction */
6924 static int handle_vmresume(struct kvm_vcpu *vcpu)
6925 {
6926
6927         return nested_vmx_run(vcpu, false);
6928 }
6929
6930 enum vmcs_field_type {
6931         VMCS_FIELD_TYPE_U16 = 0,
6932         VMCS_FIELD_TYPE_U64 = 1,
6933         VMCS_FIELD_TYPE_U32 = 2,
6934         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6935 };
6936
6937 static inline int vmcs_field_type(unsigned long field)
6938 {
6939         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6940                 return VMCS_FIELD_TYPE_U32;
6941         return (field >> 13) & 0x3 ;
6942 }
6943
6944 static inline int vmcs_field_readonly(unsigned long field)
6945 {
6946         return (((field >> 10) & 0x3) == 1);
6947 }
6948
6949 /*
6950  * Read a vmcs12 field. Since these can have varying lengths and we return
6951  * one type, we chose the biggest type (u64) and zero-extend the return value
6952  * to that size. Note that the caller, handle_vmread, might need to use only
6953  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6954  * 64-bit fields are to be returned).
6955  */
6956 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6957                                   unsigned long field, u64 *ret)
6958 {
6959         short offset = vmcs_field_to_offset(field);
6960         char *p;
6961
6962         if (offset < 0)
6963                 return offset;
6964
6965         p = ((char *)(get_vmcs12(vcpu))) + offset;
6966
6967         switch (vmcs_field_type(field)) {
6968         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6969                 *ret = *((natural_width *)p);
6970                 return 0;
6971         case VMCS_FIELD_TYPE_U16:
6972                 *ret = *((u16 *)p);
6973                 return 0;
6974         case VMCS_FIELD_TYPE_U32:
6975                 *ret = *((u32 *)p);
6976                 return 0;
6977         case VMCS_FIELD_TYPE_U64:
6978                 *ret = *((u64 *)p);
6979                 return 0;
6980         default:
6981                 WARN_ON(1);
6982                 return -ENOENT;
6983         }
6984 }
6985
6986
6987 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6988                                    unsigned long field, u64 field_value){
6989         short offset = vmcs_field_to_offset(field);
6990         char *p = ((char *) get_vmcs12(vcpu)) + offset;
6991         if (offset < 0)
6992                 return offset;
6993
6994         switch (vmcs_field_type(field)) {
6995         case VMCS_FIELD_TYPE_U16:
6996                 *(u16 *)p = field_value;
6997                 return 0;
6998         case VMCS_FIELD_TYPE_U32:
6999                 *(u32 *)p = field_value;
7000                 return 0;
7001         case VMCS_FIELD_TYPE_U64:
7002                 *(u64 *)p = field_value;
7003                 return 0;
7004         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7005                 *(natural_width *)p = field_value;
7006                 return 0;
7007         default:
7008                 WARN_ON(1);
7009                 return -ENOENT;
7010         }
7011
7012 }
7013
7014 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7015 {
7016         int i;
7017         unsigned long field;
7018         u64 field_value;
7019         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7020         const unsigned long *fields = shadow_read_write_fields;
7021         const int num_fields = max_shadow_read_write_fields;
7022
7023         preempt_disable();
7024
7025         vmcs_load(shadow_vmcs);
7026
7027         for (i = 0; i < num_fields; i++) {
7028                 field = fields[i];
7029                 switch (vmcs_field_type(field)) {
7030                 case VMCS_FIELD_TYPE_U16:
7031                         field_value = vmcs_read16(field);
7032                         break;
7033                 case VMCS_FIELD_TYPE_U32:
7034                         field_value = vmcs_read32(field);
7035                         break;
7036                 case VMCS_FIELD_TYPE_U64:
7037                         field_value = vmcs_read64(field);
7038                         break;
7039                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7040                         field_value = vmcs_readl(field);
7041                         break;
7042                 default:
7043                         WARN_ON(1);
7044                         continue;
7045                 }
7046                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7047         }
7048
7049         vmcs_clear(shadow_vmcs);
7050         vmcs_load(vmx->loaded_vmcs->vmcs);
7051
7052         preempt_enable();
7053 }
7054
7055 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7056 {
7057         const unsigned long *fields[] = {
7058                 shadow_read_write_fields,
7059                 shadow_read_only_fields
7060         };
7061         const int max_fields[] = {
7062                 max_shadow_read_write_fields,
7063                 max_shadow_read_only_fields
7064         };
7065         int i, q;
7066         unsigned long field;
7067         u64 field_value = 0;
7068         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7069
7070         vmcs_load(shadow_vmcs);
7071
7072         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7073                 for (i = 0; i < max_fields[q]; i++) {
7074                         field = fields[q][i];
7075                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7076
7077                         switch (vmcs_field_type(field)) {
7078                         case VMCS_FIELD_TYPE_U16:
7079                                 vmcs_write16(field, (u16)field_value);
7080                                 break;
7081                         case VMCS_FIELD_TYPE_U32:
7082                                 vmcs_write32(field, (u32)field_value);
7083                                 break;
7084                         case VMCS_FIELD_TYPE_U64:
7085                                 vmcs_write64(field, (u64)field_value);
7086                                 break;
7087                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7088                                 vmcs_writel(field, (long)field_value);
7089                                 break;
7090                         default:
7091                                 WARN_ON(1);
7092                                 break;
7093                         }
7094                 }
7095         }
7096
7097         vmcs_clear(shadow_vmcs);
7098         vmcs_load(vmx->loaded_vmcs->vmcs);
7099 }
7100
7101 /*
7102  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7103  * used before) all generate the same failure when it is missing.
7104  */
7105 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7106 {
7107         struct vcpu_vmx *vmx = to_vmx(vcpu);
7108         if (vmx->nested.current_vmptr == -1ull) {
7109                 nested_vmx_failInvalid(vcpu);
7110                 skip_emulated_instruction(vcpu);
7111                 return 0;
7112         }
7113         return 1;
7114 }
7115
7116 static int handle_vmread(struct kvm_vcpu *vcpu)
7117 {
7118         unsigned long field;
7119         u64 field_value;
7120         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7121         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7122         gva_t gva = 0;
7123
7124         if (!nested_vmx_check_permission(vcpu) ||
7125             !nested_vmx_check_vmcs12(vcpu))
7126                 return 1;
7127
7128         /* Decode instruction info and find the field to read */
7129         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7130         /* Read the field, zero-extended to a u64 field_value */
7131         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7132                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7133                 skip_emulated_instruction(vcpu);
7134                 return 1;
7135         }
7136         /*
7137          * Now copy part of this value to register or memory, as requested.
7138          * Note that the number of bits actually copied is 32 or 64 depending
7139          * on the guest's mode (32 or 64 bit), not on the given field's length.
7140          */
7141         if (vmx_instruction_info & (1u << 10)) {
7142                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7143                         field_value);
7144         } else {
7145                 if (get_vmx_mem_address(vcpu, exit_qualification,
7146                                 vmx_instruction_info, true, &gva))
7147                         return 1;
7148                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7149                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7150                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7151         }
7152
7153         nested_vmx_succeed(vcpu);
7154         skip_emulated_instruction(vcpu);
7155         return 1;
7156 }
7157
7158
7159 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7160 {
7161         unsigned long field;
7162         gva_t gva;
7163         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7164         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7165         /* The value to write might be 32 or 64 bits, depending on L1's long
7166          * mode, and eventually we need to write that into a field of several
7167          * possible lengths. The code below first zero-extends the value to 64
7168          * bit (field_value), and then copies only the approriate number of
7169          * bits into the vmcs12 field.
7170          */
7171         u64 field_value = 0;
7172         struct x86_exception e;
7173
7174         if (!nested_vmx_check_permission(vcpu) ||
7175             !nested_vmx_check_vmcs12(vcpu))
7176                 return 1;
7177
7178         if (vmx_instruction_info & (1u << 10))
7179                 field_value = kvm_register_readl(vcpu,
7180                         (((vmx_instruction_info) >> 3) & 0xf));
7181         else {
7182                 if (get_vmx_mem_address(vcpu, exit_qualification,
7183                                 vmx_instruction_info, false, &gva))
7184                         return 1;
7185                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7186                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7187                         kvm_inject_page_fault(vcpu, &e);
7188                         return 1;
7189                 }
7190         }
7191
7192
7193         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7194         if (vmcs_field_readonly(field)) {
7195                 nested_vmx_failValid(vcpu,
7196                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7197                 skip_emulated_instruction(vcpu);
7198                 return 1;
7199         }
7200
7201         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7202                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7203                 skip_emulated_instruction(vcpu);
7204                 return 1;
7205         }
7206
7207         nested_vmx_succeed(vcpu);
7208         skip_emulated_instruction(vcpu);
7209         return 1;
7210 }
7211
7212 /* Emulate the VMPTRLD instruction */
7213 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7214 {
7215         struct vcpu_vmx *vmx = to_vmx(vcpu);
7216         gpa_t vmptr;
7217
7218         if (!nested_vmx_check_permission(vcpu))
7219                 return 1;
7220
7221         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7222                 return 1;
7223
7224         if (vmx->nested.current_vmptr != vmptr) {
7225                 struct vmcs12 *new_vmcs12;
7226                 struct page *page;
7227                 page = nested_get_page(vcpu, vmptr);
7228                 if (page == NULL) {
7229                         nested_vmx_failInvalid(vcpu);
7230                         skip_emulated_instruction(vcpu);
7231                         return 1;
7232                 }
7233                 new_vmcs12 = kmap(page);
7234                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7235                         kunmap(page);
7236                         nested_release_page_clean(page);
7237                         nested_vmx_failValid(vcpu,
7238                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7239                         skip_emulated_instruction(vcpu);
7240                         return 1;
7241                 }
7242
7243                 nested_release_vmcs12(vmx);
7244                 vmx->nested.current_vmptr = vmptr;
7245                 vmx->nested.current_vmcs12 = new_vmcs12;
7246                 vmx->nested.current_vmcs12_page = page;
7247                 if (enable_shadow_vmcs) {
7248                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7249                                       SECONDARY_EXEC_SHADOW_VMCS);
7250                         vmcs_write64(VMCS_LINK_POINTER,
7251                                      __pa(vmx->nested.current_shadow_vmcs));
7252                         vmx->nested.sync_shadow_vmcs = true;
7253                 }
7254         }
7255
7256         nested_vmx_succeed(vcpu);
7257         skip_emulated_instruction(vcpu);
7258         return 1;
7259 }
7260
7261 /* Emulate the VMPTRST instruction */
7262 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7263 {
7264         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7265         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7266         gva_t vmcs_gva;
7267         struct x86_exception e;
7268
7269         if (!nested_vmx_check_permission(vcpu))
7270                 return 1;
7271
7272         if (get_vmx_mem_address(vcpu, exit_qualification,
7273                         vmx_instruction_info, true, &vmcs_gva))
7274                 return 1;
7275         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7276         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7277                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7278                                  sizeof(u64), &e)) {
7279                 kvm_inject_page_fault(vcpu, &e);
7280                 return 1;
7281         }
7282         nested_vmx_succeed(vcpu);
7283         skip_emulated_instruction(vcpu);
7284         return 1;
7285 }
7286
7287 /* Emulate the INVEPT instruction */
7288 static int handle_invept(struct kvm_vcpu *vcpu)
7289 {
7290         struct vcpu_vmx *vmx = to_vmx(vcpu);
7291         u32 vmx_instruction_info, types;
7292         unsigned long type;
7293         gva_t gva;
7294         struct x86_exception e;
7295         struct {
7296                 u64 eptp, gpa;
7297         } operand;
7298
7299         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7300               SECONDARY_EXEC_ENABLE_EPT) ||
7301             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7302                 kvm_queue_exception(vcpu, UD_VECTOR);
7303                 return 1;
7304         }
7305
7306         if (!nested_vmx_check_permission(vcpu))
7307                 return 1;
7308
7309         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7310                 kvm_queue_exception(vcpu, UD_VECTOR);
7311                 return 1;
7312         }
7313
7314         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7315         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7316
7317         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7318
7319         if (!(types & (1UL << type))) {
7320                 nested_vmx_failValid(vcpu,
7321                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7322                 return 1;
7323         }
7324
7325         /* According to the Intel VMX instruction reference, the memory
7326          * operand is read even if it isn't needed (e.g., for type==global)
7327          */
7328         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7329                         vmx_instruction_info, false, &gva))
7330                 return 1;
7331         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7332                                 sizeof(operand), &e)) {
7333                 kvm_inject_page_fault(vcpu, &e);
7334                 return 1;
7335         }
7336
7337         switch (type) {
7338         case VMX_EPT_EXTENT_GLOBAL:
7339                 kvm_mmu_sync_roots(vcpu);
7340                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7341                 nested_vmx_succeed(vcpu);
7342                 break;
7343         default:
7344                 /* Trap single context invalidation invept calls */
7345                 BUG_ON(1);
7346                 break;
7347         }
7348
7349         skip_emulated_instruction(vcpu);
7350         return 1;
7351 }
7352
7353 static int handle_invvpid(struct kvm_vcpu *vcpu)
7354 {
7355         struct vcpu_vmx *vmx = to_vmx(vcpu);
7356         u32 vmx_instruction_info;
7357         unsigned long type, types;
7358         gva_t gva;
7359         struct x86_exception e;
7360         int vpid;
7361
7362         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7363               SECONDARY_EXEC_ENABLE_VPID) ||
7364                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7365                 kvm_queue_exception(vcpu, UD_VECTOR);
7366                 return 1;
7367         }
7368
7369         if (!nested_vmx_check_permission(vcpu))
7370                 return 1;
7371
7372         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7373         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7374
7375         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7376
7377         if (!(types & (1UL << type))) {
7378                 nested_vmx_failValid(vcpu,
7379                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7380                 return 1;
7381         }
7382
7383         /* according to the intel vmx instruction reference, the memory
7384          * operand is read even if it isn't needed (e.g., for type==global)
7385          */
7386         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7387                         vmx_instruction_info, false, &gva))
7388                 return 1;
7389         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7390                                 sizeof(u32), &e)) {
7391                 kvm_inject_page_fault(vcpu, &e);
7392                 return 1;
7393         }
7394
7395         switch (type) {
7396         case VMX_VPID_EXTENT_ALL_CONTEXT:
7397                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7398                 nested_vmx_succeed(vcpu);
7399                 break;
7400         default:
7401                 /* Trap single context invalidation invvpid calls */
7402                 BUG_ON(1);
7403                 break;
7404         }
7405
7406         skip_emulated_instruction(vcpu);
7407         return 1;
7408 }
7409
7410 static int handle_pml_full(struct kvm_vcpu *vcpu)
7411 {
7412         unsigned long exit_qualification;
7413
7414         trace_kvm_pml_full(vcpu->vcpu_id);
7415
7416         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7417
7418         /*
7419          * PML buffer FULL happened while executing iret from NMI,
7420          * "blocked by NMI" bit has to be set before next VM entry.
7421          */
7422         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7423                         cpu_has_virtual_nmis() &&
7424                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7425                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7426                                 GUEST_INTR_STATE_NMI);
7427
7428         /*
7429          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7430          * here.., and there's no userspace involvement needed for PML.
7431          */
7432         return 1;
7433 }
7434
7435 static int handle_pcommit(struct kvm_vcpu *vcpu)
7436 {
7437         /* we never catch pcommit instruct for L1 guest. */
7438         WARN_ON(1);
7439         return 1;
7440 }
7441
7442 /*
7443  * The exit handlers return 1 if the exit was handled fully and guest execution
7444  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7445  * to be done to userspace and return 0.
7446  */
7447 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7448         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7449         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7450         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7451         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7452         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7453         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7454         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7455         [EXIT_REASON_CPUID]                   = handle_cpuid,
7456         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7457         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7458         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7459         [EXIT_REASON_HLT]                     = handle_halt,
7460         [EXIT_REASON_INVD]                    = handle_invd,
7461         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7462         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7463         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7464         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7465         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7466         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7467         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7468         [EXIT_REASON_VMREAD]                  = handle_vmread,
7469         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7470         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7471         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7472         [EXIT_REASON_VMON]                    = handle_vmon,
7473         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7474         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7475         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7476         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7477         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7478         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7479         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7480         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7481         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7482         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7483         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7484         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7485         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7486         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7487         [EXIT_REASON_INVEPT]                  = handle_invept,
7488         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7489         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7490         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7491         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7492         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7493 };
7494
7495 static const int kvm_vmx_max_exit_handlers =
7496         ARRAY_SIZE(kvm_vmx_exit_handlers);
7497
7498 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7499                                        struct vmcs12 *vmcs12)
7500 {
7501         unsigned long exit_qualification;
7502         gpa_t bitmap, last_bitmap;
7503         unsigned int port;
7504         int size;
7505         u8 b;
7506
7507         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7508                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7509
7510         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7511
7512         port = exit_qualification >> 16;
7513         size = (exit_qualification & 7) + 1;
7514
7515         last_bitmap = (gpa_t)-1;
7516         b = -1;
7517
7518         while (size > 0) {
7519                 if (port < 0x8000)
7520                         bitmap = vmcs12->io_bitmap_a;
7521                 else if (port < 0x10000)
7522                         bitmap = vmcs12->io_bitmap_b;
7523                 else
7524                         return true;
7525                 bitmap += (port & 0x7fff) / 8;
7526
7527                 if (last_bitmap != bitmap)
7528                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7529                                 return true;
7530                 if (b & (1 << (port & 7)))
7531                         return true;
7532
7533                 port++;
7534                 size--;
7535                 last_bitmap = bitmap;
7536         }
7537
7538         return false;
7539 }
7540
7541 /*
7542  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7543  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7544  * disinterest in the current event (read or write a specific MSR) by using an
7545  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7546  */
7547 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7548         struct vmcs12 *vmcs12, u32 exit_reason)
7549 {
7550         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7551         gpa_t bitmap;
7552
7553         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7554                 return true;
7555
7556         /*
7557          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7558          * for the four combinations of read/write and low/high MSR numbers.
7559          * First we need to figure out which of the four to use:
7560          */
7561         bitmap = vmcs12->msr_bitmap;
7562         if (exit_reason == EXIT_REASON_MSR_WRITE)
7563                 bitmap += 2048;
7564         if (msr_index >= 0xc0000000) {
7565                 msr_index -= 0xc0000000;
7566                 bitmap += 1024;
7567         }
7568
7569         /* Then read the msr_index'th bit from this bitmap: */
7570         if (msr_index < 1024*8) {
7571                 unsigned char b;
7572                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7573                         return true;
7574                 return 1 & (b >> (msr_index & 7));
7575         } else
7576                 return true; /* let L1 handle the wrong parameter */
7577 }
7578
7579 /*
7580  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7581  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7582  * intercept (via guest_host_mask etc.) the current event.
7583  */
7584 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7585         struct vmcs12 *vmcs12)
7586 {
7587         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7588         int cr = exit_qualification & 15;
7589         int reg = (exit_qualification >> 8) & 15;
7590         unsigned long val = kvm_register_readl(vcpu, reg);
7591
7592         switch ((exit_qualification >> 4) & 3) {
7593         case 0: /* mov to cr */
7594                 switch (cr) {
7595                 case 0:
7596                         if (vmcs12->cr0_guest_host_mask &
7597                             (val ^ vmcs12->cr0_read_shadow))
7598                                 return true;
7599                         break;
7600                 case 3:
7601                         if ((vmcs12->cr3_target_count >= 1 &&
7602                                         vmcs12->cr3_target_value0 == val) ||
7603                                 (vmcs12->cr3_target_count >= 2 &&
7604                                         vmcs12->cr3_target_value1 == val) ||
7605                                 (vmcs12->cr3_target_count >= 3 &&
7606                                         vmcs12->cr3_target_value2 == val) ||
7607                                 (vmcs12->cr3_target_count >= 4 &&
7608                                         vmcs12->cr3_target_value3 == val))
7609                                 return false;
7610                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7611                                 return true;
7612                         break;
7613                 case 4:
7614                         if (vmcs12->cr4_guest_host_mask &
7615                             (vmcs12->cr4_read_shadow ^ val))
7616                                 return true;
7617                         break;
7618                 case 8:
7619                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7620                                 return true;
7621                         break;
7622                 }
7623                 break;
7624         case 2: /* clts */
7625                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7626                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7627                         return true;
7628                 break;
7629         case 1: /* mov from cr */
7630                 switch (cr) {
7631                 case 3:
7632                         if (vmcs12->cpu_based_vm_exec_control &
7633                             CPU_BASED_CR3_STORE_EXITING)
7634                                 return true;
7635                         break;
7636                 case 8:
7637                         if (vmcs12->cpu_based_vm_exec_control &
7638                             CPU_BASED_CR8_STORE_EXITING)
7639                                 return true;
7640                         break;
7641                 }
7642                 break;
7643         case 3: /* lmsw */
7644                 /*
7645                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7646                  * cr0. Other attempted changes are ignored, with no exit.
7647                  */
7648                 if (vmcs12->cr0_guest_host_mask & 0xe &
7649                     (val ^ vmcs12->cr0_read_shadow))
7650                         return true;
7651                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7652                     !(vmcs12->cr0_read_shadow & 0x1) &&
7653                     (val & 0x1))
7654                         return true;
7655                 break;
7656         }
7657         return false;
7658 }
7659
7660 /*
7661  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7662  * should handle it ourselves in L0 (and then continue L2). Only call this
7663  * when in is_guest_mode (L2).
7664  */
7665 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7666 {
7667         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7668         struct vcpu_vmx *vmx = to_vmx(vcpu);
7669         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7670         u32 exit_reason = vmx->exit_reason;
7671
7672         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7673                                 vmcs_readl(EXIT_QUALIFICATION),
7674                                 vmx->idt_vectoring_info,
7675                                 intr_info,
7676                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7677                                 KVM_ISA_VMX);
7678
7679         if (vmx->nested.nested_run_pending)
7680                 return false;
7681
7682         if (unlikely(vmx->fail)) {
7683                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7684                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7685                 return true;
7686         }
7687
7688         switch (exit_reason) {
7689         case EXIT_REASON_EXCEPTION_NMI:
7690                 if (!is_exception(intr_info))
7691                         return false;
7692                 else if (is_page_fault(intr_info))
7693                         return enable_ept;
7694                 else if (is_no_device(intr_info) &&
7695                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7696                         return false;
7697                 return vmcs12->exception_bitmap &
7698                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7699         case EXIT_REASON_EXTERNAL_INTERRUPT:
7700                 return false;
7701         case EXIT_REASON_TRIPLE_FAULT:
7702                 return true;
7703         case EXIT_REASON_PENDING_INTERRUPT:
7704                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7705         case EXIT_REASON_NMI_WINDOW:
7706                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7707         case EXIT_REASON_TASK_SWITCH:
7708                 return true;
7709         case EXIT_REASON_CPUID:
7710                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7711                         return false;
7712                 return true;
7713         case EXIT_REASON_HLT:
7714                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7715         case EXIT_REASON_INVD:
7716                 return true;
7717         case EXIT_REASON_INVLPG:
7718                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7719         case EXIT_REASON_RDPMC:
7720                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7721         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7722                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7723         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7724         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7725         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7726         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7727         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7728         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7729                 /*
7730                  * VMX instructions trap unconditionally. This allows L1 to
7731                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7732                  */
7733                 return true;
7734         case EXIT_REASON_CR_ACCESS:
7735                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7736         case EXIT_REASON_DR_ACCESS:
7737                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7738         case EXIT_REASON_IO_INSTRUCTION:
7739                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7740         case EXIT_REASON_MSR_READ:
7741         case EXIT_REASON_MSR_WRITE:
7742                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7743         case EXIT_REASON_INVALID_STATE:
7744                 return true;
7745         case EXIT_REASON_MWAIT_INSTRUCTION:
7746                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7747         case EXIT_REASON_MONITOR_TRAP_FLAG:
7748                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7749         case EXIT_REASON_MONITOR_INSTRUCTION:
7750                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7751         case EXIT_REASON_PAUSE_INSTRUCTION:
7752                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7753                         nested_cpu_has2(vmcs12,
7754                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7755         case EXIT_REASON_MCE_DURING_VMENTRY:
7756                 return false;
7757         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7758                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7759         case EXIT_REASON_APIC_ACCESS:
7760                 return nested_cpu_has2(vmcs12,
7761                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7762         case EXIT_REASON_APIC_WRITE:
7763         case EXIT_REASON_EOI_INDUCED:
7764                 /* apic_write and eoi_induced should exit unconditionally. */
7765                 return true;
7766         case EXIT_REASON_EPT_VIOLATION:
7767                 /*
7768                  * L0 always deals with the EPT violation. If nested EPT is
7769                  * used, and the nested mmu code discovers that the address is
7770                  * missing in the guest EPT table (EPT12), the EPT violation
7771                  * will be injected with nested_ept_inject_page_fault()
7772                  */
7773                 return false;
7774         case EXIT_REASON_EPT_MISCONFIG:
7775                 /*
7776                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7777                  * table (shadow on EPT) or a merged EPT table that L0 built
7778                  * (EPT on EPT). So any problems with the structure of the
7779                  * table is L0's fault.
7780                  */
7781                 return false;
7782         case EXIT_REASON_WBINVD:
7783                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7784         case EXIT_REASON_XSETBV:
7785                 return true;
7786         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7787                 /*
7788                  * This should never happen, since it is not possible to
7789                  * set XSS to a non-zero value---neither in L1 nor in L2.
7790                  * If if it were, XSS would have to be checked against
7791                  * the XSS exit bitmap in vmcs12.
7792                  */
7793                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7794         case EXIT_REASON_PCOMMIT:
7795                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7796         default:
7797                 return true;
7798         }
7799 }
7800
7801 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7802 {
7803         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7804         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7805 }
7806
7807 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7808 {
7809         struct page *pml_pg;
7810
7811         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7812         if (!pml_pg)
7813                 return -ENOMEM;
7814
7815         vmx->pml_pg = pml_pg;
7816
7817         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7818         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7819
7820         return 0;
7821 }
7822
7823 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7824 {
7825         if (vmx->pml_pg) {
7826                 __free_page(vmx->pml_pg);
7827                 vmx->pml_pg = NULL;
7828         }
7829 }
7830
7831 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7832 {
7833         struct vcpu_vmx *vmx = to_vmx(vcpu);
7834         u64 *pml_buf;
7835         u16 pml_idx;
7836
7837         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7838
7839         /* Do nothing if PML buffer is empty */
7840         if (pml_idx == (PML_ENTITY_NUM - 1))
7841                 return;
7842
7843         /* PML index always points to next available PML buffer entity */
7844         if (pml_idx >= PML_ENTITY_NUM)
7845                 pml_idx = 0;
7846         else
7847                 pml_idx++;
7848
7849         pml_buf = page_address(vmx->pml_pg);
7850         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7851                 u64 gpa;
7852
7853                 gpa = pml_buf[pml_idx];
7854                 WARN_ON(gpa & (PAGE_SIZE - 1));
7855                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7856         }
7857
7858         /* reset PML index */
7859         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7860 }
7861
7862 /*
7863  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7864  * Called before reporting dirty_bitmap to userspace.
7865  */
7866 static void kvm_flush_pml_buffers(struct kvm *kvm)
7867 {
7868         int i;
7869         struct kvm_vcpu *vcpu;
7870         /*
7871          * We only need to kick vcpu out of guest mode here, as PML buffer
7872          * is flushed at beginning of all VMEXITs, and it's obvious that only
7873          * vcpus running in guest are possible to have unflushed GPAs in PML
7874          * buffer.
7875          */
7876         kvm_for_each_vcpu(i, vcpu, kvm)
7877                 kvm_vcpu_kick(vcpu);
7878 }
7879
7880 static void vmx_dump_sel(char *name, uint32_t sel)
7881 {
7882         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7883                name, vmcs_read32(sel),
7884                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7885                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7886                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7887 }
7888
7889 static void vmx_dump_dtsel(char *name, uint32_t limit)
7890 {
7891         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7892                name, vmcs_read32(limit),
7893                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7894 }
7895
7896 static void dump_vmcs(void)
7897 {
7898         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7899         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7900         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7901         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7902         u32 secondary_exec_control = 0;
7903         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7904         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7905         int i, n;
7906
7907         if (cpu_has_secondary_exec_ctrls())
7908                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7909
7910         pr_err("*** Guest State ***\n");
7911         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7912                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7913                vmcs_readl(CR0_GUEST_HOST_MASK));
7914         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7915                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7916         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7917         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7918             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7919         {
7920                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7921                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7922                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7923                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7924         }
7925         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7926                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7927         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7928                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7929         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7930                vmcs_readl(GUEST_SYSENTER_ESP),
7931                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7932         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7933         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7934         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7935         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7936         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7937         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7938         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7939         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7940         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7941         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7942         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7943             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7944                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7945                        efer, vmcs_readl(GUEST_IA32_PAT));
7946         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7947                vmcs_readl(GUEST_IA32_DEBUGCTL),
7948                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7949         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7950                 pr_err("PerfGlobCtl = 0x%016lx\n",
7951                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7952         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7953                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7954         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7955                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7956                vmcs_read32(GUEST_ACTIVITY_STATE));
7957         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7958                 pr_err("InterruptStatus = %04x\n",
7959                        vmcs_read16(GUEST_INTR_STATUS));
7960
7961         pr_err("*** Host State ***\n");
7962         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7963                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7964         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7965                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
7966                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
7967                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
7968                vmcs_read16(HOST_TR_SELECTOR));
7969         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7970                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
7971                vmcs_readl(HOST_TR_BASE));
7972         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7973                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
7974         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7975                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
7976                vmcs_readl(HOST_CR4));
7977         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7978                vmcs_readl(HOST_IA32_SYSENTER_ESP),
7979                vmcs_read32(HOST_IA32_SYSENTER_CS),
7980                vmcs_readl(HOST_IA32_SYSENTER_EIP));
7981         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
7982                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
7983                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
7984         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7985                 pr_err("PerfGlobCtl = 0x%016lx\n",
7986                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
7987
7988         pr_err("*** Control State ***\n");
7989         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7990                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
7991         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
7992         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7993                vmcs_read32(EXCEPTION_BITMAP),
7994                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
7995                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
7996         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7997                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7998                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
7999                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8000         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8001                vmcs_read32(VM_EXIT_INTR_INFO),
8002                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8003                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8004         pr_err("        reason=%08x qualification=%016lx\n",
8005                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8006         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8007                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8008                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8009         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8010         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8011                 pr_err("TSC Multiplier = 0x%016lx\n",
8012                        vmcs_readl(TSC_MULTIPLIER));
8013         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8014                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8015         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8016                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8017         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8018                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8019         n = vmcs_read32(CR3_TARGET_COUNT);
8020         for (i = 0; i + 1 < n; i += 4)
8021                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8022                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8023                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8024         if (i < n)
8025                 pr_err("CR3 target%u=%016lx\n",
8026                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8027         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8028                 pr_err("PLE Gap=%08x Window=%08x\n",
8029                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8030         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8031                 pr_err("Virtual processor ID = 0x%04x\n",
8032                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8033 }
8034
8035 /*
8036  * The guest has exited.  See if we can fix it or if we need userspace
8037  * assistance.
8038  */
8039 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8040 {
8041         struct vcpu_vmx *vmx = to_vmx(vcpu);
8042         u32 exit_reason = vmx->exit_reason;
8043         u32 vectoring_info = vmx->idt_vectoring_info;
8044
8045         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8046
8047         /*
8048          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8049          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8050          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8051          * mode as if vcpus is in root mode, the PML buffer must has been
8052          * flushed already.
8053          */
8054         if (enable_pml)
8055                 vmx_flush_pml_buffer(vcpu);
8056
8057         /* If guest state is invalid, start emulating */
8058         if (vmx->emulation_required)
8059                 return handle_invalid_guest_state(vcpu);
8060
8061         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8062                 nested_vmx_vmexit(vcpu, exit_reason,
8063                                   vmcs_read32(VM_EXIT_INTR_INFO),
8064                                   vmcs_readl(EXIT_QUALIFICATION));
8065                 return 1;
8066         }
8067
8068         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8069                 dump_vmcs();
8070                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8071                 vcpu->run->fail_entry.hardware_entry_failure_reason
8072                         = exit_reason;
8073                 return 0;
8074         }
8075
8076         if (unlikely(vmx->fail)) {
8077                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8078                 vcpu->run->fail_entry.hardware_entry_failure_reason
8079                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8080                 return 0;
8081         }
8082
8083         /*
8084          * Note:
8085          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8086          * delivery event since it indicates guest is accessing MMIO.
8087          * The vm-exit can be triggered again after return to guest that
8088          * will cause infinite loop.
8089          */
8090         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8091                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8092                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8093                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8094                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8095                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8096                 vcpu->run->internal.ndata = 2;
8097                 vcpu->run->internal.data[0] = vectoring_info;
8098                 vcpu->run->internal.data[1] = exit_reason;
8099                 return 0;
8100         }
8101
8102         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8103             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8104                                         get_vmcs12(vcpu))))) {
8105                 if (vmx_interrupt_allowed(vcpu)) {
8106                         vmx->soft_vnmi_blocked = 0;
8107                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8108                            vcpu->arch.nmi_pending) {
8109                         /*
8110                          * This CPU don't support us in finding the end of an
8111                          * NMI-blocked window if the guest runs with IRQs
8112                          * disabled. So we pull the trigger after 1 s of
8113                          * futile waiting, but inform the user about this.
8114                          */
8115                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8116                                "state on VCPU %d after 1 s timeout\n",
8117                                __func__, vcpu->vcpu_id);
8118                         vmx->soft_vnmi_blocked = 0;
8119                 }
8120         }
8121
8122         if (exit_reason < kvm_vmx_max_exit_handlers
8123             && kvm_vmx_exit_handlers[exit_reason])
8124                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8125         else {
8126                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8127                 kvm_queue_exception(vcpu, UD_VECTOR);
8128                 return 1;
8129         }
8130 }
8131
8132 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8133 {
8134         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8135
8136         if (is_guest_mode(vcpu) &&
8137                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8138                 return;
8139
8140         if (irr == -1 || tpr < irr) {
8141                 vmcs_write32(TPR_THRESHOLD, 0);
8142                 return;
8143         }
8144
8145         vmcs_write32(TPR_THRESHOLD, irr);
8146 }
8147
8148 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8149 {
8150         u32 sec_exec_control;
8151
8152         /*
8153          * There is not point to enable virtualize x2apic without enable
8154          * apicv
8155          */
8156         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8157                                 !vmx_cpu_uses_apicv(vcpu))
8158                 return;
8159
8160         if (!cpu_need_tpr_shadow(vcpu))
8161                 return;
8162
8163         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8164
8165         if (set) {
8166                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8167                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8168         } else {
8169                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8170                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8171         }
8172         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8173
8174         vmx_set_msr_bitmap(vcpu);
8175 }
8176
8177 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8178 {
8179         struct vcpu_vmx *vmx = to_vmx(vcpu);
8180
8181         /*
8182          * Currently we do not handle the nested case where L2 has an
8183          * APIC access page of its own; that page is still pinned.
8184          * Hence, we skip the case where the VCPU is in guest mode _and_
8185          * L1 prepared an APIC access page for L2.
8186          *
8187          * For the case where L1 and L2 share the same APIC access page
8188          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8189          * in the vmcs12), this function will only update either the vmcs01
8190          * or the vmcs02.  If the former, the vmcs02 will be updated by
8191          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8192          * the next L2->L1 exit.
8193          */
8194         if (!is_guest_mode(vcpu) ||
8195             !nested_cpu_has2(vmx->nested.current_vmcs12,
8196                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8197                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8198 }
8199
8200 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8201 {
8202         u16 status;
8203         u8 old;
8204
8205         if (isr == -1)
8206                 isr = 0;
8207
8208         status = vmcs_read16(GUEST_INTR_STATUS);
8209         old = status >> 8;
8210         if (isr != old) {
8211                 status &= 0xff;
8212                 status |= isr << 8;
8213                 vmcs_write16(GUEST_INTR_STATUS, status);
8214         }
8215 }
8216
8217 static void vmx_set_rvi(int vector)
8218 {
8219         u16 status;
8220         u8 old;
8221
8222         if (vector == -1)
8223                 vector = 0;
8224
8225         status = vmcs_read16(GUEST_INTR_STATUS);
8226         old = (u8)status & 0xff;
8227         if ((u8)vector != old) {
8228                 status &= ~0xff;
8229                 status |= (u8)vector;
8230                 vmcs_write16(GUEST_INTR_STATUS, status);
8231         }
8232 }
8233
8234 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8235 {
8236         if (!is_guest_mode(vcpu)) {
8237                 vmx_set_rvi(max_irr);
8238                 return;
8239         }
8240
8241         if (max_irr == -1)
8242                 return;
8243
8244         /*
8245          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8246          * handles it.
8247          */
8248         if (nested_exit_on_intr(vcpu))
8249                 return;
8250
8251         /*
8252          * Else, fall back to pre-APICv interrupt injection since L2
8253          * is run without virtual interrupt delivery.
8254          */
8255         if (!kvm_event_needs_reinjection(vcpu) &&
8256             vmx_interrupt_allowed(vcpu)) {
8257                 kvm_queue_interrupt(vcpu, max_irr, false);
8258                 vmx_inject_irq(vcpu);
8259         }
8260 }
8261
8262 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8263 {
8264         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8265         if (!vmx_cpu_uses_apicv(vcpu))
8266                 return;
8267
8268         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8269         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8270         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8271         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8272 }
8273
8274 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8275 {
8276         u32 exit_intr_info;
8277
8278         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8279               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8280                 return;
8281
8282         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8283         exit_intr_info = vmx->exit_intr_info;
8284
8285         /* Handle machine checks before interrupts are enabled */
8286         if (is_machine_check(exit_intr_info))
8287                 kvm_machine_check();
8288
8289         /* We need to handle NMIs before interrupts are enabled */
8290         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8291             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8292                 kvm_before_handle_nmi(&vmx->vcpu);
8293                 asm("int $2");
8294                 kvm_after_handle_nmi(&vmx->vcpu);
8295         }
8296 }
8297
8298 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8299 {
8300         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8301
8302         /*
8303          * If external interrupt exists, IF bit is set in rflags/eflags on the
8304          * interrupt stack frame, and interrupt will be enabled on a return
8305          * from interrupt handler.
8306          */
8307         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8308                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8309                 unsigned int vector;
8310                 unsigned long entry;
8311                 gate_desc *desc;
8312                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8313 #ifdef CONFIG_X86_64
8314                 unsigned long tmp;
8315 #endif
8316
8317                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8318                 desc = (gate_desc *)vmx->host_idt_base + vector;
8319                 entry = gate_offset(*desc);
8320                 asm volatile(
8321 #ifdef CONFIG_X86_64
8322                         "mov %%" _ASM_SP ", %[sp]\n\t"
8323                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8324                         "push $%c[ss]\n\t"
8325                         "push %[sp]\n\t"
8326 #endif
8327                         "pushf\n\t"
8328                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8329                         __ASM_SIZE(push) " $%c[cs]\n\t"
8330                         "call *%[entry]\n\t"
8331                         :
8332 #ifdef CONFIG_X86_64
8333                         [sp]"=&r"(tmp)
8334 #endif
8335                         :
8336                         [entry]"r"(entry),
8337                         [ss]"i"(__KERNEL_DS),
8338                         [cs]"i"(__KERNEL_CS)
8339                         );
8340         } else
8341                 local_irq_enable();
8342 }
8343
8344 static bool vmx_has_high_real_mode_segbase(void)
8345 {
8346         return enable_unrestricted_guest || emulate_invalid_guest_state;
8347 }
8348
8349 static bool vmx_mpx_supported(void)
8350 {
8351         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8352                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8353 }
8354
8355 static bool vmx_xsaves_supported(void)
8356 {
8357         return vmcs_config.cpu_based_2nd_exec_ctrl &
8358                 SECONDARY_EXEC_XSAVES;
8359 }
8360
8361 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8362 {
8363         u32 exit_intr_info;
8364         bool unblock_nmi;
8365         u8 vector;
8366         bool idtv_info_valid;
8367
8368         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8369
8370         if (cpu_has_virtual_nmis()) {
8371                 if (vmx->nmi_known_unmasked)
8372                         return;
8373                 /*
8374                  * Can't use vmx->exit_intr_info since we're not sure what
8375                  * the exit reason is.
8376                  */
8377                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8378                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8379                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8380                 /*
8381                  * SDM 3: 27.7.1.2 (September 2008)
8382                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8383                  * a guest IRET fault.
8384                  * SDM 3: 23.2.2 (September 2008)
8385                  * Bit 12 is undefined in any of the following cases:
8386                  *  If the VM exit sets the valid bit in the IDT-vectoring
8387                  *   information field.
8388                  *  If the VM exit is due to a double fault.
8389                  */
8390                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8391                     vector != DF_VECTOR && !idtv_info_valid)
8392                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8393                                       GUEST_INTR_STATE_NMI);
8394                 else
8395                         vmx->nmi_known_unmasked =
8396                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8397                                   & GUEST_INTR_STATE_NMI);
8398         } else if (unlikely(vmx->soft_vnmi_blocked))
8399                 vmx->vnmi_blocked_time +=
8400                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8401 }
8402
8403 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8404                                       u32 idt_vectoring_info,
8405                                       int instr_len_field,
8406                                       int error_code_field)
8407 {
8408         u8 vector;
8409         int type;
8410         bool idtv_info_valid;
8411
8412         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8413
8414         vcpu->arch.nmi_injected = false;
8415         kvm_clear_exception_queue(vcpu);
8416         kvm_clear_interrupt_queue(vcpu);
8417
8418         if (!idtv_info_valid)
8419                 return;
8420
8421         kvm_make_request(KVM_REQ_EVENT, vcpu);
8422
8423         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8424         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8425
8426         switch (type) {
8427         case INTR_TYPE_NMI_INTR:
8428                 vcpu->arch.nmi_injected = true;
8429                 /*
8430                  * SDM 3: 27.7.1.2 (September 2008)
8431                  * Clear bit "block by NMI" before VM entry if a NMI
8432                  * delivery faulted.
8433                  */
8434                 vmx_set_nmi_mask(vcpu, false);
8435                 break;
8436         case INTR_TYPE_SOFT_EXCEPTION:
8437                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8438                 /* fall through */
8439         case INTR_TYPE_HARD_EXCEPTION:
8440                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8441                         u32 err = vmcs_read32(error_code_field);
8442                         kvm_requeue_exception_e(vcpu, vector, err);
8443                 } else
8444                         kvm_requeue_exception(vcpu, vector);
8445                 break;
8446         case INTR_TYPE_SOFT_INTR:
8447                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8448                 /* fall through */
8449         case INTR_TYPE_EXT_INTR:
8450                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8451                 break;
8452         default:
8453                 break;
8454         }
8455 }
8456
8457 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8458 {
8459         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8460                                   VM_EXIT_INSTRUCTION_LEN,
8461                                   IDT_VECTORING_ERROR_CODE);
8462 }
8463
8464 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8465 {
8466         __vmx_complete_interrupts(vcpu,
8467                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8468                                   VM_ENTRY_INSTRUCTION_LEN,
8469                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8470
8471         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8472 }
8473
8474 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8475 {
8476         int i, nr_msrs;
8477         struct perf_guest_switch_msr *msrs;
8478
8479         msrs = perf_guest_get_msrs(&nr_msrs);
8480
8481         if (!msrs)
8482                 return;
8483
8484         for (i = 0; i < nr_msrs; i++)
8485                 if (msrs[i].host == msrs[i].guest)
8486                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8487                 else
8488                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8489                                         msrs[i].host);
8490 }
8491
8492 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8493 {
8494         struct vcpu_vmx *vmx = to_vmx(vcpu);
8495         unsigned long debugctlmsr, cr4;
8496
8497         /* Record the guest's net vcpu time for enforced NMI injections. */
8498         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8499                 vmx->entry_time = ktime_get();
8500
8501         /* Don't enter VMX if guest state is invalid, let the exit handler
8502            start emulation until we arrive back to a valid state */
8503         if (vmx->emulation_required)
8504                 return;
8505
8506         if (vmx->ple_window_dirty) {
8507                 vmx->ple_window_dirty = false;
8508                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8509         }
8510
8511         if (vmx->nested.sync_shadow_vmcs) {
8512                 copy_vmcs12_to_shadow(vmx);
8513                 vmx->nested.sync_shadow_vmcs = false;
8514         }
8515
8516         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8517                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8518         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8519                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8520
8521         cr4 = cr4_read_shadow();
8522         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8523                 vmcs_writel(HOST_CR4, cr4);
8524                 vmx->host_state.vmcs_host_cr4 = cr4;
8525         }
8526
8527         /* When single-stepping over STI and MOV SS, we must clear the
8528          * corresponding interruptibility bits in the guest state. Otherwise
8529          * vmentry fails as it then expects bit 14 (BS) in pending debug
8530          * exceptions being set, but that's not correct for the guest debugging
8531          * case. */
8532         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8533                 vmx_set_interrupt_shadow(vcpu, 0);
8534
8535         atomic_switch_perf_msrs(vmx);
8536         debugctlmsr = get_debugctlmsr();
8537
8538         vmx->__launched = vmx->loaded_vmcs->launched;
8539         asm(
8540                 /* Store host registers */
8541                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8542                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8543                 "push %%" _ASM_CX " \n\t"
8544                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8545                 "je 1f \n\t"
8546                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8547                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8548                 "1: \n\t"
8549                 /* Reload cr2 if changed */
8550                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8551                 "mov %%cr2, %%" _ASM_DX " \n\t"
8552                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8553                 "je 2f \n\t"
8554                 "mov %%" _ASM_AX", %%cr2 \n\t"
8555                 "2: \n\t"
8556                 /* Check if vmlaunch of vmresume is needed */
8557                 "cmpl $0, %c[launched](%0) \n\t"
8558                 /* Load guest registers.  Don't clobber flags. */
8559                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8560                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8561                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8562                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8563                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8564                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8565 #ifdef CONFIG_X86_64
8566                 "mov %c[r8](%0),  %%r8  \n\t"
8567                 "mov %c[r9](%0),  %%r9  \n\t"
8568                 "mov %c[r10](%0), %%r10 \n\t"
8569                 "mov %c[r11](%0), %%r11 \n\t"
8570                 "mov %c[r12](%0), %%r12 \n\t"
8571                 "mov %c[r13](%0), %%r13 \n\t"
8572                 "mov %c[r14](%0), %%r14 \n\t"
8573                 "mov %c[r15](%0), %%r15 \n\t"
8574 #endif
8575                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8576
8577                 /* Enter guest mode */
8578                 "jne 1f \n\t"
8579                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8580                 "jmp 2f \n\t"
8581                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8582                 "2: "
8583                 /* Save guest registers, load host registers, keep flags */
8584                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8585                 "pop %0 \n\t"
8586                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8587                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8588                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8589                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8590                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8591                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8592                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8593 #ifdef CONFIG_X86_64
8594                 "mov %%r8,  %c[r8](%0) \n\t"
8595                 "mov %%r9,  %c[r9](%0) \n\t"
8596                 "mov %%r10, %c[r10](%0) \n\t"
8597                 "mov %%r11, %c[r11](%0) \n\t"
8598                 "mov %%r12, %c[r12](%0) \n\t"
8599                 "mov %%r13, %c[r13](%0) \n\t"
8600                 "mov %%r14, %c[r14](%0) \n\t"
8601                 "mov %%r15, %c[r15](%0) \n\t"
8602 #endif
8603                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8604                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8605
8606                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8607                 "setbe %c[fail](%0) \n\t"
8608                 ".pushsection .rodata \n\t"
8609                 ".global vmx_return \n\t"
8610                 "vmx_return: " _ASM_PTR " 2b \n\t"
8611                 ".popsection"
8612               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8613                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8614                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8615                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8616                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8617                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8618                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8619                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8620                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8621                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8622                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8623 #ifdef CONFIG_X86_64
8624                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8625                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8626                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8627                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8628                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8629                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8630                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8631                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8632 #endif
8633                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8634                 [wordsize]"i"(sizeof(ulong))
8635               : "cc", "memory"
8636 #ifdef CONFIG_X86_64
8637                 , "rax", "rbx", "rdi", "rsi"
8638                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8639 #else
8640                 , "eax", "ebx", "edi", "esi"
8641 #endif
8642               );
8643
8644         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8645         if (debugctlmsr)
8646                 update_debugctlmsr(debugctlmsr);
8647
8648 #ifndef CONFIG_X86_64
8649         /*
8650          * The sysexit path does not restore ds/es, so we must set them to
8651          * a reasonable value ourselves.
8652          *
8653          * We can't defer this to vmx_load_host_state() since that function
8654          * may be executed in interrupt context, which saves and restore segments
8655          * around it, nullifying its effect.
8656          */
8657         loadsegment(ds, __USER_DS);
8658         loadsegment(es, __USER_DS);
8659 #endif
8660
8661         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8662                                   | (1 << VCPU_EXREG_RFLAGS)
8663                                   | (1 << VCPU_EXREG_PDPTR)
8664                                   | (1 << VCPU_EXREG_SEGMENTS)
8665                                   | (1 << VCPU_EXREG_CR3));
8666         vcpu->arch.regs_dirty = 0;
8667
8668         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8669
8670         vmx->loaded_vmcs->launched = 1;
8671
8672         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8673
8674         /*
8675          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8676          * we did not inject a still-pending event to L1 now because of
8677          * nested_run_pending, we need to re-enable this bit.
8678          */
8679         if (vmx->nested.nested_run_pending)
8680                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8681
8682         vmx->nested.nested_run_pending = 0;
8683
8684         vmx_complete_atomic_exit(vmx);
8685         vmx_recover_nmi_blocking(vmx);
8686         vmx_complete_interrupts(vmx);
8687 }
8688
8689 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8690 {
8691         struct vcpu_vmx *vmx = to_vmx(vcpu);
8692         int cpu;
8693
8694         if (vmx->loaded_vmcs == &vmx->vmcs01)
8695                 return;
8696
8697         cpu = get_cpu();
8698         vmx->loaded_vmcs = &vmx->vmcs01;
8699         vmx_vcpu_put(vcpu);
8700         vmx_vcpu_load(vcpu, cpu);
8701         vcpu->cpu = cpu;
8702         put_cpu();
8703 }
8704
8705 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8706 {
8707         struct vcpu_vmx *vmx = to_vmx(vcpu);
8708
8709         if (enable_pml)
8710                 vmx_destroy_pml_buffer(vmx);
8711         free_vpid(vmx->vpid);
8712         leave_guest_mode(vcpu);
8713         vmx_load_vmcs01(vcpu);
8714         free_nested(vmx);
8715         free_loaded_vmcs(vmx->loaded_vmcs);
8716         kfree(vmx->guest_msrs);
8717         kvm_vcpu_uninit(vcpu);
8718         kmem_cache_free(kvm_vcpu_cache, vmx);
8719 }
8720
8721 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8722 {
8723         int err;
8724         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8725         int cpu;
8726
8727         if (!vmx)
8728                 return ERR_PTR(-ENOMEM);
8729
8730         vmx->vpid = allocate_vpid();
8731
8732         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8733         if (err)
8734                 goto free_vcpu;
8735
8736         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8737         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8738                      > PAGE_SIZE);
8739
8740         err = -ENOMEM;
8741         if (!vmx->guest_msrs) {
8742                 goto uninit_vcpu;
8743         }
8744
8745         vmx->loaded_vmcs = &vmx->vmcs01;
8746         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8747         if (!vmx->loaded_vmcs->vmcs)
8748                 goto free_msrs;
8749         if (!vmm_exclusive)
8750                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8751         loaded_vmcs_init(vmx->loaded_vmcs);
8752         if (!vmm_exclusive)
8753                 kvm_cpu_vmxoff();
8754
8755         cpu = get_cpu();
8756         vmx_vcpu_load(&vmx->vcpu, cpu);
8757         vmx->vcpu.cpu = cpu;
8758         err = vmx_vcpu_setup(vmx);
8759         vmx_vcpu_put(&vmx->vcpu);
8760         put_cpu();
8761         if (err)
8762                 goto free_vmcs;
8763         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8764                 err = alloc_apic_access_page(kvm);
8765                 if (err)
8766                         goto free_vmcs;
8767         }
8768
8769         if (enable_ept) {
8770                 if (!kvm->arch.ept_identity_map_addr)
8771                         kvm->arch.ept_identity_map_addr =
8772                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8773                 err = init_rmode_identity_map(kvm);
8774                 if (err)
8775                         goto free_vmcs;
8776         }
8777
8778         if (nested) {
8779                 nested_vmx_setup_ctls_msrs(vmx);
8780                 vmx->nested.vpid02 = allocate_vpid();
8781         }
8782
8783         vmx->nested.posted_intr_nv = -1;
8784         vmx->nested.current_vmptr = -1ull;
8785         vmx->nested.current_vmcs12 = NULL;
8786
8787         /*
8788          * If PML is turned on, failure on enabling PML just results in failure
8789          * of creating the vcpu, therefore we can simplify PML logic (by
8790          * avoiding dealing with cases, such as enabling PML partially on vcpus
8791          * for the guest, etc.
8792          */
8793         if (enable_pml) {
8794                 err = vmx_create_pml_buffer(vmx);
8795                 if (err)
8796                         goto free_vmcs;
8797         }
8798
8799         return &vmx->vcpu;
8800
8801 free_vmcs:
8802         free_vpid(vmx->nested.vpid02);
8803         free_loaded_vmcs(vmx->loaded_vmcs);
8804 free_msrs:
8805         kfree(vmx->guest_msrs);
8806 uninit_vcpu:
8807         kvm_vcpu_uninit(&vmx->vcpu);
8808 free_vcpu:
8809         free_vpid(vmx->vpid);
8810         kmem_cache_free(kvm_vcpu_cache, vmx);
8811         return ERR_PTR(err);
8812 }
8813
8814 static void __init vmx_check_processor_compat(void *rtn)
8815 {
8816         struct vmcs_config vmcs_conf;
8817
8818         *(int *)rtn = 0;
8819         if (setup_vmcs_config(&vmcs_conf) < 0)
8820                 *(int *)rtn = -EIO;
8821         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8822                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8823                                 smp_processor_id());
8824                 *(int *)rtn = -EIO;
8825         }
8826 }
8827
8828 static int get_ept_level(void)
8829 {
8830         return VMX_EPT_DEFAULT_GAW + 1;
8831 }
8832
8833 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8834 {
8835         u8 cache;
8836         u64 ipat = 0;
8837
8838         /* For VT-d and EPT combination
8839          * 1. MMIO: always map as UC
8840          * 2. EPT with VT-d:
8841          *   a. VT-d without snooping control feature: can't guarantee the
8842          *      result, try to trust guest.
8843          *   b. VT-d with snooping control feature: snooping control feature of
8844          *      VT-d engine can guarantee the cache correctness. Just set it
8845          *      to WB to keep consistent with host. So the same as item 3.
8846          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8847          *    consistent with host MTRR
8848          */
8849         if (is_mmio) {
8850                 cache = MTRR_TYPE_UNCACHABLE;
8851                 goto exit;
8852         }
8853
8854         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8855                 ipat = VMX_EPT_IPAT_BIT;
8856                 cache = MTRR_TYPE_WRBACK;
8857                 goto exit;
8858         }
8859
8860         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8861                 ipat = VMX_EPT_IPAT_BIT;
8862                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8863                         cache = MTRR_TYPE_WRBACK;
8864                 else
8865                         cache = MTRR_TYPE_UNCACHABLE;
8866                 goto exit;
8867         }
8868
8869         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8870
8871 exit:
8872         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8873 }
8874
8875 static int vmx_get_lpage_level(void)
8876 {
8877         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8878                 return PT_DIRECTORY_LEVEL;
8879         else
8880                 /* For shadow and EPT supported 1GB page */
8881                 return PT_PDPE_LEVEL;
8882 }
8883
8884 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8885 {
8886         /*
8887          * These bits in the secondary execution controls field
8888          * are dynamic, the others are mostly based on the hypervisor
8889          * architecture and the guest's CPUID.  Do not touch the
8890          * dynamic bits.
8891          */
8892         u32 mask =
8893                 SECONDARY_EXEC_SHADOW_VMCS |
8894                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8895                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8896
8897         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8898
8899         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8900                      (new_ctl & ~mask) | (cur_ctl & mask));
8901 }
8902
8903 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8904 {
8905         struct kvm_cpuid_entry2 *best;
8906         struct vcpu_vmx *vmx = to_vmx(vcpu);
8907         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8908
8909         if (vmx_rdtscp_supported()) {
8910                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8911                 if (!rdtscp_enabled)
8912                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8913
8914                 if (nested) {
8915                         if (rdtscp_enabled)
8916                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8917                                         SECONDARY_EXEC_RDTSCP;
8918                         else
8919                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8920                                         ~SECONDARY_EXEC_RDTSCP;
8921                 }
8922         }
8923
8924         /* Exposing INVPCID only when PCID is exposed */
8925         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8926         if (vmx_invpcid_supported() &&
8927             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8928             !guest_cpuid_has_pcid(vcpu))) {
8929                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8930
8931                 if (best)
8932                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8933         }
8934
8935         vmcs_set_secondary_exec_control(secondary_exec_ctl);
8936
8937         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8938                 if (guest_cpuid_has_pcommit(vcpu))
8939                         vmx->nested.nested_vmx_secondary_ctls_high |=
8940                                 SECONDARY_EXEC_PCOMMIT;
8941                 else
8942                         vmx->nested.nested_vmx_secondary_ctls_high &=
8943                                 ~SECONDARY_EXEC_PCOMMIT;
8944         }
8945 }
8946
8947 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8948 {
8949         if (func == 1 && nested)
8950                 entry->ecx |= bit(X86_FEATURE_VMX);
8951 }
8952
8953 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8954                 struct x86_exception *fault)
8955 {
8956         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8957         u32 exit_reason;
8958
8959         if (fault->error_code & PFERR_RSVD_MASK)
8960                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8961         else
8962                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8963         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
8964         vmcs12->guest_physical_address = fault->address;
8965 }
8966
8967 /* Callbacks for nested_ept_init_mmu_context: */
8968
8969 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8970 {
8971         /* return the page table to be shadowed - in our case, EPT12 */
8972         return get_vmcs12(vcpu)->ept_pointer;
8973 }
8974
8975 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
8976 {
8977         WARN_ON(mmu_is_nested(vcpu));
8978         kvm_init_shadow_ept_mmu(vcpu,
8979                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
8980                         VMX_EPT_EXECUTE_ONLY_BIT);
8981         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
8982         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
8983         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8984
8985         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
8986 }
8987
8988 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8989 {
8990         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8991 }
8992
8993 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8994                                             u16 error_code)
8995 {
8996         bool inequality, bit;
8997
8998         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8999         inequality =
9000                 (error_code & vmcs12->page_fault_error_code_mask) !=
9001                  vmcs12->page_fault_error_code_match;
9002         return inequality ^ bit;
9003 }
9004
9005 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9006                 struct x86_exception *fault)
9007 {
9008         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9009
9010         WARN_ON(!is_guest_mode(vcpu));
9011
9012         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9013                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9014                                   vmcs_read32(VM_EXIT_INTR_INFO),
9015                                   vmcs_readl(EXIT_QUALIFICATION));
9016         else
9017                 kvm_inject_page_fault(vcpu, fault);
9018 }
9019
9020 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9021                                         struct vmcs12 *vmcs12)
9022 {
9023         struct vcpu_vmx *vmx = to_vmx(vcpu);
9024         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9025
9026         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9027                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9028                     vmcs12->apic_access_addr >> maxphyaddr)
9029                         return false;
9030
9031                 /*
9032                  * Translate L1 physical address to host physical
9033                  * address for vmcs02. Keep the page pinned, so this
9034                  * physical address remains valid. We keep a reference
9035                  * to it so we can release it later.
9036                  */
9037                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9038                         nested_release_page(vmx->nested.apic_access_page);
9039                 vmx->nested.apic_access_page =
9040                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9041         }
9042
9043         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9044                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9045                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9046                         return false;
9047
9048                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9049                         nested_release_page(vmx->nested.virtual_apic_page);
9050                 vmx->nested.virtual_apic_page =
9051                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9052
9053                 /*
9054                  * Failing the vm entry is _not_ what the processor does
9055                  * but it's basically the only possibility we have.
9056                  * We could still enter the guest if CR8 load exits are
9057                  * enabled, CR8 store exits are enabled, and virtualize APIC
9058                  * access is disabled; in this case the processor would never
9059                  * use the TPR shadow and we could simply clear the bit from
9060                  * the execution control.  But such a configuration is useless,
9061                  * so let's keep the code simple.
9062                  */
9063                 if (!vmx->nested.virtual_apic_page)
9064                         return false;
9065         }
9066
9067         if (nested_cpu_has_posted_intr(vmcs12)) {
9068                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9069                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9070                         return false;
9071
9072                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9073                         kunmap(vmx->nested.pi_desc_page);
9074                         nested_release_page(vmx->nested.pi_desc_page);
9075                 }
9076                 vmx->nested.pi_desc_page =
9077                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9078                 if (!vmx->nested.pi_desc_page)
9079                         return false;
9080
9081                 vmx->nested.pi_desc =
9082                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9083                 if (!vmx->nested.pi_desc) {
9084                         nested_release_page_clean(vmx->nested.pi_desc_page);
9085                         return false;
9086                 }
9087                 vmx->nested.pi_desc =
9088                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9089                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9090                         (PAGE_SIZE - 1)));
9091         }
9092
9093         return true;
9094 }
9095
9096 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9097 {
9098         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9099         struct vcpu_vmx *vmx = to_vmx(vcpu);
9100
9101         if (vcpu->arch.virtual_tsc_khz == 0)
9102                 return;
9103
9104         /* Make sure short timeouts reliably trigger an immediate vmexit.
9105          * hrtimer_start does not guarantee this. */
9106         if (preemption_timeout <= 1) {
9107                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9108                 return;
9109         }
9110
9111         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9112         preemption_timeout *= 1000000;
9113         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9114         hrtimer_start(&vmx->nested.preemption_timer,
9115                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9116 }
9117
9118 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9119                                                 struct vmcs12 *vmcs12)
9120 {
9121         int maxphyaddr;
9122         u64 addr;
9123
9124         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9125                 return 0;
9126
9127         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9128                 WARN_ON(1);
9129                 return -EINVAL;
9130         }
9131         maxphyaddr = cpuid_maxphyaddr(vcpu);
9132
9133         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9134            ((addr + PAGE_SIZE) >> maxphyaddr))
9135                 return -EINVAL;
9136
9137         return 0;
9138 }
9139
9140 /*
9141  * Merge L0's and L1's MSR bitmap, return false to indicate that
9142  * we do not use the hardware.
9143  */
9144 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9145                                                struct vmcs12 *vmcs12)
9146 {
9147         int msr;
9148         struct page *page;
9149         unsigned long *msr_bitmap;
9150
9151         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9152                 return false;
9153
9154         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9155         if (!page) {
9156                 WARN_ON(1);
9157                 return false;
9158         }
9159         msr_bitmap = (unsigned long *)kmap(page);
9160         if (!msr_bitmap) {
9161                 nested_release_page_clean(page);
9162                 WARN_ON(1);
9163                 return false;
9164         }
9165
9166         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9167                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9168                         for (msr = 0x800; msr <= 0x8ff; msr++)
9169                                 nested_vmx_disable_intercept_for_msr(
9170                                         msr_bitmap,
9171                                         vmx_msr_bitmap_nested,
9172                                         msr, MSR_TYPE_R);
9173                 /* TPR is allowed */
9174                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9175                                 vmx_msr_bitmap_nested,
9176                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9177                                 MSR_TYPE_R | MSR_TYPE_W);
9178                 if (nested_cpu_has_vid(vmcs12)) {
9179                         /* EOI and self-IPI are allowed */
9180                         nested_vmx_disable_intercept_for_msr(
9181                                 msr_bitmap,
9182                                 vmx_msr_bitmap_nested,
9183                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9184                                 MSR_TYPE_W);
9185                         nested_vmx_disable_intercept_for_msr(
9186                                 msr_bitmap,
9187                                 vmx_msr_bitmap_nested,
9188                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9189                                 MSR_TYPE_W);
9190                 }
9191         } else {
9192                 /*
9193                  * Enable reading intercept of all the x2apic
9194                  * MSRs. We should not rely on vmcs12 to do any
9195                  * optimizations here, it may have been modified
9196                  * by L1.
9197                  */
9198                 for (msr = 0x800; msr <= 0x8ff; msr++)
9199                         __vmx_enable_intercept_for_msr(
9200                                 vmx_msr_bitmap_nested,
9201                                 msr,
9202                                 MSR_TYPE_R);
9203
9204                 __vmx_enable_intercept_for_msr(
9205                                 vmx_msr_bitmap_nested,
9206                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9207                                 MSR_TYPE_W);
9208                 __vmx_enable_intercept_for_msr(
9209                                 vmx_msr_bitmap_nested,
9210                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9211                                 MSR_TYPE_W);
9212                 __vmx_enable_intercept_for_msr(
9213                                 vmx_msr_bitmap_nested,
9214                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9215                                 MSR_TYPE_W);
9216         }
9217         kunmap(page);
9218         nested_release_page_clean(page);
9219
9220         return true;
9221 }
9222
9223 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9224                                            struct vmcs12 *vmcs12)
9225 {
9226         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9227             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9228             !nested_cpu_has_vid(vmcs12) &&
9229             !nested_cpu_has_posted_intr(vmcs12))
9230                 return 0;
9231
9232         /*
9233          * If virtualize x2apic mode is enabled,
9234          * virtualize apic access must be disabled.
9235          */
9236         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9237             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9238                 return -EINVAL;
9239
9240         /*
9241          * If virtual interrupt delivery is enabled,
9242          * we must exit on external interrupts.
9243          */
9244         if (nested_cpu_has_vid(vmcs12) &&
9245            !nested_exit_on_intr(vcpu))
9246                 return -EINVAL;
9247
9248         /*
9249          * bits 15:8 should be zero in posted_intr_nv,
9250          * the descriptor address has been already checked
9251          * in nested_get_vmcs12_pages.
9252          */
9253         if (nested_cpu_has_posted_intr(vmcs12) &&
9254            (!nested_cpu_has_vid(vmcs12) ||
9255             !nested_exit_intr_ack_set(vcpu) ||
9256             vmcs12->posted_intr_nv & 0xff00))
9257                 return -EINVAL;
9258
9259         /* tpr shadow is needed by all apicv features. */
9260         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9261                 return -EINVAL;
9262
9263         return 0;
9264 }
9265
9266 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9267                                        unsigned long count_field,
9268                                        unsigned long addr_field)
9269 {
9270         int maxphyaddr;
9271         u64 count, addr;
9272
9273         if (vmcs12_read_any(vcpu, count_field, &count) ||
9274             vmcs12_read_any(vcpu, addr_field, &addr)) {
9275                 WARN_ON(1);
9276                 return -EINVAL;
9277         }
9278         if (count == 0)
9279                 return 0;
9280         maxphyaddr = cpuid_maxphyaddr(vcpu);
9281         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9282             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9283                 pr_warn_ratelimited(
9284                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9285                         addr_field, maxphyaddr, count, addr);
9286                 return -EINVAL;
9287         }
9288         return 0;
9289 }
9290
9291 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9292                                                 struct vmcs12 *vmcs12)
9293 {
9294         if (vmcs12->vm_exit_msr_load_count == 0 &&
9295             vmcs12->vm_exit_msr_store_count == 0 &&
9296             vmcs12->vm_entry_msr_load_count == 0)
9297                 return 0; /* Fast path */
9298         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9299                                         VM_EXIT_MSR_LOAD_ADDR) ||
9300             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9301                                         VM_EXIT_MSR_STORE_ADDR) ||
9302             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9303                                         VM_ENTRY_MSR_LOAD_ADDR))
9304                 return -EINVAL;
9305         return 0;
9306 }
9307
9308 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9309                                        struct vmx_msr_entry *e)
9310 {
9311         /* x2APIC MSR accesses are not allowed */
9312         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9313                 return -EINVAL;
9314         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9315             e->index == MSR_IA32_UCODE_REV)
9316                 return -EINVAL;
9317         if (e->reserved != 0)
9318                 return -EINVAL;
9319         return 0;
9320 }
9321
9322 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9323                                      struct vmx_msr_entry *e)
9324 {
9325         if (e->index == MSR_FS_BASE ||
9326             e->index == MSR_GS_BASE ||
9327             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9328             nested_vmx_msr_check_common(vcpu, e))
9329                 return -EINVAL;
9330         return 0;
9331 }
9332
9333 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9334                                       struct vmx_msr_entry *e)
9335 {
9336         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9337             nested_vmx_msr_check_common(vcpu, e))
9338                 return -EINVAL;
9339         return 0;
9340 }
9341
9342 /*
9343  * Load guest's/host's msr at nested entry/exit.
9344  * return 0 for success, entry index for failure.
9345  */
9346 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9347 {
9348         u32 i;
9349         struct vmx_msr_entry e;
9350         struct msr_data msr;
9351
9352         msr.host_initiated = false;
9353         for (i = 0; i < count; i++) {
9354                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9355                                         &e, sizeof(e))) {
9356                         pr_warn_ratelimited(
9357                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9358                                 __func__, i, gpa + i * sizeof(e));
9359                         goto fail;
9360                 }
9361                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9362                         pr_warn_ratelimited(
9363                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9364                                 __func__, i, e.index, e.reserved);
9365                         goto fail;
9366                 }
9367                 msr.index = e.index;
9368                 msr.data = e.value;
9369                 if (kvm_set_msr(vcpu, &msr)) {
9370                         pr_warn_ratelimited(
9371                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9372                                 __func__, i, e.index, e.value);
9373                         goto fail;
9374                 }
9375         }
9376         return 0;
9377 fail:
9378         return i + 1;
9379 }
9380
9381 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9382 {
9383         u32 i;
9384         struct vmx_msr_entry e;
9385
9386         for (i = 0; i < count; i++) {
9387                 struct msr_data msr_info;
9388                 if (kvm_vcpu_read_guest(vcpu,
9389                                         gpa + i * sizeof(e),
9390                                         &e, 2 * sizeof(u32))) {
9391                         pr_warn_ratelimited(
9392                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9393                                 __func__, i, gpa + i * sizeof(e));
9394                         return -EINVAL;
9395                 }
9396                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9397                         pr_warn_ratelimited(
9398                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9399                                 __func__, i, e.index, e.reserved);
9400                         return -EINVAL;
9401                 }
9402                 msr_info.host_initiated = false;
9403                 msr_info.index = e.index;
9404                 if (kvm_get_msr(vcpu, &msr_info)) {
9405                         pr_warn_ratelimited(
9406                                 "%s cannot read MSR (%u, 0x%x)\n",
9407                                 __func__, i, e.index);
9408                         return -EINVAL;
9409                 }
9410                 if (kvm_vcpu_write_guest(vcpu,
9411                                          gpa + i * sizeof(e) +
9412                                              offsetof(struct vmx_msr_entry, value),
9413                                          &msr_info.data, sizeof(msr_info.data))) {
9414                         pr_warn_ratelimited(
9415                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9416                                 __func__, i, e.index, msr_info.data);
9417                         return -EINVAL;
9418                 }
9419         }
9420         return 0;
9421 }
9422
9423 /*
9424  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9425  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9426  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9427  * guest in a way that will both be appropriate to L1's requests, and our
9428  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9429  * function also has additional necessary side-effects, like setting various
9430  * vcpu->arch fields.
9431  */
9432 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9433 {
9434         struct vcpu_vmx *vmx = to_vmx(vcpu);
9435         u32 exec_control;
9436
9437         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9438         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9439         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9440         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9441         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9442         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9443         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9444         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9445         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9446         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9447         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9448         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9449         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9450         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9451         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9452         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9453         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9454         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9455         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9456         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9457         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9458         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9459         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9460         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9461         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9462         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9463         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9464         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9465         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9466         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9467         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9468         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9469         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9470         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9471         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9472         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9473
9474         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9475                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9476                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9477         } else {
9478                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9479                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9480         }
9481         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9482                 vmcs12->vm_entry_intr_info_field);
9483         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9484                 vmcs12->vm_entry_exception_error_code);
9485         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9486                 vmcs12->vm_entry_instruction_len);
9487         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9488                 vmcs12->guest_interruptibility_info);
9489         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9490         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9491         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9492                 vmcs12->guest_pending_dbg_exceptions);
9493         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9494         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9495
9496         if (nested_cpu_has_xsaves(vmcs12))
9497                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9498         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9499
9500         exec_control = vmcs12->pin_based_vm_exec_control;
9501         exec_control |= vmcs_config.pin_based_exec_ctrl;
9502         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9503
9504         if (nested_cpu_has_posted_intr(vmcs12)) {
9505                 /*
9506                  * Note that we use L0's vector here and in
9507                  * vmx_deliver_nested_posted_interrupt.
9508                  */
9509                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9510                 vmx->nested.pi_pending = false;
9511                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9512                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9513                         page_to_phys(vmx->nested.pi_desc_page) +
9514                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9515                         (PAGE_SIZE - 1)));
9516         } else
9517                 exec_control &= ~PIN_BASED_POSTED_INTR;
9518
9519         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9520
9521         vmx->nested.preemption_timer_expired = false;
9522         if (nested_cpu_has_preemption_timer(vmcs12))
9523                 vmx_start_preemption_timer(vcpu);
9524
9525         /*
9526          * Whether page-faults are trapped is determined by a combination of
9527          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9528          * If enable_ept, L0 doesn't care about page faults and we should
9529          * set all of these to L1's desires. However, if !enable_ept, L0 does
9530          * care about (at least some) page faults, and because it is not easy
9531          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9532          * to exit on each and every L2 page fault. This is done by setting
9533          * MASK=MATCH=0 and (see below) EB.PF=1.
9534          * Note that below we don't need special code to set EB.PF beyond the
9535          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9536          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9537          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9538          *
9539          * A problem with this approach (when !enable_ept) is that L1 may be
9540          * injected with more page faults than it asked for. This could have
9541          * caused problems, but in practice existing hypervisors don't care.
9542          * To fix this, we will need to emulate the PFEC checking (on the L1
9543          * page tables), using walk_addr(), when injecting PFs to L1.
9544          */
9545         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9546                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9547         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9548                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9549
9550         if (cpu_has_secondary_exec_ctrls()) {
9551                 exec_control = vmx_secondary_exec_control(vmx);
9552
9553                 /* Take the following fields only from vmcs12 */
9554                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9555                                   SECONDARY_EXEC_RDTSCP |
9556                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9557                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9558                                   SECONDARY_EXEC_PCOMMIT);
9559                 if (nested_cpu_has(vmcs12,
9560                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9561                         exec_control |= vmcs12->secondary_vm_exec_control;
9562
9563                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9564                         /*
9565                          * If translation failed, no matter: This feature asks
9566                          * to exit when accessing the given address, and if it
9567                          * can never be accessed, this feature won't do
9568                          * anything anyway.
9569                          */
9570                         if (!vmx->nested.apic_access_page)
9571                                 exec_control &=
9572                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9573                         else
9574                                 vmcs_write64(APIC_ACCESS_ADDR,
9575                                   page_to_phys(vmx->nested.apic_access_page));
9576                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9577                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9578                         exec_control |=
9579                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9580                         kvm_vcpu_reload_apic_access_page(vcpu);
9581                 }
9582
9583                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9584                         vmcs_write64(EOI_EXIT_BITMAP0,
9585                                 vmcs12->eoi_exit_bitmap0);
9586                         vmcs_write64(EOI_EXIT_BITMAP1,
9587                                 vmcs12->eoi_exit_bitmap1);
9588                         vmcs_write64(EOI_EXIT_BITMAP2,
9589                                 vmcs12->eoi_exit_bitmap2);
9590                         vmcs_write64(EOI_EXIT_BITMAP3,
9591                                 vmcs12->eoi_exit_bitmap3);
9592                         vmcs_write16(GUEST_INTR_STATUS,
9593                                 vmcs12->guest_intr_status);
9594                 }
9595
9596                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9597         }
9598
9599
9600         /*
9601          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9602          * Some constant fields are set here by vmx_set_constant_host_state().
9603          * Other fields are different per CPU, and will be set later when
9604          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9605          */
9606         vmx_set_constant_host_state(vmx);
9607
9608         /*
9609          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9610          * entry, but only if the current (host) sp changed from the value
9611          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9612          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9613          * here we just force the write to happen on entry.
9614          */
9615         vmx->host_rsp = 0;
9616
9617         exec_control = vmx_exec_control(vmx); /* L0's desires */
9618         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9619         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9620         exec_control &= ~CPU_BASED_TPR_SHADOW;
9621         exec_control |= vmcs12->cpu_based_vm_exec_control;
9622
9623         if (exec_control & CPU_BASED_TPR_SHADOW) {
9624                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9625                                 page_to_phys(vmx->nested.virtual_apic_page));
9626                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9627         }
9628
9629         if (cpu_has_vmx_msr_bitmap() &&
9630             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9631                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9632                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9633         } else
9634                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9635
9636         /*
9637          * Merging of IO bitmap not currently supported.
9638          * Rather, exit every time.
9639          */
9640         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9641         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9642
9643         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9644
9645         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9646          * bitwise-or of what L1 wants to trap for L2, and what we want to
9647          * trap. Note that CR0.TS also needs updating - we do this later.
9648          */
9649         update_exception_bitmap(vcpu);
9650         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9651         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9652
9653         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9654          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9655          * bits are further modified by vmx_set_efer() below.
9656          */
9657         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9658
9659         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9660          * emulated by vmx_set_efer(), below.
9661          */
9662         vm_entry_controls_init(vmx,
9663                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9664                         ~VM_ENTRY_IA32E_MODE) |
9665                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9666
9667         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9668                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9669                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9670         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9671                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9672
9673
9674         set_cr4_guest_host_mask(vmx);
9675
9676         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9677                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9678
9679         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9680                 vmcs_write64(TSC_OFFSET,
9681                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9682         else
9683                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9684
9685         if (enable_vpid) {
9686                 /*
9687                  * There is no direct mapping between vpid02 and vpid12, the
9688                  * vpid02 is per-vCPU for L0 and reused while the value of
9689                  * vpid12 is changed w/ one invvpid during nested vmentry.
9690                  * The vpid12 is allocated by L1 for L2, so it will not
9691                  * influence global bitmap(for vpid01 and vpid02 allocation)
9692                  * even if spawn a lot of nested vCPUs.
9693                  */
9694                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9695                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9696                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9697                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9698                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9699                         }
9700                 } else {
9701                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9702                         vmx_flush_tlb(vcpu);
9703                 }
9704
9705         }
9706
9707         if (nested_cpu_has_ept(vmcs12)) {
9708                 kvm_mmu_unload(vcpu);
9709                 nested_ept_init_mmu_context(vcpu);
9710         }
9711
9712         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9713                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9714         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9715                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9716         else
9717                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9718         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9719         vmx_set_efer(vcpu, vcpu->arch.efer);
9720
9721         /*
9722          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9723          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9724          * The CR0_READ_SHADOW is what L2 should have expected to read given
9725          * the specifications by L1; It's not enough to take
9726          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9727          * have more bits than L1 expected.
9728          */
9729         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9730         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9731
9732         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9733         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9734
9735         /* shadow page tables on either EPT or shadow page tables */
9736         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9737         kvm_mmu_reset_context(vcpu);
9738
9739         if (!enable_ept)
9740                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9741
9742         /*
9743          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9744          */
9745         if (enable_ept) {
9746                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9747                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9748                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9749                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9750         }
9751
9752         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9753         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9754 }
9755
9756 /*
9757  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9758  * for running an L2 nested guest.
9759  */
9760 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9761 {
9762         struct vmcs12 *vmcs12;
9763         struct vcpu_vmx *vmx = to_vmx(vcpu);
9764         int cpu;
9765         struct loaded_vmcs *vmcs02;
9766         bool ia32e;
9767         u32 msr_entry_idx;
9768
9769         if (!nested_vmx_check_permission(vcpu) ||
9770             !nested_vmx_check_vmcs12(vcpu))
9771                 return 1;
9772
9773         skip_emulated_instruction(vcpu);
9774         vmcs12 = get_vmcs12(vcpu);
9775
9776         if (enable_shadow_vmcs)
9777                 copy_shadow_to_vmcs12(vmx);
9778
9779         /*
9780          * The nested entry process starts with enforcing various prerequisites
9781          * on vmcs12 as required by the Intel SDM, and act appropriately when
9782          * they fail: As the SDM explains, some conditions should cause the
9783          * instruction to fail, while others will cause the instruction to seem
9784          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9785          * To speed up the normal (success) code path, we should avoid checking
9786          * for misconfigurations which will anyway be caught by the processor
9787          * when using the merged vmcs02.
9788          */
9789         if (vmcs12->launch_state == launch) {
9790                 nested_vmx_failValid(vcpu,
9791                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9792                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9793                 return 1;
9794         }
9795
9796         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9797             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9798                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9799                 return 1;
9800         }
9801
9802         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9803                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9804                 return 1;
9805         }
9806
9807         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9808                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9809                 return 1;
9810         }
9811
9812         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9813                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9814                 return 1;
9815         }
9816
9817         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9818                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9819                 return 1;
9820         }
9821
9822         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9823                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9824                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9825             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9826                                 vmx->nested.nested_vmx_secondary_ctls_low,
9827                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9828             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9829                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9830                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9831             !vmx_control_verify(vmcs12->vm_exit_controls,
9832                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9833                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9834             !vmx_control_verify(vmcs12->vm_entry_controls,
9835                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9836                                 vmx->nested.nested_vmx_entry_ctls_high))
9837         {
9838                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9839                 return 1;
9840         }
9841
9842         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9843             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9844                 nested_vmx_failValid(vcpu,
9845                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9846                 return 1;
9847         }
9848
9849         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9850             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9851                 nested_vmx_entry_failure(vcpu, vmcs12,
9852                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9853                 return 1;
9854         }
9855         if (vmcs12->vmcs_link_pointer != -1ull) {
9856                 nested_vmx_entry_failure(vcpu, vmcs12,
9857                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9858                 return 1;
9859         }
9860
9861         /*
9862          * If the load IA32_EFER VM-entry control is 1, the following checks
9863          * are performed on the field for the IA32_EFER MSR:
9864          * - Bits reserved in the IA32_EFER MSR must be 0.
9865          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9866          *   the IA-32e mode guest VM-exit control. It must also be identical
9867          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9868          *   CR0.PG) is 1.
9869          */
9870         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9871                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9872                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9873                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9874                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9875                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9876                         nested_vmx_entry_failure(vcpu, vmcs12,
9877                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9878                         return 1;
9879                 }
9880         }
9881
9882         /*
9883          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9884          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9885          * the values of the LMA and LME bits in the field must each be that of
9886          * the host address-space size VM-exit control.
9887          */
9888         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9889                 ia32e = (vmcs12->vm_exit_controls &
9890                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9891                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9892                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9893                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9894                         nested_vmx_entry_failure(vcpu, vmcs12,
9895                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9896                         return 1;
9897                 }
9898         }
9899
9900         /*
9901          * We're finally done with prerequisite checking, and can start with
9902          * the nested entry.
9903          */
9904
9905         vmcs02 = nested_get_current_vmcs02(vmx);
9906         if (!vmcs02)
9907                 return -ENOMEM;
9908
9909         enter_guest_mode(vcpu);
9910
9911         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9912
9913         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9914                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9915
9916         cpu = get_cpu();
9917         vmx->loaded_vmcs = vmcs02;
9918         vmx_vcpu_put(vcpu);
9919         vmx_vcpu_load(vcpu, cpu);
9920         vcpu->cpu = cpu;
9921         put_cpu();
9922
9923         vmx_segment_cache_clear(vmx);
9924
9925         prepare_vmcs02(vcpu, vmcs12);
9926
9927         msr_entry_idx = nested_vmx_load_msr(vcpu,
9928                                             vmcs12->vm_entry_msr_load_addr,
9929                                             vmcs12->vm_entry_msr_load_count);
9930         if (msr_entry_idx) {
9931                 leave_guest_mode(vcpu);
9932                 vmx_load_vmcs01(vcpu);
9933                 nested_vmx_entry_failure(vcpu, vmcs12,
9934                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9935                 return 1;
9936         }
9937
9938         vmcs12->launch_state = 1;
9939
9940         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9941                 return kvm_vcpu_halt(vcpu);
9942
9943         vmx->nested.nested_run_pending = 1;
9944
9945         /*
9946          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9947          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9948          * returned as far as L1 is concerned. It will only return (and set
9949          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9950          */
9951         return 1;
9952 }
9953
9954 /*
9955  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9956  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9957  * This function returns the new value we should put in vmcs12.guest_cr0.
9958  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9959  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9960  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9961  *     didn't trap the bit, because if L1 did, so would L0).
9962  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9963  *     been modified by L2, and L1 knows it. So just leave the old value of
9964  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9965  *     isn't relevant, because if L0 traps this bit it can set it to anything.
9966  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9967  *     changed these bits, and therefore they need to be updated, but L0
9968  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9969  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9970  */
9971 static inline unsigned long
9972 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9973 {
9974         return
9975         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9976         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9977         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9978                         vcpu->arch.cr0_guest_owned_bits));
9979 }
9980
9981 static inline unsigned long
9982 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9983 {
9984         return
9985         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9986         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9987         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9988                         vcpu->arch.cr4_guest_owned_bits));
9989 }
9990
9991 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9992                                        struct vmcs12 *vmcs12)
9993 {
9994         u32 idt_vectoring;
9995         unsigned int nr;
9996
9997         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
9998                 nr = vcpu->arch.exception.nr;
9999                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10000
10001                 if (kvm_exception_is_soft(nr)) {
10002                         vmcs12->vm_exit_instruction_len =
10003                                 vcpu->arch.event_exit_inst_len;
10004                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10005                 } else
10006                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10007
10008                 if (vcpu->arch.exception.has_error_code) {
10009                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10010                         vmcs12->idt_vectoring_error_code =
10011                                 vcpu->arch.exception.error_code;
10012                 }
10013
10014                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10015         } else if (vcpu->arch.nmi_injected) {
10016                 vmcs12->idt_vectoring_info_field =
10017                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10018         } else if (vcpu->arch.interrupt.pending) {
10019                 nr = vcpu->arch.interrupt.nr;
10020                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10021
10022                 if (vcpu->arch.interrupt.soft) {
10023                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10024                         vmcs12->vm_entry_instruction_len =
10025                                 vcpu->arch.event_exit_inst_len;
10026                 } else
10027                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10028
10029                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10030         }
10031 }
10032
10033 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10034 {
10035         struct vcpu_vmx *vmx = to_vmx(vcpu);
10036
10037         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10038             vmx->nested.preemption_timer_expired) {
10039                 if (vmx->nested.nested_run_pending)
10040                         return -EBUSY;
10041                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10042                 return 0;
10043         }
10044
10045         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10046                 if (vmx->nested.nested_run_pending ||
10047                     vcpu->arch.interrupt.pending)
10048                         return -EBUSY;
10049                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10050                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10051                                   INTR_INFO_VALID_MASK, 0);
10052                 /*
10053                  * The NMI-triggered VM exit counts as injection:
10054                  * clear this one and block further NMIs.
10055                  */
10056                 vcpu->arch.nmi_pending = 0;
10057                 vmx_set_nmi_mask(vcpu, true);
10058                 return 0;
10059         }
10060
10061         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10062             nested_exit_on_intr(vcpu)) {
10063                 if (vmx->nested.nested_run_pending)
10064                         return -EBUSY;
10065                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10066                 return 0;
10067         }
10068
10069         return vmx_complete_nested_posted_interrupt(vcpu);
10070 }
10071
10072 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10073 {
10074         ktime_t remaining =
10075                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10076         u64 value;
10077
10078         if (ktime_to_ns(remaining) <= 0)
10079                 return 0;
10080
10081         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10082         do_div(value, 1000000);
10083         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10084 }
10085
10086 /*
10087  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10088  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10089  * and this function updates it to reflect the changes to the guest state while
10090  * L2 was running (and perhaps made some exits which were handled directly by L0
10091  * without going back to L1), and to reflect the exit reason.
10092  * Note that we do not have to copy here all VMCS fields, just those that
10093  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10094  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10095  * which already writes to vmcs12 directly.
10096  */
10097 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10098                            u32 exit_reason, u32 exit_intr_info,
10099                            unsigned long exit_qualification)
10100 {
10101         /* update guest state fields: */
10102         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10103         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10104
10105         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10106         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10107         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10108
10109         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10110         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10111         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10112         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10113         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10114         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10115         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10116         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10117         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10118         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10119         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10120         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10121         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10122         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10123         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10124         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10125         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10126         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10127         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10128         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10129         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10130         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10131         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10132         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10133         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10134         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10135         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10136         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10137         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10138         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10139         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10140         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10141         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10142         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10143         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10144         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10145
10146         vmcs12->guest_interruptibility_info =
10147                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10148         vmcs12->guest_pending_dbg_exceptions =
10149                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10150         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10151                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10152         else
10153                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10154
10155         if (nested_cpu_has_preemption_timer(vmcs12)) {
10156                 if (vmcs12->vm_exit_controls &
10157                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10158                         vmcs12->vmx_preemption_timer_value =
10159                                 vmx_get_preemption_timer_value(vcpu);
10160                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10161         }
10162
10163         /*
10164          * In some cases (usually, nested EPT), L2 is allowed to change its
10165          * own CR3 without exiting. If it has changed it, we must keep it.
10166          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10167          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10168          *
10169          * Additionally, restore L2's PDPTR to vmcs12.
10170          */
10171         if (enable_ept) {
10172                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10173                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10174                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10175                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10176                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10177         }
10178
10179         if (nested_cpu_has_vid(vmcs12))
10180                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10181
10182         vmcs12->vm_entry_controls =
10183                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10184                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10185
10186         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10187                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10188                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10189         }
10190
10191         /* TODO: These cannot have changed unless we have MSR bitmaps and
10192          * the relevant bit asks not to trap the change */
10193         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10194                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10195         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10196                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10197         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10198         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10199         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10200         if (vmx_mpx_supported())
10201                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10202         if (nested_cpu_has_xsaves(vmcs12))
10203                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10204
10205         /* update exit information fields: */
10206
10207         vmcs12->vm_exit_reason = exit_reason;
10208         vmcs12->exit_qualification = exit_qualification;
10209
10210         vmcs12->vm_exit_intr_info = exit_intr_info;
10211         if ((vmcs12->vm_exit_intr_info &
10212              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10213             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10214                 vmcs12->vm_exit_intr_error_code =
10215                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10216         vmcs12->idt_vectoring_info_field = 0;
10217         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10218         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10219
10220         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10221                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10222                  * instead of reading the real value. */
10223                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10224
10225                 /*
10226                  * Transfer the event that L0 or L1 may wanted to inject into
10227                  * L2 to IDT_VECTORING_INFO_FIELD.
10228                  */
10229                 vmcs12_save_pending_event(vcpu, vmcs12);
10230         }
10231
10232         /*
10233          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10234          * preserved above and would only end up incorrectly in L1.
10235          */
10236         vcpu->arch.nmi_injected = false;
10237         kvm_clear_exception_queue(vcpu);
10238         kvm_clear_interrupt_queue(vcpu);
10239 }
10240
10241 /*
10242  * A part of what we need to when the nested L2 guest exits and we want to
10243  * run its L1 parent, is to reset L1's guest state to the host state specified
10244  * in vmcs12.
10245  * This function is to be called not only on normal nested exit, but also on
10246  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10247  * Failures During or After Loading Guest State").
10248  * This function should be called when the active VMCS is L1's (vmcs01).
10249  */
10250 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10251                                    struct vmcs12 *vmcs12)
10252 {
10253         struct kvm_segment seg;
10254
10255         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10256                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10257         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10258                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10259         else
10260                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10261         vmx_set_efer(vcpu, vcpu->arch.efer);
10262
10263         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10264         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10265         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10266         /*
10267          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10268          * actually changed, because it depends on the current state of
10269          * fpu_active (which may have changed).
10270          * Note that vmx_set_cr0 refers to efer set above.
10271          */
10272         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10273         /*
10274          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10275          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10276          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10277          */
10278         update_exception_bitmap(vcpu);
10279         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10280         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10281
10282         /*
10283          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10284          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10285          */
10286         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10287         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10288
10289         nested_ept_uninit_mmu_context(vcpu);
10290
10291         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10292         kvm_mmu_reset_context(vcpu);
10293
10294         if (!enable_ept)
10295                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10296
10297         if (enable_vpid) {
10298                 /*
10299                  * Trivially support vpid by letting L2s share their parent
10300                  * L1's vpid. TODO: move to a more elaborate solution, giving
10301                  * each L2 its own vpid and exposing the vpid feature to L1.
10302                  */
10303                 vmx_flush_tlb(vcpu);
10304         }
10305
10306
10307         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10308         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10309         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10310         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10311         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10312
10313         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10314         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10315                 vmcs_write64(GUEST_BNDCFGS, 0);
10316
10317         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10318                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10319                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10320         }
10321         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10322                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10323                         vmcs12->host_ia32_perf_global_ctrl);
10324
10325         /* Set L1 segment info according to Intel SDM
10326             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10327         seg = (struct kvm_segment) {
10328                 .base = 0,
10329                 .limit = 0xFFFFFFFF,
10330                 .selector = vmcs12->host_cs_selector,
10331                 .type = 11,
10332                 .present = 1,
10333                 .s = 1,
10334                 .g = 1
10335         };
10336         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10337                 seg.l = 1;
10338         else
10339                 seg.db = 1;
10340         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10341         seg = (struct kvm_segment) {
10342                 .base = 0,
10343                 .limit = 0xFFFFFFFF,
10344                 .type = 3,
10345                 .present = 1,
10346                 .s = 1,
10347                 .db = 1,
10348                 .g = 1
10349         };
10350         seg.selector = vmcs12->host_ds_selector;
10351         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10352         seg.selector = vmcs12->host_es_selector;
10353         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10354         seg.selector = vmcs12->host_ss_selector;
10355         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10356         seg.selector = vmcs12->host_fs_selector;
10357         seg.base = vmcs12->host_fs_base;
10358         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10359         seg.selector = vmcs12->host_gs_selector;
10360         seg.base = vmcs12->host_gs_base;
10361         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10362         seg = (struct kvm_segment) {
10363                 .base = vmcs12->host_tr_base,
10364                 .limit = 0x67,
10365                 .selector = vmcs12->host_tr_selector,
10366                 .type = 11,
10367                 .present = 1
10368         };
10369         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10370
10371         kvm_set_dr(vcpu, 7, 0x400);
10372         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10373
10374         if (cpu_has_vmx_msr_bitmap())
10375                 vmx_set_msr_bitmap(vcpu);
10376
10377         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10378                                 vmcs12->vm_exit_msr_load_count))
10379                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10380 }
10381
10382 /*
10383  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10384  * and modify vmcs12 to make it see what it would expect to see there if
10385  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10386  */
10387 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10388                               u32 exit_intr_info,
10389                               unsigned long exit_qualification)
10390 {
10391         struct vcpu_vmx *vmx = to_vmx(vcpu);
10392         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10393
10394         /* trying to cancel vmlaunch/vmresume is a bug */
10395         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10396
10397         leave_guest_mode(vcpu);
10398         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10399                        exit_qualification);
10400
10401         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10402                                  vmcs12->vm_exit_msr_store_count))
10403                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10404
10405         vmx_load_vmcs01(vcpu);
10406
10407         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10408             && nested_exit_intr_ack_set(vcpu)) {
10409                 int irq = kvm_cpu_get_interrupt(vcpu);
10410                 WARN_ON(irq < 0);
10411                 vmcs12->vm_exit_intr_info = irq |
10412                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10413         }
10414
10415         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10416                                        vmcs12->exit_qualification,
10417                                        vmcs12->idt_vectoring_info_field,
10418                                        vmcs12->vm_exit_intr_info,
10419                                        vmcs12->vm_exit_intr_error_code,
10420                                        KVM_ISA_VMX);
10421
10422         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10423         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10424         vmx_segment_cache_clear(vmx);
10425
10426         /* if no vmcs02 cache requested, remove the one we used */
10427         if (VMCS02_POOL_SIZE == 0)
10428                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10429
10430         load_vmcs12_host_state(vcpu, vmcs12);
10431
10432         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10433         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10434
10435         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10436         vmx->host_rsp = 0;
10437
10438         /* Unpin physical memory we referred to in vmcs02 */
10439         if (vmx->nested.apic_access_page) {
10440                 nested_release_page(vmx->nested.apic_access_page);
10441                 vmx->nested.apic_access_page = NULL;
10442         }
10443         if (vmx->nested.virtual_apic_page) {
10444                 nested_release_page(vmx->nested.virtual_apic_page);
10445                 vmx->nested.virtual_apic_page = NULL;
10446         }
10447         if (vmx->nested.pi_desc_page) {
10448                 kunmap(vmx->nested.pi_desc_page);
10449                 nested_release_page(vmx->nested.pi_desc_page);
10450                 vmx->nested.pi_desc_page = NULL;
10451                 vmx->nested.pi_desc = NULL;
10452         }
10453
10454         /*
10455          * We are now running in L2, mmu_notifier will force to reload the
10456          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10457          */
10458         kvm_vcpu_reload_apic_access_page(vcpu);
10459
10460         /*
10461          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10462          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10463          * success or failure flag accordingly.
10464          */
10465         if (unlikely(vmx->fail)) {
10466                 vmx->fail = 0;
10467                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10468         } else
10469                 nested_vmx_succeed(vcpu);
10470         if (enable_shadow_vmcs)
10471                 vmx->nested.sync_shadow_vmcs = true;
10472
10473         /* in case we halted in L2 */
10474         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10475 }
10476
10477 /*
10478  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10479  */
10480 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10481 {
10482         if (is_guest_mode(vcpu))
10483                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10484         free_nested(to_vmx(vcpu));
10485 }
10486
10487 /*
10488  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10489  * 23.7 "VM-entry failures during or after loading guest state" (this also
10490  * lists the acceptable exit-reason and exit-qualification parameters).
10491  * It should only be called before L2 actually succeeded to run, and when
10492  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10493  */
10494 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10495                         struct vmcs12 *vmcs12,
10496                         u32 reason, unsigned long qualification)
10497 {
10498         load_vmcs12_host_state(vcpu, vmcs12);
10499         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10500         vmcs12->exit_qualification = qualification;
10501         nested_vmx_succeed(vcpu);
10502         if (enable_shadow_vmcs)
10503                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10504 }
10505
10506 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10507                                struct x86_instruction_info *info,
10508                                enum x86_intercept_stage stage)
10509 {
10510         return X86EMUL_CONTINUE;
10511 }
10512
10513 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10514 {
10515         if (ple_gap)
10516                 shrink_ple_window(vcpu);
10517 }
10518
10519 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10520                                      struct kvm_memory_slot *slot)
10521 {
10522         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10523         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10524 }
10525
10526 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10527                                        struct kvm_memory_slot *slot)
10528 {
10529         kvm_mmu_slot_set_dirty(kvm, slot);
10530 }
10531
10532 static void vmx_flush_log_dirty(struct kvm *kvm)
10533 {
10534         kvm_flush_pml_buffers(kvm);
10535 }
10536
10537 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10538                                            struct kvm_memory_slot *memslot,
10539                                            gfn_t offset, unsigned long mask)
10540 {
10541         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10542 }
10543
10544 /*
10545  * This routine does the following things for vCPU which is going
10546  * to be blocked if VT-d PI is enabled.
10547  * - Store the vCPU to the wakeup list, so when interrupts happen
10548  *   we can find the right vCPU to wake up.
10549  * - Change the Posted-interrupt descriptor as below:
10550  *      'NDST' <-- vcpu->pre_pcpu
10551  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10552  * - If 'ON' is set during this process, which means at least one
10553  *   interrupt is posted for this vCPU, we cannot block it, in
10554  *   this case, return 1, otherwise, return 0.
10555  *
10556  */
10557 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10558 {
10559         unsigned long flags;
10560         unsigned int dest;
10561         struct pi_desc old, new;
10562         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10563
10564         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10565                 !irq_remapping_cap(IRQ_POSTING_CAP))
10566                 return 0;
10567
10568         vcpu->pre_pcpu = vcpu->cpu;
10569         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10570                           vcpu->pre_pcpu), flags);
10571         list_add_tail(&vcpu->blocked_vcpu_list,
10572                       &per_cpu(blocked_vcpu_on_cpu,
10573                       vcpu->pre_pcpu));
10574         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10575                                vcpu->pre_pcpu), flags);
10576
10577         do {
10578                 old.control = new.control = pi_desc->control;
10579
10580                 /*
10581                  * We should not block the vCPU if
10582                  * an interrupt is posted for it.
10583                  */
10584                 if (pi_test_on(pi_desc) == 1) {
10585                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10586                                           vcpu->pre_pcpu), flags);
10587                         list_del(&vcpu->blocked_vcpu_list);
10588                         spin_unlock_irqrestore(
10589                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10590                                         vcpu->pre_pcpu), flags);
10591                         vcpu->pre_pcpu = -1;
10592
10593                         return 1;
10594                 }
10595
10596                 WARN((pi_desc->sn == 1),
10597                      "Warning: SN field of posted-interrupts "
10598                      "is set before blocking\n");
10599
10600                 /*
10601                  * Since vCPU can be preempted during this process,
10602                  * vcpu->cpu could be different with pre_pcpu, we
10603                  * need to set pre_pcpu as the destination of wakeup
10604                  * notification event, then we can find the right vCPU
10605                  * to wakeup in wakeup handler if interrupts happen
10606                  * when the vCPU is in blocked state.
10607                  */
10608                 dest = cpu_physical_id(vcpu->pre_pcpu);
10609
10610                 if (x2apic_enabled())
10611                         new.ndst = dest;
10612                 else
10613                         new.ndst = (dest << 8) & 0xFF00;
10614
10615                 /* set 'NV' to 'wakeup vector' */
10616                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10617         } while (cmpxchg(&pi_desc->control, old.control,
10618                         new.control) != old.control);
10619
10620         return 0;
10621 }
10622
10623 static void vmx_post_block(struct kvm_vcpu *vcpu)
10624 {
10625         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10626         struct pi_desc old, new;
10627         unsigned int dest;
10628         unsigned long flags;
10629
10630         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10631                 !irq_remapping_cap(IRQ_POSTING_CAP))
10632                 return;
10633
10634         do {
10635                 old.control = new.control = pi_desc->control;
10636
10637                 dest = cpu_physical_id(vcpu->cpu);
10638
10639                 if (x2apic_enabled())
10640                         new.ndst = dest;
10641                 else
10642                         new.ndst = (dest << 8) & 0xFF00;
10643
10644                 /* Allow posting non-urgent interrupts */
10645                 new.sn = 0;
10646
10647                 /* set 'NV' to 'notification vector' */
10648                 new.nv = POSTED_INTR_VECTOR;
10649         } while (cmpxchg(&pi_desc->control, old.control,
10650                         new.control) != old.control);
10651
10652         if(vcpu->pre_pcpu != -1) {
10653                 spin_lock_irqsave(
10654                         &per_cpu(blocked_vcpu_on_cpu_lock,
10655                         vcpu->pre_pcpu), flags);
10656                 list_del(&vcpu->blocked_vcpu_list);
10657                 spin_unlock_irqrestore(
10658                         &per_cpu(blocked_vcpu_on_cpu_lock,
10659                         vcpu->pre_pcpu), flags);
10660                 vcpu->pre_pcpu = -1;
10661         }
10662 }
10663
10664 /*
10665  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10666  *
10667  * @kvm: kvm
10668  * @host_irq: host irq of the interrupt
10669  * @guest_irq: gsi of the interrupt
10670  * @set: set or unset PI
10671  * returns 0 on success, < 0 on failure
10672  */
10673 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10674                               uint32_t guest_irq, bool set)
10675 {
10676         struct kvm_kernel_irq_routing_entry *e;
10677         struct kvm_irq_routing_table *irq_rt;
10678         struct kvm_lapic_irq irq;
10679         struct kvm_vcpu *vcpu;
10680         struct vcpu_data vcpu_info;
10681         int idx, ret = -EINVAL;
10682
10683         if (!kvm_arch_has_assigned_device(kvm) ||
10684                 !irq_remapping_cap(IRQ_POSTING_CAP))
10685                 return 0;
10686
10687         idx = srcu_read_lock(&kvm->irq_srcu);
10688         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10689         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10690
10691         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10692                 if (e->type != KVM_IRQ_ROUTING_MSI)
10693                         continue;
10694                 /*
10695                  * VT-d PI cannot support posting multicast/broadcast
10696                  * interrupts to a vCPU, we still use interrupt remapping
10697                  * for these kind of interrupts.
10698                  *
10699                  * For lowest-priority interrupts, we only support
10700                  * those with single CPU as the destination, e.g. user
10701                  * configures the interrupts via /proc/irq or uses
10702                  * irqbalance to make the interrupts single-CPU.
10703                  *
10704                  * We will support full lowest-priority interrupt later.
10705                  */
10706
10707                 kvm_set_msi_irq(e, &irq);
10708                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10709                         continue;
10710
10711                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10712                 vcpu_info.vector = irq.vector;
10713
10714                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10715                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10716
10717                 if (set)
10718                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10719                 else {
10720                         /* suppress notification event before unposting */
10721                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10722                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10723                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10724                 }
10725
10726                 if (ret < 0) {
10727                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10728                                         __func__);
10729                         goto out;
10730                 }
10731         }
10732
10733         ret = 0;
10734 out:
10735         srcu_read_unlock(&kvm->irq_srcu, idx);
10736         return ret;
10737 }
10738
10739 static struct kvm_x86_ops vmx_x86_ops = {
10740         .cpu_has_kvm_support = cpu_has_kvm_support,
10741         .disabled_by_bios = vmx_disabled_by_bios,
10742         .hardware_setup = hardware_setup,
10743         .hardware_unsetup = hardware_unsetup,
10744         .check_processor_compatibility = vmx_check_processor_compat,
10745         .hardware_enable = hardware_enable,
10746         .hardware_disable = hardware_disable,
10747         .cpu_has_accelerated_tpr = report_flexpriority,
10748         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10749
10750         .vcpu_create = vmx_create_vcpu,
10751         .vcpu_free = vmx_free_vcpu,
10752         .vcpu_reset = vmx_vcpu_reset,
10753
10754         .prepare_guest_switch = vmx_save_host_state,
10755         .vcpu_load = vmx_vcpu_load,
10756         .vcpu_put = vmx_vcpu_put,
10757
10758         .update_bp_intercept = update_exception_bitmap,
10759         .get_msr = vmx_get_msr,
10760         .set_msr = vmx_set_msr,
10761         .get_segment_base = vmx_get_segment_base,
10762         .get_segment = vmx_get_segment,
10763         .set_segment = vmx_set_segment,
10764         .get_cpl = vmx_get_cpl,
10765         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10766         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10767         .decache_cr3 = vmx_decache_cr3,
10768         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10769         .set_cr0 = vmx_set_cr0,
10770         .set_cr3 = vmx_set_cr3,
10771         .set_cr4 = vmx_set_cr4,
10772         .set_efer = vmx_set_efer,
10773         .get_idt = vmx_get_idt,
10774         .set_idt = vmx_set_idt,
10775         .get_gdt = vmx_get_gdt,
10776         .set_gdt = vmx_set_gdt,
10777         .get_dr6 = vmx_get_dr6,
10778         .set_dr6 = vmx_set_dr6,
10779         .set_dr7 = vmx_set_dr7,
10780         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10781         .cache_reg = vmx_cache_reg,
10782         .get_rflags = vmx_get_rflags,
10783         .set_rflags = vmx_set_rflags,
10784         .fpu_activate = vmx_fpu_activate,
10785         .fpu_deactivate = vmx_fpu_deactivate,
10786
10787         .tlb_flush = vmx_flush_tlb,
10788
10789         .run = vmx_vcpu_run,
10790         .handle_exit = vmx_handle_exit,
10791         .skip_emulated_instruction = skip_emulated_instruction,
10792         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10793         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10794         .patch_hypercall = vmx_patch_hypercall,
10795         .set_irq = vmx_inject_irq,
10796         .set_nmi = vmx_inject_nmi,
10797         .queue_exception = vmx_queue_exception,
10798         .cancel_injection = vmx_cancel_injection,
10799         .interrupt_allowed = vmx_interrupt_allowed,
10800         .nmi_allowed = vmx_nmi_allowed,
10801         .get_nmi_mask = vmx_get_nmi_mask,
10802         .set_nmi_mask = vmx_set_nmi_mask,
10803         .enable_nmi_window = enable_nmi_window,
10804         .enable_irq_window = enable_irq_window,
10805         .update_cr8_intercept = update_cr8_intercept,
10806         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10807         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10808         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10809         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10810         .hwapic_irr_update = vmx_hwapic_irr_update,
10811         .hwapic_isr_update = vmx_hwapic_isr_update,
10812         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10813         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10814
10815         .set_tss_addr = vmx_set_tss_addr,
10816         .get_tdp_level = get_ept_level,
10817         .get_mt_mask = vmx_get_mt_mask,
10818
10819         .get_exit_info = vmx_get_exit_info,
10820
10821         .get_lpage_level = vmx_get_lpage_level,
10822
10823         .cpuid_update = vmx_cpuid_update,
10824
10825         .rdtscp_supported = vmx_rdtscp_supported,
10826         .invpcid_supported = vmx_invpcid_supported,
10827
10828         .set_supported_cpuid = vmx_set_supported_cpuid,
10829
10830         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10831
10832         .read_tsc_offset = vmx_read_tsc_offset,
10833         .write_tsc_offset = vmx_write_tsc_offset,
10834         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10835         .read_l1_tsc = vmx_read_l1_tsc,
10836
10837         .set_tdp_cr3 = vmx_set_cr3,
10838
10839         .check_intercept = vmx_check_intercept,
10840         .handle_external_intr = vmx_handle_external_intr,
10841         .mpx_supported = vmx_mpx_supported,
10842         .xsaves_supported = vmx_xsaves_supported,
10843
10844         .check_nested_events = vmx_check_nested_events,
10845
10846         .sched_in = vmx_sched_in,
10847
10848         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10849         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10850         .flush_log_dirty = vmx_flush_log_dirty,
10851         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10852
10853         .pre_block = vmx_pre_block,
10854         .post_block = vmx_post_block,
10855
10856         .pmu_ops = &intel_pmu_ops,
10857
10858         .update_pi_irte = vmx_update_pi_irte,
10859 };
10860
10861 static int __init vmx_init(void)
10862 {
10863         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10864                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10865         if (r)
10866                 return r;
10867
10868 #ifdef CONFIG_KEXEC_CORE
10869         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10870                            crash_vmclear_local_loaded_vmcss);
10871 #endif
10872
10873         return 0;
10874 }
10875
10876 static void __exit vmx_exit(void)
10877 {
10878 #ifdef CONFIG_KEXEC_CORE
10879         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10880         synchronize_rcu();
10881 #endif
10882
10883         kvm_exit();
10884 }
10885
10886 module_init(vmx_init)
10887 module_exit(vmx_exit)