drivers/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  * Authors:
  25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  26  *   Port from Qemu.
  27  */
  28 #include <linux/mm.h>
  29 #include "irq.h"
  30
  31 /*
  32  * set irq level. If an edge is detected, then the IRR is set to 1
  33  */
  34 static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  35 {
  36         int mask;
  37         mask = 1 << irq;
  38         if (s->elcr & mask)     /* level triggered */
  39                 if (level) {
  40                         s->irr |= mask;
  41                         s->last_irr |= mask;
  42                 } else {
  43                         s->irr &= ~mask;
  44                         s->last_irr &= ~mask;
  45                 }
  46         else    /* edge triggered */
  47                 if (level) {
  48                         if ((s->last_irr & mask) == 0)
  49                                 s->irr |= mask;
  50                         s->last_irr |= mask;
  51                 } else
  52                         s->last_irr &= ~mask;
  53 }
  54
  55 /*
  56  * return the highest priority found in mask (highest = smallest
  57  * number). Return 8 if no irq
  58  */
  59 static inline int get_priority(struct kvm_kpic_state *s, int mask)
  60 {
  61         int priority;
  62         if (mask == 0)
  63                 return 8;
  64         priority = 0;
  65         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  66                 priority++;
  67         return priority;
  68 }
  69
  70 /*
  71  * return the pic wanted interrupt. return -1 if none
  72  */
  73 static int pic_get_irq(struct kvm_kpic_state *s)
  74 {
  75         int mask, cur_priority, priority;
  76
  77         mask = s->irr & ~s->imr;
  78         priority = get_priority(s, mask);
  79         if (priority == 8)
  80                 return -1;
  81         /*
  82          * compute current priority. If special fully nested mode on the
  83          * master, the IRQ coming from the slave is not taken into account
  84          * for the priority computation.
  85          */
  86         mask = s->isr;
  87         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
  88                 mask &= ~(1 << 2);
  89         cur_priority = get_priority(s, mask);
  90         if (priority < cur_priority)
  91                 /*
  92                  * higher priority found: an irq should be generated
  93                  */
  94                 return (priority + s->priority_add) & 7;
  95         else
  96                 return -1;
  97 }
  98
  99 /*
 100  * raise irq to CPU if necessary. must be called every time the active
 101  * irq may change
 102  */
 103 static void pic_update_irq(struct kvm_pic *s)
 104 {
 105         int irq2, irq;
 106
 107         irq2 = pic_get_irq(&s->pics[1]);
 108         if (irq2 >= 0) {
 109                 /*
 110                  * if irq request by slave pic, signal master PIC
 111                  */
 112                 pic_set_irq1(&s->pics[0], 2, 1);
 113                 pic_set_irq1(&s->pics[0], 2, 0);
 114         }
 115         irq = pic_get_irq(&s->pics[0]);
 116         if (irq >= 0)
 117                 s->irq_request(s->irq_request_opaque, 1);
 118         else
 119                 s->irq_request(s->irq_request_opaque, 0);
 120 }
 121
 122 void kvm_pic_set_irq(void *opaque, int irq, int level)
 123 {
 124         struct kvm_pic *s = opaque;
 125
 126         pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 127         pic_update_irq(s);
 128 }
 129
 130 /*
 131  * acknowledge interrupt 'irq'
 132  */
 133 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 134 {
 135         if (s->auto_eoi) {
 136                 if (s->rotate_on_auto_eoi)
 137                         s->priority_add = (irq + 1) & 7;
 138         } else
 139                 s->isr |= (1 << irq);
 140         /*
 141          * We don't clear a level sensitive interrupt here
 142          */
 143         if (!(s->elcr & (1 << irq)))
 144                 s->irr &= ~(1 << irq);
 145 }
 146
 147 int kvm_pic_read_irq(struct kvm_pic *s)
 148 {
 149         int irq, irq2, intno;
 150
 151         irq = pic_get_irq(&s->pics[0]);
 152         if (irq >= 0) {
 153                 pic_intack(&s->pics[0], irq);
 154                 if (irq == 2) {
 155                         irq2 = pic_get_irq(&s->pics[1]);
 156                         if (irq2 >= 0)
 157                                 pic_intack(&s->pics[1], irq2);
 158                         else
 159                                 /*
 160                                  * spurious IRQ on slave controller
 161                                  */
 162                                 irq2 = 7;
 163                         intno = s->pics[1].irq_base + irq2;
 164                         irq = irq2 + 8;
 165                 } else
 166                         intno = s->pics[0].irq_base + irq;
 167         } else {
 168                 /*
 169                  * spurious IRQ on host controller
 170                  */
 171                 irq = 7;
 172                 intno = s->pics[0].irq_base + irq;
 173         }
 174         pic_update_irq(s);
 175
 176         return intno;
 177 }
 178
 179 static void pic_reset(void *opaque)
 180 {
 181         struct kvm_kpic_state *s = opaque;
 182
 183         s->last_irr = 0;
 184         s->irr = 0;
 185         s->imr = 0;
 186         s->isr = 0;
 187         s->priority_add = 0;
 188         s->irq_base = 0;
 189         s->read_reg_select = 0;
 190         s->poll = 0;
 191         s->special_mask = 0;
 192         s->init_state = 0;
 193         s->auto_eoi = 0;
 194         s->rotate_on_auto_eoi = 0;
 195         s->special_fully_nested_mode = 0;
 196         s->init4 = 0;
 197 }
 198
 199 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 200 {
 201         struct kvm_kpic_state *s = opaque;
 202         int priority, cmd, irq;
 203
 204         addr &= 1;
 205         if (addr == 0) {
 206                 if (val & 0x10) {
 207                         pic_reset(s);   /* init */
 208                         /*
 209                          * deassert a pending interrupt
 210                          */
 211                         s->pics_state->irq_request(s->pics_state->
 212                                                    irq_request_opaque, 0);
 213                         s->init_state = 1;
 214                         s->init4 = val & 1;
 215                         if (val & 0x02)
 216                                 printk(KERN_ERR "single mode not supported");
 217                         if (val & 0x08)
 218                                 printk(KERN_ERR
 219                                        "level sensitive irq not supported");
 220                 } else if (val & 0x08) {
 221                         if (val & 0x04)
 222                                 s->poll = 1;
 223                         if (val & 0x02)
 224                                 s->read_reg_select = val & 1;
 225                         if (val & 0x40)
 226                                 s->special_mask = (val >> 5) & 1;
 227                 } else {
 228                         cmd = val >> 5;
 229                         switch (cmd) {
 230                         case 0:
 231                         case 4:
 232                                 s->rotate_on_auto_eoi = cmd >> 2;
 233                                 break;
 234                         case 1: /* end of interrupt */
 235                         case 5:
 236                                 priority = get_priority(s, s->isr);
 237                                 if (priority != 8) {
 238                                         irq = (priority + s->priority_add) & 7;
 239                                         s->isr &= ~(1 << irq);
 240                                         if (cmd == 5)
 241                                                 s->priority_add = (irq + 1) & 7;
 242                                         pic_update_irq(s->pics_state);
 243                                 }
 244                                 break;
 245                         case 3:
 246                                 irq = val & 7;
 247                                 s->isr &= ~(1 << irq);
 248                                 pic_update_irq(s->pics_state);
 249                                 break;
 250                         case 6:
 251                                 s->priority_add = (val + 1) & 7;
 252                                 pic_update_irq(s->pics_state);
 253                                 break;
 254                         case 7:
 255                                 irq = val & 7;
 256                                 s->isr &= ~(1 << irq);
 257                                 s->priority_add = (irq + 1) & 7;
 258                                 pic_update_irq(s->pics_state);
 259                                 break;
 260                         default:
 261                                 break;  /* no operation */
 262                         }
 263                 }
 264         } else
 265                 switch (s->init_state) {
 266                 case 0:         /* normal mode */
 267                         s->imr = val;
 268                         pic_update_irq(s->pics_state);
 269                         break;
 270                 case 1:
 271                         s->irq_base = val & 0xf8;
 272                         s->init_state = 2;
 273                         break;
 274                 case 2:
 275                         if (s->init4)
 276                                 s->init_state = 3;
 277                         else
 278                                 s->init_state = 0;
 279                         break;
 280                 case 3:
 281                         s->special_fully_nested_mode = (val >> 4) & 1;
 282                         s->auto_eoi = (val >> 1) & 1;
 283                         s->init_state = 0;
 284                         break;
 285                 }
 286 }
 287
 288 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 289 {
 290         int ret;
 291
 292         ret = pic_get_irq(s);
 293         if (ret >= 0) {
 294                 if (addr1 >> 7) {
 295                         s->pics_state->pics[0].isr &= ~(1 << 2);
 296                         s->pics_state->pics[0].irr &= ~(1 << 2);
 297                 }
 298                 s->irr &= ~(1 << ret);
 299                 s->isr &= ~(1 << ret);
 300                 if (addr1 >> 7 || ret != 2)
 301                         pic_update_irq(s->pics_state);
 302         } else {
 303                 ret = 0x07;
 304                 pic_update_irq(s->pics_state);
 305         }
 306
 307         return ret;
 308 }
 309
 310 static u32 pic_ioport_read(void *opaque, u32 addr1)
 311 {
 312         struct kvm_kpic_state *s = opaque;
 313         unsigned int addr;
 314         int ret;
 315
 316         addr = addr1;
 317         addr &= 1;
 318         if (s->poll) {
 319                 ret = pic_poll_read(s, addr1);
 320                 s->poll = 0;
 321         } else
 322                 if (addr == 0)
 323                         if (s->read_reg_select)
 324                                 ret = s->isr;
 325                         else
 326                                 ret = s->irr;
 327                 else
 328                         ret = s->imr;
 329         return ret;
 330 }
 331
 332 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 333 {
 334         struct kvm_kpic_state *s = opaque;
 335         s->elcr = val & s->elcr_mask;
 336 }
 337
 338 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 339 {
 340         struct kvm_kpic_state *s = opaque;
 341         return s->elcr;
 342 }
 343
 344 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr)
 345 {
 346         switch (addr) {
 347         case 0x20:
 348         case 0x21:
 349         case 0xa0:
 350         case 0xa1:
 351         case 0x4d0:
 352         case 0x4d1:
 353                 return 1;
 354         default:
 355                 return 0;
 356         }
 357 }
 358
 359 static void picdev_write(struct kvm_io_device *this,
 360                          gpa_t addr, int len, const void *val)
 361 {
 362         struct kvm_pic *s = this->private;
 363         unsigned char data = *(unsigned char *)val;
 364
 365         if (len != 1) {
 366                 if (printk_ratelimit())
 367                         printk(KERN_ERR "PIC: non byte write\n");
 368                 return;
 369         }
 370         switch (addr) {
 371         case 0x20:
 372         case 0x21:
 373         case 0xa0:
 374         case 0xa1:
 375                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 376                 break;
 377         case 0x4d0:
 378         case 0x4d1:
 379                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 380                 break;
 381         }
 382 }
 383
 384 static void picdev_read(struct kvm_io_device *this,
 385                         gpa_t addr, int len, void *val)
 386 {
 387         struct kvm_pic *s = this->private;
 388         unsigned char data = 0;
 389
 390         if (len != 1) {
 391                 if (printk_ratelimit())
 392                         printk(KERN_ERR "PIC: non byte read\n");
 393                 return;
 394         }
 395         switch (addr) {
 396         case 0x20:
 397         case 0x21:
 398         case 0xa0:
 399         case 0xa1:
 400                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 401                 break;
 402         case 0x4d0:
 403         case 0x4d1:
 404                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 405                 break;
 406         }
 407         *(unsigned char *)val = data;
 408 }
 409
 410 /*
 411  * callback when PIC0 irq status changed
 412  */
 413 static void pic_irq_request(void *opaque, int level)
 414 {
 415         struct kvm *kvm = opaque;
 416
 417         pic_irqchip(kvm)->output = level;
 418 }
 419
 420 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 421 {
 422         struct kvm_pic *s;
 423         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 424         if (!s)
 425                 return NULL;
 426         s->pics[0].elcr_mask = 0xf8;
 427         s->pics[1].elcr_mask = 0xde;
 428         s->irq_request = pic_irq_request;
 429         s->irq_request_opaque = kvm;
 430         s->pics[0].pics_state = s;
 431         s->pics[1].pics_state = s;
 432
 433         /*
 434          * Initialize PIO device
 435          */
 436         s->dev.read = picdev_read;
 437         s->dev.write = picdev_write;
 438         s->dev.in_range = picdev_in_range;
 439         s->dev.private = s;
 440         kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
 441         return s;
 442 }