2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
38 #define QLA2XXX_DRIVER_NAME "qla2xxx"
39 #define QLA2XXX_APIDEV "ql2xapidev"
42 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
43 * but that's fine as we don't look at the last 24 ones for
46 #define MAILBOX_REGISTER_COUNT_2100 8
47 #define MAILBOX_REGISTER_COUNT 32
49 #define QLA2200A_RISC_ROM_VER 4
53 #include "qla_settings.h"
56 * Data bit definitions
74 #define BIT_16 0x10000
75 #define BIT_17 0x20000
76 #define BIT_18 0x40000
77 #define BIT_19 0x80000
78 #define BIT_20 0x100000
79 #define BIT_21 0x200000
80 #define BIT_22 0x400000
81 #define BIT_23 0x800000
82 #define BIT_24 0x1000000
83 #define BIT_25 0x2000000
84 #define BIT_26 0x4000000
85 #define BIT_27 0x8000000
86 #define BIT_28 0x10000000
87 #define BIT_29 0x20000000
88 #define BIT_30 0x40000000
89 #define BIT_31 0x80000000
91 #define LSB(x) ((uint8_t)(x))
92 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
94 #define LSW(x) ((uint16_t)(x))
95 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
97 #define LSD(x) ((uint32_t)((uint64_t)(x)))
98 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
100 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
106 #define RD_REG_BYTE(addr) readb(addr)
107 #define RD_REG_WORD(addr) readw(addr)
108 #define RD_REG_DWORD(addr) readl(addr)
109 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
110 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
111 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
112 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
113 #define WRT_REG_WORD(addr, data) writew(data,addr)
114 #define WRT_REG_DWORD(addr, data) writel(data,addr)
117 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
120 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
121 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
124 * Fibre Channel device definitions.
126 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
127 #define MAX_FIBRE_DEVICES 512
128 #define MAX_FIBRE_LUNS 0xFFFF
129 #define MAX_RSCN_COUNT 32
130 #define MAX_HOST_COUNT 16
133 * Host adapter default definitions.
135 #define MAX_BUSES 1 /* We only have one bus today */
136 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
137 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
139 #define MAX_LUNS MAX_FIBRE_LUNS
140 #define MAX_CMDS_PER_LUN 255
143 * Fibre Channel device definitions.
145 #define SNS_LAST_LOOP_ID_2100 0xfe
146 #define SNS_LAST_LOOP_ID_2300 0x7ff
148 #define LAST_LOCAL_LOOP_ID 0x7d
149 #define SNS_FL_PORT 0x7e
150 #define FABRIC_CONTROLLER 0x7f
151 #define SIMPLE_NAME_SERVER 0x80
152 #define SNS_FIRST_LOOP_ID 0x81
153 #define MANAGEMENT_SERVER 0xfe
154 #define BROADCAST 0xff
157 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
158 * valid range of an N-PORT id is 0 through 0x7ef.
160 #define NPH_LAST_HANDLE 0x7ef
161 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
162 #define NPH_SNS 0x7fc /* FFFFFC */
163 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
164 #define NPH_F_PORT 0x7fe /* FFFFFE */
165 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
167 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
171 * Timeout timer counts in seconds
173 #define PORT_RETRY_TIME 1
174 #define LOOP_DOWN_TIMEOUT 60
175 #define LOOP_DOWN_TIME 255 /* 240 */
176 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
178 /* Maximum outstanding commands in ISP queues (1-65535) */
179 #define MAX_OUTSTANDING_COMMANDS 1024
181 /* ISP request and response entry counts (37-65535) */
182 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
183 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
184 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
185 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
186 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
187 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
192 * (sd.h is not exported, hence local inclusion)
193 * Data Integrity Field tuple.
195 struct sd_dif_tuple {
196 __be16 guard_tag; /* Checksum */
197 __be16 app_tag; /* Opaque storage */
198 __be32 ref_tag; /* Target LBA or indirect LBA */
206 struct fc_port *fcport;
209 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
213 uint32_t request_sense_length;
214 uint8_t *request_sense_ptr;
220 * SRB flag definitions
222 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
223 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
224 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
225 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
226 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
228 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
229 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
238 #define SRB_LOGIN_RETRIED BIT_0
239 #define SRB_LOGIN_COND_PLOGI BIT_1
240 #define SRB_LOGIN_SKIP_PRLI BIT_2
245 * Values for flags field below are as
246 * defined in tsk_mgmt_entry struct
247 * for control_flags field in qla_fw.h.
255 * values for modif field below are as
256 * defined in mrk_entry_24xx struct
257 * for the modifier field in qla_fw.h.
265 struct timer_list timer;
267 void (*done)(srb_t *);
268 void (*free)(srb_t *);
269 void (*timeout)(srb_t *);
272 /* Values for srb_ctx type */
273 #define SRB_LOGIN_CMD 1
274 #define SRB_LOGOUT_CMD 2
275 #define SRB_ELS_CMD_RPT 3
276 #define SRB_ELS_CMD_HST 4
278 #define SRB_ADISC_CMD 6
280 #define SRB_MARKER_CMD 8
286 struct srb_iocb *iocb_cmd;
287 struct fc_bsg_job *bsg_job;
297 uint32_t transfer_size;
301 * ISP I/O Register Set structure definitions.
303 struct device_reg_2xxx {
304 uint16_t flash_address; /* Flash BIOS address */
305 uint16_t flash_data; /* Flash BIOS data */
306 uint16_t unused_1[1]; /* Gap */
307 uint16_t ctrl_status; /* Control/Status */
308 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
309 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
310 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
312 uint16_t ictrl; /* Interrupt control */
313 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
314 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
316 uint16_t istatus; /* Interrupt status */
317 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
319 uint16_t semaphore; /* Semaphore */
320 uint16_t nvram; /* NVRAM register. */
321 #define NVR_DESELECT 0
322 #define NVR_BUSY BIT_15
323 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
324 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
325 #define NVR_DATA_IN BIT_3
326 #define NVR_DATA_OUT BIT_2
327 #define NVR_SELECT BIT_1
328 #define NVR_CLOCK BIT_0
330 #define NVR_WAIT_CNT 20000
342 uint16_t unused_2[59]; /* Gap */
343 } __attribute__((packed)) isp2100;
346 uint16_t req_q_in; /* In-Pointer */
347 uint16_t req_q_out; /* Out-Pointer */
349 uint16_t rsp_q_in; /* In-Pointer */
350 uint16_t rsp_q_out; /* Out-Pointer */
352 /* RISC to Host Status */
353 uint32_t host_status;
354 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
355 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
357 /* Host to Host Semaphore */
358 uint16_t host_semaphore;
359 uint16_t unused_3[17]; /* Gap */
393 uint16_t unused_4[10]; /* Gap */
394 } __attribute__((packed)) isp2300;
397 uint16_t fpm_diag_config;
398 uint16_t unused_5[0x4]; /* Gap */
400 uint16_t unused_5_1; /* Gap */
401 uint16_t pcr; /* Processor Control Register. */
402 uint16_t unused_6[0x5]; /* Gap */
403 uint16_t mctr; /* Memory Configuration and Timing. */
404 uint16_t unused_7[0x3]; /* Gap */
405 uint16_t fb_cmd_2100; /* Unused on 23XX */
406 uint16_t unused_8[0x3]; /* Gap */
407 uint16_t hccr; /* Host command & control register. */
408 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
409 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
411 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
412 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
413 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
414 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
415 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
416 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
417 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
418 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
420 uint16_t unused_9[5]; /* Gap */
421 uint16_t gpiod; /* GPIO Data register. */
422 uint16_t gpioe; /* GPIO Enable register. */
423 #define GPIO_LED_MASK 0x00C0
424 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
425 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
426 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
427 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
428 #define GPIO_LED_ALL_OFF 0x0000
429 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
430 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
434 uint16_t unused_10[8]; /* Gap */
450 uint16_t mailbox23; /* Also probe reg. */
451 } __attribute__((packed)) isp2200;
455 struct device_reg_25xxmq {
463 struct device_reg_2xxx isp;
464 struct device_reg_24xx isp24;
465 struct device_reg_25xxmq isp25mq;
466 struct device_reg_82xx isp82;
469 #define ISP_REQ_Q_IN(ha, reg) \
470 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
471 &(reg)->u.isp2100.mailbox4 : \
472 &(reg)->u.isp2300.req_q_in)
473 #define ISP_REQ_Q_OUT(ha, reg) \
474 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
475 &(reg)->u.isp2100.mailbox4 : \
476 &(reg)->u.isp2300.req_q_out)
477 #define ISP_RSP_Q_IN(ha, reg) \
478 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
479 &(reg)->u.isp2100.mailbox5 : \
480 &(reg)->u.isp2300.rsp_q_in)
481 #define ISP_RSP_Q_OUT(ha, reg) \
482 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
483 &(reg)->u.isp2100.mailbox5 : \
484 &(reg)->u.isp2300.rsp_q_out)
486 #define MAILBOX_REG(ha, reg, num) \
487 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
489 &(reg)->u.isp2100.mailbox0 + (num) : \
490 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
491 &(reg)->u.isp2300.mailbox0 + (num))
492 #define RD_MAILBOX_REG(ha, reg, num) \
493 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
494 #define WRT_MAILBOX_REG(ha, reg, num, data) \
495 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
497 #define FB_CMD_REG(ha, reg) \
498 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
499 &(reg)->fb_cmd_2100 : \
500 &(reg)->u.isp2300.fb_cmd)
501 #define RD_FB_CMD_REG(ha, reg) \
502 RD_REG_WORD(FB_CMD_REG(ha, reg))
503 #define WRT_FB_CMD_REG(ha, reg, data) \
504 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
507 uint32_t out_mb; /* outbound from driver */
508 uint32_t in_mb; /* Incoming from RISC */
509 uint16_t mb[MAILBOX_REGISTER_COUNT];
514 #define MBX_DMA_IN BIT_0
515 #define MBX_DMA_OUT BIT_1
516 #define IOCTL_CMD BIT_2
519 #define MBX_TOV_SECONDS 30
522 * ISP product identification definitions in mailboxes after reset.
524 #define PROD_ID_1 0x4953
525 #define PROD_ID_2 0x0000
526 #define PROD_ID_2a 0x5020
527 #define PROD_ID_3 0x2020
530 * ISP mailbox Self-Test status codes
532 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
533 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
534 #define MBS_BUSY 4 /* Busy. */
537 * ISP mailbox command complete status codes
539 #define MBS_COMMAND_COMPLETE 0x4000
540 #define MBS_INVALID_COMMAND 0x4001
541 #define MBS_HOST_INTERFACE_ERROR 0x4002
542 #define MBS_TEST_FAILED 0x4003
543 #define MBS_COMMAND_ERROR 0x4005
544 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
545 #define MBS_PORT_ID_USED 0x4007
546 #define MBS_LOOP_ID_USED 0x4008
547 #define MBS_ALL_IDS_IN_USE 0x4009
548 #define MBS_NOT_LOGGED_IN 0x400A
549 #define MBS_LINK_DOWN_ERROR 0x400B
550 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
553 * ISP mailbox asynchronous event status codes
555 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
556 #define MBA_RESET 0x8001 /* Reset Detected. */
557 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
558 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
559 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
560 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
561 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
563 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
564 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
565 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
566 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
567 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
568 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
569 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
570 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
571 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
572 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
573 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
574 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
575 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
576 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
577 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
578 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
580 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
581 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
582 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
583 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
584 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
585 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
586 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
587 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
588 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
589 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
590 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
591 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
592 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
593 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
595 /* ISP mailbox loopback echo diagnostic error code */
596 #define MBS_LB_RESET 0x17
598 * Firmware options 1, 2, 3.
600 #define FO1_AE_ON_LIPF8 BIT_0
601 #define FO1_AE_ALL_LIP_RESET BIT_1
602 #define FO1_CTIO_RETRY BIT_3
603 #define FO1_DISABLE_LIP_F7_SW BIT_4
604 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
605 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
606 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
607 #define FO1_SET_EMPHASIS_SWING BIT_8
608 #define FO1_AE_AUTO_BYPASS BIT_9
609 #define FO1_ENABLE_PURE_IOCB BIT_10
610 #define FO1_AE_PLOGI_RJT BIT_11
611 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
612 #define FO1_AE_QUEUE_FULL BIT_13
614 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
615 #define FO2_REV_LOOPBACK BIT_1
617 #define FO3_ENABLE_EMERG_IOCB BIT_0
618 #define FO3_AE_RND_ERROR BIT_1
620 /* 24XX additional firmware options */
621 #define ADD_FO_COUNT 3
622 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
623 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
625 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
627 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
630 * ISP mailbox commands
632 #define MBC_LOAD_RAM 1 /* Load RAM. */
633 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
634 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
635 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
636 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
637 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
638 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
639 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
640 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
641 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
642 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
643 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
644 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
645 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
646 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
647 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
648 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
649 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
650 #define MBC_RESET 0x18 /* Reset. */
651 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
652 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
653 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
654 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
655 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
656 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
657 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
658 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
659 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
660 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
661 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
662 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
663 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
664 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
665 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
666 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
667 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
668 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
669 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
670 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
671 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
672 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
673 /* Initialization Procedure */
674 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
675 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
676 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
677 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
678 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
679 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
680 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
681 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
682 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
683 #define MBC_LIP_RESET 0x6c /* LIP reset. */
684 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
686 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
687 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
688 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
689 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
690 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
691 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
692 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
693 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
694 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
695 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
696 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
699 * ISP24xx mailbox commands
701 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
702 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
703 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
704 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
705 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
706 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
707 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
708 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
709 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
710 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
711 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
712 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
713 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
714 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
715 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
716 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
717 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
718 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
720 /* Firmware return data sizes */
721 #define FCAL_MAP_SIZE 128
723 /* Mailbox bit definitions for out_mb and in_mb */
724 #define MBX_31 BIT_31
725 #define MBX_30 BIT_30
726 #define MBX_29 BIT_29
727 #define MBX_28 BIT_28
728 #define MBX_27 BIT_27
729 #define MBX_26 BIT_26
730 #define MBX_25 BIT_25
731 #define MBX_24 BIT_24
732 #define MBX_23 BIT_23
733 #define MBX_22 BIT_22
734 #define MBX_21 BIT_21
735 #define MBX_20 BIT_20
736 #define MBX_19 BIT_19
737 #define MBX_18 BIT_18
738 #define MBX_17 BIT_17
739 #define MBX_16 BIT_16
740 #define MBX_15 BIT_15
741 #define MBX_14 BIT_14
742 #define MBX_13 BIT_13
743 #define MBX_12 BIT_12
744 #define MBX_11 BIT_11
745 #define MBX_10 BIT_10
758 * Firmware state codes from get firmware state mailbox command
760 #define FSTATE_CONFIG_WAIT 0
761 #define FSTATE_WAIT_AL_PA 1
762 #define FSTATE_WAIT_LOGIN 2
763 #define FSTATE_READY 3
764 #define FSTATE_LOSS_OF_SYNC 4
765 #define FSTATE_ERROR 5
766 #define FSTATE_REINIT 6
767 #define FSTATE_NON_PART 7
769 #define FSTATE_CONFIG_CORRECT 0
770 #define FSTATE_P2P_RCV_LIP 1
771 #define FSTATE_P2P_CHOOSE_LOOP 2
772 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
773 #define FSTATE_FATAL_ERROR 4
774 #define FSTATE_LOOP_BACK_CONN 5
777 * Port Database structure definition
778 * Little endian except where noted.
780 #define PORT_DATABASE_SIZE 128 /* bytes */
784 uint8_t master_state;
787 uint8_t hard_address;
790 uint8_t node_name[WWN_SIZE];
791 uint8_t port_name[WWN_SIZE];
792 uint16_t execution_throttle;
793 uint16_t execution_count;
796 uint16_t resource_allocation;
797 uint16_t current_allocation;
800 uint16_t transmit_execution_list_next;
801 uint16_t transmit_execution_list_previous;
802 uint16_t common_features;
803 uint16_t total_concurrent_sequences;
804 uint16_t RO_by_information_category;
807 uint16_t receive_data_size;
808 uint16_t concurrent_sequences;
809 uint16_t open_sequences_per_exchange;
810 uint16_t lun_abort_flags;
811 uint16_t lun_stop_flags;
812 uint16_t stop_queue_head;
813 uint16_t stop_queue_tail;
814 uint16_t port_retry_timer;
815 uint16_t next_sequence_id;
816 uint16_t frame_count;
817 uint16_t PRLI_payload_length;
818 uint8_t prli_svc_param_word_0[2]; /* Big endian */
819 /* Bits 15-0 of word 0 */
820 uint8_t prli_svc_param_word_3[2]; /* Big endian */
821 /* Bits 15-0 of word 3 */
823 uint16_t extended_lun_info_list_pointer;
824 uint16_t extended_lun_stop_list_pointer;
828 * Port database slave/master states
830 #define PD_STATE_DISCOVERY 0
831 #define PD_STATE_WAIT_DISCOVERY_ACK 1
832 #define PD_STATE_PORT_LOGIN 2
833 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
834 #define PD_STATE_PROCESS_LOGIN 4
835 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
836 #define PD_STATE_PORT_LOGGED_IN 6
837 #define PD_STATE_PORT_UNAVAILABLE 7
838 #define PD_STATE_PROCESS_LOGOUT 8
839 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
840 #define PD_STATE_PORT_LOGOUT 10
841 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
844 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
845 #define QLA_ZIO_DISABLED 0
846 #define QLA_ZIO_DEFAULT_TIMER 2
849 * ISP Initialization Control Block.
850 * Little endian except where noted.
852 #define ICB_VERSION 1
858 * LSB BIT 0 = Enable Hard Loop Id
859 * LSB BIT 1 = Enable Fairness
860 * LSB BIT 2 = Enable Full-Duplex
861 * LSB BIT 3 = Enable Fast Posting
862 * LSB BIT 4 = Enable Target Mode
863 * LSB BIT 5 = Disable Initiator Mode
864 * LSB BIT 6 = Enable ADISC
865 * LSB BIT 7 = Enable Target Inquiry Data
867 * MSB BIT 0 = Enable PDBC Notify
868 * MSB BIT 1 = Non Participating LIP
869 * MSB BIT 2 = Descending Loop ID Search
870 * MSB BIT 3 = Acquire Loop ID in LIPA
871 * MSB BIT 4 = Stop PortQ on Full Status
872 * MSB BIT 5 = Full Login after LIP
873 * MSB BIT 6 = Node Name Option
874 * MSB BIT 7 = Ext IFWCB enable bit
876 uint8_t firmware_options[2];
878 uint16_t frame_payload_size;
879 uint16_t max_iocb_allocation;
880 uint16_t execution_throttle;
882 uint8_t retry_delay; /* unused */
883 uint8_t port_name[WWN_SIZE]; /* Big endian. */
884 uint16_t hard_address;
885 uint8_t inquiry_data;
886 uint8_t login_timeout;
887 uint8_t node_name[WWN_SIZE]; /* Big endian. */
889 uint16_t request_q_outpointer;
890 uint16_t response_q_inpointer;
891 uint16_t request_q_length;
892 uint16_t response_q_length;
893 uint32_t request_q_address[2];
894 uint32_t response_q_address[2];
896 uint16_t lun_enables;
897 uint8_t command_resource_count;
898 uint8_t immediate_notify_resource_count;
900 uint8_t reserved_2[2];
903 * LSB BIT 0 = Timer Operation mode bit 0
904 * LSB BIT 1 = Timer Operation mode bit 1
905 * LSB BIT 2 = Timer Operation mode bit 2
906 * LSB BIT 3 = Timer Operation mode bit 3
907 * LSB BIT 4 = Init Config Mode bit 0
908 * LSB BIT 5 = Init Config Mode bit 1
909 * LSB BIT 6 = Init Config Mode bit 2
910 * LSB BIT 7 = Enable Non part on LIHA failure
912 * MSB BIT 0 = Enable class 2
913 * MSB BIT 1 = Enable ACK0
916 * MSB BIT 4 = FC Tape Enable
917 * MSB BIT 5 = Enable FC Confirm
918 * MSB BIT 6 = Enable command queuing in target mode
919 * MSB BIT 7 = No Logo On Link Down
921 uint8_t add_firmware_options[2];
923 uint8_t response_accumulation_timer;
924 uint8_t interrupt_delay_timer;
927 * LSB BIT 0 = Enable Read xfr_rdy
928 * LSB BIT 1 = Soft ID only
931 * LSB BIT 4 = FCP RSP Payload [0]
932 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
933 * LSB BIT 6 = Enable Out-of-Order frame handling
934 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
936 * MSB BIT 0 = Sbus enable - 2300
940 * MSB BIT 4 = LED mode
941 * MSB BIT 5 = enable 50 ohm termination
942 * MSB BIT 6 = Data Rate (2300 only)
943 * MSB BIT 7 = Data Rate (2300 only)
945 uint8_t special_options[2];
947 uint8_t reserved_3[26];
951 * Get Link Status mailbox command return buffer.
953 #define GLSO_SEND_RPS BIT_0
954 #define GLSO_USE_DID BIT_3
956 struct link_statistics {
957 uint32_t link_fail_cnt;
958 uint32_t loss_sync_cnt;
959 uint32_t loss_sig_cnt;
960 uint32_t prim_seq_err_cnt;
961 uint32_t inval_xmit_word_cnt;
962 uint32_t inval_crc_cnt;
964 uint32_t unused1[0x1a];
967 uint32_t dumped_frames;
973 * NVRAM Command values.
975 #define NV_START_BIT BIT_2
976 #define NV_WRITE_OP (BIT_26+BIT_24)
977 #define NV_READ_OP (BIT_26+BIT_25)
978 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
979 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
980 #define NV_DELAY_COUNT 10
983 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
990 uint8_t nvram_version;
994 * NVRAM RISC parameter block
996 uint8_t parameter_block_version;
1000 * LSB BIT 0 = Enable Hard Loop Id
1001 * LSB BIT 1 = Enable Fairness
1002 * LSB BIT 2 = Enable Full-Duplex
1003 * LSB BIT 3 = Enable Fast Posting
1004 * LSB BIT 4 = Enable Target Mode
1005 * LSB BIT 5 = Disable Initiator Mode
1006 * LSB BIT 6 = Enable ADISC
1007 * LSB BIT 7 = Enable Target Inquiry Data
1009 * MSB BIT 0 = Enable PDBC Notify
1010 * MSB BIT 1 = Non Participating LIP
1011 * MSB BIT 2 = Descending Loop ID Search
1012 * MSB BIT 3 = Acquire Loop ID in LIPA
1013 * MSB BIT 4 = Stop PortQ on Full Status
1014 * MSB BIT 5 = Full Login after LIP
1015 * MSB BIT 6 = Node Name Option
1016 * MSB BIT 7 = Ext IFWCB enable bit
1018 uint8_t firmware_options[2];
1020 uint16_t frame_payload_size;
1021 uint16_t max_iocb_allocation;
1022 uint16_t execution_throttle;
1023 uint8_t retry_count;
1024 uint8_t retry_delay; /* unused */
1025 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1026 uint16_t hard_address;
1027 uint8_t inquiry_data;
1028 uint8_t login_timeout;
1029 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1032 * LSB BIT 0 = Timer Operation mode bit 0
1033 * LSB BIT 1 = Timer Operation mode bit 1
1034 * LSB BIT 2 = Timer Operation mode bit 2
1035 * LSB BIT 3 = Timer Operation mode bit 3
1036 * LSB BIT 4 = Init Config Mode bit 0
1037 * LSB BIT 5 = Init Config Mode bit 1
1038 * LSB BIT 6 = Init Config Mode bit 2
1039 * LSB BIT 7 = Enable Non part on LIHA failure
1041 * MSB BIT 0 = Enable class 2
1042 * MSB BIT 1 = Enable ACK0
1045 * MSB BIT 4 = FC Tape Enable
1046 * MSB BIT 5 = Enable FC Confirm
1047 * MSB BIT 6 = Enable command queuing in target mode
1048 * MSB BIT 7 = No Logo On Link Down
1050 uint8_t add_firmware_options[2];
1052 uint8_t response_accumulation_timer;
1053 uint8_t interrupt_delay_timer;
1056 * LSB BIT 0 = Enable Read xfr_rdy
1057 * LSB BIT 1 = Soft ID only
1060 * LSB BIT 4 = FCP RSP Payload [0]
1061 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1062 * LSB BIT 6 = Enable Out-of-Order frame handling
1063 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1065 * MSB BIT 0 = Sbus enable - 2300
1069 * MSB BIT 4 = LED mode
1070 * MSB BIT 5 = enable 50 ohm termination
1071 * MSB BIT 6 = Data Rate (2300 only)
1072 * MSB BIT 7 = Data Rate (2300 only)
1074 uint8_t special_options[2];
1076 /* Reserved for expanded RISC parameter block */
1077 uint8_t reserved_2[22];
1080 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1081 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1082 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1083 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1084 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1085 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1086 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1087 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1089 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1090 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1091 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1092 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1093 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1094 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1095 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1096 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1098 * LSB BIT 0 = Output Swing 1G bit 0
1099 * LSB BIT 1 = Output Swing 1G bit 1
1100 * LSB BIT 2 = Output Swing 1G bit 2
1101 * LSB BIT 3 = Output Emphasis 1G bit 0
1102 * LSB BIT 4 = Output Emphasis 1G bit 1
1103 * LSB BIT 5 = Output Swing 2G bit 0
1104 * LSB BIT 6 = Output Swing 2G bit 1
1105 * LSB BIT 7 = Output Swing 2G bit 2
1107 * MSB BIT 0 = Output Emphasis 2G bit 0
1108 * MSB BIT 1 = Output Emphasis 2G bit 1
1109 * MSB BIT 2 = Output Enable
1116 uint8_t seriallink_options[4];
1119 * NVRAM host parameter block
1121 * LSB BIT 0 = Enable spinup delay
1122 * LSB BIT 1 = Disable BIOS
1123 * LSB BIT 2 = Enable Memory Map BIOS
1124 * LSB BIT 3 = Enable Selectable Boot
1125 * LSB BIT 4 = Disable RISC code load
1126 * LSB BIT 5 = Set cache line size 1
1127 * LSB BIT 6 = PCI Parity Disable
1128 * LSB BIT 7 = Enable extended logging
1130 * MSB BIT 0 = Enable 64bit addressing
1131 * MSB BIT 1 = Enable lip reset
1132 * MSB BIT 2 = Enable lip full login
1133 * MSB BIT 3 = Enable target reset
1134 * MSB BIT 4 = Enable database storage
1135 * MSB BIT 5 = Enable cache flush read
1136 * MSB BIT 6 = Enable database load
1137 * MSB BIT 7 = Enable alternate WWN
1141 uint8_t boot_node_name[WWN_SIZE];
1142 uint8_t boot_lun_number;
1143 uint8_t reset_delay;
1144 uint8_t port_down_retry_count;
1145 uint8_t boot_id_number;
1146 uint16_t max_luns_per_target;
1147 uint8_t fcode_boot_port_name[WWN_SIZE];
1148 uint8_t alternate_port_name[WWN_SIZE];
1149 uint8_t alternate_node_name[WWN_SIZE];
1152 * BIT 0 = Selective Login
1153 * BIT 1 = Alt-Boot Enable
1155 * BIT 3 = Boot Order List
1157 * BIT 5 = Selective LUN
1161 uint8_t efi_parameters;
1163 uint8_t link_down_timeout;
1165 uint8_t adapter_id[16];
1167 uint8_t alt1_boot_node_name[WWN_SIZE];
1168 uint16_t alt1_boot_lun_number;
1169 uint8_t alt2_boot_node_name[WWN_SIZE];
1170 uint16_t alt2_boot_lun_number;
1171 uint8_t alt3_boot_node_name[WWN_SIZE];
1172 uint16_t alt3_boot_lun_number;
1173 uint8_t alt4_boot_node_name[WWN_SIZE];
1174 uint16_t alt4_boot_lun_number;
1175 uint8_t alt5_boot_node_name[WWN_SIZE];
1176 uint16_t alt5_boot_lun_number;
1177 uint8_t alt6_boot_node_name[WWN_SIZE];
1178 uint16_t alt6_boot_lun_number;
1179 uint8_t alt7_boot_node_name[WWN_SIZE];
1180 uint16_t alt7_boot_lun_number;
1182 uint8_t reserved_3[2];
1184 /* Offset 200-215 : Model Number */
1185 uint8_t model_number[16];
1187 /* OEM related items */
1188 uint8_t oem_specific[16];
1191 * NVRAM Adapter Features offset 232-239
1193 * LSB BIT 0 = External GBIC
1194 * LSB BIT 1 = Risc RAM parity
1195 * LSB BIT 2 = Buffer Plus Module
1196 * LSB BIT 3 = Multi Chip Adapter
1197 * LSB BIT 4 = Internal connector
1211 uint8_t adapter_features[2];
1213 uint8_t reserved_4[16];
1215 /* Subsystem vendor ID for ISP2200 */
1216 uint16_t subsystem_vendor_id_2200;
1218 /* Subsystem device ID for ISP2200 */
1219 uint16_t subsystem_device_id_2200;
1226 * ISP queue - response queue entry definition.
1231 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1242 #define SET_TARGET_ID(ha, to, from) \
1244 if (HAS_EXTENDED_IDS(ha)) \
1245 to.extended = cpu_to_le16(from); \
1247 to.id.standard = (uint8_t)from; \
1251 * ISP queue - command entry structure definition.
1253 #define COMMAND_TYPE 0x11 /* Command entry */
1255 uint8_t entry_type; /* Entry type. */
1256 uint8_t entry_count; /* Entry count. */
1257 uint8_t sys_define; /* System defined. */
1258 uint8_t entry_status; /* Entry Status. */
1259 uint32_t handle; /* System handle. */
1260 target_id_t target; /* SCSI ID */
1261 uint16_t lun; /* SCSI LUN */
1262 uint16_t control_flags; /* Control flags. */
1263 #define CF_WRITE BIT_6
1264 #define CF_READ BIT_5
1265 #define CF_SIMPLE_TAG BIT_3
1266 #define CF_ORDERED_TAG BIT_2
1267 #define CF_HEAD_TAG BIT_1
1268 uint16_t reserved_1;
1269 uint16_t timeout; /* Command timeout. */
1270 uint16_t dseg_count; /* Data segment count. */
1271 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1272 uint32_t byte_count; /* Total byte count. */
1273 uint32_t dseg_0_address; /* Data segment 0 address. */
1274 uint32_t dseg_0_length; /* Data segment 0 length. */
1275 uint32_t dseg_1_address; /* Data segment 1 address. */
1276 uint32_t dseg_1_length; /* Data segment 1 length. */
1277 uint32_t dseg_2_address; /* Data segment 2 address. */
1278 uint32_t dseg_2_length; /* Data segment 2 length. */
1282 * ISP queue - 64-Bit addressing, command entry structure definition.
1284 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1286 uint8_t entry_type; /* Entry type. */
1287 uint8_t entry_count; /* Entry count. */
1288 uint8_t sys_define; /* System defined. */
1289 uint8_t entry_status; /* Entry Status. */
1290 uint32_t handle; /* System handle. */
1291 target_id_t target; /* SCSI ID */
1292 uint16_t lun; /* SCSI LUN */
1293 uint16_t control_flags; /* Control flags. */
1294 uint16_t reserved_1;
1295 uint16_t timeout; /* Command timeout. */
1296 uint16_t dseg_count; /* Data segment count. */
1297 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1298 uint32_t byte_count; /* Total byte count. */
1299 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1300 uint32_t dseg_0_length; /* Data segment 0 length. */
1301 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1302 uint32_t dseg_1_length; /* Data segment 1 length. */
1303 } cmd_a64_entry_t, request_t;
1306 * ISP queue - continuation entry structure definition.
1308 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1310 uint8_t entry_type; /* Entry type. */
1311 uint8_t entry_count; /* Entry count. */
1312 uint8_t sys_define; /* System defined. */
1313 uint8_t entry_status; /* Entry Status. */
1315 uint32_t dseg_0_address; /* Data segment 0 address. */
1316 uint32_t dseg_0_length; /* Data segment 0 length. */
1317 uint32_t dseg_1_address; /* Data segment 1 address. */
1318 uint32_t dseg_1_length; /* Data segment 1 length. */
1319 uint32_t dseg_2_address; /* Data segment 2 address. */
1320 uint32_t dseg_2_length; /* Data segment 2 length. */
1321 uint32_t dseg_3_address; /* Data segment 3 address. */
1322 uint32_t dseg_3_length; /* Data segment 3 length. */
1323 uint32_t dseg_4_address; /* Data segment 4 address. */
1324 uint32_t dseg_4_length; /* Data segment 4 length. */
1325 uint32_t dseg_5_address; /* Data segment 5 address. */
1326 uint32_t dseg_5_length; /* Data segment 5 length. */
1327 uint32_t dseg_6_address; /* Data segment 6 address. */
1328 uint32_t dseg_6_length; /* Data segment 6 length. */
1332 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1334 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1336 uint8_t entry_type; /* Entry type. */
1337 uint8_t entry_count; /* Entry count. */
1338 uint8_t sys_define; /* System defined. */
1339 uint8_t entry_status; /* Entry Status. */
1340 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1341 uint32_t dseg_0_length; /* Data segment 0 length. */
1342 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1343 uint32_t dseg_1_length; /* Data segment 1 length. */
1344 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1345 uint32_t dseg_2_length; /* Data segment 2 length. */
1346 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1347 uint32_t dseg_3_length; /* Data segment 3 length. */
1348 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1349 uint32_t dseg_4_length; /* Data segment 4 length. */
1352 #define PO_MODE_DIF_INSERT 0
1353 #define PO_MODE_DIF_REMOVE BIT_0
1354 #define PO_MODE_DIF_PASS BIT_1
1355 #define PO_MODE_DIF_REPLACE (BIT_0 + BIT_1)
1356 #define PO_ENABLE_DIF_BUNDLING BIT_8
1357 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
1358 #define PO_DISABLE_INCR_REF_TAG BIT_5
1359 #define PO_DISABLE_GUARD_CHECK BIT_4
1361 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
1363 struct crc_context {
1364 uint32_t handle; /* System handle. */
1367 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
1368 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
1369 uint16_t guard_seed; /* Initial Guard Seed */
1370 uint16_t prot_opts; /* Requested Data Protection Mode */
1371 uint16_t blk_size; /* Data size in bytes */
1372 uint16_t runt_blk_guard; /* Guard value for runt block (tape
1374 uint32_t byte_count; /* Total byte count/ total data
1378 uint32_t reserved_1;
1379 uint16_t reserved_2;
1380 uint16_t reserved_3;
1381 uint32_t reserved_4;
1382 uint32_t data_address[2];
1383 uint32_t data_length;
1384 uint32_t reserved_5[2];
1385 uint32_t reserved_6;
1388 uint32_t dif_byte_count; /* Total DIF byte
1390 uint16_t reserved_1;
1391 uint16_t dseg_count; /* Data segment count */
1392 uint32_t reserved_2;
1393 uint32_t data_address[2];
1394 uint32_t data_length;
1395 uint32_t dif_address[2];
1396 uint32_t dif_length; /* Data segment 0
1401 struct fcp_cmnd fcp_cmnd;
1402 dma_addr_t crc_ctx_dma;
1403 /* List of DMA context transfers */
1404 struct list_head dsd_list;
1406 /* This structure should not exceed 512 bytes */
1409 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
1410 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
1413 * ISP queue - status entry structure definition.
1415 #define STATUS_TYPE 0x03 /* Status entry. */
1417 uint8_t entry_type; /* Entry type. */
1418 uint8_t entry_count; /* Entry count. */
1419 uint8_t sys_define; /* System defined. */
1420 uint8_t entry_status; /* Entry Status. */
1421 uint32_t handle; /* System handle. */
1422 uint16_t scsi_status; /* SCSI status. */
1423 uint16_t comp_status; /* Completion status. */
1424 uint16_t state_flags; /* State flags. */
1425 uint16_t status_flags; /* Status flags. */
1426 uint16_t rsp_info_len; /* Response Info Length. */
1427 uint16_t req_sense_length; /* Request sense data length. */
1428 uint32_t residual_length; /* Residual transfer length. */
1429 uint8_t rsp_info[8]; /* FCP response information. */
1430 uint8_t req_sense_data[32]; /* Request sense data. */
1434 * Status entry entry status
1436 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1437 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1438 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1439 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1440 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1441 #define RF_BUSY BIT_1 /* Busy */
1442 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1443 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1444 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1448 * Status entry SCSI status bit definitions.
1450 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1451 #define SS_RESIDUAL_UNDER BIT_11
1452 #define SS_RESIDUAL_OVER BIT_10
1453 #define SS_SENSE_LEN_VALID BIT_9
1454 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1456 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1457 #define SS_BUSY_CONDITION BIT_3
1458 #define SS_CONDITION_MET BIT_2
1459 #define SS_CHECK_CONDITION BIT_1
1462 * Status entry completion status
1464 #define CS_COMPLETE 0x0 /* No errors */
1465 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1466 #define CS_DMA 0x2 /* A DMA direction error. */
1467 #define CS_TRANSPORT 0x3 /* Transport error. */
1468 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1469 #define CS_ABORTED 0x5 /* System aborted command. */
1470 #define CS_TIMEOUT 0x6 /* Timeout error. */
1471 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1472 #define CS_DIF_ERROR 0xC /* DIF error detected */
1474 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1475 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1476 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1477 /* (selection timeout) */
1478 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1479 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1480 #define CS_PORT_BUSY 0x2B /* Port Busy */
1481 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1482 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1483 #define CS_UNKNOWN 0x81 /* Driver defined */
1484 #define CS_RETRY 0x82 /* Driver defined */
1485 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1488 * Status entry status flags
1490 #define SF_ABTS_TERMINATED BIT_10
1491 #define SF_LOGOUT_SENT BIT_13
1494 * ISP queue - status continuation entry structure definition.
1496 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1498 uint8_t entry_type; /* Entry type. */
1499 uint8_t entry_count; /* Entry count. */
1500 uint8_t sys_define; /* System defined. */
1501 uint8_t entry_status; /* Entry Status. */
1502 uint8_t data[60]; /* data */
1506 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1507 * structure definition.
1509 #define STATUS_TYPE_21 0x21 /* Status entry. */
1511 uint8_t entry_type; /* Entry type. */
1512 uint8_t entry_count; /* Entry count. */
1513 uint8_t handle_count; /* Handle count. */
1514 uint8_t entry_status; /* Entry Status. */
1515 uint32_t handle[15]; /* System handles. */
1519 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1520 * structure definition.
1522 #define STATUS_TYPE_22 0x22 /* Status entry. */
1524 uint8_t entry_type; /* Entry type. */
1525 uint8_t entry_count; /* Entry count. */
1526 uint8_t handle_count; /* Handle count. */
1527 uint8_t entry_status; /* Entry Status. */
1528 uint16_t handle[30]; /* System handles. */
1532 * ISP queue - marker entry structure definition.
1534 #define MARKER_TYPE 0x04 /* Marker entry. */
1536 uint8_t entry_type; /* Entry type. */
1537 uint8_t entry_count; /* Entry count. */
1538 uint8_t handle_count; /* Handle count. */
1539 uint8_t entry_status; /* Entry Status. */
1540 uint32_t sys_define_2; /* System defined. */
1541 target_id_t target; /* SCSI ID */
1542 uint8_t modifier; /* Modifier (7-0). */
1543 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1544 #define MK_SYNC_ID 1 /* Synchronize ID */
1545 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1546 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1547 /* clear port changed, */
1548 /* use sequence number. */
1550 uint16_t sequence_number; /* Sequence number of event */
1551 uint16_t lun; /* SCSI LUN */
1552 uint8_t reserved_2[48];
1556 * ISP queue - Management Server entry structure definition.
1558 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1560 uint8_t entry_type; /* Entry type. */
1561 uint8_t entry_count; /* Entry count. */
1562 uint8_t handle_count; /* Handle count. */
1563 uint8_t entry_status; /* Entry Status. */
1564 uint32_t handle1; /* System handle. */
1565 target_id_t loop_id;
1567 uint16_t control_flags; /* Control flags. */
1570 uint16_t cmd_dsd_count;
1571 uint16_t total_dsd_count;
1577 uint32_t rsp_bytecount;
1578 uint32_t req_bytecount;
1579 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1580 uint32_t dseg_req_length; /* Data segment 0 length. */
1581 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1582 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1587 * ISP queue - Mailbox Command entry structure definition.
1589 #define MBX_IOCB_TYPE 0x39
1592 uint8_t entry_count;
1593 uint8_t sys_define1;
1594 /* Use sys_define1 for source type */
1595 #define SOURCE_SCSI 0x00
1596 #define SOURCE_IP 0x01
1597 #define SOURCE_VI 0x02
1598 #define SOURCE_SCTP 0x03
1599 #define SOURCE_MP 0x04
1600 #define SOURCE_MPIOCTL 0x05
1601 #define SOURCE_ASYNC_IOCB 0x07
1603 uint8_t entry_status;
1606 target_id_t loop_id;
1609 uint16_t state_flags;
1610 uint16_t status_flags;
1612 uint32_t sys_define2[2];
1622 uint32_t reserved_2[2];
1623 uint8_t node_name[WWN_SIZE];
1624 uint8_t port_name[WWN_SIZE];
1628 * ISP request and response queue entry sizes
1630 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1631 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1635 * 24 bit port ID type definition.
1645 #elif defined(__LITTLE_ENDIAN)
1650 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1655 #define INVALID_PORT_ID 0xFFFFFF
1658 * Switch info gathering structure.
1662 uint8_t node_name[WWN_SIZE];
1663 uint8_t port_name[WWN_SIZE];
1664 uint8_t fabric_port_name[WWN_SIZE];
1669 * Fibre channel port type.
1681 * Fibre channel port structure.
1683 typedef struct fc_port {
1684 struct list_head list;
1685 struct scsi_qla_host *vha;
1687 uint8_t node_name[WWN_SIZE];
1688 uint8_t port_name[WWN_SIZE];
1691 uint16_t old_loop_id;
1695 uint8_t fabric_port_name[WWN_SIZE];
1698 fc_port_type_t port_type;
1703 int port_login_retry_count;
1705 atomic_t port_down_timer;
1707 struct fc_rport *rport, *drport;
1708 u32 supported_classes;
1714 * Fibre channel port/lun states.
1716 #define FCS_UNCONFIGURED 1
1717 #define FCS_DEVICE_DEAD 2
1718 #define FCS_DEVICE_LOST 3
1719 #define FCS_ONLINE 4
1724 #define FCF_FABRIC_DEVICE BIT_0
1725 #define FCF_LOGIN_NEEDED BIT_1
1726 #define FCF_FCP2_DEVICE BIT_2
1727 #define FCF_ASYNC_SENT BIT_3
1729 /* No loop ID flag. */
1730 #define FC_NO_LOOP_ID 0x1000
1735 * NOTE: All structures are big-endian in form.
1738 #define CT_REJECT_RESPONSE 0x8001
1739 #define CT_ACCEPT_RESPONSE 0x8002
1740 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1741 #define CT_REASON_CANNOT_PERFORM 0x09
1742 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1743 #define CT_EXPL_ALREADY_REGISTERED 0x10
1745 #define NS_N_PORT_TYPE 0x01
1746 #define NS_NL_PORT_TYPE 0x02
1747 #define NS_NX_PORT_TYPE 0x7F
1749 #define GA_NXT_CMD 0x100
1750 #define GA_NXT_REQ_SIZE (16 + 4)
1751 #define GA_NXT_RSP_SIZE (16 + 620)
1753 #define GID_PT_CMD 0x1A1
1754 #define GID_PT_REQ_SIZE (16 + 4)
1755 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1757 #define GPN_ID_CMD 0x112
1758 #define GPN_ID_REQ_SIZE (16 + 4)
1759 #define GPN_ID_RSP_SIZE (16 + 8)
1761 #define GNN_ID_CMD 0x113
1762 #define GNN_ID_REQ_SIZE (16 + 4)
1763 #define GNN_ID_RSP_SIZE (16 + 8)
1765 #define GFT_ID_CMD 0x117
1766 #define GFT_ID_REQ_SIZE (16 + 4)
1767 #define GFT_ID_RSP_SIZE (16 + 32)
1769 #define RFT_ID_CMD 0x217
1770 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1771 #define RFT_ID_RSP_SIZE 16
1773 #define RFF_ID_CMD 0x21F
1774 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1775 #define RFF_ID_RSP_SIZE 16
1777 #define RNN_ID_CMD 0x213
1778 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1779 #define RNN_ID_RSP_SIZE 16
1781 #define RSNN_NN_CMD 0x239
1782 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1783 #define RSNN_NN_RSP_SIZE 16
1785 #define GFPN_ID_CMD 0x11C
1786 #define GFPN_ID_REQ_SIZE (16 + 4)
1787 #define GFPN_ID_RSP_SIZE (16 + 8)
1789 #define GPSC_CMD 0x127
1790 #define GPSC_REQ_SIZE (16 + 8)
1791 #define GPSC_RSP_SIZE (16 + 2 + 2)
1795 * HBA attribute types.
1797 #define FDMI_HBA_ATTR_COUNT 9
1798 #define FDMI_HBA_NODE_NAME 1
1799 #define FDMI_HBA_MANUFACTURER 2
1800 #define FDMI_HBA_SERIAL_NUMBER 3
1801 #define FDMI_HBA_MODEL 4
1802 #define FDMI_HBA_MODEL_DESCRIPTION 5
1803 #define FDMI_HBA_HARDWARE_VERSION 6
1804 #define FDMI_HBA_DRIVER_VERSION 7
1805 #define FDMI_HBA_OPTION_ROM_VERSION 8
1806 #define FDMI_HBA_FIRMWARE_VERSION 9
1807 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1808 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1810 struct ct_fdmi_hba_attr {
1814 uint8_t node_name[WWN_SIZE];
1815 uint8_t manufacturer[32];
1816 uint8_t serial_num[8];
1818 uint8_t model_desc[80];
1819 uint8_t hw_version[16];
1820 uint8_t driver_version[32];
1821 uint8_t orom_version[16];
1822 uint8_t fw_version[16];
1823 uint8_t os_version[128];
1824 uint8_t max_ct_len[4];
1828 struct ct_fdmi_hba_attributes {
1830 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1834 * Port attribute types.
1836 #define FDMI_PORT_ATTR_COUNT 6
1837 #define FDMI_PORT_FC4_TYPES 1
1838 #define FDMI_PORT_SUPPORT_SPEED 2
1839 #define FDMI_PORT_CURRENT_SPEED 3
1840 #define FDMI_PORT_MAX_FRAME_SIZE 4
1841 #define FDMI_PORT_OS_DEVICE_NAME 5
1842 #define FDMI_PORT_HOST_NAME 6
1844 #define FDMI_PORT_SPEED_1GB 0x1
1845 #define FDMI_PORT_SPEED_2GB 0x2
1846 #define FDMI_PORT_SPEED_10GB 0x4
1847 #define FDMI_PORT_SPEED_4GB 0x8
1848 #define FDMI_PORT_SPEED_8GB 0x10
1849 #define FDMI_PORT_SPEED_16GB 0x20
1850 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1852 struct ct_fdmi_port_attr {
1856 uint8_t fc4_types[32];
1859 uint32_t max_frame_size;
1860 uint8_t os_dev_name[32];
1861 uint8_t host_name[32];
1866 * Port Attribute Block.
1868 struct ct_fdmi_port_attributes {
1870 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1873 /* FDMI definitions. */
1874 #define GRHL_CMD 0x100
1875 #define GHAT_CMD 0x101
1876 #define GRPL_CMD 0x102
1877 #define GPAT_CMD 0x110
1879 #define RHBA_CMD 0x200
1880 #define RHBA_RSP_SIZE 16
1882 #define RHAT_CMD 0x201
1883 #define RPRT_CMD 0x210
1885 #define RPA_CMD 0x211
1886 #define RPA_RSP_SIZE 16
1888 #define DHBA_CMD 0x300
1889 #define DHBA_REQ_SIZE (16 + 8)
1890 #define DHBA_RSP_SIZE 16
1892 #define DHAT_CMD 0x301
1893 #define DPRT_CMD 0x310
1894 #define DPA_CMD 0x311
1896 /* CT command header -- request/response common fields */
1906 /* CT command request */
1908 struct ct_cmd_hdr header;
1910 uint16_t max_rsp_size;
1911 uint8_t fragment_id;
1912 uint8_t reserved[3];
1915 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1931 uint8_t fc4_types[32];
1938 uint8_t fc4_feature;
1945 uint8_t node_name[8];
1949 uint8_t node_name[8];
1951 uint8_t sym_node_name[255];
1955 uint8_t hba_indentifier[8];
1959 uint8_t hba_identifier[8];
1960 uint32_t entry_count;
1961 uint8_t port_name[8];
1962 struct ct_fdmi_hba_attributes attrs;
1966 uint8_t hba_identifier[8];
1967 struct ct_fdmi_hba_attributes attrs;
1971 uint8_t port_name[8];
1972 struct ct_fdmi_port_attributes attrs;
1976 uint8_t port_name[8];
1980 uint8_t port_name[8];
1984 uint8_t port_name[8];
1988 uint8_t port_name[8];
1992 uint8_t port_name[8];
1997 /* CT command response header */
1999 struct ct_cmd_hdr header;
2002 uint8_t fragment_id;
2003 uint8_t reason_code;
2004 uint8_t explanation_code;
2005 uint8_t vendor_unique;
2008 struct ct_sns_gid_pt_data {
2009 uint8_t control_byte;
2014 struct ct_rsp_hdr header;
2020 uint8_t port_name[8];
2021 uint8_t sym_port_name_len;
2022 uint8_t sym_port_name[255];
2023 uint8_t node_name[8];
2024 uint8_t sym_node_name_len;
2025 uint8_t sym_node_name[255];
2026 uint8_t init_proc_assoc[8];
2027 uint8_t node_ip_addr[16];
2028 uint8_t class_of_service[4];
2029 uint8_t fc4_types[32];
2030 uint8_t ip_address[16];
2031 uint8_t fabric_port_name[8];
2033 uint8_t hard_address[3];
2037 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2041 uint8_t port_name[8];
2045 uint8_t node_name[8];
2049 uint8_t fc4_types[32];
2053 uint32_t entry_count;
2054 uint8_t port_name[8];
2055 struct ct_fdmi_hba_attributes attrs;
2059 uint8_t port_name[8];
2071 struct ct_sns_req req;
2072 struct ct_sns_rsp rsp;
2077 * SNS command structures -- for 2200 compatability.
2079 #define RFT_ID_SNS_SCMD_LEN 22
2080 #define RFT_ID_SNS_CMD_SIZE 60
2081 #define RFT_ID_SNS_DATA_SIZE 16
2083 #define RNN_ID_SNS_SCMD_LEN 10
2084 #define RNN_ID_SNS_CMD_SIZE 36
2085 #define RNN_ID_SNS_DATA_SIZE 16
2087 #define GA_NXT_SNS_SCMD_LEN 6
2088 #define GA_NXT_SNS_CMD_SIZE 28
2089 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2091 #define GID_PT_SNS_SCMD_LEN 6
2092 #define GID_PT_SNS_CMD_SIZE 28
2093 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2095 #define GPN_ID_SNS_SCMD_LEN 6
2096 #define GPN_ID_SNS_CMD_SIZE 28
2097 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2099 #define GNN_ID_SNS_SCMD_LEN 6
2100 #define GNN_ID_SNS_CMD_SIZE 28
2101 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2103 struct sns_cmd_pkt {
2106 uint16_t buffer_length;
2107 uint16_t reserved_1;
2108 uint32_t buffer_address[2];
2109 uint16_t subcommand_length;
2110 uint16_t reserved_2;
2111 uint16_t subcommand;
2113 uint32_t reserved_3;
2117 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2118 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2119 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2120 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2121 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2122 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2129 const struct firmware *fw;
2132 /* Return data from MBC_GET_ID_LIST call. */
2133 struct gid_list_info {
2137 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2138 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2139 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2141 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2144 typedef struct vport_info {
2145 uint8_t port_name[WWN_SIZE];
2146 uint8_t node_name[WWN_SIZE];
2149 unsigned long host_no;
2154 typedef struct vport_params {
2155 uint8_t port_name[WWN_SIZE];
2156 uint8_t node_name[WWN_SIZE];
2158 #define VP_OPTS_RETRY_ENABLE BIT_0
2159 #define VP_OPTS_VP_DISABLE BIT_1
2162 /* NPIV - return codes of VP create and modify */
2163 #define VP_RET_CODE_OK 0
2164 #define VP_RET_CODE_FATAL 1
2165 #define VP_RET_CODE_WRONG_ID 2
2166 #define VP_RET_CODE_WWPN 3
2167 #define VP_RET_CODE_RESOURCES 4
2168 #define VP_RET_CODE_NO_MEM 5
2169 #define VP_RET_CODE_NOT_FOUND 6
2176 struct isp_operations {
2178 int (*pci_config) (struct scsi_qla_host *);
2179 void (*reset_chip) (struct scsi_qla_host *);
2180 int (*chip_diag) (struct scsi_qla_host *);
2181 void (*config_rings) (struct scsi_qla_host *);
2182 void (*reset_adapter) (struct scsi_qla_host *);
2183 int (*nvram_config) (struct scsi_qla_host *);
2184 void (*update_fw_options) (struct scsi_qla_host *);
2185 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2187 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2188 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2190 irq_handler_t intr_handler;
2191 void (*enable_intrs) (struct qla_hw_data *);
2192 void (*disable_intrs) (struct qla_hw_data *);
2194 int (*abort_command) (srb_t *);
2195 int (*target_reset) (struct fc_port *, unsigned int, int);
2196 int (*lun_reset) (struct fc_port *, unsigned int, int);
2197 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2198 uint8_t, uint8_t, uint16_t *, uint8_t);
2199 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2202 uint16_t (*calc_req_entries) (uint16_t);
2203 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2204 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2205 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2208 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2209 uint32_t, uint32_t);
2210 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2213 void (*fw_dump) (struct scsi_qla_host *, int);
2215 int (*beacon_on) (struct scsi_qla_host *);
2216 int (*beacon_off) (struct scsi_qla_host *);
2217 void (*beacon_blink) (struct scsi_qla_host *);
2219 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2220 uint32_t, uint32_t);
2221 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2224 int (*get_flash_version) (struct scsi_qla_host *, void *);
2225 int (*start_scsi) (srb_t *);
2226 int (*abort_isp) (struct scsi_qla_host *);
2229 /* MSI-X Support *************************************************************/
2231 #define QLA_MSIX_CHIP_REV_24XX 3
2232 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2233 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2235 #define QLA_MSIX_DEFAULT 0x00
2236 #define QLA_MSIX_RSP_Q 0x01
2238 #define QLA_MIDX_DEFAULT 0
2239 #define QLA_MIDX_RSP_Q 1
2240 #define QLA_PCI_MSIX_CONTROL 0xa2
2242 struct scsi_qla_host;
2244 struct qla_msix_entry {
2248 struct rsp_que *rsp;
2251 #define WATCH_INTERVAL 1 /* number of seconds */
2254 enum qla_work_type {
2257 QLA_EVT_ASYNC_LOGIN,
2258 QLA_EVT_ASYNC_LOGIN_DONE,
2259 QLA_EVT_ASYNC_LOGOUT,
2260 QLA_EVT_ASYNC_LOGOUT_DONE,
2261 QLA_EVT_ASYNC_ADISC,
2262 QLA_EVT_ASYNC_ADISC_DONE,
2267 struct qla_work_evt {
2268 struct list_head list;
2269 enum qla_work_type type;
2271 #define QLA_EVT_FLAG_FREE 0x1
2275 enum fc_host_event_code code;
2279 #define QLA_IDC_ACK_REGS 7
2280 uint16_t mb[QLA_IDC_ACK_REGS];
2283 struct fc_port *fcport;
2284 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2289 #define QLA_UEVENT_CODE_FW_DUMP 0
2294 struct qla_chip_state_84xx {
2295 struct list_head list;
2299 spinlock_t access_lock;
2300 struct mutex fw_update_mutex;
2302 uint32_t op_fw_version;
2303 uint32_t op_fw_size;
2304 uint32_t op_fw_seq_size;
2305 uint32_t diag_fw_version;
2306 uint32_t gold_fw_version;
2309 struct qla_statistics {
2310 uint32_t total_isp_aborts;
2311 uint64_t input_bytes;
2312 uint64_t output_bytes;
2315 /* Multi queue support */
2316 #define MBC_INITIALIZE_MULTIQ 0x1f
2317 #define QLA_QUE_PAGE 0X1000
2318 #define QLA_MQ_SIZE 32
2319 #define QLA_MAX_QUEUES 256
2320 #define ISP_QUE_REG(ha, id) \
2322 ((void *)(ha->mqiobase) +\
2323 (QLA_QUE_PAGE * id)) :\
2324 ((void *)(ha->iobase)))
2325 #define QLA_REQ_QUE_ID(tag) \
2326 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2327 #define QLA_DEFAULT_QUE_QOS 5
2328 #define QLA_PRECONFIG_VPORTS 32
2329 #define QLA_MAX_VPORTS_QLA24XX 128
2330 #define QLA_MAX_VPORTS_QLA25XX 256
2331 /* Response queue data structure */
2335 response_t *ring_ptr;
2336 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2337 uint32_t __iomem *rsp_q_out;
2338 uint16_t ring_index;
2345 struct qla_hw_data *hw;
2346 struct qla_msix_entry *msix;
2347 struct req_que *req;
2348 srb_t *status_srb; /* status continuation entry */
2349 struct work_struct q_work;
2352 /* Request queue data structure */
2356 request_t *ring_ptr;
2357 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2358 uint32_t __iomem *req_q_out;
2359 uint16_t ring_index;
2368 struct rsp_que *rsp;
2369 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2370 uint32_t current_outstanding_cmd;
2374 /* Place holder for FW buffer parameters */
2382 * Qlogic host adapter specific data structure.
2384 struct qla_hw_data {
2385 struct pci_dev *pdev;
2387 #define SRB_MIN_REQ 128
2388 mempool_t *srb_mempool;
2391 uint32_t mbox_int :1;
2392 uint32_t mbox_busy :1;
2394 uint32_t disable_risc_code_load :1;
2395 uint32_t enable_64bit_addressing :1;
2396 uint32_t enable_lip_reset :1;
2397 uint32_t enable_target_reset :1;
2398 uint32_t enable_lip_full_login :1;
2399 uint32_t enable_led_scheme :1;
2400 uint32_t inta_enabled :1;
2401 uint32_t msi_enabled :1;
2402 uint32_t msix_enabled :1;
2403 uint32_t disable_serdes :1;
2404 uint32_t gpsc_supported :1;
2405 uint32_t npiv_supported :1;
2406 uint32_t pci_channel_io_perm_failure :1;
2407 uint32_t fce_enabled :1;
2408 uint32_t fac_supported :1;
2409 uint32_t chip_reset_done :1;
2411 uint32_t running_gold_fw :1;
2412 uint32_t eeh_busy :1;
2413 uint32_t cpu_affinity_enabled :1;
2414 uint32_t disable_msix_handshake :1;
2415 uint32_t fcp_prio_enabled :1;
2418 /* This spinlock is used to protect "io transactions", you must
2419 * acquire it before doing any IO to the card, eg with RD_REG*() and
2420 * WRT_REG*() for the duration of your entire commandtransaction.
2422 * This spinlock is of lower priority than the io request lock.
2425 spinlock_t hardware_lock ____cacheline_aligned;
2428 device_reg_t __iomem *iobase; /* Base I/O address */
2429 resource_size_t pio_address;
2431 #define MIN_IOBASE_LEN 0x100
2432 /* Multi queue data structs */
2433 device_reg_t __iomem *mqiobase;
2434 uint16_t msix_count;
2436 struct req_que **req_q_map;
2437 struct rsp_que **rsp_q_map;
2438 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2439 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2440 uint8_t max_req_queues;
2441 uint8_t max_rsp_queues;
2442 struct qla_npiv_entry *npiv_info;
2443 uint16_t nvram_npiv_size;
2445 uint16_t switch_cap;
2446 #define FLOGI_SEQ_DEL BIT_8
2447 #define FLOGI_MID_SUPPORT BIT_10
2448 #define FLOGI_VSAN_SUPPORT BIT_12
2449 #define FLOGI_SP_SUPPORT BIT_13
2451 uint8_t port_no; /* Physical port of adapter */
2453 /* Timeout timers. */
2454 uint8_t loop_down_abort_time; /* port down timer */
2455 atomic_t loop_down_timer; /* loop down timer */
2456 uint8_t link_down_timeout; /* link down timeout */
2457 uint16_t max_loop_id;
2460 uint16_t min_external_loopid; /* First external loop Id */
2462 #define PORT_SPEED_UNKNOWN 0xFFFF
2463 #define PORT_SPEED_1GB 0x00
2464 #define PORT_SPEED_2GB 0x01
2465 #define PORT_SPEED_4GB 0x03
2466 #define PORT_SPEED_8GB 0x04
2467 #define PORT_SPEED_10GB 0x13
2468 uint16_t link_data_rate; /* F/W operating speed */
2470 uint8_t current_topology;
2471 uint8_t prev_topology;
2472 #define ISP_CFG_NL 1
2474 #define ISP_CFG_FL 4
2477 uint8_t operating_mode; /* F/W operating mode */
2482 uint8_t interrupts_on;
2483 uint32_t isp_abort_cnt;
2485 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2486 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2487 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2488 uint32_t device_type;
2489 #define DT_ISP2100 BIT_0
2490 #define DT_ISP2200 BIT_1
2491 #define DT_ISP2300 BIT_2
2492 #define DT_ISP2312 BIT_3
2493 #define DT_ISP2322 BIT_4
2494 #define DT_ISP6312 BIT_5
2495 #define DT_ISP6322 BIT_6
2496 #define DT_ISP2422 BIT_7
2497 #define DT_ISP2432 BIT_8
2498 #define DT_ISP5422 BIT_9
2499 #define DT_ISP5432 BIT_10
2500 #define DT_ISP2532 BIT_11
2501 #define DT_ISP8432 BIT_12
2502 #define DT_ISP8001 BIT_13
2503 #define DT_ISP8021 BIT_14
2504 #define DT_ISP_LAST (DT_ISP8021 << 1)
2506 #define DT_IIDMA BIT_26
2507 #define DT_FWI2 BIT_27
2508 #define DT_ZIO_SUPPORTED BIT_28
2509 #define DT_OEM_001 BIT_29
2510 #define DT_ISP2200A BIT_30
2511 #define DT_EXTENDED_IDS BIT_31
2512 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2513 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2514 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2515 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2516 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2517 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2518 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2519 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2520 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2521 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2522 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2523 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2524 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2525 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2526 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2527 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
2529 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2530 IS_QLA6312(ha) || IS_QLA6322(ha))
2531 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2532 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2533 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2534 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2535 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2537 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2538 #define IS_QLA8XXX_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha))
2539 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2540 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
2542 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha))
2543 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2544 (ha)->flags.msix_enabled)
2545 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2546 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2547 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2549 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2550 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2551 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2552 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2553 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2555 /* HBA serial number */
2560 /* NVRAM configuration data */
2561 #define MAX_NVRAM_SIZE 4096
2562 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2563 uint16_t nvram_size;
2564 uint16_t nvram_base;
2570 uint16_t loop_reset_delay;
2571 uint8_t retry_count;
2572 uint8_t login_timeout;
2574 int port_down_retry_count;
2577 uint32_t login_retry_count;
2578 /* SNS command interfaces. */
2579 ms_iocb_entry_t *ms_iocb;
2580 dma_addr_t ms_iocb_dma;
2581 struct ct_sns_pkt *ct_sns;
2582 dma_addr_t ct_sns_dma;
2583 /* SNS command interfaces for 2200. */
2584 struct sns_cmd_pkt *sns_cmd;
2585 dma_addr_t sns_cmd_dma;
2587 #define SFP_DEV_SIZE 256
2588 #define SFP_BLOCK_SIZE 64
2590 dma_addr_t sfp_data_dma;
2593 dma_addr_t edc_data_dma;
2594 uint16_t edc_data_len;
2596 #define XGMAC_DATA_SIZE 4096
2598 dma_addr_t xgmac_data_dma;
2600 #define DCBX_TLV_DATA_SIZE 4096
2602 dma_addr_t dcbx_tlv_dma;
2604 struct task_struct *dpc_thread;
2605 uint8_t dpc_active; /* DPC routine is active */
2607 dma_addr_t gid_list_dma;
2608 struct gid_list_info *gid_list;
2609 int gid_list_info_size;
2611 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2612 #define DMA_POOL_SIZE 256
2613 struct dma_pool *s_dma_pool;
2615 dma_addr_t init_cb_dma;
2618 dma_addr_t ex_init_cb_dma;
2619 struct ex_init_cb_81xx *ex_init_cb;
2622 dma_addr_t async_pd_dma;
2624 /* These are used by mailbox operations. */
2625 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2628 unsigned long mbx_cmd_flags;
2629 #define MBX_INTERRUPT 1
2630 #define MBX_INTR_WAIT 2
2631 #define MBX_UPDATE_FLASH_ACTIVE 3
2633 struct mutex vport_lock; /* Virtual port synchronization */
2634 struct completion mbx_cmd_comp; /* Serialize mbx access */
2635 struct completion mbx_intr_comp; /* Used for completion notification */
2636 struct completion dcbx_comp; /* For set port config notification */
2637 int notify_dcbx_comp;
2639 /* Basic firmware related information. */
2640 uint16_t fw_major_version;
2641 uint16_t fw_minor_version;
2642 uint16_t fw_subminor_version;
2643 uint16_t fw_attributes;
2644 uint32_t fw_memory_size;
2645 uint32_t fw_transfer_size;
2646 uint32_t fw_srisc_address;
2647 #define RISC_START_ADDRESS_2100 0x1000
2648 #define RISC_START_ADDRESS_2300 0x800
2649 #define RISC_START_ADDRESS_2400 0x100000
2650 uint16_t fw_xcb_count;
2652 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2653 uint8_t fw_seriallink_options[4];
2654 uint16_t fw_seriallink_options24[4];
2656 uint8_t mpi_version[3];
2657 uint32_t mpi_capabilities;
2658 uint8_t phy_version[3];
2660 /* Firmware dump information. */
2661 struct qla2xxx_fw_dump *fw_dump;
2662 uint32_t fw_dump_len;
2664 int fw_dump_reading;
2668 uint32_t chain_offset;
2669 struct dentry *dfs_dir;
2670 struct dentry *dfs_fce;
2675 uint64_t fce_wr, fce_rd;
2676 struct mutex fce_mutex;
2679 uint16_t chip_revision;
2681 uint16_t product_id[4];
2683 uint8_t model_number[16+1];
2684 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2685 char model_desc[80];
2686 uint8_t adapter_id[16+1];
2688 /* Option ROM information. */
2689 char *optrom_buffer;
2690 uint32_t optrom_size;
2692 #define QLA_SWAITING 0
2693 #define QLA_SREADING 1
2694 #define QLA_SWRITING 2
2695 uint32_t optrom_region_start;
2696 uint32_t optrom_region_size;
2698 /* PCI expansion ROM image information. */
2699 #define ROM_CODE_TYPE_BIOS 0
2700 #define ROM_CODE_TYPE_FCODE 1
2701 #define ROM_CODE_TYPE_EFI 3
2702 uint8_t bios_revision[2];
2703 uint8_t efi_revision[2];
2704 uint8_t fcode_revision[16];
2705 uint32_t fw_revision[4];
2707 /* Offsets for flash/nvram access (set to ~0 if not used). */
2708 uint32_t flash_conf_off;
2709 uint32_t flash_data_off;
2710 uint32_t nvram_conf_off;
2711 uint32_t nvram_data_off;
2713 uint32_t fdt_wrt_disable;
2714 uint32_t fdt_erase_cmd;
2715 uint32_t fdt_block_size;
2716 uint32_t fdt_unprotect_sec_cmd;
2717 uint32_t fdt_protect_sec_cmd;
2719 uint32_t flt_region_flt;
2720 uint32_t flt_region_fdt;
2721 uint32_t flt_region_boot;
2722 uint32_t flt_region_fw;
2723 uint32_t flt_region_vpd_nvram;
2724 uint32_t flt_region_vpd;
2725 uint32_t flt_region_nvram;
2726 uint32_t flt_region_npiv_conf;
2727 uint32_t flt_region_gold_fw;
2728 uint32_t flt_region_fcp_prio;
2729 uint32_t flt_region_bootload;
2731 /* Needed for BEACON */
2732 uint16_t beacon_blink_led;
2733 uint8_t beacon_color_state;
2734 #define QLA_LED_GRN_ON 0x01
2735 #define QLA_LED_YLW_ON 0x02
2736 #define QLA_LED_ABR_ON 0x04
2737 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2738 /* ISP2322: red, green, amber. */
2741 struct fc_host_statistics fc_host_stat;
2743 struct qla_msix_entry *msix_entries;
2745 struct list_head vp_list; /* list of VP */
2746 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2747 sizeof(unsigned long)];
2748 uint16_t num_vhosts; /* number of vports created */
2749 uint16_t num_vsans; /* number of vsan created */
2750 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2751 int cur_vport_count;
2753 struct qla_chip_state_84xx *cs84xx;
2754 struct qla_statistics qla_stats;
2755 struct isp_operations *isp_ops;
2756 struct workqueue_struct *wq;
2757 struct qlfc_fw fw_buf;
2759 /* FCP_CMND priority support */
2760 struct qla_fcp_prio_cfg *fcp_prio_cfg;
2762 struct dma_pool *dl_dma_pool;
2763 #define DSD_LIST_DMA_POOL_SIZE 512
2765 struct dma_pool *fcp_cmnd_dma_pool;
2766 mempool_t *ctx_mempool;
2767 #define FCP_CMND_DMA_POOL_SIZE 512
2769 unsigned long nx_pcibase; /* Base I/O address */
2770 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */
2771 unsigned long nxdb_wr_ptr; /* Door bell write pointer */
2774 uint32_t curr_window;
2775 uint32_t ddr_mn_window;
2776 unsigned long mn_win_crb;
2777 unsigned long ms_win_crb;
2779 uint32_t nx_dev_init_timeout;
2780 uint32_t nx_reset_timeout;
2782 uint16_t portnum; /* port number */
2784 struct fw_blob *hablob;
2785 struct qla82xx_legacy_intr_set nx_legacy_intr;
2787 uint16_t gbl_dsd_inuse;
2788 uint16_t gbl_dsd_avail;
2789 struct list_head gbl_dsd_list;
2790 #define NUM_DSD_CHAIN 4096
2793 __le32 file_prd_off; /* File firmware product offset */
2797 * Qlogic scsi host structure
2799 typedef struct scsi_qla_host {
2800 struct list_head list;
2801 struct list_head vp_fcports; /* list of fcports */
2802 struct list_head work_list;
2803 spinlock_t work_lock;
2805 /* Commonly used flags and state information. */
2806 struct Scsi_Host *host;
2807 unsigned long host_no;
2808 uint8_t host_str[16];
2811 uint32_t init_done :1;
2813 uint32_t rscn_queue_overflow :1;
2814 uint32_t reset_active :1;
2816 uint32_t management_server_logged_in :1;
2817 uint32_t process_response_queue :1;
2818 uint32_t difdix_supported:1;
2821 atomic_t loop_state;
2822 #define LOOP_TIMEOUT 1
2825 #define LOOP_UPDATE 4
2826 #define LOOP_READY 5
2829 unsigned long dpc_flags;
2830 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2831 #define RESET_ACTIVE 1
2832 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2833 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2834 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2835 #define LOOP_RESYNC_ACTIVE 5
2836 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2837 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2838 #define RELOGIN_NEEDED 8
2839 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2840 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2841 #define BEACON_BLINK_NEEDED 11
2842 #define REGISTER_FDMI_NEEDED 12
2843 #define FCPORT_UPDATE_NEEDED 13
2844 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2845 #define UNLOADING 15
2846 #define NPIV_CONFIG_NEEDED 16
2847 #define ISP_UNRECOVERABLE 17
2848 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
2850 uint32_t device_flags;
2851 #define SWITCH_FOUND BIT_0
2852 #define DFLG_NO_CABLE BIT_1
2853 #define DFLG_DEV_FAILED BIT_5
2855 /* ISP configuration data. */
2856 uint16_t loop_id; /* Host adapter loop id */
2858 port_id_t d_id; /* Host adapter port id */
2859 uint8_t marker_needed;
2860 uint16_t mgmt_svr_loop_id;
2865 uint32_t rscn_queue[MAX_RSCN_COUNT];
2866 uint8_t rscn_in_ptr;
2867 uint8_t rscn_out_ptr;
2869 /* Timeout timers. */
2870 uint8_t loop_down_abort_time; /* port down timer */
2871 atomic_t loop_down_timer; /* loop down timer */
2872 uint8_t link_down_timeout; /* link down timeout */
2874 uint32_t timer_active;
2875 struct timer_list timer;
2877 uint8_t node_name[WWN_SIZE];
2878 uint8_t port_name[WWN_SIZE];
2879 uint8_t fabric_node_name[WWN_SIZE];
2881 uint16_t fcoe_vlan_id;
2882 uint16_t fcoe_fcf_idx;
2883 uint8_t fcoe_vn_port_mac[6];
2885 uint32_t vp_abort_cnt;
2887 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2888 uint16_t vp_idx; /* vport ID */
2890 unsigned long vp_flags;
2891 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2892 #define VP_CREATE_NEEDED 1
2893 #define VP_BIND_NEEDED 2
2894 #define VP_DELETE_NEEDED 3
2895 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2897 #define VP_OFFLINE 0
2900 // #define VP_DISABLE 3
2901 uint16_t vp_err_state;
2902 uint16_t vp_prev_err_state;
2903 #define VP_ERR_UNKWN 0
2904 #define VP_ERR_PORTDWN 1
2905 #define VP_ERR_FAB_UNSUPPORTED 2
2906 #define VP_ERR_FAB_NORESOURCES 3
2907 #define VP_ERR_FAB_LOGOUT 4
2908 #define VP_ERR_ADAP_NORESOURCES 5
2909 struct qla_hw_data *hw;
2910 struct req_que *req;
2911 int fw_heartbeat_counter;
2912 int seconds_since_last_heartbeat;
2916 * Macros to help code, maintain, etc.
2918 #define LOOP_TRANSITION(ha) \
2919 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2920 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2921 atomic_read(&ha->loop_state) == LOOP_DOWN)
2923 #define qla_printk(level, ha, format, arg...) \
2924 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2927 * qla2x00 local function return status codes
2929 #define MBS_MASK 0x3fff
2931 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2932 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2933 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2934 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2935 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2936 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2937 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2938 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2939 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2940 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2942 #define QLA_FUNCTION_TIMEOUT 0x100
2943 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2944 #define QLA_FUNCTION_FAILED 0x102
2945 #define QLA_MEMORY_ALLOC_FAILED 0x103
2946 #define QLA_LOCK_TIMEOUT 0x104
2947 #define QLA_ABORTED 0x105
2948 #define QLA_SUSPENDED 0x106
2949 #define QLA_BUSY 0x107
2950 #define QLA_RSCNS_HANDLED 0x108
2951 #define QLA_ALREADY_REGISTERED 0x109
2953 #define NVRAM_DELAY() udelay(10)
2955 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2958 * Flash support definitions
2960 #define OPTROM_SIZE_2300 0x20000
2961 #define OPTROM_SIZE_2322 0x100000
2962 #define OPTROM_SIZE_24XX 0x100000
2963 #define OPTROM_SIZE_25XX 0x200000
2964 #define OPTROM_SIZE_81XX 0x400000
2965 #define OPTROM_SIZE_82XX 0x800000
2967 #define OPTROM_BURST_SIZE 0x1000
2968 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
2970 #define QLA_DSDS_PER_IOCB 37
2972 #include "qla_gbl.h"
2973 #include "qla_dbg.h"
2974 #include "qla_inline.h"
2976 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)