2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmaengine.h>
41 #include <linux/atmel_pdc.h>
42 #include <linux/atmel_serial.h>
43 #include <linux/uaccess.h>
44 #include <linux/platform_data/atmel.h>
45 #include <linux/timer.h>
46 #include <linux/gpio.h>
47 #include <linux/gpio/consumer.h>
48 #include <linux/err.h>
49 #include <linux/irq.h>
50 #include <linux/suspend.h>
53 #include <asm/ioctls.h>
55 #define PDC_BUFFER_SIZE 512
56 /* Revisit: We should calculate this based on the actual port settings */
57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
59 /* The minium number of data FIFOs should be able to contain */
60 #define ATMEL_MIN_FIFO_SIZE 8
62 * These two offsets are substracted from the RX FIFO size to define the RTS
63 * high and low thresholds
65 #define ATMEL_RTS_HIGH_OFFSET 16
66 #define ATMEL_RTS_LOW_OFFSET 20
68 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
72 #include <linux/serial_core.h>
74 #include "serial_mctrl_gpio.h"
76 static void atmel_start_rx(struct uart_port *port);
77 static void atmel_stop_rx(struct uart_port *port);
79 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
81 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
82 * should coexist with the 8250 driver, such as if we have an external 16C550
84 #define SERIAL_ATMEL_MAJOR 204
85 #define MINOR_START 154
86 #define ATMEL_DEVICENAME "ttyAT"
90 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
91 * name, but it is legally reserved for the 8250 driver. */
92 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
93 #define MINOR_START 64
94 #define ATMEL_DEVICENAME "ttyS"
98 #define ATMEL_ISR_PASS_LIMIT 256
100 struct atmel_dma_buffer {
103 unsigned int dma_size;
107 struct atmel_uart_char {
112 #define ATMEL_SERIAL_RINGSIZE 1024
115 * at91: 6 USARTs and one DBGU port (SAM9260)
118 #define ATMEL_MAX_UART 7
121 * We wrap our port structure around the generic uart_port.
123 struct atmel_uart_port {
124 struct uart_port uart; /* uart */
125 struct clk *clk; /* uart clock */
126 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
127 u32 backup_imr; /* IMR saved during suspend */
128 int break_active; /* break being received */
130 bool use_dma_rx; /* enable DMA receiver */
131 bool use_pdc_rx; /* enable PDC receiver */
132 short pdc_rx_idx; /* current PDC RX buffer */
133 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
135 bool use_dma_tx; /* enable DMA transmitter */
136 bool use_pdc_tx; /* enable PDC transmitter */
137 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
139 spinlock_t lock_tx; /* port lock */
140 spinlock_t lock_rx; /* port lock */
141 struct dma_chan *chan_tx;
142 struct dma_chan *chan_rx;
143 struct dma_async_tx_descriptor *desc_tx;
144 struct dma_async_tx_descriptor *desc_rx;
145 dma_cookie_t cookie_tx;
146 dma_cookie_t cookie_rx;
147 struct scatterlist sg_tx;
148 struct scatterlist sg_rx;
149 struct tasklet_struct tasklet;
150 unsigned int irq_status;
151 unsigned int irq_status_prev;
152 unsigned int status_change;
155 struct circ_buf rx_ring;
157 struct mctrl_gpios *gpios;
158 int gpio_irq[UART_GPIO_MAX];
159 unsigned int tx_done_mask;
164 bool is_usart; /* usart or uart */
165 struct timer_list uart_timer; /* uart timer */
168 unsigned int pending;
169 unsigned int pending_status;
170 spinlock_t lock_suspended;
172 int (*prepare_rx)(struct uart_port *port);
173 int (*prepare_tx)(struct uart_port *port);
174 void (*schedule_rx)(struct uart_port *port);
175 void (*schedule_tx)(struct uart_port *port);
176 void (*release_rx)(struct uart_port *port);
177 void (*release_tx)(struct uart_port *port);
180 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
181 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
184 static struct console atmel_console;
187 #if defined(CONFIG_OF)
188 static const struct of_device_id atmel_serial_dt_ids[] = {
189 { .compatible = "atmel,at91rm9200-usart" },
190 { .compatible = "atmel,at91sam9260-usart" },
194 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
197 static inline struct atmel_uart_port *
198 to_atmel_uart_port(struct uart_port *uart)
200 return container_of(uart, struct atmel_uart_port, uart);
203 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
205 return __raw_readl(port->membase + reg);
208 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
210 __raw_writel(value, port->membase + reg);
215 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
216 static inline u8 atmel_uart_read_char(struct uart_port *port)
218 return __raw_readl(port->membase + ATMEL_US_RHR);
221 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
223 __raw_writel(value, port->membase + ATMEL_US_THR);
228 static inline u8 atmel_uart_read_char(struct uart_port *port)
230 return __raw_readb(port->membase + ATMEL_US_RHR);
233 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
235 __raw_writeb(value, port->membase + ATMEL_US_THR);
240 #ifdef CONFIG_SERIAL_ATMEL_PDC
241 static bool atmel_use_pdc_rx(struct uart_port *port)
243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
245 return atmel_port->use_pdc_rx;
248 static bool atmel_use_pdc_tx(struct uart_port *port)
250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
252 return atmel_port->use_pdc_tx;
255 static bool atmel_use_pdc_rx(struct uart_port *port)
260 static bool atmel_use_pdc_tx(struct uart_port *port)
266 static bool atmel_use_dma_tx(struct uart_port *port)
268 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
270 return atmel_port->use_dma_tx;
273 static bool atmel_use_dma_rx(struct uart_port *port)
275 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
277 return atmel_port->use_dma_rx;
280 static bool atmel_use_fifo(struct uart_port *port)
282 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
284 return atmel_port->fifo_size;
287 static unsigned int atmel_get_lines_status(struct uart_port *port)
289 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
290 unsigned int status, ret = 0;
292 status = atmel_uart_readl(port, ATMEL_US_CSR);
294 mctrl_gpio_get(atmel_port->gpios, &ret);
296 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
299 status &= ~ATMEL_US_CTS;
301 status |= ATMEL_US_CTS;
304 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
307 status &= ~ATMEL_US_DSR;
309 status |= ATMEL_US_DSR;
312 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
315 status &= ~ATMEL_US_RI;
317 status |= ATMEL_US_RI;
320 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
323 status &= ~ATMEL_US_DCD;
325 status |= ATMEL_US_DCD;
331 /* Enable or disable the rs485 support */
332 static int atmel_config_rs485(struct uart_port *port,
333 struct serial_rs485 *rs485conf)
335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
338 /* Disable interrupts */
339 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
341 mode = atmel_uart_readl(port, ATMEL_US_MR);
343 /* Resetting serial mode to RS232 (0x0) */
344 mode &= ~ATMEL_US_USMODE;
346 port->rs485 = *rs485conf;
348 if (rs485conf->flags & SER_RS485_ENABLED) {
349 dev_dbg(port->dev, "Setting UART to RS485\n");
350 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
351 atmel_uart_writel(port, ATMEL_US_TTGR,
352 rs485conf->delay_rts_after_send);
353 mode |= ATMEL_US_USMODE_RS485;
355 dev_dbg(port->dev, "Setting UART to RS232\n");
356 if (atmel_use_pdc_tx(port))
357 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
360 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
362 atmel_uart_writel(port, ATMEL_US_MR, mode);
364 /* Enable interrupts */
365 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
371 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
373 static u_int atmel_tx_empty(struct uart_port *port)
375 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
381 * Set state of the modem control output lines
383 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
385 unsigned int control = 0;
386 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
387 unsigned int rts_paused, rts_ready;
388 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
390 /* override mode to RS485 if needed, otherwise keep the current mode */
391 if (port->rs485.flags & SER_RS485_ENABLED) {
392 atmel_uart_writel(port, ATMEL_US_TTGR,
393 port->rs485.delay_rts_after_send);
394 mode &= ~ATMEL_US_USMODE;
395 mode |= ATMEL_US_USMODE_RS485;
398 /* set the RTS line state according to the mode */
399 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
400 /* force RTS line to high level */
401 rts_paused = ATMEL_US_RTSEN;
403 /* give the control of the RTS line back to the hardware */
404 rts_ready = ATMEL_US_RTSDIS;
406 /* force RTS line to high level */
407 rts_paused = ATMEL_US_RTSDIS;
409 /* force RTS line to low level */
410 rts_ready = ATMEL_US_RTSEN;
413 if (mctrl & TIOCM_RTS)
414 control |= rts_ready;
416 control |= rts_paused;
418 if (mctrl & TIOCM_DTR)
419 control |= ATMEL_US_DTREN;
421 control |= ATMEL_US_DTRDIS;
423 atmel_uart_writel(port, ATMEL_US_CR, control);
425 mctrl_gpio_set(atmel_port->gpios, mctrl);
427 /* Local loopback mode? */
428 mode &= ~ATMEL_US_CHMODE;
429 if (mctrl & TIOCM_LOOP)
430 mode |= ATMEL_US_CHMODE_LOC_LOOP;
432 mode |= ATMEL_US_CHMODE_NORMAL;
434 atmel_uart_writel(port, ATMEL_US_MR, mode);
438 * Get state of the modem control input lines
440 static u_int atmel_get_mctrl(struct uart_port *port)
442 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
443 unsigned int ret = 0, status;
445 status = atmel_uart_readl(port, ATMEL_US_CSR);
448 * The control signals are active low.
450 if (!(status & ATMEL_US_DCD))
452 if (!(status & ATMEL_US_CTS))
454 if (!(status & ATMEL_US_DSR))
456 if (!(status & ATMEL_US_RI))
459 return mctrl_gpio_get(atmel_port->gpios, &ret);
465 static void atmel_stop_tx(struct uart_port *port)
467 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
469 if (atmel_use_pdc_tx(port)) {
470 /* disable PDC transmit */
471 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
473 /* Disable interrupts */
474 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
476 if ((port->rs485.flags & SER_RS485_ENABLED) &&
477 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
478 atmel_start_rx(port);
482 * Start transmitting.
484 static void atmel_start_tx(struct uart_port *port)
486 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
488 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
490 /* The transmitter is already running. Yes, we
494 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
495 if ((port->rs485.flags & SER_RS485_ENABLED) &&
496 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
499 if (atmel_use_pdc_tx(port))
500 /* re-enable PDC transmit */
501 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
503 /* Enable interrupts */
504 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
508 * start receiving - port is in process of being opened.
510 static void atmel_start_rx(struct uart_port *port)
512 /* reset status and receiver */
513 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
515 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
517 if (atmel_use_pdc_rx(port)) {
518 /* enable PDC controller */
519 atmel_uart_writel(port, ATMEL_US_IER,
520 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
521 port->read_status_mask);
522 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
524 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
529 * Stop receiving - port is in process of being closed.
531 static void atmel_stop_rx(struct uart_port *port)
533 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
535 if (atmel_use_pdc_rx(port)) {
536 /* disable PDC receive */
537 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
538 atmel_uart_writel(port, ATMEL_US_IDR,
539 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
540 port->read_status_mask);
542 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
547 * Enable modem status interrupts
549 static void atmel_enable_ms(struct uart_port *port)
551 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
555 * Interrupt should not be enabled twice
557 if (atmel_port->ms_irq_enabled)
560 atmel_port->ms_irq_enabled = true;
562 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
563 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
565 ier |= ATMEL_US_CTSIC;
567 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
568 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
570 ier |= ATMEL_US_DSRIC;
572 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
573 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
575 ier |= ATMEL_US_RIIC;
577 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
578 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
580 ier |= ATMEL_US_DCDIC;
582 atmel_uart_writel(port, ATMEL_US_IER, ier);
586 * Disable modem status interrupts
588 static void atmel_disable_ms(struct uart_port *port)
590 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
594 * Interrupt should not be disabled twice
596 if (!atmel_port->ms_irq_enabled)
599 atmel_port->ms_irq_enabled = false;
601 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
602 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
604 idr |= ATMEL_US_CTSIC;
606 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
607 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
609 idr |= ATMEL_US_DSRIC;
611 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
612 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
614 idr |= ATMEL_US_RIIC;
616 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
617 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
619 idr |= ATMEL_US_DCDIC;
621 atmel_uart_writel(port, ATMEL_US_IDR, idr);
625 * Control the transmission of a break signal
627 static void atmel_break_ctl(struct uart_port *port, int break_state)
629 if (break_state != 0)
631 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
634 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
638 * Stores the incoming character in the ring buffer
641 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
644 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
645 struct circ_buf *ring = &atmel_port->rx_ring;
646 struct atmel_uart_char *c;
648 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
649 /* Buffer overflow, ignore char */
652 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
656 /* Make sure the character is stored before we update head. */
659 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
663 * Deal with parity, framing and overrun errors.
665 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
668 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
670 if (status & ATMEL_US_RXBRK) {
671 /* ignore side-effect */
672 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
675 if (status & ATMEL_US_PARE)
676 port->icount.parity++;
677 if (status & ATMEL_US_FRAME)
678 port->icount.frame++;
679 if (status & ATMEL_US_OVRE)
680 port->icount.overrun++;
684 * Characters received (called from interrupt handler)
686 static void atmel_rx_chars(struct uart_port *port)
688 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
689 unsigned int status, ch;
691 status = atmel_uart_readl(port, ATMEL_US_CSR);
692 while (status & ATMEL_US_RXRDY) {
693 ch = atmel_uart_read_char(port);
696 * note that the error handling code is
697 * out of the main execution path
699 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
700 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
701 || atmel_port->break_active)) {
704 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
706 if (status & ATMEL_US_RXBRK
707 && !atmel_port->break_active) {
708 atmel_port->break_active = 1;
709 atmel_uart_writel(port, ATMEL_US_IER,
713 * This is either the end-of-break
714 * condition or we've received at
715 * least one character without RXBRK
716 * being set. In both cases, the next
717 * RXBRK will indicate start-of-break.
719 atmel_uart_writel(port, ATMEL_US_IDR,
721 status &= ~ATMEL_US_RXBRK;
722 atmel_port->break_active = 0;
726 atmel_buffer_rx_char(port, status, ch);
727 status = atmel_uart_readl(port, ATMEL_US_CSR);
730 tasklet_schedule(&atmel_port->tasklet);
734 * Transmit characters (called from tasklet with TXRDY interrupt
737 static void atmel_tx_chars(struct uart_port *port)
739 struct circ_buf *xmit = &port->state->xmit;
740 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
743 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
744 atmel_uart_write_char(port, port->x_char);
748 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
751 while (atmel_uart_readl(port, ATMEL_US_CSR) &
752 atmel_port->tx_done_mask) {
753 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
754 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
756 if (uart_circ_empty(xmit))
760 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
761 uart_write_wakeup(port);
763 if (!uart_circ_empty(xmit))
764 /* Enable interrupts */
765 atmel_uart_writel(port, ATMEL_US_IER,
766 atmel_port->tx_done_mask);
769 static void atmel_complete_tx_dma(void *arg)
771 struct atmel_uart_port *atmel_port = arg;
772 struct uart_port *port = &atmel_port->uart;
773 struct circ_buf *xmit = &port->state->xmit;
774 struct dma_chan *chan = atmel_port->chan_tx;
777 spin_lock_irqsave(&port->lock, flags);
780 dmaengine_terminate_all(chan);
781 xmit->tail += atmel_port->tx_len;
782 xmit->tail &= UART_XMIT_SIZE - 1;
784 port->icount.tx += atmel_port->tx_len;
786 spin_lock_irq(&atmel_port->lock_tx);
787 async_tx_ack(atmel_port->desc_tx);
788 atmel_port->cookie_tx = -EINVAL;
789 atmel_port->desc_tx = NULL;
790 spin_unlock_irq(&atmel_port->lock_tx);
792 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
793 uart_write_wakeup(port);
796 * xmit is a circular buffer so, if we have just send data from
797 * xmit->tail to the end of xmit->buf, now we have to transmit the
798 * remaining data from the beginning of xmit->buf to xmit->head.
800 if (!uart_circ_empty(xmit))
801 tasklet_schedule(&atmel_port->tasklet);
803 spin_unlock_irqrestore(&port->lock, flags);
806 static void atmel_release_tx_dma(struct uart_port *port)
808 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
809 struct dma_chan *chan = atmel_port->chan_tx;
812 dmaengine_terminate_all(chan);
813 dma_release_channel(chan);
814 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
818 atmel_port->desc_tx = NULL;
819 atmel_port->chan_tx = NULL;
820 atmel_port->cookie_tx = -EINVAL;
824 * Called from tasklet with TXRDY interrupt is disabled.
826 static void atmel_tx_dma(struct uart_port *port)
828 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
829 struct circ_buf *xmit = &port->state->xmit;
830 struct dma_chan *chan = atmel_port->chan_tx;
831 struct dma_async_tx_descriptor *desc;
832 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
833 unsigned int tx_len, part1_len, part2_len, sg_len;
834 dma_addr_t phys_addr;
836 /* Make sure we have an idle channel */
837 if (atmel_port->desc_tx != NULL)
840 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
843 * Port xmit buffer is already mapped,
844 * and it is one page... Just adjust
845 * offsets and lengths. Since it is a circular buffer,
846 * we have to transmit till the end, and then the rest.
847 * Take the port lock to get a
848 * consistent xmit buffer state.
850 tx_len = CIRC_CNT_TO_END(xmit->head,
854 if (atmel_port->fifo_size) {
855 /* multi data mode */
856 part1_len = (tx_len & ~0x3); /* DWORD access */
857 part2_len = (tx_len & 0x3); /* BYTE access */
859 /* single data (legacy) mode */
861 part2_len = tx_len; /* BYTE access only */
864 sg_init_table(sgl, 2);
866 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
869 sg_dma_address(sg) = phys_addr;
870 sg_dma_len(sg) = part1_len;
872 phys_addr += part1_len;
877 sg_dma_address(sg) = phys_addr;
878 sg_dma_len(sg) = part2_len;
882 * save tx_len so atmel_complete_tx_dma() will increase
883 * xmit->tail correctly
885 atmel_port->tx_len = tx_len;
887 desc = dmaengine_prep_slave_sg(chan,
894 dev_err(port->dev, "Failed to send via dma!\n");
898 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
900 atmel_port->desc_tx = desc;
901 desc->callback = atmel_complete_tx_dma;
902 desc->callback_param = atmel_port;
903 atmel_port->cookie_tx = dmaengine_submit(desc);
906 if (port->rs485.flags & SER_RS485_ENABLED) {
907 /* DMA done, stop TX, start RX for RS485 */
908 atmel_start_rx(port);
912 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
913 uart_write_wakeup(port);
916 static int atmel_prepare_tx_dma(struct uart_port *port)
918 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
920 struct dma_slave_config config;
924 dma_cap_set(DMA_SLAVE, mask);
926 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
927 if (atmel_port->chan_tx == NULL)
929 dev_info(port->dev, "using %s for tx DMA transfers\n",
930 dma_chan_name(atmel_port->chan_tx));
932 spin_lock_init(&atmel_port->lock_tx);
933 sg_init_table(&atmel_port->sg_tx, 1);
934 /* UART circular tx buffer is an aligned page. */
935 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
936 sg_set_page(&atmel_port->sg_tx,
937 virt_to_page(port->state->xmit.buf),
939 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
940 nent = dma_map_sg(port->dev,
946 dev_dbg(port->dev, "need to release resource of dma\n");
949 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
950 sg_dma_len(&atmel_port->sg_tx),
951 port->state->xmit.buf,
952 &sg_dma_address(&atmel_port->sg_tx));
955 /* Configure the slave DMA */
956 memset(&config, 0, sizeof(config));
957 config.direction = DMA_MEM_TO_DEV;
958 config.dst_addr_width = (atmel_port->fifo_size) ?
959 DMA_SLAVE_BUSWIDTH_4_BYTES :
960 DMA_SLAVE_BUSWIDTH_1_BYTE;
961 config.dst_addr = port->mapbase + ATMEL_US_THR;
962 config.dst_maxburst = 1;
964 ret = dmaengine_slave_config(atmel_port->chan_tx,
967 dev_err(port->dev, "DMA tx slave configuration failed\n");
974 dev_err(port->dev, "TX channel not available, switch to pio\n");
975 atmel_port->use_dma_tx = 0;
976 if (atmel_port->chan_tx)
977 atmel_release_tx_dma(port);
981 static void atmel_complete_rx_dma(void *arg)
983 struct uart_port *port = arg;
984 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
986 tasklet_schedule(&atmel_port->tasklet);
989 static void atmel_release_rx_dma(struct uart_port *port)
991 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
992 struct dma_chan *chan = atmel_port->chan_rx;
995 dmaengine_terminate_all(chan);
996 dma_release_channel(chan);
997 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1001 atmel_port->desc_rx = NULL;
1002 atmel_port->chan_rx = NULL;
1003 atmel_port->cookie_rx = -EINVAL;
1006 static void atmel_rx_from_dma(struct uart_port *port)
1008 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1009 struct tty_port *tport = &port->state->port;
1010 struct circ_buf *ring = &atmel_port->rx_ring;
1011 struct dma_chan *chan = atmel_port->chan_rx;
1012 struct dma_tx_state state;
1013 enum dma_status dmastat;
1017 /* Reset the UART timeout early so that we don't miss one */
1018 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1019 dmastat = dmaengine_tx_status(chan,
1020 atmel_port->cookie_rx,
1022 /* Restart a new tasklet if DMA status is error */
1023 if (dmastat == DMA_ERROR) {
1024 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1025 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1026 tasklet_schedule(&atmel_port->tasklet);
1030 /* CPU claims ownership of RX DMA buffer */
1031 dma_sync_sg_for_cpu(port->dev,
1037 * ring->head points to the end of data already written by the DMA.
1038 * ring->tail points to the beginning of data to be read by the
1040 * The current transfer size should not be larger than the dma buffer
1043 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1044 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1046 * At this point ring->head may point to the first byte right after the
1047 * last byte of the dma buffer:
1048 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1050 * However ring->tail must always points inside the dma buffer:
1051 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1053 * Since we use a ring buffer, we have to handle the case
1054 * where head is lower than tail. In such a case, we first read from
1055 * tail to the end of the buffer then reset tail.
1057 if (ring->head < ring->tail) {
1058 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1060 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1062 port->icount.rx += count;
1065 /* Finally we read data from tail to head */
1066 if (ring->tail < ring->head) {
1067 count = ring->head - ring->tail;
1069 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1070 /* Wrap ring->head if needed */
1071 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1073 ring->tail = ring->head;
1074 port->icount.rx += count;
1077 /* USART retreives ownership of RX DMA buffer */
1078 dma_sync_sg_for_device(port->dev,
1084 * Drop the lock here since it might end up calling
1085 * uart_start(), which takes the lock.
1087 spin_unlock(&port->lock);
1088 tty_flip_buffer_push(tport);
1089 spin_lock(&port->lock);
1091 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1094 static int atmel_prepare_rx_dma(struct uart_port *port)
1096 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1097 struct dma_async_tx_descriptor *desc;
1098 dma_cap_mask_t mask;
1099 struct dma_slave_config config;
1100 struct circ_buf *ring;
1103 ring = &atmel_port->rx_ring;
1106 dma_cap_set(DMA_CYCLIC, mask);
1108 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1109 if (atmel_port->chan_rx == NULL)
1111 dev_info(port->dev, "using %s for rx DMA transfers\n",
1112 dma_chan_name(atmel_port->chan_rx));
1114 spin_lock_init(&atmel_port->lock_rx);
1115 sg_init_table(&atmel_port->sg_rx, 1);
1116 /* UART circular rx buffer is an aligned page. */
1117 BUG_ON(!PAGE_ALIGNED(ring->buf));
1118 sg_set_page(&atmel_port->sg_rx,
1119 virt_to_page(ring->buf),
1120 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1121 (unsigned long)ring->buf & ~PAGE_MASK);
1122 nent = dma_map_sg(port->dev,
1128 dev_dbg(port->dev, "need to release resource of dma\n");
1131 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1132 sg_dma_len(&atmel_port->sg_rx),
1134 &sg_dma_address(&atmel_port->sg_rx));
1137 /* Configure the slave DMA */
1138 memset(&config, 0, sizeof(config));
1139 config.direction = DMA_DEV_TO_MEM;
1140 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1141 config.src_addr = port->mapbase + ATMEL_US_RHR;
1142 config.src_maxburst = 1;
1144 ret = dmaengine_slave_config(atmel_port->chan_rx,
1147 dev_err(port->dev, "DMA rx slave configuration failed\n");
1151 * Prepare a cyclic dma transfer, assign 2 descriptors,
1152 * each one is half ring buffer size
1154 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1155 sg_dma_address(&atmel_port->sg_rx),
1156 sg_dma_len(&atmel_port->sg_rx),
1157 sg_dma_len(&atmel_port->sg_rx)/2,
1159 DMA_PREP_INTERRUPT);
1160 desc->callback = atmel_complete_rx_dma;
1161 desc->callback_param = port;
1162 atmel_port->desc_rx = desc;
1163 atmel_port->cookie_rx = dmaengine_submit(desc);
1168 dev_err(port->dev, "RX channel not available, switch to pio\n");
1169 atmel_port->use_dma_rx = 0;
1170 if (atmel_port->chan_rx)
1171 atmel_release_rx_dma(port);
1175 static void atmel_uart_timer_callback(unsigned long data)
1177 struct uart_port *port = (void *)data;
1178 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1180 tasklet_schedule(&atmel_port->tasklet);
1181 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1185 * receive interrupt handler.
1188 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1190 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1192 if (atmel_use_pdc_rx(port)) {
1194 * PDC receive. Just schedule the tasklet and let it
1195 * figure out the details.
1197 * TODO: We're not handling error flags correctly at
1200 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1201 atmel_uart_writel(port, ATMEL_US_IDR,
1202 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1203 tasklet_schedule(&atmel_port->tasklet);
1206 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1207 ATMEL_US_FRAME | ATMEL_US_PARE))
1208 atmel_pdc_rxerr(port, pending);
1211 if (atmel_use_dma_rx(port)) {
1212 if (pending & ATMEL_US_TIMEOUT) {
1213 atmel_uart_writel(port, ATMEL_US_IDR,
1215 tasklet_schedule(&atmel_port->tasklet);
1219 /* Interrupt receive */
1220 if (pending & ATMEL_US_RXRDY)
1221 atmel_rx_chars(port);
1222 else if (pending & ATMEL_US_RXBRK) {
1224 * End of break detected. If it came along with a
1225 * character, atmel_rx_chars will handle it.
1227 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1228 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1229 atmel_port->break_active = 0;
1234 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1237 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1241 if (pending & atmel_port->tx_done_mask) {
1242 /* Either PDC or interrupt transmission */
1243 atmel_uart_writel(port, ATMEL_US_IDR,
1244 atmel_port->tx_done_mask);
1245 tasklet_schedule(&atmel_port->tasklet);
1250 * status flags interrupt handler.
1253 atmel_handle_status(struct uart_port *port, unsigned int pending,
1254 unsigned int status)
1256 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1258 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1259 | ATMEL_US_CTSIC)) {
1260 atmel_port->irq_status = status;
1261 atmel_port->status_change = atmel_port->irq_status ^
1262 atmel_port->irq_status_prev;
1263 atmel_port->irq_status_prev = status;
1264 tasklet_schedule(&atmel_port->tasklet);
1271 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1273 struct uart_port *port = dev_id;
1274 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1275 unsigned int status, pending, mask, pass_counter = 0;
1276 bool gpio_handled = false;
1278 spin_lock(&atmel_port->lock_suspended);
1281 status = atmel_get_lines_status(port);
1282 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1283 pending = status & mask;
1284 if (!gpio_handled) {
1286 * Dealing with GPIO interrupt
1288 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1289 pending |= ATMEL_US_CTSIC;
1291 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1292 pending |= ATMEL_US_DSRIC;
1294 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1295 pending |= ATMEL_US_RIIC;
1297 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1298 pending |= ATMEL_US_DCDIC;
1300 gpio_handled = true;
1305 if (atmel_port->suspended) {
1306 atmel_port->pending |= pending;
1307 atmel_port->pending_status = status;
1308 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1313 atmel_handle_receive(port, pending);
1314 atmel_handle_status(port, pending, status);
1315 atmel_handle_transmit(port, pending);
1316 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1318 spin_unlock(&atmel_port->lock_suspended);
1320 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1323 static void atmel_release_tx_pdc(struct uart_port *port)
1325 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1326 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1328 dma_unmap_single(port->dev,
1335 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1337 static void atmel_tx_pdc(struct uart_port *port)
1339 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1340 struct circ_buf *xmit = &port->state->xmit;
1341 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1344 /* nothing left to transmit? */
1345 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1348 xmit->tail += pdc->ofs;
1349 xmit->tail &= UART_XMIT_SIZE - 1;
1351 port->icount.tx += pdc->ofs;
1354 /* more to transmit - setup next transfer */
1356 /* disable PDC transmit */
1357 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1359 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1360 dma_sync_single_for_device(port->dev,
1365 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1368 atmel_uart_writel(port, ATMEL_PDC_TPR,
1369 pdc->dma_addr + xmit->tail);
1370 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1371 /* re-enable PDC transmit */
1372 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1373 /* Enable interrupts */
1374 atmel_uart_writel(port, ATMEL_US_IER,
1375 atmel_port->tx_done_mask);
1377 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1378 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1379 /* DMA done, stop TX, start RX for RS485 */
1380 atmel_start_rx(port);
1384 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1385 uart_write_wakeup(port);
1388 static int atmel_prepare_tx_pdc(struct uart_port *port)
1390 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1391 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1392 struct circ_buf *xmit = &port->state->xmit;
1394 pdc->buf = xmit->buf;
1395 pdc->dma_addr = dma_map_single(port->dev,
1399 pdc->dma_size = UART_XMIT_SIZE;
1405 static void atmel_rx_from_ring(struct uart_port *port)
1407 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1408 struct circ_buf *ring = &atmel_port->rx_ring;
1410 unsigned int status;
1412 while (ring->head != ring->tail) {
1413 struct atmel_uart_char c;
1415 /* Make sure c is loaded after head. */
1418 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1420 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1427 * note that the error handling code is
1428 * out of the main execution path
1430 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1431 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1432 if (status & ATMEL_US_RXBRK) {
1433 /* ignore side-effect */
1434 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1437 if (uart_handle_break(port))
1440 if (status & ATMEL_US_PARE)
1441 port->icount.parity++;
1442 if (status & ATMEL_US_FRAME)
1443 port->icount.frame++;
1444 if (status & ATMEL_US_OVRE)
1445 port->icount.overrun++;
1447 status &= port->read_status_mask;
1449 if (status & ATMEL_US_RXBRK)
1451 else if (status & ATMEL_US_PARE)
1453 else if (status & ATMEL_US_FRAME)
1458 if (uart_handle_sysrq_char(port, c.ch))
1461 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1465 * Drop the lock here since it might end up calling
1466 * uart_start(), which takes the lock.
1468 spin_unlock(&port->lock);
1469 tty_flip_buffer_push(&port->state->port);
1470 spin_lock(&port->lock);
1473 static void atmel_release_rx_pdc(struct uart_port *port)
1475 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1478 for (i = 0; i < 2; i++) {
1479 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1481 dma_unmap_single(port->dev,
1489 static void atmel_rx_from_pdc(struct uart_port *port)
1491 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1492 struct tty_port *tport = &port->state->port;
1493 struct atmel_dma_buffer *pdc;
1494 int rx_idx = atmel_port->pdc_rx_idx;
1500 /* Reset the UART timeout early so that we don't miss one */
1501 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1503 pdc = &atmel_port->pdc_rx[rx_idx];
1504 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1507 /* If the PDC has switched buffers, RPR won't contain
1508 * any address within the current buffer. Since head
1509 * is unsigned, we just need a one-way comparison to
1512 * In this case, we just need to consume the entire
1513 * buffer and resubmit it for DMA. This will clear the
1514 * ENDRX bit as well, so that we can safely re-enable
1515 * all interrupts below.
1517 head = min(head, pdc->dma_size);
1519 if (likely(head != tail)) {
1520 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1521 pdc->dma_size, DMA_FROM_DEVICE);
1524 * head will only wrap around when we recycle
1525 * the DMA buffer, and when that happens, we
1526 * explicitly set tail to 0. So head will
1527 * always be greater than tail.
1529 count = head - tail;
1531 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1534 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1535 pdc->dma_size, DMA_FROM_DEVICE);
1537 port->icount.rx += count;
1542 * If the current buffer is full, we need to check if
1543 * the next one contains any additional data.
1545 if (head >= pdc->dma_size) {
1547 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1548 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1551 atmel_port->pdc_rx_idx = rx_idx;
1553 } while (head >= pdc->dma_size);
1556 * Drop the lock here since it might end up calling
1557 * uart_start(), which takes the lock.
1559 spin_unlock(&port->lock);
1560 tty_flip_buffer_push(tport);
1561 spin_lock(&port->lock);
1563 atmel_uart_writel(port, ATMEL_US_IER,
1564 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1567 static int atmel_prepare_rx_pdc(struct uart_port *port)
1569 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1572 for (i = 0; i < 2; i++) {
1573 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1575 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1576 if (pdc->buf == NULL) {
1578 dma_unmap_single(port->dev,
1579 atmel_port->pdc_rx[0].dma_addr,
1582 kfree(atmel_port->pdc_rx[0].buf);
1584 atmel_port->use_pdc_rx = 0;
1587 pdc->dma_addr = dma_map_single(port->dev,
1591 pdc->dma_size = PDC_BUFFER_SIZE;
1595 atmel_port->pdc_rx_idx = 0;
1597 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1598 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1600 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1601 atmel_port->pdc_rx[1].dma_addr);
1602 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1608 * tasklet handling tty stuff outside the interrupt handler.
1610 static void atmel_tasklet_func(unsigned long data)
1612 struct uart_port *port = (struct uart_port *)data;
1613 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1614 unsigned int status = atmel_port->irq_status;
1615 unsigned int status_change = atmel_port->status_change;
1617 /* The interrupt handler does not take the lock */
1618 spin_lock(&port->lock);
1620 atmel_port->schedule_tx(port);
1622 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1623 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1624 /* TODO: All reads to CSR will clear these interrupts! */
1625 if (status_change & ATMEL_US_RI)
1627 if (status_change & ATMEL_US_DSR)
1629 if (status_change & ATMEL_US_DCD)
1630 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1631 if (status_change & ATMEL_US_CTS)
1632 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1634 wake_up_interruptible(&port->state->port.delta_msr_wait);
1636 atmel_port->status_change = 0;
1639 atmel_port->schedule_rx(port);
1641 spin_unlock(&port->lock);
1644 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1645 struct platform_device *pdev)
1647 struct device_node *np = pdev->dev.of_node;
1648 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1651 /* DMA/PDC usage specification */
1652 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1653 if (of_get_property(np, "dmas", NULL)) {
1654 atmel_port->use_dma_rx = true;
1655 atmel_port->use_pdc_rx = false;
1657 atmel_port->use_dma_rx = false;
1658 atmel_port->use_pdc_rx = true;
1661 atmel_port->use_dma_rx = false;
1662 atmel_port->use_pdc_rx = false;
1665 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1666 if (of_get_property(np, "dmas", NULL)) {
1667 atmel_port->use_dma_tx = true;
1668 atmel_port->use_pdc_tx = false;
1670 atmel_port->use_dma_tx = false;
1671 atmel_port->use_pdc_tx = true;
1674 atmel_port->use_dma_tx = false;
1675 atmel_port->use_pdc_tx = false;
1679 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1680 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1681 atmel_port->use_dma_rx = false;
1682 atmel_port->use_dma_tx = false;
1687 static void atmel_init_rs485(struct uart_port *port,
1688 struct platform_device *pdev)
1690 struct device_node *np = pdev->dev.of_node;
1691 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1694 struct serial_rs485 *rs485conf = &port->rs485;
1696 /* rs485 properties */
1697 if (of_property_read_u32_array(np, "rs485-rts-delay",
1698 rs485_delay, 2) == 0) {
1699 rs485conf->delay_rts_before_send = rs485_delay[0];
1700 rs485conf->delay_rts_after_send = rs485_delay[1];
1701 rs485conf->flags = 0;
1704 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1705 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1707 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1709 rs485conf->flags |= SER_RS485_ENABLED;
1711 port->rs485 = pdata->rs485;
1716 static void atmel_set_ops(struct uart_port *port)
1718 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1720 if (atmel_use_dma_rx(port)) {
1721 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1722 atmel_port->schedule_rx = &atmel_rx_from_dma;
1723 atmel_port->release_rx = &atmel_release_rx_dma;
1724 } else if (atmel_use_pdc_rx(port)) {
1725 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1726 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1727 atmel_port->release_rx = &atmel_release_rx_pdc;
1729 atmel_port->prepare_rx = NULL;
1730 atmel_port->schedule_rx = &atmel_rx_from_ring;
1731 atmel_port->release_rx = NULL;
1734 if (atmel_use_dma_tx(port)) {
1735 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1736 atmel_port->schedule_tx = &atmel_tx_dma;
1737 atmel_port->release_tx = &atmel_release_tx_dma;
1738 } else if (atmel_use_pdc_tx(port)) {
1739 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1740 atmel_port->schedule_tx = &atmel_tx_pdc;
1741 atmel_port->release_tx = &atmel_release_tx_pdc;
1743 atmel_port->prepare_tx = NULL;
1744 atmel_port->schedule_tx = &atmel_tx_chars;
1745 atmel_port->release_tx = NULL;
1750 * Get ip name usart or uart
1752 static void atmel_get_ip_name(struct uart_port *port)
1754 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1755 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1758 /* usart and uart ascii */
1762 atmel_port->is_usart = false;
1764 if (name == usart) {
1765 dev_dbg(port->dev, "This is usart\n");
1766 atmel_port->is_usart = true;
1767 } else if (name == uart) {
1768 dev_dbg(port->dev, "This is uart\n");
1769 atmel_port->is_usart = false;
1771 /* fallback for older SoCs: use version field */
1772 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1776 dev_dbg(port->dev, "This version is usart\n");
1777 atmel_port->is_usart = true;
1781 dev_dbg(port->dev, "This version is uart\n");
1782 atmel_port->is_usart = false;
1785 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1790 static void atmel_free_gpio_irq(struct uart_port *port)
1792 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1793 enum mctrl_gpio_idx i;
1795 for (i = 0; i < UART_GPIO_MAX; i++)
1796 if (atmel_port->gpio_irq[i] >= 0)
1797 free_irq(atmel_port->gpio_irq[i], port);
1800 static int atmel_request_gpio_irq(struct uart_port *port)
1802 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1803 int *irq = atmel_port->gpio_irq;
1804 enum mctrl_gpio_idx i;
1807 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1811 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1812 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1813 "atmel_serial", port);
1815 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1820 * If something went wrong, rollback.
1822 while (err && (--i >= 0))
1824 free_irq(irq[i], port);
1830 * Perform initialization and enable port for reception
1832 static int atmel_startup(struct uart_port *port)
1834 struct platform_device *pdev = to_platform_device(port->dev);
1835 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1836 struct tty_struct *tty = port->state->port.tty;
1840 * Ensure that no interrupts are enabled otherwise when
1841 * request_irq() is called we could get stuck trying to
1842 * handle an unexpected interrupt
1844 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1845 atmel_port->ms_irq_enabled = false;
1850 retval = request_irq(port->irq, atmel_interrupt,
1851 IRQF_SHARED | IRQF_COND_SUSPEND,
1852 tty ? tty->name : "atmel_serial", port);
1854 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1859 * Get the GPIO lines IRQ
1861 retval = atmel_request_gpio_irq(port);
1865 tasklet_enable(&atmel_port->tasklet);
1868 * Initialize DMA (if necessary)
1870 atmel_init_property(atmel_port, pdev);
1871 atmel_set_ops(port);
1873 if (atmel_port->prepare_rx) {
1874 retval = atmel_port->prepare_rx(port);
1876 atmel_set_ops(port);
1879 if (atmel_port->prepare_tx) {
1880 retval = atmel_port->prepare_tx(port);
1882 atmel_set_ops(port);
1886 * Enable FIFO when available
1888 if (atmel_port->fifo_size) {
1889 unsigned int txrdym = ATMEL_US_ONE_DATA;
1890 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1893 atmel_uart_writel(port, ATMEL_US_CR,
1898 if (atmel_use_dma_tx(port))
1899 txrdym = ATMEL_US_FOUR_DATA;
1901 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1902 if (atmel_port->rts_high &&
1903 atmel_port->rts_low)
1904 fmr |= ATMEL_US_FRTSC |
1905 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1906 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1908 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1911 /* Save current CSR for comparison in atmel_tasklet_func() */
1912 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1913 atmel_port->irq_status = atmel_port->irq_status_prev;
1916 * Finally, enable the serial port
1918 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1919 /* enable xmit & rcvr */
1920 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1922 setup_timer(&atmel_port->uart_timer,
1923 atmel_uart_timer_callback,
1924 (unsigned long)port);
1926 if (atmel_use_pdc_rx(port)) {
1927 /* set UART timeout */
1928 if (!atmel_port->is_usart) {
1929 mod_timer(&atmel_port->uart_timer,
1930 jiffies + uart_poll_timeout(port));
1931 /* set USART timeout */
1933 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1934 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1936 atmel_uart_writel(port, ATMEL_US_IER,
1937 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1939 /* enable PDC controller */
1940 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1941 } else if (atmel_use_dma_rx(port)) {
1942 /* set UART timeout */
1943 if (!atmel_port->is_usart) {
1944 mod_timer(&atmel_port->uart_timer,
1945 jiffies + uart_poll_timeout(port));
1946 /* set USART timeout */
1948 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1949 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1951 atmel_uart_writel(port, ATMEL_US_IER,
1955 /* enable receive only */
1956 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1962 free_irq(port->irq, port);
1968 * Flush any TX data submitted for DMA. Called when the TX circular
1971 static void atmel_flush_buffer(struct uart_port *port)
1973 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1975 if (atmel_use_pdc_tx(port)) {
1976 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1977 atmel_port->pdc_tx.ofs = 0;
1984 static void atmel_shutdown(struct uart_port *port)
1986 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1989 * Prevent any tasklets being scheduled during
1992 del_timer_sync(&atmel_port->uart_timer);
1995 * Clear out any scheduled tasklets before
1996 * we destroy the buffers
1998 tasklet_disable(&atmel_port->tasklet);
1999 tasklet_kill(&atmel_port->tasklet);
2002 * Ensure everything is stopped and
2003 * disable all interrupts, port and break condition.
2005 atmel_stop_rx(port);
2006 atmel_stop_tx(port);
2008 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2009 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2013 * Shut-down the DMA.
2015 if (atmel_port->release_rx)
2016 atmel_port->release_rx(port);
2017 if (atmel_port->release_tx)
2018 atmel_port->release_tx(port);
2021 * Reset ring buffer pointers
2023 atmel_port->rx_ring.head = 0;
2024 atmel_port->rx_ring.tail = 0;
2027 * Free the interrupts
2029 free_irq(port->irq, port);
2030 atmel_free_gpio_irq(port);
2032 atmel_port->ms_irq_enabled = false;
2034 atmel_flush_buffer(port);
2038 * Power / Clock management.
2040 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2041 unsigned int oldstate)
2043 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2048 * Enable the peripheral clock for this serial port.
2049 * This is called on uart_open() or a resume event.
2051 clk_prepare_enable(atmel_port->clk);
2053 /* re-enable interrupts if we disabled some on suspend */
2054 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2057 /* Back up the interrupt mask and disable all interrupts */
2058 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2059 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2062 * Disable the peripheral clock for this serial port.
2063 * This is called on uart_close() or a suspend event.
2065 clk_disable_unprepare(atmel_port->clk);
2068 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2073 * Change the port parameters
2075 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2076 struct ktermios *old)
2078 unsigned long flags;
2079 unsigned int old_mode, mode, imr, quot, baud;
2081 /* save the current mode register */
2082 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2084 /* reset the mode, clock divisor, parity, stop bits and data size */
2085 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2086 ATMEL_US_PAR | ATMEL_US_USMODE);
2088 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2089 quot = uart_get_divisor(port, baud);
2091 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2093 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2097 switch (termios->c_cflag & CSIZE) {
2099 mode |= ATMEL_US_CHRL_5;
2102 mode |= ATMEL_US_CHRL_6;
2105 mode |= ATMEL_US_CHRL_7;
2108 mode |= ATMEL_US_CHRL_8;
2113 if (termios->c_cflag & CSTOPB)
2114 mode |= ATMEL_US_NBSTOP_2;
2117 if (termios->c_cflag & PARENB) {
2118 /* Mark or Space parity */
2119 if (termios->c_cflag & CMSPAR) {
2120 if (termios->c_cflag & PARODD)
2121 mode |= ATMEL_US_PAR_MARK;
2123 mode |= ATMEL_US_PAR_SPACE;
2124 } else if (termios->c_cflag & PARODD)
2125 mode |= ATMEL_US_PAR_ODD;
2127 mode |= ATMEL_US_PAR_EVEN;
2129 mode |= ATMEL_US_PAR_NONE;
2131 spin_lock_irqsave(&port->lock, flags);
2133 port->read_status_mask = ATMEL_US_OVRE;
2134 if (termios->c_iflag & INPCK)
2135 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2136 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2137 port->read_status_mask |= ATMEL_US_RXBRK;
2139 if (atmel_use_pdc_rx(port))
2140 /* need to enable error interrupts */
2141 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2144 * Characters to ignore
2146 port->ignore_status_mask = 0;
2147 if (termios->c_iflag & IGNPAR)
2148 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2149 if (termios->c_iflag & IGNBRK) {
2150 port->ignore_status_mask |= ATMEL_US_RXBRK;
2152 * If we're ignoring parity and break indicators,
2153 * ignore overruns too (for real raw support).
2155 if (termios->c_iflag & IGNPAR)
2156 port->ignore_status_mask |= ATMEL_US_OVRE;
2158 /* TODO: Ignore all characters if CREAD is set.*/
2160 /* update the per-port timeout */
2161 uart_update_timeout(port, termios->c_cflag, baud);
2164 * save/disable interrupts. The tty layer will ensure that the
2165 * transmitter is empty if requested by the caller, so there's
2166 * no need to wait for it here.
2168 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2169 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2171 /* disable receiver and transmitter */
2172 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2175 if (port->rs485.flags & SER_RS485_ENABLED) {
2176 atmel_uart_writel(port, ATMEL_US_TTGR,
2177 port->rs485.delay_rts_after_send);
2178 mode |= ATMEL_US_USMODE_RS485;
2179 } else if (termios->c_cflag & CRTSCTS) {
2180 /* RS232 with hardware handshake (RTS/CTS) */
2181 if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) {
2182 dev_info(port->dev, "not enabling hardware flow control because DMA is used");
2183 termios->c_cflag &= ~CRTSCTS;
2185 mode |= ATMEL_US_USMODE_HWHS;
2188 /* RS232 without hadware handshake */
2189 mode |= ATMEL_US_USMODE_NORMAL;
2192 /* set the mode, clock divisor, parity, stop bits and data size */
2193 atmel_uart_writel(port, ATMEL_US_MR, mode);
2196 * when switching the mode, set the RTS line state according to the
2197 * new mode, otherwise keep the former state
2199 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2200 unsigned int rts_state;
2202 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2203 /* let the hardware control the RTS line */
2204 rts_state = ATMEL_US_RTSDIS;
2206 /* force RTS line to low level */
2207 rts_state = ATMEL_US_RTSEN;
2210 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2213 /* set the baud rate */
2214 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2215 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2216 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2218 /* restore interrupts */
2219 atmel_uart_writel(port, ATMEL_US_IER, imr);
2221 /* CTS flow-control and modem-status interrupts */
2222 if (UART_ENABLE_MS(port, termios->c_cflag))
2223 atmel_enable_ms(port);
2225 atmel_disable_ms(port);
2227 spin_unlock_irqrestore(&port->lock, flags);
2230 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2232 if (termios->c_line == N_PPS) {
2233 port->flags |= UPF_HARDPPS_CD;
2234 spin_lock_irq(&port->lock);
2235 atmel_enable_ms(port);
2236 spin_unlock_irq(&port->lock);
2238 port->flags &= ~UPF_HARDPPS_CD;
2239 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2240 spin_lock_irq(&port->lock);
2241 atmel_disable_ms(port);
2242 spin_unlock_irq(&port->lock);
2248 * Return string describing the specified port
2250 static const char *atmel_type(struct uart_port *port)
2252 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2256 * Release the memory region(s) being used by 'port'.
2258 static void atmel_release_port(struct uart_port *port)
2260 struct platform_device *pdev = to_platform_device(port->dev);
2261 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2263 release_mem_region(port->mapbase, size);
2265 if (port->flags & UPF_IOREMAP) {
2266 iounmap(port->membase);
2267 port->membase = NULL;
2272 * Request the memory region(s) being used by 'port'.
2274 static int atmel_request_port(struct uart_port *port)
2276 struct platform_device *pdev = to_platform_device(port->dev);
2277 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2279 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2282 if (port->flags & UPF_IOREMAP) {
2283 port->membase = ioremap(port->mapbase, size);
2284 if (port->membase == NULL) {
2285 release_mem_region(port->mapbase, size);
2294 * Configure/autoconfigure the port.
2296 static void atmel_config_port(struct uart_port *port, int flags)
2298 if (flags & UART_CONFIG_TYPE) {
2299 port->type = PORT_ATMEL;
2300 atmel_request_port(port);
2305 * Verify the new serial_struct (for TIOCSSERIAL).
2307 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2310 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2312 if (port->irq != ser->irq)
2314 if (ser->io_type != SERIAL_IO_MEM)
2316 if (port->uartclk / 16 != ser->baud_base)
2318 if (port->mapbase != (unsigned long)ser->iomem_base)
2320 if (port->iobase != ser->port)
2327 #ifdef CONFIG_CONSOLE_POLL
2328 static int atmel_poll_get_char(struct uart_port *port)
2330 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2333 return atmel_uart_read_char(port);
2336 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2338 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2341 atmel_uart_write_char(port, ch);
2345 static struct uart_ops atmel_pops = {
2346 .tx_empty = atmel_tx_empty,
2347 .set_mctrl = atmel_set_mctrl,
2348 .get_mctrl = atmel_get_mctrl,
2349 .stop_tx = atmel_stop_tx,
2350 .start_tx = atmel_start_tx,
2351 .stop_rx = atmel_stop_rx,
2352 .enable_ms = atmel_enable_ms,
2353 .break_ctl = atmel_break_ctl,
2354 .startup = atmel_startup,
2355 .shutdown = atmel_shutdown,
2356 .flush_buffer = atmel_flush_buffer,
2357 .set_termios = atmel_set_termios,
2358 .set_ldisc = atmel_set_ldisc,
2360 .release_port = atmel_release_port,
2361 .request_port = atmel_request_port,
2362 .config_port = atmel_config_port,
2363 .verify_port = atmel_verify_port,
2364 .pm = atmel_serial_pm,
2365 #ifdef CONFIG_CONSOLE_POLL
2366 .poll_get_char = atmel_poll_get_char,
2367 .poll_put_char = atmel_poll_put_char,
2372 * Configure the port from the platform device resource info.
2374 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2375 struct platform_device *pdev)
2378 struct uart_port *port = &atmel_port->uart;
2379 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2381 atmel_init_property(atmel_port, pdev);
2382 atmel_set_ops(port);
2384 atmel_init_rs485(port, pdev);
2386 port->iotype = UPIO_MEM;
2387 port->flags = UPF_BOOT_AUTOCONF;
2388 port->ops = &atmel_pops;
2390 port->dev = &pdev->dev;
2391 port->mapbase = pdev->resource[0].start;
2392 port->irq = pdev->resource[1].start;
2393 port->rs485_config = atmel_config_rs485;
2395 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2396 (unsigned long)port);
2397 tasklet_disable(&atmel_port->tasklet);
2399 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2401 if (pdata && pdata->regs) {
2402 /* Already mapped by setup code */
2403 port->membase = pdata->regs;
2405 port->flags |= UPF_IOREMAP;
2406 port->membase = NULL;
2409 /* for console, the clock could already be configured */
2410 if (!atmel_port->clk) {
2411 atmel_port->clk = clk_get(&pdev->dev, "usart");
2412 if (IS_ERR(atmel_port->clk)) {
2413 ret = PTR_ERR(atmel_port->clk);
2414 atmel_port->clk = NULL;
2417 ret = clk_prepare_enable(atmel_port->clk);
2419 clk_put(atmel_port->clk);
2420 atmel_port->clk = NULL;
2423 port->uartclk = clk_get_rate(atmel_port->clk);
2424 clk_disable_unprepare(atmel_port->clk);
2425 /* only enable clock when USART is in use */
2428 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2429 if (port->rs485.flags & SER_RS485_ENABLED)
2430 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2431 else if (atmel_use_pdc_tx(port)) {
2432 port->fifosize = PDC_BUFFER_SIZE;
2433 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2435 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2441 struct platform_device *atmel_default_console_device; /* the serial console device */
2443 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2444 static void atmel_console_putchar(struct uart_port *port, int ch)
2446 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2448 atmel_uart_write_char(port, ch);
2452 * Interrupts are disabled on entering
2454 static void atmel_console_write(struct console *co, const char *s, u_int count)
2456 struct uart_port *port = &atmel_ports[co->index].uart;
2457 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2458 unsigned int status, imr;
2459 unsigned int pdc_tx;
2462 * First, save IMR and then disable interrupts
2464 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2465 atmel_uart_writel(port, ATMEL_US_IDR,
2466 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2468 /* Store PDC transmit status and disable it */
2469 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2470 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2472 uart_console_write(port, s, count, atmel_console_putchar);
2475 * Finally, wait for transmitter to become empty
2479 status = atmel_uart_readl(port, ATMEL_US_CSR);
2480 } while (!(status & ATMEL_US_TXRDY));
2482 /* Restore PDC transmit status */
2484 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2486 /* set interrupts back the way they were */
2487 atmel_uart_writel(port, ATMEL_US_IER, imr);
2491 * If the port was already initialised (eg, by a boot loader),
2492 * try to determine the current setup.
2494 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2495 int *parity, int *bits)
2497 unsigned int mr, quot;
2500 * If the baud rate generator isn't running, the port wasn't
2501 * initialized by the boot loader.
2503 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2507 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2508 if (mr == ATMEL_US_CHRL_8)
2513 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2514 if (mr == ATMEL_US_PAR_EVEN)
2516 else if (mr == ATMEL_US_PAR_ODD)
2520 * The serial core only rounds down when matching this to a
2521 * supported baud rate. Make sure we don't end up slightly
2522 * lower than one of those, as it would make us fall through
2523 * to a much lower baud rate than we really want.
2525 *baud = port->uartclk / (16 * (quot - 1));
2528 static int __init atmel_console_setup(struct console *co, char *options)
2531 struct uart_port *port = &atmel_ports[co->index].uart;
2537 if (port->membase == NULL) {
2538 /* Port not initialized yet - delay setup */
2542 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2546 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2547 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2548 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2551 uart_parse_options(options, &baud, &parity, &bits, &flow);
2553 atmel_console_get_options(port, &baud, &parity, &bits);
2555 return uart_set_options(port, co, baud, parity, bits, flow);
2558 static struct uart_driver atmel_uart;
2560 static struct console atmel_console = {
2561 .name = ATMEL_DEVICENAME,
2562 .write = atmel_console_write,
2563 .device = uart_console_device,
2564 .setup = atmel_console_setup,
2565 .flags = CON_PRINTBUFFER,
2567 .data = &atmel_uart,
2570 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2573 * Early console initialization (before VM subsystem initialized).
2575 static int __init atmel_console_init(void)
2578 if (atmel_default_console_device) {
2579 struct atmel_uart_data *pdata =
2580 dev_get_platdata(&atmel_default_console_device->dev);
2581 int id = pdata->num;
2582 struct atmel_uart_port *port = &atmel_ports[id];
2584 port->backup_imr = 0;
2585 port->uart.line = id;
2587 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2588 ret = atmel_init_port(port, atmel_default_console_device);
2591 register_console(&atmel_console);
2597 console_initcall(atmel_console_init);
2600 * Late console initialization.
2602 static int __init atmel_late_console_init(void)
2604 if (atmel_default_console_device
2605 && !(atmel_console.flags & CON_ENABLED))
2606 register_console(&atmel_console);
2611 core_initcall(atmel_late_console_init);
2613 static inline bool atmel_is_console_port(struct uart_port *port)
2615 return port->cons && port->cons->index == port->line;
2619 #define ATMEL_CONSOLE_DEVICE NULL
2621 static inline bool atmel_is_console_port(struct uart_port *port)
2627 static struct uart_driver atmel_uart = {
2628 .owner = THIS_MODULE,
2629 .driver_name = "atmel_serial",
2630 .dev_name = ATMEL_DEVICENAME,
2631 .major = SERIAL_ATMEL_MAJOR,
2632 .minor = MINOR_START,
2633 .nr = ATMEL_MAX_UART,
2634 .cons = ATMEL_CONSOLE_DEVICE,
2638 static bool atmel_serial_clk_will_stop(void)
2640 #ifdef CONFIG_ARCH_AT91
2641 return at91_suspend_entering_slow_clock();
2647 static int atmel_serial_suspend(struct platform_device *pdev,
2650 struct uart_port *port = platform_get_drvdata(pdev);
2651 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2653 if (atmel_is_console_port(port) && console_suspend_enabled) {
2654 /* Drain the TX shifter */
2655 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2660 /* we can not wake up if we're running on slow clock */
2661 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2662 if (atmel_serial_clk_will_stop()) {
2663 unsigned long flags;
2665 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2666 atmel_port->suspended = true;
2667 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2668 device_set_wakeup_enable(&pdev->dev, 0);
2671 uart_suspend_port(&atmel_uart, port);
2676 static int atmel_serial_resume(struct platform_device *pdev)
2678 struct uart_port *port = platform_get_drvdata(pdev);
2679 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2680 unsigned long flags;
2682 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2683 if (atmel_port->pending) {
2684 atmel_handle_receive(port, atmel_port->pending);
2685 atmel_handle_status(port, atmel_port->pending,
2686 atmel_port->pending_status);
2687 atmel_handle_transmit(port, atmel_port->pending);
2688 atmel_port->pending = 0;
2690 atmel_port->suspended = false;
2691 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2693 uart_resume_port(&atmel_uart, port);
2694 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2699 #define atmel_serial_suspend NULL
2700 #define atmel_serial_resume NULL
2703 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2705 enum mctrl_gpio_idx i;
2706 struct gpio_desc *gpiod;
2708 p->gpios = mctrl_gpio_init_noauto(dev, 0);
2709 if (IS_ERR(p->gpios))
2710 return PTR_ERR(p->gpios);
2712 for (i = 0; i < UART_GPIO_MAX; i++) {
2713 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2714 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2715 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2717 p->gpio_irq[i] = -EINVAL;
2723 static void atmel_serial_probe_fifos(struct atmel_uart_port *port,
2724 struct platform_device *pdev)
2726 port->fifo_size = 0;
2730 if (of_property_read_u32(pdev->dev.of_node,
2735 if (!port->fifo_size)
2738 if (port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2739 port->fifo_size = 0;
2740 dev_err(&pdev->dev, "Invalid FIFO size\n");
2745 * 0 <= rts_low <= rts_high <= fifo_size
2746 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2747 * to flush their internal TX FIFO, commonly up to 16 data, before
2748 * actually stopping to send new data. So we try to set the RTS High
2749 * Threshold to a reasonably high value respecting this 16 data
2750 * empirical rule when possible.
2752 port->rts_high = max_t(int, port->fifo_size >> 1,
2753 port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2754 port->rts_low = max_t(int, port->fifo_size >> 2,
2755 port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2757 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2759 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2761 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2765 static int atmel_serial_probe(struct platform_device *pdev)
2767 struct atmel_uart_port *port;
2768 struct device_node *np = pdev->dev.of_node;
2769 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2774 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2777 ret = of_alias_get_id(np, "serial");
2783 /* port id not found in platform data nor device-tree aliases:
2784 * auto-enumerate it */
2785 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2787 if (ret >= ATMEL_MAX_UART) {
2792 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2793 /* port already in use */
2798 port = &atmel_ports[ret];
2799 port->backup_imr = 0;
2800 port->uart.line = ret;
2801 atmel_serial_probe_fifos(port, pdev);
2803 spin_lock_init(&port->lock_suspended);
2805 ret = atmel_init_gpios(port, &pdev->dev);
2807 dev_err(&pdev->dev, "Failed to initialize GPIOs.");
2811 ret = atmel_init_port(port, pdev);
2815 if (!atmel_use_pdc_rx(&port->uart)) {
2817 data = kmalloc(sizeof(struct atmel_uart_char)
2818 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2820 goto err_alloc_ring;
2821 port->rx_ring.buf = data;
2824 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED;
2826 ret = uart_add_one_port(&atmel_uart, &port->uart);
2830 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2831 if (atmel_is_console_port(&port->uart)
2832 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2834 * The serial core enabled the clock for us, so undo
2835 * the clk_prepare_enable() in atmel_console_setup()
2837 clk_disable_unprepare(port->clk);
2841 device_init_wakeup(&pdev->dev, 1);
2842 platform_set_drvdata(pdev, port);
2845 * The peripheral clock has been disabled by atmel_init_port():
2846 * enable it before accessing I/O registers
2848 clk_prepare_enable(port->clk);
2850 if (rs485_enabled) {
2851 atmel_uart_writel(&port->uart, ATMEL_US_MR,
2852 ATMEL_US_USMODE_NORMAL);
2853 atmel_uart_writel(&port->uart, ATMEL_US_CR, ATMEL_US_RTSEN);
2857 * Get port name of usart or uart
2859 atmel_get_ip_name(&port->uart);
2862 * The peripheral clock can now safely be disabled till the port
2865 clk_disable_unprepare(port->clk);
2870 kfree(port->rx_ring.buf);
2871 port->rx_ring.buf = NULL;
2873 if (!atmel_is_console_port(&port->uart)) {
2878 clear_bit(port->uart.line, atmel_ports_in_use);
2883 static int atmel_serial_remove(struct platform_device *pdev)
2885 struct uart_port *port = platform_get_drvdata(pdev);
2886 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2889 tasklet_kill(&atmel_port->tasklet);
2891 device_init_wakeup(&pdev->dev, 0);
2893 ret = uart_remove_one_port(&atmel_uart, port);
2895 kfree(atmel_port->rx_ring.buf);
2897 /* "port" is allocated statically, so we shouldn't free it */
2899 clear_bit(port->line, atmel_ports_in_use);
2901 clk_put(atmel_port->clk);
2906 static struct platform_driver atmel_serial_driver = {
2907 .probe = atmel_serial_probe,
2908 .remove = atmel_serial_remove,
2909 .suspend = atmel_serial_suspend,
2910 .resume = atmel_serial_resume,
2912 .name = "atmel_usart",
2913 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2917 static int __init atmel_serial_init(void)
2921 ret = uart_register_driver(&atmel_uart);
2925 ret = platform_driver_register(&atmel_serial_driver);
2927 uart_unregister_driver(&atmel_uart);
2932 static void __exit atmel_serial_exit(void)
2934 platform_driver_unregister(&atmel_serial_driver);
2935 uart_unregister_driver(&atmel_uart);
2938 module_init(atmel_serial_init);
2939 module_exit(atmel_serial_exit);
2941 MODULE_AUTHOR("Rick Bronson");
2942 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2943 MODULE_LICENSE("GPL");
2944 MODULE_ALIAS("platform:atmel_usart");