2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
38 #include <linux/irq.h>
40 #include <linux/usb/ch9.h>
41 #include <linux/usb/gadget.h>
42 #include <linux/usb/of.h>
43 #include <linux/usb/otg.h>
45 #include "platform_data.h"
52 /* -------------------------------------------------------------------------- */
54 void dwc3_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
58 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
61 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
63 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
68 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
72 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
73 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
74 reg |= DWC3_GCTL_PRTCAPDIR(mode);
76 * Set this bit so that device attempts three more times at SS, even
77 * if it failed previously to operate in SS mode.
79 reg |= DWC3_GCTL_U2RSTECN;
80 reg &= ~(DWC3_GCTL_SOFITPSYNC);
81 reg &= ~(DWC3_GCTL_PWRDNSCALEMASK);
82 reg |= DWC3_GCTL_PWRDNSCALE(2);
83 reg |= DWC3_GCTL_U2EXIT_LFPS;
84 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
86 if (mode == DWC3_GCTL_PRTCAP_OTG || mode == DWC3_GCTL_PRTCAP_HOST) {
88 * Allow ITP generated off of ref clk based counter instead
89 * of UTMI/ULPI clk based counter, when superspeed only is
90 * active so that UTMI/ULPI PHY can be suspened.
92 * Starting with revision 2.50A, GFLADJ_REFCLK_LPM_SEL is used
95 if (dwc->revision < DWC3_REVISION_250A) {
96 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
97 reg |= DWC3_GCTL_SOFITPSYNC;
98 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
100 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
101 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
102 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
108 * Peforms initialization of HS and SS PHYs.
109 * If used as a part of POR or init sequence it is recommended
110 * that we should perform hard reset of the PHYs prior to invoking
112 * @dwc: pointer to our context structure
114 static int dwc3_init_usb_phys(struct dwc3 *dwc)
119 ret = usb_phy_init(dwc->usb2_phy);
121 pr_err("%s: usb_phy_init(dwc->usb2_phy) returned %d\n",
126 if (dwc->maximum_speed == USB_SPEED_HIGH)
127 goto generic_phy_init;
129 ret = usb_phy_init(dwc->usb3_phy);
132 * Setting Max speed as high when USB3 PHY initialiation
133 * is failing and USB superspeed can't be supported.
135 dwc->maximum_speed = USB_SPEED_HIGH;
137 pr_err("%s: usb_phy_init(dwc->usb3_phy) returned %d\n",
143 ret = phy_init(dwc->usb2_generic_phy);
147 ret = phy_init(dwc->usb3_generic_phy);
149 phy_exit(dwc->usb2_generic_phy);
157 * dwc3_core_reset - Issues core soft reset and PHY reset
158 * @dwc: pointer to our context structure
160 static int dwc3_core_reset(struct dwc3 *dwc)
166 usb_phy_reset(dwc->usb2_phy);
168 if (dwc->maximum_speed == USB_SPEED_SUPER)
169 usb_phy_reset(dwc->usb3_phy);
171 /* Initialize PHYs */
172 ret = dwc3_init_usb_phys(dwc);
174 pr_err("%s: dwc3_init_phys returned %d\n",
179 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
180 reg &= ~DWC3_GUSB3PIPECTL_DELAYP1TRANS;
182 /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
183 if (dwc->revision <= DWC3_REVISION_310A)
184 reg |= DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX;
186 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
188 dwc3_notify_event(dwc, DWC3_CONTROLLER_RESET_EVENT, 0);
190 dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT, 0);
196 * dwc3_soft_reset - Issue soft reset
197 * @dwc: Pointer to our controller context structure
199 static int dwc3_soft_reset(struct dwc3 *dwc)
201 unsigned long timeout;
204 timeout = jiffies + msecs_to_jiffies(500);
205 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
207 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
208 if (!(reg & DWC3_DCTL_CSFTRST))
211 if (time_after(jiffies, timeout)) {
212 dev_err(dwc->dev, "Reset Timed Out\n");
223 * dwc3_frame_length_adjustment - Adjusts frame length if required
224 * @dwc3: Pointer to our controller context structure
225 * @fladj: Value of GFLADJ_30MHZ to adjust frame length
227 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
232 if (dwc->revision < DWC3_REVISION_250A)
238 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
239 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
240 if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
241 "request value same as default, ignoring\n")) {
242 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
243 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
244 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
249 * dwc3_free_one_event_buffer - Frees one event buffer
250 * @dwc: Pointer to our controller context structure
251 * @evt: Pointer to event buffer to be freed
253 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
254 struct dwc3_event_buffer *evt)
256 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
260 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
261 * @dwc: Pointer to our controller context structure
262 * @length: size of the event buffer
264 * Returns a pointer to the allocated event buffer structure on success
265 * otherwise ERR_PTR(errno).
267 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
268 unsigned length, enum event_buf_type type)
270 struct dwc3_event_buffer *evt;
272 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
274 return ERR_PTR(-ENOMEM);
277 evt->length = length;
279 evt->buf = dma_alloc_coherent(dwc->dev, length,
280 &evt->dma, GFP_KERNEL);
282 return ERR_PTR(-ENOMEM);
288 * dwc3_free_event_buffers - frees all allocated event buffers
289 * @dwc: Pointer to our controller context structure
291 static void dwc3_free_event_buffers(struct dwc3 *dwc)
293 struct dwc3_event_buffer *evt;
296 for (i = 0; i < dwc->num_event_buffers; i++) {
297 evt = dwc->ev_buffs[i];
299 dwc3_free_one_event_buffer(dwc, evt);
304 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
305 * @dwc: pointer to our controller context structure
306 * @length: size of event buffer
308 * Returns 0 on success otherwise negative errno. In the error case, dwc
309 * may contain some buffers allocated but not all which were requested.
311 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
316 dwc->num_event_buffers = dwc->num_normal_event_buffers +
317 dwc->num_gsi_event_buffers;
319 dwc->ev_buffs = devm_kzalloc(dwc->dev,
320 sizeof(*dwc->ev_buffs) * dwc->num_event_buffers,
325 for (i = 0; i < dwc->num_normal_event_buffers; i++) {
326 struct dwc3_event_buffer *evt;
328 evt = dwc3_alloc_one_event_buffer(dwc, length,
329 EVT_BUF_TYPE_NORMAL);
331 dev_err(dwc->dev, "can't allocate event buffer\n");
334 dwc->ev_buffs[j++] = evt;
337 for (i = 0; i < dwc->num_gsi_event_buffers; i++) {
338 struct dwc3_event_buffer *evt;
340 evt = dwc3_alloc_one_event_buffer(dwc, length,
343 dev_err(dwc->dev, "can't allocate event buffer\n");
346 dwc->ev_buffs[j++] = evt;
353 * dwc3_event_buffers_setup - setup our allocated event buffers
354 * @dwc: pointer to our controller context structure
356 * Returns 0 on success otherwise negative errno.
358 int dwc3_event_buffers_setup(struct dwc3 *dwc)
360 struct dwc3_event_buffer *evt;
363 for (n = 0; n < dwc->num_event_buffers; n++) {
364 evt = dwc->ev_buffs[n];
365 dev_dbg(dwc->dev, "Event buf %pK dma %08llx length %d\n",
366 evt->buf, (unsigned long long) evt->dma,
369 memset(evt->buf, 0, evt->length);
373 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
374 lower_32_bits(evt->dma));
376 if (evt->type == EVT_BUF_TYPE_NORMAL) {
377 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
378 upper_32_bits(evt->dma));
379 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
380 DWC3_GEVNTSIZ_SIZE(evt->length));
382 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
383 DWC3_GEVNTADRHI_EVNTADRHI_GSI_EN(
384 DWC3_GEVENT_TYPE_GSI) |
385 DWC3_GEVNTADRHI_EVNTADRHI_GSI_IDX(n));
387 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
388 DWC3_GEVNTCOUNT_EVNTINTRPTMASK |
389 ((evt->length) & 0xffff));
392 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
398 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
400 struct dwc3_event_buffer *evt;
403 for (n = 0; n < dwc->num_event_buffers; n++) {
404 evt = dwc->ev_buffs[n];
408 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
409 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
410 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
411 | DWC3_GEVNTSIZ_SIZE(0));
412 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
416 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
418 if (!dwc->has_hibernation)
421 if (!dwc->nr_scratch)
424 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
425 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
426 if (!dwc->scratchbuf)
432 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
434 dma_addr_t scratch_addr;
438 if (!dwc->has_hibernation)
441 if (!dwc->nr_scratch)
444 /* should never fall here */
445 if (!WARN_ON(dwc->scratchbuf))
448 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
449 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
451 if (dma_mapping_error(dwc->dev, scratch_addr)) {
452 dev_err(dwc->dev, "failed to map scratch buffer\n");
457 dwc->scratch_addr = scratch_addr;
459 param = lower_32_bits(scratch_addr);
461 ret = dwc3_send_gadget_generic_command(dwc,
462 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
466 param = upper_32_bits(scratch_addr);
468 ret = dwc3_send_gadget_generic_command(dwc,
469 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
476 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
477 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
483 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
485 if (!dwc->has_hibernation)
488 if (!dwc->nr_scratch)
491 /* should never fall here */
492 if (!WARN_ON(dwc->scratchbuf))
495 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
496 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
497 kfree(dwc->scratchbuf);
500 static void dwc3_core_num_eps(struct dwc3 *dwc)
502 struct dwc3_hwparams *parms = &dwc->hwparams;
504 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
505 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
507 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
508 dwc->num_in_eps, dwc->num_out_eps);
511 static void dwc3_cache_hwparams(struct dwc3 *dwc)
513 struct dwc3_hwparams *parms = &dwc->hwparams;
515 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
516 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
517 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
518 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
519 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
520 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
521 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
522 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
523 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
527 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
528 * @dwc: Pointer to our controller context structure
530 * Returns 0 on success. The USB PHY interfaces are configured but not
531 * initialized. The PHY interfaces and the PHYs get initialized together with
532 * the core in dwc3_core_init.
534 static int dwc3_phy_setup(struct dwc3 *dwc)
539 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
542 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
543 * to '0' during coreConsultant configuration. So default value
544 * will be '0' when the core is reset. Application needs to set it
545 * to '1' after the core initialization is completed.
547 if (dwc->revision > DWC3_REVISION_194A)
548 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
550 if (dwc->u2ss_inp3_quirk)
551 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
553 if (dwc->req_p1p2p3_quirk)
554 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
556 if (dwc->del_p1p2p3_quirk)
557 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
559 if (dwc->del_phy_power_chg_quirk)
560 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
562 if (dwc->lfps_filter_quirk)
563 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
565 if (dwc->rx_detect_poll_quirk)
566 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
568 if (dwc->tx_de_emphasis_quirk)
569 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
571 if (dwc->dis_u3_susphy_quirk)
572 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
574 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
576 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
578 /* Select the HS PHY interface */
579 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
580 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
581 if (dwc->hsphy_interface &&
582 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
583 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
585 } else if (dwc->hsphy_interface &&
586 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
587 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
588 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
590 /* Relying on default value. */
591 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
595 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
596 /* Making sure the interface and PHY are operational */
597 ret = dwc3_soft_reset(dwc);
603 ret = dwc3_ulpi_init(dwc);
612 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
613 * '0' during coreConsultant configuration. So default value will
614 * be '0' when the core is reset. Application needs to set it to
615 * '1' after the core initialization is completed.
617 if (dwc->revision > DWC3_REVISION_194A)
618 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
620 if (dwc->dis_u2_susphy_quirk)
621 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
623 if (dwc->dis_enblslpm_quirk)
624 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
626 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
632 * dwc3_core_init - Low-level initialization of DWC3 Core
633 * @dwc: Pointer to our controller context structure
635 * Returns 0 on success otherwise negative errno.
637 int dwc3_core_init(struct dwc3 *dwc)
639 u32 hwparams4 = dwc->hwparams.hwparams4;
643 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
644 /* This should read as U3 followed by revision number */
645 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
646 /* Detected DWC_usb3 IP */
648 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
649 /* Detected DWC_usb31 IP */
650 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
651 dwc->revision |= DWC3_REVISION_IS_DWC31;
653 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
659 * Write Linux Version Code to our GUID register so it's easy to figure
660 * out which kernel version a bug was found.
662 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
664 /* Handle USB2.0-only core configuration */
665 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
666 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
667 if (dwc->max_hw_supp_speed == USB_SPEED_SUPER) {
668 dwc->max_hw_supp_speed = USB_SPEED_HIGH;
669 dwc->maximum_speed = dwc->max_hw_supp_speed;
674 * Workaround for STAR 9000961433 which affects only version
675 * 3.00a of the DWC_usb3 core. This prevents the controller
676 * interrupt from being masked while handling events. IMOD
677 * allows us to work around this issue. Enable it for the
680 if (!dwc->imod_interval && (dwc->revision == DWC3_REVISION_300A))
681 dwc->imod_interval = 1;
683 ret = dwc3_core_reset(dwc);
687 /* issue device SoftReset too */
688 ret = dwc3_soft_reset(dwc);
692 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
693 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
695 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
696 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
698 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
699 * issue which would cause xHCI compliance tests to fail.
701 * Because of that we cannot enable clock gating on such
706 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
709 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
710 dwc->dr_mode == USB_DR_MODE_OTG) &&
711 (dwc->revision >= DWC3_REVISION_210A &&
712 dwc->revision <= DWC3_REVISION_250A))
713 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
715 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
717 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
718 /* enable hibernation here */
719 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
722 * REVISIT Enabling this bit so that host-mode hibernation
723 * will work. Device-mode hibernation is not yet implemented.
725 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
728 dev_dbg(dwc->dev, "No power optimization available\n");
731 /* check if current dwc3 is on simulation board */
732 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
733 dev_dbg(dwc->dev, "it is on FPGA board\n");
737 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
738 "disable_scramble cannot be used on non-FPGA builds\n");
740 if (dwc->disable_scramble_quirk && dwc->is_fpga)
741 reg |= DWC3_GCTL_DISSCRAMBLE;
743 reg &= ~DWC3_GCTL_DISSCRAMBLE;
745 if (dwc->u2exit_lfps_quirk)
746 reg |= DWC3_GCTL_U2EXIT_LFPS;
749 * WORKAROUND: DWC3 revisions <1.90a have a bug
750 * where the device can fail to connect at SuperSpeed
751 * and falls back to high-speed mode which causes
752 * the device to enter a Connect/Disconnect loop
754 if (dwc->revision < DWC3_REVISION_190A)
755 reg |= DWC3_GCTL_U2RSTECN;
757 dwc3_core_num_eps(dwc);
760 * Disable clock gating to work around a known HW bug that causes the
761 * internal RAM clock to get stuck when entering low power modes.
763 if (dwc->disable_clk_gating) {
764 dev_dbg(dwc->dev, "Disabling controller clock gating.\n");
765 reg |= DWC3_GCTL_DSBLCLKGTNG;
768 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
770 ret = dwc3_alloc_scratch_buffers(dwc);
774 ret = dwc3_setup_scratch_buffers(dwc);
779 * clear Elastic buffer mode in GUSBPIPE_CTRL(0) register, otherwise
780 * it results in high link errors and could cause SS mode transfer
783 if (!dwc->nominal_elastic_buffer) {
784 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
785 reg &= ~DWC3_GUSB3PIPECTL_ELASTIC_BUF_MODE;
786 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
792 dwc3_free_scratch_buffers(dwc);
795 usb_phy_shutdown(dwc->usb2_phy);
796 usb_phy_shutdown(dwc->usb3_phy);
797 phy_exit(dwc->usb2_generic_phy);
798 phy_exit(dwc->usb3_generic_phy);
804 static void dwc3_core_exit(struct dwc3 *dwc)
806 dwc3_free_scratch_buffers(dwc);
807 usb_phy_shutdown(dwc->usb2_phy);
808 usb_phy_shutdown(dwc->usb3_phy);
809 phy_exit(dwc->usb2_generic_phy);
810 phy_exit(dwc->usb3_generic_phy);
813 static int dwc3_core_get_phy(struct dwc3 *dwc)
815 struct device *dev = dwc->dev;
816 struct device_node *node = dev->of_node;
820 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
821 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
823 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
824 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
827 if (IS_ERR(dwc->usb2_phy)) {
828 ret = PTR_ERR(dwc->usb2_phy);
829 if (ret == -ENXIO || ret == -ENODEV) {
830 dwc->usb2_phy = NULL;
831 } else if (ret == -EPROBE_DEFER) {
834 dev_err(dev, "no usb2 phy configured\n");
839 if (IS_ERR(dwc->usb3_phy)) {
840 ret = PTR_ERR(dwc->usb3_phy);
841 if (ret == -ENXIO || ret == -ENODEV) {
842 dwc->usb3_phy = NULL;
843 } else if (ret == -EPROBE_DEFER) {
846 dev_err(dev, "no usb3 phy configured\n");
851 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
852 if (IS_ERR(dwc->usb2_generic_phy)) {
853 ret = PTR_ERR(dwc->usb2_generic_phy);
854 if (ret == -ENOSYS || ret == -ENODEV) {
855 dwc->usb2_generic_phy = NULL;
856 } else if (ret == -EPROBE_DEFER) {
859 dev_err(dev, "no usb2 phy configured\n");
864 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
865 if (IS_ERR(dwc->usb3_generic_phy)) {
866 ret = PTR_ERR(dwc->usb3_generic_phy);
867 if (ret == -ENOSYS || ret == -ENODEV) {
868 dwc->usb3_generic_phy = NULL;
869 } else if (ret == -EPROBE_DEFER) {
872 dev_err(dev, "no usb3 phy configured\n");
880 static int dwc3_core_init_mode(struct dwc3 *dwc)
882 struct device *dev = dwc->dev;
884 switch (dwc->dr_mode) {
885 case USB_DR_MODE_PERIPHERAL:
886 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
888 case USB_DR_MODE_HOST:
889 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
891 case USB_DR_MODE_OTG:
892 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
895 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
902 static void dwc3_core_exit_mode(struct dwc3 *dwc)
904 switch (dwc->dr_mode) {
905 case USB_DR_MODE_PERIPHERAL:
906 dwc3_gadget_exit(dwc);
908 case USB_DR_MODE_HOST:
911 case USB_DR_MODE_OTG:
913 dwc3_gadget_exit(dwc);
921 /* XHCI reset, resets other CORE registers as well, re-init those */
922 void dwc3_post_host_reset_core_init(struct dwc3 *dwc)
925 dwc3_gadget_restart(dwc);
928 static void (*notify_event)(struct dwc3 *, unsigned, unsigned);
929 void dwc3_set_notifier(void (*notify)(struct dwc3 *, unsigned, unsigned))
931 notify_event = notify;
933 EXPORT_SYMBOL(dwc3_set_notifier);
935 int dwc3_notify_event(struct dwc3 *dwc, unsigned event, unsigned value)
939 if (dwc->notify_event)
940 dwc->notify_event(dwc, event, value);
946 EXPORT_SYMBOL(dwc3_notify_event);
948 int dwc3_core_pre_init(struct dwc3 *dwc)
952 dwc3_cache_hwparams(dwc);
954 ret = dwc3_phy_setup(dwc);
958 if (!dwc->ev_buffs) {
959 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
961 dev_err(dwc->dev, "failed to allocate event buffers\n");
967 ret = dwc3_core_init(dwc);
969 dev_err(dwc->dev, "failed to initialize core\n");
973 ret = phy_power_on(dwc->usb2_generic_phy);
977 ret = phy_power_on(dwc->usb3_generic_phy);
981 ret = dwc3_event_buffers_setup(dwc);
983 dev_err(dwc->dev, "failed to setup event buffers\n");
987 ret = dwc3_core_init_mode(dwc);
989 dev_err(dwc->dev, "failed to set mode with dwc3 core\n");
996 dwc3_event_buffers_cleanup(dwc);
998 phy_power_off(dwc->usb3_generic_phy);
1000 phy_power_off(dwc->usb2_generic_phy);
1002 dwc3_core_exit(dwc);
1004 dwc3_free_event_buffers(dwc);
1006 dwc3_ulpi_exit(dwc);
1011 #define DWC3_ALIGN_MASK (16 - 1)
1013 /* check whether the core supports IMOD */
1014 bool dwc3_has_imod(struct dwc3 *dwc)
1016 return ((dwc3_is_usb3(dwc) &&
1017 dwc->revision >= DWC3_REVISION_300A) ||
1018 (dwc3_is_usb31(dwc) &&
1019 dwc->revision >= DWC3_USB31_REVISION_120A));
1022 static int dwc3_probe(struct platform_device *pdev)
1024 struct device *dev = &pdev->dev;
1025 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
1026 struct resource *res;
1028 u8 lpm_nyet_threshold;
1039 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
1043 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
1047 dwc->notify_event = notify_event;
1048 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1050 dev_err(dev, "missing IRQ\n");
1053 dwc->xhci_resources[1].start = res->start;
1054 dwc->xhci_resources[1].end = res->end;
1055 dwc->xhci_resources[1].flags = res->flags;
1056 dwc->xhci_resources[1].name = res->name;
1058 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1060 /* will be enabled in dwc3_msm_resume() */
1061 irq_set_status_flags(irq, IRQ_NOAUTOEN);
1062 ret = devm_request_irq(dev, irq, dwc3_interrupt, IRQF_SHARED, "dwc3",
1065 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1072 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1074 dev_err(dev, "missing memory resource\n");
1078 dwc->reg_phys = res->start;
1079 dwc->xhci_resources[0].start = res->start;
1080 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1082 dwc->xhci_resources[0].flags = res->flags;
1083 dwc->xhci_resources[0].name = res->name;
1085 res->start += DWC3_GLOBALS_REGS_START;
1088 * Request memory region but exclude xHCI regs,
1089 * since it will be requested by the xhci-plat driver.
1091 regs = devm_ioremap_resource(dev, res);
1093 ret = PTR_ERR(regs);
1098 dwc->regs_size = resource_size(res);
1100 /* default to highest possible threshold */
1101 lpm_nyet_threshold = 0xf;
1103 /* default to -3.5dB de-emphasis */
1107 * default to assert utmi_sleep_n and use maximum allowed HIRD
1108 * threshold value of 0b1100
1110 hird_threshold = 12;
1112 dwc->maximum_speed = usb_get_maximum_speed(dev);
1113 dwc->max_hw_supp_speed = dwc->maximum_speed;
1114 dwc->dr_mode = usb_get_dr_mode(dev);
1116 dwc->has_lpm_erratum = device_property_read_bool(dev,
1117 "snps,has-lpm-erratum");
1118 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1119 &lpm_nyet_threshold);
1120 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1121 "snps,is-utmi-l1-suspend");
1122 device_property_read_u8(dev, "snps,hird-threshold",
1124 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1125 "snps,usb3_lpm_capable");
1127 dwc->needs_fifo_resize = device_property_read_bool(dev,
1130 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1131 "snps,disable_scramble_quirk");
1132 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1133 "snps,u2exit_lfps_quirk");
1134 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1135 "snps,u2ss_inp3_quirk");
1136 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1137 "snps,req_p1p2p3_quirk");
1138 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1139 "snps,del_p1p2p3_quirk");
1140 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1141 "snps,del_phy_power_chg_quirk");
1142 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1143 "snps,lfps_filter_quirk");
1144 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1145 "snps,rx_detect_poll_quirk");
1146 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1147 "snps,dis_u3_susphy_quirk");
1148 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1149 "snps,dis_u2_susphy_quirk");
1150 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1151 "snps,dis_enblslpm_quirk");
1153 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1154 "snps,tx_de_emphasis_quirk");
1155 device_property_read_u8(dev, "snps,tx_de_emphasis",
1157 device_property_read_string(dev, "snps,hsphy_interface",
1158 &dwc->hsphy_interface);
1159 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1162 dwc->nominal_elastic_buffer = device_property_read_bool(dev,
1163 "snps,nominal-elastic-buffer");
1164 dwc->usb3_u1u2_disable = device_property_read_bool(dev,
1165 "snps,usb3-u1u2-disable");
1166 dwc->disable_clk_gating = device_property_read_bool(dev,
1167 "snps,disable-clk-gating");
1168 dwc->enable_bus_suspend = device_property_read_bool(dev,
1169 "snps,bus-suspend-enable");
1171 dwc->num_normal_event_buffers = 1;
1172 ret = device_property_read_u32(dev,
1173 "snps,num-normal-evt-buffs", &num_evt_buffs);
1175 dwc->num_normal_event_buffers = num_evt_buffs;
1177 ret = device_property_read_u32(dev,
1178 "snps,num-gsi-evt-buffs", &dwc->num_gsi_event_buffers);
1180 if (dwc->enable_bus_suspend) {
1181 pm_runtime_set_autosuspend_delay(dev, 500);
1182 pm_runtime_use_autosuspend(dev);
1186 dwc->maximum_speed = pdata->maximum_speed;
1187 dwc->max_hw_supp_speed = dwc->maximum_speed;
1188 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
1189 if (pdata->lpm_nyet_threshold)
1190 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
1191 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
1192 if (pdata->hird_threshold)
1193 hird_threshold = pdata->hird_threshold;
1195 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
1196 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
1197 dwc->dr_mode = pdata->dr_mode;
1199 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
1200 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
1201 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
1202 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
1203 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
1204 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
1205 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
1206 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
1207 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
1208 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
1209 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
1211 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
1212 if (pdata->tx_de_emphasis)
1213 tx_de_emphasis = pdata->tx_de_emphasis;
1215 dwc->hsphy_interface = pdata->hsphy_interface;
1216 fladj = pdata->fladj_value;
1219 /* default to superspeed if no maximum_speed passed */
1220 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
1221 dwc->max_hw_supp_speed = dwc->maximum_speed = USB_SPEED_SUPER;
1223 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1224 dwc->tx_de_emphasis = tx_de_emphasis;
1226 dwc->hird_threshold = hird_threshold
1227 | (dwc->is_utmi_l1_suspend << 4);
1229 init_waitqueue_head(&dwc->wait_linkstate);
1230 platform_set_drvdata(pdev, dwc);
1231 ret = dwc3_core_get_phy(dwc);
1235 spin_lock_init(&dwc->lock);
1237 dev->dma_mask = dev->parent->dma_mask;
1238 dev->dma_parms = dev->parent->dma_parms;
1239 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1241 dwc->dwc_wq = alloc_ordered_workqueue("dwc_wq", WQ_HIGHPRI);
1243 pr_err("%s: Unable to create workqueue dwc_wq\n", __func__);
1247 INIT_WORK(&dwc->bh_work, dwc3_bh_work);
1249 pm_runtime_no_callbacks(dev);
1250 pm_runtime_set_active(dev);
1251 pm_runtime_enable(dev);
1252 pm_runtime_forbid(dev);
1254 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1255 dwc->dr_mode = USB_DR_MODE_HOST;
1256 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1257 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1259 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) {
1260 dwc->dr_mode = USB_DR_MODE_OTG;
1264 /* Adjust Frame Length */
1265 dwc3_frame_length_adjustment(dwc, fladj);
1267 /* Hardcode number of eps */
1268 dwc->num_in_eps = 16;
1269 dwc->num_out_eps = 16;
1271 if (dwc->dr_mode == USB_DR_MODE_OTG ||
1272 dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
1273 ret = dwc3_gadget_init(dwc);
1275 dev_err(dev, "failed to initialize gadget\n");
1280 if (dwc->dr_mode == USB_DR_MODE_OTG ||
1281 dwc->dr_mode == USB_DR_MODE_HOST) {
1282 ret = dwc3_host_init(dwc);
1284 dev_err(dev, "failed to initialize host\n");
1289 ret = dwc3_debugfs_init(dwc);
1291 dev_err(dev, "failed to initialize debugfs\n");
1295 pm_runtime_allow(dev);
1300 if (dwc->dr_mode == USB_DR_MODE_OTG ||
1301 dwc->dr_mode == USB_DR_MODE_HOST)
1302 dwc3_host_exit(dwc);
1304 if (dwc->dr_mode == USB_DR_MODE_OTG ||
1305 dwc->dr_mode == USB_DR_MODE_PERIPHERAL)
1306 dwc3_gadget_exit(dwc);
1309 * restore res->start back to its original value so that, in case the
1310 * probe is deferred, we don't end up getting error in request the
1311 * memory region the next time probe is called.
1313 res->start -= DWC3_GLOBALS_REGS_START;
1314 destroy_workqueue(dwc->dwc_wq);
1319 static int dwc3_remove(struct platform_device *pdev)
1321 struct dwc3 *dwc = platform_get_drvdata(pdev);
1322 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1325 * restore res->start back to its original value so that, in case the
1326 * probe is deferred, we don't end up getting error in request the
1327 * memory region the next time probe is called.
1329 res->start -= DWC3_GLOBALS_REGS_START;
1331 dwc3_debugfs_exit(dwc);
1332 dwc3_core_exit_mode(dwc);
1333 dwc3_event_buffers_cleanup(dwc);
1334 dwc3_free_event_buffers(dwc);
1336 phy_power_off(dwc->usb2_generic_phy);
1337 phy_power_off(dwc->usb3_generic_phy);
1339 dwc3_core_exit(dwc);
1340 dwc3_ulpi_exit(dwc);
1342 destroy_workqueue(dwc->dwc_wq);
1344 pm_runtime_put_sync(&pdev->dev);
1345 pm_runtime_disable(&pdev->dev);
1350 #ifdef CONFIG_PM_SLEEP
1351 static int dwc3_suspend(struct device *dev)
1353 struct dwc3 *dwc = dev_get_drvdata(dev);
1354 unsigned long flags;
1356 /* Check if platform glue driver handling PM, if not then handle here */
1357 if (!dwc3_notify_event(dwc, DWC3_CORE_PM_SUSPEND_EVENT, 0))
1360 spin_lock_irqsave(&dwc->lock, flags);
1362 switch (dwc->dr_mode) {
1363 case USB_DR_MODE_PERIPHERAL:
1364 case USB_DR_MODE_OTG:
1365 dwc3_gadget_suspend(dwc);
1367 case USB_DR_MODE_HOST:
1369 dwc3_event_buffers_cleanup(dwc);
1373 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1374 spin_unlock_irqrestore(&dwc->lock, flags);
1376 usb_phy_shutdown(dwc->usb3_phy);
1377 usb_phy_shutdown(dwc->usb2_phy);
1378 phy_exit(dwc->usb2_generic_phy);
1379 phy_exit(dwc->usb3_generic_phy);
1381 pinctrl_pm_select_sleep_state(dev);
1386 static int dwc3_resume(struct device *dev)
1388 struct dwc3 *dwc = dev_get_drvdata(dev);
1389 unsigned long flags;
1392 /* Check if platform glue driver handling PM, if not then handle here */
1393 if (!dwc3_notify_event(dwc, DWC3_CORE_PM_RESUME_EVENT, 0))
1396 pinctrl_pm_select_default_state(dev);
1398 usb_phy_init(dwc->usb3_phy);
1399 usb_phy_init(dwc->usb2_phy);
1400 ret = phy_init(dwc->usb2_generic_phy);
1404 ret = phy_init(dwc->usb3_generic_phy);
1406 goto err_usb2phy_init;
1408 spin_lock_irqsave(&dwc->lock, flags);
1410 dwc3_event_buffers_setup(dwc);
1411 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1413 switch (dwc->dr_mode) {
1414 case USB_DR_MODE_PERIPHERAL:
1415 case USB_DR_MODE_OTG:
1416 dwc3_gadget_resume(dwc);
1418 case USB_DR_MODE_HOST:
1424 spin_unlock_irqrestore(&dwc->lock, flags);
1426 pm_runtime_disable(dev);
1427 pm_runtime_set_active(dev);
1428 pm_runtime_enable(dev);
1433 phy_exit(dwc->usb2_generic_phy);
1438 static int dwc3_pm_restore(struct device *dev)
1441 * Set the core as runtime active to prevent the runtime
1442 * PM ops being called before the PM restore is completed.
1444 pm_runtime_disable(dev);
1445 pm_runtime_set_active(dev);
1446 pm_runtime_enable(dev);
1451 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1452 .suspend = dwc3_suspend,
1453 .resume = dwc3_resume,
1454 .freeze = dwc3_suspend,
1455 .thaw = dwc3_pm_restore,
1456 .poweroff = dwc3_suspend,
1457 .restore = dwc3_pm_restore,
1460 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
1462 #define DWC3_PM_OPS NULL
1466 static const struct of_device_id of_dwc3_match[] = {
1468 .compatible = "snps,dwc3"
1471 .compatible = "synopsys,dwc3"
1475 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1480 #define ACPI_ID_INTEL_BSW "808622B7"
1482 static const struct acpi_device_id dwc3_acpi_match[] = {
1483 { ACPI_ID_INTEL_BSW, 0 },
1486 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1489 static struct platform_driver dwc3_driver = {
1490 .probe = dwc3_probe,
1491 .remove = dwc3_remove,
1494 .of_match_table = of_match_ptr(of_dwc3_match),
1495 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1500 module_platform_driver(dwc3_driver);
1502 MODULE_ALIAS("platform:dwc3");
1503 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1504 MODULE_LICENSE("GPL v2");
1505 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");