drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38 #include <linux/irq.h>
  39
  40 #include <linux/usb/ch9.h>
  41 #include <linux/usb/gadget.h>
  42 #include <linux/usb/of.h>
  43 #include <linux/usb/otg.h>
  44
  45 #include "platform_data.h"
  46 #include "core.h"
  47 #include "gadget.h"
  48 #include "io.h"
  49
  50 #include "debug.h"
  51
  52 /* -------------------------------------------------------------------------- */
  53
  54 void dwc3_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
  55 {
  56         u32                     reg;
  57
  58         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  59
  60         if (suspend)
  61                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  62         else
  63                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  64
  65         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  66 }
  67
  68 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  69 {
  70         u32 reg;
  71
  72         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  73         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  74         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  75         /*
  76          * Set this bit so that device attempts three more times at SS, even
  77          * if it failed previously to operate in SS mode.
  78          */
  79         reg |= DWC3_GCTL_U2RSTECN;
  80         reg &= ~(DWC3_GCTL_SOFITPSYNC);
  81         reg &= ~(DWC3_GCTL_PWRDNSCALEMASK);
  82         reg |= DWC3_GCTL_PWRDNSCALE(2);
  83         reg |= DWC3_GCTL_U2EXIT_LFPS;
  84         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  85
  86         if (mode == DWC3_GCTL_PRTCAP_OTG || mode == DWC3_GCTL_PRTCAP_HOST) {
  87                 /*
  88                  * Allow ITP generated off of ref clk based counter instead
  89                  * of UTMI/ULPI clk based counter, when superspeed only is
  90                  * active so that UTMI/ULPI PHY can be suspened.
  91                  *
  92                  * Starting with revision 2.50A, GFLADJ_REFCLK_LPM_SEL is used
  93                  * instead.
  94                  */
  95                 if (dwc->revision < DWC3_REVISION_250A) {
  96                         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  97                         reg |= DWC3_GCTL_SOFITPSYNC;
  98                         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  99                 } else {
 100                         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 101                         reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
 102                         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 103                 }
 104         }
 105 }
 106
 107 /**
 108  * Peforms initialization of HS and SS PHYs.
 109  * If used as a part of POR or init sequence it is recommended
 110  * that we should perform hard reset of the PHYs prior to invoking
 111  * this function.
 112  * @dwc: pointer to our context structure
 113 */
 114 static int dwc3_init_usb_phys(struct dwc3 *dwc)
 115 {
 116         int             ret;
 117
 118         /* Bring up PHYs */
 119         ret = usb_phy_init(dwc->usb2_phy);
 120         if (ret) {
 121                 pr_err("%s: usb_phy_init(dwc->usb2_phy) returned %d\n",
 122                                 __func__, ret);
 123                 return ret;
 124         }
 125
 126         if (dwc->maximum_speed == USB_SPEED_HIGH)
 127                 goto generic_phy_init;
 128
 129         ret = usb_phy_init(dwc->usb3_phy);
 130         if (ret == -EBUSY) {
 131                 /*
 132                  * Setting Max speed as high when USB3 PHY initialiation
 133                  * is failing and USB superspeed can't be supported.
 134                  */
 135                 dwc->maximum_speed = USB_SPEED_HIGH;
 136         } else if (ret) {
 137                 pr_err("%s: usb_phy_init(dwc->usb3_phy) returned %d\n",
 138                                 __func__, ret);
 139                 return ret;
 140         }
 141
 142 generic_phy_init:
 143         ret = phy_init(dwc->usb2_generic_phy);
 144         if (ret < 0)
 145                 return ret;
 146
 147         ret = phy_init(dwc->usb3_generic_phy);
 148         if (ret < 0) {
 149                 phy_exit(dwc->usb2_generic_phy);
 150                 return ret;
 151         }
 152
 153         return 0;
 154 }
 155
 156 /**
 157  * dwc3_core_reset - Issues core soft reset and PHY reset
 158  * @dwc: pointer to our context structure
 159  */
 160 static int dwc3_core_reset(struct dwc3 *dwc)
 161 {
 162         int             ret;
 163         u32     reg;
 164
 165         /* Reset PHYs */
 166         usb_phy_reset(dwc->usb2_phy);
 167
 168         if (dwc->maximum_speed == USB_SPEED_SUPER)
 169                 usb_phy_reset(dwc->usb3_phy);
 170
 171         /* Initialize PHYs */
 172         ret = dwc3_init_usb_phys(dwc);
 173         if (ret) {
 174                 pr_err("%s: dwc3_init_phys returned %d\n",
 175                                 __func__, ret);
 176                 return ret;
 177         }
 178
 179         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 180         reg &= ~DWC3_GUSB3PIPECTL_DELAYP1TRANS;
 181
 182         /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
 183         if (dwc->revision <= DWC3_REVISION_310A)
 184                 reg |= DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX;
 185
 186         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 187
 188         dwc3_notify_event(dwc, DWC3_CONTROLLER_RESET_EVENT, 0);
 189
 190         dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT, 0);
 191
 192         return 0;
 193 }
 194
 195 /**
 196  * dwc3_soft_reset - Issue soft reset
 197  * @dwc: Pointer to our controller context structure
 198  */
 199 static int dwc3_soft_reset(struct dwc3 *dwc)
 200 {
 201         unsigned long timeout;
 202         u32 reg;
 203
 204         timeout = jiffies + msecs_to_jiffies(500);
 205         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 206         do {
 207                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 208                 if (!(reg & DWC3_DCTL_CSFTRST))
 209                         break;
 210
 211                 if (time_after(jiffies, timeout)) {
 212                         dev_err(dwc->dev, "Reset Timed Out\n");
 213                         return -ETIMEDOUT;
 214                 }
 215
 216                 cpu_relax();
 217         } while (true);
 218
 219         return 0;
 220 }
 221
 222 /*
 223  * dwc3_frame_length_adjustment - Adjusts frame length if required
 224  * @dwc3: Pointer to our controller context structure
 225  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 226  */
 227 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 228 {
 229         u32 reg;
 230         u32 dft;
 231
 232         if (dwc->revision < DWC3_REVISION_250A)
 233                 return;
 234
 235         if (fladj == 0)
 236                 return;
 237
 238         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 239         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 240         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
 241             "request value same as default, ignoring\n")) {
 242                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 243                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 244                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 245         }
 246 }
 247
 248 /**
 249  * dwc3_free_one_event_buffer - Frees one event buffer
 250  * @dwc: Pointer to our controller context structure
 251  * @evt: Pointer to event buffer to be freed
 252  */
 253 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 254                 struct dwc3_event_buffer *evt)
 255 {
 256         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 257 }
 258
 259 /**
 260  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 261  * @dwc: Pointer to our controller context structure
 262  * @length: size of the event buffer
 263  *
 264  * Returns a pointer to the allocated event buffer structure on success
 265  * otherwise ERR_PTR(errno).
 266  */
 267 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 268                 unsigned length, enum event_buf_type type)
 269 {
 270         struct dwc3_event_buffer        *evt;
 271
 272         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 273         if (!evt)
 274                 return ERR_PTR(-ENOMEM);
 275
 276         evt->dwc        = dwc;
 277         evt->length     = length;
 278         evt->type       = type;
 279         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 280                         &evt->dma, GFP_KERNEL);
 281         if (!evt->buf)
 282                 return ERR_PTR(-ENOMEM);
 283
 284         return evt;
 285 }
 286
 287 /**
 288  * dwc3_free_event_buffers - frees all allocated event buffers
 289  * @dwc: Pointer to our controller context structure
 290  */
 291 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 292 {
 293         struct dwc3_event_buffer        *evt;
 294         int i;
 295
 296         for (i = 0; i < dwc->num_event_buffers; i++) {
 297                 evt = dwc->ev_buffs[i];
 298                 if (evt)
 299                         dwc3_free_one_event_buffer(dwc, evt);
 300         }
 301 }
 302
 303 /**
 304  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 305  * @dwc: pointer to our controller context structure
 306  * @length: size of event buffer
 307  *
 308  * Returns 0 on success otherwise negative errno. In the error case, dwc
 309  * may contain some buffers allocated but not all which were requested.
 310  */
 311 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 312 {
 313         int     i;
 314         int     j = 0;
 315
 316         dwc->num_event_buffers = dwc->num_normal_event_buffers +
 317                 dwc->num_gsi_event_buffers;
 318
 319         dwc->ev_buffs = devm_kzalloc(dwc->dev,
 320                         sizeof(*dwc->ev_buffs) * dwc->num_event_buffers,
 321                         GFP_KERNEL);
 322         if (!dwc->ev_buffs)
 323                 return -ENOMEM;
 324
 325         for (i = 0; i < dwc->num_normal_event_buffers; i++) {
 326                 struct dwc3_event_buffer        *evt;
 327
 328                 evt = dwc3_alloc_one_event_buffer(dwc, length,
 329                                 EVT_BUF_TYPE_NORMAL);
 330                 if (IS_ERR(evt)) {
 331                         dev_err(dwc->dev, "can't allocate event buffer\n");
 332                         return PTR_ERR(evt);
 333                 }
 334                 dwc->ev_buffs[j++] = evt;
 335         }
 336
 337         for (i = 0; i < dwc->num_gsi_event_buffers; i++) {
 338                 struct dwc3_event_buffer        *evt;
 339
 340                 evt = dwc3_alloc_one_event_buffer(dwc, length,
 341                                 EVT_BUF_TYPE_GSI);
 342                 if (IS_ERR(evt)) {
 343                         dev_err(dwc->dev, "can't allocate event buffer\n");
 344                         return PTR_ERR(evt);
 345                 }
 346                 dwc->ev_buffs[j++] = evt;
 347         }
 348
 349         return 0;
 350 }
 351
 352 /**
 353  * dwc3_event_buffers_setup - setup our allocated event buffers
 354  * @dwc: pointer to our controller context structure
 355  *
 356  * Returns 0 on success otherwise negative errno.
 357  */
 358 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 359 {
 360         struct dwc3_event_buffer        *evt;
 361         int                             n;
 362
 363         for (n = 0; n < dwc->num_event_buffers; n++) {
 364                 evt = dwc->ev_buffs[n];
 365                 dev_dbg(dwc->dev, "Event buf %pK dma %08llx length %d\n",
 366                                 evt->buf, (unsigned long long) evt->dma,
 367                                 evt->length);
 368
 369                 memset(evt->buf, 0, evt->length);
 370
 371                 evt->lpos = 0;
 372
 373                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 374                                 lower_32_bits(evt->dma));
 375
 376                 if (evt->type == EVT_BUF_TYPE_NORMAL) {
 377                         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 378                                         upper_32_bits(evt->dma));
 379                         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 380                                         DWC3_GEVNTSIZ_SIZE(evt->length));
 381                 } else {
 382                         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 383                                 DWC3_GEVNTADRHI_EVNTADRHI_GSI_EN(
 384                                         DWC3_GEVENT_TYPE_GSI) |
 385                                 DWC3_GEVNTADRHI_EVNTADRHI_GSI_IDX(n));
 386
 387                         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 388                                 DWC3_GEVNTCOUNT_EVNTINTRPTMASK |
 389                                 ((evt->length) & 0xffff));
 390                 }
 391
 392                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 393         }
 394
 395         return 0;
 396 }
 397
 398 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 399 {
 400         struct dwc3_event_buffer        *evt;
 401         int                             n;
 402
 403         for (n = 0; n < dwc->num_event_buffers; n++) {
 404                 evt = dwc->ev_buffs[n];
 405
 406                 evt->lpos = 0;
 407
 408                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 409                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 410                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 411                                 | DWC3_GEVNTSIZ_SIZE(0));
 412                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 413         }
 414 }
 415
 416 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 417 {
 418         if (!dwc->has_hibernation)
 419                 return 0;
 420
 421         if (!dwc->nr_scratch)
 422                 return 0;
 423
 424         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 425                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 426         if (!dwc->scratchbuf)
 427                 return -ENOMEM;
 428
 429         return 0;
 430 }
 431
 432 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 433 {
 434         dma_addr_t scratch_addr;
 435         u32 param;
 436         int ret;
 437
 438         if (!dwc->has_hibernation)
 439                 return 0;
 440
 441         if (!dwc->nr_scratch)
 442                 return 0;
 443
 444          /* should never fall here */
 445         if (!WARN_ON(dwc->scratchbuf))
 446                 return 0;
 447
 448         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 449                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 450                         DMA_BIDIRECTIONAL);
 451         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 452                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 453                 ret = -EFAULT;
 454                 goto err0;
 455         }
 456
 457         dwc->scratch_addr = scratch_addr;
 458
 459         param = lower_32_bits(scratch_addr);
 460
 461         ret = dwc3_send_gadget_generic_command(dwc,
 462                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 463         if (ret < 0)
 464                 goto err1;
 465
 466         param = upper_32_bits(scratch_addr);
 467
 468         ret = dwc3_send_gadget_generic_command(dwc,
 469                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 470         if (ret < 0)
 471                 goto err1;
 472
 473         return 0;
 474
 475 err1:
 476         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 477                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 478
 479 err0:
 480         return ret;
 481 }
 482
 483 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 484 {
 485         if (!dwc->has_hibernation)
 486                 return;
 487
 488         if (!dwc->nr_scratch)
 489                 return;
 490
 491          /* should never fall here */
 492         if (!WARN_ON(dwc->scratchbuf))
 493                 return;
 494
 495         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 496                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 497         kfree(dwc->scratchbuf);
 498 }
 499
 500 static void dwc3_core_num_eps(struct dwc3 *dwc)
 501 {
 502         struct dwc3_hwparams    *parms = &dwc->hwparams;
 503
 504         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 505         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 506
 507         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 508                         dwc->num_in_eps, dwc->num_out_eps);
 509 }
 510
 511 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 512 {
 513         struct dwc3_hwparams    *parms = &dwc->hwparams;
 514
 515         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 516         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 517         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 518         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 519         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 520         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 521         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 522         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 523         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 524 }
 525
 526 /**
 527  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 528  * @dwc: Pointer to our controller context structure
 529  *
 530  * Returns 0 on success. The USB PHY interfaces are configured but not
 531  * initialized. The PHY interfaces and the PHYs get initialized together with
 532  * the core in dwc3_core_init.
 533  */
 534 static int dwc3_phy_setup(struct dwc3 *dwc)
 535 {
 536         u32 reg;
 537         int ret;
 538
 539         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 540
 541         /*
 542          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 543          * to '0' during coreConsultant configuration. So default value
 544          * will be '0' when the core is reset. Application needs to set it
 545          * to '1' after the core initialization is completed.
 546          */
 547         if (dwc->revision > DWC3_REVISION_194A)
 548                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 549
 550         if (dwc->u2ss_inp3_quirk)
 551                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 552
 553         if (dwc->req_p1p2p3_quirk)
 554                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 555
 556         if (dwc->del_p1p2p3_quirk)
 557                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 558
 559         if (dwc->del_phy_power_chg_quirk)
 560                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 561
 562         if (dwc->lfps_filter_quirk)
 563                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 564
 565         if (dwc->rx_detect_poll_quirk)
 566                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 567
 568         if (dwc->tx_de_emphasis_quirk)
 569                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 570
 571         if (dwc->dis_u3_susphy_quirk)
 572                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 573
 574         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 575
 576         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 577
 578         /* Select the HS PHY interface */
 579         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 580         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 581                 if (dwc->hsphy_interface &&
 582                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 583                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 584                         break;
 585                 } else if (dwc->hsphy_interface &&
 586                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 587                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 588                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 589                 } else {
 590                         /* Relying on default value. */
 591                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 592                                 break;
 593                 }
 594                 /* FALLTHROUGH */
 595         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 596                 /* Making sure the interface and PHY are operational */
 597                 ret = dwc3_soft_reset(dwc);
 598                 if (ret)
 599                         return ret;
 600
 601                 udelay(1);
 602
 603                 ret = dwc3_ulpi_init(dwc);
 604                 if (ret)
 605                         return ret;
 606                 /* FALLTHROUGH */
 607         default:
 608                 break;
 609         }
 610
 611         /*
 612          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 613          * '0' during coreConsultant configuration. So default value will
 614          * be '0' when the core is reset. Application needs to set it to
 615          * '1' after the core initialization is completed.
 616          */
 617         if (dwc->revision > DWC3_REVISION_194A)
 618                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 619
 620         if (dwc->dis_u2_susphy_quirk)
 621                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 622
 623         if (dwc->dis_enblslpm_quirk)
 624                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 625
 626         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 627
 628         return 0;
 629 }
 630
 631 /**
 632  * dwc3_core_init - Low-level initialization of DWC3 Core
 633  * @dwc: Pointer to our controller context structure
 634  *
 635  * Returns 0 on success otherwise negative errno.
 636  */
 637 int dwc3_core_init(struct dwc3 *dwc)
 638 {
 639         u32                     hwparams4 = dwc->hwparams.hwparams4;
 640         u32                     reg;
 641         int                     ret;
 642
 643         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 644         /* This should read as U3 followed by revision number */
 645         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 646                 /* Detected DWC_usb3 IP */
 647                 dwc->revision = reg;
 648         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 649                 /* Detected DWC_usb31 IP */
 650                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 651                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 652         } else {
 653                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 654                 ret = -ENODEV;
 655                 goto err0;
 656         }
 657
 658         /*
 659          * Write Linux Version Code to our GUID register so it's easy to figure
 660          * out which kernel version a bug was found.
 661          */
 662         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 663
 664         /* Handle USB2.0-only core configuration */
 665         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 666                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 667                 if (dwc->max_hw_supp_speed == USB_SPEED_SUPER) {
 668                         dwc->max_hw_supp_speed = USB_SPEED_HIGH;
 669                         dwc->maximum_speed = dwc->max_hw_supp_speed;
 670                 }
 671         }
 672
 673         /*
 674          * Workaround for STAR 9000961433 which affects only version
 675          * 3.00a of the DWC_usb3 core. This prevents the controller
 676          * interrupt from being masked while handling events. IMOD
 677          * allows us to work around this issue. Enable it for the
 678          * affected version.
 679          */
 680          if (!dwc->imod_interval && (dwc->revision == DWC3_REVISION_300A))
 681                 dwc->imod_interval = 1;
 682
 683         ret = dwc3_core_reset(dwc);
 684         if (ret)
 685                 goto err0;
 686
 687         /* issue device SoftReset too */
 688         ret = dwc3_soft_reset(dwc);
 689         if (ret)
 690                 goto err0;
 691
 692         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 693         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 694
 695         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 696         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 697                 /**
 698                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 699                  * issue which would cause xHCI compliance tests to fail.
 700                  *
 701                  * Because of that we cannot enable clock gating on such
 702                  * configurations.
 703                  *
 704                  * Refers to:
 705                  *
 706                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 707                  * SOF/ITP Mode Used
 708                  */
 709                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 710                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 711                                 (dwc->revision >= DWC3_REVISION_210A &&
 712                                 dwc->revision <= DWC3_REVISION_250A))
 713                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 714                 else
 715                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 716                 break;
 717         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 718                 /* enable hibernation here */
 719                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 720
 721                 /*
 722                  * REVISIT Enabling this bit so that host-mode hibernation
 723                  * will work. Device-mode hibernation is not yet implemented.
 724                  */
 725                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 726                 break;
 727         default:
 728                 dev_dbg(dwc->dev, "No power optimization available\n");
 729         }
 730
 731         /* check if current dwc3 is on simulation board */
 732         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 733                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 734                 dwc->is_fpga = true;
 735         }
 736
 737         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 738                         "disable_scramble cannot be used on non-FPGA builds\n");
 739
 740         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 741                 reg |= DWC3_GCTL_DISSCRAMBLE;
 742         else
 743                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 744
 745         if (dwc->u2exit_lfps_quirk)
 746                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 747
 748         /*
 749          * WORKAROUND: DWC3 revisions <1.90a have a bug
 750          * where the device can fail to connect at SuperSpeed
 751          * and falls back to high-speed mode which causes
 752          * the device to enter a Connect/Disconnect loop
 753          */
 754         if (dwc->revision < DWC3_REVISION_190A)
 755                 reg |= DWC3_GCTL_U2RSTECN;
 756
 757         dwc3_core_num_eps(dwc);
 758
 759         /*
 760          * Disable clock gating to work around a known HW bug that causes the
 761          * internal RAM clock to get stuck when entering low power modes.
 762          */
 763         if (dwc->disable_clk_gating) {
 764                 dev_dbg(dwc->dev, "Disabling controller clock gating.\n");
 765                 reg |= DWC3_GCTL_DSBLCLKGTNG;
 766         }
 767
 768         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 769
 770         ret = dwc3_alloc_scratch_buffers(dwc);
 771         if (ret)
 772                 goto err1;
 773
 774         ret = dwc3_setup_scratch_buffers(dwc);
 775         if (ret)
 776                 goto err2;
 777
 778         /*
 779          * clear Elastic buffer mode in GUSBPIPE_CTRL(0) register, otherwise
 780          * it results in high link errors and could cause SS mode transfer
 781          * failure.
 782          */
 783         if (!dwc->nominal_elastic_buffer) {
 784                 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 785                 reg &= ~DWC3_GUSB3PIPECTL_ELASTIC_BUF_MODE;
 786                 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 787         }
 788
 789         return 0;
 790
 791 err2:
 792         dwc3_free_scratch_buffers(dwc);
 793
 794 err1:
 795         usb_phy_shutdown(dwc->usb2_phy);
 796         usb_phy_shutdown(dwc->usb3_phy);
 797         phy_exit(dwc->usb2_generic_phy);
 798         phy_exit(dwc->usb3_generic_phy);
 799
 800 err0:
 801         return ret;
 802 }
 803
 804 static void dwc3_core_exit(struct dwc3 *dwc)
 805 {
 806         dwc3_free_scratch_buffers(dwc);
 807         usb_phy_shutdown(dwc->usb2_phy);
 808         usb_phy_shutdown(dwc->usb3_phy);
 809         phy_exit(dwc->usb2_generic_phy);
 810         phy_exit(dwc->usb3_generic_phy);
 811 }
 812
 813 static int dwc3_core_get_phy(struct dwc3 *dwc)
 814 {
 815         struct device           *dev = dwc->dev;
 816         struct device_node      *node = dev->of_node;
 817         int ret;
 818
 819         if (node) {
 820                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 821                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 822         } else {
 823                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 824                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 825         }
 826
 827         if (IS_ERR(dwc->usb2_phy)) {
 828                 ret = PTR_ERR(dwc->usb2_phy);
 829                 if (ret == -ENXIO || ret == -ENODEV) {
 830                         dwc->usb2_phy = NULL;
 831                 } else if (ret == -EPROBE_DEFER) {
 832                         return ret;
 833                 } else {
 834                         dev_err(dev, "no usb2 phy configured\n");
 835                         return ret;
 836                 }
 837         }
 838
 839         if (IS_ERR(dwc->usb3_phy)) {
 840                 ret = PTR_ERR(dwc->usb3_phy);
 841                 if (ret == -ENXIO || ret == -ENODEV) {
 842                         dwc->usb3_phy = NULL;
 843                 } else if (ret == -EPROBE_DEFER) {
 844                         return ret;
 845                 } else {
 846                         dev_err(dev, "no usb3 phy configured\n");
 847                         return ret;
 848                 }
 849         }
 850
 851         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 852         if (IS_ERR(dwc->usb2_generic_phy)) {
 853                 ret = PTR_ERR(dwc->usb2_generic_phy);
 854                 if (ret == -ENOSYS || ret == -ENODEV) {
 855                         dwc->usb2_generic_phy = NULL;
 856                 } else if (ret == -EPROBE_DEFER) {
 857                         return ret;
 858                 } else {
 859                         dev_err(dev, "no usb2 phy configured\n");
 860                         return ret;
 861                 }
 862         }
 863
 864         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 865         if (IS_ERR(dwc->usb3_generic_phy)) {
 866                 ret = PTR_ERR(dwc->usb3_generic_phy);
 867                 if (ret == -ENOSYS || ret == -ENODEV) {
 868                         dwc->usb3_generic_phy = NULL;
 869                 } else if (ret == -EPROBE_DEFER) {
 870                         return ret;
 871                 } else {
 872                         dev_err(dev, "no usb3 phy configured\n");
 873                         return ret;
 874                 }
 875         }
 876
 877         return 0;
 878 }
 879
 880 static int dwc3_core_init_mode(struct dwc3 *dwc)
 881 {
 882         struct device *dev = dwc->dev;
 883
 884         switch (dwc->dr_mode) {
 885         case USB_DR_MODE_PERIPHERAL:
 886                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 887                 break;
 888         case USB_DR_MODE_HOST:
 889                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 890                 break;
 891         case USB_DR_MODE_OTG:
 892                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 893                 break;
 894         default:
 895                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 896                 return -EINVAL;
 897         }
 898
 899         return 0;
 900 }
 901
 902 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 903 {
 904         switch (dwc->dr_mode) {
 905         case USB_DR_MODE_PERIPHERAL:
 906                 dwc3_gadget_exit(dwc);
 907                 break;
 908         case USB_DR_MODE_HOST:
 909                 dwc3_host_exit(dwc);
 910                 break;
 911         case USB_DR_MODE_OTG:
 912                 dwc3_host_exit(dwc);
 913                 dwc3_gadget_exit(dwc);
 914                 break;
 915         default:
 916                 /* do nothing */
 917                 break;
 918         }
 919
 920         /* de-assert DRVVBUS for HOST and OTG mode */
 921         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 922 }
 923
 924 /* XHCI reset, resets other CORE registers as well, re-init those */
 925 void dwc3_post_host_reset_core_init(struct dwc3 *dwc)
 926 {
 927         dwc3_core_init(dwc);
 928         dwc3_gadget_restart(dwc);
 929 }
 930
 931 static void (*notify_event)(struct dwc3 *, unsigned, unsigned);
 932 void dwc3_set_notifier(void (*notify)(struct dwc3 *, unsigned, unsigned))
 933 {
 934         notify_event = notify;
 935 }
 936 EXPORT_SYMBOL(dwc3_set_notifier);
 937
 938 int dwc3_notify_event(struct dwc3 *dwc, unsigned event, unsigned value)
 939 {
 940         int ret = 0;
 941
 942         if (dwc->notify_event)
 943                 dwc->notify_event(dwc, event, value);
 944         else
 945                 ret = -ENODEV;
 946
 947         return ret;
 948 }
 949 EXPORT_SYMBOL(dwc3_notify_event);
 950
 951 int dwc3_core_pre_init(struct dwc3 *dwc)
 952 {
 953         int ret;
 954
 955         dwc3_cache_hwparams(dwc);
 956
 957         ret = dwc3_phy_setup(dwc);
 958         if (ret)
 959                 goto err0;
 960
 961         if (!dwc->ev_buffs) {
 962                 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 963                 if (ret) {
 964                         dev_err(dwc->dev, "failed to allocate event buffers\n");
 965                         ret = -ENOMEM;
 966                         goto err1;
 967                 }
 968         }
 969
 970         ret = dwc3_core_init(dwc);
 971         if (ret) {
 972                 dev_err(dwc->dev, "failed to initialize core\n");
 973                 goto err2;
 974         }
 975
 976         ret = phy_power_on(dwc->usb2_generic_phy);
 977         if (ret < 0)
 978                 goto err3;
 979
 980         ret = phy_power_on(dwc->usb3_generic_phy);
 981         if (ret < 0)
 982                 goto err4;
 983
 984         ret = dwc3_event_buffers_setup(dwc);
 985         if (ret) {
 986                 dev_err(dwc->dev, "failed to setup event buffers\n");
 987                 goto err5;
 988         }
 989
 990         ret = dwc3_core_init_mode(dwc);
 991         if (ret) {
 992                 dev_err(dwc->dev, "failed to set mode with dwc3 core\n");
 993                 goto err6;
 994         }
 995
 996         return ret;
 997
 998 err6:
 999         dwc3_event_buffers_cleanup(dwc);
1000 err5:
1001         phy_power_off(dwc->usb3_generic_phy);
1002 err4:
1003         phy_power_off(dwc->usb2_generic_phy);
1004 err3:
1005         dwc3_core_exit(dwc);
1006 err2:
1007         dwc3_free_event_buffers(dwc);
1008 err1:
1009         dwc3_ulpi_exit(dwc);
1010 err0:
1011         return ret;
1012 }
1013
1014 #define DWC3_ALIGN_MASK         (16 - 1)
1015
1016 /* check whether the core supports IMOD */
1017 bool dwc3_has_imod(struct dwc3 *dwc)
1018 {
1019         return ((dwc3_is_usb3(dwc) &&
1020                 dwc->revision >= DWC3_REVISION_300A) ||
1021                 (dwc3_is_usb31(dwc) &&
1022                 dwc->revision >= DWC3_USB31_REVISION_120A));
1023 }
1024
1025 static int dwc3_probe(struct platform_device *pdev)
1026 {
1027         struct device           *dev = &pdev->dev;
1028         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
1029         struct resource         *res;
1030         struct dwc3             *dwc;
1031         u8                      lpm_nyet_threshold;
1032         u8                      tx_de_emphasis;
1033         u8                      hird_threshold;
1034         u32                     fladj = 0;
1035         u32                     num_evt_buffs;
1036         int                     irq;
1037         int                     ret;
1038
1039         void __iomem            *regs;
1040         void                    *mem;
1041
1042         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
1043         if (!mem)
1044                 return -ENOMEM;
1045
1046         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
1047         dwc->mem = mem;
1048         dwc->dev = dev;
1049
1050         dwc->notify_event = notify_event;
1051         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1052         if (!res) {
1053                 dev_err(dev, "missing IRQ\n");
1054                 return -ENODEV;
1055         }
1056         dwc->xhci_resources[1].start = res->start;
1057         dwc->xhci_resources[1].end = res->end;
1058         dwc->xhci_resources[1].flags = res->flags;
1059         dwc->xhci_resources[1].name = res->name;
1060
1061         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1062
1063         /* will be enabled in dwc3_msm_resume() */
1064         irq_set_status_flags(irq, IRQ_NOAUTOEN);
1065         ret = devm_request_irq(dev, irq, dwc3_interrupt, IRQF_SHARED, "dwc3",
1066                         dwc);
1067         if (ret) {
1068                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1069                                 irq, ret);
1070                 return -ENODEV;
1071         }
1072
1073         dwc->irq = irq;
1074
1075         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1076         if (!res) {
1077                 dev_err(dev, "missing memory resource\n");
1078                 return -ENODEV;
1079         }
1080
1081         dwc->reg_phys = res->start;
1082         dwc->xhci_resources[0].start = res->start;
1083         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1084                                         DWC3_XHCI_REGS_END;
1085         dwc->xhci_resources[0].flags = res->flags;
1086         dwc->xhci_resources[0].name = res->name;
1087
1088         res->start += DWC3_GLOBALS_REGS_START;
1089
1090         /*
1091          * Request memory region but exclude xHCI regs,
1092          * since it will be requested by the xhci-plat driver.
1093          */
1094         regs = devm_ioremap_resource(dev, res);
1095         if (IS_ERR(regs)) {
1096                 ret = PTR_ERR(regs);
1097                 goto err0;
1098         }
1099
1100         dwc->regs       = regs;
1101         dwc->regs_size  = resource_size(res);
1102
1103         /* default to highest possible threshold */
1104         lpm_nyet_threshold = 0xf;
1105
1106         /* default to -3.5dB de-emphasis */
1107         tx_de_emphasis = 1;
1108
1109         /*
1110          * default to assert utmi_sleep_n and use maximum allowed HIRD
1111          * threshold value of 0b1100
1112          */
1113         hird_threshold = 12;
1114
1115         dwc->maximum_speed = usb_get_maximum_speed(dev);
1116         dwc->max_hw_supp_speed = dwc->maximum_speed;
1117         dwc->dr_mode = usb_get_dr_mode(dev);
1118
1119         dwc->has_lpm_erratum = device_property_read_bool(dev,
1120                                 "snps,has-lpm-erratum");
1121         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1122                                 &lpm_nyet_threshold);
1123         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1124                                 "snps,is-utmi-l1-suspend");
1125         device_property_read_u8(dev, "snps,hird-threshold",
1126                                 &hird_threshold);
1127         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1128                                 "snps,usb3_lpm_capable");
1129
1130         dwc->needs_fifo_resize = device_property_read_bool(dev,
1131                                 "tx-fifo-resize");
1132
1133         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1134                                 "snps,disable_scramble_quirk");
1135         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1136                                 "snps,u2exit_lfps_quirk");
1137         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1138                                 "snps,u2ss_inp3_quirk");
1139         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1140                                 "snps,req_p1p2p3_quirk");
1141         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1142                                 "snps,del_p1p2p3_quirk");
1143         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1144                                 "snps,del_phy_power_chg_quirk");
1145         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1146                                 "snps,lfps_filter_quirk");
1147         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1148                                 "snps,rx_detect_poll_quirk");
1149         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1150                                 "snps,dis_u3_susphy_quirk");
1151         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1152                                 "snps,dis_u2_susphy_quirk");
1153         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1154                                 "snps,dis_enblslpm_quirk");
1155
1156         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1157                                 "snps,tx_de_emphasis_quirk");
1158         device_property_read_u8(dev, "snps,tx_de_emphasis",
1159                                 &tx_de_emphasis);
1160         device_property_read_string(dev, "snps,hsphy_interface",
1161                                     &dwc->hsphy_interface);
1162         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1163                                  &fladj);
1164
1165         dwc->nominal_elastic_buffer = device_property_read_bool(dev,
1166                                 "snps,nominal-elastic-buffer");
1167         dwc->usb3_u1u2_disable = device_property_read_bool(dev,
1168                                 "snps,usb3-u1u2-disable");
1169         dwc->disable_clk_gating = device_property_read_bool(dev,
1170                                 "snps,disable-clk-gating");
1171         dwc->enable_bus_suspend = device_property_read_bool(dev,
1172                                 "snps,bus-suspend-enable");
1173
1174         dwc->num_normal_event_buffers = 1;
1175         ret = device_property_read_u32(dev,
1176                 "snps,num-normal-evt-buffs", &num_evt_buffs);
1177         if (!ret)
1178                 dwc->num_normal_event_buffers = num_evt_buffs;
1179
1180         ret = device_property_read_u32(dev,
1181                 "snps,num-gsi-evt-buffs", &dwc->num_gsi_event_buffers);
1182
1183         if (dwc->enable_bus_suspend) {
1184                 pm_runtime_set_autosuspend_delay(dev, 500);
1185                 pm_runtime_use_autosuspend(dev);
1186         }
1187
1188         if (pdata) {
1189                 dwc->maximum_speed = pdata->maximum_speed;
1190                 dwc->max_hw_supp_speed = dwc->maximum_speed;
1191                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
1192                 if (pdata->lpm_nyet_threshold)
1193                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
1194                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
1195                 if (pdata->hird_threshold)
1196                         hird_threshold = pdata->hird_threshold;
1197
1198                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
1199                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
1200                 dwc->dr_mode = pdata->dr_mode;
1201
1202                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
1203                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
1204                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
1205                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
1206                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
1207                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
1208                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
1209                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
1210                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
1211                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
1212                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
1213
1214                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
1215                 if (pdata->tx_de_emphasis)
1216                         tx_de_emphasis = pdata->tx_de_emphasis;
1217
1218                 dwc->hsphy_interface = pdata->hsphy_interface;
1219                 fladj = pdata->fladj_value;
1220         }
1221
1222         /* default to superspeed if no maximum_speed passed */
1223         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
1224                 dwc->max_hw_supp_speed = dwc->maximum_speed = USB_SPEED_SUPER;
1225
1226         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1227         dwc->tx_de_emphasis = tx_de_emphasis;
1228
1229         dwc->hird_threshold = hird_threshold
1230                 | (dwc->is_utmi_l1_suspend << 4);
1231
1232         init_waitqueue_head(&dwc->wait_linkstate);
1233         platform_set_drvdata(pdev, dwc);
1234         ret = dwc3_core_get_phy(dwc);
1235         if (ret)
1236                 goto err0;
1237
1238         spin_lock_init(&dwc->lock);
1239
1240         dev->dma_mask   = dev->parent->dma_mask;
1241         dev->dma_parms  = dev->parent->dma_parms;
1242         dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1243
1244         dwc->dwc_wq = alloc_ordered_workqueue("dwc_wq", WQ_HIGHPRI);
1245         if (!dwc->dwc_wq) {
1246                 pr_err("%s: Unable to create workqueue dwc_wq\n", __func__);
1247                 return -ENOMEM;
1248         }
1249
1250         INIT_WORK(&dwc->bh_work, dwc3_bh_work);
1251
1252         pm_runtime_no_callbacks(dev);
1253         pm_runtime_set_active(dev);
1254         pm_runtime_enable(dev);
1255         pm_runtime_forbid(dev);
1256
1257         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1258                 dwc->dr_mode = USB_DR_MODE_HOST;
1259         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1260                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1261
1262         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) {
1263                 dwc->dr_mode = USB_DR_MODE_OTG;
1264                 dwc->is_drd = true;
1265         }
1266
1267         /* Adjust Frame Length */
1268         dwc3_frame_length_adjustment(dwc, fladj);
1269
1270         /* Hardcode number of eps */
1271         dwc->num_in_eps = 16;
1272         dwc->num_out_eps = 16;
1273
1274         if (dwc->dr_mode == USB_DR_MODE_OTG ||
1275                 dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
1276                 ret = dwc3_gadget_init(dwc);
1277                 if (ret) {
1278                         dev_err(dev, "failed to initialize gadget\n");
1279                         goto err0;
1280                 }
1281         }
1282
1283         if (dwc->dr_mode == USB_DR_MODE_OTG ||
1284                 dwc->dr_mode ==  USB_DR_MODE_HOST) {
1285                 ret = dwc3_host_init(dwc);
1286                 if (ret) {
1287                         dev_err(dev, "failed to initialize host\n");
1288                         goto err_gadget;
1289                 }
1290         }
1291
1292         ret = dwc3_debugfs_init(dwc);
1293         if (ret) {
1294                 dev_err(dev, "failed to initialize debugfs\n");
1295                 goto err_host;
1296         }
1297
1298         pm_runtime_allow(dev);
1299
1300         return 0;
1301
1302 err_host:
1303         if (dwc->dr_mode == USB_DR_MODE_OTG ||
1304                 dwc->dr_mode ==  USB_DR_MODE_HOST)
1305                 dwc3_host_exit(dwc);
1306 err_gadget:
1307         if (dwc->dr_mode == USB_DR_MODE_OTG ||
1308                 dwc->dr_mode == USB_DR_MODE_PERIPHERAL)
1309                 dwc3_gadget_exit(dwc);
1310 err0:
1311         /*
1312          * restore res->start back to its original value so that, in case the
1313          * probe is deferred, we don't end up getting error in request the
1314          * memory region the next time probe is called.
1315          */
1316         res->start -= DWC3_GLOBALS_REGS_START;
1317         destroy_workqueue(dwc->dwc_wq);
1318
1319         return ret;
1320 }
1321
1322 static int dwc3_remove(struct platform_device *pdev)
1323 {
1324         struct dwc3     *dwc = platform_get_drvdata(pdev);
1325         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1326
1327         /*
1328          * restore res->start back to its original value so that, in case the
1329          * probe is deferred, we don't end up getting error in request the
1330          * memory region the next time probe is called.
1331          */
1332         res->start -= DWC3_GLOBALS_REGS_START;
1333
1334         dwc3_debugfs_exit(dwc);
1335         dwc3_core_exit_mode(dwc);
1336         dwc3_event_buffers_cleanup(dwc);
1337         dwc3_free_event_buffers(dwc);
1338
1339         phy_power_off(dwc->usb2_generic_phy);
1340         phy_power_off(dwc->usb3_generic_phy);
1341
1342         dwc3_core_exit(dwc);
1343         dwc3_ulpi_exit(dwc);
1344
1345         destroy_workqueue(dwc->dwc_wq);
1346
1347         pm_runtime_put_sync(&pdev->dev);
1348         pm_runtime_disable(&pdev->dev);
1349
1350         return 0;
1351 }
1352
1353 #ifdef CONFIG_PM_SLEEP
1354 static int dwc3_suspend(struct device *dev)
1355 {
1356         struct dwc3     *dwc = dev_get_drvdata(dev);
1357         unsigned long   flags;
1358
1359         /* Check if platform glue driver handling PM, if not then handle here */
1360         if (!dwc3_notify_event(dwc, DWC3_CORE_PM_SUSPEND_EVENT, 0))
1361                 return 0;
1362
1363         spin_lock_irqsave(&dwc->lock, flags);
1364
1365         switch (dwc->dr_mode) {
1366         case USB_DR_MODE_PERIPHERAL:
1367         case USB_DR_MODE_OTG:
1368                 dwc3_gadget_suspend(dwc);
1369                 /* FALLTHROUGH */
1370         case USB_DR_MODE_HOST:
1371         default:
1372                 dwc3_event_buffers_cleanup(dwc);
1373                 break;
1374         }
1375
1376         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1377         spin_unlock_irqrestore(&dwc->lock, flags);
1378
1379         usb_phy_shutdown(dwc->usb3_phy);
1380         usb_phy_shutdown(dwc->usb2_phy);
1381         phy_exit(dwc->usb2_generic_phy);
1382         phy_exit(dwc->usb3_generic_phy);
1383
1384         pinctrl_pm_select_sleep_state(dev);
1385
1386         return 0;
1387 }
1388
1389 static int dwc3_resume(struct device *dev)
1390 {
1391         struct dwc3     *dwc = dev_get_drvdata(dev);
1392         unsigned long   flags;
1393         int             ret;
1394
1395         /* Check if platform glue driver handling PM, if not then handle here */
1396         if (!dwc3_notify_event(dwc, DWC3_CORE_PM_RESUME_EVENT, 0))
1397                 return 0;
1398
1399         pinctrl_pm_select_default_state(dev);
1400
1401         usb_phy_init(dwc->usb3_phy);
1402         usb_phy_init(dwc->usb2_phy);
1403         ret = phy_init(dwc->usb2_generic_phy);
1404         if (ret < 0)
1405                 return ret;
1406
1407         ret = phy_init(dwc->usb3_generic_phy);
1408         if (ret < 0)
1409                 goto err_usb2phy_init;
1410
1411         spin_lock_irqsave(&dwc->lock, flags);
1412
1413         dwc3_event_buffers_setup(dwc);
1414         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1415
1416         switch (dwc->dr_mode) {
1417         case USB_DR_MODE_PERIPHERAL:
1418         case USB_DR_MODE_OTG:
1419                 dwc3_gadget_resume(dwc);
1420                 /* FALLTHROUGH */
1421         case USB_DR_MODE_HOST:
1422         default:
1423                 /* do nothing */
1424                 break;
1425         }
1426
1427         spin_unlock_irqrestore(&dwc->lock, flags);
1428
1429         pm_runtime_disable(dev);
1430         pm_runtime_set_active(dev);
1431         pm_runtime_enable(dev);
1432
1433         return 0;
1434
1435 err_usb2phy_init:
1436         phy_exit(dwc->usb2_generic_phy);
1437
1438         return ret;
1439 }
1440
1441 static int dwc3_pm_restore(struct device *dev)
1442 {
1443         /*
1444          * Set the core as runtime active to prevent the runtime
1445          * PM ops being called before the PM restore is completed.
1446          */
1447         pm_runtime_disable(dev);
1448         pm_runtime_set_active(dev);
1449         pm_runtime_enable(dev);
1450
1451         return 0;
1452 }
1453
1454 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1455         .suspend        = dwc3_suspend,
1456         .resume         = dwc3_resume,
1457         .freeze         = dwc3_suspend,
1458         .thaw           = dwc3_pm_restore,
1459         .poweroff       = dwc3_suspend,
1460         .restore        = dwc3_pm_restore,
1461 };
1462
1463 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1464 #else
1465 #define DWC3_PM_OPS     NULL
1466 #endif
1467
1468 #ifdef CONFIG_OF
1469 static const struct of_device_id of_dwc3_match[] = {
1470         {
1471                 .compatible = "snps,dwc3"
1472         },
1473         {
1474                 .compatible = "synopsys,dwc3"
1475         },
1476         { },
1477 };
1478 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1479 #endif
1480
1481 #ifdef CONFIG_ACPI
1482
1483 #define ACPI_ID_INTEL_BSW       "808622B7"
1484
1485 static const struct acpi_device_id dwc3_acpi_match[] = {
1486         { ACPI_ID_INTEL_BSW, 0 },
1487         { },
1488 };
1489 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1490 #endif
1491
1492 static struct platform_driver dwc3_driver = {
1493         .probe          = dwc3_probe,
1494         .remove         = dwc3_remove,
1495         .driver         = {
1496                 .name   = "dwc3",
1497                 .of_match_table = of_match_ptr(of_dwc3_match),
1498                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1499                 .pm     = DWC3_PM_OPS,
1500         },
1501 };
1502
1503 module_platform_driver(dwc3_driver);
1504
1505 MODULE_ALIAS("platform:dwc3");
1506 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1507 MODULE_LICENSE("GPL v2");
1508 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");