drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/ioport.h>
  30 #include <linux/io.h>
  31 #include <linux/list.h>
  32 #include <linux/delay.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/of.h>
  35
  36 #include <linux/usb/ch9.h>
  37 #include <linux/usb/gadget.h>
  38 #include <linux/usb/of.h>
  39 #include <linux/usb/otg.h>
  40
  41 #include "platform_data.h"
  42 #include "core.h"
  43 #include "gadget.h"
  44 #include "io.h"
  45
  46 #include "debug.h"
  47
  48 /* -------------------------------------------------------------------------- */
  49
  50 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  51 {
  52         u32 reg;
  53
  54         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  55         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  56         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  57         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  58 }
  59
  60 /**
  61  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  62  * @dwc: pointer to our context structure
  63  */
  64 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  65 {
  66         u32             reg;
  67         int             ret;
  68
  69         /* Before Resetting PHY, put Core in Reset */
  70         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  71         reg |= DWC3_GCTL_CORESOFTRESET;
  72         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  73
  74         /* Assert USB3 PHY reset */
  75         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  76         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  77         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  78
  79         /* Assert USB2 PHY reset */
  80         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  81         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  82         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  83
  84         usb_phy_init(dwc->usb2_phy);
  85         usb_phy_init(dwc->usb3_phy);
  86         ret = phy_init(dwc->usb2_generic_phy);
  87         if (ret < 0)
  88                 return ret;
  89
  90         ret = phy_init(dwc->usb3_generic_phy);
  91         if (ret < 0) {
  92                 phy_exit(dwc->usb2_generic_phy);
  93                 return ret;
  94         }
  95         mdelay(100);
  96
  97         /* Clear USB3 PHY reset */
  98         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  99         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
 100         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 101
 102         /* Clear USB2 PHY reset */
 103         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 104         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 105         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 106
 107         mdelay(100);
 108
 109         /* After PHYs are stable we can take Core out of reset state */
 110         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 111         reg &= ~DWC3_GCTL_CORESOFTRESET;
 112         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 113
 114         return 0;
 115 }
 116
 117 /**
 118  * dwc3_free_one_event_buffer - Frees one event buffer
 119  * @dwc: Pointer to our controller context structure
 120  * @evt: Pointer to event buffer to be freed
 121  */
 122 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 123                 struct dwc3_event_buffer *evt)
 124 {
 125         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 126 }
 127
 128 /**
 129  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 130  * @dwc: Pointer to our controller context structure
 131  * @length: size of the event buffer
 132  *
 133  * Returns a pointer to the allocated event buffer structure on success
 134  * otherwise ERR_PTR(errno).
 135  */
 136 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 137                 unsigned length)
 138 {
 139         struct dwc3_event_buffer        *evt;
 140
 141         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 142         if (!evt)
 143                 return ERR_PTR(-ENOMEM);
 144
 145         evt->dwc        = dwc;
 146         evt->length     = length;
 147         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 148                         &evt->dma, GFP_KERNEL);
 149         if (!evt->buf)
 150                 return ERR_PTR(-ENOMEM);
 151
 152         return evt;
 153 }
 154
 155 /**
 156  * dwc3_free_event_buffers - frees all allocated event buffers
 157  * @dwc: Pointer to our controller context structure
 158  */
 159 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 160 {
 161         struct dwc3_event_buffer        *evt;
 162         int i;
 163
 164         for (i = 0; i < dwc->num_event_buffers; i++) {
 165                 evt = dwc->ev_buffs[i];
 166                 if (evt)
 167                         dwc3_free_one_event_buffer(dwc, evt);
 168         }
 169 }
 170
 171 /**
 172  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 173  * @dwc: pointer to our controller context structure
 174  * @length: size of event buffer
 175  *
 176  * Returns 0 on success otherwise negative errno. In the error case, dwc
 177  * may contain some buffers allocated but not all which were requested.
 178  */
 179 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 180 {
 181         int                     num;
 182         int                     i;
 183
 184         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 185         dwc->num_event_buffers = num;
 186
 187         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 188                         GFP_KERNEL);
 189         if (!dwc->ev_buffs) {
 190                 dev_err(dwc->dev, "can't allocate event buffers array\n");
 191                 return -ENOMEM;
 192         }
 193
 194         for (i = 0; i < num; i++) {
 195                 struct dwc3_event_buffer        *evt;
 196
 197                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 198                 if (IS_ERR(evt)) {
 199                         dev_err(dwc->dev, "can't allocate event buffer\n");
 200                         return PTR_ERR(evt);
 201                 }
 202                 dwc->ev_buffs[i] = evt;
 203         }
 204
 205         return 0;
 206 }
 207
 208 /**
 209  * dwc3_event_buffers_setup - setup our allocated event buffers
 210  * @dwc: pointer to our controller context structure
 211  *
 212  * Returns 0 on success otherwise negative errno.
 213  */
 214 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 215 {
 216         struct dwc3_event_buffer        *evt;
 217         int                             n;
 218
 219         for (n = 0; n < dwc->num_event_buffers; n++) {
 220                 evt = dwc->ev_buffs[n];
 221                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 222                                 evt->buf, (unsigned long long) evt->dma,
 223                                 evt->length);
 224
 225                 evt->lpos = 0;
 226
 227                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 228                                 lower_32_bits(evt->dma));
 229                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 230                                 upper_32_bits(evt->dma));
 231                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 232                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 233                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 234         }
 235
 236         return 0;
 237 }
 238
 239 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 240 {
 241         struct dwc3_event_buffer        *evt;
 242         int                             n;
 243
 244         for (n = 0; n < dwc->num_event_buffers; n++) {
 245                 evt = dwc->ev_buffs[n];
 246
 247                 evt->lpos = 0;
 248
 249                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 250                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 251                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 252                                 | DWC3_GEVNTSIZ_SIZE(0));
 253                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 254         }
 255 }
 256
 257 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 258 {
 259         if (!dwc->has_hibernation)
 260                 return 0;
 261
 262         if (!dwc->nr_scratch)
 263                 return 0;
 264
 265         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 266                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 267         if (!dwc->scratchbuf)
 268                 return -ENOMEM;
 269
 270         return 0;
 271 }
 272
 273 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 274 {
 275         dma_addr_t scratch_addr;
 276         u32 param;
 277         int ret;
 278
 279         if (!dwc->has_hibernation)
 280                 return 0;
 281
 282         if (!dwc->nr_scratch)
 283                 return 0;
 284
 285          /* should never fall here */
 286         if (!WARN_ON(dwc->scratchbuf))
 287                 return 0;
 288
 289         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 290                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 291                         DMA_BIDIRECTIONAL);
 292         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 293                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 294                 ret = -EFAULT;
 295                 goto err0;
 296         }
 297
 298         dwc->scratch_addr = scratch_addr;
 299
 300         param = lower_32_bits(scratch_addr);
 301
 302         ret = dwc3_send_gadget_generic_command(dwc,
 303                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 304         if (ret < 0)
 305                 goto err1;
 306
 307         param = upper_32_bits(scratch_addr);
 308
 309         ret = dwc3_send_gadget_generic_command(dwc,
 310                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 311         if (ret < 0)
 312                 goto err1;
 313
 314         return 0;
 315
 316 err1:
 317         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 318                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 319
 320 err0:
 321         return ret;
 322 }
 323
 324 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 325 {
 326         if (!dwc->has_hibernation)
 327                 return;
 328
 329         if (!dwc->nr_scratch)
 330                 return;
 331
 332          /* should never fall here */
 333         if (!WARN_ON(dwc->scratchbuf))
 334                 return;
 335
 336         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 337                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 338         kfree(dwc->scratchbuf);
 339 }
 340
 341 static void dwc3_core_num_eps(struct dwc3 *dwc)
 342 {
 343         struct dwc3_hwparams    *parms = &dwc->hwparams;
 344
 345         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 346         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 347
 348         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 349                         dwc->num_in_eps, dwc->num_out_eps);
 350 }
 351
 352 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 353 {
 354         struct dwc3_hwparams    *parms = &dwc->hwparams;
 355
 356         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 357         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 358         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 359         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 360         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 361         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 362         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 363         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 364         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 365 }
 366
 367 /**
 368  * dwc3_core_init - Low-level initialization of DWC3 Core
 369  * @dwc: Pointer to our controller context structure
 370  *
 371  * Returns 0 on success otherwise negative errno.
 372  */
 373 static int dwc3_core_init(struct dwc3 *dwc)
 374 {
 375         unsigned long           timeout;
 376         u32                     hwparams4 = dwc->hwparams.hwparams4;
 377         u32                     reg;
 378         int                     ret;
 379
 380         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 381         /* This should read as U3 followed by revision number */
 382         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 383                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 384                 ret = -ENODEV;
 385                 goto err0;
 386         }
 387         dwc->revision = reg;
 388
 389         /* issue device SoftReset too */
 390         timeout = jiffies + msecs_to_jiffies(500);
 391         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 392         do {
 393                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 394                 if (!(reg & DWC3_DCTL_CSFTRST))
 395                         break;
 396
 397                 if (time_after(jiffies, timeout)) {
 398                         dev_err(dwc->dev, "Reset Timed Out\n");
 399                         ret = -ETIMEDOUT;
 400                         goto err0;
 401                 }
 402
 403                 cpu_relax();
 404         } while (true);
 405
 406         ret = dwc3_core_soft_reset(dwc);
 407         if (ret)
 408                 goto err0;
 409
 410         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 411         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 412         reg &= ~DWC3_GCTL_DISSCRAMBLE;
 413
 414         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 415         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 416                 /**
 417                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 418                  * issue which would cause xHCI compliance tests to fail.
 419                  *
 420                  * Because of that we cannot enable clock gating on such
 421                  * configurations.
 422                  *
 423                  * Refers to:
 424                  *
 425                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 426                  * SOF/ITP Mode Used
 427                  */
 428                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 429                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 430                                 (dwc->revision >= DWC3_REVISION_210A &&
 431                                 dwc->revision <= DWC3_REVISION_250A))
 432                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 433                 else
 434                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 435                 break;
 436         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 437                 /* enable hibernation here */
 438                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 439                 break;
 440         default:
 441                 dev_dbg(dwc->dev, "No power optimization available\n");
 442         }
 443
 444         /*
 445          * WORKAROUND: DWC3 revisions <1.90a have a bug
 446          * where the device can fail to connect at SuperSpeed
 447          * and falls back to high-speed mode which causes
 448          * the device to enter a Connect/Disconnect loop
 449          */
 450         if (dwc->revision < DWC3_REVISION_190A)
 451                 reg |= DWC3_GCTL_U2RSTECN;
 452
 453         dwc3_core_num_eps(dwc);
 454
 455         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 456
 457         ret = dwc3_alloc_scratch_buffers(dwc);
 458         if (ret)
 459                 goto err1;
 460
 461         ret = dwc3_setup_scratch_buffers(dwc);
 462         if (ret)
 463                 goto err2;
 464
 465         return 0;
 466
 467 err2:
 468         dwc3_free_scratch_buffers(dwc);
 469
 470 err1:
 471         usb_phy_shutdown(dwc->usb2_phy);
 472         usb_phy_shutdown(dwc->usb3_phy);
 473         phy_exit(dwc->usb2_generic_phy);
 474         phy_exit(dwc->usb3_generic_phy);
 475
 476 err0:
 477         return ret;
 478 }
 479
 480 static void dwc3_core_exit(struct dwc3 *dwc)
 481 {
 482         dwc3_free_scratch_buffers(dwc);
 483         usb_phy_shutdown(dwc->usb2_phy);
 484         usb_phy_shutdown(dwc->usb3_phy);
 485         phy_exit(dwc->usb2_generic_phy);
 486         phy_exit(dwc->usb3_generic_phy);
 487 }
 488
 489 static int dwc3_core_get_phy(struct dwc3 *dwc)
 490 {
 491         struct device           *dev = dwc->dev;
 492         struct device_node      *node = dev->of_node;
 493         int ret;
 494
 495         if (node) {
 496                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 497                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 498         } else {
 499                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 500                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 501         }
 502
 503         if (IS_ERR(dwc->usb2_phy)) {
 504                 ret = PTR_ERR(dwc->usb2_phy);
 505                 if (ret == -ENXIO || ret == -ENODEV) {
 506                         dwc->usb2_phy = NULL;
 507                 } else if (ret == -EPROBE_DEFER) {
 508                         return ret;
 509                 } else {
 510                         dev_err(dev, "no usb2 phy configured\n");
 511                         return ret;
 512                 }
 513         }
 514
 515         if (IS_ERR(dwc->usb3_phy)) {
 516                 ret = PTR_ERR(dwc->usb3_phy);
 517                 if (ret == -ENXIO || ret == -ENODEV) {
 518                         dwc->usb3_phy = NULL;
 519                 } else if (ret == -EPROBE_DEFER) {
 520                         return ret;
 521                 } else {
 522                         dev_err(dev, "no usb3 phy configured\n");
 523                         return ret;
 524                 }
 525         }
 526
 527         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 528         if (IS_ERR(dwc->usb2_generic_phy)) {
 529                 ret = PTR_ERR(dwc->usb2_generic_phy);
 530                 if (ret == -ENOSYS || ret == -ENODEV) {
 531                         dwc->usb2_generic_phy = NULL;
 532                 } else if (ret == -EPROBE_DEFER) {
 533                         return ret;
 534                 } else {
 535                         dev_err(dev, "no usb2 phy configured\n");
 536                         return ret;
 537                 }
 538         }
 539
 540         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 541         if (IS_ERR(dwc->usb3_generic_phy)) {
 542                 ret = PTR_ERR(dwc->usb3_generic_phy);
 543                 if (ret == -ENOSYS || ret == -ENODEV) {
 544                         dwc->usb3_generic_phy = NULL;
 545                 } else if (ret == -EPROBE_DEFER) {
 546                         return ret;
 547                 } else {
 548                         dev_err(dev, "no usb3 phy configured\n");
 549                         return ret;
 550                 }
 551         }
 552
 553         return 0;
 554 }
 555
 556 static int dwc3_core_init_mode(struct dwc3 *dwc)
 557 {
 558         struct device *dev = dwc->dev;
 559         int ret;
 560
 561         switch (dwc->dr_mode) {
 562         case USB_DR_MODE_PERIPHERAL:
 563                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 564                 ret = dwc3_gadget_init(dwc);
 565                 if (ret) {
 566                         dev_err(dev, "failed to initialize gadget\n");
 567                         return ret;
 568                 }
 569                 break;
 570         case USB_DR_MODE_HOST:
 571                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 572                 ret = dwc3_host_init(dwc);
 573                 if (ret) {
 574                         dev_err(dev, "failed to initialize host\n");
 575                         return ret;
 576                 }
 577                 break;
 578         case USB_DR_MODE_OTG:
 579                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 580                 ret = dwc3_host_init(dwc);
 581                 if (ret) {
 582                         dev_err(dev, "failed to initialize host\n");
 583                         return ret;
 584                 }
 585
 586                 ret = dwc3_gadget_init(dwc);
 587                 if (ret) {
 588                         dev_err(dev, "failed to initialize gadget\n");
 589                         return ret;
 590                 }
 591                 break;
 592         default:
 593                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 594                 return -EINVAL;
 595         }
 596
 597         return 0;
 598 }
 599
 600 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 601 {
 602         switch (dwc->dr_mode) {
 603         case USB_DR_MODE_PERIPHERAL:
 604                 dwc3_gadget_exit(dwc);
 605                 break;
 606         case USB_DR_MODE_HOST:
 607                 dwc3_host_exit(dwc);
 608                 break;
 609         case USB_DR_MODE_OTG:
 610                 dwc3_host_exit(dwc);
 611                 dwc3_gadget_exit(dwc);
 612                 break;
 613         default:
 614                 /* do nothing */
 615                 break;
 616         }
 617 }
 618
 619 #define DWC3_ALIGN_MASK         (16 - 1)
 620
 621 static int dwc3_probe(struct platform_device *pdev)
 622 {
 623         struct device           *dev = &pdev->dev;
 624         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 625         struct device_node      *node = dev->of_node;
 626         struct resource         *res;
 627         struct dwc3             *dwc;
 628
 629         int                     ret = -ENOMEM;
 630
 631         void __iomem            *regs;
 632         void                    *mem;
 633
 634         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 635         if (!mem) {
 636                 dev_err(dev, "not enough memory\n");
 637                 return -ENOMEM;
 638         }
 639         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 640         dwc->mem = mem;
 641         dwc->dev = dev;
 642
 643         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 644         if (!res) {
 645                 dev_err(dev, "missing IRQ\n");
 646                 return -ENODEV;
 647         }
 648         dwc->xhci_resources[1].start = res->start;
 649         dwc->xhci_resources[1].end = res->end;
 650         dwc->xhci_resources[1].flags = res->flags;
 651         dwc->xhci_resources[1].name = res->name;
 652
 653         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 654         if (!res) {
 655                 dev_err(dev, "missing memory resource\n");
 656                 return -ENODEV;
 657         }
 658
 659         if (node) {
 660                 dwc->maximum_speed = of_usb_get_maximum_speed(node);
 661
 662                 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
 663                 dwc->dr_mode = of_usb_get_dr_mode(node);
 664         } else if (pdata) {
 665                 dwc->maximum_speed = pdata->maximum_speed;
 666
 667                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 668                 dwc->dr_mode = pdata->dr_mode;
 669         }
 670
 671         /* default to superspeed if no maximum_speed passed */
 672         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 673                 dwc->maximum_speed = USB_SPEED_SUPER;
 674
 675         ret = dwc3_core_get_phy(dwc);
 676         if (ret)
 677                 return ret;
 678
 679         dwc->xhci_resources[0].start = res->start;
 680         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 681                                         DWC3_XHCI_REGS_END;
 682         dwc->xhci_resources[0].flags = res->flags;
 683         dwc->xhci_resources[0].name = res->name;
 684
 685         res->start += DWC3_GLOBALS_REGS_START;
 686
 687         /*
 688          * Request memory region but exclude xHCI regs,
 689          * since it will be requested by the xhci-plat driver.
 690          */
 691         regs = devm_ioremap_resource(dev, res);
 692         if (IS_ERR(regs))
 693                 return PTR_ERR(regs);
 694
 695         spin_lock_init(&dwc->lock);
 696         platform_set_drvdata(pdev, dwc);
 697
 698         dwc->regs       = regs;
 699         dwc->regs_size  = resource_size(res);
 700
 701         dev->dma_mask   = dev->parent->dma_mask;
 702         dev->dma_parms  = dev->parent->dma_parms;
 703         dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 704
 705         pm_runtime_enable(dev);
 706         pm_runtime_get_sync(dev);
 707         pm_runtime_forbid(dev);
 708
 709         dwc3_cache_hwparams(dwc);
 710
 711         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 712         if (ret) {
 713                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 714                 ret = -ENOMEM;
 715                 goto err0;
 716         }
 717
 718         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 719                 dwc->dr_mode = USB_DR_MODE_HOST;
 720         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 721                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 722
 723         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 724                 dwc->dr_mode = USB_DR_MODE_OTG;
 725
 726         ret = dwc3_core_init(dwc);
 727         if (ret) {
 728                 dev_err(dev, "failed to initialize core\n");
 729                 goto err0;
 730         }
 731
 732         usb_phy_set_suspend(dwc->usb2_phy, 0);
 733         usb_phy_set_suspend(dwc->usb3_phy, 0);
 734         ret = phy_power_on(dwc->usb2_generic_phy);
 735         if (ret < 0)
 736                 goto err1;
 737
 738         ret = phy_power_on(dwc->usb3_generic_phy);
 739         if (ret < 0)
 740                 goto err_usb2phy_power;
 741
 742         ret = dwc3_event_buffers_setup(dwc);
 743         if (ret) {
 744                 dev_err(dwc->dev, "failed to setup event buffers\n");
 745                 goto err_usb3phy_power;
 746         }
 747
 748         ret = dwc3_core_init_mode(dwc);
 749         if (ret)
 750                 goto err2;
 751
 752         ret = dwc3_debugfs_init(dwc);
 753         if (ret) {
 754                 dev_err(dev, "failed to initialize debugfs\n");
 755                 goto err3;
 756         }
 757
 758         pm_runtime_allow(dev);
 759
 760         return 0;
 761
 762 err3:
 763         dwc3_core_exit_mode(dwc);
 764
 765 err2:
 766         dwc3_event_buffers_cleanup(dwc);
 767
 768 err_usb3phy_power:
 769         phy_power_off(dwc->usb3_generic_phy);
 770
 771 err_usb2phy_power:
 772         phy_power_off(dwc->usb2_generic_phy);
 773
 774 err1:
 775         usb_phy_set_suspend(dwc->usb2_phy, 1);
 776         usb_phy_set_suspend(dwc->usb3_phy, 1);
 777         dwc3_core_exit(dwc);
 778
 779 err0:
 780         dwc3_free_event_buffers(dwc);
 781
 782         return ret;
 783 }
 784
 785 static int dwc3_remove(struct platform_device *pdev)
 786 {
 787         struct dwc3     *dwc = platform_get_drvdata(pdev);
 788
 789         usb_phy_set_suspend(dwc->usb2_phy, 1);
 790         usb_phy_set_suspend(dwc->usb3_phy, 1);
 791         phy_power_off(dwc->usb2_generic_phy);
 792         phy_power_off(dwc->usb3_generic_phy);
 793
 794         pm_runtime_put_sync(&pdev->dev);
 795         pm_runtime_disable(&pdev->dev);
 796
 797         dwc3_debugfs_exit(dwc);
 798         dwc3_core_exit_mode(dwc);
 799         dwc3_event_buffers_cleanup(dwc);
 800         dwc3_free_event_buffers(dwc);
 801         dwc3_core_exit(dwc);
 802
 803         return 0;
 804 }
 805
 806 #ifdef CONFIG_PM_SLEEP
 807 static int dwc3_prepare(struct device *dev)
 808 {
 809         struct dwc3     *dwc = dev_get_drvdata(dev);
 810         unsigned long   flags;
 811
 812         spin_lock_irqsave(&dwc->lock, flags);
 813
 814         switch (dwc->dr_mode) {
 815         case USB_DR_MODE_PERIPHERAL:
 816         case USB_DR_MODE_OTG:
 817                 dwc3_gadget_prepare(dwc);
 818                 /* FALLTHROUGH */
 819         case USB_DR_MODE_HOST:
 820         default:
 821                 dwc3_event_buffers_cleanup(dwc);
 822                 break;
 823         }
 824
 825         spin_unlock_irqrestore(&dwc->lock, flags);
 826
 827         return 0;
 828 }
 829
 830 static void dwc3_complete(struct device *dev)
 831 {
 832         struct dwc3     *dwc = dev_get_drvdata(dev);
 833         unsigned long   flags;
 834
 835         spin_lock_irqsave(&dwc->lock, flags);
 836
 837         switch (dwc->dr_mode) {
 838         case USB_DR_MODE_PERIPHERAL:
 839         case USB_DR_MODE_OTG:
 840                 dwc3_gadget_complete(dwc);
 841                 /* FALLTHROUGH */
 842         case USB_DR_MODE_HOST:
 843         default:
 844                 dwc3_event_buffers_setup(dwc);
 845                 break;
 846         }
 847
 848         spin_unlock_irqrestore(&dwc->lock, flags);
 849 }
 850
 851 static int dwc3_suspend(struct device *dev)
 852 {
 853         struct dwc3     *dwc = dev_get_drvdata(dev);
 854         unsigned long   flags;
 855
 856         spin_lock_irqsave(&dwc->lock, flags);
 857
 858         switch (dwc->dr_mode) {
 859         case USB_DR_MODE_PERIPHERAL:
 860         case USB_DR_MODE_OTG:
 861                 dwc3_gadget_suspend(dwc);
 862                 /* FALLTHROUGH */
 863         case USB_DR_MODE_HOST:
 864         default:
 865                 /* do nothing */
 866                 break;
 867         }
 868
 869         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
 870         spin_unlock_irqrestore(&dwc->lock, flags);
 871
 872         usb_phy_shutdown(dwc->usb3_phy);
 873         usb_phy_shutdown(dwc->usb2_phy);
 874         phy_exit(dwc->usb2_generic_phy);
 875         phy_exit(dwc->usb3_generic_phy);
 876
 877         return 0;
 878 }
 879
 880 static int dwc3_resume(struct device *dev)
 881 {
 882         struct dwc3     *dwc = dev_get_drvdata(dev);
 883         unsigned long   flags;
 884         int             ret;
 885
 886         usb_phy_init(dwc->usb3_phy);
 887         usb_phy_init(dwc->usb2_phy);
 888         ret = phy_init(dwc->usb2_generic_phy);
 889         if (ret < 0)
 890                 return ret;
 891
 892         ret = phy_init(dwc->usb3_generic_phy);
 893         if (ret < 0)
 894                 goto err_usb2phy_init;
 895
 896         spin_lock_irqsave(&dwc->lock, flags);
 897
 898         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
 899
 900         switch (dwc->dr_mode) {
 901         case USB_DR_MODE_PERIPHERAL:
 902         case USB_DR_MODE_OTG:
 903                 dwc3_gadget_resume(dwc);
 904                 /* FALLTHROUGH */
 905         case USB_DR_MODE_HOST:
 906         default:
 907                 /* do nothing */
 908                 break;
 909         }
 910
 911         spin_unlock_irqrestore(&dwc->lock, flags);
 912
 913         pm_runtime_disable(dev);
 914         pm_runtime_set_active(dev);
 915         pm_runtime_enable(dev);
 916
 917         return 0;
 918
 919 err_usb2phy_init:
 920         phy_exit(dwc->usb2_generic_phy);
 921
 922         return ret;
 923 }
 924
 925 static const struct dev_pm_ops dwc3_dev_pm_ops = {
 926         .prepare        = dwc3_prepare,
 927         .complete       = dwc3_complete,
 928
 929         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
 930 };
 931
 932 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
 933 #else
 934 #define DWC3_PM_OPS     NULL
 935 #endif
 936
 937 #ifdef CONFIG_OF
 938 static const struct of_device_id of_dwc3_match[] = {
 939         {
 940                 .compatible = "snps,dwc3"
 941         },
 942         {
 943                 .compatible = "synopsys,dwc3"
 944         },
 945         { },
 946 };
 947 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 948 #endif
 949
 950 static struct platform_driver dwc3_driver = {
 951         .probe          = dwc3_probe,
 952         .remove         = dwc3_remove,
 953         .driver         = {
 954                 .name   = "dwc3",
 955                 .of_match_table = of_match_ptr(of_dwc3_match),
 956                 .pm     = DWC3_PM_OPS,
 957         },
 958 };
 959
 960 module_platform_driver(dwc3_driver);
 961
 962 MODULE_ALIAS("platform:dwc3");
 963 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 964 MODULE_LICENSE("GPL v2");
 965 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");