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FROMLIST: arm64: mm: Rename post_ttbr0_update_workaround
authorWill Deacon <will.deacon@arm.com>
Thu, 10 Aug 2017 12:34:30 +0000 (13:34 +0100)
committerGreg Hackmann <ghackmann@google.com>
Thu, 18 Jan 2018 18:18:51 +0000 (18:18 +0000)
The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1.
Since we're using TTBR1 for the ASID, rename the hook to make it clearer
as to what it's doing.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Laura Abbott <labbott@redhat.com>
Tested-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
 commit 158d495899ce55db453f682a8ac8390d5a426578)

Change-Id: Iaf152ca1bd0a20bd15a77afac4ad4e9ea8ada08f
Signed-off-by: Greg Hackmann <ghackmann@google.com>
arch/arm64/include/asm/assembler.h
arch/arm64/kernel/entry.S
arch/arm64/mm/proc.S

index e450bb6..610c6b5 100644 (file)
@@ -399,9 +399,9 @@ alternative_endif
        .endm
 
 /*
- * Errata workaround post TTBR0_EL1 update.
+ * Errata workaround post TTBRx_EL1 update.
  */
-       .macro  post_ttbr0_update_workaround
+       .macro  post_ttbr_update_workaround
 #ifdef CONFIG_CAVIUM_ERRATUM_27456
 alternative_if ARM64_WORKAROUND_CAVIUM_27456
        ic      iallu
index 434ef71..2856104 100644 (file)
@@ -241,7 +241,7 @@ alternative_else_nop_endif
         * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
         * corruption).
         */
-       post_ttbr0_update_workaround
+       post_ttbr_update_workaround
        .endif
 1:
        .if     \el != 0
index 2e1e253..b06a797 100644 (file)
@@ -145,7 +145,7 @@ ENTRY(cpu_do_switch_mm)
        isb
        msr     ttbr0_el1, x0                   // now update TTBR0
        isb
-       post_ttbr0_update_workaround
+       post_ttbr_update_workaround
        ret
 ENDPROC(cpu_do_switch_mm)