4 * ADデータSPIエンディアン MSB first
6 #include <p24FJ64GA004.h>
15 // AD DRDY0 INTフラグ 1=INTかかった 0=なし
16 static char ad_drdy0_int;
18 void ad_drdy0_intf_set(void)
22 void ad_drdy0_intf_clear(void)
26 char ad_is_drdy0_intf(void)
28 if (ad_drdy0_int == 1) {
48 void ad_cs(unsigned char cs)
53 for(i = 16; i > 0; i--) {
76 for(i = 16; i > 0; i--) {
91 PORTBbits.RB10 = 1; // -AD RESET
93 PORTBbits.RB10 = 0; // -AD RESET
95 PORTBbits.RB10 = 1; // -AD RESET
99 PORTBbits.RB11 = 1; // +AD START
101 PORTBbits.RB11 = 0; // +AD START
104 void ad_spi_send(unsigned char c)
106 while(spi1_tx_fifo_is_full());
110 unsigned char ad_spi_rcv(void)
112 spi1_rx_overrun_clear();
113 while(spi1_tx_fifo_is_full());
119 while(!spi1_rx_fifo_is_full());
127 for(i = 0; i < AD_CHNUM; i++) {
129 //1. Send the SDATAC command <11h>. This command cancels the RDATAC mode. RDATAC mode must be
130 //cancelled before the register write commands.
133 ad_spi_send(ADCMD_SDATAC);
135 //2. Send the register write command. The following example shows the register write as a block of nine bytes,
136 //starting at register 0 (CONFIG0).
138 ad_spi_send(ADCMD_WREG | 0); // Register write command
139 ad_spi_send(9 - 1); // 9byte write
140 // CONFIG0: RFBIAS OFF, SPI timeout enable
141 // Bit 2 RBIAS: Internal reference bias
142 // 0 = Internal reference bias disabled
143 // 1 = Internal reference bias enabled (default)
144 // Bit 0 SPI: SCLK timeout of SPI interface
145 // 0 = SPI timeout disabled
146 // 1 = SPI timeout enabled (default), when SCLK is held low for 216 clock cycles
148 ad_spi_send(0b00000101);
149 // CONFIG1: sinc1 filter, EXTREF ON, START delay = 0
150 // Bit 6 CHKSUM: Checksum
151 // 0 = Disabled (default)
152 // 1 = Conversion data checksum byte included in readback
153 // Bit 4 SINC2: Digital filter mode
154 // 0 = sinc1 filter (default)
156 // Bit 3 EXTREF: Reference select
158 // 1 = External (default)
159 // Bits 2-0 DELAY[2:0]: START conversion delay
160 // 000 = No delay (default)
162 ad_spi_send(0b00001000);
165 // CONFIG2: SYNCOUT ON, Gate control, DataRate=10Hz
166 // Bit 5 SYNCOUT: SYNCOUT clock enable
167 // 0 = SYNCOUT disabled (default)
168 // 1 = SYNCOUT enabled
169 // Bit 4 PULSE: Conversion Control mode select
170 // 0 = Gate Control mode (default)
171 // 1 = Pulse Control mode
172 // Bits 2-0 DR[2:0] Data rate setting
173 // 000 = 10SPS (default)
181 // NOTE: fCLK = 7.3728MHz
182 unsigned char rate_bit;
185 rate_bit = 0b00000010;
188 rate_bit = 0b00000100;
192 rate_bit = 0b00000000;
196 ad_spi_send(0b00100000 | rate_bit);
198 // OFC0,1,2: no offset correction
203 // FSC0,1,2: no full scale correction
206 ad_spi_send(0b01000000);
210 // 4. Take the START pin high or send the START command to start conversions.
211 ad_start_ena(); // +AD START
213 for(i = 0; i < AD_CHNUM; i++) {
215 //5. Optionally, send the RDATAC command <10h>. This permits reading of conversion data without the need of
216 //the read data command. Otherwise, the read data opcode must be sent to read each conversion result.
218 ad_spi_send(ADCMD_RDATAC);
231 for(i = 0; i < AD_CHNUM; i++) {
245 ad_spi_send(0x40); //(BUF OFF)
249 //Register 8: GPIO Configuration Register
250 //使わないpinはoutput(=1)にする
251 //bit6 GPIO6(SYNCIN) input(=0)
254 ad_spi_send(0b00111111);
257 //Register 12: Special Functions Register
258 //bit6 SYNCin=1 SYNCIN(GPIO6) Enable
261 ad_spi_send(0b01000000);