1 #include <p24FJ64GA004.h>
6 void spi1_rx_fifo_clear(void)
10 for(i = 0; i < 16; i++) c = SPI1BUF;
12 void spi2_rx_fifo_clear(void)
16 for(i = 0; i < 16; i++) c = SPI2BUF;
29 //1. Clear the SPIxBUF register.
30 for(i = 0; i < 16; i++) c = SPI1BUF;
33 //2. Write the desired settings to the SPIxCON register with MSTEN (SPIxCON1<5>) = 1.
34 // bit12 DISSCK=0 0=Internal SPI clock is enabled
35 // bit11 DISSDO=0 0 = SDOx pin is controlled by the module
36 // bit10 MODE16=0 8bit
39 // 1 = Input data sampled at end of data output time
40 // 0 = Input data sampled at middle of data output time
41 // bit8 CKE=0 DATA CHANGE=CLK Idle to Active =LtoH
42 // bit7 SSEN=0 SS pin disable
43 // bit6 CKP=0 CLK IDLE=LOW
44 // bit5 MSTEN=1 Master
45 // bit4-2 SPRE=0b111 Secondary Prescale 1:1
46 // 111 = Secondary prescale 1:1
47 // 110 = Secondary prescale 2:1
49 // 000 = Secondary prescale 8:1
50 // bit1-0 PPRE=0b01 Primarily Prescale 4:1
51 // 11 = Primary prescale 1:1
52 // 10 = Primary prescale 4:1
53 // 01 = Primary prescale 16:1
54 // 00 = Primary prescale 64:1
56 SPI1CON1 = 0b0000000000111110;
58 // Enahanced Buffer(FIFO) Disable
59 // bit0 SPIBEN: Enhanced Buffer Enable bit
60 // 1 = Enhanced Buffer enabled
61 // 0 = Enhanced Buffer disabled (Legacy mode)
63 // SPI1CON2bits.SPIBEN = 1;
65 // bit 4-2 SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
66 // 001 = Interrupt when data is available in receive buffer (SRMPT bit is set)
67 // SPI1STATbits.SISEL = 0b001;
69 //3. Clear the SPIROV bit (SPIxSTAT<6>).
70 SPI1STATbits.SPIROV = 0;
72 //4. Enable SPIx operation by setting the SPIEN bit (SPIxSTAT<15>).
73 SPI1STATbits.SPIEN = 1;
89 //1. Clear the SPIxBUF register.
90 for(i = 0; i < 16; i++) c = SPI2BUF;
91 //2. If using interrupts:
92 //• Clear the SPIxIF bit in the respective IFSx register.
94 //• Set the SPIxIE bit in the respective IECx register.
95 //• Write the SPIxIP bits in the respective IPCx register to set the interrupt priority.
98 // 0b100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot
100 SPI2STATbits.SISEL = 0b100;
102 //3. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0.
103 // SLAVE,8bit,CLK IDLE=LOW, DATA CHANGE=CLK HtoL, SS pin enable
105 // SPI1CON1 = 0b0000000110000000;
106 SPI2CON1 = 0b0000000100000000;
107 // Enahanced Buffer(FIFO) Disable
109 //4. Clear the SMP bit. SPI1CON1<9>
110 SPI2CON1bits.SMP = 0;
111 //5. If the CKE<8> bit is set, then the SSEN<7> bit must be set, thus enabling the SSx pin.
112 SPI2CON1bits.SSEN = 1;
113 //6. Clear the SPIROV bit (SPIxSTAT<6>).
114 SPI2STATbits.SPIROV = 0;
115 //7. Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>).
116 SPI2CON2bits.SPIBEN = 1;
118 //8. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>).
119 SPI2STATbits.SPIEN = 1;