1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
14 #include <linux/bitmap.h>
15 #include <linux/types.h>
16 #include <linux/jump_label.h>
17 #include <linux/kvm_types.h>
18 #include <linux/percpu.h>
19 #include <asm/arch_gicv3.h>
20 #include <asm/barrier.h>
21 #include <asm/cpufeature.h>
22 #include <asm/cputype.h>
23 #include <asm/daifflags.h>
24 #include <asm/fpsimd.h>
26 #include <asm/kvm_asm.h>
27 #include <asm/thread_info.h>
29 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
31 #define KVM_USER_MEM_SLOTS 512
32 #define KVM_HALT_POLL_NS_DEFAULT 500000
34 #include <kvm/arm_vgic.h>
35 #include <kvm/arm_arch_timer.h>
36 #include <kvm/arm_pmu.h>
38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
40 #define KVM_VCPU_MAX_FEATURES 7
42 #define KVM_REQ_SLEEP \
43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
49 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
50 KVM_DIRTY_LOG_INITIALLY_SET)
52 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
54 extern unsigned int kvm_sve_max_vl;
55 int kvm_arm_init_sve(void);
57 int __attribute_const__ kvm_target_cpu(void);
58 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
59 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
60 int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext);
61 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
64 /* The VMID generation used for the virt. memory system */
72 /* stage2 entry level table */
76 /* VTCR_EL2 value for this VM */
79 /* The last vcpu id that ran on each physical CPU */
80 int __percpu *last_vcpu_ran;
82 /* The maximum number of vCPUs depends on the used GIC model */
85 /* Interrupt controller */
86 struct vgic_dist vgic;
88 /* Mandated version of PSCI */
92 * If we encounter a data abort without valid instruction syndrome
93 * information, report this to user space. User space can (and
94 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
97 bool return_nisv_io_abort_to_user;
100 #define KVM_NR_MEM_OBJS 40
103 * We don't want allocation failures within the mmu code, so we preallocate
104 * enough memory for a single page fault in a cache.
106 struct kvm_mmu_memory_cache {
108 void *objects[KVM_NR_MEM_OBJS];
111 struct kvm_vcpu_fault_info {
112 u32 esr_el2; /* Hyp Syndrom Register */
113 u64 far_el2; /* Hyp Fault Address Register */
114 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
115 u64 disr_el1; /* Deferred [SError] Status Register */
119 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
120 MPIDR_EL1, /* MultiProcessor Affinity Register */
121 CSSELR_EL1, /* Cache Size Selection Register */
122 SCTLR_EL1, /* System Control Register */
123 ACTLR_EL1, /* Auxiliary Control Register */
124 CPACR_EL1, /* Coprocessor Access Control */
125 ZCR_EL1, /* SVE Control */
126 TTBR0_EL1, /* Translation Table Base Register 0 */
127 TTBR1_EL1, /* Translation Table Base Register 1 */
128 TCR_EL1, /* Translation Control Register */
129 ESR_EL1, /* Exception Syndrome Register */
130 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
131 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
132 FAR_EL1, /* Fault Address Register */
133 MAIR_EL1, /* Memory Attribute Indirection Register */
134 VBAR_EL1, /* Vector Base Address Register */
135 CONTEXTIDR_EL1, /* Context ID Register */
136 TPIDR_EL0, /* Thread ID, User R/W */
137 TPIDRRO_EL0, /* Thread ID, User R/O */
138 TPIDR_EL1, /* Thread ID, Privileged */
139 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
140 CNTKCTL_EL1, /* Timer Control Register (EL1) */
141 PAR_EL1, /* Physical Address Register */
142 MDSCR_EL1, /* Monitor Debug System Control Register */
143 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
144 DISR_EL1, /* Deferred Interrupt Status Register */
146 /* Performance Monitors Registers */
147 PMCR_EL0, /* Control Register */
148 PMSELR_EL0, /* Event Counter Selection Register */
149 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
150 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
151 PMCCNTR_EL0, /* Cycle Counter Register */
152 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
153 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
154 PMCCFILTR_EL0, /* Cycle Count Filter Register */
155 PMCNTENSET_EL0, /* Count Enable Set Register */
156 PMINTENSET_EL1, /* Interrupt Enable Set Register */
157 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
158 PMSWINC_EL0, /* Software Increment Register */
159 PMUSERENR_EL0, /* User Enable Register */
161 /* Pointer Authentication Registers in a strict increasing order. */
173 /* 32bit specific registers. Keep them at the end of the range */
174 DACR32_EL2, /* Domain Access Control Register */
175 IFSR32_EL2, /* Instruction Fault Status Register */
176 FPEXC32_EL2, /* Floating-Point Exception Control Register */
177 DBGVCR32_EL2, /* Debug Vector Catch Register */
179 NR_SYS_REGS /* Nothing after this line! */
183 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
184 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
185 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
186 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
187 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
188 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
189 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
190 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
191 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
192 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
193 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
194 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
195 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
196 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
197 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
198 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
199 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
200 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
201 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
202 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
203 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
204 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
205 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
206 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
207 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
208 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
209 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
210 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
211 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
213 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
214 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
215 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
216 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
217 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
218 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
219 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
221 #define NR_COPRO_REGS (NR_SYS_REGS * 2)
223 struct kvm_cpu_context {
224 struct kvm_regs gp_regs;
226 u64 sys_regs[NR_SYS_REGS];
227 u32 copro[NR_COPRO_REGS];
230 struct kvm_vcpu *__hyp_running_vcpu;
233 struct kvm_pmu_events {
238 struct kvm_host_data {
239 struct kvm_cpu_context host_ctxt;
240 struct kvm_pmu_events pmu_events;
243 typedef struct kvm_host_data kvm_host_data_t;
245 struct vcpu_reset_state {
252 struct kvm_vcpu_arch {
253 struct kvm_cpu_context ctxt;
255 unsigned int sve_max_vl;
257 /* HYP configuration */
261 /* Exception Information */
262 struct kvm_vcpu_fault_info fault;
264 /* State of various workarounds, see kvm_asm.h for bit assignment */
265 u64 workaround_flags;
267 /* Miscellaneous vcpu state flags */
271 * We maintain more than a single set of debug registers to support
272 * debugging the guest from the host and to maintain separate host and
273 * guest state during world switches. vcpu_debug_state are the debug
274 * registers of the vcpu as the guest sees them. host_debug_state are
275 * the host registers which are saved and restored during
276 * world switches. external_debug_state contains the debug
277 * values we want to debug the guest. This is set via the
278 * KVM_SET_GUEST_DEBUG ioctl.
280 * debug_ptr points to the set of debug registers that should be loaded
281 * onto the hardware when running the guest.
283 struct kvm_guest_debug_arch *debug_ptr;
284 struct kvm_guest_debug_arch vcpu_debug_state;
285 struct kvm_guest_debug_arch external_debug_state;
287 /* Pointer to host CPU context */
288 struct kvm_cpu_context *host_cpu_context;
290 struct thread_info *host_thread_info; /* hyp VA */
291 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
294 /* {Break,watch}point registers */
295 struct kvm_guest_debug_arch regs;
296 /* Statistical profiling extension */
301 struct vgic_cpu vgic_cpu;
302 struct arch_timer_cpu timer_cpu;
306 * Anything that is not used directly from assembly code goes
311 * Guest registers we preserve during guest debugging.
313 * These shadow registers are updated by the kvm_handle_sys_reg
314 * trap handler if the guest accesses or updates them while we
315 * are using guest debug.
319 } guest_debug_preserved;
321 /* vcpu power-off state */
324 /* Don't run the guest (internal implementation need) */
327 /* Cache some mmu pages needed inside spinlock regions */
328 struct kvm_mmu_memory_cache mmu_page_cache;
330 /* Target CPU and feature flags */
332 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
334 /* Detect first run of a vcpu */
337 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
340 /* Additional reset state */
341 struct vcpu_reset_state reset_state;
343 /* True when deferrable sysregs are loaded on the physical CPU,
344 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
345 bool sysregs_loaded_on_cpu;
355 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
356 #define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \
357 sve_ffr_offset((vcpu)->arch.sve_max_vl)))
359 #define vcpu_sve_state_size(vcpu) ({ \
361 unsigned int __vcpu_vq; \
363 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
366 __vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \
367 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
373 /* vcpu_arch flags field values: */
374 #define KVM_ARM64_DEBUG_DIRTY (1 << 0)
375 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */
376 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */
377 #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */
378 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */
379 #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */
380 #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */
381 #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */
383 #define vcpu_has_sve(vcpu) (system_supports_sve() && \
384 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE))
386 #define vcpu_has_ptrauth(vcpu) ((system_supports_address_auth() || \
387 system_supports_generic_auth()) && \
388 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH))
390 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
393 * Only use __vcpu_sys_reg if you know you want the memory backed version of a
394 * register, and not the one most recently accessed by a running VCPU. For
395 * example, for userspace access or for system registers that are never context
396 * switched, but only emulated.
398 #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
400 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
401 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
404 * CP14 and CP15 live in the same array, as they are backed by the
405 * same system registers.
407 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
408 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
411 ulong remote_tlb_flush;
414 struct kvm_vcpu_stat {
415 u64 halt_successful_poll;
416 u64 halt_attempted_poll;
417 u64 halt_poll_success_ns;
418 u64 halt_poll_fail_ns;
419 u64 halt_poll_invalid;
425 u64 mmio_exit_kernel;
429 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
430 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
431 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
432 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
433 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
434 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
435 struct kvm_vcpu_events *events);
437 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
438 struct kvm_vcpu_events *events);
440 #define KVM_ARCH_WANT_MMU_NOTIFIER
441 int kvm_unmap_hva_range(struct kvm *kvm,
442 unsigned long start, unsigned long end);
443 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
444 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
445 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
447 void kvm_arm_halt_guest(struct kvm *kvm);
448 void kvm_arm_resume_guest(struct kvm *kvm);
450 u64 __kvm_call_hyp(void *hypfn, ...);
453 * The couple of isb() below are there to guarantee the same behaviour
454 * on VHE as on !VHE, where the eret to EL1 acts as a context
455 * synchronization event.
457 #define kvm_call_hyp(f, ...) \
463 __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \
467 #define kvm_call_hyp_ret(f, ...) \
469 typeof(f(__VA_ARGS__)) ret; \
472 ret = f(__VA_ARGS__); \
475 ret = __kvm_call_hyp(kvm_ksym_ref(f), \
482 void force_vm_exit(const cpumask_t *mask);
483 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
485 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
486 int exception_index);
487 void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
488 int exception_index);
491 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
492 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
494 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
495 int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
496 phys_addr_t fault_ipa);
498 int kvm_perf_init(void);
499 int kvm_perf_teardown(void);
501 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
502 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
503 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
505 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
506 struct kvm_device_attr *attr);
507 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
508 struct kvm_device_attr *attr);
509 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
510 struct kvm_device_attr *attr);
512 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
514 vcpu_arch->steal.base = GPA_INVALID;
517 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
519 return (vcpu_arch->steal.base != GPA_INVALID);
522 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
524 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
526 DECLARE_PER_CPU(kvm_host_data_t, kvm_host_data);
528 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
530 /* The host's MPIDR is immutable, so let's set it up at boot time */
531 cpu_ctxt->sys_regs[MPIDR_EL1] = read_cpuid_mpidr();
534 static inline bool kvm_arch_requires_vhe(void)
537 * The Arm architecture specifies that implementation of SVE
538 * requires VHE also to be implemented. The KVM code for arm64
539 * relies on this when SVE is present:
541 if (system_supports_sve())
547 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
549 static inline void kvm_arch_hardware_unsetup(void) {}
550 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
551 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
552 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
554 void kvm_arm_init_debug(void);
555 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
556 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
557 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
558 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
559 struct kvm_device_attr *attr);
560 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
561 struct kvm_device_attr *attr);
562 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
563 struct kvm_device_attr *attr);
565 /* Guest/host FPSIMD coordination helpers */
566 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
567 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
568 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
569 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
571 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
573 return (!has_vhe() && attr->exclude_host);
576 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
577 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
579 return kvm_arch_vcpu_run_map_fp(vcpu);
582 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
583 void kvm_clr_pmu_events(u32 clr);
585 void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
586 void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
588 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
589 static inline void kvm_clr_pmu_events(u32 clr) {}
592 #define KVM_BP_HARDEN_UNKNOWN -1
593 #define KVM_BP_HARDEN_WA_NEEDED 0
594 #define KVM_BP_HARDEN_NOT_REQUIRED 1
596 static inline int kvm_arm_harden_branch_predictor(void)
598 switch (get_spectre_v2_workaround_state()) {
599 case ARM64_BP_HARDEN_WA_NEEDED:
600 return KVM_BP_HARDEN_WA_NEEDED;
601 case ARM64_BP_HARDEN_NOT_REQUIRED:
602 return KVM_BP_HARDEN_NOT_REQUIRED;
603 case ARM64_BP_HARDEN_UNKNOWN:
605 return KVM_BP_HARDEN_UNKNOWN;
609 #define KVM_SSBD_UNKNOWN -1
610 #define KVM_SSBD_FORCE_DISABLE 0
611 #define KVM_SSBD_KERNEL 1
612 #define KVM_SSBD_FORCE_ENABLE 2
613 #define KVM_SSBD_MITIGATED 3
615 static inline int kvm_arm_have_ssbd(void)
617 switch (arm64_get_ssbd_state()) {
618 case ARM64_SSBD_FORCE_DISABLE:
619 return KVM_SSBD_FORCE_DISABLE;
620 case ARM64_SSBD_KERNEL:
621 return KVM_SSBD_KERNEL;
622 case ARM64_SSBD_FORCE_ENABLE:
623 return KVM_SSBD_FORCE_ENABLE;
624 case ARM64_SSBD_MITIGATED:
625 return KVM_SSBD_MITIGATED;
626 case ARM64_SSBD_UNKNOWN:
628 return KVM_SSBD_UNKNOWN;
632 void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
633 void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
635 int kvm_set_ipa_limit(void);
637 #define __KVM_HAVE_ARCH_VM_ALLOC
638 struct kvm *kvm_arch_alloc_vm(void);
639 void kvm_arch_free_vm(struct kvm *kvm);
641 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type);
643 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
644 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
646 #define kvm_arm_vcpu_sve_finalized(vcpu) \
647 ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED)
649 #endif /* __ARM64_KVM_HOST_H__ */