arch/x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13 #include <asm/page.h>
  14
  15 /*
  16  * While not explicitly listed in the TLFS, Hyper-V always runs with a page size
  17  * of 4096. These definitions are used when communicating with Hyper-V using
  18  * guest physical pages and guest physical page addresses, since the guest page
  19  * size may not be 4096 on all architectures.
  20  */
  21 #define HV_HYP_PAGE_SHIFT      12
  22 #define HV_HYP_PAGE_SIZE       BIT(HV_HYP_PAGE_SHIFT)
  23 #define HV_HYP_PAGE_MASK       (~(HV_HYP_PAGE_SIZE - 1))
  24
  25 /*
  26  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  27  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  28  */
  29 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  30 #define HYPERV_CPUID_INTERFACE                  0x40000001
  31 #define HYPERV_CPUID_VERSION                    0x40000002
  32 #define HYPERV_CPUID_FEATURES                   0x40000003
  33 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  34 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  35 #define HYPERV_CPUID_NESTED_FEATURES            0x4000000A
  36
  37 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  38 #define HYPERV_CPUID_MIN                        0x40000005
  39 #define HYPERV_CPUID_MAX                        0x4000ffff
  40
  41 /*
  42  * Feature identification. EAX indicates which features are available
  43  * to the partition based upon the current partition privileges.
  44  * These are HYPERV_CPUID_FEATURES.EAX bits.
  45  */
  46
  47 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */
  48 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         BIT(0)
  49 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/
  50 #define HV_MSR_TIME_REF_COUNT_AVAILABLE         BIT(1)
  51 /*
  52  * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM
  53  * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available
  54  */
  55 #define HV_X64_MSR_SYNIC_AVAILABLE              BIT(2)
  56 /*
  57  * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through
  58  * HV_X64_MSR_STIMER3_COUNT) available
  59  */
  60 #define HV_MSR_SYNTIMER_AVAILABLE               BIT(3)
  61 /*
  62  * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
  63  * are available
  64  */
  65 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        BIT(4)
  66 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/
  67 #define HV_X64_MSR_HYPERCALL_AVAILABLE          BIT(5)
  68 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/
  69 #define HV_X64_MSR_VP_INDEX_AVAILABLE           BIT(6)
  70 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/
  71 #define HV_X64_MSR_RESET_AVAILABLE              BIT(7)
  72 /*
  73  * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE,
  74  * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE,
  75  * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available
  76  */
  77 #define HV_X64_MSR_STAT_PAGES_AVAILABLE         BIT(8)
  78 /* Partition reference TSC MSR is available */
  79 #define HV_MSR_REFERENCE_TSC_AVAILABLE          BIT(9)
  80 /* Partition Guest IDLE MSR is available */
  81 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE         BIT(10)
  82 /*
  83  * There is a single feature flag that signifies if the partition has access
  84  * to MSRs with local APIC and TSC frequencies.
  85  */
  86 #define HV_X64_ACCESS_FREQUENCY_MSRS            BIT(11)
  87 /* AccessReenlightenmentControls privilege */
  88 #define HV_X64_ACCESS_REENLIGHTENMENT           BIT(13)
  89 /* AccessTscInvariantControls privilege */
  90 #define HV_X64_ACCESS_TSC_INVARIANT             BIT(15)
  91
  92 /*
  93  * Feature identification: indicates which flags were specified at partition
  94  * creation. The format is the same as the partition creation flag structure
  95  * defined in section Partition Creation Flags.
  96  * These are HYPERV_CPUID_FEATURES.EBX bits.
  97  */
  98 #define HV_X64_CREATE_PARTITIONS                BIT(0)
  99 #define HV_X64_ACCESS_PARTITION_ID              BIT(1)
 100 #define HV_X64_ACCESS_MEMORY_POOL               BIT(2)
 101 #define HV_X64_ADJUST_MESSAGE_BUFFERS           BIT(3)
 102 #define HV_X64_POST_MESSAGES                    BIT(4)
 103 #define HV_X64_SIGNAL_EVENTS                    BIT(5)
 104 #define HV_X64_CREATE_PORT                      BIT(6)
 105 #define HV_X64_CONNECT_PORT                     BIT(7)
 106 #define HV_X64_ACCESS_STATS                     BIT(8)
 107 #define HV_X64_DEBUGGING                        BIT(11)
 108 #define HV_X64_CPU_POWER_MANAGEMENT             BIT(12)
 109
 110 /*
 111  * Feature identification. EDX indicates which miscellaneous features
 112  * are available to the partition.
 113  * These are HYPERV_CPUID_FEATURES.EDX bits.
 114  */
 115 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
 116 #define HV_X64_MWAIT_AVAILABLE                          BIT(0)
 117 /* Guest debugging support is available */
 118 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                BIT(1)
 119 /* Performance Monitor support is available*/
 120 #define HV_X64_PERF_MONITOR_AVAILABLE                   BIT(2)
 121 /* Support for physical CPU dynamic partitioning events is available*/
 122 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       BIT(3)
 123 /*
 124  * Support for passing hypercall input parameter block via XMM
 125  * registers is available
 126  */
 127 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           BIT(4)
 128 /* Support for a virtual guest idle state is available */
 129 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               BIT(5)
 130 /* Frequency MSRs available */
 131 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE             BIT(8)
 132 /* Crash MSR available */
 133 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE            BIT(10)
 134 /* stimer Direct Mode is available */
 135 #define HV_STIMER_DIRECT_MODE_AVAILABLE                 BIT(19)
 136
 137 /*
 138  * Implementation recommendations. Indicates which behaviors the hypervisor
 139  * recommends the OS implement for optimal performance.
 140  * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
 141  */
 142 /*
 143  * Recommend using hypercall for address space switches rather
 144  * than MOV to CR3 instruction
 145  */
 146 #define HV_X64_AS_SWITCH_RECOMMENDED                    BIT(0)
 147 /* Recommend using hypercall for local TLB flushes rather
 148  * than INVLPG or MOV to CR3 instructions */
 149 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED              BIT(1)
 150 /*
 151  * Recommend using hypercall for remote TLB flushes rather
 152  * than inter-processor interrupts
 153  */
 154 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED             BIT(2)
 155 /*
 156  * Recommend using MSRs for accessing APIC registers
 157  * EOI, ICR and TPR rather than their memory-mapped counterparts
 158  */
 159 #define HV_X64_APIC_ACCESS_RECOMMENDED                  BIT(3)
 160 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
 161 #define HV_X64_SYSTEM_RESET_RECOMMENDED                 BIT(4)
 162 /*
 163  * Recommend using relaxed timing for this partition. If used,
 164  * the VM should disable any watchdog timeouts that rely on the
 165  * timely delivery of external interrupts
 166  */
 167 #define HV_X64_RELAXED_TIMING_RECOMMENDED               BIT(5)
 168
 169 /*
 170  * Recommend not using Auto End-Of-Interrupt feature
 171  */
 172 #define HV_DEPRECATING_AEOI_RECOMMENDED                 BIT(9)
 173
 174 /*
 175  * Recommend using cluster IPI hypercalls.
 176  */
 177 #define HV_X64_CLUSTER_IPI_RECOMMENDED                  BIT(10)
 178
 179 /* Recommend using the newer ExProcessorMasks interface */
 180 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED           BIT(11)
 181
 182 /* Recommend using enlightened VMCS */
 183 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED             BIT(14)
 184
 185 /*
 186  * Virtual processor will never share a physical core with another virtual
 187  * processor, except for virtual processors that are reported as sibling SMT
 188  * threads.
 189  */
 190 #define HV_X64_NO_NONARCH_CORESHARING                  BIT(18)
 191
 192 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
 193 #define HV_X64_NESTED_DIRECT_FLUSH                      BIT(17)
 194 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH               BIT(18)
 195 #define HV_X64_NESTED_MSR_BITMAP                        BIT(19)
 196
 197 /* Hyper-V specific model specific registers (MSRs) */
 198
 199 /* MSR used to identify the guest OS. */
 200 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 201
 202 /* MSR used to setup pages used to communicate with the hypervisor. */
 203 #define HV_X64_MSR_HYPERCALL                    0x40000001
 204
 205 /* MSR used to provide vcpu index */
 206 #define HV_X64_MSR_VP_INDEX                     0x40000002
 207
 208 /* MSR used to reset the guest OS. */
 209 #define HV_X64_MSR_RESET                        0x40000003
 210
 211 /* MSR used to provide vcpu runtime in 100ns units */
 212 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 213
 214 /* MSR used to read the per-partition time reference counter */
 215 #define HV_X64_MSR_TIME_REF_COUNT               0x40000020
 216
 217 /* A partition's reference time stamp counter (TSC) page */
 218 #define HV_X64_MSR_REFERENCE_TSC                0x40000021
 219
 220 /* MSR used to retrieve the TSC frequency */
 221 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 222
 223 /* MSR used to retrieve the local APIC timer frequency */
 224 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 225
 226 /* Define the virtual APIC registers */
 227 #define HV_X64_MSR_EOI                          0x40000070
 228 #define HV_X64_MSR_ICR                          0x40000071
 229 #define HV_X64_MSR_TPR                          0x40000072
 230 #define HV_X64_MSR_VP_ASSIST_PAGE               0x40000073
 231
 232 /* Define synthetic interrupt controller model specific registers. */
 233 #define HV_X64_MSR_SCONTROL                     0x40000080
 234 #define HV_X64_MSR_SVERSION                     0x40000081
 235 #define HV_X64_MSR_SIEFP                        0x40000082
 236 #define HV_X64_MSR_SIMP                         0x40000083
 237 #define HV_X64_MSR_EOM                          0x40000084
 238 #define HV_X64_MSR_SINT0                        0x40000090
 239 #define HV_X64_MSR_SINT1                        0x40000091
 240 #define HV_X64_MSR_SINT2                        0x40000092
 241 #define HV_X64_MSR_SINT3                        0x40000093
 242 #define HV_X64_MSR_SINT4                        0x40000094
 243 #define HV_X64_MSR_SINT5                        0x40000095
 244 #define HV_X64_MSR_SINT6                        0x40000096
 245 #define HV_X64_MSR_SINT7                        0x40000097
 246 #define HV_X64_MSR_SINT8                        0x40000098
 247 #define HV_X64_MSR_SINT9                        0x40000099
 248 #define HV_X64_MSR_SINT10                       0x4000009A
 249 #define HV_X64_MSR_SINT11                       0x4000009B
 250 #define HV_X64_MSR_SINT12                       0x4000009C
 251 #define HV_X64_MSR_SINT13                       0x4000009D
 252 #define HV_X64_MSR_SINT14                       0x4000009E
 253 #define HV_X64_MSR_SINT15                       0x4000009F
 254
 255 /*
 256  * Synthetic Timer MSRs. Four timers per vcpu.
 257  */
 258 #define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
 259 #define HV_X64_MSR_STIMER0_COUNT                0x400000B1
 260 #define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
 261 #define HV_X64_MSR_STIMER1_COUNT                0x400000B3
 262 #define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
 263 #define HV_X64_MSR_STIMER2_COUNT                0x400000B5
 264 #define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
 265 #define HV_X64_MSR_STIMER3_COUNT                0x400000B7
 266
 267 /* Hyper-V guest idle MSR */
 268 #define HV_X64_MSR_GUEST_IDLE                   0x400000F0
 269
 270 /* Hyper-V guest crash notification MSR's */
 271 #define HV_X64_MSR_CRASH_P0                     0x40000100
 272 #define HV_X64_MSR_CRASH_P1                     0x40000101
 273 #define HV_X64_MSR_CRASH_P2                     0x40000102
 274 #define HV_X64_MSR_CRASH_P3                     0x40000103
 275 #define HV_X64_MSR_CRASH_P4                     0x40000104
 276 #define HV_X64_MSR_CRASH_CTL                    0x40000105
 277
 278 /* TSC emulation after migration */
 279 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 280 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 281 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 282
 283 /* TSC invariant control */
 284 #define HV_X64_MSR_TSC_INVARIANT_CONTROL        0x40000118
 285
 286 /*
 287  * Declare the MSR used to setup pages used to communicate with the hypervisor.
 288  */
 289 union hv_x64_msr_hypercall_contents {
 290         u64 as_uint64;
 291         struct {
 292                 u64 enable:1;
 293                 u64 reserved:11;
 294                 u64 guest_physical_address:52;
 295         } __packed;
 296 };
 297
 298 /*
 299  * TSC page layout.
 300  */
 301 struct ms_hyperv_tsc_page {
 302         volatile u32 tsc_sequence;
 303         u32 reserved1;
 304         volatile u64 tsc_scale;
 305         volatile s64 tsc_offset;
 306         u64 reserved2[509];
 307 }  __packed;
 308
 309 /*
 310  * The guest OS needs to register the guest ID with the hypervisor.
 311  * The guest ID is a 64 bit entity and the structure of this ID is
 312  * specified in the Hyper-V specification:
 313  *
 314  * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx
 315  *
 316  * While the current guideline does not specify how Linux guest ID(s)
 317  * need to be generated, our plan is to publish the guidelines for
 318  * Linux and other guest operating systems that currently are hosted
 319  * on Hyper-V. The implementation here conforms to this yet
 320  * unpublished guidelines.
 321  *
 322  *
 323  * Bit(s)
 324  * 63 - Indicates if the OS is Open Source or not; 1 is Open Source
 325  * 62:56 - Os Type; Linux is 0x100
 326  * 55:48 - Distro specific identification
 327  * 47:16 - Linux kernel version number
 328  * 15:0  - Distro specific identification
 329  *
 330  *
 331  */
 332
 333 #define HV_LINUX_VENDOR_ID              0x8100
 334
 335 struct hv_reenlightenment_control {
 336         __u64 vector:8;
 337         __u64 reserved1:8;
 338         __u64 enabled:1;
 339         __u64 reserved2:15;
 340         __u64 target_vp:32;
 341 }  __packed;
 342
 343 struct hv_tsc_emulation_control {
 344         __u64 enabled:1;
 345         __u64 reserved:63;
 346 } __packed;
 347
 348 struct hv_tsc_emulation_status {
 349         __u64 inprogress:1;
 350         __u64 reserved:63;
 351 } __packed;
 352
 353 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 354 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 355 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 356                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 357
 358 /*
 359  * Crash notification (HV_X64_MSR_CRASH_CTL) flags.
 360  */
 361 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG           BIT_ULL(62)
 362 #define HV_CRASH_CTL_CRASH_NOTIFY               BIT_ULL(63)
 363 #define HV_X64_MSR_CRASH_PARAMS         \
 364                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 365
 366 #define HV_IPI_LOW_VECTOR       0x10
 367 #define HV_IPI_HIGH_VECTOR      0xff
 368
 369 /* Declare the various hypercall operations. */
 370 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE      0x0002
 371 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST       0x0003
 372 #define HVCALL_NOTIFY_LONG_SPIN_WAIT            0x0008
 373 #define HVCALL_SEND_IPI                         0x000b
 374 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX  0x0013
 375 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX   0x0014
 376 #define HVCALL_SEND_IPI_EX                      0x0015
 377 #define HVCALL_POST_MESSAGE                     0x005c
 378 #define HVCALL_SIGNAL_EVENT                     0x005d
 379 #define HVCALL_RETARGET_INTERRUPT               0x007e
 380 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
 381 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0
 382
 383 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE        0x00000001
 384 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
 385 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK  \
 386                 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 387
 388 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */
 389 #define HV_X64_ENLIGHTENED_VMCS_VERSION         0xff
 390
 391 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 392 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 393
 394 #define HV_PROCESSOR_POWER_STATE_C0             0
 395 #define HV_PROCESSOR_POWER_STATE_C1             1
 396 #define HV_PROCESSOR_POWER_STATE_C2             2
 397 #define HV_PROCESSOR_POWER_STATE_C3             3
 398
 399 #define HV_FLUSH_ALL_PROCESSORS                 BIT(0)
 400 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES     BIT(1)
 401 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY       BIT(2)
 402 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT      BIT(3)
 403
 404 enum HV_GENERIC_SET_FORMAT {
 405         HV_GENERIC_SET_SPARSE_4K,
 406         HV_GENERIC_SET_ALL,
 407 };
 408
 409 #define HV_PARTITION_ID_SELF                    ((u64)-1)
 410
 411 #define HV_HYPERCALL_RESULT_MASK        GENMASK_ULL(15, 0)
 412 #define HV_HYPERCALL_FAST_BIT           BIT(16)
 413 #define HV_HYPERCALL_VARHEAD_OFFSET     17
 414 #define HV_HYPERCALL_REP_COMP_OFFSET    32
 415 #define HV_HYPERCALL_REP_COMP_MASK      GENMASK_ULL(43, 32)
 416 #define HV_HYPERCALL_REP_START_OFFSET   48
 417 #define HV_HYPERCALL_REP_START_MASK     GENMASK_ULL(59, 48)
 418
 419 /* hypercall status code */
 420 #define HV_STATUS_SUCCESS                       0
 421 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
 422 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
 423 #define HV_STATUS_INVALID_ALIGNMENT             4
 424 #define HV_STATUS_INVALID_PARAMETER             5
 425 #define HV_STATUS_INSUFFICIENT_MEMORY           11
 426 #define HV_STATUS_INVALID_PORT_ID               17
 427 #define HV_STATUS_INVALID_CONNECTION_ID         18
 428 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 429
 430 /*
 431  * The Hyper-V TimeRefCount register and the TSC
 432  * page provide a guest VM clock with 100ns tick rate
 433  */
 434 #define HV_CLOCK_HZ (NSEC_PER_SEC/100)
 435
 436 typedef struct _HV_REFERENCE_TSC_PAGE {
 437         __u32 tsc_sequence;
 438         __u32 res1;
 439         __u64 tsc_scale;
 440         __s64 tsc_offset;
 441 }  __packed HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE;
 442
 443 /* Define the number of synthetic interrupt sources. */
 444 #define HV_SYNIC_SINT_COUNT             (16)
 445 /* Define the expected SynIC version. */
 446 #define HV_SYNIC_VERSION_1              (0x1)
 447 /* Valid SynIC vectors are 16-255. */
 448 #define HV_SYNIC_FIRST_VALID_VECTOR     (16)
 449
 450 #define HV_SYNIC_CONTROL_ENABLE         (1ULL << 0)
 451 #define HV_SYNIC_SIMP_ENABLE            (1ULL << 0)
 452 #define HV_SYNIC_SIEFP_ENABLE           (1ULL << 0)
 453 #define HV_SYNIC_SINT_MASKED            (1ULL << 16)
 454 #define HV_SYNIC_SINT_AUTO_EOI          (1ULL << 17)
 455 #define HV_SYNIC_SINT_VECTOR_MASK       (0xFF)
 456
 457 #define HV_SYNIC_STIMER_COUNT           (4)
 458
 459 /* Define synthetic interrupt controller message constants. */
 460 #define HV_MESSAGE_SIZE                 (256)
 461 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT   (240)
 462 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT  (30)
 463
 464 /* Define hypervisor message types. */
 465 enum hv_message_type {
 466         HVMSG_NONE                      = 0x00000000,
 467
 468         /* Memory access messages. */
 469         HVMSG_UNMAPPED_GPA              = 0x80000000,
 470         HVMSG_GPA_INTERCEPT             = 0x80000001,
 471
 472         /* Timer notification messages. */
 473         HVMSG_TIMER_EXPIRED                     = 0x80000010,
 474
 475         /* Error messages. */
 476         HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
 477         HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
 478         HVMSG_UNSUPPORTED_FEATURE               = 0x80000022,
 479
 480         /* Trace buffer complete messages. */
 481         HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
 482
 483         /* Platform-specific processor intercept messages. */
 484         HVMSG_X64_IOPORT_INTERCEPT              = 0x80010000,
 485         HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
 486         HVMSG_X64_CPUID_INTERCEPT               = 0x80010002,
 487         HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
 488         HVMSG_X64_APIC_EOI                      = 0x80010004,
 489         HVMSG_X64_LEGACY_FP_ERROR               = 0x80010005
 490 };
 491
 492 /* Define synthetic interrupt controller message flags. */
 493 union hv_message_flags {
 494         __u8 asu8;
 495         struct {
 496                 __u8 msg_pending:1;
 497                 __u8 reserved:7;
 498         } __packed;
 499 };
 500
 501 /* Define port identifier type. */
 502 union hv_port_id {
 503         __u32 asu32;
 504         struct {
 505                 __u32 id:24;
 506                 __u32 reserved:8;
 507         } __packed u;
 508 };
 509
 510 /* Define synthetic interrupt controller message header. */
 511 struct hv_message_header {
 512         __u32 message_type;
 513         __u8 payload_size;
 514         union hv_message_flags message_flags;
 515         __u8 reserved[2];
 516         union {
 517                 __u64 sender;
 518                 union hv_port_id port;
 519         };
 520 } __packed;
 521
 522 /* Define synthetic interrupt controller message format. */
 523 struct hv_message {
 524         struct hv_message_header header;
 525         union {
 526                 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
 527         } u;
 528 } __packed;
 529
 530 /* Define the synthetic interrupt message page layout. */
 531 struct hv_message_page {
 532         struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
 533 } __packed;
 534
 535 /* Define timer message payload structure. */
 536 struct hv_timer_message_payload {
 537         __u32 timer_index;
 538         __u32 reserved;
 539         __u64 expiration_time;  /* When the timer expired */
 540         __u64 delivery_time;    /* When the message was delivered */
 541 } __packed;
 542
 543 struct hv_nested_enlightenments_control {
 544         struct {
 545                 __u32 directhypercall:1;
 546                 __u32 reserved:31;
 547         } features;
 548         struct {
 549                 __u32 reserved;
 550         } hypercallControls;
 551 } __packed;
 552
 553 /* Define virtual processor assist page structure. */
 554 struct hv_vp_assist_page {
 555         __u32 apic_assist;
 556         __u32 reserved1;
 557         __u64 vtl_control[3];
 558         struct hv_nested_enlightenments_control nested_control;
 559         __u8 enlighten_vmentry;
 560         __u8 reserved2[7];
 561         __u64 current_nested_vmcs;
 562 } __packed;
 563
 564 struct hv_enlightened_vmcs {
 565         u32 revision_id;
 566         u32 abort;
 567
 568         u16 host_es_selector;
 569         u16 host_cs_selector;
 570         u16 host_ss_selector;
 571         u16 host_ds_selector;
 572         u16 host_fs_selector;
 573         u16 host_gs_selector;
 574         u16 host_tr_selector;
 575
 576         u16 padding16_1;
 577
 578         u64 host_ia32_pat;
 579         u64 host_ia32_efer;
 580
 581         u64 host_cr0;
 582         u64 host_cr3;
 583         u64 host_cr4;
 584
 585         u64 host_ia32_sysenter_esp;
 586         u64 host_ia32_sysenter_eip;
 587         u64 host_rip;
 588         u32 host_ia32_sysenter_cs;
 589
 590         u32 pin_based_vm_exec_control;
 591         u32 vm_exit_controls;
 592         u32 secondary_vm_exec_control;
 593
 594         u64 io_bitmap_a;
 595         u64 io_bitmap_b;
 596         u64 msr_bitmap;
 597
 598         u16 guest_es_selector;
 599         u16 guest_cs_selector;
 600         u16 guest_ss_selector;
 601         u16 guest_ds_selector;
 602         u16 guest_fs_selector;
 603         u16 guest_gs_selector;
 604         u16 guest_ldtr_selector;
 605         u16 guest_tr_selector;
 606
 607         u32 guest_es_limit;
 608         u32 guest_cs_limit;
 609         u32 guest_ss_limit;
 610         u32 guest_ds_limit;
 611         u32 guest_fs_limit;
 612         u32 guest_gs_limit;
 613         u32 guest_ldtr_limit;
 614         u32 guest_tr_limit;
 615         u32 guest_gdtr_limit;
 616         u32 guest_idtr_limit;
 617
 618         u32 guest_es_ar_bytes;
 619         u32 guest_cs_ar_bytes;
 620         u32 guest_ss_ar_bytes;
 621         u32 guest_ds_ar_bytes;
 622         u32 guest_fs_ar_bytes;
 623         u32 guest_gs_ar_bytes;
 624         u32 guest_ldtr_ar_bytes;
 625         u32 guest_tr_ar_bytes;
 626
 627         u64 guest_es_base;
 628         u64 guest_cs_base;
 629         u64 guest_ss_base;
 630         u64 guest_ds_base;
 631         u64 guest_fs_base;
 632         u64 guest_gs_base;
 633         u64 guest_ldtr_base;
 634         u64 guest_tr_base;
 635         u64 guest_gdtr_base;
 636         u64 guest_idtr_base;
 637
 638         u64 padding64_1[3];
 639
 640         u64 vm_exit_msr_store_addr;
 641         u64 vm_exit_msr_load_addr;
 642         u64 vm_entry_msr_load_addr;
 643
 644         u64 cr3_target_value0;
 645         u64 cr3_target_value1;
 646         u64 cr3_target_value2;
 647         u64 cr3_target_value3;
 648
 649         u32 page_fault_error_code_mask;
 650         u32 page_fault_error_code_match;
 651
 652         u32 cr3_target_count;
 653         u32 vm_exit_msr_store_count;
 654         u32 vm_exit_msr_load_count;
 655         u32 vm_entry_msr_load_count;
 656
 657         u64 tsc_offset;
 658         u64 virtual_apic_page_addr;
 659         u64 vmcs_link_pointer;
 660
 661         u64 guest_ia32_debugctl;
 662         u64 guest_ia32_pat;
 663         u64 guest_ia32_efer;
 664
 665         u64 guest_pdptr0;
 666         u64 guest_pdptr1;
 667         u64 guest_pdptr2;
 668         u64 guest_pdptr3;
 669
 670         u64 guest_pending_dbg_exceptions;
 671         u64 guest_sysenter_esp;
 672         u64 guest_sysenter_eip;
 673
 674         u32 guest_activity_state;
 675         u32 guest_sysenter_cs;
 676
 677         u64 cr0_guest_host_mask;
 678         u64 cr4_guest_host_mask;
 679         u64 cr0_read_shadow;
 680         u64 cr4_read_shadow;
 681         u64 guest_cr0;
 682         u64 guest_cr3;
 683         u64 guest_cr4;
 684         u64 guest_dr7;
 685
 686         u64 host_fs_base;
 687         u64 host_gs_base;
 688         u64 host_tr_base;
 689         u64 host_gdtr_base;
 690         u64 host_idtr_base;
 691         u64 host_rsp;
 692
 693         u64 ept_pointer;
 694
 695         u16 virtual_processor_id;
 696         u16 padding16_2[3];
 697
 698         u64 padding64_2[5];
 699         u64 guest_physical_address;
 700
 701         u32 vm_instruction_error;
 702         u32 vm_exit_reason;
 703         u32 vm_exit_intr_info;
 704         u32 vm_exit_intr_error_code;
 705         u32 idt_vectoring_info_field;
 706         u32 idt_vectoring_error_code;
 707         u32 vm_exit_instruction_len;
 708         u32 vmx_instruction_info;
 709
 710         u64 exit_qualification;
 711         u64 exit_io_instruction_ecx;
 712         u64 exit_io_instruction_esi;
 713         u64 exit_io_instruction_edi;
 714         u64 exit_io_instruction_eip;
 715
 716         u64 guest_linear_address;
 717         u64 guest_rsp;
 718         u64 guest_rflags;
 719
 720         u32 guest_interruptibility_info;
 721         u32 cpu_based_vm_exec_control;
 722         u32 exception_bitmap;
 723         u32 vm_entry_controls;
 724         u32 vm_entry_intr_info_field;
 725         u32 vm_entry_exception_error_code;
 726         u32 vm_entry_instruction_len;
 727         u32 tpr_threshold;
 728
 729         u64 guest_rip;
 730
 731         u32 hv_clean_fields;
 732         u32 hv_padding_32;
 733         u32 hv_synthetic_controls;
 734         struct {
 735                 u32 nested_flush_hypercall:1;
 736                 u32 msr_bitmap:1;
 737                 u32 reserved:30;
 738         }  __packed hv_enlightenments_control;
 739         u32 hv_vp_id;
 740
 741         u64 hv_vm_id;
 742         u64 partition_assist_page;
 743         u64 padding64_4[4];
 744         u64 guest_bndcfgs;
 745         u64 padding64_5[7];
 746         u64 xss_exit_bitmap;
 747         u64 padding64_6[7];
 748 } __packed;
 749
 750 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE                     0
 751 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP                BIT(0)
 752 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP               BIT(1)
 753 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2             BIT(2)
 754 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1             BIT(3)
 755 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC             BIT(4)
 756 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT            BIT(5)
 757 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY            BIT(6)
 758 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN            BIT(7)
 759 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR                     BIT(8)
 760 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT             BIT(9)
 761 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC              BIT(10)
 762 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1               BIT(11)
 763 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2               BIT(12)
 764 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER             BIT(13)
 765 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1                BIT(14)
 766 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL    BIT(15)
 767
 768 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL                      0xFFFF
 769
 770 /* Define synthetic interrupt controller flag constants. */
 771 #define HV_EVENT_FLAGS_COUNT            (256 * 8)
 772 #define HV_EVENT_FLAGS_LONG_COUNT       (256 / sizeof(unsigned long))
 773
 774 /*
 775  * Synthetic timer configuration.
 776  */
 777 union hv_stimer_config {
 778         u64 as_uint64;
 779         struct {
 780                 u64 enable:1;
 781                 u64 periodic:1;
 782                 u64 lazy:1;
 783                 u64 auto_enable:1;
 784                 u64 apic_vector:8;
 785                 u64 direct_mode:1;
 786                 u64 reserved_z0:3;
 787                 u64 sintx:4;
 788                 u64 reserved_z1:44;
 789         } __packed;
 790 };
 791
 792
 793 /* Define the synthetic interrupt controller event flags format. */
 794 union hv_synic_event_flags {
 795         unsigned long flags[HV_EVENT_FLAGS_LONG_COUNT];
 796 };
 797
 798 /* Define SynIC control register. */
 799 union hv_synic_scontrol {
 800         u64 as_uint64;
 801         struct {
 802                 u64 enable:1;
 803                 u64 reserved:63;
 804         } __packed;
 805 };
 806
 807 /* Define synthetic interrupt source. */
 808 union hv_synic_sint {
 809         u64 as_uint64;
 810         struct {
 811                 u64 vector:8;
 812                 u64 reserved1:8;
 813                 u64 masked:1;
 814                 u64 auto_eoi:1;
 815                 u64 polling:1;
 816                 u64 reserved2:45;
 817         } __packed;
 818 };
 819
 820 /* Define the format of the SIMP register */
 821 union hv_synic_simp {
 822         u64 as_uint64;
 823         struct {
 824                 u64 simp_enabled:1;
 825                 u64 preserved:11;
 826                 u64 base_simp_gpa:52;
 827         } __packed;
 828 };
 829
 830 /* Define the format of the SIEFP register */
 831 union hv_synic_siefp {
 832         u64 as_uint64;
 833         struct {
 834                 u64 siefp_enabled:1;
 835                 u64 preserved:11;
 836                 u64 base_siefp_gpa:52;
 837         } __packed;
 838 };
 839
 840 struct hv_vpset {
 841         u64 format;
 842         u64 valid_bank_mask;
 843         u64 bank_contents[];
 844 } __packed;
 845
 846 /* HvCallSendSyntheticClusterIpi hypercall */
 847 struct hv_send_ipi {
 848         u32 vector;
 849         u32 reserved;
 850         u64 cpu_mask;
 851 } __packed;
 852
 853 /* HvCallSendSyntheticClusterIpiEx hypercall */
 854 struct hv_send_ipi_ex {
 855         u32 vector;
 856         u32 reserved;
 857         struct hv_vpset vp_set;
 858 } __packed;
 859
 860 /* HvFlushGuestPhysicalAddressSpace hypercalls */
 861 struct hv_guest_mapping_flush {
 862         u64 address_space;
 863         u64 flags;
 864 } __packed;
 865
 866 /*
 867  *  HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited
 868  *  by the bitwidth of "additional_pages" in union hv_gpa_page_range.
 869  */
 870 #define HV_MAX_FLUSH_PAGES (2048)
 871
 872 /* HvFlushGuestPhysicalAddressList hypercall */
 873 union hv_gpa_page_range {
 874         u64 address_space;
 875         struct {
 876                 u64 additional_pages:11;
 877                 u64 largepage:1;
 878                 u64 basepfn:52;
 879         } page;
 880 };
 881
 882 /*
 883  * All input flush parameters should be in single page. The max flush
 884  * count is equal with how many entries of union hv_gpa_page_range can
 885  * be populated into the input parameter page.
 886  */
 887 #define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) /  \
 888                                 sizeof(union hv_gpa_page_range))
 889
 890 struct hv_guest_mapping_flush_list {
 891         u64 address_space;
 892         u64 flags;
 893         union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT];
 894 };
 895
 896 /* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */
 897 struct hv_tlb_flush {
 898         u64 address_space;
 899         u64 flags;
 900         u64 processor_mask;
 901         u64 gva_list[];
 902 } __packed;
 903
 904 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */
 905 struct hv_tlb_flush_ex {
 906         u64 address_space;
 907         u64 flags;
 908         struct hv_vpset hv_vp_set;
 909         u64 gva_list[];
 910 } __packed;
 911
 912 struct hv_partition_assist_pg {
 913         u32 tlb_lock_count;
 914 };
 915
 916 union hv_msi_entry {
 917         u64 as_uint64;
 918         struct {
 919                 u32 address;
 920                 u32 data;
 921         } __packed;
 922 };
 923
 924 struct hv_interrupt_entry {
 925         u32 source;                     /* 1 for MSI(-X) */
 926         u32 reserved1;
 927         union hv_msi_entry msi_entry;
 928 } __packed;
 929
 930 /*
 931  * flags for hv_device_interrupt_target.flags
 932  */
 933 #define HV_DEVICE_INTERRUPT_TARGET_MULTICAST            1
 934 #define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET        2
 935
 936 struct hv_device_interrupt_target {
 937         u32 vector;
 938         u32 flags;
 939         union {
 940                 u64 vp_mask;
 941                 struct hv_vpset vp_set;
 942         };
 943 } __packed;
 944
 945 /* HvRetargetDeviceInterrupt hypercall */
 946 struct hv_retarget_device_interrupt {
 947         u64 partition_id;               /* use "self" */
 948         u64 device_id;
 949         struct hv_interrupt_entry int_entry;
 950         u64 reserved2;
 951         struct hv_device_interrupt_target int_target;
 952 } __packed __aligned(8);
 953 #endif