arch/x86/include/asm/hyperv-tlfs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2
   3 /*
   4  * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
   5  * Specification (TLFS):
   6  * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
   7  */
   8
   9 #ifndef _ASM_X86_HYPERV_TLFS_H
  10 #define _ASM_X86_HYPERV_TLFS_H
  11
  12 #include <linux/types.h>
  13 #include <asm/page.h>
  14 /*
  15  * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
  16  * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
  17  */
  18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS   0x40000000
  19 #define HYPERV_CPUID_INTERFACE                  0x40000001
  20 #define HYPERV_CPUID_VERSION                    0x40000002
  21 #define HYPERV_CPUID_FEATURES                   0x40000003
  22 #define HYPERV_CPUID_ENLIGHTMENT_INFO           0x40000004
  23 #define HYPERV_CPUID_IMPLEMENT_LIMITS           0x40000005
  24 #define HYPERV_CPUID_NESTED_FEATURES            0x4000000A
  25
  26 #define HYPERV_HYPERVISOR_PRESENT_BIT           0x80000000
  27 #define HYPERV_CPUID_MIN                        0x40000005
  28 #define HYPERV_CPUID_MAX                        0x4000ffff
  29
  30 /*
  31  * Aliases for Group A features that have X64 in the name.
  32  * On x86/x64 these are HYPERV_CPUID_FEATURES.EAX bits.
  33  */
  34
  35 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE         \
  36                 HV_MSR_VP_RUNTIME_AVAILABLE
  37 #define HV_X64_MSR_SYNIC_AVAILABLE              \
  38                 HV_MSR_SYNIC_AVAILABLE
  39 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE        \
  40                 HV_MSR_APIC_ACCESS_AVAILABLE
  41 #define HV_X64_MSR_HYPERCALL_AVAILABLE          \
  42                 HV_MSR_HYPERCALL_AVAILABLE
  43 #define HV_X64_MSR_VP_INDEX_AVAILABLE           \
  44                 HV_MSR_VP_INDEX_AVAILABLE
  45 #define HV_X64_MSR_RESET_AVAILABLE              \
  46                 HV_MSR_RESET_AVAILABLE
  47 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE         \
  48                 HV_MSR_GUEST_IDLE_AVAILABLE
  49 #define HV_X64_ACCESS_FREQUENCY_MSRS            \
  50                 HV_ACCESS_FREQUENCY_MSRS
  51 #define HV_X64_ACCESS_REENLIGHTENMENT           \
  52                 HV_ACCESS_REENLIGHTENMENT
  53 #define HV_X64_ACCESS_TSC_INVARIANT             \
  54                 HV_ACCESS_TSC_INVARIANT
  55
  56 /*
  57  * Aliases for Group B features that have X64 in the name.
  58  * On x86/x64 these are HYPERV_CPUID_FEATURES.EBX bits.
  59  */
  60 #define HV_X64_POST_MESSAGES            HV_POST_MESSAGES
  61 #define HV_X64_SIGNAL_EVENTS            HV_SIGNAL_EVENTS
  62
  63 /*
  64  * Group D Features.  The bit assignments are custom to each architecture.
  65  * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits.
  66  */
  67 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */
  68 #define HV_X64_MWAIT_AVAILABLE                          BIT(0)
  69 /* Guest debugging support is available */
  70 #define HV_X64_GUEST_DEBUGGING_AVAILABLE                BIT(1)
  71 /* Performance Monitor support is available*/
  72 #define HV_X64_PERF_MONITOR_AVAILABLE                   BIT(2)
  73 /* Support for physical CPU dynamic partitioning events is available*/
  74 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE       BIT(3)
  75 /*
  76  * Support for passing hypercall input parameter block via XMM
  77  * registers is available
  78  */
  79 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE           BIT(4)
  80 /* Support for a virtual guest idle state is available */
  81 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE               BIT(5)
  82 /* Frequency MSRs available */
  83 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE             BIT(8)
  84 /* Crash MSR available */
  85 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE            BIT(10)
  86 /* stimer Direct Mode is available */
  87 #define HV_STIMER_DIRECT_MODE_AVAILABLE                 BIT(19)
  88
  89 /*
  90  * Implementation recommendations. Indicates which behaviors the hypervisor
  91  * recommends the OS implement for optimal performance.
  92  * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
  93  */
  94 /*
  95  * Recommend using hypercall for address space switches rather
  96  * than MOV to CR3 instruction
  97  */
  98 #define HV_X64_AS_SWITCH_RECOMMENDED                    BIT(0)
  99 /* Recommend using hypercall for local TLB flushes rather
 100  * than INVLPG or MOV to CR3 instructions */
 101 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED              BIT(1)
 102 /*
 103  * Recommend using hypercall for remote TLB flushes rather
 104  * than inter-processor interrupts
 105  */
 106 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED             BIT(2)
 107 /*
 108  * Recommend using MSRs for accessing APIC registers
 109  * EOI, ICR and TPR rather than their memory-mapped counterparts
 110  */
 111 #define HV_X64_APIC_ACCESS_RECOMMENDED                  BIT(3)
 112 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */
 113 #define HV_X64_SYSTEM_RESET_RECOMMENDED                 BIT(4)
 114 /*
 115  * Recommend using relaxed timing for this partition. If used,
 116  * the VM should disable any watchdog timeouts that rely on the
 117  * timely delivery of external interrupts
 118  */
 119 #define HV_X64_RELAXED_TIMING_RECOMMENDED               BIT(5)
 120
 121 /*
 122  * Recommend not using Auto End-Of-Interrupt feature
 123  */
 124 #define HV_DEPRECATING_AEOI_RECOMMENDED                 BIT(9)
 125
 126 /*
 127  * Recommend using cluster IPI hypercalls.
 128  */
 129 #define HV_X64_CLUSTER_IPI_RECOMMENDED                  BIT(10)
 130
 131 /* Recommend using the newer ExProcessorMasks interface */
 132 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED           BIT(11)
 133
 134 /* Recommend using enlightened VMCS */
 135 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED             BIT(14)
 136
 137 /*
 138  * Virtual processor will never share a physical core with another virtual
 139  * processor, except for virtual processors that are reported as sibling SMT
 140  * threads.
 141  */
 142 #define HV_X64_NO_NONARCH_CORESHARING                   BIT(18)
 143
 144 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
 145 #define HV_X64_NESTED_DIRECT_FLUSH                      BIT(17)
 146 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH               BIT(18)
 147 #define HV_X64_NESTED_MSR_BITMAP                        BIT(19)
 148
 149 /* Hyper-V specific model specific registers (MSRs) */
 150
 151 /* MSR used to identify the guest OS. */
 152 #define HV_X64_MSR_GUEST_OS_ID                  0x40000000
 153
 154 /* MSR used to setup pages used to communicate with the hypervisor. */
 155 #define HV_X64_MSR_HYPERCALL                    0x40000001
 156
 157 /* MSR used to provide vcpu index */
 158 #define HV_X64_MSR_VP_INDEX                     0x40000002
 159
 160 /* MSR used to reset the guest OS. */
 161 #define HV_X64_MSR_RESET                        0x40000003
 162
 163 /* MSR used to provide vcpu runtime in 100ns units */
 164 #define HV_X64_MSR_VP_RUNTIME                   0x40000010
 165
 166 /* MSR used to read the per-partition time reference counter */
 167 #define HV_X64_MSR_TIME_REF_COUNT               0x40000020
 168
 169 /* A partition's reference time stamp counter (TSC) page */
 170 #define HV_X64_MSR_REFERENCE_TSC                0x40000021
 171
 172 /* MSR used to retrieve the TSC frequency */
 173 #define HV_X64_MSR_TSC_FREQUENCY                0x40000022
 174
 175 /* MSR used to retrieve the local APIC timer frequency */
 176 #define HV_X64_MSR_APIC_FREQUENCY               0x40000023
 177
 178 /* Define the virtual APIC registers */
 179 #define HV_X64_MSR_EOI                          0x40000070
 180 #define HV_X64_MSR_ICR                          0x40000071
 181 #define HV_X64_MSR_TPR                          0x40000072
 182 #define HV_X64_MSR_VP_ASSIST_PAGE               0x40000073
 183
 184 /* Define synthetic interrupt controller model specific registers. */
 185 #define HV_X64_MSR_SCONTROL                     0x40000080
 186 #define HV_X64_MSR_SVERSION                     0x40000081
 187 #define HV_X64_MSR_SIEFP                        0x40000082
 188 #define HV_X64_MSR_SIMP                         0x40000083
 189 #define HV_X64_MSR_EOM                          0x40000084
 190 #define HV_X64_MSR_SINT0                        0x40000090
 191 #define HV_X64_MSR_SINT1                        0x40000091
 192 #define HV_X64_MSR_SINT2                        0x40000092
 193 #define HV_X64_MSR_SINT3                        0x40000093
 194 #define HV_X64_MSR_SINT4                        0x40000094
 195 #define HV_X64_MSR_SINT5                        0x40000095
 196 #define HV_X64_MSR_SINT6                        0x40000096
 197 #define HV_X64_MSR_SINT7                        0x40000097
 198 #define HV_X64_MSR_SINT8                        0x40000098
 199 #define HV_X64_MSR_SINT9                        0x40000099
 200 #define HV_X64_MSR_SINT10                       0x4000009A
 201 #define HV_X64_MSR_SINT11                       0x4000009B
 202 #define HV_X64_MSR_SINT12                       0x4000009C
 203 #define HV_X64_MSR_SINT13                       0x4000009D
 204 #define HV_X64_MSR_SINT14                       0x4000009E
 205 #define HV_X64_MSR_SINT15                       0x4000009F
 206
 207 /*
 208  * Synthetic Timer MSRs. Four timers per vcpu.
 209  */
 210 #define HV_X64_MSR_STIMER0_CONFIG               0x400000B0
 211 #define HV_X64_MSR_STIMER0_COUNT                0x400000B1
 212 #define HV_X64_MSR_STIMER1_CONFIG               0x400000B2
 213 #define HV_X64_MSR_STIMER1_COUNT                0x400000B3
 214 #define HV_X64_MSR_STIMER2_CONFIG               0x400000B4
 215 #define HV_X64_MSR_STIMER2_COUNT                0x400000B5
 216 #define HV_X64_MSR_STIMER3_CONFIG               0x400000B6
 217 #define HV_X64_MSR_STIMER3_COUNT                0x400000B7
 218
 219 /* Hyper-V guest idle MSR */
 220 #define HV_X64_MSR_GUEST_IDLE                   0x400000F0
 221
 222 /* Hyper-V guest crash notification MSR's */
 223 #define HV_X64_MSR_CRASH_P0                     0x40000100
 224 #define HV_X64_MSR_CRASH_P1                     0x40000101
 225 #define HV_X64_MSR_CRASH_P2                     0x40000102
 226 #define HV_X64_MSR_CRASH_P3                     0x40000103
 227 #define HV_X64_MSR_CRASH_P4                     0x40000104
 228 #define HV_X64_MSR_CRASH_CTL                    0x40000105
 229
 230 /* TSC emulation after migration */
 231 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 232 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 233 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 234
 235 /* TSC invariant control */
 236 #define HV_X64_MSR_TSC_INVARIANT_CONTROL        0x40000118
 237
 238 /*
 239  * Declare the MSR used to setup pages used to communicate with the hypervisor.
 240  */
 241 union hv_x64_msr_hypercall_contents {
 242         u64 as_uint64;
 243         struct {
 244                 u64 enable:1;
 245                 u64 reserved:11;
 246                 u64 guest_physical_address:52;
 247         } __packed;
 248 };
 249
 250 struct hv_reenlightenment_control {
 251         __u64 vector:8;
 252         __u64 reserved1:8;
 253         __u64 enabled:1;
 254         __u64 reserved2:15;
 255         __u64 target_vp:32;
 256 }  __packed;
 257
 258 struct hv_tsc_emulation_control {
 259         __u64 enabled:1;
 260         __u64 reserved:63;
 261 } __packed;
 262
 263 struct hv_tsc_emulation_status {
 264         __u64 inprogress:1;
 265         __u64 reserved:63;
 266 } __packed;
 267
 268 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
 269 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
 270 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK  \
 271                 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
 272
 273 #define HV_X64_MSR_CRASH_PARAMS         \
 274                 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
 275
 276 #define HV_IPI_LOW_VECTOR       0x10
 277 #define HV_IPI_HIGH_VECTOR      0xff
 278
 279 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE        0x00000001
 280 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
 281 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK  \
 282                 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 283
 284 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */
 285 #define HV_X64_ENLIGHTENED_VMCS_VERSION         0xff
 286
 287 #define HV_X64_MSR_TSC_REFERENCE_ENABLE         0x00000001
 288 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT  12
 289
 290
 291 /* Define hypervisor message types. */
 292 enum hv_message_type {
 293         HVMSG_NONE                      = 0x00000000,
 294
 295         /* Memory access messages. */
 296         HVMSG_UNMAPPED_GPA              = 0x80000000,
 297         HVMSG_GPA_INTERCEPT             = 0x80000001,
 298
 299         /* Timer notification messages. */
 300         HVMSG_TIMER_EXPIRED             = 0x80000010,
 301
 302         /* Error messages. */
 303         HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
 304         HVMSG_UNRECOVERABLE_EXCEPTION   = 0x80000021,
 305         HVMSG_UNSUPPORTED_FEATURE       = 0x80000022,
 306
 307         /* Trace buffer complete messages. */
 308         HVMSG_EVENTLOG_BUFFERCOMPLETE   = 0x80000040,
 309
 310         /* Platform-specific processor intercept messages. */
 311         HVMSG_X64_IOPORT_INTERCEPT      = 0x80010000,
 312         HVMSG_X64_MSR_INTERCEPT         = 0x80010001,
 313         HVMSG_X64_CPUID_INTERCEPT       = 0x80010002,
 314         HVMSG_X64_EXCEPTION_INTERCEPT   = 0x80010003,
 315         HVMSG_X64_APIC_EOI              = 0x80010004,
 316         HVMSG_X64_LEGACY_FP_ERROR       = 0x80010005
 317 };
 318
 319 struct hv_nested_enlightenments_control {
 320         struct {
 321                 __u32 directhypercall:1;
 322                 __u32 reserved:31;
 323         } features;
 324         struct {
 325                 __u32 reserved;
 326         } hypercallControls;
 327 } __packed;
 328
 329 /* Define virtual processor assist page structure. */
 330 struct hv_vp_assist_page {
 331         __u32 apic_assist;
 332         __u32 reserved1;
 333         __u64 vtl_control[3];
 334         struct hv_nested_enlightenments_control nested_control;
 335         __u8 enlighten_vmentry;
 336         __u8 reserved2[7];
 337         __u64 current_nested_vmcs;
 338 } __packed;
 339
 340 struct hv_enlightened_vmcs {
 341         u32 revision_id;
 342         u32 abort;
 343
 344         u16 host_es_selector;
 345         u16 host_cs_selector;
 346         u16 host_ss_selector;
 347         u16 host_ds_selector;
 348         u16 host_fs_selector;
 349         u16 host_gs_selector;
 350         u16 host_tr_selector;
 351
 352         u16 padding16_1;
 353
 354         u64 host_ia32_pat;
 355         u64 host_ia32_efer;
 356
 357         u64 host_cr0;
 358         u64 host_cr3;
 359         u64 host_cr4;
 360
 361         u64 host_ia32_sysenter_esp;
 362         u64 host_ia32_sysenter_eip;
 363         u64 host_rip;
 364         u32 host_ia32_sysenter_cs;
 365
 366         u32 pin_based_vm_exec_control;
 367         u32 vm_exit_controls;
 368         u32 secondary_vm_exec_control;
 369
 370         u64 io_bitmap_a;
 371         u64 io_bitmap_b;
 372         u64 msr_bitmap;
 373
 374         u16 guest_es_selector;
 375         u16 guest_cs_selector;
 376         u16 guest_ss_selector;
 377         u16 guest_ds_selector;
 378         u16 guest_fs_selector;
 379         u16 guest_gs_selector;
 380         u16 guest_ldtr_selector;
 381         u16 guest_tr_selector;
 382
 383         u32 guest_es_limit;
 384         u32 guest_cs_limit;
 385         u32 guest_ss_limit;
 386         u32 guest_ds_limit;
 387         u32 guest_fs_limit;
 388         u32 guest_gs_limit;
 389         u32 guest_ldtr_limit;
 390         u32 guest_tr_limit;
 391         u32 guest_gdtr_limit;
 392         u32 guest_idtr_limit;
 393
 394         u32 guest_es_ar_bytes;
 395         u32 guest_cs_ar_bytes;
 396         u32 guest_ss_ar_bytes;
 397         u32 guest_ds_ar_bytes;
 398         u32 guest_fs_ar_bytes;
 399         u32 guest_gs_ar_bytes;
 400         u32 guest_ldtr_ar_bytes;
 401         u32 guest_tr_ar_bytes;
 402
 403         u64 guest_es_base;
 404         u64 guest_cs_base;
 405         u64 guest_ss_base;
 406         u64 guest_ds_base;
 407         u64 guest_fs_base;
 408         u64 guest_gs_base;
 409         u64 guest_ldtr_base;
 410         u64 guest_tr_base;
 411         u64 guest_gdtr_base;
 412         u64 guest_idtr_base;
 413
 414         u64 padding64_1[3];
 415
 416         u64 vm_exit_msr_store_addr;
 417         u64 vm_exit_msr_load_addr;
 418         u64 vm_entry_msr_load_addr;
 419
 420         u64 cr3_target_value0;
 421         u64 cr3_target_value1;
 422         u64 cr3_target_value2;
 423         u64 cr3_target_value3;
 424
 425         u32 page_fault_error_code_mask;
 426         u32 page_fault_error_code_match;
 427
 428         u32 cr3_target_count;
 429         u32 vm_exit_msr_store_count;
 430         u32 vm_exit_msr_load_count;
 431         u32 vm_entry_msr_load_count;
 432
 433         u64 tsc_offset;
 434         u64 virtual_apic_page_addr;
 435         u64 vmcs_link_pointer;
 436
 437         u64 guest_ia32_debugctl;
 438         u64 guest_ia32_pat;
 439         u64 guest_ia32_efer;
 440
 441         u64 guest_pdptr0;
 442         u64 guest_pdptr1;
 443         u64 guest_pdptr2;
 444         u64 guest_pdptr3;
 445
 446         u64 guest_pending_dbg_exceptions;
 447         u64 guest_sysenter_esp;
 448         u64 guest_sysenter_eip;
 449
 450         u32 guest_activity_state;
 451         u32 guest_sysenter_cs;
 452
 453         u64 cr0_guest_host_mask;
 454         u64 cr4_guest_host_mask;
 455         u64 cr0_read_shadow;
 456         u64 cr4_read_shadow;
 457         u64 guest_cr0;
 458         u64 guest_cr3;
 459         u64 guest_cr4;
 460         u64 guest_dr7;
 461
 462         u64 host_fs_base;
 463         u64 host_gs_base;
 464         u64 host_tr_base;
 465         u64 host_gdtr_base;
 466         u64 host_idtr_base;
 467         u64 host_rsp;
 468
 469         u64 ept_pointer;
 470
 471         u16 virtual_processor_id;
 472         u16 padding16_2[3];
 473
 474         u64 padding64_2[5];
 475         u64 guest_physical_address;
 476
 477         u32 vm_instruction_error;
 478         u32 vm_exit_reason;
 479         u32 vm_exit_intr_info;
 480         u32 vm_exit_intr_error_code;
 481         u32 idt_vectoring_info_field;
 482         u32 idt_vectoring_error_code;
 483         u32 vm_exit_instruction_len;
 484         u32 vmx_instruction_info;
 485
 486         u64 exit_qualification;
 487         u64 exit_io_instruction_ecx;
 488         u64 exit_io_instruction_esi;
 489         u64 exit_io_instruction_edi;
 490         u64 exit_io_instruction_eip;
 491
 492         u64 guest_linear_address;
 493         u64 guest_rsp;
 494         u64 guest_rflags;
 495
 496         u32 guest_interruptibility_info;
 497         u32 cpu_based_vm_exec_control;
 498         u32 exception_bitmap;
 499         u32 vm_entry_controls;
 500         u32 vm_entry_intr_info_field;
 501         u32 vm_entry_exception_error_code;
 502         u32 vm_entry_instruction_len;
 503         u32 tpr_threshold;
 504
 505         u64 guest_rip;
 506
 507         u32 hv_clean_fields;
 508         u32 hv_padding_32;
 509         u32 hv_synthetic_controls;
 510         struct {
 511                 u32 nested_flush_hypercall:1;
 512                 u32 msr_bitmap:1;
 513                 u32 reserved:30;
 514         }  __packed hv_enlightenments_control;
 515         u32 hv_vp_id;
 516
 517         u64 hv_vm_id;
 518         u64 partition_assist_page;
 519         u64 padding64_4[4];
 520         u64 guest_bndcfgs;
 521         u64 padding64_5[7];
 522         u64 xss_exit_bitmap;
 523         u64 padding64_6[7];
 524 } __packed;
 525
 526 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE                     0
 527 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP                BIT(0)
 528 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP               BIT(1)
 529 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2             BIT(2)
 530 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1             BIT(3)
 531 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC             BIT(4)
 532 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT            BIT(5)
 533 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY            BIT(6)
 534 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN            BIT(7)
 535 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR                     BIT(8)
 536 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT             BIT(9)
 537 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC              BIT(10)
 538 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1               BIT(11)
 539 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2               BIT(12)
 540 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER             BIT(13)
 541 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1                BIT(14)
 542 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL    BIT(15)
 543
 544 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL                      0xFFFF
 545
 546 struct hv_partition_assist_pg {
 547         u32 tlb_lock_count;
 548 };
 549
 550
 551 #include <asm-generic/hyperv-tlfs.h>
 552
 553 #endif