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drm/i915/gvt: properly check per_ctx bb valid state
authorZhenyu Wang <zhenyuw@linux.intel.com>
Thu, 19 Oct 2017 05:54:06 +0000 (13:54 +0800)
committerZhi Wang <zhi.a.wang@intel.com>
Thu, 26 Oct 2017 17:37:13 +0000 (01:37 +0800)
Need to check valid state for per_ctx bb and bypass batch buffer
combine for scan if necessary. Otherwise adding invalid MI batch
buffer start cmd for per_ctx bb will cause scan failure, which is
taken as -EFAULT now so vGPU would be put in failsafe. This trys
to fix that by checking per_ctx bb valid state. Also remove old
invalid WARNING that indirect ctx bb shouldn't depend on valid
per_ctx bb.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
drivers/gpu/drm/i915/gvt/cmd_parser.c
drivers/gpu/drm/i915/gvt/execlist.c
drivers/gpu/drm/i915/gvt/scheduler.h

index 21c36e2..d4726a3 100644 (file)
@@ -2723,6 +2723,9 @@ static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
        uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
        unsigned char *bb_start_sva;
 
+       if (!wa_ctx->per_ctx.valid)
+               return 0;
+
        per_ctx_start[0] = 0x18800001;
        per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
 
index 91b4300..e5320b4 100644 (file)
@@ -701,8 +701,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id,
                        CACHELINE_BYTES;
                workload->wa_ctx.per_ctx.guest_gma =
                        per_ctx & PER_CTX_ADDR_MASK;
-
-               WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));
+               workload->wa_ctx.per_ctx.valid = per_ctx & 1;
        }
 
        if (emulate_schedule_in)
index 0d431a9..93a49eb 100644 (file)
@@ -68,6 +68,7 @@ struct shadow_indirect_ctx {
 struct shadow_per_ctx {
        unsigned long guest_gma;
        unsigned long shadow_gma;
+       unsigned valid;
 };
 
 struct intel_shadow_wa_ctx {