drm/i915: Add Wa_1409120013:icl,ehl

This chicken bit should be set before enabling FBC to avoid screen
corruption when the plane size has odd vertical and horizontal
dimensions.  It is safe to leave the bit set even when FBC is disabled.

v2:
 - The bspec's name for this bit on these platforms ("Spare 14") is
   pretty meaningless.  Let's rename the bit definition to something
   that more accurately reflects what the bit really does.  (Clint)

v3:
 - The chicken register was already defined (along with a few other
   gen9-specific bits) farther down.  Just add the new bit definition
   there.  (Clint)

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190612183631.30540-1-matthew.d.roper@intel.com
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d0c2623..daee496 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3163,6 +3163,7 @@ enum i915_power_well_id {
 #define ILK_DPFC_FENCE_YOFF    _MMIO(0x43218)
 #define ILK_DPFC_CHICKEN       _MMIO(0x43224)
 #define   ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
+#define   ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL    (1 << 14)
 #define   ILK_DPFC_NUKE_ON_ANY_MODIFICATION    (1 << 23)
 #define ILK_FBC_RT_BASE                _MMIO(0x2128)
 #define   ILK_FBC_RT_VALID     (1 << 0)

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 5679f2f..d36cada 100644 (file)
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -344,6 +344,10 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
                           HSW_FBCQ_DIS);
        }
 
+       if (IS_GEN(dev_priv, 11))
+               /* Wa_1409120013:icl,ehl */
+               I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
+
        I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 
        intel_fbc_recompress(dev_priv);