1 /**************************************************************************//**
3 * @brief CMSIS Cortex-M Core Instruction Access Header File
8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
22 ******************************************************************************/
24 #ifndef __CORE_CMINSTR_H
25 #define __CORE_CMINSTR_H
28 /* ########################## Core Instruction Access ######################### */
29 /** \ingroup CMSIS_Core
30 \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
31 Access to dedicated instructions
35 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
36 /* ARM armcc specific functions */
38 #if (__ARMCC_VERSION < 400677)
39 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
43 /** \brief No Operation
45 No Operation does nothing. This instruction can be used for code alignment purposes.
50 /** \brief Wait For Interrupt
52 Wait For Interrupt is a hint instruction that suspends execution
53 until one of a number of events occurs.
58 /** \brief Wait For Event
60 Wait For Event is a hint instruction that permits the processor to enter
61 a low-power state until one of a number of events occurs.
68 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
73 /** \brief Instruction Synchronization Barrier
75 Instruction Synchronization Barrier flushes the pipeline in the processor,
76 so that all instructions following the ISB are fetched from cache or
77 memory, after the instruction has been completed.
79 #define __ISB() __isb(0xF)
82 /** \brief Data Synchronization Barrier
84 This function acts as a special kind of Data Memory Barrier.
85 It completes when all explicit memory accesses before this instruction complete.
87 #define __DSB() __dsb(0xF)
90 /** \brief Data Memory Barrier
92 This function ensures the apparent order of the explicit memory operations before
93 and after the instruction, without ensuring their completion.
95 #define __DMB() __dmb(0xF)
98 /** \brief Reverse byte order (32 bit)
100 This function reverses the byte order in integer value.
102 \param [in] value Value to reverse
103 \return Reversed value
108 /** \brief Reverse byte order (16 bit)
110 This function reverses the byte order in two unsigned short values.
112 \param [in] value Value to reverse
113 \return Reversed value
115 static __INLINE __ASM uint32_t __REV16(uint32_t value)
122 /** \brief Reverse byte order in signed short value
124 This function reverses the byte order in a signed short value with sign extension to integer.
126 \param [in] value Value to reverse
127 \return Reversed value
129 static __INLINE __ASM int32_t __REVSH(int32_t value)
136 #if (__CORTEX_M >= 0x03)
138 /** \brief Reverse bit order of value
140 This function reverses the bit order of the given value.
142 \param [in] value Value to reverse
143 \return Reversed value
145 #define __RBIT __rbit
148 /** \brief LDR Exclusive (8 bit)
150 This function performs a exclusive LDR command for 8 bit value.
152 \param [in] ptr Pointer to data
153 \return value of type uint8_t at (*ptr)
155 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
158 /** \brief LDR Exclusive (16 bit)
160 This function performs a exclusive LDR command for 16 bit values.
162 \param [in] ptr Pointer to data
163 \return value of type uint16_t at (*ptr)
165 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
168 /** \brief LDR Exclusive (32 bit)
170 This function performs a exclusive LDR command for 32 bit values.
172 \param [in] ptr Pointer to data
173 \return value of type uint32_t at (*ptr)
175 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
178 /** \brief STR Exclusive (8 bit)
180 This function performs a exclusive STR command for 8 bit values.
182 \param [in] value Value to store
183 \param [in] ptr Pointer to location
184 \return 0 Function succeeded
185 \return 1 Function failed
187 #define __STREXB(value, ptr) __strex(value, ptr)
190 /** \brief STR Exclusive (16 bit)
192 This function performs a exclusive STR command for 16 bit values.
194 \param [in] value Value to store
195 \param [in] ptr Pointer to location
196 \return 0 Function succeeded
197 \return 1 Function failed
199 #define __STREXH(value, ptr) __strex(value, ptr)
202 /** \brief STR Exclusive (32 bit)
204 This function performs a exclusive STR command for 32 bit values.
206 \param [in] value Value to store
207 \param [in] ptr Pointer to location
208 \return 0 Function succeeded
209 \return 1 Function failed
211 #define __STREXW(value, ptr) __strex(value, ptr)
214 /** \brief Remove the exclusive lock
216 This function removes the exclusive lock which is created by LDREX.
219 #define __CLREX __clrex
222 /** \brief Signed Saturate
224 This function saturates a signed value.
226 \param [in] value Value to be saturated
227 \param [in] sat Bit position to saturate to (1..32)
228 \return Saturated value
230 #define __SSAT __ssat
233 /** \brief Unsigned Saturate
235 This function saturates an unsigned value.
237 \param [in] value Value to be saturated
238 \param [in] sat Bit position to saturate to (0..31)
239 \return Saturated value
241 #define __USAT __usat
244 /** \brief Count leading zeros
246 This function counts the number of leading zeros of a data value.
248 \param [in] value Value to count the leading zeros
249 \return number of leading zeros in value
253 #endif /* (__CORTEX_M >= 0x03) */
257 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
258 /* IAR iccarm specific functions */
260 #include <cmsis_iar.h>
263 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
264 /* GNU gcc specific functions */
266 /** \brief No Operation
268 No Operation does nothing. This instruction can be used for code alignment purposes.
270 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
272 __ASM volatile ("nop");
276 /** \brief Wait For Interrupt
278 Wait For Interrupt is a hint instruction that suspends execution
279 until one of a number of events occurs.
281 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
283 __ASM volatile ("wfi");
287 /** \brief Wait For Event
289 Wait For Event is a hint instruction that permits the processor to enter
290 a low-power state until one of a number of events occurs.
292 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
294 __ASM volatile ("wfe");
298 /** \brief Send Event
300 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
302 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
304 __ASM volatile ("sev");
308 /** \brief Instruction Synchronization Barrier
310 Instruction Synchronization Barrier flushes the pipeline in the processor,
311 so that all instructions following the ISB are fetched from cache or
312 memory, after the instruction has been completed.
314 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
316 __ASM volatile ("isb");
320 /** \brief Data Synchronization Barrier
322 This function acts as a special kind of Data Memory Barrier.
323 It completes when all explicit memory accesses before this instruction complete.
325 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
327 __ASM volatile ("dsb");
331 /** \brief Data Memory Barrier
333 This function ensures the apparent order of the explicit memory operations before
334 and after the instruction, without ensuring their completion.
336 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
338 __ASM volatile ("dmb");
342 /** \brief Reverse byte order (32 bit)
344 This function reverses the byte order in integer value.
346 \param [in] value Value to reverse
347 \return Reversed value
349 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
353 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
358 /** \brief Reverse byte order (16 bit)
360 This function reverses the byte order in two unsigned short values.
362 \param [in] value Value to reverse
363 \return Reversed value
365 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
369 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
374 /** \brief Reverse byte order in signed short value
376 This function reverses the byte order in a signed short value with sign extension to integer.
378 \param [in] value Value to reverse
379 \return Reversed value
381 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
385 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
390 #if (__CORTEX_M >= 0x03)
392 /** \brief Reverse bit order of value
394 This function reverses the bit order of the given value.
396 \param [in] value Value to reverse
397 \return Reversed value
399 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
403 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
408 /** \brief LDR Exclusive (8 bit)
410 This function performs a exclusive LDR command for 8 bit value.
412 \param [in] ptr Pointer to data
413 \return value of type uint8_t at (*ptr)
415 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
419 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
424 /** \brief LDR Exclusive (16 bit)
426 This function performs a exclusive LDR command for 16 bit values.
428 \param [in] ptr Pointer to data
429 \return value of type uint16_t at (*ptr)
431 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
435 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
440 /** \brief LDR Exclusive (32 bit)
442 This function performs a exclusive LDR command for 32 bit values.
444 \param [in] ptr Pointer to data
445 \return value of type uint32_t at (*ptr)
447 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
451 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
456 /** \brief STR Exclusive (8 bit)
458 This function performs a exclusive STR command for 8 bit values.
460 \param [in] value Value to store
461 \param [in] ptr Pointer to location
462 \return 0 Function succeeded
463 \return 1 Function failed
465 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
469 __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
474 /** \brief STR Exclusive (16 bit)
476 This function performs a exclusive STR command for 16 bit values.
478 \param [in] value Value to store
479 \param [in] ptr Pointer to location
480 \return 0 Function succeeded
481 \return 1 Function failed
483 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
487 __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
492 /** \brief STR Exclusive (32 bit)
494 This function performs a exclusive STR command for 32 bit values.
496 \param [in] value Value to store
497 \param [in] ptr Pointer to location
498 \return 0 Function succeeded
499 \return 1 Function failed
501 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
505 __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
510 /** \brief Remove the exclusive lock
512 This function removes the exclusive lock which is created by LDREX.
515 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
517 __ASM volatile ("clrex");
521 /** \brief Signed Saturate
523 This function saturates a signed value.
525 \param [in] value Value to be saturated
526 \param [in] sat Bit position to saturate to (1..32)
527 \return Saturated value
529 #define __SSAT(ARG1,ARG2) \
531 uint32_t __RES, __ARG1 = (ARG1); \
532 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
537 /** \brief Unsigned Saturate
539 This function saturates an unsigned value.
541 \param [in] value Value to be saturated
542 \param [in] sat Bit position to saturate to (0..31)
543 \return Saturated value
545 #define __USAT(ARG1,ARG2) \
547 uint32_t __RES, __ARG1 = (ARG1); \
548 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
553 /** \brief Count leading zeros
555 This function counts the number of leading zeros of a data value.
557 \param [in] value Value to count the leading zeros
558 \return number of leading zeros in value
560 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
564 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
568 #endif /* (__CORTEX_M >= 0x03) */
573 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
574 /* TASKING carm specific functions */
577 * The CMSIS functions have been implemented as intrinsics in the compiler.
578 * Please use "carm -?i" to get an up to date list of all intrinsics,
579 * Including the CMSIS ones.
584 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
586 #endif /* __CORE_CMINSTR_H */