3 #include <t_services.h>
9 #define PEEPINGTEST // Define PEEPING test to see the top 4 of FIFO after enabling SPORT RX
12 #define SLEEPDURATION 2000
14 #define SLEEPDURATION 10
17 struct dma_descripter{
18 struct dma_descripter * next_descripter;
19 unsigned int * start_address;
20 unsigned short config;
21 unsigned short x_count;
22 unsigned short x_modify;
25 static struct dma_descripter rx_dma_dsc0, rx_dma_dsc1;
27 unsigned int dummy_buffer0[RXIF_BUFSIZE], dummy_buffer1[RXIF_BUFSIZE];
32 void rx_if_task(VP_INT exinf)
35 vmsk_log(LOG_UPTO(LOG_INFO), LOG_UPTO(LOG_EMERG));
36 syslog(LOG_NOTICE, "Sample program starts (exinf = %d).", (INT) exinf);
38 syscall(serial_ctl_por(TASK_PORTID,
39 (IOCTL_CRLF | IOCTL_FCSND | IOCTL_FCRCV)));
49 0 << 14 | // TCKFE, 0:sample at down edge, 1:sample at up edge
50 0 << 13 | // LATFS, 0:early frame sync, 1:late frame sync
51 0 << 12 | // LTFS, 0:Active high TFS, 1:Active low TFS
52 0 << 11 | // DITFS, 0:data dependent TFS generation, 1:data independent TFS generation
53 0 << 10 | // TFSR, 0:TFS is not required every word, 1:TFS is required every word
54 0 << 9 | // ITFS, 0:external TFS, 1:internal TFS
55 0 << 4 | // TLSBIT, 0:MSB first transmission, 1:LSB first transmission
56 0 << 2 | // TDTYPE 0:normal, 1:reserved, 2:u-law, 3:a-law
57 0 << 1 | // ITCLK, 0:external clock generation, 1:internal clock generation
58 0 << 0 ; // TSPEN 0:Tx disable, 1:Tx enable
61 0 << 10 | // TRFST, 0:left streo ch first, 1:right stereo ch first
62 0 << 9 | // TSFESE, 0:normal frame sync, 1:LR frame clock
63 0 << 8 | // TXSE, 0:secondary ch disable, 1:secondary ch enable
64 0 << 0 ; // SLEN 0-1:not allowed,2-31:Serial word length - 1
68 0 << 14 | // RCKFE, 0:sample at down edge, 1:sample at up edge
69 0 << 13 | // LARFS, 0:early frame sync, 1:late frame sync
70 0 << 12 | // LRFS, 0:Active high RFS, 1:Active low RFS
71 1 << 10 | // RFSR, 0:RFS is not required every word, 1:RFS is required every word
72 0 << 9 | // IRFS, 0:external RFS, 1:internal RFS
73 0 << 4 | // RLSBIT, 0:MSB first transmission, 1:LSB first transmission
74 0 << 2 | // RDTYPE 0:zero fill, 1:sign extend, 2:u-law, 3:a-law
75 0 << 1 | // IRCLK, 0:external clock generation, 1:internal clock generation
76 0 << 0 ; // RSPEN 0:Rx disable, 1:Rx enable
79 0 << 10 | // RRFST, 0:left streo ch first, 1:right stereo ch first
80 0 << 9 | // RSFESE, 0:normal frame sync, 1:LR frame clock
81 1 << 8 | // RXSE, 0:secondary ch disable, 1:secondary ch enable
82 29 << 0 ; // SLEN 0-1:not allowed,2-31:Serial word length - 1
88 rx_dma_dsc0.next_descripter = &rx_dma_dsc1;
89 rx_dma_dsc0.start_address = dummy_buffer0;
90 rx_dma_dsc0.x_count = RXIF_BUFSIZE;
91 rx_dma_dsc0.x_modify = sizeof(dummy_buffer0[0]);
93 7 <<12 | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
94 7 << 8 | // NDSIZE, the # of element of the next descripter to fetch
95 0 << 7 | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
96 1 << 6 | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
97 1 << 5 | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
98 0 << 4 | // DMA2D, 0:Linear DMA, 1:2D DMA
99 2 << 2 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
100 1 << 1 | // WNR, 0:Read from memory, 1:Write to Memory
101 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
103 rx_dma_dsc1.next_descripter = &rx_dma_dsc0;
104 rx_dma_dsc1.start_address = dummy_buffer1;
105 rx_dma_dsc1.x_count = RXIF_BUFSIZE;
106 rx_dma_dsc1.x_modify = sizeof(dummy_buffer1[0]);
108 7 <<12 | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
109 7 << 8 | // NDSIZE, the # of element of the next descripter to fetch
110 0 << 7 | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
111 1 << 6 | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
112 1 << 5 | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
113 0 << 4 | // DMA2D, 0:Linear DMA, 1:2D DMA
114 2 << 2 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
115 1 << 1 | // WNR, 0:Read from memory, 1:Write to Memory
116 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
121 int count = 0, event = 0;
126 *pDMA1_NEXT_DESC_PTR = & rx_dma_dsc0;
127 *pDMA1_CONFIG = rx_dma_dsc1.config;
129 *pSPORT0_RCR1 |= RSPEN; // RX SPORT Enable
142 // FIFOにデータがたまったはずである。
143 // FIFOデータを読みだして下位2bitのみ表示する
144 rx[0] = dummy_buffer0[0]; // 下位2bitのみ抽出
145 rx[1] = dummy_buffer0[1]; // 下位2bitのみ抽出
146 rx[2] = dummy_buffer0[2]; // 下位2bitのみ抽出
147 rx[3] = dummy_buffer0[3]; // 下位2bitのみ抽出
150 *pSPORT0_RCR1 &= ~RSPEN; // RX SPORT disable
155 syslog( LOG_NOTICE, "RX word : %08x,%08x,%08x,%08x", rx[0], rx[1], rx[2], rx[3] );
159 if (!( count % 1000 ))
160 syslog( LOG_NOTICE, "trial : %d, event : %d", count, event);
163 tslp_tsk(SLEEPDURATION);
169 syslog(LOG_NOTICE, "Sample program ends.");