1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15 Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
16 data path or MDP data path.
17 In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
19 MUTEX device node must be siblings to the central MMSYS_CONFIG node.
20 For a description of the MMSYS_CONFIG binding, see
21 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
28 - const: mediatek,mt2701-disp-mutex
30 - const: mediatek,mt2712-disp-mutex
32 - const: mediatek,mt8167-disp-mutex
34 - const: mediatek,mt8173-disp-mutex
36 - const: mediatek,mt8183-disp-mutex
38 - const: mediatek,mt8192-disp-mutex
40 - const: mediatek,mt8195-disp-mutex
48 description: A phandle and PM domain specifier as defined by bindings of
49 the power controller specified by phandle. See
50 Documentation/devicetree/bindings/power/power-domain.yaml for details.
54 - description: MUTEX Clock
58 The event id which is mapping to the specific hardware event signal
59 to gce. The event id is defined in the gce header
60 include/dt-bindings/gce/<chip>-gce.h of each chips.
61 $ref: /schemas/types.yaml#/definitions/uint32-array
70 additionalProperties: false
74 #include <dt-bindings/interrupt-controller/arm-gic.h>
75 #include <dt-bindings/clock/mt8173-clk.h>
76 #include <dt-bindings/power/mt8173-power.h>
77 #include <dt-bindings/gce/mt8173-gce.h>
83 mutex: mutex@14020000 {
84 compatible = "mediatek,mt8173-disp-mutex";
85 reg = <0 0x14020000 0 0x1000>;
86 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
87 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
88 clocks = <&mmsys CLK_MM_MUTEX_32K>;
89 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
90 <CMDQ_EVENT_MUTEX1_STREAM_EOF>;