arch/arm/mach-davinci/devices-da8xx.c

   1 /*
   2  * DA8XX/OMAP L1XX platform device data
   3  *
   4  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
   5  * Derived from code that was:
   6  *      Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/serial_8250.h>
  17 #include <linux/ahci_platform.h>
  18 #include <linux/clk.h>
  19
  20 #include <mach/cputype.h>
  21 #include <mach/common.h>
  22 #include <mach/time.h>
  23 #include <mach/da8xx.h>
  24 #include <mach/cpuidle.h>
  25 #include <mach/sram.h>
  26
  27 #include "clock.h"
  28 #include "asp.h"
  29
  30 #define DA8XX_TPCC_BASE                 0x01c00000
  31 #define DA8XX_TPTC0_BASE                0x01c08000
  32 #define DA8XX_TPTC1_BASE                0x01c08400
  33 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
  34 #define DA8XX_I2C0_BASE                 0x01c22000
  35 #define DA8XX_RTC_BASE                  0x01c23000
  36 #define DA8XX_PRUSS_MEM_BASE            0x01c30000
  37 #define DA8XX_MMCSD0_BASE               0x01c40000
  38 #define DA8XX_SPI0_BASE                 0x01c41000
  39 #define DA830_SPI1_BASE                 0x01e12000
  40 #define DA8XX_LCD_CNTRL_BASE            0x01e13000
  41 #define DA850_SATA_BASE                 0x01e18000
  42 #define DA850_MMCSD1_BASE               0x01e1b000
  43 #define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
  44 #define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
  45 #define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
  46 #define DA8XX_EMAC_MDIO_BASE            0x01e24000
  47 #define DA8XX_I2C1_BASE                 0x01e28000
  48 #define DA850_TPCC1_BASE                0x01e30000
  49 #define DA850_TPTC2_BASE                0x01e38000
  50 #define DA850_SPI1_BASE                 0x01f0e000
  51 #define DA8XX_DDR2_CTL_BASE             0xb0000000
  52
  53 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
  54 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
  55 #define DA8XX_EMAC_RAM_OFFSET           0x0000
  56 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
  57
  58 #define DA8XX_DMA_SPI0_RX       EDMA_CTLR_CHAN(0, 14)
  59 #define DA8XX_DMA_SPI0_TX       EDMA_CTLR_CHAN(0, 15)
  60 #define DA8XX_DMA_MMCSD0_RX     EDMA_CTLR_CHAN(0, 16)
  61 #define DA8XX_DMA_MMCSD0_TX     EDMA_CTLR_CHAN(0, 17)
  62 #define DA8XX_DMA_SPI1_RX       EDMA_CTLR_CHAN(0, 18)
  63 #define DA8XX_DMA_SPI1_TX       EDMA_CTLR_CHAN(0, 19)
  64 #define DA850_DMA_MMCSD1_RX     EDMA_CTLR_CHAN(1, 28)
  65 #define DA850_DMA_MMCSD1_TX     EDMA_CTLR_CHAN(1, 29)
  66
  67 void __iomem *da8xx_syscfg0_base;
  68 void __iomem *da8xx_syscfg1_base;
  69
  70 static struct plat_serial8250_port da8xx_serial_pdata[] = {
  71         {
  72                 .mapbase        = DA8XX_UART0_BASE,
  73                 .irq            = IRQ_DA8XX_UARTINT0,
  74                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  75                                         UPF_IOREMAP,
  76                 .iotype         = UPIO_MEM,
  77                 .regshift       = 2,
  78         },
  79         {
  80                 .mapbase        = DA8XX_UART1_BASE,
  81                 .irq            = IRQ_DA8XX_UARTINT1,
  82                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  83                                         UPF_IOREMAP,
  84                 .iotype         = UPIO_MEM,
  85                 .regshift       = 2,
  86         },
  87         {
  88                 .mapbase        = DA8XX_UART2_BASE,
  89                 .irq            = IRQ_DA8XX_UARTINT2,
  90                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  91                                         UPF_IOREMAP,
  92                 .iotype         = UPIO_MEM,
  93                 .regshift       = 2,
  94         },
  95         {
  96                 .flags  = 0,
  97         },
  98 };
  99
 100 struct platform_device da8xx_serial_device = {
 101         .name   = "serial8250",
 102         .id     = PLAT8250_DEV_PLATFORM,
 103         .dev    = {
 104                 .platform_data  = da8xx_serial_pdata,
 105         },
 106 };
 107
 108 static const s8 da8xx_queue_tc_mapping[][2] = {
 109         /* {event queue no, TC no} */
 110         {0, 0},
 111         {1, 1},
 112         {-1, -1}
 113 };
 114
 115 static const s8 da8xx_queue_priority_mapping[][2] = {
 116         /* {event queue no, Priority} */
 117         {0, 3},
 118         {1, 7},
 119         {-1, -1}
 120 };
 121
 122 static const s8 da850_queue_tc_mapping[][2] = {
 123         /* {event queue no, TC no} */
 124         {0, 0},
 125         {-1, -1}
 126 };
 127
 128 static const s8 da850_queue_priority_mapping[][2] = {
 129         /* {event queue no, Priority} */
 130         {0, 3},
 131         {-1, -1}
 132 };
 133
 134 static struct edma_soc_info da830_edma_cc0_info = {
 135         .n_channel              = 32,
 136         .n_region               = 4,
 137         .n_slot                 = 128,
 138         .n_tc                   = 2,
 139         .n_cc                   = 1,
 140         .queue_tc_mapping       = da8xx_queue_tc_mapping,
 141         .queue_priority_mapping = da8xx_queue_priority_mapping,
 142         .default_queue          = EVENTQ_1,
 143 };
 144
 145 static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
 146         &da830_edma_cc0_info,
 147 };
 148
 149 static struct edma_soc_info da850_edma_cc_info[] = {
 150         {
 151                 .n_channel              = 32,
 152                 .n_region               = 4,
 153                 .n_slot                 = 128,
 154                 .n_tc                   = 2,
 155                 .n_cc                   = 1,
 156                 .queue_tc_mapping       = da8xx_queue_tc_mapping,
 157                 .queue_priority_mapping = da8xx_queue_priority_mapping,
 158                 .default_queue          = EVENTQ_1,
 159         },
 160         {
 161                 .n_channel              = 32,
 162                 .n_region               = 4,
 163                 .n_slot                 = 128,
 164                 .n_tc                   = 1,
 165                 .n_cc                   = 1,
 166                 .queue_tc_mapping       = da850_queue_tc_mapping,
 167                 .queue_priority_mapping = da850_queue_priority_mapping,
 168                 .default_queue          = EVENTQ_0,
 169         },
 170 };
 171
 172 static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
 173         &da850_edma_cc_info[0],
 174         &da850_edma_cc_info[1],
 175 };
 176
 177 static struct resource da830_edma_resources[] = {
 178         {
 179                 .name   = "edma_cc0",
 180                 .start  = DA8XX_TPCC_BASE,
 181                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 182                 .flags  = IORESOURCE_MEM,
 183         },
 184         {
 185                 .name   = "edma_tc0",
 186                 .start  = DA8XX_TPTC0_BASE,
 187                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 188                 .flags  = IORESOURCE_MEM,
 189         },
 190         {
 191                 .name   = "edma_tc1",
 192                 .start  = DA8XX_TPTC1_BASE,
 193                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 194                 .flags  = IORESOURCE_MEM,
 195         },
 196         {
 197                 .name   = "edma0",
 198                 .start  = IRQ_DA8XX_CCINT0,
 199                 .flags  = IORESOURCE_IRQ,
 200         },
 201         {
 202                 .name   = "edma0_err",
 203                 .start  = IRQ_DA8XX_CCERRINT,
 204                 .flags  = IORESOURCE_IRQ,
 205         },
 206 };
 207
 208 static struct resource da850_edma_resources[] = {
 209         {
 210                 .name   = "edma_cc0",
 211                 .start  = DA8XX_TPCC_BASE,
 212                 .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         {
 216                 .name   = "edma_tc0",
 217                 .start  = DA8XX_TPTC0_BASE,
 218                 .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
 219                 .flags  = IORESOURCE_MEM,
 220         },
 221         {
 222                 .name   = "edma_tc1",
 223                 .start  = DA8XX_TPTC1_BASE,
 224                 .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
 225                 .flags  = IORESOURCE_MEM,
 226         },
 227         {
 228                 .name   = "edma_cc1",
 229                 .start  = DA850_TPCC1_BASE,
 230                 .end    = DA850_TPCC1_BASE + SZ_32K - 1,
 231                 .flags  = IORESOURCE_MEM,
 232         },
 233         {
 234                 .name   = "edma_tc2",
 235                 .start  = DA850_TPTC2_BASE,
 236                 .end    = DA850_TPTC2_BASE + SZ_1K - 1,
 237                 .flags  = IORESOURCE_MEM,
 238         },
 239         {
 240                 .name   = "edma0",
 241                 .start  = IRQ_DA8XX_CCINT0,
 242                 .flags  = IORESOURCE_IRQ,
 243         },
 244         {
 245                 .name   = "edma0_err",
 246                 .start  = IRQ_DA8XX_CCERRINT,
 247                 .flags  = IORESOURCE_IRQ,
 248         },
 249         {
 250                 .name   = "edma1",
 251                 .start  = IRQ_DA850_CCINT1,
 252                 .flags  = IORESOURCE_IRQ,
 253         },
 254         {
 255                 .name   = "edma1_err",
 256                 .start  = IRQ_DA850_CCERRINT1,
 257                 .flags  = IORESOURCE_IRQ,
 258         },
 259 };
 260
 261 static struct platform_device da830_edma_device = {
 262         .name           = "edma",
 263         .id             = -1,
 264         .dev = {
 265                 .platform_data = da830_edma_info,
 266         },
 267         .num_resources  = ARRAY_SIZE(da830_edma_resources),
 268         .resource       = da830_edma_resources,
 269 };
 270
 271 static struct platform_device da850_edma_device = {
 272         .name           = "edma",
 273         .id             = -1,
 274         .dev = {
 275                 .platform_data = da850_edma_info,
 276         },
 277         .num_resources  = ARRAY_SIZE(da850_edma_resources),
 278         .resource       = da850_edma_resources,
 279 };
 280
 281 int __init da830_register_edma(struct edma_rsv_info *rsv)
 282 {
 283         da830_edma_cc0_info.rsv = rsv;
 284
 285         return platform_device_register(&da830_edma_device);
 286 }
 287
 288 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
 289 {
 290         if (rsv) {
 291                 da850_edma_cc_info[0].rsv = rsv[0];
 292                 da850_edma_cc_info[1].rsv = rsv[1];
 293         }
 294
 295         return platform_device_register(&da850_edma_device);
 296 }
 297
 298 static struct resource da8xx_i2c_resources0[] = {
 299         {
 300                 .start  = DA8XX_I2C0_BASE,
 301                 .end    = DA8XX_I2C0_BASE + SZ_4K - 1,
 302                 .flags  = IORESOURCE_MEM,
 303         },
 304         {
 305                 .start  = IRQ_DA8XX_I2CINT0,
 306                 .end    = IRQ_DA8XX_I2CINT0,
 307                 .flags  = IORESOURCE_IRQ,
 308         },
 309 };
 310
 311 static struct platform_device da8xx_i2c_device0 = {
 312         .name           = "i2c_davinci",
 313         .id             = 1,
 314         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources0),
 315         .resource       = da8xx_i2c_resources0,
 316 };
 317
 318 static struct resource da8xx_i2c_resources1[] = {
 319         {
 320                 .start  = DA8XX_I2C1_BASE,
 321                 .end    = DA8XX_I2C1_BASE + SZ_4K - 1,
 322                 .flags  = IORESOURCE_MEM,
 323         },
 324         {
 325                 .start  = IRQ_DA8XX_I2CINT1,
 326                 .end    = IRQ_DA8XX_I2CINT1,
 327                 .flags  = IORESOURCE_IRQ,
 328         },
 329 };
 330
 331 static struct platform_device da8xx_i2c_device1 = {
 332         .name           = "i2c_davinci",
 333         .id             = 2,
 334         .num_resources  = ARRAY_SIZE(da8xx_i2c_resources1),
 335         .resource       = da8xx_i2c_resources1,
 336 };
 337
 338 int __init da8xx_register_i2c(int instance,
 339                 struct davinci_i2c_platform_data *pdata)
 340 {
 341         struct platform_device *pdev;
 342
 343         if (instance == 0)
 344                 pdev = &da8xx_i2c_device0;
 345         else if (instance == 1)
 346                 pdev = &da8xx_i2c_device1;
 347         else
 348                 return -EINVAL;
 349
 350         pdev->dev.platform_data = pdata;
 351         return platform_device_register(pdev);
 352 }
 353
 354 static struct resource da8xx_watchdog_resources[] = {
 355         {
 356                 .start  = DA8XX_WDOG_BASE,
 357                 .end    = DA8XX_WDOG_BASE + SZ_4K - 1,
 358                 .flags  = IORESOURCE_MEM,
 359         },
 360 };
 361
 362 struct platform_device da8xx_wdt_device = {
 363         .name           = "watchdog",
 364         .id             = -1,
 365         .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
 366         .resource       = da8xx_watchdog_resources,
 367 };
 368
 369 void da8xx_restart(char mode, const char *cmd)
 370 {
 371         davinci_watchdog_reset(&da8xx_wdt_device);
 372 }
 373
 374 int __init da8xx_register_watchdog(void)
 375 {
 376         return platform_device_register(&da8xx_wdt_device);
 377 }
 378
 379 static struct resource da8xx_emac_resources[] = {
 380         {
 381                 .start  = DA8XX_EMAC_CPPI_PORT_BASE,
 382                 .end    = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
 383                 .flags  = IORESOURCE_MEM,
 384         },
 385         {
 386                 .start  = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 387                 .end    = IRQ_DA8XX_C0_RX_THRESH_PULSE,
 388                 .flags  = IORESOURCE_IRQ,
 389         },
 390         {
 391                 .start  = IRQ_DA8XX_C0_RX_PULSE,
 392                 .end    = IRQ_DA8XX_C0_RX_PULSE,
 393                 .flags  = IORESOURCE_IRQ,
 394         },
 395         {
 396                 .start  = IRQ_DA8XX_C0_TX_PULSE,
 397                 .end    = IRQ_DA8XX_C0_TX_PULSE,
 398                 .flags  = IORESOURCE_IRQ,
 399         },
 400         {
 401                 .start  = IRQ_DA8XX_C0_MISC_PULSE,
 402                 .end    = IRQ_DA8XX_C0_MISC_PULSE,
 403                 .flags  = IORESOURCE_IRQ,
 404         },
 405 };
 406
 407 struct emac_platform_data da8xx_emac_pdata = {
 408         .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
 409         .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
 410         .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
 411         .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
 412         .version                = EMAC_VERSION_2,
 413 };
 414
 415 static struct platform_device da8xx_emac_device = {
 416         .name           = "davinci_emac",
 417         .id             = 1,
 418         .dev = {
 419                 .platform_data  = &da8xx_emac_pdata,
 420         },
 421         .num_resources  = ARRAY_SIZE(da8xx_emac_resources),
 422         .resource       = da8xx_emac_resources,
 423 };
 424
 425 static struct resource da8xx_mdio_resources[] = {
 426         {
 427                 .start  = DA8XX_EMAC_MDIO_BASE,
 428                 .end    = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
 429                 .flags  = IORESOURCE_MEM,
 430         },
 431 };
 432
 433 static struct platform_device da8xx_mdio_device = {
 434         .name           = "davinci_mdio",
 435         .id             = 0,
 436         .num_resources  = ARRAY_SIZE(da8xx_mdio_resources),
 437         .resource       = da8xx_mdio_resources,
 438 };
 439
 440 int __init da8xx_register_emac(void)
 441 {
 442         int ret;
 443
 444         ret = platform_device_register(&da8xx_mdio_device);
 445         if (ret < 0)
 446                 return ret;
 447         ret = platform_device_register(&da8xx_emac_device);
 448         if (ret < 0)
 449                 return ret;
 450         ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
 451                             NULL, &da8xx_emac_device.dev);
 452         return ret;
 453 }
 454
 455 static struct resource da830_mcasp1_resources[] = {
 456         {
 457                 .name   = "mcasp1",
 458                 .start  = DAVINCI_DA830_MCASP1_REG_BASE,
 459                 .end    = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
 460                 .flags  = IORESOURCE_MEM,
 461         },
 462         /* TX event */
 463         {
 464                 .start  = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 465                 .end    = DAVINCI_DA830_DMA_MCASP1_AXEVT,
 466                 .flags  = IORESOURCE_DMA,
 467         },
 468         /* RX event */
 469         {
 470                 .start  = DAVINCI_DA830_DMA_MCASP1_AREVT,
 471                 .end    = DAVINCI_DA830_DMA_MCASP1_AREVT,
 472                 .flags  = IORESOURCE_DMA,
 473         },
 474 };
 475
 476 static struct platform_device da830_mcasp1_device = {
 477         .name           = "davinci-mcasp",
 478         .id             = 1,
 479         .num_resources  = ARRAY_SIZE(da830_mcasp1_resources),
 480         .resource       = da830_mcasp1_resources,
 481 };
 482
 483 static struct resource da850_mcasp_resources[] = {
 484         {
 485                 .name   = "mcasp",
 486                 .start  = DAVINCI_DA8XX_MCASP0_REG_BASE,
 487                 .end    = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
 488                 .flags  = IORESOURCE_MEM,
 489         },
 490         /* TX event */
 491         {
 492                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 493                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
 494                 .flags  = IORESOURCE_DMA,
 495         },
 496         /* RX event */
 497         {
 498                 .start  = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 499                 .end    = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
 500                 .flags  = IORESOURCE_DMA,
 501         },
 502 };
 503
 504 static struct platform_device da850_mcasp_device = {
 505         .name           = "davinci-mcasp",
 506         .id             = 0,
 507         .num_resources  = ARRAY_SIZE(da850_mcasp_resources),
 508         .resource       = da850_mcasp_resources,
 509 };
 510
 511 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
 512 {
 513         /* DA830/OMAP-L137 has 3 instances of McASP */
 514         if (cpu_is_davinci_da830() && id == 1) {
 515                 da830_mcasp1_device.dev.platform_data = pdata;
 516                 platform_device_register(&da830_mcasp1_device);
 517         } else if (cpu_is_davinci_da850()) {
 518                 da850_mcasp_device.dev.platform_data = pdata;
 519                 platform_device_register(&da850_mcasp_device);
 520         }
 521 }
 522
 523 static struct resource da8xx_pruss_resources[] = {
 524         {
 525                 .start  = DA8XX_PRUSS_MEM_BASE,
 526                 .end    = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
 527                 .flags  = IORESOURCE_MEM,
 528         },
 529         {
 530                 .start  = IRQ_DA8XX_EVTOUT0,
 531                 .end    = IRQ_DA8XX_EVTOUT0,
 532                 .flags  = IORESOURCE_IRQ,
 533         },
 534         {
 535                 .start  = IRQ_DA8XX_EVTOUT1,
 536                 .end    = IRQ_DA8XX_EVTOUT1,
 537                 .flags  = IORESOURCE_IRQ,
 538         },
 539         {
 540                 .start  = IRQ_DA8XX_EVTOUT2,
 541                 .end    = IRQ_DA8XX_EVTOUT2,
 542                 .flags  = IORESOURCE_IRQ,
 543         },
 544         {
 545                 .start  = IRQ_DA8XX_EVTOUT3,
 546                 .end    = IRQ_DA8XX_EVTOUT3,
 547                 .flags  = IORESOURCE_IRQ,
 548         },
 549         {
 550                 .start  = IRQ_DA8XX_EVTOUT4,
 551                 .end    = IRQ_DA8XX_EVTOUT4,
 552                 .flags  = IORESOURCE_IRQ,
 553         },
 554         {
 555                 .start  = IRQ_DA8XX_EVTOUT5,
 556                 .end    = IRQ_DA8XX_EVTOUT5,
 557                 .flags  = IORESOURCE_IRQ,
 558         },
 559         {
 560                 .start  = IRQ_DA8XX_EVTOUT6,
 561                 .end    = IRQ_DA8XX_EVTOUT6,
 562                 .flags  = IORESOURCE_IRQ,
 563         },
 564         {
 565                 .start  = IRQ_DA8XX_EVTOUT7,
 566                 .end    = IRQ_DA8XX_EVTOUT7,
 567                 .flags  = IORESOURCE_IRQ,
 568         },
 569 };
 570
 571 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
 572         .pintc_base     = 0x4000,
 573 };
 574
 575 static struct platform_device da8xx_uio_pruss_dev = {
 576         .name           = "pruss_uio",
 577         .id             = -1,
 578         .num_resources  = ARRAY_SIZE(da8xx_pruss_resources),
 579         .resource       = da8xx_pruss_resources,
 580         .dev            = {
 581                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 582                 .platform_data          = &da8xx_uio_pruss_pdata,
 583         }
 584 };
 585
 586 int __init da8xx_register_uio_pruss(void)
 587 {
 588         da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
 589         return platform_device_register(&da8xx_uio_pruss_dev);
 590 }
 591
 592 static const struct display_panel disp_panel = {
 593         QVGA,
 594         16,
 595         16,
 596         COLOR_ACTIVE,
 597 };
 598
 599 static struct lcd_ctrl_config lcd_cfg = {
 600         &disp_panel,
 601         .ac_bias                = 255,
 602         .ac_bias_intrpt         = 0,
 603         .dma_burst_sz           = 16,
 604         .bpp                    = 16,
 605         .fdd                    = 255,
 606         .tft_alt_mode           = 0,
 607         .stn_565_mode           = 0,
 608         .mono_8bit_mode         = 0,
 609         .invert_line_clock      = 1,
 610         .invert_frm_clock       = 1,
 611         .sync_edge              = 0,
 612         .sync_ctrl              = 1,
 613         .raster_order           = 0,
 614         .fifo_th                = 6,
 615 };
 616
 617 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
 618         .manu_name              = "sharp",
 619         .controller_data        = &lcd_cfg,
 620         .type                   = "Sharp_LCD035Q3DG01",
 621 };
 622
 623 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
 624         .manu_name              = "sharp",
 625         .controller_data        = &lcd_cfg,
 626         .type                   = "Sharp_LK043T1DG01",
 627 };
 628
 629 static struct resource da8xx_lcdc_resources[] = {
 630         [0] = { /* registers */
 631                 .start  = DA8XX_LCD_CNTRL_BASE,
 632                 .end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
 633                 .flags  = IORESOURCE_MEM,
 634         },
 635         [1] = { /* interrupt */
 636                 .start  = IRQ_DA8XX_LCDINT,
 637                 .end    = IRQ_DA8XX_LCDINT,
 638                 .flags  = IORESOURCE_IRQ,
 639         },
 640 };
 641
 642 static struct platform_device da8xx_lcdc_device = {
 643         .name           = "da8xx_lcdc",
 644         .id             = 0,
 645         .num_resources  = ARRAY_SIZE(da8xx_lcdc_resources),
 646         .resource       = da8xx_lcdc_resources,
 647 };
 648
 649 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
 650 {
 651         da8xx_lcdc_device.dev.platform_data = pdata;
 652         return platform_device_register(&da8xx_lcdc_device);
 653 }
 654
 655 static struct resource da8xx_mmcsd0_resources[] = {
 656         {               /* registers */
 657                 .start  = DA8XX_MMCSD0_BASE,
 658                 .end    = DA8XX_MMCSD0_BASE + SZ_4K - 1,
 659                 .flags  = IORESOURCE_MEM,
 660         },
 661         {               /* interrupt */
 662                 .start  = IRQ_DA8XX_MMCSDINT0,
 663                 .end    = IRQ_DA8XX_MMCSDINT0,
 664                 .flags  = IORESOURCE_IRQ,
 665         },
 666         {               /* DMA RX */
 667                 .start  = DA8XX_DMA_MMCSD0_RX,
 668                 .end    = DA8XX_DMA_MMCSD0_RX,
 669                 .flags  = IORESOURCE_DMA,
 670         },
 671         {               /* DMA TX */
 672                 .start  = DA8XX_DMA_MMCSD0_TX,
 673                 .end    = DA8XX_DMA_MMCSD0_TX,
 674                 .flags  = IORESOURCE_DMA,
 675         },
 676 };
 677
 678 static struct platform_device da8xx_mmcsd0_device = {
 679         .name           = "davinci_mmc",
 680         .id             = 0,
 681         .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
 682         .resource       = da8xx_mmcsd0_resources,
 683 };
 684
 685 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
 686 {
 687         da8xx_mmcsd0_device.dev.platform_data = config;
 688         return platform_device_register(&da8xx_mmcsd0_device);
 689 }
 690
 691 #ifdef CONFIG_ARCH_DAVINCI_DA850
 692 static struct resource da850_mmcsd1_resources[] = {
 693         {               /* registers */
 694                 .start  = DA850_MMCSD1_BASE,
 695                 .end    = DA850_MMCSD1_BASE + SZ_4K - 1,
 696                 .flags  = IORESOURCE_MEM,
 697         },
 698         {               /* interrupt */
 699                 .start  = IRQ_DA850_MMCSDINT0_1,
 700                 .end    = IRQ_DA850_MMCSDINT0_1,
 701                 .flags  = IORESOURCE_IRQ,
 702         },
 703         {               /* DMA RX */
 704                 .start  = DA850_DMA_MMCSD1_RX,
 705                 .end    = DA850_DMA_MMCSD1_RX,
 706                 .flags  = IORESOURCE_DMA,
 707         },
 708         {               /* DMA TX */
 709                 .start  = DA850_DMA_MMCSD1_TX,
 710                 .end    = DA850_DMA_MMCSD1_TX,
 711                 .flags  = IORESOURCE_DMA,
 712         },
 713 };
 714
 715 static struct platform_device da850_mmcsd1_device = {
 716         .name           = "davinci_mmc",
 717         .id             = 1,
 718         .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
 719         .resource       = da850_mmcsd1_resources,
 720 };
 721
 722 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
 723 {
 724         da850_mmcsd1_device.dev.platform_data = config;
 725         return platform_device_register(&da850_mmcsd1_device);
 726 }
 727 #endif
 728
 729 static struct resource da8xx_rtc_resources[] = {
 730         {
 731                 .start          = DA8XX_RTC_BASE,
 732                 .end            = DA8XX_RTC_BASE + SZ_4K - 1,
 733                 .flags          = IORESOURCE_MEM,
 734         },
 735         { /* timer irq */
 736                 .start          = IRQ_DA8XX_RTC,
 737                 .end            = IRQ_DA8XX_RTC,
 738                 .flags          = IORESOURCE_IRQ,
 739         },
 740         { /* alarm irq */
 741                 .start          = IRQ_DA8XX_RTC,
 742                 .end            = IRQ_DA8XX_RTC,
 743                 .flags          = IORESOURCE_IRQ,
 744         },
 745 };
 746
 747 static struct platform_device da8xx_rtc_device = {
 748         .name           = "omap_rtc",
 749         .id             = -1,
 750         .num_resources  = ARRAY_SIZE(da8xx_rtc_resources),
 751         .resource       = da8xx_rtc_resources,
 752 };
 753
 754 int da8xx_register_rtc(void)
 755 {
 756         int ret;
 757         void __iomem *base;
 758
 759         base = ioremap(DA8XX_RTC_BASE, SZ_4K);
 760         if (WARN_ON(!base))
 761                 return -ENOMEM;
 762
 763         /* Unlock the rtc's registers */
 764         __raw_writel(0x83e70b13, base + 0x6c);
 765         __raw_writel(0x95a4f1e0, base + 0x70);
 766
 767         iounmap(base);
 768
 769         ret = platform_device_register(&da8xx_rtc_device);
 770         if (!ret)
 771                 /* Atleast on DA850, RTC is a wakeup source */
 772                 device_init_wakeup(&da8xx_rtc_device.dev, true);
 773
 774         return ret;
 775 }
 776
 777 static void __iomem *da8xx_ddr2_ctlr_base;
 778 void __iomem * __init da8xx_get_mem_ctlr(void)
 779 {
 780         if (da8xx_ddr2_ctlr_base)
 781                 return da8xx_ddr2_ctlr_base;
 782
 783         da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
 784         if (!da8xx_ddr2_ctlr_base)
 785                 pr_warning("%s: Unable to map DDR2 controller", __func__);
 786
 787         return da8xx_ddr2_ctlr_base;
 788 }
 789
 790 static struct resource da8xx_cpuidle_resources[] = {
 791         {
 792                 .start          = DA8XX_DDR2_CTL_BASE,
 793                 .end            = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
 794                 .flags          = IORESOURCE_MEM,
 795         },
 796 };
 797
 798 /* DA8XX devices support DDR2 power down */
 799 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
 800         .ddr2_pdown     = 1,
 801 };
 802
 803
 804 static struct platform_device da8xx_cpuidle_device = {
 805         .name                   = "cpuidle-davinci",
 806         .num_resources          = ARRAY_SIZE(da8xx_cpuidle_resources),
 807         .resource               = da8xx_cpuidle_resources,
 808         .dev = {
 809                 .platform_data  = &da8xx_cpuidle_pdata,
 810         },
 811 };
 812
 813 int __init da8xx_register_cpuidle(void)
 814 {
 815         da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
 816
 817         return platform_device_register(&da8xx_cpuidle_device);
 818 }
 819
 820 static struct resource da8xx_spi0_resources[] = {
 821         [0] = {
 822                 .start  = DA8XX_SPI0_BASE,
 823                 .end    = DA8XX_SPI0_BASE + SZ_4K - 1,
 824                 .flags  = IORESOURCE_MEM,
 825         },
 826         [1] = {
 827                 .start  = IRQ_DA8XX_SPINT0,
 828                 .end    = IRQ_DA8XX_SPINT0,
 829                 .flags  = IORESOURCE_IRQ,
 830         },
 831         [2] = {
 832                 .start  = DA8XX_DMA_SPI0_RX,
 833                 .end    = DA8XX_DMA_SPI0_RX,
 834                 .flags  = IORESOURCE_DMA,
 835         },
 836         [3] = {
 837                 .start  = DA8XX_DMA_SPI0_TX,
 838                 .end    = DA8XX_DMA_SPI0_TX,
 839                 .flags  = IORESOURCE_DMA,
 840         },
 841 };
 842
 843 static struct resource da8xx_spi1_resources[] = {
 844         [0] = {
 845                 .start  = DA830_SPI1_BASE,
 846                 .end    = DA830_SPI1_BASE + SZ_4K - 1,
 847                 .flags  = IORESOURCE_MEM,
 848         },
 849         [1] = {
 850                 .start  = IRQ_DA8XX_SPINT1,
 851                 .end    = IRQ_DA8XX_SPINT1,
 852                 .flags  = IORESOURCE_IRQ,
 853         },
 854         [2] = {
 855                 .start  = DA8XX_DMA_SPI1_RX,
 856                 .end    = DA8XX_DMA_SPI1_RX,
 857                 .flags  = IORESOURCE_DMA,
 858         },
 859         [3] = {
 860                 .start  = DA8XX_DMA_SPI1_TX,
 861                 .end    = DA8XX_DMA_SPI1_TX,
 862                 .flags  = IORESOURCE_DMA,
 863         },
 864 };
 865
 866 struct davinci_spi_platform_data da8xx_spi_pdata[] = {
 867         [0] = {
 868                 .version        = SPI_VERSION_2,
 869                 .intr_line      = 1,
 870                 .dma_event_q    = EVENTQ_0,
 871         },
 872         [1] = {
 873                 .version        = SPI_VERSION_2,
 874                 .intr_line      = 1,
 875                 .dma_event_q    = EVENTQ_0,
 876         },
 877 };
 878
 879 static struct platform_device da8xx_spi_device[] = {
 880         [0] = {
 881                 .name           = "spi_davinci",
 882                 .id             = 0,
 883                 .num_resources  = ARRAY_SIZE(da8xx_spi0_resources),
 884                 .resource       = da8xx_spi0_resources,
 885                 .dev            = {
 886                         .platform_data = &da8xx_spi_pdata[0],
 887                 },
 888         },
 889         [1] = {
 890                 .name           = "spi_davinci",
 891                 .id             = 1,
 892                 .num_resources  = ARRAY_SIZE(da8xx_spi1_resources),
 893                 .resource       = da8xx_spi1_resources,
 894                 .dev            = {
 895                         .platform_data = &da8xx_spi_pdata[1],
 896                 },
 897         },
 898 };
 899
 900 int __init da8xx_register_spi(int instance, const struct spi_board_info *info,
 901                               unsigned len)
 902 {
 903         int ret;
 904
 905         if (instance < 0 || instance > 1)
 906                 return -EINVAL;
 907
 908         ret = spi_register_board_info(info, len);
 909         if (ret)
 910                 pr_warning("%s: failed to register board info for spi %d :"
 911                            " %d\n", __func__, instance, ret);
 912
 913         da8xx_spi_pdata[instance].num_chipselect = len;
 914
 915         if (instance == 1 && cpu_is_davinci_da850()) {
 916                 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
 917                 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
 918         }
 919
 920         return platform_device_register(&da8xx_spi_device[instance]);
 921 }
 922
 923 #ifdef CONFIG_ARCH_DAVINCI_DA850
 924
 925 static struct resource da850_sata_resources[] = {
 926         {
 927                 .start  = DA850_SATA_BASE,
 928                 .end    = DA850_SATA_BASE + 0x1fff,
 929                 .flags  = IORESOURCE_MEM,
 930         },
 931         {
 932                 .start  = IRQ_DA850_SATAINT,
 933                 .flags  = IORESOURCE_IRQ,
 934         },
 935 };
 936
 937 /* SATA PHY Control Register offset from AHCI base */
 938 #define SATA_P0PHYCR_REG        0x178
 939
 940 #define SATA_PHY_MPY(x)         ((x) << 0)
 941 #define SATA_PHY_LOS(x)         ((x) << 6)
 942 #define SATA_PHY_RXCDR(x)       ((x) << 10)
 943 #define SATA_PHY_RXEQ(x)        ((x) << 13)
 944 #define SATA_PHY_TXSWING(x)     ((x) << 19)
 945 #define SATA_PHY_ENPLL(x)       ((x) << 31)
 946
 947 static struct clk *da850_sata_clk;
 948 static unsigned long da850_sata_refclkpn;
 949
 950 /* Supported DA850 SATA crystal frequencies */
 951 #define KHZ_TO_HZ(freq) ((freq) * 1000)
 952 static unsigned long da850_sata_xtal[] = {
 953         KHZ_TO_HZ(300000),
 954         KHZ_TO_HZ(250000),
 955         0,                      /* Reserved */
 956         KHZ_TO_HZ(187500),
 957         KHZ_TO_HZ(150000),
 958         KHZ_TO_HZ(125000),
 959         KHZ_TO_HZ(120000),
 960         KHZ_TO_HZ(100000),
 961         KHZ_TO_HZ(75000),
 962         KHZ_TO_HZ(60000),
 963 };
 964
 965 static int da850_sata_init(struct device *dev, void __iomem *addr)
 966 {
 967         int i, ret;
 968         unsigned int val;
 969
 970         da850_sata_clk = clk_get(dev, NULL);
 971         if (IS_ERR(da850_sata_clk))
 972                 return PTR_ERR(da850_sata_clk);
 973
 974         ret = clk_prepare_enable(da850_sata_clk);
 975         if (ret)
 976                 goto err0;
 977
 978         /* Enable SATA clock receiver */
 979         val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
 980         val &= ~BIT(0);
 981         __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
 982
 983         /* Get the multiplier needed for 1.5GHz PLL output */
 984         for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
 985                 if (da850_sata_xtal[i] == da850_sata_refclkpn)
 986                         break;
 987
 988         if (i == ARRAY_SIZE(da850_sata_xtal)) {
 989                 ret = -EINVAL;
 990                 goto err1;
 991         }
 992
 993         val = SATA_PHY_MPY(i + 1) |
 994                 SATA_PHY_LOS(1) |
 995                 SATA_PHY_RXCDR(4) |
 996                 SATA_PHY_RXEQ(1) |
 997                 SATA_PHY_TXSWING(3) |
 998                 SATA_PHY_ENPLL(1);
 999
1000         __raw_writel(val, addr + SATA_P0PHYCR_REG);
1001
1002         return 0;
1003
1004 err1:
1005         clk_disable_unprepare(da850_sata_clk);
1006 err0:
1007         clk_put(da850_sata_clk);
1008         return ret;
1009 }
1010
1011 static void da850_sata_exit(struct device *dev)
1012 {
1013         clk_disable_unprepare(da850_sata_clk);
1014         clk_put(da850_sata_clk);
1015 }
1016
1017 static struct ahci_platform_data da850_sata_pdata = {
1018         .init   = da850_sata_init,
1019         .exit   = da850_sata_exit,
1020 };
1021
1022 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1023
1024 static struct platform_device da850_sata_device = {
1025         .name   = "ahci",
1026         .id     = -1,
1027         .dev    = {
1028                 .platform_data          = &da850_sata_pdata,
1029                 .dma_mask               = &da850_sata_dmamask,
1030                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1031         },
1032         .num_resources  = ARRAY_SIZE(da850_sata_resources),
1033         .resource       = da850_sata_resources,
1034 };
1035
1036 int __init da850_register_sata(unsigned long refclkpn)
1037 {
1038         da850_sata_refclkpn = refclkpn;
1039         if (!da850_sata_refclkpn)
1040                 return -EINVAL;
1041
1042         return platform_device_register(&da850_sata_device);
1043 }
1044 #endif