arch/h8300/kernel/timer/timer8.c

   1 /*
   2  *  linux/arch/h8300/kernel/cpu/timer/timer8.c
   3  *
   4  *  Yoshinori Sato <ysato@users.sourcefoge.jp>
   5  *
   6  *  8bit Timer driver
   7  *
   8  */
   9
  10 #include <linux/errno.h>
  11 #include <linux/sched.h>
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/slab.h>
  17 #include <linux/clocksource.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/module.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/irq.h>
  23 #include <asm/timer.h>
  24
  25 #define _8TCR   0
  26 #define _8TCSR  2
  27 #define TCORA   4
  28 #define TCORB   6
  29 #define _8TCNT  8
  30
  31 #define FLAG_REPROGRAM (1 << 0)
  32 #define FLAG_SKIPEVENT (1 << 1)
  33 #define FLAG_IRQCONTEXT (1 << 2)
  34 #define FLAG_STARTED (1 << 3)
  35
  36 #define ONESHOT  0
  37 #define PERIODIC 1
  38
  39 #define RELATIVE 0
  40 #define ABSOLUTE 1
  41
  42 struct timer8_priv {
  43         struct platform_device *pdev;
  44         int mode;
  45         union {
  46                 struct clocksource cs;
  47                 struct clock_event_device ced;
  48         } clk;
  49         struct irqaction irqaction;
  50         unsigned long mapbase;
  51         raw_spinlock_t lock;
  52         unsigned long total_cycles;
  53         unsigned int cs_enabled;
  54         unsigned long flags;
  55         unsigned int rate;
  56         unsigned short tcora;
  57         unsigned short div;
  58 };
  59
  60 static const int div_rate[] = {8, 64, 8192};
  61
  62 static unsigned long timer8_get_counter(struct timer8_priv *p)
  63 {
  64         unsigned long v1, v2, v3;
  65         int o1, o2;
  66
  67         o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;
  68
  69         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
  70         do {
  71                 o2 = o1;
  72                 v1 = ctrl_inw(p->mapbase + _8TCNT);
  73                 v2 = ctrl_inw(p->mapbase + _8TCNT);
  74                 v3 = ctrl_inw(p->mapbase + _8TCNT);
  75                 o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;
  76         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
  77                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
  78
  79         v2 |= o1 << 10;
  80         return v2;
  81 }
  82
  83 static irqreturn_t timer8_interrupt(int irq, void *dev_id)
  84 {
  85         struct timer8_priv *p = dev_id;
  86
  87         switch (p->mode) {
  88         case H8300_TMR8_CLKSRC:
  89                 ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x20,
  90                           p->mapbase + _8TCSR);
  91                 p->total_cycles += 0x10000;
  92                 break;
  93         case H8300_TMR8_CLKEVTDEV:
  94                 ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x40,
  95                           p->mapbase + _8TCSR);
  96                 p->flags |= FLAG_IRQCONTEXT;
  97                 ctrl_outw(p->tcora, p->mapbase + TCORA);
  98                 if (!(p->flags & FLAG_SKIPEVENT)) {
  99                         if (p->clk.ced.mode == CLOCK_EVT_MODE_ONESHOT)
 100                                 ctrl_outw(0x0000, p->mapbase + _8TCR);
 101                         p->clk.ced.event_handler(&p->clk.ced);
 102                 }
 103                 p->flags &= ~(FLAG_SKIPEVENT | FLAG_IRQCONTEXT);
 104                 break;
 105         }
 106
 107         return IRQ_HANDLED;
 108 }
 109
 110 static inline struct timer8_priv *cs_to_priv(struct clocksource *cs)
 111 {
 112         return container_of(cs, struct timer8_priv, clk.cs);
 113 }
 114
 115 static cycle_t timer8_clocksource_read(struct clocksource *cs)
 116 {
 117         struct timer8_priv *p = cs_to_priv(cs);
 118         unsigned long flags, raw;
 119         unsigned long value;
 120
 121         raw_spin_lock_irqsave(&p->lock, flags);
 122         value = p->total_cycles;
 123         raw = timer8_get_counter(p);
 124         raw_spin_unlock_irqrestore(&p->lock, flags);
 125
 126         return value + raw;
 127 }
 128
 129 static int timer8_clocksource_enable(struct clocksource *cs)
 130 {
 131         struct timer8_priv *p = cs_to_priv(cs);
 132
 133         WARN_ON(p->cs_enabled);
 134
 135         p->total_cycles = 0;
 136         ctrl_outw(0, p->mapbase + _8TCNT);
 137         ctrl_outw(0x2400 | p->div, p->mapbase + _8TCR);
 138
 139         p->cs_enabled = true;
 140         return 0;
 141 }
 142
 143 static void timer8_clocksource_disable(struct clocksource *cs)
 144 {
 145         struct timer8_priv *p = cs_to_priv(cs);
 146
 147         WARN_ON(!p->cs_enabled);
 148
 149         ctrl_outb(0, p->mapbase + _8TCR);
 150         p->cs_enabled = false;
 151 }
 152
 153 static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
 154 {
 155         unsigned long flags;
 156         unsigned long now;
 157
 158         raw_spin_lock_irqsave(&p->lock, flags);
 159         if (delta >= 0x10000)
 160                 dev_warn(&p->pdev->dev, "delta out of range\n");
 161         now = timer8_get_counter(p);
 162         p->tcora = delta;
 163         ctrl_outb(ctrl_inb(p->mapbase + _8TCR) | 0x40, p->mapbase + _8TCR);
 164         if (delta > now)
 165                 ctrl_outw(delta, p->mapbase + TCORA);
 166         else
 167                 ctrl_outw(now + 1, p->mapbase + TCORA);
 168
 169         raw_spin_unlock_irqrestore(&p->lock, flags);
 170 }
 171
 172 static int timer8_enable(struct timer8_priv *p)
 173 {
 174         p->rate = get_cpu_clock() / div_rate[p->div];
 175         ctrl_outw(0xffff, p->mapbase + TCORA);
 176         ctrl_outw(0x0000, p->mapbase + _8TCNT);
 177         ctrl_outw(0x0c01, p->mapbase + _8TCR);
 178
 179         return 0;
 180 }
 181
 182 static int timer8_start(struct timer8_priv *p)
 183 {
 184         int ret = 0;
 185         unsigned long flags;
 186
 187         raw_spin_lock_irqsave(&p->lock, flags);
 188
 189         if (!(p->flags & FLAG_STARTED))
 190                 ret = timer8_enable(p);
 191
 192         if (ret)
 193                 goto out;
 194         p->flags |= FLAG_STARTED;
 195
 196  out:
 197         raw_spin_unlock_irqrestore(&p->lock, flags);
 198
 199         return ret;
 200 }
 201
 202 static void timer8_stop(struct timer8_priv *p)
 203 {
 204         unsigned long flags;
 205
 206         raw_spin_lock_irqsave(&p->lock, flags);
 207
 208         ctrl_outw(0x0000, p->mapbase + _8TCR);
 209
 210         raw_spin_unlock_irqrestore(&p->lock, flags);
 211 }
 212
 213 static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
 214 {
 215         return container_of(ced, struct timer8_priv, clk.ced);
 216 }
 217
 218 static void timer8_clock_event_start(struct timer8_priv *p, int periodic)
 219 {
 220         struct clock_event_device *ced = &p->clk.ced;
 221
 222         timer8_start(p);
 223
 224         ced->shift = 32;
 225         ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
 226         ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
 227         ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);
 228
 229         timer8_set_next(p, periodic?(p->rate + HZ/2) / HZ:0x10000);
 230 }
 231
 232 static void timer8_clock_event_mode(enum clock_event_mode mode,
 233                                     struct clock_event_device *ced)
 234 {
 235         struct timer8_priv *p = ced_to_priv(ced);
 236
 237         switch (mode) {
 238         case CLOCK_EVT_MODE_PERIODIC:
 239                 dev_info(&p->pdev->dev, "used for periodic clock events\n");
 240                 timer8_stop(p);
 241                 timer8_clock_event_start(p, PERIODIC);
 242                 break;
 243         case CLOCK_EVT_MODE_ONESHOT:
 244                 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
 245                 timer8_stop(p);
 246                 timer8_clock_event_start(p, ONESHOT);
 247                 break;
 248         case CLOCK_EVT_MODE_SHUTDOWN:
 249         case CLOCK_EVT_MODE_UNUSED:
 250                 timer8_stop(p);
 251                 break;
 252         default:
 253                 break;
 254         }
 255 }
 256
 257 static int timer8_clock_event_next(unsigned long delta,
 258                                    struct clock_event_device *ced)
 259 {
 260         struct timer8_priv *p = ced_to_priv(ced);
 261
 262         BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
 263         timer8_set_next(p, delta - 1);
 264
 265         return 0;
 266 }
 267
 268 #define CMI 0
 269 #define OVI 1
 270 static int __init timer8_setup(struct timer8_priv *p,
 271                                struct platform_device *pdev)
 272 {
 273         struct h8300_timer8_config *cfg = dev_get_platdata(&pdev->dev);
 274         struct resource *res;
 275         int irq[2];
 276         int ret;
 277
 278         memset(p, 0, sizeof(*p));
 279         p->pdev = pdev;
 280
 281         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
 282         if (!res) {
 283                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
 284                 return -ENXIO;
 285         }
 286
 287         irq[CMI] = platform_get_irq(p->pdev, CMI);
 288         irq[OVI] = platform_get_irq(p->pdev, OVI);
 289         if (irq[CMI] < 0 || irq[OVI] < 0) {
 290                 dev_err(&p->pdev->dev, "failed to get irq\n");
 291                 return -ENXIO;
 292         }
 293
 294         p->mapbase = res->start;
 295
 296         p->irqaction.name = dev_name(&p->pdev->dev);
 297         p->irqaction.handler = timer8_interrupt;
 298         p->irqaction.dev_id = p;
 299         p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER;
 300
 301         p->mode = cfg->mode;
 302         p->div = cfg->div;
 303         switch(p->mode) {
 304         case H8300_TMR8_CLKSRC:
 305                 p->clk.cs.name = pdev->name;
 306                 p->clk.cs.rating = cfg->rating;
 307                 p->clk.cs.read = timer8_clocksource_read;
 308                 p->clk.cs.enable = timer8_clocksource_enable;
 309                 p->clk.cs.disable = timer8_clocksource_disable;
 310                 p->clk.cs.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
 311                 p->clk.cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 312
 313                 ret = setup_irq(irq[OVI], &p->irqaction);
 314                 if (ret < 0) {
 315                         dev_err(&p->pdev->dev,
 316                                 "failed to request irq %d\n", irq[OVI]);
 317                         return ret;
 318                 }
 319                 clocksource_register_hz(&p->clk.cs,
 320                                         get_cpu_clock() / div_rate[p->div]);
 321                 break;
 322         case H8300_TMR8_CLKEVTDEV:
 323                 p->clk.ced.name = pdev->name;
 324                 p->clk.ced.features = CLOCK_EVT_FEAT_PERIODIC |
 325                                         CLOCK_EVT_FEAT_ONESHOT;
 326                 p->clk.ced.rating = cfg->rating;
 327                 p->clk.ced.cpumask = cpumask_of(0);
 328                 p->clk.ced.set_next_event = timer8_clock_event_next;
 329                 p->clk.ced.set_mode = timer8_clock_event_mode;
 330
 331                 ret = setup_irq(irq[CMI], &p->irqaction);
 332                 if (ret < 0) {
 333                         dev_err(&p->pdev->dev,
 334                                 "failed to request irq %d\n", irq[CMI]);
 335                         return ret;
 336                 }
 337                 clockevents_register_device(&p->clk.ced);
 338                 break;
 339         }
 340         platform_set_drvdata(pdev, p);
 341
 342         return 0;
 343 }
 344
 345 static int timer8_probe(struct platform_device *pdev)
 346 {
 347         struct timer8_priv *p = platform_get_drvdata(pdev);
 348
 349         if (p) {
 350                 dev_info(&pdev->dev, "kept as earlytimer\n");
 351                 return 0;
 352         }
 353
 354         p = kmalloc(sizeof(*p), GFP_KERNEL);
 355         if (p == NULL) {
 356                 dev_err(&pdev->dev, "failed to allocate driver data"
 357                         " out of memory\n");
 358                 return -ENOMEM;
 359         }
 360
 361         return timer8_setup(p, pdev);
 362 }
 363
 364 static int timer8_remove(struct platform_device *pdev)
 365 {
 366         return -EBUSY;
 367 }
 368
 369 static struct platform_driver timer8_driver = {
 370         .probe          = timer8_probe,
 371         .remove         = timer8_remove,
 372         .driver         = {
 373                 .name   = "h8300-8timer",
 374         }
 375 };
 376
 377 static int __init timer8_init(void)
 378 {
 379         return platform_driver_register(&timer8_driver);
 380 }
 381
 382 static void __exit timer8_exit(void)
 383 {
 384         platform_driver_unregister(&timer8_driver);
 385 }
 386
 387 early_platform_init("earlytimer", &timer8_driver);
 388 subsys_initcall(timer8_init);
 389 module_exit(timer8_exit);
 390 MODULE_AUTHOR("Yoshinori Sato");
 391 MODULE_DESCRIPTION("H8/300 8bit Timer Driver");
 392 MODULE_LICENSE("GPL v2");