arch/mips/kernel/smp-cps.c

   1 /*
   2  * Copyright (C) 2013 Imagination Technologies
   3  * Author: Paul Burton <paul.burton@imgtec.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/io.h>
  12 #include <linux/sched.h>
  13 #include <linux/slab.h>
  14 #include <linux/smp.h>
  15 #include <linux/types.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/gic.h>
  19 #include <asm/mips-cm.h>
  20 #include <asm/mips-cpc.h>
  21 #include <asm/mips_mt.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/pm-cps.h>
  24 #include <asm/smp-cps.h>
  25 #include <asm/time.h>
  26 #include <asm/uasm.h>
  27
  28 static DECLARE_BITMAP(core_power, NR_CPUS);
  29
  30 struct core_boot_config *mips_cps_core_bootcfg;
  31
  32 static unsigned core_vpe_count(unsigned core)
  33 {
  34         unsigned cfg;
  35
  36         if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
  37                 return 1;
  38
  39         write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
  40         cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
  41         return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
  42 }
  43
  44 static void __init cps_smp_setup(void)
  45 {
  46         unsigned int ncores, nvpes, core_vpes;
  47         int c, v;
  48
  49         /* Detect & record VPE topology */
  50         ncores = mips_cm_numcores();
  51         pr_info("VPE topology ");
  52         for (c = nvpes = 0; c < ncores; c++) {
  53                 core_vpes = core_vpe_count(c);
  54                 pr_cont("%c%u", c ? ',' : '{', core_vpes);
  55
  56                 /* Use the number of VPEs in core 0 for smp_num_siblings */
  57                 if (!c)
  58                         smp_num_siblings = core_vpes;
  59
  60                 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
  61                         cpu_data[nvpes + v].core = c;
  62 #ifdef CONFIG_MIPS_MT_SMP
  63                         cpu_data[nvpes + v].vpe_id = v;
  64 #endif
  65                 }
  66
  67                 nvpes += core_vpes;
  68         }
  69         pr_cont("} total %u\n", nvpes);
  70
  71         /* Indicate present CPUs (CPU being synonymous with VPE) */
  72         for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
  73                 set_cpu_possible(v, true);
  74                 set_cpu_present(v, true);
  75                 __cpu_number_map[v] = v;
  76                 __cpu_logical_map[v] = v;
  77         }
  78
  79         /* Core 0 is powered up (we're running on it) */
  80         bitmap_set(core_power, 0, 1);
  81
  82         /* Initialise core 0 */
  83         mips_cps_core_init();
  84
  85         /* Make core 0 coherent with everything */
  86         write_gcr_cl_coherence(0xff);
  87 }
  88
  89 static void __init cps_prepare_cpus(unsigned int max_cpus)
  90 {
  91         unsigned ncores, core_vpes, c;
  92         u32 *entry_code;
  93
  94         mips_mt_set_cpuoptions();
  95
  96         /* Patch the start of mips_cps_core_entry to provide the CM base */
  97         entry_code = (u32 *)&mips_cps_core_entry;
  98         UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
  99         dma_cache_wback_inv((unsigned long)&mips_cps_core_entry,
 100                             (void *)entry_code - (void *)&mips_cps_core_entry);
 101
 102         /* Allocate core boot configuration structs */
 103         ncores = mips_cm_numcores();
 104         mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
 105                                         GFP_KERNEL);
 106         if (!mips_cps_core_bootcfg) {
 107                 pr_err("Failed to allocate boot config for %u cores\n", ncores);
 108                 goto err_out;
 109         }
 110
 111         /* Allocate VPE boot configuration structs */
 112         for (c = 0; c < ncores; c++) {
 113                 core_vpes = core_vpe_count(c);
 114                 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
 115                                 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
 116                                 GFP_KERNEL);
 117                 if (!mips_cps_core_bootcfg[c].vpe_config) {
 118                         pr_err("Failed to allocate %u VPE boot configs\n",
 119                                core_vpes);
 120                         goto err_out;
 121                 }
 122         }
 123
 124         /* Mark this CPU as booted */
 125         atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
 126                    1 << cpu_vpe_id(&current_cpu_data));
 127
 128         return;
 129 err_out:
 130         /* Clean up allocations */
 131         if (mips_cps_core_bootcfg) {
 132                 for (c = 0; c < ncores; c++)
 133                         kfree(mips_cps_core_bootcfg[c].vpe_config);
 134                 kfree(mips_cps_core_bootcfg);
 135                 mips_cps_core_bootcfg = NULL;
 136         }
 137
 138         /* Effectively disable SMP by declaring CPUs not present */
 139         for_each_possible_cpu(c) {
 140                 if (c == 0)
 141                         continue;
 142                 set_cpu_present(c, false);
 143         }
 144 }
 145
 146 static void boot_core(unsigned core)
 147 {
 148         u32 access;
 149
 150         /* Select the appropriate core */
 151         write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
 152
 153         /* Set its reset vector */
 154         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
 155
 156         /* Ensure its coherency is disabled */
 157         write_gcr_co_coherence(0);
 158
 159         /* Ensure the core can access the GCRs */
 160         access = read_gcr_access();
 161         access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
 162         write_gcr_access(access);
 163
 164         if (mips_cpc_present()) {
 165                 /* Reset the core */
 166                 mips_cpc_lock_other(core);
 167                 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
 168                 mips_cpc_unlock_other();
 169         } else {
 170                 /* Take the core out of reset */
 171                 write_gcr_co_reset_release(0);
 172         }
 173
 174         /* The core is now powered up */
 175         bitmap_set(core_power, core, 1);
 176 }
 177
 178 static void remote_vpe_boot(void *dummy)
 179 {
 180         mips_cps_boot_vpes();
 181 }
 182
 183 static void cps_boot_secondary(int cpu, struct task_struct *idle)
 184 {
 185         unsigned core = cpu_data[cpu].core;
 186         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 187         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 188         struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
 189         unsigned int remote;
 190         int err;
 191
 192         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
 193         vpe_cfg->sp = __KSTK_TOS(idle);
 194         vpe_cfg->gp = (unsigned long)task_thread_info(idle);
 195
 196         atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
 197
 198         preempt_disable();
 199
 200         if (!test_bit(core, core_power)) {
 201                 /* Boot a VPE on a powered down core */
 202                 boot_core(core);
 203                 goto out;
 204         }
 205
 206         if (core != current_cpu_data.core) {
 207                 /* Boot a VPE on another powered up core */
 208                 for (remote = 0; remote < NR_CPUS; remote++) {
 209                         if (cpu_data[remote].core != core)
 210                                 continue;
 211                         if (cpu_online(remote))
 212                                 break;
 213                 }
 214                 BUG_ON(remote >= NR_CPUS);
 215
 216                 err = smp_call_function_single(remote, remote_vpe_boot,
 217                                                NULL, 1);
 218                 if (err)
 219                         panic("Failed to call remote CPU\n");
 220                 goto out;
 221         }
 222
 223         BUG_ON(!cpu_has_mipsmt);
 224
 225         /* Boot a VPE on this core */
 226         mips_cps_boot_vpes();
 227 out:
 228         preempt_enable();
 229 }
 230
 231 static void cps_init_secondary(void)
 232 {
 233         /* Disable MT - we only want to run 1 TC per VPE */
 234         if (cpu_has_mipsmt)
 235                 dmt();
 236
 237         change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
 238                                  STATUSF_IP6 | STATUSF_IP7);
 239 }
 240
 241 static void cps_smp_finish(void)
 242 {
 243         write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
 244
 245 #ifdef CONFIG_MIPS_MT_FPAFF
 246         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 247         if (cpu_has_fpu)
 248                 cpu_set(smp_processor_id(), mt_fpu_cpumask);
 249 #endif /* CONFIG_MIPS_MT_FPAFF */
 250
 251         local_irq_enable();
 252 }
 253
 254 static void cps_cpus_done(void)
 255 {
 256 }
 257
 258 #ifdef CONFIG_HOTPLUG_CPU
 259
 260 static int cps_cpu_disable(void)
 261 {
 262         unsigned cpu = smp_processor_id();
 263         struct core_boot_config *core_cfg;
 264
 265         if (!cpu)
 266                 return -EBUSY;
 267
 268         if (!cps_pm_support_state(CPS_PM_POWER_GATED))
 269                 return -EINVAL;
 270
 271         core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
 272         atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
 273         smp_mb__after_atomic_dec();
 274         set_cpu_online(cpu, false);
 275         cpu_clear(cpu, cpu_callin_map);
 276
 277         return 0;
 278 }
 279
 280 static DECLARE_COMPLETION(cpu_death_chosen);
 281 static unsigned cpu_death_sibling;
 282 static enum {
 283         CPU_DEATH_HALT,
 284         CPU_DEATH_POWER,
 285 } cpu_death;
 286
 287 void play_dead(void)
 288 {
 289         unsigned cpu, core;
 290
 291         local_irq_disable();
 292         idle_task_exit();
 293         cpu = smp_processor_id();
 294         cpu_death = CPU_DEATH_POWER;
 295
 296         if (cpu_has_mipsmt) {
 297                 core = cpu_data[cpu].core;
 298
 299                 /* Look for another online VPE within the core */
 300                 for_each_online_cpu(cpu_death_sibling) {
 301                         if (cpu_data[cpu_death_sibling].core != core)
 302                                 continue;
 303
 304                         /*
 305                          * There is an online VPE within the core. Just halt
 306                          * this TC and leave the core alone.
 307                          */
 308                         cpu_death = CPU_DEATH_HALT;
 309                         break;
 310                 }
 311         }
 312
 313         /* This CPU has chosen its way out */
 314         complete(&cpu_death_chosen);
 315
 316         if (cpu_death == CPU_DEATH_HALT) {
 317                 /* Halt this TC */
 318                 write_c0_tchalt(TCHALT_H);
 319                 instruction_hazard();
 320         } else {
 321                 /* Power down the core */
 322                 cps_pm_enter_state(CPS_PM_POWER_GATED);
 323         }
 324
 325         /* This should never be reached */
 326         panic("Failed to offline CPU %u", cpu);
 327 }
 328
 329 static void wait_for_sibling_halt(void *ptr_cpu)
 330 {
 331         unsigned cpu = (unsigned)ptr_cpu;
 332         unsigned vpe_id = cpu_data[cpu].vpe_id;
 333         unsigned halted;
 334         unsigned long flags;
 335
 336         do {
 337                 local_irq_save(flags);
 338                 settc(vpe_id);
 339                 halted = read_tc_c0_tchalt();
 340                 local_irq_restore(flags);
 341         } while (!(halted & TCHALT_H));
 342 }
 343
 344 static void cps_cpu_die(unsigned int cpu)
 345 {
 346         unsigned core = cpu_data[cpu].core;
 347         unsigned stat;
 348         int err;
 349
 350         /* Wait for the cpu to choose its way out */
 351         if (!wait_for_completion_timeout(&cpu_death_chosen,
 352                                          msecs_to_jiffies(5000))) {
 353                 pr_err("CPU%u: didn't offline\n", cpu);
 354                 return;
 355         }
 356
 357         /*
 358          * Now wait for the CPU to actually offline. Without doing this that
 359          * offlining may race with one or more of:
 360          *
 361          *   - Onlining the CPU again.
 362          *   - Powering down the core if another VPE within it is offlined.
 363          *   - A sibling VPE entering a non-coherent state.
 364          *
 365          * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
 366          * with which we could race, so do nothing.
 367          */
 368         if (cpu_death == CPU_DEATH_POWER) {
 369                 /*
 370                  * Wait for the core to enter a powered down or clock gated
 371                  * state, the latter happening when a JTAG probe is connected
 372                  * in which case the CPC will refuse to power down the core.
 373                  */
 374                 do {
 375                         mips_cpc_lock_other(core);
 376                         stat = read_cpc_co_stat_conf();
 377                         stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
 378                         mips_cpc_unlock_other();
 379                 } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
 380                          stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
 381                          stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
 382
 383                 /* Indicate the core is powered off */
 384                 bitmap_clear(core_power, core, 1);
 385         } else if (cpu_has_mipsmt) {
 386                 /*
 387                  * Have a CPU with access to the offlined CPUs registers wait
 388                  * for its TC to halt.
 389                  */
 390                 err = smp_call_function_single(cpu_death_sibling,
 391                                                wait_for_sibling_halt,
 392                                                (void *)cpu, 1);
 393                 if (err)
 394                         panic("Failed to call remote sibling CPU\n");
 395         }
 396 }
 397
 398 #endif /* CONFIG_HOTPLUG_CPU */
 399
 400 static struct plat_smp_ops cps_smp_ops = {
 401         .smp_setup              = cps_smp_setup,
 402         .prepare_cpus           = cps_prepare_cpus,
 403         .boot_secondary         = cps_boot_secondary,
 404         .init_secondary         = cps_init_secondary,
 405         .smp_finish             = cps_smp_finish,
 406         .send_ipi_single        = gic_send_ipi_single,
 407         .send_ipi_mask          = gic_send_ipi_mask,
 408         .cpus_done              = cps_cpus_done,
 409 #ifdef CONFIG_HOTPLUG_CPU
 410         .cpu_disable            = cps_cpu_disable,
 411         .cpu_die                = cps_cpu_die,
 412 #endif
 413 };
 414
 415 bool mips_cps_smp_in_use(void)
 416 {
 417         extern struct plat_smp_ops *mp_ops;
 418         return mp_ops == &cps_smp_ops;
 419 }
 420
 421 int register_cps_smp_ops(void)
 422 {
 423         if (!mips_cm_present()) {
 424                 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
 425                 return -ENODEV;
 426         }
 427
 428         /* check we have a GIC - we need one for IPIs */
 429         if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
 430                 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
 431                 return -ENODEV;
 432         }
 433
 434         register_smp_ops(&cps_smp_ops);
 435         return 0;
 436 }