drivers/gpu/drm/radeon/radeon_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/radeon_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "radeon_reg.h"
  46 #include "radeon.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  51 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
  52
  53 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  54 {
  55         struct radeon_mman *mman;
  56         struct radeon_device *rdev;
  57
  58         mman = container_of(bdev, struct radeon_mman, bdev);
  59         rdev = container_of(mman, struct radeon_device, mman);
  60         return rdev;
  61 }
  62
  63
  64 /*
  65  * Global memory.
  66  */
  67 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  68 {
  69         return ttm_mem_global_init(ref->object);
  70 }
  71
  72 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  73 {
  74         ttm_mem_global_release(ref->object);
  75 }
  76
  77 static int radeon_ttm_global_init(struct radeon_device *rdev)
  78 {
  79         struct drm_global_reference *global_ref;
  80         int r;
  81
  82         rdev->mman.mem_global_referenced = false;
  83         global_ref = &rdev->mman.mem_global_ref;
  84         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  85         global_ref->size = sizeof(struct ttm_mem_global);
  86         global_ref->init = &radeon_ttm_mem_global_init;
  87         global_ref->release = &radeon_ttm_mem_global_release;
  88         r = drm_global_item_ref(global_ref);
  89         if (r != 0) {
  90                 DRM_ERROR("Failed setting up TTM memory accounting "
  91                           "subsystem.\n");
  92                 return r;
  93         }
  94
  95         rdev->mman.bo_global_ref.mem_glob =
  96                 rdev->mman.mem_global_ref.object;
  97         global_ref = &rdev->mman.bo_global_ref.ref;
  98         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  99         global_ref->size = sizeof(struct ttm_bo_global);
 100         global_ref->init = &ttm_bo_global_init;
 101         global_ref->release = &ttm_bo_global_release;
 102         r = drm_global_item_ref(global_ref);
 103         if (r != 0) {
 104                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 105                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 106                 return r;
 107         }
 108
 109         rdev->mman.mem_global_referenced = true;
 110         return 0;
 111 }
 112
 113 static void radeon_ttm_global_fini(struct radeon_device *rdev)
 114 {
 115         if (rdev->mman.mem_global_referenced) {
 116                 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
 117                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 118                 rdev->mman.mem_global_referenced = false;
 119         }
 120 }
 121
 122 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 123 {
 124         return 0;
 125 }
 126
 127 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 128                                 struct ttm_mem_type_manager *man)
 129 {
 130         struct radeon_device *rdev;
 131
 132         rdev = radeon_get_rdev(bdev);
 133
 134         switch (type) {
 135         case TTM_PL_SYSTEM:
 136                 /* System memory */
 137                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 138                 man->available_caching = TTM_PL_MASK_CACHING;
 139                 man->default_caching = TTM_PL_FLAG_CACHED;
 140                 break;
 141         case TTM_PL_TT:
 142                 man->func = &ttm_bo_manager_func;
 143                 man->gpu_offset = rdev->mc.gtt_start;
 144                 man->available_caching = TTM_PL_MASK_CACHING;
 145                 man->default_caching = TTM_PL_FLAG_CACHED;
 146                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 147 #if IS_ENABLED(CONFIG_AGP)
 148                 if (rdev->flags & RADEON_IS_AGP) {
 149                         if (!rdev->ddev->agp) {
 150                                 DRM_ERROR("AGP is not enabled for memory type %u\n",
 151                                           (unsigned)type);
 152                                 return -EINVAL;
 153                         }
 154                         if (!rdev->ddev->agp->cant_use_aperture)
 155                                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 156                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 157                                                  TTM_PL_FLAG_WC;
 158                         man->default_caching = TTM_PL_FLAG_WC;
 159                 }
 160 #endif
 161                 break;
 162         case TTM_PL_VRAM:
 163                 /* "On-card" video ram */
 164                 man->func = &ttm_bo_manager_func;
 165                 man->gpu_offset = rdev->mc.vram_start;
 166                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 167                              TTM_MEMTYPE_FLAG_MAPPABLE;
 168                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 169                 man->default_caching = TTM_PL_FLAG_WC;
 170                 break;
 171         default:
 172                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 173                 return -EINVAL;
 174         }
 175         return 0;
 176 }
 177
 178 static void radeon_evict_flags(struct ttm_buffer_object *bo,
 179                                 struct ttm_placement *placement)
 180 {
 181         static struct ttm_place placements = {
 182                 .fpfn = 0,
 183                 .lpfn = 0,
 184                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 185         };
 186
 187         struct radeon_bo *rbo;
 188
 189         if (!radeon_ttm_bo_is_radeon_bo(bo)) {
 190                 placement->placement = &placements;
 191                 placement->busy_placement = &placements;
 192                 placement->num_placement = 1;
 193                 placement->num_busy_placement = 1;
 194                 return;
 195         }
 196         rbo = container_of(bo, struct radeon_bo, tbo);
 197         switch (bo->mem.mem_type) {
 198         case TTM_PL_VRAM:
 199                 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
 200                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 201                 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
 202                          bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
 203                         unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 204                         int i;
 205
 206                         /* Try evicting to the CPU inaccessible part of VRAM
 207                          * first, but only set GTT as busy placement, so this
 208                          * BO will be evicted to GTT rather than causing other
 209                          * BOs to be evicted from VRAM
 210                          */
 211                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
 212                                                          RADEON_GEM_DOMAIN_GTT);
 213                         rbo->placement.num_busy_placement = 0;
 214                         for (i = 0; i < rbo->placement.num_placement; i++) {
 215                                 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
 216                                         if (rbo->placements[0].fpfn < fpfn)
 217                                                 rbo->placements[0].fpfn = fpfn;
 218                                 } else {
 219                                         rbo->placement.busy_placement =
 220                                                 &rbo->placements[i];
 221                                         rbo->placement.num_busy_placement = 1;
 222                                 }
 223                         }
 224                 } else
 225                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 226                 break;
 227         case TTM_PL_TT:
 228         default:
 229                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 230         }
 231         *placement = rbo->placement;
 232 }
 233
 234 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 235 {
 236         struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
 237
 238         if (radeon_ttm_tt_has_userptr(bo->ttm))
 239                 return -EPERM;
 240         return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 241 }
 242
 243 static void radeon_move_null(struct ttm_buffer_object *bo,
 244                              struct ttm_mem_reg *new_mem)
 245 {
 246         struct ttm_mem_reg *old_mem = &bo->mem;
 247
 248         BUG_ON(old_mem->mm_node != NULL);
 249         *old_mem = *new_mem;
 250         new_mem->mm_node = NULL;
 251 }
 252
 253 static int radeon_move_blit(struct ttm_buffer_object *bo,
 254                         bool evict, bool no_wait_gpu,
 255                         struct ttm_mem_reg *new_mem,
 256                         struct ttm_mem_reg *old_mem)
 257 {
 258         struct radeon_device *rdev;
 259         uint64_t old_start, new_start;
 260         struct radeon_fence *fence;
 261         unsigned num_pages;
 262         int r, ridx;
 263
 264         rdev = radeon_get_rdev(bo->bdev);
 265         ridx = radeon_copy_ring_index(rdev);
 266         old_start = old_mem->start << PAGE_SHIFT;
 267         new_start = new_mem->start << PAGE_SHIFT;
 268
 269         switch (old_mem->mem_type) {
 270         case TTM_PL_VRAM:
 271                 old_start += rdev->mc.vram_start;
 272                 break;
 273         case TTM_PL_TT:
 274                 old_start += rdev->mc.gtt_start;
 275                 break;
 276         default:
 277                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 278                 return -EINVAL;
 279         }
 280         switch (new_mem->mem_type) {
 281         case TTM_PL_VRAM:
 282                 new_start += rdev->mc.vram_start;
 283                 break;
 284         case TTM_PL_TT:
 285                 new_start += rdev->mc.gtt_start;
 286                 break;
 287         default:
 288                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 289                 return -EINVAL;
 290         }
 291         if (!rdev->ring[ridx].ready) {
 292                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 293                 return -EINVAL;
 294         }
 295
 296         BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
 297
 298         num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
 299         fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
 300         if (IS_ERR(fence))
 301                 return PTR_ERR(fence);
 302
 303         r = ttm_bo_move_accel_cleanup(bo, &fence->base,
 304                                       evict, no_wait_gpu, new_mem);
 305         radeon_fence_unref(&fence);
 306         return r;
 307 }
 308
 309 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
 310                                 bool evict, bool interruptible,
 311                                 bool no_wait_gpu,
 312                                 struct ttm_mem_reg *new_mem)
 313 {
 314         struct radeon_device *rdev;
 315         struct ttm_mem_reg *old_mem = &bo->mem;
 316         struct ttm_mem_reg tmp_mem;
 317         struct ttm_place placements;
 318         struct ttm_placement placement;
 319         int r;
 320
 321         rdev = radeon_get_rdev(bo->bdev);
 322         tmp_mem = *new_mem;
 323         tmp_mem.mm_node = NULL;
 324         placement.num_placement = 1;
 325         placement.placement = &placements;
 326         placement.num_busy_placement = 1;
 327         placement.busy_placement = &placements;
 328         placements.fpfn = 0;
 329         placements.lpfn = 0;
 330         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 331         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 332                              interruptible, no_wait_gpu);
 333         if (unlikely(r)) {
 334                 return r;
 335         }
 336
 337         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 338         if (unlikely(r)) {
 339                 goto out_cleanup;
 340         }
 341
 342         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 343         if (unlikely(r)) {
 344                 goto out_cleanup;
 345         }
 346         r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 347         if (unlikely(r)) {
 348                 goto out_cleanup;
 349         }
 350         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
 351 out_cleanup:
 352         ttm_bo_mem_put(bo, &tmp_mem);
 353         return r;
 354 }
 355
 356 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
 357                                 bool evict, bool interruptible,
 358                                 bool no_wait_gpu,
 359                                 struct ttm_mem_reg *new_mem)
 360 {
 361         struct radeon_device *rdev;
 362         struct ttm_mem_reg *old_mem = &bo->mem;
 363         struct ttm_mem_reg tmp_mem;
 364         struct ttm_placement placement;
 365         struct ttm_place placements;
 366         int r;
 367
 368         rdev = radeon_get_rdev(bo->bdev);
 369         tmp_mem = *new_mem;
 370         tmp_mem.mm_node = NULL;
 371         placement.num_placement = 1;
 372         placement.placement = &placements;
 373         placement.num_busy_placement = 1;
 374         placement.busy_placement = &placements;
 375         placements.fpfn = 0;
 376         placements.lpfn = 0;
 377         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 378         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 379                              interruptible, no_wait_gpu);
 380         if (unlikely(r)) {
 381                 return r;
 382         }
 383         r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
 384         if (unlikely(r)) {
 385                 goto out_cleanup;
 386         }
 387         r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 388         if (unlikely(r)) {
 389                 goto out_cleanup;
 390         }
 391 out_cleanup:
 392         ttm_bo_mem_put(bo, &tmp_mem);
 393         return r;
 394 }
 395
 396 static int radeon_bo_move(struct ttm_buffer_object *bo,
 397                         bool evict, bool interruptible,
 398                         bool no_wait_gpu,
 399                         struct ttm_mem_reg *new_mem)
 400 {
 401         struct radeon_device *rdev;
 402         struct radeon_bo *rbo;
 403         struct ttm_mem_reg *old_mem = &bo->mem;
 404         int r;
 405
 406         /* Can't move a pinned BO */
 407         rbo = container_of(bo, struct radeon_bo, tbo);
 408         if (WARN_ON_ONCE(rbo->pin_count > 0))
 409                 return -EINVAL;
 410
 411         rdev = radeon_get_rdev(bo->bdev);
 412         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 413                 radeon_move_null(bo, new_mem);
 414                 return 0;
 415         }
 416         if ((old_mem->mem_type == TTM_PL_TT &&
 417              new_mem->mem_type == TTM_PL_SYSTEM) ||
 418             (old_mem->mem_type == TTM_PL_SYSTEM &&
 419              new_mem->mem_type == TTM_PL_TT)) {
 420                 /* bind is enough */
 421                 radeon_move_null(bo, new_mem);
 422                 return 0;
 423         }
 424         if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
 425             rdev->asic->copy.copy == NULL) {
 426                 /* use memcpy */
 427                 goto memcpy;
 428         }
 429
 430         if (old_mem->mem_type == TTM_PL_VRAM &&
 431             new_mem->mem_type == TTM_PL_SYSTEM) {
 432                 r = radeon_move_vram_ram(bo, evict, interruptible,
 433                                         no_wait_gpu, new_mem);
 434         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 435                    new_mem->mem_type == TTM_PL_VRAM) {
 436                 r = radeon_move_ram_vram(bo, evict, interruptible,
 437                                             no_wait_gpu, new_mem);
 438         } else {
 439                 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 440         }
 441
 442         if (r) {
 443 memcpy:
 444                 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
 445                 if (r) {
 446                         return r;
 447                 }
 448         }
 449
 450         /* update statistics */
 451         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
 452         return 0;
 453 }
 454
 455 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 456 {
 457         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 458         struct radeon_device *rdev = radeon_get_rdev(bdev);
 459
 460         mem->bus.addr = NULL;
 461         mem->bus.offset = 0;
 462         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 463         mem->bus.base = 0;
 464         mem->bus.is_iomem = false;
 465         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 466                 return -EINVAL;
 467         switch (mem->mem_type) {
 468         case TTM_PL_SYSTEM:
 469                 /* system memory */
 470                 return 0;
 471         case TTM_PL_TT:
 472 #if IS_ENABLED(CONFIG_AGP)
 473                 if (rdev->flags & RADEON_IS_AGP) {
 474                         /* RADEON_IS_AGP is set only if AGP is active */
 475                         mem->bus.offset = mem->start << PAGE_SHIFT;
 476                         mem->bus.base = rdev->mc.agp_base;
 477                         mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
 478                 }
 479 #endif
 480                 break;
 481         case TTM_PL_VRAM:
 482                 mem->bus.offset = mem->start << PAGE_SHIFT;
 483                 /* check if it's visible */
 484                 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
 485                         return -EINVAL;
 486                 mem->bus.base = rdev->mc.aper_base;
 487                 mem->bus.is_iomem = true;
 488 #ifdef __alpha__
 489                 /*
 490                  * Alpha: use bus.addr to hold the ioremap() return,
 491                  * so we can modify bus.base below.
 492                  */
 493                 if (mem->placement & TTM_PL_FLAG_WC)
 494                         mem->bus.addr =
 495                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 496                                            mem->bus.size);
 497                 else
 498                         mem->bus.addr =
 499                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 500                                                 mem->bus.size);
 501
 502                 /*
 503                  * Alpha: Use just the bus offset plus
 504                  * the hose/domain memory base for bus.base.
 505                  * It then can be used to build PTEs for VRAM
 506                  * access, as done in ttm_bo_vm_fault().
 507                  */
 508                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 509                         rdev->ddev->hose->dense_mem_base;
 510 #endif
 511                 break;
 512         default:
 513                 return -EINVAL;
 514         }
 515         return 0;
 516 }
 517
 518 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 519 {
 520 }
 521
 522 /*
 523  * TTM backend functions.
 524  */
 525 struct radeon_ttm_tt {
 526         struct ttm_dma_tt               ttm;
 527         struct radeon_device            *rdev;
 528         u64                             offset;
 529
 530         uint64_t                        userptr;
 531         struct mm_struct                *usermm;
 532         uint32_t                        userflags;
 533 };
 534
 535 /* prepare the sg table with the user pages */
 536 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 537 {
 538         struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 539         struct radeon_ttm_tt *gtt = (void *)ttm;
 540         unsigned pinned = 0, nents;
 541         int r;
 542
 543         int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 544         enum dma_data_direction direction = write ?
 545                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 546
 547         if (current->mm != gtt->usermm)
 548                 return -EPERM;
 549
 550         if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
 551                 /* check that we only pin down anonymous memory
 552                    to prevent problems with writeback */
 553                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 554                 struct vm_area_struct *vma;
 555                 vma = find_vma(gtt->usermm, gtt->userptr);
 556                 if (!vma || vma->vm_file || vma->vm_end < end)
 557                         return -EPERM;
 558         }
 559
 560         do {
 561                 unsigned num_pages = ttm->num_pages - pinned;
 562                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 563                 struct page **pages = ttm->pages + pinned;
 564
 565                 r = get_user_pages(userptr, num_pages, write, 0, pages, NULL);
 566                 if (r < 0)
 567                         goto release_pages;
 568
 569                 pinned += r;
 570
 571         } while (pinned < ttm->num_pages);
 572
 573         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 574                                       ttm->num_pages << PAGE_SHIFT,
 575                                       GFP_KERNEL);
 576         if (r)
 577                 goto release_sg;
 578
 579         r = -ENOMEM;
 580         nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 581         if (nents != ttm->sg->nents)
 582                 goto release_sg;
 583
 584         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 585                                          gtt->ttm.dma_address, ttm->num_pages);
 586
 587         return 0;
 588
 589 release_sg:
 590         kfree(ttm->sg);
 591
 592 release_pages:
 593         release_pages(ttm->pages, pinned, 0);
 594         return r;
 595 }
 596
 597 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 598 {
 599         struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 600         struct radeon_ttm_tt *gtt = (void *)ttm;
 601         struct sg_page_iter sg_iter;
 602
 603         int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 604         enum dma_data_direction direction = write ?
 605                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 606
 607         /* double check that we don't free the table twice */
 608         if (!ttm->sg->sgl)
 609                 return;
 610
 611         /* free the sg table and pages again */
 612         dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 613
 614         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 615                 struct page *page = sg_page_iter_page(&sg_iter);
 616                 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
 617                         set_page_dirty(page);
 618
 619                 mark_page_accessed(page);
 620                 put_page(page);
 621         }
 622
 623         sg_free_table(ttm->sg);
 624 }
 625
 626 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
 627                                    struct ttm_mem_reg *bo_mem)
 628 {
 629         struct radeon_ttm_tt *gtt = (void*)ttm;
 630         uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
 631                 RADEON_GART_PAGE_WRITE;
 632         int r;
 633
 634         if (gtt->userptr) {
 635                 radeon_ttm_tt_pin_userptr(ttm);
 636                 flags &= ~RADEON_GART_PAGE_WRITE;
 637         }
 638
 639         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 640         if (!ttm->num_pages) {
 641                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 642                      ttm->num_pages, bo_mem, ttm);
 643         }
 644         if (ttm->caching_state == tt_cached)
 645                 flags |= RADEON_GART_PAGE_SNOOP;
 646         r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
 647                              ttm->pages, gtt->ttm.dma_address, flags);
 648         if (r) {
 649                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 650                           ttm->num_pages, (unsigned)gtt->offset);
 651                 return r;
 652         }
 653         return 0;
 654 }
 655
 656 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
 657 {
 658         struct radeon_ttm_tt *gtt = (void *)ttm;
 659
 660         radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
 661
 662         if (gtt->userptr)
 663                 radeon_ttm_tt_unpin_userptr(ttm);
 664
 665         return 0;
 666 }
 667
 668 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
 669 {
 670         struct radeon_ttm_tt *gtt = (void *)ttm;
 671
 672         ttm_dma_tt_fini(&gtt->ttm);
 673         kfree(gtt);
 674 }
 675
 676 static struct ttm_backend_func radeon_backend_func = {
 677         .bind = &radeon_ttm_backend_bind,
 678         .unbind = &radeon_ttm_backend_unbind,
 679         .destroy = &radeon_ttm_backend_destroy,
 680 };
 681
 682 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
 683                                     unsigned long size, uint32_t page_flags,
 684                                     struct page *dummy_read_page)
 685 {
 686         struct radeon_device *rdev;
 687         struct radeon_ttm_tt *gtt;
 688
 689         rdev = radeon_get_rdev(bdev);
 690 #if IS_ENABLED(CONFIG_AGP)
 691         if (rdev->flags & RADEON_IS_AGP) {
 692                 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
 693                                          size, page_flags, dummy_read_page);
 694         }
 695 #endif
 696
 697         gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
 698         if (gtt == NULL) {
 699                 return NULL;
 700         }
 701         gtt->ttm.ttm.func = &radeon_backend_func;
 702         gtt->rdev = rdev;
 703         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 704                 kfree(gtt);
 705                 return NULL;
 706         }
 707         return &gtt->ttm.ttm;
 708 }
 709
 710 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
 711 {
 712         if (!ttm || ttm->func != &radeon_backend_func)
 713                 return NULL;
 714         return (struct radeon_ttm_tt *)ttm;
 715 }
 716
 717 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
 718 {
 719         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 720         struct radeon_device *rdev;
 721         unsigned i;
 722         int r;
 723         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 724
 725         if (ttm->state != tt_unpopulated)
 726                 return 0;
 727
 728         if (gtt && gtt->userptr) {
 729                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 730                 if (!ttm->sg)
 731                         return -ENOMEM;
 732
 733                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 734                 ttm->state = tt_unbound;
 735                 return 0;
 736         }
 737
 738         if (slave && ttm->sg) {
 739                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 740                                                  gtt->ttm.dma_address, ttm->num_pages);
 741                 ttm->state = tt_unbound;
 742                 return 0;
 743         }
 744
 745         rdev = radeon_get_rdev(ttm->bdev);
 746 #if IS_ENABLED(CONFIG_AGP)
 747         if (rdev->flags & RADEON_IS_AGP) {
 748                 return ttm_agp_tt_populate(ttm);
 749         }
 750 #endif
 751
 752 #ifdef CONFIG_SWIOTLB
 753         if (swiotlb_nr_tbl()) {
 754                 return ttm_dma_populate(&gtt->ttm, rdev->dev);
 755         }
 756 #endif
 757
 758         r = ttm_pool_populate(ttm);
 759         if (r) {
 760                 return r;
 761         }
 762
 763         for (i = 0; i < ttm->num_pages; i++) {
 764                 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
 765                                                        0, PAGE_SIZE,
 766                                                        PCI_DMA_BIDIRECTIONAL);
 767                 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
 768                         while (i--) {
 769                                 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 770                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 771                                 gtt->ttm.dma_address[i] = 0;
 772                         }
 773                         ttm_pool_unpopulate(ttm);
 774                         return -EFAULT;
 775                 }
 776         }
 777         return 0;
 778 }
 779
 780 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
 781 {
 782         struct radeon_device *rdev;
 783         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 784         unsigned i;
 785         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 786
 787         if (gtt && gtt->userptr) {
 788                 kfree(ttm->sg);
 789                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 790                 return;
 791         }
 792
 793         if (slave)
 794                 return;
 795
 796         rdev = radeon_get_rdev(ttm->bdev);
 797 #if IS_ENABLED(CONFIG_AGP)
 798         if (rdev->flags & RADEON_IS_AGP) {
 799                 ttm_agp_tt_unpopulate(ttm);
 800                 return;
 801         }
 802 #endif
 803
 804 #ifdef CONFIG_SWIOTLB
 805         if (swiotlb_nr_tbl()) {
 806                 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
 807                 return;
 808         }
 809 #endif
 810
 811         for (i = 0; i < ttm->num_pages; i++) {
 812                 if (gtt->ttm.dma_address[i]) {
 813                         pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 814                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 815                 }
 816         }
 817
 818         ttm_pool_unpopulate(ttm);
 819 }
 820
 821 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 822                               uint32_t flags)
 823 {
 824         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 825
 826         if (gtt == NULL)
 827                 return -EINVAL;
 828
 829         gtt->userptr = addr;
 830         gtt->usermm = current->mm;
 831         gtt->userflags = flags;
 832         return 0;
 833 }
 834
 835 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
 836 {
 837         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 838
 839         if (gtt == NULL)
 840                 return false;
 841
 842         return !!gtt->userptr;
 843 }
 844
 845 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
 846 {
 847         struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 848
 849         if (gtt == NULL)
 850                 return false;
 851
 852         return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 853 }
 854
 855 static struct ttm_bo_driver radeon_bo_driver = {
 856         .ttm_tt_create = &radeon_ttm_tt_create,
 857         .ttm_tt_populate = &radeon_ttm_tt_populate,
 858         .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
 859         .invalidate_caches = &radeon_invalidate_caches,
 860         .init_mem_type = &radeon_init_mem_type,
 861         .evict_flags = &radeon_evict_flags,
 862         .move = &radeon_bo_move,
 863         .verify_access = &radeon_verify_access,
 864         .move_notify = &radeon_bo_move_notify,
 865         .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
 866         .io_mem_reserve = &radeon_ttm_io_mem_reserve,
 867         .io_mem_free = &radeon_ttm_io_mem_free,
 868 };
 869
 870 int radeon_ttm_init(struct radeon_device *rdev)
 871 {
 872         int r;
 873
 874         r = radeon_ttm_global_init(rdev);
 875         if (r) {
 876                 return r;
 877         }
 878         /* No others user of address space so set it to 0 */
 879         r = ttm_bo_device_init(&rdev->mman.bdev,
 880                                rdev->mman.bo_global_ref.ref.object,
 881                                &radeon_bo_driver,
 882                                rdev->ddev->anon_inode->i_mapping,
 883                                DRM_FILE_PAGE_OFFSET,
 884                                rdev->need_dma32);
 885         if (r) {
 886                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 887                 return r;
 888         }
 889         rdev->mman.initialized = true;
 890         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
 891                                 rdev->mc.real_vram_size >> PAGE_SHIFT);
 892         if (r) {
 893                 DRM_ERROR("Failed initializing VRAM heap.\n");
 894                 return r;
 895         }
 896         /* Change the size here instead of the init above so only lpfn is affected */
 897         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 898
 899         r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
 900                              RADEON_GEM_DOMAIN_VRAM, 0, NULL,
 901                              NULL, &rdev->stollen_vga_memory);
 902         if (r) {
 903                 return r;
 904         }
 905         r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 906         if (r)
 907                 return r;
 908         r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
 909         radeon_bo_unreserve(rdev->stollen_vga_memory);
 910         if (r) {
 911                 radeon_bo_unref(&rdev->stollen_vga_memory);
 912                 return r;
 913         }
 914         DRM_INFO("radeon: %uM of VRAM memory ready\n",
 915                  (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
 916         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
 917                                 rdev->mc.gtt_size >> PAGE_SHIFT);
 918         if (r) {
 919                 DRM_ERROR("Failed initializing GTT heap.\n");
 920                 return r;
 921         }
 922         DRM_INFO("radeon: %uM of GTT memory ready.\n",
 923                  (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
 924
 925         r = radeon_ttm_debugfs_init(rdev);
 926         if (r) {
 927                 DRM_ERROR("Failed to init debugfs\n");
 928                 return r;
 929         }
 930         return 0;
 931 }
 932
 933 void radeon_ttm_fini(struct radeon_device *rdev)
 934 {
 935         int r;
 936
 937         if (!rdev->mman.initialized)
 938                 return;
 939         radeon_ttm_debugfs_fini(rdev);
 940         if (rdev->stollen_vga_memory) {
 941                 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 942                 if (r == 0) {
 943                         radeon_bo_unpin(rdev->stollen_vga_memory);
 944                         radeon_bo_unreserve(rdev->stollen_vga_memory);
 945                 }
 946                 radeon_bo_unref(&rdev->stollen_vga_memory);
 947         }
 948         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 949         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
 950         ttm_bo_device_release(&rdev->mman.bdev);
 951         radeon_gart_fini(rdev);
 952         radeon_ttm_global_fini(rdev);
 953         rdev->mman.initialized = false;
 954         DRM_INFO("radeon: ttm finalized\n");
 955 }
 956
 957 /* this should only be called at bootup or when userspace
 958  * isn't running */
 959 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
 960 {
 961         struct ttm_mem_type_manager *man;
 962
 963         if (!rdev->mman.initialized)
 964                 return;
 965
 966         man = &rdev->mman.bdev.man[TTM_PL_VRAM];
 967         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
 968         man->size = size >> PAGE_SHIFT;
 969 }
 970
 971 static struct vm_operations_struct radeon_ttm_vm_ops;
 972 static const struct vm_operations_struct *ttm_vm_ops = NULL;
 973
 974 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 975 {
 976         struct ttm_buffer_object *bo;
 977         struct radeon_device *rdev;
 978         int r;
 979
 980         bo = (struct ttm_buffer_object *)vma->vm_private_data;
 981         if (bo == NULL) {
 982                 return VM_FAULT_NOPAGE;
 983         }
 984         rdev = radeon_get_rdev(bo->bdev);
 985         down_read(&rdev->pm.mclk_lock);
 986         r = ttm_vm_ops->fault(vma, vmf);
 987         up_read(&rdev->pm.mclk_lock);
 988         return r;
 989 }
 990
 991 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
 992 {
 993         struct drm_file *file_priv;
 994         struct radeon_device *rdev;
 995         int r;
 996
 997         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
 998                 return -EINVAL;
 999         }
1000
1001         file_priv = filp->private_data;
1002         rdev = file_priv->minor->dev->dev_private;
1003         if (rdev == NULL) {
1004                 return -EINVAL;
1005         }
1006         r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
1007         if (unlikely(r != 0)) {
1008                 return r;
1009         }
1010         if (unlikely(ttm_vm_ops == NULL)) {
1011                 ttm_vm_ops = vma->vm_ops;
1012                 radeon_ttm_vm_ops = *ttm_vm_ops;
1013                 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
1014         }
1015         vma->vm_ops = &radeon_ttm_vm_ops;
1016         return 0;
1017 }
1018
1019 #if defined(CONFIG_DEBUG_FS)
1020
1021 static int radeon_mm_dump_table(struct seq_file *m, void *data)
1022 {
1023         struct drm_info_node *node = (struct drm_info_node *)m->private;
1024         unsigned ttm_pl = *(int *)node->info_ent->data;
1025         struct drm_device *dev = node->minor->dev;
1026         struct radeon_device *rdev = dev->dev_private;
1027         struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
1028         int ret;
1029         struct ttm_bo_global *glob = rdev->mman.bdev.glob;
1030
1031         spin_lock(&glob->lru_lock);
1032         ret = drm_mm_dump_table(m, mm);
1033         spin_unlock(&glob->lru_lock);
1034         return ret;
1035 }
1036
1037 static int ttm_pl_vram = TTM_PL_VRAM;
1038 static int ttm_pl_tt = TTM_PL_TT;
1039
1040 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1041         {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1042         {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1043         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1044 #ifdef CONFIG_SWIOTLB
1045         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1046 #endif
1047 };
1048
1049 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1050 {
1051         struct radeon_device *rdev = inode->i_private;
1052         i_size_write(inode, rdev->mc.mc_vram_size);
1053         filep->private_data = inode->i_private;
1054         return 0;
1055 }
1056
1057 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1058                                     size_t size, loff_t *pos)
1059 {
1060         struct radeon_device *rdev = f->private_data;
1061         ssize_t result = 0;
1062         int r;
1063
1064         if (size & 0x3 || *pos & 0x3)
1065                 return -EINVAL;
1066
1067         while (size) {
1068                 unsigned long flags;
1069                 uint32_t value;
1070
1071                 if (*pos >= rdev->mc.mc_vram_size)
1072                         return result;
1073
1074                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1075                 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1076                 if (rdev->family >= CHIP_CEDAR)
1077                         WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1078                 value = RREG32(RADEON_MM_DATA);
1079                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1080
1081                 r = put_user(value, (uint32_t *)buf);
1082                 if (r)
1083                         return r;
1084
1085                 result += 4;
1086                 buf += 4;
1087                 *pos += 4;
1088                 size -= 4;
1089         }
1090
1091         return result;
1092 }
1093
1094 static const struct file_operations radeon_ttm_vram_fops = {
1095         .owner = THIS_MODULE,
1096         .open = radeon_ttm_vram_open,
1097         .read = radeon_ttm_vram_read,
1098         .llseek = default_llseek
1099 };
1100
1101 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1102 {
1103         struct radeon_device *rdev = inode->i_private;
1104         i_size_write(inode, rdev->mc.gtt_size);
1105         filep->private_data = inode->i_private;
1106         return 0;
1107 }
1108
1109 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1110                                    size_t size, loff_t *pos)
1111 {
1112         struct radeon_device *rdev = f->private_data;
1113         ssize_t result = 0;
1114         int r;
1115
1116         while (size) {
1117                 loff_t p = *pos / PAGE_SIZE;
1118                 unsigned off = *pos & ~PAGE_MASK;
1119                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1120                 struct page *page;
1121                 void *ptr;
1122
1123                 if (p >= rdev->gart.num_cpu_pages)
1124                         return result;
1125
1126                 page = rdev->gart.pages[p];
1127                 if (page) {
1128                         ptr = kmap(page);
1129                         ptr += off;
1130
1131                         r = copy_to_user(buf, ptr, cur_size);
1132                         kunmap(rdev->gart.pages[p]);
1133                 } else
1134                         r = clear_user(buf, cur_size);
1135
1136                 if (r)
1137                         return -EFAULT;
1138
1139                 result += cur_size;
1140                 buf += cur_size;
1141                 *pos += cur_size;
1142                 size -= cur_size;
1143         }
1144
1145         return result;
1146 }
1147
1148 static const struct file_operations radeon_ttm_gtt_fops = {
1149         .owner = THIS_MODULE,
1150         .open = radeon_ttm_gtt_open,
1151         .read = radeon_ttm_gtt_read,
1152         .llseek = default_llseek
1153 };
1154
1155 #endif
1156
1157 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1158 {
1159 #if defined(CONFIG_DEBUG_FS)
1160         unsigned count;
1161
1162         struct drm_minor *minor = rdev->ddev->primary;
1163         struct dentry *ent, *root = minor->debugfs_root;
1164
1165         ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1166                                   rdev, &radeon_ttm_vram_fops);
1167         if (IS_ERR(ent))
1168                 return PTR_ERR(ent);
1169         rdev->mman.vram = ent;
1170
1171         ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1172                                   rdev, &radeon_ttm_gtt_fops);
1173         if (IS_ERR(ent))
1174                 return PTR_ERR(ent);
1175         rdev->mman.gtt = ent;
1176
1177         count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1178
1179 #ifdef CONFIG_SWIOTLB
1180         if (!swiotlb_nr_tbl())
1181                 --count;
1182 #endif
1183
1184         return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1185 #else
1186
1187         return 0;
1188 #endif
1189 }
1190
1191 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1192 {
1193 #if defined(CONFIG_DEBUG_FS)
1194
1195         debugfs_remove(rdev->mman.vram);
1196         rdev->mman.vram = NULL;
1197
1198         debugfs_remove(rdev->mman.gtt);
1199         rdev->mman.gtt = NULL;
1200 #endif
1201 }