drivers/mmc/host/sdhci-pxav3.c

   1 /*
   2  * Copyright (C) 2010 Marvell International Ltd.
   3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
   4  *              Kevin Wang <dwang4@marvell.com>
   5  *              Mingwei Wang <mwwang@marvell.com>
   6  *              Philip Rakity <prakity@marvell.com>
   7  *              Mark Brown <markb@marvell.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/slot-gpio.h>
  28 #include <linux/platform_data/pxa_sdhci.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_gpio.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/mbus.h>
  38
  39 #include "sdhci.h"
  40 #include "sdhci-pltfm.h"
  41
  42 #define PXAV3_RPM_DELAY_MS     50
  43
  44 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
  45 #define SDCLK_SEL       0x100
  46 #define SDCLK_DELAY_SHIFT       9
  47 #define SDCLK_DELAY_MASK        0x1f
  48
  49 #define SD_CFG_FIFO_PARAM       0x100
  50 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
  51 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
  52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
  53
  54 #define SD_SPI_MODE          0x108
  55 #define SD_CE_ATA_1          0x10C
  56
  57 #define SD_CE_ATA_2          0x10E
  58 #define SDCE_MISC_INT           (1<<2)
  59 #define SDCE_MISC_INT_EN        (1<<1)
  60
  61 struct sdhci_pxa {
  62         struct clk *clk_core;
  63         struct clk *clk_io;
  64         u8      power_mode;
  65         void __iomem *sdio3_conf_reg;
  66 };
  67
  68 /*
  69  * These registers are relative to the second register region, for the
  70  * MBus bridge.
  71  */
  72 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
  73 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
  74 #define SDHCI_MAX_WIN_NUM       8
  75
  76 /*
  77  * Fields below belong to SDIO3 Configuration Register (third register
  78  * region for the Armada 38x flavor)
  79  */
  80
  81 #define SDIO3_CONF_CLK_INV      BIT(0)
  82 #define SDIO3_CONF_SD_FB_CLK    BIT(2)
  83
  84 static int mv_conf_mbus_windows(struct platform_device *pdev,
  85                                 const struct mbus_dram_target_info *dram)
  86 {
  87         int i;
  88         void __iomem *regs;
  89         struct resource *res;
  90
  91         if (!dram) {
  92                 dev_err(&pdev->dev, "no mbus dram info\n");
  93                 return -EINVAL;
  94         }
  95
  96         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  97         if (!res) {
  98                 dev_err(&pdev->dev, "cannot get mbus registers\n");
  99                 return -EINVAL;
 100         }
 101
 102         regs = ioremap(res->start, resource_size(res));
 103         if (!regs) {
 104                 dev_err(&pdev->dev, "cannot map mbus registers\n");
 105                 return -ENOMEM;
 106         }
 107
 108         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
 109                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
 110                 writel(0, regs + SDHCI_WINDOW_BASE(i));
 111         }
 112
 113         for (i = 0; i < dram->num_cs; i++) {
 114                 const struct mbus_dram_window *cs = dram->cs + i;
 115
 116                 /* Write size, attributes and target id to control register */
 117                 writel(((cs->size - 1) & 0xffff0000) |
 118                         (cs->mbus_attr << 8) |
 119                         (dram->mbus_dram_target_id << 4) | 1,
 120                         regs + SDHCI_WINDOW_CTRL(i));
 121                 /* Write base address to base register */
 122                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
 123         }
 124
 125         iounmap(regs);
 126
 127         return 0;
 128 }
 129
 130 static int armada_38x_quirks(struct platform_device *pdev,
 131                              struct sdhci_host *host)
 132 {
 133         struct device_node *np = pdev->dev.of_node;
 134         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 135         struct sdhci_pxa *pxa = pltfm_host->priv;
 136         struct resource *res;
 137
 138         host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 139         host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
 140         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 141                                            "conf-sdio3");
 142         if (res) {
 143                 pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
 144                 if (IS_ERR(pxa->sdio3_conf_reg))
 145                         return PTR_ERR(pxa->sdio3_conf_reg);
 146         } else {
 147                 /*
 148                  * According to erratum 'FE-2946959' both SDR50 and DDR50
 149                  * modes require specific clock adjustments in SDIO3
 150                  * Configuration register, if the adjustment is not done,
 151                  * remove them from the capabilities.
 152                  */
 153                 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 154                 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
 155
 156                 dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
 157         }
 158
 159         /*
 160          * According to erratum 'ERR-7878951' Armada 38x SDHCI
 161          * controller has different capabilities than the ones shown
 162          * in its registers
 163          */
 164         host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 165         if (of_property_read_bool(np, "no-1-8-v")) {
 166                 host->caps &= ~SDHCI_CAN_VDD_180;
 167                 host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
 168         } else {
 169                 host->caps &= ~SDHCI_CAN_VDD_330;
 170         }
 171         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
 172
 173         return 0;
 174 }
 175
 176 static void pxav3_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
 179         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 180
 181         sdhci_reset(host, mask);
 182
 183         if (mask == SDHCI_RESET_ALL) {
 184                 /*
 185                  * tune timing of read data/command when crc error happen
 186                  * no performance impact
 187                  */
 188                 if (pdata && 0 != pdata->clk_delay_cycles) {
 189                         u16 tmp;
 190
 191                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 192                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
 193                                 << SDCLK_DELAY_SHIFT;
 194                         tmp |= SDCLK_SEL;
 195                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 196                 }
 197         }
 198 }
 199
 200 #define MAX_WAIT_COUNT 5
 201 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 202 {
 203         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 204         struct sdhci_pxa *pxa = pltfm_host->priv;
 205         u16 tmp;
 206         int count;
 207
 208         if (pxa->power_mode == MMC_POWER_UP
 209                         && power_mode == MMC_POWER_ON) {
 210
 211                 dev_dbg(mmc_dev(host->mmc),
 212                                 "%s: slot->power_mode = %d,"
 213                                 "ios->power_mode = %d\n",
 214                                 __func__,
 215                                 pxa->power_mode,
 216                                 power_mode);
 217
 218                 /* set we want notice of when 74 clocks are sent */
 219                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 220                 tmp |= SDCE_MISC_INT_EN;
 221                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 222
 223                 /* start sending the 74 clocks */
 224                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
 225                 tmp |= SDCFG_GEN_PAD_CLK_ON;
 226                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
 227
 228                 /* slowest speed is about 100KHz or 10usec per clock */
 229                 udelay(740);
 230                 count = 0;
 231
 232                 while (count++ < MAX_WAIT_COUNT) {
 233                         if ((readw(host->ioaddr + SD_CE_ATA_2)
 234                                                 & SDCE_MISC_INT) == 0)
 235                                 break;
 236                         udelay(10);
 237                 }
 238
 239                 if (count == MAX_WAIT_COUNT)
 240                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
 241
 242                 /* clear the interrupt bit if posted */
 243                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 244                 tmp |= SDCE_MISC_INT;
 245                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 246         }
 247         pxa->power_mode = power_mode;
 248 }
 249
 250 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 251 {
 252         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 253         struct sdhci_pxa *pxa = pltfm_host->priv;
 254         u16 ctrl_2;
 255
 256         /*
 257          * Set V18_EN -- UHS modes do not work without this.
 258          * does not change signaling voltage
 259          */
 260         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 261
 262         /* Select Bus Speed Mode for host */
 263         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 264         switch (uhs) {
 265         case MMC_TIMING_UHS_SDR12:
 266                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 267                 break;
 268         case MMC_TIMING_UHS_SDR25:
 269                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 270                 break;
 271         case MMC_TIMING_UHS_SDR50:
 272                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
 273                 break;
 274         case MMC_TIMING_UHS_SDR104:
 275                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
 276                 break;
 277         case MMC_TIMING_MMC_DDR52:
 278         case MMC_TIMING_UHS_DDR50:
 279                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
 280                 break;
 281         }
 282
 283         /*
 284          * Update SDIO3 Configuration register according to erratum
 285          * FE-2946959
 286          */
 287         if (pxa->sdio3_conf_reg) {
 288                 u8 reg_val  = readb(pxa->sdio3_conf_reg);
 289
 290                 if (uhs == MMC_TIMING_UHS_SDR50 ||
 291                     uhs == MMC_TIMING_UHS_DDR50) {
 292                         reg_val &= ~SDIO3_CONF_CLK_INV;
 293                         reg_val |= SDIO3_CONF_SD_FB_CLK;
 294                 } else {
 295                         reg_val |= SDIO3_CONF_CLK_INV;
 296                         reg_val &= ~SDIO3_CONF_SD_FB_CLK;
 297                 }
 298                 writeb(reg_val, pxa->sdio3_conf_reg);
 299         }
 300
 301         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 302         dev_dbg(mmc_dev(host->mmc),
 303                 "%s uhs = %d, ctrl_2 = %04X\n",
 304                 __func__, uhs, ctrl_2);
 305 }
 306
 307 static const struct sdhci_ops pxav3_sdhci_ops = {
 308         .set_clock = sdhci_set_clock,
 309         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
 310         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 311         .set_bus_width = sdhci_set_bus_width,
 312         .reset = pxav3_reset,
 313         .set_uhs_signaling = pxav3_set_uhs_signaling,
 314 };
 315
 316 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
 317         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
 318                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 319                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
 320                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 321         .ops = &pxav3_sdhci_ops,
 322 };
 323
 324 #ifdef CONFIG_OF
 325 static const struct of_device_id sdhci_pxav3_of_match[] = {
 326         {
 327                 .compatible = "mrvl,pxav3-mmc",
 328         },
 329         {
 330                 .compatible = "marvell,armada-380-sdhci",
 331         },
 332         {},
 333 };
 334 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
 335
 336 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 337 {
 338         struct sdhci_pxa_platdata *pdata;
 339         struct device_node *np = dev->of_node;
 340         u32 clk_delay_cycles;
 341
 342         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 343         if (!pdata)
 344                 return NULL;
 345
 346         if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
 347                                   &clk_delay_cycles))
 348                 pdata->clk_delay_cycles = clk_delay_cycles;
 349
 350         return pdata;
 351 }
 352 #else
 353 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 354 {
 355         return NULL;
 356 }
 357 #endif
 358
 359 static int sdhci_pxav3_probe(struct platform_device *pdev)
 360 {
 361         struct sdhci_pltfm_host *pltfm_host;
 362         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 363         struct device *dev = &pdev->dev;
 364         struct device_node *np = pdev->dev.of_node;
 365         struct sdhci_host *host = NULL;
 366         struct sdhci_pxa *pxa = NULL;
 367         const struct of_device_id *match;
 368         int ret;
 369
 370         pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
 371         if (!pxa)
 372                 return -ENOMEM;
 373
 374         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
 375         if (IS_ERR(host))
 376                 return PTR_ERR(host);
 377
 378         pltfm_host = sdhci_priv(host);
 379         pltfm_host->priv = pxa;
 380
 381         pxa->clk_io = devm_clk_get(dev, "io");
 382         if (IS_ERR(pxa->clk_io))
 383                 pxa->clk_io = devm_clk_get(dev, NULL);
 384         if (IS_ERR(pxa->clk_io)) {
 385                 dev_err(dev, "failed to get io clock\n");
 386                 ret = PTR_ERR(pxa->clk_io);
 387                 goto err_clk_get;
 388         }
 389         pltfm_host->clk = pxa->clk_io;
 390         clk_prepare_enable(pxa->clk_io);
 391
 392         pxa->clk_core = devm_clk_get(dev, "core");
 393         if (!IS_ERR(pxa->clk_core))
 394                 clk_prepare_enable(pxa->clk_core);
 395
 396         /* enable 1/8V DDR capable */
 397         host->mmc->caps |= MMC_CAP_1_8V_DDR;
 398
 399         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
 400                 ret = armada_38x_quirks(pdev, host);
 401                 if (ret < 0)
 402                         goto err_clk_get;
 403                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
 404                 if (ret < 0)
 405                         goto err_mbus_win;
 406         }
 407
 408         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
 409         if (match) {
 410                 ret = mmc_of_parse(host->mmc);
 411                 if (ret)
 412                         goto err_of_parse;
 413                 sdhci_get_of_property(pdev);
 414                 pdata = pxav3_get_mmc_pdata(dev);
 415                 pdev->dev.platform_data = pdata;
 416         } else if (pdata) {
 417                 /* on-chip device */
 418                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
 419                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 420
 421                 /* If slot design supports 8 bit data, indicate this to MMC. */
 422                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 423                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 424
 425                 if (pdata->quirks)
 426                         host->quirks |= pdata->quirks;
 427                 if (pdata->quirks2)
 428                         host->quirks2 |= pdata->quirks2;
 429                 if (pdata->host_caps)
 430                         host->mmc->caps |= pdata->host_caps;
 431                 if (pdata->host_caps2)
 432                         host->mmc->caps2 |= pdata->host_caps2;
 433                 if (pdata->pm_caps)
 434                         host->mmc->pm_caps |= pdata->pm_caps;
 435
 436                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
 437                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
 438                                                   0);
 439                         if (ret) {
 440                                 dev_err(mmc_dev(host->mmc),
 441                                         "failed to allocate card detect gpio\n");
 442                                 goto err_cd_req;
 443                         }
 444                 }
 445         }
 446
 447         pm_runtime_get_noresume(&pdev->dev);
 448         pm_runtime_set_active(&pdev->dev);
 449         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
 450         pm_runtime_use_autosuspend(&pdev->dev);
 451         pm_runtime_enable(&pdev->dev);
 452         pm_suspend_ignore_children(&pdev->dev, 1);
 453
 454         ret = sdhci_add_host(host);
 455         if (ret) {
 456                 dev_err(&pdev->dev, "failed to add host\n");
 457                 goto err_add_host;
 458         }
 459
 460         platform_set_drvdata(pdev, host);
 461
 462         if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
 463                 device_init_wakeup(&pdev->dev, 1);
 464
 465         pm_runtime_put_autosuspend(&pdev->dev);
 466
 467         return 0;
 468
 469 err_add_host:
 470         pm_runtime_disable(&pdev->dev);
 471         pm_runtime_put_noidle(&pdev->dev);
 472 err_of_parse:
 473 err_cd_req:
 474 err_mbus_win:
 475         clk_disable_unprepare(pxa->clk_io);
 476         clk_disable_unprepare(pxa->clk_core);
 477 err_clk_get:
 478         sdhci_pltfm_free(pdev);
 479         return ret;
 480 }
 481
 482 static int sdhci_pxav3_remove(struct platform_device *pdev)
 483 {
 484         struct sdhci_host *host = platform_get_drvdata(pdev);
 485         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 486         struct sdhci_pxa *pxa = pltfm_host->priv;
 487
 488         pm_runtime_get_sync(&pdev->dev);
 489         pm_runtime_disable(&pdev->dev);
 490         pm_runtime_put_noidle(&pdev->dev);
 491
 492         sdhci_remove_host(host, 1);
 493
 494         clk_disable_unprepare(pxa->clk_io);
 495         clk_disable_unprepare(pxa->clk_core);
 496
 497         sdhci_pltfm_free(pdev);
 498
 499         return 0;
 500 }
 501
 502 #ifdef CONFIG_PM_SLEEP
 503 static int sdhci_pxav3_suspend(struct device *dev)
 504 {
 505         int ret;
 506         struct sdhci_host *host = dev_get_drvdata(dev);
 507
 508         pm_runtime_get_sync(dev);
 509         ret = sdhci_suspend_host(host);
 510         pm_runtime_mark_last_busy(dev);
 511         pm_runtime_put_autosuspend(dev);
 512
 513         return ret;
 514 }
 515
 516 static int sdhci_pxav3_resume(struct device *dev)
 517 {
 518         int ret;
 519         struct sdhci_host *host = dev_get_drvdata(dev);
 520
 521         pm_runtime_get_sync(dev);
 522         ret = sdhci_resume_host(host);
 523         pm_runtime_mark_last_busy(dev);
 524         pm_runtime_put_autosuspend(dev);
 525
 526         return ret;
 527 }
 528 #endif
 529
 530 #ifdef CONFIG_PM
 531 static int sdhci_pxav3_runtime_suspend(struct device *dev)
 532 {
 533         struct sdhci_host *host = dev_get_drvdata(dev);
 534         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 535         struct sdhci_pxa *pxa = pltfm_host->priv;
 536         int ret;
 537
 538         ret = sdhci_runtime_suspend_host(host);
 539         if (ret)
 540                 return ret;
 541
 542         clk_disable_unprepare(pxa->clk_io);
 543         if (!IS_ERR(pxa->clk_core))
 544                 clk_disable_unprepare(pxa->clk_core);
 545
 546         return 0;
 547 }
 548
 549 static int sdhci_pxav3_runtime_resume(struct device *dev)
 550 {
 551         struct sdhci_host *host = dev_get_drvdata(dev);
 552         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 553         struct sdhci_pxa *pxa = pltfm_host->priv;
 554
 555         clk_prepare_enable(pxa->clk_io);
 556         if (!IS_ERR(pxa->clk_core))
 557                 clk_prepare_enable(pxa->clk_core);
 558
 559         return sdhci_runtime_resume_host(host);
 560 }
 561 #endif
 562
 563 #ifdef CONFIG_PM
 564 static const struct dev_pm_ops sdhci_pxav3_pmops = {
 565         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
 566         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
 567                 sdhci_pxav3_runtime_resume, NULL)
 568 };
 569
 570 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
 571
 572 #else
 573 #define SDHCI_PXAV3_PMOPS NULL
 574 #endif
 575
 576 static struct platform_driver sdhci_pxav3_driver = {
 577         .driver         = {
 578                 .name   = "sdhci-pxav3",
 579                 .of_match_table = of_match_ptr(sdhci_pxav3_of_match),
 580                 .pm     = SDHCI_PXAV3_PMOPS,
 581         },
 582         .probe          = sdhci_pxav3_probe,
 583         .remove         = sdhci_pxav3_remove,
 584 };
 585
 586 module_platform_driver(sdhci_pxav3_driver);
 587
 588 MODULE_DESCRIPTION("SDHCI driver for pxav3");
 589 MODULE_AUTHOR("Marvell International Ltd.");
 590 MODULE_LICENSE("GPL v2");
 591