sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = codec->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110         case WM8994_DC_SERVO_4E:
 111                 return 1;
 112         default:
 113                 return 0;
 114         }
 115 }
 116
 117 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 118         unsigned int value)
 119 {
 120         int ret;
 121
 122         BUG_ON(reg > WM8994_MAX_REGISTER);
 123
 124         if (!wm8994_volatile(codec, reg)) {
 125                 ret = snd_soc_cache_write(codec, reg, value);
 126                 if (ret != 0)
 127                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 128                                 reg, ret);
 129         }
 130
 131         return wm8994_reg_write(codec->control_data, reg, value);
 132 }
 133
 134 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 135                                 unsigned int reg)
 136 {
 137         unsigned int val;
 138         int ret;
 139
 140         BUG_ON(reg > WM8994_MAX_REGISTER);
 141
 142         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 143             reg < codec->driver->reg_cache_size) {
 144                 ret = snd_soc_cache_read(codec, reg, &val);
 145                 if (ret >= 0)
 146                         return val;
 147                 else
 148                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 149                                 reg, ret);
 150         }
 151
 152         return wm8994_reg_read(codec->control_data, reg);
 153 }
 154
 155 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 156 {
 157         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 158         int rate;
 159         int reg1 = 0;
 160         int offset;
 161
 162         if (aif)
 163                 offset = 4;
 164         else
 165                 offset = 0;
 166
 167         switch (wm8994->sysclk[aif]) {
 168         case WM8994_SYSCLK_MCLK1:
 169                 rate = wm8994->mclk[0];
 170                 break;
 171
 172         case WM8994_SYSCLK_MCLK2:
 173                 reg1 |= 0x8;
 174                 rate = wm8994->mclk[1];
 175                 break;
 176
 177         case WM8994_SYSCLK_FLL1:
 178                 reg1 |= 0x10;
 179                 rate = wm8994->fll[0].out;
 180                 break;
 181
 182         case WM8994_SYSCLK_FLL2:
 183                 reg1 |= 0x18;
 184                 rate = wm8994->fll[1].out;
 185                 break;
 186
 187         default:
 188                 return -EINVAL;
 189         }
 190
 191         if (rate >= 13500000) {
 192                 rate /= 2;
 193                 reg1 |= WM8994_AIF1CLK_DIV;
 194
 195                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 196                         aif + 1, rate);
 197         }
 198
 199         wm8994->aifclk[aif] = rate;
 200
 201         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 202                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 203                             reg1);
 204
 205         return 0;
 206 }
 207
 208 static int configure_clock(struct snd_soc_codec *codec)
 209 {
 210         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 211         int change, new;
 212
 213         /* Bring up the AIF clocks first */
 214         configure_aif_clock(codec, 0);
 215         configure_aif_clock(codec, 1);
 216
 217         /* Then switch CLK_SYS over to the higher of them; a change
 218          * can only happen as a result of a clocking change which can
 219          * only be made outside of DAPM so we can safely redo the
 220          * clocking.
 221          */
 222
 223         /* If they're equal it doesn't matter which is used */
 224         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 225                 return 0;
 226
 227         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 228                 new = WM8994_SYSCLK_SRC;
 229         else
 230                 new = 0;
 231
 232         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 233                                      WM8994_SYSCLK_SRC, new);
 234         if (!change)
 235                 return 0;
 236
 237         snd_soc_dapm_sync(&codec->dapm);
 238
 239         return 0;
 240 }
 241
 242 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 243                          struct snd_soc_dapm_widget *sink)
 244 {
 245         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 246         const char *clk;
 247
 248         /* Check what we're currently using for CLK_SYS */
 249         if (reg & WM8994_SYSCLK_SRC)
 250                 clk = "AIF2CLK";
 251         else
 252                 clk = "AIF1CLK";
 253
 254         return strcmp(source->name, clk) == 0;
 255 }
 256
 257 static const char *sidetone_hpf_text[] = {
 258         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 259 };
 260
 261 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
 262                             WM8994_SIDETONE, 7, sidetone_hpf_text);
 263
 264 static const char *adc_hpf_text[] = {
 265         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 266 };
 267
 268 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
 269                             WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
 270
 271 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
 272                             WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
 273
 274 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
 275                             WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
 276
 277 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 278 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 279 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 280 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 281 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 282 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 283 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 284
 285 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 286 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 287         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 288         .put = wm8994_put_drc_sw, \
 289         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 290
 291 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 292                              struct snd_ctl_elem_value *ucontrol)
 293 {
 294         struct soc_mixer_control *mc =
 295                 (struct soc_mixer_control *)kcontrol->private_value;
 296         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 297         int mask, ret;
 298
 299         /* Can't enable both ADC and DAC paths simultaneously */
 300         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 301                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 302                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 303         else
 304                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 305
 306         ret = snd_soc_read(codec, mc->reg);
 307         if (ret < 0)
 308                 return ret;
 309         if (ret & mask)
 310                 return -EINVAL;
 311
 312         return snd_soc_put_volsw(kcontrol, ucontrol);
 313 }
 314
 315 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 316 {
 317         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 318         struct wm8994_pdata *pdata = wm8994->pdata;
 319         int base = wm8994_drc_base[drc];
 320         int cfg = wm8994->drc_cfg[drc];
 321         int save, i;
 322
 323         /* Save any enables; the configuration should clear them. */
 324         save = snd_soc_read(codec, base);
 325         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 326                 WM8994_AIF1ADC1R_DRC_ENA;
 327
 328         for (i = 0; i < WM8994_DRC_REGS; i++)
 329                 snd_soc_update_bits(codec, base + i, 0xffff,
 330                                     pdata->drc_cfgs[cfg].regs[i]);
 331
 332         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 333                              WM8994_AIF1ADC1L_DRC_ENA |
 334                              WM8994_AIF1ADC1R_DRC_ENA, save);
 335 }
 336
 337 /* Icky as hell but saves code duplication */
 338 static int wm8994_get_drc(const char *name)
 339 {
 340         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 341                 return 0;
 342         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 343                 return 1;
 344         if (strcmp(name, "AIF2DRC Mode") == 0)
 345                 return 2;
 346         return -EINVAL;
 347 }
 348
 349 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 350                                struct snd_ctl_elem_value *ucontrol)
 351 {
 352         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 353         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 354         struct wm8994_pdata *pdata = wm8994->pdata;
 355         int drc = wm8994_get_drc(kcontrol->id.name);
 356         int value = ucontrol->value.integer.value[0];
 357
 358         if (drc < 0)
 359                 return drc;
 360
 361         if (value >= pdata->num_drc_cfgs)
 362                 return -EINVAL;
 363
 364         wm8994->drc_cfg[drc] = value;
 365
 366         wm8994_set_drc(codec, drc);
 367
 368         return 0;
 369 }
 370
 371 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 372                                struct snd_ctl_elem_value *ucontrol)
 373 {
 374         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 375         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 376         int drc = wm8994_get_drc(kcontrol->id.name);
 377
 378         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 379
 380         return 0;
 381 }
 382
 383 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 384 {
 385         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 386         struct wm8994_pdata *pdata = wm8994->pdata;
 387         int base = wm8994_retune_mobile_base[block];
 388         int iface, best, best_val, save, i, cfg;
 389
 390         if (!pdata || !wm8994->num_retune_mobile_texts)
 391                 return;
 392
 393         switch (block) {
 394         case 0:
 395         case 1:
 396                 iface = 0;
 397                 break;
 398         case 2:
 399                 iface = 1;
 400                 break;
 401         default:
 402                 return;
 403         }
 404
 405         /* Find the version of the currently selected configuration
 406          * with the nearest sample rate. */
 407         cfg = wm8994->retune_mobile_cfg[block];
 408         best = 0;
 409         best_val = INT_MAX;
 410         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 411                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 412                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 413                     abs(pdata->retune_mobile_cfgs[i].rate
 414                         - wm8994->dac_rates[iface]) < best_val) {
 415                         best = i;
 416                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 417                                        - wm8994->dac_rates[iface]);
 418                 }
 419         }
 420
 421         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 422                 block,
 423                 pdata->retune_mobile_cfgs[best].name,
 424                 pdata->retune_mobile_cfgs[best].rate,
 425                 wm8994->dac_rates[iface]);
 426
 427         /* The EQ will be disabled while reconfiguring it, remember the
 428          * current configuration.
 429          */
 430         save = snd_soc_read(codec, base);
 431         save &= WM8994_AIF1DAC1_EQ_ENA;
 432
 433         for (i = 0; i < WM8994_EQ_REGS; i++)
 434                 snd_soc_update_bits(codec, base + i, 0xffff,
 435                                 pdata->retune_mobile_cfgs[best].regs[i]);
 436
 437         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 438 }
 439
 440 /* Icky as hell but saves code duplication */
 441 static int wm8994_get_retune_mobile_block(const char *name)
 442 {
 443         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 444                 return 0;
 445         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 446                 return 1;
 447         if (strcmp(name, "AIF2 EQ Mode") == 0)
 448                 return 2;
 449         return -EINVAL;
 450 }
 451
 452 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 453                                          struct snd_ctl_elem_value *ucontrol)
 454 {
 455         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 456         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 457         struct wm8994_pdata *pdata = wm8994->pdata;
 458         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 459         int value = ucontrol->value.integer.value[0];
 460
 461         if (block < 0)
 462                 return block;
 463
 464         if (value >= pdata->num_retune_mobile_cfgs)
 465                 return -EINVAL;
 466
 467         wm8994->retune_mobile_cfg[block] = value;
 468
 469         wm8994_set_retune_mobile(codec, block);
 470
 471         return 0;
 472 }
 473
 474 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 475                                          struct snd_ctl_elem_value *ucontrol)
 476 {
 477         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 478         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 479         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 480
 481         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 482
 483         return 0;
 484 }
 485
 486 static const char *aif_chan_src_text[] = {
 487         "Left", "Right"
 488 };
 489
 490 static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
 491                             WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
 492
 493 static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
 494                             WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
 495
 496 static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
 497                             WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
 498
 499 static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
 500                             WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
 501
 502 static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
 503                             WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
 504
 505 static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
 506                             WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
 507
 508 static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
 509                             WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
 510
 511 static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
 512                             WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
 513
 514 static const char *osr_text[] = {
 515         "Low Power", "High Performance",
 516 };
 517
 518 static SOC_ENUM_SINGLE_DECL(dac_osr,
 519                             WM8994_OVERSAMPLING, 0, osr_text);
 520
 521 static SOC_ENUM_SINGLE_DECL(adc_osr,
 522                             WM8994_OVERSAMPLING, 1, osr_text);
 523
 524 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 525 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 526                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 527                  1, 119, 0, digital_tlv),
 528 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 529                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 530                  1, 119, 0, digital_tlv),
 531 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 532                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 533                  1, 119, 0, digital_tlv),
 534
 535 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 536 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 537 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 538 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 539
 540 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 541 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 542 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 543 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 544
 545 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 546                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 547 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 548                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 549 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 550                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 551
 552 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 553 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 554
 555 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 556 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 557 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 558
 559 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 560 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 561 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 562
 563 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 564 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 565 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 566
 567 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 568 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 569 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 570
 571 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 572                5, 12, 0, st_tlv),
 573 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 574                0, 12, 0, st_tlv),
 575 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 576                5, 12, 0, st_tlv),
 577 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 578                0, 12, 0, st_tlv),
 579 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 580 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 581
 582 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 583 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 584
 585 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 586 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 587
 588 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 589 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 590
 591 SOC_ENUM("ADC OSR", adc_osr),
 592 SOC_ENUM("DAC OSR", dac_osr),
 593
 594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 595                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 596 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 597              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 598
 599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 600                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 601 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 602              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 603
 604 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 605                6, 1, 1, wm_hubs_spkmix_tlv),
 606 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 607                2, 1, 1, wm_hubs_spkmix_tlv),
 608
 609 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 610                6, 1, 1, wm_hubs_spkmix_tlv),
 611 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 612                2, 1, 1, wm_hubs_spkmix_tlv),
 613
 614 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 615                10, 15, 0, wm8994_3d_tlv),
 616 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 617            8, 1, 0),
 618 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 619                10, 15, 0, wm8994_3d_tlv),
 620 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 621            8, 1, 0),
 622 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 623                10, 15, 0, wm8994_3d_tlv),
 624 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 625            8, 1, 0),
 626 };
 627
 628 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 629 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 630                eq_tlv),
 631 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 632                eq_tlv),
 633 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 634                eq_tlv),
 635 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 636                eq_tlv),
 637 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 638                eq_tlv),
 639
 640 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 641                eq_tlv),
 642 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 649                eq_tlv),
 650
 651 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 660                eq_tlv),
 661 };
 662
 663 static const char *wm8958_ng_text[] = {
 664         "30ms", "125ms", "250ms", "500ms",
 665 };
 666
 667 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
 668                             WM8958_AIF1_DAC1_NOISE_GATE,
 669                             WM8958_AIF1DAC1_NG_THR_SHIFT,
 670                             wm8958_ng_text);
 671
 672 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
 673                             WM8958_AIF1_DAC2_NOISE_GATE,
 674                             WM8958_AIF1DAC2_NG_THR_SHIFT,
 675                             wm8958_ng_text);
 676
 677 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
 678                             WM8958_AIF2_DAC_NOISE_GATE,
 679                             WM8958_AIF2DAC_NG_THR_SHIFT,
 680                             wm8958_ng_text);
 681
 682 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 683 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 684
 685 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 686            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 687 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 688 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 689                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 690                7, 1, ng_tlv),
 691
 692 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 693            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 694 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 695 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 696                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 697                7, 1, ng_tlv),
 698
 699 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 700            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 701 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 702 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 703                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 704                7, 1, ng_tlv),
 705 };
 706
 707 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 708 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 709                mixin_boost_tlv),
 710 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 711                mixin_boost_tlv),
 712 };
 713
 714 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 715                          struct snd_kcontrol *kcontrol, int event)
 716 {
 717         struct snd_soc_codec *codec = w->codec;
 718
 719         switch (event) {
 720         case SND_SOC_DAPM_PRE_PMU:
 721                 return configure_clock(codec);
 722
 723         case SND_SOC_DAPM_POST_PMU:
 724                 /*
 725                  * JACKDET won't run until we start the clock and it
 726                  * only reports deltas, make sure we notify the state
 727                  * up the stack on startup.  Use a *very* generous
 728                  * timeout for paranoia, there's no urgency and we
 729                  * don't want false reports.
 730                  */
 731                 if (wm8994->jackdet && !wm8994->clk_has_run) {
 732                         queue_delayed_work(system_power_efficient_wq,
 733                                            &wm8994->jackdet_bootstrap,
 734                                            msecs_to_jiffies(1000));
 735                         wm8994->clk_has_run = true;
 736                 }
 737                 break;
 738
 739         case SND_SOC_DAPM_POST_PMD:
 740                 configure_clock(codec);
 741                 break;
 742         }
 743
 744         return 0;
 745 }
 746
 747 static void vmid_reference(struct snd_soc_codec *codec)
 748 {
 749         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 750
 751         wm8994->vmid_refcount++;
 752
 753         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 754                 wm8994->vmid_refcount);
 755
 756         if (wm8994->vmid_refcount == 1) {
 757                 /* Startup bias, VMID ramp & buffer */
 758                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 759                                     WM8994_STARTUP_BIAS_ENA |
 760                                     WM8994_VMID_BUF_ENA |
 761                                     WM8994_VMID_RAMP_MASK,
 762                                     WM8994_STARTUP_BIAS_ENA |
 763                                     WM8994_VMID_BUF_ENA |
 764                                     (0x11 << WM8994_VMID_RAMP_SHIFT));
 765
 766                 /* Main bias enable, VMID=2x40k */
 767                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 768                                     WM8994_BIAS_ENA |
 769                                     WM8994_VMID_SEL_MASK,
 770                                     WM8994_BIAS_ENA | 0x2);
 771
 772                 msleep(20);
 773         }
 774 }
 775
 776 static void vmid_dereference(struct snd_soc_codec *codec)
 777 {
 778         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 779
 780         wm8994->vmid_refcount--;
 781
 782         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 783                 wm8994->vmid_refcount);
 784
 785         if (wm8994->vmid_refcount == 0) {
 786                 /* Switch over to startup biases */
 787                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 788                                     WM8994_BIAS_SRC |
 789                                     WM8994_STARTUP_BIAS_ENA |
 790                                     WM8994_VMID_BUF_ENA |
 791                                     WM8994_VMID_RAMP_MASK,
 792                                     WM8994_BIAS_SRC |
 793                                     WM8994_STARTUP_BIAS_ENA |
 794                                     WM8994_VMID_BUF_ENA |
 795                                     (1 << WM8994_VMID_RAMP_SHIFT));
 796
 797                 /* Disable main biases */
 798                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 799                                     WM8994_BIAS_ENA |
 800                                     WM8994_VMID_SEL_MASK, 0);
 801
 802                 /* Discharge line */
 803                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 804                                     WM8994_LINEOUT1_DISCH |
 805                                     WM8994_LINEOUT2_DISCH,
 806                                     WM8994_LINEOUT1_DISCH |
 807                                     WM8994_LINEOUT2_DISCH);
 808
 809                 msleep(5);
 810
 811                 /* Switch off startup biases */
 812                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 813                                     WM8994_BIAS_SRC |
 814                                     WM8994_STARTUP_BIAS_ENA |
 815                                     WM8994_VMID_BUF_ENA |
 816                                     WM8994_VMID_RAMP_MASK, 0);
 817         }
 818 }
 819
 820 static int vmid_event(struct snd_soc_dapm_widget *w,
 821                       struct snd_kcontrol *kcontrol, int event)
 822 {
 823         struct snd_soc_codec *codec = w->codec;
 824
 825         switch (event) {
 826         case SND_SOC_DAPM_PRE_PMU:
 827                 vmid_reference(codec);
 828                 break;
 829
 830         case SND_SOC_DAPM_POST_PMD:
 831                 vmid_dereference(codec);
 832                 break;
 833         }
 834
 835         return 0;
 836 }
 837
 838 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 839 {
 840         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 841         int enable = 1;
 842         int source = 0;  /* GCC flow analysis can't track enable */
 843         int reg, reg_r;
 844
 845         /* Only support direct DAC->headphone paths */
 846         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 847         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 848                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 849                 enable = 0;
 850         }
 851
 852         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 853         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 854                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 855                 enable = 0;
 856         }
 857
 858         /* We also need the same setting for L/R and only one path */
 859         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 860         switch (reg) {
 861         case WM8994_AIF2DACL_TO_DAC1L:
 862                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 863                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 864                 break;
 865         case WM8994_AIF1DAC2L_TO_DAC1L:
 866                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 867                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 868                 break;
 869         case WM8994_AIF1DAC1L_TO_DAC1L:
 870                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 871                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 872                 break;
 873         default:
 874                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 875                 enable = 0;
 876                 break;
 877         }
 878
 879         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 880         if (reg_r != reg) {
 881                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 882                 enable = 0;
 883         }
 884
 885         if (enable) {
 886                 dev_dbg(codec->dev, "Class W enabled\n");
 887                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 888                                     WM8994_CP_DYN_PWR |
 889                                     WM8994_CP_DYN_SRC_SEL_MASK,
 890                                     source | WM8994_CP_DYN_PWR);
 891                 wm8994->hubs.class_w = true;
 892
 893         } else {
 894                 dev_dbg(codec->dev, "Class W disabled\n");
 895                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 896                                     WM8994_CP_DYN_PWR, 0);
 897                 wm8994->hubs.class_w = false;
 898         }
 899 }
 900
 901 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 902                           struct snd_kcontrol *kcontrol, int event)
 903 {
 904         struct snd_soc_codec *codec = w->codec;
 905         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 906
 907         switch (event) {
 908         case SND_SOC_DAPM_PRE_PMU:
 909 <<<<<<< HEAD
 910                 if (wm8994->aif1clk_enable)
 911                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 912                                             WM8994_AIF1CLK_ENA_MASK,
 913                                             WM8994_AIF1CLK_ENA);
 914                 if (wm8994->aif2clk_enable)
 915                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 916                                             WM8994_AIF2CLK_ENA_MASK,
 917                                             WM8994_AIF2CLK_ENA);
 918 =======
 919                 if (wm8994->aif1clk_enable) {
 920                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 921                                             WM8994_AIF1CLK_ENA_MASK,
 922                                             WM8994_AIF1CLK_ENA);
 923                         wm8994->aif1clk_enable = 0;
 924                 }
 925                 if (wm8994->aif2clk_enable) {
 926                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 927                                             WM8994_AIF2CLK_ENA_MASK,
 928                                             WM8994_AIF2CLK_ENA);
 929                         wm8994->aif2clk_enable = 0;
 930                 }
 931 >>>>>>> d10902812c9cd5583130a4ebb9ad19c60b68149d
 932                 break;
 933         }
 934
 935         /* We may also have postponed startup of DSP, handle that. */
 936         wm8958_aif_ev(w, kcontrol, event);
 937
 938         return 0;
 939 }
 940
 941 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 942                            struct snd_kcontrol *kcontrol, int event)
 943 {
 944         struct snd_soc_codec *codec = w->codec;
 945         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 946
 947         switch (event) {
 948         case SND_SOC_DAPM_POST_PMD:
 949 <<<<<<< HEAD
 950                 if (wm8994->aif1clk_enable) {
 951                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 952                                             WM8994_AIF1CLK_ENA_MASK, 0);
 953                         wm8994->aif1clk_enable = 0;
 954                 }
 955                 if (wm8994->aif2clk_enable) {
 956                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 957                                             WM8994_AIF2CLK_ENA_MASK, 0);
 958                         wm8994->aif2clk_enable = 0;
 959 =======
 960                 if (wm8994->aif1clk_disable) {
 961                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 962                                             WM8994_AIF1CLK_ENA_MASK, 0);
 963                         wm8994->aif1clk_disable = 0;
 964                 }
 965                 if (wm8994->aif2clk_disable) {
 966                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 967                                             WM8994_AIF2CLK_ENA_MASK, 0);
 968                         wm8994->aif2clk_disable = 0;
 969 >>>>>>> d10902812c9cd5583130a4ebb9ad19c60b68149d
 970                 }
 971                 break;
 972         }
 973
 974         return 0;
 975 }
 976
 977 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 978                       struct snd_kcontrol *kcontrol, int event)
 979 {
 980         struct snd_soc_codec *codec = w->codec;
 981         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 982
 983         switch (event) {
 984         case SND_SOC_DAPM_PRE_PMU:
 985                 wm8994->aif1clk_enable = 1;
 986                 break;
 987 <<<<<<< HEAD
 988 =======
 989         case SND_SOC_DAPM_POST_PMD:
 990                 wm8994->aif1clk_disable = 1;
 991                 break;
 992 >>>>>>> d10902812c9cd5583130a4ebb9ad19c60b68149d
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 999                       struct snd_kcontrol *kcontrol, int event)
1000 {
1001         struct snd_soc_codec *codec = w->codec;
1002         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1003
1004         switch (event) {
1005         case SND_SOC_DAPM_PRE_PMU:
1006                 wm8994->aif2clk_enable = 1;
1007                 break;
1008 <<<<<<< HEAD
1009 =======
1010         case SND_SOC_DAPM_POST_PMD:
1011                 wm8994->aif2clk_disable = 1;
1012                 break;
1013 >>>>>>> d10902812c9cd5583130a4ebb9ad19c60b68149d
1014         }
1015
1016         return 0;
1017 }
1018
1019 <<<<<<< HEAD
1020 =======
1021 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1022                       struct snd_kcontrol *kcontrol, int event)
1023 {
1024         late_enable_ev(w, kcontrol, event);
1025         return 0;
1026 }
1027
1028 <<<<<<< HEAD
1029 >>>>>>> d10902812c9cd5583130a4ebb9ad19c60b68149d
1030 =======
1031 static int micbias_ev(struct snd_soc_dapm_widget *w,
1032                       struct snd_kcontrol *kcontrol, int event)
1033 {
1034         late_enable_ev(w, kcontrol, event);
1035         return 0;
1036 }
1037
1038 >>>>>>> c7f46b7aa4ae5cbef32eb5e016512a14f936affa
1039 static int dac_ev(struct snd_soc_dapm_widget *w,
1040                   struct snd_kcontrol *kcontrol, int event)
1041 {
1042         struct snd_soc_codec *codec = w->codec;
1043         unsigned int mask = 1 << w->shift;
1044
1045         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1046                             mask, mask);
1047         return 0;
1048 }
1049
1050 static const char *hp_mux_text[] = {
1051         "Mixer",
1052         "DAC",
1053 };
1054
1055 #define WM8994_HP_ENUM(xname, xenum) \
1056 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1057         .info = snd_soc_info_enum_double, \
1058         .get = snd_soc_dapm_get_enum_double, \
1059         .put = wm8994_put_hp_enum, \
1060         .private_value = (unsigned long)&xenum }
1061
1062 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1063                               struct snd_ctl_elem_value *ucontrol)
1064 {
1065         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1066         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1067         struct snd_soc_codec *codec = w->codec;
1068         int ret;
1069
1070         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1071
1072         wm8994_update_class_w(codec);
1073
1074         return ret;
1075 }
1076
1077 static const struct soc_enum hpl_enum =
1078         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1079
1080 static const struct snd_kcontrol_new hpl_mux =
1081         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1082
1083 static const struct soc_enum hpr_enum =
1084         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1085
1086 static const struct snd_kcontrol_new hpr_mux =
1087         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1088
1089 static const char *adc_mux_text[] = {
1090         "ADC",
1091         "DMIC",
1092 };
1093
1094 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1095
1096 static const struct snd_kcontrol_new adcl_mux =
1097         SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1098
1099 static const struct snd_kcontrol_new adcr_mux =
1100         SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1101
1102 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1103 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1104 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1105 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1106 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1107 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1108 };
1109
1110 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1111 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1112 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1113 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1114 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1115 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1116 };
1117
1118 /* Debugging; dump chip status after DAPM transitions */
1119 static int post_ev(struct snd_soc_dapm_widget *w,
1120             struct snd_kcontrol *kcontrol, int event)
1121 {
1122         struct snd_soc_codec *codec = w->codec;
1123         dev_dbg(codec->dev, "SRC status: %x\n",
1124                 snd_soc_read(codec,
1125                              WM8994_RATE_STATUS));
1126         return 0;
1127 }
1128
1129 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1130 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1131                 1, 1, 0),
1132 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1133                 0, 1, 0),
1134 };
1135
1136 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1137 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1138                 1, 1, 0),
1139 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1140                 0, 1, 0),
1141 };
1142
1143 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1144 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1145                 1, 1, 0),
1146 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1147                 0, 1, 0),
1148 };
1149
1150 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1151 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1152                 1, 1, 0),
1153 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1154                 0, 1, 0),
1155 };
1156
1157 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1158 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1159                 5, 1, 0),
1160 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1161                 4, 1, 0),
1162 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1163                 2, 1, 0),
1164 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1165                 1, 1, 0),
1166 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1167                 0, 1, 0),
1168 };
1169
1170 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1171 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1172                 5, 1, 0),
1173 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1174                 4, 1, 0),
1175 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1176                 2, 1, 0),
1177 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1178                 1, 1, 0),
1179 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1180                 0, 1, 0),
1181 };
1182
1183 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1184 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1185                 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1186         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1187         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1188
1189 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1190                               struct snd_ctl_elem_value *ucontrol)
1191 {
1192         struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
1193         int ret;
1194
1195         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1196
1197         wm8994_update_class_w(codec);
1198
1199         return ret;
1200 }
1201
1202 static const struct snd_kcontrol_new dac1l_mix[] = {
1203 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1204                       5, 1, 0),
1205 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1206                       4, 1, 0),
1207 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1208                       2, 1, 0),
1209 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1210                       1, 1, 0),
1211 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1212                       0, 1, 0),
1213 };
1214
1215 static const struct snd_kcontrol_new dac1r_mix[] = {
1216 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1217                       5, 1, 0),
1218 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1219                       4, 1, 0),
1220 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1221                       2, 1, 0),
1222 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1223                       1, 1, 0),
1224 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1225                       0, 1, 0),
1226 };
1227
1228 static const char *sidetone_text[] = {
1229         "ADC/DMIC1", "DMIC2",
1230 };
1231
1232 static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1233                             WM8994_SIDETONE, 0, sidetone_text);
1234
1235 static const struct snd_kcontrol_new sidetone1_mux =
1236         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1237
1238 static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1239                             WM8994_SIDETONE, 1, sidetone_text);
1240
1241 static const struct snd_kcontrol_new sidetone2_mux =
1242         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1243
1244 static const char *aif1dac_text[] = {
1245         "AIF1DACDAT", "AIF3DACDAT",
1246 };
1247
1248 static const char *loopback_text[] = {
1249         "None", "ADCDAT",
1250 };
1251
1252 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1253                             WM8994_AIF1_CONTROL_2,
1254                             WM8994_AIF1_LOOPBACK_SHIFT,
1255                             loopback_text);
1256
1257 static const struct snd_kcontrol_new aif1_loopback =
1258         SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1259
1260 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1261                             WM8994_AIF2_CONTROL_2,
1262                             WM8994_AIF2_LOOPBACK_SHIFT,
1263                             loopback_text);
1264
1265 static const struct snd_kcontrol_new aif2_loopback =
1266         SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1267
1268 static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1269                             WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1270
1271 static const struct snd_kcontrol_new aif1dac_mux =
1272         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1273
1274 static const char *aif2dac_text[] = {
1275         "AIF2DACDAT", "AIF3DACDAT",
1276 };
1277
1278 static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1279                             WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1280
1281 static const struct snd_kcontrol_new aif2dac_mux =
1282         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1283
1284 static const char *aif2adc_text[] = {
1285         "AIF2ADCDAT", "AIF3DACDAT",
1286 };
1287
1288 static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1289                             WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1290
1291 static const struct snd_kcontrol_new aif2adc_mux =
1292         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1293
1294 static const char *aif3adc_text[] = {
1295         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1296 };
1297
1298 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1299                             WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1300
1301 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1302         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1303
1304 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1305                             WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1306
1307 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1308         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1309
1310 static const char *mono_pcm_out_text[] = {
1311         "None", "AIF2ADCL", "AIF2ADCR",
1312 };
1313
1314 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1315                             WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1316
1317 static const struct snd_kcontrol_new mono_pcm_out_mux =
1318         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1319
1320 static const char *aif2dac_src_text[] = {
1321         "AIF2", "AIF3",
1322 };
1323
1324 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1325 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1326                             WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1327
1328 static const struct snd_kcontrol_new aif2dacl_src_mux =
1329         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1330
1331 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1332                             WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1333
1334 static const struct snd_kcontrol_new aif2dacr_src_mux =
1335         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1336
1337 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1338 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1339         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1340 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1341         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1342
1343 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1344         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1345 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1346         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1347 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1348         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1349 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1350         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1351 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1352         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1353
1354 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1355                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1356                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1357 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1358                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1359                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1360 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1361                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1362 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1363                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1364
1365 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1366 };
1367
1368 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1369 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1370                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1371                     SND_SOC_DAPM_PRE_PMD),
1372 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1373                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1374                     SND_SOC_DAPM_PRE_PMD),
1375 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1376 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1377                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1378 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1379                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1380 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1381 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1382 };
1383
1384 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1385 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1386         dac_ev, SND_SOC_DAPM_PRE_PMU),
1387 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1388         dac_ev, SND_SOC_DAPM_PRE_PMU),
1389 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1390         dac_ev, SND_SOC_DAPM_PRE_PMU),
1391 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1392         dac_ev, SND_SOC_DAPM_PRE_PMU),
1393 };
1394
1395 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1396 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1397 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1398 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1399 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1400 };
1401
1402 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1403 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1404 };
1405
1406 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1407 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1408                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1409 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1410                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1411 };
1412
1413 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1414 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1415 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1416 };
1417
1418 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1419 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1420 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1421 SND_SOC_DAPM_INPUT("Clock"),
1422
1423 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1424                       SND_SOC_DAPM_PRE_PMU),
1425 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1426                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1427
1428 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1429                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1430                     SND_SOC_DAPM_PRE_PMD),
1431
1432 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1433 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1434 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1435
1436 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1437                      0, SND_SOC_NOPM, 9, 0),
1438 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1439                      0, SND_SOC_NOPM, 8, 0),
1440 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1441                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1442                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1443 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1444                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1445                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1446
1447 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1448                      0, SND_SOC_NOPM, 11, 0),
1449 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1450                      0, SND_SOC_NOPM, 10, 0),
1451 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1452                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1453                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1454 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1455                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1456                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1457
1458 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1459                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1460 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1461                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1462
1463 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1464                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1465 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1466                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1467
1468 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1469                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1470 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1471                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1472
1473 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1474 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1475
1476 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1477                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1478 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1479                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1480
1481 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1482                      SND_SOC_NOPM, 13, 0),
1483 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1484                      SND_SOC_NOPM, 12, 0),
1485 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1486                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1487                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1488 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1489                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1490                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1491
1492 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1493 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1494 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1495 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1496
1497 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1498 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1499 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1500
1501 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1502 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1503
1504 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1505
1506 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1507 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1508 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1509 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1510
1511 /* Power is done with the muxes since the ADC power also controls the
1512  * downsampling chain, the chip will automatically manage the analogue
1513  * specific portions.
1514  */
1515 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1516 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1517
1518 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1519 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1520
1521 SND_SOC_DAPM_POST("Debug log", post_ev),
1522 };
1523
1524 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1525 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1526 };
1527
1528 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1529 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1530 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1531 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1532 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1533 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1534 };
1535
1536 static const struct snd_soc_dapm_route intercon[] = {
1537         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1538         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1539
1540         { "DSP1CLK", NULL, "CLK_SYS" },
1541         { "DSP2CLK", NULL, "CLK_SYS" },
1542         { "DSPINTCLK", NULL, "CLK_SYS" },
1543
1544         { "AIF1ADC1L", NULL, "AIF1CLK" },
1545         { "AIF1ADC1L", NULL, "DSP1CLK" },
1546         { "AIF1ADC1R", NULL, "AIF1CLK" },
1547         { "AIF1ADC1R", NULL, "DSP1CLK" },
1548         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1549
1550         { "AIF1DAC1L", NULL, "AIF1CLK" },
1551         { "AIF1DAC1L", NULL, "DSP1CLK" },
1552         { "AIF1DAC1R", NULL, "AIF1CLK" },
1553         { "AIF1DAC1R", NULL, "DSP1CLK" },
1554         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1555
1556         { "AIF1ADC2L", NULL, "AIF1CLK" },
1557         { "AIF1ADC2L", NULL, "DSP1CLK" },
1558         { "AIF1ADC2R", NULL, "AIF1CLK" },
1559         { "AIF1ADC2R", NULL, "DSP1CLK" },
1560         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1561
1562         { "AIF1DAC2L", NULL, "AIF1CLK" },
1563         { "AIF1DAC2L", NULL, "DSP1CLK" },
1564         { "AIF1DAC2R", NULL, "AIF1CLK" },
1565         { "AIF1DAC2R", NULL, "DSP1CLK" },
1566         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1567
1568         { "AIF2ADCL", NULL, "AIF2CLK" },
1569         { "AIF2ADCL", NULL, "DSP2CLK" },
1570         { "AIF2ADCR", NULL, "AIF2CLK" },
1571         { "AIF2ADCR", NULL, "DSP2CLK" },
1572         { "AIF2ADCR", NULL, "DSPINTCLK" },
1573
1574         { "AIF2DACL", NULL, "AIF2CLK" },
1575         { "AIF2DACL", NULL, "DSP2CLK" },
1576         { "AIF2DACR", NULL, "AIF2CLK" },
1577         { "AIF2DACR", NULL, "DSP2CLK" },
1578         { "AIF2DACR", NULL, "DSPINTCLK" },
1579
1580         { "DMIC1L", NULL, "DMIC1DAT" },
1581         { "DMIC1L", NULL, "CLK_SYS" },
1582         { "DMIC1R", NULL, "DMIC1DAT" },
1583         { "DMIC1R", NULL, "CLK_SYS" },
1584         { "DMIC2L", NULL, "DMIC2DAT" },
1585         { "DMIC2L", NULL, "CLK_SYS" },
1586         { "DMIC2R", NULL, "DMIC2DAT" },
1587         { "DMIC2R", NULL, "CLK_SYS" },
1588
1589         { "ADCL", NULL, "AIF1CLK" },
1590         { "ADCL", NULL, "DSP1CLK" },
1591         { "ADCL", NULL, "DSPINTCLK" },
1592
1593         { "ADCR", NULL, "AIF1CLK" },
1594         { "ADCR", NULL, "DSP1CLK" },
1595         { "ADCR", NULL, "DSPINTCLK" },
1596
1597         { "ADCL Mux", "ADC", "ADCL" },
1598         { "ADCL Mux", "DMIC", "DMIC1L" },
1599         { "ADCR Mux", "ADC", "ADCR" },
1600         { "ADCR Mux", "DMIC", "DMIC1R" },
1601
1602         { "DAC1L", NULL, "AIF1CLK" },
1603         { "DAC1L", NULL, "DSP1CLK" },
1604         { "DAC1L", NULL, "DSPINTCLK" },
1605
1606         { "DAC1R", NULL, "AIF1CLK" },
1607         { "DAC1R", NULL, "DSP1CLK" },
1608         { "DAC1R", NULL, "DSPINTCLK" },
1609
1610         { "DAC2L", NULL, "AIF2CLK" },
1611         { "DAC2L", NULL, "DSP2CLK" },
1612         { "DAC2L", NULL, "DSPINTCLK" },
1613
1614         { "DAC2R", NULL, "AIF2DACR" },
1615         { "DAC2R", NULL, "AIF2CLK" },
1616         { "DAC2R", NULL, "DSP2CLK" },
1617         { "DAC2R", NULL, "DSPINTCLK" },
1618
1619         { "TOCLK", NULL, "CLK_SYS" },
1620
1621         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1622         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1623         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1624
1625         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1626         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1627         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1628
1629         /* AIF1 outputs */
1630         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1631         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1632         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1633
1634         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1635         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1636         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1637
1638         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1639         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1640         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1641
1642         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1643         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1644         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1645
1646         /* Pin level routing for AIF3 */
1647         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1648         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1649         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1650         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1651
1652         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1653         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1654         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1655         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1656         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1657         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1658         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1659
1660         /* DAC1 inputs */
1661         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1662         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1663         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1664         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1665         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1666
1667         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1668         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1669         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1670         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1671         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1672
1673         /* DAC2/AIF2 outputs  */
1674         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1675         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1676         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1677         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1678         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1679         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1680
1681         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1682         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1683         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1684         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1685         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1686         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1687
1688         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1689         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1690         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1691         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1692
1693         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1694
1695         /* AIF3 output */
1696         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1697         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1698         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1699         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1700         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1701         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1702         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1703         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1704
1705         /* Loopback */
1706         { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1707         { "AIF1 Loopback", "None", "AIF1DACDAT" },
1708         { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1709         { "AIF2 Loopback", "None", "AIF2DACDAT" },
1710
1711         /* Sidetone */
1712         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1713         { "Left Sidetone", "DMIC2", "DMIC2L" },
1714         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1715         { "Right Sidetone", "DMIC2", "DMIC2R" },
1716
1717         /* Output stages */
1718         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1719         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1720
1721         { "SPKL", "DAC1 Switch", "DAC1L" },
1722         { "SPKL", "DAC2 Switch", "DAC2L" },
1723
1724         { "SPKR", "DAC1 Switch", "DAC1R" },
1725         { "SPKR", "DAC2 Switch", "DAC2R" },
1726
1727         { "Left Headphone Mux", "DAC", "DAC1L" },
1728         { "Right Headphone Mux", "DAC", "DAC1R" },
1729 };
1730
1731 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1732         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1733         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1734         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1735         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1736         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1737         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1738         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1739         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1740 };
1741
1742 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1743         { "DAC1L", NULL, "DAC1L Mixer" },
1744         { "DAC1R", NULL, "DAC1R Mixer" },
1745         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1746         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1747 };
1748
1749 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1750         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1751         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1752         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1753         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1754         { "MICBIAS1", NULL, "CLK_SYS" },
1755         { "MICBIAS1", NULL, "MICBIAS Supply" },
1756         { "MICBIAS2", NULL, "CLK_SYS" },
1757         { "MICBIAS2", NULL, "MICBIAS Supply" },
1758 };
1759
1760 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1761         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1762         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1763         { "MICBIAS1", NULL, "VMID" },
1764         { "MICBIAS2", NULL, "VMID" },
1765 };
1766
1767 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1768         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1769         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1770
1771         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1772         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1773         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1774         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1775
1776         { "AIF3DACDAT", NULL, "AIF3" },
1777         { "AIF3ADCDAT", NULL, "AIF3" },
1778
1779         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1780         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1781
1782         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1783 };
1784
1785 /* The size in bits of the FLL divide multiplied by 10
1786  * to allow rounding later */
1787 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1788
1789 struct fll_div {
1790         u16 outdiv;
1791         u16 n;
1792         u16 k;
1793         u16 lambda;
1794         u16 clk_ref_div;
1795         u16 fll_fratio;
1796 };
1797
1798 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
1799                                  int freq_in, int freq_out)
1800 {
1801         u64 Kpart;
1802         unsigned int K, Ndiv, Nmod, gcd_fll;
1803
1804         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1805
1806         /* Scale the input frequency down to <= 13.5MHz */
1807         fll->clk_ref_div = 0;
1808         while (freq_in > 13500000) {
1809                 fll->clk_ref_div++;
1810                 freq_in /= 2;
1811
1812                 if (fll->clk_ref_div > 3)
1813                         return -EINVAL;
1814         }
1815         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1816
1817         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1818         fll->outdiv = 3;
1819         while (freq_out * (fll->outdiv + 1) < 90000000) {
1820                 fll->outdiv++;
1821                 if (fll->outdiv > 63)
1822                         return -EINVAL;
1823         }
1824         freq_out *= fll->outdiv + 1;
1825         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1826
1827         if (freq_in > 1000000) {
1828                 fll->fll_fratio = 0;
1829         } else if (freq_in > 256000) {
1830                 fll->fll_fratio = 1;
1831                 freq_in *= 2;
1832         } else if (freq_in > 128000) {
1833                 fll->fll_fratio = 2;
1834                 freq_in *= 4;
1835         } else if (freq_in > 64000) {
1836                 fll->fll_fratio = 3;
1837                 freq_in *= 8;
1838         } else {
1839                 fll->fll_fratio = 4;
1840                 freq_in *= 16;
1841         }
1842         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1843
1844         /* Now, calculate N.K */
1845         Ndiv = freq_out / freq_in;
1846
1847         fll->n = Ndiv;
1848         Nmod = freq_out % freq_in;
1849         pr_debug("Nmod=%d\n", Nmod);
1850
1851         switch (control->type) {
1852         case WM8994:
1853                 /* Calculate fractional part - scale up so we can round. */
1854                 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1855
1856                 do_div(Kpart, freq_in);
1857
1858                 K = Kpart & 0xFFFFFFFF;
1859
1860                 if ((K % 10) >= 5)
1861                         K += 5;
1862
1863                 /* Move down to proper range now rounding is done */
1864                 fll->k = K / 10;
1865                 fll->lambda = 0;
1866
1867                 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1868                 break;
1869
1870         default:
1871                 gcd_fll = gcd(freq_out, freq_in);
1872
1873                 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
1874                 fll->lambda = freq_in / gcd_fll;
1875
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1882                           unsigned int freq_in, unsigned int freq_out)
1883 {
1884         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1885         struct wm8994 *control = wm8994->wm8994;
1886         int reg_offset, ret;
1887         struct fll_div fll;
1888         u16 reg, clk1, aif_reg, aif_src;
1889         unsigned long timeout;
1890         bool was_enabled;
1891
1892         switch (id) {
1893         case WM8994_FLL1:
1894                 reg_offset = 0;
1895                 id = 0;
1896                 aif_src = 0x10;
1897                 break;
1898         case WM8994_FLL2:
1899                 reg_offset = 0x20;
1900                 id = 1;
1901                 aif_src = 0x18;
1902                 break;
1903         default:
1904                 return -EINVAL;
1905         }
1906
1907         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1908         was_enabled = reg & WM8994_FLL1_ENA;
1909
1910         switch (src) {
1911         case 0:
1912                 /* Allow no source specification when stopping */
1913                 if (freq_out)
1914                         return -EINVAL;
1915                 src = wm8994->fll[id].src;
1916                 break;
1917         case WM8994_FLL_SRC_MCLK1:
1918         case WM8994_FLL_SRC_MCLK2:
1919         case WM8994_FLL_SRC_LRCLK:
1920         case WM8994_FLL_SRC_BCLK:
1921                 break;
1922         case WM8994_FLL_SRC_INTERNAL:
1923                 freq_in = 12000000;
1924                 freq_out = 12000000;
1925                 break;
1926         default:
1927                 return -EINVAL;
1928         }
1929
1930         /* Are we changing anything? */
1931         if (wm8994->fll[id].src == src &&
1932             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1933                 return 0;
1934
1935         /* If we're stopping the FLL redo the old config - no
1936          * registers will actually be written but we avoid GCC flow
1937          * analysis bugs spewing warnings.
1938          */
1939         if (freq_out)
1940                 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
1941         else
1942                 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
1943                                             wm8994->fll[id].out);
1944         if (ret < 0)
1945                 return ret;
1946
1947         /* Make sure that we're not providing SYSCLK right now */
1948         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
1949         if (clk1 & WM8994_SYSCLK_SRC)
1950                 aif_reg = WM8994_AIF2_CLOCKING_1;
1951         else
1952                 aif_reg = WM8994_AIF1_CLOCKING_1;
1953         reg = snd_soc_read(codec, aif_reg);
1954
1955         if ((reg & WM8994_AIF1CLK_ENA) &&
1956             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
1957                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
1958                         id + 1);
1959                 return -EBUSY;
1960         }
1961
1962         /* We always need to disable the FLL while reconfiguring */
1963         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1964                             WM8994_FLL1_ENA, 0);
1965
1966         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
1967             freq_in == freq_out && freq_out) {
1968                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
1969                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1970                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
1971                 goto out;
1972         }
1973
1974         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1975                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1976         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1977                             WM8994_FLL1_OUTDIV_MASK |
1978                             WM8994_FLL1_FRATIO_MASK, reg);
1979
1980         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1981                             WM8994_FLL1_K_MASK, fll.k);
1982
1983         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1984                             WM8994_FLL1_N_MASK,
1985                             fll.n << WM8994_FLL1_N_SHIFT);
1986
1987         if (fll.lambda) {
1988                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
1989                                     WM8958_FLL1_LAMBDA_MASK,
1990                                     fll.lambda);
1991                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
1992                                     WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
1993         } else {
1994                 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
1995                                     WM8958_FLL1_EFS_ENA, 0);
1996         }
1997
1998         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1999                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2000                             WM8994_FLL1_REFCLK_DIV_MASK |
2001                             WM8994_FLL1_REFCLK_SRC_MASK,
2002                             ((src == WM8994_FLL_SRC_INTERNAL)
2003                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2004                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2005                             (src - 1));
2006
2007         /* Clear any pending completion from a previous failure */
2008         try_wait_for_completion(&wm8994->fll_locked[id]);
2009
2010         /* Enable (with fractional mode if required) */
2011         if (freq_out) {
2012                 /* Enable VMID if we need it */
2013                 if (!was_enabled) {
2014                         active_reference(codec);
2015
2016                         switch (control->type) {
2017                         case WM8994:
2018                                 vmid_reference(codec);
2019                                 break;
2020                         case WM8958:
2021                                 if (control->revision < 1)
2022                                         vmid_reference(codec);
2023                                 break;
2024                         default:
2025                                 break;
2026                         }
2027                 }
2028
2029                 reg = WM8994_FLL1_ENA;
2030
2031                 if (fll.k)
2032                         reg |= WM8994_FLL1_FRAC;
2033                 if (src == WM8994_FLL_SRC_INTERNAL)
2034                         reg |= WM8994_FLL1_OSC_ENA;
2035
2036                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2037                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2038                                     WM8994_FLL1_FRAC, reg);
2039
2040                 if (wm8994->fll_locked_irq) {
2041                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2042                                                               msecs_to_jiffies(10));
2043                         if (timeout == 0)
2044                                 dev_warn(codec->dev,
2045                                          "Timed out waiting for FLL lock\n");
2046                 } else {
2047                         msleep(5);
2048                 }
2049         } else {
2050                 if (was_enabled) {
2051                         switch (control->type) {
2052                         case WM8994:
2053                                 vmid_dereference(codec);
2054                                 break;
2055                         case WM8958:
2056                                 if (control->revision < 1)
2057                                         vmid_dereference(codec);
2058                                 break;
2059                         default:
2060                                 break;
2061                         }
2062
2063                         active_dereference(codec);
2064                 }
2065         }
2066
2067 out:
2068         wm8994->fll[id].in = freq_in;
2069         wm8994->fll[id].out = freq_out;
2070         wm8994->fll[id].src = src;
2071
2072         configure_clock(codec);
2073
2074         /*
2075          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2076          * for detection.
2077          */
2078         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2079                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2080
2081                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2082                         & WM8994_AIF1CLK_RATE_MASK;
2083                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2084                         & WM8994_AIF1CLK_RATE_MASK;
2085
2086                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2087                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2088                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2089                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2090         } else if (wm8994->aifdiv[0]) {
2091                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2092                                     WM8994_AIF1CLK_RATE_MASK,
2093                                     wm8994->aifdiv[0]);
2094                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2095                                     WM8994_AIF2CLK_RATE_MASK,
2096                                     wm8994->aifdiv[1]);
2097
2098                 wm8994->aifdiv[0] = 0;
2099                 wm8994->aifdiv[1] = 0;
2100         }
2101
2102         return 0;
2103 }
2104
2105 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2106 {
2107         struct completion *completion = data;
2108
2109         complete(completion);
2110
2111         return IRQ_HANDLED;
2112 }
2113
2114 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2115
2116 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2117                           unsigned int freq_in, unsigned int freq_out)
2118 {
2119         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2120 }
2121
2122 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2123                 int clk_id, unsigned int freq, int dir)
2124 {
2125         struct snd_soc_codec *codec = dai->codec;
2126         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2127         int i;
2128
2129         switch (dai->id) {
2130         case 1:
2131         case 2:
2132                 break;
2133
2134         default:
2135                 /* AIF3 shares clocking with AIF1/2 */
2136                 return -EINVAL;
2137         }
2138
2139         switch (clk_id) {
2140         case WM8994_SYSCLK_MCLK1:
2141                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2142                 wm8994->mclk[0] = freq;
2143                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2144                         dai->id, freq);
2145                 break;
2146
2147         case WM8994_SYSCLK_MCLK2:
2148                 /* TODO: Set GPIO AF */
2149                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2150                 wm8994->mclk[1] = freq;
2151                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2152                         dai->id, freq);
2153                 break;
2154
2155         case WM8994_SYSCLK_FLL1:
2156                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2157                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2158                 break;
2159
2160         case WM8994_SYSCLK_FLL2:
2161                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2162                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2163                 break;
2164
2165         case WM8994_SYSCLK_OPCLK:
2166                 /* Special case - a division (times 10) is given and
2167                  * no effect on main clocking.
2168                  */
2169                 if (freq) {
2170                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2171                                 if (opclk_divs[i] == freq)
2172                                         break;
2173                         if (i == ARRAY_SIZE(opclk_divs))
2174                                 return -EINVAL;
2175                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2176                                             WM8994_OPCLK_DIV_MASK, i);
2177                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2178                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2179                 } else {
2180                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2181                                             WM8994_OPCLK_ENA, 0);
2182                 }
2183
2184         default:
2185                 return -EINVAL;
2186         }
2187
2188         configure_clock(codec);
2189
2190         /*
2191          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2192          * for detection.
2193          */
2194         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2195                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2196
2197                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2198                         & WM8994_AIF1CLK_RATE_MASK;
2199                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2200                         & WM8994_AIF1CLK_RATE_MASK;
2201
2202                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2203                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2204                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2205                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2206         } else if (wm8994->aifdiv[0]) {
2207                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2208                                     WM8994_AIF1CLK_RATE_MASK,
2209                                     wm8994->aifdiv[0]);
2210                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2211                                     WM8994_AIF2CLK_RATE_MASK,
2212                                     wm8994->aifdiv[1]);
2213
2214                 wm8994->aifdiv[0] = 0;
2215                 wm8994->aifdiv[1] = 0;
2216         }
2217
2218         return 0;
2219 }
2220
2221 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2222                                  enum snd_soc_bias_level level)
2223 {
2224         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2225         struct wm8994 *control = wm8994->wm8994;
2226
2227         wm_hubs_set_bias_level(codec, level);
2228
2229         switch (level) {
2230         case SND_SOC_BIAS_ON:
2231                 break;
2232
2233         case SND_SOC_BIAS_PREPARE:
2234                 /* MICBIAS into regulating mode */
2235                 switch (control->type) {
2236                 case WM8958:
2237                 case WM1811:
2238                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2239                                             WM8958_MICB1_MODE, 0);
2240                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2241                                             WM8958_MICB2_MODE, 0);
2242                         break;
2243                 default:
2244                         break;
2245                 }
2246
2247                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2248                         active_reference(codec);
2249                 break;
2250
2251         case SND_SOC_BIAS_STANDBY:
2252                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2253                         switch (control->type) {
2254                         case WM8958:
2255                                 if (control->revision == 0) {
2256                                         /* Optimise performance for rev A */
2257                                         snd_soc_update_bits(codec,
2258                                                             WM8958_CHARGE_PUMP_2,
2259                                                             WM8958_CP_DISCH,
2260                                                             WM8958_CP_DISCH);
2261                                 }
2262                                 break;
2263
2264                         default:
2265                                 break;
2266                         }
2267
2268                         /* Discharge LINEOUT1 & 2 */
2269                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2270                                             WM8994_LINEOUT1_DISCH |
2271                                             WM8994_LINEOUT2_DISCH,
2272                                             WM8994_LINEOUT1_DISCH |
2273                                             WM8994_LINEOUT2_DISCH);
2274                 }
2275
2276                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2277                         active_dereference(codec);
2278
2279                 /* MICBIAS into bypass mode on newer devices */
2280                 switch (control->type) {
2281                 case WM8958:
2282                 case WM1811:
2283                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2284                                             WM8958_MICB1_MODE,
2285                                             WM8958_MICB1_MODE);
2286                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2287                                             WM8958_MICB2_MODE,
2288                                             WM8958_MICB2_MODE);
2289                         break;
2290                 default:
2291                         break;
2292                 }
2293                 break;
2294
2295         case SND_SOC_BIAS_OFF:
2296                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2297                         wm8994->cur_fw = NULL;
2298                 break;
2299         }
2300
2301         codec->dapm.bias_level = level;
2302
2303         return 0;
2304 }
2305
2306 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2307 {
2308         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2309         struct snd_soc_dapm_context *dapm = &codec->dapm;
2310
2311         switch (mode) {
2312         case WM8994_VMID_NORMAL:
2313                 snd_soc_dapm_mutex_lock(dapm);
2314
2315                 if (wm8994->hubs.lineout1_se) {
2316                         snd_soc_dapm_disable_pin_unlocked(dapm,
2317                                                           "LINEOUT1N Driver");
2318                         snd_soc_dapm_disable_pin_unlocked(dapm,
2319                                                           "LINEOUT1P Driver");
2320                 }
2321                 if (wm8994->hubs.lineout2_se) {
2322                         snd_soc_dapm_disable_pin_unlocked(dapm,
2323                                                           "LINEOUT2N Driver");
2324                         snd_soc_dapm_disable_pin_unlocked(dapm,
2325                                                           "LINEOUT2P Driver");
2326                 }
2327
2328                 /* Do the sync with the old mode to allow it to clean up */
2329                 snd_soc_dapm_sync_unlocked(dapm);
2330                 wm8994->vmid_mode = mode;
2331
2332                 snd_soc_dapm_mutex_unlock(dapm);
2333                 break;
2334
2335         case WM8994_VMID_FORCE:
2336                 snd_soc_dapm_mutex_lock(dapm);
2337
2338                 if (wm8994->hubs.lineout1_se) {
2339                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2340                                                                "LINEOUT1N Driver");
2341                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2342                                                                "LINEOUT1P Driver");
2343                 }
2344                 if (wm8994->hubs.lineout2_se) {
2345                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2346                                                                "LINEOUT2N Driver");
2347                         snd_soc_dapm_force_enable_pin_unlocked(dapm,
2348                                                                "LINEOUT2P Driver");
2349                 }
2350
2351                 wm8994->vmid_mode = mode;
2352                 snd_soc_dapm_sync_unlocked(dapm);
2353
2354                 snd_soc_dapm_mutex_unlock(dapm);
2355                 break;
2356
2357         default:
2358                 return -EINVAL;
2359         }
2360
2361         return 0;
2362 }
2363
2364 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2365 {
2366         struct snd_soc_codec *codec = dai->codec;
2367         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2368         struct wm8994 *control = wm8994->wm8994;
2369         int ms_reg;
2370         int aif1_reg;
2371         int dac_reg;
2372         int adc_reg;
2373         int ms = 0;
2374         int aif1 = 0;
2375         int lrclk = 0;
2376
2377         switch (dai->id) {
2378         case 1:
2379                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2380                 aif1_reg = WM8994_AIF1_CONTROL_1;
2381                 dac_reg = WM8994_AIF1DAC_LRCLK;
2382                 adc_reg = WM8994_AIF1ADC_LRCLK;
2383                 break;
2384         case 2:
2385                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2386                 aif1_reg = WM8994_AIF2_CONTROL_1;
2387                 dac_reg = WM8994_AIF1DAC_LRCLK;
2388                 adc_reg = WM8994_AIF1ADC_LRCLK;
2389                 break;
2390         default:
2391                 return -EINVAL;
2392         }
2393
2394         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2395         case SND_SOC_DAIFMT_CBS_CFS:
2396                 break;
2397         case SND_SOC_DAIFMT_CBM_CFM:
2398                 ms = WM8994_AIF1_MSTR;
2399                 break;
2400         default:
2401                 return -EINVAL;
2402         }
2403
2404         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2405         case SND_SOC_DAIFMT_DSP_B:
2406                 aif1 |= WM8994_AIF1_LRCLK_INV;
2407                 lrclk |= WM8958_AIF1_LRCLK_INV;
2408         case SND_SOC_DAIFMT_DSP_A:
2409                 aif1 |= 0x18;
2410                 break;
2411         case SND_SOC_DAIFMT_I2S:
2412                 aif1 |= 0x10;
2413                 break;
2414         case SND_SOC_DAIFMT_RIGHT_J:
2415                 break;
2416         case SND_SOC_DAIFMT_LEFT_J:
2417                 aif1 |= 0x8;
2418                 break;
2419         default:
2420                 return -EINVAL;
2421         }
2422
2423         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2424         case SND_SOC_DAIFMT_DSP_A:
2425         case SND_SOC_DAIFMT_DSP_B:
2426                 /* frame inversion not valid for DSP modes */
2427                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2428                 case SND_SOC_DAIFMT_NB_NF:
2429                         break;
2430                 case SND_SOC_DAIFMT_IB_NF:
2431                         aif1 |= WM8994_AIF1_BCLK_INV;
2432                         break;
2433                 default:
2434                         return -EINVAL;
2435                 }
2436                 break;
2437
2438         case SND_SOC_DAIFMT_I2S:
2439         case SND_SOC_DAIFMT_RIGHT_J:
2440         case SND_SOC_DAIFMT_LEFT_J:
2441                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2442                 case SND_SOC_DAIFMT_NB_NF:
2443                         break;
2444                 case SND_SOC_DAIFMT_IB_IF:
2445                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2446                         lrclk |= WM8958_AIF1_LRCLK_INV;
2447                         break;
2448                 case SND_SOC_DAIFMT_IB_NF:
2449                         aif1 |= WM8994_AIF1_BCLK_INV;
2450                         break;
2451                 case SND_SOC_DAIFMT_NB_IF:
2452                         aif1 |= WM8994_AIF1_LRCLK_INV;
2453                         lrclk |= WM8958_AIF1_LRCLK_INV;
2454                         break;
2455                 default:
2456                         return -EINVAL;
2457                 }
2458                 break;
2459         default:
2460                 return -EINVAL;
2461         }
2462
2463         /* The AIF2 format configuration needs to be mirrored to AIF3
2464          * on WM8958 if it's in use so just do it all the time. */
2465         switch (control->type) {
2466         case WM1811:
2467         case WM8958:
2468                 if (dai->id == 2)
2469                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2470                                             WM8994_AIF1_LRCLK_INV |
2471                                             WM8958_AIF3_FMT_MASK, aif1);
2472                 break;
2473
2474         default:
2475                 break;
2476         }
2477
2478         snd_soc_update_bits(codec, aif1_reg,
2479                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2480                             WM8994_AIF1_FMT_MASK,
2481                             aif1);
2482         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2483                             ms);
2484         snd_soc_update_bits(codec, dac_reg,
2485                             WM8958_AIF1_LRCLK_INV, lrclk);
2486         snd_soc_update_bits(codec, adc_reg,
2487                             WM8958_AIF1_LRCLK_INV, lrclk);
2488
2489         return 0;
2490 }
2491
2492 static struct {
2493         int val, rate;
2494 } srs[] = {
2495         { 0,   8000 },
2496         { 1,  11025 },
2497         { 2,  12000 },
2498         { 3,  16000 },
2499         { 4,  22050 },
2500         { 5,  24000 },
2501         { 6,  32000 },
2502         { 7,  44100 },
2503         { 8,  48000 },
2504         { 9,  88200 },
2505         { 10, 96000 },
2506 };
2507
2508 static int fs_ratios[] = {
2509         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2510 };
2511
2512 static int bclk_divs[] = {
2513         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2514         640, 880, 960, 1280, 1760, 1920
2515 };
2516
2517 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2518                             struct snd_pcm_hw_params *params,
2519                             struct snd_soc_dai *dai)
2520 {
2521         struct snd_soc_codec *codec = dai->codec;
2522         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2523         struct wm8994 *control = wm8994->wm8994;
2524         struct wm8994_pdata *pdata = &control->pdata;
2525         int aif1_reg;
2526         int aif2_reg;
2527         int bclk_reg;
2528         int lrclk_reg;
2529         int rate_reg;
2530         int aif1 = 0;
2531         int aif2 = 0;
2532         int bclk = 0;
2533         int lrclk = 0;
2534         int rate_val = 0;
2535         int id = dai->id - 1;
2536
2537         int i, cur_val, best_val, bclk_rate, best;
2538
2539         switch (dai->id) {
2540         case 1:
2541                 aif1_reg = WM8994_AIF1_CONTROL_1;
2542                 aif2_reg = WM8994_AIF1_CONTROL_2;
2543                 bclk_reg = WM8994_AIF1_BCLK;
2544                 rate_reg = WM8994_AIF1_RATE;
2545                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2546                     wm8994->lrclk_shared[0]) {
2547                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2548                 } else {
2549                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2550                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2551                 }
2552                 break;
2553         case 2:
2554                 aif1_reg = WM8994_AIF2_CONTROL_1;
2555                 aif2_reg = WM8994_AIF2_CONTROL_2;
2556                 bclk_reg = WM8994_AIF2_BCLK;
2557                 rate_reg = WM8994_AIF2_RATE;
2558                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2559                     wm8994->lrclk_shared[1]) {
2560                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2561                 } else {
2562                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2563                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2564                 }
2565                 break;
2566         default:
2567                 return -EINVAL;
2568         }
2569
2570         bclk_rate = params_rate(params);
2571         switch (params_width(params)) {
2572         case 16:
2573                 bclk_rate *= 16;
2574                 break;
2575         case 20:
2576                 bclk_rate *= 20;
2577                 aif1 |= 0x20;
2578                 break;
2579         case 24:
2580                 bclk_rate *= 24;
2581                 aif1 |= 0x40;
2582                 break;
2583         case 32:
2584                 bclk_rate *= 32;
2585                 aif1 |= 0x60;
2586                 break;
2587         default:
2588                 return -EINVAL;
2589         }
2590
2591         wm8994->channels[id] = params_channels(params);
2592         if (pdata->max_channels_clocked[id] &&
2593             wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2594                 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2595                         pdata->max_channels_clocked[id], wm8994->channels[id]);
2596                 wm8994->channels[id] = pdata->max_channels_clocked[id];
2597         }
2598
2599         switch (wm8994->channels[id]) {
2600         case 1:
2601         case 2:
2602                 bclk_rate *= 2;
2603                 break;
2604         default:
2605                 bclk_rate *= 4;
2606                 break;
2607         }
2608
2609         /* Try to find an appropriate sample rate; look for an exact match. */
2610         for (i = 0; i < ARRAY_SIZE(srs); i++)
2611                 if (srs[i].rate == params_rate(params))
2612                         break;
2613         if (i == ARRAY_SIZE(srs))
2614                 return -EINVAL;
2615         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2616
2617         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2618         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2619                 dai->id, wm8994->aifclk[id], bclk_rate);
2620
2621         if (wm8994->channels[id] == 1 &&
2622             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2623                 aif2 |= WM8994_AIF1_MONO;
2624
2625         if (wm8994->aifclk[id] == 0) {
2626                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2627                 return -EINVAL;
2628         }
2629
2630         /* AIFCLK/fs ratio; look for a close match in either direction */
2631         best = 0;
2632         best_val = abs((fs_ratios[0] * params_rate(params))
2633                        - wm8994->aifclk[id]);
2634         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2635                 cur_val = abs((fs_ratios[i] * params_rate(params))
2636                               - wm8994->aifclk[id]);
2637                 if (cur_val >= best_val)
2638                         continue;
2639                 best = i;
2640                 best_val = cur_val;
2641         }
2642         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2643                 dai->id, fs_ratios[best]);
2644         rate_val |= best;
2645
2646         /* We may not get quite the right frequency if using
2647          * approximate clocks so look for the closest match that is
2648          * higher than the target (we need to ensure that there enough
2649          * BCLKs to clock out the samples).
2650          */
2651         best = 0;
2652         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2653                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2654                 if (cur_val < 0) /* BCLK table is sorted */
2655                         break;
2656                 best = i;
2657         }
2658         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2659         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2660                 bclk_divs[best], bclk_rate);
2661         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2662
2663         lrclk = bclk_rate / params_rate(params);
2664         if (!lrclk) {
2665                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2666                         bclk_rate);
2667                 return -EINVAL;
2668         }
2669         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2670                 lrclk, bclk_rate / lrclk);
2671
2672         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2673         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2674         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2675         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2676                             lrclk);
2677         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2678                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2679
2680         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2681                 switch (dai->id) {
2682                 case 1:
2683                         wm8994->dac_rates[0] = params_rate(params);
2684                         wm8994_set_retune_mobile(codec, 0);
2685                         wm8994_set_retune_mobile(codec, 1);
2686                         break;
2687                 case 2:
2688                         wm8994->dac_rates[1] = params_rate(params);
2689                         wm8994_set_retune_mobile(codec, 2);
2690                         break;
2691                 }
2692         }
2693
2694         return 0;
2695 }
2696
2697 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2698                                  struct snd_pcm_hw_params *params,
2699                                  struct snd_soc_dai *dai)
2700 {
2701         struct snd_soc_codec *codec = dai->codec;
2702         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2703         struct wm8994 *control = wm8994->wm8994;
2704         int aif1_reg;
2705         int aif1 = 0;
2706
2707         switch (dai->id) {
2708         case 3:
2709                 switch (control->type) {
2710                 case WM1811:
2711                 case WM8958:
2712                         aif1_reg = WM8958_AIF3_CONTROL_1;
2713                         break;
2714                 default:
2715                         return 0;
2716                 }
2717                 break;
2718         default:
2719                 return 0;
2720         }
2721
2722         switch (params_width(params)) {
2723         case 16:
2724                 break;
2725         case 20:
2726                 aif1 |= 0x20;
2727                 break;
2728         case 24:
2729                 aif1 |= 0x40;
2730                 break;
2731         case 32:
2732                 aif1 |= 0x60;
2733                 break;
2734         default:
2735                 return -EINVAL;
2736         }
2737
2738         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2739 }
2740
2741 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2742 {
2743         struct snd_soc_codec *codec = codec_dai->codec;
2744         int mute_reg;
2745         int reg;
2746
2747         switch (codec_dai->id) {
2748         case 1:
2749                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2750                 break;
2751         case 2:
2752                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2753                 break;
2754         default:
2755                 return -EINVAL;
2756         }
2757
2758         if (mute)
2759                 reg = WM8994_AIF1DAC1_MUTE;
2760         else
2761                 reg = 0;
2762
2763         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2764
2765         return 0;
2766 }
2767
2768 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2769 {
2770         struct snd_soc_codec *codec = codec_dai->codec;
2771         int reg, val, mask;
2772
2773         switch (codec_dai->id) {
2774         case 1:
2775                 reg = WM8994_AIF1_MASTER_SLAVE;
2776                 mask = WM8994_AIF1_TRI;
2777                 break;
2778         case 2:
2779                 reg = WM8994_AIF2_MASTER_SLAVE;
2780                 mask = WM8994_AIF2_TRI;
2781                 break;
2782         default:
2783                 return -EINVAL;
2784         }
2785
2786         if (tristate)
2787                 val = mask;
2788         else
2789                 val = 0;
2790
2791         return snd_soc_update_bits(codec, reg, mask, val);
2792 }
2793
2794 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2795 {
2796         struct snd_soc_codec *codec = dai->codec;
2797
2798         /* Disable the pulls on the AIF if we're using it to save power. */
2799         snd_soc_update_bits(codec, WM8994_GPIO_3,
2800                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2801         snd_soc_update_bits(codec, WM8994_GPIO_4,
2802                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2803         snd_soc_update_bits(codec, WM8994_GPIO_5,
2804                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2805
2806         return 0;
2807 }
2808
2809 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2810
2811 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2812                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2813
2814 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2815         .set_sysclk     = wm8994_set_dai_sysclk,
2816         .set_fmt        = wm8994_set_dai_fmt,
2817         .hw_params      = wm8994_hw_params,
2818         .digital_mute   = wm8994_aif_mute,
2819         .set_pll        = wm8994_set_fll,
2820         .set_tristate   = wm8994_set_tristate,
2821 };
2822
2823 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2824         .set_sysclk     = wm8994_set_dai_sysclk,
2825         .set_fmt        = wm8994_set_dai_fmt,
2826         .hw_params      = wm8994_hw_params,
2827         .digital_mute   = wm8994_aif_mute,
2828         .set_pll        = wm8994_set_fll,
2829         .set_tristate   = wm8994_set_tristate,
2830 };
2831
2832 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2833         .hw_params      = wm8994_aif3_hw_params,
2834 };
2835
2836 static struct snd_soc_dai_driver wm8994_dai[] = {
2837         {
2838                 .name = "wm8994-aif1",
2839                 .id = 1,
2840                 .playback = {
2841                         .stream_name = "AIF1 Playback",
2842                         .channels_min = 1,
2843                         .channels_max = 2,
2844                         .rates = WM8994_RATES,
2845                         .formats = WM8994_FORMATS,
2846                         .sig_bits = 24,
2847                 },
2848                 .capture = {
2849                         .stream_name = "AIF1 Capture",
2850                         .channels_min = 1,
2851                         .channels_max = 2,
2852                         .rates = WM8994_RATES,
2853                         .formats = WM8994_FORMATS,
2854                         .sig_bits = 24,
2855                  },
2856                 .ops = &wm8994_aif1_dai_ops,
2857         },
2858         {
2859                 .name = "wm8994-aif2",
2860                 .id = 2,
2861                 .playback = {
2862                         .stream_name = "AIF2 Playback",
2863                         .channels_min = 1,
2864                         .channels_max = 2,
2865                         .rates = WM8994_RATES,
2866                         .formats = WM8994_FORMATS,
2867                         .sig_bits = 24,
2868                 },
2869                 .capture = {
2870                         .stream_name = "AIF2 Capture",
2871                         .channels_min = 1,
2872                         .channels_max = 2,
2873                         .rates = WM8994_RATES,
2874                         .formats = WM8994_FORMATS,
2875                         .sig_bits = 24,
2876                 },
2877                 .probe = wm8994_aif2_probe,
2878                 .ops = &wm8994_aif2_dai_ops,
2879         },
2880         {
2881                 .name = "wm8994-aif3",
2882                 .id = 3,
2883                 .playback = {
2884                         .stream_name = "AIF3 Playback",
2885                         .channels_min = 1,
2886                         .channels_max = 2,
2887                         .rates = WM8994_RATES,
2888                         .formats = WM8994_FORMATS,
2889                         .sig_bits = 24,
2890                 },
2891                 .capture = {
2892                         .stream_name = "AIF3 Capture",
2893                         .channels_min = 1,
2894                         .channels_max = 2,
2895                         .rates = WM8994_RATES,
2896                         .formats = WM8994_FORMATS,
2897                         .sig_bits = 24,
2898                  },
2899                 .ops = &wm8994_aif3_dai_ops,
2900         }
2901 };
2902
2903 #ifdef CONFIG_PM
2904 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
2905 {
2906         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2907         int i, ret;
2908
2909         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2910                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2911                        sizeof(struct wm8994_fll_config));
2912                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2913                 if (ret < 0)
2914                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2915                                  i + 1, ret);
2916         }
2917
2918         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2919
2920         return 0;
2921 }
2922
2923 static int wm8994_codec_resume(struct snd_soc_codec *codec)
2924 {
2925         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2926         int i, ret;
2927
2928         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2929                 if (!wm8994->fll_suspend[i].out)
2930                         continue;
2931
2932                 ret = _wm8994_set_fll(codec, i + 1,
2933                                      wm8994->fll_suspend[i].src,
2934                                      wm8994->fll_suspend[i].in,
2935                                      wm8994->fll_suspend[i].out);
2936                 if (ret < 0)
2937                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2938                                  i + 1, ret);
2939         }
2940
2941         return 0;
2942 }
2943 #else
2944 #define wm8994_codec_suspend NULL
2945 #define wm8994_codec_resume NULL
2946 #endif
2947
2948 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2949 {
2950         struct snd_soc_codec *codec = wm8994->hubs.codec;
2951         struct wm8994 *control = wm8994->wm8994;
2952         struct wm8994_pdata *pdata = &control->pdata;
2953         struct snd_kcontrol_new controls[] = {
2954                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2955                              wm8994->retune_mobile_enum,
2956                              wm8994_get_retune_mobile_enum,
2957                              wm8994_put_retune_mobile_enum),
2958                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2959                              wm8994->retune_mobile_enum,
2960                              wm8994_get_retune_mobile_enum,
2961                              wm8994_put_retune_mobile_enum),
2962                 SOC_ENUM_EXT("AIF2 EQ Mode",
2963                              wm8994->retune_mobile_enum,
2964                              wm8994_get_retune_mobile_enum,
2965                              wm8994_put_retune_mobile_enum),
2966         };
2967         int ret, i, j;
2968         const char **t;
2969
2970         /* We need an array of texts for the enum API but the number
2971          * of texts is likely to be less than the number of
2972          * configurations due to the sample rate dependency of the
2973          * configurations. */
2974         wm8994->num_retune_mobile_texts = 0;
2975         wm8994->retune_mobile_texts = NULL;
2976         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2977                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2978                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2979                                    wm8994->retune_mobile_texts[j]) == 0)
2980                                 break;
2981                 }
2982
2983                 if (j != wm8994->num_retune_mobile_texts)
2984                         continue;
2985
2986                 /* Expand the array... */
2987                 t = krealloc(wm8994->retune_mobile_texts,
2988                              sizeof(char *) *
2989                              (wm8994->num_retune_mobile_texts + 1),
2990                              GFP_KERNEL);
2991                 if (t == NULL)
2992                         continue;
2993
2994                 /* ...store the new entry... */
2995                 t[wm8994->num_retune_mobile_texts] =
2996                         pdata->retune_mobile_cfgs[i].name;
2997
2998                 /* ...and remember the new version. */
2999                 wm8994->num_retune_mobile_texts++;
3000                 wm8994->retune_mobile_texts = t;
3001         }
3002
3003         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3004                 wm8994->num_retune_mobile_texts);
3005
3006         wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3007         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3008
3009         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3010                                    ARRAY_SIZE(controls));
3011         if (ret != 0)
3012                 dev_err(wm8994->hubs.codec->dev,
3013                         "Failed to add ReTune Mobile controls: %d\n", ret);
3014 }
3015
3016 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3017 {
3018         struct snd_soc_codec *codec = wm8994->hubs.codec;
3019         struct wm8994 *control = wm8994->wm8994;
3020         struct wm8994_pdata *pdata = &control->pdata;
3021         int ret, i;
3022
3023         if (!pdata)
3024                 return;
3025
3026         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3027                                       pdata->lineout2_diff,
3028                                       pdata->lineout1fb,
3029                                       pdata->lineout2fb,
3030                                       pdata->jd_scthr,
3031                                       pdata->jd_thr,
3032                                       pdata->micb1_delay,
3033                                       pdata->micb2_delay,
3034                                       pdata->micbias1_lvl,
3035                                       pdata->micbias2_lvl);
3036
3037         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3038
3039         if (pdata->num_drc_cfgs) {
3040                 struct snd_kcontrol_new controls[] = {
3041                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3042                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3043                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3044                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3045                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3046                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3047                 };
3048
3049                 /* We need an array of texts for the enum API */
3050                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3051                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3052                 if (!wm8994->drc_texts)
3053                         return;
3054
3055                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3056                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3057
3058                 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3059                 wm8994->drc_enum.texts = wm8994->drc_texts;
3060
3061                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3062                                            ARRAY_SIZE(controls));
3063                 for (i = 0; i < WM8994_NUM_DRC; i++)
3064                         wm8994_set_drc(codec, i);
3065         } else {
3066                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3067                                                  wm8994_drc_controls,
3068                                                  ARRAY_SIZE(wm8994_drc_controls));
3069         }
3070
3071         if (ret != 0)
3072                 dev_err(wm8994->hubs.codec->dev,
3073                         "Failed to add DRC mode controls: %d\n", ret);
3074
3075
3076         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3077                 pdata->num_retune_mobile_cfgs);
3078
3079         if (pdata->num_retune_mobile_cfgs)
3080                 wm8994_handle_retune_mobile_pdata(wm8994);
3081         else
3082                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3083                                      ARRAY_SIZE(wm8994_eq_controls));
3084
3085         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3086                 if (pdata->micbias[i]) {
3087                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3088                                 pdata->micbias[i] & 0xffff);
3089                 }
3090         }
3091 }
3092
3093 /**
3094  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3095  *
3096  * @codec:   WM8994 codec
3097  * @jack:    jack to report detection events on
3098  * @micbias: microphone bias to detect on
3099  *
3100  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3101  * being used to bring out signals to the processor then only platform
3102  * data configuration is needed for WM8994 and processor GPIOs should
3103  * be configured using snd_soc_jack_add_gpios() instead.
3104  *
3105  * Configuration of detection levels is available via the micbias1_lvl
3106  * and micbias2_lvl platform data members.
3107  */
3108 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3109                       int micbias)
3110 {
3111         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3112         struct wm8994_micdet *micdet;
3113         struct wm8994 *control = wm8994->wm8994;
3114         int reg, ret;
3115
3116         if (control->type != WM8994) {
3117                 dev_warn(codec->dev, "Not a WM8994\n");
3118                 return -EINVAL;
3119         }
3120
3121         switch (micbias) {
3122         case 1:
3123                 micdet = &wm8994->micdet[0];
3124                 if (jack)
3125                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3126                                                             "MICBIAS1");
3127                 else
3128                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3129                                                        "MICBIAS1");
3130                 break;
3131         case 2:
3132                 micdet = &wm8994->micdet[1];
3133                 if (jack)
3134                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3135                                                             "MICBIAS1");
3136                 else
3137                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3138                                                        "MICBIAS1");
3139                 break;
3140         default:
3141                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3142                 return -EINVAL;
3143         }
3144
3145         if (ret != 0)
3146                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3147                          micbias, ret);
3148
3149         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3150                 micbias, jack);
3151
3152         /* Store the configuration */
3153         micdet->jack = jack;
3154         micdet->detecting = true;
3155
3156         /* If either of the jacks is set up then enable detection */
3157         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3158                 reg = WM8994_MICD_ENA;
3159         else
3160                 reg = 0;
3161
3162         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3163
3164         /* enable MICDET and MICSHRT deboune */
3165         snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3166                             WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3167                             WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3168                             WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3169
3170         snd_soc_dapm_sync(&codec->dapm);
3171
3172         return 0;
3173 }
3174 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3175
3176 static void wm8994_mic_work(struct work_struct *work)
3177 {
3178         struct wm8994_priv *priv = container_of(work,
3179                                                 struct wm8994_priv,
3180                                                 mic_work.work);
3181         struct regmap *regmap = priv->wm8994->regmap;
3182         struct device *dev = priv->wm8994->dev;
3183         unsigned int reg;
3184         int ret;
3185         int report;
3186
3187         pm_runtime_get_sync(dev);
3188
3189         ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3190         if (ret < 0) {
3191                 dev_err(dev, "Failed to read microphone status: %d\n",
3192                         ret);
3193                 pm_runtime_put(dev);
3194                 return;
3195         }
3196
3197         dev_dbg(dev, "Microphone status: %x\n", reg);
3198
3199         report = 0;
3200         if (reg & WM8994_MIC1_DET_STS) {
3201                 if (priv->micdet[0].detecting)
3202                         report = SND_JACK_HEADSET;
3203         }
3204         if (reg & WM8994_MIC1_SHRT_STS) {
3205                 if (priv->micdet[0].detecting)
3206                         report = SND_JACK_HEADPHONE;
3207                 else
3208                         report |= SND_JACK_BTN_0;
3209         }
3210         if (report)
3211                 priv->micdet[0].detecting = false;
3212         else
3213                 priv->micdet[0].detecting = true;
3214
3215         snd_soc_jack_report(priv->micdet[0].jack, report,
3216                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3217
3218         report = 0;
3219         if (reg & WM8994_MIC2_DET_STS) {
3220                 if (priv->micdet[1].detecting)
3221                         report = SND_JACK_HEADSET;
3222         }
3223         if (reg & WM8994_MIC2_SHRT_STS) {
3224                 if (priv->micdet[1].detecting)
3225                         report = SND_JACK_HEADPHONE;
3226                 else
3227                         report |= SND_JACK_BTN_0;
3228         }
3229         if (report)
3230                 priv->micdet[1].detecting = false;
3231         else
3232                 priv->micdet[1].detecting = true;
3233
3234         snd_soc_jack_report(priv->micdet[1].jack, report,
3235                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3236
3237         pm_runtime_put(dev);
3238 }
3239
3240 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3241 {
3242         struct wm8994_priv *priv = data;
3243         struct snd_soc_codec *codec = priv->hubs.codec;
3244
3245 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3246         trace_snd_soc_jack_irq(dev_name(codec->dev));
3247 #endif
3248
3249         pm_wakeup_event(codec->dev, 300);
3250
3251         queue_delayed_work(system_power_efficient_wq,
3252                            &priv->mic_work, msecs_to_jiffies(250));
3253
3254         return IRQ_HANDLED;
3255 }
3256
3257 /* Should be called with accdet_lock held */
3258 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3259 {
3260         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3261
3262         if (!wm8994->jackdet)
3263                 return;
3264
3265         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3266
3267         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3268
3269         if (wm8994->wm8994->pdata.jd_ext_cap)
3270                 snd_soc_dapm_disable_pin(&codec->dapm,
3271                                          "MICBIAS2");
3272 }
3273
3274 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3275 {
3276         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3277         int report;
3278
3279         report = 0;
3280         if (status & 0x4)
3281                 report |= SND_JACK_BTN_0;
3282
3283         if (status & 0x8)
3284                 report |= SND_JACK_BTN_1;
3285
3286         if (status & 0x10)
3287                 report |= SND_JACK_BTN_2;
3288
3289         if (status & 0x20)
3290                 report |= SND_JACK_BTN_3;
3291
3292         if (status & 0x40)
3293                 report |= SND_JACK_BTN_4;
3294
3295         if (status & 0x80)
3296                 report |= SND_JACK_BTN_5;
3297
3298         snd_soc_jack_report(wm8994->micdet[0].jack, report,
3299                             wm8994->btn_mask);
3300 }
3301
3302 static void wm8958_open_circuit_work(struct work_struct *work)
3303 {
3304         struct wm8994_priv *wm8994 = container_of(work,
3305                                                   struct wm8994_priv,
3306                                                   open_circuit_work.work);
3307         struct device *dev = wm8994->wm8994->dev;
3308
3309         mutex_lock(&wm8994->accdet_lock);
3310
3311         wm1811_micd_stop(wm8994->hubs.codec);
3312
3313         dev_dbg(dev, "Reporting open circuit\n");
3314
3315         wm8994->jack_mic = false;
3316         wm8994->mic_detecting = true;
3317
3318         wm8958_micd_set_rate(wm8994->hubs.codec);
3319
3320         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3321                             wm8994->btn_mask |
3322                             SND_JACK_HEADSET);
3323
3324         mutex_unlock(&wm8994->accdet_lock);
3325 }
3326
3327 static void wm8958_mic_id(void *data, u16 status)
3328 {
3329         struct snd_soc_codec *codec = data;
3330         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3331
3332         /* Either nothing present or just starting detection */
3333         if (!(status & WM8958_MICD_STS)) {
3334                 /* If nothing present then clear our statuses */
3335                 dev_dbg(codec->dev, "Detected open circuit\n");
3336
3337                 queue_delayed_work(system_power_efficient_wq,
3338                                    &wm8994->open_circuit_work,
3339                                    msecs_to_jiffies(2500));
3340                 return;
3341         }
3342
3343         /* If the measurement is showing a high impedence we've got a
3344          * microphone.
3345          */
3346         if (status & 0x600) {
3347                 dev_dbg(codec->dev, "Detected microphone\n");
3348
3349                 wm8994->mic_detecting = false;
3350                 wm8994->jack_mic = true;
3351
3352                 wm8958_micd_set_rate(codec);
3353
3354                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3355                                     SND_JACK_HEADSET);
3356         }
3357
3358
3359         if (status & 0xfc) {
3360                 dev_dbg(codec->dev, "Detected headphone\n");
3361                 wm8994->mic_detecting = false;
3362
3363                 wm8958_micd_set_rate(codec);
3364
3365                 /* If we have jackdet that will detect removal */
3366                 wm1811_micd_stop(codec);
3367
3368                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3369                                     SND_JACK_HEADSET);
3370         }
3371 }
3372
3373 /* Deferred mic detection to allow for extra settling time */
3374 static void wm1811_mic_work(struct work_struct *work)
3375 {
3376         struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3377                                                   mic_work.work);
3378         struct wm8994 *control = wm8994->wm8994;
3379         struct snd_soc_codec *codec = wm8994->hubs.codec;
3380
3381         pm_runtime_get_sync(codec->dev);
3382
3383         /* If required for an external cap force MICBIAS on */
3384         if (control->pdata.jd_ext_cap) {
3385                 snd_soc_dapm_force_enable_pin(&codec->dapm,
3386                                               "MICBIAS2");
3387                 snd_soc_dapm_sync(&codec->dapm);
3388         }
3389
3390         mutex_lock(&wm8994->accdet_lock);
3391
3392         dev_dbg(codec->dev, "Starting mic detection\n");
3393
3394         /* Use a user-supplied callback if we have one */
3395         if (wm8994->micd_cb) {
3396                 wm8994->micd_cb(wm8994->micd_cb_data);
3397         } else {
3398                 /*
3399                  * Start off measument of microphone impedence to find out
3400                  * what's actually there.
3401                  */
3402                 wm8994->mic_detecting = true;
3403                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3404
3405                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3406                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3407         }
3408
3409         mutex_unlock(&wm8994->accdet_lock);
3410
3411         pm_runtime_put(codec->dev);
3412 }
3413
3414 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3415 {
3416         struct wm8994_priv *wm8994 = data;
3417         struct wm8994 *control = wm8994->wm8994;
3418         struct snd_soc_codec *codec = wm8994->hubs.codec;
3419         int reg, delay;
3420         bool present;
3421
3422         pm_runtime_get_sync(codec->dev);
3423
3424         cancel_delayed_work_sync(&wm8994->mic_complete_work);
3425
3426         mutex_lock(&wm8994->accdet_lock);
3427
3428         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3429         if (reg < 0) {
3430                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3431                 mutex_unlock(&wm8994->accdet_lock);
3432                 pm_runtime_put(codec->dev);
3433                 return IRQ_NONE;
3434         }
3435
3436         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3437
3438         present = reg & WM1811_JACKDET_LVL;
3439
3440         if (present) {
3441                 dev_dbg(codec->dev, "Jack detected\n");
3442
3443                 wm8958_micd_set_rate(codec);
3444
3445                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3446                                     WM8958_MICB2_DISCH, 0);
3447
3448                 /* Disable debounce while inserted */
3449                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3450                                     WM1811_JACKDET_DB, 0);
3451
3452                 delay = control->pdata.micdet_delay;
3453                 queue_delayed_work(system_power_efficient_wq,
3454                                    &wm8994->mic_work,
3455                                    msecs_to_jiffies(delay));
3456         } else {
3457                 dev_dbg(codec->dev, "Jack not detected\n");
3458
3459                 cancel_delayed_work_sync(&wm8994->mic_work);
3460
3461                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3462                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3463
3464                 /* Enable debounce while removed */
3465                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3466                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3467
3468                 wm8994->mic_detecting = false;
3469                 wm8994->jack_mic = false;
3470                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3471                                     WM8958_MICD_ENA, 0);
3472                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3473         }
3474
3475         mutex_unlock(&wm8994->accdet_lock);
3476
3477         /* Turn off MICBIAS if it was on for an external cap */
3478         if (control->pdata.jd_ext_cap && !present)
3479                 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3480
3481         if (present)
3482                 snd_soc_jack_report(wm8994->micdet[0].jack,
3483                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3484         else
3485                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3486                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3487                                     wm8994->btn_mask);
3488
3489         /* Since we only report deltas force an update, ensures we
3490          * avoid bootstrapping issues with the core. */
3491         snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3492
3493         pm_runtime_put(codec->dev);
3494         return IRQ_HANDLED;
3495 }
3496
3497 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3498 {
3499         struct wm8994_priv *wm8994 = container_of(work,
3500                                                 struct wm8994_priv,
3501                                                 jackdet_bootstrap.work);
3502         wm1811_jackdet_irq(0, wm8994);
3503 }
3504
3505 /**
3506  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3507  *
3508  * @codec:   WM8958 codec
3509  * @jack:    jack to report detection events on
3510  *
3511  * Enable microphone detection functionality for the WM8958.  By
3512  * default simple detection which supports the detection of up to 6
3513  * buttons plus video and microphone functionality is supported.
3514  *
3515  * The WM8958 has an advanced jack detection facility which is able to
3516  * support complex accessory detection, especially when used in
3517  * conjunction with external circuitry.  In order to provide maximum
3518  * flexiblity a callback is provided which allows a completely custom
3519  * detection algorithm.
3520  */
3521 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3522                       wm1811_micdet_cb det_cb, void *det_cb_data,
3523                       wm1811_mic_id_cb id_cb, void *id_cb_data)
3524 {
3525         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3526         struct wm8994 *control = wm8994->wm8994;
3527         u16 micd_lvl_sel;
3528
3529         switch (control->type) {
3530         case WM1811:
3531         case WM8958:
3532                 break;
3533         default:
3534                 return -EINVAL;
3535         }
3536
3537         if (jack) {
3538                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3539                 snd_soc_dapm_sync(&codec->dapm);
3540
3541                 wm8994->micdet[0].jack = jack;
3542
3543                 if (det_cb) {
3544                         wm8994->micd_cb = det_cb;
3545                         wm8994->micd_cb_data = det_cb_data;
3546                 } else {
3547                         wm8994->mic_detecting = true;
3548                         wm8994->jack_mic = false;
3549                 }
3550
3551                 if (id_cb) {
3552                         wm8994->mic_id_cb = id_cb;
3553                         wm8994->mic_id_cb_data = id_cb_data;
3554                 } else {
3555                         wm8994->mic_id_cb = wm8958_mic_id;
3556                         wm8994->mic_id_cb_data = codec;
3557                 }
3558
3559                 wm8958_micd_set_rate(codec);
3560
3561                 /* Detect microphones and short circuits by default */
3562                 if (control->pdata.micd_lvl_sel)
3563                         micd_lvl_sel = control->pdata.micd_lvl_sel;
3564                 else
3565                         micd_lvl_sel = 0x41;
3566
3567                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3568                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3569                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3570
3571                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3572                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3573
3574                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3575
3576                 /*
3577                  * If we can use jack detection start off with that,
3578                  * otherwise jump straight to microphone detection.
3579                  */
3580                 if (wm8994->jackdet) {
3581                         /* Disable debounce for the initial detect */
3582                         snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3583                                             WM1811_JACKDET_DB, 0);
3584
3585                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3586                                             WM8958_MICB2_DISCH,
3587                                             WM8958_MICB2_DISCH);
3588                         snd_soc_update_bits(codec, WM8994_LDO_1,
3589                                             WM8994_LDO1_DISCH, 0);
3590                         wm1811_jackdet_set_mode(codec,
3591                                                 WM1811_JACKDET_MODE_JACK);
3592                 } else {
3593                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3594                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3595                 }
3596
3597         } else {
3598                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3599                                     WM8958_MICD_ENA, 0);
3600                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3601                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3602                 snd_soc_dapm_sync(&codec->dapm);
3603         }
3604
3605         return 0;
3606 }
3607 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3608
3609 static void wm8958_mic_work(struct work_struct *work)
3610 {
3611         struct wm8994_priv *wm8994 = container_of(work,
3612                                                   struct wm8994_priv,
3613                                                   mic_complete_work.work);
3614         struct snd_soc_codec *codec = wm8994->hubs.codec;
3615
3616         pm_runtime_get_sync(codec->dev);
3617
3618         mutex_lock(&wm8994->accdet_lock);
3619
3620         wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3621
3622         mutex_unlock(&wm8994->accdet_lock);
3623
3624         pm_runtime_put(codec->dev);
3625 }
3626
3627 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3628 {
3629         struct wm8994_priv *wm8994 = data;
3630         struct snd_soc_codec *codec = wm8994->hubs.codec;
3631         int reg, count, ret, id_delay;
3632
3633         /*
3634          * Jack detection may have detected a removal simulataneously
3635          * with an update of the MICDET status; if so it will have
3636          * stopped detection and we can ignore this interrupt.
3637          */
3638         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3639                 return IRQ_HANDLED;
3640
3641         cancel_delayed_work_sync(&wm8994->mic_complete_work);
3642         cancel_delayed_work_sync(&wm8994->open_circuit_work);
3643
3644         pm_runtime_get_sync(codec->dev);
3645
3646         /* We may occasionally read a detection without an impedence
3647          * range being provided - if that happens loop again.
3648          */
3649         count = 10;
3650         do {
3651                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3652                 if (reg < 0) {
3653                         dev_err(codec->dev,
3654                                 "Failed to read mic detect status: %d\n",
3655                                 reg);
3656                         pm_runtime_put(codec->dev);
3657                         return IRQ_NONE;
3658                 }
3659
3660                 if (!(reg & WM8958_MICD_VALID)) {
3661                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3662                         goto out;
3663                 }
3664
3665                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3666                         break;
3667
3668                 msleep(1);
3669         } while (count--);
3670
3671         if (count == 0)
3672                 dev_warn(codec->dev, "No impedance range reported for jack\n");
3673
3674 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3675         trace_snd_soc_jack_irq(dev_name(codec->dev));
3676 #endif
3677
3678         /* Avoid a transient report when the accessory is being removed */
3679         if (wm8994->jackdet) {
3680                 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3681                 if (ret < 0) {
3682                         dev_err(codec->dev, "Failed to read jack status: %d\n",
3683                                 ret);
3684                 } else if (!(ret & WM1811_JACKDET_LVL)) {
3685                         dev_dbg(codec->dev, "Ignoring removed jack\n");
3686                         goto out;
3687                 }
3688         } else if (!(reg & WM8958_MICD_STS)) {
3689                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3690                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3691                                     wm8994->btn_mask);
3692                 wm8994->mic_detecting = true;
3693                 goto out;
3694         }
3695
3696         wm8994->mic_status = reg;
3697         id_delay = wm8994->wm8994->pdata.mic_id_delay;
3698
3699         if (wm8994->mic_detecting)
3700                 queue_delayed_work(system_power_efficient_wq,
3701                                    &wm8994->mic_complete_work,
3702                                    msecs_to_jiffies(id_delay));
3703         else
3704                 wm8958_button_det(codec, reg);
3705
3706 out:
3707         pm_runtime_put(codec->dev);
3708         return IRQ_HANDLED;
3709 }
3710
3711 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3712 {
3713         struct snd_soc_codec *codec = data;
3714
3715         dev_err(codec->dev, "FIFO error\n");
3716
3717         return IRQ_HANDLED;
3718 }
3719
3720 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3721 {
3722         struct snd_soc_codec *codec = data;
3723
3724         dev_err(codec->dev, "Thermal warning\n");
3725
3726         return IRQ_HANDLED;
3727 }
3728
3729 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3730 {
3731         struct snd_soc_codec *codec = data;
3732
3733         dev_crit(codec->dev, "Thermal shutdown\n");
3734
3735         return IRQ_HANDLED;
3736 }
3737
3738 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3739 {
3740         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3741         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3742         struct snd_soc_dapm_context *dapm = &codec->dapm;
3743         unsigned int reg;
3744         int ret, i;
3745
3746         wm8994->hubs.codec = codec;
3747
3748         mutex_init(&wm8994->accdet_lock);
3749         INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3750                           wm1811_jackdet_bootstrap);
3751         INIT_DELAYED_WORK(&wm8994->open_circuit_work,
3752                           wm8958_open_circuit_work);
3753
3754         switch (control->type) {
3755         case WM8994:
3756                 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3757                 break;
3758         case WM1811:
3759                 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3760                 break;
3761         default:
3762                 break;
3763         }
3764
3765         INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
3766
3767         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3768                 init_completion(&wm8994->fll_locked[i]);
3769
3770         wm8994->micdet_irq = control->pdata.micdet_irq;
3771
3772         /* By default use idle_bias_off, will override for WM8994 */
3773         codec->dapm.idle_bias_off = 1;
3774
3775         /* Set revision-specific configuration */
3776         switch (control->type) {
3777         case WM8994:
3778                 /* Single ended line outputs should have VMID on. */
3779                 if (!control->pdata.lineout1_diff ||
3780                     !control->pdata.lineout2_diff)
3781                         codec->dapm.idle_bias_off = 0;
3782
3783                 switch (control->revision) {
3784                 case 2:
3785                 case 3:
3786                         wm8994->hubs.dcs_codes_l = -5;
3787                         wm8994->hubs.dcs_codes_r = -5;
3788                         wm8994->hubs.hp_startup_mode = 1;
3789                         wm8994->hubs.dcs_readback_mode = 1;
3790                         wm8994->hubs.series_startup = 1;
3791                         break;
3792                 default:
3793                         wm8994->hubs.dcs_readback_mode = 2;
3794                         break;
3795                 }
3796                 break;
3797
3798         case WM8958:
3799                 wm8994->hubs.dcs_readback_mode = 1;
3800                 wm8994->hubs.hp_startup_mode = 1;
3801
3802                 switch (control->revision) {
3803                 case 0:
3804                         break;
3805                 default:
3806                         wm8994->fll_byp = true;
3807                         break;
3808                 }
3809                 break;
3810
3811         case WM1811:
3812                 wm8994->hubs.dcs_readback_mode = 2;
3813                 wm8994->hubs.no_series_update = 1;
3814                 wm8994->hubs.hp_startup_mode = 1;
3815                 wm8994->hubs.no_cache_dac_hp_direct = true;
3816                 wm8994->fll_byp = true;
3817
3818                 wm8994->hubs.dcs_codes_l = -9;
3819                 wm8994->hubs.dcs_codes_r = -7;
3820
3821                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3822                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3823                 break;
3824
3825         default:
3826                 break;
3827         }
3828
3829         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3830                            wm8994_fifo_error, "FIFO error", codec);
3831         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3832                            wm8994_temp_warn, "Thermal warning", codec);
3833         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3834                            wm8994_temp_shut, "Thermal shutdown", codec);
3835
3836         switch (control->type) {
3837         case WM8994:
3838                 if (wm8994->micdet_irq)
3839                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3840                                                    wm8994_mic_irq,
3841                                                    IRQF_TRIGGER_RISING,
3842                                                    "Mic1 detect",
3843                                                    wm8994);
3844                  else
3845                         ret = wm8994_request_irq(wm8994->wm8994,
3846                                         WM8994_IRQ_MIC1_DET,
3847                                         wm8994_mic_irq, "Mic 1 detect",
3848                                         wm8994);
3849
3850                 if (ret != 0)
3851                         dev_warn(codec->dev,
3852                                  "Failed to request Mic1 detect IRQ: %d\n",
3853                                  ret);
3854
3855
3856                 ret = wm8994_request_irq(wm8994->wm8994,
3857                                          WM8994_IRQ_MIC1_SHRT,
3858                                          wm8994_mic_irq, "Mic 1 short",
3859                                          wm8994);
3860                 if (ret != 0)
3861                         dev_warn(codec->dev,
3862                                  "Failed to request Mic1 short IRQ: %d\n",
3863                                  ret);
3864
3865                 ret = wm8994_request_irq(wm8994->wm8994,
3866                                          WM8994_IRQ_MIC2_DET,
3867                                          wm8994_mic_irq, "Mic 2 detect",
3868                                          wm8994);
3869                 if (ret != 0)
3870                         dev_warn(codec->dev,
3871                                  "Failed to request Mic2 detect IRQ: %d\n",
3872                                  ret);
3873
3874                 ret = wm8994_request_irq(wm8994->wm8994,
3875                                          WM8994_IRQ_MIC2_SHRT,
3876                                          wm8994_mic_irq, "Mic 2 short",
3877                                          wm8994);
3878                 if (ret != 0)
3879                         dev_warn(codec->dev,
3880                                  "Failed to request Mic2 short IRQ: %d\n",
3881                                  ret);
3882                 break;
3883
3884         case WM8958:
3885         case WM1811:
3886                 if (wm8994->micdet_irq) {
3887                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3888                                                    wm8958_mic_irq,
3889                                                    IRQF_TRIGGER_RISING,
3890                                                    "Mic detect",
3891                                                    wm8994);
3892                         if (ret != 0)
3893                                 dev_warn(codec->dev,
3894                                          "Failed to request Mic detect IRQ: %d\n",
3895                                          ret);
3896                 } else {
3897                         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3898                                            wm8958_mic_irq, "Mic detect",
3899                                            wm8994);
3900                 }
3901         }
3902
3903         switch (control->type) {
3904         case WM1811:
3905                 if (control->cust_id > 1 || control->revision > 1) {
3906                         ret = wm8994_request_irq(wm8994->wm8994,
3907                                                  WM8994_IRQ_GPIO(6),
3908                                                  wm1811_jackdet_irq, "JACKDET",
3909                                                  wm8994);
3910                         if (ret == 0)
3911                                 wm8994->jackdet = true;
3912                 }
3913                 break;
3914         default:
3915                 break;
3916         }
3917
3918         wm8994->fll_locked_irq = true;
3919         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3920                 ret = wm8994_request_irq(wm8994->wm8994,
3921                                          WM8994_IRQ_FLL1_LOCK + i,
3922                                          wm8994_fll_locked_irq, "FLL lock",
3923                                          &wm8994->fll_locked[i]);
3924                 if (ret != 0)
3925                         wm8994->fll_locked_irq = false;
3926         }
3927
3928         /* Make sure we can read from the GPIOs if they're inputs */
3929         pm_runtime_get_sync(codec->dev);
3930
3931         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3932          * configured on init - if a system wants to do this dynamically
3933          * at runtime we can deal with that then.
3934          */
3935         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3936         if (ret < 0) {
3937                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3938                 goto err_irq;
3939         }
3940         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3941                 wm8994->lrclk_shared[0] = 1;
3942                 wm8994_dai[0].symmetric_rates = 1;
3943         } else {
3944                 wm8994->lrclk_shared[0] = 0;
3945         }
3946
3947         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3948         if (ret < 0) {
3949                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3950                 goto err_irq;
3951         }
3952         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3953                 wm8994->lrclk_shared[1] = 1;
3954                 wm8994_dai[1].symmetric_rates = 1;
3955         } else {
3956                 wm8994->lrclk_shared[1] = 0;
3957         }
3958
3959         pm_runtime_put(codec->dev);
3960
3961         /* Latch volume update bits */
3962         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
3963                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
3964                                     wm8994_vu_bits[i].mask,
3965                                     wm8994_vu_bits[i].mask);
3966
3967         /* Set the low bit of the 3D stereo depth so TLV matches */
3968         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3969                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3970                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3971         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3972                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3973                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3974         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3975                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3976                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3977
3978         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3979          * use this; it only affects behaviour on idle TDM clock
3980          * cycles. */
3981         switch (control->type) {
3982         case WM8994:
3983         case WM8958:
3984                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3985                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3986                 break;
3987         default:
3988                 break;
3989         }
3990
3991         /* Put MICBIAS into bypass mode by default on newer devices */
3992         switch (control->type) {
3993         case WM8958:
3994         case WM1811:
3995                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3996                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3997                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3998                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3999                 break;
4000         default:
4001                 break;
4002         }
4003
4004         wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4005         wm_hubs_update_class_w(codec);
4006
4007         wm8994_handle_pdata(wm8994);
4008
4009         wm_hubs_add_analogue_controls(codec);
4010         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4011                              ARRAY_SIZE(wm8994_snd_controls));
4012         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4013                                   ARRAY_SIZE(wm8994_dapm_widgets));
4014
4015         switch (control->type) {
4016         case WM8994:
4017                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4018                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
4019                 if (control->revision < 4) {
4020                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4021                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4022                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4023                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4024                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4025                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4026                 } else {
4027                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4028                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4029                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4030                                                   ARRAY_SIZE(wm8994_adc_widgets));
4031                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4032                                                   ARRAY_SIZE(wm8994_dac_widgets));
4033                 }
4034                 break;
4035         case WM8958:
4036                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4037                                      ARRAY_SIZE(wm8958_snd_controls));
4038                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4039                                           ARRAY_SIZE(wm8958_dapm_widgets));
4040                 if (control->revision < 1) {
4041                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4042                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4043                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4044                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4045                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4046                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4047                 } else {
4048                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4049                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4050                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4051                                                   ARRAY_SIZE(wm8994_adc_widgets));
4052                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4053                                                   ARRAY_SIZE(wm8994_dac_widgets));
4054                 }
4055                 break;
4056
4057         case WM1811:
4058                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4059                                      ARRAY_SIZE(wm8958_snd_controls));
4060                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4061                                           ARRAY_SIZE(wm8958_dapm_widgets));
4062                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4063                                           ARRAY_SIZE(wm8994_lateclk_widgets));
4064                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4065                                           ARRAY_SIZE(wm8994_adc_widgets));
4066                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4067                                           ARRAY_SIZE(wm8994_dac_widgets));
4068                 break;
4069         }
4070
4071         wm_hubs_add_analogue_routes(codec, 0, 0);
4072         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4073                                  wm_hubs_dcs_done, "DC servo done",
4074                                  &wm8994->hubs);
4075         if (ret == 0)
4076                 wm8994->hubs.dcs_done_irq = true;
4077         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4078
4079         switch (control->type) {
4080         case WM8994:
4081                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4082                                         ARRAY_SIZE(wm8994_intercon));
4083
4084                 if (control->revision < 4) {
4085                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4086                                                 ARRAY_SIZE(wm8994_revd_intercon));
4087                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4088                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4089                 } else {
4090                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4091                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4092                 }
4093                 break;
4094         case WM8958:
4095                 if (control->revision < 1) {
4096                         snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4097                                                 ARRAY_SIZE(wm8994_intercon));
4098                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4099                                                 ARRAY_SIZE(wm8994_revd_intercon));
4100                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4101                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4102                 } else {
4103                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4104                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4105                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4106                                                 ARRAY_SIZE(wm8958_intercon));
4107                 }
4108
4109                 wm8958_dsp2_init(codec);
4110                 break;
4111         case WM1811:
4112                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4113                                         ARRAY_SIZE(wm8994_lateclk_intercon));
4114                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4115                                         ARRAY_SIZE(wm8958_intercon));
4116                 break;
4117         }
4118
4119         return 0;
4120
4121 err_irq:
4122         if (wm8994->jackdet)
4123                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4124         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4125         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4126         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4127         if (wm8994->micdet_irq)
4128                 free_irq(wm8994->micdet_irq, wm8994);
4129         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4130                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4131                                 &wm8994->fll_locked[i]);
4132         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4133                         &wm8994->hubs);
4134         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4135         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4136         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4137
4138         return ret;
4139 }
4140
4141 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4142 {
4143         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4144         struct wm8994 *control = wm8994->wm8994;
4145         int i;
4146
4147         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4148                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4149                                 &wm8994->fll_locked[i]);
4150
4151         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4152                         &wm8994->hubs);
4153         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4154         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4155         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4156
4157         if (wm8994->jackdet)
4158                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4159
4160         switch (control->type) {
4161         case WM8994:
4162                 if (wm8994->micdet_irq)
4163                         free_irq(wm8994->micdet_irq, wm8994);
4164                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4165                                 wm8994);
4166                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4167                                 wm8994);
4168                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4169                                 wm8994);
4170                 break;
4171
4172         case WM1811:
4173         case WM8958:
4174                 if (wm8994->micdet_irq)
4175                         free_irq(wm8994->micdet_irq, wm8994);
4176                 break;
4177         }
4178         release_firmware(wm8994->mbc);
4179         release_firmware(wm8994->mbc_vss);
4180         release_firmware(wm8994->enh_eq);
4181         kfree(wm8994->retune_mobile_texts);
4182         return 0;
4183 }
4184
4185 static struct regmap *wm8994_get_regmap(struct device *dev)
4186 {
4187         struct wm8994 *control = dev_get_drvdata(dev->parent);
4188
4189         return control->regmap;
4190 }
4191
4192 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4193         .probe =        wm8994_codec_probe,
4194         .remove =       wm8994_codec_remove,
4195         .suspend =      wm8994_codec_suspend,
4196         .resume =       wm8994_codec_resume,
4197         .get_regmap =   wm8994_get_regmap,
4198         .set_bias_level = wm8994_set_bias_level,
4199 };
4200
4201 static int wm8994_probe(struct platform_device *pdev)
4202 {
4203         struct wm8994_priv *wm8994;
4204
4205         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4206                               GFP_KERNEL);
4207         if (wm8994 == NULL)
4208                 return -ENOMEM;
4209         platform_set_drvdata(pdev, wm8994);
4210
4211         mutex_init(&wm8994->fw_lock);
4212
4213         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4214
4215         pm_runtime_enable(&pdev->dev);
4216         pm_runtime_idle(&pdev->dev);
4217
4218         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4219                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4220 }
4221
4222 static int wm8994_remove(struct platform_device *pdev)
4223 {
4224         snd_soc_unregister_codec(&pdev->dev);
4225         pm_runtime_disable(&pdev->dev);
4226
4227         return 0;
4228 }
4229
4230 #ifdef CONFIG_PM_SLEEP
4231 static int wm8994_suspend(struct device *dev)
4232 {
4233         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4234
4235         /* Drop down to power saving mode when system is suspended */
4236         if (wm8994->jackdet && !wm8994->active_refcount)
4237                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4238                                    WM1811_JACKDET_MODE_MASK,
4239                                    wm8994->jackdet_mode);
4240
4241         return 0;
4242 }
4243
4244 static int wm8994_resume(struct device *dev)
4245 {
4246         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4247
4248         if (wm8994->jackdet && wm8994->jackdet_mode)
4249                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4250                                    WM1811_JACKDET_MODE_MASK,
4251                                    WM1811_JACKDET_MODE_AUDIO);
4252
4253         return 0;
4254 }
4255 #endif
4256
4257 static const struct dev_pm_ops wm8994_pm_ops = {
4258         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4259 };
4260
4261 static struct platform_driver wm8994_codec_driver = {
4262         .driver = {
4263                 .name = "wm8994-codec",
4264                 .pm = &wm8994_pm_ops,
4265         },
4266         .probe = wm8994_probe,
4267         .remove = wm8994_remove,
4268 };
4269
4270 module_platform_driver(wm8994_codec_driver);
4271
4272 MODULE_DESCRIPTION("ASoC WM8994 driver");
4273 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4274 MODULE_LICENSE("GPL");
4275 MODULE_ALIAS("platform:wm8994-codec");