Merge branch 'clk-next' of git://git.linaro.org/people/mturquette/linux into next...

* 'clk-next' of git://git.linaro.org/people/mturquette/linux:
  clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate().
  clk: Provide dummy clk_unregister()
  ARM: Kirkwood: Replace clock gating
  ARM: Orion: Audio: Add clk/clkdev support
  ARM: Orion: PCIE: Add support for clk
  ARM: Orion: XOR: Add support for clk
  ARM: Orion: CESA: Add support for clk
  ARM: Orion: SDIO: Add support for clk.
  ARM: Orion: NAND: Add support for clk, if there is one.
  ARM: Orion: EHCI: Add support for enabling clocks
  ARM: Orion: SATA: Add per channel clk/clkdev support.
  ARM: Orion: UART: Get the clock rate via clk_get_rate().
  ARM: Orion: WDT: Add clk/clkdev support
  ARM: Orion: Eth: Add clk/clkdev support.
  ARM: Orion: SPI: Add clk/clkdev support.
  ARM: Orion: Add clocks using the generic clk infrastructure.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/Documentation/ABI/testing/sysfs-bus-hsi b/Documentation/ABI/testing/sysfs-bus-hsi
new file mode 100644 (file)
index 0000000..1b1b282
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-hsi
@@ -0,0 +1,19 @@
+What:          /sys/bus/hsi
+Date:          April 2012
+KernelVersion: 3.4
+Contact:       Carlos Chinea <carlos.chinea@nokia.com>
+Description:
+               High Speed Synchronous Serial Interface (HSI) is a
+               serial interface mainly used for connecting application
+               engines (APE) with cellular modem engines (CMT) in cellular
+               handsets.
+               The bus will be populated with devices (hsi_clients) representing
+               the protocols available in the system. Bus drivers implement
+               those protocols.
+
+What:          /sys/bus/hsi/devices/.../modalias
+Date:          April 2012
+KernelVersion: 3.4
+Contact:       Carlos Chinea <carlos.chinea@nokia.com>
+Description:   Stores the same MODALIAS value emitted by uevent
+               Format: hsi:<hsi_client device name>

diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
index 253a35c..28a9af9 100644 (file)
--- a/Documentation/arm/SPEAr/overview.txt
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -17,14 +17,14 @@ Introduction
   SPEAr (Platform)
        - SPEAr3XX (3XX SOC series, based on ARM9)
                - SPEAr300 (SOC)
-                       - SPEAr300_EVB (Evaluation Board)
+                       - SPEAr300 Evaluation Board
                - SPEAr310 (SOC)
-                       - SPEAr310_EVB (Evaluation Board)
+                       - SPEAr310 Evaluation Board
                - SPEAr320 (SOC)
-                       - SPEAr320_EVB (Evaluation Board)
+                       - SPEAr320 Evaluation Board
        - SPEAr6XX (6XX SOC series, based on ARM9)
                - SPEAr600 (SOC)
-                       - SPEAr600_EVB (Evaluation Board)
+                       - SPEAr600 Evaluation Board
        - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
                - SPEAr1300 (SOC)
 
@@ -51,10 +51,11 @@ Introduction
   Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
   spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
   specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
-  mach-spear* also contains board specific files for each machine type.
+  mach-spear* doesn't contains board specific files as they fully support
+  Flattened Device Tree.
 
 
   Document Author
   ---------------
 
-  Viresh Kumar, (c) 2010 ST Microelectronics
+  Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics

diff --git a/Documentation/devicetree/bindings/arm/spear-timer.txt b/Documentation/devicetree/bindings/arm/spear-timer.txt
new file mode 100644 (file)
index 0000000..c001722
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-timer.txt
@@ -0,0 +1,18 @@
+* SPEAr ARM Timer
+
+** Timer node required properties:
+
+- compatible : Should be:
+       "st,spear-timer"
+- reg: Address range of the timer registers
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupt: Should contain the timer interrupt number
+
+Example:
+
+       timer@f0000000 {
+               compatible = "st,spear-timer";
+               reg = <0xf0000000 0x400>;
+               interrupts = <2>;
+       };

diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt
index f8e54f0..aa5f355 100644 (file)
--- a/Documentation/devicetree/bindings/arm/spear.txt
+++ b/Documentation/devicetree/bindings/arm/spear.txt
@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
 Required root node property:
 
 compatible = "st,spear600";
+
+Boards with the ST SPEAr300 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear300";
+
+Boards with the ST SPEAr310 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear310";
+
+Boards with the ST SPEAr320 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear320";

diff --git a/Documentation/devicetree/bindings/ata/calxeda-sata.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
similarity index 90%
rename from Documentation/devicetree/bindings/ata/calxeda-sata.txt
rename to Documentation/devicetree/bindings/ata/ahci-platform.txt
index 79caa56..8bb8a76 100644 (file)
--- a/Documentation/devicetree/bindings/ata/calxeda-sata.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -1,10 +1,10 @@
-* Calxeda SATA Controller
+* AHCI SATA Controller
 
 SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 
 Required properties:
-- compatible        : compatible list, contains "calxeda,hb-ahci"
+- compatible        : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci"
 - interrupts        : <interrupt mapping for SATA IRQ>
 - reg               : <registers mapping>
 
@@ -14,4 +14,3 @@ Example:
                 reg = <0xffe08000 0x1000>;
                 interrupts = <115>;
         };
-

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
new file mode 100644 (file)
index 0000000..ab19e6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -0,0 +1,95 @@
+* Freescale IOMUX Controller (IOMUXC) for i.MX
+
+The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are up to
+8 muxing options (called ALT modes). Since different modules require
+different PAD settings (like pull up, keeper, etc) the IOMUXC controls
+also the PAD settings parameters.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Freescale IMX pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and config
+of the pins in that group. The 'mux' selects the function mode(also named mux
+mode) this pin can work on and the 'config' configures various pad settings
+such as pull-up, open drain, drive strength, etc.
+
+Required properties for iomux controller:
+- compatible: "fsl,<soc>-iomuxc"
+  Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
+  pins and functions of each SoC.
+
+Bits used for CONFIG:
+NO_PAD_CTL(1 << 31): indicate this pin does not need config.
+
+SION(1 << 30): Software Input On Field.
+Force the selected mux mode input path no matter of MUX_MODE functionality.
+By default the input path is determined by functionality of the selected
+mux mode (regular).
+
+Other bits are used for PAD setting.
+Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
+of bits definitions.
+
+NOTE:
+Some requirements for using fsl,imx-pinctrl binding:
+1. We have pin function node defined under iomux controller node to represent
+   what pinmux functions this SoC supports.
+2. The pin configuration node intends to work on a specific function should
+   to be defined under that specific function node.
+   The function node's name should represent well about what function
+   this group of pins in this pin configuration node are working on.
+3. The driver can use the function node's name and pin configuration node's
+   name describe the pin function and group hierarchy.
+   For example, Linux IMX pinctrl driver takes the function node's name
+   as the function name and pin configuration node's name as group name to
+   create the map table.
+4. Each pin configuration node should have a phandle, devices can set pins
+   configurations by referring to the phandle of that pin configuration node.
+
+Examples:
+usdhc@0219c000 { /* uSDHC4 */
+       fsl,card-wired;
+       vmmc-supply = <&reg_3p3v>;
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc4_1>;
+};
+
+iomuxc@020e0000 {
+       compatible = "fsl,imx6q-iomuxc";
+       reg = <0x020e0000 0x4000>;
+
+       /* shared pinctrl settings */
+       usdhc4 {
+               pinctrl_usdhc4_1: usdhc4grp-1 {
+                       fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+                                   1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+                                   1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                   1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                   1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                   1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                   1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+                                   1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+                                   1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+                                   1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+               };
+       };
+       ....
+};
+Refer to the IOMUXC controller chapter in imx6q datasheet,
+0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
+80Ohm driver strength and Fast Slew Rate.
+User should refer to each SoC spec to set the correct value.
+
+TODO: when dtc macro support is available, we can change above raw data
+to dt macro which can get better readability in dts file.

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
new file mode 100644 (file)
index 0000000..82b43f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt
@@ -0,0 +1,1628 @@
+* Freescale IMX6Q IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6q-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
+  pin working on a specific function, CONFIG is the pad setting value like
+  pull-up for this pin. Please refer to imx6q datasheet for the valid pad
+  config settings.
+
+CONFIG bits definition:
+PAD_CTL_HYS                     (1 << 16)
+PAD_CTL_PUS_100K_DOWN           (0 << 14)
+PAD_CTL_PUS_47K_UP              (1 << 14)
+PAD_CTL_PUS_100K_UP             (2 << 14)
+PAD_CTL_PUS_22K_UP              (3 << 14)
+PAD_CTL_PUE                     (1 << 13)
+PAD_CTL_PKE                     (1 << 12)
+PAD_CTL_ODE                     (1 << 11)
+PAD_CTL_SPEED_LOW               (1 << 6)
+PAD_CTL_SPEED_MED               (2 << 6)
+PAD_CTL_SPEED_HIGH              (3 << 6)
+PAD_CTL_DSE_DISABLE             (0 << 3)
+PAD_CTL_DSE_240ohm              (1 << 3)
+PAD_CTL_DSE_120ohm              (2 << 3)
+PAD_CTL_DSE_80ohm               (3 << 3)
+PAD_CTL_DSE_60ohm               (4 << 3)
+PAD_CTL_DSE_48ohm               (5 << 3)
+PAD_CTL_DSE_40ohm               (6 << 3)
+PAD_CTL_DSE_34ohm               (7 << 3)
+PAD_CTL_SRE_FAST                (1 << 0)
+PAD_CTL_SRE_SLOW                (0 << 0)
+
+See below for available PIN_FUNC_ID for imx6q:
+MX6Q_PAD_SD2_DAT1__USDHC2_DAT1                 0
+MX6Q_PAD_SD2_DAT1__ECSPI5_SS0                  1
+MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2              2
+MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS            3
+MX6Q_PAD_SD2_DAT1__KPP_COL_7                   4
+MX6Q_PAD_SD2_DAT1__GPIO_1_14                   5
+MX6Q_PAD_SD2_DAT1__CCM_WAIT                    6
+MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0              7
+MX6Q_PAD_SD2_DAT2__USDHC2_DAT2                 8
+MX6Q_PAD_SD2_DAT2__ECSPI5_SS1                  9
+MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3              10
+MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD             11
+MX6Q_PAD_SD2_DAT2__KPP_ROW_6                   12
+MX6Q_PAD_SD2_DAT2__GPIO_1_13                   13
+MX6Q_PAD_SD2_DAT2__CCM_STOP                    14
+MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1              15
+MX6Q_PAD_SD2_DAT0__USDHC2_DAT0                 16
+MX6Q_PAD_SD2_DAT0__ECSPI5_MISO                 17
+MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD             18
+MX6Q_PAD_SD2_DAT0__KPP_ROW_7                   19
+MX6Q_PAD_SD2_DAT0__GPIO_1_15                   20
+MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT              21
+MX6Q_PAD_SD2_DAT0__TESTO_2                     22
+MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA             23
+MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC             24
+MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK         25
+MX6Q_PAD_RGMII_TXC__GPIO_6_19                  26
+MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0                27
+MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT             28
+MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY                29
+MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0             30
+MX6Q_PAD_RGMII_TD0__GPIO_6_20                  31
+MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1                32
+MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG                33
+MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1             34
+MX6Q_PAD_RGMII_TD1__GPIO_6_21                  35
+MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2                36
+MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP               37
+MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA                38
+MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2             39
+MX6Q_PAD_RGMII_TD2__GPIO_6_22                  40
+MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3                41
+MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP               42
+MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK                43
+MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3             44
+MX6Q_PAD_RGMII_TD3__GPIO_6_23                  45
+MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4                46
+MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA          47
+MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL            48
+MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24               49
+MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5          50
+MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY                51
+MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0             52
+MX6Q_PAD_RGMII_RD0__GPIO_6_25                  53
+MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6                54
+MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE                55
+MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL            56
+MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26               57
+MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7          58
+MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT          59
+MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL                60
+MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1             61
+MX6Q_PAD_RGMII_RD1__GPIO_6_27                  62
+MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8                63
+MX6Q_PAD_RGMII_RD1__SJC_FAIL                   64
+MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA                65
+MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2             66
+MX6Q_PAD_RGMII_RD2__GPIO_6_28                  67
+MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9                68
+MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK                69
+MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3             70
+MX6Q_PAD_RGMII_RD3__GPIO_6_29                  71
+MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10                72
+MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE           73
+MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC             74
+MX6Q_PAD_RGMII_RXC__GPIO_6_30                  75
+MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11                76
+MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25               77
+MX6Q_PAD_EIM_A25__ECSPI4_SS1                   78
+MX6Q_PAD_EIM_A25__ECSPI2_RDY                   79
+MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12               80
+MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS               81
+MX6Q_PAD_EIM_A25__GPIO_5_2                     82
+MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE             83
+MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0          84
+MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2               85
+MX6Q_PAD_EIM_EB2__ECSPI1_SS0                   86
+MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK              87
+MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19               88
+MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL              89
+MX6Q_PAD_EIM_EB2__GPIO_2_30                    90
+MX6Q_PAD_EIM_EB2__I2C2_SCL                     91
+MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30                        92
+MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16               93
+MX6Q_PAD_EIM_D16__ECSPI1_SCLK                  94
+MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5                        95
+MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18               96
+MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA              97
+MX6Q_PAD_EIM_D16__GPIO_3_16                    98
+MX6Q_PAD_EIM_D16__I2C2_SDA                     99
+MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17               100
+MX6Q_PAD_EIM_D17__ECSPI1_MISO                  101
+MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6                        102
+MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK             103
+MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT               104
+MX6Q_PAD_EIM_D17__GPIO_3_17                    105
+MX6Q_PAD_EIM_D17__I2C3_SCL                     106
+MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1          107
+MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18               108
+MX6Q_PAD_EIM_D18__ECSPI1_MOSI                  109
+MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7                        110
+MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17               111
+MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS               112
+MX6Q_PAD_EIM_D18__GPIO_3_18                    113
+MX6Q_PAD_EIM_D18__I2C3_SDA                     114
+MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2          115
+MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19               116
+MX6Q_PAD_EIM_D19__ECSPI1_SS1                   117
+MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8                        118
+MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16               119
+MX6Q_PAD_EIM_D19__UART1_CTS                    120
+MX6Q_PAD_EIM_D19__GPIO_3_19                    121
+MX6Q_PAD_EIM_D19__EPIT1_EPITO                  122
+MX6Q_PAD_EIM_D19__PL301_PER1_HRESP             123
+MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20               124
+MX6Q_PAD_EIM_D20__ECSPI4_SS0                   125
+MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16               126
+MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15               127
+MX6Q_PAD_EIM_D20__UART1_RTS                    128
+MX6Q_PAD_EIM_D20__GPIO_3_20                    129
+MX6Q_PAD_EIM_D20__EPIT2_EPITO                  130
+MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21               131
+MX6Q_PAD_EIM_D21__ECSPI4_SCLK                  132
+MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17               133
+MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11               134
+MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC             135
+MX6Q_PAD_EIM_D21__GPIO_3_21                    136
+MX6Q_PAD_EIM_D21__I2C1_SCL                     137
+MX6Q_PAD_EIM_D21__SPDIF_IN1                    138
+MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22               139
+MX6Q_PAD_EIM_D22__ECSPI4_MISO                  140
+MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1                        141
+MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10               142
+MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR            143
+MX6Q_PAD_EIM_D22__GPIO_3_22                    144
+MX6Q_PAD_EIM_D22__SPDIF_OUT1                   145
+MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE            146
+MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23               147
+MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS               148
+MX6Q_PAD_EIM_D23__UART3_CTS                    149
+MX6Q_PAD_EIM_D23__UART1_DCD                    150
+MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN            151
+MX6Q_PAD_EIM_D23__GPIO_3_23                    152
+MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2                        153
+MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14               154
+MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3               155
+MX6Q_PAD_EIM_EB3__ECSPI4_RDY                   156
+MX6Q_PAD_EIM_EB3__UART3_RTS                    157
+MX6Q_PAD_EIM_EB3__UART1_RI                     158
+MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC              159
+MX6Q_PAD_EIM_EB3__GPIO_2_31                    160
+MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3                        161
+MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31                        162
+MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24               163
+MX6Q_PAD_EIM_D24__ECSPI4_SS2                   164
+MX6Q_PAD_EIM_D24__UART3_TXD                    165
+MX6Q_PAD_EIM_D24__ECSPI1_SS2                   166
+MX6Q_PAD_EIM_D24__ECSPI2_SS2                   167
+MX6Q_PAD_EIM_D24__GPIO_3_24                    168
+MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS             169
+MX6Q_PAD_EIM_D24__UART1_DTR                    170
+MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25               171
+MX6Q_PAD_EIM_D25__ECSPI4_SS3                   172
+MX6Q_PAD_EIM_D25__UART3_RXD                    173
+MX6Q_PAD_EIM_D25__ECSPI1_SS3                   174
+MX6Q_PAD_EIM_D25__ECSPI2_SS3                   175
+MX6Q_PAD_EIM_D25__GPIO_3_25                    176
+MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC              177
+MX6Q_PAD_EIM_D25__UART1_DSR                    178
+MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26               179
+MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11               180
+MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1                        181
+MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14               182
+MX6Q_PAD_EIM_D26__UART2_TXD                    183
+MX6Q_PAD_EIM_D26__GPIO_3_26                    184
+MX6Q_PAD_EIM_D26__IPU1_SISG_2                  185
+MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22            186
+MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27               187
+MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13               188
+MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0                        189
+MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13               190
+MX6Q_PAD_EIM_D27__UART2_RXD                    191
+MX6Q_PAD_EIM_D27__GPIO_3_27                    192
+MX6Q_PAD_EIM_D27__IPU1_SISG_3                  193
+MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23            194
+MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28               195
+MX6Q_PAD_EIM_D28__I2C1_SDA                     196
+MX6Q_PAD_EIM_D28__ECSPI4_MOSI                  197
+MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12               198
+MX6Q_PAD_EIM_D28__UART2_CTS                    199
+MX6Q_PAD_EIM_D28__GPIO_3_28                    200
+MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG                        201
+MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13               202
+MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29               203
+MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15               204
+MX6Q_PAD_EIM_D29__ECSPI4_SS0                   205
+MX6Q_PAD_EIM_D29__UART2_RTS                    206
+MX6Q_PAD_EIM_D29__GPIO_3_29                    207
+MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC              208
+MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14               209
+MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30               210
+MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21            211
+MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11               212
+MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3                        213
+MX6Q_PAD_EIM_D30__UART3_CTS                    214
+MX6Q_PAD_EIM_D30__GPIO_3_30                    215
+MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC              216
+MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0           217
+MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31               218
+MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20            219
+MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12               220
+MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2                        221
+MX6Q_PAD_EIM_D31__UART3_RTS                    222
+MX6Q_PAD_EIM_D31__GPIO_3_31                    223
+MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR             224
+MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1           225
+MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24               226
+MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19            227
+MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19               228
+MX6Q_PAD_EIM_A24__IPU2_SISG_2                  229
+MX6Q_PAD_EIM_A24__IPU1_SISG_2                  230
+MX6Q_PAD_EIM_A24__GPIO_5_4                     231
+MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2           232
+MX6Q_PAD_EIM_A24__SRC_BT_CFG_24                        233
+MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23               234
+MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18            235
+MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18               236
+MX6Q_PAD_EIM_A23__IPU2_SISG_3                  237
+MX6Q_PAD_EIM_A23__IPU1_SISG_3                  238
+MX6Q_PAD_EIM_A23__GPIO_6_6                     239
+MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3           240
+MX6Q_PAD_EIM_A23__SRC_BT_CFG_23                        241
+MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22               242
+MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17            243
+MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17               244
+MX6Q_PAD_EIM_A22__GPIO_2_16                    245
+MX6Q_PAD_EIM_A22__TPSMP_HDATA_0                        246
+MX6Q_PAD_EIM_A22__SRC_BT_CFG_22                        247
+MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21               248
+MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16            249
+MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16               250
+MX6Q_PAD_EIM_A21__RESERVED_RESERVED            251
+MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18                252
+MX6Q_PAD_EIM_A21__GPIO_2_17                    253
+MX6Q_PAD_EIM_A21__TPSMP_HDATA_1                        254
+MX6Q_PAD_EIM_A21__SRC_BT_CFG_21                        255
+MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20               256
+MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15            257
+MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15               258
+MX6Q_PAD_EIM_A20__RESERVED_RESERVED            259
+MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19                260
+MX6Q_PAD_EIM_A20__GPIO_2_18                    261
+MX6Q_PAD_EIM_A20__TPSMP_HDATA_2                        262
+MX6Q_PAD_EIM_A20__SRC_BT_CFG_20                        263
+MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19               264
+MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14            265
+MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14               266
+MX6Q_PAD_EIM_A19__RESERVED_RESERVED            267
+MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20                268
+MX6Q_PAD_EIM_A19__GPIO_2_19                    269
+MX6Q_PAD_EIM_A19__TPSMP_HDATA_3                        270
+MX6Q_PAD_EIM_A19__SRC_BT_CFG_19                        271
+MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18               272
+MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13            273
+MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13               274
+MX6Q_PAD_EIM_A18__RESERVED_RESERVED            275
+MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21                276
+MX6Q_PAD_EIM_A18__GPIO_2_20                    277
+MX6Q_PAD_EIM_A18__TPSMP_HDATA_4                        278
+MX6Q_PAD_EIM_A18__SRC_BT_CFG_18                        279
+MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17               280
+MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12            281
+MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12               282
+MX6Q_PAD_EIM_A17__RESERVED_RESERVED            283
+MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22                284
+MX6Q_PAD_EIM_A17__GPIO_2_21                    285
+MX6Q_PAD_EIM_A17__TPSMP_HDATA_5                        286
+MX6Q_PAD_EIM_A17__SRC_BT_CFG_17                        287
+MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16               288
+MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK            289
+MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK             290
+MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23                291
+MX6Q_PAD_EIM_A16__GPIO_2_22                    292
+MX6Q_PAD_EIM_A16__TPSMP_HDATA_6                        293
+MX6Q_PAD_EIM_A16__SRC_BT_CFG_16                        294
+MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0               295
+MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5                        296
+MX6Q_PAD_EIM_CS0__ECSPI2_SCLK                  297
+MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24                298
+MX6Q_PAD_EIM_CS0__GPIO_2_23                    299
+MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7                        300
+MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1               301
+MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6                        302
+MX6Q_PAD_EIM_CS1__ECSPI2_MOSI                  303
+MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25                304
+MX6Q_PAD_EIM_CS1__GPIO_2_24                    305
+MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8                        306
+MX6Q_PAD_EIM_OE__WEIM_WEIM_OE                  307
+MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7                 308
+MX6Q_PAD_EIM_OE__ECSPI2_MISO                   309
+MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26         310
+MX6Q_PAD_EIM_OE__GPIO_2_25                     311
+MX6Q_PAD_EIM_OE__TPSMP_HDATA_9                 312
+MX6Q_PAD_EIM_RW__WEIM_WEIM_RW                  313
+MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8                 314
+MX6Q_PAD_EIM_RW__ECSPI2_SS0                    315
+MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27         316
+MX6Q_PAD_EIM_RW__GPIO_2_26                     317
+MX6Q_PAD_EIM_RW__TPSMP_HDATA_10                        318
+MX6Q_PAD_EIM_RW__SRC_BT_CFG_29                 319
+MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA                        320
+MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17               321
+MX6Q_PAD_EIM_LBA__ECSPI2_SS1                   322
+MX6Q_PAD_EIM_LBA__GPIO_2_27                    323
+MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11               324
+MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26                        325
+MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0               326
+MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11            327
+MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11               328
+MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0         329
+MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY                 330
+MX6Q_PAD_EIM_EB0__GPIO_2_28                    331
+MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12               332
+MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27                        333
+MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1               334
+MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10            335
+MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10               336
+MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1                337
+MX6Q_PAD_EIM_EB1__GPIO_2_29                    338
+MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13               339
+MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28                        340
+MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0             341
+MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9             342
+MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9                        343
+MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2                344
+MX6Q_PAD_EIM_DA0__GPIO_3_0                     345
+MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14               346
+MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0                 347
+MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1             348
+MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8             349
+MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8                        350
+MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3         351
+MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE           352
+MX6Q_PAD_EIM_DA1__GPIO_3_1                     353
+MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15               354
+MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1                 355
+MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2             356
+MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7             357
+MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7                        358
+MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4         359
+MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE           360
+MX6Q_PAD_EIM_DA2__GPIO_3_2                     361
+MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16               362
+MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2                 363
+MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3             364
+MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6             365
+MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6                        366
+MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5         367
+MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ               368
+MX6Q_PAD_EIM_DA3__GPIO_3_3                     369
+MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17               370
+MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3                 371
+MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4             372
+MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5             373
+MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5                        374
+MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6         375
+MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN         376
+MX6Q_PAD_EIM_DA4__GPIO_3_4                     377
+MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18               378
+MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4                 379
+MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5             380
+MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4             381
+MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4                        382
+MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7         383
+MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP         384
+MX6Q_PAD_EIM_DA5__GPIO_3_5                     385
+MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19               386
+MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5                 387
+MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6             388
+MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3             389
+MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3                        390
+MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8         391
+MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN         392
+MX6Q_PAD_EIM_DA6__GPIO_3_6                     393
+MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20               394
+MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6                 395
+MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7             396
+MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2             397
+MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2                        398
+MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9         399
+MX6Q_PAD_EIM_DA7__GPIO_3_7                     400
+MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21               401
+MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7                 402
+MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8             403
+MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1             404
+MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1                        405
+MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10                406
+MX6Q_PAD_EIM_DA8__GPIO_3_8                     407
+MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22               408
+MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8                 409
+MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9             410
+MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0             411
+MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0                        412
+MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11                413
+MX6Q_PAD_EIM_DA9__GPIO_3_9                     414
+MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23               415
+MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9                 416
+MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10           417
+MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15              418
+MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN           419
+MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12                420
+MX6Q_PAD_EIM_DA10__GPIO_3_10                   421
+MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24              422
+MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10               423
+MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11           424
+MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2               425
+MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC             426
+MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13                427
+MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6          428
+MX6Q_PAD_EIM_DA11__GPIO_3_11                   429
+MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25              430
+MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11               431
+MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12           432
+MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3               433
+MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC             434
+MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14                435
+MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3                436
+MX6Q_PAD_EIM_DA12__GPIO_3_12                   437
+MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26              438
+MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12               439
+MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13           440
+MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS              441
+MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK             442
+MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15                443
+MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4                444
+MX6Q_PAD_EIM_DA13__GPIO_3_13                   445
+MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27              446
+MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13               447
+MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14           448
+MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS              449
+MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK             450
+MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16                451
+MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5                452
+MX6Q_PAD_EIM_DA14__GPIO_3_14                   453
+MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28              454
+MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14               455
+MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15           456
+MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1               457
+MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4               458
+MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17                459
+MX6Q_PAD_EIM_DA15__GPIO_3_15                   460
+MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29              461
+MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15               462
+MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT              463
+MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B           464
+MX6Q_PAD_EIM_WAIT__GPIO_5_0                    465
+MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30              466
+MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25               467
+MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK              468
+MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16              469
+MX6Q_PAD_EIM_BCLK__GPIO_6_31                   470
+MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31              471
+MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK                472
+MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK                473
+MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28                474
+MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0                475
+MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16               476
+MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0            477
+MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15             478
+MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15             479
+MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC            480
+MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29                481
+MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1                482
+MX6Q_PAD_DI0_PIN15__GPIO_4_17                  483
+MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1          484
+MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2               485
+MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2               486
+MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD             487
+MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30         488
+MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2         489
+MX6Q_PAD_DI0_PIN2__GPIO_4_18                   490
+MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2                        491
+MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9          492
+MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3               493
+MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3               494
+MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS            495
+MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31                496
+MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3         497
+MX6Q_PAD_DI0_PIN3__GPIO_4_19                   498
+MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3           499
+MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10         500
+MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4               501
+MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4               502
+MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD             503
+MX6Q_PAD_DI0_PIN4__USDHC1_WP                   504
+MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD            505
+MX6Q_PAD_DI0_PIN4__GPIO_4_20                   506
+MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4           507
+MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11         508
+MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0          509
+MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0          510
+MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK               511
+MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0                512
+MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN         513
+MX6Q_PAD_DISP0_DAT0__GPIO_4_21                 514
+MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5         515
+MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1          516
+MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1          517
+MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI               518
+MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1                519
+MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL                520
+MX6Q_PAD_DISP0_DAT1__GPIO_4_22                 521
+MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6              522
+MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12                523
+MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2          524
+MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2          525
+MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO               526
+MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2                527
+MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE           528
+MX6Q_PAD_DISP0_DAT2__GPIO_4_23                 529
+MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7              530
+MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13                531
+MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3          532
+MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3          533
+MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0                        534
+MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3                535
+MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR                536
+MX6Q_PAD_DISP0_DAT3__GPIO_4_24                 537
+MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8           538
+MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14                539
+MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4          540
+MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4          541
+MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1                        542
+MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4                543
+MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB                544
+MX6Q_PAD_DISP0_DAT4__GPIO_4_25                 545
+MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9         546
+MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15                547
+MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5          548
+MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5          549
+MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2                        550
+MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS          551
+MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS                552
+MX6Q_PAD_DISP0_DAT5__GPIO_4_26                 553
+MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10             554
+MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16                555
+MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6          556
+MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6          557
+MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3                        558
+MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC           559
+MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT                560
+MX6Q_PAD_DISP0_DAT6__GPIO_4_27                 561
+MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11             562
+MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17                563
+MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7          564
+MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7          565
+MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY                        566
+MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5                567
+MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0                568
+MX6Q_PAD_DISP0_DAT7__GPIO_4_28                 569
+MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12             570
+MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18                571
+MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8          572
+MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8          573
+MX6Q_PAD_DISP0_DAT8__PWM1_PWMO                 574
+MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B              575
+MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1                576
+MX6Q_PAD_DISP0_DAT8__GPIO_4_29                 577
+MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13             578
+MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19                579
+MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9          580
+MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9          581
+MX6Q_PAD_DISP0_DAT9__PWM2_PWMO                 582
+MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B              583
+MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2                584
+MX6Q_PAD_DISP0_DAT9__GPIO_4_30                 585
+MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14             586
+MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20                587
+MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10                588
+MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10                589
+MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6             590
+MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3                591
+MX6Q_PAD_DISP0_DAT10__GPIO_4_31                        592
+MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15            593
+MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21                594
+MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11                595
+MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11                596
+MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7                597
+MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4                598
+MX6Q_PAD_DISP0_DAT11__GPIO_5_5                 599
+MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16            600
+MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22                601
+MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12                602
+MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12                603
+MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED                604
+MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5                605
+MX6Q_PAD_DISP0_DAT12__GPIO_5_6                 606
+MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17            607
+MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23                608
+MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13                609
+MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13                610
+MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS         611
+MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0                612
+MX6Q_PAD_DISP0_DAT13__GPIO_5_7                 613
+MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18            614
+MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24                615
+MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14                616
+MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14                617
+MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC          618
+MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1                619
+MX6Q_PAD_DISP0_DAT14__GPIO_5_8                 620
+MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19            621
+MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15                622
+MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15                623
+MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1               624
+MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1               625
+MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2                626
+MX6Q_PAD_DISP0_DAT15__GPIO_5_9                 627
+MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20            628
+MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25                629
+MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16                630
+MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16                631
+MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI              632
+MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC          633
+MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0         634
+MX6Q_PAD_DISP0_DAT16__GPIO_5_10                        635
+MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21            636
+MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26                637
+MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17                638
+MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17                639
+MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO              640
+MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD          641
+MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1         642
+MX6Q_PAD_DISP0_DAT17__GPIO_5_11                        643
+MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22            644
+MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27                645
+MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18                646
+MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18                647
+MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0               648
+MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS         649
+MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS         650
+MX6Q_PAD_DISP0_DAT18__GPIO_5_12                        651
+MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23            652
+MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2           653
+MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19                654
+MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19                655
+MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK              656
+MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD          657
+MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC          658
+MX6Q_PAD_DISP0_DAT19__GPIO_5_13                        659
+MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24            660
+MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3           661
+MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20                662
+MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20                663
+MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK              664
+MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC          665
+MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7                666
+MX6Q_PAD_DISP0_DAT20__GPIO_5_14                        667
+MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25            668
+MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28                669
+MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21                670
+MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21                671
+MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI              672
+MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD          673
+MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0                674
+MX6Q_PAD_DISP0_DAT21__GPIO_5_15                        675
+MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26            676
+MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29                677
+MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22                678
+MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22                679
+MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO              680
+MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS         681
+MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1                682
+MX6Q_PAD_DISP0_DAT22__GPIO_5_16                        683
+MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27            684
+MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30                685
+MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23                686
+MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23                687
+MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0               688
+MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD          689
+MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2                690
+MX6Q_PAD_DISP0_DAT23__GPIO_5_17                        691
+MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28            692
+MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31                693
+MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED          694
+MX6Q_PAD_ENET_MDIO__ENET_MDIO                  695
+MX6Q_PAD_ENET_MDIO__ESAI1_SCKR                 696
+MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3                697
+MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT         698
+MX6Q_PAD_ENET_MDIO__GPIO_1_22                  699
+MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK                        700
+MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED         701
+MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK             702
+MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR               703
+MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4                704
+MX6Q_PAD_ENET_REF_CLK__GPIO_1_23               705
+MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK             706
+MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH          707
+MX6Q_PAD_ENET_RX_ER__ENET_RX_ER                        708
+MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR                        709
+MX6Q_PAD_ENET_RX_ER__SPDIF_IN1                 710
+MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT                711
+MX6Q_PAD_ENET_RX_ER__GPIO_1_24                 712
+MX6Q_PAD_ENET_RX_ER__PHY_TDI                   713
+MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD         714
+MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED          715
+MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN               716
+MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT               717
+MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK             718
+MX6Q_PAD_ENET_CRS_DV__GPIO_1_25                        719
+MX6Q_PAD_ENET_CRS_DV__PHY_TDO                  720
+MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD                721
+MX6Q_PAD_ENET_RXD1__MLB_MLBSIG                 722
+MX6Q_PAD_ENET_RXD1__ENET_RDATA_1               723
+MX6Q_PAD_ENET_RXD1__ESAI1_FST                  724
+MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT         725
+MX6Q_PAD_ENET_RXD1__GPIO_1_26                  726
+MX6Q_PAD_ENET_RXD1__PHY_TCK                    727
+MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON          728
+MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT             729
+MX6Q_PAD_ENET_RXD0__ENET_RDATA_0               730
+MX6Q_PAD_ENET_RXD0__ESAI1_HCKT                 731
+MX6Q_PAD_ENET_RXD0__SPDIF_OUT1                 732
+MX6Q_PAD_ENET_RXD0__GPIO_1_27                  733
+MX6Q_PAD_ENET_RXD0__PHY_TMS                    734
+MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV                735
+MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED           736
+MX6Q_PAD_ENET_TX_EN__ENET_TX_EN                        737
+MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2             738
+MX6Q_PAD_ENET_TX_EN__GPIO_1_28                 739
+MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI              740
+MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH            741
+MX6Q_PAD_ENET_TXD1__MLB_MLBCLK                 742
+MX6Q_PAD_ENET_TXD1__ENET_TDATA_1               743
+MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3              744
+MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN                745
+MX6Q_PAD_ENET_TXD1__GPIO_1_29                  746
+MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO               747
+MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD          748
+MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED            749
+MX6Q_PAD_ENET_TXD0__ENET_TDATA_0               750
+MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1              751
+MX6Q_PAD_ENET_TXD0__GPIO_1_30                  752
+MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK               753
+MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD          754
+MX6Q_PAD_ENET_MDC__MLB_MLBDAT                  755
+MX6Q_PAD_ENET_MDC__ENET_MDC                    756
+MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0               757
+MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN         758
+MX6Q_PAD_ENET_MDC__GPIO_1_31                   759
+MX6Q_PAD_ENET_MDC__SATA_PHY_TMS                        760
+MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON           761
+MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40              762
+MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41              763
+MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42              764
+MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43              765
+MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44              766
+MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45              767
+MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46              768
+MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47              769
+MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5          770
+MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5            771
+MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32              772
+MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33              773
+MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34              774
+MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35              775
+MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36              776
+MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37              777
+MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38              778
+MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39              779
+MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4            780
+MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4          781
+MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24              782
+MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25              783
+MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26              784
+MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27              785
+MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28              786
+MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29              787
+MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3          788
+MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30              789
+MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31              790
+MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3            791
+MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16              792
+MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17              793
+MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18              794
+MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19              795
+MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20              796
+MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21              797
+MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22              798
+MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2          799
+MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23              800
+MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2            801
+MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0                        802
+MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1                        803
+MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2                        804
+MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3                        805
+MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4                        806
+MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5                        807
+MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6                        808
+MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7                        809
+MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8                        810
+MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9                        811
+MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10              812
+MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11              813
+MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12              814
+MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13              815
+MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14              816
+MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15              817
+MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS               818
+MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0              819
+MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1              820
+MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS               821
+MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET           822
+MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0          823
+MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1          824
+MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0                825
+MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2          826
+MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0                827
+MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1                828
+MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1                829
+MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0          830
+MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1          831
+MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE             832
+MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0                        833
+MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1                        834
+MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2                        835
+MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3                        836
+MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4                        837
+MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5                        838
+MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0          839
+MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6                        840
+MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7                        841
+MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0            842
+MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8                        843
+MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9                        844
+MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10              845
+MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11              846
+MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12              847
+MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13              848
+MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14              849
+MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1          850
+MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15              851
+MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1            852
+MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48              853
+MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49              854
+MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50              855
+MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51              856
+MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52              857
+MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53              858
+MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54              859
+MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55              860
+MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6          861
+MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6            862
+MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56              863
+MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7          864
+MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57              865
+MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58              866
+MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59              867
+MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60              868
+MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7            869
+MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61              870
+MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62              871
+MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63              872
+MX6Q_PAD_KEY_COL0__ECSPI1_SCLK                 873
+MX6Q_PAD_KEY_COL0__ENET_RDATA_3                        874
+MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC             875
+MX6Q_PAD_KEY_COL0__KPP_COL_0                   876
+MX6Q_PAD_KEY_COL0__UART4_TXD                   877
+MX6Q_PAD_KEY_COL0__GPIO_4_6                    878
+MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT              879
+MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST              880
+MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI                 881
+MX6Q_PAD_KEY_ROW0__ENET_TDATA_3                        882
+MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD             883
+MX6Q_PAD_KEY_ROW0__KPP_ROW_0                   884
+MX6Q_PAD_KEY_ROW0__UART4_RXD                   885
+MX6Q_PAD_KEY_ROW0__GPIO_4_7                    886
+MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT              887
+MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0           888
+MX6Q_PAD_KEY_COL1__ECSPI1_MISO                 889
+MX6Q_PAD_KEY_COL1__ENET_MDIO                   890
+MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS            891
+MX6Q_PAD_KEY_COL1__KPP_COL_1                   892
+MX6Q_PAD_KEY_COL1__UART5_TXD                   893
+MX6Q_PAD_KEY_COL1__GPIO_4_8                    894
+MX6Q_PAD_KEY_COL1__USDHC1_VSELECT              895
+MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1         896
+MX6Q_PAD_KEY_ROW1__ECSPI1_SS0                  897
+MX6Q_PAD_KEY_ROW1__ENET_COL                    898
+MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD             899
+MX6Q_PAD_KEY_ROW1__KPP_ROW_1                   900
+MX6Q_PAD_KEY_ROW1__UART5_RXD                   901
+MX6Q_PAD_KEY_ROW1__GPIO_4_9                    902
+MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT              903
+MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2          904
+MX6Q_PAD_KEY_COL2__ECSPI1_SS1                  905
+MX6Q_PAD_KEY_COL2__ENET_RDATA_2                        906
+MX6Q_PAD_KEY_COL2__CAN1_TXCAN                  907
+MX6Q_PAD_KEY_COL2__KPP_COL_2                   908
+MX6Q_PAD_KEY_COL2__ENET_MDC                    909
+MX6Q_PAD_KEY_COL2__GPIO_4_10                   910
+MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP                911
+MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3          912
+MX6Q_PAD_KEY_ROW2__ECSPI1_SS2                  913
+MX6Q_PAD_KEY_ROW2__ENET_TDATA_2                        914
+MX6Q_PAD_KEY_ROW2__CAN1_RXCAN                  915
+MX6Q_PAD_KEY_ROW2__KPP_ROW_2                   916
+MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT              917
+MX6Q_PAD_KEY_ROW2__GPIO_4_11                   918
+MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE            919
+MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4           920
+MX6Q_PAD_KEY_COL3__ECSPI1_SS3                  921
+MX6Q_PAD_KEY_COL3__ENET_CRS                    922
+MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL             923
+MX6Q_PAD_KEY_COL3__KPP_COL_3                   924
+MX6Q_PAD_KEY_COL3__I2C2_SCL                    925
+MX6Q_PAD_KEY_COL3__GPIO_4_12                   926
+MX6Q_PAD_KEY_COL3__SPDIF_IN1                   927
+MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5           928
+MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT              929
+MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK           930
+MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA             931
+MX6Q_PAD_KEY_ROW3__KPP_ROW_3                   932
+MX6Q_PAD_KEY_ROW3__I2C2_SDA                    933
+MX6Q_PAD_KEY_ROW3__GPIO_4_13                   934
+MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT              935
+MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6           936
+MX6Q_PAD_KEY_COL4__CAN2_TXCAN                  937
+MX6Q_PAD_KEY_COL4__IPU1_SISG_4                 938
+MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC            939
+MX6Q_PAD_KEY_COL4__KPP_COL_4                   940
+MX6Q_PAD_KEY_COL4__UART5_RTS                   941
+MX6Q_PAD_KEY_COL4__GPIO_4_14                   942
+MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49               943
+MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7          944
+MX6Q_PAD_KEY_ROW4__CAN2_RXCAN                  945
+MX6Q_PAD_KEY_ROW4__IPU1_SISG_5                 946
+MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR           947
+MX6Q_PAD_KEY_ROW4__KPP_ROW_4                   948
+MX6Q_PAD_KEY_ROW4__UART5_CTS                   949
+MX6Q_PAD_KEY_ROW4__GPIO_4_15                   950
+MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50               951
+MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8           952
+MX6Q_PAD_GPIO_0__CCM_CLKO                      953
+MX6Q_PAD_GPIO_0__KPP_COL_5                     954
+MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK             955
+MX6Q_PAD_GPIO_0__EPIT1_EPITO                   956
+MX6Q_PAD_GPIO_0__GPIO_1_0                      957
+MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR              958
+MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5                959
+MX6Q_PAD_GPIO_1__ESAI1_SCKR                    960
+MX6Q_PAD_GPIO_1__WDOG2_WDOG_B                  961
+MX6Q_PAD_GPIO_1__KPP_ROW_5                     962
+MX6Q_PAD_GPIO_1__PWM2_PWMO                     963
+MX6Q_PAD_GPIO_1__GPIO_1_1                      964
+MX6Q_PAD_GPIO_1__USDHC1_CD                     965
+MX6Q_PAD_GPIO_1__SRC_TESTER_ACK                        966
+MX6Q_PAD_GPIO_9__ESAI1_FSR                     967
+MX6Q_PAD_GPIO_9__WDOG1_WDOG_B                  968
+MX6Q_PAD_GPIO_9__KPP_COL_6                     969
+MX6Q_PAD_GPIO_9__CCM_REF_EN_B                  970
+MX6Q_PAD_GPIO_9__PWM1_PWMO                     971
+MX6Q_PAD_GPIO_9__GPIO_1_9                      972
+MX6Q_PAD_GPIO_9__USDHC1_WP                     973
+MX6Q_PAD_GPIO_9__SRC_EARLY_RST                 974
+MX6Q_PAD_GPIO_3__ESAI1_HCKR                    975
+MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0          976
+MX6Q_PAD_GPIO_3__I2C3_SCL                      977
+MX6Q_PAD_GPIO_3__ANATOP_24M_OUT                        978
+MX6Q_PAD_GPIO_3__CCM_CLKO2                     979
+MX6Q_PAD_GPIO_3__GPIO_1_3                      980
+MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC               981
+MX6Q_PAD_GPIO_3__MLB_MLBCLK                    982
+MX6Q_PAD_GPIO_6__ESAI1_SCKT                    983
+MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1          984
+MX6Q_PAD_GPIO_6__I2C3_SDA                      985
+MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0                 986
+MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB               987
+MX6Q_PAD_GPIO_6__GPIO_1_6                      988
+MX6Q_PAD_GPIO_6__USDHC2_LCTL                   989
+MX6Q_PAD_GPIO_6__MLB_MLBSIG                    990
+MX6Q_PAD_GPIO_2__ESAI1_FST                     991
+MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2          992
+MX6Q_PAD_GPIO_2__KPP_ROW_6                     993
+MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1                 994
+MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0           995
+MX6Q_PAD_GPIO_2__GPIO_1_2                      996
+MX6Q_PAD_GPIO_2__USDHC2_WP                     997
+MX6Q_PAD_GPIO_2__MLB_MLBDAT                    998
+MX6Q_PAD_GPIO_4__ESAI1_HCKT                    999
+MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3          1000
+MX6Q_PAD_GPIO_4__KPP_COL_7                     1001
+MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2                 1002
+MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1           1003
+MX6Q_PAD_GPIO_4__GPIO_1_4                      1004
+MX6Q_PAD_GPIO_4__USDHC2_CD                     1005
+MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA                1006
+MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3                 1007
+MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4          1008
+MX6Q_PAD_GPIO_5__KPP_ROW_7                     1009
+MX6Q_PAD_GPIO_5__CCM_CLKO                      1010
+MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2           1011
+MX6Q_PAD_GPIO_5__GPIO_1_5                      1012
+MX6Q_PAD_GPIO_5__I2C3_SCL                      1013
+MX6Q_PAD_GPIO_5__CHEETAH_EVENTI                        1014
+MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1                 1015
+MX6Q_PAD_GPIO_7__ECSPI5_RDY                    1016
+MX6Q_PAD_GPIO_7__EPIT1_EPITO                   1017
+MX6Q_PAD_GPIO_7__CAN1_TXCAN                    1018
+MX6Q_PAD_GPIO_7__UART2_TXD                     1019
+MX6Q_PAD_GPIO_7__GPIO_1_7                      1020
+MX6Q_PAD_GPIO_7__SPDIF_PLOCK                   1021
+MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE                1022
+MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0                 1023
+MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT         1024
+MX6Q_PAD_GPIO_8__EPIT2_EPITO                   1025
+MX6Q_PAD_GPIO_8__CAN1_RXCAN                    1026
+MX6Q_PAD_GPIO_8__UART2_RXD                     1027
+MX6Q_PAD_GPIO_8__GPIO_1_8                      1028
+MX6Q_PAD_GPIO_8__SPDIF_SRCLK                   1029
+MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK         1030
+MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2                        1031
+MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN          1032
+MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT                1033
+MX6Q_PAD_GPIO_16__USDHC1_LCTL                  1034
+MX6Q_PAD_GPIO_16__SPDIF_IN1                    1035
+MX6Q_PAD_GPIO_16__GPIO_7_11                    1036
+MX6Q_PAD_GPIO_16__I2C3_SDA                     1037
+MX6Q_PAD_GPIO_16__SJC_DE_B                     1038
+MX6Q_PAD_GPIO_17__ESAI1_TX0                    1039
+MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN          1040
+MX6Q_PAD_GPIO_17__CCM_PMIC_RDY                 1041
+MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0                1042
+MX6Q_PAD_GPIO_17__SPDIF_OUT1                   1043
+MX6Q_PAD_GPIO_17__GPIO_7_12                    1044
+MX6Q_PAD_GPIO_17__SJC_JTAG_ACT                 1045
+MX6Q_PAD_GPIO_18__ESAI1_TX1                    1046
+MX6Q_PAD_GPIO_18__ENET_RX_CLK                  1047
+MX6Q_PAD_GPIO_18__USDHC3_VSELECT               1048
+MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1                1049
+MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK            1050
+MX6Q_PAD_GPIO_18__GPIO_7_13                    1051
+MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5                1052
+MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST               1053
+MX6Q_PAD_GPIO_19__KPP_COL_5                    1054
+MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT         1055
+MX6Q_PAD_GPIO_19__SPDIF_OUT1                   1056
+MX6Q_PAD_GPIO_19__CCM_CLKO                     1057
+MX6Q_PAD_GPIO_19__ECSPI1_RDY                   1058
+MX6Q_PAD_GPIO_19__GPIO_4_5                     1059
+MX6Q_PAD_GPIO_19__ENET_TX_ER                   1060
+MX6Q_PAD_GPIO_19__SRC_INT_BOOT                 1061
+MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK         1062
+MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12         1063
+MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0          1064
+MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18                        1065
+MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29           1066
+MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO           1067
+MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC            1068
+MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13           1069
+MX6Q_PAD_CSI0_MCLK__CCM_CLKO                   1070
+MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1            1071
+MX6Q_PAD_CSI0_MCLK__GPIO_5_19                  1072
+MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30         1073
+MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL              1074
+MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN         1075
+MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0           1076
+MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14                1077
+MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2         1078
+MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20               1079
+MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31           1080
+MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK           1081
+MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC           1082
+MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1             1083
+MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15          1084
+MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3           1085
+MX6Q_PAD_CSI0_VSYNC__GPIO_5_21                 1086
+MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32             1087
+MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0           1088
+MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4              1089
+MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2              1090
+MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK                        1091
+MX6Q_PAD_CSI0_DAT4__KPP_COL_5                  1092
+MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC            1093
+MX6Q_PAD_CSI0_DAT4__GPIO_5_22                  1094
+MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43              1095
+MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1            1096
+MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5              1097
+MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3              1098
+MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI                        1099
+MX6Q_PAD_CSI0_DAT5__KPP_ROW_5                  1100
+MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD            1101
+MX6Q_PAD_CSI0_DAT5__GPIO_5_23                  1102
+MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44         1103
+MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2            1104
+MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6              1105
+MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4              1106
+MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO                        1107
+MX6Q_PAD_CSI0_DAT6__KPP_COL_6                  1108
+MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS           1109
+MX6Q_PAD_CSI0_DAT6__GPIO_5_24                  1110
+MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45         1111
+MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3            1112
+MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7              1113
+MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5              1114
+MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0                 1115
+MX6Q_PAD_CSI0_DAT7__KPP_ROW_6                  1116
+MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD            1117
+MX6Q_PAD_CSI0_DAT7__GPIO_5_25                  1118
+MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46         1119
+MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4            1120
+MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8              1121
+MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6              1122
+MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK                        1123
+MX6Q_PAD_CSI0_DAT8__KPP_COL_7                  1124
+MX6Q_PAD_CSI0_DAT8__I2C1_SDA                   1125
+MX6Q_PAD_CSI0_DAT8__GPIO_5_26                  1126
+MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47         1127
+MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5            1128
+MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9              1129
+MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7              1130
+MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI                        1131
+MX6Q_PAD_CSI0_DAT9__KPP_ROW_7                  1132
+MX6Q_PAD_CSI0_DAT9__I2C1_SCL                   1133
+MX6Q_PAD_CSI0_DAT9__GPIO_5_27                  1134
+MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48         1135
+MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6            1136
+MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10            1137
+MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC           1138
+MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO               1139
+MX6Q_PAD_CSI0_DAT10__UART1_TXD                 1140
+MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4           1141
+MX6Q_PAD_CSI0_DAT10__GPIO_5_28                 1142
+MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33                1143
+MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7           1144
+MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11            1145
+MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS          1146
+MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0                        1147
+MX6Q_PAD_CSI0_DAT11__UART1_RXD                 1148
+MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5           1149
+MX6Q_PAD_CSI0_DAT11__GPIO_5_29                 1150
+MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34                1151
+MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8           1152
+MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12            1153
+MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8             1154
+MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16          1155
+MX6Q_PAD_CSI0_DAT12__UART4_TXD                 1156
+MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6           1157
+MX6Q_PAD_CSI0_DAT12__GPIO_5_30                 1158
+MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35                1159
+MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9           1160
+MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13            1161
+MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9             1162
+MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17          1163
+MX6Q_PAD_CSI0_DAT13__UART4_RXD                 1164
+MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7           1165
+MX6Q_PAD_CSI0_DAT13__GPIO_5_31                 1166
+MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36                1167
+MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10          1168
+MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14            1169
+MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10            1170
+MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18          1171
+MX6Q_PAD_CSI0_DAT14__UART5_TXD                 1172
+MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8           1173
+MX6Q_PAD_CSI0_DAT14__GPIO_6_0                  1174
+MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37                1175
+MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11          1176
+MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15            1177
+MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11            1178
+MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19          1179
+MX6Q_PAD_CSI0_DAT15__UART5_RXD                 1180
+MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9           1181
+MX6Q_PAD_CSI0_DAT15__GPIO_6_1                  1182
+MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38                1183
+MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12          1184
+MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16            1185
+MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12            1186
+MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20          1187
+MX6Q_PAD_CSI0_DAT16__UART4_RTS                 1188
+MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10          1189
+MX6Q_PAD_CSI0_DAT16__GPIO_6_2                  1190
+MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39                1191
+MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13          1192
+MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17            1193
+MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13            1194
+MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21          1195
+MX6Q_PAD_CSI0_DAT17__UART4_CTS                 1196
+MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11          1197
+MX6Q_PAD_CSI0_DAT17__GPIO_6_3                  1198
+MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40                1199
+MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14          1200
+MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18            1201
+MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14            1202
+MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22          1203
+MX6Q_PAD_CSI0_DAT18__UART5_RTS                 1204
+MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12          1205
+MX6Q_PAD_CSI0_DAT18__GPIO_6_4                  1206
+MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41                1207
+MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15          1208
+MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19            1209
+MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15            1210
+MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23          1211
+MX6Q_PAD_CSI0_DAT19__UART5_CTS                 1212
+MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13          1213
+MX6Q_PAD_CSI0_DAT19__GPIO_6_5                  1214
+MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42                1215
+MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9            1216
+MX6Q_PAD_JTAG_TMS__SJC_TMS                     1217
+MX6Q_PAD_JTAG_MOD__SJC_MOD                     1218
+MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB                 1219
+MX6Q_PAD_JTAG_TDI__SJC_TDI                     1220
+MX6Q_PAD_JTAG_TCK__SJC_TCK                     1221
+MX6Q_PAD_JTAG_TDO__SJC_TDO                     1222
+MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3            1223
+MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2            1224
+MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK            1225
+MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1            1226
+MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0            1227
+MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3            1228
+MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK            1229
+MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2            1230
+MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1            1231
+MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0            1232
+MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1         1233
+MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM                1234
+MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ                1235
+MX6Q_PAD_POR_B__SRC_POR_B                      1236
+MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1           1237
+MX6Q_PAD_RESET_IN_B__SRC_RESET_B               1238
+MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0           1239
+MX6Q_PAD_TEST_MODE__TCU_TEST_MODE              1240
+MX6Q_PAD_SD3_DAT7__USDHC3_DAT7                 1241
+MX6Q_PAD_SD3_DAT7__UART1_TXD                   1242
+MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24            1243
+MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0                1244
+MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0                1245
+MX6Q_PAD_SD3_DAT7__GPIO_6_17                   1246
+MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12                1247
+MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV            1248
+MX6Q_PAD_SD3_DAT6__USDHC3_DAT6                 1249
+MX6Q_PAD_SD3_DAT6__UART1_RXD                   1250
+MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25            1251
+MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1                1252
+MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1                1253
+MX6Q_PAD_SD3_DAT6__GPIO_6_18                   1254
+MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13                1255
+MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10             1256
+MX6Q_PAD_SD3_DAT5__USDHC3_DAT5                 1257
+MX6Q_PAD_SD3_DAT5__UART2_TXD                   1258
+MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26            1259
+MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2                1260
+MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2                1261
+MX6Q_PAD_SD3_DAT5__GPIO_7_0                    1262
+MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14                1263
+MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11             1264
+MX6Q_PAD_SD3_DAT4__USDHC3_DAT4                 1265
+MX6Q_PAD_SD3_DAT4__UART2_RXD                   1266
+MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27            1267
+MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3                1268
+MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3                1269
+MX6Q_PAD_SD3_DAT4__GPIO_7_1                    1270
+MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15                1271
+MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12             1272
+MX6Q_PAD_SD3_CMD__USDHC3_CMD                   1273
+MX6Q_PAD_SD3_CMD__UART2_CTS                    1274
+MX6Q_PAD_SD3_CMD__CAN1_TXCAN                   1275
+MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4         1276
+MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4         1277
+MX6Q_PAD_SD3_CMD__GPIO_7_2                     1278
+MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16         1279
+MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13              1280
+MX6Q_PAD_SD3_CLK__USDHC3_CLK                   1281
+MX6Q_PAD_SD3_CLK__UART2_RTS                    1282
+MX6Q_PAD_SD3_CLK__CAN1_RXCAN                   1283
+MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5         1284
+MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5         1285
+MX6Q_PAD_SD3_CLK__GPIO_7_3                     1286
+MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17         1287
+MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14              1288
+MX6Q_PAD_SD3_DAT0__USDHC3_DAT0                 1289
+MX6Q_PAD_SD3_DAT0__UART1_CTS                   1290
+MX6Q_PAD_SD3_DAT0__CAN2_TXCAN                  1291
+MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6                1292
+MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6                1293
+MX6Q_PAD_SD3_DAT0__GPIO_7_4                    1294
+MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18                1295
+MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15             1296
+MX6Q_PAD_SD3_DAT1__USDHC3_DAT1                 1297
+MX6Q_PAD_SD3_DAT1__UART1_RTS                   1298
+MX6Q_PAD_SD3_DAT1__CAN2_RXCAN                  1299
+MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7                1300
+MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7                1301
+MX6Q_PAD_SD3_DAT1__GPIO_7_5                    1302
+MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19                1303
+MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0              1304
+MX6Q_PAD_SD3_DAT2__USDHC3_DAT2                 1305
+MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28            1306
+MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8                1307
+MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8                1308
+MX6Q_PAD_SD3_DAT2__GPIO_7_6                    1309
+MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20                1310
+MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1              1311
+MX6Q_PAD_SD3_DAT3__USDHC3_DAT3                 1312
+MX6Q_PAD_SD3_DAT3__UART3_CTS                   1313
+MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29            1314
+MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9                1315
+MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9                1316
+MX6Q_PAD_SD3_DAT3__GPIO_7_7                    1317
+MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21                1318
+MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2              1319
+MX6Q_PAD_SD3_RST__USDHC3_RST                   1320
+MX6Q_PAD_SD3_RST__UART3_RTS                    1321
+MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30             1322
+MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10                1323
+MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10                1324
+MX6Q_PAD_SD3_RST__GPIO_7_8                     1325
+MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22         1326
+MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3                1327
+MX6Q_PAD_NANDF_CLE__RAWNAND_CLE                        1328
+MX6Q_PAD_NANDF_CLE__IPU2_SISG_4                        1329
+MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31           1330
+MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11                1331
+MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11                1332
+MX6Q_PAD_NANDF_CLE__GPIO_6_7                   1333
+MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23                1334
+MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0             1335
+MX6Q_PAD_NANDF_ALE__RAWNAND_ALE                        1336
+MX6Q_PAD_NANDF_ALE__USDHC4_RST                 1337
+MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0            1338
+MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12                1339
+MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12                1340
+MX6Q_PAD_NANDF_ALE__GPIO_6_8                   1341
+MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24         1342
+MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1             1343
+MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN            1344
+MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5               1345
+MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1          1346
+MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13                1347
+MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13                1348
+MX6Q_PAD_NANDF_WP_B__GPIO_6_9                  1349
+MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32                1350
+MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0                1351
+MX6Q_PAD_NANDF_RB0__RAWNAND_READY0             1352
+MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1              1353
+MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2            1354
+MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14                1355
+MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14                1356
+MX6Q_PAD_NANDF_RB0__GPIO_6_10                  1357
+MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33                1358
+MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1         1359
+MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N               1360
+MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15                1361
+MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15                1362
+MX6Q_PAD_NANDF_CS0__GPIO_6_11                  1363
+MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2         1364
+MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N               1365
+MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT             1366
+MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT             1367
+MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3            1368
+MX6Q_PAD_NANDF_CS1__GPIO_6_14                  1369
+MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT         1370
+MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N               1371
+MX6Q_PAD_NANDF_CS2__IPU1_SISG_0                        1372
+MX6Q_PAD_NANDF_CS2__ESAI1_TX0                  1373
+MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE              1374
+MX6Q_PAD_NANDF_CS2__CCM_CLKO2                  1375
+MX6Q_PAD_NANDF_CS2__GPIO_6_15                  1376
+MX6Q_PAD_NANDF_CS2__IPU2_SISG_0                        1377
+MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N               1378
+MX6Q_PAD_NANDF_CS3__IPU1_SISG_1                        1379
+MX6Q_PAD_NANDF_CS3__ESAI1_TX1                  1380
+MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26             1381
+MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4            1382
+MX6Q_PAD_NANDF_CS3__GPIO_6_16                  1383
+MX6Q_PAD_NANDF_CS3__IPU2_SISG_1                        1384
+MX6Q_PAD_NANDF_CS3__TPSMP_CLK                  1385
+MX6Q_PAD_SD4_CMD__USDHC4_CMD                   1386
+MX6Q_PAD_SD4_CMD__RAWNAND_RDN                  1387
+MX6Q_PAD_SD4_CMD__UART3_TXD                    1388
+MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5              1389
+MX6Q_PAD_SD4_CMD__GPIO_7_9                     1390
+MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR              1391
+MX6Q_PAD_SD4_CLK__USDHC4_CLK                   1392
+MX6Q_PAD_SD4_CLK__RAWNAND_WRN                  1393
+MX6Q_PAD_SD4_CLK__UART3_RXD                    1394
+MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6              1395
+MX6Q_PAD_SD4_CLK__GPIO_7_10                    1396
+MX6Q_PAD_NANDF_D0__RAWNAND_D0                  1397
+MX6Q_PAD_NANDF_D0__USDHC1_DAT4                 1398
+MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0         1399
+MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16                1400
+MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16                1401
+MX6Q_PAD_NANDF_D0__GPIO_2_0                    1402
+MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0         1403
+MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0         1404
+MX6Q_PAD_NANDF_D1__RAWNAND_D1                  1405
+MX6Q_PAD_NANDF_D1__USDHC1_DAT5                 1406
+MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1                1407
+MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17                1408
+MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17                1409
+MX6Q_PAD_NANDF_D1__GPIO_2_1                    1410
+MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1         1411
+MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1         1412
+MX6Q_PAD_NANDF_D2__RAWNAND_D2                  1413
+MX6Q_PAD_NANDF_D2__USDHC1_DAT6                 1414
+MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2         1415
+MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18                1416
+MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18                1417
+MX6Q_PAD_NANDF_D2__GPIO_2_2                    1418
+MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2         1419
+MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2         1420
+MX6Q_PAD_NANDF_D3__RAWNAND_D3                  1421
+MX6Q_PAD_NANDF_D3__USDHC1_DAT7                 1422
+MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3         1423
+MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19                1424
+MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19                1425
+MX6Q_PAD_NANDF_D3__GPIO_2_3                    1426
+MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3         1427
+MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3         1428
+MX6Q_PAD_NANDF_D4__RAWNAND_D4                  1429
+MX6Q_PAD_NANDF_D4__USDHC2_DAT4                 1430
+MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4         1431
+MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20                1432
+MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20                1433
+MX6Q_PAD_NANDF_D4__GPIO_2_4                    1434
+MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4         1435
+MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4         1436
+MX6Q_PAD_NANDF_D5__RAWNAND_D5                  1437
+MX6Q_PAD_NANDF_D5__USDHC2_DAT5                 1438
+MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5         1439
+MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21                1440
+MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21                1441
+MX6Q_PAD_NANDF_D5__GPIO_2_5                    1442
+MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5         1443
+MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5         1444
+MX6Q_PAD_NANDF_D6__RAWNAND_D6                  1445
+MX6Q_PAD_NANDF_D6__USDHC2_DAT6                 1446
+MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6         1447
+MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22                1448
+MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22                1449
+MX6Q_PAD_NANDF_D6__GPIO_2_6                    1450
+MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6         1451
+MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6         1452
+MX6Q_PAD_NANDF_D7__RAWNAND_D7                  1453
+MX6Q_PAD_NANDF_D7__USDHC2_DAT7                 1454
+MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7         1455
+MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23                1456
+MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23                1457
+MX6Q_PAD_NANDF_D7__GPIO_2_7                    1458
+MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7         1459
+MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7         1460
+MX6Q_PAD_SD4_DAT0__RAWNAND_D8                  1461
+MX6Q_PAD_SD4_DAT0__USDHC4_DAT0                 1462
+MX6Q_PAD_SD4_DAT0__RAWNAND_DQS                 1463
+MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24                1464
+MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24                1465
+MX6Q_PAD_SD4_DAT0__GPIO_2_8                    1466
+MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8         1467
+MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8         1468
+MX6Q_PAD_SD4_DAT1__RAWNAND_D9                  1469
+MX6Q_PAD_SD4_DAT1__USDHC4_DAT1                 1470
+MX6Q_PAD_SD4_DAT1__PWM3_PWMO                   1471
+MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25                1472
+MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25                1473
+MX6Q_PAD_SD4_DAT1__GPIO_2_9                    1474
+MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9         1475
+MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9         1476
+MX6Q_PAD_SD4_DAT2__RAWNAND_D10                 1477
+MX6Q_PAD_SD4_DAT2__USDHC4_DAT2                 1478
+MX6Q_PAD_SD4_DAT2__PWM4_PWMO                   1479
+MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26                1480
+MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26                1481
+MX6Q_PAD_SD4_DAT2__GPIO_2_10                   1482
+MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10                1483
+MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10                1484
+MX6Q_PAD_SD4_DAT3__RAWNAND_D11                 1485
+MX6Q_PAD_SD4_DAT3__USDHC4_DAT3                 1486
+MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27                1487
+MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27                1488
+MX6Q_PAD_SD4_DAT3__GPIO_2_11                   1489
+MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11                1490
+MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11                1491
+MX6Q_PAD_SD4_DAT4__RAWNAND_D12                 1492
+MX6Q_PAD_SD4_DAT4__USDHC4_DAT4                 1493
+MX6Q_PAD_SD4_DAT4__UART2_RXD                   1494
+MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28                1495
+MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28                1496
+MX6Q_PAD_SD4_DAT4__GPIO_2_12                   1497
+MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12                1498
+MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12                1499
+MX6Q_PAD_SD4_DAT5__RAWNAND_D13                 1500
+MX6Q_PAD_SD4_DAT5__USDHC4_DAT5                 1501
+MX6Q_PAD_SD4_DAT5__UART2_RTS                   1502
+MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29                1503
+MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29                1504
+MX6Q_PAD_SD4_DAT5__GPIO_2_13                   1505
+MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13                1506
+MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13                1507
+MX6Q_PAD_SD4_DAT6__RAWNAND_D14                 1508
+MX6Q_PAD_SD4_DAT6__USDHC4_DAT6                 1509
+MX6Q_PAD_SD4_DAT6__UART2_CTS                   1510
+MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30                1511
+MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30                1512
+MX6Q_PAD_SD4_DAT6__GPIO_2_14                   1513
+MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14                1514
+MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14                1515
+MX6Q_PAD_SD4_DAT7__RAWNAND_D15                 1516
+MX6Q_PAD_SD4_DAT7__USDHC4_DAT7                 1517
+MX6Q_PAD_SD4_DAT7__UART2_TXD                   1518
+MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31                1519
+MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31                1520
+MX6Q_PAD_SD4_DAT7__GPIO_2_15                   1521
+MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15                1522
+MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15                1523
+MX6Q_PAD_SD1_DAT1__USDHC1_DAT1                 1524
+MX6Q_PAD_SD1_DAT1__ECSPI5_SS0                  1525
+MX6Q_PAD_SD1_DAT1__PWM3_PWMO                   1526
+MX6Q_PAD_SD1_DAT1__GPT_CAPIN2                  1527
+MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7             1528
+MX6Q_PAD_SD1_DAT1__GPIO_1_17                   1529
+MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0           1530
+MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8              1531
+MX6Q_PAD_SD1_DAT0__USDHC1_DAT0                 1532
+MX6Q_PAD_SD1_DAT0__ECSPI5_MISO                 1533
+MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS                1534
+MX6Q_PAD_SD1_DAT0__GPT_CAPIN1                  1535
+MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8             1536
+MX6Q_PAD_SD1_DAT0__GPIO_1_16                   1537
+MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1           1538
+MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7              1539
+MX6Q_PAD_SD1_DAT3__USDHC1_DAT3                 1540
+MX6Q_PAD_SD1_DAT3__ECSPI5_SS2                  1541
+MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3                 1542
+MX6Q_PAD_SD1_DAT3__PWM1_PWMO                   1543
+MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B                        1544
+MX6Q_PAD_SD1_DAT3__GPIO_1_21                   1545
+MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB                1546
+MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6              1547
+MX6Q_PAD_SD1_CMD__USDHC1_CMD                   1548
+MX6Q_PAD_SD1_CMD__ECSPI5_MOSI                  1549
+MX6Q_PAD_SD1_CMD__PWM4_PWMO                    1550
+MX6Q_PAD_SD1_CMD__GPT_CMPOUT1                  1551
+MX6Q_PAD_SD1_CMD__GPIO_1_18                    1552
+MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5               1553
+MX6Q_PAD_SD1_DAT2__USDHC1_DAT2                 1554
+MX6Q_PAD_SD1_DAT2__ECSPI5_SS1                  1555
+MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2                 1556
+MX6Q_PAD_SD1_DAT2__PWM2_PWMO                   1557
+MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B                        1558
+MX6Q_PAD_SD1_DAT2__GPIO_1_19                   1559
+MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB                1560
+MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4              1561
+MX6Q_PAD_SD1_CLK__USDHC1_CLK                   1562
+MX6Q_PAD_SD1_CLK__ECSPI5_SCLK                  1563
+MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT               1564
+MX6Q_PAD_SD1_CLK__GPT_CLKIN                    1565
+MX6Q_PAD_SD1_CLK__GPIO_1_20                    1566
+MX6Q_PAD_SD1_CLK__PHY_DTB_0                    1567
+MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0               1568
+MX6Q_PAD_SD2_CLK__USDHC2_CLK                   1569
+MX6Q_PAD_SD2_CLK__ECSPI5_SCLK                  1570
+MX6Q_PAD_SD2_CLK__KPP_COL_5                    1571
+MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS             1572
+MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9              1573
+MX6Q_PAD_SD2_CLK__GPIO_1_10                    1574
+MX6Q_PAD_SD2_CLK__PHY_DTB_1                    1575
+MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1               1576
+MX6Q_PAD_SD2_CMD__USDHC2_CMD                   1577
+MX6Q_PAD_SD2_CMD__ECSPI5_MOSI                  1578
+MX6Q_PAD_SD2_CMD__KPP_ROW_5                    1579
+MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC              1580
+MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10             1581
+MX6Q_PAD_SD2_CMD__GPIO_1_11                    1582
+MX6Q_PAD_SD2_DAT3__USDHC2_DAT3                 1583
+MX6Q_PAD_SD2_DAT3__ECSPI5_SS3                  1584
+MX6Q_PAD_SD2_DAT3__KPP_COL_6                   1585
+MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC             1586
+MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11            1587
+MX6Q_PAD_SD2_DAT3__GPIO_1_12                   1588
+MX6Q_PAD_SD2_DAT3__SJC_DONE                    1589
+MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3              1590

diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
new file mode 100644 (file)
index 0000000..f7e8e8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
@@ -0,0 +1,918 @@
+* Freescale MXS Pin Controller
+
+The pins controlled by mxs pin controller are organized in banks, each bank
+has 32 pins.  Each pin has 4 multiplexing functions, and generally, the 4th
+function is GPIO.  The configuration on the pins includes drive strength,
+voltage and pull-up.
+
+Required properties:
+- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
+- reg: Should contain the register physical address and length for the
+  pin controller.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+
+The node of mxs pin controller acts as a container for an arbitrary number of
+subnodes.  Each of these subnodes represents some desired configuration for
+a group of pins, and only affects those parameters that are explicitly listed.
+In other words, a subnode that describes a drive strength parameter implies no
+information about pull-up. For this reason, even seemingly boolean values are
+actually tristates in this binding: unspecified, off, or on. Unspecified is
+represented as an absent property, and off/on are represented as integer
+values 0 and 1.
+
+Those subnodes under mxs pin controller node will fall into two categories.
+One is to set up a group of pins for a function, both mux selection and pin
+configurations, and it's called group node in the binding document.   The other
+one is to adjust the pin configuration for some particular pins that need a
+different configuration than what is defined in group node.  The binding
+document calls this type of node config node.
+
+On mxs, there is no hardware pin group. The pin group in this binding only
+means a group of pins put together for particular peripheral to work in
+particular function, like SSP0 functioning as mmc0-8bit.  That said, the
+group node should include all the pins needed for one function rather than
+having these pins defined in several group nodes.  It also means each of
+"pinctrl-*" phandle in client device node should only have one group node
+pointed in there, while the phandle can have multiple config node referenced
+there to adjust configurations for some pins in the group.
+
+Required subnode-properties:
+- fsl,pinmux-ids: An integer array.  Each integer in the array specify a pin
+  with given mux function, with bank, pin and mux packed as below.
+
+    [15..12] : bank number
+    [11..4]  : pin number
+    [3..0]   : mux selection
+
+  This integer with mux selection packed is used as an entity by both group
+  and config nodes to identify a pin.  The mux selection in the integer takes
+  effects only on group node, and will get ignored by driver with config node,
+  since config node is only meant to set up pin configurations.
+
+  Valid values for these integers are listed below.
+
+- reg: Should be the index of the group nodes for same function.  This property
+  is required only for group nodes, and should not be present in any config
+  nodes.
+
+Optional subnode-properties:
+- fsl,drive-strength: Integer.
+    0: 4 mA
+    1: 8 mA
+    2: 12 mA
+    3: 16 mA
+- fsl,voltage: Integer.
+    0: 1.8 V
+    1: 3.3 V
+- fsl,pull-up: Integer.
+    0: Disable the internal pull-up
+    1: Enable the internal pull-up
+
+Examples:
+
+pinctrl@80018000 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       compatible = "fsl,imx28-pinctrl";
+       reg = <0x80018000 2000>;
+
+       mmc0_8bit_pins_a: mmc0-8bit@0 {
+               reg = <0>;
+               fsl,pinmux-ids = <
+                       0x2000 0x2010 0x2020 0x2030
+                       0x2040 0x2050 0x2060 0x2070
+                       0x2080 0x2090 0x20a0>;
+               fsl,drive-strength = <1>;
+               fsl,voltage = <1>;
+               fsl,pull-up = <1>;
+       };
+
+       mmc_cd_cfg: mmc-cd-cfg {
+               fsl,pinmux-ids = <0x2090>;
+               fsl,pull-up = <0>;
+       };
+
+       mmc_sck_cfg: mmc-sck-cfg {
+               fsl,pinmux-ids = <0x20a0>;
+               fsl,drive-strength = <2>;
+               fsl,pull-up = <0>;
+       };
+};
+
+In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
+to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
+applied on all these pins.  And config nodes mmc-cd-cfg and mmc-sck-cfg are
+adjusting the configuration for pins card-detection and clock from what group
+node mmc0-8bit defines.  Only the configuration properties to be adjusted need
+to be listed in the config nodes.
+
+Valid values for i.MX28 pinmux-id:
+
+pinmux                                         id
+------                                         --
+MX28_PAD_GPMI_D00__GPMI_D0                     0x0000
+MX28_PAD_GPMI_D01__GPMI_D1                     0x0010
+MX28_PAD_GPMI_D02__GPMI_D2                     0x0020
+MX28_PAD_GPMI_D03__GPMI_D3                     0x0030
+MX28_PAD_GPMI_D04__GPMI_D4                     0x0040
+MX28_PAD_GPMI_D05__GPMI_D5                     0x0050
+MX28_PAD_GPMI_D06__GPMI_D6                     0x0060
+MX28_PAD_GPMI_D07__GPMI_D7                     0x0070
+MX28_PAD_GPMI_CE0N__GPMI_CE0N                  0x0100
+MX28_PAD_GPMI_CE1N__GPMI_CE1N                  0x0110
+MX28_PAD_GPMI_CE2N__GPMI_CE2N                  0x0120
+MX28_PAD_GPMI_CE3N__GPMI_CE3N                  0x0130
+MX28_PAD_GPMI_RDY0__GPMI_READY0                        0x0140
+MX28_PAD_GPMI_RDY1__GPMI_READY1                        0x0150
+MX28_PAD_GPMI_RDY2__GPMI_READY2                        0x0160
+MX28_PAD_GPMI_RDY3__GPMI_READY3                        0x0170
+MX28_PAD_GPMI_RDN__GPMI_RDN                    0x0180
+MX28_PAD_GPMI_WRN__GPMI_WRN                    0x0190
+MX28_PAD_GPMI_ALE__GPMI_ALE                    0x01a0
+MX28_PAD_GPMI_CLE__GPMI_CLE                    0x01b0
+MX28_PAD_GPMI_RESETN__GPMI_RESETN              0x01c0
+MX28_PAD_LCD_D00__LCD_D0                       0x1000
+MX28_PAD_LCD_D01__LCD_D1                       0x1010
+MX28_PAD_LCD_D02__LCD_D2                       0x1020
+MX28_PAD_LCD_D03__LCD_D3                       0x1030
+MX28_PAD_LCD_D04__LCD_D4                       0x1040
+MX28_PAD_LCD_D05__LCD_D5                       0x1050
+MX28_PAD_LCD_D06__LCD_D6                       0x1060
+MX28_PAD_LCD_D07__LCD_D7                       0x1070
+MX28_PAD_LCD_D08__LCD_D8                       0x1080
+MX28_PAD_LCD_D09__LCD_D9                       0x1090
+MX28_PAD_LCD_D10__LCD_D10                      0x10a0
+MX28_PAD_LCD_D11__LCD_D11                      0x10b0
+MX28_PAD_LCD_D12__LCD_D12                      0x10c0
+MX28_PAD_LCD_D13__LCD_D13                      0x10d0
+MX28_PAD_LCD_D14__LCD_D14                      0x10e0
+MX28_PAD_LCD_D15__LCD_D15                      0x10f0
+MX28_PAD_LCD_D16__LCD_D16                      0x1100
+MX28_PAD_LCD_D17__LCD_D17                      0x1110
+MX28_PAD_LCD_D18__LCD_D18                      0x1120
+MX28_PAD_LCD_D19__LCD_D19                      0x1130
+MX28_PAD_LCD_D20__LCD_D20                      0x1140
+MX28_PAD_LCD_D21__LCD_D21                      0x1150
+MX28_PAD_LCD_D22__LCD_D22                      0x1160
+MX28_PAD_LCD_D23__LCD_D23                      0x1170
+MX28_PAD_LCD_RD_E__LCD_RD_E                    0x1180
+MX28_PAD_LCD_WR_RWN__LCD_WR_RWN                        0x1190
+MX28_PAD_LCD_RS__LCD_RS                                0x11a0
+MX28_PAD_LCD_CS__LCD_CS                                0x11b0
+MX28_PAD_LCD_VSYNC__LCD_VSYNC                  0x11c0
+MX28_PAD_LCD_HSYNC__LCD_HSYNC                  0x11d0
+MX28_PAD_LCD_DOTCLK__LCD_DOTCLK                        0x11e0
+MX28_PAD_LCD_ENABLE__LCD_ENABLE                        0x11f0
+MX28_PAD_SSP0_DATA0__SSP0_D0                   0x2000
+MX28_PAD_SSP0_DATA1__SSP0_D1                   0x2010
+MX28_PAD_SSP0_DATA2__SSP0_D2                   0x2020
+MX28_PAD_SSP0_DATA3__SSP0_D3                   0x2030
+MX28_PAD_SSP0_DATA4__SSP0_D4                   0x2040
+MX28_PAD_SSP0_DATA5__SSP0_D5                   0x2050
+MX28_PAD_SSP0_DATA6__SSP0_D6                   0x2060
+MX28_PAD_SSP0_DATA7__SSP0_D7                   0x2070
+MX28_PAD_SSP0_CMD__SSP0_CMD                    0x2080
+MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT         0x2090
+MX28_PAD_SSP0_SCK__SSP0_SCK                    0x20a0
+MX28_PAD_SSP1_SCK__SSP1_SCK                    0x20c0
+MX28_PAD_SSP1_CMD__SSP1_CMD                    0x20d0
+MX28_PAD_SSP1_DATA0__SSP1_D0                   0x20e0
+MX28_PAD_SSP1_DATA3__SSP1_D3                   0x20f0
+MX28_PAD_SSP2_SCK__SSP2_SCK                    0x2100
+MX28_PAD_SSP2_MOSI__SSP2_CMD                   0x2110
+MX28_PAD_SSP2_MISO__SSP2_D0                    0x2120
+MX28_PAD_SSP2_SS0__SSP2_D3                     0x2130
+MX28_PAD_SSP2_SS1__SSP2_D4                     0x2140
+MX28_PAD_SSP2_SS2__SSP2_D5                     0x2150
+MX28_PAD_SSP3_SCK__SSP3_SCK                    0x2180
+MX28_PAD_SSP3_MOSI__SSP3_CMD                   0x2190
+MX28_PAD_SSP3_MISO__SSP3_D0                    0x21a0
+MX28_PAD_SSP3_SS0__SSP3_D3                     0x21b0
+MX28_PAD_AUART0_RX__AUART0_RX                  0x3000
+MX28_PAD_AUART0_TX__AUART0_TX                  0x3010
+MX28_PAD_AUART0_CTS__AUART0_CTS                        0x3020
+MX28_PAD_AUART0_RTS__AUART0_RTS                        0x3030
+MX28_PAD_AUART1_RX__AUART1_RX                  0x3040
+MX28_PAD_AUART1_TX__AUART1_TX                  0x3050
+MX28_PAD_AUART1_CTS__AUART1_CTS                        0x3060
+MX28_PAD_AUART1_RTS__AUART1_RTS                        0x3070
+MX28_PAD_AUART2_RX__AUART2_RX                  0x3080
+MX28_PAD_AUART2_TX__AUART2_TX                  0x3090
+MX28_PAD_AUART2_CTS__AUART2_CTS                        0x30a0
+MX28_PAD_AUART2_RTS__AUART2_RTS                        0x30b0
+MX28_PAD_AUART3_RX__AUART3_RX                  0x30c0
+MX28_PAD_AUART3_TX__AUART3_TX                  0x30d0
+MX28_PAD_AUART3_CTS__AUART3_CTS                        0x30e0
+MX28_PAD_AUART3_RTS__AUART3_RTS                        0x30f0
+MX28_PAD_PWM0__PWM_0                           0x3100
+MX28_PAD_PWM1__PWM_1                           0x3110
+MX28_PAD_PWM2__PWM_2                           0x3120
+MX28_PAD_SAIF0_MCLK__SAIF0_MCLK                        0x3140
+MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK              0x3150
+MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK            0x3160
+MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0            0x3170
+MX28_PAD_I2C0_SCL__I2C0_SCL                    0x3180
+MX28_PAD_I2C0_SDA__I2C0_SDA                    0x3190
+MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0            0x31a0
+MX28_PAD_SPDIF__SPDIF_TX                       0x31b0
+MX28_PAD_PWM3__PWM_3                           0x31c0
+MX28_PAD_PWM4__PWM_4                           0x31d0
+MX28_PAD_LCD_RESET__LCD_RESET                  0x31e0
+MX28_PAD_ENET0_MDC__ENET0_MDC                  0x4000
+MX28_PAD_ENET0_MDIO__ENET0_MDIO                        0x4010
+MX28_PAD_ENET0_RX_EN__ENET0_RX_EN              0x4020
+MX28_PAD_ENET0_RXD0__ENET0_RXD0                        0x4030
+MX28_PAD_ENET0_RXD1__ENET0_RXD1                        0x4040
+MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK            0x4050
+MX28_PAD_ENET0_TX_EN__ENET0_TX_EN              0x4060
+MX28_PAD_ENET0_TXD0__ENET0_TXD0                        0x4070
+MX28_PAD_ENET0_TXD1__ENET0_TXD1                        0x4080
+MX28_PAD_ENET0_RXD2__ENET0_RXD2                        0x4090
+MX28_PAD_ENET0_RXD3__ENET0_RXD3                        0x40a0
+MX28_PAD_ENET0_TXD2__ENET0_TXD2                        0x40b0
+MX28_PAD_ENET0_TXD3__ENET0_TXD3                        0x40c0
+MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK            0x40d0
+MX28_PAD_ENET0_COL__ENET0_COL                  0x40e0
+MX28_PAD_ENET0_CRS__ENET0_CRS                  0x40f0
+MX28_PAD_ENET_CLK__CLKCTRL_ENET                        0x4100
+MX28_PAD_JTAG_RTCK__JTAG_RTCK                  0x4140
+MX28_PAD_EMI_D00__EMI_DATA0                    0x5000
+MX28_PAD_EMI_D01__EMI_DATA1                    0x5010
+MX28_PAD_EMI_D02__EMI_DATA2                    0x5020
+MX28_PAD_EMI_D03__EMI_DATA3                    0x5030
+MX28_PAD_EMI_D04__EMI_DATA4                    0x5040
+MX28_PAD_EMI_D05__EMI_DATA5                    0x5050
+MX28_PAD_EMI_D06__EMI_DATA6                    0x5060
+MX28_PAD_EMI_D07__EMI_DATA7                    0x5070
+MX28_PAD_EMI_D08__EMI_DATA8                    0x5080
+MX28_PAD_EMI_D09__EMI_DATA9                    0x5090
+MX28_PAD_EMI_D10__EMI_DATA10                   0x50a0
+MX28_PAD_EMI_D11__EMI_DATA11                   0x50b0
+MX28_PAD_EMI_D12__EMI_DATA12                   0x50c0
+MX28_PAD_EMI_D13__EMI_DATA13                   0x50d0
+MX28_PAD_EMI_D14__EMI_DATA14                   0x50e0
+MX28_PAD_EMI_D15__EMI_DATA15                   0x50f0
+MX28_PAD_EMI_ODT0__EMI_ODT0                    0x5100
+MX28_PAD_EMI_DQM0__EMI_DQM0                    0x5110
+MX28_PAD_EMI_ODT1__EMI_ODT1                    0x5120
+MX28_PAD_EMI_DQM1__EMI_DQM1                    0x5130
+MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK        0x5140
+MX28_PAD_EMI_CLK__EMI_CLK                      0x5150
+MX28_PAD_EMI_DQS0__EMI_DQS0                    0x5160
+MX28_PAD_EMI_DQS1__EMI_DQS1                    0x5170
+MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN            0x51a0
+MX28_PAD_EMI_A00__EMI_ADDR0                    0x6000
+MX28_PAD_EMI_A01__EMI_ADDR1                    0x6010
+MX28_PAD_EMI_A02__EMI_ADDR2                    0x6020
+MX28_PAD_EMI_A03__EMI_ADDR3                    0x6030
+MX28_PAD_EMI_A04__EMI_ADDR4                    0x6040
+MX28_PAD_EMI_A05__EMI_ADDR5                    0x6050
+MX28_PAD_EMI_A06__EMI_ADDR6                    0x6060
+MX28_PAD_EMI_A07__EMI_ADDR7                    0x6070
+MX28_PAD_EMI_A08__EMI_ADDR8                    0x6080
+MX28_PAD_EMI_A09__EMI_ADDR9                    0x6090
+MX28_PAD_EMI_A10__EMI_ADDR10                   0x60a0
+MX28_PAD_EMI_A11__EMI_ADDR11                   0x60b0
+MX28_PAD_EMI_A12__EMI_ADDR12                   0x60c0
+MX28_PAD_EMI_A13__EMI_ADDR13                   0x60d0
+MX28_PAD_EMI_A14__EMI_ADDR14                   0x60e0
+MX28_PAD_EMI_BA0__EMI_BA0                      0x6100
+MX28_PAD_EMI_BA1__EMI_BA1                      0x6110
+MX28_PAD_EMI_BA2__EMI_BA2                      0x6120
+MX28_PAD_EMI_CASN__EMI_CASN                    0x6130
+MX28_PAD_EMI_RASN__EMI_RASN                    0x6140
+MX28_PAD_EMI_WEN__EMI_WEN                      0x6150
+MX28_PAD_EMI_CE0N__EMI_CE0N                    0x6160
+MX28_PAD_EMI_CE1N__EMI_CE1N                    0x6170
+MX28_PAD_EMI_CKE__EMI_CKE                      0x6180
+MX28_PAD_GPMI_D00__SSP1_D0                     0x0001
+MX28_PAD_GPMI_D01__SSP1_D1                     0x0011
+MX28_PAD_GPMI_D02__SSP1_D2                     0x0021
+MX28_PAD_GPMI_D03__SSP1_D3                     0x0031
+MX28_PAD_GPMI_D04__SSP1_D4                     0x0041
+MX28_PAD_GPMI_D05__SSP1_D5                     0x0051
+MX28_PAD_GPMI_D06__SSP1_D6                     0x0061
+MX28_PAD_GPMI_D07__SSP1_D7                     0x0071
+MX28_PAD_GPMI_CE0N__SSP3_D0                    0x0101
+MX28_PAD_GPMI_CE1N__SSP3_D3                    0x0111
+MX28_PAD_GPMI_CE2N__CAN1_TX                    0x0121
+MX28_PAD_GPMI_CE3N__CAN1_RX                    0x0131
+MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT           0x0141
+MX28_PAD_GPMI_RDY1__SSP1_CMD                   0x0151
+MX28_PAD_GPMI_RDY2__CAN0_TX                    0x0161
+MX28_PAD_GPMI_RDY3__CAN0_RX                    0x0171
+MX28_PAD_GPMI_RDN__SSP3_SCK                    0x0181
+MX28_PAD_GPMI_WRN__SSP1_SCK                    0x0191
+MX28_PAD_GPMI_ALE__SSP3_D1                     0x01a1
+MX28_PAD_GPMI_CLE__SSP3_D2                     0x01b1
+MX28_PAD_GPMI_RESETN__SSP3_CMD                 0x01c1
+MX28_PAD_LCD_D03__ETM_DA8                      0x1031
+MX28_PAD_LCD_D04__ETM_DA9                      0x1041
+MX28_PAD_LCD_D08__ETM_DA3                      0x1081
+MX28_PAD_LCD_D09__ETM_DA4                      0x1091
+MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT                0x1141
+MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN         0x1151
+MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT                0x1161
+MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN         0x1171
+MX28_PAD_LCD_RD_E__LCD_VSYNC                   0x1181
+MX28_PAD_LCD_WR_RWN__LCD_HSYNC                 0x1191
+MX28_PAD_LCD_RS__LCD_DOTCLK                    0x11a1
+MX28_PAD_LCD_CS__LCD_ENABLE                    0x11b1
+MX28_PAD_LCD_VSYNC__SAIF1_SDATA0               0x11c1
+MX28_PAD_LCD_HSYNC__SAIF1_SDATA1               0x11d1
+MX28_PAD_LCD_DOTCLK__SAIF1_MCLK                        0x11e1
+MX28_PAD_SSP0_DATA4__SSP2_D0                   0x2041
+MX28_PAD_SSP0_DATA5__SSP2_D3                   0x2051
+MX28_PAD_SSP0_DATA6__SSP2_CMD                  0x2061
+MX28_PAD_SSP0_DATA7__SSP2_SCK                  0x2071
+MX28_PAD_SSP1_SCK__SSP2_D1                     0x20c1
+MX28_PAD_SSP1_CMD__SSP2_D2                     0x20d1
+MX28_PAD_SSP1_DATA0__SSP2_D6                   0x20e1
+MX28_PAD_SSP1_DATA3__SSP2_D7                   0x20f1
+MX28_PAD_SSP2_SCK__AUART2_RX                   0x2101
+MX28_PAD_SSP2_MOSI__AUART2_TX                  0x2111
+MX28_PAD_SSP2_MISO__AUART3_RX                  0x2121
+MX28_PAD_SSP2_SS0__AUART3_TX                   0x2131
+MX28_PAD_SSP2_SS1__SSP2_D1                     0x2141
+MX28_PAD_SSP2_SS2__SSP2_D2                     0x2151
+MX28_PAD_SSP3_SCK__AUART4_TX                   0x2181
+MX28_PAD_SSP3_MOSI__AUART4_RX                  0x2191
+MX28_PAD_SSP3_MISO__AUART4_RTS                 0x21a1
+MX28_PAD_SSP3_SS0__AUART4_CTS                  0x21b1
+MX28_PAD_AUART0_RX__I2C0_SCL                   0x3001
+MX28_PAD_AUART0_TX__I2C0_SDA                   0x3011
+MX28_PAD_AUART0_CTS__AUART4_RX                 0x3021
+MX28_PAD_AUART0_RTS__AUART4_TX                 0x3031
+MX28_PAD_AUART1_RX__SSP2_CARD_DETECT           0x3041
+MX28_PAD_AUART1_TX__SSP3_CARD_DETECT           0x3051
+MX28_PAD_AUART1_CTS__USB0_OVERCURRENT          0x3061
+MX28_PAD_AUART1_RTS__USB0_ID                   0x3071
+MX28_PAD_AUART2_RX__SSP3_D1                    0x3081
+MX28_PAD_AUART2_TX__SSP3_D2                    0x3091
+MX28_PAD_AUART2_CTS__I2C1_SCL                  0x30a1
+MX28_PAD_AUART2_RTS__I2C1_SDA                  0x30b1
+MX28_PAD_AUART3_RX__CAN0_TX                    0x30c1
+MX28_PAD_AUART3_TX__CAN0_RX                    0x30d1
+MX28_PAD_AUART3_CTS__CAN1_TX                   0x30e1
+MX28_PAD_AUART3_RTS__CAN1_RX                   0x30f1
+MX28_PAD_PWM0__I2C1_SCL                                0x3101
+MX28_PAD_PWM1__I2C1_SDA                                0x3111
+MX28_PAD_PWM2__USB0_ID                         0x3121
+MX28_PAD_SAIF0_MCLK__PWM_3                     0x3141
+MX28_PAD_SAIF0_LRCLK__PWM_4                    0x3151
+MX28_PAD_SAIF0_BITCLK__PWM_5                   0x3161
+MX28_PAD_SAIF0_SDATA0__PWM_6                   0x3171
+MX28_PAD_I2C0_SCL__TIMROT_ROTARYA              0x3181
+MX28_PAD_I2C0_SDA__TIMROT_ROTARYB              0x3191
+MX28_PAD_SAIF1_SDATA0__PWM_7                   0x31a1
+MX28_PAD_LCD_RESET__LCD_VSYNC                  0x31e1
+MX28_PAD_ENET0_MDC__GPMI_CE4N                  0x4001
+MX28_PAD_ENET0_MDIO__GPMI_CE5N                 0x4011
+MX28_PAD_ENET0_RX_EN__GPMI_CE6N                        0x4021
+MX28_PAD_ENET0_RXD0__GPMI_CE7N                 0x4031
+MX28_PAD_ENET0_RXD1__GPMI_READY4               0x4041
+MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER           0x4051
+MX28_PAD_ENET0_TX_EN__GPMI_READY5              0x4061
+MX28_PAD_ENET0_TXD0__GPMI_READY6               0x4071
+MX28_PAD_ENET0_TXD1__GPMI_READY7               0x4081
+MX28_PAD_ENET0_RXD2__ENET1_RXD0                        0x4091
+MX28_PAD_ENET0_RXD3__ENET1_RXD1                        0x40a1
+MX28_PAD_ENET0_TXD2__ENET1_TXD0                        0x40b1
+MX28_PAD_ENET0_TXD3__ENET1_TXD1                        0x40c1
+MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER             0x40d1
+MX28_PAD_ENET0_COL__ENET1_TX_EN                        0x40e1
+MX28_PAD_ENET0_CRS__ENET1_RX_EN                        0x40f1
+MX28_PAD_GPMI_CE2N__ENET0_RX_ER                        0x0122
+MX28_PAD_GPMI_CE3N__SAIF1_MCLK                 0x0132
+MX28_PAD_GPMI_RDY0__USB0_ID                    0x0142
+MX28_PAD_GPMI_RDY2__ENET0_TX_ER                        0x0162
+MX28_PAD_GPMI_RDY3__HSADC_TRIGGER              0x0172
+MX28_PAD_GPMI_ALE__SSP3_D4                     0x01a2
+MX28_PAD_GPMI_CLE__SSP3_D5                     0x01b2
+MX28_PAD_LCD_D00__ETM_DA0                      0x1002
+MX28_PAD_LCD_D01__ETM_DA1                      0x1012
+MX28_PAD_LCD_D02__ETM_DA2                      0x1022
+MX28_PAD_LCD_D03__ETM_DA3                      0x1032
+MX28_PAD_LCD_D04__ETM_DA4                      0x1042
+MX28_PAD_LCD_D05__ETM_DA5                      0x1052
+MX28_PAD_LCD_D06__ETM_DA6                      0x1062
+MX28_PAD_LCD_D07__ETM_DA7                      0x1072
+MX28_PAD_LCD_D08__ETM_DA8                      0x1082
+MX28_PAD_LCD_D09__ETM_DA9                      0x1092
+MX28_PAD_LCD_D10__ETM_DA10                     0x10a2
+MX28_PAD_LCD_D11__ETM_DA11                     0x10b2
+MX28_PAD_LCD_D12__ETM_DA12                     0x10c2
+MX28_PAD_LCD_D13__ETM_DA13                     0x10d2
+MX28_PAD_LCD_D14__ETM_DA14                     0x10e2
+MX28_PAD_LCD_D15__ETM_DA15                     0x10f2
+MX28_PAD_LCD_D16__ETM_DA7                      0x1102
+MX28_PAD_LCD_D17__ETM_DA6                      0x1112
+MX28_PAD_LCD_D18__ETM_DA5                      0x1122
+MX28_PAD_LCD_D19__ETM_DA4                      0x1132
+MX28_PAD_LCD_D20__ETM_DA3                      0x1142
+MX28_PAD_LCD_D21__ETM_DA2                      0x1152
+MX28_PAD_LCD_D22__ETM_DA1                      0x1162
+MX28_PAD_LCD_D23__ETM_DA0                      0x1172
+MX28_PAD_LCD_RD_E__ETM_TCTL                    0x1182
+MX28_PAD_LCD_WR_RWN__ETM_TCLK                  0x1192
+MX28_PAD_LCD_HSYNC__ETM_TCTL                   0x11d2
+MX28_PAD_LCD_DOTCLK__ETM_TCLK                  0x11e2
+MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT       0x20c2
+MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN                0x20d2
+MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT     0x20e2
+MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN      0x20f2
+MX28_PAD_SSP2_SCK__SAIF0_SDATA1                        0x2102
+MX28_PAD_SSP2_MOSI__SAIF0_SDATA2               0x2112
+MX28_PAD_SSP2_MISO__SAIF1_SDATA1               0x2122
+MX28_PAD_SSP2_SS0__SAIF1_SDATA2                        0x2132
+MX28_PAD_SSP2_SS1__USB1_OVERCURRENT            0x2142
+MX28_PAD_SSP2_SS2__USB0_OVERCURRENT            0x2152
+MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT       0x2182
+MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN       0x2192
+MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT      0x21a2
+MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN                0x21b2
+MX28_PAD_AUART0_RX__DUART_CTS                  0x3002
+MX28_PAD_AUART0_TX__DUART_RTS                  0x3012
+MX28_PAD_AUART0_CTS__DUART_RX                  0x3022
+MX28_PAD_AUART0_RTS__DUART_TX                  0x3032
+MX28_PAD_AUART1_RX__PWM_0                      0x3042
+MX28_PAD_AUART1_TX__PWM_1                      0x3052
+MX28_PAD_AUART1_CTS__TIMROT_ROTARYA            0x3062
+MX28_PAD_AUART1_RTS__TIMROT_ROTARYB            0x3072
+MX28_PAD_AUART2_RX__SSP3_D4                    0x3082
+MX28_PAD_AUART2_TX__SSP3_D5                    0x3092
+MX28_PAD_AUART2_CTS__SAIF1_BITCLK              0x30a2
+MX28_PAD_AUART2_RTS__SAIF1_LRCLK               0x30b2
+MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT      0x30c2
+MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN       0x30d2
+MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT     0x30e2
+MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN      0x30f2
+MX28_PAD_PWM0__DUART_RX                                0x3102
+MX28_PAD_PWM1__DUART_TX                                0x3112
+MX28_PAD_PWM2__USB1_OVERCURRENT                        0x3122
+MX28_PAD_SAIF0_MCLK__AUART4_CTS                        0x3142
+MX28_PAD_SAIF0_LRCLK__AUART4_RTS               0x3152
+MX28_PAD_SAIF0_BITCLK__AUART4_RX               0x3162
+MX28_PAD_SAIF0_SDATA0__AUART4_TX               0x3172
+MX28_PAD_I2C0_SCL__DUART_RX                    0x3182
+MX28_PAD_I2C0_SDA__DUART_TX                    0x3192
+MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1            0x31a2
+MX28_PAD_SPDIF__ENET1_RX_ER                    0x31b2
+MX28_PAD_ENET0_MDC__SAIF0_SDATA1               0x4002
+MX28_PAD_ENET0_MDIO__SAIF0_SDATA2              0x4012
+MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1             0x4022
+MX28_PAD_ENET0_RXD0__SAIF1_SDATA2              0x4032
+MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT   0x4052
+MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT     0x4092
+MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN      0x40a2
+MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT     0x40b2
+MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN      0x40c2
+MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN    0x40d2
+MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT      0x40e2
+MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN       0x40f2
+MX28_PAD_GPMI_D00__GPIO_0_0                    0x0003
+MX28_PAD_GPMI_D01__GPIO_0_1                    0x0013
+MX28_PAD_GPMI_D02__GPIO_0_2                    0x0023
+MX28_PAD_GPMI_D03__GPIO_0_3                    0x0033
+MX28_PAD_GPMI_D04__GPIO_0_4                    0x0043
+MX28_PAD_GPMI_D05__GPIO_0_5                    0x0053
+MX28_PAD_GPMI_D06__GPIO_0_6                    0x0063
+MX28_PAD_GPMI_D07__GPIO_0_7                    0x0073
+MX28_PAD_GPMI_CE0N__GPIO_0_16                  0x0103
+MX28_PAD_GPMI_CE1N__GPIO_0_17                  0x0113
+MX28_PAD_GPMI_CE2N__GPIO_0_18                  0x0123
+MX28_PAD_GPMI_CE3N__GPIO_0_19                  0x0133
+MX28_PAD_GPMI_RDY0__GPIO_0_20                  0x0143
+MX28_PAD_GPMI_RDY1__GPIO_0_21                  0x0153
+MX28_PAD_GPMI_RDY2__GPIO_0_22                  0x0163
+MX28_PAD_GPMI_RDY3__GPIO_0_23                  0x0173
+MX28_PAD_GPMI_RDN__GPIO_0_24                   0x0183
+MX28_PAD_GPMI_WRN__GPIO_0_25                   0x0193
+MX28_PAD_GPMI_ALE__GPIO_0_26                   0x01a3
+MX28_PAD_GPMI_CLE__GPIO_0_27                   0x01b3
+MX28_PAD_GPMI_RESETN__GPIO_0_28                        0x01c3
+MX28_PAD_LCD_D00__GPIO_1_0                     0x1003
+MX28_PAD_LCD_D01__GPIO_1_1                     0x1013
+MX28_PAD_LCD_D02__GPIO_1_2                     0x1023
+MX28_PAD_LCD_D03__GPIO_1_3                     0x1033
+MX28_PAD_LCD_D04__GPIO_1_4                     0x1043
+MX28_PAD_LCD_D05__GPIO_1_5                     0x1053
+MX28_PAD_LCD_D06__GPIO_1_6                     0x1063
+MX28_PAD_LCD_D07__GPIO_1_7                     0x1073
+MX28_PAD_LCD_D08__GPIO_1_8                     0x1083
+MX28_PAD_LCD_D09__GPIO_1_9                     0x1093
+MX28_PAD_LCD_D10__GPIO_1_10                    0x10a3
+MX28_PAD_LCD_D11__GPIO_1_11                    0x10b3
+MX28_PAD_LCD_D12__GPIO_1_12                    0x10c3
+MX28_PAD_LCD_D13__GPIO_1_13                    0x10d3
+MX28_PAD_LCD_D14__GPIO_1_14                    0x10e3
+MX28_PAD_LCD_D15__GPIO_1_15                    0x10f3
+MX28_PAD_LCD_D16__GPIO_1_16                    0x1103
+MX28_PAD_LCD_D17__GPIO_1_17                    0x1113
+MX28_PAD_LCD_D18__GPIO_1_18                    0x1123
+MX28_PAD_LCD_D19__GPIO_1_19                    0x1133
+MX28_PAD_LCD_D20__GPIO_1_20                    0x1143
+MX28_PAD_LCD_D21__GPIO_1_21                    0x1153
+MX28_PAD_LCD_D22__GPIO_1_22                    0x1163
+MX28_PAD_LCD_D23__GPIO_1_23                    0x1173
+MX28_PAD_LCD_RD_E__GPIO_1_24                   0x1183
+MX28_PAD_LCD_WR_RWN__GPIO_1_25                 0x1193
+MX28_PAD_LCD_RS__GPIO_1_26                     0x11a3
+MX28_PAD_LCD_CS__GPIO_1_27                     0x11b3
+MX28_PAD_LCD_VSYNC__GPIO_1_28                  0x11c3
+MX28_PAD_LCD_HSYNC__GPIO_1_29                  0x11d3
+MX28_PAD_LCD_DOTCLK__GPIO_1_30                 0x11e3
+MX28_PAD_LCD_ENABLE__GPIO_1_31                 0x11f3
+MX28_PAD_SSP0_DATA0__GPIO_2_0                  0x2003
+MX28_PAD_SSP0_DATA1__GPIO_2_1                  0x2013
+MX28_PAD_SSP0_DATA2__GPIO_2_2                  0x2023
+MX28_PAD_SSP0_DATA3__GPIO_2_3                  0x2033
+MX28_PAD_SSP0_DATA4__GPIO_2_4                  0x2043
+MX28_PAD_SSP0_DATA5__GPIO_2_5                  0x2053
+MX28_PAD_SSP0_DATA6__GPIO_2_6                  0x2063
+MX28_PAD_SSP0_DATA7__GPIO_2_7                  0x2073
+MX28_PAD_SSP0_CMD__GPIO_2_8                    0x2083
+MX28_PAD_SSP0_DETECT__GPIO_2_9                 0x2093
+MX28_PAD_SSP0_SCK__GPIO_2_10                   0x20a3
+MX28_PAD_SSP1_SCK__GPIO_2_12                   0x20c3
+MX28_PAD_SSP1_CMD__GPIO_2_13                   0x20d3
+MX28_PAD_SSP1_DATA0__GPIO_2_14                 0x20e3
+MX28_PAD_SSP1_DATA3__GPIO_2_15                 0x20f3
+MX28_PAD_SSP2_SCK__GPIO_2_16                   0x2103
+MX28_PAD_SSP2_MOSI__GPIO_2_17                  0x2113
+MX28_PAD_SSP2_MISO__GPIO_2_18                  0x2123
+MX28_PAD_SSP2_SS0__GPIO_2_19                   0x2133
+MX28_PAD_SSP2_SS1__GPIO_2_20                   0x2143
+MX28_PAD_SSP2_SS2__GPIO_2_21                   0x2153
+MX28_PAD_SSP3_SCK__GPIO_2_24                   0x2183
+MX28_PAD_SSP3_MOSI__GPIO_2_25                  0x2193
+MX28_PAD_SSP3_MISO__GPIO_2_26                  0x21a3
+MX28_PAD_SSP3_SS0__GPIO_2_27                   0x21b3
+MX28_PAD_AUART0_RX__GPIO_3_0                   0x3003
+MX28_PAD_AUART0_TX__GPIO_3_1                   0x3013
+MX28_PAD_AUART0_CTS__GPIO_3_2                  0x3023
+MX28_PAD_AUART0_RTS__GPIO_3_3                  0x3033
+MX28_PAD_AUART1_RX__GPIO_3_4                   0x3043
+MX28_PAD_AUART1_TX__GPIO_3_5                   0x3053
+MX28_PAD_AUART1_CTS__GPIO_3_6                  0x3063
+MX28_PAD_AUART1_RTS__GPIO_3_7                  0x3073
+MX28_PAD_AUART2_RX__GPIO_3_8                   0x3083
+MX28_PAD_AUART2_TX__GPIO_3_9                   0x3093
+MX28_PAD_AUART2_CTS__GPIO_3_10                 0x30a3
+MX28_PAD_AUART2_RTS__GPIO_3_11                 0x30b3
+MX28_PAD_AUART3_RX__GPIO_3_12                  0x30c3
+MX28_PAD_AUART3_TX__GPIO_3_13                  0x30d3
+MX28_PAD_AUART3_CTS__GPIO_3_14                 0x30e3
+MX28_PAD_AUART3_RTS__GPIO_3_15                 0x30f3
+MX28_PAD_PWM0__GPIO_3_16                       0x3103
+MX28_PAD_PWM1__GPIO_3_17                       0x3113
+MX28_PAD_PWM2__GPIO_3_18                       0x3123
+MX28_PAD_SAIF0_MCLK__GPIO_3_20                 0x3143
+MX28_PAD_SAIF0_LRCLK__GPIO_3_21                        0x3153
+MX28_PAD_SAIF0_BITCLK__GPIO_3_22               0x3163
+MX28_PAD_SAIF0_SDATA0__GPIO_3_23               0x3173
+MX28_PAD_I2C0_SCL__GPIO_3_24                   0x3183
+MX28_PAD_I2C0_SDA__GPIO_3_25                   0x3193
+MX28_PAD_SAIF1_SDATA0__GPIO_3_26               0x31a3
+MX28_PAD_SPDIF__GPIO_3_27                      0x31b3
+MX28_PAD_PWM3__GPIO_3_28                       0x31c3
+MX28_PAD_PWM4__GPIO_3_29                       0x31d3
+MX28_PAD_LCD_RESET__GPIO_3_30                  0x31e3
+MX28_PAD_ENET0_MDC__GPIO_4_0                   0x4003
+MX28_PAD_ENET0_MDIO__GPIO_4_1                  0x4013
+MX28_PAD_ENET0_RX_EN__GPIO_4_2                 0x4023
+MX28_PAD_ENET0_RXD0__GPIO_4_3                  0x4033
+MX28_PAD_ENET0_RXD1__GPIO_4_4                  0x4043
+MX28_PAD_ENET0_TX_CLK__GPIO_4_5                        0x4053
+MX28_PAD_ENET0_TX_EN__GPIO_4_6                 0x4063
+MX28_PAD_ENET0_TXD0__GPIO_4_7                  0x4073
+MX28_PAD_ENET0_TXD1__GPIO_4_8                  0x4083
+MX28_PAD_ENET0_RXD2__GPIO_4_9                  0x4093
+MX28_PAD_ENET0_RXD3__GPIO_4_10                 0x40a3
+MX28_PAD_ENET0_TXD2__GPIO_4_11                 0x40b3
+MX28_PAD_ENET0_TXD3__GPIO_4_12                 0x40c3
+MX28_PAD_ENET0_RX_CLK__GPIO_4_13               0x40d3
+MX28_PAD_ENET0_COL__GPIO_4_14                  0x40e3
+MX28_PAD_ENET0_CRS__GPIO_4_15                  0x40f3
+MX28_PAD_ENET_CLK__GPIO_4_16                   0x4103
+MX28_PAD_JTAG_RTCK__GPIO_4_20                  0x4143
+
+Valid values for i.MX23 pinmux-id:
+
+pinmux                                         id
+------                                         --
+MX23_PAD_GPMI_D00__GPMI_D00                    0x0000
+MX23_PAD_GPMI_D01__GPMI_D01                    0x0010
+MX23_PAD_GPMI_D02__GPMI_D02                    0x0020
+MX23_PAD_GPMI_D03__GPMI_D03                    0x0030
+MX23_PAD_GPMI_D04__GPMI_D04                    0x0040
+MX23_PAD_GPMI_D05__GPMI_D05                    0x0050
+MX23_PAD_GPMI_D06__GPMI_D06                    0x0060
+MX23_PAD_GPMI_D07__GPMI_D07                    0x0070
+MX23_PAD_GPMI_D08__GPMI_D08                    0x0080
+MX23_PAD_GPMI_D09__GPMI_D09                    0x0090
+MX23_PAD_GPMI_D10__GPMI_D10                    0x00a0
+MX23_PAD_GPMI_D11__GPMI_D11                    0x00b0
+MX23_PAD_GPMI_D12__GPMI_D12                    0x00c0
+MX23_PAD_GPMI_D13__GPMI_D13                    0x00d0
+MX23_PAD_GPMI_D14__GPMI_D14                    0x00e0
+MX23_PAD_GPMI_D15__GPMI_D15                    0x00f0
+MX23_PAD_GPMI_CLE__GPMI_CLE                    0x0100
+MX23_PAD_GPMI_ALE__GPMI_ALE                    0x0110
+MX23_PAD_GPMI_CE2N__GPMI_CE2N                  0x0120
+MX23_PAD_GPMI_RDY0__GPMI_RDY0                  0x0130
+MX23_PAD_GPMI_RDY1__GPMI_RDY1                  0x0140
+MX23_PAD_GPMI_RDY2__GPMI_RDY2                  0x0150
+MX23_PAD_GPMI_RDY3__GPMI_RDY3                  0x0160
+MX23_PAD_GPMI_WPN__GPMI_WPN                    0x0170
+MX23_PAD_GPMI_WRN__GPMI_WRN                    0x0180
+MX23_PAD_GPMI_RDN__GPMI_RDN                    0x0190
+MX23_PAD_AUART1_CTS__AUART1_CTS                        0x01a0
+MX23_PAD_AUART1_RTS__AUART1_RTS                        0x01b0
+MX23_PAD_AUART1_RX__AUART1_RX                  0x01c0
+MX23_PAD_AUART1_TX__AUART1_TX                  0x01d0
+MX23_PAD_I2C_SCL__I2C_SCL                      0x01e0
+MX23_PAD_I2C_SDA__I2C_SDA                      0x01f0
+MX23_PAD_LCD_D00__LCD_D00                      0x1000
+MX23_PAD_LCD_D01__LCD_D01                      0x1010
+MX23_PAD_LCD_D02__LCD_D02                      0x1020
+MX23_PAD_LCD_D03__LCD_D03                      0x1030
+MX23_PAD_LCD_D04__LCD_D04                      0x1040
+MX23_PAD_LCD_D05__LCD_D05                      0x1050
+MX23_PAD_LCD_D06__LCD_D06                      0x1060
+MX23_PAD_LCD_D07__LCD_D07                      0x1070
+MX23_PAD_LCD_D08__LCD_D08                      0x1080
+MX23_PAD_LCD_D09__LCD_D09                      0x1090
+MX23_PAD_LCD_D10__LCD_D10                      0x10a0
+MX23_PAD_LCD_D11__LCD_D11                      0x10b0
+MX23_PAD_LCD_D12__LCD_D12                      0x10c0
+MX23_PAD_LCD_D13__LCD_D13                      0x10d0
+MX23_PAD_LCD_D14__LCD_D14                      0x10e0
+MX23_PAD_LCD_D15__LCD_D15                      0x10f0
+MX23_PAD_LCD_D16__LCD_D16                      0x1100
+MX23_PAD_LCD_D17__LCD_D17                      0x1110
+MX23_PAD_LCD_RESET__LCD_RESET                  0x1120
+MX23_PAD_LCD_RS__LCD_RS                                0x1130
+MX23_PAD_LCD_WR__LCD_WR                                0x1140
+MX23_PAD_LCD_CS__LCD_CS                                0x1150
+MX23_PAD_LCD_DOTCK__LCD_DOTCK                  0x1160
+MX23_PAD_LCD_ENABLE__LCD_ENABLE                        0x1170
+MX23_PAD_LCD_HSYNC__LCD_HSYNC                  0x1180
+MX23_PAD_LCD_VSYNC__LCD_VSYNC                  0x1190
+MX23_PAD_PWM0__PWM0                            0x11a0
+MX23_PAD_PWM1__PWM1                            0x11b0
+MX23_PAD_PWM2__PWM2                            0x11c0
+MX23_PAD_PWM3__PWM3                            0x11d0
+MX23_PAD_PWM4__PWM4                            0x11e0
+MX23_PAD_SSP1_CMD__SSP1_CMD                    0x2000
+MX23_PAD_SSP1_DETECT__SSP1_DETECT              0x2010
+MX23_PAD_SSP1_DATA0__SSP1_DATA0                        0x2020
+MX23_PAD_SSP1_DATA1__SSP1_DATA1                        0x2030
+MX23_PAD_SSP1_DATA2__SSP1_DATA2                        0x2040
+MX23_PAD_SSP1_DATA3__SSP1_DATA3                        0x2050
+MX23_PAD_SSP1_SCK__SSP1_SCK                    0x2060
+MX23_PAD_ROTARYA__ROTARYA                      0x2070
+MX23_PAD_ROTARYB__ROTARYB                      0x2080
+MX23_PAD_EMI_A00__EMI_A00                      0x2090
+MX23_PAD_EMI_A01__EMI_A01                      0x20a0
+MX23_PAD_EMI_A02__EMI_A02                      0x20b0
+MX23_PAD_EMI_A03__EMI_A03                      0x20c0
+MX23_PAD_EMI_A04__EMI_A04                      0x20d0
+MX23_PAD_EMI_A05__EMI_A05                      0x20e0
+MX23_PAD_EMI_A06__EMI_A06                      0x20f0
+MX23_PAD_EMI_A07__EMI_A07                      0x2100
+MX23_PAD_EMI_A08__EMI_A08                      0x2110
+MX23_PAD_EMI_A09__EMI_A09                      0x2120
+MX23_PAD_EMI_A10__EMI_A10                      0x2130
+MX23_PAD_EMI_A11__EMI_A11                      0x2140
+MX23_PAD_EMI_A12__EMI_A12                      0x2150
+MX23_PAD_EMI_BA0__EMI_BA0                      0x2160
+MX23_PAD_EMI_BA1__EMI_BA1                      0x2170
+MX23_PAD_EMI_CASN__EMI_CASN                    0x2180
+MX23_PAD_EMI_CE0N__EMI_CE0N                    0x2190
+MX23_PAD_EMI_CE1N__EMI_CE1N                    0x21a0
+MX23_PAD_GPMI_CE1N__GPMI_CE1N                  0x21b0
+MX23_PAD_GPMI_CE0N__GPMI_CE0N                  0x21c0
+MX23_PAD_EMI_CKE__EMI_CKE                      0x21d0
+MX23_PAD_EMI_RASN__EMI_RASN                    0x21e0
+MX23_PAD_EMI_WEN__EMI_WEN                      0x21f0
+MX23_PAD_EMI_D00__EMI_D00                      0x3000
+MX23_PAD_EMI_D01__EMI_D01                      0x3010
+MX23_PAD_EMI_D02__EMI_D02                      0x3020
+MX23_PAD_EMI_D03__EMI_D03                      0x3030
+MX23_PAD_EMI_D04__EMI_D04                      0x3040
+MX23_PAD_EMI_D05__EMI_D05                      0x3050
+MX23_PAD_EMI_D06__EMI_D06                      0x3060
+MX23_PAD_EMI_D07__EMI_D07                      0x3070
+MX23_PAD_EMI_D08__EMI_D08                      0x3080
+MX23_PAD_EMI_D09__EMI_D09                      0x3090
+MX23_PAD_EMI_D10__EMI_D10                      0x30a0
+MX23_PAD_EMI_D11__EMI_D11                      0x30b0
+MX23_PAD_EMI_D12__EMI_D12                      0x30c0
+MX23_PAD_EMI_D13__EMI_D13                      0x30d0
+MX23_PAD_EMI_D14__EMI_D14                      0x30e0
+MX23_PAD_EMI_D15__EMI_D15                      0x30f0
+MX23_PAD_EMI_DQM0__EMI_DQM0                    0x3100
+MX23_PAD_EMI_DQM1__EMI_DQM1                    0x3110
+MX23_PAD_EMI_DQS0__EMI_DQS0                    0x3120
+MX23_PAD_EMI_DQS1__EMI_DQS1                    0x3130
+MX23_PAD_EMI_CLK__EMI_CLK                      0x3140
+MX23_PAD_EMI_CLKN__EMI_CLKN                    0x3150
+MX23_PAD_GPMI_D00__LCD_D8                      0x0001
+MX23_PAD_GPMI_D01__LCD_D9                      0x0011
+MX23_PAD_GPMI_D02__LCD_D10                     0x0021
+MX23_PAD_GPMI_D03__LCD_D11                     0x0031
+MX23_PAD_GPMI_D04__LCD_D12                     0x0041
+MX23_PAD_GPMI_D05__LCD_D13                     0x0051
+MX23_PAD_GPMI_D06__LCD_D14                     0x0061
+MX23_PAD_GPMI_D07__LCD_D15                     0x0071
+MX23_PAD_GPMI_D08__LCD_D18                     0x0081
+MX23_PAD_GPMI_D09__LCD_D19                     0x0091
+MX23_PAD_GPMI_D10__LCD_D20                     0x00a1
+MX23_PAD_GPMI_D11__LCD_D21                     0x00b1
+MX23_PAD_GPMI_D12__LCD_D22                     0x00c1
+MX23_PAD_GPMI_D13__LCD_D23                     0x00d1
+MX23_PAD_GPMI_D14__AUART2_RX                   0x00e1
+MX23_PAD_GPMI_D15__AUART2_TX                   0x00f1
+MX23_PAD_GPMI_CLE__LCD_D16                     0x0101
+MX23_PAD_GPMI_ALE__LCD_D17                     0x0111
+MX23_PAD_GPMI_CE2N__ATA_A2                     0x0121
+MX23_PAD_AUART1_RTS__IR_CLK                    0x01b1
+MX23_PAD_AUART1_RX__IR_RX                      0x01c1
+MX23_PAD_AUART1_TX__IR_TX                      0x01d1
+MX23_PAD_I2C_SCL__GPMI_RDY2                    0x01e1
+MX23_PAD_I2C_SDA__GPMI_CE2N                    0x01f1
+MX23_PAD_LCD_D00__ETM_DA8                      0x1001
+MX23_PAD_LCD_D01__ETM_DA9                      0x1011
+MX23_PAD_LCD_D02__ETM_DA10                     0x1021
+MX23_PAD_LCD_D03__ETM_DA11                     0x1031
+MX23_PAD_LCD_D04__ETM_DA12                     0x1041
+MX23_PAD_LCD_D05__ETM_DA13                     0x1051
+MX23_PAD_LCD_D06__ETM_DA14                     0x1061
+MX23_PAD_LCD_D07__ETM_DA15                     0x1071
+MX23_PAD_LCD_D08__ETM_DA0                      0x1081
+MX23_PAD_LCD_D09__ETM_DA1                      0x1091
+MX23_PAD_LCD_D10__ETM_DA2                      0x10a1
+MX23_PAD_LCD_D11__ETM_DA3                      0x10b1
+MX23_PAD_LCD_D12__ETM_DA4                      0x10c1
+MX23_PAD_LCD_D13__ETM_DA5                      0x10d1
+MX23_PAD_LCD_D14__ETM_DA6                      0x10e1
+MX23_PAD_LCD_D15__ETM_DA7                      0x10f1
+MX23_PAD_LCD_RESET__ETM_TCTL                   0x1121
+MX23_PAD_LCD_RS__ETM_TCLK                      0x1131
+MX23_PAD_LCD_DOTCK__GPMI_RDY3                  0x1161
+MX23_PAD_LCD_ENABLE__I2C_SCL                   0x1171
+MX23_PAD_LCD_HSYNC__I2C_SDA                    0x1181
+MX23_PAD_LCD_VSYNC__LCD_BUSY                   0x1191
+MX23_PAD_PWM0__ROTARYA                         0x11a1
+MX23_PAD_PWM1__ROTARYB                         0x11b1
+MX23_PAD_PWM2__GPMI_RDY3                       0x11c1
+MX23_PAD_PWM3__ETM_TCTL                                0x11d1
+MX23_PAD_PWM4__ETM_TCLK                                0x11e1
+MX23_PAD_SSP1_DETECT__GPMI_CE3N                        0x2011
+MX23_PAD_SSP1_DATA1__I2C_SCL                   0x2031
+MX23_PAD_SSP1_DATA2__I2C_SDA                   0x2041
+MX23_PAD_ROTARYA__AUART2_RTS                   0x2071
+MX23_PAD_ROTARYB__AUART2_CTS                   0x2081
+MX23_PAD_GPMI_D00__SSP2_DATA0                  0x0002
+MX23_PAD_GPMI_D01__SSP2_DATA1                  0x0012
+MX23_PAD_GPMI_D02__SSP2_DATA2                  0x0022
+MX23_PAD_GPMI_D03__SSP2_DATA3                  0x0032
+MX23_PAD_GPMI_D04__SSP2_DATA4                  0x0042
+MX23_PAD_GPMI_D05__SSP2_DATA5                  0x0052
+MX23_PAD_GPMI_D06__SSP2_DATA6                  0x0062
+MX23_PAD_GPMI_D07__SSP2_DATA7                  0x0072
+MX23_PAD_GPMI_D08__SSP1_DATA4                  0x0082
+MX23_PAD_GPMI_D09__SSP1_DATA5                  0x0092
+MX23_PAD_GPMI_D10__SSP1_DATA6                  0x00a2
+MX23_PAD_GPMI_D11__SSP1_DATA7                  0x00b2
+MX23_PAD_GPMI_D15__GPMI_CE3N                   0x00f2
+MX23_PAD_GPMI_RDY0__SSP2_DETECT                        0x0132
+MX23_PAD_GPMI_RDY1__SSP2_CMD                   0x0142
+MX23_PAD_GPMI_WRN__SSP2_SCK                    0x0182
+MX23_PAD_AUART1_CTS__SSP1_DATA4                        0x01a2
+MX23_PAD_AUART1_RTS__SSP1_DATA5                        0x01b2
+MX23_PAD_AUART1_RX__SSP1_DATA6                 0x01c2
+MX23_PAD_AUART1_TX__SSP1_DATA7                 0x01d2
+MX23_PAD_I2C_SCL__AUART1_TX                    0x01e2
+MX23_PAD_I2C_SDA__AUART1_RX                    0x01f2
+MX23_PAD_LCD_D08__SAIF2_SDATA0                 0x1082
+MX23_PAD_LCD_D09__SAIF1_SDATA0                 0x1092
+MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK             0x10a2
+MX23_PAD_LCD_D11__SAIF_LRCLK                   0x10b2
+MX23_PAD_LCD_D12__SAIF2_SDATA1                 0x10c2
+MX23_PAD_LCD_D13__SAIF2_SDATA2                 0x10d2
+MX23_PAD_LCD_D14__SAIF1_SDATA2                 0x10e2
+MX23_PAD_LCD_D15__SAIF1_SDATA1                 0x10f2
+MX23_PAD_LCD_D16__SAIF_ALT_BITCLK              0x1102
+MX23_PAD_LCD_RESET__GPMI_CE3N                  0x1122
+MX23_PAD_PWM0__DUART_RX                                0x11a2
+MX23_PAD_PWM1__DUART_TX                                0x11b2
+MX23_PAD_PWM3__AUART1_CTS                      0x11d2
+MX23_PAD_PWM4__AUART1_RTS                      0x11e2
+MX23_PAD_SSP1_CMD__JTAG_TDO                    0x2002
+MX23_PAD_SSP1_DETECT__USB_OTG_ID               0x2012
+MX23_PAD_SSP1_DATA0__JTAG_TDI                  0x2022
+MX23_PAD_SSP1_DATA1__JTAG_TCLK                 0x2032
+MX23_PAD_SSP1_DATA2__JTAG_RTCK                 0x2042
+MX23_PAD_SSP1_DATA3__JTAG_TMS                  0x2052
+MX23_PAD_SSP1_SCK__JTAG_TRST                   0x2062
+MX23_PAD_ROTARYA__SPDIF                                0x2072
+MX23_PAD_ROTARYB__GPMI_CE3N                    0x2082
+MX23_PAD_GPMI_D00__GPIO_0_0                    0x0003
+MX23_PAD_GPMI_D01__GPIO_0_1                    0x0013
+MX23_PAD_GPMI_D02__GPIO_0_2                    0x0023
+MX23_PAD_GPMI_D03__GPIO_0_3                    0x0033
+MX23_PAD_GPMI_D04__GPIO_0_4                    0x0043
+MX23_PAD_GPMI_D05__GPIO_0_5                    0x0053
+MX23_PAD_GPMI_D06__GPIO_0_6                    0x0063
+MX23_PAD_GPMI_D07__GPIO_0_7                    0x0073
+MX23_PAD_GPMI_D08__GPIO_0_8                    0x0083
+MX23_PAD_GPMI_D09__GPIO_0_9                    0x0093
+MX23_PAD_GPMI_D10__GPIO_0_10                   0x00a3
+MX23_PAD_GPMI_D11__GPIO_0_11                   0x00b3
+MX23_PAD_GPMI_D12__GPIO_0_12                   0x00c3
+MX23_PAD_GPMI_D13__GPIO_0_13                   0x00d3
+MX23_PAD_GPMI_D14__GPIO_0_14                   0x00e3
+MX23_PAD_GPMI_D15__GPIO_0_15                   0x00f3
+MX23_PAD_GPMI_CLE__GPIO_0_16                   0x0103
+MX23_PAD_GPMI_ALE__GPIO_0_17                   0x0113
+MX23_PAD_GPMI_CE2N__GPIO_0_18                  0x0123
+MX23_PAD_GPMI_RDY0__GPIO_0_19                  0x0133
+MX23_PAD_GPMI_RDY1__GPIO_0_20                  0x0143
+MX23_PAD_GPMI_RDY2__GPIO_0_21                  0x0153
+MX23_PAD_GPMI_RDY3__GPIO_0_22                  0x0163
+MX23_PAD_GPMI_WPN__GPIO_0_23                   0x0173
+MX23_PAD_GPMI_WRN__GPIO_0_24                   0x0183
+MX23_PAD_GPMI_RDN__GPIO_0_25                   0x0193
+MX23_PAD_AUART1_CTS__GPIO_0_26                 0x01a3
+MX23_PAD_AUART1_RTS__GPIO_0_27                 0x01b3
+MX23_PAD_AUART1_RX__GPIO_0_28                  0x01c3
+MX23_PAD_AUART1_TX__GPIO_0_29                  0x01d3
+MX23_PAD_I2C_SCL__GPIO_0_30                    0x01e3
+MX23_PAD_I2C_SDA__GPIO_0_31                    0x01f3
+MX23_PAD_LCD_D00__GPIO_1_0                     0x1003
+MX23_PAD_LCD_D01__GPIO_1_1                     0x1013
+MX23_PAD_LCD_D02__GPIO_1_2                     0x1023
+MX23_PAD_LCD_D03__GPIO_1_3                     0x1033
+MX23_PAD_LCD_D04__GPIO_1_4                     0x1043
+MX23_PAD_LCD_D05__GPIO_1_5                     0x1053
+MX23_PAD_LCD_D06__GPIO_1_6                     0x1063
+MX23_PAD_LCD_D07__GPIO_1_7                     0x1073
+MX23_PAD_LCD_D08__GPIO_1_8                     0x1083
+MX23_PAD_LCD_D09__GPIO_1_9                     0x1093
+MX23_PAD_LCD_D10__GPIO_1_10                    0x10a3
+MX23_PAD_LCD_D11__GPIO_1_11                    0x10b3
+MX23_PAD_LCD_D12__GPIO_1_12                    0x10c3
+MX23_PAD_LCD_D13__GPIO_1_13                    0x10d3
+MX23_PAD_LCD_D14__GPIO_1_14                    0x10e3
+MX23_PAD_LCD_D15__GPIO_1_15                    0x10f3
+MX23_PAD_LCD_D16__GPIO_1_16                    0x1103
+MX23_PAD_LCD_D17__GPIO_1_17                    0x1113
+MX23_PAD_LCD_RESET__GPIO_1_18                  0x1123
+MX23_PAD_LCD_RS__GPIO_1_19                     0x1133
+MX23_PAD_LCD_WR__GPIO_1_20                     0x1143
+MX23_PAD_LCD_CS__GPIO_1_21                     0x1153
+MX23_PAD_LCD_DOTCK__GPIO_1_22                  0x1163
+MX23_PAD_LCD_ENABLE__GPIO_1_23                 0x1173
+MX23_PAD_LCD_HSYNC__GPIO_1_24                  0x1183
+MX23_PAD_LCD_VSYNC__GPIO_1_25                  0x1193
+MX23_PAD_PWM0__GPIO_1_26                       0x11a3
+MX23_PAD_PWM1__GPIO_1_27                       0x11b3
+MX23_PAD_PWM2__GPIO_1_28                       0x11c3
+MX23_PAD_PWM3__GPIO_1_29                       0x11d3
+MX23_PAD_PWM4__GPIO_1_30                       0x11e3
+MX23_PAD_SSP1_CMD__GPIO_2_0                    0x2003
+MX23_PAD_SSP1_DETECT__GPIO_2_1                 0x2013
+MX23_PAD_SSP1_DATA0__GPIO_2_2                  0x2023
+MX23_PAD_SSP1_DATA1__GPIO_2_3                  0x2033
+MX23_PAD_SSP1_DATA2__GPIO_2_4                  0x2043
+MX23_PAD_SSP1_DATA3__GPIO_2_5                  0x2053
+MX23_PAD_SSP1_SCK__GPIO_2_6                    0x2063
+MX23_PAD_ROTARYA__GPIO_2_7                     0x2073
+MX23_PAD_ROTARYB__GPIO_2_8                     0x2083
+MX23_PAD_EMI_A00__GPIO_2_9                     0x2093
+MX23_PAD_EMI_A01__GPIO_2_10                    0x20a3
+MX23_PAD_EMI_A02__GPIO_2_11                    0x20b3
+MX23_PAD_EMI_A03__GPIO_2_12                    0x20c3
+MX23_PAD_EMI_A04__GPIO_2_13                    0x20d3
+MX23_PAD_EMI_A05__GPIO_2_14                    0x20e3
+MX23_PAD_EMI_A06__GPIO_2_15                    0x20f3
+MX23_PAD_EMI_A07__GPIO_2_16                    0x2103
+MX23_PAD_EMI_A08__GPIO_2_17                    0x2113
+MX23_PAD_EMI_A09__GPIO_2_18                    0x2123
+MX23_PAD_EMI_A10__GPIO_2_19                    0x2133
+MX23_PAD_EMI_A11__GPIO_2_20                    0x2143
+MX23_PAD_EMI_A12__GPIO_2_21                    0x2153
+MX23_PAD_EMI_BA0__GPIO_2_22                    0x2163
+MX23_PAD_EMI_BA1__GPIO_2_23                    0x2173
+MX23_PAD_EMI_CASN__GPIO_2_24                   0x2183
+MX23_PAD_EMI_CE0N__GPIO_2_25                   0x2193
+MX23_PAD_EMI_CE1N__GPIO_2_26                   0x21a3
+MX23_PAD_GPMI_CE1N__GPIO_2_27                  0x21b3
+MX23_PAD_GPMI_CE0N__GPIO_2_28                  0x21c3
+MX23_PAD_EMI_CKE__GPIO_2_29                    0x21d3
+MX23_PAD_EMI_RASN__GPIO_2_30                   0x21e3
+MX23_PAD_EMI_WEN__GPIO_2_31                    0x21f3

diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
new file mode 100644 (file)
index 0000000..c8e5782
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
@@ -0,0 +1,132 @@
+NVIDIA Tegra20 pinmux controller
+
+Required properties:
+- compatible: "nvidia,tegra20-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the tri-state, mux, pull-up/down, and pad control register sets.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Tegra's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, tristate, drive strength, etc.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function or tristate parameter. For this
+reason, even seemingly boolean values are actually tristates in this binding:
+unspecified, off, or on. Unspecified is represented as an absent property,
+and off/on are represented as integer values 0 and 1.
+
+Required subnode-properties:
+- nvidia,pins : An array of strings. Each string contains the name of a pin or
+    group. Valid values for these names are listed below.
+
+Optional subnode-properties:
+- nvidia,function: A string containing the name of the function to mux to the
+  pin or group. Valid values for function names are listed below. See the Tegra
+  TRM to determine which are valid for each pin or group.
+- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
+    0: none, 1: down, 2: up.
+- nvidia,tristate: Integer.
+    0: drive, 1: tristate.
+- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
+    0: no, 1: yes.
+- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
+    0: no, 1: yes.
+- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
+    most power. Controls the drive power or current. See "Low Power Mode"
+    or "LPMD1" and "LPMD0" in the Tegra TRM.
+- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
+    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
+    Tegra TRM.
+- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
+    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
+    Tegra TRM.
+- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
+    fastest. The range of valid values depends on the pingroup. See
+    "DRVDN_SLWR" in the Tegra TRM.
+- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
+    fastest. The range of valid values depends on the pingroup. See
+    "DRVUP_SLWF" in the Tegra TRM.
+
+Note that many of these properties are only valid for certain specific pins
+or groups. See the Tegra TRM and various pinmux spreadsheets for complete
+details regarding which groups support which functionality. The Linux pinctrl
+driver may also be a useful reference, since it consolidates, disambiguates,
+and corrects data from all those sources.
+
+Valid values for pin and group names are:
+
+  mux groups:
+
+    These all support nvidia,function, nvidia,tristate, and many support
+    nvidia,pull.
+
+    ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
+    ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
+    gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
+    ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
+    ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
+    lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
+    owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
+    spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
+    uca, ucb, uda.
+
+  tristate groups:
+
+    These only support nvidia,pull.
+
+    ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
+    ld19_18, ld21_20, ld23_22.
+
+  drive groups:
+
+    With some exceptions, these support nvidia,high-speed-mode,
+    nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
+    nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling.
+
+    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
+    drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
+    drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
+    drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
+    drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
+    drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
+    drive_uda.
+
+Example:
+
+       pinctrl@70000000 {
+               compatible = "nvidia,tegra20-pinmux";
+               reg = < 0x70000014 0x10    /* Tri-state registers */
+                       0x70000080 0x20    /* Mux registers */
+                       0x700000a0 0x14    /* Pull-up/down registers */
+                       0x70000868 0xa8 >; /* Pad control registers */
+       };
+
+Example board file extract:
+
+       pinctrl@70000000 {
+               sdio4_default: sdio4_default {
+                       atb {
+                               nvidia,pins = "atb", "gma", "gme";
+                               nvidia,function = "sdio4";
+                               nvidia,pull = <0>;
+                               nvidia,tristate = <0>;
+                       };
+               };
+       };
+
+       sdhci@c8000600 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdio4_default>;
+       };

diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
new file mode 100644 (file)
index 0000000..c275b70
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
@@ -0,0 +1,132 @@
+NVIDIA Tegra30 pinmux controller
+
+The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
+as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
+that binding as a baseline, and only documents the differences between the
+two bindings.
+
+Required properties:
+- compatible: "nvidia,tegra30-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the pad control and mux registers.
+
+Tegra30 adds the following optional properties for pin configuration subnodes:
+- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
+- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
+- nvidia,lock: Integer. Lock the pin configuration against further changes
+    until reset. 0: no, 1: yes.
+- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
+
+As with Tegra20, see the Tegra TRM for complete details regarding which groups
+support which functionality.
+
+Valid values for pin and group names are:
+
+  per-pin mux groups:
+
+    These all support nvidia,function, nvidia,tristate, nvidia,pull,
+    nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
+    nvidia,io-reset.
+
+    clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
+    dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
+    gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
+    sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
+    uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
+    lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
+    sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
+    lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
+    lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
+    lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
+    gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
+    gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
+    gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
+    gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
+    gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
+    uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
+    gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
+    vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
+    vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
+    lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
+    dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
+    lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
+    ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
+    ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
+    dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
+    kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+    kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
+    kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
+    kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
+    kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
+    vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
+    sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
+    pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
+    lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
+    clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
+    spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
+    spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
+    sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
+    sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
+    sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
+    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
+    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
+    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
+    cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
+    clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
+    pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
+    pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
+    pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
+    clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
+    pwr_int_n.
+
+  drive groups:
+
+    These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
+    nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all
+    support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
+
+    ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
+    dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
+    gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
+    uart3, uda, vi1.
+
+Example:
+
+       pinctrl@70000000 {
+               compatible = "nvidia,tegra30-pinmux";
+               reg = < 0x70000868 0xd0     /* Pad control registers */
+                       0x70003000 0x3e0 >; /* Mux registers */
+       };
+
+Example board file extract:
+
+       pinctrl@70000000 {
+               sdmmc4_default: pinmux {
+                       sdmmc4_clk_pcc4 {
+                               nvidia,pins =   "sdmmc4_clk_pcc4",
+                                               "sdmmc4_rst_n_pcc3";
+                               nvidia,function = "sdmmc4";
+                               nvidia,pull = <0>;
+                               nvidia,tristate = <0>;
+                       };
+                       sdmmc4_dat0_paa0 {
+                               nvidia,pins =   "sdmmc4_dat0_paa0",
+                                               "sdmmc4_dat1_paa1",
+                                               "sdmmc4_dat2_paa2",
+                                               "sdmmc4_dat3_paa3",
+                                               "sdmmc4_dat4_paa4",
+                                               "sdmmc4_dat5_paa5",
+                                               "sdmmc4_dat6_paa6",
+                                               "sdmmc4_dat7_paa7";
+                               nvidia,function = "sdmmc4";
+                               nvidia,pull = <2>;
+                               nvidia,tristate = <0>;
+                       };
+               };
+       };
+
+       sdhci@78000400 {
+               pinctrl-names = "default";
+               pinctrl-0 = <&sdmmc4_default>;
+       };

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
new file mode 100644 (file)
index 0000000..c95ea82
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -0,0 +1,128 @@
+== Introduction ==
+
+Hardware modules that control pin multiplexing or configuration parameters
+such as pull-up/down, tri-state, drive-strength etc are designated as pin
+controllers. Each pin controller must be represented as a node in device tree,
+just like any other hardware module.
+
+Hardware modules whose signals are affected by pin configuration are
+designated client devices. Again, each client device must be represented as a
+node in device tree, just like any other hardware module.
+
+For a client device to operate correctly, certain pin controllers must
+set up certain specific pin configurations. Some client devices need a
+single static pin configuration, e.g. set up during initialization. Others
+need to reconfigure pins at run-time, for example to tri-state pins when the
+device is inactive. Hence, each client device can define a set of named
+states. The number and names of those states is defined by the client device's
+own binding.
+
+The common pinctrl bindings defined in this file provide an infrastructure
+for client device device tree nodes to map those state names to the pin
+configuration used by those states.
+
+Note that pin controllers themselves may also be client devices of themselves.
+For example, a pin controller may set up its own "active" state when the
+driver loads. This would allow representing a board's static pin configuration
+in a single place, rather than splitting it across multiple client device
+nodes. The decision to do this or not somewhat rests with the author of
+individual board device tree files, and any requirements imposed by the
+bindings for the individual client devices in use by that board, i.e. whether
+they require certain specific named states for dynamic pin configuration.
+
+== Pinctrl client devices ==
+
+For each client device individually, every pin state is assigned an integer
+ID. These numbers start at 0, and are contiguous. For each state ID, a unique
+property exists to define the pin configuration. Each state may also be
+assigned a name. When names are used, another property exists to map from
+those names to the integer IDs.
+
+Each client device's own binding determines the set of states the must be
+defined in its device tree node, and whether to define the set of state
+IDs that must be provided, or whether to define the set of state names that
+must be provided.
+
+Required properties:
+pinctrl-0:     List of phandles, each pointing at a pin configuration
+               node. These referenced pin configuration nodes must be child
+               nodes of the pin controller that they configure. Multiple
+               entries may exist in this list so that multiple pin
+               controllers may be configured, or so that a state may be built
+               from multiple nodes for a single pin controller, each
+               contributing part of the overall configuration. See the next
+               section of this document for details of the format of these
+               pin configuration nodes.
+
+               In some cases, it may be useful to define a state, but for it
+               to be empty. This may be required when a common IP block is
+               used in an SoC either without a pin controller, or where the
+               pin controller does not affect the HW module in question. If
+               the binding for that IP block requires certain pin states to
+               exist, they must still be defined, but may be left empty.
+
+Optional properties:
+pinctrl-1:     List of phandles, each pointing at a pin configuration
+               node within a pin controller.
+...
+pinctrl-n:     List of phandles, each pointing at a pin configuration
+               node within a pin controller.
+pinctrl-names: The list of names to assign states. List entry 0 defines the
+               name for integer state ID 0, list entry 1 for state ID 1, and
+               so on.
+
+For example:
+
+       /* For a client device requiring named states */
+       device {
+               pinctrl-names = "active", "idle";
+               pinctrl-0 = <&state_0_node_a>;
+               pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+       };
+
+       /* For the same device if using state IDs */
+       device {
+               pinctrl-0 = <&state_0_node_a>;
+               pinctrl-1 = <&state_1_node_a &state_1_node_b>;
+       };
+
+       /*
+        * For an IP block whose binding supports pin configuration,
+        * but in use on an SoC that doesn't have any pin control hardware
+        */
+       device {
+               pinctrl-names = "active", "idle";
+               pinctrl-0 = <>;
+               pinctrl-1 = <>;
+       };
+
+== Pin controller devices ==
+
+Pin controller devices should contain the pin configuration nodes that client
+devices reference.
+
+For example:
+
+       pincontroller {
+               ... /* Standard DT properties for the device itself elided */
+
+               state_0_node_a {
+                       ...
+               };
+               state_1_node_a {
+                       ...
+               };
+               state_1_node_b {
+                       ...
+               };
+       }
+
+The contents of each of those pin configuration child nodes is defined
+entirely by the binding for the individual pin controller device. There
+exists no common standard for this content.
+
+The pin configuration nodes need not be direct children of the pin controller
+device; they may be grandchildren, for example. Whether this is legal, and
+whether there is any interaction between the child and intermediate parent
+nodes, is again defined entirely by the binding for the individual pin
+controller device.

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
new file mode 100644 (file)
index 0000000..3664d37
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt
@@ -0,0 +1,108 @@
+ST Microelectronics, SPEAr pinmux controller
+
+Required properties:
+- compatible   : "st,spear300-pinmux"
+               : "st,spear310-pinmux"
+               : "st,spear320-pinmux"
+- reg          : Address range of the pinctrl registers
+- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
+       - Its values for SPEAr300:
+               - NAND_MODE             : <0>
+               - NOR_MODE              : <1>
+               - PHOTO_FRAME_MODE      : <2>
+               - LEND_IP_PHONE_MODE    : <3>
+               - HEND_IP_PHONE_MODE    : <4>
+               - LEND_WIFI_PHONE_MODE  : <5>
+               - HEND_WIFI_PHONE_MODE  : <6>
+               - ATA_PABX_WI2S_MODE    : <7>
+               - ATA_PABX_I2S_MODE     : <8>
+               - CAML_LCDW_MODE        : <9>
+               - CAMU_LCD_MODE         : <10>
+               - CAMU_WLCD_MODE        : <11>
+               - CAML_LCD_MODE         : <12>
+       - Its values for SPEAr320:
+               - AUTO_NET_SMII_MODE    : <0>
+               - AUTO_NET_MII_MODE     : <1>
+               - AUTO_EXP_MODE         : <2>
+               - SMALL_PRINTERS_MODE   : <3>
+               - EXTENDED_MODE         : <4>
+
+Please refer to pinctrl-bindings.txt in this directory for details of the common
+pinctrl bindings used by client devices.
+
+SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
+of these subnodes represents muxing for a pin, a group, or a list of pins or
+groups.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Required subnode-properties:
+- st,pins : An array of strings. Each string contains the name of a pin or
+  group.
+- st,function: A string containing the name of the function to mux to the pin or
+  group. See the SPEAr's TRM to determine which are valid for each pin or group.
+
+  Valid values for group and function names can be found from looking at the
+  group and function arrays in driver files:
+  drivers/pinctrl/spear/pinctrl-spear3*0.c
+
+Valid values for group names are:
+For All SPEAr3xx machines:
+       "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
+       "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
+       "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
+       "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"
+
+For SPEAr300 machines:
+       "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
+       "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
+       "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
+       "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
+
+For SPEAr310 machines:
+       "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
+       "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"
+
+For SPEAr320 machines:
+       "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
+       "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
+       "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
+       "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
+       "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
+       "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
+       "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
+       "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
+       "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
+       "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
+       "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
+       "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
+       "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
+       "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
+       "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
+       "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
+       "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
+       "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
+       "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
+       "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
+       "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
+       "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
+       "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"
+
+Valid values for function names are:
+For All SPEAr3xx machines:
+       "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
+       "uart0", "timer_0_1", "timer_2_3"
+
+For SPEAr300 machines:
+       "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"
+
+For SPEAr310 machines:
+       "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
+       "rs485_1", "tdm"
+
+For SPEAr320 machines:
+       "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
+       "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
+       "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
+       "mii0_1", "i2c1", "i2c2"

diff --git a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
deleted file mode 100644 (file)
index 36f82db..0000000
--- a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-NVIDIA Tegra 2 pinmux controller
-
-Required properties:
-- compatible : "nvidia,tegra20-pinmux"
-

diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt
index 2c3cd41..9cc4444 100644 (file)
--- a/Documentation/devicetree/bindings/sound/sgtl5000.txt
+++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt
@@ -3,6 +3,8 @@
 Required properties:
 - compatible : "fsl,sgtl5000".
 
+- reg : the I2C address of the device
+
 Example:
 
 codec: sgtl5000@0a {

diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index 2a596a4..950856b 100644 (file)
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -276,3 +276,11 @@ REGULATOR
   devm_regulator_get()
   devm_regulator_put()
   devm_regulator_bulk_get()
+
+CLOCK
+  devm_clk_get()
+  devm_clk_put()
+
+PINCTRL
+  devm_pinctrl_get()
+  devm_pinctrl_put()

diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt
index bd80ba5..1619a8c 100644 (file)
--- a/Documentation/networking/ip-sysctl.txt
+++ b/Documentation/networking/ip-sysctl.txt
@@ -147,7 +147,7 @@ tcp_adv_win_scale - INTEGER
        (if tcp_adv_win_scale > 0) or bytes-bytes/2^(-tcp_adv_win_scale),
        if it is <= 0.
        Possible values are [-31, 31], inclusive.
-       Default: 2
+       Default: 1
 
 tcp_allowed_congestion_control - STRING
        Show/set the congestion control choices available to non-privileged
@@ -410,7 +410,7 @@ tcp_rmem - vector of 3 INTEGERs: min, default, max
        net.core.rmem_max.  Calling setsockopt() with SO_RCVBUF disables
        automatic tuning of that socket's receive buffer size, in which
        case this value is ignored.
-       Default: between 87380B and 4MB, depending on RAM size.
+       Default: between 87380B and 6MB, depending on RAM size.
 
 tcp_sack - BOOLEAN
        Enable select acknowledgments (SACKS).

diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index d97bccf..e40f4b4 100644 (file)
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -152,11 +152,9 @@ static const struct foo_group foo_groups[] = {
 };
 
 
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 {
-       if (selector >= ARRAY_SIZE(foo_groups))
-               return -EINVAL;
-       return 0;
+       return ARRAY_SIZE(foo_groups);
 }
 
 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -175,7 +173,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinctrl_ops foo_pctrl_ops = {
-       .list_groups = foo_list_groups,
+       .get_groups_count = foo_get_groups_count,
        .get_group_name = foo_get_group_name,
        .get_group_pins = foo_get_group_pins,
 };
@@ -186,13 +184,12 @@ static struct pinctrl_desc foo_desc = {
        .pctlops = &foo_pctrl_ops,
 };
 
-The pin control subsystem will call the .list_groups() function repeatedly
-beginning on 0 until it returns non-zero to determine legal selectors, then
-it will call the other functions to retrieve the name and pins of the group.
-Maintaining the data structure of the groups is up to the driver, this is
-just a simple example - in practice you may need more entries in your group
-structure, for example specific register ranges associated with each group
-and so on.
+The pin control subsystem will call the .get_groups_count() function to
+determine total number of legal selectors, then it will call the other functions
+to retrieve the name and pins of the group. Maintaining the data structure of
+the groups is up to the driver, this is just a simple example - in practice you
+may need more entries in your group structure, for example specific register
+ranges associated with each group and so on.
 
 
 Pin configuration
@@ -606,11 +603,9 @@ static const struct foo_group foo_groups[] = {
 };
 
 
-static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int foo_get_groups_count(struct pinctrl_dev *pctldev)
 {
-       if (selector >= ARRAY_SIZE(foo_groups))
-               return -EINVAL;
-       return 0;
+       return ARRAY_SIZE(foo_groups);
 }
 
 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
@@ -629,7 +624,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinctrl_ops foo_pctrl_ops = {
-       .list_groups = foo_list_groups,
+       .get_groups_count = foo_get_groups_count,
        .get_group_name = foo_get_group_name,
        .get_group_pins = foo_get_group_pins,
 };
@@ -640,7 +635,7 @@ struct foo_pmx_func {
        const unsigned num_groups;
 };
 
-static const char * const spi0_groups[] = { "spi0_1_grp" };
+static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
 static const char * const i2c0_groups[] = { "i2c0_grp" };
 static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
                                        "mmc0_3_grp" };
@@ -663,11 +658,9 @@ static const struct foo_pmx_func foo_functions[] = {
        },
 };
 
-int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+int foo_get_functions_count(struct pinctrl_dev *pctldev)
 {
-       if (selector >= ARRAY_SIZE(foo_functions))
-               return -EINVAL;
-       return 0;
+       return ARRAY_SIZE(foo_functions);
 }
 
 const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
@@ -703,7 +696,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 struct pinmux_ops foo_pmxops = {
-       .list_functions = foo_list_funcs,
+       .get_functions_count = foo_get_functions_count,
        .get_function_name = foo_get_fname,
        .get_function_groups = foo_get_groups,
        .enable = foo_enable,
@@ -786,7 +779,7 @@ and spi on the second function mapping:
 
 #include <linux/pinctrl/machine.h>
 
-static const struct pinctrl_map __initdata mapping[] = {
+static const struct pinctrl_map mapping[] __initconst = {
        {
                .dev_name = "foo-spi.0",
                .name = PINCTRL_STATE_DEFAULT,
@@ -952,13 +945,13 @@ case), we define a mapping like this:
 The result of grabbing this mapping from the device with something like
 this (see next paragraph):
 
-       p = pinctrl_get(dev);
+       p = devm_pinctrl_get(dev);
        s = pinctrl_lookup_state(p, "8bit");
        ret = pinctrl_select_state(p, s);
 
 or more simply:
 
-       p = pinctrl_get_select(dev, "8bit");
+       p = devm_pinctrl_get_select(dev, "8bit");
 
 Will be that you activate all the three bottom records in the mapping at
 once. Since they share the same name, pin controller device, function and
@@ -992,7 +985,7 @@ foo_probe()
        /* Allocate a state holder named "foo" etc */
        struct foo_state *foo = ...;
 
-       foo->p = pinctrl_get(&device);
+       foo->p = devm_pinctrl_get(&device);
        if (IS_ERR(foo->p)) {
                /* FIXME: clean up "foo" here */
                return PTR_ERR(foo->p);
@@ -1000,24 +993,17 @@ foo_probe()
 
        foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
        if (IS_ERR(foo->s)) {
-               pinctrl_put(foo->p);
                /* FIXME: clean up "foo" here */
                return PTR_ERR(s);
        }
 
        ret = pinctrl_select_state(foo->s);
        if (ret < 0) {
-               pinctrl_put(foo->p);
                /* FIXME: clean up "foo" here */
                return ret;
        }
 }
 
-foo_remove()
-{
-       pinctrl_put(state->p);
-}
-
 This get/lookup/select/put sequence can just as well be handled by bus drivers
 if you don't want each and every driver to handle it and you know the
 arrangement on your bus.
@@ -1029,6 +1015,11 @@ The semantics of the pinctrl APIs are:
   kernel memory to hold the pinmux state. All mapping table parsing or similar
   slow operations take place within this API.
 
+- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
+  to be called automatically on the retrieved pointer when the associated
+  device is removed. It is recommended to use this function over plain
+  pinctrl_get().
+
 - pinctrl_lookup_state() is called in process context to obtain a handle to a
   specific state for a the client device. This operation may be slow too.
 
@@ -1041,14 +1032,30 @@ The semantics of the pinctrl APIs are:
 
 - pinctrl_put() frees all information associated with a pinctrl handle.
 
+- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
+  explicitly destroy a pinctrl object returned by devm_pinctrl_get().
+  However, use of this function will be rare, due to the automatic cleanup
+  that will occur even without calling it.
+
+  pinctrl_get() must be paired with a plain pinctrl_put().
+  pinctrl_get() may not be paired with devm_pinctrl_put().
+  devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
+  devm_pinctrl_get() may not be paired with plain pinctrl_put().
+
 Usually the pin control core handled the get/put pair and call out to the
 device drivers bookkeeping operations, like checking available functions and
 the associated pins, whereas the enable/disable pass on to the pin controller
 driver which takes care of activating and/or deactivating the mux setting by
 quickly poking some registers.
 
-The pins are allocated for your device when you issue the pinctrl_get() call,
-after this you should be able to see this in the debugfs listing of all pins.
+The pins are allocated for your device when you issue the devm_pinctrl_get()
+call, after this you should be able to see this in the debugfs listing of all
+pins.
+
+NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
+requested pinctrl handles, for example if the pinctrl driver has not yet
+registered. Thus make sure that the error path in your driver gracefully
+cleans up and is ready to retry the probing later in the startup process.
 
 
 System pin control hogging
@@ -1094,13 +1101,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
 
 #include <linux/pinctrl/consumer.h>
 
-foo_switch()
-{
-       struct pinctrl *p;
-       struct pinctrl_state *s1, *s2;
+struct pinctrl *p;
+struct pinctrl_state *s1, *s2;
 
+foo_probe()
+{
        /* Setup */
-       p = pinctrl_get(&device);
+       p = devm_pinctrl_get(&device);
        if (IS_ERR(p))
                ...
 
@@ -1111,7 +1118,10 @@ foo_switch()
        s2 = pinctrl_lookup_state(foo->p, "pos-B");
        if (IS_ERR(s2))
                ...
+}
 
+foo_switch()
+{
        /* Enable on position A */
        ret = pinctrl_select_state(s1);
        if (ret < 0)
@@ -1125,8 +1135,6 @@ foo_switch()
            ...
 
        ...
-
-       pinctrl_put(p);
 }
 
 The above has to be done from process context.

diff --git a/Documentation/power/freezing-of-tasks.txt b/Documentation/power/freezing-of-tasks.txt
index ec715cd..6ec291e 100644 (file)
--- a/Documentation/power/freezing-of-tasks.txt
+++ b/Documentation/power/freezing-of-tasks.txt
@@ -9,7 +9,7 @@ architectures).
 
 II. How does it work?
 
-There are four per-task flags used for that, PF_NOFREEZE, PF_FROZEN, TIF_FREEZE
+There are three per-task flags used for that, PF_NOFREEZE, PF_FROZEN
 and PF_FREEZER_SKIP (the last one is auxiliary).  The tasks that have
 PF_NOFREEZE unset (all user space processes and some kernel threads) are
 regarded as 'freezable' and treated in a special way before the system enters a
@@ -17,30 +17,31 @@ suspend state as well as before a hibernation image is created (in what follows
 we only consider hibernation, but the description also applies to suspend).
 
 Namely, as the first step of the hibernation procedure the function
-freeze_processes() (defined in kernel/power/process.c) is called.  It executes
-try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
-either wakes them up, if they are kernel threads, or sends fake signals to them,
-if they are user space processes.  A task that has TIF_FREEZE set, should react
-to it by calling the function called __refrigerator() (defined in
-kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
-to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
-Then, we say that the task is 'frozen' and therefore the set of functions
-handling this mechanism is referred to as 'the freezer' (these functions are
-defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
-User space processes are generally frozen before kernel threads.
+freeze_processes() (defined in kernel/power/process.c) is called.  A system-wide
+variable system_freezing_cnt (as opposed to a per-task flag) is used to indicate
+whether the system is to undergo a freezing operation. And freeze_processes()
+sets this variable.  After this, it executes try_to_freeze_tasks() that sends a
+fake signal to all user space processes, and wakes up all the kernel threads.
+All freezable tasks must react to that by calling try_to_freeze(), which
+results in a call to __refrigerator() (defined in kernel/freezer.c), which sets
+the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes
+it loop until PF_FROZEN is cleared for it. Then, we say that the task is
+'frozen' and therefore the set of functions handling this mechanism is referred
+to as 'the freezer' (these functions are defined in kernel/power/process.c,
+kernel/freezer.c & include/linux/freezer.h). User space processes are generally
+frozen before kernel threads.
 
 __refrigerator() must not be called directly.  Instead, use the
 try_to_freeze() function (defined in include/linux/freezer.h), that checks
-the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the
-flag is set.
+if the task is to be frozen and makes the task enter __refrigerator().
 
 For user space processes try_to_freeze() is called automatically from the
 signal-handling code, but the freezable kernel threads need to call it
 explicitly in suitable places or use the wait_event_freezable() or
 wait_event_freezable_timeout() macros (defined in include/linux/freezer.h)
-that combine interruptible sleep with checking if TIF_FREEZE is set and calling
-try_to_freeze().  The main loop of a freezable kernel thread may look like the
-following one:
+that combine interruptible sleep with checking if the task is to be frozen and
+calling try_to_freeze().  The main loop of a freezable kernel thread may look
+like the following one:
 
        set_freezable();
        do {
@@ -53,7 +54,7 @@ following one:
 (from drivers/usb/core/hub.c::hub_thread()).
 
 If a freezable kernel thread fails to call try_to_freeze() after the freezer has
-set TIF_FREEZE for it, the freezing of tasks will fail and the entire
+initiated a freezing operation, the freezing of tasks will fail and the entire
 hibernation operation will be cancelled.  For this reason, freezable kernel
 threads must call try_to_freeze() somewhere or use one of the
 wait_event_freezable() and wait_event_freezable_timeout() macros.

diff --git a/Documentation/security/keys.txt b/Documentation/security/keys.txt
index 7877170..d389acd 100644 (file)
--- a/Documentation/security/keys.txt
+++ b/Documentation/security/keys.txt
@@ -123,7 +123,7 @@ KEY SERVICE OVERVIEW
 
 The key service provides a number of features besides keys:
 
- (*) The key service defines two special key types:
+ (*) The key service defines three special key types:
 
      (+) "keyring"
 
@@ -137,6 +137,18 @@ The key service provides a number of features besides keys:
         blobs of data. These can be created, updated and read by userspace,
         and aren't intended for use by kernel services.
 
+     (+) "logon"
+
+        Like a "user" key, a "logon" key has a payload that is an arbitrary
+        blob of data. It is intended as a place to store secrets which are
+        accessible to the kernel but not to userspace programs.
+
+        The description can be arbitrary, but must be prefixed with a non-zero
+        length string that describes the key "subclass". The subclass is
+        separated from the rest of the description by a ':'. "logon" keys can
+        be created and updated from userspace, but the payload is only
+        readable from kernel space.
+
  (*) Each process subscribes to three keyrings: a thread-specific keyring, a
      process-specific keyring, and a session-specific keyring.
 

diff --git a/MAINTAINERS b/MAINTAINERS
index 164e9a1..09c8892 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1978,10 +1978,7 @@ S:       Maintained
 F:     drivers/net/ethernet/ti/cpmac.c
 
 CPU FREQUENCY DRIVERS
-M:     Dave Jones <davej@redhat.com>
 L:     cpufreq@vger.kernel.org
-W:     http://www.codemonkey.org.uk/projects/cpufreq/
-T:     git git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq.git
 S:     Maintained
 F:     drivers/cpufreq/
 F:     include/linux/cpufreq.h
@@ -3602,6 +3599,7 @@ S:        Supported
 F:     drivers/net/wireless/iwlegacy/
 
 INTEL WIRELESS WIFI LINK (iwlwifi)
+M:     Johannes Berg <johannes.berg@intel.com>
 M:     Wey-Yi Guy <wey-yi.w.guy@intel.com>
 M:     Intel Linux Wireless <ilw@linux.intel.com>
 L:     linux-wireless@vger.kernel.org
@@ -5244,6 +5242,14 @@ M:       Linus Walleij <linus.walleij@linaro.org>
 S:     Maintained
 F:     drivers/pinctrl/
 
+PIN CONTROLLER - ST SPEAR
+M:     Viresh Kumar <viresh.kumar@st.com>
+L:     spear-devel@list.st.com
+L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+W:     http://www.st.com/spear
+S:     Maintained
+F:     driver/pinctrl/spear/
+
 PKTCDVD DRIVER
 M:     Peter Osterlund <petero2@telia.com>
 S:     Maintained
@@ -5901,11 +5907,11 @@ F:      Documentation/scsi/st.txt
 F:     drivers/scsi/st*
 
 SCTP PROTOCOL
-M:     Vlad Yasevich <vladislav.yasevich@hp.com>
+M:     Vlad Yasevich <vyasevich@gmail.com>
 M:     Sridhar Samudrala <sri@us.ibm.com>
 L:     linux-sctp@vger.kernel.org
 W:     http://lksctp.sourceforge.net
-S:     Supported
+S:     Maintained
 F:     Documentation/networking/sctp.txt
 F:     include/linux/sctp.h
 F:     include/net/sctp/
@@ -6336,24 +6342,7 @@ L:       spear-devel@list.st.com
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:     http://www.st.com/spear
 S:     Maintained
-F:     arch/arm/mach-spear*/clock.c
-F:     arch/arm/plat-spear/clock.c
-F:     arch/arm/plat-spear/include/plat/clock.h
-
-SPEAR PAD MULTIPLEXING SUPPORT
-M:     Viresh Kumar <viresh.kumar@st.com>
-L:     spear-devel@list.st.com
-L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-W:     http://www.st.com/spear
-S:     Maintained
-F:     arch/arm/plat-spear/include/plat/padmux.h
-F:     arch/arm/plat-spear/padmux.c
-F:     arch/arm/mach-spear*/spear*xx.c
-F:     arch/arm/mach-spear*/include/mach/generic.h
-F:     arch/arm/mach-spear3xx/spear3*0.c
-F:     arch/arm/mach-spear3xx/spear3*0_evb.c
-F:     arch/arm/mach-spear6xx/spear600.c
-F:     arch/arm/mach-spear6xx/spear600_evb.c
+F:     drivers/clk/spear/
 
 SPI SUBSYSTEM
 M:     Grant Likely <grant.likely@secretlab.ca>
@@ -7588,8 +7577,8 @@ F:        Documentation/filesystems/xfs.txt
 F:     fs/xfs/
 
 XILINX AXI ETHERNET DRIVER
-M:     Ariane Keller <ariane.keller@tik.ee.ethz.ch>
-M:     Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
+M:     Anirudha Sarangi <anirudh@xilinx.com>
+M:     John Linn <John.Linn@xilinx.com>
 S:     Maintained
 F:     drivers/net/ethernet/xilinx/xilinx_axienet*
 

diff --git a/Makefile b/Makefile
index afc868e..9e384ae 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 3
 PATCHLEVEL = 4
 SUBLEVEL = 0
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc6
 NAME = Saber-toothed Squirrel
 
 # *DOCUMENTATION*

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 56a4df9..22e58a9 100644 (file)
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -477,7 +477,7 @@ config ALPHA_BROKEN_IRQ_MASK
 
 config VGA_HOSE
        bool
-       depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI
+       depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI)
        default y
        help
          Support VGA on an arbitrary hose; needed for several platforms

diff --git a/arch/alpha/include/asm/rtc.h b/arch/alpha/include/asm/rtc.h
index 1f7fba6..d70408d 100644 (file)
--- a/arch/alpha/include/asm/rtc.h
+++ b/arch/alpha/include/asm/rtc.h
@@ -1,14 +1,10 @@
 #ifndef _ALPHA_RTC_H
 #define _ALPHA_RTC_H
 
-#if defined(CONFIG_ALPHA_GENERIC)
+#if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) \
+ || defined(CONFIG_ALPHA_GENERIC)
 # define get_rtc_time          alpha_mv.rtc_get_time
 # define set_rtc_time          alpha_mv.rtc_set_time
-#else
-# if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP)
-#  define get_rtc_time         marvel_get_rtc_time
-#  define set_rtc_time         marvel_set_rtc_time
-# endif
 #endif
 
 #include <asm-generic/rtc.h>

diff --git a/arch/alpha/kernel/core_tsunami.c b/arch/alpha/kernel/core_tsunami.c
index 5e7c28f..61893d7 100644 (file)
--- a/arch/alpha/kernel/core_tsunami.c
+++ b/arch/alpha/kernel/core_tsunami.c
@@ -11,6 +11,7 @@
 #include <asm/core_tsunami.h>
 #undef __EXTERN_INLINE
 
+#include <linux/module.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/sched.h>

diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index 14a4b6a..407accc 100644 (file)
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -317,7 +317,7 @@ marvel_init_irq(void)
 }
 
 static int 
-marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
        struct pci_controller *hose = dev->sysdata;
        struct io7_port *io7_port = hose->sysdata;

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9be624a..0a166b5 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -468,7 +468,9 @@ config ARCH_MXS
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
+       select COMMON_CLK
        select HAVE_CLK_PREPARE
+       select PINCTRL
        help
          Support for Freescale MXS-based family of processors
 
@@ -980,6 +982,7 @@ config PLAT_SPEAR
        select ARM_AMBA
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
+       select COMMON_CLK
        select CLKSRC_MMIO
        select GENERIC_CLOCKEVENTS
        select HAVE_CLK
@@ -1187,6 +1190,15 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config ARM_ERRATA_326103
+       bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
+       depends on CPU_V6
+       help
+         Executing a SWP instruction to read-only memory does not set bit 11
+         of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
+         treat the access as a read, preventing a COW from occurring and
+         causing the faulting task to livelock.
+
 config ARM_ERRATA_411920
        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
        depends on CPU_V6 || CPU_V6K

diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 15ded0d..45bc4bb 100644 (file)
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -10,7 +10,7 @@
        intc: interrupt-controller@02080000 {
                compatible = "qcom,msm-8660-qgic";
                interrupt-controller;
-               #interrupt-cells = <1>;
+               #interrupt-cells = <3>;
                reg = < 0x02080000 0x1000 >,
                      < 0x02081000 0x1000 >;
        };
@@ -19,6 +19,6 @@
                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                reg = <0x19c40000 0x1000>,
                      <0x19c00000 0x1000>;
-               interrupts = <195>;
+               interrupts = <0 195 0x0>;
        };
 };

diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644 (file)
index 0000000..fc82b1a
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,246 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear300.dtsi"
+
+/ {
+       model = "ST SPEAr300 Evaluation Board";
+       compatible = "st,spear300-evb", "st,spear300";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       memory {
+               reg = <0 0x40000000>;
+       };
+
+       ahb {
+               pinmux@99000000 {
+                       st,pinmux-mode = <2>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&state_default>;
+
+                       state_default: pinmux {
+                               i2c0 {
+                                       st,pins = "i2c0_grp";
+                                       st,function = "i2c0";
+                               };
+                               ssp0 {
+                                       st,pins = "ssp0_grp";
+                                       st,function = "ssp0";
+                               };
+                               mii0 {
+                                       st,pins = "mii0_grp";
+                                       st,function = "mii0";
+                               };
+                               uart0 {
+                                       st,pins = "uart0_grp";
+                                       st,function = "uart0";
+                               };
+                               clcd {
+                                       st,pins = "clcd_pfmode_grp";
+                                       st,function = "clcd";
+                               };
+                               sdhci {
+                                       st,pins = "sdhci_4bit_grp";
+                                       st,function = "sdhci";
+                               };
+                               gpio1 {
+                                       st,pins = "gpio1_4_to_7_grp",
+                                               "gpio1_0_to_3_grp";
+                                       st,function = "gpio1";
+                               };
+                       };
+               };
+
+               clcd@60000000 {
+                       status = "okay";
+               };
+
+               dma@fc400000 {
+                       status = "okay";
+               };
+
+               fsmc: flash@94000000 {
+                       status = "okay";
+               };
+
+               gmac: eth@e0800000 {
+                       status = "okay";
+               };
+
+               sdhci@70000000 {
+                       int-gpio = <&gpio1 0 0>;
+                       power-gpio = <&gpio1 2 1>;
+                       status = "okay";
+               };
+
+               smi: flash@fc000000 {
+                       status = "okay";
+                       clock-rate=<50000000>;
+
+                       flash@f8000000 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0xf8000000 0x800000>;
+                               st,smi-fast-mode;
+
+                               partition@0 {
+                                       label = "xloader";
+                                       reg = <0x0 0x10000>;
+                               };
+                               partition@10000 {
+                                       label = "u-boot";
+                                       reg = <0x10000 0x40000>;
+                               };
+                               partition@50000 {
+                                       label = "linux";
+                                       reg = <0x50000 0x2c0000>;
+                               };
+                               partition@310000 {
+                                       label = "rootfs";
+                                       reg = <0x310000 0x4f0000>;
+                               };
+                       };
+               };
+
+               spi0: spi@d0100000 {
+                       status = "okay";
+               };
+
+               ehci@e1800000 {
+                       status = "okay";
+               };
+
+               ohci@e1900000 {
+                       status = "okay";
+               };
+
+               ohci@e2100000 {
+                       status = "okay";
+               };
+
+               apb {
+                       gpio0: gpio@fc980000 {
+                              status = "okay";
+                       };
+
+                       gpio1: gpio@a9000000 {
+                              status = "okay";
+                       };
+
+                       i2c0: i2c@d0180000 {
+                              status = "okay";
+                       };
+
+                       kbd@a0000000 {
+                               linux,keymap = < 0x00000001
+                                                0x00010002
+                                                0x00020003
+                                                0x00030004
+                                                0x00040005
+                                                0x00050006
+                                                0x00060007
+                                                0x00070008
+                                                0x00080009
+                                                0x0100000a
+                                                0x0101000c
+                                                0x0102000d
+                                                0x0103000e
+                                                0x0104000f
+                                                0x01050010
+                                                0x01060011
+                                                0x01070012
+                                                0x01080013
+                                                0x02000014
+                                                0x02010015
+                                                0x02020016
+                                                0x02030017
+                                                0x02040018
+                                                0x02050019
+                                                0x0206001a
+                                                0x0207001b
+                                                0x0208001c
+                                                0x0300001d
+                                                0x0301001e
+                                                0x0302001f
+                                                0x03030020
+                                                0x03040021
+                                                0x03050022
+                                                0x03060023
+                                                0x03070024
+                                                0x03080025
+                                                0x04000026
+                                                0x04010027
+                                                0x04020028
+                                                0x04030029
+                                                0x0404002a
+                                                0x0405002b
+                                                0x0406002c
+                                                0x0407002d
+                                                0x0408002e
+                                                0x0500002f
+                                                0x05010030
+                                                0x05020031
+                                                0x05030032
+                                                0x05040033
+                                                0x05050034
+                                                0x05060035
+                                                0x05070036
+                                                0x05080037
+                                                0x06000038
+                                                0x06010039
+                                                0x0602003a
+                                                0x0603003b
+                                                0x0604003c
+                                                0x0605003d
+                                                0x0606003e
+                                                0x0607003f
+                                                0x06080040
+                                                0x07000041
+                                                0x07010042
+                                                0x07020043
+                                                0x07030044
+                                                0x07040045
+                                                0x07050046
+                                                0x07060047
+                                                0x07070048
+                                                0x07080049
+                                                0x0800004a
+                                                0x0801004b
+                                                0x0802004c
+                                                0x0803004d
+                                                0x0804004e
+                                                0x0805004f
+                                                0x08060050
+                                                0x08070051
+                                                0x08080052 >;
+                              autorepeat;
+                              st,mode = <0>;
+                              status = "okay";
+                       };
+
+                       rtc@fc900000 {
+                              status = "okay";
+                       };
+
+                       serial@d0000000 {
+                              status = "okay";
+                       };
+
+                       wdt@fc880000 {
+                              status = "okay";
+                       };
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644 (file)
index 0000000..01c5e35
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,77 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+       ahb {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               ranges = <0x60000000 0x60000000 0x50000000
+                         0xd0000000 0xd0000000 0x30000000>;
+
+               pinmux@99000000 {
+                       compatible = "st,spear300-pinmux";
+                       reg = <0x99000000 0x1000>;
+               };
+
+               clcd@60000000 {
+                       compatible = "arm,clcd-pl110", "arm,primecell";
+                       reg = <0x60000000 0x1000>;
+                       interrupts = <30>;
+                       status = "disabled";
+               };
+
+               fsmc: flash@94000000 {
+                       compatible = "st,spear600-fsmc-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x94000000 0x1000        /* FSMC Register */
+                              0x80000000 0x0010>;      /* NAND Base */
+                       reg-names = "fsmc_regs", "nand_data";
+                       st,ale-off = <0x20000>;
+                       st,cle-off = <0x10000>;
+                       status = "disabled";
+               };
+
+               sdhci@70000000 {
+                       compatible = "st,sdhci-spear";
+                       reg = <0x70000000 0x100>;
+                       interrupts = <1>;
+                       status = "disabled";
+               };
+
+               apb {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "simple-bus";
+                       ranges = <0xa0000000 0xa0000000 0x10000000
+                                 0xd0000000 0xd0000000 0x30000000>;
+
+                       gpio1: gpio@a9000000 {
+                               #gpio-cells = <2>;
+                               compatible = "arm,pl061", "arm,primecell";
+                               gpio-controller;
+                               reg = <0xa9000000 0x1000>;
+                               status = "disabled";
+                       };
+
+                       kbd@a0000000 {
+                               compatible = "st,spear300-kbd";
+                               reg = <0xa0000000 0x1000>;
+                               status = "disabled";
+                       };
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644 (file)
index 0000000..dc5e2d4
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,188 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear310.dtsi"
+
+/ {
+       model = "ST SPEAr310 Evaluation Board";
+       compatible = "st,spear310-evb", "st,spear310";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       memory {
+               reg = <0 0x40000000>;
+       };
+
+       ahb {
+               pinmux@b4000000 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&state_default>;
+
+                       state_default: pinmux {
+                               gpio0 {
+                                       st,pins = "gpio0_pin0_grp",
+                                               "gpio0_pin1_grp",
+                                               "gpio0_pin2_grp",
+                                               "gpio0_pin3_grp",
+                                               "gpio0_pin4_grp",
+                                               "gpio0_pin5_grp";
+                                       st,function = "gpio0";
+                               };
+                               i2c0 {
+                                       st,pins = "i2c0_grp";
+                                       st,function = "i2c0";
+                               };
+                               mii0 {
+                                       st,pins = "mii0_grp";
+                                       st,function = "mii0";
+                               };
+                               ssp0 {
+                                       st,pins = "ssp0_grp";
+                                       st,function = "ssp0";
+                               };
+                               uart0 {
+                                       st,pins = "uart0_grp";
+                                       st,function = "uart0";
+                               };
+                               emi {
+                                       st,pins = "emi_cs_0_to_5_grp";
+                                       st,function = "emi";
+                               };
+                               fsmc {
+                                       st,pins = "fsmc_grp";
+                                       st,function = "fsmc";
+                               };
+                               uart1 {
+                                       st,pins = "uart1_grp";
+                                       st,function = "uart1";
+                               };
+                               uart2 {
+                                       st,pins = "uart2_grp";
+                                       st,function = "uart2";
+                               };
+                               uart3 {
+                                       st,pins = "uart3_grp";
+                                       st,function = "uart3";
+                               };
+                               uart4 {
+                                       st,pins = "uart4_grp";
+                                       st,function = "uart4";
+                               };
+                               uart5 {
+                                       st,pins = "uart5_grp";
+                                       st,function = "uart5";
+                               };
+                       };
+               };
+
+               dma@fc400000 {
+                       status = "okay";
+               };
+
+               fsmc: flash@44000000 {
+                       status = "okay";
+               };
+
+               gmac: eth@e0800000 {
+                       status = "okay";
+               };
+
+               smi: flash@fc000000 {
+                       status = "okay";
+                       clock-rate=<50000000>;
+
+                       flash@f8000000 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0xf8000000 0x800000>;
+                               st,smi-fast-mode;
+
+                               partition@0 {
+                                       label = "xloader";
+                                       reg = <0x0 0x10000>;
+                               };
+                               partition@10000 {
+                                       label = "u-boot";
+                                       reg = <0x10000 0x40000>;
+                               };
+                               partition@50000 {
+                                       label = "linux";
+                                       reg = <0x50000 0x2c0000>;
+                               };
+                               partition@310000 {
+                                       label = "rootfs";
+                                       reg = <0x310000 0x4f0000>;
+                               };
+                       };
+               };
+
+               spi0: spi@d0100000 {
+                       status = "okay";
+               };
+
+               ehci@e1800000 {
+                       status = "okay";
+               };
+
+               ohci@e1900000 {
+                       status = "okay";
+               };
+
+               ohci@e2100000 {
+                       status = "okay";
+               };
+
+               apb {
+                       gpio0: gpio@fc980000 {
+                              status = "okay";
+                       };
+
+                       i2c0: i2c@d0180000 {
+                              status = "okay";
+                       };
+
+                       rtc@fc900000 {
+                              status = "okay";
+                       };
+
+                       serial@d0000000 {
+                              status = "okay";
+                       };
+
+                       serial@b2000000 {
+                              status = "okay";
+                       };
+
+                       serial@b2080000 {
+                              status = "okay";
+                       };
+
+                       serial@b2100000 {
+                              status = "okay";
+                       };
+
+                       serial@b2180000 {
+                              status = "okay";
+                       };
+
+                       serial@b2200000 {
+                              status = "okay";
+                       };
+
+                       wdt@fc880000 {
+                              status = "okay";
+                       };
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644 (file)
index 0000000..e47081c
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,80 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+       ahb {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               ranges = <0x40000000 0x40000000 0x10000000
+                         0xb0000000 0xb0000000 0x10000000
+                         0xd0000000 0xd0000000 0x30000000>;
+
+               pinmux@b4000000 {
+                       compatible = "st,spear310-pinmux";
+                       reg = <0xb4000000 0x1000>;
+               };
+
+               fsmc: flash@44000000 {
+                       compatible = "st,spear600-fsmc-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x44000000 0x1000        /* FSMC Register */
+                              0x40000000 0x0010>;      /* NAND Base */
+                       reg-names = "fsmc_regs", "nand_data";
+                       st,ale-off = <0x10000>;
+                       st,cle-off = <0x20000>;
+                       status = "disabled";
+               };
+
+               apb {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "simple-bus";
+                       ranges = <0xb0000000 0xb0000000 0x10000000
+                                 0xd0000000 0xd0000000 0x30000000>;
+
+                       serial@b2000000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0xb2000000 0x1000>;
+                               status = "disabled";
+                       };
+
+                       serial@b2080000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0xb2080000 0x1000>;
+                               status = "disabled";
+                       };
+
+                       serial@b2100000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0xb2100000 0x1000>;
+                               status = "disabled";
+                       };
+
+                       serial@b2180000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0xb2180000 0x1000>;
+                               status = "disabled";
+                       };
+
+                       serial@b2200000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0xb2200000 0x1000>;
+                               status = "disabled";
+                       };
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644 (file)
index 0000000..6308fa3
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,198 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear320.dtsi"
+
+/ {
+       model = "ST SPEAr300 Evaluation Board";
+       compatible = "st,spear300-evb", "st,spear300";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       memory {
+               reg = <0 0x40000000>;
+       };
+
+       ahb {
+               pinmux@b3000000 {
+                       st,pinmux-mode = <3>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&state_default>;
+
+                       state_default: pinmux {
+                               i2c0 {
+                                       st,pins = "i2c0_grp";
+                                       st,function = "i2c0";
+                               };
+                               mii0 {
+                                       st,pins = "mii0_grp";
+                                       st,function = "mii0";
+                               };
+                               ssp0 {
+                                       st,pins = "ssp0_grp";
+                                       st,function = "ssp0";
+                               };
+                               uart0 {
+                                       st,pins = "uart0_grp";
+                                       st,function = "uart0";
+                               };
+                               sdhci {
+                                       st,pins = "sdhci_cd_51_grp";
+                                       st,function = "sdhci";
+                               };
+                               i2s {
+                                       st,pins = "i2s_grp";
+                                       st,function = "i2s";
+                               };
+                               uart1 {
+                                       st,pins = "uart1_grp";
+                                       st,function = "uart1";
+                               };
+                               uart2 {
+                                       st,pins = "uart2_grp";
+                                       st,function = "uart2";
+                               };
+                               can0 {
+                                       st,pins = "can0_grp";
+                                       st,function = "can0";
+                               };
+                               can1 {
+                                       st,pins = "can1_grp";
+                                       st,function = "can1";
+                               };
+                               mii2 {
+                                       st,pins = "mii2_grp";
+                                       st,function = "mii2";
+                               };
+                               pwm0_1 {
+                                       st,pins = "pwm0_1_pin_14_15_grp";
+                                       st,function = "pwm0_1";
+                               };
+                               pwm2 {
+                                       st,pins = "pwm2_pin_13_grp";
+                                       st,function = "pwm2";
+                               };
+                       };
+               };
+
+               clcd@90000000 {
+                       status = "okay";
+               };
+
+               dma@fc400000 {
+                       status = "okay";
+               };
+
+               fsmc: flash@4c000000 {
+                       status = "okay";
+               };
+
+               gmac: eth@e0800000 {
+                       status = "okay";
+               };
+
+               sdhci@70000000 {
+                       power-gpio = <&gpio0 2 1>;
+                       power_always_enb;
+                       status = "okay";
+               };
+
+               smi: flash@fc000000 {
+                       status = "okay";
+                       clock-rate=<50000000>;
+
+                       flash@f8000000 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0xf8000000 0x800000>;
+                               st,smi-fast-mode;
+
+                               partition@0 {
+                                       label = "xloader";
+                                       reg = <0x0 0x10000>;
+                               };
+                               partition@10000 {
+                                       label = "u-boot";
+                                       reg = <0x10000 0x40000>;
+                               };
+                               partition@50000 {
+                                       label = "linux";
+                                       reg = <0x50000 0x2c0000>;
+                               };
+                               partition@310000 {
+                                       label = "rootfs";
+                                       reg = <0x310000 0x4f0000>;
+                               };
+                       };
+               };
+
+               spi0: spi@d0100000 {
+                       status = "okay";
+               };
+
+               spi1: spi@a5000000 {
+                       status = "okay";
+               };
+
+               spi2: spi@a6000000 {
+                       status = "okay";
+               };
+
+               ehci@e1800000 {
+                       status = "okay";
+               };
+
+               ohci@e1900000 {
+                       status = "okay";
+               };
+
+               ohci@e2100000 {
+                       status = "okay";
+               };
+
+               apb {
+                       gpio0: gpio@fc980000 {
+                              status = "okay";
+                       };
+
+                       i2c0: i2c@d0180000 {
+                              status = "okay";
+                       };
+
+                       i2c1: i2c@a7000000 {
+                              status = "okay";
+                       };
+
+                       rtc@fc900000 {
+                              status = "okay";
+                       };
+
+                       serial@d0000000 {
+                              status = "okay";
+                       };
+
+                       serial@a3000000 {
+                              status = "okay";
+                       };
+
+                       serial@a4000000 {
+                              status = "okay";
+                       };
+
+                       wdt@fc880000 {
+                              status = "okay";
+                       };
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644 (file)
index 0000000..5372ca3
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,95 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "spear3xx.dtsi"
+
+/ {
+       ahb {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               ranges = <0x40000000 0x40000000 0x80000000
+                         0xd0000000 0xd0000000 0x30000000>;
+
+               pinmux@b3000000 {
+                       compatible = "st,spear320-pinmux";
+                       reg = <0xb3000000 0x1000>;
+               };
+
+               clcd@90000000 {
+                       compatible = "arm,clcd-pl110", "arm,primecell";
+                       reg = <0x90000000 0x1000>;
+                       interrupts = <33>;
+                       status = "disabled";
+               };
+
+               fsmc: flash@4c000000 {
+                       compatible = "st,spear600-fsmc-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x4c000000 0x1000        /* FSMC Register */
+                              0x50000000 0x0010>;      /* NAND Base */
+                       reg-names = "fsmc_regs", "nand_data";
+                       st,ale-off = <0x20000>;
+                       st,cle-off = <0x10000>;
+                       status = "disabled";
+               };
+
+               sdhci@70000000 {
+                       compatible = "st,sdhci-spear";
+                       reg = <0x70000000 0x100>;
+                       interrupts = <29>;
+                       status = "disabled";
+               };
+
+               spi1: spi@a5000000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0xa5000000 0x1000>;
+                       status = "disabled";
+               };
+
+               spi2: spi@a6000000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0xa6000000 0x1000>;
+                       status = "disabled";
+               };
+
+               apb {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "simple-bus";
+                       ranges = <0xa0000000 0xa0000000 0x10000000
+                                 0xd0000000 0xd0000000 0x30000000>;
+
+                       i2c1: i2c@a7000000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "snps,designware-i2c";
+                               reg = <0xa7000000 0x1000>;
+                               status = "disabled";
+                       };
+
+                       serial@a3000000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0xa3000000 0x1000>;
+                               status = "disabled";
+                       };
+
+                       serial@a4000000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0xa4000000 0x1000>;
+                               status = "disabled";
+                       };
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644 (file)
index 0000000..9107255
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,150 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+       interrupt-parent = <&vic>;
+
+       cpus {
+               cpu@0 {
+                       compatible = "arm,arm926ejs";
+               };
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
+
+       ahb {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+               vic: interrupt-controller@f1100000 {
+                       compatible = "arm,pl190-vic";
+                       interrupt-controller;
+                       reg = <0xf1100000 0x1000>;
+                       #interrupt-cells = <1>;
+               };
+
+               dma@fc400000 {
+                       compatible = "arm,pl080", "arm,primecell";
+                       reg = <0xfc400000 0x1000>;
+                       interrupt-parent = <&vic>;
+                       interrupts = <8>;
+                       status = "disabled";
+               };
+
+               gmac: eth@e0800000 {
+                       compatible = "st,spear600-gmac";
+                       reg = <0xe0800000 0x8000>;
+                       interrupts = <23 22>;
+                       interrupt-names = "macirq", "eth_wake_irq";
+                       status = "disabled";
+               };
+
+               smi: flash@fc000000 {
+                       compatible = "st,spear600-smi";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0xfc000000 0x1000>;
+                       interrupts = <9>;
+                       status = "disabled";
+               };
+
+               spi0: spi@d0100000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0xd0100000 0x1000>;
+                       interrupts = <20>;
+                       status = "disabled";
+               };
+
+               ehci@e1800000 {
+                       compatible = "st,spear600-ehci", "usb-ehci";
+                       reg = <0xe1800000 0x1000>;
+                       interrupts = <26>;
+                       status = "disabled";
+               };
+
+               ohci@e1900000 {
+                       compatible = "st,spear600-ohci", "usb-ohci";
+                       reg = <0xe1900000 0x1000>;
+                       interrupts = <25>;
+                       status = "disabled";
+               };
+
+               ohci@e2100000 {
+                       compatible = "st,spear600-ohci", "usb-ohci";
+                       reg = <0xe2100000 0x1000>;
+                       interrupts = <27>;
+                       status = "disabled";
+               };
+
+               apb {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "simple-bus";
+                       ranges = <0xd0000000 0xd0000000 0x30000000>;
+
+                       gpio0: gpio@fc980000 {
+                               compatible = "arm,pl061", "arm,primecell";
+                               reg = <0xfc980000 0x1000>;
+                               interrupts = <11>;
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               status = "disabled";
+                       };
+
+                       i2c0: i2c@d0180000 {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               compatible = "snps,designware-i2c";
+                               reg = <0xd0180000 0x1000>;
+                               interrupts = <21>;
+                               status = "disabled";
+                       };
+
+                       rtc@fc900000 {
+                               compatible = "st,spear-rtc";
+                               reg = <0xfc900000 0x1000>;
+                               interrupts = <10>;
+                               status = "disabled";
+                       };
+
+                       serial@d0000000 {
+                               compatible = "arm,pl011", "arm,primecell";
+                               reg = <0xd0000000 0x1000>;
+                               interrupts = <19>;
+                               status = "disabled";
+                       };
+
+                       wdt@fc880000 {
+                               compatible = "arm,sp805", "arm,primecell";
+                               reg = <0xfc880000 0x1000>;
+                               interrupts = <12>;
+                               status = "disabled";
+                       };
+
+                       timer@f0000000 {
+                               compatible = "st,spear-timer";
+                               reg = <0xf0000000 0x400>;
+                               interrupts = <2>;
+                       };
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e..1119c22 100644 (file)
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,11 +24,44 @@
        };
 
        ahb {
+               dma@fc400000 {
+                       status = "okay";
+               };
+
                gmac: ethernet@e0800000 {
                        phy-mode = "gmii";
                        status = "okay";
                };
 
+               smi: flash@fc000000 {
+                       status = "okay";
+                       clock-rate=<50000000>;
+
+                       flash@f8000000 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               reg = <0xf8000000 0x800000>;
+                               st,smi-fast-mode;
+
+                               partition@0 {
+                                       label = "xloader";
+                                       reg = <0x0 0x10000>;
+                               };
+                               partition@10000 {
+                                       label = "u-boot";
+                                       reg = <0x10000 0x40000>;
+                               };
+                               partition@50000 {
+                                       label = "linux";
+                                       reg = <0x50000 0x2c0000>;
+                               };
+                               partition@310000 {
+                                       label = "rootfs";
+                                       reg = <0x310000 0x4f0000>;
+                               };
+                       };
+               };
+
                apb {
                        serial@d0000000 {
                                status = "okay";

diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885..089f0a4 100644 (file)
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
                        #interrupt-cells = <1>;
                };
 
+               dma@fc400000 {
+                       compatible = "arm,pl080", "arm,primecell";
+                       reg = <0xfc400000 0x1000>;
+                       interrupt-parent = <&vic1>;
+                       interrupts = <10>;
+                       status = "disabled";
+               };
+
                gmac: ethernet@e0800000 {
                        compatible = "st,spear600-gmac";
                        reg = <0xe0800000 0x8000>;
@@ -169,6 +177,12 @@
                                interrupts = <28>;
                                status = "disabled";
                        };
+
+                       timer@f0000000 {
+                               compatible = "st,spear-timer";
+                               reg = <0xf0000000 0x400>;
+                               interrupts = <16>;
+                       };
                };
        };
 };

diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 0b32925..e2fe319 100644 (file)
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -173,7 +173,7 @@
                        mmc@5000 {
                                compatible = "arm,primecell";
                                reg = < 0x5000 0x1000>;
-                               interrupts = <22>;
+                               interrupts = <22 34>;
                        };
                        kmi@6000 {
                                compatible = "arm,pl050", "arm,primecell";

diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 1664610..7e81752 100644 (file)
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -41,7 +41,7 @@
                        mmc@b000 {
                                compatible = "arm,primecell";
                                reg = <0xb000 0x1000>;
-                               interrupts = <23>;
+                               interrupts = <23 34>;
                        };
                };
        };

diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 42da918..082175c 100644 (file)
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_ARCH_S3C24XX=y
+# CONFIG_CPU_S3C2410 is not set
+CONFIG_CPU_S3C2440=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
 CONFIG_MACH_MINI2440=y

diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f..865980c 100644 (file)
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,70 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
-CONFIG_BOARD_SPEAR310_EVB=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR300=y
+CONFIG_MACH_SPEAR310=y
+CONFIG_MACH_SPEAR320=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +76,7 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
+CONFIG_JFFS2_FS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +84,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set

diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e83..a2a1265 100644 (file)
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,60 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +66,7 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
+CONFIG_JFFS2_FS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +74,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set

diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index d4c24d4..0f04d84 100644 (file)
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *);
 extern void vfp_sync_hwstate(struct thread_info *);
 extern void vfp_flush_hwstate(struct thread_info *);
 
+struct user_vfp;
+struct user_vfp_exc;
+
+extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,
+                                          struct user_vfp_exc __user *);
+extern int vfp_restore_user_hwstate(struct user_vfp __user *,
+                                   struct user_vfp_exc __user *);
 #endif
 
 /*

diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 60843eb..73409e6 100644 (file)
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -7,6 +7,8 @@
 
        .macro set_tls_v6k, tp, tmp1, tmp2
        mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+       mov     \tmp1, #0
+       mcr     p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
        .endm
 
        .macro set_tls_v6, tp, tmp1, tmp2
@@ -15,6 +17,8 @@
        mov     \tmp2, #0xffff0fff
        tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+       movne   \tmp1, #0
+       mcrne   p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
        streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
        .endm
 

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 71ccdbf..8349d4e 100644 (file)
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc)
        }
 
        c = irq_data_get_irq_chip(d);
-       if (c->irq_set_affinity)
-               c->irq_set_affinity(d, affinity, true);
-       else
+       if (!c->irq_set_affinity)
                pr_debug("IRQ%u: unable to set affinity\n", d->irq);
+       else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
+               cpumask_copy(d->affinity, affinity);
 
        return ret;
 }

diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 7cb532f..d68d1b6 100644 (file)
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
 
 static int preserve_vfp_context(struct vfp_sigframe __user *frame)
 {
-       struct thread_info *thread = current_thread_info();
-       struct vfp_hard_struct *h = &thread->vfpstate.hard;
        const unsigned long magic = VFP_MAGIC;
        const unsigned long size = VFP_STORAGE_SIZE;
        int err = 0;
 
-       vfp_sync_hwstate(thread);
        __put_user_error(magic, &frame->magic, err);
        __put_user_error(size, &frame->size, err);
 
-       /*
-        * Copy the floating point registers. There can be unused
-        * registers see asm/hwcap.h for details.
-        */
-       err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
-                             sizeof(h->fpregs));
-       /*
-        * Copy the status and control register.
-        */
-       __put_user_error(h->fpscr, &frame->ufp.fpscr, err);
-
-       /*
-        * Copy the exception registers.
-        */
-       __put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
-       __put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
-       __put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
+       if (err)
+               return -EFAULT;
 
-       return err ? -EFAULT : 0;
+       return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc);
 }
 
 static int restore_vfp_context(struct vfp_sigframe __user *frame)
 {
-       struct thread_info *thread = current_thread_info();
-       struct vfp_hard_struct *h = &thread->vfpstate.hard;
        unsigned long magic;
        unsigned long size;
-       unsigned long fpexc;
        int err = 0;
 
        __get_user_error(magic, &frame->magic, err);
@@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
        if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
                return -EINVAL;
 
-       vfp_flush_hwstate(thread);
-
-       /*
-        * Copy the floating point registers. There can be unused
-        * registers see asm/hwcap.h for details.
-        */
-       err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
-                               sizeof(h->fpregs));
-       /*
-        * Copy the status and control register.
-        */
-       __get_user_error(h->fpscr, &frame->ufp.fpscr, err);
-
-       /*
-        * Sanitise and restore the exception registers.
-        */
-       __get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
-       /* Ensure the VFP is enabled. */
-       fpexc |= FPEXC_EN;
-       /* Ensure FPINST2 is invalid and the exception flag is cleared. */
-       fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
-       h->fpexc = fpexc;
-
-       __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
-       __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
-
-       return err ? -EFAULT : 0;
+       return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc);
 }
 
 #endif

diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index addbbe8..f6a4d32 100644 (file)
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -510,10 +510,6 @@ static void ipi_cpu_stop(unsigned int cpu)
        local_fiq_disable();
        local_irq_disable();
 
-#ifdef CONFIG_HOTPLUG_CPU
-       platform_cpu_kill(cpu);
-#endif
-
        while (1)
                cpu_relax();
 }
@@ -576,17 +572,25 @@ void smp_send_reschedule(int cpu)
        smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static void smp_kill_cpus(cpumask_t *mask)
+{
+       unsigned int cpu;
+       for_each_cpu(cpu, mask)
+               platform_cpu_kill(cpu);
+}
+#else
+static void smp_kill_cpus(cpumask_t *mask) { }
+#endif
+
 void smp_send_stop(void)
 {
        unsigned long timeout;
+       struct cpumask mask;
 
-       if (num_online_cpus() > 1) {
-               struct cpumask mask;
-               cpumask_copy(&mask, cpu_online_mask);
-               cpumask_clear_cpu(smp_processor_id(), &mask);
-
-               smp_cross_call(&mask, IPI_CPU_STOP);
-       }
+       cpumask_copy(&mask, cpu_online_mask);
+       cpumask_clear_cpu(smp_processor_id(), &mask);
+       smp_cross_call(&mask, IPI_CPU_STOP);
 
        /* Wait up to one second for other CPUs to stop */
        timeout = USEC_PER_SEC;
@@ -595,6 +599,8 @@ void smp_send_stop(void)
 
        if (num_online_cpus() > 1)
                pr_warning("SMP: failed to stop secondary CPUs\n");
+
+       smp_kill_cpus(&mask);
 }
 
 /*

diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 5b150af..fef42b2 100644 (file)
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
         * The twd clock events must be reprogrammed to account for the new
         * frequency.  The timer is local to a cpu, so cross-call to the
         * changing cpu.
-        *
-        * Only wait for it to finish, if the cpu is active to avoid
-        * deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
-        * booting of that cpu.
         */
        if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
                smp_call_function_single(freqs->cpu, twd_update_frequency,
-                                        NULL, cpu_active(freqs->cpu));
+                       NULL, 1);
 
        return NOTIFY_OK;
 }

diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index df54c2a..6efd1e5 100644 (file)
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
                .ctrlbit        = (1 << 3),
        }, {
                .name           = "hsmmc",
-               .devname        = "s3c-sdhci.0",
+               .devname        = "exynos4-sdhci.0",
                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 5),
        }, {
                .name           = "hsmmc",
-               .devname        = "s3c-sdhci.1",
+               .devname        = "exynos4-sdhci.1",
                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 6),
        }, {
                .name           = "hsmmc",
-               .devname        = "s3c-sdhci.2",
+               .devname        = "exynos4-sdhci.2",
                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
                .name           = "hsmmc",
-               .devname        = "s3c-sdhci.3",
+               .devname        = "exynos4-sdhci.3",
                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 8),
@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
        .clk    = {
                .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.0",
+               .devname        = "exynos4-sdhci.0",
                .parent         = &exynos4_clk_dout_mmc0.clk,
                .enable         = exynos4_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 0),
@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
        .clk    = {
                .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.1",
+               .devname        = "exynos4-sdhci.1",
                .parent         = &exynos4_clk_dout_mmc1.clk,
                .enable         = exynos4_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 4),
@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
        .clk    = {
                .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.2",
+               .devname        = "exynos4-sdhci.2",
                .parent         = &exynos4_clk_dout_mmc2.clk,
                .enable         = exynos4_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 8),
@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
        .clk    = {
                .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.3",
+               .devname        = "exynos4-sdhci.3",
                .parent         = &exynos4_clk_dout_mmc3.clk,
                .enable         = exynos4_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 12),
@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-       CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+       CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+       CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+       CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+       CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
        CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982..5cd7a8b 100644 (file)
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
                .ctrlbit        = (1 << 20),
        }, {
                .name           = "hsmmc",
-               .devname        = "s3c-sdhci.0",
+               .devname        = "exynos4-sdhci.0",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 12),
        }, {
                .name           = "hsmmc",
-               .devname        = "s3c-sdhci.1",
+               .devname        = "exynos4-sdhci.1",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 13),
        }, {
                .name           = "hsmmc",
-               .devname        = "s3c-sdhci.2",
+               .devname        = "exynos4-sdhci.2",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 14),
        }, {
                .name           = "hsmmc",
-               .devname        = "s3c-sdhci.3",
+               .devname        = "exynos4-sdhci.3",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 15),
@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
        .clk    = {
                .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.0",
+               .devname        = "exynos4-sdhci.0",
                .parent         = &exynos5_clk_dout_mmc0.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 0),
@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
        .clk    = {
                .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.1",
+               .devname        = "exynos4-sdhci.1",
                .parent         = &exynos5_clk_dout_mmc1.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 4),
@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
        .clk    = {
                .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.2",
+               .devname        = "exynos4-sdhci.2",
                .parent         = &exynos5_clk_dout_mmc2.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 8),
@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
        .clk    = {
                .name           = "sclk_mmc",
-               .devname        = "s3c-sdhci.3",
+               .devname        = "exynos4-sdhci.3",
                .parent         = &exynos5_clk_dout_mmc3.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 12),
@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-       CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+       CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+       CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+       CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+       CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 8614aab..5ccd6e8 100644 (file)
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
        s3c_fimc_setname(2, "exynos4-fimc");
        s3c_fimc_setname(3, "exynos4-fimc");
 
+       s3c_sdhci_setname(0, "exynos4-sdhci");
+       s3c_sdhci_setname(1, "exynos4-sdhci");
+       s3c_sdhci_setname(2, "exynos4-sdhci");
+       s3c_sdhci_setname(3, "exynos4-sdhci");
+
        /* The I2C bus controllers are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
        s3c_i2c1_setname("s3c2440-i2c");
@@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
        s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
        s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
 
+       s3c_sdhci_setname(0, "exynos4-sdhci");
+       s3c_sdhci_setname(1, "exynos4-sdhci");
+       s3c_sdhci_setname(2, "exynos4-sdhci");
+       s3c_sdhci_setname(3, "exynos4-sdhci");
+
        /* The I2C bus controllers are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
        s3c_i2c1_setname("s3c2440-i2c");
@@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
 {
        int irq;
 
-       gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+#ifdef CONFIG_OF
+       of_irq_init(exynos4_dt_irq_match);
+#endif
 
        for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
index b025db4..7903501 100644 (file)
--- a/arch/arm/mach-exynos/dev-dwmci.c
+++ b/arch/arm/mach-exynos/dev-dwmci.c
@@ -16,6 +16,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/mmc/dw_mmc.h>
 
 #include <plat/devs.h>
@@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
 }
 
 static struct resource exynos4_dwmci_resource[] = {
-       [0] = {
-               .start  = EXYNOS4_PA_DWMCI,
-               .end    = EXYNOS4_PA_DWMCI + SZ_4K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       [1] = {
-               .start  = IRQ_DWMCI,
-               .end    = IRQ_DWMCI,
-               .flags  = IORESOURCE_IRQ,
-       }
+       [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
+       [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
 };
 
 static struct dw_mci_board exynos4_dwci_pdata = {

diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b4f1f90..ed90aef 100644 (file)
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
                                MMC_CAP_ERASE),
+       .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };

diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 7ebf79c..cb2b027 100644 (file)
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
        .max_width              = 8,
        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+       .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7561eca..a57a8ec 100644 (file)
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -34,6 +34,7 @@ config ARCH_MX53
 config SOC_IMX1
        bool
        select ARCH_MX1
+       select COMMON_CLK
        select CPU_ARM920T
        select IMX_HAVE_IOMUX_V1
        select MXC_AVIC
@@ -42,12 +43,14 @@ config SOC_IMX21
        bool
        select MACH_MX21
        select CPU_ARM926T
+       select COMMON_CLK
        select IMX_HAVE_IOMUX_V1
        select MXC_AVIC
 
 config SOC_IMX25
        bool
        select ARCH_MX25
+       select COMMON_CLK
        select CPU_ARM926T
        select ARCH_MXC_IOMUX_V3
        select MXC_AVIC
@@ -56,6 +59,7 @@ config SOC_IMX27
        bool
        select MACH_MX27
        select CPU_ARM926T
+       select COMMON_CLK
        select IMX_HAVE_IOMUX_V1
        select MXC_AVIC
 
@@ -64,12 +68,14 @@ config SOC_IMX31
        select CPU_V6
        select IMX_HAVE_PLATFORM_MXC_RNGA
        select MXC_AVIC
+       select COMMON_CLK
        select SMP_ON_UP if SMP
 
 config SOC_IMX35
        bool
        select CPU_V6
        select ARCH_MXC_IOMUX_V3
+       select COMMON_CLK
        select HAVE_EPIT
        select MXC_AVIC
        select SMP_ON_UP if SMP
@@ -77,6 +83,7 @@ config SOC_IMX35
 config SOC_IMX5
        select CPU_V7
        select MXC_TZIC
+       select COMMON_CLK
        select ARCH_MXC_IOMUX_V3
        select ARCH_HAS_CPUFREQ
        select ARCH_MX5
@@ -836,12 +843,15 @@ config SOC_IMX6Q
        bool "i.MX6 Quad support"
        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
+       select COMMON_CLK
        select CPU_V7
        select HAVE_ARM_SCU
        select HAVE_IMX_GPC
        select HAVE_IMX_MMDC
        select HAVE_IMX_SRC
        select HAVE_SMP
+       select PINCTRL
+       select PINCTRL_IMX6Q
        select USE_OF
 
        help

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ab939c5..629a339 100644 (file)
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,15 +1,18 @@
-obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
-obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
+obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o
+obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o
 
-obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
+obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
 
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
-obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
+obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
 
-obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
-obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o
+obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+
+obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
+                           clk-pfd.o clk-busy.o
 
 # Support for CMOS sensor interface
 obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -70,7 +73,7 @@ obj-$(CONFIG_CPU_V7) += head-v7.o
 AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o

diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
new file mode 100644 (file)
index 0000000..1a7a8dd
--- /dev/null
+++ b/arch/arm/mach-imx/clk-busy.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/err.h>
+#include "clk.h"
+
+static int clk_busy_wait(void __iomem *reg, u8 shift)
+{
+       unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+       while (readl_relaxed(reg) & (1 << shift))
+               if (time_after(jiffies, timeout))
+                       return -ETIMEDOUT;
+
+       return 0;
+}
+
+struct clk_busy_divider {
+       struct clk_divider div;
+       const struct clk_ops *div_ops;
+       void __iomem *reg;
+       u8 shift;
+};
+
+static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw)
+{
+       struct clk_divider *div = container_of(hw, struct clk_divider, hw);
+
+       return container_of(div, struct clk_busy_divider, div);
+}
+
+static unsigned long clk_busy_divider_recalc_rate(struct clk_hw *hw,
+                                                 unsigned long parent_rate)
+{
+       struct clk_busy_divider *busy = to_clk_busy_divider(hw);
+
+       return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate);
+}
+
+static long clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate,
+                                       unsigned long *prate)
+{
+       struct clk_busy_divider *busy = to_clk_busy_divider(hw);
+
+       return busy->div_ops->round_rate(&busy->div.hw, rate, prate);
+}
+
+static int clk_busy_divider_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       struct clk_busy_divider *busy = to_clk_busy_divider(hw);
+       int ret;
+
+       ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate);
+       if (!ret)
+               ret = clk_busy_wait(busy->reg, busy->shift);
+
+       return ret;
+}
+
+static struct clk_ops clk_busy_divider_ops = {
+       .recalc_rate = clk_busy_divider_recalc_rate,
+       .round_rate = clk_busy_divider_round_rate,
+       .set_rate = clk_busy_divider_set_rate,
+};
+
+struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
+                                void __iomem *reg, u8 shift, u8 width,
+                                void __iomem *busy_reg, u8 busy_shift)
+{
+       struct clk_busy_divider *busy;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       busy = kzalloc(sizeof(*busy), GFP_KERNEL);
+       if (!busy)
+               return ERR_PTR(-ENOMEM);
+
+       busy->reg = busy_reg;
+       busy->shift = busy_shift;
+
+       busy->div.reg = reg;
+       busy->div.shift = shift;
+       busy->div.width = width;
+       busy->div.lock = &imx_ccm_lock;
+       busy->div_ops = &clk_divider_ops;
+
+       init.name = name;
+       init.ops = &clk_busy_divider_ops;
+       init.flags = CLK_SET_RATE_PARENT;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       busy->div.hw.init = &init;
+
+       clk = clk_register(NULL, &busy->div.hw);
+       if (!clk)
+               kfree(busy);
+
+       return clk;
+}
+
+struct clk_busy_mux {
+       struct clk_mux mux;
+       const struct clk_ops *mux_ops;
+       void __iomem *reg;
+       u8 shift;
+};
+
+static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw)
+{
+       struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
+
+       return container_of(mux, struct clk_busy_mux, mux);
+}
+
+static u8 clk_busy_mux_get_parent(struct clk_hw *hw)
+{
+       struct clk_busy_mux *busy = to_clk_busy_mux(hw);
+
+       return busy->mux_ops->get_parent(&busy->mux.hw);
+}
+
+static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+       struct clk_busy_mux *busy = to_clk_busy_mux(hw);
+       int ret;
+
+       ret = busy->mux_ops->set_parent(&busy->mux.hw, index);
+       if (!ret)
+               ret = clk_busy_wait(busy->reg, busy->shift);
+
+       return ret;
+}
+
+struct clk_ops clk_busy_mux_ops = {
+       .get_parent = clk_busy_mux_get_parent,
+       .set_parent = clk_busy_mux_set_parent,
+};
+
+struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
+                            u8 width, void __iomem *busy_reg, u8 busy_shift,
+                            const char **parent_names, int num_parents)
+{
+       struct clk_busy_mux *busy;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       busy = kzalloc(sizeof(*busy), GFP_KERNEL);
+       if (!busy)
+               return ERR_PTR(-ENOMEM);
+
+       busy->reg = busy_reg;
+       busy->shift = busy_shift;
+
+       busy->mux.reg = reg;
+       busy->mux.shift = shift;
+       busy->mux.width = width;
+       busy->mux.lock = &imx_ccm_lock;
+       busy->mux_ops = &clk_mux_ops;
+
+       init.name = name;
+       init.ops = &clk_busy_mux_ops;
+       init.flags = 0;
+       init.parent_names = parent_names;
+       init.num_parents = num_parents;
+
+       busy->mux.hw.init = &init;
+
+       clk = clk_register(NULL, &busy->mux.hw);
+       if (IS_ERR(clk))
+               kfree(busy);
+
+       return clk;
+}

diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
new file mode 100644 (file)
index 0000000..3c1b8ff
--- /dev/null
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Gated clock implementation
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's ouput
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static int clk_gate2_enable(struct clk_hw *hw)
+{
+       struct clk_gate *gate = to_clk_gate(hw);
+       u32 reg;
+       unsigned long flags = 0;
+
+       if (gate->lock)
+               spin_lock_irqsave(gate->lock, flags);
+
+       reg = readl(gate->reg);
+       reg |= 3 << gate->bit_idx;
+       writel(reg, gate->reg);
+
+       if (gate->lock)
+               spin_unlock_irqrestore(gate->lock, flags);
+
+       return 0;
+}
+
+static void clk_gate2_disable(struct clk_hw *hw)
+{
+       struct clk_gate *gate = to_clk_gate(hw);
+       u32 reg;
+       unsigned long flags = 0;
+
+       if (gate->lock)
+               spin_lock_irqsave(gate->lock, flags);
+
+       reg = readl(gate->reg);
+       reg &= ~(3 << gate->bit_idx);
+       writel(reg, gate->reg);
+
+       if (gate->lock)
+               spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static int clk_gate2_is_enabled(struct clk_hw *hw)
+{
+       u32 reg;
+       struct clk_gate *gate = to_clk_gate(hw);
+
+       reg = readl(gate->reg);
+
+       if (((reg >> gate->bit_idx) & 3) == 3)
+               return 1;
+
+       return 0;
+}
+
+static struct clk_ops clk_gate2_ops = {
+       .enable = clk_gate2_enable,
+       .disable = clk_gate2_disable,
+       .is_enabled = clk_gate2_is_enabled,
+};
+
+struct clk *clk_register_gate2(struct device *dev, const char *name,
+               const char *parent_name, unsigned long flags,
+               void __iomem *reg, u8 bit_idx,
+               u8 clk_gate2_flags, spinlock_t *lock)
+{
+       struct clk_gate *gate;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+       if (!gate)
+               return ERR_PTR(-ENOMEM);
+
+       /* struct clk_gate assignments */
+       gate->reg = reg;
+       gate->bit_idx = bit_idx;
+       gate->flags = clk_gate2_flags;
+       gate->lock = lock;
+
+       init.name = name;
+       init.ops = &clk_gate2_ops;
+       init.flags = flags;
+       init.parent_names = parent_name ? &parent_name : NULL;
+       init.num_parents = parent_name ? 1 : 0;
+
+       gate->hw.init = &init;
+
+       clk = clk_register(dev, &gate->hw);
+       if (IS_ERR(clk))
+               kfree(clk);
+
+       return clk;
+}

diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
new file mode 100644 (file)
index 0000000..0f0beb5
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -0,0 +1,115 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include "clk.h"
+
+/* CCM register addresses */
+#define IO_ADDR_CCM(off)       (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+#define CCM_CSCR       IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0     IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0     IO_ADDR_CCM(0xc)
+#define CCM_PCDR       IO_ADDR_CCM(0x20)
+
+/* SCM register addresses */
+#define IO_ADDR_SCM(off)       (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+#define SCM_GCCR       IO_ADDR_SCM(0xc)
+
+static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
+static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem",
+                               "fclk", };
+enum imx1_clks {
+       dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu,
+       fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
+       mma_gate, usbd_gate, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx1_clocks_init(unsigned long fref)
+{
+       int i;
+
+       clk[dummy] = imx_clk_fixed("dummy", 0);
+       clk[clk32] = imx_clk_fixed("clk32", fref);
+       clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
+       clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
+       clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
+       clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
+                       ARRAY_SIZE(prem_sel_clks));
+       clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
+       clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
+       clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
+       clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1);
+       clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4);
+       clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3);
+       clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4);
+       clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4);
+       clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7);
+       clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
+                       ARRAY_SIZE(clko_sel_clks));
+       clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4);
+       clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
+       clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
+       clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("imx1 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+       clk_register_clkdev(clk[dma_gate], "ahb", "imx-dma");
+       clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
+       clk_register_clkdev(clk[mma_gate], "mma", NULL);
+       clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
+       clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
+       clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
+       clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
+       clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
+       clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
+       clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
+       clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
+       clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2");
+       clk_register_clkdev(clk[hclk], NULL, "imx-i2c.0");
+       clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
+       clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
+       clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
+       clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
+       clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
+       clk_register_clkdev(clk[per2], "per", "imx-fb.0");
+       clk_register_clkdev(clk[dummy], "ipg", "imx-fb.0");
+       clk_register_clkdev(clk[dummy], "ahb", "imx-fb.0");
+       clk_register_clkdev(clk[hclk], "mshc", NULL);
+       clk_register_clkdev(clk[per3], "ssi", NULL);
+       clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
+       clk_register_clkdev(clk[clko], "clko", NULL);
+
+       mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+                       MX1_TIM1_INT);
+
+       return 0;
+}

diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
new file mode 100644 (file)
index 0000000..4e4f384
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include "clk.h"
+
+#define IO_ADDR_CCM(off)       (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR               IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0             IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1             IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0             IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1             IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL          IO_ADDR_CCM(0x14)
+#define CCM_PCDR0              IO_ADDR_CCM(0x18)
+#define CCM_PCDR1              IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0              IO_ADDR_CCM(0x20)
+#define CCM_PCCR1              IO_ADDR_CCM(0x24)
+#define CCM_CCSR               IO_ADDR_CCM(0x28)
+#define CCM_PMCTL              IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT            IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL            IO_ADDR_CCM(0x34)
+
+static const char *mpll_sel_clks[] = { "fpm", "ckih", };
+static const char *spll_sel_clks[] = { "fpm", "ckih", };
+
+enum imx21_clks {
+       ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
+       per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
+       uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
+       pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
+       lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
+       per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
+       ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
+       emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
+       gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mx21_clocks_init(unsigned long lref, unsigned long href)
+{
+       int i;
+
+       clk[ckil] = imx_clk_fixed("ckil", lref);
+       clk[ckih] = imx_clk_fixed("ckih", href);
+       clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
+       clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
+                       ARRAY_SIZE(mpll_sel_clks));
+       clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
+                       ARRAY_SIZE(spll_sel_clks));
+       clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
+       clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
+       clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
+       clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
+       clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
+       clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
+       clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
+       clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
+       clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
+       clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
+       clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
+       clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
+       clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
+       clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
+       clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
+       clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
+       clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
+       clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
+       clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
+       clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
+       clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
+       clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
+       clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
+       clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
+       clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
+       clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
+       clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
+       clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
+       clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
+       clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
+       clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
+       clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
+       clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
+       clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
+       clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
+       clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
+       clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
+       clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
+       clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
+       clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
+       clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
+       clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
+       clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
+       clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
+       clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
+       clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("i.MX21 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+       clk_register_clkdev(clk[per1], "per1", NULL);
+       clk_register_clkdev(clk[per2], "per2", NULL);
+       clk_register_clkdev(clk[per3], "per3", NULL);
+       clk_register_clkdev(clk[per4], "per4", NULL);
+       clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
+       clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
+       clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
+       clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
+       clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
+       clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
+       clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
+       clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
+       clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
+       clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
+       clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
+       clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
+       clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
+       clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
+       clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
+       clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
+       clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
+       clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
+       clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
+       clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
+       clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
+       clk_register_clkdev(clk[per3], "per", "imx-fb.0");
+       clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
+       clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx-fb.0");
+       clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
+       clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
+       clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand.0");
+       clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx-dma");
+       clk_register_clkdev(clk[dma_gate], "ipg", "imx-dma");
+       clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
+       clk_register_clkdev(clk[i2c_gate], NULL, "imx-i2c.0");
+       clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
+       clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
+       clk_register_clkdev(clk[brom_gate], "brom", NULL);
+       clk_register_clkdev(clk[emma_gate], "emma", NULL);
+       clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
+       clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
+       clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
+       clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
+       clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
+       clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
+       clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
+       clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
+
+       mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
+                       MX21_INT_GPT1);
+       return 0;
+}

diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
new file mode 100644 (file)
index 0000000..d9833bb
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#include "clk.h"
+
+#define CRM_BASE       MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
+
+#define CCM_MPCTL      0x00
+#define CCM_UPCTL      0x04
+#define CCM_CCTL       0x08
+#define CCM_CGCR0      0x0C
+#define CCM_CGCR1      0x10
+#define CCM_CGCR2      0x14
+#define CCM_PCDR0      0x18
+#define CCM_PCDR1      0x1C
+#define CCM_PCDR2      0x20
+#define CCM_PCDR3      0x24
+#define CCM_RCSR       0x28
+#define CCM_CRDR       0x2C
+#define CCM_DCVR0      0x30
+#define CCM_DCVR1      0x34
+#define CCM_DCVR2      0x38
+#define CCM_DCVR3      0x3c
+#define CCM_LTR0       0x40
+#define CCM_LTR1       0x44
+#define CCM_LTR2       0x48
+#define CCM_LTR3       0x4c
+#define CCM_MCR                0x64
+
+#define ccm(x) (CRM_BASE + (x))
+
+static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
+static const char *per_sel_clks[] = { "ahb", "upll", };
+
+enum mx25_clks {
+       dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
+       per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel,
+       per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
+       per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
+       per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
+       csi_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, gpt_ipg_per, i2c_ipg_per,
+       lcdc_ipg_per, nfc_ipg_per, ssi1_ipg_per, ssi2_ipg_per, uart_ipg_per,
+       csi_ahb, esdhc1_ahb, esdhc2_ahb, fec_ahb, lcdc_ahb, sdma_ahb,
+       usbotg_ahb, can1_ipg, can2_ipg, csi_ipg, cspi1_ipg, cspi2_ipg,
+       cspi3_ipg, dryice_ipg, esdhc1_ipg, esdhc2_ipg, fec_ipg, iim_ipg,
+       kpp_ipg, lcdc_ipg, pwm1_ipg, pwm2_ipg, pwm3_ipg, pwm4_ipg, sdma_ipg,
+       ssi1_ipg, ssi2_ipg, tsc_ipg, uart1_ipg, uart2_ipg, uart3_ipg,
+       uart4_ipg, uart5_ipg, wdt_ipg, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx25_clocks_init(void)
+{
+       int i;
+
+       clk[dummy] = imx_clk_fixed("dummy", 0);
+       clk[osc] = imx_clk_fixed("osc", 24000000);
+       clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
+       clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
+       clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
+       clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+       clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2);
+       clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2);
+       clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); 
+       clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+       clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+       clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
+       clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
+       clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
+       clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6);
+       clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6);
+       clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6);
+       clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6);
+       clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6);
+       clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6);
+       clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6);
+       clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6);
+       clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6);
+       clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6);
+       clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6);
+       clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
+       clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
+       clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
+       clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0),  3);
+       clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0),  4);
+       clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0),  5);
+       clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0),  6);
+       clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per8", ccm(CCM_CGCR0),  7);
+       clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "ipg_per", ccm(CCM_CGCR0),  8);
+       clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
+       clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
+       clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
+       clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
+       clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
+       clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
+       clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
+       clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
+       clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
+       clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
+       clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1),  2);
+       clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1),  3);
+       clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1),  4);
+       clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1),  5);
+       clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1),  6);
+       clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1),  7);
+       clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1),  8);
+       clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
+       clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
+       clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
+       clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
+       clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
+       clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
+       clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
+       clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2),  0);
+       clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2),  1);
+       clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2),  2);
+       clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2),  6);
+       clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
+       clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
+       clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
+       clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14);
+       clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15);
+       clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
+       clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
+       clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
+       clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("i.MX25 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+       /* i.mx25 has the i.mx21 type uart */
+       clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
+       clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
+       clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
+       clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
+       clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
+       clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
+       clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
+       clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
+       clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
+       clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
+       clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+       clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
+       clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
+       clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
+       clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
+       clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
+       clk_register_clkdev(clk[nfc_ipg_per], NULL, "mxc_nand.0");
+       /* i.mx25 has the i.mx35 type cspi */
+       clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
+       clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
+       clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
+       clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
+       clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
+       clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
+       clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
+       clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
+       clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
+       clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
+       clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
+       clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
+       clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
+       clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.0");
+       clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.1");
+       clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx-i2c.2");
+       clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
+       clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
+       clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
+       clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx-fb.0");
+       clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
+       clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
+       clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
+       clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
+       clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
+       clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
+       clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
+       clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
+       clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
+       clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
+       clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
+       clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
+       clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
+       clk_register_clkdev(clk[csi_ipg_per], "per", "mx2-camera.0");
+       clk_register_clkdev(clk[csi_ipg], "ipg", "mx2-camera.0");
+       clk_register_clkdev(clk[csi_ahb], "ahb", "mx2-camera.0");
+       clk_register_clkdev(clk[dummy], "audmux", NULL);
+       clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
+       clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
+       /* i.mx25 has the i.mx35 type sdma */
+       clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
+       clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
+       clk_register_clkdev(clk[iim_ipg], "iim", NULL);
+
+       mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
+       return 0;
+}

diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
new file mode 100644 (file)
index 0000000..50a7ebd
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -0,0 +1,290 @@
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include "clk.h"
+
+#define IO_ADDR_CCM(off)       (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR               IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0             IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1             IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0             IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1             IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL          IO_ADDR_CCM(0x14)
+#define CCM_PCDR0              IO_ADDR_CCM(0x18)
+#define CCM_PCDR1              IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0              IO_ADDR_CCM(0x20)
+#define CCM_PCCR1              IO_ADDR_CCM(0x24)
+#define CCM_CCSR               IO_ADDR_CCM(0x28)
+#define CCM_PMCTL              IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT            IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL            IO_ADDR_CCM(0x34)
+
+#define CCM_CSCR_UPDATE_DIS    (1 << 31)
+#define CCM_CSCR_SSI2          (1 << 23)
+#define CCM_CSCR_SSI1          (1 << 22)
+#define CCM_CSCR_VPU           (1 << 21)
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           (1 << 0)
+
+/* i.MX27 TO 2+ */
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
+static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
+static const char *clko_sel_clks[] = {
+       "ckil", "prem", "ckih", "ckih",
+       "ckih", "mpll", "spll", "cpu_div",
+       "ahb", "ipg", "per1_div", "per2_div",
+       "per3_div", "per4_div", "ssi1_div", "ssi2_div",
+       "nfc_div", "mshc_div", "vpu_div", "60m",
+       "32k", "usb_div", "dptc",
+};
+
+static const char *ssi_sel_clks[] = { "spll", "mpll", };
+
+enum mx27_clks {
+       dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
+       per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
+       clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
+       clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
+       sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
+       rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
+       kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
+       gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
+       gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
+       emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
+       cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
+       vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
+       usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
+       vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
+       csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
+       uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
+       uart2_ipg_gate, uart1_ipg_gate, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx27_clocks_init(unsigned long fref)
+{
+       int i;
+
+       clk[dummy] = imx_clk_fixed("dummy", 0);
+       clk[ckih] = imx_clk_fixed("ckih", fref);
+       clk[ckil] = imx_clk_fixed("ckil", 32768);
+       clk[mpll] = imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0);
+       clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
+       clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
+
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
+               clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
+               clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+       } else {
+               clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
+               clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
+       }
+
+       clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
+       clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
+       clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
+       clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
+       clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
+       clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
+       clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 3);
+       clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
+       clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
+       clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
+               clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
+       else
+               clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
+       clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
+       clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+       clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
+       clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
+       clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 3);
+       clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
+       clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
+       clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
+       clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
+       clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
+       clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
+       clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
+       clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
+       clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
+       clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
+       clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
+       clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
+       clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
+       clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
+       clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
+       clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
+       clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
+       clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
+       clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
+       clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
+       clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
+       clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
+       clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
+       clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
+       clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
+       clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
+       clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
+       clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
+       clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
+       clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
+       clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
+       clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
+       clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
+       clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
+       clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
+       clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
+       clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
+       clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
+       clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
+       clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
+       clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
+       clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
+       clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
+       clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
+       clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
+       clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
+       clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
+       clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
+       clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
+       clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
+       clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
+       clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
+       clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
+       clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
+       clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
+       clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
+       clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
+       clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("i.MX27 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+       clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
+       clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
+       clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
+       clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
+       clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
+       clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
+       clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
+       clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
+       clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
+       clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
+       clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
+       clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
+       clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
+       clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
+       clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
+       clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1");
+       clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
+       clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2");
+       clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3");
+       clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3");
+       clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4");
+       clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
+       clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
+       clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
+       clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
+       clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.0");
+       clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "mxc-mmc.0");
+       clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.1");
+       clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.1");
+       clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.2");
+       clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.2");
+       clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
+       clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
+       clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
+       clk_register_clkdev(clk[per3_gate], "per", "imx-fb.0");
+       clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
+       clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx-fb.0");
+       clk_register_clkdev(clk[csi_ahb_gate], NULL, "mx2-camera.0");
+       clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
+       clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
+       clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
+       clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
+       clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
+       clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
+       clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
+       clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
+       clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
+       clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
+       clk_register_clkdev(clk[vpu_baud_gate], "per", "imx-vpu");
+       clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "imx-vpu");
+       clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
+       clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma");
+       clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
+       clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
+       clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
+       clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx-i2c.0");
+       clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx-i2c.1");
+       clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
+       clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
+       clk_register_clkdev(clk[emma_ahb_gate], "ahb", "imx-emma");
+       clk_register_clkdev(clk[emma_ipg_gate], "ipg", "imx-emma");
+       clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
+       clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
+       clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
+       clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
+       clk_register_clkdev(clk[rtc_ipg_gate], "rtc", NULL);
+       clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
+       clk_register_clkdev(clk[cpu_div], "cpu", NULL);
+       clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
+       clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
+       clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
+
+       mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+                       MX27_INT_GPT1);
+
+       clk_prepare_enable(clk[emi_ahb_gate]);
+
+       return 0;
+}
+
+#ifdef CONFIG_OF
+int __init mx27_clocks_init_dt(void)
+{
+       struct device_node *np;
+       u32 fref = 26000000; /* default */
+
+       for_each_compatible_node(np, NULL, "fixed-clock") {
+               if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
+                       continue;
+
+               if (!of_property_read_u32(np, "clock-frequency", &fref))
+                       break;
+       }
+
+       return mx27_clocks_init(fref);
+}
+#endif

diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
new file mode 100644 (file)
index 0000000..a854b9c
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/mx31.h>
+#include <mach/common.h>
+
+#include "clk.h"
+#include "crmregs-imx3.h"
+
+static const char *mcu_main_sel[] = { "spll", "mpll", };
+static const char *per_sel[] = { "per_div", "ipg", };
+static const char *csi_sel[] = { "upll", "spll", };
+static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
+
+enum mx31_clks {
+       ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
+       per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
+       fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
+       iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
+       uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
+       mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
+       sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
+       uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
+       gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx31_clocks_init(unsigned long fref)
+{
+       void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
+       int i;
+
+       clk[ckih] = imx_clk_fixed("ckih", fref);
+       clk[ckil] = imx_clk_fixed("ckil", 32768);
+       clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
+       clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL);
+       clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL);
+       clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
+       clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
+       clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
+       clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
+       clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
+       clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
+       clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
+       clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
+       clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
+       clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
+       clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
+       clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
+       clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
+       clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
+       clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
+       clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
+       clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
+       clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
+       clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
+       clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
+       clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
+       clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
+       clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
+       clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
+       clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
+       clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
+       clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
+       clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
+       clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
+       clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
+       clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
+       clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
+       clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
+       clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
+       clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
+       clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
+       clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
+       clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
+       clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
+       clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
+       clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
+       clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
+       clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
+       clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
+       clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
+       clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
+       clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
+       clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
+       clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
+       clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
+       clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
+       clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
+       clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("imx31 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+       clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
+       clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+       clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0");
+       clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1");
+       clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
+       clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
+       clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
+       clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
+       clk_register_clkdev(clk[epit1_gate], "epit", NULL);
+       clk_register_clkdev(clk[epit2_gate], "epit", NULL);
+       clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
+       clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
+       clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
+       clk_register_clkdev(clk[kpp_gate], "kpp", NULL);
+       clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
+       clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
+       clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1");
+       clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
+       clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2");
+       clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
+       clk_register_clkdev(clk[usb_div_post], "per", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usb_gate], "ahb", "fsl-usb2-udc");
+       clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
+       clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
+       /* i.mx31 has the i.mx21 type uart */
+       clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
+       clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
+       clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
+       clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
+       clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
+       clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
+       clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3");
+       clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3");
+       clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4");
+       clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4");
+       clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+       clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+       clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+       clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
+       clk_register_clkdev(clk[sdhc1_gate], NULL, "mxc-mmc.0");
+       clk_register_clkdev(clk[sdhc2_gate], NULL, "mxc-mmc.1");
+       clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
+       clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
+       clk_register_clkdev(clk[firi_gate], "firi", NULL);
+       clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
+       clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
+       clk_register_clkdev(clk[rng_gate], "rng", NULL);
+       clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
+       clk_register_clkdev(clk[iim_gate], "iim", NULL);
+
+       clk_set_parent(clk[csi], clk[upll]);
+       clk_prepare_enable(clk[emi_gate]);
+       clk_prepare_enable(clk[iim_gate]);
+       mx31_revision();
+       clk_disable_unprepare(clk[iim_gate]);
+
+       mxc_timer_init(NULL, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
+                       MX31_INT_GPT);
+
+       return 0;
+}

diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
new file mode 100644 (file)
index 0000000..a9e60bf
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include "crmregs-imx3.h"
+#include "clk.h"
+
+struct arm_ahb_div {
+       unsigned char arm, ahb, sel;
+};
+
+static struct arm_ahb_div clk_consumer[] = {
+       { .arm = 1, .ahb = 4, .sel = 0},
+       { .arm = 1, .ahb = 3, .sel = 1},
+       { .arm = 2, .ahb = 2, .sel = 0},
+       { .arm = 0, .ahb = 0, .sel = 0},
+       { .arm = 0, .ahb = 0, .sel = 0},
+       { .arm = 0, .ahb = 0, .sel = 0},
+       { .arm = 4, .ahb = 1, .sel = 0},
+       { .arm = 1, .ahb = 5, .sel = 0},
+       { .arm = 1, .ahb = 8, .sel = 0},
+       { .arm = 1, .ahb = 6, .sel = 1},
+       { .arm = 2, .ahb = 4, .sel = 0},
+       { .arm = 0, .ahb = 0, .sel = 0},
+       { .arm = 0, .ahb = 0, .sel = 0},
+       { .arm = 0, .ahb = 0, .sel = 0},
+       { .arm = 4, .ahb = 2, .sel = 0},
+       { .arm = 0, .ahb = 0, .sel = 0},
+};
+
+static char hsp_div_532[] = { 4, 8, 3, 0 };
+static char hsp_div_400[] = { 3, 6, 3, 0 };
+
+static const char *std_sel[] = {"ppll", "arm"};
+static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
+
+enum mx35_clks {
+       ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
+       arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
+       esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
+       spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
+       ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate,
+       audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate,
+       edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
+       esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate,
+       gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate,
+       kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
+       rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
+       ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
+       wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
+       clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx35_clocks_init()
+{
+       void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
+       u32 pdr0, consumer_sel, hsp_sel;
+       struct arm_ahb_div *aad;
+       unsigned char *hsp_div;
+       int i;
+
+       pdr0 = __raw_readl(base + MXC_CCM_PDR0);
+       consumer_sel = (pdr0 >> 16) & 0xf;
+       aad = &clk_consumer[consumer_sel];
+       if (!aad->arm) {
+               pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
+               /*
+                * We are basically stuck. Continue with a default entry and hope we
+                * get far enough to actually show the above message
+                */
+               aad = &clk_consumer[0];
+       }
+
+       clk[ckih] = imx_clk_fixed("ckih", 24000000);
+       clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL);
+       clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL);
+
+       clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
+
+       if (aad->sel)
+               clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
+       else
+               clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
+
+       if (clk_get_rate(clk[arm]) > 400000000)
+               hsp_div = hsp_div_532;
+       else
+               hsp_div = hsp_div_400;
+
+       hsp_sel = (pdr0 >> 20) & 0x3;
+       if (!hsp_div[hsp_sel]) {
+               pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
+               hsp_sel = 0;
+       }
+
+       clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
+
+       clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
+       clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
+
+       clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
+       clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
+       clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
+
+       clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
+       clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
+
+       clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
+       clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
+       clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
+       clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
+
+       clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
+       clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ 
+       clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
+
+       clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
+       clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
+       clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
+       clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
+       clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
+
+       clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
+       clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
+
+       clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
+
+       clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0,  0);
+       clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0,  2);
+       clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0,  4);
+       clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0,  6);
+       clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0,  8);
+       clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
+       clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
+       clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
+       clk[edio_gate] = imx_clk_gate2("edio_gate",   "ipg", base + MX35_CCM_CGR0, 16);
+       clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
+       clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
+       clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
+       clk[esai_gate] = imx_clk_gate2("esai_gate",   "ipg", base + MX35_CCM_CGR0, 24);
+       clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
+       clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
+       clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
+
+       clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1,  0);
+       clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1,  2);
+       clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1,  4);
+       clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1,  6);
+       clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1,  8);
+       clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
+       clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
+       clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
+       clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
+       clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
+       clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
+       clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
+       clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
+       clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
+       clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
+       clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
+
+       clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2,  0);
+       clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2,  2);
+       clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2,  4);
+       clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2,  6);
+       clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2,  8);
+       clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
+       clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
+       clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
+       clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
+       clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
+       clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
+       clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
+       clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
+       clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
+       clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
+
+       clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3,  0);
+       clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3,  2);
+       clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3,  4);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("i.MX35 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+
+       clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
+       clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
+       clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
+       clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
+       clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
+       clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1");
+       clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1");
+       clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0");
+       clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1");
+       clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0");
+       clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0");
+       clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0");
+       clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1");
+       clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1");
+       clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1");
+       clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
+       clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
+       clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
+       /* i.mx35 has the i.mx27 type fec */
+       clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
+       clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
+       clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
+       clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+       clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+       clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+       clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
+       clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
+       clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
+       clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
+       clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
+       clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
+       clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
+       clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
+       /* i.mx35 has the i.mx21 type uart */
+       clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
+       clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
+       clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
+       clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
+       clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
+       clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
+       clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
+       clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1");
+       clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
+       clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
+       clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
+       clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
+       clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
+       clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
+       clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+
+       clk_prepare_enable(clk[spba_gate]);
+       clk_prepare_enable(clk[gpio1_gate]);
+       clk_prepare_enable(clk[gpio2_gate]);
+       clk_prepare_enable(clk[gpio3_gate]);
+       clk_prepare_enable(clk[iim_gate]);
+       clk_prepare_enable(clk[emi_gate]);
+
+       imx_print_silicon_rev("i.MX35", mx35_revision());
+
+#ifdef CONFIG_MXC_USE_EPIT
+       epit_timer_init(&epit1_clk,
+                       MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
+#else
+       mxc_timer_init(NULL, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR),
+                       MX35_INT_GPT);
+#endif
+
+       return 0;
+}

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
new file mode 100644 (file)
index 0000000..b8a382d
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/err.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include "crm-regs-imx5.h"
+#include "clk.h"
+
+/* Low-power Audio Playback Mode clock */
+static const char *lp_apm_sel[] = { "osc", };
+
+/* This is used multiple times */
+static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
+static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
+static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
+static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
+static const char *per_root_sel[] = { "per_podf", "ipg", };
+static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
+static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
+static const char *emi_slow_sel[] = { "main_bus", "ahb", };
+static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
+static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
+static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
+static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
+static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
+static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
+static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
+static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
+static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
+static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
+static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
+static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
+
+enum imx5_clks {
+       dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
+       uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
+       emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
+       usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di,
+       tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
+       uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
+       gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
+       gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
+       esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
+       ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
+       ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
+       ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
+       vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
+       uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
+       esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
+       mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
+       ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
+       ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
+       periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
+       tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
+       esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
+       usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
+       pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
+       ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
+       usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
+       clk_max
+};
+
+static struct clk *clk[clk_max];
+
+static void __init mx5_clocks_common_init(unsigned long rate_ckil,
+               unsigned long rate_osc, unsigned long rate_ckih1,
+               unsigned long rate_ckih2)
+{
+       int i;
+
+       clk[dummy] = imx_clk_fixed("dummy", 0);
+       clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
+       clk[osc] = imx_clk_fixed("osc", rate_osc);
+       clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
+       clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
+
+       clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
+                               lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
+       clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
+                               periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
+       clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
+                               main_bus_sel, ARRAY_SIZE(main_bus_sel));
+       clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1,
+                               per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
+       clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
+       clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
+       clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
+       clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0,
+                               per_root_sel, ARRAY_SIZE(per_root_sel));
+       clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
+       clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
+       clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
+       clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
+       clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
+       clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
+       clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
+       clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
+       clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
+       clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
+       clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
+       clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
+                               standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+       clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
+       clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
+
+       clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
+                               standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+       clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
+                               standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+       clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
+       clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
+       clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
+       clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
+       clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
+       clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
+
+       clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
+                               emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
+       clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
+       clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
+       clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
+                               standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+       clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
+       clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
+       clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
+                               standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
+       clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
+       clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
+       clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
+       clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
+       clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
+                               usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
+       clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
+       clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
+       clk[tve_di] = imx_clk_fixed("tve_di", 65000000); /* FIXME */
+       clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, tve_sel, ARRAY_SIZE(tve_sel));
+       clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
+       clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
+       clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
+       clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
+       clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
+       clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
+       clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
+       clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
+       clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
+       clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20);
+       clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
+       clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
+       clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
+       clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
+       clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18);
+       clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
+       clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
+       clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
+       clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
+       clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
+       clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
+       clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
+       clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
+       clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
+       clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
+       clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
+       clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
+       clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
+       clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
+       clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
+       clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
+       clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
+       clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
+       clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
+       clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
+       clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
+       clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
+       clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
+       clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
+       clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
+       clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
+       clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
+       clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
+       clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
+       clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
+       clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("i.MX5 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+       
+       clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
+       clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
+       clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
+       clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
+       clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1");
+       clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
+       clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2");
+       clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
+       clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3");
+       clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
+       clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4");
+       clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
+       clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0");
+       clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
+       clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
+       clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
+       clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx51-cspi.0");
+       clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
+       clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
+       clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
+       clk_register_clkdev(clk[i2c2_gate], NULL, "imx-i2c.1");
+       clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0");
+       clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0");
+       clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0");
+       clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1");
+       clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1");
+       clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1");
+       clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2");
+       clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2");
+       clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2");
+       clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
+       clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
+       clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
+       clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
+       clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
+       clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
+       clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
+       clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
+       clk_register_clkdev(clk[iim_gate], "iim", NULL);
+       clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
+       clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
+       clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
+       clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
+       clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
+
+       /* Set SDHC parents to be PLL2 */
+       clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
+       clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]);
+
+       /* move usb phy clk to 24MHz */
+       clk_set_parent(clk[usb_phy_sel], clk[osc]);
+
+       clk_prepare_enable(clk[gpc_dvfs]);
+       clk_prepare_enable(clk[ahb_max]); /* esdhc3 */
+       clk_prepare_enable(clk[aips_tz1]);
+       clk_prepare_enable(clk[aips_tz2]); /* fec */
+       clk_prepare_enable(clk[spba]);
+       clk_prepare_enable(clk[emi_fast_gate]); /* fec */
+       clk_prepare_enable(clk[tmax1]);
+       clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
+       clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
+}
+
+int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
+                       unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+       int i;
+
+       clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
+       clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
+       clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
+       clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
+                               mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
+       clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
+                               mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
+       clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
+                               mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
+       clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
+       clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
+       clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
+       clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
+       clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
+       clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
+       clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
+       clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
+       clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
+       clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
+       clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
+       clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("i.MX51 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+       mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+
+       clk_register_clkdev(clk[hsi2c_gate], NULL, "imx-i2c.2");
+       clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
+       clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
+       clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
+       clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
+       clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
+       clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
+       clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
+       clk_register_clkdev(clk[ipu_gate], "hsp", "imx51-ipu");
+       clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
+       clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
+       clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
+       clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0");
+       clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1");
+       clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1");
+       clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1");
+       clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2");
+       clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2");
+       clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2");
+       clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
+       clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
+       clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
+
+       /* set the usboh3 parent to pll2_sw */
+       clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
+
+       /* set SDHC root clock to 166.25MHZ*/
+       clk_set_rate(clk[esdhc_a_podf], 166250000);
+       clk_set_rate(clk[esdhc_b_podf], 166250000);
+
+       /* System timer */
+       mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
+               MX51_INT_GPT);
+
+       clk_prepare_enable(clk[iim_gate]);
+       imx_print_silicon_rev("i.MX51", mx51_revision());
+       clk_disable_unprepare(clk[iim_gate]);
+
+       return 0;
+}
+
+int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
+                       unsigned long rate_ckih1, unsigned long rate_ckih2)
+{
+       int i;
+       unsigned long r;
+
+       clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
+       clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
+       clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
+       clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
+
+       clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
+                               mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
+       clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+       clk[ldb_di1_div] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1);
+       clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
+       clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
+                               mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
+       clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+       clk[ldb_di0_div] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1);
+       clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
+       clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
+       clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
+                               mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
+       clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
+                               mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
+       clk[tve_ext_sel] = imx_clk_mux("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
+                               mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
+       clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
+       clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
+       clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
+       clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
+       clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
+       clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
+       clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
+       clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
+       clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6);
+       clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
+       clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("i.MX53 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+       mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+
+       clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
+       clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
+       clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
+       clk_register_clkdev(clk[ipu_gate], "bus", "imx53-ipu");
+       clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx53-ipu");
+       clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx53-ipu");
+       clk_register_clkdev(clk[ipu_gate], "hsp", "imx53-ipu");
+       clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
+       clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
+       clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
+       clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0");
+       clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1");
+       clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1");
+       clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1");
+       clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2");
+       clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2");
+       clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2");
+       clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
+       clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
+       clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
+
+       /* set SDHC root clock to 200MHZ*/
+       clk_set_rate(clk[esdhc_a_podf], 200000000);
+       clk_set_rate(clk[esdhc_b_podf], 200000000);
+
+       /* System timer */
+       mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+               MX53_INT_GPT);
+
+       clk_prepare_enable(clk[iim_gate]);
+       imx_print_silicon_rev("i.MX53", mx53_revision());
+       clk_disable_unprepare(clk[iim_gate]);
+
+       r = clk_round_rate(clk[usboh3_per_gate], 54000000);
+       clk_set_rate(clk[usboh3_per_gate], r);
+
+       return 0;
+}
+
+#ifdef CONFIG_OF
+static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
+                                  unsigned long *ckih1, unsigned long *ckih2)
+{
+       struct device_node *np;
+
+       /* retrieve the freqency of fixed clocks from device tree */
+       for_each_compatible_node(np, NULL, "fixed-clock") {
+               u32 rate;
+               if (of_property_read_u32(np, "clock-frequency", &rate))
+                       continue;
+
+               if (of_device_is_compatible(np, "fsl,imx-ckil"))
+                       *ckil = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-osc"))
+                       *osc = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+                       *ckih1 = rate;
+               else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
+                       *ckih2 = rate;
+       }
+}
+
+int __init mx51_clocks_init_dt(void)
+{
+       unsigned long ckil, osc, ckih1, ckih2;
+
+       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+       return mx51_clocks_init(ckil, osc, ckih1, ckih2);
+}
+
+int __init mx53_clocks_init_dt(void)
+{
+       unsigned long ckil, osc, ckih1, ckih2;
+
+       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+       return mx53_clocks_init(ckil, osc, ckih1, ckih2);
+}
+#endif

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
new file mode 100644 (file)
index 0000000..f40a35d
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -0,0 +1,439 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <mach/common.h>
+#include "clk.h"
+
+#define CCGR0                          0x68
+#define CCGR1                          0x6c
+#define CCGR2                          0x70
+#define CCGR3                          0x74
+#define CCGR4                          0x78
+#define CCGR5                          0x7c
+#define CCGR6                          0x80
+#define CCGR7                          0x84
+
+#define CLPCR                          0x54
+#define BP_CLPCR_LPM                   0
+#define BM_CLPCR_LPM                   (0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY     (0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM    (0x1 << 5)
+#define BM_CLPCR_SBYOS                 (0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC           (0x1 << 7)
+#define BM_CLPCR_VSTBY                 (0x1 << 8)
+#define BP_CLPCR_STBY_COUNT            9
+#define BM_CLPCR_STBY_COUNT            (0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN          (0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM         (0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM                (0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS   (0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS   (0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI                (0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI                (0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI                (0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI                (0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE         (0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE                (0x1 << 27)
+
+static void __iomem *ccm_base;
+
+void __init imx6q_clock_map_io(void) { }
+
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+{
+       u32 val = readl_relaxed(ccm_base + CLPCR);
+
+       val &= ~BM_CLPCR_LPM;
+       switch (mode) {
+       case WAIT_CLOCKED:
+               break;
+       case WAIT_UNCLOCKED:
+               val |= 0x1 << BP_CLPCR_LPM;
+               break;
+       case STOP_POWER_ON:
+               val |= 0x2 << BP_CLPCR_LPM;
+               break;
+       case WAIT_UNCLOCKED_POWER_OFF:
+               val |= 0x1 << BP_CLPCR_LPM;
+               val &= ~BM_CLPCR_VSTBY;
+               val &= ~BM_CLPCR_SBYOS;
+               break;
+       case STOP_POWER_OFF:
+               val |= 0x2 << BP_CLPCR_LPM;
+               val |= 0x3 << BP_CLPCR_STBY_COUNT;
+               val |= BM_CLPCR_VSTBY;
+               val |= BM_CLPCR_SBYOS;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       writel_relaxed(val, ccm_base + CLPCR);
+
+       return 0;
+}
+
+static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
+static const char *pll1_sw_sels[]      = { "pll1_sys", "step", };
+static const char *periph_pre_sels[]   = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
+static const char *periph_clk2_sels[]  = { "pll3_usb_otg", "osc", };
+static const char *periph_sels[]       = { "periph_pre", "periph_clk2", };
+static const char *periph2_sels[]      = { "periph2_pre", "periph2_clk2", };
+static const char *axi_sels[]          = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *audio_sels[]        = { "pll4_audio", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
+static const char *gpu_axi_sels[]      = { "axi", "ahb", };
+static const char *gpu2d_core_sels[]   = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
+static const char *gpu3d_core_sels[]   = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
+static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
+static const char *ipu_sels[]          = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
+static const char *ldb_di_sels[]       = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *ipu_di_pre_sels[]   = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+static const char *ipu1_di0_sels[]     = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *ipu1_di1_sels[]     = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *ipu2_di0_sels[]     = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *ipu2_di1_sels[]     = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *hsi_tx_sels[]       = { "pll3_120m", "pll2_pfd2_396m", };
+static const char *pcie_axi_sels[]     = { "axi", "ahb", };
+static const char *ssi_sels[]          = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio", };
+static const char *usdhc_sels[]        = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
+static const char *emi_sels[]          = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *vdo_axi_sels[]      = { "axi", "ahb", };
+static const char *vpu_axi_sels[]      = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video",
+                                   "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
+                                   "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
+
+static const char * const clks_init_on[] __initconst = {
+       "mmdc_ch0_axi", "mmdc_ch1_axi", "usboh3",
+};
+
+enum mx6q_clks {
+       dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
+       pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
+       pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
+       periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
+       esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
+       gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
+       ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
+       ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
+       ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
+       usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
+       emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
+       periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
+       asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
+       gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
+       ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
+       ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
+       ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
+       usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
+       emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
+       mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
+       can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
+       esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
+       hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
+       ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
+       mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,
+       gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
+       ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
+       usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
+       pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, clk_max
+};
+
+static struct clk *clk[clk_max];
+
+int __init mx6q_clocks_init(void)
+{
+       struct device_node *np;
+       void __iomem *base;
+       struct clk *c;
+       int i, irq;
+
+       clk[dummy] = imx_clk_fixed("dummy", 0);
+
+       /* retrieve the freqency of fixed clocks from device tree */
+       for_each_compatible_node(np, NULL, "fixed-clock") {
+               u32 rate;
+               if (of_property_read_u32(np, "clock-frequency", &rate))
+                       continue;
+
+               if (of_device_is_compatible(np, "fsl,imx-ckil"))
+                       clk[ckil] = imx_clk_fixed("ckil", rate);
+               else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+                       clk[ckih] = imx_clk_fixed("ckih", rate);
+               else if (of_device_is_compatible(np, "fsl,imx-osc"))
+                       clk[osc] = imx_clk_fixed("osc", rate);
+       }
+
+       np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
+       base = of_iomap(np, 0);
+       WARN_ON(!base);
+
+       /*                   type                               name         parent_name  base     gate_mask div_mask */
+       clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,       "pll1_sys",     "osc", base,        0x2000,   0x7f);
+       clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,   "pll2_bus",     "osc", base + 0x30, 0x2000,   0x1);
+       clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,       "pll3_usb_otg", "osc", base + 0x10, 0x2000,   0x3);
+       clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll4_audio",   "osc", base + 0x70, 0x2000,   0x7f);
+       clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x2000,   0x7f);
+       clk[pll6_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll6_mlb",     "osc", base + 0xd0, 0x2000,   0x0);
+       clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x2000,   0x3);
+       clk[pll8_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll8_enet",    "osc", base + 0xe0, 0x182000, 0x3);
+
+       /*                                name              parent_name        reg       idx */
+       clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
+       clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
+       clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
+       clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
+       clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
+       clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
+       clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
+
+       /*                                    name         parent_name     mult div */
+       clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
+       clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
+       clk[pll3_80m]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
+       clk[pll3_60m]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
+       clk[twd]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
+
+       np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
+       base = of_iomap(np, 0);
+       WARN_ON(!base);
+       ccm_base = base;
+
+       /*                                  name                reg       shift width parent_names     num_parents */
+       clk[step]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
+       clk[pll1_sw]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+       clk[periph_pre]       = imx_clk_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+       clk[periph2_pre]      = imx_clk_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+       clk[periph_clk2_sel]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+       clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+       clk[axi_sel]          = imx_clk_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
+       clk[esai_sel]         = imx_clk_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+       clk[asrc_sel]         = imx_clk_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
+       clk[spdif_sel]        = imx_clk_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+       clk[gpu2d_axi]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+       clk[gpu3d_axi]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+       clk[gpu2d_core_sel]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
+       clk[gpu3d_core_sel]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
+       clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
+       clk[ipu1_sel]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+       clk[ipu2_sel]         = imx_clk_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
+       clk[ldb_di0_sel]      = imx_clk_mux("ldb_di0_sel",      base + 0x2c, 9,  3, ldb_di_sels,       ARRAY_SIZE(ldb_di_sels));
+       clk[ldb_di1_sel]      = imx_clk_mux("ldb_di1_sel",      base + 0x2c, 12, 3, ldb_di_sels,       ARRAY_SIZE(ldb_di_sels));
+       clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+       clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+       clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+       clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels));
+       clk[ipu1_di0_sel]     = imx_clk_mux("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels));
+       clk[ipu1_di1_sel]     = imx_clk_mux("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels));
+       clk[ipu2_di0_sel]     = imx_clk_mux("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels));
+       clk[ipu2_di1_sel]     = imx_clk_mux("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels));
+       clk[hsi_tx_sel]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
+       clk[pcie_axi_sel]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
+       clk[ssi1_sel]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+       clk[ssi2_sel]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+       clk[ssi3_sel]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+       clk[usdhc1_sel]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+       clk[usdhc2_sel]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+       clk[usdhc3_sel]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+       clk[usdhc4_sel]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+       clk[enfc_sel]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
+       clk[emi_sel]          = imx_clk_mux("emi_sel",          base + 0x1c, 27, 2, emi_sels,          ARRAY_SIZE(emi_sels));
+       clk[emi_slow_sel]     = imx_clk_mux("emi_slow_sel",     base + 0x1c, 29, 2, emi_sels,          ARRAY_SIZE(emi_sels));
+       clk[vdo_axi_sel]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
+       clk[vpu_axi_sel]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
+       clk[cko1_sel]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
+
+       /*                              name         reg      shift width busy: reg, shift parent_names  num_parents */
+       clk[periph]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
+       clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
+
+       /*                                      name                parent_name          reg       shift width */
+       clk[periph_clk2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
+       clk[periph2_clk2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
+       clk[ipg]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
+       clk[ipg_per]          = imx_clk_divider("ipg_per",          "ipg",               base + 0x1c, 0,  6);
+       clk[esai_pred]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
+       clk[esai_podf]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
+       clk[asrc_pred]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
+       clk[asrc_podf]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
+       clk[spdif_pred]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
+       clk[spdif_podf]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
+       clk[can_root]         = imx_clk_divider("can_root",         "pll3_usb_otg",      base + 0x20, 2,  6);
+       clk[ecspi_root]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
+       clk[gpu2d_core_podf]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
+       clk[gpu3d_core_podf]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
+       clk[gpu3d_shader]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
+       clk[ipu1_podf]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
+       clk[ipu2_podf]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
+       clk[ldb_di0_podf]     = imx_clk_divider("ldb_di0_podf",     "ldb_di0_sel",       base + 0x20, 10, 1);
+       clk[ldb_di1_podf]     = imx_clk_divider("ldb_di1_podf",     "ldb_di1_sel",       base + 0x20, 11, 1);
+       clk[ipu1_di0_pre]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
+       clk[ipu1_di1_pre]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
+       clk[ipu2_di0_pre]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
+       clk[ipu2_di1_pre]     = imx_clk_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
+       clk[hsi_tx_podf]      = imx_clk_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
+       clk[ssi1_pred]        = imx_clk_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
+       clk[ssi1_podf]        = imx_clk_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
+       clk[ssi2_pred]        = imx_clk_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
+       clk[ssi2_podf]        = imx_clk_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
+       clk[ssi3_pred]        = imx_clk_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
+       clk[ssi3_podf]        = imx_clk_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
+       clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
+       clk[usdhc1_podf]      = imx_clk_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
+       clk[usdhc2_podf]      = imx_clk_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
+       clk[usdhc3_podf]      = imx_clk_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
+       clk[usdhc4_podf]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
+       clk[enfc_pred]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
+       clk[enfc_podf]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
+       clk[emi_podf]         = imx_clk_divider("emi_podf",         "emi_sel",           base + 0x1c, 20, 3);
+       clk[emi_slow_podf]    = imx_clk_divider("emi_slow_podf",    "emi_slow_sel",      base + 0x1c, 23, 3);
+       clk[vpu_axi_podf]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
+       clk[cko1_podf]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
+
+       /*                                            name                 parent_name    reg        shift width busy: reg, shift */
+       clk[axi]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
+       clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
+       clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
+       clk[arm]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
+       clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
+
+       /*                                name             parent_name          reg         shift */
+       clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "ahb",               base + 0x68, 4);
+       clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
+       clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
+       clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
+       clk[can2_ipg]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
+       clk[can2_serial]  = imx_clk_gate2("can2_serial",   "can_root",          base + 0x68, 20);
+       clk[ecspi1]       = imx_clk_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
+       clk[ecspi2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
+       clk[ecspi3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
+       clk[ecspi4]       = imx_clk_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
+       clk[ecspi5]       = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
+       clk[enet]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
+       clk[esai]         = imx_clk_gate2("esai",          "esai_podf",         base + 0x6c, 16);
+       clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
+       clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
+       clk[gpu2d_core]   = imx_clk_gate2("gpu2d_core",    "gpu2d_core_podf",   base + 0x6c, 24);
+       clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
+       clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
+       clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
+       clk[i2c1]         = imx_clk_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
+       clk[i2c2]         = imx_clk_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
+       clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
+       clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
+       clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
+       clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
+       clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
+       clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
+       clk[ipu2]         = imx_clk_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
+       clk[ipu2_di0]     = imx_clk_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
+       clk[ldb_di0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
+       clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
+       clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
+       clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
+       clk[mlb]          = imx_clk_gate2("mlb",           "pll6_mlb",          base + 0x74, 18);
+       clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
+       clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
+       clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
+       clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
+       clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
+       clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
+       clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
+       clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
+       clk[pwm4]         = imx_clk_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
+       clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
+       clk[gpmi_bch]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
+       clk[gpmi_io]      = imx_clk_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
+       clk[gpmi_apb]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
+       clk[sata]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
+       clk[sdma]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
+       clk[spba]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
+       clk[ssi1]         = imx_clk_gate2("ssi1",          "ssi1_podf",         base + 0x7c, 18);
+       clk[ssi2]         = imx_clk_gate2("ssi2",          "ssi2_podf",         base + 0x7c, 20);
+       clk[ssi3]         = imx_clk_gate2("ssi3",          "ssi3_podf",         base + 0x7c, 22);
+       clk[uart_ipg]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
+       clk[uart_serial]  = imx_clk_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
+       clk[usboh3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
+       clk[usdhc1]       = imx_clk_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
+       clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
+       clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
+       clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+       clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
+       clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
+       clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
+
+       for (i = 0; i < ARRAY_SIZE(clk); i++)
+               if (IS_ERR(clk[i]))
+                       pr_err("i.MX6q clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clk[i]));
+
+       clk_register_clkdev(clk[mmdc_ch0_axi], NULL, "mmdc_ch0_axi");
+       clk_register_clkdev(clk[mmdc_ch1_axi], NULL, "mmdc_ch1_axi");
+       clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
+       clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+       clk_register_clkdev(clk[twd], NULL, "smp_twd");
+       clk_register_clkdev(clk[usboh3], NULL, "usboh3");
+       clk_register_clkdev(clk[uart_serial], "per", "2020000.uart");
+       clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.uart");
+       clk_register_clkdev(clk[uart_serial], "per", "21e8000.uart");
+       clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.uart");
+       clk_register_clkdev(clk[uart_serial], "per", "21ec000.uart");
+       clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.uart");
+       clk_register_clkdev(clk[uart_serial], "per", "21f0000.uart");
+       clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.uart");
+       clk_register_clkdev(clk[uart_serial], "per", "21f4000.uart");
+       clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.uart");
+       clk_register_clkdev(clk[enet], NULL, "2188000.enet");
+       clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
+       clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
+       clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
+       clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
+       clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
+       clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
+       clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
+       clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
+       clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
+       clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
+       clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
+       clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
+       clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
+       clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
+       clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
+
+       for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) {
+               c = clk_get_sys(clks_init_on[i], NULL);
+               if (IS_ERR(c)) {
+                       pr_err("%s: failed to get clk %s", __func__,
+                              clks_init_on[i]);
+                       return PTR_ERR(c);
+               }
+               clk_prepare_enable(c);
+       }
+
+       np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
+       base = of_iomap(np, 0);
+       WARN_ON(!base);
+       irq = irq_of_parse_and_map(np, 0);
+       mxc_timer_init(NULL, base, irq);
+
+       return 0;
+}

diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
new file mode 100644 (file)
index 0000000..e2ed416
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pfd.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include "clk.h"
+
+/**
+ * struct clk_pfd - IMX PFD clock
+ * @clk_hw:    clock source
+ * @reg:       PFD register address
+ * @idx:       the index of PFD encoded in the register
+ *
+ * PFD clock found on i.MX6 series.  Each register for PFD has 4 clk_pfd
+ * data encoded, and member idx is used to specify the one.  And each
+ * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
+ */
+struct clk_pfd {
+       struct clk_hw   hw;
+       void __iomem    *reg;
+       u8              idx;
+};
+
+#define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw)
+
+#define SET    0x4
+#define CLR    0x8
+#define OTG    0xc
+
+static int clk_pfd_enable(struct clk_hw *hw)
+{
+       struct clk_pfd *pfd = to_clk_pfd(hw);
+
+       writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
+
+       return 0;
+}
+
+static void clk_pfd_disable(struct clk_hw *hw)
+{
+       struct clk_pfd *pfd = to_clk_pfd(hw);
+
+       writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
+}
+
+static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
+                                        unsigned long parent_rate)
+{
+       struct clk_pfd *pfd = to_clk_pfd(hw);
+       u64 tmp = parent_rate;
+       u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
+
+       tmp *= 18;
+       do_div(tmp, frac);
+
+       return tmp;
+}
+
+static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long *prate)
+{
+       u64 tmp = *prate;
+       u8 frac;
+
+       tmp = tmp * 18 + rate / 2;
+       do_div(tmp, rate);
+       frac = tmp;
+       if (frac < 12)
+               frac = 12;
+       else if (frac > 35)
+               frac = 35;
+       tmp = *prate;
+       tmp *= 18;
+       do_div(tmp, frac);
+
+       return tmp;
+}
+
+static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       struct clk_pfd *pfd = to_clk_pfd(hw);
+       u64 tmp = parent_rate;
+       u8 frac;
+
+       tmp = tmp * 18 + rate / 2;
+       do_div(tmp, rate);
+       frac = tmp;
+       if (frac < 12)
+               frac = 12;
+       else if (frac > 35)
+               frac = 35;
+
+       writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR);
+       writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET);
+
+       return 0;
+}
+
+static const struct clk_ops clk_pfd_ops = {
+       .enable         = clk_pfd_enable,
+       .disable        = clk_pfd_disable,
+       .recalc_rate    = clk_pfd_recalc_rate,
+       .round_rate     = clk_pfd_round_rate,
+       .set_rate       = clk_pfd_set_rate,
+};
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+                       void __iomem *reg, u8 idx)
+{
+       struct clk_pfd *pfd;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
+       if (!pfd)
+               return ERR_PTR(-ENOMEM);
+
+       pfd->reg = reg;
+       pfd->idx = idx;
+
+       init.name = name;
+       init.ops = &clk_pfd_ops;
+       init.flags = 0;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       pfd->hw.init = &init;
+
+       clk = clk_register(NULL, &pfd->hw);
+       if (IS_ERR(clk))
+               kfree(pfd);
+
+       return clk;
+}

diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
new file mode 100644 (file)
index 0000000..2d856f9
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -0,0 +1,66 @@
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+#include "clk.h"
+
+/**
+ * pll v1
+ *
+ * @clk_hw     clock source
+ * @parent     the parent clock name
+ * @base       base address of pll registers
+ *
+ * PLL clock version 1, found on i.MX1/21/25/27/31/35
+ */
+struct clk_pllv1 {
+       struct clk_hw   hw;
+       void __iomem    *base;
+};
+
+#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
+
+static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       struct clk_pllv1 *pll = to_clk_pllv1(hw);
+
+       return mxc_decode_pll(readl(pll->base), parent_rate);
+}
+
+struct clk_ops clk_pllv1_ops = {
+       .recalc_rate = clk_pllv1_recalc_rate,
+};
+
+struct clk *imx_clk_pllv1(const char *name, const char *parent,
+               void __iomem *base)
+{
+       struct clk_pllv1 *pll;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll)
+               return ERR_PTR(-ENOMEM);
+
+       pll->base = base;
+
+       init.name = name;
+       init.ops = &clk_pllv1_ops;
+       init.flags = 0;
+       init.parent_names = &parent;
+       init.num_parents = 1;
+
+       pll->hw.init = &init;
+
+       clk = clk_register(NULL, &pll->hw);
+       if (IS_ERR(clk))
+               kfree(pll);
+
+       return clk;
+}

diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
new file mode 100644 (file)
index 0000000..4685919
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -0,0 +1,249 @@
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <asm/div64.h>
+
+#include "clk.h"
+
+#define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk))
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL                 0x00
+#define MXC_PLL_DP_CONFIG              0x04
+#define MXC_PLL_DP_OP                  0x08
+#define MXC_PLL_DP_MFD                 0x0C
+#define MXC_PLL_DP_MFN                 0x10
+#define MXC_PLL_DP_MFNMINUS            0x14
+#define MXC_PLL_DP_MFNPLUS             0x18
+#define MXC_PLL_DP_HFS_OP              0x1C
+#define MXC_PLL_DP_HFS_MFD             0x20
+#define MXC_PLL_DP_HFS_MFN             0x24
+#define MXC_PLL_DP_MFN_TOGC            0x28
+#define MXC_PLL_DP_DESTAT              0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL                0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN     0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MXC_PLL_DP_CTL_ADE             0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV     0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK        (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET      8
+#define MXC_PLL_DP_CTL_HFSM            0x80
+#define MXC_PLL_DP_CTL_PRE             0x40
+#define MXC_PLL_DP_CTL_UPEN            0x20
+#define MXC_PLL_DP_CTL_RST             0x10
+#define MXC_PLL_DP_CTL_RCP             0x8
+#define MXC_PLL_DP_CTL_PLM             0x4
+#define MXC_PLL_DP_CTL_BRM0            0x2
+#define MXC_PLL_DP_CTL_LRF             0x1
+
+#define MXC_PLL_DP_CONFIG_BIST         0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE       0x4
+#define MXC_PLL_DP_CONFIG_AREN         0x2
+#define MXC_PLL_DP_CONFIG_LDREQ                0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET       4
+#define MXC_PLL_DP_OP_MFI_MASK         (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET       0
+#define MXC_PLL_DP_OP_PDF_MASK         0xF
+
+#define MXC_PLL_DP_MFD_OFFSET          0
+#define MXC_PLL_DP_MFD_MASK            0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET          0x0
+#define MXC_PLL_DP_MFN_MASK            0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS    (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN     (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK   0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL      (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN          0x07FFFFFF
+
+#define MAX_DPLL_WAIT_TRIES    1000 /* 1000 * udelay(1) = 1ms */
+
+struct clk_pllv2 {
+       struct clk_hw   hw;
+       void __iomem    *base;
+};
+
+static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+       unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+       void __iomem *pllbase;
+       s64 temp;
+       struct clk_pllv2 *pll = to_clk_pllv2(hw);
+
+       pllbase = pll->base;
+
+       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+       dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
+
+       if (pll_hfsm == 0) {
+               dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+       } else {
+               dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+       }
+       pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+       mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
+       mfi = (mfi <= 5) ? 5 : mfi;
+       mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+       mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
+       /* Sign extend to 32-bits */
+       if (mfn >= 0x04000000) {
+               mfn |= 0xFC000000;
+               mfn_abs = -mfn;
+       }
+
+       ref_clk = 2 * parent_rate;
+       if (dbl != 0)
+               ref_clk *= 2;
+
+       ref_clk /= (pdf + 1);
+       temp = (u64) ref_clk * mfn_abs;
+       do_div(temp, mfd + 1);
+       if (mfn < 0)
+               temp = -temp;
+       temp = (ref_clk * mfi) + temp;
+
+       return temp;
+}
+
+static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       struct clk_pllv2 *pll = to_clk_pllv2(hw);
+       u32 reg;
+       void __iomem *pllbase;
+       long mfi, pdf, mfn, mfd = 999999;
+       s64 temp64;
+       unsigned long quad_parent_rate;
+       unsigned long pll_hfsm, dp_ctl;
+
+       pllbase = pll->base;
+
+       quad_parent_rate = 4 * parent_rate;
+       pdf = mfi = -1;
+       while (++pdf < 16 && mfi < 5)
+               mfi = rate * (pdf+1) / quad_parent_rate;
+       if (mfi > 15)
+               return -EINVAL;
+       pdf--;
+
+       temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
+       do_div(temp64, quad_parent_rate/1000000);
+       mfn = (long)temp64;
+
+       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+       /* use dpdck0_2 */
+       __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
+       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
+       if (pll_hfsm == 0) {
+               reg = mfi << 4 | pdf;
+               __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
+               __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
+               __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
+       } else {
+               reg = mfi << 4 | pdf;
+               __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
+               __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
+               __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
+       }
+
+       return 0;
+}
+
+static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long *prate)
+{
+       return rate;
+}
+
+static int clk_pllv2_prepare(struct clk_hw *hw)
+{
+       struct clk_pllv2 *pll = to_clk_pllv2(hw);
+       u32 reg;
+       void __iomem *pllbase;
+       int i = 0;
+
+       pllbase = pll->base;
+       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
+       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+
+       /* Wait for lock */
+       do {
+               reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
+               if (reg & MXC_PLL_DP_CTL_LRF)
+                       break;
+
+               udelay(1);
+       } while (++i < MAX_DPLL_WAIT_TRIES);
+
+       if (i == MAX_DPLL_WAIT_TRIES) {
+               pr_err("MX5: pll locking failed\n");
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static void clk_pllv2_unprepare(struct clk_hw *hw)
+{
+       struct clk_pllv2 *pll = to_clk_pllv2(hw);
+       u32 reg;
+       void __iomem *pllbase;
+
+       pllbase = pll->base;
+       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
+       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
+}
+
+struct clk_ops clk_pllv2_ops = {
+       .prepare = clk_pllv2_prepare,
+       .unprepare = clk_pllv2_unprepare,
+       .recalc_rate = clk_pllv2_recalc_rate,
+       .round_rate = clk_pllv2_round_rate,
+       .set_rate = clk_pllv2_set_rate,
+};
+
+struct clk *imx_clk_pllv2(const char *name, const char *parent,
+               void __iomem *base)
+{
+       struct clk_pllv2 *pll;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll)
+               return ERR_PTR(-ENOMEM);
+
+       pll->base = base;
+
+       init.name = name;
+       init.ops = &clk_pllv2_ops;
+       init.flags = 0;
+       init.parent_names = &parent;
+       init.num_parents = 1;
+
+       pll->hw.init = &init;
+
+       clk = clk_register(NULL, &pll->hw);
+       if (IS_ERR(clk))
+               kfree(pll);
+
+       return clk;
+}

diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
new file mode 100644 (file)
index 0000000..36aac94
--- /dev/null
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define PLL_NUM_OFFSET         0x10
+#define PLL_DENOM_OFFSET       0x20
+
+#define BM_PLL_POWER           (0x1 << 12)
+#define BM_PLL_ENABLE          (0x1 << 13)
+#define BM_PLL_BYPASS          (0x1 << 16)
+#define BM_PLL_LOCK            (0x1 << 31)
+
+/**
+ * struct clk_pllv3 - IMX PLL clock version 3
+ * @clk_hw:     clock source
+ * @base:       base address of PLL registers
+ * @powerup_set: set POWER bit to power up the PLL
+ * @gate_mask:  mask of gate bits
+ * @div_mask:   mask of divider bits
+ *
+ * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
+ * is actually a multiplier, and always sits at bit 0.
+ */
+struct clk_pllv3 {
+       struct clk_hw   hw;
+       void __iomem    *base;
+       bool            powerup_set;
+       u32             gate_mask;
+       u32             div_mask;
+};
+
+#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
+
+static int clk_pllv3_prepare(struct clk_hw *hw)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       unsigned long timeout = jiffies + msecs_to_jiffies(10);
+       u32 val;
+
+       val = readl_relaxed(pll->base);
+       val &= ~BM_PLL_BYPASS;
+       if (pll->powerup_set)
+               val |= BM_PLL_POWER;
+       else
+               val &= ~BM_PLL_POWER;
+       writel_relaxed(val, pll->base);
+
+       /* Wait for PLL to lock */
+       while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
+               if (time_after(jiffies, timeout))
+                       return -ETIMEDOUT;
+
+       return 0;
+}
+
+static void clk_pllv3_unprepare(struct clk_hw *hw)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 val;
+
+       val = readl_relaxed(pll->base);
+       val |= BM_PLL_BYPASS;
+       if (pll->powerup_set)
+               val &= ~BM_PLL_POWER;
+       else
+               val |= BM_PLL_POWER;
+       writel_relaxed(val, pll->base);
+}
+
+static int clk_pllv3_enable(struct clk_hw *hw)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 val;
+
+       val = readl_relaxed(pll->base);
+       val |= pll->gate_mask;
+       writel_relaxed(val, pll->base);
+
+       return 0;
+}
+
+static void clk_pllv3_disable(struct clk_hw *hw)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 val;
+
+       val = readl_relaxed(pll->base);
+       val &= ~pll->gate_mask;
+       writel_relaxed(val, pll->base);
+}
+
+static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
+                                          unsigned long parent_rate)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 div = readl_relaxed(pll->base)  & pll->div_mask;
+
+       return (div == 1) ? parent_rate * 22 : parent_rate * 20;
+}
+
+static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+       unsigned long parent_rate = *prate;
+
+       return (rate >= parent_rate * 22) ? parent_rate * 22 :
+                                           parent_rate * 20;
+}
+
+static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 val, div;
+
+       if (rate == parent_rate * 22)
+               div = 1;
+       else if (rate == parent_rate * 20)
+               div = 0;
+       else
+               return -EINVAL;
+
+       val = readl_relaxed(pll->base);
+       val &= ~pll->div_mask;
+       val |= div;
+       writel_relaxed(val, pll->base);
+
+       return 0;
+}
+
+static const struct clk_ops clk_pllv3_ops = {
+       .prepare        = clk_pllv3_prepare,
+       .unprepare      = clk_pllv3_unprepare,
+       .enable         = clk_pllv3_enable,
+       .disable        = clk_pllv3_disable,
+       .recalc_rate    = clk_pllv3_recalc_rate,
+       .round_rate     = clk_pllv3_round_rate,
+       .set_rate       = clk_pllv3_set_rate,
+};
+
+static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
+                                              unsigned long parent_rate)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 div = readl_relaxed(pll->base) & pll->div_mask;
+
+       return parent_rate * div / 2;
+}
+
+static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
+                                    unsigned long *prate)
+{
+       unsigned long parent_rate = *prate;
+       unsigned long min_rate = parent_rate * 54 / 2;
+       unsigned long max_rate = parent_rate * 108 / 2;
+       u32 div;
+
+       if (rate > max_rate)
+               rate = max_rate;
+       else if (rate < min_rate)
+               rate = min_rate;
+       div = rate * 2 / parent_rate;
+
+       return parent_rate * div / 2;
+}
+
+static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       unsigned long min_rate = parent_rate * 54 / 2;
+       unsigned long max_rate = parent_rate * 108 / 2;
+       u32 val, div;
+
+       if (rate < min_rate || rate > max_rate)
+               return -EINVAL;
+
+       div = rate * 2 / parent_rate;
+       val = readl_relaxed(pll->base);
+       val &= ~pll->div_mask;
+       val |= div;
+       writel_relaxed(val, pll->base);
+
+       return 0;
+}
+
+static const struct clk_ops clk_pllv3_sys_ops = {
+       .prepare        = clk_pllv3_prepare,
+       .unprepare      = clk_pllv3_unprepare,
+       .enable         = clk_pllv3_enable,
+       .disable        = clk_pllv3_disable,
+       .recalc_rate    = clk_pllv3_sys_recalc_rate,
+       .round_rate     = clk_pllv3_sys_round_rate,
+       .set_rate       = clk_pllv3_sys_set_rate,
+};
+
+static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
+                                             unsigned long parent_rate)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
+       u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
+       u32 div = readl_relaxed(pll->base) & pll->div_mask;
+
+       return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+}
+
+static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
+                                   unsigned long *prate)
+{
+       unsigned long parent_rate = *prate;
+       unsigned long min_rate = parent_rate * 27;
+       unsigned long max_rate = parent_rate * 54;
+       u32 div;
+       u32 mfn, mfd = 1000000;
+       s64 temp64;
+
+       if (rate > max_rate)
+               rate = max_rate;
+       else if (rate < min_rate)
+               rate = min_rate;
+
+       div = rate / parent_rate;
+       temp64 = (u64) (rate - div * parent_rate);
+       temp64 *= mfd;
+       do_div(temp64, parent_rate);
+       mfn = temp64;
+
+       return parent_rate * div + parent_rate / mfd * mfn;
+}
+
+static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       unsigned long min_rate = parent_rate * 27;
+       unsigned long max_rate = parent_rate * 54;
+       u32 val, div;
+       u32 mfn, mfd = 1000000;
+       s64 temp64;
+
+       if (rate < min_rate || rate > max_rate)
+               return -EINVAL;
+
+       div = rate / parent_rate;
+       temp64 = (u64) (rate - div * parent_rate);
+       temp64 *= mfd;
+       do_div(temp64, parent_rate);
+       mfn = temp64;
+
+       val = readl_relaxed(pll->base);
+       val &= ~pll->div_mask;
+       val |= div;
+       writel_relaxed(val, pll->base);
+       writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
+       writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
+
+       return 0;
+}
+
+static const struct clk_ops clk_pllv3_av_ops = {
+       .prepare        = clk_pllv3_prepare,
+       .unprepare      = clk_pllv3_unprepare,
+       .enable         = clk_pllv3_enable,
+       .disable        = clk_pllv3_disable,
+       .recalc_rate    = clk_pllv3_av_recalc_rate,
+       .round_rate     = clk_pllv3_av_round_rate,
+       .set_rate       = clk_pllv3_av_set_rate,
+};
+
+static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
+                                               unsigned long parent_rate)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 div = readl_relaxed(pll->base) & pll->div_mask;
+
+       switch (div) {
+       case 0:
+               return 25000000;
+       case 1:
+               return 50000000;
+       case 2:
+               return 100000000;
+       case 3:
+               return 125000000;
+       }
+
+       return 0;
+}
+
+static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
+                                     unsigned long *prate)
+{
+       if (rate >= 125000000)
+               rate = 125000000;
+       else if (rate >= 100000000)
+               rate = 100000000;
+       else if (rate >= 50000000)
+               rate = 50000000;
+       else
+               rate = 25000000;
+       return rate;
+}
+
+static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
+               unsigned long parent_rate)
+{
+       struct clk_pllv3 *pll = to_clk_pllv3(hw);
+       u32 val, div;
+
+       switch (rate) {
+       case 25000000:
+               div = 0;
+               break;
+       case 50000000:
+               div = 1;
+               break;
+       case 100000000:
+               div = 2;
+               break;
+       case 125000000:
+               div = 3;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       val = readl_relaxed(pll->base);
+       val &= ~pll->div_mask;
+       val |= div;
+       writel_relaxed(val, pll->base);
+
+       return 0;
+}
+
+static const struct clk_ops clk_pllv3_enet_ops = {
+       .prepare        = clk_pllv3_prepare,
+       .unprepare      = clk_pllv3_unprepare,
+       .enable         = clk_pllv3_enable,
+       .disable        = clk_pllv3_disable,
+       .recalc_rate    = clk_pllv3_enet_recalc_rate,
+       .round_rate     = clk_pllv3_enet_round_rate,
+       .set_rate       = clk_pllv3_enet_set_rate,
+};
+
+static const struct clk_ops clk_pllv3_mlb_ops = {
+       .prepare        = clk_pllv3_prepare,
+       .unprepare      = clk_pllv3_unprepare,
+       .enable         = clk_pllv3_enable,
+       .disable        = clk_pllv3_disable,
+};
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+                         const char *parent_name, void __iomem *base,
+                         u32 gate_mask, u32 div_mask)
+{
+       struct clk_pllv3 *pll;
+       const struct clk_ops *ops;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll)
+               return ERR_PTR(-ENOMEM);
+
+       switch (type) {
+       case IMX_PLLV3_SYS:
+               ops = &clk_pllv3_sys_ops;
+               break;
+       case IMX_PLLV3_USB:
+               ops = &clk_pllv3_ops;
+               pll->powerup_set = true;
+               break;
+       case IMX_PLLV3_AV:
+               ops = &clk_pllv3_av_ops;
+               break;
+       case IMX_PLLV3_ENET:
+               ops = &clk_pllv3_enet_ops;
+               break;
+       case IMX_PLLV3_MLB:
+               ops = &clk_pllv3_mlb_ops;
+               break;
+       default:
+               ops = &clk_pllv3_ops;
+       }
+       pll->base = base;
+       pll->gate_mask = gate_mask;
+       pll->div_mask = div_mask;
+
+       init.name = name;
+       init.ops = ops;
+       init.flags = 0;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       pll->hw.init = &init;
+
+       clk = clk_register(NULL, &pll->hw);
+       if (IS_ERR(clk))
+               kfree(pll);
+
+       return clk;
+}

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
new file mode 100644 (file)
index 0000000..1bf64fe
--- /dev/null
+++ b/arch/arm/mach-imx/clk.h
@@ -0,0 +1,83 @@
+#ifndef __MACH_IMX_CLK_H
+#define __MACH_IMX_CLK_H
+
+#include <linux/spinlock.h>
+#include <linux/clk-provider.h>
+#include <mach/clock.h>
+
+struct clk *imx_clk_pllv1(const char *name, const char *parent,
+               void __iomem *base);
+
+struct clk *imx_clk_pllv2(const char *name, const char *parent,
+               void __iomem *base);
+
+enum imx_pllv3_type {
+       IMX_PLLV3_GENERIC,
+       IMX_PLLV3_SYS,
+       IMX_PLLV3_USB,
+       IMX_PLLV3_AV,
+       IMX_PLLV3_ENET,
+       IMX_PLLV3_MLB,
+};
+
+struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+               const char *parent_name, void __iomem *base, u32 gate_mask,
+               u32 div_mask);
+
+struct clk *clk_register_gate2(struct device *dev, const char *name,
+               const char *parent_name, unsigned long flags,
+               void __iomem *reg, u8 bit_idx,
+               u8 clk_gate_flags, spinlock_t *lock);
+
+static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
+               void __iomem *reg, u8 shift)
+{
+       return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+                       shift, 0, &imx_ccm_lock);
+}
+
+struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+               void __iomem *reg, u8 idx);
+
+struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
+                                void __iomem *reg, u8 shift, u8 width,
+                                void __iomem *busy_reg, u8 busy_shift);
+
+struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
+                            u8 width, void __iomem *busy_reg, u8 busy_shift,
+                            const char **parent_names, int num_parents);
+
+static inline struct clk *imx_clk_fixed(const char *name, int rate)
+{
+       return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *imx_clk_divider(const char *name, const char *parent,
+               void __iomem *reg, u8 shift, u8 width)
+{
+       return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+                       reg, shift, width, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+               void __iomem *reg, u8 shift)
+{
+       return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+                       shift, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
+               u8 shift, u8 width, const char **parents, int num_parents)
+{
+       return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
+                       width, 0, &imx_ccm_lock);
+}
+
+static inline struct clk *imx_clk_fixed_factor(const char *name,
+               const char *parent, unsigned int mult, unsigned int div)
+{
+       return clk_register_fixed_factor(NULL, name, parent,
+                       CLK_SET_RATE_PARENT, mult, div);
+}
+
+#endif

diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
deleted file mode 100644 (file)
index 4aabeb2..0000000
--- a/arch/arm/mach-imx/clock-imx1.c
+++ /dev/null
@@ -1,636 +0,0 @@
-/*
- *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/math64.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#define IO_ADDR_CCM(off)       (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
-
-/* CCM register addresses */
-#define CCM_CSCR       IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0     IO_ADDR_CCM(0x4)
-#define CCM_SPCTL0     IO_ADDR_CCM(0xc)
-#define CCM_PCDR       IO_ADDR_CCM(0x20)
-
-#define CCM_CSCR_CLKO_OFFSET   29
-#define CCM_CSCR_CLKO_MASK     (0x7 << 29)
-#define CCM_CSCR_USB_OFFSET    26
-#define CCM_CSCR_USB_MASK      (0x7 << 26)
-#define CCM_CSCR_OSC_EN_SHIFT  17
-#define CCM_CSCR_SYSTEM_SEL    (1 << 16)
-#define CCM_CSCR_BCLK_OFFSET   10
-#define CCM_CSCR_BCLK_MASK     (0xf << 10)
-#define CCM_CSCR_PRESC         (1 << 15)
-
-#define CCM_PCDR_PCLK3_OFFSET  16
-#define CCM_PCDR_PCLK3_MASK    (0x7f << 16)
-#define CCM_PCDR_PCLK2_OFFSET  4
-#define CCM_PCDR_PCLK2_MASK    (0xf << 4)
-#define CCM_PCDR_PCLK1_OFFSET  0
-#define CCM_PCDR_PCLK1_MASK    0xf
-
-#define IO_ADDR_SCM(off)       (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
-
-/* SCM register addresses */
-#define SCM_GCCR       IO_ADDR_SCM(0xc)
-
-#define SCM_GCCR_DMA_CLK_EN_OFFSET     3
-#define SCM_GCCR_CSI_CLK_EN_OFFSET     2
-#define SCM_GCCR_MMA_CLK_EN_OFFSET     1
-#define SCM_GCCR_USBD_CLK_EN_OFFSET    0
-
-static int _clk_enable(struct clk *clk)
-{
-       unsigned int reg;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg |= 1 << clk->enable_shift;
-       __raw_writel(reg, clk->enable_reg);
-
-       return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
-       unsigned int reg;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg &= ~(1 << clk->enable_shift);
-       __raw_writel(reg, clk->enable_reg);
-}
-
-static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
-                              struct clk *parent)
-{
-       int i;
-
-       for (i = 0; i < size; i++)
-               if (parent == clk_arr[i])
-                       return i;
-
-       return -EINVAL;
-}
-
-static unsigned long
-_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
-{
-       int div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (parent_rate % rate)
-               div++;
-
-       if (div > limit)
-               div = limit;
-
-       return parent_rate / div;
-}
-
-static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
-{
-       return clk->parent->round_rate(clk->parent, rate);
-}
-
-static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
-{
-       return clk->parent->set_rate(clk->parent, rate);
-}
-
-static unsigned long clk16m_get_rate(struct clk *clk)
-{
-       return 16000000;
-}
-
-static struct clk clk16m = {
-       .get_rate = clk16m_get_rate,
-       .enable = _clk_enable,
-       .enable_reg = CCM_CSCR,
-       .enable_shift = CCM_CSCR_OSC_EN_SHIFT,
-       .disable = _clk_disable,
-};
-
-/* in Hz */
-static unsigned long clk32_rate;
-
-static unsigned long clk32_get_rate(struct clk *clk)
-{
-       return clk32_rate;
-}
-
-static struct clk clk32 = {
-       .get_rate = clk32_get_rate,
-};
-
-static unsigned long clk32_premult_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) * 512;
-}
-
-static struct clk clk32_premult = {
-       .parent = &clk32,
-       .get_rate = clk32_premult_get_rate,
-};
-
-static const struct clk *prem_clk_clocks[] = {
-       &clk32_premult,
-       &clk16m,
-};
-
-static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
-{
-       int i;
-       unsigned int reg = __raw_readl(CCM_CSCR);
-
-       i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
-                               parent);
-
-       switch (i) {
-       case 0:
-               reg &= ~CCM_CSCR_SYSTEM_SEL;
-               break;
-       case 1:
-               reg |= CCM_CSCR_SYSTEM_SEL;
-               break;
-       default:
-               return i;
-       }
-
-       __raw_writel(reg, CCM_CSCR);
-
-       return 0;
-}
-
-static struct clk prem_clk = {
-       .set_parent = prem_clk_set_parent,
-};
-
-static unsigned long system_clk_get_rate(struct clk *clk)
-{
-       return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
-                             clk_get_rate(clk->parent));
-}
-
-static struct clk system_clk = {
-       .parent = &prem_clk,
-       .get_rate = system_clk_get_rate,
-};
-
-static unsigned long mcu_clk_get_rate(struct clk *clk)
-{
-       return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
-                             clk_get_rate(clk->parent));
-}
-
-static struct clk mcu_clk = {
-       .parent = &clk32_premult,
-       .get_rate = mcu_clk_get_rate,
-};
-
-static unsigned long fclk_get_rate(struct clk *clk)
-{
-       unsigned long fclk = clk_get_rate(clk->parent);
-
-       if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
-               fclk /= 2;
-
-       return fclk;
-}
-
-static struct clk fclk = {
-       .parent = &mcu_clk,
-       .get_rate = fclk_get_rate,
-};
-
-/*
- *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
- */
-static unsigned long hclk_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
-                       CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
-}
-
-static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
-{
-       return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int hclk_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned int div;
-       unsigned int reg;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-
-       if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-
-       div--;
-
-       reg = __raw_readl(CCM_CSCR);
-       reg &= ~CCM_CSCR_BCLK_MASK;
-       reg |= div << CCM_CSCR_BCLK_OFFSET;
-       __raw_writel(reg, CCM_CSCR);
-
-       return 0;
-}
-
-static struct clk hclk = {
-       .parent = &system_clk,
-       .get_rate = hclk_get_rate,
-       .round_rate = hclk_round_rate,
-       .set_rate = hclk_set_rate,
-};
-
-static unsigned long clk48m_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
-                       CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
-}
-
-static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
-{
-       return _clk_simple_round_rate(clk, rate, 8);
-}
-
-static int clk48m_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned int div;
-       unsigned int reg;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-
-       if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-
-       div--;
-
-       reg = __raw_readl(CCM_CSCR);
-       reg &= ~CCM_CSCR_USB_MASK;
-       reg |= div << CCM_CSCR_USB_OFFSET;
-       __raw_writel(reg, CCM_CSCR);
-
-       return 0;
-}
-
-static struct clk clk48m = {
-       .parent = &system_clk,
-       .get_rate = clk48m_get_rate,
-       .round_rate = clk48m_round_rate,
-       .set_rate = clk48m_set_rate,
-};
-
-/*
- *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
- */
-static unsigned long perclk1_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-                       CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
-}
-
-static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
-{
-       return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int perclk1_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned int div;
-       unsigned int reg;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-
-       if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-
-       div--;
-
-       reg = __raw_readl(CCM_PCDR);
-       reg &= ~CCM_PCDR_PCLK1_MASK;
-       reg |= div << CCM_PCDR_PCLK1_OFFSET;
-       __raw_writel(reg, CCM_PCDR);
-
-       return 0;
-}
-
-/*
- *  get peripheral clock 2 ( LCD, SD, SPI[12] )
- */
-static unsigned long perclk2_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-                       CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
-}
-
-static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
-{
-       return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int perclk2_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned int div;
-       unsigned int reg;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-
-       if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-
-       div--;
-
-       reg = __raw_readl(CCM_PCDR);
-       reg &= ~CCM_PCDR_PCLK2_MASK;
-       reg |= div << CCM_PCDR_PCLK2_OFFSET;
-       __raw_writel(reg, CCM_PCDR);
-
-       return 0;
-}
-
-/*
- *  get peripheral clock 3 ( SSI )
- */
-static unsigned long perclk3_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-                       CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
-}
-
-static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
-{
-       return _clk_simple_round_rate(clk, rate, 128);
-}
-
-static int perclk3_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned int div;
-       unsigned int reg;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-
-       if (div > 128 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-
-       div--;
-
-       reg = __raw_readl(CCM_PCDR);
-       reg &= ~CCM_PCDR_PCLK3_MASK;
-       reg |= div << CCM_PCDR_PCLK3_OFFSET;
-       __raw_writel(reg, CCM_PCDR);
-
-       return 0;
-}
-
-static struct clk perclk[] = {
-       {
-               .id = 0,
-               .parent = &system_clk,
-               .get_rate = perclk1_get_rate,
-               .round_rate = perclk1_round_rate,
-               .set_rate = perclk1_set_rate,
-       }, {
-               .id = 1,
-               .parent = &system_clk,
-               .get_rate = perclk2_get_rate,
-               .round_rate = perclk2_round_rate,
-               .set_rate = perclk2_set_rate,
-       }, {
-               .id = 2,
-               .parent = &system_clk,
-               .get_rate = perclk3_get_rate,
-               .round_rate = perclk3_round_rate,
-               .set_rate = perclk3_set_rate,
-       }
-};
-
-static const struct clk *clko_clocks[] = {
-       &perclk[0],
-       &hclk,
-       &clk48m,
-       &clk16m,
-       &prem_clk,
-       &fclk,
-};
-
-static int clko_set_parent(struct clk *clk, struct clk *parent)
-{
-       int i;
-       unsigned int reg;
-
-       i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
-       if (i < 0)
-               return i;
-
-       reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
-       reg |= i << CCM_CSCR_CLKO_OFFSET;
-       __raw_writel(reg, CCM_CSCR);
-
-       if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
-               clk->set_rate = _clk_parent_set_rate;
-               clk->round_rate = _clk_parent_round_rate;
-       } else {
-               clk->set_rate = NULL;
-               clk->round_rate = NULL;
-       }
-
-       return 0;
-}
-
-static struct clk clko_clk = {
-       .set_parent = clko_set_parent,
-};
-
-static struct clk dma_clk = {
-       .parent = &hclk,
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-       .enable = _clk_enable,
-       .enable_reg = SCM_GCCR,
-       .enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk csi_clk = {
-       .parent = &hclk,
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-       .enable = _clk_enable,
-       .enable_reg = SCM_GCCR,
-       .enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk mma_clk = {
-       .parent = &hclk,
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-       .enable = _clk_enable,
-       .enable_reg = SCM_GCCR,
-       .enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk usbd_clk = {
-       .parent = &clk48m,
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-       .enable = _clk_enable,
-       .enable_reg = SCM_GCCR,
-       .enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk gpt_clk = {
-       .parent = &perclk[0],
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk uart_clk = {
-       .parent = &perclk[0],
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk i2c_clk = {
-       .parent = &hclk,
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk spi_clk = {
-       .parent = &perclk[1],
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk sdhc_clk = {
-       .parent = &perclk[1],
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk lcdc_clk = {
-       .parent = &perclk[1],
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk mshc_clk = {
-       .parent = &hclk,
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk ssi_clk = {
-       .parent = &perclk[2],
-       .round_rate = _clk_parent_round_rate,
-       .set_rate = _clk_parent_set_rate,
-};
-
-static struct clk rtc_clk = {
-       .parent = &clk32,
-};
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c, \
-       },
-static struct clk_lookup lookups[] __initdata = {
-       _REGISTER_CLOCK(NULL, "dma", dma_clk)
-       _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
-       _REGISTER_CLOCK(NULL, "mma", mma_clk)
-       _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
-       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-       _REGISTER_CLOCK("imx1-uart.0", NULL, uart_clk)
-       _REGISTER_CLOCK("imx1-uart.1", NULL, uart_clk)
-       _REGISTER_CLOCK("imx1-uart.2", NULL, uart_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-       _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
-       _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
-       _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
-       _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-       _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
-       _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
-       _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
-};
-
-int __init mx1_clocks_init(unsigned long fref)
-{
-       unsigned int reg;
-
-       /* disable clocks we are able to */
-       __raw_writel(0, SCM_GCCR);
-
-       clk32_rate = fref;
-       reg = __raw_readl(CCM_CSCR);
-
-       /* detect clock reference for system PLL */
-       if (reg & CCM_CSCR_SYSTEM_SEL) {
-               prem_clk.parent = &clk16m;
-       } else {
-               /* ensure that oscillator is disabled */
-               reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
-               __raw_writel(reg, CCM_CSCR);
-               prem_clk.parent = &clk32_premult;
-       }
-
-       /* detect reference for CLKO */
-       reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
-       clko_clk.parent = (struct clk *)clko_clocks[reg];
-
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-       clk_enable(&hclk);
-       clk_enable(&fclk);
-
-       mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
-                       MX1_TIM1_INT);
-
-       return 0;
-}

diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
deleted file mode 100644 (file)
index ee15d8c..0000000
--- a/arch/arm/mach-imx/clock-imx21.c
+++ /dev/null
@@ -1,1239 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/div64.h>
-
-#define IO_ADDR_CCM(off)       (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
-
-/* Register offsets */
-#define CCM_CSCR               IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0             IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1             IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0             IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1             IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL          IO_ADDR_CCM(0x14)
-#define CCM_PCDR0              IO_ADDR_CCM(0x18)
-#define CCM_PCDR1              IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0              IO_ADDR_CCM(0x20)
-#define CCM_PCCR1              IO_ADDR_CCM(0x24)
-#define CCM_CCSR               IO_ADDR_CCM(0x28)
-#define CCM_PMCTL              IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT            IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL            IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_PRESC_OFFSET  29
-#define CCM_CSCR_PRESC_MASK    (0x7 << CCM_CSCR_PRESC_OFFSET)
-
-#define CCM_CSCR_USB_OFFSET    26
-#define CCM_CSCR_USB_MASK      (0x7 << CCM_CSCR_USB_OFFSET)
-#define CCM_CSCR_SD_OFFSET     24
-#define CCM_CSCR_SD_MASK       (0x3 << CCM_CSCR_SD_OFFSET)
-#define CCM_CSCR_SPLLRES       (1 << 22)
-#define CCM_CSCR_MPLLRES       (1 << 21)
-#define CCM_CSCR_SSI2_OFFSET   20
-#define CCM_CSCR_SSI2          (1 << CCM_CSCR_SSI2_OFFSET)
-#define CCM_CSCR_SSI1_OFFSET   19
-#define CCM_CSCR_SSI1          (1 << CCM_CSCR_SSI1_OFFSET)
-#define CCM_CSCR_FIR_OFFSET    18
-#define CCM_CSCR_FIR           (1 << CCM_CSCR_FIR_OFFSET)
-#define CCM_CSCR_SP            (1 << 17)
-#define CCM_CSCR_MCU           (1 << 16)
-#define CCM_CSCR_BCLK_OFFSET   10
-#define CCM_CSCR_BCLK_MASK     (0xf << CCM_CSCR_BCLK_OFFSET)
-#define CCM_CSCR_IPDIV_OFFSET  9
-#define CCM_CSCR_IPDIV         (1 << CCM_CSCR_IPDIV_OFFSET)
-
-#define CCM_CSCR_OSC26MDIV     (1 << 4)
-#define CCM_CSCR_OSC26M                (1 << 3)
-#define CCM_CSCR_FPM           (1 << 2)
-#define CCM_CSCR_SPEN          (1 << 1)
-#define CCM_CSCR_MPEN          1
-
-#define CCM_MPCTL0_CPLM                (1 << 31)
-#define CCM_MPCTL0_PD_OFFSET   26
-#define CCM_MPCTL0_PD_MASK     (0xf << 26)
-#define CCM_MPCTL0_MFD_OFFSET  16
-#define CCM_MPCTL0_MFD_MASK    (0x3ff << 16)
-#define CCM_MPCTL0_MFI_OFFSET  10
-#define CCM_MPCTL0_MFI_MASK    (0xf << 10)
-#define CCM_MPCTL0_MFN_OFFSET  0
-#define CCM_MPCTL0_MFN_MASK    0x3ff
-
-#define CCM_MPCTL1_LF          (1 << 15)
-#define CCM_MPCTL1_BRMO                (1 << 6)
-
-#define CCM_SPCTL0_CPLM                (1 << 31)
-#define CCM_SPCTL0_PD_OFFSET   26
-#define CCM_SPCTL0_PD_MASK     (0xf << 26)
-#define CCM_SPCTL0_MFD_OFFSET  16
-#define CCM_SPCTL0_MFD_MASK    (0x3ff << 16)
-#define CCM_SPCTL0_MFI_OFFSET  10
-#define CCM_SPCTL0_MFI_MASK    (0xf << 10)
-#define CCM_SPCTL0_MFN_OFFSET  0
-#define CCM_SPCTL0_MFN_MASK    0x3ff
-
-#define CCM_SPCTL1_LF          (1 << 15)
-#define CCM_SPCTL1_BRMO                (1 << 6)
-
-#define CCM_OSC26MCTL_PEAK_OFFSET      16
-#define CCM_OSC26MCTL_PEAK_MASK                (0x3 << 16)
-#define CCM_OSC26MCTL_AGC_OFFSET       8
-#define CCM_OSC26MCTL_AGC_MASK         (0x3f << 8)
-#define CCM_OSC26MCTL_ANATEST_OFFSET   0
-#define CCM_OSC26MCTL_ANATEST_MASK     0x3f
-
-#define CCM_PCDR0_SSI2BAUDDIV_OFFSET   26
-#define CCM_PCDR0_SSI2BAUDDIV_MASK     (0x3f << 26)
-#define CCM_PCDR0_SSI1BAUDDIV_OFFSET   16
-#define CCM_PCDR0_SSI1BAUDDIV_MASK     (0x3f << 16)
-#define CCM_PCDR0_NFCDIV_OFFSET                12
-#define CCM_PCDR0_NFCDIV_MASK          (0xf << 12)
-#define CCM_PCDR0_48MDIV_OFFSET                5
-#define CCM_PCDR0_48MDIV_MASK          (0x7 << CCM_PCDR0_48MDIV_OFFSET)
-#define CCM_PCDR0_FIRIDIV_OFFSET       0
-#define CCM_PCDR0_FIRIDIV_MASK         0x1f
-#define CCM_PCDR1_PERDIV4_OFFSET       24
-#define CCM_PCDR1_PERDIV4_MASK         (0x3f << 24)
-#define CCM_PCDR1_PERDIV3_OFFSET       16
-#define CCM_PCDR1_PERDIV3_MASK         (0x3f << 16)
-#define CCM_PCDR1_PERDIV2_OFFSET       8
-#define CCM_PCDR1_PERDIV2_MASK         (0x3f << 8)
-#define CCM_PCDR1_PERDIV1_OFFSET       0
-#define CCM_PCDR1_PERDIV1_MASK         0x3f
-
-#define CCM_PCCR_HCLK_CSI_OFFSET       31
-#define CCM_PCCR_HCLK_CSI_REG          CCM_PCCR0
-#define CCM_PCCR_HCLK_DMA_OFFSET       30
-#define CCM_PCCR_HCLK_DMA_REG          CCM_PCCR0
-#define CCM_PCCR_HCLK_BROM_OFFSET      28
-#define CCM_PCCR_HCLK_BROM_REG         CCM_PCCR0
-#define CCM_PCCR_HCLK_EMMA_OFFSET      27
-#define CCM_PCCR_HCLK_EMMA_REG         CCM_PCCR0
-#define CCM_PCCR_HCLK_LCDC_OFFSET      26
-#define CCM_PCCR_HCLK_LCDC_REG         CCM_PCCR0
-#define CCM_PCCR_HCLK_SLCDC_OFFSET     25
-#define CCM_PCCR_HCLK_SLCDC_REG                CCM_PCCR0
-#define CCM_PCCR_HCLK_USBOTG_OFFSET    24
-#define CCM_PCCR_HCLK_USBOTG_REG       CCM_PCCR0
-#define CCM_PCCR_HCLK_BMI_OFFSET       23
-#define CCM_PCCR_BMI_MASK              (1 << CCM_PCCR_BMI_MASK)
-#define CCM_PCCR_HCLK_BMI_REG          CCM_PCCR0
-#define CCM_PCCR_PERCLK4_OFFSET                22
-#define CCM_PCCR_PERCLK4_REG           CCM_PCCR0
-#define CCM_PCCR_SLCDC_OFFSET          21
-#define CCM_PCCR_SLCDC_REG             CCM_PCCR0
-#define CCM_PCCR_FIRI_BAUD_OFFSET      20
-#define CCM_PCCR_FIRI_BAUD_MASK                (1 << CCM_PCCR_FIRI_BAUD_MASK)
-#define CCM_PCCR_FIRI_BAUD_REG         CCM_PCCR0
-#define CCM_PCCR_NFC_OFFSET            19
-#define CCM_PCCR_NFC_REG               CCM_PCCR0
-#define CCM_PCCR_LCDC_OFFSET           18
-#define CCM_PCCR_LCDC_REG              CCM_PCCR0
-#define CCM_PCCR_SSI1_BAUD_OFFSET      17
-#define CCM_PCCR_SSI1_BAUD_REG         CCM_PCCR0
-#define CCM_PCCR_SSI2_BAUD_OFFSET      16
-#define CCM_PCCR_SSI2_BAUD_REG         CCM_PCCR0
-#define CCM_PCCR_EMMA_OFFSET           15
-#define CCM_PCCR_EMMA_REG              CCM_PCCR0
-#define CCM_PCCR_USBOTG_OFFSET         14
-#define CCM_PCCR_USBOTG_REG            CCM_PCCR0
-#define CCM_PCCR_DMA_OFFSET            13
-#define CCM_PCCR_DMA_REG               CCM_PCCR0
-#define CCM_PCCR_I2C1_OFFSET           12
-#define CCM_PCCR_I2C1_REG              CCM_PCCR0
-#define CCM_PCCR_GPIO_OFFSET           11
-#define CCM_PCCR_GPIO_REG              CCM_PCCR0
-#define CCM_PCCR_SDHC2_OFFSET          10
-#define CCM_PCCR_SDHC2_REG             CCM_PCCR0
-#define CCM_PCCR_SDHC1_OFFSET          9
-#define CCM_PCCR_SDHC1_REG             CCM_PCCR0
-#define CCM_PCCR_FIRI_OFFSET           8
-#define CCM_PCCR_FIRI_MASK             (1 << CCM_PCCR_BAUD_MASK)
-#define CCM_PCCR_FIRI_REG              CCM_PCCR0
-#define CCM_PCCR_SSI2_IPG_OFFSET       7
-#define CCM_PCCR_SSI2_REG              CCM_PCCR0
-#define CCM_PCCR_SSI1_IPG_OFFSET       6
-#define CCM_PCCR_SSI1_REG              CCM_PCCR0
-#define CCM_PCCR_CSPI2_OFFSET          5
-#define        CCM_PCCR_CSPI2_REG              CCM_PCCR0
-#define CCM_PCCR_CSPI1_OFFSET          4
-#define        CCM_PCCR_CSPI1_REG              CCM_PCCR0
-#define CCM_PCCR_UART4_OFFSET          3
-#define CCM_PCCR_UART4_REG             CCM_PCCR0
-#define CCM_PCCR_UART3_OFFSET          2
-#define CCM_PCCR_UART3_REG             CCM_PCCR0
-#define CCM_PCCR_UART2_OFFSET          1
-#define CCM_PCCR_UART2_REG             CCM_PCCR0
-#define CCM_PCCR_UART1_OFFSET          0
-#define CCM_PCCR_UART1_REG             CCM_PCCR0
-
-#define CCM_PCCR_OWIRE_OFFSET          31
-#define CCM_PCCR_OWIRE_REG             CCM_PCCR1
-#define CCM_PCCR_KPP_OFFSET            30
-#define CCM_PCCR_KPP_REG               CCM_PCCR1
-#define CCM_PCCR_RTC_OFFSET            29
-#define CCM_PCCR_RTC_REG               CCM_PCCR1
-#define CCM_PCCR_PWM_OFFSET            28
-#define CCM_PCCR_PWM_REG               CCM_PCCR1
-#define CCM_PCCR_GPT3_OFFSET           27
-#define CCM_PCCR_GPT3_REG              CCM_PCCR1
-#define CCM_PCCR_GPT2_OFFSET           26
-#define CCM_PCCR_GPT2_REG              CCM_PCCR1
-#define CCM_PCCR_GPT1_OFFSET           25
-#define CCM_PCCR_GPT1_REG              CCM_PCCR1
-#define CCM_PCCR_WDT_OFFSET            24
-#define CCM_PCCR_WDT_REG               CCM_PCCR1
-#define CCM_PCCR_CSPI3_OFFSET          23
-#define        CCM_PCCR_CSPI3_REG              CCM_PCCR1
-
-#define CCM_PCCR_CSPI1_MASK            (1 << CCM_PCCR_CSPI1_OFFSET)
-#define CCM_PCCR_CSPI2_MASK            (1 << CCM_PCCR_CSPI2_OFFSET)
-#define CCM_PCCR_CSPI3_MASK            (1 << CCM_PCCR_CSPI3_OFFSET)
-#define CCM_PCCR_DMA_MASK              (1 << CCM_PCCR_DMA_OFFSET)
-#define CCM_PCCR_EMMA_MASK             (1 << CCM_PCCR_EMMA_OFFSET)
-#define CCM_PCCR_GPIO_MASK             (1 << CCM_PCCR_GPIO_OFFSET)
-#define CCM_PCCR_GPT1_MASK             (1 << CCM_PCCR_GPT1_OFFSET)
-#define CCM_PCCR_GPT2_MASK             (1 << CCM_PCCR_GPT2_OFFSET)
-#define CCM_PCCR_GPT3_MASK             (1 << CCM_PCCR_GPT3_OFFSET)
-#define CCM_PCCR_HCLK_BROM_MASK                (1 << CCM_PCCR_HCLK_BROM_OFFSET)
-#define CCM_PCCR_HCLK_CSI_MASK         (1 << CCM_PCCR_HCLK_CSI_OFFSET)
-#define CCM_PCCR_HCLK_DMA_MASK         (1 << CCM_PCCR_HCLK_DMA_OFFSET)
-#define CCM_PCCR_HCLK_EMMA_MASK                (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
-#define CCM_PCCR_HCLK_LCDC_MASK                (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
-#define CCM_PCCR_HCLK_SLCDC_MASK       (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
-#define CCM_PCCR_HCLK_USBOTG_MASK      (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
-#define CCM_PCCR_I2C1_MASK             (1 << CCM_PCCR_I2C1_OFFSET)
-#define CCM_PCCR_KPP_MASK              (1 << CCM_PCCR_KPP_OFFSET)
-#define CCM_PCCR_LCDC_MASK             (1 << CCM_PCCR_LCDC_OFFSET)
-#define CCM_PCCR_NFC_MASK              (1 << CCM_PCCR_NFC_OFFSET)
-#define CCM_PCCR_OWIRE_MASK            (1 << CCM_PCCR_OWIRE_OFFSET)
-#define CCM_PCCR_PERCLK4_MASK          (1 << CCM_PCCR_PERCLK4_OFFSET)
-#define CCM_PCCR_PWM_MASK              (1 << CCM_PCCR_PWM_OFFSET)
-#define CCM_PCCR_RTC_MASK              (1 << CCM_PCCR_RTC_OFFSET)
-#define CCM_PCCR_SDHC1_MASK            (1 << CCM_PCCR_SDHC1_OFFSET)
-#define CCM_PCCR_SDHC2_MASK            (1 << CCM_PCCR_SDHC2_OFFSET)
-#define CCM_PCCR_SLCDC_MASK            (1 << CCM_PCCR_SLCDC_OFFSET)
-#define CCM_PCCR_SSI1_BAUD_MASK                (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
-#define CCM_PCCR_SSI1_IPG_MASK         (1 << CCM_PCCR_SSI1_IPG_OFFSET)
-#define CCM_PCCR_SSI2_BAUD_MASK                (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
-#define CCM_PCCR_SSI2_IPG_MASK         (1 << CCM_PCCR_SSI2_IPG_OFFSET)
-#define CCM_PCCR_UART1_MASK            (1 << CCM_PCCR_UART1_OFFSET)
-#define CCM_PCCR_UART2_MASK            (1 << CCM_PCCR_UART2_OFFSET)
-#define CCM_PCCR_UART3_MASK            (1 << CCM_PCCR_UART3_OFFSET)
-#define CCM_PCCR_UART4_MASK            (1 << CCM_PCCR_UART4_OFFSET)
-#define CCM_PCCR_USBOTG_MASK           (1 << CCM_PCCR_USBOTG_OFFSET)
-#define CCM_PCCR_WDT_MASK              (1 << CCM_PCCR_WDT_OFFSET)
-
-#define CCM_CCSR_32KSR         (1 << 15)
-
-#define CCM_CCSR_CLKMODE1      (1 << 9)
-#define CCM_CCSR_CLKMODE0      (1 << 8)
-
-#define CCM_CCSR_CLKOSEL_OFFSET 0
-#define CCM_CCSR_CLKOSEL_MASK  0x1f
-
-#define SYS_FMCR               0x14    /* Functional Muxing Control Reg */
-#define SYS_CHIP_ID            0x00    /* The offset of CHIP ID register */
-
-static int _clk_enable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg |= 1 << clk->enable_shift;
-       __raw_writel(reg, clk->enable_reg);
-       return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg &= ~(1 << clk->enable_shift);
-       __raw_writel(reg, clk->enable_reg);
-}
-
-static unsigned long _clk_generic_round_rate(struct clk *clk,
-                       unsigned long rate,
-                       u32 max_divisor)
-{
-       u32 div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (parent_rate % rate)
-               div++;
-
-       if (div > max_divisor)
-               div = max_divisor;
-
-       return parent_rate / div;
-}
-
-static int _clk_spll_enable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(CCM_CSCR);
-       reg |= CCM_CSCR_SPEN;
-       __raw_writel(reg, CCM_CSCR);
-
-       while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
-               ;
-       return 0;
-}
-
-static void _clk_spll_disable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(CCM_CSCR);
-       reg &= ~CCM_CSCR_SPEN;
-       __raw_writel(reg, CCM_CSCR);
-}
-
-
-#define CSCR() (__raw_readl(CCM_CSCR))
-#define PCDR0() (__raw_readl(CCM_PCDR0))
-#define PCDR1() (__raw_readl(CCM_PCDR1))
-
-static unsigned long _clk_perclkx_round_rate(struct clk *clk,
-                                            unsigned long rate)
-{
-       return _clk_generic_round_rate(clk, rate, 64);
-}
-
-static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg;
-       u32 div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (clk->id < 0 || clk->id > 3)
-               return -EINVAL;
-
-       div = parent_rate / rate;
-       if (div > 64 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-       div--;
-
-       reg =
-           __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
-                                      (clk->id << 3));
-       reg |= div << (clk->id << 3);
-       __raw_writel(reg, CCM_PCDR1);
-
-       return 0;
-}
-
-static unsigned long _clk_usb_recalc(struct clk *clk)
-{
-       unsigned long usb_pdf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
-
-       return parent_rate / (usb_pdf + 1U);
-}
-
-static unsigned long _clk_usb_round_rate(struct clk *clk,
-                                            unsigned long rate)
-{
-       return _clk_generic_round_rate(clk, rate, 8);
-}
-
-static int _clk_usb_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg;
-       u32 div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-       div--;
-
-       reg = CSCR() & ~CCM_CSCR_USB_MASK;
-       reg |= div << CCM_CSCR_USB_OFFSET;
-       __raw_writel(reg, CCM_CSCR);
-
-       return 0;
-}
-
-static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
-{
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
-
-       return 2UL * parent_rate / pdf;
-}
-
-static unsigned long _clk_ssi1_recalc(struct clk *clk)
-{
-       return _clk_ssix_recalc(clk,
-               (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK)
-               >> CCM_PCDR0_SSI1BAUDDIV_OFFSET);
-}
-
-static unsigned long _clk_ssi2_recalc(struct clk *clk)
-{
-       return _clk_ssix_recalc(clk,
-               (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
-               CCM_PCDR0_SSI2BAUDDIV_OFFSET);
-}
-
-static unsigned long _clk_nfc_recalc(struct clk *clk)
-{
-       unsigned long nfc_pdf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK)
-               >> CCM_PCDR0_NFCDIV_OFFSET;
-
-       return parent_rate / (nfc_pdf + 1);
-}
-
-static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
-{
-       return clk->parent->round_rate(clk->parent, rate);
-}
-
-static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
-{
-       return clk->parent->set_rate(clk->parent, rate);
-}
-
-static unsigned long external_high_reference; /* in Hz */
-
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
-{
-       return external_high_reference;
-}
-
-/*
- * the high frequency external clock reference
- * Default case is 26MHz.
- */
-static struct clk ckih_clk = {
-       .get_rate = get_high_reference_clock_rate,
-};
-
-static unsigned long external_low_reference; /* in Hz */
-
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
-{
-       return external_low_reference;
-}
-
-/*
- * the low frequency external clock reference
- * Default case is 32.768kHz.
- */
-static struct clk ckil_clk = {
-       .get_rate = get_low_reference_clock_rate,
-};
-
-
-static unsigned long _clk_fpm_recalc(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) * 512;
-}
-
-/* Output of frequency pre multiplier */
-static struct clk fpm_clk = {
-       .parent = &ckil_clk,
-       .get_rate = _clk_fpm_recalc,
-};
-
-static unsigned long get_mpll_clk(struct clk *clk)
-{
-       uint32_t reg;
-       unsigned long ref_clk;
-       unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
-       unsigned long long temp;
-
-       ref_clk = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(CCM_MPCTL0);
-       pdf = (reg & CCM_MPCTL0_PD_MASK)  >> CCM_MPCTL0_PD_OFFSET;
-       mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
-       mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
-       mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
-
-       mfi = (mfi <= 5) ? 5 : mfi;
-       temp = 2LL * ref_clk * mfn;
-       do_div(temp, mfd + 1);
-       temp = 2LL * ref_clk * mfi + temp;
-       do_div(temp, pdf + 1);
-
-       return (unsigned long)temp;
-}
-
-static struct clk mpll_clk = {
-       .parent = &ckih_clk,
-       .get_rate = get_mpll_clk,
-};
-
-static unsigned long _clk_fclk_get_rate(struct clk *clk)
-{
-       unsigned long parent_rate;
-       u32 div;
-
-       div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
-       parent_rate = clk_get_rate(clk->parent);
-
-       return parent_rate / (div+1);
-}
-
-static struct clk fclk_clk = {
-       .parent = &mpll_clk,
-       .get_rate = _clk_fclk_get_rate
-};
-
-static unsigned long get_spll_clk(struct clk *clk)
-{
-       uint32_t reg;
-       unsigned long ref_clk;
-       unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
-       unsigned long long temp;
-
-       ref_clk = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(CCM_SPCTL0);
-       pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
-       mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
-       mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
-       mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
-
-       mfi = (mfi <= 5) ? 5 : mfi;
-       temp = 2LL * ref_clk * mfn;
-       do_div(temp, mfd + 1);
-       temp = 2LL * ref_clk * mfi + temp;
-       do_div(temp, pdf + 1);
-
-       return (unsigned long)temp;
-}
-
-static struct clk spll_clk = {
-       .parent = &ckih_clk,
-       .get_rate = get_spll_clk,
-       .enable = _clk_spll_enable,
-       .disable = _clk_spll_disable,
-};
-
-static unsigned long get_hclk_clk(struct clk *clk)
-{
-       unsigned long rate;
-       unsigned long bclk_pdf;
-
-       bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
-               >> CCM_CSCR_BCLK_OFFSET;
-
-       rate = clk_get_rate(clk->parent);
-       return rate / (bclk_pdf + 1);
-}
-
-static struct clk hclk_clk = {
-       .parent = &fclk_clk,
-       .get_rate = get_hclk_clk,
-};
-
-static unsigned long get_ipg_clk(struct clk *clk)
-{
-       unsigned long rate;
-       unsigned long ipg_pdf;
-
-       ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
-
-       rate = clk_get_rate(clk->parent);
-       return rate / (ipg_pdf + 1);
-}
-
-static struct clk ipg_clk = {
-       .parent = &hclk_clk,
-       .get_rate = get_ipg_clk,
-};
-
-static unsigned long _clk_perclkx_recalc(struct clk *clk)
-{
-       unsigned long perclk_pdf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (clk->id < 0 || clk->id > 3)
-               return 0;
-
-       perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
-
-       return parent_rate / (perclk_pdf + 1);
-}
-
-static struct clk per_clk[] = {
-       {
-               .id = 0,
-               .parent = &mpll_clk,
-               .get_rate = _clk_perclkx_recalc,
-       }, {
-               .id = 1,
-               .parent = &mpll_clk,
-               .get_rate = _clk_perclkx_recalc,
-       }, {
-               .id = 2,
-               .parent = &mpll_clk,
-               .round_rate = _clk_perclkx_round_rate,
-               .set_rate = _clk_perclkx_set_rate,
-               .get_rate = _clk_perclkx_recalc,
-               /* Enable/Disable done via lcd_clkc[1] */
-       }, {
-               .id = 3,
-               .parent = &mpll_clk,
-               .round_rate = _clk_perclkx_round_rate,
-               .set_rate = _clk_perclkx_set_rate,
-               .get_rate = _clk_perclkx_recalc,
-               /* Enable/Disable done via csi_clk[1] */
-       },
-};
-
-static struct clk uart_ipg_clk[];
-
-static struct clk uart_clk[] = {
-       {
-               .id = 0,
-               .parent = &per_clk[0],
-               .secondary = &uart_ipg_clk[0],
-       }, {
-               .id = 1,
-               .parent = &per_clk[0],
-               .secondary = &uart_ipg_clk[1],
-       }, {
-               .id = 2,
-               .parent = &per_clk[0],
-               .secondary = &uart_ipg_clk[2],
-       }, {
-               .id = 3,
-               .parent = &per_clk[0],
-               .secondary = &uart_ipg_clk[3],
-       },
-};
-
-static struct clk uart_ipg_clk[] = {
-       {
-               .id = 0,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_UART1_REG,
-               .enable_shift = CCM_PCCR_UART1_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 1,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_UART2_REG,
-               .enable_shift = CCM_PCCR_UART2_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 2,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_UART3_REG,
-               .enable_shift = CCM_PCCR_UART3_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 3,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_UART4_REG,
-               .enable_shift = CCM_PCCR_UART4_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk gpt_ipg_clk[];
-
-static struct clk gpt_clk[] = {
-       {
-               .id = 0,
-               .parent = &per_clk[0],
-               .secondary = &gpt_ipg_clk[0],
-       }, {
-               .id = 1,
-               .parent = &per_clk[0],
-               .secondary = &gpt_ipg_clk[1],
-       }, {
-               .id = 2,
-               .parent = &per_clk[0],
-               .secondary = &gpt_ipg_clk[2],
-       },
-};
-
-static struct clk gpt_ipg_clk[] = {
-       {
-               .id = 0,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_GPT1_REG,
-               .enable_shift = CCM_PCCR_GPT1_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 1,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_GPT2_REG,
-               .enable_shift = CCM_PCCR_GPT2_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 2,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_GPT3_REG,
-               .enable_shift = CCM_PCCR_GPT3_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk pwm_clk[] = {
-       {
-               .parent = &per_clk[0],
-               .secondary = &pwm_clk[1],
-       }, {
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_PWM_REG,
-               .enable_shift = CCM_PCCR_PWM_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk sdhc_ipg_clk[];
-
-static struct clk sdhc_clk[] = {
-       {
-               .id = 0,
-               .parent = &per_clk[1],
-               .secondary = &sdhc_ipg_clk[0],
-       }, {
-               .id = 1,
-               .parent = &per_clk[1],
-               .secondary = &sdhc_ipg_clk[1],
-       },
-};
-
-static struct clk sdhc_ipg_clk[] = {
-       {
-               .id = 0,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_SDHC1_REG,
-               .enable_shift = CCM_PCCR_SDHC1_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 1,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_SDHC2_REG,
-               .enable_shift = CCM_PCCR_SDHC2_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk cspi_ipg_clk[];
-
-static struct clk cspi_clk[] = {
-       {
-               .id = 0,
-               .parent = &per_clk[1],
-               .secondary = &cspi_ipg_clk[0],
-       }, {
-               .id = 1,
-               .parent = &per_clk[1],
-               .secondary = &cspi_ipg_clk[1],
-       }, {
-               .id = 2,
-               .parent = &per_clk[1],
-               .secondary = &cspi_ipg_clk[2],
-       },
-};
-
-static struct clk cspi_ipg_clk[] = {
-       {
-               .id = 0,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_CSPI1_REG,
-               .enable_shift = CCM_PCCR_CSPI1_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 1,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_CSPI2_REG,
-               .enable_shift = CCM_PCCR_CSPI2_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 3,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_CSPI3_REG,
-               .enable_shift = CCM_PCCR_CSPI3_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk lcdc_clk[] = {
-       {
-               .parent = &per_clk[2],
-               .secondary = &lcdc_clk[1],
-               .round_rate = _clk_parent_round_rate,
-               .set_rate = _clk_parent_set_rate,
-       }, {
-               .parent = &ipg_clk,
-               .secondary = &lcdc_clk[2],
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_LCDC_REG,
-               .enable_shift = CCM_PCCR_LCDC_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .parent = &hclk_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_HCLK_LCDC_REG,
-               .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk csi_clk[] = {
-       {
-               .parent = &per_clk[3],
-               .secondary = &csi_clk[1],
-               .round_rate = _clk_parent_round_rate,
-               .set_rate = _clk_parent_set_rate,
-       }, {
-               .parent = &hclk_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_HCLK_CSI_REG,
-               .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk usb_clk[] = {
-       {
-               .parent = &spll_clk,
-               .secondary = &usb_clk[1],
-               .get_rate = _clk_usb_recalc,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_USBOTG_REG,
-               .enable_shift = CCM_PCCR_USBOTG_OFFSET,
-               .disable = _clk_disable,
-               .round_rate = _clk_usb_round_rate,
-               .set_rate = _clk_usb_set_rate,
-       }, {
-               .parent = &hclk_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_HCLK_USBOTG_REG,
-               .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET,
-               .disable = _clk_disable,
-       }
-};
-
-static struct clk ssi_ipg_clk[];
-
-static struct clk ssi_clk[] = {
-       {
-               .id = 0,
-               .parent = &mpll_clk,
-               .secondary = &ssi_ipg_clk[0],
-               .get_rate = _clk_ssi1_recalc,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_SSI1_BAUD_REG,
-               .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 1,
-               .parent = &mpll_clk,
-               .secondary = &ssi_ipg_clk[1],
-               .get_rate = _clk_ssi2_recalc,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_SSI2_BAUD_REG,
-               .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk ssi_ipg_clk[] = {
-       {
-               .id = 0,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_SSI1_REG,
-               .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET,
-               .disable = _clk_disable,
-       }, {
-               .id = 1,
-               .parent = &ipg_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_SSI2_REG,
-               .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-
-static struct clk nfc_clk = {
-       .parent = &fclk_clk,
-       .get_rate = _clk_nfc_recalc,
-       .enable = _clk_enable,
-       .enable_reg = CCM_PCCR_NFC_REG,
-       .enable_shift = CCM_PCCR_NFC_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk dma_clk[] = {
-       {
-               .parent = &hclk_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_DMA_REG,
-               .enable_shift = CCM_PCCR_DMA_OFFSET,
-               .disable = _clk_disable,
-               .secondary = &dma_clk[1],
-       },  {
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_HCLK_DMA_REG,
-               .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET,
-               .disable = _clk_disable,
-       },
-};
-
-static struct clk brom_clk = {
-       .parent = &hclk_clk,
-       .enable = _clk_enable,
-       .enable_reg = CCM_PCCR_HCLK_BROM_REG,
-       .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk emma_clk[] = {
-       {
-               .parent = &hclk_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_EMMA_REG,
-               .enable_shift = CCM_PCCR_EMMA_OFFSET,
-               .disable = _clk_disable,
-               .secondary = &emma_clk[1],
-       }, {
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_HCLK_EMMA_REG,
-               .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET,
-               .disable = _clk_disable,
-       }
-};
-
-static struct clk slcdc_clk[] = {
-       {
-               .parent = &hclk_clk,
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_SLCDC_REG,
-               .enable_shift = CCM_PCCR_SLCDC_OFFSET,
-               .disable = _clk_disable,
-               .secondary = &slcdc_clk[1],
-       }, {
-               .enable = _clk_enable,
-               .enable_reg = CCM_PCCR_HCLK_SLCDC_REG,
-               .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET,
-               .disable = _clk_disable,
-       }
-};
-
-static struct clk wdog_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_enable,
-       .enable_reg = CCM_PCCR_WDT_REG,
-       .enable_shift = CCM_PCCR_WDT_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk gpio_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_enable,
-       .enable_reg = CCM_PCCR_GPIO_REG,
-       .enable_shift = CCM_PCCR_GPIO_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk i2c_clk = {
-       .id = 0,
-       .parent = &ipg_clk,
-       .enable = _clk_enable,
-       .enable_reg = CCM_PCCR_I2C1_REG,
-       .enable_shift = CCM_PCCR_I2C1_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk kpp_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_enable,
-       .enable_reg = CCM_PCCR_KPP_REG,
-       .enable_shift = CCM_PCCR_KPP_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk owire_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_enable,
-       .enable_reg = CCM_PCCR_OWIRE_REG,
-       .enable_shift = CCM_PCCR_OWIRE_OFFSET,
-       .disable = _clk_disable,
-};
-
-static struct clk rtc_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_enable,
-       .enable_reg = CCM_PCCR_RTC_REG,
-       .enable_shift = CCM_PCCR_RTC_OFFSET,
-       .disable = _clk_disable,
-};
-
-static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
-{
-       return _clk_generic_round_rate(clk, rate, 8);
-}
-
-static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg;
-       u32 div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-
-       if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-       div--;
-
-       reg = __raw_readl(CCM_PCDR0);
-
-       if (clk->parent == &usb_clk[0]) {
-               reg &= ~CCM_PCDR0_48MDIV_MASK;
-               reg |= div << CCM_PCDR0_48MDIV_OFFSET;
-       }
-       __raw_writel(reg, CCM_PCDR0);
-
-       return 0;
-}
-
-static unsigned long _clk_clko_recalc(struct clk *clk)
-{
-       u32 div = 0;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (clk->parent == &usb_clk[0]) /* 48M */
-               div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK
-                        >> CCM_PCDR0_48MDIV_OFFSET;
-       div++;
-
-       return parent_rate / div;
-}
-
-static struct clk clko_clk;
-
-static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
-
-       if (parent == &ckil_clk)
-               reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &fpm_clk)
-               reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &ckih_clk)
-               reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == mpll_clk.parent)
-               reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == spll_clk.parent)
-               reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &mpll_clk)
-               reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &spll_clk)
-               reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &fclk_clk)
-               reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &hclk_clk)
-               reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &ipg_clk)
-               reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &per_clk[0])
-               reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &per_clk[1])
-               reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &per_clk[2])
-               reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &per_clk[3])
-               reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &ssi_clk[0])
-               reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &ssi_clk[1])
-               reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &nfc_clk)
-               reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &usb_clk[0])
-               reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET;
-       else if (parent == &clko_clk)
-               reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
-       else
-               return -EINVAL;
-
-       __raw_writel(reg, CCM_CCSR);
-
-       return 0;
-}
-
-static struct clk clko_clk = {
-       .get_rate = _clk_clko_recalc,
-       .set_rate = _clk_clko_set_rate,
-       .round_rate = _clk_clko_round_rate,
-       .set_parent = _clk_clko_set_parent,
-};
-
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c, \
-       },
-static struct clk_lookup lookups[] = {
-/* It's unlikely that any driver wants one of them directly:
-       _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
-       _REGISTER_CLOCK(NULL, "ckil", ckil_clk)
-       _REGISTER_CLOCK(NULL, "fpm", fpm_clk)
-       _REGISTER_CLOCK(NULL, "mpll", mpll_clk)
-       _REGISTER_CLOCK(NULL, "spll", spll_clk)
-       _REGISTER_CLOCK(NULL, "fclk", fclk_clk)
-       _REGISTER_CLOCK(NULL, "hclk", hclk_clk)
-       _REGISTER_CLOCK(NULL, "ipg", ipg_clk)
-*/
-       _REGISTER_CLOCK(NULL, "perclk1", per_clk[0])
-       _REGISTER_CLOCK(NULL, "perclk2", per_clk[1])
-       _REGISTER_CLOCK(NULL, "perclk3", per_clk[2])
-       _REGISTER_CLOCK(NULL, "perclk4", per_clk[3])
-       _REGISTER_CLOCK(NULL, "clko", clko_clk)
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart_clk[0])
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart_clk[1])
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart_clk[2])
-       _REGISTER_CLOCK("imx21-uart.3", NULL, uart_clk[3])
-       _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0])
-       _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1])
-       _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2])
-       _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
-       _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
-       _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
-       _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0])
-       _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1])
-       _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2])
-       _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
-       _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
-       _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
-       _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
-       _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
-       _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-       _REGISTER_CLOCK(NULL, "dma", dma_clk[0])
-       _REGISTER_CLOCK(NULL, "brom", brom_clk)
-       _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
-       _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
-       _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-       _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
-       _REGISTER_CLOCK(NULL, "owire", owire_clk)
-       _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-};
-
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
-int __init mx21_clocks_init(unsigned long lref, unsigned long href)
-{
-       u32 cscr;
-
-       external_low_reference = lref;
-       external_high_reference = href;
-
-       /* detect clock reference for both system PLL */
-       cscr = CSCR();
-       if (cscr & CCM_CSCR_MCU)
-               mpll_clk.parent = &ckih_clk;
-       else
-               mpll_clk.parent = &fpm_clk;
-
-       if (cscr & CCM_CSCR_SP)
-               spll_clk.parent = &ckih_clk;
-       else
-               spll_clk.parent = &fpm_clk;
-
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-       /* Turn off all clock gates */
-       __raw_writel(0, CCM_PCCR0);
-       __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1);
-
-       /* This turns of the serial PLL as well */
-       spll_clk.disable(&spll_clk);
-
-       /* This will propagate to all children and init all the clock rates. */
-       clk_enable(&per_clk[0]);
-       clk_enable(&gpio_clk);
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-       clk_enable(&uart_clk[0]);
-#endif
-
-       mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
-                       MX21_INT_GPT1);
-       return 0;
-}

diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
deleted file mode 100644 (file)
index b0fec74..0000000
--- a/arch/arm/mach-imx/clock-imx25.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * Copyright (C) 2009 by Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/mx25.h>
-
-#define CRM_BASE       MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
-
-#define CCM_MPCTL      0x00
-#define CCM_UPCTL      0x04
-#define CCM_CCTL       0x08
-#define CCM_CGCR0      0x0C
-#define CCM_CGCR1      0x10
-#define CCM_CGCR2      0x14
-#define CCM_PCDR0      0x18
-#define CCM_PCDR1      0x1C
-#define CCM_PCDR2      0x20
-#define CCM_PCDR3      0x24
-#define CCM_RCSR       0x28
-#define CCM_CRDR       0x2C
-#define CCM_DCVR0      0x30
-#define CCM_DCVR1      0x34
-#define CCM_DCVR2      0x38
-#define CCM_DCVR3      0x3c
-#define CCM_LTR0       0x40
-#define CCM_LTR1       0x44
-#define CCM_LTR2       0x48
-#define CCM_LTR3       0x4c
-
-static unsigned long get_rate_mpll(void)
-{
-       ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
-
-       return mxc_decode_pll(mpctl, 24000000);
-}
-
-static unsigned long get_rate_upll(void)
-{
-       ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
-
-       return mxc_decode_pll(mpctl, 24000000);
-}
-
-unsigned long get_rate_arm(struct clk *clk)
-{
-       unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
-       unsigned long rate = get_rate_mpll();
-
-       if (cctl & (1 << 14))
-               rate = (rate * 3) >> 2;
-
-       return rate / ((cctl >> 30) + 1);
-}
-
-static unsigned long get_rate_ahb(struct clk *clk)
-{
-       unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
-
-       return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
-}
-
-static unsigned long get_rate_ipg(struct clk *clk)
-{
-       return get_rate_ahb(NULL) >> 1;
-}
-
-static unsigned long get_rate_per(int per)
-{
-       unsigned long ofs = (per & 0x3) * 8;
-       unsigned long reg = per & ~0x3;
-       unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
-       unsigned long fref;
-
-       if (readl(CRM_BASE + 0x64) & (1 << per))
-               fref = get_rate_upll();
-       else
-               fref = get_rate_ahb(NULL);
-
-       return fref / (val + 1);
-}
-
-static unsigned long get_rate_uart(struct clk *clk)
-{
-       return get_rate_per(15);
-}
-
-static unsigned long get_rate_ssi2(struct clk *clk)
-{
-       return get_rate_per(14);
-}
-
-static unsigned long get_rate_ssi1(struct clk *clk)
-{
-       return get_rate_per(13);
-}
-
-static unsigned long get_rate_i2c(struct clk *clk)
-{
-       return get_rate_per(6);
-}
-
-static unsigned long get_rate_nfc(struct clk *clk)
-{
-       return get_rate_per(8);
-}
-
-static unsigned long get_rate_gpt(struct clk *clk)
-{
-       return get_rate_per(5);
-}
-
-static unsigned long get_rate_lcdc(struct clk *clk)
-{
-       return get_rate_per(7);
-}
-
-static unsigned long get_rate_esdhc1(struct clk *clk)
-{
-       return get_rate_per(3);
-}
-
-static unsigned long get_rate_esdhc2(struct clk *clk)
-{
-       return get_rate_per(4);
-}
-
-static unsigned long get_rate_csi(struct clk *clk)
-{
-       return get_rate_per(0);
-}
-
-static unsigned long get_rate_otg(struct clk *clk)
-{
-       unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
-       unsigned long rate = get_rate_upll();
-
-       return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
-}
-
-static int clk_cgcr_enable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg |= 1 << clk->enable_shift;
-       __raw_writel(reg, clk->enable_reg);
-
-       return 0;
-}
-
-static void clk_cgcr_disable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg &= ~(1 << clk->enable_shift);
-       __raw_writel(reg, clk->enable_reg);
-}
-
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, s)       \
-       static struct clk name = {                      \
-               .id             = i,                    \
-               .enable_reg     = CRM_BASE + er,        \
-               .enable_shift   = es,                   \
-               .get_rate       = gr,                   \
-               .set_rate       = sr,                   \
-               .enable         = clk_cgcr_enable,      \
-               .disable        = clk_cgcr_disable,     \
-               .secondary      = s,                    \
-       }
-
-/*
- * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
- * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
- * taken from the Freescale released BSP.
- *
- * bit reg     offset  clock
- *
- * 0   CGCR1   0       AUDMUX
- * 12  CGCR1   12      ESAI
- * 16  CGCR1   16      GPIO1
- * 17  CGCR1   17      GPIO2
- * 18  CGCR1   18      GPIO3
- * 23  CGCR1   23      I2C1
- * 24  CGCR1   24      I2C2
- * 25  CGCR1   25      I2C3
- * 27  CGCR1   27      IOMUXC
- * 28  CGCR1   28      KPP
- * 30  CGCR1   30      OWIRE
- * 36  CGCR2   4       RTIC
- * 51  CGCR2   19      WDOG
- */
-
-DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
-DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
-DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1,         NULL, NULL);
-DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0,  3, get_rate_esdhc1,         NULL,
-               &esdhc1_ahb_clk);
-DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2,         NULL, NULL);
-DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0,  4, get_rate_esdhc2,         NULL,
-               &esdhc2_ahb_clk);
-DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL,      NULL, NULL);
-DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,       NULL, NULL);
-DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,      NULL, NULL);
-DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,      NULL, &lcdc_ahb_clk);
-DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
-DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
-DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
-DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
-DEFINE_CLOCK(pwm1_clk,  0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(pwm2_clk,  0, CCM_CGCR2,  0, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(pwm3_clk,  0, CCM_CGCR2,  1, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(pwm4_clk,  0, CCM_CGCR2,  2, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(kpp_clk,   0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(tsc_clk,   0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(i2c_clk,   0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
-DEFINE_CLOCK(fec_clk,   0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
-DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(lcdc_clk,  0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
-DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
-DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
-DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
-DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2,  6, get_rate_ipg, NULL, &sdma_ahb_clk);
-DEFINE_CLOCK(esdhc1_clk,  0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
-               &esdhc1_per_clk);
-DEFINE_CLOCK(esdhc2_clk,  1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
-               &esdhc2_per_clk);
-DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
-DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
-DEFINE_CLOCK(can1_clk,  0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(can2_clk,  1, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
-DEFINE_CLOCK(iim_clk,    0, CCM_CGCR1, 26, NULL, NULL, NULL);
-
-#define _REGISTER_CLOCK(d, n, c)       \
-       {                               \
-               .dev_id = d,            \
-               .con_id = n,            \
-               .clk = &c,              \
-       },
-
-static struct clk_lookup lookups[] = {
-       /* i.mx25 has the i.mx21 type uart */
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-       _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-       _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
-       _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-       /* i.mx25 has the i.mx35 type cspi */
-       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
-       _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
-       _REGISTER_CLOCK("imx35-cspi.2", NULL, cspi3_clk)
-       _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
-       _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
-       _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
-       _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
-       _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
-       _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
-       _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
-       _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
-       _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
-       _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
-       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx25.0", NULL, esdhc1_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx25.1", NULL, esdhc2_clk)
-       _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
-       _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
-       _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
-       _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
-       /* i.mx25 has the i.mx35 type sdma */
-       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-       _REGISTER_CLOCK(NULL, "iim", iim_clk)
-};
-
-int __init mx25_clocks_init(void)
-{
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-       /* Turn off all clocks except the ones we need to survive, namely:
-        * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
-        * SCC
-        */
-       __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
-       __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
-       __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-       clk_enable(&uart1_clk);
-#endif
-
-       /* Clock source for lcdc and csi is upll */
-       __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
-                       CRM_BASE + 0x64);
-
-       /* Clock source for gpt is ahb_div */
-       __raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
-
-       clk_enable(&iim_clk);
-       imx_print_silicon_rev("i.MX25", mx25_revision());
-       clk_disable(&iim_clk);
-
-       mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
-
-       return 0;
-}

diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
deleted file mode 100644 (file)
index 98e04f5..0000000
--- a/arch/arm/mach-imx/clock-imx27.c
+++ /dev/null
@@ -1,785 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-
-#include <asm/div64.h>
-
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-
-#define IO_ADDR_CCM(off)       (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
-
-/* Register offsets */
-#define CCM_CSCR               IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0             IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1             IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0             IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1             IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL          IO_ADDR_CCM(0x14)
-#define CCM_PCDR0              IO_ADDR_CCM(0x18)
-#define CCM_PCDR1              IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0              IO_ADDR_CCM(0x20)
-#define CCM_PCCR1              IO_ADDR_CCM(0x24)
-#define CCM_CCSR               IO_ADDR_CCM(0x28)
-#define CCM_PMCTL              IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT            IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL            IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_UPDATE_DIS    (1 << 31)
-#define CCM_CSCR_SSI2          (1 << 23)
-#define CCM_CSCR_SSI1          (1 << 22)
-#define CCM_CSCR_VPU           (1 << 21)
-#define CCM_CSCR_MSHC           (1 << 20)
-#define CCM_CSCR_SPLLRES        (1 << 19)
-#define CCM_CSCR_MPLLRES        (1 << 18)
-#define CCM_CSCR_SP             (1 << 17)
-#define CCM_CSCR_MCU            (1 << 16)
-#define CCM_CSCR_OSC26MDIV      (1 << 4)
-#define CCM_CSCR_OSC26M         (1 << 3)
-#define CCM_CSCR_FPM            (1 << 2)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           (1 << 0)
-
-/* i.MX27 TO 2+ */
-#define CCM_CSCR_ARM_SRC        (1 << 15)
-
-#define CCM_SPCTL1_LF           (1 << 15)
-#define CCM_SPCTL1_BRMO         (1 << 6)
-
-static struct clk mpll_main1_clk, mpll_main2_clk;
-
-static int clk_pccr_enable(struct clk *clk)
-{
-       unsigned long reg;
-
-       if (!clk->enable_reg)
-               return 0;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg |= 1 << clk->enable_shift;
-       __raw_writel(reg, clk->enable_reg);
-
-       return 0;
-}
-
-static void clk_pccr_disable(struct clk *clk)
-{
-       unsigned long reg;
-
-       if (!clk->enable_reg)
-               return;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg &= ~(1 << clk->enable_shift);
-       __raw_writel(reg, clk->enable_reg);
-}
-
-static int clk_spll_enable(struct clk *clk)
-{
-       unsigned long reg;
-
-       reg = __raw_readl(CCM_CSCR);
-       reg |= CCM_CSCR_SPEN;
-       __raw_writel(reg, CCM_CSCR);
-
-       while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
-
-       return 0;
-}
-
-static void clk_spll_disable(struct clk *clk)
-{
-       unsigned long reg;
-
-       reg = __raw_readl(CCM_CSCR);
-       reg &= ~CCM_CSCR_SPEN;
-       __raw_writel(reg, CCM_CSCR);
-}
-
-static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
-{
-       int cscr = __raw_readl(CCM_CSCR);
-
-       if (clk->parent == parent)
-               return 0;
-
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-               if (parent == &mpll_main1_clk) {
-                       cscr |= CCM_CSCR_ARM_SRC;
-               } else {
-                       if (parent == &mpll_main2_clk)
-                               cscr &= ~CCM_CSCR_ARM_SRC;
-                       else
-                               return -EINVAL;
-               }
-               __raw_writel(cscr, CCM_CSCR);
-               clk->parent = parent;
-               return 0;
-       }
-       return -ENODEV;
-}
-
-static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
-{
-       int div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (parent_rate % rate)
-               div++;
-
-       if (div > 4)
-               div = 4;
-
-       return parent_rate / div;
-}
-
-static int set_rate_cpu(struct clk *clk, unsigned long rate)
-{
-       unsigned int div;
-       uint32_t reg;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-
-       if (div > 4 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-
-       div--;
-
-       reg = __raw_readl(CCM_CSCR);
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-               reg &= ~(3 << 12);
-               reg |= div << 12;
-               reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
-               __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
-       } else {
-               printk(KERN_ERR "Can't set CPU frequency!\n");
-       }
-
-       return 0;
-}
-
-static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
-{
-       u32 div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (parent_rate % rate)
-               div++;
-
-       if (div > 64)
-               div = 64;
-
-       return parent_rate / div;
-}
-
-static int set_rate_per(struct clk *clk, unsigned long rate)
-{
-       u32 reg;
-       u32 div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (clk->id < 0 || clk->id > 3)
-               return -EINVAL;
-
-       div = parent_rate / rate;
-       if (div > 64 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-       div--;
-
-       reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
-       reg |= div << (clk->id << 3);
-       __raw_writel(reg, CCM_PCDR1);
-
-       return 0;
-}
-
-static unsigned long get_rate_usb(struct clk *clk)
-{
-       unsigned long usb_pdf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
-
-       return parent_rate / (usb_pdf + 1U);
-}
-
-static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
-{
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-               pdf += 4;  /* MX27 TO2+ */
-       else
-               pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
-
-       return 2UL * parent_rate / pdf;
-}
-
-static unsigned long get_rate_ssi1(struct clk *clk)
-{
-       return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
-}
-
-static unsigned long get_rate_ssi2(struct clk *clk)
-{
-       return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
-}
-
-static unsigned long get_rate_nfc(struct clk *clk)
-{
-       unsigned long nfc_pdf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-               nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
-       else
-               nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
-
-       return parent_rate / (nfc_pdf + 1);
-}
-
-static unsigned long get_rate_vpu(struct clk *clk)
-{
-       unsigned long vpu_pdf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-               vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
-               vpu_pdf += 4;
-       } else {
-               vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
-               vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
-       }
-
-       return 2UL * parent_rate / vpu_pdf;
-}
-
-static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
-{
-       return clk->parent->round_rate(clk->parent, rate);
-}
-
-static unsigned long get_rate_parent(struct clk *clk)
-{
-       return clk_get_rate(clk->parent);
-}
-
-static int set_rate_parent(struct clk *clk, unsigned long rate)
-{
-       return clk->parent->set_rate(clk->parent, rate);
-}
-
-/* in Hz */
-static unsigned long external_high_reference = 26000000;
-
-static unsigned long get_rate_high_reference(struct clk *clk)
-{
-       return external_high_reference;
-}
-
-/* in Hz */
-static unsigned long external_low_reference = 32768;
-
-static unsigned long get_rate_low_reference(struct clk *clk)
-{
-       return external_low_reference;
-}
-
-static unsigned long get_rate_fpm(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) * 1024;
-}
-
-static unsigned long get_rate_mpll(struct clk *clk)
-{
-       return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
-                       clk_get_rate(clk->parent));
-}
-
-static unsigned long get_rate_mpll_main(struct clk *clk)
-{
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       /* i.MX27 TO2:
-        * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
-        * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
-        */
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
-               return 2UL * parent_rate / 3UL;
-
-       return parent_rate;
-}
-
-static unsigned long get_rate_spll(struct clk *clk)
-{
-       uint32_t reg;
-       unsigned long rate;
-
-       rate = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(CCM_SPCTL0);
-
-       /* On TO2 we have to write the value back. Otherwise we
-        * read 0 from this register the next time.
-        */
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-               __raw_writel(reg, CCM_SPCTL0);
-
-       return mxc_decode_pll(reg, rate);
-}
-
-static unsigned long get_rate_cpu(struct clk *clk)
-{
-       u32 div;
-       unsigned long rate;
-
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-               div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
-       else
-               div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
-
-       rate = clk_get_rate(clk->parent);
-       return rate / (div + 1);
-}
-
-static unsigned long get_rate_ahb(struct clk *clk)
-{
-       unsigned long rate, bclk_pdf;
-
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-               bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
-       else
-               bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
-
-       rate = clk_get_rate(clk->parent);
-       return rate / (bclk_pdf + 1);
-}
-
-static unsigned long get_rate_ipg(struct clk *clk)
-{
-       unsigned long rate, ipg_pdf;
-
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
-               return clk_get_rate(clk->parent);
-       else
-               ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
-
-       rate = clk_get_rate(clk->parent);
-       return rate / (ipg_pdf + 1);
-}
-
-static unsigned long get_rate_per(struct clk *clk)
-{
-       unsigned long perclk_pdf, parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (clk->id < 0 || clk->id > 3)
-               return 0;
-
-       perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
-
-       return parent_rate / (perclk_pdf + 1);
-}
-
-/*
- * the high frequency external clock reference
- * Default case is 26MHz. Could be changed at runtime
- * with a call to change_external_high_reference()
- */
-static struct clk ckih_clk = {
-       .get_rate       = get_rate_high_reference,
-};
-
-static struct clk mpll_clk = {
-       .parent         = &ckih_clk,
-       .get_rate       = get_rate_mpll,
-};
-
-/* For i.MX27 TO2, it is the MPLL path 1 of ARM core
- * It provides the clock source whose rate is same as MPLL
- */
-static struct clk mpll_main1_clk = {
-       .id             = 0,
-       .parent         = &mpll_clk,
-       .get_rate       = get_rate_mpll_main,
-};
-
-/* For i.MX27 TO2, it is the MPLL path 2 of ARM core
- * It provides the clock source whose rate is same MPLL * 2 / 3
- */
-static struct clk mpll_main2_clk = {
-       .id             = 1,
-       .parent         = &mpll_clk,
-       .get_rate       = get_rate_mpll_main,
-};
-
-static struct clk ahb_clk = {
-       .parent         = &mpll_main2_clk,
-       .get_rate       = get_rate_ahb,
-};
-
-static struct clk ipg_clk = {
-       .parent         = &ahb_clk,
-       .get_rate       = get_rate_ipg,
-};
-
-static struct clk cpu_clk = {
-       .parent = &mpll_main2_clk,
-       .set_parent = clk_cpu_set_parent,
-       .round_rate = round_rate_cpu,
-       .get_rate = get_rate_cpu,
-       .set_rate = set_rate_cpu,
-};
-
-static struct clk spll_clk = {
-       .parent = &ckih_clk,
-       .get_rate = get_rate_spll,
-       .enable = clk_spll_enable,
-       .disable = clk_spll_disable,
-};
-
-/*
- * the low frequency external clock reference
- * Default case is 32.768kHz.
- */
-static struct clk ckil_clk = {
-       .get_rate = get_rate_low_reference,
-};
-
-/* Output of frequency pre multiplier */
-static struct clk fpm_clk = {
-       .parent = &ckil_clk,
-       .get_rate = get_rate_fpm,
-};
-
-#define PCCR0 CCM_PCCR0
-#define PCCR1 CCM_PCCR1
-
-#define DEFINE_CLOCK(name, i, er, es, gr, s, p)                \
-       static struct clk name = {                      \
-               .id             = i,                    \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .get_rate       = gr,                   \
-               .enable         = clk_pccr_enable,      \
-               .disable        = clk_pccr_disable,     \
-               .secondary      = s,                    \
-               .parent         = p,                    \
-       }
-
-#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)      \
-       static struct clk name = {                              \
-               .id             = i,                            \
-               .enable_reg     = er,                           \
-               .enable_shift   = es,                           \
-               .get_rate       = get_rate_##getsetround,       \
-               .set_rate       = set_rate_##getsetround,       \
-               .round_rate     = round_rate_##getsetround,     \
-               .enable         = clk_pccr_enable,              \
-               .disable        = clk_pccr_disable,             \
-               .secondary      = s,                            \
-               .parent         = p,                            \
-       }
-
-/* Forward declaration to keep the following list in order */
-static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
-                 dma_clk1, lcdc_clk2, vpu_clk1;
-
-/* All clocks we can gate through PCCRx in the order of PCCRx bits */
-DEFINE_CLOCK(ssi2_clk1,    1, PCCR0,  0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ssi1_clk1,    0, PCCR0,  1, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(slcdc_clk,    0, PCCR0,  2, NULL, &slcdc_clk1, &ahb_clk);
-DEFINE_CLOCK(sdhc3_clk1,   0, PCCR0,  3, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdhc2_clk1,   0, PCCR0,  4, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdhc1_clk1,   0, PCCR0,  5, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(scc_clk,      0, PCCR0,  6, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sahara2_clk,  0, PCCR0,  7, NULL, &sahara2_clk1, &ahb_clk);
-DEFINE_CLOCK(rtic_clk,     0, PCCR0,  8, NULL, &rtic_clk1, &ahb_clk);
-DEFINE_CLOCK(rtc_clk,      0, PCCR0,  9, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(pwm_clk1,     0, PCCR0, 11, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(owire_clk,    0, PCCR0, 12, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(mstick_clk1,  0, PCCR0, 13, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(lcdc_clk1,    0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
-DEFINE_CLOCK(kpp_clk,      0, PCCR0, 15, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(iim_clk,      0, PCCR0, 16, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(i2c2_clk,     1, PCCR0, 17, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(i2c1_clk,     0, PCCR0, 18, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt6_clk1,    0, PCCR0, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt5_clk1,    0, PCCR0, 20, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt4_clk1,    0, PCCR0, 21, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt3_clk1,    0, PCCR0, 22, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt2_clk1,    0, PCCR0, 23, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt1_clk1,    0, PCCR0, 24, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpio_clk,     0, PCCR0, 25, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(fec_clk,      0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
-DEFINE_CLOCK(emma_clk,     0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
-DEFINE_CLOCK(dma_clk,      0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
-DEFINE_CLOCK(cspi13_clk1,  0, PCCR0, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi2_clk1,   0, PCCR0, 30, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi1_clk1,   0, PCCR0, 31, NULL, NULL, &ipg_clk);
-
-DEFINE_CLOCK(mstick_clk,   0, PCCR1,  2, NULL, &mstick_clk1, &ipg_clk);
-DEFINE_CLOCK(nfc_clk,      0, PCCR1,  3, get_rate_nfc, NULL, &cpu_clk);
-DEFINE_CLOCK(ssi2_clk,     1, PCCR1,  4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
-DEFINE_CLOCK(ssi1_clk,     0, PCCR1,  5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
-DEFINE_CLOCK(vpu_clk,      0, PCCR1,  6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
-DEFINE_CLOCK1(per4_clk,    3, PCCR1,  7, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per3_clk,    2, PCCR1,  8, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per2_clk,    1, PCCR1,  9, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per1_clk,    0, PCCR1, 10, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK(usb_clk1,     0, PCCR1, 11, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(slcdc_clk1,   0, PCCR1, 12, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(rtic_clk1,    0, PCCR1, 14, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(lcdc_clk2,    0, PCCR1, 15, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(vpu_clk1,     0, PCCR1, 16, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(fec_clk1,     0, PCCR1, 17, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(emma_clk1,    0, PCCR1, 18, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(emi_clk,      0, PCCR1, 19, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(dma_clk1,     0, PCCR1, 20, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(csi_clk1,     0, PCCR1, 21, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(brom_clk,     0, PCCR1, 22, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(pata_clk,      0, PCCR1, 23, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(wdog_clk,     0, PCCR1, 24, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(usb_clk,      0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
-DEFINE_CLOCK(uart6_clk1,   0, PCCR1, 26, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart5_clk1,   0, PCCR1, 27, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart4_clk1,   0, PCCR1, 28, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart3_clk1,   0, PCCR1, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart2_clk1,   0, PCCR1, 30, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart1_clk1,   0, PCCR1, 31, NULL, NULL, &ipg_clk);
-
-/* Clocks we cannot directly gate, but drivers need their rates */
-DEFINE_CLOCK(cspi1_clk,    0, NULL,   0, NULL, &cspi1_clk1, &per2_clk);
-DEFINE_CLOCK(cspi2_clk,    1, NULL,   0, NULL, &cspi2_clk1, &per2_clk);
-DEFINE_CLOCK(cspi3_clk,    2, NULL,   0, NULL, &cspi13_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc1_clk,    0, NULL,   0, NULL, &sdhc1_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc2_clk,    1, NULL,   0, NULL, &sdhc2_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc3_clk,    2, NULL,   0, NULL, &sdhc3_clk1, &per2_clk);
-DEFINE_CLOCK(pwm_clk,      0, NULL,   0, NULL, &pwm_clk1, &per1_clk);
-DEFINE_CLOCK(gpt1_clk,     0, NULL,   0, NULL, &gpt1_clk1, &per1_clk);
-DEFINE_CLOCK(gpt2_clk,     1, NULL,   0, NULL, &gpt2_clk1, &per1_clk);
-DEFINE_CLOCK(gpt3_clk,     2, NULL,   0, NULL, &gpt3_clk1, &per1_clk);
-DEFINE_CLOCK(gpt4_clk,     3, NULL,   0, NULL, &gpt4_clk1, &per1_clk);
-DEFINE_CLOCK(gpt5_clk,     4, NULL,   0, NULL, &gpt5_clk1, &per1_clk);
-DEFINE_CLOCK(gpt6_clk,     5, NULL,   0, NULL, &gpt6_clk1, &per1_clk);
-DEFINE_CLOCK(uart1_clk,    0, NULL,   0, NULL, &uart1_clk1, &per1_clk);
-DEFINE_CLOCK(uart2_clk,    1, NULL,   0, NULL, &uart2_clk1, &per1_clk);
-DEFINE_CLOCK(uart3_clk,    2, NULL,   0, NULL, &uart3_clk1, &per1_clk);
-DEFINE_CLOCK(uart4_clk,    3, NULL,   0, NULL, &uart4_clk1, &per1_clk);
-DEFINE_CLOCK(uart5_clk,    4, NULL,   0, NULL, &uart5_clk1, &per1_clk);
-DEFINE_CLOCK(uart6_clk,    5, NULL,   0, NULL, &uart6_clk1, &per1_clk);
-DEFINE_CLOCK1(lcdc_clk,    0, NULL,   0, parent, &lcdc_clk1, &per3_clk);
-DEFINE_CLOCK1(csi_clk,     0, NULL,   0, parent, &csi_clk1, &per4_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c, \
-       },
-
-static struct clk_lookup lookups[] = {
-       /* i.mx27 has the i.mx21 type uart */
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-       _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-       _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-       _REGISTER_CLOCK("imx21-uart.5", NULL, uart6_clk)
-       _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
-       _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
-       _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
-       _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
-       _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
-       _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
-       _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
-       _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
-       _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
-       _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
-       _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
-       _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
-       _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-       _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
-       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-       _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-       _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
-       _REGISTER_CLOCK(NULL, "dma", dma_clk)
-       _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
-       _REGISTER_CLOCK(NULL, "brom", brom_clk)
-       _REGISTER_CLOCK(NULL, "emma", emma_clk)
-       _REGISTER_CLOCK("m2m-emmaprp.0", NULL, emma_clk)
-       _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
-       _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
-       _REGISTER_CLOCK(NULL, "emi", emi_clk)
-       _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
-       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-       _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
-       _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-       _REGISTER_CLOCK(NULL, "iim", iim_clk)
-       _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
-       _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
-       _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-       _REGISTER_CLOCK(NULL, "scc", scc_clk)
-};
-
-/* Adjust the clock path for TO2 and later */
-static void __init to2_adjust_clocks(void)
-{
-       unsigned long cscr = __raw_readl(CCM_CSCR);
-
-       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
-               if (cscr & CCM_CSCR_ARM_SRC)
-                       cpu_clk.parent = &mpll_main1_clk;
-
-               if (!(cscr & CCM_CSCR_SSI2))
-                       ssi1_clk.parent = &spll_clk;
-
-               if (!(cscr & CCM_CSCR_SSI1))
-                       ssi1_clk.parent = &spll_clk;
-
-               if (!(cscr & CCM_CSCR_VPU))
-                       vpu_clk.parent = &spll_clk;
-       } else {
-               cpu_clk.parent = &mpll_clk;
-               cpu_clk.set_parent = NULL;
-               cpu_clk.round_rate = NULL;
-               cpu_clk.set_rate = NULL;
-               ahb_clk.parent = &mpll_clk;
-
-               per1_clk.parent = &mpll_clk;
-               per2_clk.parent = &mpll_clk;
-               per3_clk.parent = &mpll_clk;
-               per4_clk.parent = &mpll_clk;
-
-               ssi1_clk.parent = &mpll_clk;
-               ssi2_clk.parent = &mpll_clk;
-
-               vpu_clk.parent = &mpll_clk;
-       }
-}
-
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
-int __init mx27_clocks_init(unsigned long fref)
-{
-       u32 cscr = __raw_readl(CCM_CSCR);
-
-       external_high_reference = fref;
-
-       /* detect clock reference for both system PLLs */
-       if (cscr & CCM_CSCR_MCU)
-               mpll_clk.parent = &ckih_clk;
-       else
-               mpll_clk.parent = &fpm_clk;
-
-       if (cscr & CCM_CSCR_SP)
-               spll_clk.parent = &ckih_clk;
-       else
-               spll_clk.parent = &fpm_clk;
-
-       to2_adjust_clocks();
-
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-       /* Turn off all clocks we do not need */
-       __raw_writel(0, CCM_PCCR0);
-       __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
-
-       spll_clk.disable(&spll_clk);
-
-       /* enable basic clocks */
-       clk_enable(&per1_clk);
-       clk_enable(&gpio_clk);
-       clk_enable(&emi_clk);
-       clk_enable(&iim_clk);
-       imx_print_silicon_rev("i.MX27", mx27_revision());
-       clk_disable(&iim_clk);
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-       clk_enable(&uart1_clk);
-#endif
-
-       mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
-                       MX27_INT_GPT1);
-
-       return 0;
-}
-
-#ifdef CONFIG_OF
-int __init mx27_clocks_init_dt(void)
-{
-       struct device_node *np;
-       u32 fref = 26000000; /* default */
-
-       for_each_compatible_node(np, NULL, "fixed-clock") {
-               if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
-                       continue;
-
-               if (!of_property_read_u32(np, "clock-frequency", &fref))
-                       break;
-       }
-
-       return mx27_clocks_init(fref);
-}
-#endif

diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
deleted file mode 100644 (file)
index 3a943cd..0000000
--- a/arch/arm/mach-imx/clock-imx31.c
+++ /dev/null
@@ -1,630 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <asm/div64.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/mx31.h>
-#include <mach/common.h>
-
-#include "crmregs-imx3.h"
-
-#define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
-
-static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
-{
-       u32 min_pre, temp_pre, old_err, err;
-
-       if (div >= 512) {
-               *pre = 8;
-               *post = 64;
-       } else if (div >= 64) {
-               min_pre = (div - 1) / 64 + 1;
-               old_err = 8;
-               for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
-                       err = div % temp_pre;
-                       if (err == 0) {
-                               *pre = temp_pre;
-                               break;
-                       }
-                       err = temp_pre - err;
-                       if (err < old_err) {
-                               old_err = err;
-                               *pre = temp_pre;
-                       }
-               }
-               *post = (div + *pre - 1) / *pre;
-       } else if (div <= 8) {
-               *pre = div;
-               *post = 1;
-       } else {
-               *pre = 1;
-               *post = div;
-       }
-}
-
-static struct clk mcu_pll_clk;
-static struct clk serial_pll_clk;
-static struct clk ipg_clk;
-static struct clk ckih_clk;
-
-static int cgr_enable(struct clk *clk)
-{
-       u32 reg;
-
-       if (!clk->enable_reg)
-               return 0;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg |= 3 << clk->enable_shift;
-       __raw_writel(reg, clk->enable_reg);
-
-       return 0;
-}
-
-static void cgr_disable(struct clk *clk)
-{
-       u32 reg;
-
-       if (!clk->enable_reg)
-               return;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg &= ~(3 << clk->enable_shift);
-
-       /* special case for EMI clock */
-       if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
-               reg |= (1 << clk->enable_shift);
-
-       __raw_writel(reg, clk->enable_reg);
-}
-
-static unsigned long pll_ref_get_rate(void)
-{
-       unsigned long ccmr;
-       unsigned int prcs;
-
-       ccmr = __raw_readl(MXC_CCM_CCMR);
-       prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
-       if (prcs == 0x1)
-               return CKIL_CLK_FREQ * 1024;
-       else
-               return clk_get_rate(&ckih_clk);
-}
-
-static unsigned long usb_pll_get_rate(struct clk *clk)
-{
-       unsigned long reg;
-
-       reg = __raw_readl(MXC_CCM_UPCTL);
-
-       return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static unsigned long serial_pll_get_rate(struct clk *clk)
-{
-       unsigned long reg;
-
-       reg = __raw_readl(MXC_CCM_SRPCTL);
-
-       return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static unsigned long mcu_pll_get_rate(struct clk *clk)
-{
-       unsigned long reg, ccmr;
-
-       ccmr = __raw_readl(MXC_CCM_CCMR);
-
-       if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
-               return clk_get_rate(&ckih_clk);
-
-       reg = __raw_readl(MXC_CCM_MPCTL);
-
-       return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static int usb_pll_enable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CCMR);
-       reg |= MXC_CCM_CCMR_UPE;
-       __raw_writel(reg, MXC_CCM_CCMR);
-
-       /* No lock bit on MX31, so using max time from spec */
-       udelay(80);
-
-       return 0;
-}
-
-static void usb_pll_disable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CCMR);
-       reg &= ~MXC_CCM_CCMR_UPE;
-       __raw_writel(reg, MXC_CCM_CCMR);
-}
-
-static int serial_pll_enable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CCMR);
-       reg |= MXC_CCM_CCMR_SPE;
-       __raw_writel(reg, MXC_CCM_CCMR);
-
-       /* No lock bit on MX31, so using max time from spec */
-       udelay(80);
-
-       return 0;
-}
-
-static void serial_pll_disable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CCMR);
-       reg &= ~MXC_CCM_CCMR_SPE;
-       __raw_writel(reg, MXC_CCM_CCMR);
-}
-
-#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
-#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
-#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
-
-static unsigned long mcu_main_get_rate(struct clk *clk)
-{
-       u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
-
-       if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
-               return clk_get_rate(&serial_pll_clk);
-       else
-               return clk_get_rate(&mcu_pll_clk);
-}
-
-static unsigned long ahb_get_rate(struct clk *clk)
-{
-       unsigned long max_pdf;
-
-       max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
-                      MXC_CCM_PDR0_MAX_PODF_OFFSET);
-       return clk_get_rate(clk->parent) / (max_pdf + 1);
-}
-
-static unsigned long ipg_get_rate(struct clk *clk)
-{
-       unsigned long ipg_pdf;
-
-       ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
-                      MXC_CCM_PDR0_IPG_PODF_OFFSET);
-       return clk_get_rate(clk->parent) / (ipg_pdf + 1);
-}
-
-static unsigned long nfc_get_rate(struct clk *clk)
-{
-       unsigned long nfc_pdf;
-
-       nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
-                      MXC_CCM_PDR0_NFC_PODF_OFFSET);
-       return clk_get_rate(clk->parent) / (nfc_pdf + 1);
-}
-
-static unsigned long hsp_get_rate(struct clk *clk)
-{
-       unsigned long hsp_pdf;
-
-       hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
-                      MXC_CCM_PDR0_HSP_PODF_OFFSET);
-       return clk_get_rate(clk->parent) / (hsp_pdf + 1);
-}
-
-static unsigned long usb_get_rate(struct clk *clk)
-{
-       unsigned long usb_pdf, usb_prepdf;
-
-       usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
-                      MXC_CCM_PDR1_USB_PODF_OFFSET);
-       usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
-                         MXC_CCM_PDR1_USB_PRDF_OFFSET);
-       return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
-}
-
-static unsigned long csi_get_rate(struct clk *clk)
-{
-       u32 reg, pre, post;
-
-       reg = __raw_readl(MXC_CCM_PDR0);
-       pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
-           MXC_CCM_PDR0_CSI_PRDF_OFFSET;
-       pre++;
-       post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
-           MXC_CCM_PDR0_CSI_PODF_OFFSET;
-       post++;
-       return clk_get_rate(clk->parent) / (pre * post);
-}
-
-static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
-{
-       u32 pre, post, parent = clk_get_rate(clk->parent);
-       u32 div = parent / rate;
-
-       if (parent % rate)
-               div++;
-
-       __calc_pre_post_dividers(div, &pre, &post);
-
-       return parent / (pre * post);
-}
-
-static int csi_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
-
-       div = parent / rate;
-
-       if ((parent / div) != rate)
-               return -EINVAL;
-
-       __calc_pre_post_dividers(div, &pre, &post);
-
-       /* Set CSI clock divider */
-       reg = __raw_readl(MXC_CCM_PDR0) &
-           ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
-       reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
-       reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
-       __raw_writel(reg, MXC_CCM_PDR0);
-
-       return 0;
-}
-
-static unsigned long ssi1_get_rate(struct clk *clk)
-{
-       unsigned long ssi1_pdf, ssi1_prepdf;
-
-       ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
-                       MXC_CCM_PDR1_SSI1_PODF_OFFSET);
-       ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
-                          MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
-       return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
-}
-
-static unsigned long ssi2_get_rate(struct clk *clk)
-{
-       unsigned long ssi2_pdf, ssi2_prepdf;
-
-       ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
-                       MXC_CCM_PDR1_SSI2_PODF_OFFSET);
-       ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
-                          MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
-       return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
-}
-
-static unsigned long firi_get_rate(struct clk *clk)
-{
-       unsigned long firi_pdf, firi_prepdf;
-
-       firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
-                       MXC_CCM_PDR1_FIRI_PODF_OFFSET);
-       firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
-                          MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
-       return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
-}
-
-static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
-{
-       u32 pre, post;
-       u32 parent = clk_get_rate(clk->parent);
-       u32 div = parent / rate;
-
-       if (parent % rate)
-               div++;
-
-       __calc_pre_post_dividers(div, &pre, &post);
-
-       return parent / (pre * post);
-
-}
-
-static int firi_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
-
-       div = parent / rate;
-
-       if ((parent / div) != rate)
-               return -EINVAL;
-
-       __calc_pre_post_dividers(div, &pre, &post);
-
-       /* Set FIRI clock divider */
-       reg = __raw_readl(MXC_CCM_PDR1) &
-           ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
-       reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
-       reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
-       __raw_writel(reg, MXC_CCM_PDR1);
-
-       return 0;
-}
-
-static unsigned long mbx_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / 2;
-}
-
-static unsigned long mstick1_get_rate(struct clk *clk)
-{
-       unsigned long msti_pdf;
-
-       msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
-                       MXC_CCM_PDR2_MST1_PDF_OFFSET);
-       return clk_get_rate(clk->parent) / (msti_pdf + 1);
-}
-
-static unsigned long mstick2_get_rate(struct clk *clk)
-{
-       unsigned long msti_pdf;
-
-       msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
-                       MXC_CCM_PDR2_MST2_PDF_OFFSET);
-       return clk_get_rate(clk->parent) / (msti_pdf + 1);
-}
-
-static unsigned long ckih_rate;
-
-static unsigned long clk_ckih_get_rate(struct clk *clk)
-{
-       return ckih_rate;
-}
-
-static unsigned long clk_ckil_get_rate(struct clk *clk)
-{
-       return CKIL_CLK_FREQ;
-}
-
-static struct clk ckih_clk = {
-       .get_rate = clk_ckih_get_rate,
-};
-
-static struct clk mcu_pll_clk = {
-       .parent = &ckih_clk,
-       .get_rate = mcu_pll_get_rate,
-};
-
-static struct clk mcu_main_clk = {
-       .parent = &mcu_pll_clk,
-       .get_rate = mcu_main_get_rate,
-};
-
-static struct clk serial_pll_clk = {
-       .parent = &ckih_clk,
-       .get_rate = serial_pll_get_rate,
-       .enable = serial_pll_enable,
-       .disable = serial_pll_disable,
-};
-
-static struct clk usb_pll_clk = {
-       .parent = &ckih_clk,
-       .get_rate = usb_pll_get_rate,
-       .enable = usb_pll_enable,
-       .disable = usb_pll_disable,
-};
-
-static struct clk ahb_clk = {
-       .parent = &mcu_main_clk,
-       .get_rate = ahb_get_rate,
-};
-
-#define DEFINE_CLOCK(name, i, er, es, gr, s, p)                \
-       static struct clk name = {                      \
-               .id             = i,                    \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .get_rate       = gr,                   \
-               .enable         = cgr_enable,           \
-               .disable        = cgr_disable,          \
-               .secondary      = s,                    \
-               .parent         = p,                    \
-       }
-
-#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)      \
-       static struct clk name = {                              \
-               .id             = i,                            \
-               .enable_reg     = er,                           \
-               .enable_shift   = es,                           \
-               .get_rate       = getsetround##_get_rate,       \
-               .set_rate       = getsetround##_set_rate,       \
-               .round_rate     = getsetround##_round_rate,     \
-               .enable         = cgr_enable,                   \
-               .disable        = cgr_disable,                  \
-               .secondary      = s,                            \
-               .parent         = p,                            \
-       }
-
-DEFINE_CLOCK(perclk_clk,  0, NULL,          0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
-
-DEFINE_CLOCK(sdhc1_clk,   0, MXC_CCM_CGR0,  0, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(sdhc2_clk,   1, MXC_CCM_CGR0,  2, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(gpt_clk,     0, MXC_CCM_CGR0,  4, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(epit1_clk,   0, MXC_CCM_CGR0,  6, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(epit2_clk,   1, MXC_CCM_CGR0,  8, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(iim_clk,     0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(pata_clk,     0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdma_clk1,   0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(cspi3_clk,   2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(rng_clk,     0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart1_clk,   0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart2_clk,   1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(ssi1_clk,    0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
-DEFINE_CLOCK(i2c1_clk,    0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(i2c2_clk,    1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(i2c3_clk,    2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
-
-DEFINE_CLOCK(mpeg4_clk,   0, MXC_CCM_CGR1,  0, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1,  2, mstick1_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1,  4, mstick2_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK1(csi_clk,    0, MXC_CCM_CGR1,  6, csi, NULL, &serial_pll_clk);
-DEFINE_CLOCK(rtc_clk,     0, MXC_CCM_CGR1,  8, NULL, NULL, &ckil_clk);
-DEFINE_CLOCK(wdog_clk,    0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(pwm_clk,     0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(usb_clk2,    0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(kpp_clk,     0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ipu_clk,     0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
-DEFINE_CLOCK(uart3_clk,   2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart4_clk,   3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart5_clk,   4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(owire_clk,   0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
-
-DEFINE_CLOCK(ssi2_clk,    1, MXC_CCM_CGR2,  0, ssi2_get_rate, NULL, &serial_pll_clk);
-DEFINE_CLOCK(cspi1_clk,   0, MXC_CCM_CGR2,  2, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi2_clk,   1, MXC_CCM_CGR2,  4, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(mbx_clk,     0, MXC_CCM_CGR2,  6, mbx_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(emi_clk,     0, MXC_CCM_CGR2,  8, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(rtic_clk,    0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK1(firi_clk,   0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
-
-DEFINE_CLOCK(sdma_clk2,   0, NULL,          0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c, \
-       },
-
-static struct clk_lookup lookups[] = {
-       _REGISTER_CLOCK(NULL, "emi", emi_clk)
-       _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
-       _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
-       _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
-       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-       _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
-       _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-       _REGISTER_CLOCK(NULL, "epit", epit1_clk)
-       _REGISTER_CLOCK(NULL, "epit", epit2_clk)
-       _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-       _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
-       _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
-       _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
-       _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
-       /* i.mx31 has the i.mx21 type uart */
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-       _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-       _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-       _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
-       _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
-       _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
-       _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
-       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-       _REGISTER_CLOCK(NULL, "firi", firi_clk)
-       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-       _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
-       _REGISTER_CLOCK(NULL, "rng", rng_clk)
-       _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1)
-       _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
-       _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
-       _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
-       _REGISTER_CLOCK(NULL, "scc", scc_clk)
-       _REGISTER_CLOCK(NULL, "iim", iim_clk)
-       _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
-       _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
-};
-
-int __init mx31_clocks_init(unsigned long fref)
-{
-       u32 reg;
-
-       ckih_rate = fref;
-
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-       /* change the csi_clk parent if necessary */
-       reg = __raw_readl(MXC_CCM_CCMR);
-       if (!(reg & MXC_CCM_CCMR_CSCS))
-               if (clk_set_parent(&csi_clk, &usb_pll_clk))
-                       pr_err("%s: error changing csi_clk parent\n", __func__);
-
-
-       /* Turn off all possible clocks */
-       __raw_writel((3 << 4), MXC_CCM_CGR0);
-       __raw_writel(0, MXC_CCM_CGR1);
-       __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
-                    1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
-                                          MX32, but still required to be set */
-                    MXC_CCM_CGR2);
-
-       /*
-        * Before turning off usb_pll make sure ipg_per_clk is generated
-        * by ipg_clk and not usb_pll.
-        */
-       __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
-
-       usb_pll_disable(&usb_pll_clk);
-
-       pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
-
-       clk_enable(&gpt_clk);
-       clk_enable(&emi_clk);
-       clk_enable(&iim_clk);
-       mx31_revision();
-       clk_disable(&iim_clk);
-
-       clk_enable(&serial_pll_clk);
-
-       if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
-               reg = __raw_readl(MXC_CCM_PMCR1);
-               /* No PLL restart on DVFS switch; enable auto EMI handshake */
-               reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
-               __raw_writel(reg, MXC_CCM_PMCR1);
-       }
-
-       mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
-                       MX31_INT_GPT);
-
-       return 0;
-}

diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
deleted file mode 100644 (file)
index e56c1a8..0000000
--- a/arch/arm/mach-imx/clock-imx35.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/*
- * Copyright (C) 2009 by Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#include "crmregs-imx3.h"
-
-#ifdef HAVE_SET_RATE_SUPPORT
-static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
-{
-       u32 min_pre, temp_pre, old_err, err;
-
-       min_pre = (div - 1) / maxpost + 1;
-       old_err = 8;
-
-       for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
-               if (div > (temp_pre * maxpost))
-                       break;
-
-               if (div < (temp_pre * temp_pre))
-                       continue;
-
-               err = div % temp_pre;
-
-               if (err == 0) {
-                       *pre = temp_pre;
-                       break;
-               }
-
-               err = temp_pre - err;
-
-               if (err < old_err) {
-                       old_err = err;
-                       *pre = temp_pre;
-               }
-       }
-
-       *post = (div + *pre - 1) / *pre;
-}
-
-/* get the best values for a 3-bit divider combined with a 6-bit divider */
-static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
-{
-       if (div >= 512) {
-               *pre = 8;
-               *post = 64;
-       } else if (div >= 64) {
-               calc_dividers(div, pre, post, 64);
-       } else if (div <= 8) {
-               *pre = div;
-               *post = 1;
-       } else {
-               *pre = 1;
-               *post = div;
-       }
-}
-
-/* get the best values for two cascaded 3-bit dividers */
-static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
-{
-       if (div >= 64) {
-               *pre = *post = 8;
-       } else if (div > 8) {
-               calc_dividers(div, pre, post, 8);
-       } else {
-               *pre = 1;
-               *post = div;
-       }
-}
-#endif
-
-static unsigned long get_rate_mpll(void)
-{
-       ulong mpctl = __raw_readl(MX35_CCM_MPCTL);
-
-       return mxc_decode_pll(mpctl, 24000000);
-}
-
-static unsigned long get_rate_ppll(void)
-{
-       ulong ppctl = __raw_readl(MX35_CCM_PPCTL);
-
-       return mxc_decode_pll(ppctl, 24000000);
-}
-
-struct arm_ahb_div {
-       unsigned char arm, ahb, sel;
-};
-
-static struct arm_ahb_div clk_consumer[] = {
-       { .arm = 1, .ahb = 4, .sel = 0},
-       { .arm = 1, .ahb = 3, .sel = 1},
-       { .arm = 2, .ahb = 2, .sel = 0},
-       { .arm = 0, .ahb = 0, .sel = 0},
-       { .arm = 0, .ahb = 0, .sel = 0},
-       { .arm = 0, .ahb = 0, .sel = 0},
-       { .arm = 4, .ahb = 1, .sel = 0},
-       { .arm = 1, .ahb = 5, .sel = 0},
-       { .arm = 1, .ahb = 8, .sel = 0},
-       { .arm = 1, .ahb = 6, .sel = 1},
-       { .arm = 2, .ahb = 4, .sel = 0},
-       { .arm = 0, .ahb = 0, .sel = 0},
-       { .arm = 0, .ahb = 0, .sel = 0},
-       { .arm = 0, .ahb = 0, .sel = 0},
-       { .arm = 4, .ahb = 2, .sel = 0},
-       { .arm = 0, .ahb = 0, .sel = 0},
-};
-
-static unsigned long get_rate_arm(void)
-{
-       unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
-       struct arm_ahb_div *aad;
-       unsigned long fref = get_rate_mpll();
-
-       aad = &clk_consumer[(pdr0 >> 16) & 0xf];
-       if (aad->sel)
-               fref = fref * 3 / 4;
-
-       return fref / aad->arm;
-}
-
-static unsigned long get_rate_ahb(struct clk *clk)
-{
-       unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
-       struct arm_ahb_div *aad;
-       unsigned long fref = get_rate_arm();
-
-       aad = &clk_consumer[(pdr0 >> 16) & 0xf];
-
-       return fref / aad->ahb;
-}
-
-static unsigned long get_rate_ipg(struct clk *clk)
-{
-       return get_rate_ahb(NULL) >> 1;
-}
-
-static unsigned long get_rate_uart(struct clk *clk)
-{
-       unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
-       unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
-       unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
-
-       if (pdr3 & (1 << 14))
-               return get_rate_arm() / div;
-       else
-               return get_rate_ppll() / div;
-}
-
-static unsigned long get_rate_sdhc(struct clk *clk)
-{
-       unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
-       unsigned long div, rate;
-
-       if (pdr3 & (1 << 6))
-               rate = get_rate_arm();
-       else
-               rate = get_rate_ppll();
-
-       switch (clk->id) {
-       default:
-       case 0:
-               div = pdr3 & 0x3f;
-               break;
-       case 1:
-               div = (pdr3 >> 8) & 0x3f;
-               break;
-       case 2:
-               div = (pdr3 >> 16) & 0x3f;
-               break;
-       }
-
-       return rate / (div + 1);
-}
-
-static unsigned long get_rate_mshc(struct clk *clk)
-{
-       unsigned long pdr1 = __raw_readl(MXC_CCM_PDR1);
-       unsigned long div1, div2, rate;
-
-       if (pdr1 & (1 << 7))
-               rate = get_rate_arm();
-       else
-               rate = get_rate_ppll();
-
-       div1 = (pdr1 >> 29) & 0x7;
-       div2 = (pdr1 >> 22) & 0x3f;
-
-       return rate / ((div1 + 1) * (div2 + 1));
-}
-
-static unsigned long get_rate_ssi(struct clk *clk)
-{
-       unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
-       unsigned long div1, div2, rate;
-
-       if (pdr2 & (1 << 6))
-               rate = get_rate_arm();
-       else
-               rate = get_rate_ppll();
-
-       switch (clk->id) {
-       default:
-       case 0:
-               div1 = pdr2 & 0x3f;
-               div2 = (pdr2 >> 24) & 0x7;
-               break;
-       case 1:
-               div1 = (pdr2 >> 8) & 0x3f;
-               div2 = (pdr2 >> 27) & 0x7;
-               break;
-       }
-
-       return rate / ((div1 + 1) * (div2 + 1));
-}
-
-static unsigned long get_rate_csi(struct clk *clk)
-{
-       unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
-       unsigned long rate;
-
-       if (pdr2 & (1 << 7))
-               rate = get_rate_arm();
-       else
-               rate = get_rate_ppll();
-
-       return rate / (((pdr2 >> 16) & 0x3f) + 1);
-}
-
-static unsigned long get_rate_otg(struct clk *clk)
-{
-       unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
-       unsigned long rate;
-
-       if (pdr4 & (1 << 9))
-               rate = get_rate_arm();
-       else
-               rate = get_rate_ppll();
-
-       return rate / (((pdr4 >> 22) & 0x3f) + 1);
-}
-
-static unsigned long get_rate_ipg_per(struct clk *clk)
-{
-       unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
-       unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
-       unsigned long div;
-
-       if (pdr0 & (1 << 26)) {
-               div = (pdr4 >> 16) & 0x3f;
-               return get_rate_arm() / (div + 1);
-       } else {
-               div = (pdr0 >> 12) & 0x7;
-               return get_rate_ahb(NULL) / (div + 1);
-       }
-}
-
-static unsigned long get_rate_hsp(struct clk *clk)
-{
-       unsigned long hsp_podf = (__raw_readl(MXC_CCM_PDR0) >> 20) & 0x03;
-       unsigned long fref = get_rate_mpll();
-
-       if (fref > 400 * 1000 * 1000) {
-               switch (hsp_podf) {
-               case 0:
-                       return fref >> 2;
-               case 1:
-                       return fref >> 3;
-               case 2:
-                       return fref / 3;
-               }
-       } else {
-               switch (hsp_podf) {
-               case 0:
-               case 2:
-                       return fref / 3;
-               case 1:
-                       return fref / 6;
-               }
-       }
-
-       return 0;
-}
-
-static int clk_cgr_enable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg |= 3 << clk->enable_shift;
-       __raw_writel(reg, clk->enable_reg);
-
-       return 0;
-}
-
-static void clk_cgr_disable(struct clk *clk)
-{
-       u32 reg;
-
-       reg = __raw_readl(clk->enable_reg);
-       reg &= ~(3 << clk->enable_shift);
-       __raw_writel(reg, clk->enable_reg);
-}
-
-#define DEFINE_CLOCK(name, i, er, es, gr, sr)          \
-       static struct clk name = {                      \
-               .id             = i,                    \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .get_rate       = gr,                   \
-               .set_rate       = sr,                   \
-               .enable         = clk_cgr_enable,       \
-               .disable        = clk_cgr_disable,      \
-       }
-
-DEFINE_CLOCK(asrc_clk,   0, MX35_CCM_CGR0,  0, NULL, NULL);
-DEFINE_CLOCK(pata_clk,    0, MX35_CCM_CGR0,  2, get_rate_ipg, NULL);
-/* DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR0,  4, NULL, NULL); */
-DEFINE_CLOCK(can1_clk,   0, MX35_CCM_CGR0,  6, get_rate_ipg, NULL);
-DEFINE_CLOCK(can2_clk,   1, MX35_CCM_CGR0,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi1_clk,  0, MX35_CCM_CGR0, 10, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi2_clk,  1, MX35_CCM_CGR0, 12, get_rate_ipg, NULL);
-DEFINE_CLOCK(ect_clk,    0, MX35_CCM_CGR0, 14, get_rate_ipg, NULL);
-DEFINE_CLOCK(edio_clk,   0, MX35_CCM_CGR0, 16, NULL, NULL);
-DEFINE_CLOCK(emi_clk,    0, MX35_CCM_CGR0, 18, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit1_clk,  0, MX35_CCM_CGR0, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit2_clk,  1, MX35_CCM_CGR0, 22, get_rate_ipg, NULL);
-DEFINE_CLOCK(esai_clk,   0, MX35_CCM_CGR0, 24, NULL, NULL);
-DEFINE_CLOCK(esdhc1_clk, 0, MX35_CCM_CGR0, 26, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc2_clk, 1, MX35_CCM_CGR0, 28, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc3_clk, 2, MX35_CCM_CGR0, 30, get_rate_sdhc, NULL);
-
-DEFINE_CLOCK(fec_clk,    0, MX35_CCM_CGR1,  0, get_rate_ipg, NULL);
-DEFINE_CLOCK(gpio1_clk,  0, MX35_CCM_CGR1,  2, NULL, NULL);
-DEFINE_CLOCK(gpio2_clk,  1, MX35_CCM_CGR1,  4, NULL, NULL);
-DEFINE_CLOCK(gpio3_clk,  2, MX35_CCM_CGR1,  6, NULL, NULL);
-DEFINE_CLOCK(gpt_clk,    0, MX35_CCM_CGR1,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(i2c1_clk,   0, MX35_CCM_CGR1, 10, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c2_clk,   1, MX35_CCM_CGR1, 12, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c3_clk,   2, MX35_CCM_CGR1, 14, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(iomuxc_clk, 0, MX35_CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, MX35_CCM_CGR1, 18, get_rate_hsp, NULL);
-DEFINE_CLOCK(kpp_clk,    0, MX35_CCM_CGR1, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(mlb_clk,    0, MX35_CCM_CGR1, 22, get_rate_ahb, NULL);
-DEFINE_CLOCK(mshc_clk,   0, MX35_CCM_CGR1, 24, get_rate_mshc, NULL);
-DEFINE_CLOCK(owire_clk,  0, MX35_CCM_CGR1, 26, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(pwm_clk,    0, MX35_CCM_CGR1, 28, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(rngc_clk,   0, MX35_CCM_CGR1, 30, get_rate_ipg, NULL);
-
-DEFINE_CLOCK(rtc_clk,    0, MX35_CCM_CGR2,  0, get_rate_ipg, NULL);
-DEFINE_CLOCK(rtic_clk,   0, MX35_CCM_CGR2,  2, get_rate_ahb, NULL);
-DEFINE_CLOCK(scc_clk,    0, MX35_CCM_CGR2,  4, get_rate_ipg, NULL);
-DEFINE_CLOCK(sdma_clk,   0, MX35_CCM_CGR2,  6, NULL, NULL);
-DEFINE_CLOCK(spba_clk,   0, MX35_CCM_CGR2,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(spdif_clk,  0, MX35_CCM_CGR2, 10, NULL, NULL);
-DEFINE_CLOCK(ssi1_clk,   0, MX35_CCM_CGR2, 12, get_rate_ssi, NULL);
-DEFINE_CLOCK(ssi2_clk,   1, MX35_CCM_CGR2, 14, get_rate_ssi, NULL);
-DEFINE_CLOCK(uart1_clk,  0, MX35_CCM_CGR2, 16, get_rate_uart, NULL);
-DEFINE_CLOCK(uart2_clk,  1, MX35_CCM_CGR2, 18, get_rate_uart, NULL);
-DEFINE_CLOCK(uart3_clk,  2, MX35_CCM_CGR2, 20, get_rate_uart, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, MX35_CCM_CGR2, 22, get_rate_otg, NULL);
-DEFINE_CLOCK(wdog_clk,   0, MX35_CCM_CGR2, 24, NULL, NULL);
-DEFINE_CLOCK(max_clk,    0, MX35_CCM_CGR2, 26, NULL, NULL);
-DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR2, 30, NULL, NULL);
-
-DEFINE_CLOCK(csi_clk,    0, MX35_CCM_CGR3,  0, get_rate_csi, NULL);
-DEFINE_CLOCK(iim_clk,    0, MX35_CCM_CGR3,  2, NULL, NULL);
-DEFINE_CLOCK(gpu2d_clk,  0, MX35_CCM_CGR3,  4, NULL, NULL);
-
-DEFINE_CLOCK(usbahb_clk, 0, 0,         0, get_rate_ahb, NULL);
-
-static int clk_dummy_enable(struct clk *clk)
-{
-       return 0;
-}
-
-static void clk_dummy_disable(struct clk *clk)
-{
-}
-
-static unsigned long get_rate_nfc(struct clk *clk)
-{
-       unsigned long div1;
-
-       div1 = (__raw_readl(MX35_CCM_PDR4) >> 28) + 1;
-
-       return get_rate_ahb(NULL) / div1;
-}
-
-/* NAND Controller: It seems it can't be disabled */
-static struct clk nfc_clk = {
-       .id             = 0,
-       .enable_reg     = 0,
-       .enable_shift   = 0,
-       .get_rate       = get_rate_nfc,
-       .set_rate       = NULL, /* set_rate_nfc, */
-       .enable         = clk_dummy_enable,
-       .disable        = clk_dummy_disable
-};
-
-#define _REGISTER_CLOCK(d, n, c)       \
-       {                               \
-               .dev_id = d,            \
-               .con_id = n,            \
-               .clk = &c,              \
-       },
-
-static struct clk_lookup lookups[] = {
-       _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
-       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-       _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
-       _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
-       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
-       _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
-       _REGISTER_CLOCK(NULL, "ect", ect_clk)
-       _REGISTER_CLOCK(NULL, "edio", edio_clk)
-       _REGISTER_CLOCK(NULL, "emi", emi_clk)
-       _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
-       _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
-       _REGISTER_CLOCK(NULL, "esai", esai_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx35.0", NULL, esdhc1_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx35.1", NULL, esdhc2_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx35.2", NULL, esdhc3_clk)
-       /* i.mx35 has the i.mx27 type fec */
-       _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
-       _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
-       _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
-       _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
-       _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-       _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
-       _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
-       _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
-       _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
-       _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
-       _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
-       _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
-       _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
-       _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
-       _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
-       _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-       _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
-       _REGISTER_CLOCK(NULL, "scc", scc_clk)
-       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-       _REGISTER_CLOCK(NULL, "spba", spba_clk)
-       _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
-       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-       /* i.mx35 has the i.mx21 type uart */
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
-       _REGISTER_CLOCK(NULL, "max", max_clk)
-       _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
-       _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
-       _REGISTER_CLOCK(NULL, "iim", iim_clk)
-       _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
-       _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-};
-
-int __init mx35_clocks_init()
-{
-       unsigned int cgr2 = 3 << 26;
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-       cgr2 |= 3 << 16;
-#endif
-
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-       /* Turn off all clocks except the ones we need to survive, namely:
-        * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
-        */
-       __raw_writel((3 << 18), MX35_CCM_CGR0);
-       __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
-                       MX35_CCM_CGR1);
-       __raw_writel(cgr2, MX35_CCM_CGR2);
-       __raw_writel(0, MX35_CCM_CGR3);
-
-       clk_enable(&iim_clk);
-       imx_print_silicon_rev("i.MX35", mx35_revision());
-       clk_disable(&iim_clk);
-
-       /*
-        * Check if we came up in internal boot mode. If yes, we need some
-        * extra clocks turned on, otherwise the MX35 boot ROM code will
-        * hang after a watchdog reset.
-        */
-       if (!(__raw_readl(MX35_CCM_RCSR) & (3 << 10))) {
-               /* Additionally turn on UART1, SCC, and IIM clocks */
-               clk_enable(&iim_clk);
-               clk_enable(&uart1_clk);
-               clk_enable(&scc_clk);
-       }
-
-#ifdef CONFIG_MXC_USE_EPIT
-       epit_timer_init(&epit1_clk,
-                       MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
-#else
-       mxc_timer_init(&gpt_clk,
-                       MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
-#endif
-
-       return 0;
-}

diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
deleted file mode 100644 (file)
index 111c328..0000000
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ /dev/null
@@ -1,2111 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/div64.h>
-#include <asm/mach/map.h>
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-
-#define PLL_BASE               IMX_IO_ADDRESS(MX6Q_ANATOP_BASE_ADDR)
-#define PLL1_SYS               (PLL_BASE + 0x000)
-#define PLL2_BUS               (PLL_BASE + 0x030)
-#define PLL3_USB_OTG           (PLL_BASE + 0x010)
-#define PLL4_AUDIO             (PLL_BASE + 0x070)
-#define PLL5_VIDEO             (PLL_BASE + 0x0a0)
-#define PLL6_MLB               (PLL_BASE + 0x0d0)
-#define PLL7_USB_HOST          (PLL_BASE + 0x020)
-#define PLL8_ENET              (PLL_BASE + 0x0e0)
-#define PFD_480                        (PLL_BASE + 0x0f0)
-#define PFD_528                        (PLL_BASE + 0x100)
-#define PLL_NUM_OFFSET         0x010
-#define PLL_DENOM_OFFSET       0x020
-
-#define PFD0                   7
-#define PFD1                   15
-#define PFD2                   23
-#define PFD3                   31
-#define PFD_FRAC_MASK          0x3f
-
-#define BM_PLL_BYPASS                  (0x1 << 16)
-#define BM_PLL_ENABLE                  (0x1 << 13)
-#define BM_PLL_POWER_DOWN              (0x1 << 12)
-#define BM_PLL_LOCK                    (0x1 << 31)
-#define BP_PLL_SYS_DIV_SELECT          0
-#define BM_PLL_SYS_DIV_SELECT          (0x7f << 0)
-#define BP_PLL_BUS_DIV_SELECT          0
-#define BM_PLL_BUS_DIV_SELECT          (0x1 << 0)
-#define BP_PLL_USB_DIV_SELECT          0
-#define BM_PLL_USB_DIV_SELECT          (0x3 << 0)
-#define BP_PLL_AV_DIV_SELECT           0
-#define BM_PLL_AV_DIV_SELECT           (0x7f << 0)
-#define BP_PLL_ENET_DIV_SELECT         0
-#define BM_PLL_ENET_DIV_SELECT         (0x3 << 0)
-#define BM_PLL_ENET_EN_PCIE            (0x1 << 19)
-#define BM_PLL_ENET_EN_SATA            (0x1 << 20)
-
-#define CCM_BASE       IMX_IO_ADDRESS(MX6Q_CCM_BASE_ADDR)
-#define CCR            (CCM_BASE + 0x00)
-#define CCDR           (CCM_BASE + 0x04)
-#define CSR            (CCM_BASE + 0x08)
-#define CCSR           (CCM_BASE + 0x0c)
-#define CACRR          (CCM_BASE + 0x10)
-#define CBCDR          (CCM_BASE + 0x14)
-#define CBCMR          (CCM_BASE + 0x18)
-#define CSCMR1         (CCM_BASE + 0x1c)
-#define CSCMR2         (CCM_BASE + 0x20)
-#define CSCDR1         (CCM_BASE + 0x24)
-#define CS1CDR         (CCM_BASE + 0x28)
-#define CS2CDR         (CCM_BASE + 0x2c)
-#define CDCDR          (CCM_BASE + 0x30)
-#define CHSCCDR                (CCM_BASE + 0x34)
-#define CSCDR2         (CCM_BASE + 0x38)
-#define CSCDR3         (CCM_BASE + 0x3c)
-#define CSCDR4         (CCM_BASE + 0x40)
-#define CWDR           (CCM_BASE + 0x44)
-#define CDHIPR         (CCM_BASE + 0x48)
-#define CDCR           (CCM_BASE + 0x4c)
-#define CTOR           (CCM_BASE + 0x50)
-#define CLPCR          (CCM_BASE + 0x54)
-#define CISR           (CCM_BASE + 0x58)
-#define CIMR           (CCM_BASE + 0x5c)
-#define CCOSR          (CCM_BASE + 0x60)
-#define CGPR           (CCM_BASE + 0x64)
-#define CCGR0          (CCM_BASE + 0x68)
-#define CCGR1          (CCM_BASE + 0x6c)
-#define CCGR2          (CCM_BASE + 0x70)
-#define CCGR3          (CCM_BASE + 0x74)
-#define CCGR4          (CCM_BASE + 0x78)
-#define CCGR5          (CCM_BASE + 0x7c)
-#define CCGR6          (CCM_BASE + 0x80)
-#define CCGR7          (CCM_BASE + 0x84)
-#define CMEOR          (CCM_BASE + 0x88)
-
-#define CG0            0
-#define CG1            2
-#define CG2            4
-#define CG3            6
-#define CG4            8
-#define CG5            10
-#define CG6            12
-#define CG7            14
-#define CG8            16
-#define CG9            18
-#define CG10           20
-#define CG11           22
-#define CG12           24
-#define CG13           26
-#define CG14           28
-#define CG15           30
-
-#define BM_CCSR_PLL1_SW_SEL            (0x1 << 2)
-#define BM_CCSR_STEP_SEL               (0x1 << 8)
-
-#define BP_CACRR_ARM_PODF              0
-#define BM_CACRR_ARM_PODF              (0x7 << 0)
-
-#define BP_CBCDR_PERIPH2_CLK2_PODF     0
-#define BM_CBCDR_PERIPH2_CLK2_PODF     (0x7 << 0)
-#define BP_CBCDR_MMDC_CH1_AXI_PODF     3
-#define BM_CBCDR_MMDC_CH1_AXI_PODF     (0x7 << 3)
-#define BP_CBCDR_AXI_SEL               6
-#define BM_CBCDR_AXI_SEL               (0x3 << 6)
-#define BP_CBCDR_IPG_PODF              8
-#define BM_CBCDR_IPG_PODF              (0x3 << 8)
-#define BP_CBCDR_AHB_PODF              10
-#define BM_CBCDR_AHB_PODF              (0x7 << 10)
-#define BP_CBCDR_AXI_PODF              16
-#define BM_CBCDR_AXI_PODF              (0x7 << 16)
-#define BP_CBCDR_MMDC_CH0_AXI_PODF     19
-#define BM_CBCDR_MMDC_CH0_AXI_PODF     (0x7 << 19)
-#define BP_CBCDR_PERIPH_CLK_SEL                25
-#define BM_CBCDR_PERIPH_CLK_SEL                (0x1 << 25)
-#define BP_CBCDR_PERIPH2_CLK_SEL       26
-#define BM_CBCDR_PERIPH2_CLK_SEL       (0x1 << 26)
-#define BP_CBCDR_PERIPH_CLK2_PODF      27
-#define BM_CBCDR_PERIPH_CLK2_PODF      (0x7 << 27)
-
-#define BP_CBCMR_GPU2D_AXI_SEL         0
-#define BM_CBCMR_GPU2D_AXI_SEL         (0x1 << 0)
-#define BP_CBCMR_GPU3D_AXI_SEL         1
-#define BM_CBCMR_GPU3D_AXI_SEL         (0x1 << 1)
-#define BP_CBCMR_GPU3D_CORE_SEL                4
-#define BM_CBCMR_GPU3D_CORE_SEL                (0x3 << 4)
-#define BP_CBCMR_GPU3D_SHADER_SEL      8
-#define BM_CBCMR_GPU3D_SHADER_SEL      (0x3 << 8)
-#define BP_CBCMR_PCIE_AXI_SEL          10
-#define BM_CBCMR_PCIE_AXI_SEL          (0x1 << 10)
-#define BP_CBCMR_VDO_AXI_SEL           11
-#define BM_CBCMR_VDO_AXI_SEL           (0x1 << 11)
-#define BP_CBCMR_PERIPH_CLK2_SEL       12
-#define BM_CBCMR_PERIPH_CLK2_SEL       (0x3 << 12)
-#define BP_CBCMR_VPU_AXI_SEL           14
-#define BM_CBCMR_VPU_AXI_SEL           (0x3 << 14)
-#define BP_CBCMR_GPU2D_CORE_SEL                16
-#define BM_CBCMR_GPU2D_CORE_SEL                (0x3 << 16)
-#define BP_CBCMR_PRE_PERIPH_CLK_SEL    18
-#define BM_CBCMR_PRE_PERIPH_CLK_SEL    (0x3 << 18)
-#define BP_CBCMR_PERIPH2_CLK2_SEL      20
-#define BM_CBCMR_PERIPH2_CLK2_SEL      (0x1 << 20)
-#define BP_CBCMR_PRE_PERIPH2_CLK_SEL   21
-#define BM_CBCMR_PRE_PERIPH2_CLK_SEL   (0x3 << 21)
-#define BP_CBCMR_GPU2D_CORE_PODF       23
-#define BM_CBCMR_GPU2D_CORE_PODF       (0x7 << 23)
-#define BP_CBCMR_GPU3D_CORE_PODF       26
-#define BM_CBCMR_GPU3D_CORE_PODF       (0x7 << 26)
-#define BP_CBCMR_GPU3D_SHADER_PODF     29
-#define BM_CBCMR_GPU3D_SHADER_PODF     (0x7 << 29)
-
-#define BP_CSCMR1_PERCLK_PODF          0
-#define BM_CSCMR1_PERCLK_PODF          (0x3f << 0)
-#define BP_CSCMR1_SSI1_SEL             10
-#define BM_CSCMR1_SSI1_SEL             (0x3 << 10)
-#define BP_CSCMR1_SSI2_SEL             12
-#define BM_CSCMR1_SSI2_SEL             (0x3 << 12)
-#define BP_CSCMR1_SSI3_SEL             14
-#define BM_CSCMR1_SSI3_SEL             (0x3 << 14)
-#define BP_CSCMR1_USDHC1_SEL           16
-#define BM_CSCMR1_USDHC1_SEL           (0x1 << 16)
-#define BP_CSCMR1_USDHC2_SEL           17
-#define BM_CSCMR1_USDHC2_SEL           (0x1 << 17)
-#define BP_CSCMR1_USDHC3_SEL           18
-#define BM_CSCMR1_USDHC3_SEL           (0x1 << 18)
-#define BP_CSCMR1_USDHC4_SEL           19
-#define BM_CSCMR1_USDHC4_SEL           (0x1 << 19)
-#define BP_CSCMR1_EMI_PODF             20
-#define BM_CSCMR1_EMI_PODF             (0x7 << 20)
-#define BP_CSCMR1_EMI_SLOW_PODF                23
-#define BM_CSCMR1_EMI_SLOW_PODF                (0x7 << 23)
-#define BP_CSCMR1_EMI_SEL              27
-#define BM_CSCMR1_EMI_SEL              (0x3 << 27)
-#define BP_CSCMR1_EMI_SLOW_SEL         29
-#define BM_CSCMR1_EMI_SLOW_SEL         (0x3 << 29)
-
-#define BP_CSCMR2_CAN_PODF             2
-#define BM_CSCMR2_CAN_PODF             (0x3f << 2)
-#define BM_CSCMR2_LDB_DI0_IPU_DIV      (0x1 << 10)
-#define BM_CSCMR2_LDB_DI1_IPU_DIV      (0x1 << 11)
-#define BP_CSCMR2_ESAI_SEL             19
-#define BM_CSCMR2_ESAI_SEL             (0x3 << 19)
-
-#define BP_CSCDR1_UART_PODF            0
-#define BM_CSCDR1_UART_PODF            (0x3f << 0)
-#define BP_CSCDR1_USDHC1_PODF          11
-#define BM_CSCDR1_USDHC1_PODF          (0x7 << 11)
-#define BP_CSCDR1_USDHC2_PODF          16
-#define BM_CSCDR1_USDHC2_PODF          (0x7 << 16)
-#define BP_CSCDR1_USDHC3_PODF          19
-#define BM_CSCDR1_USDHC3_PODF          (0x7 << 19)
-#define BP_CSCDR1_USDHC4_PODF          22
-#define BM_CSCDR1_USDHC4_PODF          (0x7 << 22)
-#define BP_CSCDR1_VPU_AXI_PODF         25
-#define BM_CSCDR1_VPU_AXI_PODF         (0x7 << 25)
-
-#define BP_CS1CDR_SSI1_PODF            0
-#define BM_CS1CDR_SSI1_PODF            (0x3f << 0)
-#define BP_CS1CDR_SSI1_PRED            6
-#define BM_CS1CDR_SSI1_PRED            (0x7 << 6)
-#define BP_CS1CDR_ESAI_PRED            9
-#define BM_CS1CDR_ESAI_PRED            (0x7 << 9)
-#define BP_CS1CDR_SSI3_PODF            16
-#define BM_CS1CDR_SSI3_PODF            (0x3f << 16)
-#define BP_CS1CDR_SSI3_PRED            22
-#define BM_CS1CDR_SSI3_PRED            (0x7 << 22)
-#define BP_CS1CDR_ESAI_PODF            25
-#define BM_CS1CDR_ESAI_PODF            (0x7 << 25)
-
-#define BP_CS2CDR_SSI2_PODF            0
-#define BM_CS2CDR_SSI2_PODF            (0x3f << 0)
-#define BP_CS2CDR_SSI2_PRED            6
-#define BM_CS2CDR_SSI2_PRED            (0x7 << 6)
-#define BP_CS2CDR_LDB_DI0_SEL          9
-#define BM_CS2CDR_LDB_DI0_SEL          (0x7 << 9)
-#define BP_CS2CDR_LDB_DI1_SEL          12
-#define BM_CS2CDR_LDB_DI1_SEL          (0x7 << 12)
-#define BP_CS2CDR_ENFC_SEL             16
-#define BM_CS2CDR_ENFC_SEL             (0x3 << 16)
-#define BP_CS2CDR_ENFC_PRED            18
-#define BM_CS2CDR_ENFC_PRED            (0x7 << 18)
-#define BP_CS2CDR_ENFC_PODF            21
-#define BM_CS2CDR_ENFC_PODF            (0x3f << 21)
-
-#define BP_CDCDR_ASRC_SERIAL_SEL       7
-#define BM_CDCDR_ASRC_SERIAL_SEL       (0x3 << 7)
-#define BP_CDCDR_ASRC_SERIAL_PODF      9
-#define BM_CDCDR_ASRC_SERIAL_PODF      (0x7 << 9)
-#define BP_CDCDR_ASRC_SERIAL_PRED      12
-#define BM_CDCDR_ASRC_SERIAL_PRED      (0x7 << 12)
-#define BP_CDCDR_SPDIF_SEL             20
-#define BM_CDCDR_SPDIF_SEL             (0x3 << 20)
-#define BP_CDCDR_SPDIF_PODF            22
-#define BM_CDCDR_SPDIF_PODF            (0x7 << 22)
-#define BP_CDCDR_SPDIF_PRED            25
-#define BM_CDCDR_SPDIF_PRED            (0x7 << 25)
-#define BP_CDCDR_HSI_TX_PODF           29
-#define BM_CDCDR_HSI_TX_PODF           (0x7 << 29)
-#define BP_CDCDR_HSI_TX_SEL            28
-#define BM_CDCDR_HSI_TX_SEL            (0x1 << 28)
-
-#define BP_CHSCCDR_IPU1_DI0_SEL                0
-#define BM_CHSCCDR_IPU1_DI0_SEL                (0x7 << 0)
-#define BP_CHSCCDR_IPU1_DI0_PRE_PODF   3
-#define BM_CHSCCDR_IPU1_DI0_PRE_PODF   (0x7 << 3)
-#define BP_CHSCCDR_IPU1_DI0_PRE_SEL    6
-#define BM_CHSCCDR_IPU1_DI0_PRE_SEL    (0x7 << 6)
-#define BP_CHSCCDR_IPU1_DI1_SEL                9
-#define BM_CHSCCDR_IPU1_DI1_SEL                (0x7 << 9)
-#define BP_CHSCCDR_IPU1_DI1_PRE_PODF   12
-#define BM_CHSCCDR_IPU1_DI1_PRE_PODF   (0x7 << 12)
-#define BP_CHSCCDR_IPU1_DI1_PRE_SEL    15
-#define BM_CHSCCDR_IPU1_DI1_PRE_SEL    (0x7 << 15)
-
-#define BP_CSCDR2_IPU2_DI0_SEL         0
-#define BM_CSCDR2_IPU2_DI0_SEL         (0x7)
-#define BP_CSCDR2_IPU2_DI0_PRE_PODF    3
-#define BM_CSCDR2_IPU2_DI0_PRE_PODF    (0x7 << 3)
-#define BP_CSCDR2_IPU2_DI0_PRE_SEL     6
-#define BM_CSCDR2_IPU2_DI0_PRE_SEL     (0x7 << 6)
-#define BP_CSCDR2_IPU2_DI1_SEL         9
-#define BM_CSCDR2_IPU2_DI1_SEL         (0x7 << 9)
-#define BP_CSCDR2_IPU2_DI1_PRE_PODF    12
-#define BM_CSCDR2_IPU2_DI1_PRE_PODF    (0x7 << 12)
-#define BP_CSCDR2_IPU2_DI1_PRE_SEL     15
-#define BM_CSCDR2_IPU2_DI1_PRE_SEL     (0x7 << 15)
-#define BP_CSCDR2_ECSPI_CLK_PODF       19
-#define BM_CSCDR2_ECSPI_CLK_PODF       (0x3f << 19)
-
-#define BP_CSCDR3_IPU1_HSP_SEL         9
-#define BM_CSCDR3_IPU1_HSP_SEL         (0x3 << 9)
-#define BP_CSCDR3_IPU1_HSP_PODF                11
-#define BM_CSCDR3_IPU1_HSP_PODF                (0x7 << 11)
-#define BP_CSCDR3_IPU2_HSP_SEL         14
-#define BM_CSCDR3_IPU2_HSP_SEL         (0x3 << 14)
-#define BP_CSCDR3_IPU2_HSP_PODF                16
-#define BM_CSCDR3_IPU2_HSP_PODF                (0x7 << 16)
-
-#define BM_CDHIPR_AXI_PODF_BUSY                (0x1 << 0)
-#define BM_CDHIPR_AHB_PODF_BUSY                (0x1 << 1)
-#define BM_CDHIPR_MMDC_CH1_PODF_BUSY   (0x1 << 2)
-#define BM_CDHIPR_PERIPH2_SEL_BUSY     (0x1 << 3)
-#define BM_CDHIPR_MMDC_CH0_PODF_BUSY   (0x1 << 4)
-#define BM_CDHIPR_PERIPH_SEL_BUSY      (0x1 << 5)
-#define BM_CDHIPR_ARM_PODF_BUSY                (0x1 << 16)
-
-#define BP_CLPCR_LPM                   0
-#define BM_CLPCR_LPM                   (0x3 << 0)
-#define BM_CLPCR_BYPASS_PMIC_READY     (0x1 << 2)
-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM    (0x1 << 5)
-#define BM_CLPCR_SBYOS                 (0x1 << 6)
-#define BM_CLPCR_DIS_REF_OSC           (0x1 << 7)
-#define BM_CLPCR_VSTBY                 (0x1 << 8)
-#define BP_CLPCR_STBY_COUNT            9
-#define BM_CLPCR_STBY_COUNT            (0x3 << 9)
-#define BM_CLPCR_COSC_PWRDOWN          (0x1 << 11)
-#define BM_CLPCR_WB_PER_AT_LPM         (0x1 << 16)
-#define BM_CLPCR_WB_CORE_AT_LPM                (0x1 << 17)
-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS   (0x1 << 19)
-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS   (0x1 << 21)
-#define BM_CLPCR_MASK_CORE0_WFI                (0x1 << 22)
-#define BM_CLPCR_MASK_CORE1_WFI                (0x1 << 23)
-#define BM_CLPCR_MASK_CORE2_WFI                (0x1 << 24)
-#define BM_CLPCR_MASK_CORE3_WFI                (0x1 << 25)
-#define BM_CLPCR_MASK_SCU_IDLE         (0x1 << 26)
-#define BM_CLPCR_MASK_L2CC_IDLE                (0x1 << 27)
-
-#define BP_CCOSR_CKO1_EN               7
-#define BP_CCOSR_CKO1_PODF             4
-#define BM_CCOSR_CKO1_PODF             (0x7 << 4)
-#define BP_CCOSR_CKO1_SEL              0
-#define BM_CCOSR_CKO1_SEL              (0xf << 0)
-
-#define FREQ_480M      480000000
-#define FREQ_528M      528000000
-#define FREQ_594M      594000000
-#define FREQ_650M      650000000
-#define FREQ_1300M     1300000000
-
-static struct clk pll1_sys;
-static struct clk pll2_bus;
-static struct clk pll3_usb_otg;
-static struct clk pll4_audio;
-static struct clk pll5_video;
-static struct clk pll6_mlb;
-static struct clk pll7_usb_host;
-static struct clk pll8_enet;
-static struct clk apbh_dma_clk;
-static struct clk arm_clk;
-static struct clk ipg_clk;
-static struct clk ahb_clk;
-static struct clk axi_clk;
-static struct clk mmdc_ch0_axi_clk;
-static struct clk mmdc_ch1_axi_clk;
-static struct clk periph_clk;
-static struct clk periph_pre_clk;
-static struct clk periph_clk2_clk;
-static struct clk periph2_clk;
-static struct clk periph2_pre_clk;
-static struct clk periph2_clk2_clk;
-static struct clk gpu2d_core_clk;
-static struct clk gpu3d_core_clk;
-static struct clk gpu3d_shader_clk;
-static struct clk ipg_perclk;
-static struct clk emi_clk;
-static struct clk emi_slow_clk;
-static struct clk can1_clk;
-static struct clk uart_clk;
-static struct clk usdhc1_clk;
-static struct clk usdhc2_clk;
-static struct clk usdhc3_clk;
-static struct clk usdhc4_clk;
-static struct clk vpu_clk;
-static struct clk hsi_tx_clk;
-static struct clk ipu1_di0_pre_clk;
-static struct clk ipu1_di1_pre_clk;
-static struct clk ipu2_di0_pre_clk;
-static struct clk ipu2_di1_pre_clk;
-static struct clk ipu1_clk;
-static struct clk ipu2_clk;
-static struct clk ssi1_clk;
-static struct clk ssi3_clk;
-static struct clk esai_clk;
-static struct clk ssi2_clk;
-static struct clk spdif_clk;
-static struct clk asrc_serial_clk;
-static struct clk gpu2d_axi_clk;
-static struct clk gpu3d_axi_clk;
-static struct clk pcie_clk;
-static struct clk vdo_axi_clk;
-static struct clk ldb_di0_clk;
-static struct clk ldb_di1_clk;
-static struct clk ipu1_di0_clk;
-static struct clk ipu1_di1_clk;
-static struct clk ipu2_di0_clk;
-static struct clk ipu2_di1_clk;
-static struct clk enfc_clk;
-static struct clk cko1_clk;
-static struct clk dummy_clk = {};
-
-static unsigned long external_high_reference;
-static unsigned long external_low_reference;
-static unsigned long oscillator_reference;
-
-static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
-{
-       return oscillator_reference;
-}
-
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
-{
-       return external_high_reference;
-}
-
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
-{
-       return external_low_reference;
-}
-
-static struct clk ckil_clk = {
-       .get_rate = get_low_reference_clock_rate,
-};
-
-static struct clk ckih_clk = {
-       .get_rate = get_high_reference_clock_rate,
-};
-
-static struct clk osc_clk = {
-       .get_rate = get_oscillator_reference_clock_rate,
-};
-
-static inline void __iomem *pll_get_reg_addr(struct clk *pll)
-{
-       if (pll == &pll1_sys)
-               return PLL1_SYS;
-       else if (pll == &pll2_bus)
-               return PLL2_BUS;
-       else if (pll == &pll3_usb_otg)
-               return PLL3_USB_OTG;
-       else if (pll == &pll4_audio)
-               return PLL4_AUDIO;
-       else if (pll == &pll5_video)
-               return PLL5_VIDEO;
-       else if (pll == &pll6_mlb)
-               return PLL6_MLB;
-       else if (pll == &pll7_usb_host)
-               return PLL7_USB_HOST;
-       else if (pll == &pll8_enet)
-               return PLL8_ENET;
-       else
-               BUG();
-
-       return NULL;
-}
-
-static int pll_enable(struct clk *clk)
-{
-       int timeout = 0x100000;
-       void __iomem *reg;
-       u32 val;
-
-       reg = pll_get_reg_addr(clk);
-       val = readl_relaxed(reg);
-       val &= ~BM_PLL_BYPASS;
-       val &= ~BM_PLL_POWER_DOWN;
-       /* 480MHz PLLs have the opposite definition for power bit */
-       if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
-               val |= BM_PLL_POWER_DOWN;
-       writel_relaxed(val, reg);
-
-       /* Wait for PLL to lock */
-       while (!(readl_relaxed(reg) & BM_PLL_LOCK) && --timeout)
-               cpu_relax();
-
-       if (unlikely(!timeout))
-               return -EBUSY;
-
-       /* Enable the PLL output now */
-       val = readl_relaxed(reg);
-       val |= BM_PLL_ENABLE;
-       writel_relaxed(val, reg);
-
-       return 0;
-}
-
-static void pll_disable(struct clk *clk)
-{
-       void __iomem *reg;
-       u32 val;
-
-       reg = pll_get_reg_addr(clk);
-       val = readl_relaxed(reg);
-       val &= ~BM_PLL_ENABLE;
-       val |= BM_PLL_BYPASS;
-       val |= BM_PLL_POWER_DOWN;
-       if (clk == &pll3_usb_otg || clk == &pll7_usb_host)
-               val &= ~BM_PLL_POWER_DOWN;
-       writel_relaxed(val, reg);
-}
-
-static unsigned long pll1_sys_get_rate(struct clk *clk)
-{
-       u32 div = (readl_relaxed(PLL1_SYS) & BM_PLL_SYS_DIV_SELECT) >>
-                 BP_PLL_SYS_DIV_SELECT;
-
-       return clk_get_rate(clk->parent) * div / 2;
-}
-
-static int pll1_sys_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 val, div;
-
-       if (rate < FREQ_650M || rate > FREQ_1300M)
-               return -EINVAL;
-
-       div = rate * 2 / clk_get_rate(clk->parent);
-       val = readl_relaxed(PLL1_SYS);
-       val &= ~BM_PLL_SYS_DIV_SELECT;
-       val |= div << BP_PLL_SYS_DIV_SELECT;
-       writel_relaxed(val, PLL1_SYS);
-
-       return 0;
-}
-
-static unsigned long pll8_enet_get_rate(struct clk *clk)
-{
-       u32 div = (readl_relaxed(PLL8_ENET) & BM_PLL_ENET_DIV_SELECT) >>
-                 BP_PLL_ENET_DIV_SELECT;
-
-       switch (div) {
-       case 0:
-               return 25000000;
-       case 1:
-               return 50000000;
-       case 2:
-               return 100000000;
-       case 3:
-               return 125000000;
-       }
-
-       return 0;
-}
-
-static int pll8_enet_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 val, div;
-
-       switch (rate) {
-       case 25000000:
-               div = 0;
-               break;
-       case 50000000:
-               div = 1;
-               break;
-       case 100000000:
-               div = 2;
-               break;
-       case 125000000:
-               div = 3;
-               break;
-       default:
-               return -EINVAL;
-       }
-
-       val = readl_relaxed(PLL8_ENET);
-       val &= ~BM_PLL_ENET_DIV_SELECT;
-       val |= div << BP_PLL_ENET_DIV_SELECT;
-       writel_relaxed(val, PLL8_ENET);
-
-       return 0;
-}
-
-static unsigned long pll_av_get_rate(struct clk *clk)
-{
-       void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
-       unsigned long parent_rate = clk_get_rate(clk->parent);
-       u32 mfn = readl_relaxed(reg + PLL_NUM_OFFSET);
-       u32 mfd = readl_relaxed(reg + PLL_DENOM_OFFSET);
-       u32 div = (readl_relaxed(reg) & BM_PLL_AV_DIV_SELECT) >>
-                 BP_PLL_AV_DIV_SELECT;
-
-       return (parent_rate * div) + ((parent_rate / mfd) * mfn);
-}
-
-static int pll_av_set_rate(struct clk *clk, unsigned long rate)
-{
-       void __iomem *reg = (clk == &pll4_audio) ? PLL4_AUDIO : PLL5_VIDEO;
-       unsigned int parent_rate = clk_get_rate(clk->parent);
-       u32 val, div;
-       u32 mfn, mfd = 1000000;
-       s64 temp64;
-
-       if (rate < FREQ_650M || rate > FREQ_1300M)
-               return -EINVAL;
-
-       div = rate / parent_rate;
-       temp64 = (u64) (rate - div * parent_rate);
-       temp64 *= mfd;
-       do_div(temp64, parent_rate);
-       mfn = temp64;
-
-       val = readl_relaxed(reg);
-       val &= ~BM_PLL_AV_DIV_SELECT;
-       val |= div << BP_PLL_AV_DIV_SELECT;
-       writel_relaxed(val, reg);
-       writel_relaxed(mfn, reg + PLL_NUM_OFFSET);
-       writel_relaxed(mfd, reg + PLL_DENOM_OFFSET);
-
-       return 0;
-}
-
-static void __iomem *pll_get_div_reg_bit(struct clk *clk, u32 *bp, u32 *bm)
-{
-       void __iomem *reg;
-
-       if (clk == &pll2_bus) {
-               reg = PLL2_BUS;
-               *bp = BP_PLL_BUS_DIV_SELECT;
-               *bm = BM_PLL_BUS_DIV_SELECT;
-       } else if (clk == &pll3_usb_otg) {
-               reg = PLL3_USB_OTG;
-               *bp = BP_PLL_USB_DIV_SELECT;
-               *bm = BM_PLL_USB_DIV_SELECT;
-       } else if (clk == &pll7_usb_host) {
-               reg = PLL7_USB_HOST;
-               *bp = BP_PLL_USB_DIV_SELECT;
-               *bm = BM_PLL_USB_DIV_SELECT;
-       } else {
-               BUG();
-       }
-
-       return reg;
-}
-
-static unsigned long pll_get_rate(struct clk *clk)
-{
-       void __iomem *reg;
-       u32 div, bp, bm;
-
-       reg = pll_get_div_reg_bit(clk, &bp, &bm);
-       div = (readl_relaxed(reg) & bm) >> bp;
-
-       return (div == 1) ? clk_get_rate(clk->parent) * 22 :
-                           clk_get_rate(clk->parent) * 20;
-}
-
-static int pll_set_rate(struct clk *clk, unsigned long rate)
-{
-       void __iomem *reg;
-       u32 val, div, bp, bm;
-
-       if (rate == FREQ_528M)
-               div = 1;
-       else if (rate == FREQ_480M)
-               div = 0;
-       else
-               return -EINVAL;
-
-       reg = pll_get_div_reg_bit(clk, &bp, &bm);
-       val = readl_relaxed(reg);
-       val &= ~bm;
-       val |= div << bp;
-       writel_relaxed(val, reg);
-
-       return 0;
-}
-
-#define pll2_bus_get_rate      pll_get_rate
-#define pll2_bus_set_rate      pll_set_rate
-#define pll3_usb_otg_get_rate  pll_get_rate
-#define pll3_usb_otg_set_rate  pll_set_rate
-#define pll7_usb_host_get_rate pll_get_rate
-#define pll7_usb_host_set_rate pll_set_rate
-#define pll4_audio_get_rate    pll_av_get_rate
-#define pll4_audio_set_rate    pll_av_set_rate
-#define pll5_video_get_rate    pll_av_get_rate
-#define pll5_video_set_rate    pll_av_set_rate
-#define pll6_mlb_get_rate      NULL
-#define pll6_mlb_set_rate      NULL
-
-#define DEF_PLL(name)                                  \
-       static struct clk name = {                      \
-               .enable         = pll_enable,           \
-               .disable        = pll_disable,          \
-               .get_rate       = name##_get_rate,      \
-               .set_rate       = name##_set_rate,      \
-               .parent         = &osc_clk,             \
-       }
-
-DEF_PLL(pll1_sys);
-DEF_PLL(pll2_bus);
-DEF_PLL(pll3_usb_otg);
-DEF_PLL(pll4_audio);
-DEF_PLL(pll5_video);
-DEF_PLL(pll6_mlb);
-DEF_PLL(pll7_usb_host);
-DEF_PLL(pll8_enet);
-
-static unsigned long pfd_get_rate(struct clk *clk)
-{
-       u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
-       u32 frac, bp_frac;
-
-       if (apbh_dma_clk.usecount == 0)
-               apbh_dma_clk.enable(&apbh_dma_clk);
-
-       bp_frac = clk->enable_shift - 7;
-       frac = readl_relaxed(clk->enable_reg) >> bp_frac & PFD_FRAC_MASK;
-       do_div(tmp, frac);
-
-       return tmp;
-}
-
-static int pfd_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 val, frac, bp_frac;
-       u64 tmp = (u64) clk_get_rate(clk->parent) * 18;
-
-       if (apbh_dma_clk.usecount == 0)
-               apbh_dma_clk.enable(&apbh_dma_clk);
-
-       /*
-        * Round up the divider so that we don't set a rate
-        * higher than what is requested
-        */
-       tmp += rate / 2;
-       do_div(tmp, rate);
-       frac = tmp;
-       frac = (frac < 12) ? 12 : frac;
-       frac = (frac > 35) ? 35 : frac;
-
-       /*
-        * The frac field always starts from 7 bits lower
-        * position of enable bit
-        */
-       bp_frac = clk->enable_shift - 7;
-       val = readl_relaxed(clk->enable_reg);
-       val &= ~(PFD_FRAC_MASK << bp_frac);
-       val |= frac << bp_frac;
-       writel_relaxed(val, clk->enable_reg);
-
-       tmp = (u64) clk_get_rate(clk->parent) * 18;
-       do_div(tmp, frac);
-
-       if (apbh_dma_clk.usecount == 0)
-               apbh_dma_clk.disable(&apbh_dma_clk);
-
-       return 0;
-}
-
-static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
-{
-       u32 frac;
-       u64 tmp;
-
-       tmp = (u64) clk_get_rate(clk->parent) * 18;
-       tmp += rate / 2;
-       do_div(tmp, rate);
-       frac = tmp;
-       frac = (frac < 12) ? 12 : frac;
-       frac = (frac > 35) ? 35 : frac;
-       tmp = (u64) clk_get_rate(clk->parent) * 18;
-       do_div(tmp, frac);
-
-       return tmp;
-}
-
-static int pfd_enable(struct clk *clk)
-{
-       u32 val;
-
-       if (apbh_dma_clk.usecount == 0)
-               apbh_dma_clk.enable(&apbh_dma_clk);
-
-       val = readl_relaxed(clk->enable_reg);
-       val &= ~(1 << clk->enable_shift);
-       writel_relaxed(val, clk->enable_reg);
-
-       if (apbh_dma_clk.usecount == 0)
-               apbh_dma_clk.disable(&apbh_dma_clk);
-
-       return 0;
-}
-
-static void pfd_disable(struct clk *clk)
-{
-       u32 val;
-
-       if (apbh_dma_clk.usecount == 0)
-               apbh_dma_clk.enable(&apbh_dma_clk);
-
-       val = readl_relaxed(clk->enable_reg);
-       val |= 1 << clk->enable_shift;
-       writel_relaxed(val, clk->enable_reg);
-
-       if (apbh_dma_clk.usecount == 0)
-               apbh_dma_clk.disable(&apbh_dma_clk);
-}
-
-#define DEF_PFD(name, er, es, p)                       \
-       static struct clk name = {                      \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .enable         = pfd_enable,           \
-               .disable        = pfd_disable,          \
-               .get_rate       = pfd_get_rate,         \
-               .set_rate       = pfd_set_rate,         \
-               .round_rate     = pfd_round_rate,       \
-               .parent         = p,                    \
-       }
-
-DEF_PFD(pll2_pfd_352m, PFD_528, PFD0, &pll2_bus);
-DEF_PFD(pll2_pfd_594m, PFD_528, PFD1, &pll2_bus);
-DEF_PFD(pll2_pfd_400m, PFD_528, PFD2, &pll2_bus);
-DEF_PFD(pll3_pfd_720m, PFD_480, PFD0, &pll3_usb_otg);
-DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
-DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
-DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
-
-static unsigned long twd_clk_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / 2;
-}
-
-static struct clk twd_clk = {
-       .parent = &arm_clk,
-       .get_rate = twd_clk_get_rate,
-};
-
-static unsigned long pll2_200m_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / 2;
-}
-
-static struct clk pll2_200m = {
-       .parent = &pll2_pfd_400m,
-       .get_rate = pll2_200m_get_rate,
-};
-
-static unsigned long pll3_120m_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / 4;
-}
-
-static struct clk pll3_120m = {
-       .parent = &pll3_usb_otg,
-       .get_rate = pll3_120m_get_rate,
-};
-
-static unsigned long pll3_80m_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / 6;
-}
-
-static struct clk pll3_80m = {
-       .parent = &pll3_usb_otg,
-       .get_rate = pll3_80m_get_rate,
-};
-
-static unsigned long pll3_60m_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / 8;
-}
-
-static struct clk pll3_60m = {
-       .parent = &pll3_usb_otg,
-       .get_rate = pll3_60m_get_rate,
-};
-
-static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 val = readl_relaxed(CCSR);
-
-       if (parent == &pll1_sys) {
-               val &= ~BM_CCSR_PLL1_SW_SEL;
-               val &= ~BM_CCSR_STEP_SEL;
-       } else if (parent == &osc_clk) {
-               val |= BM_CCSR_PLL1_SW_SEL;
-               val &= ~BM_CCSR_STEP_SEL;
-       } else if (parent == &pll2_pfd_400m) {
-               val |= BM_CCSR_PLL1_SW_SEL;
-               val |= BM_CCSR_STEP_SEL;
-       } else {
-               return -EINVAL;
-       }
-
-       writel_relaxed(val, CCSR);
-
-       return 0;
-}
-
-static struct clk pll1_sw_clk = {
-       .parent = &pll1_sys,
-       .set_parent = pll1_sw_clk_set_parent,
-};
-
-static void calc_pred_podf_dividers(u32 div, u32 *pred, u32 *podf)
-{
-       u32 min_pred, temp_pred, old_err, err;
-
-       if (div >= 512) {
-               *pred = 8;
-               *podf = 64;
-       } else if (div >= 8) {
-               min_pred = (div - 1) / 64 + 1;
-               old_err = 8;
-               for (temp_pred = 8; temp_pred >= min_pred; temp_pred--) {
-                       err = div % temp_pred;
-                       if (err == 0) {
-                               *pred = temp_pred;
-                               break;
-                       }
-                       err = temp_pred - err;
-                       if (err < old_err) {
-                               old_err = err;
-                               *pred = temp_pred;
-                       }
-               }
-               *podf = (div + *pred - 1) / *pred;
-       } else if (div < 8) {
-               *pred = div;
-               *podf = 1;
-       }
-}
-
-static int _clk_enable(struct clk *clk)
-{
-       u32 reg;
-       reg = readl_relaxed(clk->enable_reg);
-       reg |= 0x3 << clk->enable_shift;
-       writel_relaxed(reg, clk->enable_reg);
-
-       return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
-       u32 reg;
-       reg = readl_relaxed(clk->enable_reg);
-       reg &= ~(0x3 << clk->enable_shift);
-       writel_relaxed(reg, clk->enable_reg);
-}
-
-static int _clk_enable_1b(struct clk *clk)
-{
-       u32 reg;
-       reg = readl_relaxed(clk->enable_reg);
-       reg |= 0x1 << clk->enable_shift;
-       writel_relaxed(reg, clk->enable_reg);
-
-       return 0;
-}
-
-static void _clk_disable_1b(struct clk *clk)
-{
-       u32 reg;
-       reg = readl_relaxed(clk->enable_reg);
-       reg &= ~(0x1 << clk->enable_shift);
-       writel_relaxed(reg, clk->enable_reg);
-}
-
-struct divider {
-       struct clk *clk;
-       void __iomem *reg;
-       u32 bp_pred;
-       u32 bm_pred;
-       u32 bp_podf;
-       u32 bm_podf;
-};
-
-#define DEF_CLK_DIV1(d, c, r, b)                               \
-       static struct divider d = {                             \
-               .clk = c,                                       \
-               .reg = r,                                       \
-               .bp_podf = BP_##r##_##b##_PODF,                 \
-               .bm_podf = BM_##r##_##b##_PODF,                 \
-       }
-
-DEF_CLK_DIV1(arm_div,          &arm_clk,               CACRR,  ARM);
-DEF_CLK_DIV1(ipg_div,          &ipg_clk,               CBCDR,  IPG);
-DEF_CLK_DIV1(ahb_div,          &ahb_clk,               CBCDR,  AHB);
-DEF_CLK_DIV1(axi_div,          &axi_clk,               CBCDR,  AXI);
-DEF_CLK_DIV1(mmdc_ch0_axi_div, &mmdc_ch0_axi_clk,      CBCDR,  MMDC_CH0_AXI);
-DEF_CLK_DIV1(mmdc_ch1_axi_div, &mmdc_ch1_axi_clk,      CBCDR,  MMDC_CH1_AXI);
-DEF_CLK_DIV1(periph_clk2_div,  &periph_clk2_clk,       CBCDR,  PERIPH_CLK2);
-DEF_CLK_DIV1(periph2_clk2_div, &periph2_clk2_clk,      CBCDR,  PERIPH2_CLK2);
-DEF_CLK_DIV1(gpu2d_core_div,   &gpu2d_core_clk,        CBCMR,  GPU2D_CORE);
-DEF_CLK_DIV1(gpu3d_core_div,   &gpu3d_core_clk,        CBCMR,  GPU3D_CORE);
-DEF_CLK_DIV1(gpu3d_shader_div, &gpu3d_shader_clk,      CBCMR,  GPU3D_SHADER);
-DEF_CLK_DIV1(ipg_perclk_div,   &ipg_perclk,            CSCMR1, PERCLK);
-DEF_CLK_DIV1(emi_div,          &emi_clk,               CSCMR1, EMI);
-DEF_CLK_DIV1(emi_slow_div,     &emi_slow_clk,          CSCMR1, EMI_SLOW);
-DEF_CLK_DIV1(can_div,          &can1_clk,              CSCMR2, CAN);
-DEF_CLK_DIV1(uart_div,         &uart_clk,              CSCDR1, UART);
-DEF_CLK_DIV1(usdhc1_div,       &usdhc1_clk,            CSCDR1, USDHC1);
-DEF_CLK_DIV1(usdhc2_div,       &usdhc2_clk,            CSCDR1, USDHC2);
-DEF_CLK_DIV1(usdhc3_div,       &usdhc3_clk,            CSCDR1, USDHC3);
-DEF_CLK_DIV1(usdhc4_div,       &usdhc4_clk,            CSCDR1, USDHC4);
-DEF_CLK_DIV1(vpu_div,          &vpu_clk,               CSCDR1, VPU_AXI);
-DEF_CLK_DIV1(hsi_tx_div,       &hsi_tx_clk,            CDCDR,  HSI_TX);
-DEF_CLK_DIV1(ipu1_di0_pre_div, &ipu1_di0_pre_clk,      CHSCCDR, IPU1_DI0_PRE);
-DEF_CLK_DIV1(ipu1_di1_pre_div, &ipu1_di1_pre_clk,      CHSCCDR, IPU1_DI1_PRE);
-DEF_CLK_DIV1(ipu2_di0_pre_div, &ipu2_di0_pre_clk,      CSCDR2, IPU2_DI0_PRE);
-DEF_CLK_DIV1(ipu2_di1_pre_div, &ipu2_di1_pre_clk,      CSCDR2, IPU2_DI1_PRE);
-DEF_CLK_DIV1(ipu1_div,         &ipu1_clk,              CSCDR3, IPU1_HSP);
-DEF_CLK_DIV1(ipu2_div,         &ipu2_clk,              CSCDR3, IPU2_HSP);
-DEF_CLK_DIV1(cko1_div,         &cko1_clk,              CCOSR, CKO1);
-
-#define DEF_CLK_DIV2(d, c, r, b)                               \
-       static struct divider d = {                             \
-               .clk = c,                                       \
-               .reg = r,                                       \
-               .bp_pred = BP_##r##_##b##_PRED,                 \
-               .bm_pred = BM_##r##_##b##_PRED,                 \
-               .bp_podf = BP_##r##_##b##_PODF,                 \
-               .bm_podf = BM_##r##_##b##_PODF,                 \
-       }
-
-DEF_CLK_DIV2(ssi1_div,         &ssi1_clk,              CS1CDR, SSI1);
-DEF_CLK_DIV2(ssi3_div,         &ssi3_clk,              CS1CDR, SSI3);
-DEF_CLK_DIV2(esai_div,         &esai_clk,              CS1CDR, ESAI);
-DEF_CLK_DIV2(ssi2_div,         &ssi2_clk,              CS2CDR, SSI2);
-DEF_CLK_DIV2(enfc_div,         &enfc_clk,              CS2CDR, ENFC);
-DEF_CLK_DIV2(spdif_div,                &spdif_clk,             CDCDR,  SPDIF);
-DEF_CLK_DIV2(asrc_serial_div,  &asrc_serial_clk,       CDCDR,  ASRC_SERIAL);
-
-static struct divider *dividers[] = {
-       &arm_div,
-       &ipg_div,
-       &ahb_div,
-       &axi_div,
-       &mmdc_ch0_axi_div,
-       &mmdc_ch1_axi_div,
-       &periph_clk2_div,
-       &periph2_clk2_div,
-       &gpu2d_core_div,
-       &gpu3d_core_div,
-       &gpu3d_shader_div,
-       &ipg_perclk_div,
-       &emi_div,
-       &emi_slow_div,
-       &can_div,
-       &uart_div,
-       &usdhc1_div,
-       &usdhc2_div,
-       &usdhc3_div,
-       &usdhc4_div,
-       &vpu_div,
-       &hsi_tx_div,
-       &ipu1_di0_pre_div,
-       &ipu1_di1_pre_div,
-       &ipu2_di0_pre_div,
-       &ipu2_di1_pre_div,
-       &ipu1_div,
-       &ipu2_div,
-       &ssi1_div,
-       &ssi3_div,
-       &esai_div,
-       &ssi2_div,
-       &enfc_div,
-       &spdif_div,
-       &asrc_serial_div,
-       &cko1_div,
-};
-
-static unsigned long ldb_di_clk_get_rate(struct clk *clk)
-{
-       u32 val = readl_relaxed(CSCMR2);
-
-       val &= (clk == &ldb_di0_clk) ? BM_CSCMR2_LDB_DI0_IPU_DIV :
-                                      BM_CSCMR2_LDB_DI1_IPU_DIV;
-       if (val)
-               return clk_get_rate(clk->parent) / 7;
-       else
-               return clk_get_rate(clk->parent) * 2 / 7;
-}
-
-static int ldb_di_clk_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned long parent_rate = clk_get_rate(clk->parent);
-       u32 val = readl_relaxed(CSCMR2);
-
-       if (rate * 7 <= parent_rate + parent_rate / 20)
-               val |= BM_CSCMR2_LDB_DI0_IPU_DIV;
-       else
-               val &= ~BM_CSCMR2_LDB_DI0_IPU_DIV;
-
-       writel_relaxed(val, CSCMR2);
-
-       return 0;
-}
-
-static unsigned long ldb_di_clk_round_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned long parent_rate = clk_get_rate(clk->parent);
-
-       if (rate * 7 <= parent_rate + parent_rate / 20)
-               return parent_rate / 7;
-       else
-               return 2 * parent_rate / 7;
-}
-
-static unsigned long _clk_get_rate(struct clk *clk)
-{
-       struct divider *d;
-       u32 val, pred, podf;
-       int i, num;
-
-       if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
-               return ldb_di_clk_get_rate(clk);
-
-       num = ARRAY_SIZE(dividers);
-       for (i = 0; i < num; i++)
-               if (dividers[i]->clk == clk) {
-                       d = dividers[i];
-                       break;
-               }
-       if (i == num)
-               return clk_get_rate(clk->parent);
-
-       val = readl_relaxed(d->reg);
-       pred = ((val & d->bm_pred) >> d->bp_pred) + 1;
-       podf = ((val & d->bm_podf) >> d->bp_podf) + 1;
-
-       return clk_get_rate(clk->parent) / (pred * podf);
-}
-
-static int clk_busy_wait(struct clk *clk)
-{
-       int timeout = 0x100000;
-       u32 bm;
-
-       if (clk == &axi_clk)
-               bm = BM_CDHIPR_AXI_PODF_BUSY;
-       else if (clk == &ahb_clk)
-               bm = BM_CDHIPR_AHB_PODF_BUSY;
-       else if (clk == &mmdc_ch0_axi_clk)
-               bm = BM_CDHIPR_MMDC_CH0_PODF_BUSY;
-       else if (clk == &periph_clk)
-               bm = BM_CDHIPR_PERIPH_SEL_BUSY;
-       else if (clk == &arm_clk)
-               bm = BM_CDHIPR_ARM_PODF_BUSY;
-       else
-               return -EINVAL;
-
-       while ((readl_relaxed(CDHIPR) & bm) && --timeout)
-               cpu_relax();
-
-       if (unlikely(!timeout))
-               return -EBUSY;
-
-       return 0;
-}
-
-static int _clk_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned long parent_rate = clk_get_rate(clk->parent);
-       struct divider *d;
-       u32 val, div, max_div, pred = 0, podf;
-       int i, num;
-
-       if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
-               return ldb_di_clk_set_rate(clk, rate);
-
-       num = ARRAY_SIZE(dividers);
-       for (i = 0; i < num; i++)
-               if (dividers[i]->clk == clk) {
-                       d = dividers[i];
-                       break;
-               }
-       if (i == num)
-               return -EINVAL;
-
-       max_div = ((d->bm_pred >> d->bp_pred) + 1) *
-                 ((d->bm_podf >> d->bp_podf) + 1);
-
-       div = parent_rate / rate;
-       if (div == 0)
-               div++;
-
-       if ((parent_rate / div != rate) || div > max_div)
-               return -EINVAL;
-
-       if (d->bm_pred) {
-               calc_pred_podf_dividers(div, &pred, &podf);
-       } else {
-               pred = 1;
-               podf = div;
-       }
-
-       val = readl_relaxed(d->reg);
-       val &= ~(d->bm_pred | d->bm_podf);
-       val |= (pred - 1) << d->bp_pred | (podf - 1) << d->bp_podf;
-       writel_relaxed(val, d->reg);
-
-       if (clk == &axi_clk || clk == &ahb_clk ||
-           clk == &mmdc_ch0_axi_clk || clk == &arm_clk)
-               return clk_busy_wait(clk);
-
-       return 0;
-}
-
-static unsigned long _clk_round_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned long parent_rate = clk_get_rate(clk->parent);
-       u32 div = parent_rate / rate;
-       u32 div_max, pred = 0, podf;
-       struct divider *d;
-       int i, num;
-
-       if (clk == &ldb_di0_clk || clk == &ldb_di1_clk)
-               return ldb_di_clk_round_rate(clk, rate);
-
-       num = ARRAY_SIZE(dividers);
-       for (i = 0; i < num; i++)
-               if (dividers[i]->clk == clk) {
-                       d = dividers[i];
-                       break;
-               }
-       if (i == num)
-               return -EINVAL;
-
-       if (div == 0 || parent_rate % rate)
-               div++;
-
-       if (d->bm_pred) {
-               calc_pred_podf_dividers(div, &pred, &podf);
-               div = pred * podf;
-       } else {
-               div_max = (d->bm_podf >> d->bp_podf) + 1;
-               if (div > div_max)
-                       div = div_max;
-       }
-
-       return parent_rate / div;
-}
-
-struct multiplexer {
-       struct clk *clk;
-       void __iomem *reg;
-       u32 bp;
-       u32 bm;
-       int pnum;
-       struct clk *parents[];
-};
-
-static struct multiplexer axi_mux = {
-       .clk = &axi_clk,
-       .reg = CBCDR,
-       .bp = BP_CBCDR_AXI_SEL,
-       .bm = BM_CBCDR_AXI_SEL,
-       .parents = {
-               &periph_clk,
-               &pll2_pfd_400m,
-               &pll3_pfd_540m,
-               NULL
-       },
-};
-
-static struct multiplexer periph_mux = {
-       .clk = &periph_clk,
-       .reg = CBCDR,
-       .bp = BP_CBCDR_PERIPH_CLK_SEL,
-       .bm = BM_CBCDR_PERIPH_CLK_SEL,
-       .parents = {
-               &periph_pre_clk,
-               &periph_clk2_clk,
-               NULL
-       },
-};
-
-static struct multiplexer periph_pre_mux = {
-       .clk = &periph_pre_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_PRE_PERIPH_CLK_SEL,
-       .bm = BM_CBCMR_PRE_PERIPH_CLK_SEL,
-       .parents = {
-               &pll2_bus,
-               &pll2_pfd_400m,
-               &pll2_pfd_352m,
-               &pll2_200m,
-               NULL
-       },
-};
-
-static struct multiplexer periph_clk2_mux = {
-       .clk = &periph_clk2_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_PERIPH_CLK2_SEL,
-       .bm = BM_CBCMR_PERIPH_CLK2_SEL,
-       .parents = {
-               &pll3_usb_otg,
-               &osc_clk,
-               NULL
-       },
-};
-
-static struct multiplexer periph2_mux = {
-       .clk = &periph2_clk,
-       .reg = CBCDR,
-       .bp = BP_CBCDR_PERIPH2_CLK_SEL,
-       .bm = BM_CBCDR_PERIPH2_CLK_SEL,
-       .parents = {
-               &periph2_pre_clk,
-               &periph2_clk2_clk,
-               NULL
-       },
-};
-
-static struct multiplexer periph2_pre_mux = {
-       .clk = &periph2_pre_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_PRE_PERIPH2_CLK_SEL,
-       .bm = BM_CBCMR_PRE_PERIPH2_CLK_SEL,
-       .parents = {
-               &pll2_bus,
-               &pll2_pfd_400m,
-               &pll2_pfd_352m,
-               &pll2_200m,
-               NULL
-       },
-};
-
-static struct multiplexer periph2_clk2_mux = {
-       .clk = &periph2_clk2_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_PERIPH2_CLK2_SEL,
-       .bm = BM_CBCMR_PERIPH2_CLK2_SEL,
-       .parents = {
-               &pll3_usb_otg,
-               &osc_clk,
-               NULL
-       },
-};
-
-static struct multiplexer gpu2d_axi_mux = {
-       .clk = &gpu2d_axi_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_GPU2D_AXI_SEL,
-       .bm = BM_CBCMR_GPU2D_AXI_SEL,
-       .parents = {
-               &axi_clk,
-               &ahb_clk,
-               NULL
-       },
-};
-
-static struct multiplexer gpu3d_axi_mux = {
-       .clk = &gpu3d_axi_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_GPU3D_AXI_SEL,
-       .bm = BM_CBCMR_GPU3D_AXI_SEL,
-       .parents = {
-               &axi_clk,
-               &ahb_clk,
-               NULL
-       },
-};
-
-static struct multiplexer gpu3d_core_mux = {
-       .clk = &gpu3d_core_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_GPU3D_CORE_SEL,
-       .bm = BM_CBCMR_GPU3D_CORE_SEL,
-       .parents = {
-               &mmdc_ch0_axi_clk,
-               &pll3_usb_otg,
-               &pll2_pfd_594m,
-               &pll2_pfd_400m,
-               NULL
-       },
-};
-
-static struct multiplexer gpu3d_shader_mux = {
-       .clk = &gpu3d_shader_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_GPU3D_SHADER_SEL,
-       .bm = BM_CBCMR_GPU3D_SHADER_SEL,
-       .parents = {
-               &mmdc_ch0_axi_clk,
-               &pll3_usb_otg,
-               &pll2_pfd_594m,
-               &pll3_pfd_720m,
-               NULL
-       },
-};
-
-static struct multiplexer pcie_axi_mux = {
-       .clk = &pcie_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_PCIE_AXI_SEL,
-       .bm = BM_CBCMR_PCIE_AXI_SEL,
-       .parents = {
-               &axi_clk,
-               &ahb_clk,
-               NULL
-       },
-};
-
-static struct multiplexer vdo_axi_mux = {
-       .clk = &vdo_axi_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_VDO_AXI_SEL,
-       .bm = BM_CBCMR_VDO_AXI_SEL,
-       .parents = {
-               &axi_clk,
-               &ahb_clk,
-               NULL
-       },
-};
-
-static struct multiplexer vpu_axi_mux = {
-       .clk = &vpu_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_VPU_AXI_SEL,
-       .bm = BM_CBCMR_VPU_AXI_SEL,
-       .parents = {
-               &axi_clk,
-               &pll2_pfd_400m,
-               &pll2_pfd_352m,
-               NULL
-       },
-};
-
-static struct multiplexer gpu2d_core_mux = {
-       .clk = &gpu2d_core_clk,
-       .reg = CBCMR,
-       .bp = BP_CBCMR_GPU2D_CORE_SEL,
-       .bm = BM_CBCMR_GPU2D_CORE_SEL,
-       .parents = {
-               &axi_clk,
-               &pll3_usb_otg,
-               &pll2_pfd_352m,
-               &pll2_pfd_400m,
-               NULL
-       },
-};
-
-#define DEF_SSI_MUX(id)                                                        \
-       static struct multiplexer ssi##id##_mux = {                     \
-               .clk = &ssi##id##_clk,                                  \
-               .reg = CSCMR1,                                          \
-               .bp = BP_CSCMR1_SSI##id##_SEL,                          \
-               .bm = BM_CSCMR1_SSI##id##_SEL,                          \
-               .parents = {                                            \
-                       &pll3_pfd_508m,                                 \
-                       &pll3_pfd_454m,                                 \
-                       &pll4_audio,                                    \
-                       NULL                                            \
-               },                                                      \
-       }
-
-DEF_SSI_MUX(1);
-DEF_SSI_MUX(2);
-DEF_SSI_MUX(3);
-
-#define DEF_USDHC_MUX(id)                                              \
-       static struct multiplexer usdhc##id##_mux = {                   \
-               .clk = &usdhc##id##_clk,                                \
-               .reg = CSCMR1,                                          \
-               .bp = BP_CSCMR1_USDHC##id##_SEL,                        \
-               .bm = BM_CSCMR1_USDHC##id##_SEL,                        \
-               .parents = {                                            \
-                       &pll2_pfd_400m,                                 \
-                       &pll2_pfd_352m,                                 \
-                       NULL                                            \
-               },                                                      \
-       }
-
-DEF_USDHC_MUX(1);
-DEF_USDHC_MUX(2);
-DEF_USDHC_MUX(3);
-DEF_USDHC_MUX(4);
-
-static struct multiplexer emi_mux = {
-       .clk = &emi_clk,
-       .reg = CSCMR1,
-       .bp = BP_CSCMR1_EMI_SEL,
-       .bm = BM_CSCMR1_EMI_SEL,
-       .parents = {
-               &axi_clk,
-               &pll3_usb_otg,
-               &pll2_pfd_400m,
-               &pll2_pfd_352m,
-               NULL
-       },
-};
-
-static struct multiplexer emi_slow_mux = {
-       .clk = &emi_slow_clk,
-       .reg = CSCMR1,
-       .bp = BP_CSCMR1_EMI_SLOW_SEL,
-       .bm = BM_CSCMR1_EMI_SLOW_SEL,
-       .parents = {
-               &axi_clk,
-               &pll3_usb_otg,
-               &pll2_pfd_400m,
-               &pll2_pfd_352m,
-               NULL
-       },
-};
-
-static struct multiplexer esai_mux = {
-       .clk = &esai_clk,
-       .reg = CSCMR2,
-       .bp = BP_CSCMR2_ESAI_SEL,
-       .bm = BM_CSCMR2_ESAI_SEL,
-       .parents = {
-               &pll4_audio,
-               &pll3_pfd_508m,
-               &pll3_pfd_454m,
-               &pll3_usb_otg,
-               NULL
-       },
-};
-
-#define DEF_LDB_DI_MUX(id)                                             \
-       static struct multiplexer ldb_di##id##_mux = {                  \
-               .clk = &ldb_di##id##_clk,                               \
-               .reg = CS2CDR,                                          \
-               .bp = BP_CS2CDR_LDB_DI##id##_SEL,                       \
-               .bm = BM_CS2CDR_LDB_DI##id##_SEL,                       \
-               .parents = {                                            \
-                       &pll5_video,                                    \
-                       &pll2_pfd_352m,                                 \
-                       &pll2_pfd_400m,                                 \
-                       &pll3_pfd_540m,                                 \
-                       &pll3_usb_otg,                                  \
-                       NULL                                            \
-               },                                                      \
-       }
-
-DEF_LDB_DI_MUX(0);
-DEF_LDB_DI_MUX(1);
-
-static struct multiplexer enfc_mux = {
-       .clk = &enfc_clk,
-       .reg = CS2CDR,
-       .bp = BP_CS2CDR_ENFC_SEL,
-       .bm = BM_CS2CDR_ENFC_SEL,
-       .parents = {
-               &pll2_pfd_352m,
-               &pll2_bus,
-               &pll3_usb_otg,
-               &pll2_pfd_400m,
-               NULL
-       },
-};
-
-static struct multiplexer spdif_mux = {
-       .clk = &spdif_clk,
-       .reg = CDCDR,
-       .bp = BP_CDCDR_SPDIF_SEL,
-       .bm = BM_CDCDR_SPDIF_SEL,
-       .parents = {
-               &pll4_audio,
-               &pll3_pfd_508m,
-               &pll3_pfd_454m,
-               &pll3_usb_otg,
-               NULL
-       },
-};
-
-static struct multiplexer asrc_serial_mux = {
-       .clk = &asrc_serial_clk,
-       .reg = CDCDR,
-       .bp = BP_CDCDR_ASRC_SERIAL_SEL,
-       .bm = BM_CDCDR_ASRC_SERIAL_SEL,
-       .parents = {
-               &pll4_audio,
-               &pll3_pfd_508m,
-               &pll3_pfd_454m,
-               &pll3_usb_otg,
-               NULL
-       },
-};
-
-static struct multiplexer hsi_tx_mux = {
-       .clk = &hsi_tx_clk,
-       .reg = CDCDR,
-       .bp = BP_CDCDR_HSI_TX_SEL,
-       .bm = BM_CDCDR_HSI_TX_SEL,
-       .parents = {
-               &pll3_120m,
-               &pll2_pfd_400m,
-               NULL
-       },
-};
-
-#define DEF_IPU_DI_PRE_MUX(r, i, d)                                    \
-       static struct multiplexer ipu##i##_di##d##_pre_mux = {          \
-               .clk = &ipu##i##_di##d##_pre_clk,                       \
-               .reg = r,                                               \
-               .bp = BP_##r##_IPU##i##_DI##d##_PRE_SEL,                \
-               .bm = BM_##r##_IPU##i##_DI##d##_PRE_SEL,                \
-               .parents = {                                            \
-                       &mmdc_ch0_axi_clk,                              \
-                       &pll3_usb_otg,                                  \
-                       &pll5_video,                                    \
-                       &pll2_pfd_352m,                                 \
-                       &pll2_pfd_400m,                                 \
-                       &pll3_pfd_540m,                                 \
-                       NULL                                            \
-               },                                                      \
-       }
-
-DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 0);
-DEF_IPU_DI_PRE_MUX(CHSCCDR, 1, 1);
-DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 0);
-DEF_IPU_DI_PRE_MUX(CSCDR2, 2, 1);
-
-#define DEF_IPU_DI_MUX(r, i, d)                                                \
-       static struct multiplexer ipu##i##_di##d##_mux = {              \
-               .clk = &ipu##i##_di##d##_clk,                           \
-               .reg = r,                                               \
-               .bp = BP_##r##_IPU##i##_DI##d##_SEL,                    \
-               .bm = BM_##r##_IPU##i##_DI##d##_SEL,                    \
-               .parents = {                                            \
-                       &ipu##i##_di##d##_pre_clk,                      \
-                       &dummy_clk,                                     \
-                       &dummy_clk,                                     \
-                       &ldb_di0_clk,                                   \
-                       &ldb_di1_clk,                                   \
-                       NULL                                            \
-               },                                                      \
-       }
-
-DEF_IPU_DI_MUX(CHSCCDR, 1, 0);
-DEF_IPU_DI_MUX(CHSCCDR, 1, 1);
-DEF_IPU_DI_MUX(CSCDR2, 2, 0);
-DEF_IPU_DI_MUX(CSCDR2, 2, 1);
-
-#define DEF_IPU_MUX(id)                                                        \
-       static struct multiplexer ipu##id##_mux = {                     \
-               .clk = &ipu##id##_clk,                                  \
-               .reg = CSCDR3,                                          \
-               .bp = BP_CSCDR3_IPU##id##_HSP_SEL,                      \
-               .bm = BM_CSCDR3_IPU##id##_HSP_SEL,                      \
-               .parents = {                                            \
-                       &mmdc_ch0_axi_clk,                              \
-                       &pll2_pfd_400m,                                 \
-                       &pll3_120m,                                     \
-                       &pll3_pfd_540m,                                 \
-                       NULL                                            \
-               },                                                      \
-       }
-
-DEF_IPU_MUX(1);
-DEF_IPU_MUX(2);
-
-static struct multiplexer cko1_mux = {
-       .clk = &cko1_clk,
-       .reg = CCOSR,
-       .bp = BP_CCOSR_CKO1_SEL,
-       .bm = BM_CCOSR_CKO1_SEL,
-       .parents = {
-               &pll3_usb_otg,
-               &pll2_bus,
-               &pll1_sys,
-               &pll5_video,
-               &dummy_clk,
-               &axi_clk,
-               &enfc_clk,
-               &ipu1_di0_clk,
-               &ipu1_di1_clk,
-               &ipu2_di0_clk,
-               &ipu2_di1_clk,
-               &ahb_clk,
-               &ipg_clk,
-               &ipg_perclk,
-               &ckil_clk,
-               &pll4_audio,
-               NULL
-       },
-};
-
-static struct multiplexer *multiplexers[] = {
-       &axi_mux,
-       &periph_mux,
-       &periph_pre_mux,
-       &periph_clk2_mux,
-       &periph2_mux,
-       &periph2_pre_mux,
-       &periph2_clk2_mux,
-       &gpu2d_axi_mux,
-       &gpu3d_axi_mux,
-       &gpu3d_core_mux,
-       &gpu3d_shader_mux,
-       &pcie_axi_mux,
-       &vdo_axi_mux,
-       &vpu_axi_mux,
-       &gpu2d_core_mux,
-       &ssi1_mux,
-       &ssi2_mux,
-       &ssi3_mux,
-       &usdhc1_mux,
-       &usdhc2_mux,
-       &usdhc3_mux,
-       &usdhc4_mux,
-       &emi_mux,
-       &emi_slow_mux,
-       &esai_mux,
-       &ldb_di0_mux,
-       &ldb_di1_mux,
-       &enfc_mux,
-       &spdif_mux,
-       &asrc_serial_mux,
-       &hsi_tx_mux,
-       &ipu1_di0_pre_mux,
-       &ipu1_di0_mux,
-       &ipu1_di1_pre_mux,
-       &ipu1_di1_mux,
-       &ipu2_di0_pre_mux,
-       &ipu2_di0_mux,
-       &ipu2_di1_pre_mux,
-       &ipu2_di1_mux,
-       &ipu1_mux,
-       &ipu2_mux,
-       &cko1_mux,
-};
-
-static int _clk_set_parent(struct clk *clk, struct clk *parent)
-{
-       struct multiplexer *m;
-       int i, num;
-       u32 val;
-
-       num = ARRAY_SIZE(multiplexers);
-       for (i = 0; i < num; i++)
-               if (multiplexers[i]->clk == clk) {
-                       m = multiplexers[i];
-                       break;
-               }
-       if (i == num)
-               return -EINVAL;
-
-       i = 0;
-       while (m->parents[i]) {
-               if (parent == m->parents[i])
-                       break;
-               i++;
-       }
-       if (!m->parents[i] || m->parents[i] == &dummy_clk)
-               return -EINVAL;
-
-       val = readl_relaxed(m->reg);
-       val &= ~m->bm;
-       val |= i << m->bp;
-       writel_relaxed(val, m->reg);
-
-       if (clk == &periph_clk)
-               return clk_busy_wait(clk);
-
-       return 0;
-}
-
-#define DEF_NG_CLK(name, p)                            \
-       static struct clk name = {                      \
-               .get_rate       = _clk_get_rate,        \
-               .set_rate       = _clk_set_rate,        \
-               .round_rate     = _clk_round_rate,      \
-               .set_parent     = _clk_set_parent,      \
-               .parent         = p,                    \
-       }
-
-DEF_NG_CLK(periph_clk2_clk,    &osc_clk);
-DEF_NG_CLK(periph_pre_clk,     &pll2_bus);
-DEF_NG_CLK(periph_clk,         &periph_pre_clk);
-DEF_NG_CLK(periph2_clk2_clk,   &osc_clk);
-DEF_NG_CLK(periph2_pre_clk,    &pll2_bus);
-DEF_NG_CLK(periph2_clk,                &periph2_pre_clk);
-DEF_NG_CLK(axi_clk,            &periph_clk);
-DEF_NG_CLK(emi_clk,            &axi_clk);
-DEF_NG_CLK(arm_clk,            &pll1_sw_clk);
-DEF_NG_CLK(ahb_clk,            &periph_clk);
-DEF_NG_CLK(ipg_clk,            &ahb_clk);
-DEF_NG_CLK(ipg_perclk,         &ipg_clk);
-DEF_NG_CLK(ipu1_di0_pre_clk,   &pll3_pfd_540m);
-DEF_NG_CLK(ipu1_di1_pre_clk,   &pll3_pfd_540m);
-DEF_NG_CLK(ipu2_di0_pre_clk,   &pll3_pfd_540m);
-DEF_NG_CLK(ipu2_di1_pre_clk,   &pll3_pfd_540m);
-DEF_NG_CLK(asrc_serial_clk,    &pll3_usb_otg);
-
-#define DEF_CLK(name, er, es, p, s)                    \
-       static struct clk name = {                      \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .enable         = _clk_enable,          \
-               .disable        = _clk_disable,         \
-               .get_rate       = _clk_get_rate,        \
-               .set_rate       = _clk_set_rate,        \
-               .round_rate     = _clk_round_rate,      \
-               .set_parent     = _clk_set_parent,      \
-               .parent         = p,                    \
-               .secondary      = s,                    \
-       }
-
-#define DEF_CLK_1B(name, er, es, p, s)                 \
-       static struct clk name = {                      \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .enable         = _clk_enable_1b,       \
-               .disable        = _clk_disable_1b,      \
-               .get_rate       = _clk_get_rate,        \
-               .set_rate       = _clk_set_rate,        \
-               .round_rate     = _clk_round_rate,      \
-               .set_parent     = _clk_set_parent,      \
-               .parent         = p,                    \
-               .secondary      = s,                    \
-       }
-
-DEF_CLK(aips_tz1_clk,    CCGR0, CG0,  &ahb_clk,          NULL);
-DEF_CLK(aips_tz2_clk,    CCGR0, CG1,  &ahb_clk,          NULL);
-DEF_CLK(apbh_dma_clk,    CCGR0, CG2,  &ahb_clk,          NULL);
-DEF_CLK(asrc_clk,        CCGR0, CG3,  &pll4_audio,       NULL);
-DEF_CLK(can1_serial_clk,  CCGR0, CG8,  &pll3_usb_otg,    NULL);
-DEF_CLK(can1_clk,        CCGR0, CG7,  &pll3_usb_otg,     &can1_serial_clk);
-DEF_CLK(can2_serial_clk,  CCGR0, CG10, &pll3_usb_otg,    NULL);
-DEF_CLK(can2_clk,        CCGR0, CG9,  &pll3_usb_otg,     &can2_serial_clk);
-DEF_CLK(ecspi1_clk,      CCGR1, CG0,  &pll3_60m,         NULL);
-DEF_CLK(ecspi2_clk,      CCGR1, CG1,  &pll3_60m,         NULL);
-DEF_CLK(ecspi3_clk,      CCGR1, CG2,  &pll3_60m,         NULL);
-DEF_CLK(ecspi4_clk,      CCGR1, CG3,  &pll3_60m,         NULL);
-DEF_CLK(ecspi5_clk,      CCGR1, CG4,  &pll3_60m,         NULL);
-DEF_CLK(enet_clk,        CCGR1, CG5,  &ipg_clk,          NULL);
-DEF_CLK(esai_clk,        CCGR1, CG8,  &pll3_usb_otg,     NULL);
-DEF_CLK(gpt_serial_clk,          CCGR1, CG11, &ipg_perclk,       NULL);
-DEF_CLK(gpt_clk,         CCGR1, CG10, &ipg_perclk,       &gpt_serial_clk);
-DEF_CLK(gpu2d_core_clk,          CCGR1, CG12, &pll2_pfd_352m,    &gpu2d_axi_clk);
-DEF_CLK(gpu3d_core_clk,          CCGR1, CG13, &pll2_pfd_594m,    &gpu3d_axi_clk);
-DEF_CLK(gpu3d_shader_clk, CCGR1, CG13, &pll3_pfd_720m,   &gpu3d_axi_clk);
-DEF_CLK(hdmi_iahb_clk,   CCGR2, CG0,  &ahb_clk,          NULL);
-DEF_CLK(hdmi_isfr_clk,   CCGR2, CG2,  &pll3_pfd_540m,    &hdmi_iahb_clk);
-DEF_CLK(i2c1_clk,        CCGR2, CG3,  &ipg_perclk,       NULL);
-DEF_CLK(i2c2_clk,        CCGR2, CG4,  &ipg_perclk,       NULL);
-DEF_CLK(i2c3_clk,        CCGR2, CG5,  &ipg_perclk,       NULL);
-DEF_CLK(iim_clk,         CCGR2, CG6,  &ipg_clk,          NULL);
-DEF_CLK(enfc_clk,        CCGR2, CG7,  &pll2_pfd_352m,    NULL);
-DEF_CLK(ipu1_clk,        CCGR3, CG0,  &mmdc_ch0_axi_clk, NULL);
-DEF_CLK(ipu1_di0_clk,    CCGR3, CG1,  &ipu1_di0_pre_clk, NULL);
-DEF_CLK(ipu1_di1_clk,    CCGR3, CG2,  &ipu1_di1_pre_clk, NULL);
-DEF_CLK(ipu2_clk,        CCGR3, CG3,  &mmdc_ch0_axi_clk, NULL);
-DEF_CLK(ipu2_di0_clk,    CCGR3, CG4,  &ipu2_di0_pre_clk, NULL);
-DEF_CLK(ipu2_di1_clk,    CCGR3, CG5,  &ipu2_di1_pre_clk, NULL);
-DEF_CLK(ldb_di0_clk,     CCGR3, CG6,  &pll3_pfd_540m,    NULL);
-DEF_CLK(ldb_di1_clk,     CCGR3, CG7,  &pll3_pfd_540m,    NULL);
-DEF_CLK(hsi_tx_clk,      CCGR3, CG8,  &pll2_pfd_400m,    NULL);
-DEF_CLK(mlb_clk,         CCGR3, CG9,  &pll6_mlb,         NULL);
-DEF_CLK(mmdc_ch0_ipg_clk, CCGR3, CG12, &ipg_clk,         NULL);
-DEF_CLK(mmdc_ch0_axi_clk, CCGR3, CG10, &periph_clk,      &mmdc_ch0_ipg_clk);
-DEF_CLK(mmdc_ch1_ipg_clk, CCGR3, CG13, &ipg_clk,         NULL);
-DEF_CLK(mmdc_ch1_axi_clk, CCGR3, CG11, &periph2_clk,     &mmdc_ch1_ipg_clk);
-DEF_CLK(openvg_axi_clk,   CCGR3, CG13, &axi_clk,         NULL);
-DEF_CLK(pwm1_clk,        CCGR4, CG8,  &ipg_perclk,       NULL);
-DEF_CLK(pwm2_clk,        CCGR4, CG9,  &ipg_perclk,       NULL);
-DEF_CLK(pwm3_clk,        CCGR4, CG10, &ipg_perclk,       NULL);
-DEF_CLK(pwm4_clk,        CCGR4, CG11, &ipg_perclk,       NULL);
-DEF_CLK(gpmi_bch_apb_clk, CCGR4, CG12, &usdhc3_clk,      NULL);
-DEF_CLK(gpmi_bch_clk,    CCGR4, CG13, &usdhc4_clk,       &gpmi_bch_apb_clk);
-DEF_CLK(gpmi_apb_clk,    CCGR4, CG15, &usdhc3_clk,       &gpmi_bch_clk);
-DEF_CLK(gpmi_io_clk,     CCGR4, CG14, &enfc_clk,         &gpmi_apb_clk);
-DEF_CLK(sdma_clk,        CCGR5, CG3,  &ahb_clk,          NULL);
-DEF_CLK(spba_clk,        CCGR5, CG6,  &ipg_clk,          NULL);
-DEF_CLK(spdif_clk,       CCGR5, CG7,  &pll3_usb_otg,     &spba_clk);
-DEF_CLK(ssi1_clk,        CCGR5, CG9,  &pll3_pfd_508m,    NULL);
-DEF_CLK(ssi2_clk,        CCGR5, CG10, &pll3_pfd_508m,    NULL);
-DEF_CLK(ssi3_clk,        CCGR5, CG11, &pll3_pfd_508m,    NULL);
-DEF_CLK(uart_serial_clk,  CCGR5, CG13, &pll3_usb_otg,    NULL);
-DEF_CLK(uart_clk,        CCGR5, CG12, &pll3_80m,         &uart_serial_clk);
-DEF_CLK(usboh3_clk,      CCGR6, CG0,  &ipg_clk,          NULL);
-DEF_CLK(usdhc1_clk,      CCGR6, CG1,  &pll2_pfd_400m,    NULL);
-DEF_CLK(usdhc2_clk,      CCGR6, CG2,  &pll2_pfd_400m,    NULL);
-DEF_CLK(usdhc3_clk,      CCGR6, CG3,  &pll2_pfd_400m,    NULL);
-DEF_CLK(usdhc4_clk,      CCGR6, CG4,  &pll2_pfd_400m,    NULL);
-DEF_CLK(emi_slow_clk,    CCGR6, CG5,  &axi_clk,          NULL);
-DEF_CLK(vdo_axi_clk,     CCGR6, CG6,  &axi_clk,          NULL);
-DEF_CLK(vpu_clk,         CCGR6, CG7,  &axi_clk,          NULL);
-DEF_CLK_1B(cko1_clk,     CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL);
-
-static int pcie_clk_enable(struct clk *clk)
-{
-       u32 val;
-
-       val = readl_relaxed(PLL8_ENET);
-       val |= BM_PLL_ENET_EN_PCIE;
-       writel_relaxed(val, PLL8_ENET);
-
-       return _clk_enable(clk);
-}
-
-static void pcie_clk_disable(struct clk *clk)
-{
-       u32 val;
-
-       _clk_disable(clk);
-
-       val = readl_relaxed(PLL8_ENET);
-       val &= BM_PLL_ENET_EN_PCIE;
-       writel_relaxed(val, PLL8_ENET);
-}
-
-static struct clk pcie_clk = {
-       .enable_reg = CCGR4,
-       .enable_shift = CG0,
-       .enable = pcie_clk_enable,
-       .disable = pcie_clk_disable,
-       .set_parent = _clk_set_parent,
-       .parent = &axi_clk,
-       .secondary = &pll8_enet,
-};
-
-static int sata_clk_enable(struct clk *clk)
-{
-       u32 val;
-
-       val = readl_relaxed(PLL8_ENET);
-       val |= BM_PLL_ENET_EN_SATA;
-       writel_relaxed(val, PLL8_ENET);
-
-       return _clk_enable(clk);
-}
-
-static void sata_clk_disable(struct clk *clk)
-{
-       u32 val;
-
-       _clk_disable(clk);
-
-       val = readl_relaxed(PLL8_ENET);
-       val &= BM_PLL_ENET_EN_SATA;
-       writel_relaxed(val, PLL8_ENET);
-}
-
-static struct clk sata_clk = {
-       .enable_reg = CCGR5,
-       .enable_shift = CG2,
-       .enable = sata_clk_enable,
-       .disable = sata_clk_disable,
-       .parent = &ipg_clk,
-       .secondary = &pll8_enet,
-};
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c, \
-       }
-
-static struct clk_lookup lookups[] = {
-       _REGISTER_CLOCK("2020000.uart", NULL, uart_clk),
-       _REGISTER_CLOCK("21e8000.uart", NULL, uart_clk),
-       _REGISTER_CLOCK("21ec000.uart", NULL, uart_clk),
-       _REGISTER_CLOCK("21f0000.uart", NULL, uart_clk),
-       _REGISTER_CLOCK("21f4000.uart", NULL, uart_clk),
-       _REGISTER_CLOCK("2188000.enet", NULL, enet_clk),
-       _REGISTER_CLOCK("2190000.usdhc", NULL, usdhc1_clk),
-       _REGISTER_CLOCK("2194000.usdhc", NULL, usdhc2_clk),
-       _REGISTER_CLOCK("2198000.usdhc", NULL, usdhc3_clk),
-       _REGISTER_CLOCK("219c000.usdhc", NULL, usdhc4_clk),
-       _REGISTER_CLOCK("21a0000.i2c", NULL, i2c1_clk),
-       _REGISTER_CLOCK("21a4000.i2c", NULL, i2c2_clk),
-       _REGISTER_CLOCK("21a8000.i2c", NULL, i2c3_clk),
-       _REGISTER_CLOCK("2008000.ecspi", NULL, ecspi1_clk),
-       _REGISTER_CLOCK("200c000.ecspi", NULL, ecspi2_clk),
-       _REGISTER_CLOCK("2010000.ecspi", NULL, ecspi3_clk),
-       _REGISTER_CLOCK("2014000.ecspi", NULL, ecspi4_clk),
-       _REGISTER_CLOCK("2018000.ecspi", NULL, ecspi5_clk),
-       _REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
-       _REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
-       _REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
-       _REGISTER_CLOCK("smp_twd", NULL, twd_clk),
-       _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
-       _REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
-       _REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
-       _REGISTER_CLOCK(NULL, "aips_tz2_clk", aips_tz2_clk),
-       _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk),
-       _REGISTER_CLOCK(NULL, "can2_clk", can2_clk),
-       _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_isfr_clk),
-       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
-       _REGISTER_CLOCK(NULL, "mlb_clk", mlb_clk),
-       _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
-       _REGISTER_CLOCK(NULL, "pwm1_clk", pwm1_clk),
-       _REGISTER_CLOCK(NULL, "pwm2_clk", pwm2_clk),
-       _REGISTER_CLOCK(NULL, "pwm3_clk", pwm3_clk),
-       _REGISTER_CLOCK(NULL, "pwm4_clk", pwm4_clk),
-       _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
-       _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
-       _REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
-       _REGISTER_CLOCK(NULL, "cko1_clk", cko1_clk),
-};
-
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-{
-       u32 val = readl_relaxed(CLPCR);
-
-       val &= ~BM_CLPCR_LPM;
-       switch (mode) {
-       case WAIT_CLOCKED:
-               break;
-       case WAIT_UNCLOCKED:
-               val |= 0x1 << BP_CLPCR_LPM;
-               break;
-       case STOP_POWER_ON:
-               val |= 0x2 << BP_CLPCR_LPM;
-               break;
-       case WAIT_UNCLOCKED_POWER_OFF:
-               val |= 0x1 << BP_CLPCR_LPM;
-               val &= ~BM_CLPCR_VSTBY;
-               val &= ~BM_CLPCR_SBYOS;
-               break;
-       case STOP_POWER_OFF:
-               val |= 0x2 << BP_CLPCR_LPM;
-               val |= 0x3 << BP_CLPCR_STBY_COUNT;
-               val |= BM_CLPCR_VSTBY;
-               val |= BM_CLPCR_SBYOS;
-               break;
-       default:
-               return -EINVAL;
-       }
-       writel_relaxed(val, CLPCR);
-
-       return 0;
-}
-
-static struct map_desc imx6q_clock_desc[] = {
-       imx_map_entry(MX6Q, CCM, MT_DEVICE),
-       imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
-};
-
-void __init imx6q_clock_map_io(void)
-{
-       iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
-}
-
-int __init mx6q_clocks_init(void)
-{
-       struct device_node *np;
-       void __iomem *base;
-       int i, irq;
-
-       /* retrieve the freqency of fixed clocks from device tree */
-       for_each_compatible_node(np, NULL, "fixed-clock") {
-               u32 rate;
-               if (of_property_read_u32(np, "clock-frequency", &rate))
-                       continue;
-
-               if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                       external_low_reference = rate;
-               else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                       external_high_reference = rate;
-               else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                       oscillator_reference = rate;
-       }
-
-       for (i = 0; i < ARRAY_SIZE(lookups); i++)
-               clkdev_add(&lookups[i]);
-
-       /* only keep necessary clocks on */
-       writel_relaxed(0x3 << CG0  | 0x3 << CG1  | 0x3 << CG2,  CCGR0);
-       writel_relaxed(0x3 << CG8  | 0x3 << CG9  | 0x3 << CG10, CCGR2);
-       writel_relaxed(0x3 << CG10 | 0x3 << CG12,               CCGR3);
-       writel_relaxed(0x3 << CG4  | 0x3 << CG6  | 0x3 << CG7,  CCGR4);
-       writel_relaxed(0x3 << CG0,                              CCGR5);
-       writel_relaxed(0,                                       CCGR6);
-       writel_relaxed(0,                                       CCGR7);
-
-       clk_enable(&uart_clk);
-       clk_enable(&mmdc_ch0_axi_clk);
-
-       clk_set_rate(&pll4_audio, FREQ_650M);
-       clk_set_rate(&pll5_video, FREQ_650M);
-       clk_set_parent(&ipu1_di0_clk, &ipu1_di0_pre_clk);
-       clk_set_parent(&ipu1_di0_pre_clk, &pll5_video);
-       clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594m);
-       clk_set_rate(&gpu3d_shader_clk, FREQ_594M);
-       clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk);
-       clk_set_rate(&gpu3d_core_clk, FREQ_528M);
-       clk_set_parent(&asrc_serial_clk, &pll3_usb_otg);
-       clk_set_rate(&asrc_serial_clk, 1500000);
-       clk_set_rate(&enfc_clk, 11000000);
-
-       /*
-        * Before pinctrl API is available, we have to rely on the pad
-        * configuration set up by bootloader.  For usdhc example here,
-        * u-boot sets up the pads for 49.5 MHz case, and we have to lower
-        * the usdhc clock from 198 to 49.5 MHz to match the pad configuration.
-        *
-        * FIXME: This is should be removed after pinctrl API is available.
-        * At that time, usdhc driver can call pinctrl API to change pad
-        * configuration dynamically per different usdhc clock settings.
-        */
-       clk_set_rate(&usdhc1_clk, 49500000);
-       clk_set_rate(&usdhc2_clk, 49500000);
-       clk_set_rate(&usdhc3_clk, 49500000);
-       clk_set_rate(&usdhc4_clk, 49500000);
-
-       clk_set_parent(&cko1_clk, &ahb_clk);
-
-       np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
-       base = of_iomap(np, 0);
-       WARN_ON(!base);
-       irq = irq_of_parse_and_map(np, 0);
-       mxc_timer_init(&gpt_clk, base, irq);
-
-       return 0;
-}

diff --git a/arch/arm/mach-imx/clock-mx51-mx53.c b/arch/arm/mach-imx/clock-mx51-mx53.c
deleted file mode 100644 (file)
index 0847050..0000000
--- a/arch/arm/mach-imx/clock-mx51-mx53.c
+++ /dev/null
@@ -1,1675 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/of.h>
-
-#include <asm/div64.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-
-#include "crm-regs-imx5.h"
-
-/* External clock values passed-in by the board code */
-static unsigned long external_high_reference, external_low_reference;
-static unsigned long oscillator_reference, ckih2_reference;
-
-static struct clk osc_clk;
-static struct clk pll1_main_clk;
-static struct clk pll1_sw_clk;
-static struct clk pll2_sw_clk;
-static struct clk pll3_sw_clk;
-static struct clk mx53_pll4_sw_clk;
-static struct clk lp_apm_clk;
-static struct clk periph_apm_clk;
-static struct clk ahb_clk;
-static struct clk ipg_clk;
-static struct clk usboh3_clk;
-static struct clk emi_fast_clk;
-static struct clk ipu_clk;
-static struct clk mipi_hsc1_clk;
-static struct clk esdhc1_clk;
-static struct clk esdhc2_clk;
-static struct clk esdhc3_mx53_clk;
-
-#define MAX_DPLL_WAIT_TRIES    1000 /* 1000 * udelay(1) = 1ms */
-
-/* calculate best pre and post dividers to get the required divider */
-static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
-       u32 max_pre, u32 max_post)
-{
-       if (div >= max_pre * max_post) {
-               *pre = max_pre;
-               *post = max_post;
-       } else if (div >= max_pre) {
-               u32 min_pre, temp_pre, old_err, err;
-               min_pre = DIV_ROUND_UP(div, max_post);
-               old_err = max_pre;
-               for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
-                       err = div % temp_pre;
-                       if (err == 0) {
-                               *pre = temp_pre;
-                               break;
-                       }
-                       err = temp_pre - err;
-                       if (err < old_err) {
-                               old_err = err;
-                               *pre = temp_pre;
-                       }
-               }
-               *post = DIV_ROUND_UP(div, *pre);
-       } else {
-               *pre = div;
-               *post = 1;
-       }
-}
-
-static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
-{
-       u32 reg = __raw_readl(clk->enable_reg);
-
-       reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-       reg |= mode << clk->enable_shift;
-
-       __raw_writel(reg, clk->enable_reg);
-}
-
-static int _clk_ccgr_enable(struct clk *clk)
-{
-       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
-       return 0;
-}
-
-static void _clk_ccgr_disable(struct clk *clk)
-{
-       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
-}
-
-static int _clk_ccgr_enable_inrun(struct clk *clk)
-{
-       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
-       return 0;
-}
-
-static void _clk_ccgr_disable_inwait(struct clk *clk)
-{
-       _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
-}
-
-/*
- * For the 4-to-1 muxed input clock
- */
-static inline u32 _get_mux(struct clk *parent, struct clk *m0,
-                          struct clk *m1, struct clk *m2, struct clk *m3)
-{
-       if (parent == m0)
-               return 0;
-       else if (parent == m1)
-               return 1;
-       else if (parent == m2)
-               return 2;
-       else if (parent == m3)
-               return 3;
-       else
-               BUG();
-
-       return -EINVAL;
-}
-
-static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
-{
-       if (pll == &pll1_main_clk)
-               return MX51_DPLL1_BASE;
-       else if (pll == &pll2_sw_clk)
-               return MX51_DPLL2_BASE;
-       else if (pll == &pll3_sw_clk)
-               return MX51_DPLL3_BASE;
-       else
-               BUG();
-
-       return NULL;
-}
-
-static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
-{
-       if (pll == &pll1_main_clk)
-               return MX53_DPLL1_BASE;
-       else if (pll == &pll2_sw_clk)
-               return MX53_DPLL2_BASE;
-       else if (pll == &pll3_sw_clk)
-               return MX53_DPLL3_BASE;
-       else if (pll == &mx53_pll4_sw_clk)
-               return MX53_DPLL4_BASE;
-       else
-               BUG();
-
-       return NULL;
-}
-
-static inline void __iomem *_get_pll_base(struct clk *pll)
-{
-       if (cpu_is_mx51())
-               return _mx51_get_pll_base(pll);
-       else
-               return _mx53_get_pll_base(pll);
-}
-
-static unsigned long clk_pll_get_rate(struct clk *clk)
-{
-       long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
-       unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
-       void __iomem *pllbase;
-       s64 temp;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       pllbase = _get_pll_base(clk);
-
-       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
-       dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
-
-       if (pll_hfsm == 0) {
-               dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
-               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
-               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
-       } else {
-               dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
-               dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
-               dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
-       }
-       pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
-       mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
-       mfi = (mfi <= 5) ? 5 : mfi;
-       mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
-       mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
-       /* Sign extend to 32-bits */
-       if (mfn >= 0x04000000) {
-               mfn |= 0xFC000000;
-               mfn_abs = -mfn;
-       }
-
-       ref_clk = 2 * parent_rate;
-       if (dbl != 0)
-               ref_clk *= 2;
-
-       ref_clk /= (pdf + 1);
-       temp = (u64) ref_clk * mfn_abs;
-       do_div(temp, mfd + 1);
-       if (mfn < 0)
-               temp = -temp;
-       temp = (ref_clk * mfi) + temp;
-
-       return temp;
-}
-
-static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg;
-       void __iomem *pllbase;
-
-       long mfi, pdf, mfn, mfd = 999999;
-       s64 temp64;
-       unsigned long quad_parent_rate;
-       unsigned long pll_hfsm, dp_ctl;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       pllbase = _get_pll_base(clk);
-
-       quad_parent_rate = 4 * parent_rate;
-       pdf = mfi = -1;
-       while (++pdf < 16 && mfi < 5)
-               mfi = rate * (pdf+1) / quad_parent_rate;
-       if (mfi > 15)
-               return -EINVAL;
-       pdf--;
-
-       temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
-       do_div(temp64, quad_parent_rate/1000000);
-       mfn = (long)temp64;
-
-       dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-       /* use dpdck0_2 */
-       __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
-       pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
-       if (pll_hfsm == 0) {
-               reg = mfi << 4 | pdf;
-               __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
-               __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
-               __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
-       } else {
-               reg = mfi << 4 | pdf;
-               __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
-               __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
-               __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
-       }
-
-       return 0;
-}
-
-static int _clk_pll_enable(struct clk *clk)
-{
-       u32 reg;
-       void __iomem *pllbase;
-       int i = 0;
-
-       pllbase = _get_pll_base(clk);
-       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-       if (reg & MXC_PLL_DP_CTL_UPEN)
-               return 0;
-
-       reg |= MXC_PLL_DP_CTL_UPEN;
-       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-
-       /* Wait for lock */
-       do {
-               reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-               if (reg & MXC_PLL_DP_CTL_LRF)
-                       break;
-
-               udelay(1);
-       } while (++i < MAX_DPLL_WAIT_TRIES);
-
-       if (i == MAX_DPLL_WAIT_TRIES) {
-               pr_err("MX5: pll locking failed\n");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static void _clk_pll_disable(struct clk *clk)
-{
-       u32 reg;
-       void __iomem *pllbase;
-
-       pllbase = _get_pll_base(clk);
-       reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
-       __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
-}
-
-static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg, step;
-
-       reg = __raw_readl(MXC_CCM_CCSR);
-
-       /* When switching from pll_main_clk to a bypass clock, first select a
-        * multiplexed clock in 'step_sel', then shift the glitchless mux
-        * 'pll1_sw_clk_sel'.
-        *
-        * When switching back, do it in reverse order
-        */
-       if (parent == &pll1_main_clk) {
-               /* Switch to pll1_main_clk */
-               reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-               __raw_writel(reg, MXC_CCM_CCSR);
-               /* step_clk mux switched to lp_apm, to save power. */
-               reg = __raw_readl(MXC_CCM_CCSR);
-               reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
-               reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
-                               MXC_CCM_CCSR_STEP_SEL_OFFSET);
-       } else {
-               if (parent == &lp_apm_clk) {
-                       step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
-               } else  if (parent == &pll2_sw_clk) {
-                       step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
-               } else  if (parent == &pll3_sw_clk) {
-                       step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
-               } else
-                       return -EINVAL;
-
-               reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
-               reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
-
-               __raw_writel(reg, MXC_CCM_CCSR);
-               /* Switch to step_clk */
-               reg = __raw_readl(MXC_CCM_CCSR);
-               reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
-       }
-       __raw_writel(reg, MXC_CCM_CCSR);
-       return 0;
-}
-
-static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
-{
-       u32 reg, div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(MXC_CCM_CCSR);
-
-       if (clk->parent == &pll2_sw_clk) {
-               div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
-                      MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
-       } else if (clk->parent == &pll3_sw_clk) {
-               div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
-                      MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
-       } else
-               div = 1;
-       return parent_rate / div;
-}
-
-static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CCSR);
-
-       if (parent == &pll2_sw_clk)
-               reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
-       else
-               reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
-
-       __raw_writel(reg, MXC_CCM_CCSR);
-       return 0;
-}
-
-static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       if (parent == &osc_clk)
-               reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
-       else
-               return -EINVAL;
-
-       __raw_writel(reg, MXC_CCM_CCSR);
-
-       return 0;
-}
-
-static unsigned long clk_cpu_get_rate(struct clk *clk)
-{
-       u32 cacrr, div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-       cacrr = __raw_readl(MXC_CCM_CACRR);
-       div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
-
-       return parent_rate / div;
-}
-
-static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, cpu_podf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-       cpu_podf = parent_rate / rate - 1;
-       /* use post divider to change freq */
-       reg = __raw_readl(MXC_CCM_CACRR);
-       reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
-       reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
-       __raw_writel(reg, MXC_CCM_CACRR);
-
-       return 0;
-}
-
-static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg, mux;
-       int i = 0;
-
-       mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
-
-       reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
-       reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
-       __raw_writel(reg, MXC_CCM_CBCMR);
-
-       /* Wait for lock */
-       do {
-               reg = __raw_readl(MXC_CCM_CDHIPR);
-               if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
-                       break;
-
-               udelay(1);
-       } while (++i < MAX_DPLL_WAIT_TRIES);
-
-       if (i == MAX_DPLL_WAIT_TRIES) {
-               pr_err("MX5: Set parent for periph_apm clock failed\n");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-
-       if (parent == &pll2_sw_clk)
-               reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-       else if (parent == &periph_apm_clk)
-               reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
-       else
-               return -EINVAL;
-
-       __raw_writel(reg, MXC_CCM_CBCDR);
-
-       return 0;
-}
-
-static struct clk main_bus_clk = {
-       .parent = &pll2_sw_clk,
-       .set_parent = _clk_main_bus_set_parent,
-};
-
-static unsigned long clk_ahb_get_rate(struct clk *clk)
-{
-       u32 reg, div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-              MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
-       return parent_rate / div;
-}
-
-
-static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, div;
-       unsigned long parent_rate;
-       int i = 0;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-               return -EINVAL;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
-       reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-       __raw_writel(reg, MXC_CCM_CBCDR);
-
-       /* Wait for lock */
-       do {
-               reg = __raw_readl(MXC_CCM_CDHIPR);
-               if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
-                       break;
-
-               udelay(1);
-       } while (++i < MAX_DPLL_WAIT_TRIES);
-
-       if (i == MAX_DPLL_WAIT_TRIES) {
-               pr_err("MX5: clk_ahb_set_rate failed\n");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static unsigned long _clk_ahb_round_rate(struct clk *clk,
-                                               unsigned long rate)
-{
-       u32 div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       div = parent_rate / rate;
-       if (div > 8)
-               div = 8;
-       else if (div == 0)
-               div++;
-       return parent_rate / div;
-}
-
-
-static int _clk_max_enable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_enable(clk);
-
-       /* Handshake with MAX when LPM is entered. */
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       if (cpu_is_mx51())
-               reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-       else if (cpu_is_mx53())
-               reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-
-       return 0;
-}
-
-static void _clk_max_disable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_disable_inwait(clk);
-
-       /* No Handshake with MAX when LPM is entered as its disabled. */
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       if (cpu_is_mx51())
-               reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-       else if (cpu_is_mx53())
-               reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static unsigned long clk_ipg_get_rate(struct clk *clk)
-{
-       u32 reg, div;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-              MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
-
-       return parent_rate / div;
-}
-
-static unsigned long clk_ipg_per_get_rate(struct clk *clk)
-{
-       u32 reg, prediv1, prediv2, podf;
-       unsigned long parent_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
-               /* the main_bus_clk is the one before the DVFS engine */
-               reg = __raw_readl(MXC_CCM_CBCDR);
-               prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-                          MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
-               prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-                          MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
-               podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-                       MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
-               return parent_rate / (prediv1 * prediv2 * podf);
-       } else if (clk->parent == &ipg_clk)
-               return parent_rate;
-       else
-               BUG();
-}
-
-static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CBCMR);
-
-       reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
-       reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
-
-       if (parent == &ipg_clk)
-               reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
-       else if (parent == &lp_apm_clk)
-               reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
-       else if (parent != &main_bus_clk)
-               return -EINVAL;
-
-       __raw_writel(reg, MXC_CCM_CBCMR);
-
-       return 0;
-}
-
-#define clk_nfc_set_parent     NULL
-
-static unsigned long clk_nfc_get_rate(struct clk *clk)
-{
-       unsigned long rate;
-       u32 reg, div;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
-              MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
-       rate = clk_get_rate(clk->parent) / div;
-       WARN_ON(rate == 0);
-       return rate;
-}
-
-static unsigned long clk_nfc_round_rate(struct clk *clk,
-                                               unsigned long rate)
-{
-       u32 div;
-       unsigned long parent_rate = clk_get_rate(clk->parent);
-
-       if (!rate)
-               return -EINVAL;
-
-       div = parent_rate / rate;
-
-       if (parent_rate % rate)
-               div++;
-
-       if (div > 8)
-               return -EINVAL;
-
-       return parent_rate / div;
-
-}
-
-static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, div;
-
-       div = clk_get_rate(clk->parent) / rate;
-       if (div == 0)
-               div++;
-       if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
-               return -EINVAL;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
-       reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
-       __raw_writel(reg, MXC_CCM_CBCDR);
-
-       while (__raw_readl(MXC_CCM_CDHIPR) &
-                       MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
-       }
-
-       return 0;
-}
-
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
-{
-       return external_high_reference;
-}
-
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
-{
-       return external_low_reference;
-}
-
-static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
-{
-       return oscillator_reference;
-}
-
-static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
-{
-       return ckih2_reference;
-}
-
-static unsigned long clk_emi_slow_get_rate(struct clk *clk)
-{
-       u32 reg, div;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
-              MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
-
-       return clk_get_rate(clk->parent) / div;
-}
-
-static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
-{
-       unsigned long rate;
-       u32 reg, div;
-
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
-               MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
-       rate = clk_get_rate(clk->parent) / div;
-
-       return rate;
-}
-
-/* External high frequency clock */
-static struct clk ckih_clk = {
-       .get_rate = get_high_reference_clock_rate,
-};
-
-static struct clk ckih2_clk = {
-       .get_rate = get_ckih2_reference_clock_rate,
-};
-
-static struct clk osc_clk = {
-       .get_rate = get_oscillator_reference_clock_rate,
-};
-
-/* External low frequency (32kHz) clock */
-static struct clk ckil_clk = {
-       .get_rate = get_low_reference_clock_rate,
-};
-
-static struct clk pll1_main_clk = {
-       .parent = &osc_clk,
-       .get_rate = clk_pll_get_rate,
-       .enable = _clk_pll_enable,
-       .disable = _clk_pll_disable,
-};
-
-/* Clock tree block diagram (WIP):
- *     CCM: Clock Controller Module
- *
- * PLL output -> |
- *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
- * PLL bypass -> |
- *
- */
-
-/* PLL1 SW supplies to ARM core */
-static struct clk pll1_sw_clk = {
-       .parent = &pll1_main_clk,
-       .set_parent = _clk_pll1_sw_set_parent,
-       .get_rate = clk_pll1_sw_get_rate,
-};
-
-/* PLL2 SW supplies to AXI/AHB/IP buses */
-static struct clk pll2_sw_clk = {
-       .parent = &osc_clk,
-       .get_rate = clk_pll_get_rate,
-       .set_rate = _clk_pll_set_rate,
-       .set_parent = _clk_pll2_sw_set_parent,
-       .enable = _clk_pll_enable,
-       .disable = _clk_pll_disable,
-};
-
-/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
-static struct clk pll3_sw_clk = {
-       .parent = &osc_clk,
-       .set_rate = _clk_pll_set_rate,
-       .get_rate = clk_pll_get_rate,
-       .enable = _clk_pll_enable,
-       .disable = _clk_pll_disable,
-};
-
-/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
-static struct clk mx53_pll4_sw_clk = {
-       .parent = &osc_clk,
-       .set_rate = _clk_pll_set_rate,
-       .enable = _clk_pll_enable,
-       .disable = _clk_pll_disable,
-};
-
-/* Low-power Audio Playback Mode clock */
-static struct clk lp_apm_clk = {
-       .parent = &osc_clk,
-       .set_parent = _clk_lp_apm_set_parent,
-};
-
-static struct clk periph_apm_clk = {
-       .parent = &pll1_sw_clk,
-       .set_parent = _clk_periph_apm_set_parent,
-};
-
-static struct clk cpu_clk = {
-       .parent = &pll1_sw_clk,
-       .get_rate = clk_cpu_get_rate,
-       .set_rate = clk_cpu_set_rate,
-};
-
-static struct clk ahb_clk = {
-       .parent = &main_bus_clk,
-       .get_rate = clk_ahb_get_rate,
-       .set_rate = _clk_ahb_set_rate,
-       .round_rate = _clk_ahb_round_rate,
-};
-
-static struct clk iim_clk = {
-       .parent = &ipg_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
-};
-
-/* Main IP interface clock for access to registers */
-static struct clk ipg_clk = {
-       .parent = &ahb_clk,
-       .get_rate = clk_ipg_get_rate,
-};
-
-static struct clk ipg_perclk = {
-       .parent = &lp_apm_clk,
-       .get_rate = clk_ipg_per_get_rate,
-       .set_parent = _clk_ipg_per_set_parent,
-};
-
-static struct clk ahb_max_clk = {
-       .parent = &ahb_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
-       .enable = _clk_max_enable,
-       .disable = _clk_max_disable,
-};
-
-static struct clk aips_tz1_clk = {
-       .parent = &ahb_clk,
-       .secondary = &ahb_max_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk aips_tz2_clk = {
-       .parent = &ahb_clk,
-       .secondary = &ahb_max_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk gpc_dvfs_clk = {
-       .enable_reg = MXC_CCM_CCGR5,
-       .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable,
-};
-
-static struct clk gpt_32k_clk = {
-       .id = 0,
-       .parent = &ckil_clk,
-};
-
-static struct clk dummy_clk = {
-       .id = 0,
-};
-
-static struct clk emi_slow_clk = {
-       .parent = &pll2_sw_clk,
-       .enable_reg = MXC_CCM_CCGR5,
-       .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable_inwait,
-       .get_rate = clk_emi_slow_get_rate,
-};
-
-static int clk_ipu_enable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_enable(clk);
-
-       /* Enable handshake with IPU when certain clock rates are changed */
-       reg = __raw_readl(MXC_CCM_CCDR);
-       reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
-       __raw_writel(reg, MXC_CCM_CCDR);
-
-       /* Enable handshake with IPU when LPM is entered */
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-
-       return 0;
-}
-
-static void clk_ipu_disable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_disable(clk);
-
-       /* Disable handshake with IPU whe dividers are changed */
-       reg = __raw_readl(MXC_CCM_CCDR);
-       reg |= MXC_CCM_CCDR_IPU_HS_MASK;
-       __raw_writel(reg, MXC_CCM_CCDR);
-
-       /* Disable handshake with IPU when LPM is entered */
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static struct clk ahbmux1_clk = {
-       .parent = &ahb_clk,
-       .secondary = &ahb_max_clk,
-       .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable_inwait,
-};
-
-static struct clk ipu_sec_clk = {
-       .parent = &emi_fast_clk,
-       .secondary = &ahbmux1_clk,
-};
-
-static struct clk ddr_hf_clk = {
-       .parent = &pll1_sw_clk,
-       .get_rate = _clk_ddr_hf_get_rate,
-};
-
-static struct clk ddr_clk = {
-       .parent = &ddr_hf_clk,
-};
-
-/* clock definitions for MIPI HSC unit which has been removed
- * from documentation, but not from hardware
- */
-static int _clk_hsc_enable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_enable(clk);
-       /* Handshake with IPU when certain clock rates are changed. */
-       reg = __raw_readl(MXC_CCM_CCDR);
-       reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
-       __raw_writel(reg, MXC_CCM_CCDR);
-
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-
-       return 0;
-}
-
-static void _clk_hsc_disable(struct clk *clk)
-{
-       u32 reg;
-
-       _clk_ccgr_disable(clk);
-       /* No handshake with HSC as its not enabled. */
-       reg = __raw_readl(MXC_CCM_CCDR);
-       reg |= MXC_CCM_CCDR_HSC_HS_MASK;
-       __raw_writel(reg, MXC_CCM_CCDR);
-
-       reg = __raw_readl(MXC_CCM_CLPCR);
-       reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
-       __raw_writel(reg, MXC_CCM_CLPCR);
-}
-
-static struct clk mipi_hsp_clk = {
-       .parent = &ipu_clk,
-       .enable_reg = MXC_CCM_CCGR4,
-       .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
-       .enable = _clk_hsc_enable,
-       .disable = _clk_hsc_disable,
-       .secondary = &mipi_hsc1_clk,
-};
-
-#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)  \
-       static struct clk name = {                      \
-               .id             = i,                    \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .get_rate       = pfx##_get_rate,       \
-               .set_rate       = pfx##_set_rate,       \
-               .round_rate     = pfx##_round_rate,     \
-               .set_parent     = pfx##_set_parent,     \
-               .enable         = _clk_ccgr_enable,     \
-               .disable        = _clk_ccgr_disable,    \
-               .parent         = p,                    \
-               .secondary      = s,                    \
-       }
-
-#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)   \
-       static struct clk name = {                      \
-               .id             = i,                    \
-               .enable_reg     = er,                   \
-               .enable_shift   = es,                   \
-               .get_rate       = pfx##_get_rate,       \
-               .set_rate       = pfx##_set_rate,       \
-               .set_parent     = pfx##_set_parent,     \
-               .enable         = _clk_max_enable,      \
-               .disable        = _clk_max_disable,     \
-               .parent         = p,                    \
-               .secondary      = s,                    \
-       }
-
-#define CLK_GET_RATE(name, nr, bitsname)                               \
-static unsigned long clk_##name##_get_rate(struct clk *clk)            \
-{                                                                      \
-       u32 reg, pred, podf;                                            \
-                                                                       \
-       reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
-       pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
-               >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
-       podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
-               >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
-                                                                       \
-       return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
-                       (pred + 1) * (podf + 1));                       \
-}
-
-#define CLK_SET_PARENT(name, nr, bitsname)                             \
-static int clk_##name##_set_parent(struct clk *clk, struct clk *parent)        \
-{                                                                      \
-       u32 reg, mux;                                                   \
-                                                                       \
-       mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
-                       &pll3_sw_clk, &lp_apm_clk);                     \
-       reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
-               ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
-       reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
-       __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
-                                                                       \
-       return 0;                                                       \
-}
-
-#define CLK_SET_RATE(name, nr, bitsname)                               \
-static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)  \
-{                                                                      \
-       u32 reg, div, parent_rate;                                      \
-       u32 pre = 0, post = 0;                                          \
-                                                                       \
-       parent_rate = clk_get_rate(clk->parent);                        \
-       div = parent_rate / rate;                                       \
-                                                                       \
-       if ((parent_rate / div) != rate)                                \
-               return -EINVAL;                                         \
-                                                                       \
-       __calc_pre_post_dividers(div, &pre, &post,                      \
-               (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
-               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
-               (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
-               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
-                                                                       \
-       /* Set sdhc1 clock divider */                                   \
-       reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
-               ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
-               | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
-       reg |= (post - 1) <<                                            \
-               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
-       reg |= (pre - 1) <<                                             \
-               MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
-       __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
-                                                                       \
-       return 0;                                                       \
-}
-
-/* UART */
-CLK_GET_RATE(uart, 1, UART)
-CLK_SET_PARENT(uart, 1, UART)
-
-static struct clk uart_root_clk = {
-       .parent = &pll2_sw_clk,
-       .get_rate = clk_uart_get_rate,
-       .set_parent = clk_uart_set_parent,
-};
-
-/* USBOH3 */
-CLK_GET_RATE(usboh3, 1, USBOH3)
-CLK_SET_PARENT(usboh3, 1, USBOH3)
-
-static struct clk usboh3_clk = {
-       .parent = &pll2_sw_clk,
-       .get_rate = clk_usboh3_get_rate,
-       .set_parent = clk_usboh3_set_parent,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable,
-       .enable_reg = MXC_CCM_CCGR2,
-       .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
-};
-
-static struct clk usb_ahb_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_ccgr_enable,
-       .disable = _clk_ccgr_disable,
-       .enable_reg = MXC_CCM_CCGR2,
-       .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
-};
-
-static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-
-       if (parent == &pll3_sw_clk)
-               reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
-
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-static struct clk usb_phy1_clk = {
-       .parent = &pll3_sw_clk,
-       .set_parent = clk_usb_phy1_set_parent,
-       .enable = _clk_ccgr_enable,
-       .enable_reg = MXC_CCM_CCGR2,
-       .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
-       .disable = _clk_ccgr_disable,
-};
-
-/* eCSPI */
-CLK_GET_RATE(ecspi, 2, CSPI)
-CLK_SET_PARENT(ecspi, 1, CSPI)
-
-static struct clk ecspi_main_clk = {
-       .parent = &pll3_sw_clk,
-       .get_rate = clk_ecspi_get_rate,
-       .set_parent = clk_ecspi_set_parent,
-};
-
-/* eSDHC */
-CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
-CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
-CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
-
-/* mx51 specific */
-CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
-CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
-CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
-
-static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1);
-       if (parent == &esdhc1_clk)
-               reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
-       else if (parent == &esdhc2_clk)
-               reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
-       else
-               return -EINVAL;
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1);
-       if (parent == &esdhc1_clk)
-               reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-       else if (parent == &esdhc2_clk)
-               reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-       else
-               return -EINVAL;
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-/* mx53 specific */
-static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1);
-       if (parent == &esdhc1_clk)
-               reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
-       else if (parent == &esdhc3_mx53_clk)
-               reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
-       else
-               return -EINVAL;
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
-CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
-CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
-
-static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
-{
-       u32 reg;
-
-       reg = __raw_readl(MXC_CCM_CSCMR1);
-       if (parent == &esdhc1_clk)
-               reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-       else if (parent == &esdhc3_mx53_clk)
-               reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
-       else
-               return -EINVAL;
-       __raw_writel(reg, MXC_CCM_CSCMR1);
-
-       return 0;
-}
-
-#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)         \
-       static struct clk name = {                                      \
-               .id             = i,                                    \
-               .enable_reg     = er,                                   \
-               .enable_shift   = es,                                   \
-               .get_rate       = gr,                                   \
-               .set_rate       = sr,                                   \
-               .enable         = e,                                    \
-               .disable        = d,                                    \
-               .parent         = p,                                    \
-               .secondary      = s,                                    \
-       }
-
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                    \
-       DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
-
-/* Shared peripheral bus arbiter */
-DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
-       NULL,  NULL, &ipg_clk, NULL);
-
-/* UART */
-DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
-       NULL,  NULL, &ipg_clk, &aips_tz1_clk);
-DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
-       NULL,  NULL, &ipg_clk, &aips_tz1_clk);
-DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
-       NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
-       NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
-       NULL,  NULL, &ipg_clk, &spba_clk);
-DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
-DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
-DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
-DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart4_ipg_clk);
-DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
-       NULL,  NULL, &uart_root_clk, &uart5_ipg_clk);
-
-/* GPT */
-DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
-       NULL,  NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-       NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
-
-DEFINE_CLOCK(pwm1_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG6_OFFSET,
-       NULL, NULL, &ipg_perclk, NULL);
-DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
-       NULL, NULL, &ipg_perclk, NULL);
-
-/* I2C */
-DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
-       NULL, NULL, &ipg_perclk, NULL);
-DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
-       NULL, NULL, &ipg_perclk, NULL);
-DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
-       NULL, NULL, &ipg_perclk, NULL);
-
-/* FEC */
-DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
-       NULL,  NULL, &ipg_clk, NULL);
-
-/* NFC */
-DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
-       clk_nfc, &emi_slow_clk, NULL);
-
-/* SSI */
-DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
-       NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
-DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
-       NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
-DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
-       NULL, NULL, &ipg_clk, NULL);
-DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
-       NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
-
-/* eCSPI */
-DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
-               NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
-               &ipg_clk, &spba_clk);
-DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
-               NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
-DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
-               NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
-               &ipg_clk, &aips_tz2_clk);
-DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
-               NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
-
-/* CSPI */
-DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
-               NULL, NULL, &ipg_clk, &aips_tz2_clk);
-DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
-               NULL, NULL, &ipg_clk, &cspi_ipg_clk);
-
-/* SDMA */
-DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
-               NULL, NULL, &ahb_clk, NULL);
-
-/* eSDHC */
-DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
-       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
-       clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
-DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
-       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
-       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
-       NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
-
-/* mx51 specific */
-DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
-       clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
-
-static struct clk esdhc3_clk = {
-       .id = 2,
-       .parent = &esdhc1_clk,
-       .set_parent = clk_esdhc3_set_parent,
-       .enable_reg = MXC_CCM_CCGR3,
-       .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
-       .enable  = _clk_max_enable,
-       .disable = _clk_max_disable,
-       .secondary = &esdhc3_ipg_clk,
-};
-static struct clk esdhc4_clk = {
-       .id = 3,
-       .parent = &esdhc1_clk,
-       .set_parent = clk_esdhc4_set_parent,
-       .enable_reg = MXC_CCM_CCGR3,
-       .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
-       .enable  = _clk_max_enable,
-       .disable = _clk_max_disable,
-       .secondary = &esdhc4_ipg_clk,
-};
-
-/* mx53 specific */
-static struct clk esdhc2_mx53_clk = {
-       .id = 2,
-       .parent = &esdhc1_clk,
-       .set_parent = clk_esdhc2_mx53_set_parent,
-       .enable_reg = MXC_CCM_CCGR3,
-       .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
-       .enable  = _clk_max_enable,
-       .disable = _clk_max_disable,
-       .secondary = &esdhc3_ipg_clk,
-};
-
-DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
-       clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
-
-static struct clk esdhc4_mx53_clk = {
-       .id = 3,
-       .parent = &esdhc1_clk,
-       .set_parent = clk_esdhc4_mx53_set_parent,
-       .enable_reg = MXC_CCM_CCGR3,
-       .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
-       .enable  = _clk_max_enable,
-       .disable = _clk_max_disable,
-       .secondary = &esdhc4_ipg_clk,
-};
-
-static struct clk sata_clk = {
-       .parent = &ipg_clk,
-       .enable = _clk_max_enable,
-       .enable_reg = MXC_CCM_CCGR4,
-       .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
-       .disable = _clk_max_disable,
-};
-
-static struct clk ahci_phy_clk = {
-       .parent = &usb_phy1_clk,
-};
-
-static struct clk ahci_dma_clk = {
-       .parent = &ahb_clk,
-};
-
-DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
-DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
-DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
-
-/* IPU */
-DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
-       NULL,  NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
-
-DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
-               NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
-               &ddr_clk, NULL);
-
-DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
-               NULL, NULL, &pll3_sw_clk, NULL);
-DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
-               NULL, NULL, &pll3_sw_clk, NULL);
-
-/* PATA */
-DEFINE_CLOCK(pata_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG0_OFFSET,
-               NULL, NULL, &ipg_clk, &spba_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c,   \
-       },
-
-static struct clk_lookup mx51_lookups[] = {
-       /* i.mx51 has the i.mx21 type uart */
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-       /* i.mx51 has the i.mx27 type fec */
-       _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
-       _REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
-       _REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-       _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
-       _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
-       _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
-       _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
-       _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
-       _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
-       _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
-       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-       _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
-       /* i.mx51 has the i.mx35 type sdma */
-       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-       _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
-       _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
-       _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
-       _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
-       _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
-       /* i.mx51 has the i.mx35 type cspi */
-       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
-       _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
-       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
-       _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
-       _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
-       _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
-       _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
-       _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
-       _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk)
-       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-};
-
-static struct clk_lookup mx53_lookups[] = {
-       /* i.mx53 has the i.mx21 type uart */
-       _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
-       _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
-       _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
-       _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
-       _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
-       _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-       /* i.mx53 has the i.mx25 type fec */
-       _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
-       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
-       _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
-       _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
-       _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
-       /* i.mx53 has the i.mx51 type ecspi */
-       _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
-       _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
-       /* i.mx53 has the i.mx25 type cspi */
-       _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
-       _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
-       _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
-       _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
-       /* i.mx53 has the i.mx35 type sdma */
-       _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
-       _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-       _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
-       _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
-       _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
-       _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
-       _REGISTER_CLOCK("imx53-ahci.0", "ahci", sata_clk)
-       _REGISTER_CLOCK("imx53-ahci.0", "ahci_phy", ahci_phy_clk)
-       _REGISTER_CLOCK("imx53-ahci.0", "ahci_dma", ahci_dma_clk)
-};
-
-static void clk_tree_init(void)
-{
-       u32 reg;
-
-       ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
-
-       /*
-        * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
-        * 8MHz, its derived from lp_apm.
-        *
-        * FIXME: Verify if true for all boards
-        */
-       reg = __raw_readl(MXC_CCM_CBCDR);
-       reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
-       reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
-       reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
-       reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
-       __raw_writel(reg, MXC_CCM_CBCDR);
-}
-
-int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
-                       unsigned long ckih1, unsigned long ckih2)
-{
-       int i;
-
-       external_low_reference = ckil;
-       external_high_reference = ckih1;
-       ckih2_reference = ckih2;
-       oscillator_reference = osc;
-
-       for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
-               clkdev_add(&mx51_lookups[i]);
-
-       clk_tree_init();
-
-       clk_enable(&cpu_clk);
-       clk_enable(&main_bus_clk);
-
-       clk_enable(&iim_clk);
-       imx_print_silicon_rev("i.MX51", mx51_revision());
-       clk_disable(&iim_clk);
-
-       /* move usb_phy_clk to 24MHz */
-       clk_set_parent(&usb_phy1_clk, &osc_clk);
-
-       /* set the usboh3_clk parent to pll2_sw_clk */
-       clk_set_parent(&usboh3_clk, &pll2_sw_clk);
-
-       /* Set SDHC parents to be PLL2 */
-       clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
-       clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
-
-       /* set SDHC root clock as 166.25MHZ*/
-       clk_set_rate(&esdhc1_clk, 166250000);
-       clk_set_rate(&esdhc2_clk, 166250000);
-
-       /* System timer */
-       mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-               MX51_INT_GPT);
-       return 0;
-}
-
-int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
-                       unsigned long ckih1, unsigned long ckih2)
-{
-       int i;
-
-       external_low_reference = ckil;
-       external_high_reference = ckih1;
-       ckih2_reference = ckih2;
-       oscillator_reference = osc;
-
-       for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
-               clkdev_add(&mx53_lookups[i]);
-
-       clk_tree_init();
-
-       clk_set_parent(&uart_root_clk, &pll3_sw_clk);
-       clk_enable(&cpu_clk);
-       clk_enable(&main_bus_clk);
-
-       clk_enable(&iim_clk);
-       imx_print_silicon_rev("i.MX53", mx53_revision());
-       clk_disable(&iim_clk);
-
-       /* Set SDHC parents to be PLL2 */
-       clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
-       clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
-
-       /* set SDHC root clock as 200MHZ*/
-       clk_set_rate(&esdhc1_clk, 200000000);
-       clk_set_rate(&esdhc3_mx53_clk, 200000000);
-
-       /* System timer */
-       mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
-               MX53_INT_GPT);
-       return 0;
-}
-
-#ifdef CONFIG_OF
-static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
-                                  unsigned long *ckih1, unsigned long *ckih2)
-{
-       struct device_node *np;
-
-       /* retrieve the freqency of fixed clocks from device tree */
-       for_each_compatible_node(np, NULL, "fixed-clock") {
-               u32 rate;
-               if (of_property_read_u32(np, "clock-frequency", &rate))
-                       continue;
-
-               if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                       *ckil = rate;
-               else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                       *osc = rate;
-               else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                       *ckih1 = rate;
-               else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
-                       *ckih2 = rate;
-       }
-}
-
-int __init mx51_clocks_init_dt(void)
-{
-       unsigned long ckil, osc, ckih1, ckih2;
-
-       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-       return mx51_clocks_init(ckil, osc, ckih1, ckih2);
-}
-
-int __init mx53_clocks_init_dt(void)
-{
-       unsigned long ckil, osc, ckih1, ckih2;
-
-       clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-       return mx53_clocks_init(ckil, osc, ckih1, ckih2);
-}
-#endif

diff --git a/arch/arm/mach-imx/crmregs-imx3.h b/arch/arm/mach-imx/crmregs-imx3.h
index 5314127..a1dfde5 100644 (file)
--- a/arch/arm/mach-imx/crmregs-imx3.h
+++ b/arch/arm/mach-imx/crmregs-imx3.h
@@ -24,48 +24,47 @@
 #define CKIH_CLK_FREQ_27MHZ     27000000
 #define CKIL_CLK_FREQ           32768
 
-#define MXC_CCM_BASE           (cpu_is_mx31() ? \
-MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR))
+extern void __iomem *mx3_ccm_base;
 
 /* Register addresses */
-#define MXC_CCM_CCMR           (MXC_CCM_BASE + 0x00)
-#define MXC_CCM_PDR0           (MXC_CCM_BASE + 0x04)
-#define MXC_CCM_PDR1           (MXC_CCM_BASE + 0x08)
-#define MX35_CCM_PDR2          (MXC_CCM_BASE + 0x0C)
-#define MXC_CCM_RCSR           (MXC_CCM_BASE + 0x0C)
-#define MX35_CCM_PDR3          (MXC_CCM_BASE + 0x10)
-#define MXC_CCM_MPCTL          (MXC_CCM_BASE + 0x10)
-#define MX35_CCM_PDR4          (MXC_CCM_BASE + 0x14)
-#define MXC_CCM_UPCTL          (MXC_CCM_BASE + 0x14)
-#define MX35_CCM_RCSR          (MXC_CCM_BASE + 0x18)
-#define MXC_CCM_SRPCTL         (MXC_CCM_BASE + 0x18)
-#define MX35_CCM_MPCTL         (MXC_CCM_BASE + 0x1C)
-#define MXC_CCM_COSR           (MXC_CCM_BASE + 0x1C)
-#define MX35_CCM_PPCTL         (MXC_CCM_BASE + 0x20)
-#define MXC_CCM_CGR0           (MXC_CCM_BASE + 0x20)
-#define MX35_CCM_ACMR          (MXC_CCM_BASE + 0x24)
-#define MXC_CCM_CGR1           (MXC_CCM_BASE + 0x24)
-#define MX35_CCM_COSR          (MXC_CCM_BASE + 0x28)
-#define MXC_CCM_CGR2           (MXC_CCM_BASE + 0x28)
-#define MX35_CCM_CGR0          (MXC_CCM_BASE + 0x2C)
-#define MXC_CCM_WIMR           (MXC_CCM_BASE + 0x2C)
-#define MX35_CCM_CGR1          (MXC_CCM_BASE + 0x30)
-#define MXC_CCM_LDC            (MXC_CCM_BASE + 0x30)
-#define MX35_CCM_CGR2          (MXC_CCM_BASE + 0x34)
-#define MXC_CCM_DCVR0          (MXC_CCM_BASE + 0x34)
-#define MX35_CCM_CGR3          (MXC_CCM_BASE + 0x38)
-#define MXC_CCM_DCVR1          (MXC_CCM_BASE + 0x38)
-#define MXC_CCM_DCVR2          (MXC_CCM_BASE + 0x3C)
-#define MXC_CCM_DCVR3          (MXC_CCM_BASE + 0x40)
-#define MXC_CCM_LTR0           (MXC_CCM_BASE + 0x44)
-#define MXC_CCM_LTR1           (MXC_CCM_BASE + 0x48)
-#define MXC_CCM_LTR2           (MXC_CCM_BASE + 0x4C)
-#define MXC_CCM_LTR3           (MXC_CCM_BASE + 0x50)
-#define MXC_CCM_LTBR0          (MXC_CCM_BASE + 0x54)
-#define MXC_CCM_LTBR1          (MXC_CCM_BASE + 0x58)
-#define MXC_CCM_PMCR0          (MXC_CCM_BASE + 0x5C)
-#define MXC_CCM_PMCR1          (MXC_CCM_BASE + 0x60)
-#define MXC_CCM_PDR2           (MXC_CCM_BASE + 0x64)
+#define MXC_CCM_CCMR           0x00
+#define MXC_CCM_PDR0           0x04
+#define MXC_CCM_PDR1           0x08
+#define MX35_CCM_PDR2          0x0C
+#define MXC_CCM_RCSR           0x0C
+#define MX35_CCM_PDR3          0x10
+#define MXC_CCM_MPCTL          0x10
+#define MX35_CCM_PDR4          0x14
+#define MXC_CCM_UPCTL          0x14
+#define MX35_CCM_RCSR          0x18
+#define MXC_CCM_SRPCTL         0x18
+#define MX35_CCM_MPCTL         0x1C
+#define MXC_CCM_COSR           0x1C
+#define MX35_CCM_PPCTL         0x20
+#define MXC_CCM_CGR0           0x20
+#define MX35_CCM_ACMR          0x24
+#define MXC_CCM_CGR1           0x24
+#define MX35_CCM_COSR          0x28
+#define MXC_CCM_CGR2           0x28
+#define MX35_CCM_CGR0          0x2C
+#define MXC_CCM_WIMR           0x2C
+#define MX35_CCM_CGR1          0x30
+#define MXC_CCM_LDC            0x30
+#define MX35_CCM_CGR2          0x34
+#define MXC_CCM_DCVR0          0x34
+#define MX35_CCM_CGR3          0x38
+#define MXC_CCM_DCVR1          0x38
+#define MXC_CCM_DCVR2          0x3C
+#define MXC_CCM_DCVR3          0x40
+#define MXC_CCM_LTR0           0x44
+#define MXC_CCM_LTR1           0x48
+#define MXC_CCM_LTR2           0x4C
+#define MXC_CCM_LTR3           0x50
+#define MXC_CCM_LTBR0          0x54
+#define MXC_CCM_LTBR1          0x58
+#define MXC_CCM_PMCR0          0x5C
+#define MXC_CCM_PMCR1          0x60
+#define MXC_CCM_PDR2           0x64
 
 /* Register bit definitions */
 #define MXC_CCM_CCMR_WBEN                       (1 << 27)

diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5cca573..5f577fb 100644 (file)
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -14,6 +14,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -81,6 +82,8 @@ static void __init imx51_dt_init(void)
 
        of_irq_init(imx51_irq_match);
 
+       pinctrl_provide_dummies();
+
        node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
        if (node) {
                of_id = of_match_node(imx51_iomuxc_of_match, node);

diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 4172279..574eca4 100644 (file)
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -15,6 +15,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -88,6 +89,8 @@ static void __init imx53_dt_init(void)
 
        of_irq_init(imx53_irq_match);
 
+       pinctrl_provide_dummies();
+
        node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
        if (node) {
                of_id = of_match_node(imx53_iomuxc_of_match, node);

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index da6c1d9..3df360a 100644 (file)
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -19,6 +19,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
 #include <asm/smp_twd.h>
@@ -77,6 +78,12 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 
 static void __init imx6q_init_machine(void)
 {
+       /*
+        * This should be removed when all imx6q boards have pinctrl
+        * states for devices defined in device tree.
+        */
+       pinctrl_provide_dummies();
+
        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
                                           ksz9021rn_phy_fixup);

diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 2bded59..fcafd3d 100644 (file)
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -18,6 +18,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/map.h>
 
@@ -58,4 +59,5 @@ void __init imx1_soc_init(void)
                                                MX1_GPIO_INT_PORTC, 0);
        mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
                                                MX1_GPIO_INT_PORTD, 0);
+       pinctrl_provide_dummies();
 }

diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 14d540e..5f43905 100644 (file)
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -20,6 +20,7 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/devices-common.h>
@@ -88,6 +89,7 @@ void __init imx21_soc_init(void)
        mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
        mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
 
+       pinctrl_provide_dummies();
        imx_add_imx_dma();
        platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
                                        ARRAY_SIZE(imx21_audmux_res));

diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 153b457..6ff3714 100644 (file)
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/err.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
@@ -95,6 +96,7 @@ void __init imx25_soc_init(void)
        mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
        mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
 
+       pinctrl_provide_dummies();
        /* i.mx25 has the i.mx35 type sdma */
        imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
        /* i.mx25 has the i.mx31 type audmux */

diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 8cb3f5e..2566255 100644 (file)
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -20,6 +20,7 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/devices-common.h>
@@ -89,6 +90,7 @@ void __init imx27_soc_init(void)
        mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
        mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
 
+       pinctrl_provide_dummies();
        imx_add_imx_dma();
        /* imx27 has the imx21 type audmux */
        platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,

diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 7412738..967ed5b 100644 (file)
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/err.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/pgtable.h>
 #include <asm/system_misc.h>
@@ -31,6 +32,10 @@
 #include <mach/iomux-v3.h>
 #include <mach/irqs.h>
 
+#include "crmregs-imx3.h"
+
+void __iomem *mx3_ccm_base;
+
 static void imx3_idle(void)
 {
        unsigned long reg = 0;
@@ -137,6 +142,7 @@ void __init imx31_init_early(void)
        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
        arch_ioremap_caller = imx3_ioremap_caller;
        arm_pm_idle = imx3_idle;
+       mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
 }
 
 void __init mx31_init_irq(void)
@@ -210,6 +216,7 @@ void __init imx35_init_early(void)
        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
        arm_pm_idle = imx3_idle;
        arch_ioremap_caller = imx3_ioremap_caller;
+       mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
 }
 
 void __init mx35_init_irq(void)
@@ -267,6 +274,7 @@ void __init imx35_soc_init(void)
        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
 
+       pinctrl_provide_dummies();
        if (to_version == 1) {
                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
                        strlen(imx35_sdma_pdata.fw_name));

diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index e10f391..8b4dc20 100644 (file)
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -14,6 +14,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
@@ -32,6 +33,7 @@ static void imx5_idle(void)
                gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
                if (IS_ERR(gpc_dvfs_clk))
                        return;
+               clk_prepare(gpc_dvfs_clk);
        }
        clk_enable(gpc_dvfs_clk);
        mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
@@ -223,6 +225,7 @@ void __init imx53_soc_init(void)
        mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
        mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
 
+       pinctrl_provide_dummies();
        /* i.mx53 has the i.mx35 type sdma */
        imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
 

diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
index b375243..822103b 100644 (file)
--- a/arch/arm/mach-imx/pm-imx3.c
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -21,14 +21,14 @@
  */
 void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
 {
-       int reg = __raw_readl(MXC_CCM_CCMR);
+       int reg = __raw_readl(mx3_ccm_base + MXC_CCM_CCMR);
        reg &= ~MXC_CCM_CCMR_LPM_MASK;
 
        switch (mode) {
        case MX3_WAIT:
                if (cpu_is_mx35())
                        reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
-               __raw_writel(reg, MXC_CCM_CCMR);
+               __raw_writel(reg, mx3_ccm_base + MXC_CCM_CCMR);
                break;
        default:
                pr_err("Unknown cpu power mode: %d\n", mode);

diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 962e711..fb3496a 100644 (file)
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -17,6 +17,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/memblock.h>
 
@@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
        msm_map_msm8x60_io();
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id msm_dt_gic_match[] __initdata = {
+       { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
+       {}
+};
+#endif
+
 static void __init msm8x60_init_irq(void)
 {
-       gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                (void *)MSM_QGIC_CPU_BASE);
+       if (!of_have_populated_dt())
+               gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+                        (void *)MSM_QGIC_CPU_BASE);
+#ifdef CONFIG_OF
+       else
+               of_irq_init(msm_dt_gic_match);
+#endif
 
        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
        {}
 };
 
-static struct of_device_id msm_dt_gic_match[] __initdata = {
-       { .compatible = "qcom,msm-8660-qgic", },
-       {}
-};
-
 static void __init msm8x60_dt_init(void)
 {
-       irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
-                               GIC_SPI_START);
-
        if (of_machine_is_compatible("qcom,msm8660-surf")) {
                printk(KERN_INFO "Init surf UART registers\n");
                msm8x60_init_uart12dm();

diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f996..07d5383 100644 (file)
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -9,11 +9,13 @@ config SOC_IMX23
        bool
        select CPU_ARM926T
        select HAVE_PWM
+       select PINCTRL_IMX23
 
 config SOC_IMX28
        bool
        select CPU_ARM926T
        select HAVE_PWM
+       select PINCTRL_IMX28
 
 comment "MXS platforms:"
 

diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 908bf9a..6ce21a2 100644 (file)
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,12 +1,9 @@
 # Common support
-obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o
+obj-y := devices.o icoll.o iomux.o system.o timer.o mm.o
 
 obj-$(CONFIG_MXS_OCOTP) += ocotp.o
 obj-$(CONFIG_PM) += pm.o
 
-obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
-obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
-
 obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o

diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
deleted file mode 100644 (file)
index e3ac52c..0000000
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ /dev/null
@@ -1,536 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/jiffies.h>
-#include <linux/clkdev.h>
-
-#include <asm/clkdev.h>
-#include <asm/div64.h>
-
-#include <mach/mx23.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-
-#include "regs-clkctrl-mx23.h"
-
-#define CLKCTRL_BASE_ADDR      MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
-#define DIGCTRL_BASE_ADDR      MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
-
-#define PARENT_RATE_SHIFT      8
-
-static int _raw_clk_enable(struct clk *clk)
-{
-       u32 reg;
-
-       if (clk->enable_reg) {
-               reg = __raw_readl(clk->enable_reg);
-               reg &= ~(1 << clk->enable_shift);
-               __raw_writel(reg, clk->enable_reg);
-       }
-
-       return 0;
-}
-
-static void _raw_clk_disable(struct clk *clk)
-{
-       u32 reg;
-
-       if (clk->enable_reg) {
-               reg = __raw_readl(clk->enable_reg);
-               reg |= 1 << clk->enable_shift;
-               __raw_writel(reg, clk->enable_reg);
-       }
-}
-
-/*
- * ref_xtal_clk
- */
-static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
-{
-       return 24000000;
-}
-
-static struct clk ref_xtal_clk = {
-       .get_rate = ref_xtal_clk_get_rate,
-};
-
-/*
- * pll_clk
- */
-static unsigned long pll_clk_get_rate(struct clk *clk)
-{
-       return 480000000;
-}
-
-static int pll_clk_enable(struct clk *clk)
-{
-       __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
-                       BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
-
-       /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
-        * and is incorrect (excessive). Per definition of the PLLCTRL0
-        * POWER field, waiting at least 10us.
-        */
-       udelay(10);
-
-       return 0;
-}
-
-static void pll_clk_disable(struct clk *clk)
-{
-       __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
-                       BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
-}
-
-static struct clk pll_clk = {
-        .get_rate = pll_clk_get_rate,
-        .enable = pll_clk_enable,
-        .disable = pll_clk_disable,
-        .parent = &ref_xtal_clk,
-};
-
-/*
- * ref_clk
- */
-#define _CLK_GET_RATE_REF(name, sr, ss)                                        \
-static unsigned long name##_get_rate(struct clk *clk)                  \
-{                                                                      \
-       unsigned long parent_rate;                                      \
-       u32 reg, div;                                                   \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
-       div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
-       parent_rate = clk_get_rate(clk->parent);                        \
-                                                                       \
-       return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
-                       div, PARENT_RATE_SHIFT);                        \
-}
-
-_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
-_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
-_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
-_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
-
-#define _DEFINE_CLOCK_REF(name, er, es)                                        \
-       static struct clk name = {                                      \
-               .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
-               .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
-               .get_rate       = name##_get_rate,                      \
-               .enable         = _raw_clk_enable,                      \
-               .disable        = _raw_clk_disable,                     \
-               .parent         = &pll_clk,                             \
-       }
-
-_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
-_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
-_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
-_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
-
-/*
- * General clocks
- *
- * clk_get_rate
- */
-static unsigned long rtc_clk_get_rate(struct clk *clk)
-{
-       /* ref_xtal_clk is implemented as the only parent */
-       return clk_get_rate(clk->parent) / 768;
-}
-
-static unsigned long clk32k_clk_get_rate(struct clk *clk)
-{
-       return clk->parent->get_rate(clk->parent) / 750;
-}
-
-#define _CLK_GET_RATE(name, rs)                                                \
-static unsigned long name##_get_rate(struct clk *clk)                  \
-{                                                                      \
-       u32 reg, div;                                                   \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-                                                                       \
-       if (clk->parent == &ref_xtal_clk)                               \
-               div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
-                       BP_CLKCTRL_##rs##_DIV_XTAL;                     \
-       else                                                            \
-               div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
-                       BP_CLKCTRL_##rs##_DIV_##rs;                     \
-                                                                       \
-       if (!div)                                                       \
-               return -EINVAL;                                         \
-                                                                       \
-       return clk_get_rate(clk->parent) / div;                         \
-}
-
-_CLK_GET_RATE(cpu_clk, CPU)
-_CLK_GET_RATE(emi_clk, EMI)
-
-#define _CLK_GET_RATE1(name, rs)                                       \
-static unsigned long name##_get_rate(struct clk *clk)                  \
-{                                                                      \
-       u32 reg, div;                                                   \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-       div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
-                                                                       \
-       if (!div)                                                       \
-               return -EINVAL;                                         \
-                                                                       \
-       return clk_get_rate(clk->parent) / div;                         \
-}
-
-_CLK_GET_RATE1(hbus_clk, HBUS)
-_CLK_GET_RATE1(xbus_clk, XBUS)
-_CLK_GET_RATE1(ssp_clk, SSP)
-_CLK_GET_RATE1(gpmi_clk, GPMI)
-_CLK_GET_RATE1(lcdif_clk, PIX)
-
-#define _CLK_GET_RATE_STUB(name)                                       \
-static unsigned long name##_get_rate(struct clk *clk)                  \
-{                                                                      \
-       return clk_get_rate(clk->parent);                               \
-}
-
-_CLK_GET_RATE_STUB(uart_clk)
-_CLK_GET_RATE_STUB(audio_clk)
-_CLK_GET_RATE_STUB(pwm_clk)
-
-/*
- * clk_set_rate
- */
-static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
-{
-       u32 reg, bm_busy, div_max, d, f, div, frac;
-       unsigned long diff, parent_rate, calc_rate;
-
-       parent_rate = clk_get_rate(clk->parent);
-
-       if (clk->parent == &ref_xtal_clk) {
-               div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
-               bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
-               div = DIV_ROUND_UP(parent_rate, rate);
-               if (div == 0 || div > div_max)
-                       return -EINVAL;
-       } else {
-               div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
-               bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
-               rate >>= PARENT_RATE_SHIFT;
-               parent_rate >>= PARENT_RATE_SHIFT;
-               diff = parent_rate;
-               div = frac = 1;
-               for (d = 1; d <= div_max; d++) {
-                       f = parent_rate * 18 / d / rate;
-                       if ((parent_rate * 18 / d) % rate)
-                               f++;
-                       if (f < 18 || f > 35)
-                               continue;
-
-                       calc_rate = parent_rate * 18 / f / d;
-                       if (calc_rate > rate)
-                               continue;
-
-                       if (rate - calc_rate < diff) {
-                               frac = f;
-                               div = d;
-                               diff = rate - calc_rate;
-                       }
-
-                       if (diff == 0)
-                               break;
-               }
-
-               if (diff == parent_rate)
-                       return -EINVAL;
-
-               reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
-               reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
-               reg |= frac;
-               __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
-       }
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
-       reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
-       reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
-
-       mxs_clkctrl_timeout(HW_CLKCTRL_CPU, bm_busy);
-
-       return 0;
-}
-
-#define _CLK_SET_RATE(name, dr)                                                \
-static int name##_set_rate(struct clk *clk, unsigned long rate)                \
-{                                                                      \
-       u32 reg, div_max, div;                                          \
-       unsigned long parent_rate;                                      \
-                                                                       \
-       parent_rate = clk_get_rate(clk->parent);                        \
-       div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
-                                                                       \
-       div = DIV_ROUND_UP(parent_rate, rate);                          \
-       if (div == 0 || div > div_max)                                  \
-               return -EINVAL;                                         \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-       reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
-       reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
-       if (reg & (1 << clk->enable_shift)) {                           \
-               pr_err("%s: clock is gated\n", __func__);               \
-               return -EINVAL;                                         \
-       }                                                               \
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-                                                                       \
-       mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);   \
-       return 0;                                                       \
-}
-
-_CLK_SET_RATE(xbus_clk, XBUS)
-_CLK_SET_RATE(ssp_clk, SSP)
-_CLK_SET_RATE(gpmi_clk, GPMI)
-_CLK_SET_RATE(lcdif_clk, PIX)
-
-#define _CLK_SET_RATE_STUB(name)                                       \
-static int name##_set_rate(struct clk *clk, unsigned long rate)                \
-{                                                                      \
-       return -EINVAL;                                                 \
-}
-
-_CLK_SET_RATE_STUB(emi_clk)
-_CLK_SET_RATE_STUB(uart_clk)
-_CLK_SET_RATE_STUB(audio_clk)
-_CLK_SET_RATE_STUB(pwm_clk)
-_CLK_SET_RATE_STUB(clk32k_clk)
-
-/*
- * clk_set_parent
- */
-#define _CLK_SET_PARENT(name, bit)                                     \
-static int name##_set_parent(struct clk *clk, struct clk *parent)      \
-{                                                                      \
-       if (parent != clk->parent) {                                    \
-               __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG);    \
-               clk->parent = parent;                                   \
-       }                                                               \
-                                                                       \
-       return 0;                                                       \
-}
-
-_CLK_SET_PARENT(cpu_clk, CPU)
-_CLK_SET_PARENT(emi_clk, EMI)
-_CLK_SET_PARENT(ssp_clk, SSP)
-_CLK_SET_PARENT(gpmi_clk, GPMI)
-_CLK_SET_PARENT(lcdif_clk, PIX)
-
-#define _CLK_SET_PARENT_STUB(name)                                     \
-static int name##_set_parent(struct clk *clk, struct clk *parent)      \
-{                                                                      \
-       if (parent != clk->parent)                                      \
-               return -EINVAL;                                         \
-       else                                                            \
-               return 0;                                               \
-}
-
-_CLK_SET_PARENT_STUB(uart_clk)
-_CLK_SET_PARENT_STUB(audio_clk)
-_CLK_SET_PARENT_STUB(pwm_clk)
-_CLK_SET_PARENT_STUB(clk32k_clk)
-
-/*
- * clk definition
- */
-static struct clk cpu_clk = {
-       .get_rate = cpu_clk_get_rate,
-       .set_rate = cpu_clk_set_rate,
-       .set_parent = cpu_clk_set_parent,
-       .parent = &ref_cpu_clk,
-};
-
-static struct clk hbus_clk = {
-       .get_rate = hbus_clk_get_rate,
-       .parent = &cpu_clk,
-};
-
-static struct clk xbus_clk = {
-       .get_rate = xbus_clk_get_rate,
-       .set_rate = xbus_clk_set_rate,
-       .parent = &ref_xtal_clk,
-};
-
-static struct clk rtc_clk = {
-       .get_rate = rtc_clk_get_rate,
-       .parent = &ref_xtal_clk,
-};
-
-/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
-static struct clk usb_clk = {
-       .enable_reg = DIGCTRL_BASE_ADDR,
-       .enable_shift = 2,
-       .enable = _raw_clk_enable,
-       .disable = _raw_clk_disable,
-       .parent = &pll_clk,
-};
-
-#define _DEFINE_CLOCK(name, er, es, p)                                 \
-       static struct clk name = {                                      \
-               .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
-               .enable_shift   = BP_CLKCTRL_##er##_##es,               \
-               .get_rate       = name##_get_rate,                      \
-               .set_rate       = name##_set_rate,                      \
-               .set_parent     = name##_set_parent,                    \
-               .enable         = _raw_clk_enable,                      \
-               .disable        = _raw_clk_disable,                     \
-               .parent         = p,                                    \
-       }
-
-_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c, \
-       },
-
-static struct clk_lookup lookups[] = {
-       /* for amba bus driver */
-       _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
-       /* for amba-pl011 driver */
-       _REGISTER_CLOCK("duart", NULL, uart_clk)
-       _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
-       _REGISTER_CLOCK("rtc", NULL, rtc_clk)
-       _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
-       _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
-       _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
-       _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
-       _REGISTER_CLOCK(NULL, "usb", usb_clk)
-       _REGISTER_CLOCK(NULL, "audio", audio_clk)
-       _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
-       _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
-       _REGISTER_CLOCK("imx23-gpmi-nand", NULL, gpmi_clk)
-};
-
-static int clk_misc_init(void)
-{
-       u32 reg;
-       int ret;
-
-       /* Fix up parent per register setting */
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
-       cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
-                       &ref_xtal_clk : &ref_cpu_clk;
-       emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
-                       &ref_xtal_clk : &ref_emi_clk;
-       ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
-                       &ref_xtal_clk : &ref_io_clk;
-       gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
-                       &ref_xtal_clk : &ref_io_clk;
-       lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
-                       &ref_xtal_clk : &ref_pix_clk;
-
-       /* Use int div over frac when both are available */
-       __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
-       __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
-       __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
-       reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
-       reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-       reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
-       reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
-
-       /*
-        * Set safe hbus clock divider. A divider of 3 ensure that
-        * the Vddd voltage required for the cpu clock is sufficiently
-        * high for the hbus clock.
-        */
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
-       reg &= BM_CLKCTRL_HBUS_DIV;
-       reg |= 3 << BP_CLKCTRL_HBUS_DIV;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
-
-       ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_BUSY);
-
-       /* Gate off cpu clock in WFI for power saving */
-       __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
-
-       /*
-        * 480 MHz seems too high to be ssp clock source directly,
-        * so set frac to get a 288 MHz ref_io.
-        */
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
-       reg &= ~BM_CLKCTRL_FRAC_IOFRAC;
-       reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
-
-       return ret;
-}
-
-int __init mx23_clocks_init(void)
-{
-       clk_misc_init();
-
-       /*
-        * source ssp clock from ref_io than ref_xtal,
-        * as ref_xtal only provides 24 MHz as maximum.
-        */
-       clk_set_parent(&ssp_clk, &ref_io_clk);
-
-       clk_prepare_enable(&cpu_clk);
-       clk_prepare_enable(&hbus_clk);
-       clk_prepare_enable(&xbus_clk);
-       clk_prepare_enable(&emi_clk);
-       clk_prepare_enable(&uart_clk);
-
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-       mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
-
-       return 0;
-}

diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
deleted file mode 100644 (file)
index cea29c9..0000000
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ /dev/null
@@ -1,803 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/jiffies.h>
-#include <linux/clkdev.h>
-#include <linux/spinlock.h>
-
-#include <asm/clkdev.h>
-#include <asm/div64.h>
-
-#include <mach/mx28.h>
-#include <mach/common.h>
-#include <mach/clock.h>
-#include <mach/digctl.h>
-
-#include "regs-clkctrl-mx28.h"
-
-#define CLKCTRL_BASE_ADDR      MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
-#define DIGCTRL_BASE_ADDR      MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
-
-#define PARENT_RATE_SHIFT      8
-
-static struct clk pll2_clk;
-static struct clk cpu_clk;
-static struct clk emi_clk;
-static struct clk saif0_clk;
-static struct clk saif1_clk;
-static struct clk clk32k_clk;
-static DEFINE_SPINLOCK(clkmux_lock);
-
-/*
- * HW_SAIF_CLKMUX_SEL:
- *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
- *             clock pins selected for SAIF1 input clocks.
- *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
- *             SAIF0 clock inputs selected for SAIF1 input clocks.
- *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
- *             clocks.
- *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
- *             clocks.
- */
-int mxs_saif_clkmux_select(unsigned int clkmux)
-{
-       if (clkmux > 0x3)
-               return -EINVAL;
-
-       spin_lock(&clkmux_lock);
-       __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
-                       DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
-       __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
-                       DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
-       spin_unlock(&clkmux_lock);
-
-       return 0;
-}
-
-static int _raw_clk_enable(struct clk *clk)
-{
-       u32 reg;
-
-       if (clk->enable_reg) {
-               reg = __raw_readl(clk->enable_reg);
-               reg &= ~(1 << clk->enable_shift);
-               __raw_writel(reg, clk->enable_reg);
-       }
-
-       return 0;
-}
-
-static void _raw_clk_disable(struct clk *clk)
-{
-       u32 reg;
-
-       if (clk->enable_reg) {
-               reg = __raw_readl(clk->enable_reg);
-               reg |= 1 << clk->enable_shift;
-               __raw_writel(reg, clk->enable_reg);
-       }
-}
-
-/*
- * ref_xtal_clk
- */
-static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
-{
-       return 24000000;
-}
-
-static struct clk ref_xtal_clk = {
-       .get_rate = ref_xtal_clk_get_rate,
-};
-
-/*
- * pll_clk
- */
-static unsigned long pll0_clk_get_rate(struct clk *clk)
-{
-       return 480000000;
-}
-
-static unsigned long pll1_clk_get_rate(struct clk *clk)
-{
-       return 480000000;
-}
-
-static unsigned long pll2_clk_get_rate(struct clk *clk)
-{
-       return 50000000;
-}
-
-#define _CLK_ENABLE_PLL(name, r, g)                                    \
-static int name##_enable(struct clk *clk)                              \
-{                                                                      \
-       __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
-                    CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET);    \
-       udelay(10);                                                     \
-                                                                       \
-       if (clk == &pll2_clk)                                           \
-               __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
-       else                                                            \
-               __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
-                                                                       \
-       return 0;                                                       \
-}
-
-_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
-_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
-_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
-
-#define _CLK_DISABLE_PLL(name, r, g)                                   \
-static void name##_disable(struct clk *clk)                            \
-{                                                                      \
-       __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
-                    CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR);    \
-                                                                       \
-       if (clk == &pll2_clk)                                           \
-               __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
-       else                                                            \
-               __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
-                                                                       \
-}
-
-_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
-_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
-_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
-
-#define _DEFINE_CLOCK_PLL(name)                                                \
-       static struct clk name = {                                      \
-               .get_rate       = name##_get_rate,                      \
-               .enable         = name##_enable,                        \
-               .disable        = name##_disable,                       \
-               .parent         = &ref_xtal_clk,                        \
-       }
-
-_DEFINE_CLOCK_PLL(pll0_clk);
-_DEFINE_CLOCK_PLL(pll1_clk);
-_DEFINE_CLOCK_PLL(pll2_clk);
-
-/*
- * ref_clk
- */
-#define _CLK_GET_RATE_REF(name, sr, ss)                                        \
-static unsigned long name##_get_rate(struct clk *clk)                  \
-{                                                                      \
-       unsigned long parent_rate;                                      \
-       u32 reg, div;                                                   \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
-       div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
-       parent_rate = clk_get_rate(clk->parent);                        \
-                                                                       \
-       return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
-                       div, PARENT_RATE_SHIFT);                        \
-}
-
-_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
-_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
-_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
-_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
-_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
-_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
-
-#define _DEFINE_CLOCK_REF(name, er, es)                                        \
-       static struct clk name = {                                      \
-               .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
-               .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
-               .get_rate       = name##_get_rate,                      \
-               .enable         = _raw_clk_enable,                      \
-               .disable        = _raw_clk_disable,                     \
-               .parent         = &pll0_clk,                            \
-       }
-
-_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
-_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
-_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
-_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
-_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
-_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
-
-/*
- * General clocks
- *
- * clk_get_rate
- */
-static unsigned long lradc_clk_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / 16;
-}
-
-static unsigned long rtc_clk_get_rate(struct clk *clk)
-{
-       /* ref_xtal_clk is implemented as the only parent */
-       return clk_get_rate(clk->parent) / 768;
-}
-
-static unsigned long clk32k_clk_get_rate(struct clk *clk)
-{
-       return clk->parent->get_rate(clk->parent) / 750;
-}
-
-static unsigned long spdif_clk_get_rate(struct clk *clk)
-{
-       return clk_get_rate(clk->parent) / 4;
-}
-
-#define _CLK_GET_RATE(name, rs)                                                \
-static unsigned long name##_get_rate(struct clk *clk)                  \
-{                                                                      \
-       u32 reg, div;                                                   \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-                                                                       \
-       if (clk->parent == &ref_xtal_clk)                               \
-               div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
-                       BP_CLKCTRL_##rs##_DIV_XTAL;                     \
-       else                                                            \
-               div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
-                       BP_CLKCTRL_##rs##_DIV_##rs;                     \
-                                                                       \
-       if (!div)                                                       \
-               return -EINVAL;                                         \
-                                                                       \
-       return clk_get_rate(clk->parent) / div;                         \
-}
-
-_CLK_GET_RATE(cpu_clk, CPU)
-_CLK_GET_RATE(emi_clk, EMI)
-
-#define _CLK_GET_RATE1(name, rs)                                       \
-static unsigned long name##_get_rate(struct clk *clk)                  \
-{                                                                      \
-       u32 reg, div;                                                   \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-       div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
-                                                                       \
-       if (!div)                                                       \
-               return -EINVAL;                                         \
-                                                                       \
-       if (clk == &saif0_clk || clk == &saif1_clk)                     \
-               return clk_get_rate(clk->parent) >> 16 * div;           \
-       else                                                            \
-               return clk_get_rate(clk->parent) / div;                 \
-}
-
-_CLK_GET_RATE1(hbus_clk, HBUS)
-_CLK_GET_RATE1(xbus_clk, XBUS)
-_CLK_GET_RATE1(ssp0_clk, SSP0)
-_CLK_GET_RATE1(ssp1_clk, SSP1)
-_CLK_GET_RATE1(ssp2_clk, SSP2)
-_CLK_GET_RATE1(ssp3_clk, SSP3)
-_CLK_GET_RATE1(gpmi_clk, GPMI)
-_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
-_CLK_GET_RATE1(saif0_clk, SAIF0)
-_CLK_GET_RATE1(saif1_clk, SAIF1)
-
-#define _CLK_GET_RATE_STUB(name)                                       \
-static unsigned long name##_get_rate(struct clk *clk)                  \
-{                                                                      \
-       return clk_get_rate(clk->parent);                               \
-}
-
-_CLK_GET_RATE_STUB(uart_clk)
-_CLK_GET_RATE_STUB(pwm_clk)
-_CLK_GET_RATE_STUB(can0_clk)
-_CLK_GET_RATE_STUB(can1_clk)
-_CLK_GET_RATE_STUB(fec_clk)
-
-/*
- * clk_set_rate
- */
-/* fool compiler */
-#define BM_CLKCTRL_CPU_DIV     0
-#define BP_CLKCTRL_CPU_DIV     0
-#define BM_CLKCTRL_CPU_BUSY    0
-
-#define _CLK_SET_RATE(name, dr, fr, fs)                                        \
-static int name##_set_rate(struct clk *clk, unsigned long rate)                \
-{                                                                      \
-       u32 reg, bm_busy, div_max, d, f, div, frac;                     \
-       unsigned long diff, parent_rate, calc_rate;                     \
-                                                                       \
-       div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
-       bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
-                                                                       \
-       if (clk->parent == &ref_xtal_clk) {                             \
-               parent_rate = clk_get_rate(clk->parent);                \
-               div = DIV_ROUND_UP(parent_rate, rate);                  \
-               if (clk == &cpu_clk) {                                  \
-                       div_max = BM_CLKCTRL_CPU_DIV_XTAL >>            \
-                               BP_CLKCTRL_CPU_DIV_XTAL;                \
-                       bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;         \
-               }                                                       \
-               if (div == 0 || div > div_max)                          \
-                       return -EINVAL;                                 \
-       } else {                                                        \
-               /*                                                      \
-                * hack alert: this block modifies clk->parent, too,    \
-                * so the base to use it the grand parent.              \
-                */                                                     \
-               parent_rate = clk_get_rate(clk->parent->parent);        \
-               rate >>= PARENT_RATE_SHIFT;                             \
-               parent_rate >>= PARENT_RATE_SHIFT;                      \
-               diff = parent_rate;                                     \
-               div = frac = 1;                                         \
-               if (clk == &cpu_clk) {                                  \
-                       div_max = BM_CLKCTRL_CPU_DIV_CPU >>             \
-                               BP_CLKCTRL_CPU_DIV_CPU;                 \
-                       bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;          \
-               }                                                       \
-               for (d = 1; d <= div_max; d++) {                        \
-                       f = parent_rate * 18 / d / rate;                \
-                       if ((parent_rate * 18 / d) % rate)              \
-                               f++;                                    \
-                       if (f < 18 || f > 35)                           \
-                               continue;                               \
-                                                                       \
-                       calc_rate = parent_rate * 18 / f / d;           \
-                       if (calc_rate > rate)                           \
-                               continue;                               \
-                                                                       \
-                       if (rate - calc_rate < diff) {                  \
-                               frac = f;                               \
-                               div = d;                                \
-                               diff = rate - calc_rate;                \
-                       }                                               \
-                                                                       \
-                       if (diff == 0)                                  \
-                               break;                                  \
-               }                                                       \
-                                                                       \
-               if (diff == parent_rate)                                \
-                       return -EINVAL;                                 \
-                                                                       \
-               reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
-               reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC;                   \
-               reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC;            \
-               __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
-       }                                                               \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-       if (clk == &cpu_clk) {                                          \
-               reg &= ~BM_CLKCTRL_CPU_DIV_CPU;                         \
-               reg |= div << BP_CLKCTRL_CPU_DIV_CPU;                   \
-       } else {                                                        \
-               reg &= ~BM_CLKCTRL_##dr##_DIV;                          \
-               reg |= div << BP_CLKCTRL_##dr##_DIV;                    \
-               if (reg & (1 << clk->enable_shift)) {                   \
-                       pr_err("%s: clock is gated\n", __func__);       \
-                       return -EINVAL;                                 \
-               }                                                       \
-       }                                                               \
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-                                                                       \
-       return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, bm_busy);           \
-}
-
-_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
-_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
-_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
-_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
-_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
-_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
-_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
-
-#define _CLK_SET_RATE1(name, dr)                                       \
-static int name##_set_rate(struct clk *clk, unsigned long rate)                \
-{                                                                      \
-       u32 reg, div_max, div;                                          \
-       unsigned long parent_rate;                                      \
-                                                                       \
-       parent_rate = clk_get_rate(clk->parent);                        \
-       div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
-                                                                       \
-       div = DIV_ROUND_UP(parent_rate, rate);                          \
-       if (div == 0 || div > div_max)                                  \
-               return -EINVAL;                                         \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-       reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
-       reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
-       if (reg & (1 << clk->enable_shift)) {                           \
-               pr_err("%s: clock is gated\n", __func__);               \
-               return -EINVAL;                                         \
-       }                                                               \
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
-                                                                       \
-       return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);\
-}
-
-_CLK_SET_RATE1(xbus_clk, XBUS)
-
-/* saif clock uses 16 bits frac div */
-#define _CLK_SET_RATE_SAIF(name, rs)                                   \
-static int name##_set_rate(struct clk *clk, unsigned long rate)                \
-{                                                                      \
-       u16 div;                                                        \
-       u32 reg;                                                        \
-       u64 lrate;                                                      \
-       unsigned long parent_rate;                                      \
-                                                                       \
-       parent_rate = clk_get_rate(clk->parent);                        \
-       if (rate > parent_rate)                                         \
-               return -EINVAL;                                         \
-                                                                       \
-       lrate = (u64)rate << 16;                                        \
-       do_div(lrate, parent_rate);                                     \
-       div = (u16)lrate;                                               \
-                                                                       \
-       if (!div)                                                       \
-               return -EINVAL;                                         \
-                                                                       \
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-       reg &= ~BM_CLKCTRL_##rs##_DIV;                                  \
-       reg |= div << BP_CLKCTRL_##rs##_DIV;                            \
-       if (reg & (1 << clk->enable_shift)) {                           \
-               pr_err("%s: clock is gated\n", __func__);               \
-               return -EINVAL;                                         \
-       }                                                               \
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-                                                                       \
-       return mxs_clkctrl_timeout(HW_CLKCTRL_##rs, BM_CLKCTRL_##rs##_BUSY);\
-}
-
-_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
-_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
-
-#define _CLK_SET_RATE_STUB(name)                                       \
-static int name##_set_rate(struct clk *clk, unsigned long rate)                \
-{                                                                      \
-       return -EINVAL;                                                 \
-}
-
-_CLK_SET_RATE_STUB(emi_clk)
-_CLK_SET_RATE_STUB(uart_clk)
-_CLK_SET_RATE_STUB(pwm_clk)
-_CLK_SET_RATE_STUB(spdif_clk)
-_CLK_SET_RATE_STUB(clk32k_clk)
-_CLK_SET_RATE_STUB(can0_clk)
-_CLK_SET_RATE_STUB(can1_clk)
-_CLK_SET_RATE_STUB(fec_clk)
-
-/*
- * clk_set_parent
- */
-#define _CLK_SET_PARENT(name, bit)                                     \
-static int name##_set_parent(struct clk *clk, struct clk *parent)      \
-{                                                                      \
-       if (parent != clk->parent) {                                    \
-               __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
-                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG);    \
-               clk->parent = parent;                                   \
-       }                                                               \
-                                                                       \
-       return 0;                                                       \
-}
-
-_CLK_SET_PARENT(cpu_clk, CPU)
-_CLK_SET_PARENT(emi_clk, EMI)
-_CLK_SET_PARENT(ssp0_clk, SSP0)
-_CLK_SET_PARENT(ssp1_clk, SSP1)
-_CLK_SET_PARENT(ssp2_clk, SSP2)
-_CLK_SET_PARENT(ssp3_clk, SSP3)
-_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
-_CLK_SET_PARENT(gpmi_clk, GPMI)
-_CLK_SET_PARENT(saif0_clk, SAIF0)
-_CLK_SET_PARENT(saif1_clk, SAIF1)
-
-#define _CLK_SET_PARENT_STUB(name)                                     \
-static int name##_set_parent(struct clk *clk, struct clk *parent)      \
-{                                                                      \
-       if (parent != clk->parent)                                      \
-               return -EINVAL;                                         \
-       else                                                            \
-               return 0;                                               \
-}
-
-_CLK_SET_PARENT_STUB(pwm_clk)
-_CLK_SET_PARENT_STUB(uart_clk)
-_CLK_SET_PARENT_STUB(clk32k_clk)
-_CLK_SET_PARENT_STUB(spdif_clk)
-_CLK_SET_PARENT_STUB(fec_clk)
-_CLK_SET_PARENT_STUB(can0_clk)
-_CLK_SET_PARENT_STUB(can1_clk)
-
-/*
- * clk definition
- */
-static struct clk cpu_clk = {
-       .get_rate = cpu_clk_get_rate,
-       .set_rate = cpu_clk_set_rate,
-       .set_parent = cpu_clk_set_parent,
-       .parent = &ref_cpu_clk,
-};
-
-static struct clk hbus_clk = {
-       .get_rate = hbus_clk_get_rate,
-       .parent = &cpu_clk,
-};
-
-static struct clk xbus_clk = {
-       .get_rate = xbus_clk_get_rate,
-       .set_rate = xbus_clk_set_rate,
-       .parent = &ref_xtal_clk,
-};
-
-static struct clk lradc_clk = {
-       .get_rate = lradc_clk_get_rate,
-       .parent = &clk32k_clk,
-};
-
-static struct clk rtc_clk = {
-       .get_rate = rtc_clk_get_rate,
-       .parent = &ref_xtal_clk,
-};
-
-/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
-static struct clk usb0_clk = {
-       .enable_reg = DIGCTRL_BASE_ADDR,
-       .enable_shift = 2,
-       .enable = _raw_clk_enable,
-       .disable = _raw_clk_disable,
-       .parent = &pll0_clk,
-};
-
-static struct clk usb1_clk = {
-       .enable_reg = DIGCTRL_BASE_ADDR,
-       .enable_shift = 16,
-       .enable = _raw_clk_enable,
-       .disable = _raw_clk_disable,
-       .parent = &pll1_clk,
-};
-
-#define _DEFINE_CLOCK(name, er, es, p)                                 \
-       static struct clk name = {                                      \
-               .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
-               .enable_shift   = BP_CLKCTRL_##er##_##es,               \
-               .get_rate       = name##_get_rate,                      \
-               .set_rate       = name##_set_rate,                      \
-               .set_parent     = name##_set_parent,                    \
-               .enable         = _raw_clk_enable,                      \
-               .disable        = _raw_clk_disable,                     \
-               .parent         = p,                                    \
-       }
-
-_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
-_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
-_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
-_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
-_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
-_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
-       { \
-               .dev_id = d, \
-               .con_id = n, \
-               .clk = &c, \
-       },
-
-static struct clk_lookup lookups[] = {
-       /* for amba bus driver */
-       _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
-       /* for amba-pl011 driver */
-       _REGISTER_CLOCK("duart", NULL, uart_clk)
-       _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
-       _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
-       _REGISTER_CLOCK("imx28-gpmi-nand", NULL, gpmi_clk)
-       _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
-       _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
-       _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
-       _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
-       _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
-       _REGISTER_CLOCK("rtc", NULL, rtc_clk)
-       _REGISTER_CLOCK("pll2", NULL, pll2_clk)
-       _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
-       _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
-       _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
-       _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
-       _REGISTER_CLOCK("mxs-mmc.2", NULL, ssp2_clk)
-       _REGISTER_CLOCK("mxs-mmc.3", NULL, ssp3_clk)
-       _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
-       _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
-       _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
-       _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
-       _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
-       _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
-       _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
-       _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
-       _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
-       _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
-       _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
-};
-
-static int clk_misc_init(void)
-{
-       u32 reg;
-       int ret;
-
-       /* Fix up parent per register setting */
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
-       cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
-                       &ref_xtal_clk : &ref_cpu_clk;
-       emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
-                       &ref_xtal_clk : &ref_emi_clk;
-       ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
-                       &ref_xtal_clk : &ref_io0_clk;
-       ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
-                       &ref_xtal_clk : &ref_io0_clk;
-       ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
-                       &ref_xtal_clk : &ref_io1_clk;
-       ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
-                       &ref_xtal_clk : &ref_io1_clk;
-       lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
-                       &ref_xtal_clk : &ref_pix_clk;
-       gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
-                       &ref_xtal_clk : &ref_gpmi_clk;
-       saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
-                       &ref_xtal_clk : &pll0_clk;
-       saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
-                       &ref_xtal_clk : &pll0_clk;
-
-       /* Use int div over frac when both are available */
-       __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
-       __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
-       __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
-       reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
-       reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
-       reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
-       reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
-       reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-       reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
-       reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
-
-       /* SAIF has to use frac div for functional operation */
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
-       reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
-
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
-       reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
-
-       /*
-        * Set safe hbus clock divider. A divider of 3 ensure that
-        * the Vddd voltage required for the cpu clock is sufficiently
-        * high for the hbus clock.
-        */
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
-       reg &= BM_CLKCTRL_HBUS_DIV;
-       reg |= 3 << BP_CLKCTRL_HBUS_DIV;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
-
-       ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_ASM_BUSY);
-
-       /* Gate off cpu clock in WFI for power saving */
-       __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
-                       CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
-
-       /*
-        * Extra fec clock setting
-        * The DENX M28 uses an external clock source
-        * and the clock output must not be enabled
-        */
-       if (!machine_is_m28evk()) {
-               reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
-               reg &= ~BM_CLKCTRL_ENET_SLEEP;
-               reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
-               __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
-       }
-
-       /*
-        * 480 MHz seems too high to be ssp clock source directly,
-        * so set frac0 to get a 288 MHz ref_io0.
-        */
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
-       reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
-       reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
-
-       return ret;
-}
-
-int __init mx28_clocks_init(void)
-{
-       clk_misc_init();
-
-       /*
-        * source ssp clock from ref_io0 than ref_xtal,
-        * as ref_xtal only provides 24 MHz as maximum.
-        */
-       clk_set_parent(&ssp0_clk, &ref_io0_clk);
-       clk_set_parent(&ssp1_clk, &ref_io0_clk);
-       clk_set_parent(&ssp2_clk, &ref_io1_clk);
-       clk_set_parent(&ssp3_clk, &ref_io1_clk);
-
-       clk_prepare_enable(&cpu_clk);
-       clk_prepare_enable(&hbus_clk);
-       clk_prepare_enable(&xbus_clk);
-       clk_prepare_enable(&emi_clk);
-       clk_prepare_enable(&uart_clk);
-
-       clk_set_parent(&lcdif_clk, &ref_pix_clk);
-       clk_set_parent(&saif0_clk, &pll0_clk);
-       clk_set_parent(&saif1_clk, &pll0_clk);
-
-       /*
-        * Set an initial clock rate for the saif internal logic to work
-        * properly. This is important when working in EXTMASTER mode that
-        * uses the other saif's BITCLK&LRCLK but it still needs a basic
-        * clock which should be fast enough for the internal logic.
-        */
-       clk_set_rate(&saif0_clk, 24000000);
-       clk_set_rate(&saif1_clk, 24000000);
-
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-       mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
-
-       return 0;
-}

diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
deleted file mode 100644 (file)
index 97a6f4a..0000000
--- a/arch/arm/mach-mxs/clock.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * Based on arch/arm/plat-omap/clock.c
- *
- * Copyright (C) 2004 - 2005 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-/* #define DEBUG */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
-#include <linux/semaphore.h>
-#include <linux/string.h>
-
-#include <mach/clock.h>
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-/*-------------------------------------------------------------------------
- * Standard clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
-
-static void __clk_disable(struct clk *clk)
-{
-       if (clk == NULL || IS_ERR(clk))
-               return;
-       WARN_ON(!clk->usecount);
-
-       if (!(--clk->usecount)) {
-               if (clk->disable)
-                       clk->disable(clk);
-               __clk_disable(clk->parent);
-       }
-}
-
-static int __clk_enable(struct clk *clk)
-{
-       if (clk == NULL || IS_ERR(clk))
-               return -EINVAL;
-
-       if (clk->usecount++ == 0) {
-               __clk_enable(clk->parent);
-
-               if (clk->enable)
-                       clk->enable(clk);
-       }
-       return 0;
-}
-
-/*
- * The clk_enable/clk_disable could be called by drivers in atomic context,
- * so they should not really hold mutex.  Instead, clk_prepare/clk_unprepare
- * can hold a mutex, as the pair will only be called in non-atomic context.
- * Before migrating to common clk framework, we can have __clk_enable and
- * __clk_disable called in clk_prepare/clk_unprepare with mutex held and
- * leave clk_enable/clk_disable as the dummy functions.
- */
-int clk_prepare(struct clk *clk)
-{
-       int ret = 0;
-
-       if (clk == NULL || IS_ERR(clk))
-               return -EINVAL;
-
-       mutex_lock(&clocks_mutex);
-       ret = __clk_enable(clk);
-       mutex_unlock(&clocks_mutex);
-
-       return ret;
-}
-EXPORT_SYMBOL(clk_prepare);
-
-void clk_unprepare(struct clk *clk)
-{
-       if (clk == NULL || IS_ERR(clk))
-               return;
-
-       mutex_lock(&clocks_mutex);
-       __clk_disable(clk);
-       mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_unprepare);
-
-int clk_enable(struct clk *clk)
-{
-       return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-       /* nothing to do */
-}
-EXPORT_SYMBOL(clk_disable);
-
-/* Retrieve the *current* clock rate. If the clock itself
- * does not provide a special calculation routine, ask
- * its parent and so on, until one is able to return
- * a valid clock rate
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-       if (clk == NULL || IS_ERR(clk))
-               return 0UL;
-
-       if (clk->get_rate)
-               return clk->get_rate(clk);
-
-       return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/* Round the requested clock rate to the nearest supported
- * rate that is less than or equal to the requested rate.
- * This is dependent on the clock's current parent.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-       if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
-               return 0;
-
-       return clk->round_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/* Set the clock to the requested clock rate. The rate must
- * match a supported rate exactly based on what clk_round_rate returns
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-       int ret = -EINVAL;
-
-       if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
-               return ret;
-
-       mutex_lock(&clocks_mutex);
-       ret = clk->set_rate(clk, rate);
-       mutex_unlock(&clocks_mutex);
-
-       return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/* Set the clock's parent to another clock source */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-       int ret = -EINVAL;
-       struct clk *old;
-
-       if (clk == NULL || IS_ERR(clk) || parent == NULL ||
-           IS_ERR(parent) || clk->set_parent == NULL)
-               return ret;
-
-       if (clk->usecount)
-               clk_prepare_enable(parent);
-
-       mutex_lock(&clocks_mutex);
-       ret = clk->set_parent(clk, parent);
-       if (ret == 0) {
-               old = clk->parent;
-               clk->parent = parent;
-       } else {
-               old = parent;
-       }
-       mutex_unlock(&clocks_mutex);
-
-       if (clk->usecount)
-               clk_disable(old);
-
-       return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/* Retrieve the clock's parent clock source */
-struct clk *clk_get_parent(struct clk *clk)
-{
-       struct clk *ret = NULL;
-
-       if (clk == NULL || IS_ERR(clk))
-               return ret;
-
-       return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);

diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
deleted file mode 100644 (file)
index 592c9ab..0000000
--- a/arch/arm/mach-mxs/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MACH_MXS_CLOCK_H__
-#define __MACH_MXS_CLOCK_H__
-
-#ifndef __ASSEMBLY__
-#include <linux/list.h>
-
-struct module;
-
-struct clk {
-       int id;
-       /* Source clock this clk depends on */
-       struct clk *parent;
-       /* Reference count of clock enable/disable */
-       __s8 usecount;
-       /* Register bit position for clock's enable/disable control. */
-       u8 enable_shift;
-       /* Register address for clock's enable/disable control. */
-       void __iomem *enable_reg;
-       u32 flags;
-       /* get the current clock rate (always a fresh value) */
-       unsigned long (*get_rate) (struct clk *);
-       /* Function ptr to set the clock to a new rate. The rate must match a
-          supported rate returned from round_rate. Leave blank if clock is not
-          programmable */
-       int (*set_rate) (struct clk *, unsigned long);
-       /* Function ptr to round the requested clock rate to the nearest
-          supported rate that is less than or equal to the requested rate. */
-       unsigned long (*round_rate) (struct clk *, unsigned long);
-       /* Function ptr to enable the clock. Leave blank if clock can not
-          be gated. */
-       int (*enable) (struct clk *);
-       /* Function ptr to disable the clock. Leave blank if clock can not
-          be gated. */
-       void (*disable) (struct clk *);
-       /* Function ptr to set the parent clock of the clock. */
-       int (*set_parent) (struct clk *, struct clk *);
-};
-
-int clk_register(struct clk *clk);
-void clk_unregister(struct clk *clk);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __MACH_MXS_CLOCK_H__ */

diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index c50c3ea..84af61c 100644 (file)
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -11,19 +11,19 @@
 #ifndef __MACH_MXS_COMMON_H__
 #define __MACH_MXS_COMMON_H__
 
-struct clk;
-
 extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
-extern void mxs_timer_init(struct clk *, int);
+extern void mxs_timer_init(int);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
+extern void mx23_soc_init(void);
 extern int mx23_register_gpios(void);
 extern int mx23_clocks_init(void);
 extern void mx23_map_io(void);
 extern void mx23_init_irq(void);
 
+extern void mx28_soc_init(void);
 extern int mx28_register_gpios(void);
 extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
@@ -31,6 +31,4 @@ extern void mx28_init_irq(void);
 
 extern void icoll_init_irq(void);
 
-extern int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask);
-
 #endif /* __MACH_MXS_COMMON_H__ */

diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
index 48a7fab..5e90b9d 100644 (file)
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ b/arch/arm/mach-mxs/mach-apx4devkit.c
@@ -207,6 +207,8 @@ static int apx4devkit_phy_fixup(struct phy_device *phy)
 
 static void __init apx4devkit_init(void)
 {
+       mx28_soc_init();
+
        mxs_iomux_setup_multiple_pads(apx4devkit_pads,
                        ARRAY_SIZE(apx4devkit_pads));
 

diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 06d7996..4c00c87 100644 (file)
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -319,6 +319,8 @@ static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
 
 static void __init m28evk_init(void)
 {
+       mx28_soc_init();
+
        mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
 
        mx28_add_duart();

diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 5ea1c57..e7272a4 100644 (file)
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -141,6 +141,8 @@ static void __init mx23evk_init(void)
 {
        int ret;
 
+       mx23_soc_init();
+
        mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
 
        mx23_add_duart();

diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index e386c14..dafd48e 100644 (file)
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -226,7 +226,7 @@ static void __init mx28evk_fec_reset(void)
        struct clk *clk;
 
        /* Enable fec phy clock */
-       clk = clk_get_sys("pll2", NULL);
+       clk = clk_get_sys("enet_out", NULL);
        if (!IS_ERR(clk))
                clk_prepare_enable(clk);
 
@@ -413,6 +413,8 @@ static void __init mx28evk_init(void)
 {
        int ret;
 
+       mx28_soc_init();
+
        mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
 
        mx28_add_duart();

diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index a626c07..6548965 100644 (file)
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -85,6 +85,8 @@ static void __init stmp378x_dvb_init(void)
 {
        int ret;
 
+       mx23_soc_init();
+
        mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
                        ARRAY_SIZE(stmp378x_dvb_pads));
 

diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 2c0862e..8837029 100644 (file)
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -146,6 +146,8 @@ static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
 
 static void __init tx28_stk5v3_init(void)
 {
+       mx28_soc_init();
+
        mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
                        ARRAY_SIZE(tx28_stk5v3_pads));
 

diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index 50af5ce..67a384e 100644 (file)
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,6 +13,7 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/map.h>
 
@@ -61,3 +62,13 @@ void __init mx28_init_irq(void)
 {
        icoll_init_irq();
 }
+
+void __init mx23_soc_init(void)
+{
+       pinctrl_provide_dummies();
+}
+
+void __init mx28_soc_init(void)
+{
+       pinctrl_provide_dummies();
+}

diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
deleted file mode 100644 (file)
index 0ea5c9d..0000000
--- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * Freescale CLKCTRL Register Definitions
- *
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.48
- * Template revision: 26195
- */
-
-#ifndef __REGS_CLKCTRL_MX23_H__
-#define __REGS_CLKCTRL_MX23_H__
-
-
-#define HW_CLKCTRL_PLLCTRL0    (0x00000000)
-#define HW_CLKCTRL_PLLCTRL0_SET        (0x00000004)
-#define HW_CLKCTRL_PLLCTRL0_CLR        (0x00000008)
-#define HW_CLKCTRL_PLLCTRL0_TOG        (0x0000000c)
-
-#define BP_CLKCTRL_PLLCTRL0_LFR_SEL    28
-#define BM_CLKCTRL_PLLCTRL0_LFR_SEL    0x30000000
-#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)  \
-               (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLLCTRL0_CP_SEL     24
-#define BM_CLKCTRL_PLLCTRL0_CP_SEL     0x03000000
-#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)  \
-               (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLLCTRL0_DIV_SEL    20
-#define BM_CLKCTRL_PLLCTRL0_DIV_SEL    0x00300000
-#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)  \
-               (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER     0x1
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST    0x2
-#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS        0x00040000
-#define BM_CLKCTRL_PLLCTRL0_POWER      0x00010000
-
-#define HW_CLKCTRL_PLLCTRL1    (0x00000010)
-
-#define BM_CLKCTRL_PLLCTRL1_LOCK       0x80000000
-#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
-#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
-#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
-#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)  \
-               (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
-
-#define HW_CLKCTRL_CPU (0x00000020)
-#define HW_CLKCTRL_CPU_SET     (0x00000024)
-#define HW_CLKCTRL_CPU_CLR     (0x00000028)
-#define HW_CLKCTRL_CPU_TOG     (0x0000002c)
-
-#define BM_CLKCTRL_CPU_BUSY_REF_XTAL   0x20000000
-#define BM_CLKCTRL_CPU_BUSY_REF_CPU    0x10000000
-#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN        0x04000000
-#define BP_CLKCTRL_CPU_DIV_XTAL        16
-#define BM_CLKCTRL_CPU_DIV_XTAL        0x03FF0000
-#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
-               (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BM_CLKCTRL_CPU_INTERRUPT_WAIT  0x00001000
-#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
-#define BP_CLKCTRL_CPU_DIV_CPU 0
-#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
-#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
-               (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
-
-#define HW_CLKCTRL_HBUS        (0x00000030)
-#define HW_CLKCTRL_HBUS_SET    (0x00000034)
-#define HW_CLKCTRL_HBUS_CLR    (0x00000038)
-#define HW_CLKCTRL_HBUS_TOG    (0x0000003c)
-
-#define BM_CLKCTRL_HBUS_BUSY   0x20000000
-#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE  0x10000000
-#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE  0x08000000
-#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE      0x04000000
-#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE      0x02000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE  0x01000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE      0x00800000
-#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE     0x00400000
-#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE    0x00200000
-#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
-#define BP_CLKCTRL_HBUS_SLOW_DIV       16
-#define BM_CLKCTRL_HBUS_SLOW_DIV       0x00070000
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
-               (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN    0x00000020
-#define BP_CLKCTRL_HBUS_DIV    0
-#define BM_CLKCTRL_HBUS_DIV    0x0000001F
-#define BF_CLKCTRL_HBUS_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
-
-#define HW_CLKCTRL_XBUS        (0x00000040)
-
-#define BM_CLKCTRL_XBUS_BUSY   0x80000000
-#define BM_CLKCTRL_XBUS_DIV_FRAC_EN    0x00000400
-#define BP_CLKCTRL_XBUS_DIV    0
-#define BM_CLKCTRL_XBUS_DIV    0x000003FF
-#define BF_CLKCTRL_XBUS_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
-
-#define HW_CLKCTRL_XTAL        (0x00000050)
-#define HW_CLKCTRL_XTAL_SET    (0x00000054)
-#define HW_CLKCTRL_XTAL_CLR    (0x00000058)
-#define HW_CLKCTRL_XTAL_TOG    (0x0000005c)
-
-#define BP_CLKCTRL_XTAL_UART_CLK_GATE  31
-#define BM_CLKCTRL_XTAL_UART_CLK_GATE  0x80000000
-#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE       30
-#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE       0x40000000
-#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE        29
-#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE        0x20000000
-#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE        0x10000000
-#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE     0x08000000
-#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE     26
-#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE     0x04000000
-#define BP_CLKCTRL_XTAL_DIV_UART       0
-#define BM_CLKCTRL_XTAL_DIV_UART       0x00000003
-#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
-               (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
-
-#define HW_CLKCTRL_PIX (0x00000060)
-
-#define BP_CLKCTRL_PIX_CLKGATE 31
-#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
-#define BM_CLKCTRL_PIX_BUSY    0x20000000
-#define BM_CLKCTRL_PIX_DIV_FRAC_EN     0x00001000
-#define BP_CLKCTRL_PIX_DIV     0
-#define BM_CLKCTRL_PIX_DIV     0x00000FFF
-#define BF_CLKCTRL_PIX_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_PIX_DIV)
-
-#define HW_CLKCTRL_SSP (0x00000070)
-
-#define BP_CLKCTRL_SSP_CLKGATE 31
-#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
-#define BM_CLKCTRL_SSP_BUSY    0x20000000
-#define BM_CLKCTRL_SSP_DIV_FRAC_EN     0x00000200
-#define BP_CLKCTRL_SSP_DIV     0
-#define BM_CLKCTRL_SSP_DIV     0x000001FF
-#define BF_CLKCTRL_SSP_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_SSP_DIV)
-
-#define HW_CLKCTRL_GPMI        (0x00000080)
-
-#define BP_CLKCTRL_GPMI_CLKGATE        31
-#define BM_CLKCTRL_GPMI_CLKGATE        0x80000000
-#define BM_CLKCTRL_GPMI_BUSY   0x20000000
-#define BM_CLKCTRL_GPMI_DIV_FRAC_EN    0x00000400
-#define BP_CLKCTRL_GPMI_DIV    0
-#define BM_CLKCTRL_GPMI_DIV    0x000003FF
-#define BF_CLKCTRL_GPMI_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
-
-#define HW_CLKCTRL_SPDIF       (0x00000090)
-
-#define BM_CLKCTRL_SPDIF_CLKGATE       0x80000000
-
-#define HW_CLKCTRL_EMI (0x000000a0)
-
-#define BP_CLKCTRL_EMI_CLKGATE 31
-#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_EMI_SYNC_MODE_EN    0x40000000
-#define BM_CLKCTRL_EMI_BUSY_REF_XTAL   0x20000000
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI    0x10000000
-#define BM_CLKCTRL_EMI_BUSY_REF_CPU    0x08000000
-#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE  0x04000000
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE       0x00010000
-#define BP_CLKCTRL_EMI_DIV_XTAL        8
-#define BM_CLKCTRL_EMI_DIV_XTAL        0x00000F00
-#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
-               (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_DIV_EMI 0
-#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
-#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
-               (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
-
-#define HW_CLKCTRL_IR  (0x000000b0)
-
-#define BM_CLKCTRL_IR_CLKGATE  0x80000000
-#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
-#define BM_CLKCTRL_IR_IR_BUSY  0x10000000
-#define BM_CLKCTRL_IR_IROV_BUSY        0x08000000
-#define BP_CLKCTRL_IR_IROV_DIV 16
-#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
-#define BF_CLKCTRL_IR_IROV_DIV(v)  \
-               (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
-#define BP_CLKCTRL_IR_IR_DIV   0
-#define BM_CLKCTRL_IR_IR_DIV   0x000003FF
-#define BF_CLKCTRL_IR_IR_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
-
-#define HW_CLKCTRL_SAIF        (0x000000c0)
-
-#define BM_CLKCTRL_SAIF_CLKGATE        0x80000000
-#define BM_CLKCTRL_SAIF_BUSY   0x20000000
-#define BM_CLKCTRL_SAIF_DIV_FRAC_EN    0x00010000
-#define BP_CLKCTRL_SAIF_DIV    0
-#define BM_CLKCTRL_SAIF_DIV    0x0000FFFF
-#define BF_CLKCTRL_SAIF_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
-
-#define HW_CLKCTRL_TV  (0x000000d0)
-
-#define BM_CLKCTRL_TV_CLK_TV108M_GATE  0x80000000
-#define BM_CLKCTRL_TV_CLK_TV_GATE      0x40000000
-
-#define HW_CLKCTRL_ETM (0x000000e0)
-
-#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
-#define BM_CLKCTRL_ETM_BUSY    0x20000000
-#define BM_CLKCTRL_ETM_DIV_FRAC_EN     0x00000040
-#define BP_CLKCTRL_ETM_DIV     0
-#define BM_CLKCTRL_ETM_DIV     0x0000003F
-#define BF_CLKCTRL_ETM_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_ETM_DIV)
-
-#define HW_CLKCTRL_FRAC        (0x000000f0)
-#define HW_CLKCTRL_FRAC_SET    (0x000000f4)
-#define HW_CLKCTRL_FRAC_CLR    (0x000000f8)
-#define HW_CLKCTRL_FRAC_TOG    (0x000000fc)
-
-#define BP_CLKCTRL_FRAC_CLKGATEIO      31
-#define BM_CLKCTRL_FRAC_CLKGATEIO      0x80000000
-#define BM_CLKCTRL_FRAC_IO_STABLE      0x40000000
-#define BP_CLKCTRL_FRAC_IOFRAC 24
-#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
-#define BF_CLKCTRL_FRAC_IOFRAC(v)  \
-               (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
-#define BP_CLKCTRL_FRAC_CLKGATEPIX     23
-#define BM_CLKCTRL_FRAC_CLKGATEPIX     0x00800000
-#define BM_CLKCTRL_FRAC_PIX_STABLE     0x00400000
-#define BP_CLKCTRL_FRAC_PIXFRAC        16
-#define BM_CLKCTRL_FRAC_PIXFRAC        0x003F0000
-#define BF_CLKCTRL_FRAC_PIXFRAC(v)  \
-               (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
-#define BP_CLKCTRL_FRAC_CLKGATEEMI     15
-#define BM_CLKCTRL_FRAC_CLKGATEEMI     0x00008000
-#define BM_CLKCTRL_FRAC_EMI_STABLE     0x00004000
-#define BP_CLKCTRL_FRAC_EMIFRAC        8
-#define BM_CLKCTRL_FRAC_EMIFRAC        0x00003F00
-#define BF_CLKCTRL_FRAC_EMIFRAC(v)  \
-               (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
-#define BP_CLKCTRL_FRAC_CLKGATECPU     7
-#define BM_CLKCTRL_FRAC_CLKGATECPU     0x00000080
-#define BM_CLKCTRL_FRAC_CPU_STABLE     0x00000040
-#define BP_CLKCTRL_FRAC_CPUFRAC        0
-#define BM_CLKCTRL_FRAC_CPUFRAC        0x0000003F
-#define BF_CLKCTRL_FRAC_CPUFRAC(v)  \
-               (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
-
-#define HW_CLKCTRL_FRAC1       (0x00000100)
-#define HW_CLKCTRL_FRAC1_SET   (0x00000104)
-#define HW_CLKCTRL_FRAC1_CLR   (0x00000108)
-#define HW_CLKCTRL_FRAC1_TOG   (0x0000010c)
-
-#define BM_CLKCTRL_FRAC1_CLKGATEVID    0x80000000
-#define BM_CLKCTRL_FRAC1_VID_STABLE    0x40000000
-
-#define HW_CLKCTRL_CLKSEQ      (0x00000110)
-#define HW_CLKCTRL_CLKSEQ_SET  (0x00000114)
-#define HW_CLKCTRL_CLKSEQ_CLR  (0x00000118)
-#define HW_CLKCTRL_CLKSEQ_TOG  (0x0000011c)
-
-#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM   0x00000100
-#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU   0x00000080
-#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI   0x00000040
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP   0x00000020
-#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI  0x00000010
-#define BM_CLKCTRL_CLKSEQ_BYPASS_IR    0x00000008
-#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX   0x00000002
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF  0x00000001
-
-#define HW_CLKCTRL_RESET       (0x00000120)
-
-#define BM_CLKCTRL_RESET_CHIP  0x00000002
-#define BM_CLKCTRL_RESET_DIG   0x00000001
-
-#define HW_CLKCTRL_STATUS      (0x00000130)
-
-#define BP_CLKCTRL_STATUS_CPU_LIMIT    30
-#define BM_CLKCTRL_STATUS_CPU_LIMIT    0xC0000000
-#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
-               (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-
-#define HW_CLKCTRL_VERSION     (0x00000140)
-
-#define BP_CLKCTRL_VERSION_MAJOR       24
-#define BM_CLKCTRL_VERSION_MAJOR       0xFF000000
-#define BF_CLKCTRL_VERSION_MAJOR(v) \
-               (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
-#define BP_CLKCTRL_VERSION_MINOR       16
-#define BM_CLKCTRL_VERSION_MINOR       0x00FF0000
-#define BF_CLKCTRL_VERSION_MINOR(v)  \
-               (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
-#define BP_CLKCTRL_VERSION_STEP        0
-#define BM_CLKCTRL_VERSION_STEP        0x0000FFFF
-#define BF_CLKCTRL_VERSION_STEP(v)  \
-               (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
-
-#endif /* __REGS_CLKCTRL_MX23_H__ */

diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
deleted file mode 100644 (file)
index 7d1b061..0000000
--- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h
+++ /dev/null
@@ -1,486 +0,0 @@
-/*
- * Freescale CLKCTRL Register Definitions
- *
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- * This file is created by xml file. Don't Edit it.
- *
- * Xml Revision: 1.48
- * Template revision: 26195
- */
-
-#ifndef __REGS_CLKCTRL_MX28_H__
-#define __REGS_CLKCTRL_MX28_H__
-
-#define HW_CLKCTRL_PLL0CTRL0   (0x00000000)
-#define HW_CLKCTRL_PLL0CTRL0_SET       (0x00000004)
-#define HW_CLKCTRL_PLL0CTRL0_CLR       (0x00000008)
-#define HW_CLKCTRL_PLL0CTRL0_TOG       (0x0000000c)
-
-#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL   28
-#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL   0x30000000
-#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v)  \
-               (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_CP_SEL    24
-#define BM_CLKCTRL_PLL0CTRL0_CP_SEL    0x03000000
-#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v)  \
-               (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL   20
-#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL   0x00300000
-#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v)  \
-               (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER     0x1
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST    0x2
-#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS       0x00040000
-#define BM_CLKCTRL_PLL0CTRL0_POWER     0x00020000
-
-#define HW_CLKCTRL_PLL0CTRL1   (0x00000010)
-
-#define BM_CLKCTRL_PLL0CTRL1_LOCK      0x80000000
-#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK        0x40000000
-#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT        0
-#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT        0x0000FFFF
-#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v)  \
-               (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
-
-#define HW_CLKCTRL_PLL1CTRL0   (0x00000020)
-#define HW_CLKCTRL_PLL1CTRL0_SET       (0x00000024)
-#define HW_CLKCTRL_PLL1CTRL0_CLR       (0x00000028)
-#define HW_CLKCTRL_PLL1CTRL0_TOG       (0x0000002c)
-
-#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI        0x80000000
-#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL   28
-#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL   0x30000000
-#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v)  \
-               (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_CP_SEL    24
-#define BM_CLKCTRL_PLL1CTRL0_CP_SEL    0x03000000
-#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v)  \
-               (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2   0x1
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05  0x2
-#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
-#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL   20
-#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL   0x00300000
-#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v)  \
-               (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT   0x0
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER     0x1
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST    0x2
-#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS       0x00040000
-#define BM_CLKCTRL_PLL1CTRL0_POWER     0x00020000
-
-#define HW_CLKCTRL_PLL1CTRL1   (0x00000030)
-
-#define BM_CLKCTRL_PLL1CTRL1_LOCK      0x80000000
-#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK        0x40000000
-#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT        0
-#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT        0x0000FFFF
-#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v)  \
-               (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
-
-#define HW_CLKCTRL_PLL2CTRL0   (0x00000040)
-#define HW_CLKCTRL_PLL2CTRL0_SET       (0x00000044)
-#define HW_CLKCTRL_PLL2CTRL0_CLR       (0x00000048)
-#define HW_CLKCTRL_PLL2CTRL0_TOG       (0x0000004c)
-
-#define BM_CLKCTRL_PLL2CTRL0_CLKGATE   0x80000000
-#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL   28
-#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL   0x30000000
-#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v)  \
-               (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
-#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B   0x04000000
-#define BP_CLKCTRL_PLL2CTRL0_CP_SEL    24
-#define BM_CLKCTRL_PLL2CTRL0_CP_SEL    0x03000000
-#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v)  \
-               (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
-#define BM_CLKCTRL_PLL2CTRL0_POWER     0x00800000
-
-#define HW_CLKCTRL_CPU (0x00000050)
-#define HW_CLKCTRL_CPU_SET     (0x00000054)
-#define HW_CLKCTRL_CPU_CLR     (0x00000058)
-#define HW_CLKCTRL_CPU_TOG     (0x0000005c)
-
-#define BM_CLKCTRL_CPU_BUSY_REF_XTAL   0x20000000
-#define BM_CLKCTRL_CPU_BUSY_REF_CPU    0x10000000
-#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN        0x04000000
-#define BP_CLKCTRL_CPU_DIV_XTAL        16
-#define BM_CLKCTRL_CPU_DIV_XTAL        0x03FF0000
-#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
-               (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
-#define BM_CLKCTRL_CPU_INTERRUPT_WAIT  0x00001000
-#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
-#define BP_CLKCTRL_CPU_DIV_CPU 0
-#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
-#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
-               (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
-
-#define HW_CLKCTRL_HBUS        (0x00000060)
-#define HW_CLKCTRL_HBUS_SET    (0x00000064)
-#define HW_CLKCTRL_HBUS_CLR    (0x00000068)
-#define HW_CLKCTRL_HBUS_TOG    (0x0000006c)
-
-#define BM_CLKCTRL_HBUS_ASM_BUSY       0x80000000
-#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE  0x40000000
-#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE  0x20000000
-#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE  0x08000000
-#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE      0x04000000
-#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE      0x02000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE  0x01000000
-#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE      0x00800000
-#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE     0x00400000
-#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE    0x00200000
-#define BM_CLKCTRL_HBUS_ASM_ENABLE     0x00100000
-#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE  0x00080000
-#define BP_CLKCTRL_HBUS_SLOW_DIV       16
-#define BM_CLKCTRL_HBUS_SLOW_DIV       0x00070000
-#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
-               (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
-#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN    0x00000020
-#define BP_CLKCTRL_HBUS_DIV    0
-#define BM_CLKCTRL_HBUS_DIV    0x0000001F
-#define BF_CLKCTRL_HBUS_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
-
-#define HW_CLKCTRL_XBUS        (0x00000070)
-
-#define BM_CLKCTRL_XBUS_BUSY   0x80000000
-#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE  0x00000800
-#define BM_CLKCTRL_XBUS_DIV_FRAC_EN    0x00000400
-#define BP_CLKCTRL_XBUS_DIV    0
-#define BM_CLKCTRL_XBUS_DIV    0x000003FF
-#define BF_CLKCTRL_XBUS_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
-
-#define HW_CLKCTRL_XTAL        (0x00000080)
-#define HW_CLKCTRL_XTAL_SET    (0x00000084)
-#define HW_CLKCTRL_XTAL_CLR    (0x00000088)
-#define HW_CLKCTRL_XTAL_TOG    (0x0000008c)
-
-#define BP_CLKCTRL_XTAL_UART_CLK_GATE  31
-#define BM_CLKCTRL_XTAL_UART_CLK_GATE  0x80000000
-#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE        29
-#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE        0x20000000
-#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE     26
-#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE     0x04000000
-#define BP_CLKCTRL_XTAL_DIV_UART       0
-#define BM_CLKCTRL_XTAL_DIV_UART       0x00000003
-#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
-               (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
-
-#define HW_CLKCTRL_SSP0        (0x00000090)
-
-#define BP_CLKCTRL_SSP0_CLKGATE        31
-#define BM_CLKCTRL_SSP0_CLKGATE        0x80000000
-#define BM_CLKCTRL_SSP0_BUSY   0x20000000
-#define BM_CLKCTRL_SSP0_DIV_FRAC_EN    0x00000200
-#define BP_CLKCTRL_SSP0_DIV    0
-#define BM_CLKCTRL_SSP0_DIV    0x000001FF
-#define BF_CLKCTRL_SSP0_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
-
-#define HW_CLKCTRL_SSP1        (0x000000a0)
-
-#define BP_CLKCTRL_SSP1_CLKGATE        31
-#define BM_CLKCTRL_SSP1_CLKGATE        0x80000000
-#define BM_CLKCTRL_SSP1_BUSY   0x20000000
-#define BM_CLKCTRL_SSP1_DIV_FRAC_EN    0x00000200
-#define BP_CLKCTRL_SSP1_DIV    0
-#define BM_CLKCTRL_SSP1_DIV    0x000001FF
-#define BF_CLKCTRL_SSP1_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
-
-#define HW_CLKCTRL_SSP2        (0x000000b0)
-
-#define BP_CLKCTRL_SSP2_CLKGATE        31
-#define BM_CLKCTRL_SSP2_CLKGATE        0x80000000
-#define BM_CLKCTRL_SSP2_BUSY   0x20000000
-#define BM_CLKCTRL_SSP2_DIV_FRAC_EN    0x00000200
-#define BP_CLKCTRL_SSP2_DIV    0
-#define BM_CLKCTRL_SSP2_DIV    0x000001FF
-#define BF_CLKCTRL_SSP2_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
-
-#define HW_CLKCTRL_SSP3        (0x000000c0)
-
-#define BP_CLKCTRL_SSP3_CLKGATE        31
-#define BM_CLKCTRL_SSP3_CLKGATE        0x80000000
-#define BM_CLKCTRL_SSP3_BUSY   0x20000000
-#define BM_CLKCTRL_SSP3_DIV_FRAC_EN    0x00000200
-#define BP_CLKCTRL_SSP3_DIV    0
-#define BM_CLKCTRL_SSP3_DIV    0x000001FF
-#define BF_CLKCTRL_SSP3_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
-
-#define HW_CLKCTRL_GPMI        (0x000000d0)
-
-#define BP_CLKCTRL_GPMI_CLKGATE        31
-#define BM_CLKCTRL_GPMI_CLKGATE        0x80000000
-#define BM_CLKCTRL_GPMI_BUSY   0x20000000
-#define BM_CLKCTRL_GPMI_DIV_FRAC_EN    0x00000400
-#define BP_CLKCTRL_GPMI_DIV    0
-#define BM_CLKCTRL_GPMI_DIV    0x000003FF
-#define BF_CLKCTRL_GPMI_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
-
-#define HW_CLKCTRL_SPDIF       (0x000000e0)
-
-#define BP_CLKCTRL_SPDIF_CLKGATE       31
-#define BM_CLKCTRL_SPDIF_CLKGATE       0x80000000
-
-#define HW_CLKCTRL_EMI (0x000000f0)
-
-#define BP_CLKCTRL_EMI_CLKGATE 31
-#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
-#define BM_CLKCTRL_EMI_SYNC_MODE_EN    0x40000000
-#define BM_CLKCTRL_EMI_BUSY_REF_XTAL   0x20000000
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI    0x10000000
-#define BM_CLKCTRL_EMI_BUSY_REF_CPU    0x08000000
-#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE  0x04000000
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE       0x00010000
-#define BP_CLKCTRL_EMI_DIV_XTAL        8
-#define BM_CLKCTRL_EMI_DIV_XTAL        0x00000F00
-#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
-               (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
-#define BP_CLKCTRL_EMI_DIV_EMI 0
-#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
-#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
-               (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
-
-#define HW_CLKCTRL_SAIF0       (0x00000100)
-
-#define BP_CLKCTRL_SAIF0_CLKGATE       31
-#define BM_CLKCTRL_SAIF0_CLKGATE       0x80000000
-#define BM_CLKCTRL_SAIF0_BUSY  0x20000000
-#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN   0x00010000
-#define BP_CLKCTRL_SAIF0_DIV   0
-#define BM_CLKCTRL_SAIF0_DIV   0x0000FFFF
-#define BF_CLKCTRL_SAIF0_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
-
-#define HW_CLKCTRL_SAIF1       (0x00000110)
-
-#define BP_CLKCTRL_SAIF1_CLKGATE       31
-#define BM_CLKCTRL_SAIF1_CLKGATE       0x80000000
-#define BM_CLKCTRL_SAIF1_BUSY  0x20000000
-#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN   0x00010000
-#define BP_CLKCTRL_SAIF1_DIV   0
-#define BM_CLKCTRL_SAIF1_DIV   0x0000FFFF
-#define BF_CLKCTRL_SAIF1_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
-
-#define HW_CLKCTRL_DIS_LCDIF   (0x00000120)
-
-#define BP_CLKCTRL_DIS_LCDIF_CLKGATE   31
-#define BM_CLKCTRL_DIS_LCDIF_CLKGATE   0x80000000
-#define BM_CLKCTRL_DIS_LCDIF_BUSY      0x20000000
-#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN       0x00002000
-#define BP_CLKCTRL_DIS_LCDIF_DIV       0
-#define BM_CLKCTRL_DIS_LCDIF_DIV       0x00001FFF
-#define BF_CLKCTRL_DIS_LCDIF_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
-
-#define HW_CLKCTRL_ETM (0x00000130)
-
-#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
-#define BM_CLKCTRL_ETM_BUSY    0x20000000
-#define BM_CLKCTRL_ETM_DIV_FRAC_EN     0x00000080
-#define BP_CLKCTRL_ETM_DIV     0
-#define BM_CLKCTRL_ETM_DIV     0x0000007F
-#define BF_CLKCTRL_ETM_DIV(v)  \
-               (((v) << 0) & BM_CLKCTRL_ETM_DIV)
-
-#define HW_CLKCTRL_ENET        (0x00000140)
-
-#define BM_CLKCTRL_ENET_SLEEP  0x80000000
-#define BP_CLKCTRL_ENET_DISABLE        30
-#define BM_CLKCTRL_ENET_DISABLE        0x40000000
-#define BM_CLKCTRL_ENET_STATUS 0x20000000
-#define BM_CLKCTRL_ENET_BUSY_TIME      0x08000000
-#define BP_CLKCTRL_ENET_DIV_TIME       21
-#define BM_CLKCTRL_ENET_DIV_TIME       0x07E00000
-#define BF_CLKCTRL_ENET_DIV_TIME(v)  \
-               (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
-#define BM_CLKCTRL_ENET_BUSY   0x08000000
-#define BP_CLKCTRL_ENET_DIV    21
-#define BM_CLKCTRL_ENET_DIV    0x07E00000
-#define BF_CLKCTRL_ENET_DIV(v)  \
-               (((v) << 21) & BM_CLKCTRL_ENET_DIV)
-#define BP_CLKCTRL_ENET_TIME_SEL       19
-#define BM_CLKCTRL_ENET_TIME_SEL       0x00180000
-#define BF_CLKCTRL_ENET_TIME_SEL(v)  \
-               (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
-#define BV_CLKCTRL_ENET_TIME_SEL__XTAL      0x0
-#define BV_CLKCTRL_ENET_TIME_SEL__PLL       0x1
-#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK  0x2
-#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
-#define BM_CLKCTRL_ENET_CLK_OUT_EN     0x00040000
-#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP       0x00020000
-#define BM_CLKCTRL_ENET_RESET_BY_SW    0x00010000
-
-#define HW_CLKCTRL_HSADC       (0x00000150)
-
-#define BM_CLKCTRL_HSADC_RESETB        0x40000000
-#define BP_CLKCTRL_HSADC_FREQDIV       28
-#define BM_CLKCTRL_HSADC_FREQDIV       0x30000000
-#define BF_CLKCTRL_HSADC_FREQDIV(v)  \
-               (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
-
-#define HW_CLKCTRL_FLEXCAN     (0x00000160)
-
-#define BP_CLKCTRL_FLEXCAN_STOP_CAN0   30
-#define BM_CLKCTRL_FLEXCAN_STOP_CAN0   0x40000000
-#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
-#define BP_CLKCTRL_FLEXCAN_STOP_CAN1   28
-#define BM_CLKCTRL_FLEXCAN_STOP_CAN1   0x10000000
-#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
-
-#define HW_CLKCTRL_FRAC0       (0x000001b0)
-#define HW_CLKCTRL_FRAC0_SET   (0x000001b4)
-#define HW_CLKCTRL_FRAC0_CLR   (0x000001b8)
-#define HW_CLKCTRL_FRAC0_TOG   (0x000001bc)
-
-#define BP_CLKCTRL_FRAC0_CLKGATEIO0    31
-#define BM_CLKCTRL_FRAC0_CLKGATEIO0    0x80000000
-#define BM_CLKCTRL_FRAC0_IO0_STABLE    0x40000000
-#define BP_CLKCTRL_FRAC0_IO0FRAC       24
-#define BM_CLKCTRL_FRAC0_IO0FRAC       0x3F000000
-#define BF_CLKCTRL_FRAC0_IO0FRAC(v)  \
-               (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
-#define BP_CLKCTRL_FRAC0_CLKGATEIO1    23
-#define BM_CLKCTRL_FRAC0_CLKGATEIO1    0x00800000
-#define BM_CLKCTRL_FRAC0_IO1_STABLE    0x00400000
-#define BP_CLKCTRL_FRAC0_IO1FRAC       16
-#define BM_CLKCTRL_FRAC0_IO1FRAC       0x003F0000
-#define BF_CLKCTRL_FRAC0_IO1FRAC(v)  \
-               (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
-#define BP_CLKCTRL_FRAC0_CLKGATEEMI    15
-#define BM_CLKCTRL_FRAC0_CLKGATEEMI    0x00008000
-#define BM_CLKCTRL_FRAC0_EMI_STABLE    0x00004000
-#define BP_CLKCTRL_FRAC0_EMIFRAC       8
-#define BM_CLKCTRL_FRAC0_EMIFRAC       0x00003F00
-#define BF_CLKCTRL_FRAC0_EMIFRAC(v)  \
-               (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
-#define BP_CLKCTRL_FRAC0_CLKGATECPU    7
-#define BM_CLKCTRL_FRAC0_CLKGATECPU    0x00000080
-#define BM_CLKCTRL_FRAC0_CPU_STABLE    0x00000040
-#define BP_CLKCTRL_FRAC0_CPUFRAC       0
-#define BM_CLKCTRL_FRAC0_CPUFRAC       0x0000003F
-#define BF_CLKCTRL_FRAC0_CPUFRAC(v)  \
-               (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
-
-#define HW_CLKCTRL_FRAC1       (0x000001c0)
-#define HW_CLKCTRL_FRAC1_SET   (0x000001c4)
-#define HW_CLKCTRL_FRAC1_CLR   (0x000001c8)
-#define HW_CLKCTRL_FRAC1_TOG   (0x000001cc)
-
-#define BP_CLKCTRL_FRAC1_CLKGATEGPMI   23
-#define BM_CLKCTRL_FRAC1_CLKGATEGPMI   0x00800000
-#define BM_CLKCTRL_FRAC1_GPMI_STABLE   0x00400000
-#define BP_CLKCTRL_FRAC1_GPMIFRAC      16
-#define BM_CLKCTRL_FRAC1_GPMIFRAC      0x003F0000
-#define BF_CLKCTRL_FRAC1_GPMIFRAC(v)  \
-               (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
-#define BP_CLKCTRL_FRAC1_CLKGATEHSADC  15
-#define BM_CLKCTRL_FRAC1_CLKGATEHSADC  0x00008000
-#define BM_CLKCTRL_FRAC1_HSADC_STABLE  0x00004000
-#define BP_CLKCTRL_FRAC1_HSADCFRAC     8
-#define BM_CLKCTRL_FRAC1_HSADCFRAC     0x00003F00
-#define BF_CLKCTRL_FRAC1_HSADCFRAC(v)  \
-               (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
-#define BP_CLKCTRL_FRAC1_CLKGATEPIX    7
-#define BM_CLKCTRL_FRAC1_CLKGATEPIX    0x00000080
-#define BM_CLKCTRL_FRAC1_PIX_STABLE    0x00000040
-#define BP_CLKCTRL_FRAC1_PIXFRAC       0
-#define BM_CLKCTRL_FRAC1_PIXFRAC       0x0000003F
-#define BF_CLKCTRL_FRAC1_PIXFRAC(v)  \
-               (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
-
-#define HW_CLKCTRL_CLKSEQ      (0x000001d0)
-#define HW_CLKCTRL_CLKSEQ_SET  (0x000001d4)
-#define HW_CLKCTRL_CLKSEQ_CLR  (0x000001d8)
-#define HW_CLKCTRL_CLKSEQ_TOG  (0x000001dc)
-
-#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU   0x00040000
-#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF     0x00004000
-#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
-#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD    0x0
-#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM   0x00000100
-#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI   0x00000080
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3  0x00000040
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2  0x00000020
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1  0x00000010
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0  0x00000008
-#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI  0x00000004
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002
-#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001
-
-#define HW_CLKCTRL_RESET       (0x000001e0)
-
-#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE      0x00000020
-#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
-#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE  0x00000008
-#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004
-#define BM_CLKCTRL_RESET_CHIP  0x00000002
-#define BM_CLKCTRL_RESET_DIG   0x00000001
-
-#define HW_CLKCTRL_STATUS      (0x000001f0)
-
-#define BP_CLKCTRL_STATUS_CPU_LIMIT    30
-#define BM_CLKCTRL_STATUS_CPU_LIMIT    0xC0000000
-#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
-               (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
-
-#define HW_CLKCTRL_VERSION     (0x00000200)
-
-#define BP_CLKCTRL_VERSION_MAJOR       24
-#define BM_CLKCTRL_VERSION_MAJOR       0xFF000000
-#define BF_CLKCTRL_VERSION_MAJOR(v) \
-               (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
-#define BP_CLKCTRL_VERSION_MINOR       16
-#define BM_CLKCTRL_VERSION_MINOR       0x00FF0000
-#define BF_CLKCTRL_VERSION_MINOR(v)  \
-               (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
-#define BP_CLKCTRL_VERSION_STEP        0
-#define BM_CLKCTRL_VERSION_STEP        0x0000FFFF
-#define BF_CLKCTRL_VERSION_STEP(v)  \
-               (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
-
-#endif /* __REGS_CLKCTRL_MX28_H__ */

diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 80ac1fc..30042e2 100644 (file)
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -37,8 +37,6 @@
 #define MXS_MODULE_CLKGATE             (1 << 30)
 #define MXS_MODULE_SFTRST              (1 << 31)
 
-#define CLKCTRL_TIMEOUT                10      /* 10 ms */
-
 static void __iomem *mxs_clkctrl_reset_addr;
 
 /*
@@ -139,17 +137,3 @@ error:
        return -ETIMEDOUT;
 }
 EXPORT_SYMBOL(mxs_reset_block);
-
-int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask)
-{
-       unsigned long timeout = jiffies + msecs_to_jiffies(CLKCTRL_TIMEOUT);
-       while (readl_relaxed(MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR)
-                                               + reg_offset) & mask) {
-               if (time_after(jiffies, timeout)) {
-                       pr_err("Timeout at CLKCTRL + 0x%x\n", reg_offset);
-                       return -ETIMEDOUT;
-               }
-       }
-
-       return 0;
-}

diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 564a632..02d36de 100644 (file)
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -20,6 +20,7 @@
  * MA 02110-1301, USA.
  */
 
+#include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clockchips.h>
@@ -243,8 +244,16 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
        return 0;
 }
 
-void __init mxs_timer_init(struct clk *timer_clk, int irq)
+void __init mxs_timer_init(int irq)
 {
+       struct clk *timer_clk;
+
+       timer_clk = clk_get_sys("timrot", NULL);
+       if (IS_ERR(timer_clk)) {
+               pr_err("%s: failed to get clk\n", __func__);
+               return;
+       }
+
        clk_prepare_enable(timer_clk);
 
        /*

diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index c54cef2..cbf51ae 100644 (file)
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -17,6 +17,7 @@
  *
  * bit     23 - Input/Output (PXA2xx specific)
  * bit     24 - Wakeup Enable(PXA2xx specific)
+ * bit     25 - Keep Output  (PXA2xx specific)
  */
 
 #define MFP_DIR_IN             (0x0 << 23)
@@ -25,6 +26,12 @@
 #define MFP_DIR(x)             (((x) >> 23) & 0x1)
 
 #define MFP_LPM_CAN_WAKEUP     (0x1 << 24)
+
+/*
+ * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
+ * retain their last output level (low or high).
+ * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
+ */
 #define MFP_LPM_KEEP_OUTPUT    (0x1 << 25)
 
 #define WAKEUP_ON_EDGE_RISE    (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)

diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index b0a8428..ef0426a 100644 (file)
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -33,6 +33,8 @@
 #define BANK_OFF(n)    (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPLR(x)                __REG2(0x40E00000, BANK_OFF((x) >> 5))
 #define GPDR(x)                __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
+#define GPSR(x)                __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
+#define GPCR(x)                __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
 
 #define PWER_WE35      (1 << 24)
 
@@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
 #ifdef CONFIG_PM
 static unsigned long saved_gafr[2][4];
 static unsigned long saved_gpdr[4];
+static unsigned long saved_gplr[4];
 static unsigned long saved_pgsr[4];
 
 static int pxa2xx_mfp_suspend(void)
@@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
        }
 
        for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
-
                saved_gafr[0][i] = GAFR_L(i);
                saved_gafr[1][i] = GAFR_U(i);
                saved_gpdr[i] = GPDR(i * 32);
+               saved_gplr[i] = GPLR(i * 32);
                saved_pgsr[i] = PGSR(i);
 
-               GPDR(i * 32) = gpdr_lpm[i];
+               GPSR(i * 32) = PGSR(i);
+               GPCR(i * 32) = ~PGSR(i);
+       }
+
+       /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
+       for (i = 0; i < pxa_last_gpio; i++) {
+               if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
+                   ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
+                    (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
+                       GPDR(i) |= GPIO_bit(i);
+               else
+                       GPDR(i) &= ~GPIO_bit(i);
        }
+
        return 0;
 }
 
@@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
        for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
                GAFR_L(i) = saved_gafr[0][i];
                GAFR_U(i) = saved_gafr[1][i];
+               GPSR(i * 32) = saved_gplr[i];
+               GPCR(i * 32) = ~saved_gplr[i];
                GPDR(i * 32) = saved_gpdr[i];
                PGSR(i) = saved_pgsr[i];
        }

diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 6bce78e..4726c24 100644 (file)
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
        pxa_register_device(&pxa27x_device_i2c_power, info);
 }
 
+static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
+       .gpio_set_wake = gpio_set_wake,
+};
+
 static struct platform_device *devices[] __initdata = {
-       &pxa_device_gpio,
        &pxa27x_device_udc,
        &pxa_device_pmu,
        &pxa_device_i2s,
@@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
                register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                register_syscore_ops(&pxa2xx_clock_syscore_ops);
 
+               pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
        }
 

diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 0f3a327..b34287a 100644 (file)
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
        help
          Compile in platform device definition for Samsung TouchScreen.
 
-# cpu-specific sections
-
-if CPU_S3C2410
-
 config S3C2410_DMA
        bool
        depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -127,6 +123,10 @@ config S3C2410_PM
        help
          Power Management code common to S3C2410 and better
 
+# cpu-specific sections
+
+if CPU_S3C2410
+
 config S3C24XX_SIMTEC_NOR
        bool
        help

diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index a8933de..3239566 100644 (file)
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -25,6 +25,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/mmc/host.h>
 #include <linux/interrupt.h>
 
 #include <asm/hardware/vic.h>
@@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
 /* MoviNAND */
 static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
        .max_width              = 4,
+       .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
 };
 

diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 7c524b4..16be4c5 100644 (file)
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
 }
 
 static struct resource sa1100_rtc_resources[] = {
-       DEFINE_RES_MEM(0x90010000, 0x9001003f),
+       DEFINE_RES_MEM(0x90010000, 0x40),
        DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
        DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
 };

diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0..8bd3729 100644 (file)
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
 if ARCH_SPEAR3XX
 
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-       bool "SPEAr300 Evaluation Board"
-       select MACH_SPEAR300
-       help
-         Supports ST SPEAr300 Evaluation Board
-
-config BOARD_SPEAR310_EVB
-       bool "SPEAr310 Evaluation Board"
-       select MACH_SPEAR310
-       help
-         Supports ST SPEAr310 Evaluation Board
-
-config BOARD_SPEAR320_EVB
-       bool "SPEAr320 Evaluation Board"
-       select MACH_SPEAR320
-       help
-         Supports ST SPEAr320 Evaluation Board
-
-endmenu
-
 config MACH_SPEAR300
-       bool "SPEAr300"
+       bool "SPEAr300 Machine support with Device Tree"
+       select PINCTRL_SPEAR300
        help
-         Supports ST SPEAr300 Machine
+         Supports ST SPEAr300 machine configured via the device-tree
 
 config MACH_SPEAR310
-       bool "SPEAr310"
+       bool "SPEAr310 Machine support with Device Tree"
+       select PINCTRL_SPEAR310
        help
-         Supports ST SPEAr310 Machine
+         Supports ST SPEAr310 machine configured via the device-tree
 
 config MACH_SPEAR320
-       bool "SPEAr320"
+       bool "SPEAr320 Machine support with Device Tree"
+       select PINCTRL_SPEAR320
        help
-         Supports ST SPEAr320 Machine
-
+         Supports ST SPEAr320 machine configured via the device-tree
+endmenu
 endif #ARCH_SPEAR3XX

diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b248624..8d12faa 100644 (file)
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 
 # common files
-obj-y  += spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX)    += spear3xx.o
 
 # spear300 specific files
 obj-$(CONFIG_MACH_SPEAR300) += spear300.o
 
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
-
-
 # spear310 specific files
 obj-$(CONFIG_MACH_SPEAR310) += spear310.o
 
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
-
-
 # spear320 specific files
 obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o

diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c..d93e217 100644 (file)
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y     += 0x00008000
 params_phys-y  := 0x00000100
 initrd_phys-y  := 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR300)    += spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310)    += spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320)    += spear320-evb.dtb

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644 (file)
index 6c4841f..0000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,760 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/clock.c
- *
- * SPEAr3xx machines clock framework source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <asm/mach-types.h>
-#include <plat/clock.h>
-#include <mach/misc_regs.h>
-
-/* root clks */
-/* 32 KHz oscillator clock */
-static struct clk osc_32k_clk = {
-       .flags = ALWAYS_ENABLED,
-       .rate = 32000,
-};
-
-/* 24 MHz oscillator clock */
-static struct clk osc_24m_clk = {
-       .flags = ALWAYS_ENABLED,
-       .rate = 24000000,
-};
-
-/* clock derived from 32 KHz osc clk */
-/* rtc clock */
-static struct clk rtc_clk = {
-       .pclk = &osc_32k_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = RTC_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from 24 MHz osc clk */
-/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
-       .mode_mask = PLL_MODE_MASK,
-       .mode_shift = PLL_MODE_SHIFT,
-       .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
-       .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
-       .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
-       .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
-       .div_p_mask = PLL_DIV_P_MASK,
-       .div_p_shift = PLL_DIV_P_SHIFT,
-       .div_n_mask = PLL_DIV_N_MASK,
-       .div_n_shift = PLL_DIV_N_SHIFT,
-};
-
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
-       .mode_reg = PLL1_CTR,
-       .cfg_reg = PLL1_FRQ,
-       .masks = &pll1_masks,
-};
-
-/* pll rate configuration table, in ascending order of rates */
-struct pll_rate_tbl pll_rtbl[] = {
-       {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
-       {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
-};
-
-/* PLL1 clock */
-static struct clk pll1_clk = {
-       .flags = ENABLED_ON_INIT,
-       .pclk = &osc_24m_clk,
-       .en_reg = PLL1_CTR,
-       .en_reg_bit = PLL_ENABLE,
-       .calc_rate = &pll_calc_rate,
-       .recalc = &pll_clk_recalc,
-       .set_rate = &pll_clk_set_rate,
-       .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
-       .private_data = &pll1_config,
-};
-
-/* PLL3 48 MHz clock */
-static struct clk pll3_48m_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &osc_24m_clk,
-       .rate = 48000000,
-};
-
-/* watch dog timer clock */
-static struct clk wdt_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &osc_24m_clk,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from pll1 clk */
-/* cpu clock */
-static struct clk cpu_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .recalc = &follow_parent,
-};
-
-/* ahb masks structure */
-static struct bus_clk_masks ahb_masks = {
-       .mask = PLL_HCLK_RATIO_MASK,
-       .shift = PLL_HCLK_RATIO_SHIFT,
-};
-
-/* ahb configuration structure */
-static struct bus_clk_config ahb_config = {
-       .reg = CORE_CLK_CFG,
-       .masks = &ahb_masks,
-};
-
-/* ahb rate configuration table, in ascending order of rates */
-struct bus_rate_tbl bus_rtbl[] = {
-       {.div = 3}, /* == parent divided by 4 */
-       {.div = 2}, /* == parent divided by 3 */
-       {.div = 1}, /* == parent divided by 2 */
-       {.div = 0}, /* == parent divided by 1 */
-};
-
-/* ahb clock */
-static struct clk ahb_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .calc_rate = &bus_calc_rate,
-       .recalc = &bus_clk_recalc,
-       .set_rate = &bus_clk_set_rate,
-       .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-       .private_data = &ahb_config,
-};
-
-/* auxiliary synthesizers masks */
-static struct aux_clk_masks aux_masks = {
-       .eq_sel_mask = AUX_EQ_SEL_MASK,
-       .eq_sel_shift = AUX_EQ_SEL_SHIFT,
-       .eq1_mask = AUX_EQ1_SEL,
-       .eq2_mask = AUX_EQ2_SEL,
-       .xscale_sel_mask = AUX_XSCALE_MASK,
-       .xscale_sel_shift = AUX_XSCALE_SHIFT,
-       .yscale_sel_mask = AUX_YSCALE_MASK,
-       .yscale_sel_shift = AUX_YSCALE_SHIFT,
-};
-
-/* uart synth configurations */
-static struct aux_clk_config uart_synth_config = {
-       .synth_reg = UART_CLK_SYNT,
-       .masks = &aux_masks,
-};
-
-/* aux rate configuration table, in ascending order of rates */
-struct aux_rate_tbl aux_rtbl[] = {
-       /* For PLL1 = 332 MHz */
-       {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
-       {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
-       {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
-};
-
-/* uart synth clock */
-static struct clk uart_synth_clk = {
-       .en_reg = UART_CLK_SYNT,
-       .en_reg_bit = AUX_SYNT_ENB,
-       .pclk = &pll1_clk,
-       .calc_rate = &aux_calc_rate,
-       .recalc = &aux_clk_recalc,
-       .set_rate = &aux_clk_set_rate,
-       .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
-       .private_data = &uart_synth_config,
-};
-
-/* uart parents */
-static struct pclk_info uart_pclk_info[] = {
-       {
-               .pclk = &uart_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* uart parent select structure */
-static struct pclk_sel uart_pclk_sel = {
-       .pclk_info = uart_pclk_info,
-       .pclk_count = ARRAY_SIZE(uart_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = UART_CLK_MASK,
-};
-
-/* uart clock */
-static struct clk uart_clk = {
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = UART_CLK_ENB,
-       .pclk_sel = &uart_pclk_sel,
-       .pclk_sel_shift = UART_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* firda configurations */
-static struct aux_clk_config firda_synth_config = {
-       .synth_reg = FIRDA_CLK_SYNT,
-       .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk firda_synth_clk = {
-       .en_reg = FIRDA_CLK_SYNT,
-       .en_reg_bit = AUX_SYNT_ENB,
-       .pclk = &pll1_clk,
-       .calc_rate = &aux_calc_rate,
-       .recalc = &aux_clk_recalc,
-       .set_rate = &aux_clk_set_rate,
-       .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
-       .private_data = &firda_synth_config,
-};
-
-/* firda parents */
-static struct pclk_info firda_pclk_info[] = {
-       {
-               .pclk = &firda_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* firda parent select structure */
-static struct pclk_sel firda_pclk_sel = {
-       .pclk_info = firda_pclk_info,
-       .pclk_count = ARRAY_SIZE(firda_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = FIRDA_CLK_MASK,
-};
-
-/* firda clock */
-static struct clk firda_clk = {
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = FIRDA_CLK_ENB,
-       .pclk_sel = &firda_pclk_sel,
-       .pclk_sel_shift = FIRDA_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* gpt synthesizer masks */
-static struct gpt_clk_masks gpt_masks = {
-       .mscale_sel_mask = GPT_MSCALE_MASK,
-       .mscale_sel_shift = GPT_MSCALE_SHIFT,
-       .nscale_sel_mask = GPT_NSCALE_MASK,
-       .nscale_sel_shift = GPT_NSCALE_SHIFT,
-};
-
-/* gpt rate configuration table, in ascending order of rates */
-struct gpt_rate_tbl gpt_rtbl[] = {
-       /* For pll1 = 332 MHz */
-       {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
-       {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
-       {.mscale = 1, .nscale = 0}, /* 83 MHz */
-};
-
-/* gpt0 synth clk config*/
-static struct gpt_clk_config gpt0_synth_config = {
-       .synth_reg = PRSC1_CLK_CFG,
-       .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt0_synth_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .calc_rate = &gpt_calc_rate,
-       .recalc = &gpt_clk_recalc,
-       .set_rate = &gpt_clk_set_rate,
-       .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-       .private_data = &gpt0_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt0_pclk_info[] = {
-       {
-               .pclk = &gpt0_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt0_pclk_sel = {
-       .pclk_info = gpt0_pclk_info,
-       .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt0 timer clock */
-static struct clk gpt0_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk_sel = &gpt0_pclk_sel,
-       .pclk_sel_shift = GPT0_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* gpt1 synth clk configurations */
-static struct gpt_clk_config gpt1_synth_config = {
-       .synth_reg = PRSC2_CLK_CFG,
-       .masks = &gpt_masks,
-};
-
-/* gpt1 synth clock */
-static struct clk gpt1_synth_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .calc_rate = &gpt_calc_rate,
-       .recalc = &gpt_clk_recalc,
-       .set_rate = &gpt_clk_set_rate,
-       .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-       .private_data = &gpt1_synth_config,
-};
-
-static struct pclk_info gpt1_pclk_info[] = {
-       {
-               .pclk = &gpt1_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt1_pclk_sel = {
-       .pclk_info = gpt1_pclk_info,
-       .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt1 timer clock */
-static struct clk gpt1_clk = {
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = GPT1_CLK_ENB,
-       .pclk_sel = &gpt1_pclk_sel,
-       .pclk_sel_shift = GPT1_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* gpt2 synth clk configurations */
-static struct gpt_clk_config gpt2_synth_config = {
-       .synth_reg = PRSC3_CLK_CFG,
-       .masks = &gpt_masks,
-};
-
-/* gpt1 synth clock */
-static struct clk gpt2_synth_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .calc_rate = &gpt_calc_rate,
-       .recalc = &gpt_clk_recalc,
-       .set_rate = &gpt_clk_set_rate,
-       .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-       .private_data = &gpt2_synth_config,
-};
-
-static struct pclk_info gpt2_pclk_info[] = {
-       {
-               .pclk = &gpt2_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt2_pclk_sel = {
-       .pclk_info = gpt2_pclk_info,
-       .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt2 timer clock */
-static struct clk gpt2_clk = {
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = GPT2_CLK_ENB,
-       .pclk_sel = &gpt2_pclk_sel,
-       .pclk_sel_shift = GPT2_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from pll3 clk */
-/* usbh clock */
-static struct clk usbh_clk = {
-       .pclk = &pll3_48m_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = USBH_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* usbd clock */
-static struct clk usbd_clk = {
-       .pclk = &pll3_48m_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = USBD_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from ahb clk */
-/* apb masks structure */
-static struct bus_clk_masks apb_masks = {
-       .mask = HCLK_PCLK_RATIO_MASK,
-       .shift = HCLK_PCLK_RATIO_SHIFT,
-};
-
-/* apb configuration structure */
-static struct bus_clk_config apb_config = {
-       .reg = CORE_CLK_CFG,
-       .masks = &apb_masks,
-};
-
-/* apb clock */
-static struct clk apb_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &ahb_clk,
-       .calc_rate = &bus_calc_rate,
-       .recalc = &bus_clk_recalc,
-       .set_rate = &bus_clk_set_rate,
-       .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-       .private_data = &apb_config,
-};
-
-/* i2c clock */
-static struct clk i2c_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = I2C_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* dma clock */
-static struct clk dma_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = DMA_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* jpeg clock */
-static struct clk jpeg_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = JPEG_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* gmac clock */
-static struct clk gmac_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = GMAC_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* smi clock */
-static struct clk smi_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = SMI_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* c3 clock */
-static struct clk c3_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = C3_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from apb clk */
-/* adc clock */
-static struct clk adc_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = ADC_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* emi clock */
-static struct clk emi_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &ahb_clk,
-       .recalc = &follow_parent,
-};
-#endif
-
-/* ssp clock */
-static struct clk ssp0_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = SSP_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* gpio clock */
-static struct clk gpio_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = GPIO_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-static struct clk dummy_apb_pclk;
-
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
-       defined(CONFIG_MACH_SPEAR320)
-/* fsmc clock */
-static struct clk fsmc_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &ahb_clk,
-       .recalc = &follow_parent,
-};
-#endif
-
-/* common clocks to spear310 and spear320 */
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* uart1 clock */
-static struct clk uart1_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* uart2 clock */
-static struct clk uart2_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
-
-/* common clocks to spear300 and spear320 */
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
-/* clcd clock */
-static struct clk clcd_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll3_48m_clk,
-       .recalc = &follow_parent,
-};
-
-/* sdhci clock */
-static struct clk sdhci_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &ahb_clk,
-       .recalc = &follow_parent,
-};
-#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
-
-/* spear300 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR300
-/* gpio1 clock */
-static struct clk gpio1_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* keyboard clock */
-static struct clk kbd_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-#endif
-
-/* spear310 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR310
-/* uart3 clock */
-static struct clk uart3_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* uart4 clock */
-static struct clk uart4_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* uart5 clock */
-static struct clk uart5_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-#endif
-
-/* spear320 machine specific clock structures */
-#ifdef CONFIG_MACH_SPEAR320
-/* can0 clock */
-static struct clk can0_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* can1 clock */
-static struct clk can1_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* i2c1 clock */
-static struct clk i2c1_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &ahb_clk,
-       .recalc = &follow_parent,
-};
-
-/* ssp1 clock */
-static struct clk ssp1_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* ssp2 clock */
-static struct clk ssp2_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* pwm clock */
-static struct clk pwm_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-#endif
-
-/* array of all spear 3xx clock lookups */
-static struct clk_lookup spear_clk_lookups[] = {
-       { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
-       /* root clks */
-       { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-       { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
-       /* clock derived from 32 KHz osc clk */
-       { .dev_id = "rtc-spear",        .clk = &rtc_clk},
-       /* clock derived from 24 MHz osc clk */
-       { .con_id = "pll1_clk",         .clk = &pll1_clk},
-       { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-       { .dev_id = "wdt",              .clk = &wdt_clk},
-       /* clock derived from pll1 clk */
-       { .con_id = "cpu_clk",          .clk = &cpu_clk},
-       { .con_id = "ahb_clk",          .clk = &ahb_clk},
-       { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-       { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-       { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-       { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
-       { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-       { .dev_id = "uart",             .clk = &uart_clk},
-       { .dev_id = "firda",            .clk = &firda_clk},
-       { .dev_id = "gpt0",             .clk = &gpt0_clk},
-       { .dev_id = "gpt1",             .clk = &gpt1_clk},
-       { .dev_id = "gpt2",             .clk = &gpt2_clk},
-       /* clock derived from pll3 clk */
-       { .dev_id = "designware_udc",   .clk = &usbd_clk},
-       { .con_id = "usbh_clk",         .clk = &usbh_clk},
-       /* clock derived from ahb clk */
-       { .con_id = "apb_clk",          .clk = &apb_clk},
-       { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
-       { .dev_id = "dma",              .clk = &dma_clk},
-       { .dev_id = "jpeg",             .clk = &jpeg_clk},
-       { .dev_id = "gmac",             .clk = &gmac_clk},
-       { .dev_id = "smi",              .clk = &smi_clk},
-       { .dev_id = "c3",               .clk = &c3_clk},
-       /* clock derived from apb clk */
-       { .dev_id = "adc",              .clk = &adc_clk},
-       { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-       { .dev_id = "gpio",             .clk = &gpio_clk},
-};
-
-/* array of all spear 300 clock lookups */
-#ifdef CONFIG_MACH_SPEAR300
-static struct clk_lookup spear300_clk_lookups[] = {
-       { .dev_id = "clcd",             .clk = &clcd_clk},
-       { .con_id = "fsmc",             .clk = &fsmc_clk},
-       { .dev_id = "gpio1",            .clk = &gpio1_clk},
-       { .dev_id = "keyboard",         .clk = &kbd_clk},
-       { .dev_id = "sdhci",            .clk = &sdhci_clk},
-};
-#endif
-
-/* array of all spear 310 clock lookups */
-#ifdef CONFIG_MACH_SPEAR310
-static struct clk_lookup spear310_clk_lookups[] = {
-       { .con_id = "fsmc",             .clk = &fsmc_clk},
-       { .con_id = "emi",              .clk = &emi_clk},
-       { .dev_id = "uart1",            .clk = &uart1_clk},
-       { .dev_id = "uart2",            .clk = &uart2_clk},
-       { .dev_id = "uart3",            .clk = &uart3_clk},
-       { .dev_id = "uart4",            .clk = &uart4_clk},
-       { .dev_id = "uart5",            .clk = &uart5_clk},
-};
-#endif
-
-/* array of all spear 320 clock lookups */
-#ifdef CONFIG_MACH_SPEAR320
-static struct clk_lookup spear320_clk_lookups[] = {
-       { .dev_id = "clcd",             .clk = &clcd_clk},
-       { .con_id = "fsmc",             .clk = &fsmc_clk},
-       { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
-       { .con_id = "emi",              .clk = &emi_clk},
-       { .dev_id = "pwm",              .clk = &pwm_clk},
-       { .dev_id = "sdhci",            .clk = &sdhci_clk},
-       { .dev_id = "c_can_platform.0", .clk = &can0_clk},
-       { .dev_id = "c_can_platform.1", .clk = &can1_clk},
-       { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-       { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-       { .dev_id = "uart1",            .clk = &uart1_clk},
-       { .dev_id = "uart2",            .clk = &uart2_clk},
-};
-#endif
-
-void __init spear3xx_clk_init(void)
-{
-       int i, cnt;
-       struct clk_lookup *lookups;
-
-       if (machine_is_spear300()) {
-               cnt = ARRAY_SIZE(spear300_clk_lookups);
-               lookups = spear300_clk_lookups;
-       } else if (machine_is_spear310()) {
-               cnt = ARRAY_SIZE(spear310_clk_lookups);
-               lookups = spear310_clk_lookups;
-       } else {
-               cnt = ARRAY_SIZE(spear320_clk_lookups);
-               lookups = spear320_clk_lookups;
-       }
-
-       for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
-               clk_register(&spear_clk_lookups[i]);
-
-       for (i = 0; i < cnt; i++)
-               clk_register(&lookups[i]);
-
-       clk_init();
-}

diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5..4a95b94 100644 (file)
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,189 +14,24 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <plat/padmux.h>
-
-/* spear3xx declarations */
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE                SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ   SPEAR3XX_IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ   SPEAR3XX_IRQ_CPU_GPT1_2
 
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 
 /* Add spear3xx family function declarations here */
+void __init spear_setup_of_timer(void);
 void __init spear3xx_clk_init(void);
-void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
-void __init spear3xx_init(void);
+void __init spear3xx_dt_init_irq(void);
 
 void spear_restart(char, const char *);
 
-/* pad mux declarations */
-#define PMX_FIRDA_MASK         (1 << 14)
-#define PMX_I2C_MASK           (1 << 13)
-#define PMX_SSP_CS_MASK                (1 << 12)
-#define PMX_SSP_MASK           (1 << 11)
-#define PMX_MII_MASK           (1 << 10)
-#define PMX_GPIO_PIN0_MASK     (1 << 9)
-#define PMX_GPIO_PIN1_MASK     (1 << 8)
-#define PMX_GPIO_PIN2_MASK     (1 << 7)
-#define PMX_GPIO_PIN3_MASK     (1 << 6)
-#define PMX_GPIO_PIN4_MASK     (1 << 5)
-#define PMX_GPIO_PIN5_MASK     (1 << 4)
-#define PMX_UART0_MODEM_MASK   (1 << 3)
-#define PMX_UART0_MASK         (1 << 2)
-#define PMX_TIMER_3_4_MASK     (1 << 1)
-#define PMX_TIMER_1_2_MASK     (1 << 0)
-
-/* pad mux devices */
-extern struct pmx_dev spear3xx_pmx_firda;
-extern struct pmx_dev spear3xx_pmx_i2c;
-extern struct pmx_dev spear3xx_pmx_ssp_cs;
-extern struct pmx_dev spear3xx_pmx_ssp;
-extern struct pmx_dev spear3xx_pmx_mii;
-extern struct pmx_dev spear3xx_pmx_gpio_pin0;
-extern struct pmx_dev spear3xx_pmx_gpio_pin1;
-extern struct pmx_dev spear3xx_pmx_gpio_pin2;
-extern struct pmx_dev spear3xx_pmx_gpio_pin3;
-extern struct pmx_dev spear3xx_pmx_gpio_pin4;
-extern struct pmx_dev spear3xx_pmx_gpio_pin5;
-extern struct pmx_dev spear3xx_pmx_uart0_modem;
-extern struct pmx_dev spear3xx_pmx_uart0;
-extern struct pmx_dev spear3xx_pmx_timer_3_4;
-extern struct pmx_dev spear3xx_pmx_timer_1_2;
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* padmux plgpio devices */
-extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
-extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
-extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
-extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
-extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
-extern struct pmx_dev spear3xx_pmx_plgpio_28;
-extern struct pmx_dev spear3xx_pmx_plgpio_29;
-extern struct pmx_dev spear3xx_pmx_plgpio_30;
-extern struct pmx_dev spear3xx_pmx_plgpio_31;
-extern struct pmx_dev spear3xx_pmx_plgpio_32;
-extern struct pmx_dev spear3xx_pmx_plgpio_33;
-extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
-extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
-extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
-extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
-#endif
-
-/* spear300 declarations */
-#ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
-extern struct amba_device spear300_gpio1_device;
-
-/* pad mux modes */
-extern struct pmx_mode spear300_nand_mode;
-extern struct pmx_mode spear300_nor_mode;
-extern struct pmx_mode spear300_photo_frame_mode;
-extern struct pmx_mode spear300_lend_ip_phone_mode;
-extern struct pmx_mode spear300_hend_ip_phone_mode;
-extern struct pmx_mode spear300_lend_wifi_phone_mode;
-extern struct pmx_mode spear300_hend_wifi_phone_mode;
-extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
-extern struct pmx_mode spear300_ata_pabx_i2s_mode;
-extern struct pmx_mode spear300_caml_lcdw_mode;
-extern struct pmx_mode spear300_camu_lcd_mode;
-extern struct pmx_mode spear300_camu_wlcd_mode;
-extern struct pmx_mode spear300_caml_lcd_mode;
-
-/* pad mux devices */
-extern struct pmx_dev spear300_pmx_fsmc_2_chips;
-extern struct pmx_dev spear300_pmx_fsmc_4_chips;
-extern struct pmx_dev spear300_pmx_keyboard;
-extern struct pmx_dev spear300_pmx_clcd;
-extern struct pmx_dev spear300_pmx_telecom_gpio;
-extern struct pmx_dev spear300_pmx_telecom_tdm;
-extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev spear300_pmx_telecom_camera;
-extern struct pmx_dev spear300_pmx_telecom_dac;
-extern struct pmx_dev spear300_pmx_telecom_i2s;
-extern struct pmx_dev spear300_pmx_telecom_boot_pins;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
-extern struct pmx_dev spear300_pmx_gpio1;
-
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-               u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR300 */
-
-/* spear310 declarations */
-#ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
-
-/* pad mux devices */
-extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev spear310_pmx_emi_cs_2_3;
-extern struct pmx_dev spear310_pmx_uart1;
-extern struct pmx_dev spear310_pmx_uart2;
-extern struct pmx_dev spear310_pmx_uart3_4_5;
-extern struct pmx_dev spear310_pmx_fsmc;
-extern struct pmx_dev spear310_pmx_rs485_0_1;
-extern struct pmx_dev spear310_pmx_tdm0;
-
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-               u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR310 */
-
-/* spear320 declarations */
-#ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
-
-/* pad mux modes */
-extern struct pmx_mode spear320_auto_net_smii_mode;
-extern struct pmx_mode spear320_auto_net_mii_mode;
-extern struct pmx_mode spear320_auto_exp_mode;
-extern struct pmx_mode spear320_small_printers_mode;
-
-/* pad mux devices */
-extern struct pmx_dev spear320_pmx_clcd;
-extern struct pmx_dev spear320_pmx_emi;
-extern struct pmx_dev spear320_pmx_fsmc;
-extern struct pmx_dev spear320_pmx_spp;
-extern struct pmx_dev spear320_pmx_sdhci;
-extern struct pmx_dev spear320_pmx_i2s;
-extern struct pmx_dev spear320_pmx_uart1;
-extern struct pmx_dev spear320_pmx_uart1_modem;
-extern struct pmx_dev spear320_pmx_uart2;
-extern struct pmx_dev spear320_pmx_touchscreen;
-extern struct pmx_dev spear320_pmx_can;
-extern struct pmx_dev spear320_pmx_sdhci_led;
-extern struct pmx_dev spear320_pmx_pwm0;
-extern struct pmx_dev spear320_pmx_pwm1;
-extern struct pmx_dev spear320_pmx_pwm2;
-extern struct pmx_dev spear320_pmx_pwm3;
-extern struct pmx_dev spear320_pmx_ssp1;
-extern struct pmx_dev spear320_pmx_ssp2;
-extern struct pmx_dev spear320_pmx_mii1;
-extern struct pmx_dev spear320_pmx_smii0;
-extern struct pmx_dev spear320_pmx_smii1;
-extern struct pmx_dev spear320_pmx_i2c1;
-
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-               u8 pmx_dev_count);
-
-#endif /* CONFIG_MACH_SPEAR320 */
-
 #endif /* __MACH_GENERIC_H */

diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d..40a8c17 100644 (file)
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)          (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */

diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e26544..51bd62a 100644 (file)
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,14 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-/* SPEAr3xx IRQ definitions */
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0            0
+/* FIXME: probe all these from DT */
 #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM          1
-#define SPEAR3XX_IRQ_CPU_GPT1_1                        2
-#define SPEAR3XX_IRQ_CPU_GPT1_2                        3
-#define SPEAR3XX_IRQ_BASIC_GPT1_1              4
-#define SPEAR3XX_IRQ_BASIC_GPT1_2              5
-#define SPEAR3XX_IRQ_BASIC_GPT2_1              6
-#define SPEAR3XX_IRQ_BASIC_GPT2_2              7
-#define SPEAR3XX_IRQ_BASIC_DMA                 8
-#define SPEAR3XX_IRQ_BASIC_SMI                 9
-#define SPEAR3XX_IRQ_BASIC_RTC                 10
-#define SPEAR3XX_IRQ_BASIC_GPIO                        11
-#define SPEAR3XX_IRQ_BASIC_WDT                 12
-#define SPEAR3XX_IRQ_DDR_CONTROLLER            13
-#define SPEAR3XX_IRQ_SYS_ERROR                 14
-#define SPEAR3XX_IRQ_WAKEUP_RCV                        15
-#define SPEAR3XX_IRQ_JPEG                      16
-#define SPEAR3XX_IRQ_IRDA                      17
-#define SPEAR3XX_IRQ_ADC                       18
-#define SPEAR3XX_IRQ_UART                      19
-#define SPEAR3XX_IRQ_SSP                       20
-#define SPEAR3XX_IRQ_I2C                       21
-#define SPEAR3XX_IRQ_MAC_1                     22
-#define SPEAR3XX_IRQ_MAC_2                     23
-#define SPEAR3XX_IRQ_USB_DEV                   24
-#define SPEAR3XX_IRQ_USB_H_OHCI_0              25
-#define SPEAR3XX_IRQ_USB_H_EHCI_0              26
-#define SPEAR3XX_IRQ_USB_H_EHCI_1              SPEAR3XX_IRQ_USB_H_EHCI_0
-#define SPEAR3XX_IRQ_USB_H_OHCI_1              27
 #define SPEAR3XX_IRQ_GEN_RAS_1                 28
 #define SPEAR3XX_IRQ_GEN_RAS_2                 29
 #define SPEAR3XX_IRQ_GEN_RAS_3                 30
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1            31
 #define SPEAR3XX_IRQ_VIC_END                   32
-
 #define SPEAR3XX_VIRQ_START                    SPEAR3XX_IRQ_VIC_END
 
-/* SPEAr300 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S                        (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S              (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S                      (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM                      (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L                 (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F                 (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V                 (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD                 (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1                    (SPEAR3XX_VIRQ_START + 8)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD                      SPEAR3XX_IRQ_GEN_RAS_3
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI                     SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0                    (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1                    (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2                    (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3                    (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0             (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1             (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2             (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3             (SPEAR3XX_VIRQ_START + 7)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1                    (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2                    (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3                    (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4                    (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5                    (SPEAR3XX_VIRQ_START + 12)
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI                      (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO                   (SPEAR3XX_VIRQ_START + 14)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC                 (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0                  (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1                  (SPEAR3XX_VIRQ_START + 17)
-
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI                      (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD                     (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP                      (SPEAR3XX_VIRQ_START + 2)
-
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI                     SPEAR3XX_IRQ_GEN_RAS_2
-
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO                   (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY                 (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC                  (SPEAR3XX_VIRQ_START + 5)
-
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU                     (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL                     (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1                    (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2                    (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1                     (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2                     (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0                    (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1               (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0             (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1                (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1                     (SPEAR3XX_VIRQ_START + 16)
-
-/*
- * GPIO pins virtual irqs
- * Use the lowest number for the GPIO virtual IRQs base on which subarchs
- * we have compiled in
- */
-#if defined(CONFIG_MACH_SPEAR310)
-#define SPEAR3XX_GPIO_INT_BASE                 (SPEAR3XX_VIRQ_START + 18)
-#elif defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_GPIO_INT_BASE                 (SPEAR3XX_VIRQ_START + 17)
-#else
-#define SPEAR3XX_GPIO_INT_BASE                 (SPEAR3XX_VIRQ_START + 9)
-#endif
-
-#define SPEAR300_GPIO1_INT_BASE                        (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_PLGPIO_COUNT  102
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_PLGPIO_INT_BASE               (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_GPIO_INT_END                  (SPEAR3XX_PLGPIO_INT_BASE + \
-                                                       SPEAR3XX_PLGPIO_COUNT)
-#else
-#define SPEAR3XX_GPIO_INT_END  (SPEAR300_GPIO1_INT_BASE + 8)
-#endif
-
-#define SPEAR3XX_VIRQ_END      SPEAR3XX_GPIO_INT_END
-#define NR_IRQS                        SPEAR3XX_VIRQ_END
+#define NR_IRQS                        160
 
 #endif /* __MACH_IRQS_H */

diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8..18e2ac5 100644 (file)
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,9 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #define MISC_BASE              IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR            (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR           (MISC_BASE + 0x004)
-#define PLL1_CTR               (MISC_BASE + 0x008)
-#define PLL1_FRQ               (MISC_BASE + 0x00C)
-#define PLL1_MOD               (MISC_BASE + 0x010)
-#define PLL2_CTR               (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE             2
-#define PLL_MODE_SHIFT         4
-#define PLL_MODE_MASK          0x3
-#define PLL_MODE_NORMAL                0
-#define PLL_MODE_FRACTION      1
-#define PLL_MODE_DITH_DSB      2
-#define PLL_MODE_DITH_SSB      3
-
-#define PLL2_FRQ               (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT                0
-#define PLL_DIV_N_MASK         0xFF
-#define PLL_DIV_P_SHIFT                8
-#define PLL_DIV_P_MASK         0x7
-#define PLL_NORM_FDBK_M_SHIFT  24
-#define PLL_NORM_FDBK_M_MASK   0xFF
-#define PLL_DITH_FDBK_M_SHIFT  16
-#define PLL_DITH_FDBK_M_MASK   0xFFFF
-
-#define PLL2_MOD               (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG            (MISC_BASE + 0x020)
-#define CORE_CLK_CFG           (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT   10
-#define PLL_HCLK_RATIO_MASK    0x3
-#define HCLK_PCLK_RATIO_SHIFT  8
-#define HCLK_PCLK_RATIO_MASK   0x3
-
-#define PERIP_CLK_CFG          (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define UART_CLK_SHIFT         4
-#define UART_CLK_MASK          0x1
-#define FIRDA_CLK_SHIFT                5
-#define FIRDA_CLK_MASK         0x3
-#define GPT0_CLK_SHIFT         8
-#define GPT1_CLK_SHIFT         11
-#define GPT2_CLK_SHIFT         12
-#define GPT_CLK_MASK           0x1
-#define AUX_CLK_PLL3_VAL       0
-#define AUX_CLK_PLL1_VAL       1
-
-#define PERIP1_CLK_ENB         (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART_CLK_ENB           3
-#define SSP_CLK_ENB            5
-#define I2C_CLK_ENB            7
-#define JPEG_CLK_ENB           8
-#define FIRDA_CLK_ENB          10
-#define GPT1_CLK_ENB           11
-#define GPT2_CLK_ENB           12
-#define ADC_CLK_ENB            15
-#define RTC_CLK_ENB            17
-#define GPIO_CLK_ENB           18
-#define DMA_CLK_ENB            19
-#define SMI_CLK_ENB            21
-#define GMAC_CLK_ENB           23
-#define USBD_CLK_ENB           24
-#define USBH_CLK_ENB           25
-#define C3_CLK_ENB             31
-
-#define SOC_CORE_ID            (MISC_BASE + 0x030)
-#define RAS_CLK_ENB            (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST         (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST           8
-
-#define SOC_USER_ID            (MISC_BASE + 0x03C)
-#define RAS_SOF_RST            (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG          (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG          (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG          (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT       0
-#define GPT_MSCALE_MASK                0xFFF
-#define GPT_NSCALE_SHIFT       12
-#define GPT_NSCALE_MASK                0xF
-
-#define AMEM_CLK_CFG           (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG           (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT          (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT         (MISC_BASE + 0x060)
-#define UART_CLK_SYNT          (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT          (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT          (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT          (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT          (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT          (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB           31
-#define AUX_EQ_SEL_SHIFT       30
-#define AUX_EQ_SEL_MASK                1
-#define AUX_EQ1_SEL            0
-#define AUX_EQ2_SEL            1
-#define AUX_XSCALE_SHIFT       16
-#define AUX_XSCALE_MASK                0xFFF
-#define AUX_YSCALE_SHIFT       0
-#define AUX_YSCALE_MASK                0xFFF
-
-#define ICM1_ARB_CFG           (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG           (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG           (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG           (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG           (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG           (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG           (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG           (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG           (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG            (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG           (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR           (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR           (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR          (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR          (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR          (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR          (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR           (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR           (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR           (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR           (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR                (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG       (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG       (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG                (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR                (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR          (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR          (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR          (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR          (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR          (MISC_BASE + 0x104)
-#define BIST1_STS_RES          (MISC_BASE + 0x108)
-#define BIST2_STS_RES          (MISC_BASE + 0x10C)
-#define BIST3_STS_RES          (MISC_BASE + 0x110)
-#define BIST4_STS_RES          (MISC_BASE + 0x114)
-#define BIST5_STS_RES          (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR         (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */

diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd983..51eb953 100644 (file)
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,60 +15,26 @@
 #define __MACH_SPEAR3XX_H
 
 #include <asm/memory.h>
-#include <mach/spear300.h>
-#include <mach/spear310.h>
-#include <mach/spear320.h>
-
-#define SPEAR3XX_ML_SDRAM_BASE         UL(0x00000000)
-
-#define SPEAR3XX_ICM9_BASE             UL(0xC0000000)
 
 /* ICM1 - Low speed connection */
 #define SPEAR3XX_ICM1_2_BASE           UL(0xD0000000)
+#define VA_SPEAR3XX_ICM1_2_BASE                UL(0xFD000000)
 #define SPEAR3XX_ICM1_UART_BASE                UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE     IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_ADC_BASE         UL(0xD0080000)
+#define VA_SPEAR3XX_ICM1_UART_BASE     (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
 #define SPEAR3XX_ICM1_SSP_BASE         UL(0xD0100000)
-#define SPEAR3XX_ICM1_I2C_BASE         UL(0xD0180000)
-#define SPEAR3XX_ICM1_JPEG_BASE                UL(0xD0800000)
-#define SPEAR3XX_ICM1_IRDA_BASE                UL(0xD1000000)
-#define SPEAR3XX_ICM1_SRAM_BASE                UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE    UL(0xD8800000)
-#define SPEAR3XX_ICM2_HWACCEL1_BASE    UL(0xD9000000)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE             UL(0xE0000000)
-#define SPEAR3XX_ICM4_MII_BASE         UL(0xE0800000)
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE   UL(0xE1000000)
-#define SPEAR3XX_ICM4_USBD_CSR_BASE    UL(0xE1100000)
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE   UL(0xE1200000)
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE   UL(0xE1900000)
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE   UL(0xE2100000)
-#define SPEAR3XX_ICM4_USB_ARB_BASE     UL(0xE2800000)
 
 /* ML1 - Multi Layer CPU Subsystem */
 #define SPEAR3XX_ICM3_ML1_2_BASE       UL(0xF0000000)
-#define SPEAR3XX_ML1_TMR_BASE          UL(0xF0000000)
-#define SPEAR3XX_ML1_VIC_BASE          UL(0xF1100000)
-#define VA_SPEAR3XX_ML1_VIC_BASE       IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE                UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE                UL(0xF8000000)
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE    UL(0xFC000000)
+#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
 #define SPEAR3XX_ICM3_DMA_BASE         UL(0xFC400000)
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE  UL(0xFC600000)
-#define SPEAR3XX_ICM3_TMR0_BASE                UL(0xFC800000)
-#define SPEAR3XX_ICM3_WDT_BASE         UL(0xFC880000)
-#define SPEAR3XX_ICM3_RTC_BASE         UL(0xFC900000)
-#define SPEAR3XX_ICM3_GPIO_BASE                UL(0xFC980000)
 #define SPEAR3XX_ICM3_SYS_CTRL_BASE    UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR3XX_ICM3_MISC_REG_BASE    UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_TMR1_BASE                UL(0xFCB00000)
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE            SPEAR3XX_ICM1_UART_BASE
@@ -78,4 +44,17 @@
 #define SPEAR_SYS_CTRL_BASE            SPEAR3XX_ICM3_SYS_CTRL_BASE
 #define VA_SPEAR_SYS_CTRL_BASE         VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
 
+/* SPEAr320 Macros */
+#define SPEAR320_SOC_CONFIG_BASE       UL(0xB3000000)
+#define VA_SPEAR320_SOC_CONFIG_BASE    UL(0xFE000000)
+#define SPEAR320_CONTROL_REG           IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
+#define SPEAR320_EXT_CTRL_REG          IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
+       #define SPEAR320_UARTX_PCLK_MASK                0x1
+       #define SPEAR320_UART2_PCLK_SHIFT               8
+       #define SPEAR320_UART3_PCLK_SHIFT               9
+       #define SPEAR320_UART4_PCLK_SHIFT               10
+       #define SPEAR320_UART5_PCLK_SHIFT               11
+       #define SPEAR320_UART6_PCLK_SHIFT               12
+       #define SPEAR320_RS485_PCLK_SHIFT               13
+
 #endif /* __MACH_SPEAR3XX_H */

diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644 (file)
index 3b6ea07..0000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear300.h
- *
- * SPEAr300 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef CONFIG_MACH_SPEAR300
-
-#ifndef __MACH_SPEAR300_H
-#define __MACH_SPEAR300_H
-
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE          UL(0x50000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG      0x54
-#define SPEAR300_INT_STS_MASK_REG      0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK    (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK  (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK          (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK          (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK     (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK     (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK     (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK     (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK                (1 << 8)
-
-#define SPEAR300_SHIRQ_RAS1_MASK       0x1FF
-
-#define SPEAR300_CLCD_BASE             UL(0x60000000)
-#define SPEAR300_SDHCI_BASE            UL(0x70000000)
-#define SPEAR300_NAND_0_BASE           UL(0x80000000)
-#define SPEAR300_NAND_1_BASE           UL(0x84000000)
-#define SPEAR300_NAND_2_BASE           UL(0x88000000)
-#define SPEAR300_NAND_3_BASE           UL(0x8c000000)
-#define SPEAR300_NOR_0_BASE            UL(0x90000000)
-#define SPEAR300_NOR_1_BASE            UL(0x91000000)
-#define SPEAR300_NOR_2_BASE            UL(0x92000000)
-#define SPEAR300_NOR_3_BASE            UL(0x93000000)
-#define SPEAR300_FSMC_BASE             UL(0x94000000)
-#define SPEAR300_SOC_CONFIG_BASE       UL(0x99000000)
-#define SPEAR300_KEYBOARD_BASE         UL(0xA0000000)
-#define SPEAR300_GPIO_BASE             UL(0xA9000000)
-
-#endif /* __MACH_SPEAR300_H */
-
-#endif /* CONFIG_MACH_SPEAR300 */

diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644 (file)
index 1567d0d..0000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear310.h
- *
- * SPEAr310 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef CONFIG_MACH_SPEAR310
-
-#ifndef __MACH_SPEAR310_H
-#define __MACH_SPEAR310_H
-
-#define SPEAR310_NAND_BASE             UL(0x40000000)
-#define SPEAR310_FSMC_BASE             UL(0x44000000)
-#define SPEAR310_UART1_BASE            UL(0xB2000000)
-#define SPEAR310_UART2_BASE            UL(0xB2080000)
-#define SPEAR310_UART3_BASE            UL(0xB2100000)
-#define SPEAR310_UART4_BASE            UL(0xB2180000)
-#define SPEAR310_UART5_BASE            UL(0xB2200000)
-#define SPEAR310_HDLC_BASE             UL(0xB2800000)
-#define SPEAR310_RS485_0_BASE          UL(0xB3000000)
-#define SPEAR310_RS485_1_BASE          UL(0xB3800000)
-#define SPEAR310_SOC_CONFIG_BASE       UL(0xB4000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG      0x04
-#define SPEAR310_SMII0_IRQ_MASK                (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK                (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK                (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK                (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK                (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK                (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK                (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK                (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK                (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK          (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK     (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK      (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK      (1 << 16)
-
-#define SPEAR310_SHIRQ_RAS1_MASK       0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK       0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK       0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK       0x1C000
-
-#endif /* __MACH_SPEAR310_H */
-
-#endif /* CONFIG_MACH_SPEAR310 */

diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644 (file)
index 8cfa83f..0000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear320.h
- *
- * SPEAr320 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef CONFIG_MACH_SPEAR320
-
-#ifndef __MACH_SPEAR320_H
-#define __MACH_SPEAR320_H
-
-#define SPEAR320_EMI_CTRL_BASE         UL(0x40000000)
-#define SPEAR320_FSMC_BASE             UL(0x4C000000)
-#define SPEAR320_NAND_BASE             UL(0x50000000)
-#define SPEAR320_I2S_BASE              UL(0x60000000)
-#define SPEAR320_SDHCI_BASE            UL(0x70000000)
-#define SPEAR320_CLCD_BASE             UL(0x90000000)
-#define SPEAR320_PAR_PORT_BASE         UL(0xA0000000)
-#define SPEAR320_CAN0_BASE             UL(0xA1000000)
-#define SPEAR320_CAN1_BASE             UL(0xA2000000)
-#define SPEAR320_UART1_BASE            UL(0xA3000000)
-#define SPEAR320_UART2_BASE            UL(0xA4000000)
-#define SPEAR320_SSP0_BASE             UL(0xA5000000)
-#define SPEAR320_SSP1_BASE             UL(0xA6000000)
-#define SPEAR320_I2C_BASE              UL(0xA7000000)
-#define SPEAR320_PWM_BASE              UL(0xA8000000)
-#define SPEAR320_SMII0_BASE            UL(0xAA000000)
-#define SPEAR320_SMII1_BASE            UL(0xAB000000)
-#define SPEAR320_SOC_CONFIG_BASE       UL(0xB3000000)
-
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG              0x04
-#define SPEAR320_INT_CLR_MASK_REG              0x04
-#define SPEAR320_INT_ENB_MASK_REG              0x08
-#define SPEAR320_GPIO_IRQ_MASK                 (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK             (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK              (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK                  (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK                 (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK                  (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK                        (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK                        (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK                        (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK                        (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK                        (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK                 (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK                 (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK                        (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK           (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK         (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK    (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK                 (1 << 21)
-
-#define SPEAR320_SHIRQ_RAS1_MASK               0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK               0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK       0x3FF800
-
-#endif /* __MACH_SPEAR320_H */
-
-#endif /* CONFIG_MACH_SPEAR320 */

diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db668..f74a05b 100644 (file)
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,372 +3,62 @@
  *
  * SPEAr300 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr300: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG     0x00
-#define MODE_CONFIG_REG                0x04
-
-/* modes */
-#define NAND_MODE                      (1 << 0)
-#define NOR_MODE                       (1 << 1)
-#define PHOTO_FRAME_MODE               (1 << 2)
-#define LEND_IP_PHONE_MODE             (1 << 3)
-#define HEND_IP_PHONE_MODE             (1 << 4)
-#define LEND_WIFI_PHONE_MODE           (1 << 5)
-#define HEND_WIFI_PHONE_MODE           (1 << 6)
-#define ATA_PABX_WI2S_MODE             (1 << 7)
-#define ATA_PABX_I2S_MODE              (1 << 8)
-#define CAML_LCDW_MODE                 (1 << 9)
-#define CAMU_LCD_MODE                  (1 << 10)
-#define CAMU_WLCD_MODE                 (1 << 11)
-#define CAML_LCD_MODE                  (1 << 12)
-#define ALL_MODES                      0x1FFF
-
-struct pmx_mode spear300_nand_mode = {
-       .id = NAND_MODE,
-       .name = "nand mode",
-       .mask = 0x00,
-};
-
-struct pmx_mode spear300_nor_mode = {
-       .id = NOR_MODE,
-       .name = "nor mode",
-       .mask = 0x01,
-};
-
-struct pmx_mode spear300_photo_frame_mode = {
-       .id = PHOTO_FRAME_MODE,
-       .name = "photo frame mode",
-       .mask = 0x02,
-};
-
-struct pmx_mode spear300_lend_ip_phone_mode = {
-       .id = LEND_IP_PHONE_MODE,
-       .name = "lend ip phone mode",
-       .mask = 0x03,
-};
-
-struct pmx_mode spear300_hend_ip_phone_mode = {
-       .id = HEND_IP_PHONE_MODE,
-       .name = "hend ip phone mode",
-       .mask = 0x04,
-};
-
-struct pmx_mode spear300_lend_wifi_phone_mode = {
-       .id = LEND_WIFI_PHONE_MODE,
-       .name = "lend wifi phone mode",
-       .mask = 0x05,
-};
-
-struct pmx_mode spear300_hend_wifi_phone_mode = {
-       .id = HEND_WIFI_PHONE_MODE,
-       .name = "hend wifi phone mode",
-       .mask = 0x06,
-};
-
-struct pmx_mode spear300_ata_pabx_wi2s_mode = {
-       .id = ATA_PABX_WI2S_MODE,
-       .name = "ata pabx wi2s mode",
-       .mask = 0x07,
-};
-
-struct pmx_mode spear300_ata_pabx_i2s_mode = {
-       .id = ATA_PABX_I2S_MODE,
-       .name = "ata pabx i2s mode",
-       .mask = 0x08,
-};
-
-struct pmx_mode spear300_caml_lcdw_mode = {
-       .id = CAML_LCDW_MODE,
-       .name = "caml lcdw mode",
-       .mask = 0x0C,
-};
-
-struct pmx_mode spear300_camu_lcd_mode = {
-       .id = CAMU_LCD_MODE,
-       .name = "camu lcd mode",
-       .mask = 0x0D,
-};
-
-struct pmx_mode spear300_camu_wlcd_mode = {
-       .id = CAMU_WLCD_MODE,
-       .name = "camu wlcd mode",
-       .mask = 0x0E,
-};
-
-struct pmx_mode spear300_caml_lcd_mode = {
-       .id = CAML_LCD_MODE,
-       .name = "caml lcd mode",
-       .mask = 0x0F,
-};
-
-/* devices */
-static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
-       {
-               .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                       ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-               .mask = PMX_FIRDA_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_fsmc_2_chips = {
-       .name = "fsmc_2_chips",
-       .modes = pmx_fsmc_2_chips_modes,
-       .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
-       {
-               .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                       ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-               .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_fsmc_4_chips = {
-       .name = "fsmc_4_chips",
-       .modes = pmx_fsmc_4_chips_modes,
-       .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_keyboard_modes[] = {
-       {
-               .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                       LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                       CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
-                       CAML_LCD_MODE,
-               .mask = 0x0,
-       },
-};
-
-struct pmx_dev spear300_pmx_keyboard = {
-       .name = "keyboard",
-       .modes = pmx_keyboard_modes,
-       .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-       {
-               .ids = PHOTO_FRAME_MODE,
-               .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
-       }, {
-               .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                       CAMU_LCD_MODE | CAML_LCD_MODE,
-               .mask = PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_clcd = {
-       .name = "clcd",
-       .modes = pmx_clcd_modes,
-       .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
-       {
-               .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
-               .mask = PMX_MII_MASK,
-       }, {
-               .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
-               .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-       }, {
-               .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
-               .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
-       }, {
-               .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
-               .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
-       }, {
-               .ids = ATA_PABX_WI2S_MODE,
-               .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
-                       | PMX_UART0_MODEM_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_gpio = {
-       .name = "telecom_gpio",
-       .modes = pmx_telecom_gpio_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
-       {
-               .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                       HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
-                       | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
-                       | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                       | CAMU_WLCD_MODE | CAML_LCD_MODE,
-               .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_tdm = {
-       .name = "telecom_tdm",
-       .modes = pmx_telecom_tdm_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
-       {
-               .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                       LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
-                       | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
-                       CAML_LCDW_MODE | CAML_LCD_MODE,
-               .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
-       .name = "telecom_spi_cs_i2c_clk",
-       .modes = pmx_telecom_spi_cs_i2c_clk_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
-       {
-               .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
-               .mask = PMX_MII_MASK,
-       }, {
-               .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
-               .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_camera = {
-       .name = "telecom_camera",
-       .modes = pmx_telecom_camera_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
-       {
-               .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                       | CAMU_WLCD_MODE | CAML_LCD_MODE,
-               .mask = PMX_TIMER_1_2_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_dac = {
-       .name = "telecom_dac",
-       .modes = pmx_telecom_dac_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
-       {
-               .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
-                       | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                       ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                       | CAMU_WLCD_MODE | CAML_LCD_MODE,
-               .mask = PMX_UART0_MODEM_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_i2s = {
-       .name = "telecom_i2s",
-       .modes = pmx_telecom_i2s_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
-       {
-               .ids = NAND_MODE | NOR_MODE,
-               .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                       PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_boot_pins = {
-       .name = "telecom_boot_pins",
-       .modes = pmx_telecom_boot_pins_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
-       {
-               .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                       HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                       HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                       CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
-                       ATA_PABX_I2S_MODE,
-               .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                       PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                       PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
-       .name = "telecom_sdhci_4bit",
-       .modes = pmx_telecom_sdhci_4bit_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
-       {
-               .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                       HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                       HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                       CAMU_WLCD_MODE | CAML_LCD_MODE,
-               .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                       PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                       PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
-       .name = "telecom_sdhci_8bit",
-       .modes = pmx_telecom_sdhci_8bit_modes,
-       .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_gpio1_modes[] = {
-       {
-               .ids = PHOTO_FRAME_MODE,
-               .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                       PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear300_pmx_gpio1 = {
-       .name = "arm gpio1",
-       .modes = pmx_gpio1_modes,
-       .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
-       .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-       .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
-       .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
+#include <mach/spear.h>
+
+/* Base address of various IPs */
+#define SPEAR300_TELECOM_BASE          UL(0x50000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG      0x54
+#define SPEAR300_INT_STS_MASK_REG      0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK    (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK  (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK          (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK          (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK     (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK     (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK     (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK     (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK                (1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK       0x1FF
+
+#define SPEAR300_SOC_CONFIG_BASE       UL(0x99000000)
+
+
+/* SPEAr300 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR300_VIRQ_IT_PERS_S                        (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S              (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S                      (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM                      (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L                 (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F                 (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V                 (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD                 (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1                    (SPEAR3XX_VIRQ_START + 8)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR300_IRQ_CLCD                      SPEAR3XX_IRQ_GEN_RAS_3
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR300_IRQ_SDHCI                     SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -423,45 +113,238 @@ static struct spear_shirq shirq_ras1 = {
        },
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-       .gpio_base      = 8,
-       .irq_base       = SPEAR300_GPIO1_INT_BASE,
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear300_dma_info[] = {
+       {
+               .bus_id = "uart0_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart0_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp0_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp0_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "i2c_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "i2c_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "irda",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "adc",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "to_jpeg",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "from_jpeg",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras0_rx",
+               .min_signal = 0,
+               .max_signal = 0,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras0_tx",
+               .min_signal = 1,
+               .max_signal = 1,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras1_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras1_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras2_rx",
+               .min_signal = 4,
+               .max_signal = 4,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras2_tx",
+               .min_signal = 5,
+               .max_signal = 5,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras3_rx",
+               .min_signal = 6,
+               .max_signal = 6,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras3_tx",
+               .min_signal = 7,
+               .max_signal = 7,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras4_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras4_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras5_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras5_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras6_rx",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras6_tx",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras7_rx",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras7_tx",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       },
 };
 
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
-       {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+/* Add SPEAr300 auxdata to pass platform data */
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+       OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                       &pl022_plat_data),
+       OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                       &pl080_plat_data),
+       {}
+};
 
-/* spear300 routines */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-               u8 pmx_dev_count)
+static void __init spear300_dt_init(void)
 {
-       int ret = 0;
+       int ret;
+
+       pl080_plat_data.slave_channels = spear300_dma_info;
+       pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
 
-       /* call spear3xx family common init function */
-       spear3xx_init();
+       of_platform_populate(NULL, of_default_bus_match_table,
+                       spear300_auxdata_lookup, NULL);
 
        /* shared irq registration */
        shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
        if (shirq_ras1.regs.base) {
                ret = spear_shirq_register(&shirq_ras1);
                if (ret)
-                       printk(KERN_ERR "Error registering Shared IRQ\n");
+                       pr_err("Error registering Shared IRQ\n");
        }
+}
 
-       /* pmx initialization */
-       pmx_driver.mode = pmx_mode;
-       pmx_driver.devs = pmx_devs;
-       pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear300_dt_board_compat[] = {
+       "st,spear300",
+       "st,spear300-evb",
+       NULL,
+};
 
-       pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
-       if (pmx_driver.base) {
-               ret = pmx_register(&pmx_driver);
-               if (ret)
-                       printk(KERN_ERR "padmux: registration failed. err no"
-                                       ": %d\n", ret);
-               /* Free Mapping, device selection already done */
-               iounmap(pmx_driver.base);
-       }
+static void __init spear300_map_io(void)
+{
+       spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+       .map_io         =       spear300_map_io,
+       .init_irq       =       spear3xx_dt_init_irq,
+       .handle_irq     =       vic_handle_irq,
+       .timer          =       &spear3xx_timer,
+       .init_machine   =       spear300_dt_init,
+       .restart        =       spear_restart,
+       .dt_compat      =       spear300_dt_board_compat,
+MACHINE_END

diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644 (file)
index 3462ab9..0000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-       /* spear3xx specific devices */
-       &spear3xx_pmx_i2c,
-       &spear3xx_pmx_ssp_cs,
-       &spear3xx_pmx_ssp,
-       &spear3xx_pmx_mii,
-       &spear3xx_pmx_uart0,
-
-       /* spear300 specific devices */
-       &spear300_pmx_fsmc_2_chips,
-       &spear300_pmx_clcd,
-       &spear300_pmx_telecom_sdhci_4bit,
-       &spear300_pmx_gpio1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-       /* spear3xx specific devices */
-       &spear3xx_gpio_device,
-       &spear3xx_uart_device,
-
-       /* spear300 specific devices */
-       &spear300_gpio1_device,
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-       /* spear3xx specific devices */
-
-       /* spear300 specific devices */
-};
-
-static void __init spear300_evb_init(void)
-{
-       unsigned int i;
-
-       /* call spear300 machine init function */
-       spear300_init(&spear300_photo_frame_mode, pmx_devs,
-                       ARRAY_SIZE(pmx_devs));
-
-       /* Add Platform Devices */
-       platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-       /* Add Amba Devices */
-       for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-               amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-       .atag_offset    =       0x100,
-       .map_io         =       spear3xx_map_io,
-       .init_irq       =       spear3xx_init_irq,
-       .handle_irq     =       vic_handle_irq,
-       .timer          =       &spear3xx_timer,
-       .init_machine   =       spear300_evb_init,
-       .restart        =       spear_restart,
-MACHINE_END

diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6f..84dfb09 100644 (file)
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,141 +3,84 @@
  *
  * SPEAr310 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr310: " fmt
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG     0x08
-
-/* devices */
-static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
-       .name = "emi_cs_0_1_4_5",
-       .modes = pmx_emi_cs_0_1_4_5_modes,
-       .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_TIMER_1_2_MASK,
-       },
-};
-
-struct pmx_dev spear310_pmx_emi_cs_2_3 = {
-       .name = "emi_cs_2_3",
-       .modes = pmx_emi_cs_2_3_modes,
-       .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_FIRDA_MASK,
-       },
-};
-
-struct pmx_dev spear310_pmx_uart1 = {
-       .name = "uart1",
-       .modes = pmx_uart1_modes,
-       .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_TIMER_1_2_MASK,
-       },
-};
-
-struct pmx_dev spear310_pmx_uart2 = {
-       .name = "uart2",
-       .modes = pmx_uart2_modes,
-       .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_UART0_MODEM_MASK,
-       },
-};
-
-struct pmx_dev spear310_pmx_uart3_4_5 = {
-       .name = "uart3_4_5",
-       .modes = pmx_uart3_4_5_modes,
-       .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_SSP_CS_MASK,
-       },
-};
-
-struct pmx_dev spear310_pmx_fsmc = {
-       .name = "fsmc",
-       .modes = pmx_fsmc_modes,
-       .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear310_pmx_rs485_0_1 = {
-       .name = "rs485_0_1",
-       .modes = pmx_rs485_0_1_modes,
-       .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_tdm0_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear310_pmx_tdm0 = {
-       .name = "tdm0",
-       .modes = pmx_tdm0_modes,
-       .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
-       .enb_on_reset = 1,
-};
+#include <mach/spear.h>
+
+#define SPEAR310_UART1_BASE            UL(0xB2000000)
+#define SPEAR310_UART2_BASE            UL(0xB2080000)
+#define SPEAR310_UART3_BASE            UL(0xB2100000)
+#define SPEAR310_UART4_BASE            UL(0xB2180000)
+#define SPEAR310_UART5_BASE            UL(0xB2200000)
+#define SPEAR310_SOC_CONFIG_BASE       UL(0xB4000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR310_INT_STS_MASK_REG      0x04
+#define SPEAR310_SMII0_IRQ_MASK                (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK                (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK                (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK                (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK                (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK                (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK                (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK                (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK                (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK          (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK     (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK      (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK      (1 << 16)
+
+#define SPEAR310_SHIRQ_RAS1_MASK       0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK       0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK       0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK       0x1C000
+
+/* SPEAr310 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR310_VIRQ_SMII0                    (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1                    (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2                    (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3                    (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0             (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1             (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2             (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3             (SPEAR3XX_VIRQ_START + 7)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR310_VIRQ_UART1                    (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2                    (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3                    (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4                    (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5                    (SPEAR3XX_VIRQ_START + 12)
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR310_VIRQ_EMI                      (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO                   (SPEAR3XX_VIRQ_START + 14)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR310_VIRQ_TDM_HDLC                 (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0                  (SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1                  (SPEAR3XX_VIRQ_START + 17)
 
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-       .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -255,17 +198,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
        },
 };
 
-/* Add spear310 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+       {
+               .bus_id = "uart0_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart0_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp0_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp0_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "i2c_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "i2c_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "irda",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "adc",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "to_jpeg",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "from_jpeg",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart1_rx",
+               .min_signal = 0,
+               .max_signal = 0,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart1_tx",
+               .min_signal = 1,
+               .max_signal = 1,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart2_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart2_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart3_rx",
+               .min_signal = 4,
+               .max_signal = 4,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart3_tx",
+               .min_signal = 5,
+               .max_signal = 5,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart4_rx",
+               .min_signal = 6,
+               .max_signal = 6,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart4_tx",
+               .min_signal = 7,
+               .max_signal = 7,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart5_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart5_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras5_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras5_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras6_rx",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras6_tx",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras7_rx",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras7_tx",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       },
+};
 
-/* spear310 routines */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-               u8 pmx_dev_count)
+/* uart devices plat data */
+static struct amba_pl011_data spear310_uart_data[] = {
+       {
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "uart1_tx",
+               .dma_rx_param = "uart1_rx",
+       }, {
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "uart2_tx",
+               .dma_rx_param = "uart2_rx",
+       }, {
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "uart3_tx",
+               .dma_rx_param = "uart3_rx",
+       }, {
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "uart4_tx",
+               .dma_rx_param = "uart4_rx",
+       }, {
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "uart5_tx",
+               .dma_rx_param = "uart5_rx",
+       },
+};
+
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+       OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                       &pl022_plat_data),
+       OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                       &pl080_plat_data),
+       OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+                       &spear310_uart_data[0]),
+       OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+                       &spear310_uart_data[1]),
+       OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+                       &spear310_uart_data[2]),
+       OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+                       &spear310_uart_data[3]),
+       OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+                       &spear310_uart_data[4]),
+       {}
+};
+
+static void __init spear310_dt_init(void)
 {
        void __iomem *base;
-       int ret = 0;
+       int ret;
 
-       /* call spear3xx family common init function */
-       spear3xx_init();
+       pl080_plat_data.slave_channels = spear310_dma_info;
+       pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+
+       of_platform_populate(NULL, of_default_bus_match_table,
+                       spear310_auxdata_lookup, NULL);
 
        /* shared irq registration */
        base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +447,45 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                shirq_ras1.regs.base = base;
                ret = spear_shirq_register(&shirq_ras1);
                if (ret)
-                       printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                       pr_err("Error registering Shared IRQ 1\n");
 
                /* shirq 2 */
                shirq_ras2.regs.base = base;
                ret = spear_shirq_register(&shirq_ras2);
                if (ret)
-                       printk(KERN_ERR "Error registering Shared IRQ 2\n");
+                       pr_err("Error registering Shared IRQ 2\n");
 
                /* shirq 3 */
                shirq_ras3.regs.base = base;
                ret = spear_shirq_register(&shirq_ras3);
                if (ret)
-                       printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                       pr_err("Error registering Shared IRQ 3\n");
 
                /* shirq 4 */
                shirq_intrcomm_ras.regs.base = base;
                ret = spear_shirq_register(&shirq_intrcomm_ras);
                if (ret)
-                       printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                       pr_err("Error registering Shared IRQ 4\n");
        }
+}
 
-       /* pmx initialization */
-       pmx_driver.base = base;
-       pmx_driver.mode = pmx_mode;
-       pmx_driver.devs = pmx_devs;
-       pmx_driver.devs_count = pmx_dev_count;
+static const char * const spear310_dt_board_compat[] = {
+       "st,spear310",
+       "st,spear310-evb",
+       NULL,
+};
 
-       ret = pmx_register(&pmx_driver);
-       if (ret)
-               printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                               ret);
+static void __init spear310_map_io(void)
+{
+       spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+       .map_io         =       spear310_map_io,
+       .init_irq       =       spear3xx_dt_init_irq,
+       .handle_irq     =       vic_handle_irq,
+       .timer          =       &spear3xx_timer,
+       .init_machine   =       spear310_dt_init,
+       .restart        =       spear_restart,
+       .dt_compat      =       spear310_dt_board_compat,
+MACHINE_END

diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644 (file)
index f92c499..0000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-       /* spear3xx specific devices */
-       &spear3xx_pmx_i2c,
-       &spear3xx_pmx_ssp,
-       &spear3xx_pmx_gpio_pin0,
-       &spear3xx_pmx_gpio_pin1,
-       &spear3xx_pmx_gpio_pin2,
-       &spear3xx_pmx_gpio_pin3,
-       &spear3xx_pmx_gpio_pin4,
-       &spear3xx_pmx_gpio_pin5,
-       &spear3xx_pmx_uart0,
-
-       /* spear310 specific devices */
-       &spear310_pmx_emi_cs_0_1_4_5,
-       &spear310_pmx_emi_cs_2_3,
-       &spear310_pmx_uart1,
-       &spear310_pmx_uart2,
-       &spear310_pmx_uart3_4_5,
-       &spear310_pmx_fsmc,
-       &spear310_pmx_rs485_0_1,
-       &spear310_pmx_tdm0,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-       /* spear3xx specific devices */
-       &spear3xx_gpio_device,
-       &spear3xx_uart_device,
-
-       /* spear310 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-       /* spear3xx specific devices */
-
-       /* spear310 specific devices */
-};
-
-static void __init spear310_evb_init(void)
-{
-       unsigned int i;
-
-       /* call spear310 machine init function */
-       spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-
-       /* Add Platform Devices */
-       platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-       /* Add Amba Devices */
-       for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-               amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-       .atag_offset    =       0x100,
-       .map_io         =       spear3xx_map_io,
-       .init_irq       =       spear3xx_init_irq,
-       .handle_irq     =       vic_handle_irq,
-       .timer          =       &spear3xx_timer,
-       .init_machine   =       spear310_evb_init,
-       .restart        =       spear_restart,
-MACHINE_END

diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf19..a88fa84 100644 (file)
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,386 +3,84 @@
  *
  * SPEAr320 machine source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/ptrace.h>
-#include <asm/irq.h>
+#define pr_fmt(fmt) "SPEAr320: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* pad multiplexing support */
-/* muxing registers */
-#define PAD_MUX_CONFIG_REG     0x0C
-#define MODE_CONFIG_REG                0x10
-
-/* modes */
-#define AUTO_NET_SMII_MODE     (1 << 0)
-#define AUTO_NET_MII_MODE      (1 << 1)
-#define AUTO_EXP_MODE          (1 << 2)
-#define SMALL_PRINTERS_MODE    (1 << 3)
-#define ALL_MODES              0xF
-
-struct pmx_mode spear320_auto_net_smii_mode = {
-       .id = AUTO_NET_SMII_MODE,
-       .name = "Automation Networking SMII Mode",
-       .mask = 0x00,
-};
-
-struct pmx_mode spear320_auto_net_mii_mode = {
-       .id = AUTO_NET_MII_MODE,
-       .name = "Automation Networking MII Mode",
-       .mask = 0x01,
-};
-
-struct pmx_mode spear320_auto_exp_mode = {
-       .id = AUTO_EXP_MODE,
-       .name = "Automation Expanded Mode",
-       .mask = 0x02,
-};
-
-struct pmx_mode spear320_small_printers_mode = {
-       .id = SMALL_PRINTERS_MODE,
-       .name = "Small Printers Mode",
-       .mask = 0x03,
-};
-
-/* devices */
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE,
-               .mask = 0x0,
-       },
-};
-
-struct pmx_dev spear320_pmx_clcd = {
-       .name = "clcd",
-       .modes = pmx_clcd_modes,
-       .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_emi_modes[] = {
-       {
-               .ids = AUTO_EXP_MODE,
-               .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_emi = {
-       .name = "emi",
-       .modes = pmx_emi_modes,
-       .mode_count = ARRAY_SIZE(pmx_emi_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-       {
-               .ids = ALL_MODES,
-               .mask = 0x0,
-       },
-};
-
-struct pmx_dev spear320_pmx_fsmc = {
-       .name = "fsmc",
-       .modes = pmx_fsmc_modes,
-       .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_spp_modes[] = {
-       {
-               .ids = SMALL_PRINTERS_MODE,
-               .mask = 0x0,
-       },
-};
-
-struct pmx_dev spear320_pmx_spp = {
-       .name = "spp",
-       .modes = pmx_spp_modes,
-       .mode_count = ARRAY_SIZE(pmx_spp_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_sdhci_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
-                       SMALL_PRINTERS_MODE,
-               .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_sdhci = {
-       .name = "sdhci",
-       .modes = pmx_sdhci_modes,
-       .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_i2s_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-               .mask = PMX_UART0_MODEM_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_i2s = {
-       .name = "i2s",
-       .modes = pmx_i2s_modes,
-       .mode_count = ARRAY_SIZE(pmx_i2s_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-       {
-               .ids = ALL_MODES,
-               .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_uart1 = {
-       .name = "uart1",
-       .modes = pmx_uart1_modes,
-       .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
-       {
-               .ids = AUTO_EXP_MODE,
-               .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
-                       PMX_SSP_CS_MASK,
-       }, {
-               .ids = SMALL_PRINTERS_MODE,
-               .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
-                       PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_uart1_modem = {
-       .name = "uart1_modem",
-       .modes = pmx_uart1_modem_modes,
-       .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-       {
-               .ids = ALL_MODES,
-               .mask = PMX_FIRDA_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_uart2 = {
-       .name = "uart2",
-       .modes = pmx_uart2_modes,
-       .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_touchscreen_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE,
-               .mask = PMX_SSP_CS_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_touchscreen = {
-       .name = "touchscreen",
-       .modes = pmx_touchscreen_modes,
-       .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_can_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
-               .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                       PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_can = {
-       .name = "can",
-       .modes = pmx_can_modes,
-       .mode_count = ARRAY_SIZE(pmx_can_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-               .mask = PMX_SSP_CS_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_sdhci_led = {
-       .name = "sdhci_led",
-       .modes = pmx_sdhci_led_modes,
-       .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm0_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-               .mask = PMX_UART0_MODEM_MASK,
-       }, {
-               .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_pwm0 = {
-       .name = "pwm0",
-       .modes = pmx_pwm0_modes,
-       .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm1_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-               .mask = PMX_UART0_MODEM_MASK,
-       }, {
-               .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_pwm1 = {
-       .name = "pwm1",
-       .modes = pmx_pwm1_modes,
-       .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm2_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-               .mask = PMX_SSP_CS_MASK,
-       }, {
-               .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_pwm2 = {
-       .name = "pwm2",
-       .modes = pmx_pwm2_modes,
-       .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_pwm3_modes[] = {
-       {
-               .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_pwm3 = {
-       .name = "pwm3",
-       .modes = pmx_pwm3_modes,
-       .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_ssp1_modes[] = {
-       {
-               .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_ssp1 = {
-       .name = "ssp1",
-       .modes = pmx_ssp1_modes,
-       .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_ssp2_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_ssp2 = {
-       .name = "ssp2",
-       .modes = pmx_ssp2_modes,
-       .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_mii1_modes[] = {
-       {
-               .ids = AUTO_NET_MII_MODE,
-               .mask = 0x0,
-       },
-};
-
-struct pmx_dev spear320_pmx_mii1 = {
-       .name = "mii1",
-       .modes = pmx_mii1_modes,
-       .mode_count = ARRAY_SIZE(pmx_mii1_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_smii0_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_smii0 = {
-       .name = "smii0",
-       .modes = pmx_smii0_modes,
-       .mode_count = ARRAY_SIZE(pmx_smii0_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_smii1_modes[] = {
-       {
-               .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear320_pmx_smii1 = {
-       .name = "smii1",
-       .modes = pmx_smii1_modes,
-       .mode_count = ARRAY_SIZE(pmx_smii1_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_i2c1_modes[] = {
-       {
-               .ids = AUTO_EXP_MODE,
-               .mask = 0x0,
-       },
-};
-
-struct pmx_dev spear320_pmx_i2c1 = {
-       .name = "i2c1",
-       .modes = pmx_i2c1_modes,
-       .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
-       .enb_on_reset = 1,
-};
-
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-       .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
-       .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
+#include <mach/spear.h>
+
+#define SPEAR320_UART1_BASE            UL(0xA3000000)
+#define SPEAR320_UART2_BASE            UL(0xA4000000)
+#define SPEAR320_SSP0_BASE             UL(0xA5000000)
+#define SPEAR320_SSP1_BASE             UL(0xA6000000)
+
+/* Interrupt registers offsets and masks */
+#define SPEAR320_INT_STS_MASK_REG              0x04
+#define SPEAR320_INT_CLR_MASK_REG              0x04
+#define SPEAR320_INT_ENB_MASK_REG              0x08
+#define SPEAR320_GPIO_IRQ_MASK                 (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK             (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK              (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK                  (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK                 (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK                  (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK                        (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK                        (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK                        (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK                        (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK                        (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK                 (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK                 (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK                        (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK           (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK         (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK    (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK                 (1 << 21)
+
+#define SPEAR320_SHIRQ_RAS1_MASK               0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK               0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK       0x3FF800
+
+/* SPEAr320 Virtual irq definitions */
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR320_VIRQ_EMI                      (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD                     (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP                      (SPEAR3XX_VIRQ_START + 2)
+
+/* IRQs sharing IRQ_GEN_RAS_2 */
+#define SPEAR320_IRQ_SDHCI                     SPEAR3XX_IRQ_GEN_RAS_2
+
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR320_VIRQ_PLGPIO                   (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY                 (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC                  (SPEAR3XX_VIRQ_START + 5)
+
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
+#define SPEAR320_VIRQ_CANU                     (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL                     (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1                    (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2                    (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1                     (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2                     (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0                    (SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1               (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0             (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1                (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C1                     (SPEAR3XX_VIRQ_START + 16)
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -508,17 +206,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
        },
 };
 
-/* Add spear320 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+       {
+               .bus_id = "uart0_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart0_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp0_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp0_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "i2c0_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "i2c0_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "irda",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "adc",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "to_jpeg",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "from_jpeg",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp1_rx",
+               .min_signal = 0,
+               .max_signal = 0,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ssp1_tx",
+               .min_signal = 1,
+               .max_signal = 1,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ssp2_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ssp2_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "uart1_rx",
+               .min_signal = 4,
+               .max_signal = 4,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "uart1_tx",
+               .min_signal = 5,
+               .max_signal = 5,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "uart2_rx",
+               .min_signal = 6,
+               .max_signal = 6,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "uart2_tx",
+               .min_signal = 7,
+               .max_signal = 7,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "i2c1_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "i2c1_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "i2c2_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "i2c2_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "i2s_rx",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "i2s_tx",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "rs485_rx",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "rs485_tx",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       },
+};
+
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+       {
+               .bus_id = 1,
+               .enable_dma = 1,
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "ssp1_tx",
+               .dma_rx_param = "ssp1_rx",
+               .num_chipselect = 2,
+       }, {
+               .bus_id = 2,
+               .enable_dma = 1,
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "ssp2_tx",
+               .dma_rx_param = "ssp2_rx",
+               .num_chipselect = 2,
+       }
+};
+
+static struct amba_pl011_data spear320_uart_data[] = {
+       {
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "uart1_tx",
+               .dma_rx_param = "uart1_rx",
+       }, {
+               .dma_filter = pl08x_filter_id,
+               .dma_tx_param = "uart2_tx",
+               .dma_rx_param = "uart2_rx",
+       },
+};
 
-/* spear320 routines */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-               u8 pmx_dev_count)
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
+       OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                       &pl022_plat_data),
+       OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                       &pl080_plat_data),
+       OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+                       &spear320_ssp_data[0]),
+       OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+                       &spear320_ssp_data[1]),
+       OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+                       &spear320_uart_data[0]),
+       OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+                       &spear320_uart_data[1]),
+       {}
+};
+
+static void __init spear320_dt_init(void)
 {
        void __iomem *base;
-       int ret = 0;
+       int ret;
 
-       /* call spear3xx family common init function */
-       spear3xx_init();
+       pl080_plat_data.slave_channels = spear320_dma_info;
+       pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
+
+       of_platform_populate(NULL, of_default_bus_match_table,
+                       spear320_auxdata_lookup, NULL);
 
        /* shared irq registration */
        base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +458,49 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                shirq_ras1.regs.base = base;
                ret = spear_shirq_register(&shirq_ras1);
                if (ret)
-                       printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                       pr_err("Error registering Shared IRQ 1\n");
 
                /* shirq 3 */
                shirq_ras3.regs.base = base;
                ret = spear_shirq_register(&shirq_ras3);
                if (ret)
-                       printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                       pr_err("Error registering Shared IRQ 3\n");
 
                /* shirq 4 */
                shirq_intrcomm_ras.regs.base = base;
                ret = spear_shirq_register(&shirq_intrcomm_ras);
                if (ret)
-                       printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                       pr_err("Error registering Shared IRQ 4\n");
        }
+}
+
+static const char * const spear320_dt_board_compat[] = {
+       "st,spear320",
+       "st,spear320-evb",
+       NULL,
+};
 
-       /* pmx initialization */
-       pmx_driver.base = base;
-       pmx_driver.mode = pmx_mode;
-       pmx_driver.devs = pmx_devs;
-       pmx_driver.devs_count = pmx_dev_count;
+struct map_desc spear320_io_desc[] __initdata = {
+       {
+               .virtual        = VA_SPEAR320_SOC_CONFIG_BASE,
+               .pfn            = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
+               .length         = SZ_16M,
+               .type           = MT_DEVICE
+       },
+};
 
-       ret = pmx_register(&pmx_driver);
-       if (ret)
-               printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                               ret);
+static void __init spear320_map_io(void)
+{
+       iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
+       spear3xx_map_io();
 }
+
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+       .map_io         =       spear320_map_io,
+       .init_irq       =       spear3xx_dt_init_irq,
+       .handle_irq     =       vic_handle_irq,
+       .timer          =       &spear3xx_timer,
+       .init_machine   =       spear320_dt_init,
+       .restart        =       spear_restart,
+       .dt_compat      =       spear320_dt_board_compat,
+MACHINE_END

diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644 (file)
index 105334a..0000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-       /* spear3xx specific devices */
-       &spear3xx_pmx_i2c,
-       &spear3xx_pmx_ssp,
-       &spear3xx_pmx_mii,
-       &spear3xx_pmx_uart0,
-
-       /* spear320 specific devices */
-       &spear320_pmx_fsmc,
-       &spear320_pmx_sdhci,
-       &spear320_pmx_i2s,
-       &spear320_pmx_uart1,
-       &spear320_pmx_uart2,
-       &spear320_pmx_can,
-       &spear320_pmx_pwm0,
-       &spear320_pmx_pwm1,
-       &spear320_pmx_pwm2,
-       &spear320_pmx_mii1,
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-       /* spear3xx specific devices */
-       &spear3xx_gpio_device,
-       &spear3xx_uart_device,
-
-       /* spear320 specific devices */
-};
-
-static struct platform_device *plat_devs[] __initdata = {
-       /* spear3xx specific devices */
-
-       /* spear320 specific devices */
-};
-
-static void __init spear320_evb_init(void)
-{
-       unsigned int i;
-
-       /* call spear320 machine init function */
-       spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-                       ARRAY_SIZE(pmx_devs));
-
-       /* Add Platform Devices */
-       platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-
-       /* Add Amba Devices */
-       for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-               amba_device_register(amba_devs[i], &iomem_resource);
-}
-
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-       .atag_offset    =       0x100,
-       .map_io         =       spear3xx_map_io,
-       .init_irq       =       spear3xx_init_irq,
-       .handle_irq     =       vic_handle_irq,
-       .timer          =       &spear3xx_timer,
-       .init_machine   =       spear320_evb_init,
-       .restart        =       spear_restart,
-MACHINE_END

diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c3..f22419e 100644 (file)
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
  *
  * SPEAr3XX machines common source file
  *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <linux/types.h>
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
+
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-
-/* Add spear3xx machines common devices here */
-/* gpio device registration */
-static struct pl061_platform_data gpio_plat_data = {
-       .gpio_base      = 0,
-       .irq_base       = SPEAR3XX_GPIO_INT_BASE,
+#include <mach/spear.h>
+
+/* ssp device registration */
+struct pl022_ssp_controller pl022_plat_data = {
+       .bus_id = 0,
+       .enable_dma = 1,
+       .dma_filter = pl08x_filter_id,
+       .dma_tx_param = "ssp0_tx",
+       .dma_rx_param = "ssp0_rx",
+       /*
+        * This is number of spi devices that can be connected to spi. There are
+        * two type of chipselects on which slave devices can work. One is chip
+        * select provided by spi masters other is controlled through external
+        * gpio's. We can't use chipselect provided from spi master (because as
+        * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+        * this number now depends on number of gpios available for spi. each
+        * slave on each master requires a separate gpio pin.
+        */
+       .num_chipselect = 2,
+};
+
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+       .memcpy_channel = {
+               .bus_id = "memcpy",
+               .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                       PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                       PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                       PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                       PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                       PL080_CONTROL_PROT_SYS),
+       },
+       .lli_buses = PL08X_AHB1,
+       .mem_buses = PL08X_AHB1,
+       .get_signal = pl080_get_signal,
+       .put_signal = pl080_put_signal,
 };
 
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
-       {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
-
-/* uart device registration */
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
-       {SPEAR3XX_IRQ_UART}, NULL);
-
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
-       /* nothing to do for now */
-}
-
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-       vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-
-/* Following will create static virtual/physical mappings */
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL            VIRTUAL
+ * 0xD0000000          0xFD000000
+ * 0xFC000000          0xFC000000
+ */
 struct map_desc spear3xx_io_desc[] __initdata = {
        {
-               .virtual        = VA_SPEAR3XX_ICM1_UART_BASE,
-               .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE
-       }, {
-               .virtual        = VA_SPEAR3XX_ML1_VIC_BASE,
-               .pfn            = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE
-       }, {
-               .virtual        = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
-               .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-               .length         = SZ_4K,
+               .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
+               .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+               .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-               .virtual        = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
-               .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-               .length         = SZ_4K,
+               .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
+               .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+               .length         = SZ_16M,
                .type           = MT_DEVICE
        },
 };
@@ -76,441 +83,15 @@ struct map_desc spear3xx_io_desc[] __initdata = {
 void __init spear3xx_map_io(void)
 {
        iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-
-       /* This will initialize clock framework */
-       spear3xx_clk_init();
 }
 
-/* pad multiplexing support */
-/* devices */
-static struct pmx_dev_mode pmx_firda_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_FIRDA_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_firda = {
-       .name = "firda",
-       .modes = pmx_firda_modes,
-       .mode_count = ARRAY_SIZE(pmx_firda_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_i2c_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_I2C_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_i2c = {
-       .name = "i2c",
-       .modes = pmx_i2c_modes,
-       .mode_count = ARRAY_SIZE(pmx_i2c_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_SSP_CS_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_ssp_cs = {
-       .name = "ssp_chip_selects",
-       .modes = pmx_ssp_cs_modes,
-       .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_ssp_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_SSP_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_ssp = {
-       .name = "ssp",
-       .modes = pmx_ssp_modes,
-       .mode_count = ARRAY_SIZE(pmx_ssp_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_mii_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_mii = {
-       .name = "mii",
-       .modes = pmx_mii_modes,
-       .mode_count = ARRAY_SIZE(pmx_mii_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_GPIO_PIN0_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin0 = {
-       .name = "gpio_pin0",
-       .modes = pmx_gpio_pin0_modes,
-       .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_GPIO_PIN1_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin1 = {
-       .name = "gpio_pin1",
-       .modes = pmx_gpio_pin1_modes,
-       .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_GPIO_PIN2_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin2 = {
-       .name = "gpio_pin2",
-       .modes = pmx_gpio_pin2_modes,
-       .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_GPIO_PIN3_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin3 = {
-       .name = "gpio_pin3",
-       .modes = pmx_gpio_pin3_modes,
-       .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_GPIO_PIN4_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin4 = {
-       .name = "gpio_pin4",
-       .modes = pmx_gpio_pin4_modes,
-       .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_GPIO_PIN5_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_gpio_pin5 = {
-       .name = "gpio_pin5",
-       .modes = pmx_gpio_pin5_modes,
-       .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_UART0_MODEM_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_uart0_modem = {
-       .name = "uart0_modem",
-       .modes = pmx_uart0_modem_modes,
-       .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_uart0_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_UART0_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_uart0 = {
-       .name = "uart0",
-       .modes = pmx_uart0_modes,
-       .mode_count = ARRAY_SIZE(pmx_uart0_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_timer_3_4 = {
-       .name = "timer_3_4",
-       .modes = pmx_timer_3_4_modes,
-       .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
-       .enb_on_reset = 0,
-};
-
-static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
-       {
-               .ids = 0xffffffff,
-               .mask = PMX_TIMER_1_2_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_timer_1_2 = {
-       .name = "timer_1_2",
-       .modes = pmx_timer_1_2_modes,
-       .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
-       .enb_on_reset = 0,
-};
-
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* plgpios devices */
-static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_FIRDA_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
-       .name = "plgpio 0 and 1",
-       .modes = pmx_plgpio_0_1_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_UART0_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
-       .name = "plgpio 2 and 3",
-       .modes = pmx_plgpio_2_3_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_I2C_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
-       .name = "plgpio 4 and 5",
-       .modes = pmx_plgpio_4_5_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_SSP_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
-       .name = "plgpio 6 to 9",
-       .modes = pmx_plgpio_6_9_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_MII_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
-       .name = "plgpio 10 to 27",
-       .modes = pmx_plgpio_10_27_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_GPIO_PIN0_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_28 = {
-       .name = "plgpio 28",
-       .modes = pmx_plgpio_28_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_GPIO_PIN1_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_29 = {
-       .name = "plgpio 29",
-       .modes = pmx_plgpio_29_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_GPIO_PIN2_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_30 = {
-       .name = "plgpio 30",
-       .modes = pmx_plgpio_30_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_GPIO_PIN3_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_31 = {
-       .name = "plgpio 31",
-       .modes = pmx_plgpio_31_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_GPIO_PIN4_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_32 = {
-       .name = "plgpio 32",
-       .modes = pmx_plgpio_32_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_GPIO_PIN5_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_33 = {
-       .name = "plgpio 33",
-       .modes = pmx_plgpio_33_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_SSP_CS_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
-       .name = "plgpio 34 to 36",
-       .modes = pmx_plgpio_34_36_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_UART0_MODEM_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
-       .name = "plgpio 37 to 42",
-       .modes = pmx_plgpio_37_42_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_TIMER_1_2_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
-       .name = "plgpio 43, 44, 47 and 48",
-       .modes = pmx_plgpio_43_44_47_48_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
-       .enb_on_reset = 1,
-};
-
-static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
-       {
-               .ids = 0x00,
-               .mask = PMX_TIMER_3_4_MASK,
-       },
-};
-
-struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
-       .name = "plgpio 45, 46, 49 and 50",
-       .modes = pmx_plgpio_45_46_49_50_modes,
-       .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
-       .enb_on_reset = 1,
-};
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
-
 static void __init spear3xx_timer_init(void)
 {
        char pclk_name[] = "pll3_48m_clk";
        struct clk *gpt_clk, *pclk;
 
+       spear3xx_clk_init();
+
        /* get the system timer clock */
        gpt_clk = clk_get_sys("gpt0", NULL);
        if (IS_ERR(gpt_clk)) {
@@ -530,9 +111,19 @@ static void __init spear3xx_timer_init(void)
        clk_put(gpt_clk);
        clk_put(pclk);
 
-       spear_setup_timer();
+       spear_setup_of_timer();
 }
 
 struct sys_timer spear3xx_timer = {
        .init = spear3xx_timer_init,
 };
+
+static const struct of_device_id vic_of_match[] __initconst = {
+       { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+       { /* Sentinel */ }
+};
+
+void __init spear3xx_dt_init_irq(void)
+{
+       of_irq_init(vic_of_match);
+}

diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750..898831d 100644 (file)
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
 #
 
 # common files
-obj-y  += clock.o spear6xx.o
+obj-y  += spear6xx.o

diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c..af493da 100644 (file)
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y     += 0x00008000
 params_phys-y  := 0x00000100
 initrd_phys-y  := 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT)        += spear600-evb.dtb

diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644 (file)
index a86499a..0000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,683 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/clock.c
- *
- * SPEAr6xx machines clock framework source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <plat/clock.h>
-#include <mach/misc_regs.h>
-
-/* root clks */
-/* 32 KHz oscillator clock */
-static struct clk osc_32k_clk = {
-       .flags = ALWAYS_ENABLED,
-       .rate = 32000,
-};
-
-/* 30 MHz oscillator clock */
-static struct clk osc_30m_clk = {
-       .flags = ALWAYS_ENABLED,
-       .rate = 30000000,
-};
-
-/* clock derived from 32 KHz osc clk */
-/* rtc clock */
-static struct clk rtc_clk = {
-       .pclk = &osc_32k_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = RTC_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from 30 MHz osc clk */
-/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
-       .mode_mask = PLL_MODE_MASK,
-       .mode_shift = PLL_MODE_SHIFT,
-       .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
-       .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
-       .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
-       .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
-       .div_p_mask = PLL_DIV_P_MASK,
-       .div_p_shift = PLL_DIV_P_SHIFT,
-       .div_n_mask = PLL_DIV_N_MASK,
-       .div_n_shift = PLL_DIV_N_SHIFT,
-};
-
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
-       .mode_reg = PLL1_CTR,
-       .cfg_reg = PLL1_FRQ,
-       .masks = &pll1_masks,
-};
-
-/* pll rate configuration table, in ascending order of rates */
-struct pll_rate_tbl pll_rtbl[] = {
-       {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
-       {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
-};
-
-/* PLL1 clock */
-static struct clk pll1_clk = {
-       .flags = ENABLED_ON_INIT,
-       .pclk = &osc_30m_clk,
-       .en_reg = PLL1_CTR,
-       .en_reg_bit = PLL_ENABLE,
-       .calc_rate = &pll_calc_rate,
-       .recalc = &pll_clk_recalc,
-       .set_rate = &pll_clk_set_rate,
-       .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
-       .private_data = &pll1_config,
-};
-
-/* PLL3 48 MHz clock */
-static struct clk pll3_48m_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &osc_30m_clk,
-       .rate = 48000000,
-};
-
-/* watch dog timer clock */
-static struct clk wdt_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &osc_30m_clk,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from pll1 clk */
-/* cpu clock */
-static struct clk cpu_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .recalc = &follow_parent,
-};
-
-/* ahb masks structure */
-static struct bus_clk_masks ahb_masks = {
-       .mask = PLL_HCLK_RATIO_MASK,
-       .shift = PLL_HCLK_RATIO_SHIFT,
-};
-
-/* ahb configuration structure */
-static struct bus_clk_config ahb_config = {
-       .reg = CORE_CLK_CFG,
-       .masks = &ahb_masks,
-};
-
-/* ahb rate configuration table, in ascending order of rates */
-struct bus_rate_tbl bus_rtbl[] = {
-       {.div = 3}, /* == parent divided by 4 */
-       {.div = 2}, /* == parent divided by 3 */
-       {.div = 1}, /* == parent divided by 2 */
-       {.div = 0}, /* == parent divided by 1 */
-};
-
-/* ahb clock */
-static struct clk ahb_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .calc_rate = &bus_calc_rate,
-       .recalc = &bus_clk_recalc,
-       .set_rate = &bus_clk_set_rate,
-       .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-       .private_data = &ahb_config,
-};
-
-/* auxiliary synthesizers masks */
-static struct aux_clk_masks aux_masks = {
-       .eq_sel_mask = AUX_EQ_SEL_MASK,
-       .eq_sel_shift = AUX_EQ_SEL_SHIFT,
-       .eq1_mask = AUX_EQ1_SEL,
-       .eq2_mask = AUX_EQ2_SEL,
-       .xscale_sel_mask = AUX_XSCALE_MASK,
-       .xscale_sel_shift = AUX_XSCALE_SHIFT,
-       .yscale_sel_mask = AUX_YSCALE_MASK,
-       .yscale_sel_shift = AUX_YSCALE_SHIFT,
-};
-
-/* uart configurations */
-static struct aux_clk_config uart_synth_config = {
-       .synth_reg = UART_CLK_SYNT,
-       .masks = &aux_masks,
-};
-
-/* aux rate configuration table, in ascending order of rates */
-struct aux_rate_tbl aux_rtbl[] = {
-       /* For PLL1 = 332 MHz */
-       {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
-       {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
-       {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
-};
-
-/* uart synth clock */
-static struct clk uart_synth_clk = {
-       .en_reg = UART_CLK_SYNT,
-       .en_reg_bit = AUX_SYNT_ENB,
-       .pclk = &pll1_clk,
-       .calc_rate = &aux_calc_rate,
-       .recalc = &aux_clk_recalc,
-       .set_rate = &aux_clk_set_rate,
-       .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-       .private_data = &uart_synth_config,
-};
-
-/* uart parents */
-static struct pclk_info uart_pclk_info[] = {
-       {
-               .pclk = &uart_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* uart parent select structure */
-static struct pclk_sel uart_pclk_sel = {
-       .pclk_info = uart_pclk_info,
-       .pclk_count = ARRAY_SIZE(uart_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = UART_CLK_MASK,
-};
-
-/* uart0 clock */
-static struct clk uart0_clk = {
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = UART0_CLK_ENB,
-       .pclk_sel = &uart_pclk_sel,
-       .pclk_sel_shift = UART_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* uart1 clock */
-static struct clk uart1_clk = {
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = UART1_CLK_ENB,
-       .pclk_sel = &uart_pclk_sel,
-       .pclk_sel_shift = UART_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* firda configurations */
-static struct aux_clk_config firda_synth_config = {
-       .synth_reg = FIRDA_CLK_SYNT,
-       .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk firda_synth_clk = {
-       .en_reg = FIRDA_CLK_SYNT,
-       .en_reg_bit = AUX_SYNT_ENB,
-       .pclk = &pll1_clk,
-       .calc_rate = &aux_calc_rate,
-       .recalc = &aux_clk_recalc,
-       .set_rate = &aux_clk_set_rate,
-       .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-       .private_data = &firda_synth_config,
-};
-
-/* firda parents */
-static struct pclk_info firda_pclk_info[] = {
-       {
-               .pclk = &firda_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* firda parent select structure */
-static struct pclk_sel firda_pclk_sel = {
-       .pclk_info = firda_pclk_info,
-       .pclk_count = ARRAY_SIZE(firda_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = FIRDA_CLK_MASK,
-};
-
-/* firda clock */
-static struct clk firda_clk = {
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = FIRDA_CLK_ENB,
-       .pclk_sel = &firda_pclk_sel,
-       .pclk_sel_shift = FIRDA_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* clcd configurations */
-static struct aux_clk_config clcd_synth_config = {
-       .synth_reg = CLCD_CLK_SYNT,
-       .masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk clcd_synth_clk = {
-       .en_reg = CLCD_CLK_SYNT,
-       .en_reg_bit = AUX_SYNT_ENB,
-       .pclk = &pll1_clk,
-       .calc_rate = &aux_calc_rate,
-       .recalc = &aux_clk_recalc,
-       .set_rate = &aux_clk_set_rate,
-       .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-       .private_data = &clcd_synth_config,
-};
-
-/* clcd parents */
-static struct pclk_info clcd_pclk_info[] = {
-       {
-               .pclk = &clcd_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* clcd parent select structure */
-static struct pclk_sel clcd_pclk_sel = {
-       .pclk_info = clcd_pclk_info,
-       .pclk_count = ARRAY_SIZE(clcd_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = CLCD_CLK_MASK,
-};
-
-/* clcd clock */
-static struct clk clcd_clk = {
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = CLCD_CLK_ENB,
-       .pclk_sel = &clcd_pclk_sel,
-       .pclk_sel_shift = CLCD_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* gpt synthesizer masks */
-static struct gpt_clk_masks gpt_masks = {
-       .mscale_sel_mask = GPT_MSCALE_MASK,
-       .mscale_sel_shift = GPT_MSCALE_SHIFT,
-       .nscale_sel_mask = GPT_NSCALE_MASK,
-       .nscale_sel_shift = GPT_NSCALE_SHIFT,
-};
-
-/* gpt rate configuration table, in ascending order of rates */
-struct gpt_rate_tbl gpt_rtbl[] = {
-       /* For pll1 = 332 MHz */
-       {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
-       {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
-       {.mscale = 1, .nscale = 0}, /* 83 MHz */
-};
-
-/* gpt0 synth clk config*/
-static struct gpt_clk_config gpt0_synth_config = {
-       .synth_reg = PRSC1_CLK_CFG,
-       .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt0_synth_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .calc_rate = &gpt_calc_rate,
-       .recalc = &gpt_clk_recalc,
-       .set_rate = &gpt_clk_set_rate,
-       .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-       .private_data = &gpt0_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt0_pclk_info[] = {
-       {
-               .pclk = &gpt0_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt0_pclk_sel = {
-       .pclk_info = gpt0_pclk_info,
-       .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt0 ARM1 subsystem timer clock */
-static struct clk gpt0_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk_sel = &gpt0_pclk_sel,
-       .pclk_sel_shift = GPT0_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-
-/* Note: gpt0 and gpt1 share same parent clocks */
-/* gpt parent select structure */
-static struct pclk_sel gpt1_pclk_sel = {
-       .pclk_info = gpt0_pclk_info,
-       .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt1 timer clock */
-static struct clk gpt1_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk_sel = &gpt1_pclk_sel,
-       .pclk_sel_shift = GPT1_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* gpt2 synth clk config*/
-static struct gpt_clk_config gpt2_synth_config = {
-       .synth_reg = PRSC2_CLK_CFG,
-       .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt2_synth_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .calc_rate = &gpt_calc_rate,
-       .recalc = &gpt_clk_recalc,
-       .set_rate = &gpt_clk_set_rate,
-       .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-       .private_data = &gpt2_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt2_pclk_info[] = {
-       {
-               .pclk = &gpt2_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt2_pclk_sel = {
-       .pclk_info = gpt2_pclk_info,
-       .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt2 timer clock */
-static struct clk gpt2_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk_sel = &gpt2_pclk_sel,
-       .pclk_sel_shift = GPT2_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* gpt3 synth clk config*/
-static struct gpt_clk_config gpt3_synth_config = {
-       .synth_reg = PRSC3_CLK_CFG,
-       .masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt3_synth_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &pll1_clk,
-       .calc_rate = &gpt_calc_rate,
-       .recalc = &gpt_clk_recalc,
-       .set_rate = &gpt_clk_set_rate,
-       .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-       .private_data = &gpt3_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt3_pclk_info[] = {
-       {
-               .pclk = &gpt3_synth_clk,
-               .pclk_val = AUX_CLK_PLL1_VAL,
-       }, {
-               .pclk = &pll3_48m_clk,
-               .pclk_val = AUX_CLK_PLL3_VAL,
-       },
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt3_pclk_sel = {
-       .pclk_info = gpt3_pclk_info,
-       .pclk_count = ARRAY_SIZE(gpt3_pclk_info),
-       .pclk_sel_reg = PERIP_CLK_CFG,
-       .pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt3 timer clock */
-static struct clk gpt3_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk_sel = &gpt3_pclk_sel,
-       .pclk_sel_shift = GPT3_CLK_SHIFT,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from pll3 clk */
-/* usbh0 clock */
-static struct clk usbh0_clk = {
-       .pclk = &pll3_48m_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = USBH0_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* usbh1 clock */
-static struct clk usbh1_clk = {
-       .pclk = &pll3_48m_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = USBH1_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* usbd clock */
-static struct clk usbd_clk = {
-       .pclk = &pll3_48m_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = USBD_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from ahb clk */
-/* apb masks structure */
-static struct bus_clk_masks apb_masks = {
-       .mask = HCLK_PCLK_RATIO_MASK,
-       .shift = HCLK_PCLK_RATIO_SHIFT,
-};
-
-/* apb configuration structure */
-static struct bus_clk_config apb_config = {
-       .reg = CORE_CLK_CFG,
-       .masks = &apb_masks,
-};
-
-/* apb clock */
-static struct clk apb_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &ahb_clk,
-       .calc_rate = &bus_calc_rate,
-       .recalc = &bus_clk_recalc,
-       .set_rate = &bus_clk_set_rate,
-       .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-       .private_data = &apb_config,
-};
-
-/* i2c clock */
-static struct clk i2c_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = I2C_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* dma clock */
-static struct clk dma_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = DMA_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* jpeg clock */
-static struct clk jpeg_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = JPEG_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* gmac clock */
-static struct clk gmac_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = GMAC_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* smi clock */
-static struct clk smi_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = SMI_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* fsmc clock */
-static struct clk fsmc_clk = {
-       .pclk = &ahb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = FSMC_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* clock derived from apb clk */
-/* adc clock */
-static struct clk adc_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = ADC_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* ssp0 clock */
-static struct clk ssp0_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = SSP0_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* ssp1 clock */
-static struct clk ssp1_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = SSP1_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* ssp2 clock */
-static struct clk ssp2_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = SSP2_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* gpio0 ARM subsystem clock */
-static struct clk gpio0_clk = {
-       .flags = ALWAYS_ENABLED,
-       .pclk = &apb_clk,
-       .recalc = &follow_parent,
-};
-
-/* gpio1 clock */
-static struct clk gpio1_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = GPIO1_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-/* gpio2 clock */
-static struct clk gpio2_clk = {
-       .pclk = &apb_clk,
-       .en_reg = PERIP1_CLK_ENB,
-       .en_reg_bit = GPIO2_CLK_ENB,
-       .recalc = &follow_parent,
-};
-
-static struct clk dummy_apb_pclk;
-
-/* array of all spear 6xx clock lookups */
-static struct clk_lookup spear_clk_lookups[] = {
-       { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
-       /* root clks */
-       { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
-       { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
-       /* clock derived from 32 KHz os          clk */
-       { .dev_id = "rtc-spear",        .clk = &rtc_clk},
-       /* clock derived from 30 MHz os          clk */
-       { .con_id = "pll1_clk",         .clk = &pll1_clk},
-       { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
-       { .dev_id = "wdt",              .clk = &wdt_clk},
-       /* clock derived from pll1 clk */
-       { .con_id = "cpu_clk",          .clk = &cpu_clk},
-       { .con_id = "ahb_clk",          .clk = &ahb_clk},
-       { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
-       { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
-       { .con_id = "clcd_synth_clk",   .clk = &clcd_synth_clk},
-       { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
-       { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
-       { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
-       { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
-       { .dev_id = "d0080000.serial",  .clk = &uart1_clk},
-       { .dev_id = "firda",            .clk = &firda_clk},
-       { .dev_id = "clcd",             .clk = &clcd_clk},
-       { .dev_id = "gpt0",             .clk = &gpt0_clk},
-       { .dev_id = "gpt1",             .clk = &gpt1_clk},
-       { .dev_id = "gpt2",             .clk = &gpt2_clk},
-       { .dev_id = "gpt3",             .clk = &gpt3_clk},
-       /* clock derived from pll3 clk */
-       { .dev_id = "designware_udc",   .clk = &usbd_clk},
-       { .con_id = "usbh.0_clk",       .clk = &usbh0_clk},
-       { .con_id = "usbh.1_clk",       .clk = &usbh1_clk},
-       /* clock derived from ahb clk */
-       { .con_id = "apb_clk",          .clk = &apb_clk},
-       { .dev_id = "d0200000.i2c",     .clk = &i2c_clk},
-       { .dev_id = "dma",              .clk = &dma_clk},
-       { .dev_id = "jpeg",             .clk = &jpeg_clk},
-       { .dev_id = "gmac",             .clk = &gmac_clk},
-       { .dev_id = "smi",              .clk = &smi_clk},
-       { .dev_id = "fsmc-nand",        .clk = &fsmc_clk},
-       /* clock derived from apb clk */
-       { .dev_id = "adc",              .clk = &adc_clk},
-       { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
-       { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
-       { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
-       { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
-       { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},
-       { .dev_id = "d8100000.gpio",    .clk = &gpio2_clk},
-};
-
-void __init spear6xx_clk_init(void)
-{
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
-               clk_register(&spear_clk_lookups[i]);
-
-       clk_init();
-}

diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b993..65514b1 100644 (file)
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
 #define __MACH_GENERIC_H
 
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE                SPEAR6XX_CPU_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ   IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ   IRQ_CPU_GPT1_2
-
-/* Add spear6xx family device structure declarations here */
-extern struct amba_device gpio_device[];
-extern struct amba_device uart_device[];
-extern struct sys_timer spear6xx_timer;
-
-/* Add spear6xx family function declarations here */
-void __init spear_setup_timer(void);
-void __init spear6xx_map_io(void);
-void __init spear6xx_init_irq(void);
-void __init spear6xx_init(void);
-void __init spear600_init(void);
-void __init spear6xx_clk_init(void);
 
+void __init spear_setup_of_timer(void);
 void spear_restart(char, const char *);
-
-/* Add spear600 machine device structure declarations here */
+void __init spear6xx_clk_init(void);
 
 #endif /* __MACH_GENERIC_H */

diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96a..40a8c17 100644 (file)
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)          (x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */

diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b0..37a5c41 100644 (file)
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,10 @@
 
 /* IRQ definitions */
 /* VIC 1 */
-#define IRQ_INTRCOMM_SW_IRQ                    0
-#define IRQ_INTRCOMM_CPU_1                     1
-#define IRQ_INTRCOMM_CPU_2                     2
-#define IRQ_INTRCOMM_RAS2A11_1                 3
-#define IRQ_INTRCOMM_RAS2A11_2                 4
-#define IRQ_INTRCOMM_RAS2A12_1                 5
-#define IRQ_INTRCOMM_RAS2A12_2                 6
-#define IRQ_GEN_RAS_0                          7
-#define IRQ_GEN_RAS_1                          8
-#define IRQ_GEN_RAS_2                          9
-#define IRQ_GEN_RAS_3                          10
-#define IRQ_GEN_RAS_4                          11
-#define IRQ_GEN_RAS_5                          12
-#define IRQ_GEN_RAS_6                          13
-#define IRQ_GEN_RAS_7                          14
-#define IRQ_GEN_RAS_8                          15
-#define IRQ_CPU_GPT1_1                         16
-#define IRQ_CPU_GPT1_2                         17
-#define IRQ_LOCAL_GPIO                         18
-#define IRQ_PLL_UNLOCK                         19
-#define IRQ_JPEG                               20
-#define IRQ_FSMC                               21
-#define IRQ_IRDA                               22
-#define IRQ_RESERVED                           23
-#define IRQ_UART_0                             24
-#define IRQ_UART_1                             25
-#define IRQ_SSP_1                              26
-#define IRQ_SSP_2                              27
-#define IRQ_I2C                                        28
-#define IRQ_GEN_RAS_9                          29
-#define IRQ_GEN_RAS_10                         30
-#define IRQ_GEN_RAS_11                         31
-
-/* VIC 2 */
-#define IRQ_APPL_GPT1_1                                32
-#define IRQ_APPL_GPT1_2                                33
-#define IRQ_APPL_GPT2_1                                34
-#define IRQ_APPL_GPT2_2                                35
-#define IRQ_APPL_GPIO                          36
-#define IRQ_APPL_SSP                           37
-#define IRQ_APPL_ADC                           38
-#define IRQ_APPL_RESERVED                      39
-#define IRQ_AHB_EXP_MASTER                     40
-#define IRQ_DDR_CONTROLLER                     41
-#define IRQ_BASIC_DMA                          42
-#define IRQ_BASIC_RESERVED1                    43
-#define IRQ_BASIC_SMI                          44
-#define IRQ_BASIC_CLCD                         45
-#define IRQ_EXP_AHB_1                          46
-#define IRQ_EXP_AHB_2                          47
-#define IRQ_BASIC_GPT1_1                       48
-#define IRQ_BASIC_GPT1_2                       49
-#define IRQ_BASIC_RTC                          50
-#define IRQ_BASIC_GPIO                         51
-#define IRQ_BASIC_WDT                          52
-#define IRQ_BASIC_RESERVED                     53
-#define IRQ_AHB_EXP_SLAVE                      54
-#define IRQ_GMAC_1                             55
-#define IRQ_GMAC_2                             56
-#define IRQ_USB_DEV                            57
-#define IRQ_USB_H_OHCI_0                       58
-#define IRQ_USB_H_EHCI_0                       59
-#define IRQ_USB_H_OHCI_1                       60
-#define IRQ_USB_H_EHCI_1                       61
-#define IRQ_EXP_AHB_3                          62
-#define IRQ_EXP_AHB_4                          63
-
 #define IRQ_VIC_END                            64
 
 /* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE    IRQ_VIC_END
-#define SPEAR_GPIO0_INT_BASE   SPEAR_GPIO_INT_BASE
-#define SPEAR_GPIO1_INT_BASE   (SPEAR_GPIO0_INT_BASE + 8)
-#define SPEAR_GPIO2_INT_BASE   (SPEAR_GPIO1_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END     (SPEAR_GPIO2_INT_BASE + 8)
-#define VIRTUAL_IRQS           (SPEAR_GPIO_INT_END - IRQ_VIC_END)
-#define NR_IRQS                        (IRQ_VIC_END + VIRTUAL_IRQS)
+#define VIRTUAL_IRQS                           24
+#define NR_IRQS                                        (IRQ_VIC_END + VIRTUAL_IRQS)
 
 #endif /* __MACH_IRQS_H */

diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a0..179e457 100644 (file)
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,9 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #define MISC_BASE              IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR            (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR           (MISC_BASE + 0x004)
-#define PLL1_CTR               (MISC_BASE + 0x008)
-#define PLL1_FRQ               (MISC_BASE + 0x00C)
-#define PLL1_MOD               (MISC_BASE + 0x010)
-#define PLL2_CTR               (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE             2
-#define PLL_MODE_SHIFT         4
-#define PLL_MODE_MASK          0x3
-#define PLL_MODE_NORMAL                0
-#define PLL_MODE_FRACTION      1
-#define PLL_MODE_DITH_DSB      2
-#define PLL_MODE_DITH_SSB      3
-
-#define PLL2_FRQ               (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT                0
-#define PLL_DIV_N_MASK         0xFF
-#define PLL_DIV_P_SHIFT                8
-#define PLL_DIV_P_MASK         0x7
-#define PLL_NORM_FDBK_M_SHIFT  24
-#define PLL_NORM_FDBK_M_MASK   0xFF
-#define PLL_DITH_FDBK_M_SHIFT  16
-#define PLL_DITH_FDBK_M_MASK   0xFFFF
-
-#define PLL2_MOD               (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG            (MISC_BASE + 0x020)
-#define CORE_CLK_CFG           (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT   10
-#define PLL_HCLK_RATIO_MASK    0x3
-#define HCLK_PCLK_RATIO_SHIFT  8
-#define HCLK_PCLK_RATIO_MASK   0x3
-
-#define PERIP_CLK_CFG          (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define CLCD_CLK_SHIFT         2
-#define CLCD_CLK_MASK          0x3
-#define UART_CLK_SHIFT         4
-#define UART_CLK_MASK          0x1
-#define FIRDA_CLK_SHIFT                5
-#define FIRDA_CLK_MASK         0x3
-#define GPT0_CLK_SHIFT         8
-#define GPT1_CLK_SHIFT         10
-#define GPT2_CLK_SHIFT         11
-#define GPT3_CLK_SHIFT         12
-#define GPT_CLK_MASK           0x1
-#define AUX_CLK_PLL3_VAL       0
-#define AUX_CLK_PLL1_VAL       1
-
-#define PERIP1_CLK_ENB         (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART0_CLK_ENB          3
-#define UART1_CLK_ENB          4
-#define SSP0_CLK_ENB           5
-#define SSP1_CLK_ENB           6
-#define I2C_CLK_ENB            7
-#define JPEG_CLK_ENB           8
-#define FSMC_CLK_ENB           9
-#define FIRDA_CLK_ENB          10
-#define GPT2_CLK_ENB           11
-#define GPT3_CLK_ENB           12
-#define GPIO2_CLK_ENB          13
-#define SSP2_CLK_ENB           14
-#define ADC_CLK_ENB            15
-#define GPT1_CLK_ENB           11
-#define RTC_CLK_ENB            17
-#define GPIO1_CLK_ENB          18
-#define DMA_CLK_ENB            19
-#define SMI_CLK_ENB            21
-#define CLCD_CLK_ENB           22
-#define GMAC_CLK_ENB           23
-#define USBD_CLK_ENB           24
-#define USBH0_CLK_ENB          25
-#define USBH1_CLK_ENB          26
-
-#define SOC_CORE_ID            (MISC_BASE + 0x030)
-#define RAS_CLK_ENB            (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST         (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST           8
-
-#define SOC_USER_ID            (MISC_BASE + 0x03C)
-#define RAS_SOF_RST            (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG          (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG          (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG          (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT       0
-#define GPT_MSCALE_MASK                0xFFF
-#define GPT_NSCALE_SHIFT       12
-#define GPT_NSCALE_MASK                0xF
-
-#define AMEM_CLK_CFG           (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG           (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT          (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT         (MISC_BASE + 0x060)
-#define UART_CLK_SYNT          (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT          (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT          (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT          (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT          (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT          (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB           31
-#define AUX_EQ_SEL_SHIFT       30
-#define AUX_EQ_SEL_MASK                1
-#define AUX_EQ1_SEL            0
-#define AUX_EQ2_SEL            1
-#define AUX_XSCALE_SHIFT       16
-#define AUX_XSCALE_MASK                0xFFF
-#define AUX_YSCALE_SHIFT       0
-#define AUX_YSCALE_MASK                0xFFF
-
-#define ICM1_ARB_CFG           (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG           (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG           (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG           (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG           (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG           (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG           (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG           (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG           (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG            (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG           (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR           (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR           (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR          (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR          (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR          (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR          (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR           (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR           (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR           (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR           (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR                (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG       (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG       (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG                (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR                (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR          (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR          (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR          (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR          (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR          (MISC_BASE + 0x104)
-#define BIST1_STS_RES          (MISC_BASE + 0x108)
-#define BIST2_STS_RES          (MISC_BASE + 0x10C)
-#define BIST3_STS_RES          (MISC_BASE + 0x110)
-#define BIST4_STS_RES          (MISC_BASE + 0x114)
-#define BIST5_STS_RES          (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR         (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */

diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd6215..cb8ed2f 100644 (file)
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,25 @@
 #define __MACH_SPEAR6XX_H
 
 #include <asm/memory.h>
-#include <mach/spear600.h>
 
-#define SPEAR6XX_ML_SDRAM_BASE         UL(0x00000000)
 /* ICM1 - Low speed connection */
 #define SPEAR6XX_ICM1_BASE             UL(0xD0000000)
-
+#define VA_SPEAR6XX_ICM1_BASE          UL(0xFD000000)
 #define SPEAR6XX_ICM1_UART0_BASE       UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE    IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-
-#define SPEAR6XX_ICM1_UART1_BASE       UL(0xD0080000)
-#define SPEAR6XX_ICM1_SSP0_BASE                UL(0xD0100000)
-#define SPEAR6XX_ICM1_SSP1_BASE                UL(0xD0180000)
-#define SPEAR6XX_ICM1_I2C_BASE         UL(0xD0200000)
-#define SPEAR6XX_ICM1_JPEG_BASE                UL(0xD0800000)
-#define SPEAR6XX_ICM1_IRDA_BASE                UL(0xD1000000)
-#define SPEAR6XX_ICM1_FSMC_BASE                UL(0xD1800000)
-#define SPEAR6XX_ICM1_NAND_BASE                UL(0xD2000000)
-#define SPEAR6XX_ICM1_SRAM_BASE                UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE             UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR0_BASE                UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR1_BASE                UL(0xD8080000)
-#define SPEAR6XX_ICM2_GPIO_BASE                UL(0xD8100000)
-#define SPEAR6XX_ICM2_SSP2_BASE                UL(0xD8180000)
-#define SPEAR6XX_ICM2_ADC_BASE         UL(0xD8200000)
+#define VA_SPEAR6XX_ICM1_UART0_BASE    (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
 
 /* ML-1, 2 - Multi Layer CPU Subsystem */
 #define SPEAR6XX_ML_CPU_BASE           UL(0xF0000000)
-#define SPEAR6XX_CPU_TMR_BASE          UL(0xF0000000)
-#define SPEAR6XX_CPU_GPIO_BASE         UL(0xF0100000)
-#define SPEAR6XX_CPU_VIC_SEC_BASE      UL(0xF1000000)
-#define VA_SPEAR6XX_CPU_VIC_SEC_BASE   IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_BASE      UL(0xF1100000)
-#define VA_SPEAR6XX_CPU_VIC_PRI_BASE   IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE                UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE             UL(0xF8000000)
-#define SPEAR6XX_ICM3_SMEM_BASE                UL(0xF8000000)
 #define SPEAR6XX_ICM3_SMI_CTRL_BASE    UL(0xFC000000)
-#define SPEAR6XX_ICM3_CLCD_BASE                UL(0xFC200000)
+#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
 #define SPEAR6XX_ICM3_DMA_BASE         UL(0xFC400000)
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE  UL(0xFC600000)
-#define SPEAR6XX_ICM3_TMR_BASE         UL(0xFC800000)
-#define SPEAR6XX_ICM3_WDT_BASE         UL(0xFC880000)
-#define SPEAR6XX_ICM3_RTC_BASE         UL(0xFC900000)
-#define SPEAR6XX_ICM3_GPIO_BASE                UL(0xFC980000)
 #define SPEAR6XX_ICM3_SYS_CTRL_BASE    UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR6XX_ICM3_MISC_REG_BASE    UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE             UL(0xE0000000)
-#define SPEAR6XX_ICM4_GMAC_BASE                UL(0xE0800000)
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE   UL(0xE1000000)
-#define SPEAR6XX_ICM4_USBD_CSR_BASE    UL(0xE1100000)
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE   UL(0xE1200000)
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE   UL(0xE1800000)
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE   UL(0xE1900000)
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE   UL(0xE2000000)
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE   UL(0xE2100000)
-#define SPEAR6XX_ICM4_USB_ARB_BASE     UL(0xE2800000)
+#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE            SPEAR6XX_ICM1_UART0_BASE

diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644 (file)
index c068cc5..0000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-spear66xx/include/mach/spear600.h
- *
- * SPEAr600 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef CONFIG_MACH_SPEAR600
-
-#ifndef __MACH_SPEAR600_H
-#define __MACH_SPEAR600_H
-
-#endif /* __MACH_SPEAR600_H */
-
-#endif /* CONFIG_MACH_SPEAR600 */

diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14..2e2e359 100644 (file)
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,41 +13,404 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
-/* Following will create static virtual/physical mappings */
-static struct map_desc spear6xx_io_desc[] __initdata = {
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
        {
-               .virtual        = VA_SPEAR6XX_ICM1_UART0_BASE,
-               .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE
+               .bus_id = "ssp1_rx",
+               .min_signal = 0,
+               .max_signal = 0,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
        }, {
-               .virtual        = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
-               .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE
+               .bus_id = "ssp1_tx",
+               .min_signal = 1,
+               .max_signal = 1,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
        }, {
-               .virtual        = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
-               .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE
+               .bus_id = "uart0_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart0_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart1_rx",
+               .min_signal = 4,
+               .max_signal = 4,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "uart1_tx",
+               .min_signal = 5,
+               .max_signal = 5,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp2_rx",
+               .min_signal = 6,
+               .max_signal = 6,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ssp2_tx",
+               .min_signal = 7,
+               .max_signal = 7,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ssp0_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ssp0_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "i2c_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "i2c_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "irda",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "adc",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "to_jpeg",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "from_jpeg",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 0,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras0_rx",
+               .min_signal = 0,
+               .max_signal = 0,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras0_tx",
+               .min_signal = 1,
+               .max_signal = 1,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras1_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras1_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras2_rx",
+               .min_signal = 4,
+               .max_signal = 4,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras2_tx",
+               .min_signal = 5,
+               .max_signal = 5,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras3_rx",
+               .min_signal = 6,
+               .max_signal = 6,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras3_tx",
+               .min_signal = 7,
+               .max_signal = 7,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras4_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras4_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras5_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras5_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras6_rx",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras6_tx",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras7_rx",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
+       }, {
+               .bus_id = "ras7_tx",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 1,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB1,
        }, {
-               .virtual        = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
-               .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
-               .length         = SZ_4K,
+               .bus_id = "ext0_rx",
+               .min_signal = 0,
+               .max_signal = 0,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext0_tx",
+               .min_signal = 1,
+               .max_signal = 1,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext1_rx",
+               .min_signal = 2,
+               .max_signal = 2,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext1_tx",
+               .min_signal = 3,
+               .max_signal = 3,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext2_rx",
+               .min_signal = 4,
+               .max_signal = 4,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext2_tx",
+               .min_signal = 5,
+               .max_signal = 5,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext3_rx",
+               .min_signal = 6,
+               .max_signal = 6,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext3_tx",
+               .min_signal = 7,
+               .max_signal = 7,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext4_rx",
+               .min_signal = 8,
+               .max_signal = 8,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext4_tx",
+               .min_signal = 9,
+               .max_signal = 9,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext5_rx",
+               .min_signal = 10,
+               .max_signal = 10,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext5_tx",
+               .min_signal = 11,
+               .max_signal = 11,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext6_rx",
+               .min_signal = 12,
+               .max_signal = 12,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext6_tx",
+               .min_signal = 13,
+               .max_signal = 13,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext7_rx",
+               .min_signal = 14,
+               .max_signal = 14,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       }, {
+               .bus_id = "ext7_tx",
+               .min_signal = 15,
+               .max_signal = 15,
+               .muxval = 2,
+               .cctl = 0,
+               .periph_buses = PL08X_AHB2,
+       },
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+       .memcpy_channel = {
+               .bus_id = "memcpy",
+               .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                       PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                       PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                       PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                       PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                       PL080_CONTROL_PROT_SYS),
+       },
+       .lli_buses = PL08X_AHB1,
+       .mem_buses = PL08X_AHB1,
+       .get_signal = pl080_get_signal,
+       .put_signal = pl080_put_signal,
+       .slave_channels = spear600_dma_info,
+       .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL            VIRTUAL
+ * 0xF0000000          0xF0000000
+ * 0xF1000000          0xF1000000
+ * 0xD0000000          0xFD000000
+ * 0xFC000000          0xFC000000
+ */
+struct map_desc spear6xx_io_desc[] __initdata = {
+       {
+               .virtual        = VA_SPEAR6XX_ML_CPU_BASE,
+               .pfn            = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+               .length         = 2 * SZ_16M,
+               .type           = MT_DEVICE
+       },      {
+               .virtual        = VA_SPEAR6XX_ICM1_BASE,
+               .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+               .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-               .virtual        = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
-               .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
-               .length         = SZ_4K,
+               .virtual        = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
+               .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
+               .length         = SZ_16M,
                .type           = MT_DEVICE
        },
 };
@@ -56,9 +419,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
 void __init spear6xx_map_io(void)
 {
        iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
-
-       /* This will initialize clock framework */
-       spear6xx_clk_init();
 }
 
 static void __init spear6xx_timer_init(void)
@@ -66,6 +426,8 @@ static void __init spear6xx_timer_init(void)
        char pclk_name[] = "pll3_48m_clk";
        struct clk *gpt_clk, *pclk;
 
+       spear6xx_clk_init();
+
        /* get the system timer clock */
        gpt_clk = clk_get_sys("gpt0", NULL);
        if (IS_ERR(gpt_clk)) {
@@ -85,16 +447,24 @@ static void __init spear6xx_timer_init(void)
        clk_put(gpt_clk);
        clk_put(pclk);
 
-       spear_setup_timer();
+       spear_setup_of_timer();
 }
 
 struct sys_timer spear6xx_timer = {
        .init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+       OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+                       &pl080_plat_data),
+       {}
+};
+
 static void __init spear600_dt_init(void)
 {
-       of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+       of_platform_populate(NULL, of_default_bus_match_table,
+                       spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 1621ad0..3333974 100644 (file)
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
 
        for (i = 0; i < U300_VIC_IRQS_END; i++)
                set_bit(i, (unsigned long *) &mask[0]);
-       vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
-       vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
+       vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
+                mask[0], mask[0]);
+       vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
+                mask[1], mask[1]);
 }
 
 

diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index a38f802..cb04bd6 100644 (file)
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                .min_uV = 1800000,
                                .max_uV = 1800000,
                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                               .valid_ops_mask =
-                               REGULATOR_CHANGE_VOLTAGE |
-                               REGULATOR_CHANGE_STATUS,
                                .always_on = 1,
                                .boot_on = 1,
                        },
@@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                .min_uV = 2500000,
                                .max_uV = 2500000,
                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                               .valid_ops_mask =
-                               REGULATOR_CHANGE_VOLTAGE |
-                               REGULATOR_CHANGE_STATUS,
                                .always_on = 1,
                                .boot_on = 1,
                        },
@@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                .max_uV = 1800000,
                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
                                .valid_ops_mask =
-                               REGULATOR_CHANGE_VOLTAGE |
-                               REGULATOR_CHANGE_STATUS,
+                               REGULATOR_CHANGE_VOLTAGE,
                                .always_on = 1,
                                .boot_on = 1,
                        },

diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ee78a26..ec09c1e 100644 (file)
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -12,101 +12,101 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-#define IRQ_U300_INTCON0_START         0
-#define IRQ_U300_INTCON1_START         32
+#define IRQ_U300_INTCON0_START         1
+#define IRQ_U300_INTCON1_START         33
 /* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT              0
-#define IRQ_U300_IRQ1_EXT              1
-#define IRQ_U300_DMA                   2
-#define IRQ_U300_VIDEO_ENC_0           3
-#define IRQ_U300_VIDEO_ENC_1           4
-#define IRQ_U300_AAIF_RX               5
-#define IRQ_U300_AAIF_TX               6
-#define IRQ_U300_AAIF_VGPIO            7
-#define IRQ_U300_AAIF_WAKEUP           8
-#define IRQ_U300_PCM_I2S0_FRAME                9
-#define IRQ_U300_PCM_I2S0_FIFO         10
-#define IRQ_U300_PCM_I2S1_FRAME                11
-#define IRQ_U300_PCM_I2S1_FIFO         12
-#define IRQ_U300_XGAM_GAMCON           13
-#define IRQ_U300_XGAM_CDI              14
-#define IRQ_U300_XGAM_CDICON           15
+#define IRQ_U300_IRQ0_EXT              1
+#define IRQ_U300_IRQ1_EXT              2
+#define IRQ_U300_DMA                   3
+#define IRQ_U300_VIDEO_ENC_0           4
+#define IRQ_U300_VIDEO_ENC_1           5
+#define IRQ_U300_AAIF_RX               6
+#define IRQ_U300_AAIF_TX               7
+#define IRQ_U300_AAIF_VGPIO            8
+#define IRQ_U300_AAIF_WAKEUP           9
+#define IRQ_U300_PCM_I2S0_FRAME                10
+#define IRQ_U300_PCM_I2S0_FIFO         11
+#define IRQ_U300_PCM_I2S1_FRAME                12
+#define IRQ_U300_PCM_I2S1_FIFO         13
+#define IRQ_U300_XGAM_GAMCON           14
+#define IRQ_U300_XGAM_CDI              15
+#define IRQ_U300_XGAM_CDICON           16
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
 /* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC           16
+#define IRQ_U300_XGAM_MMIACC           17
 #endif
-#define IRQ_U300_XGAM_PDI              17
-#define IRQ_U300_XGAM_PDICON           18
-#define IRQ_U300_XGAM_GAMEACC          19
-#define IRQ_U300_XGAM_MCIDCT           20
-#define IRQ_U300_APEX                  21
-#define IRQ_U300_UART0                 22
-#define IRQ_U300_SPI                   23
-#define IRQ_U300_TIMER_APP_OS          24
-#define IRQ_U300_TIMER_APP_DD          25
-#define IRQ_U300_TIMER_APP_GP1         26
-#define IRQ_U300_TIMER_APP_GP2         27
-#define IRQ_U300_TIMER_OS              28
-#define IRQ_U300_TIMER_MS              29
-#define IRQ_U300_KEYPAD_KEYBF          30
-#define IRQ_U300_KEYPAD_KEYBR          31
+#define IRQ_U300_XGAM_PDI              18
+#define IRQ_U300_XGAM_PDICON           19
+#define IRQ_U300_XGAM_GAMEACC          20
+#define IRQ_U300_XGAM_MCIDCT           21
+#define IRQ_U300_APEX                  22
+#define IRQ_U300_UART0                 23
+#define IRQ_U300_SPI                   24
+#define IRQ_U300_TIMER_APP_OS          25
+#define IRQ_U300_TIMER_APP_DD          26
+#define IRQ_U300_TIMER_APP_GP1         27
+#define IRQ_U300_TIMER_APP_GP2         28
+#define IRQ_U300_TIMER_OS              29
+#define IRQ_U300_TIMER_MS              30
+#define IRQ_U300_KEYPAD_KEYBF          31
+#define IRQ_U300_KEYPAD_KEYBR          32
 /* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0            32
-#define IRQ_U300_GPIO_PORT1            33
-#define IRQ_U300_GPIO_PORT2            34
+#define IRQ_U300_GPIO_PORT0            33
+#define IRQ_U300_GPIO_PORT1            34
+#define IRQ_U300_GPIO_PORT2            35
 
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
     defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                  35
-#define IRQ_U300_EVHIST                        36
-#define IRQ_U300_MSPRO                 37
-#define IRQ_U300_MMCSD_MCIINTR0                38
-#define IRQ_U300_MMCSD_MCIINTR1                39
-#define IRQ_U300_I2C0                  40
-#define IRQ_U300_I2C1                  41
-#define IRQ_U300_RTC                   42
-#define IRQ_U300_NFIF                  43
-#define IRQ_U300_NFIF2                 44
+#define IRQ_U300_WDOG                  36
+#define IRQ_U300_EVHIST                        37
+#define IRQ_U300_MSPRO                 38
+#define IRQ_U300_MMCSD_MCIINTR0                39
+#define IRQ_U300_MMCSD_MCIINTR1                40
+#define IRQ_U300_I2C0                  41
+#define IRQ_U300_I2C1                  42
+#define IRQ_U300_RTC                   43
+#define IRQ_U300_NFIF                  44
+#define IRQ_U300_NFIF2                 45
 #endif
 
 /* DB3150 and DB3200 have only 45 IRQs */
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END              45
+#define U300_VIC_IRQS_END              46
 #endif
 
 /* The DB3350-specific interrupt lines */
 #ifdef CONFIG_MACH_U300_BS335
-#define IRQ_U300_ISP_F0                        45
-#define IRQ_U300_ISP_F1                        46
-#define IRQ_U300_ISP_F2                        47
-#define IRQ_U300_ISP_F3                        48
-#define IRQ_U300_ISP_F4                        49
-#define IRQ_U300_GPIO_PORT3            50
-#define IRQ_U300_SYSCON_PLL_LOCK       51
-#define IRQ_U300_UART1                 52
-#define IRQ_U300_GPIO_PORT4            53
-#define IRQ_U300_GPIO_PORT5            54
-#define IRQ_U300_GPIO_PORT6            55
-#define U300_VIC_IRQS_END              56
+#define IRQ_U300_ISP_F0                        46
+#define IRQ_U300_ISP_F1                        47
+#define IRQ_U300_ISP_F2                        48
+#define IRQ_U300_ISP_F3                        49
+#define IRQ_U300_ISP_F4                        50
+#define IRQ_U300_GPIO_PORT3            51
+#define IRQ_U300_SYSCON_PLL_LOCK       52
+#define IRQ_U300_UART1                 53
+#define IRQ_U300_GPIO_PORT4            54
+#define IRQ_U300_GPIO_PORT5            55
+#define IRQ_U300_GPIO_PORT6            56
+#define U300_VIC_IRQS_END              57
 #endif
 
 /* The DB3210-specific interrupt lines */
 #ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3            35
-#define IRQ_U300_GPIO_PORT4            36
-#define IRQ_U300_WDOG                  37
-#define IRQ_U300_EVHIST                        38
-#define IRQ_U300_MSPRO                 39
-#define IRQ_U300_MMCSD_MCIINTR0                40
-#define IRQ_U300_MMCSD_MCIINTR1                41
-#define IRQ_U300_I2C0                  42
-#define IRQ_U300_I2C1                  43
-#define IRQ_U300_RTC                   44
-#define IRQ_U300_NFIF                  45
-#define IRQ_U300_NFIF2                 46
-#define IRQ_U300_SYSCON_PLL_LOCK       47
-#define U300_VIC_IRQS_END              48
+#define IRQ_U300_GPIO_PORT3            36
+#define IRQ_U300_GPIO_PORT4            37
+#define IRQ_U300_WDOG                  38
+#define IRQ_U300_EVHIST                        39
+#define IRQ_U300_MSPRO                 40
+#define IRQ_U300_MMCSD_MCIINTR0                41
+#define IRQ_U300_MMCSD_MCIINTR1                42
+#define IRQ_U300_I2C0                  43
+#define IRQ_U300_I2C1                  44
+#define IRQ_U300_RTC                   45
+#define IRQ_U300_NFIF                  46
+#define IRQ_U300_NFIF2                 47
+#define IRQ_U300_SYSCON_PLL_LOCK       48
+#define U300_VIC_IRQS_END              49
 #endif
 
 /* Maximum 8*7 GPIO lines */
@@ -117,6 +117,6 @@
 #define IRQ_U300_GPIO_END              (U300_VIC_IRQS_END)
 #endif
 
-#define NR_IRQS                                (IRQ_U300_GPIO_END)
+#define NR_IRQS                                (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 
 #endif

diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c
index 2b2d51c..0127490 100644 (file)
--- a/arch/arm/mach-ux500/mbox-db5500.c
+++ b/arch/arm/mach-ux500/mbox-db5500.c
@@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev,
        return sprintf(buf, "0x%X\n", mbox_value);
 }
 
-static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
+static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
 
 static int mbox_show(struct seq_file *s, void *data)
 {

diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index ff1f7cc..8074199 100644 (file)
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
 /*
- * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
- * The test below covers all the write situations, including Java bytecodes
+ * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
  */
-       bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+#ifdef CONFIG_ARM_ERRATA_326103
+       ldr     ip, =0x4107b36
+       mrc     p15, 0, r3, c0, c0, 0           @ get processor id
+       teq     ip, r3, lsr #4                  @ r0 ARM1136?
+       bne     do_DataAbort
        tst     r5, #PSR_J_BIT                  @ Java?
+       tsteq   r5, #PSR_T_BIT                  @ Thumb?
        bne     do_DataAbort
-       do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
-       ldreq   r3, [r4]                        @ read aborted ARM instruction
+       bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+       ldr     r3, [r4]                        @ read aborted ARM instruction
 #ifdef CONFIG_CPU_ENDIAN_BE8
-       reveq   r3, r3
+       rev     r3, r3
 #endif
        do_ldrd_abort tmp=ip, insn=r3
        tst     r3, #1 << 20                    @ L = 0 -> write
        orreq   r1, r1, #1 << 11                @ yes.
+#endif
        b       do_DataAbort

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a53fd2a..2a8e380 100644 (file)
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -32,6 +32,7 @@ static void __iomem *l2x0_base;
 static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;      /* Bitmask of active ways */
 static u32 l2x0_size;
+static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -61,12 +62,7 @@ static inline void cache_sync(void)
 {
        void __iomem *base = l2x0_base;
 
-#ifdef CONFIG_PL310_ERRATA_753970
-       /* write to an unmmapped register */
-       writel_relaxed(0, base + L2X0_DUMMY_REG);
-#else
-       writel_relaxed(0, base + L2X0_CACHE_SYNC);
-#endif
+       writel_relaxed(0, base + sync_reg_offset);
        cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
@@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr)
 }
 
 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+static inline void debug_writel(unsigned long val)
+{
+       if (outer_cache.set_debug)
+               outer_cache.set_debug(val);
+}
 
-#define debug_writel(val)      outer_cache.set_debug(val)
-
-static void l2x0_set_debug(unsigned long val)
+static void pl310_set_debug(unsigned long val)
 {
        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
 }
@@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val)
 {
 }
 
-#define l2x0_set_debug NULL
+#define pl310_set_debug        NULL
 #endif
 
 #ifdef CONFIG_PL310_ERRATA_588369
@@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                else
                        ways = 8;
                type = "L310";
+#ifdef CONFIG_PL310_ERRATA_753970
+               /* Unmapped register. */
+               sync_reg_offset = L2X0_DUMMY_REG;
+#endif
+               outer_cache.set_debug = pl310_set_debug;
                break;
        case L2X0_CACHE_ID_PART_L210:
                ways = (aux >> 13) & 0xf;
@@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
        outer_cache.flush_all = l2x0_flush_all;
        outer_cache.inv_all = l2x0_inv_all;
        outer_cache.disable = l2x0_disable;
-       outer_cache.set_debug = l2x0_set_debug;
 
        printk(KERN_INFO "%s cache controller enabled\n", type);
        printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 595079f..8f5813b 100644 (file)
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -293,11 +293,11 @@ EXPORT_SYMBOL(pfn_valid);
 #endif
 
 #ifndef CONFIG_SPARSEMEM
-static void arm_memory_present(void)
+static void __init arm_memory_present(void)
 {
 }
 #else
-static void arm_memory_present(void)
+static void __init arm_memory_present(void)
 {
        struct memblock_region *reg;
 

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index b86f893..2c7cf2f 100644 (file)
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -618,8 +618,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
        }
 }
 
-static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
-       unsigned long phys, const struct mem_type *type)
+static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
+       unsigned long end, unsigned long phys, const struct mem_type *type)
 {
        pud_t *pud = pud_offset(pgd, addr);
        unsigned long next;

diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 2ed3ab1..5079787 100644 (file)
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -41,6 +41,7 @@
 #include <mach/clock.h>
 #include <mach/hardware.h>
 
+#ifndef CONFIG_COMMON_CLK
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 
@@ -200,6 +201,16 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
+#else
+
+/*
+ * Lock to protect the clock module (ccm) registers. Used
+ * on all i.MXs
+ */
+DEFINE_SPINLOCK(imx_ccm_lock);
+
+#endif /* CONFIG_COMMON_CLK */
+
 /*
  * Get the resulting clock rate from a PLL register value and the input
  * frequency. PLLs with this register layout can at least be found on

diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 753a598..bd940c7 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -23,6 +23,7 @@
 #ifndef __ASSEMBLY__
 #include <linux/list.h>
 
+#ifndef CONFIG_COMMON_CLK
 struct module;
 
 struct clk {
@@ -59,6 +60,9 @@ struct clk {
 
 int clk_register(struct clk *clk);
 void clk_unregister(struct clk *clk);
+#endif /* CONFIG_COMMON_CLK */
+
+extern spinlock_t imx_ccm_lock;
 
 unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
 

diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 7daf7c9..99f958c 100644 (file)
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -25,6 +25,7 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/err.h>
 
 #include <mach/hardware.h>
 #include <asm/sched_clock.h>
@@ -282,6 +283,19 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
        uint32_t tctl_val;
+       struct clk *timer_ipg_clk;
+
+       if (!timer_clk) {
+               timer_clk = clk_get_sys("imx-gpt.0", "per");
+               if (IS_ERR(timer_clk)) {
+                       pr_err("i.MX timer: unable to get clk\n");
+                       return;
+               }
+
+               timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
+               if (!IS_ERR(timer_ipg_clk))
+                       clk_prepare_enable(timer_ipg_clk);
+       }
 
        clk_prepare_enable(timer_clk);
 

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index ecdb3da..c58d896 100644 (file)
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -916,6 +916,13 @@ void omap_start_dma(int lch)
                        l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
        l |= OMAP_DMA_CCR_EN;
 
+       /*
+        * As dma_write() uses IO accessors which are weakly ordered, there
+        * is no guarantee that data in coherent DMA memory will be visible
+        * to the DMA device.  Add a memory barrier here to ensure that any
+        * such data is visible prior to enabling DMA.
+        */
+       mb();
        p->dma_write(l, CCR, lch);
 
        dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
@@ -965,6 +972,13 @@ void omap_stop_dma(int lch)
                p->dma_write(l, CCR, lch);
        }
 
+       /*
+        * Ensure that data transferred by DMA is visible to any access
+        * after DMA has been disabled.  This is important for coherent
+        * DMA regions.
+        */
+       mb();
+
        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                int next_lch, cur_lch = lch;
                char dma_chan_link_map[dma_lch_count];

diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 317e246..e834c5e 100644 (file)
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -18,6 +18,8 @@
 #ifndef __PLAT_S3C_SDHCI_H
 #define __PLAT_S3C_SDHCI_H __FILE__
 
+#include <plat/devs.h>
+
 struct platform_device;
 struct mmc_host;
 struct mmc_card;
@@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
 
 #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
 
+static inline void s3c_sdhci_setname(int id, char *name)
+{
+       switch (id) {
+#ifdef CONFIG_S3C_DEV_HSMMC
+       case 0:
+               s3c_device_hsmmc0.name = name;
+               break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+       case 1:
+               s3c_device_hsmmc1.name = name;
+               break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+       case 2:
+               s3c_device_hsmmc2.name = name;
+               break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+       case 3:
+               s3c_device_hsmmc3.name = name;
+               break;
+#endif
+       }
+}
+
 #endif /* __PLAT_S3C_SDHCI_H */

diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbc..387655b 100644 (file)
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -9,9 +9,11 @@ choice
        default ARCH_SPEAR3XX
 
 config ARCH_SPEAR3XX
-       bool "SPEAr3XX"
+       bool "ST SPEAr3xx with Device Tree"
        select ARM_VIC
        select CPU_ARM926T
+       select USE_OF
+       select PINCTRL
        help
          Supports for ARM's SPEAR3XX family
 

diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b..38f1235 100644 (file)
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
 #
 
 # Common support
-obj-y  := clock.o restart.o time.o
+obj-y  := restart.o time.o pl080.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)    += shirq.o padmux.o
+obj-$(CONFIG_ARCH_SPEAR3XX)    += shirq.o

diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
deleted file mode 100644 (file)
index 67dd003..0000000
--- a/arch/arm/plat-spear/clock.c
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
- * arch/arm/plat-spear/clock.c
- *
- * Clock framework for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/bug.h>
-#include <linux/clk.h>
-#include <linux/debugfs.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <plat/clock.h>
-
-static DEFINE_SPINLOCK(clocks_lock);
-static LIST_HEAD(root_clks);
-#ifdef CONFIG_DEBUG_FS
-static LIST_HEAD(clocks);
-#endif
-
-static void propagate_rate(struct clk *, int on_init);
-#ifdef CONFIG_DEBUG_FS
-static int clk_debugfs_reparent(struct clk *);
-#endif
-
-static int generic_clk_enable(struct clk *clk)
-{
-       unsigned int val;
-
-       if (!clk->en_reg)
-               return -EFAULT;
-
-       val = readl(clk->en_reg);
-       if (unlikely(clk->flags & RESET_TO_ENABLE))
-               val &= ~(1 << clk->en_reg_bit);
-       else
-               val |= 1 << clk->en_reg_bit;
-
-       writel(val, clk->en_reg);
-
-       return 0;
-}
-
-static void generic_clk_disable(struct clk *clk)
-{
-       unsigned int val;
-
-       if (!clk->en_reg)
-               return;
-
-       val = readl(clk->en_reg);
-       if (unlikely(clk->flags & RESET_TO_ENABLE))
-               val |= 1 << clk->en_reg_bit;
-       else
-               val &= ~(1 << clk->en_reg_bit);
-
-       writel(val, clk->en_reg);
-}
-
-/* generic clk ops */
-static struct clkops generic_clkops = {
-       .enable = generic_clk_enable,
-       .disable = generic_clk_disable,
-};
-
-/* returns current programmed clocks clock info structure */
-static struct pclk_info *pclk_info_get(struct clk *clk)
-{
-       unsigned int val, i;
-       struct pclk_info *info = NULL;
-
-       val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
-               & clk->pclk_sel->pclk_sel_mask;
-
-       for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
-               if (clk->pclk_sel->pclk_info[i].pclk_val == val)
-                       info = &clk->pclk_sel->pclk_info[i];
-       }
-
-       return info;
-}
-
-/*
- * Set Update pclk, and pclk_info of clk and add clock sibling node to current
- * parents children list
- */
-static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&clocks_lock, flags);
-       list_del(&clk->sibling);
-       list_add(&clk->sibling, &pclk_info->pclk->children);
-
-       clk->pclk = pclk_info->pclk;
-       spin_unlock_irqrestore(&clocks_lock, flags);
-
-#ifdef CONFIG_DEBUG_FS
-       clk_debugfs_reparent(clk);
-#endif
-}
-
-static void do_clk_disable(struct clk *clk)
-{
-       if (!clk)
-               return;
-
-       if (!clk->usage_count) {
-               WARN_ON(1);
-               return;
-       }
-
-       clk->usage_count--;
-
-       if (clk->usage_count == 0) {
-               /*
-                * Surely, there are no active childrens or direct users
-                * of this clock
-                */
-               if (clk->pclk)
-                       do_clk_disable(clk->pclk);
-
-               if (clk->ops && clk->ops->disable)
-                       clk->ops->disable(clk);
-       }
-}
-
-static int do_clk_enable(struct clk *clk)
-{
-       int ret = 0;
-
-       if (!clk)
-               return -EFAULT;
-
-       if (clk->usage_count == 0) {
-               if (clk->pclk) {
-                       ret = do_clk_enable(clk->pclk);
-                       if (ret)
-                               goto err;
-               }
-               if (clk->ops && clk->ops->enable) {
-                       ret = clk->ops->enable(clk);
-                       if (ret) {
-                               if (clk->pclk)
-                                       do_clk_disable(clk->pclk);
-                               goto err;
-                       }
-               }
-               /*
-                * Since the clock is going to be used for the first
-                * time please reclac
-                */
-               if (clk->recalc) {
-                       ret = clk->recalc(clk);
-                       if (ret)
-                               goto err;
-               }
-       }
-       clk->usage_count++;
-err:
-       return ret;
-}
-
-/*
- * clk_enable - inform the system when the clock source should be running.
- * @clk: clock source
- *
- * If the clock can not be enabled/disabled, this should return success.
- *
- * Returns success (0) or negative errno.
- */
-int clk_enable(struct clk *clk)
-{
-       unsigned long flags;
-       int ret = 0;
-
-       spin_lock_irqsave(&clocks_lock, flags);
-       ret = do_clk_enable(clk);
-       spin_unlock_irqrestore(&clocks_lock, flags);
-       return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-/*
- * clk_disable - inform the system when the clock source is no longer required.
- * @clk: clock source
- *
- * Inform the system that a clock source is no longer required by
- * a driver and may be shut down.
- *
- * Implementation detail: if the clock source is shared between
- * multiple drivers, clk_enable() calls must be balanced by the
- * same number of clk_disable() calls for the clock source to be
- * disabled.
- */
-void clk_disable(struct clk *clk)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&clocks_lock, flags);
-       do_clk_disable(clk);
-       spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/**
- * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
- *              This is only valid once the clock source has been enabled.
- * @clk: clock source
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-       unsigned long flags, rate;
-
-       spin_lock_irqsave(&clocks_lock, flags);
-       rate = clk->rate;
-       spin_unlock_irqrestore(&clocks_lock, flags);
-
-       return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/**
- * clk_set_parent - set the parent clock source for this clock
- * @clk: clock source
- * @parent: parent clock source
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-       int i, found = 0, val = 0;
-       unsigned long flags;
-
-       if (!clk || !parent)
-               return -EFAULT;
-       if (clk->pclk == parent)
-               return 0;
-       if (!clk->pclk_sel)
-               return -EPERM;
-
-       /* check if requested parent is in clk parent list */
-       for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
-               if (clk->pclk_sel->pclk_info[i].pclk == parent) {
-                       found = 1;
-                       break;
-               }
-       }
-
-       if (!found)
-               return -EINVAL;
-
-       spin_lock_irqsave(&clocks_lock, flags);
-       /* reflect parent change in hardware */
-       val = readl(clk->pclk_sel->pclk_sel_reg);
-       val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
-       val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift;
-       writel(val, clk->pclk_sel->pclk_sel_reg);
-       spin_unlock_irqrestore(&clocks_lock, flags);
-
-       /* reflect parent change in software */
-       clk_reparent(clk, &clk->pclk_sel->pclk_info[i]);
-
-       propagate_rate(clk, 0);
-       return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/**
- * clk_set_rate - set the clock rate for a clock source
- * @clk: clock source
- * @rate: desired clock rate in Hz
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-       unsigned long flags;
-       int ret = -EINVAL;
-
-       if (!clk || !rate)
-               return -EFAULT;
-
-       if (clk->set_rate) {
-               spin_lock_irqsave(&clocks_lock, flags);
-               ret = clk->set_rate(clk, rate);
-               if (!ret)
-                       /* if successful -> propagate */
-                       propagate_rate(clk, 0);
-               spin_unlock_irqrestore(&clocks_lock, flags);
-       } else if (clk->pclk) {
-               u32 mult = clk->div_factor ? clk->div_factor : 1;
-               ret = clk_set_rate(clk->pclk, mult * rate);
-       }
-
-       return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/* registers clock in platform clock framework */
-void clk_register(struct clk_lookup *cl)
-{
-       struct clk *clk;
-       unsigned long flags;
-
-       if (!cl || !cl->clk)
-               return;
-       clk = cl->clk;
-
-       spin_lock_irqsave(&clocks_lock, flags);
-
-       INIT_LIST_HEAD(&clk->children);
-       if (clk->flags & ALWAYS_ENABLED)
-               clk->ops = NULL;
-       else if (!clk->ops)
-               clk->ops = &generic_clkops;
-
-       /* root clock don't have any parents */
-       if (!clk->pclk && !clk->pclk_sel) {
-               list_add(&clk->sibling, &root_clks);
-       } else if (clk->pclk && !clk->pclk_sel) {
-               /* add clocks with only one parent to parent's children list */
-               list_add(&clk->sibling, &clk->pclk->children);
-       } else {
-               /* clocks with more than one parent */
-               struct pclk_info *pclk_info;
-
-               pclk_info = pclk_info_get(clk);
-               if (!pclk_info) {
-                       pr_err("CLKDEV: invalid pclk info of clk with"
-                                       " %s dev_id and %s con_id\n",
-                                       cl->dev_id, cl->con_id);
-               } else {
-                       clk->pclk = pclk_info->pclk;
-                       list_add(&clk->sibling, &pclk_info->pclk->children);
-               }
-       }
-
-       spin_unlock_irqrestore(&clocks_lock, flags);
-
-       /* debugfs specific */
-#ifdef CONFIG_DEBUG_FS
-       list_add(&clk->node, &clocks);
-       clk->cl = cl;
-#endif
-
-       /* add clock to arm clockdev framework */
-       clkdev_add(cl);
-}
-
-/**
- * propagate_rate - recalculate and propagate all clocks to children
- * @pclk: parent clock required to be propogated
- * @on_init: flag for enabling clocks which are ENABLED_ON_INIT.
- *
- * Recalculates all children clocks
- */
-void propagate_rate(struct clk *pclk, int on_init)
-{
-       struct clk *clk, *_temp;
-       int ret = 0;
-
-       list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) {
-               if (clk->recalc) {
-                       ret = clk->recalc(clk);
-                       /*
-                        * recalc will return error if clk out is not programmed
-                        * In this case configure default rate.
-                        */
-                       if (ret && clk->set_rate)
-                               clk->set_rate(clk, 0);
-               }
-               propagate_rate(clk, on_init);
-
-               if (!on_init)
-                       continue;
-
-               /* Enable clks enabled on init, in software view */
-               if (clk->flags & ENABLED_ON_INIT)
-                       do_clk_enable(clk);
-       }
-}
-
-/**
- * round_rate_index - return closest programmable rate index in rate_config tbl
- * @clk: ptr to clock structure
- * @drate: desired rate
- * @rate: final rate will be returned in this variable only.
- *
- * Finds index in rate_config for highest clk rate which is less than
- * requested rate. If there is no clk rate lesser than requested rate then
- * -EINVAL is returned. This routine assumes that rate_config is written
- * in incrementing order of clk rates.
- * If drate passed is zero then default rate is programmed.
- */
-static int
-round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate)
-{
-       unsigned long tmp = 0, prev_rate = 0;
-       int index;
-
-       if (!clk->calc_rate)
-               return -EFAULT;
-
-       if (!drate)
-               return -EINVAL;
-
-       /*
-        * This loops ends on two conditions:
-        * - as soon as clk is found with rate greater than requested rate.
-        * - if all clks in rate_config are smaller than requested rate.
-        */
-       for (index = 0; index < clk->rate_config.count; index++) {
-               prev_rate = tmp;
-               tmp = clk->calc_rate(clk, index);
-               if (drate < tmp) {
-                       index--;
-                       break;
-               }
-       }
-       /* return if can't find suitable clock */
-       if (index < 0) {
-               index = -EINVAL;
-               *rate = 0;
-       } else if (index == clk->rate_config.count) {
-               /* program with highest clk rate possible */
-               index = clk->rate_config.count - 1;
-               *rate = tmp;
-       } else
-               *rate = prev_rate;
-
-       return index;
-}
-
-/**
- * clk_round_rate - adjust a rate to the exact rate a clock can provide
- * @clk: clock source
- * @rate: desired clock rate in Hz
- *
- * Returns rounded clock rate in Hz, or negative errno.
- */
-long clk_round_rate(struct clk *clk, unsigned long drate)
-{
-       long rate = 0;
-       int index;
-
-       /*
-        * propagate call to parent who supports calc_rate. Similar approach is
-        * used in clk_set_rate.
-        */
-       if (!clk->calc_rate) {
-               u32 mult;
-               if (!clk->pclk)
-                       return clk->rate;
-
-               mult = clk->div_factor ? clk->div_factor : 1;
-               return clk_round_rate(clk->pclk, mult * drate) / mult;
-       }
-
-       index = round_rate_index(clk, drate, &rate);
-       if (index >= 0)
-               return rate;
-       else
-               return index;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/*All below functions are called with lock held */
-
-/*
- * Calculates pll clk rate for specific value of mode, m, n and p
- *
- * In normal mode
- * rate = (2 * M[15:8] * Fin)/(N * 2^P)
- *
- * In Dithered mode
- * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
- */
-unsigned long pll_calc_rate(struct clk *clk, int index)
-{
-       unsigned long rate = clk->pclk->rate;
-       struct pll_rate_tbl *tbls = clk->rate_config.tbls;
-       unsigned int mode;
-
-       mode = tbls[index].mode ? 256 : 1;
-       return (((2 * rate / 10000) * tbls[index].m) /
-                       (mode * tbls[index].n * (1 << tbls[index].p))) * 10000;
-}
-
-/*
- * calculates current programmed rate of pll1
- *
- * In normal mode
- * rate = (2 * M[15:8] * Fin)/(N * 2^P)
- *
- * In Dithered mode
- * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
- */
-int pll_clk_recalc(struct clk *clk)
-{
-       struct pll_clk_config *config = clk->private_data;
-       unsigned int num = 2, den = 0, val, mode = 0;
-
-       mode = (readl(config->mode_reg) >> config->masks->mode_shift) &
-               config->masks->mode_mask;
-
-       val = readl(config->cfg_reg);
-       /* calculate denominator */
-       den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask;
-       den = 1 << den;
-       den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask;
-
-       /* calculate numerator & denominator */
-       if (!mode) {
-               /* Normal mode */
-               num *= (val >> config->masks->norm_fdbk_m_shift) &
-                       config->masks->norm_fdbk_m_mask;
-       } else {
-               /* Dithered mode */
-               num *= (val >> config->masks->dith_fdbk_m_shift) &
-                       config->masks->dith_fdbk_m_mask;
-               den *= 256;
-       }
-
-       if (!den)
-               return -EINVAL;
-
-       clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
-       return 0;
-}
-
-/*
- * Configures new clock rate of pll
- */
-int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-       struct pll_rate_tbl *tbls = clk->rate_config.tbls;
-       struct pll_clk_config *config = clk->private_data;
-       unsigned long val, rate;
-       int i;
-
-       i = round_rate_index(clk, desired_rate, &rate);
-       if (i < 0)
-               return i;
-
-       val = readl(config->mode_reg) &
-               ~(config->masks->mode_mask << config->masks->mode_shift);
-       val |= (tbls[i].mode & config->masks->mode_mask) <<
-               config->masks->mode_shift;
-       writel(val, config->mode_reg);
-
-       val = readl(config->cfg_reg) &
-               ~(config->masks->div_p_mask << config->masks->div_p_shift);
-       val |= (tbls[i].p & config->masks->div_p_mask) <<
-               config->masks->div_p_shift;
-       val &= ~(config->masks->div_n_mask << config->masks->div_n_shift);
-       val |= (tbls[i].n & config->masks->div_n_mask) <<
-               config->masks->div_n_shift;
-       val &= ~(config->masks->dith_fdbk_m_mask <<
-                       config->masks->dith_fdbk_m_shift);
-       if (tbls[i].mode)
-               val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) <<
-                       config->masks->dith_fdbk_m_shift;
-       else
-               val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) <<
-                       config->masks->norm_fdbk_m_shift;
-
-       writel(val, config->cfg_reg);
-
-       clk->rate = rate;
-
-       return 0;
-}
-
-/*
- * Calculates ahb, apb clk rate for specific value of div
- */
-unsigned long bus_calc_rate(struct clk *clk, int index)
-{
-       unsigned long rate = clk->pclk->rate;
-       struct bus_rate_tbl *tbls = clk->rate_config.tbls;
-
-       return rate / (tbls[index].div + 1);
-}
-
-/* calculates current programmed rate of ahb or apb bus */
-int bus_clk_recalc(struct clk *clk)
-{
-       struct bus_clk_config *config = clk->private_data;
-       unsigned int div;
-
-       div = ((readl(config->reg) >> config->masks->shift) &
-                       config->masks->mask) + 1;
-
-       if (!div)
-               return -EINVAL;
-
-       clk->rate = (unsigned long)clk->pclk->rate / div;
-       return 0;
-}
-
-/* Configures new clock rate of AHB OR APB bus */
-int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-       struct bus_rate_tbl *tbls = clk->rate_config.tbls;
-       struct bus_clk_config *config = clk->private_data;
-       unsigned long val, rate;
-       int i;
-
-       i = round_rate_index(clk, desired_rate, &rate);
-       if (i < 0)
-               return i;
-
-       val = readl(config->reg) &
-               ~(config->masks->mask << config->masks->shift);
-       val |= (tbls[i].div & config->masks->mask) << config->masks->shift;
-       writel(val, config->reg);
-
-       clk->rate = rate;
-
-       return 0;
-}
-
-/*
- * gives rate for different values of eq, x and y
- *
- * Fout from synthesizer can be given from two equations:
- * Fout1 = (Fin * X/Y)/2               EQ1
- * Fout2 = Fin * X/Y                   EQ2
- */
-unsigned long aux_calc_rate(struct clk *clk, int index)
-{
-       unsigned long rate = clk->pclk->rate;
-       struct aux_rate_tbl *tbls = clk->rate_config.tbls;
-       u8 eq = tbls[index].eq ? 1 : 2;
-
-       return (((rate/10000) * tbls[index].xscale) /
-                       (tbls[index].yscale * eq)) * 10000;
-}
-
-/*
- * calculates current programmed rate of auxiliary synthesizers
- * used by: UART, FIRDA
- *
- * Fout from synthesizer can be given from two equations:
- * Fout1 = (Fin * X/Y)/2
- * Fout2 = Fin * X/Y
- *
- * Selection of eqn 1 or 2 is programmed in register
- */
-int aux_clk_recalc(struct clk *clk)
-{
-       struct aux_clk_config *config = clk->private_data;
-       unsigned int num = 1, den = 1, val, eqn;
-
-       val = readl(config->synth_reg);
-
-       eqn = (val >> config->masks->eq_sel_shift) &
-               config->masks->eq_sel_mask;
-       if (eqn == config->masks->eq1_mask)
-               den *= 2;
-
-       /* calculate numerator */
-       num = (val >> config->masks->xscale_sel_shift) &
-               config->masks->xscale_sel_mask;
-
-       /* calculate denominator */
-       den *= (val >> config->masks->yscale_sel_shift) &
-               config->masks->yscale_sel_mask;
-
-       if (!den)
-               return -EINVAL;
-
-       clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
-       return 0;
-}
-
-/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
-int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-       struct aux_rate_tbl *tbls = clk->rate_config.tbls;
-       struct aux_clk_config *config = clk->private_data;
-       unsigned long val, rate;
-       int i;
-
-       i = round_rate_index(clk, desired_rate, &rate);
-       if (i < 0)
-               return i;
-
-       val = readl(config->synth_reg) &
-               ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift);
-       val |= (tbls[i].eq & config->masks->eq_sel_mask) <<
-               config->masks->eq_sel_shift;
-       val &= ~(config->masks->xscale_sel_mask <<
-                       config->masks->xscale_sel_shift);
-       val |= (tbls[i].xscale & config->masks->xscale_sel_mask) <<
-               config->masks->xscale_sel_shift;
-       val &= ~(config->masks->yscale_sel_mask <<
-                       config->masks->yscale_sel_shift);
-       val |= (tbls[i].yscale & config->masks->yscale_sel_mask) <<
-               config->masks->yscale_sel_shift;
-       writel(val, config->synth_reg);
-
-       clk->rate = rate;
-
-       return 0;
-}
-
-/*
- * Calculates gpt clk rate for different values of mscale and nscale
- *
- * Fout= Fin/((2 ^ (N+1)) * (M+1))
- */
-unsigned long gpt_calc_rate(struct clk *clk, int index)
-{
-       unsigned long rate = clk->pclk->rate;
-       struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
-
-       return rate / ((1 << (tbls[index].nscale + 1)) *
-                       (tbls[index].mscale + 1));
-}
-
-/*
- * calculates current programmed rate of gpt synthesizers
- * Fout from synthesizer can be given from below equations:
- * Fout= Fin/((2 ^ (N+1)) * (M+1))
- */
-int gpt_clk_recalc(struct clk *clk)
-{
-       struct gpt_clk_config *config = clk->private_data;
-       unsigned int div = 1, val;
-
-       val = readl(config->synth_reg);
-       div += (val >> config->masks->mscale_sel_shift) &
-               config->masks->mscale_sel_mask;
-       div *= 1 << (((val >> config->masks->nscale_sel_shift) &
-                               config->masks->nscale_sel_mask) + 1);
-
-       if (!div)
-               return -EINVAL;
-
-       clk->rate = (unsigned long)clk->pclk->rate / div;
-       return 0;
-}
-
-/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/
-int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-       struct gpt_rate_tbl *tbls = clk->rate_config.tbls;
-       struct gpt_clk_config *config = clk->private_data;
-       unsigned long val, rate;
-       int i;
-
-       i = round_rate_index(clk, desired_rate, &rate);
-       if (i < 0)
-               return i;
-
-       val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask <<
-                       config->masks->mscale_sel_shift);
-       val |= (tbls[i].mscale & config->masks->mscale_sel_mask) <<
-               config->masks->mscale_sel_shift;
-       val &= ~(config->masks->nscale_sel_mask <<
-                       config->masks->nscale_sel_shift);
-       val |= (tbls[i].nscale & config->masks->nscale_sel_mask) <<
-               config->masks->nscale_sel_shift;
-       writel(val, config->synth_reg);
-
-       clk->rate = rate;
-
-       return 0;
-}
-
-/*
- * Calculates clcd clk rate for different values of div
- *
- * Fout from synthesizer can be given from below equation:
- * Fout= Fin/2*div (division factor)
- * div is 17 bits:-
- *     0-13 (fractional part)
- *     14-16 (integer part)
- * To calculate Fout we left shift val by 14 bits and divide Fin by
- * complete div (including fractional part) and then right shift the
- * result by 14 places.
- */
-unsigned long clcd_calc_rate(struct clk *clk, int index)
-{
-       unsigned long rate = clk->pclk->rate;
-       struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
-
-       rate /= 1000;
-       rate <<= 12;
-       rate /= (2 * tbls[index].div);
-       rate >>= 12;
-       rate *= 1000;
-
-       return rate;
-}
-
-/*
- * calculates current programmed rate of clcd synthesizer
- * Fout from synthesizer can be given from below equation:
- * Fout= Fin/2*div (division factor)
- * div is 17 bits:-
- *     0-13 (fractional part)
- *     14-16 (integer part)
- * To calculate Fout we left shift val by 14 bits and divide Fin by
- * complete div (including fractional part) and then right shift the
- * result by 14 places.
- */
-int clcd_clk_recalc(struct clk *clk)
-{
-       struct clcd_clk_config *config = clk->private_data;
-       unsigned int div = 1;
-       unsigned long prate;
-       unsigned int val;
-
-       val = readl(config->synth_reg);
-       div = (val >> config->masks->div_factor_shift) &
-               config->masks->div_factor_mask;
-
-       if (!div)
-               return -EINVAL;
-
-       prate = clk->pclk->rate / 1000; /* first level division, make it KHz */
-
-       clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12;
-       clk->rate *= 1000;
-       return 0;
-}
-
-/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/
-int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate)
-{
-       struct clcd_rate_tbl *tbls = clk->rate_config.tbls;
-       struct clcd_clk_config *config = clk->private_data;
-       unsigned long val, rate;
-       int i;
-
-       i = round_rate_index(clk, desired_rate, &rate);
-       if (i < 0)
-               return i;
-
-       val = readl(config->synth_reg) & ~(config->masks->div_factor_mask <<
-                       config->masks->div_factor_shift);
-       val |= (tbls[i].div & config->masks->div_factor_mask) <<
-               config->masks->div_factor_shift;
-       writel(val, config->synth_reg);
-
-       clk->rate = rate;
-
-       return 0;
-}
-
-/*
- * Used for clocks that always have value as the parent clock divided by a
- * fixed divisor
- */
-int follow_parent(struct clk *clk)
-{
-       unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor;
-
-       clk->rate = clk->pclk->rate/div_factor;
-       return 0;
-}
-
-/**
- * recalc_root_clocks - recalculate and propagate all root clocks
- *
- * Recalculates all root clocks (clocks with no parent), which if the
- * clock's .recalc is set correctly, should also propagate their rates.
- */
-void recalc_root_clocks(void)
-{
-       struct clk *pclk;
-       unsigned long flags;
-       int ret = 0;
-
-       spin_lock_irqsave(&clocks_lock, flags);
-       list_for_each_entry(pclk, &root_clks, sibling) {
-               if (pclk->recalc) {
-                       ret = pclk->recalc(pclk);
-                       /*
-                        * recalc will return error if clk out is not programmed
-                        * In this case configure default clock.
-                        */
-                       if (ret && pclk->set_rate)
-                               pclk->set_rate(pclk, 0);
-               }
-               propagate_rate(pclk, 1);
-               /* Enable clks enabled on init, in software view */
-               if (pclk->flags & ENABLED_ON_INIT)
-                       do_clk_enable(pclk);
-       }
-       spin_unlock_irqrestore(&clocks_lock, flags);
-}
-
-void __init clk_init(void)
-{
-       recalc_root_clocks();
-}
-
-#ifdef CONFIG_DEBUG_FS
-/*
- *     debugfs support to trace clock tree hierarchy and attributes
- */
-static struct dentry *clk_debugfs_root;
-static int clk_debugfs_register_one(struct clk *c)
-{
-       int err;
-       struct dentry *d;
-       struct clk *pa = c->pclk;
-       char s[255];
-       char *p = s;
-
-       if (c) {
-               if (c->cl->con_id)
-                       p += sprintf(p, "%s", c->cl->con_id);
-               if (c->cl->dev_id)
-                       p += sprintf(p, "%s", c->cl->dev_id);
-       }
-       d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
-       if (!d)
-               return -ENOMEM;
-       c->dent = d;
-
-       d = debugfs_create_u32("usage_count", S_IRUGO, c->dent,
-                       (u32 *)&c->usage_count);
-       if (!d) {
-               err = -ENOMEM;
-               goto err_out;
-       }
-       d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
-       if (!d) {
-               err = -ENOMEM;
-               goto err_out;
-       }
-       d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
-       if (!d) {
-               err = -ENOMEM;
-               goto err_out;
-       }
-       return 0;
-
-err_out:
-       debugfs_remove_recursive(c->dent);
-       return err;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
-       int err;
-       struct clk *pa = c->pclk;
-
-       if (pa && !pa->dent) {
-               err = clk_debugfs_register(pa);
-               if (err)
-                       return err;
-       }
-
-       if (!c->dent) {
-               err = clk_debugfs_register_one(c);
-               if (err)
-                       return err;
-       }
-       return 0;
-}
-
-static int __init clk_debugfs_init(void)
-{
-       struct clk *c;
-       struct dentry *d;
-       int err;
-
-       d = debugfs_create_dir("clock", NULL);
-       if (!d)
-               return -ENOMEM;
-       clk_debugfs_root = d;
-
-       list_for_each_entry(c, &clocks, node) {
-               err = clk_debugfs_register(c);
-               if (err)
-                       goto err_out;
-       }
-       return 0;
-err_out:
-       debugfs_remove_recursive(clk_debugfs_root);
-       return err;
-}
-late_initcall(clk_debugfs_init);
-
-static int clk_debugfs_reparent(struct clk *c)
-{
-       debugfs_remove(c->dent);
-       return clk_debugfs_register_one(c);
-}
-#endif /* CONFIG_DEBUG_FS */

diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
deleted file mode 100644 (file)
index 0062baf..0000000
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/clock.h
- *
- * Clock framework definitions for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_CLOCK_H
-#define __PLAT_CLOCK_H
-
-#include <linux/list.h>
-#include <linux/clkdev.h>
-#include <linux/types.h>
-
-/* clk structure flags */
-#define        ALWAYS_ENABLED          (1 << 0) /* clock always enabled */
-#define        RESET_TO_ENABLE         (1 << 1) /* reset register bit to enable clk */
-#define        ENABLED_ON_INIT         (1 << 2) /* clocks enabled at init */
-
-/**
- * struct clkops - clock operations
- * @enable: pointer to clock enable function
- * @disable: pointer to clock disable function
- */
-struct clkops {
-       int (*enable) (struct clk *);
-       void (*disable) (struct clk *);
-};
-
-/**
- * struct pclk_info - parents info
- * @pclk: pointer to parent clk
- * @pclk_val: value to be written for selecting this parent
- */
-struct pclk_info {
-       struct clk *pclk;
-       u8 pclk_val;
-};
-
-/**
- * struct pclk_sel - parents selection configuration
- * @pclk_info: pointer to array of parent clock info
- * @pclk_count: number of parents
- * @pclk_sel_reg: register for selecting a parent
- * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
- */
-struct pclk_sel {
-       struct pclk_info *pclk_info;
-       u8 pclk_count;
-       void __iomem *pclk_sel_reg;
-       unsigned int pclk_sel_mask;
-};
-
-/**
- * struct rate_config - clk rate configurations
- * @tbls: array of device specific clk rate tables, in ascending order of rates
- * @count: size of tbls array
- * @default_index: default setting when originally disabled
- */
-struct rate_config {
-       void *tbls;
-       u8 count;
-       u8 default_index;
-};
-
-/**
- * struct clk - clock structure
- * @usage_count: num of users who enabled this clock
- * @flags: flags for clock properties
- * @rate: programmed clock rate in Hz
- * @en_reg: clk enable/disable reg
- * @en_reg_bit: clk enable/disable bit
- * @ops: clk enable/disable ops - generic_clkops selected if NULL
- * @recalc: pointer to clock rate recalculate function
- * @set_rate: pointer to clock set rate function
- * @calc_rate: pointer to clock get rate function for index
- * @rate_config: rate configuration information, used by set_rate
- * @div_factor: division factor to parent clock.
- * @pclk: current parent clk
- * @pclk_sel: pointer to parent selection structure
- * @pclk_sel_shift: register shift for selecting parent of this clock
- * @children: list for childrens or this clock
- * @sibling: node for list of clocks having same parents
- * @private_data: clock specific private data
- * @node: list to maintain clocks linearly
- * @cl: clocklook up associated with this clock
- * @dent: object for debugfs
- */
-struct clk {
-       unsigned int usage_count;
-       unsigned int flags;
-       unsigned long rate;
-       void __iomem *en_reg;
-       u8 en_reg_bit;
-       const struct clkops *ops;
-       int (*recalc) (struct clk *);
-       int (*set_rate) (struct clk *, unsigned long rate);
-       unsigned long (*calc_rate)(struct clk *, int index);
-       struct rate_config rate_config;
-       unsigned int div_factor;
-
-       struct clk *pclk;
-       struct pclk_sel *pclk_sel;
-       unsigned int pclk_sel_shift;
-
-       struct list_head children;
-       struct list_head sibling;
-       void *private_data;
-#ifdef CONFIG_DEBUG_FS
-       struct list_head node;
-       struct clk_lookup *cl;
-       struct dentry *dent;
-#endif
-};
-
-/* pll configuration structure */
-struct pll_clk_masks {
-       u32 mode_mask;
-       u32 mode_shift;
-
-       u32 norm_fdbk_m_mask;
-       u32 norm_fdbk_m_shift;
-       u32 dith_fdbk_m_mask;
-       u32 dith_fdbk_m_shift;
-       u32 div_p_mask;
-       u32 div_p_shift;
-       u32 div_n_mask;
-       u32 div_n_shift;
-};
-
-struct pll_clk_config {
-       void __iomem *mode_reg;
-       void __iomem *cfg_reg;
-       struct pll_clk_masks *masks;
-};
-
-/* pll clk rate config structure */
-struct pll_rate_tbl {
-       u8 mode;
-       u16 m;
-       u8 n;
-       u8 p;
-};
-
-/* ahb and apb bus configuration structure */
-struct bus_clk_masks {
-       u32 mask;
-       u32 shift;
-};
-
-struct bus_clk_config {
-       void __iomem *reg;
-       struct bus_clk_masks *masks;
-};
-
-/* ahb and apb clk bus rate config structure */
-struct bus_rate_tbl {
-       u8 div;
-};
-
-/* Aux clk configuration structure: applicable to UART and FIRDA */
-struct aux_clk_masks {
-       u32 eq_sel_mask;
-       u32 eq_sel_shift;
-       u32 eq1_mask;
-       u32 eq2_mask;
-       u32 xscale_sel_mask;
-       u32 xscale_sel_shift;
-       u32 yscale_sel_mask;
-       u32 yscale_sel_shift;
-};
-
-struct aux_clk_config {
-       void __iomem *synth_reg;
-       struct aux_clk_masks *masks;
-};
-
-/* aux clk rate config structure */
-struct aux_rate_tbl {
-       u16 xscale;
-       u16 yscale;
-       u8 eq;
-};
-
-/* GPT clk configuration structure */
-struct gpt_clk_masks {
-       u32 mscale_sel_mask;
-       u32 mscale_sel_shift;
-       u32 nscale_sel_mask;
-       u32 nscale_sel_shift;
-};
-
-struct gpt_clk_config {
-       void __iomem *synth_reg;
-       struct gpt_clk_masks *masks;
-};
-
-/* gpt clk rate config structure */
-struct gpt_rate_tbl {
-       u16 mscale;
-       u16 nscale;
-};
-
-/* clcd clk configuration structure */
-struct clcd_synth_masks {
-       u32 div_factor_mask;
-       u32 div_factor_shift;
-};
-
-struct clcd_clk_config {
-       void __iomem *synth_reg;
-       struct clcd_synth_masks *masks;
-};
-
-/* clcd clk rate config structure */
-struct clcd_rate_tbl {
-       u16 div;
-};
-
-/* platform specific clock functions */
-void __init clk_init(void);
-void clk_register(struct clk_lookup *cl);
-void recalc_root_clocks(void);
-
-/* clock recalc & set rate functions */
-int follow_parent(struct clk *clk);
-unsigned long pll_calc_rate(struct clk *clk, int index);
-int pll_clk_recalc(struct clk *clk);
-int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long bus_calc_rate(struct clk *clk, int index);
-int bus_clk_recalc(struct clk *clk);
-int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long gpt_calc_rate(struct clk *clk, int index);
-int gpt_clk_recalc(struct clk *clk);
-int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long aux_calc_rate(struct clk *clk, int index);
-int aux_clk_recalc(struct clk *clk);
-int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-unsigned long clcd_calc_rate(struct clk *clk, int index);
-int clcd_clk_recalc(struct clk *clk);
-int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate);
-
-#endif /* __PLAT_CLOCK_H */

diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 02b160a..ab3de72 100644 (file)
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -12,7 +12,7 @@
  */
 
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
                .macro  addruart, rp, rv, tmp
                mov     \rp, #SPEAR_DBG_UART_BASE               @ Physical base

diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
deleted file mode 100644 (file)
index 70187d7..0000000
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/hardware.h
- *
- * Hardware definitions for SPEAr
- *
- * Copyright (C) 2010 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_HARDWARE_H
-#define __PLAT_HARDWARE_H
-
-#endif /* __PLAT_HARDWARE_H */

diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644 (file)
index 877f3ad..0000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.h
- *
- * SPEAr platform specific gpio pads muxing file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_PADMUX_H
-#define __PLAT_PADMUX_H
-
-#include <linux/types.h>
-
-/*
- * struct pmx_reg: configuration structure for mode reg and mux reg
- *
- * offset: offset of mode reg
- * mask: mask of mode reg
- */
-struct pmx_reg {
-       u32 offset;
-       u32 mask;
-};
-
-/*
- * struct pmx_dev_mode: configuration structure every group of modes of a device
- *
- * ids: all modes for this configuration
- * mask: mask for supported mode
- */
-struct pmx_dev_mode {
-       u32 ids;
-       u32 mask;
-};
-
-/*
- * struct pmx_mode: mode definition structure
- *
- * name: mode name
- * mask: mode mask
- */
-struct pmx_mode {
-       char *name;
-       u32 id;
-       u32 mask;
-};
-
-/*
- * struct pmx_dev: device definition structure
- *
- * name: device name
- * modes: device configuration array for different modes supported
- * mode_count: size of modes array
- * is_active: is peripheral active/enabled
- * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
- */
-struct pmx_dev {
-       char *name;
-       struct pmx_dev_mode *modes;
-       u8 mode_count;
-       bool is_active;
-       bool enb_on_reset;
-};
-
-/*
- * struct pmx_driver: driver definition structure
- *
- * mode: mode to be set
- * devs: array of pointer to pmx devices
- * devs_count: ARRAY_SIZE of devs
- * base: base address of soc config registers
- * mode_reg: structure of mode config register
- * mux_reg: structure of device mux config register
- */
-struct pmx_driver {
-       struct pmx_mode *mode;
-       struct pmx_dev **devs;
-       u8 devs_count;
-       u32 *base;
-       struct pmx_reg mode_reg;
-       struct pmx_reg mux_reg;
-};
-
-/* pmx functions */
-int pmx_register(struct pmx_driver *driver);
-
-#endif /* __PLAT_PADMUX_H */

diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644 (file)
index 0000000..e14a3e4
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+
+#endif /* __PLAT_PL080_H */

diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 1bf8452..6dd455b 100644 (file)
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -13,7 +13,7 @@
 
 #include <linux/io.h>
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #ifndef __PLAT_UNCOMPRESS_H
 #define __PLAT_UNCOMPRESS_H

diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644 (file)
index 555eec6..0000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.c
- *
- * SPEAr platform specific gpio pads muxing source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <plat/padmux.h>
-
-/*
- * struct pmx: pmx definition structure
- *
- * base: base address of configuration registers
- * mode_reg: mode configurations
- * mux_reg: muxing configurations
- * active_mode: pointer to current active mode
- */
-struct pmx {
-       u32 base;
-       struct pmx_reg mode_reg;
-       struct pmx_reg mux_reg;
-       struct pmx_mode *active_mode;
-};
-
-static struct pmx *pmx;
-
-/**
- * pmx_mode_set - Enables an multiplexing mode
- * @mode - pointer to pmx mode
- *
- * It will set mode of operation in hardware.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_mode_set(struct pmx_mode *mode)
-{
-       u32 val;
-
-       if (!mode->name)
-               return -EFAULT;
-
-       pmx->active_mode = mode;
-
-       val = readl(pmx->base + pmx->mode_reg.offset);
-       val &= ~pmx->mode_reg.mask;
-       val |= mode->mask & pmx->mode_reg.mask;
-       writel(val, pmx->base + pmx->mode_reg.offset);
-
-       return 0;
-}
-
-/**
- * pmx_devs_enable - Enables list of devices
- * @devs - pointer to pmx device array
- * @count - number of devices to enable
- *
- * It will enable pads for all required peripherals once and only once.
- * If peripheral is not supported by current mode then request is rejected.
- * Conflicts between peripherals are not handled and peripherals will be
- * enabled in the order they are present in pmx_dev array.
- * In case of conflicts last peripheral enabled will be present.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
-{
-       u32 val, i, mask;
-
-       if (!count)
-               return -EINVAL;
-
-       val = readl(pmx->base + pmx->mux_reg.offset);
-       for (i = 0; i < count; i++) {
-               u8 j = 0;
-
-               if (!devs[i]->name || !devs[i]->modes) {
-                       printk(KERN_ERR "padmux: dev name or modes is null\n");
-                       continue;
-               }
-               /* check if peripheral exists in active mode */
-               if (pmx->active_mode) {
-                       bool found = false;
-                       for (j = 0; j < devs[i]->mode_count; j++) {
-                               if (devs[i]->modes[j].ids &
-                                               pmx->active_mode->id) {
-                                       found = true;
-                                       break;
-                               }
-                       }
-                       if (found == false) {
-                               printk(KERN_ERR "%s device not available in %s"\
-                                               "mode\n", devs[i]->name,
-                                               pmx->active_mode->name);
-                               continue;
-                       }
-               }
-
-               /* enable peripheral */
-               mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
-               if (devs[i]->enb_on_reset)
-                       val &= ~mask;
-               else
-                       val |= mask;
-
-               devs[i]->is_active = true;
-       }
-       writel(val, pmx->base + pmx->mux_reg.offset);
-       kfree(pmx);
-
-       /* this will ensure that multiplexing can't be changed now */
-       pmx = (struct pmx *)-1;
-
-       return 0;
-}
-
-/**
- * pmx_register - registers a platform requesting pad mux feature
- * @driver - pointer to driver structure containing driver specific parameters
- *
- * Also this must be called only once. This will allocate memory for pmx
- * structure, will call pmx_mode_set, will call pmx_devs_enable.
- * Returns -ve on Err otherwise 0
- */
-int pmx_register(struct pmx_driver *driver)
-{
-       int ret = 0;
-
-       if (pmx)
-               return -EPERM;
-       if (!driver->base || !driver->devs)
-               return -EFAULT;
-
-       pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
-       if (!pmx)
-               return -ENOMEM;
-
-       pmx->base = (u32)driver->base;
-       pmx->mode_reg.offset = driver->mode_reg.offset;
-       pmx->mode_reg.mask = driver->mode_reg.mask;
-       pmx->mux_reg.offset = driver->mux_reg.offset;
-       pmx->mux_reg.mask = driver->mux_reg.mask;
-
-       /* choose mode to enable */
-       if (driver->mode) {
-               ret = pmx_mode_set(driver->mode);
-               if (ret)
-                       goto pmx_fail;
-       }
-       ret = pmx_devs_enable(driver->devs, driver->devs_count);
-       if (ret)
-               goto pmx_fail;
-
-       return 0;
-
-pmx_fail:
-       return ret;
-}

diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644 (file)
index 0000000..a56a067
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,80 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/spear.h>
+#include <mach/misc_regs.h>
+
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+
+struct {
+       unsigned char busy;
+       unsigned char val;
+} signals[16] = {{0, 0}, };
+
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+       const struct pl08x_channel_data *cd = ch->cd;
+       unsigned int signal = cd->min_signal, val;
+       unsigned long flags;
+
+       spin_lock_irqsave(&lock, flags);
+
+       /* Return if signal is already acquired by somebody else */
+       if (signals[signal].busy &&
+                       (signals[signal].val != cd->muxval)) {
+               spin_unlock_irqrestore(&lock, flags);
+               return -EBUSY;
+       }
+
+       /* If acquiring for the first time, configure it */
+       if (!signals[signal].busy) {
+               val = readl(DMA_CHN_CFG);
+
+               /*
+                * Each request line has two bits in DMA_CHN_CFG register. To
+                * goto the bits of current request line, do left shift of
+                * value by 2 * signal number.
+                */
+               val &= ~(0x3 << (signal * 2));
+               val |= cd->muxval << (signal * 2);
+               writel(val, DMA_CHN_CFG);
+       }
+
+       signals[signal].busy++;
+       signals[signal].val = cd->muxval;
+       spin_unlock_irqrestore(&lock, flags);
+
+       return signal;
+}
+
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+       const struct pl08x_channel_data *cd = ch->cd;
+       unsigned long flags;
+
+       spin_lock_irqsave(&lock, flags);
+
+       /* if signal is not used */
+       if (!signals[cd->min_signal].busy)
+               BUG();
+
+       signals[cd->min_signal].busy--;
+
+       spin_unlock_irqrestore(&lock, flags);
+}

diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 16f203e..4471a23 100644 (file)
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -13,7 +13,7 @@
 #include <linux/io.h>
 #include <asm/system_misc.h>
 #include <asm/hardware/sp810.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 #include <mach/generic.h>
 
 void spear_restart(char mode, const char *cmd)

diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index abb5bde..03321af 100644 (file)
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -15,14 +15,15 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 
 /*
  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
@@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = {
        .handler = spear_timer_interrupt
 };
 
-static void __init spear_clockevent_init(void)
+static void __init spear_clockevent_init(int irq)
 {
        u32 tick_rate;
 
@@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void)
 
        clockevents_register_device(&clkevt);
 
-       setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
+       setup_irq(irq, &spear_timer_irq);
 }
 
-void __init spear_setup_timer(void)
+const static struct of_device_id timer_of_match[] __initconst = {
+       { .compatible = "st,spear-timer", },
+       { },
+};
+
+void __init spear_setup_of_timer(void)
 {
-       int ret;
+       struct device_node *np;
+       int irq, ret;
+
+       np = of_find_matching_node(NULL, timer_of_match);
+       if (!np) {
+               pr_err("%s: No timer passed via DT\n", __func__);
+               return;
+       }
 
-       if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
-               pr_err("%s:cannot get IO addr\n", __func__);
+       irq = irq_of_parse_and_map(np, 0);
+       if (!irq) {
+               pr_err("%s: No irq passed for timer via DT\n", __func__);
                return;
        }
 
-       gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
+       gpt_base = of_iomap(np, 0);
        if (!gpt_base) {
-               pr_err("%s:ioremap failed for gpt\n", __func__);
-               goto err_mem;
+               pr_err("%s: of iomap failed\n", __func__);
+               return;
        }
 
        gpt_clk = clk_get_sys("gpt0", NULL);
@@ -219,21 +233,19 @@ void __init spear_setup_timer(void)
                goto err_iomap;
        }
 
-       ret = clk_enable(gpt_clk);
+       ret = clk_prepare_enable(gpt_clk);
        if (ret < 0) {
-               pr_err("%s:couldn't enable gpt clock\n", __func__);
-               goto err_clk;
+               pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
+               goto err_prepare_enable_clk;
        }
 
-       spear_clockevent_init();
+       spear_clockevent_init(irq);
        spear_clocksource_init();
 
        return;
 
-err_clk:
+err_prepare_enable_clk:
        clk_put(gpt_clk);
 err_iomap:
        iounmap(gpt_base);
-err_mem:
-       release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
 }

diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 858748e..bc683b8 100644 (file)
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -17,6 +17,8 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/user.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
@@ -529,6 +531,103 @@ void vfp_flush_hwstate(struct thread_info *thread)
 }
 
 /*
+ * Save the current VFP state into the provided structures and prepare
+ * for entry into a new function (signal handler).
+ */
+int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp,
+                                   struct user_vfp_exc __user *ufp_exc)
+{
+       struct thread_info *thread = current_thread_info();
+       struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
+       int err = 0;
+
+       /* Ensure that the saved hwstate is up-to-date. */
+       vfp_sync_hwstate(thread);
+
+       /*
+        * Copy the floating point registers. There can be unused
+        * registers see asm/hwcap.h for details.
+        */
+       err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs,
+                             sizeof(hwstate->fpregs));
+       /*
+        * Copy the status and control register.
+        */
+       __put_user_error(hwstate->fpscr, &ufp->fpscr, err);
+
+       /*
+        * Copy the exception registers.
+        */
+       __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err);
+       __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
+       __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
+
+       if (err)
+               return -EFAULT;
+
+       /* Ensure that VFP is disabled. */
+       vfp_flush_hwstate(thread);
+
+       /*
+        * As per the PCS, clear the length and stride bits for function
+        * entry.
+        */
+       hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK);
+
+       /*
+        * Disable VFP in the hwstate so that we can detect if it gets
+        * used.
+        */
+       hwstate->fpexc &= ~FPEXC_EN;
+       return 0;
+}
+
+/* Sanitise and restore the current VFP state from the provided structures. */
+int vfp_restore_user_hwstate(struct user_vfp __user *ufp,
+                            struct user_vfp_exc __user *ufp_exc)
+{
+       struct thread_info *thread = current_thread_info();
+       struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
+       unsigned long fpexc;
+       int err = 0;
+
+       /*
+        * If VFP has been used, then disable it to avoid corrupting
+        * the new thread state.
+        */
+       if (hwstate->fpexc & FPEXC_EN)
+               vfp_flush_hwstate(thread);
+
+       /*
+        * Copy the floating point registers. There can be unused
+        * registers see asm/hwcap.h for details.
+        */
+       err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs,
+                               sizeof(hwstate->fpregs));
+       /*
+        * Copy the status and control register.
+        */
+       __get_user_error(hwstate->fpscr, &ufp->fpscr, err);
+
+       /*
+        * Sanitise and restore the exception registers.
+        */
+       __get_user_error(fpexc, &ufp_exc->fpexc, err);
+
+       /* Ensure the VFP is enabled. */
+       fpexc |= FPEXC_EN;
+
+       /* Ensure FPINST2 is invalid and the exception flag is cleared. */
+       fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
+       hwstate->fpexc = fpexc;
+
+       __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
+       __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
+
+       return err ? -EFAULT : 0;
+}
+
+/*
  * VFP hardware can lose all context when a CPU goes offline.
  * As we will be running in SMP mode with CPU hotplug, we will save the
  * hardware state at every thread switch.  We clear our held state when

diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 1633a6f..85038f5 100644 (file)
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
-#endif
+#endif /* CONFIG_RTC_DRV_BFIN */
 
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_UART0
@@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
                .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif /* CONFIG_SERIAL_BFIN_UART0 */
 #ifdef CONFIG_SERIAL_BFIN_UART1
 static struct resource bfin_uart1_resources[] = {
        {
@@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
                .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif /* CONFIG_SERIAL_BFIN_UART1 */
 #ifdef CONFIG_SERIAL_BFIN_UART2
 static struct resource bfin_uart2_resources[] = {
        {
@@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
                .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
        },
 };
-#endif
-#endif
+#endif /* CONFIG_SERIAL_BFIN_UART2 */
+#endif /* CONFIG_SERIAL_BFIN */
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 #ifdef CONFIG_BFIN_SIR0
@@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
        .resource = bfin_sir0_resources,
 };
-#endif
+#endif /* CONFIG_BFIN_SIR0 */
 #ifdef CONFIG_BFIN_SIR1
 static struct resource bfin_sir1_resources[] = {
        {
@@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
        .resource = bfin_sir1_resources,
 };
-#endif
+#endif /* CONFIG_BFIN_SIR1 */
 #ifdef CONFIG_BFIN_SIR2
 static struct resource bfin_sir2_resources[] = {
        {
@@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
        .num_resources = ARRAY_SIZE(bfin_sir2_resources),
        .resource = bfin_sir2_resources,
 };
-#endif
-#endif
+#endif /* CONFIG_BFIN_SIR2 */
+#endif /* CONFIG_BFIN_SIR */
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
@@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
                .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 static struct resource bfin_sport1_uart_resources[] = {
        {
@@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
                .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
 static struct resource bfin_sport2_uart_resources[] = {
        {
@@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
                .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
 static struct resource bfin_sport3_uart_resources[] = {
        {
@@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
                .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
        },
 };
-#endif
-#endif
+#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
+#endif /* CONFIG_SERIAL_BFIN_SPORT */
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
 static unsigned short bfin_can_peripherals[] = {
@@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
                .platform_data = &bfin_can_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif /* CONFIG_CAN_BFIN */
 
 /*
  *  USB-LAN EzExtender board
@@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
                .platform_data  = &smc91x_info,
        },
 };
-#endif
+#endif /* CONFIG_SMC91X */
 
 #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
@@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
 };
-#endif
+#endif /* CONFIG_MTD_M25P80 */
+#endif /* CONFIG_SPI_BFIN5XX */
 
 #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
 #include <linux/spi/ad7879.h>
@@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
        .gpio_export            = 1,    /* Export GPIO to gpiolib */
        .gpio_base              = -1,   /* Dynamic allocation */
 };
-#endif
+#endif /* CONFIG_TOUCHSCREEN_AD7879 */
 
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 #include <asm/bfin-lq035q1.h>
@@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
                .platform_data = &bfin_lq035q1_data,
        },
 };
-#endif
+#endif /* CONFIG_FB_BFIN_LQ035Q1 */
 
 static struct spi_board_info bf538_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
@@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .controller_data = &spi_flash_chip_info,
                .mode = SPI_MODE_3,
        },
-#endif
+#endif /* CONFIG_MTD_M25P80 */
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
        {
                .modalias = "ad7879",
@@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .chip_select = 1,
                .mode = SPI_CPHA | SPI_CPOL,
        },
-#endif
+#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
        {
                .modalias = "bfin-lq035q1-spi",
@@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .chip_select = 2,
                .mode = SPI_CPHA | SPI_CPOL,
        },
-#endif
+#endif /* CONFIG_FB_BFIN_LQ035Q1 */
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
        {
                .modalias = "spidev",
@@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = 1,
        },
-#endif
+#endif /* CONFIG_SPI_SPIDEV */
 };
 
 /* SPI (0) */
@@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = {
                },
 };
 
-#endif  /* spi master and devices */
-
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
        [0] = {
@@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = {
        .num_resources = ARRAY_SIZE(bfin_twi1_resource),
        .resource = bfin_twi1_resource,
 };
-#endif
-#endif
+#endif /* CONFIG_BF542 */
+#endif /* CONFIG_I2C_BLACKFIN_TWI */
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 #include <linux/gpio_keys.h>

diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c
index 3730221..0f2367c 100644 (file)
--- a/arch/hexagon/kernel/dma.c
+++ b/arch/hexagon/kernel/dma.c
@@ -22,6 +22,7 @@
 #include <linux/bootmem.h>
 #include <linux/genalloc.h>
 #include <asm/dma-mapping.h>
+#include <linux/module.h>
 
 struct dma_map_ops *dma_ops;
 EXPORT_SYMBOL(dma_ops);

diff --git a/arch/hexagon/kernel/process.c b/arch/hexagon/kernel/process.c
index 18c4f0b..ff02821 100644 (file)
--- a/arch/hexagon/kernel/process.c
+++ b/arch/hexagon/kernel/process.c
@@ -1,7 +1,7 @@
 /*
  * Process creation support for Hexagon
  *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle;
 void cpu_idle(void)
 {
        while (1) {
-               tick_nohz_stop_sched_tick(1);
+               tick_nohz_idle_enter();
                local_irq_disable();
                while (!need_resched()) {
                        idle_sleep();
@@ -97,7 +97,7 @@ void cpu_idle(void)
                        local_irq_disable();
                }
                local_irq_enable();
-               tick_nohz_restart_sched_tick();
+               tick_nohz_idle_exit();
                schedule();
        }
 }

diff --git a/arch/hexagon/kernel/ptrace.c b/arch/hexagon/kernel/ptrace.c
index 32342de..96c3b2c 100644 (file)
--- a/arch/hexagon/kernel/ptrace.c
+++ b/arch/hexagon/kernel/ptrace.c
@@ -28,6 +28,7 @@
 #include <linux/ptrace.h>
 #include <linux/regset.h>
 #include <linux/user.h>
+#include <linux/elf.h>
 
 #include <asm/user.h>
 

diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c
index 9b44a9e..1298141 100644 (file)
--- a/arch/hexagon/kernel/smp.c
+++ b/arch/hexagon/kernel/smp.c
@@ -1,7 +1,7 @@
 /*
  * SMP support for Hexagon
  *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -28,6 +28,7 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/spinlock.h>
+#include <linux/cpu.h>
 
 #include <asm/time.h>    /*  timer_interrupt  */
 #include <asm/hexagon_vm.h>
@@ -177,7 +178,12 @@ void __cpuinit start_secondary(void)
 
        printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu);
 
+       notify_cpu_starting(cpu);
+
+       ipi_call_lock();
        set_cpu_online(cpu, true);
+       ipi_call_unlock();
+
        local_irq_enable();
 
        cpu_idle();

diff --git a/arch/hexagon/kernel/time.c b/arch/hexagon/kernel/time.c
index 6bee15c..5d9b33b 100644 (file)
--- a/arch/hexagon/kernel/time.c
+++ b/arch/hexagon/kernel/time.c
@@ -28,6 +28,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/module.h>
 
 #include <asm/timer-regs.h>
 #include <asm/hexagon_vm.h>

diff --git a/arch/hexagon/kernel/vdso.c b/arch/hexagon/kernel/vdso.c
index f212a45..5d39f42 100644 (file)
--- a/arch/hexagon/kernel/vdso.c
+++ b/arch/hexagon/kernel/vdso.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
+#include <linux/binfmts.h>
 
 #include <asm/vdso.h>
 

diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
index e215070..9c717bf 100644 (file)
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void)
 
 static int ar933x_wmac_reset(void)
 {
-       ath79_device_reset_clear(AR933X_RESET_WMAC);
        ath79_device_reset_set(AR933X_RESET_WMAC);
+       ath79_device_reset_clear(AR933X_RESET_WMAC);
 
        return 0;
 }

diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
index a865c98..5ad1a9c 100644 (file)
--- a/arch/mips/include/asm/mach-jz4740/irq.h
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -45,7 +45,7 @@
 #define JZ4740_IRQ_LCD         JZ4740_IRQ(30)
 
 /* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA(x)      (JZ4740_IRQ(32) + (X))
+#define JZ4740_IRQ_DMA(x)      (JZ4740_IRQ(32) + (x))
 
 #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
 #define JZ4740_IRQ_GPIO(x)     (JZ4740_IRQ(48) + (x))

diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 73c0d45..9b02cfb 100644 (file)
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -37,12 +37,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
                write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
        } while (0)
 
-
-static inline unsigned long get_current_pgd(void)
-{
-       return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
-}
-
 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
 
 /*

diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 185ca00..d5a338a 100644 (file)
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -257,11 +257,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs)
                return -EFAULT;
        sigdelsetmask(&newset, ~_BLOCKABLE);
 
-       spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-       current->blocked = newset;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&newset);
 
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -286,11 +283,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
                return -EFAULT;
        sigdelsetmask(&newset, ~_BLOCKABLE);
 
-       spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-       current->blocked = newset;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&newset);
 
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -362,10 +356,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
 
        sigdelsetmask(&blocked, ~_BLOCKABLE);
-       spin_lock_irq(&current->sighand->siglock);
-       current->blocked = blocked;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&blocked);
 
        sig = restore_sigcontext(&regs, &frame->sf_sc);
        if (sig < 0)
@@ -401,10 +392,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
 
        sigdelsetmask(&set, ~_BLOCKABLE);
-       spin_lock_irq(&current->sighand->siglock);
-       current->blocked = set;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&set);
 
        sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
        if (sig < 0)
@@ -580,12 +568,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
        if (ret)
                return ret;
 
-       spin_lock_irq(&current->sighand->siglock);
-       sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
-       if (!(ka->sa.sa_flags & SA_NODEFER))
-               sigaddset(&current->blocked, sig);
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       block_sigmask(ka, sig);
 
        return ret;
 }

diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 06b5da3..ac3b8d8 100644 (file)
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs)
                return -EFAULT;
        sigdelsetmask(&newset, ~_BLOCKABLE);
 
-       spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-       current->blocked = newset;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&newset);
 
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
                return -EFAULT;
        sigdelsetmask(&newset, ~_BLOCKABLE);
 
-       spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-       current->blocked = newset;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&newset);
 
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
 
        sigdelsetmask(&blocked, ~_BLOCKABLE);
-       spin_lock_irq(&current->sighand->siglock);
-       current->blocked = blocked;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&blocked);
 
        sig = restore_sigcontext32(&regs, &frame->sf_sc);
        if (sig < 0)
@@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
 
        sigdelsetmask(&set, ~_BLOCKABLE);
-       spin_lock_irq(&current->sighand->siglock);
-       current->blocked = set;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&set);
 
        sig = restore_sigcontext32(&regs, &frame->rs_uc.uc_mcontext);
        if (sig < 0)

diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index ae29e89..86eb4b0 100644 (file)
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -93,11 +93,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
        sigset_from_compat(&newset, &uset);
        sigdelsetmask(&newset, ~_BLOCKABLE);
 
-       spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-       current->blocked = newset;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&newset);
 
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -121,10 +118,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
 
        sigdelsetmask(&set, ~_BLOCKABLE);
-       spin_lock_irq(&current->sighand->siglock);
-       current->blocked = set;
-       recalc_sigpending();
-       spin_unlock_irq(&current->sighand->siglock);
+       set_current_blocked(&set);
 
        sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
        if (sig < 0)

diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c
index 4f00459..0b33933 100644 (file)
--- a/arch/parisc/kernel/pdc_cons.c
+++ b/arch/parisc/kernel/pdc_cons.c
@@ -104,7 +104,7 @@ static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp)
 
 static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp)
 {
-       if (!tty->count) {
+       if (tty->count == 1) {
                del_timer_sync(&pdc_console_timer);
                tty_port_tty_set(&tty_port, NULL);
        }

diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
new file mode 100644 (file)
index 0000000..1cf0b77
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
@@ -0,0 +1,43 @@
+/*
+ * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+message@42400 {
+       compatible = "fsl,mpic-v3.1-msgr";
+       reg = <0x42400 0x200>;
+       interrupts = <
+               0xb4 2 0 0
+               0xb5 2 0 0
+               0xb6 2 0 0
+               0xb7 2 0 0>;
+};

diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index fdedf7b..71c30eb 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -53,6 +53,16 @@ timer@41100 {
                      3 0 3 0>;
 };
 
+message@41400 {
+       compatible = "fsl,mpic-v3.1-msgr";
+       reg = <0x41400 0x200>;
+       interrupts = <
+               0xb0 2 0 0
+               0xb1 2 0 0
+               0xb2 2 0 0
+               0xb3 2 0 0>;
+};
+
 msi@41600 {
        compatible = "fsl,mpic-msi";
        reg = <0x41600 0x80>;

diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index e648af9..0e40843 100644 (file)
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -18,10 +18,6 @@
 #include <linux/atomic.h>
 
 
-/* Define a way to iterate across irqs. */
-#define for_each_irq(i) \
-       for ((i) = 0; (i) < NR_IRQS; ++(i))
-
 extern atomic_t ppc_n_lost_interrupts;
 
 /* This number is used when no interrupt has been assigned */

diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c65b929..c9f698a 100644 (file)
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -275,9 +275,6 @@ struct mpic
        unsigned int            isu_mask;
        /* Number of sources */
        unsigned int            num_sources;
-       /* default senses array */
-       unsigned char           *senses;
-       unsigned int            senses_count;
 
        /* vector numbers used for internal sources (ipi/timers) */
        unsigned int            ipi_vecs[4];
@@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node,
 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                            phys_addr_t phys_addr);
 
-/* Set default sense codes
- *
- * @mpic:      controller
- * @senses:    array of sense codes
- * @count:     size of above array
- *
- * Optionally provide an array (indexed on hardware interrupt numbers
- * for this MPIC) of default sense codes for the chip. Those are linux
- * sense codes IRQ_TYPE_*
- *
- * The driver gets ownership of the pointer, don't dispose of it or
- * anything like that. __init only.
- */
-extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
-
 
 /* Initialize the controller. After this has been called, none of the above
  * should be called again for this mpic

diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
index 3ec37dc..326d33c 100644 (file)
--- a/arch/powerpc/include/asm/mpic_msgr.h
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -13,6 +13,7 @@
 
 #include <linux/types.h>
 #include <linux/spinlock.h>
+#include <asm/smp.h>
 
 struct mpic_msgr {
        u32 __iomem *base;

diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index b86faa9..8a97aa7 100644 (file)
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -15,11 +15,6 @@
 #ifndef __ASM_POWERPC_REG_BOOKE_H__
 #define __ASM_POWERPC_REG_BOOKE_H__
 
-#ifdef CONFIG_BOOKE_WDT
-extern u32 booke_wdt_enabled;
-extern u32 booke_wdt_period;
-#endif /* CONFIG_BOOKE_WDT */
-
 /* Machine State Register (MSR) Fields */
 #define MSR_GS         (1<<28) /* Guest state */
 #define MSR_UCLE       (1<<26) /* User-mode cache lock enable */

diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5ec1b23..43eb74f 100644 (file)
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -330,14 +330,10 @@ void migrate_irqs(void)
 
        alloc_cpumask_var(&mask, GFP_KERNEL);
 
-       for_each_irq(irq) {
+       for_each_irq_desc(irq, desc) {
                struct irq_data *data;
                struct irq_chip *chip;
 
-               desc = irq_to_desc(irq);
-               if (!desc)
-                       continue;
-
                data = irq_desc_get_irq_data(desc);
                if (irqd_is_per_cpu(data))
                        continue;

diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index c957b12..5df7777 100644 (file)
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -23,14 +23,11 @@
 
 void machine_kexec_mask_interrupts(void) {
        unsigned int i;
+       struct irq_desc *desc;
 
-       for_each_irq(i) {
-               struct irq_desc *desc = irq_to_desc(i);
+       for_each_irq_desc(i, desc) {
                struct irq_chip *chip;
 
-               if (!desc)
-                       continue;
-
                chip = irq_desc_get_chip(desc);
                if (!chip)
                        continue;

diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 9825f29..ec8a53f 100644 (file)
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr)
 }
 
 #ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+
 /* Checks wdt=x and wdt_period=xx command-line option */
 notrace int __init early_parse_wdt(char *p)
 {

diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index af1ab5e..5c3cf2d 100644 (file)
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -48,7 +48,13 @@
 /*
  * Assembly helpers from arch/powerpc/net/bpf_jit.S:
  */
-extern u8 sk_load_word[], sk_load_half[], sk_load_byte[], sk_load_byte_msh[];
+#define DECLARE_LOAD_FUNC(func)        \
+       extern u8 func[], func##_negative_offset[], func##_positive_offset[]
+
+DECLARE_LOAD_FUNC(sk_load_word);
+DECLARE_LOAD_FUNC(sk_load_half);
+DECLARE_LOAD_FUNC(sk_load_byte);
+DECLARE_LOAD_FUNC(sk_load_byte_msh);
 
 #define FUNCTION_DESCR_SIZE    24
 

diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S
index ff4506e..55ba385 100644 (file)
--- a/arch/powerpc/net/bpf_jit_64.S
+++ b/arch/powerpc/net/bpf_jit_64.S
@@ -31,14 +31,13 @@
  * then branch directly to slow_path_XXX if required.  (In fact, could
  * load a spare GPR with the address of slow_path_generic and pass size
  * as an argument, making the call site a mtlr, li and bllr.)
- *
- * Technically, the "is addr < 0" check is unnecessary & slowing down
- * the ABS path, as it's statically checked on generation.
  */
        .globl  sk_load_word
 sk_load_word:
        cmpdi   r_addr, 0
-       blt     bpf_error
+       blt     bpf_slow_path_word_neg
+       .globl  sk_load_word_positive_offset
+sk_load_word_positive_offset:
        /* Are we accessing past headlen? */
        subi    r_scratch1, r_HL, 4
        cmpd    r_scratch1, r_addr
@@ -51,7 +50,9 @@ sk_load_word:
        .globl  sk_load_half
 sk_load_half:
        cmpdi   r_addr, 0
-       blt     bpf_error
+       blt     bpf_slow_path_half_neg
+       .globl  sk_load_half_positive_offset
+sk_load_half_positive_offset:
        subi    r_scratch1, r_HL, 2
        cmpd    r_scratch1, r_addr
        blt     bpf_slow_path_half
@@ -61,7 +62,9 @@ sk_load_half:
        .globl  sk_load_byte
 sk_load_byte:
        cmpdi   r_addr, 0
-       blt     bpf_error
+       blt     bpf_slow_path_byte_neg
+       .globl  sk_load_byte_positive_offset
+sk_load_byte_positive_offset:
        cmpd    r_HL, r_addr
        ble     bpf_slow_path_byte
        lbzx    r_A, r_D, r_addr
@@ -69,22 +72,20 @@ sk_load_byte:
 
 /*
  * BPF_S_LDX_B_MSH: ldxb  4*([offset]&0xf)
- * r_addr is the offset value, already known positive
+ * r_addr is the offset value
  */
        .globl sk_load_byte_msh
 sk_load_byte_msh:
+       cmpdi   r_addr, 0
+       blt     bpf_slow_path_byte_msh_neg
+       .globl sk_load_byte_msh_positive_offset
+sk_load_byte_msh_positive_offset:
        cmpd    r_HL, r_addr
        ble     bpf_slow_path_byte_msh
        lbzx    r_X, r_D, r_addr
        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
        blr
 
-bpf_error:
-       /* Entered with cr0 = lt */
-       li      r3, 0
-       /* Generated code will 'blt epilogue', returning 0. */
-       blr
-
 /* Call out to skb_copy_bits:
  * We'll need to back up our volatile regs first; we have
  * local variable space at r1+(BPF_PPC_STACK_BASIC).
@@ -136,3 +137,84 @@ bpf_slow_path_byte_msh:
        lbz     r_X, BPF_PPC_STACK_BASIC+(2*8)(r1)
        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
        blr
+
+/* Call out to bpf_internal_load_pointer_neg_helper:
+ * We'll need to back up our volatile regs first; we have
+ * local variable space at r1+(BPF_PPC_STACK_BASIC).
+ * Allocate a new stack frame here to remain ABI-compliant in
+ * stashing LR.
+ */
+#define sk_negative_common(SIZE)                               \
+       mflr    r0;                                             \
+       std     r0, 16(r1);                                     \
+       /* R3 goes in parameter space of caller's frame */      \
+       std     r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+       std     r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+       std     r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+       stdu    r1, -BPF_PPC_SLOWPATH_FRAME(r1);                \
+       /* R3 = r_skb, as passed */                             \
+       mr      r4, r_addr;                                     \
+       li      r5, SIZE;                                       \
+       bl      bpf_internal_load_pointer_neg_helper;           \
+       /* R3 != 0 on success */                                \
+       addi    r1, r1, BPF_PPC_SLOWPATH_FRAME;                 \
+       ld      r0, 16(r1);                                     \
+       ld      r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+       ld      r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+       mtlr    r0;                                             \
+       cmpldi  r3, 0;                                          \
+       beq     bpf_error_slow; /* cr0 = EQ */                  \
+       mr      r_addr, r3;                                     \
+       ld      r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+       /* Great success! */
+
+bpf_slow_path_word_neg:
+       lis     r_scratch1,-32  /* SKF_LL_OFF */
+       cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+       blt     bpf_error       /* cr0 = LT */
+       .globl  sk_load_word_negative_offset
+sk_load_word_negative_offset:
+       sk_negative_common(4)
+       lwz     r_A, 0(r_addr)
+       blr
+
+bpf_slow_path_half_neg:
+       lis     r_scratch1,-32  /* SKF_LL_OFF */
+       cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+       blt     bpf_error       /* cr0 = LT */
+       .globl  sk_load_half_negative_offset
+sk_load_half_negative_offset:
+       sk_negative_common(2)
+       lhz     r_A, 0(r_addr)
+       blr
+
+bpf_slow_path_byte_neg:
+       lis     r_scratch1,-32  /* SKF_LL_OFF */
+       cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+       blt     bpf_error       /* cr0 = LT */
+       .globl  sk_load_byte_negative_offset
+sk_load_byte_negative_offset:
+       sk_negative_common(1)
+       lbz     r_A, 0(r_addr)
+       blr
+
+bpf_slow_path_byte_msh_neg:
+       lis     r_scratch1,-32  /* SKF_LL_OFF */
+       cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+       blt     bpf_error       /* cr0 = LT */
+       .globl  sk_load_byte_msh_negative_offset
+sk_load_byte_msh_negative_offset:
+       sk_negative_common(1)
+       lbz     r_X, 0(r_addr)
+       rlwinm  r_X, r_X, 2, 32-4-2, 31-2
+       blr
+
+bpf_error_slow:
+       /* fabricate a cr0 = lt */
+       li      r_scratch1, -1
+       cmpdi   r_scratch1, 0
+bpf_error:
+       /* Entered with cr0 = lt */
+       li      r3, 0
+       /* Generated code will 'blt epilogue', returning 0. */
+       blr

diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 73619d3..2dc8b14 100644 (file)
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -127,6 +127,9 @@ static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx)
        PPC_BLR();
 }
 
+#define CHOOSE_LOAD_FUNC(K, func) \
+       ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
+
 /* Assemble the body code between the prologue & epilogue. */
 static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                              struct codegen_context *ctx,
@@ -391,21 +394,16 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
 
                        /*** Absolute loads from packet header/data ***/
                case BPF_S_LD_W_ABS:
-                       func = sk_load_word;
+                       func = CHOOSE_LOAD_FUNC(K, sk_load_word);
                        goto common_load;
                case BPF_S_LD_H_ABS:
-                       func = sk_load_half;
+                       func = CHOOSE_LOAD_FUNC(K, sk_load_half);
                        goto common_load;
                case BPF_S_LD_B_ABS:
-                       func = sk_load_byte;
+                       func = CHOOSE_LOAD_FUNC(K, sk_load_byte);
                common_load:
-                       /*
-                        * Load from [K].  Reference with the (negative)
-                        * SKF_NET_OFF/SKF_LL_OFF offsets is unsupported.
-                        */
+                       /* Load from [K]. */
                        ctx->seen |= SEEN_DATAREF;
-                       if ((int)K < 0)
-                               return -ENOTSUPP;
                        PPC_LI64(r_scratch1, func);
                        PPC_MTLR(r_scratch1);
                        PPC_LI32(r_addr, K);
@@ -429,7 +427,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                common_load_ind:
                        /*
                         * Load from [X + K].  Negative offsets are tested for
-                        * in the helper functions, and result in a 'ret 0'.
+                        * in the helper functions.
                         */
                        ctx->seen |= SEEN_DATAREF | SEEN_XREG;
                        PPC_LI64(r_scratch1, func);
@@ -443,13 +441,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                        break;
 
                case BPF_S_LDX_B_MSH:
-                       /*
-                        * x86 version drops packet (RET 0) when K<0, whereas
-                        * interpreter does allow K<0 (__load_pointer, special
-                        * ancillary data).  common_load returns ENOTSUPP if K<0,
-                        * so we fall back to interpreter & filter works.
-                        */
-                       func = sk_load_byte_msh;
+                       func = CHOOSE_LOAD_FUNC(K, sk_load_byte_msh);
                        goto common_load;
                        break;
 

diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 9fef530..67dac22 100644 (file)
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
        { .compatible = "fsl,qe", },
        { .compatible = "fsl,cpm2", },
        { .compatible = "fsl,srio", },
+       /* So that the DMA channel nodes can be probed individually: */
+       { .compatible = "fsl,eloplus-dma", },
+       /* For the PMC driver */
+       { .compatible = "fsl,mpc8548-guts", },
+       /* Probably unnecessary? */
+       { .compatible = "gpio-leds", },
        {},
 };
 

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 9a6f044..d208ebc 100644 (file)
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -399,12 +399,6 @@ static int __init board_fixups(void)
 machine_arch_initcall(mpc8568_mds, board_fixups);
 machine_arch_initcall(mpc8569_mds, board_fixups);
 
-static struct of_device_id mpc85xx_ids[] = {
-       { .compatible = "fsl,mpc8548-guts", },
-       { .compatible = "gpio-leds", },
-       {},
-};
-
 static int __init mpc85xx_publish_devices(void)
 {
        if (machine_is(mpc8568_mds))
@@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void)
        if (machine_is(mpc8569_mds))
                simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 
-       mpc85xx_common_publish_devices();
-       of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
-
-       return 0;
+       return mpc85xx_common_publish_devices();
 }
 
 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);

diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index e74b7cd..f700c81 100644 (file)
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void)
        pr_info("Freescale P1022 DS reference board\n");
 }
 
-static struct of_device_id __initdata p1022_ds_ids[] = {
-       /* So that the DMA channel nodes can be probed individually: */
-       { .compatible = "fsl,eloplus-dma", },
-       {},
-};
-
-static int __init p1022_ds_publish_devices(void)
-{
-       mpc85xx_common_publish_devices();
-       return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
-}
-machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
+machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
 

diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index d09f3e8..85825b5 100644 (file)
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -114,7 +114,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
                pr_devel("axon_msi: woff %x roff %x msi %x\n",
                          write_offset, msic->read_offset, msi);
 
-               if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
+               if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
                        generic_handle_irq(msi);
                        msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
                } else {
@@ -276,9 +276,6 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
        if (rc)
                return rc;
 
-       /* We rely on being able to stash a virq in a u16 */
-       BUILD_BUG_ON(NR_IRQS > 65536);
-
        list_for_each_entry(entry, &dev->msi_list, list) {
                virq = irq_create_direct_mapping(msic->irq_domain);
                if (virq == NO_IRQ) {
@@ -392,7 +389,8 @@ static int axon_msi_probe(struct platform_device *device)
        }
        memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
 
-       msic->irq_domain = irq_domain_add_nomap(dn, 0, &msic_host_ops, msic);
+       /* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
+       msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
        if (!msic->irq_domain) {
                printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
                       dn->full_name);

diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
index f9a48af..8c6dc42 100644 (file)
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ b/arch/powerpc/platforms/cell/beat_interrupt.c
@@ -248,6 +248,6 @@ void beatic_deinit_IRQ(void)
 {
        int     i;
 
-       for (i = 1; i < NR_IRQS; i++)
+       for (i = 1; i < nr_irqs; i++)
                beat_destruct_irq_plug(i);
 }

diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c
index 996c5ff..03685a3 100644 (file)
--- a/arch/powerpc/platforms/powermac/low_i2c.c
+++ b/arch/powerpc/platforms/powermac/low_i2c.c
@@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data)
        unsigned long flags;
 
        spin_lock_irqsave(&host->lock, flags);
+
+       /*
+        * If the timer is pending, that means we raced with the
+        * irq, in which case we just return
+        */
+       if (timer_pending(&host->timeout_timer))
+               goto skip;
+
        kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
        if (host->state != state_idle) {
                host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
                add_timer(&host->timeout_timer);
        }
+ skip:
        spin_unlock_irqrestore(&host->lock, flags);
 }
 

diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 66ad93d..c4e6305 100644 (file)
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -57,9 +57,9 @@ static int max_real_irqs;
 
 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
 
-#define NR_MASK_WORDS  ((NR_IRQS + 31) / 32)
-static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+/* The max irq number this driver deals with is 128; see max_irqs */
+static DECLARE_BITMAP(ppc_lost_interrupts, 128);
+static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
 static int pmac_irq_cascade = -1;
 static struct irq_domain *pmac_pic_host;
 

diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index aadbe4f..178a5f3 100644 (file)
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -30,9 +30,9 @@ config PPC_SPLPAR
          two or more partitions.
 
 config EEH
-       bool "PCI Extended Error Handling (EEH)" if EXPERT
+       bool
        depends on PPC_PSERIES && PCI
-       default y if !EXPERT
+       default y
 
 config PSERIES_MSI
        bool

diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index 309d38e..a75e37d 100644 (file)
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
        pr_debug("EEH: Adding device %s\n", pci_name(dev));
 
        dn = pci_device_to_OF_node(dev);
-       edev = pci_dev_to_eeh_dev(dev);
+       edev = of_node_to_eeh_dev(dn);
        if (edev->pdev == dev) {
                pr_debug("EEH: Already referenced !\n");
                return;

diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index d3be961..10386b6 100644 (file)
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -51,8 +51,7 @@
 static intctl_cpm2_t __iomem *cpm2_intctl;
 
 static struct irq_domain *cpm2_pic_host;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
 
 static const u_char irq_to_siureg[] = {
        1, 1, 1, 1, 1, 1, 1, 1,

diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index d5f5416..b724622 100644 (file)
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -18,69 +18,45 @@
 extern int cpm_get_irq(struct pt_regs *regs);
 
 static struct irq_domain *mpc8xx_pic_host;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+static unsigned long mpc8xx_cached_irq_mask;
 static sysconf8xx_t __iomem *siu_reg;
 
-int cpm_get_irq(struct pt_regs *regs);
+static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d)
+{
+       return 0x80000000 >> irqd_to_hwirq(d);
+}
 
 static void mpc8xx_unmask_irq(struct irq_data *d)
 {
-       int     bit, word;
-       unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-       bit = irq_nr & 0x1f;
-       word = irq_nr >> 5;
-
-       ppc_cached_irq_mask[word] |= (1 << (31-bit));
-       out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+       mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
+       out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static void mpc8xx_mask_irq(struct irq_data *d)
 {
-       int     bit, word;
-       unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-       bit = irq_nr & 0x1f;
-       word = irq_nr >> 5;
-
-       ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
-       out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+       mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d);
+       out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static void mpc8xx_ack(struct irq_data *d)
 {
-       int     bit;
-       unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-       bit = irq_nr & 0x1f;
-       out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
+       out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d));
 }
 
 static void mpc8xx_end_irq(struct irq_data *d)
 {
-       int bit, word;
-       unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-       bit = irq_nr & 0x1f;
-       word = irq_nr >> 5;
-
-       ppc_cached_irq_mask[word] |= (1 << (31-bit));
-       out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+       mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
+       out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-       if (flow_type & IRQ_TYPE_EDGE_FALLING) {
-               irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
+       /* only external IRQ senses are programmable */
+       if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) {
                unsigned int siel = in_be32(&siu_reg->sc_siel);
-
-               /* only external IRQ senses are programmable */
-               if ((hw & 1) == 0) {
-                       siel |= (0x80000000 >> hw);
-                       out_be32(&siu_reg->sc_siel, siel);
-                       __irq_set_handler_locked(d->irq, handle_edge_irq);
-               }
+               siel |= mpc8xx_irqd_to_bit(d);
+               out_be32(&siu_reg->sc_siel, siel);
+               __irq_set_handler_locked(d->irq, handle_edge_irq);
        }
        return 0;
 }
@@ -132,6 +108,9 @@ static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
                IRQ_TYPE_EDGE_FALLING,
        };
 
+       if (intspec[0] > 0x1f)
+               return 0;
+
        *out_hwirq = intspec[0];
        if (intsize > 1 && intspec[1] < 4)
                *out_flags = map_pic_senses[intspec[1]];

diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9ac71eb..395af13 100644 (file)
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq)
 }
 
 /* Determine if the linux irq is an IPI */
-static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
+static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
 {
-       unsigned int src = virq_to_hw(irq);
-
        return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 }
 
 /* Determine if the linux irq is a timer */
-static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
+static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
 {
-       unsigned int src = virq_to_hw(irq);
-
        return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 }
 
@@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
        if (src >= mpic->num_sources)
                return -EINVAL;
 
+       vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
+
+       /* We don't support "none" type */
        if (flow_type == IRQ_TYPE_NONE)
-               if (mpic->senses && src < mpic->senses_count)
-                       flow_type = mpic->senses[src];
-       if (flow_type == IRQ_TYPE_NONE)
-               flow_type = IRQ_TYPE_LEVEL_LOW;
+               flow_type = IRQ_TYPE_DEFAULT;
+
+       /* Default: read HW settings */
+       if (flow_type == IRQ_TYPE_DEFAULT) {
+               switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
+                              MPIC_INFO(VECPRI_SENSE_MASK))) {
+                       case MPIC_INFO(VECPRI_SENSE_EDGE) |
+                            MPIC_INFO(VECPRI_POLARITY_POSITIVE):
+                               flow_type = IRQ_TYPE_EDGE_RISING;
+                               break;
+                       case MPIC_INFO(VECPRI_SENSE_EDGE) |
+                            MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
+                               flow_type = IRQ_TYPE_EDGE_FALLING;
+                               break;
+                       case MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                            MPIC_INFO(VECPRI_POLARITY_POSITIVE):
+                               flow_type = IRQ_TYPE_LEVEL_HIGH;
+                               break;
+                       case MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                            MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
+                               flow_type = IRQ_TYPE_LEVEL_LOW;
+                               break;
+               }
+       }
 
+       /* Apply to irq desc */
        irqd_set_trigger_type(d, flow_type);
 
+       /* Apply to HW */
        if (mpic_is_ht_interrupt(mpic, src))
                vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
                        MPIC_VECPRI_SENSE_EDGE;
        else
                vecpri = mpic_type_to_vecpri(mpic, flow_type);
 
-       vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
        vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
                        MPIC_INFO(VECPRI_SENSE_MASK));
        vnew |= vecpri;
@@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
        irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
 
        /* Set default irq type */
-       irq_set_irq_type(virq, IRQ_TYPE_NONE);
+       irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
 
        /* If the MPIC was reset, then all vectors have already been
         * initialized.  Otherwise, a per source lazy initialization
@@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                mpic->num_sources = isu_first + mpic->isu_size;
 }
 
-void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
-{
-       mpic->senses = senses;
-       mpic->senses_count = count;
-}
-
 void __init mpic_init(struct mpic *mpic)
 {
        int i, cpu;
@@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
                return;
 
        raw_spin_lock_irqsave(&mpic_lock, flags);
-       if (mpic_is_ipi(mpic, irq)) {
+       if (mpic_is_ipi(mpic, src)) {
                reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
                        ~MPIC_VECPRI_PRIORITY_MASK;
                mpic_ipi_write(src - mpic->ipi_vecs[0],
                               reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
-       } else if (mpic_is_tm(mpic, irq)) {
+       } else if (mpic_is_tm(mpic, src)) {
                reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
                        ~MPIC_VECPRI_PRIORITY_MASK;
                mpic_tm_write(src - mpic->timer_vecs[0],

diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
index 6e7fa38..483d8fa 100644 (file)
--- a/arch/powerpc/sysdev/mpic_msgr.c
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -27,6 +27,7 @@
 
 static struct mpic_msgr **mpic_msgrs;
 static unsigned int mpic_msgr_count;
+static DEFINE_RAW_SPINLOCK(msgrs_lock);
 
 static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
 {
@@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
        if (reg_num >= mpic_msgr_count)
                return ERR_PTR(-ENODEV);
 
-       raw_spin_lock_irqsave(&msgr->lock, flags);
-       if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
-               msgr = mpic_msgrs[reg_num];
+       raw_spin_lock_irqsave(&msgrs_lock, flags);
+       msgr = mpic_msgrs[reg_num];
+       if (msgr->in_use == MSGR_FREE)
                msgr->in_use = MSGR_INUSE;
-       }
-       raw_spin_unlock_irqrestore(&msgr->lock, flags);
+       raw_spin_unlock_irqrestore(&msgrs_lock, flags);
 
        return msgr;
 }
@@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev)
 
                reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
                msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
-               msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
+               msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
                msgr->in_use = MSGR_FREE;
                msgr->num = i;
                raw_spin_lock_init(&msgr->lock);

diff --git a/arch/powerpc/sysdev/scom.c b/arch/powerpc/sysdev/scom.c
index 49a3ece..702256a 100644 (file)
--- a/arch/powerpc/sysdev/scom.c
+++ b/arch/powerpc/sysdev/scom.c
@@ -22,6 +22,7 @@
 #include <linux/debugfs.h>
 #include <linux/slab.h>
 #include <linux/export.h>
+#include <asm/debug.h>
 #include <asm/prom.h>
 #include <asm/scom.h>
 

diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c
index ea5e204..cd1d18d 100644 (file)
--- a/arch/powerpc/sysdev/xics/xics-common.c
+++ b/arch/powerpc/sysdev/xics/xics-common.c
@@ -188,6 +188,7 @@ void xics_migrate_irqs_away(void)
 {
        int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
        unsigned int irq, virq;
+       struct irq_desc *desc;
 
        /* If we used to be the default server, move to the new "boot_cpuid" */
        if (hw_cpu == xics_default_server)
@@ -202,8 +203,7 @@ void xics_migrate_irqs_away(void)
        /* Allow IPIs again... */
        icp_ops->set_priority(DEFAULT_PRIORITY);
 
-       for_each_irq(virq) {
-               struct irq_desc *desc;
+       for_each_irq_desc(virq, desc) {
                struct irq_chip *chip;
                long server;
                unsigned long flags;
@@ -212,9 +212,8 @@ void xics_migrate_irqs_away(void)
                /* We can't set affinity on ISA interrupts */
                if (virq < NUM_ISA_INTERRUPTS)
                        continue;
-               desc = irq_to_desc(virq);
                /* We only need to migrate enabled IRQS */
-               if (!desc || !desc->action)
+               if (!desc->action)
                        continue;
                if (desc->irq_data.domain != xics_host)
                        continue;

diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 37f2f4a..f4c1c20 100644 (file)
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -11,7 +11,7 @@
 #include <linux/types.h>
 #include <asm/cmpxchg.h>
 
-#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
+#define ATOMIC_INIT(i) { (i) }
 
 #define atomic_read(v)         (*(volatile int *)&(v)->counter)
 #define atomic_set(v,i)                ((v)->counter = (i))

diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 324eef9..e99b104 100644 (file)
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -86,7 +86,7 @@ static noinline int vmalloc_fault(unsigned long address)
        pte_t *pte_k;
 
        /* Make sure we are in vmalloc/module/P3 area: */
-       if (!(address >= VMALLOC_START && address < P3_ADDR_MAX))
+       if (!(address >= P3SEG && address < P3_ADDR_MAX))
                return -1;
 
        /*

diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 5d5a635..32e6cbe 100644 (file)
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -47,8 +47,8 @@ struct pci_controller {
  */
 #define PCI_DMA_BUS_IS_PHYS     1
 
-int __devinit tile_pci_init(void);
-int __devinit pcibios_init(void);
+int __init tile_pci_init(void);
+int __init pcibios_init(void);
 
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
 

diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index a1bb59e..b56d12b 100644 (file)
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -141,7 +141,7 @@ static int __devinit tile_init_irqs(int controller_id,
  *
  * Returns the number of controllers discovered.
  */
-int __devinit tile_pci_init(void)
+int __init tile_pci_init(void)
 {
        int i;
 
@@ -287,7 +287,7 @@ static void __devinit fixup_read_and_payload_sizes(void)
  * The controllers have been set up by the time we get here, by a call to
  * tile_pci_init.
  */
-int __devinit pcibios_init(void)
+int __init pcibios_init(void)
 {
        int i;
 

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1d14cc6..c9866b0 100644 (file)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -81,7 +81,7 @@ config X86
        select CLKEVT_I8253
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
        select GENERIC_IOMAP
-       select DCACHE_WORD_ACCESS if !DEBUG_PAGEALLOC
+       select DCACHE_WORD_ACCESS
 
 config INSTRUCTION_DECODER
        def_bool (KPROBES || PERF_EVENTS)

diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index a055993..c85e3ac 100644 (file)
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -33,6 +33,9 @@
        __HEAD
 ENTRY(startup_32)
 #ifdef CONFIG_EFI_STUB
+       jmp     preferred_addr
+
+       .balign 0x10
        /*
         * We don't need the return address, so set up the stack so
         * efi_main() can find its arugments.
@@ -41,12 +44,17 @@ ENTRY(startup_32)
 
        call    efi_main
        cmpl    $0, %eax
-       je      preferred_addr
        movl    %eax, %esi
-       call    1f
+       jne     2f
 1:
+       /* EFI init failed, so hang. */
+       hlt
+       jmp     1b
+2:
+       call    3f
+3:
        popl    %eax
-       subl    $1b, %eax
+       subl    $3b, %eax
        subl    BP_pref_address(%esi), %eax
        add     BP_code32_start(%esi), %eax
        leal    preferred_addr(%eax), %eax

diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 558d76c..87e03a1 100644 (file)
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -200,18 +200,28 @@ ENTRY(startup_64)
         * entire text+data+bss and hopefully all of memory.
         */
 #ifdef CONFIG_EFI_STUB
-       pushq   %rsi
+       /*
+        * The entry point for the PE/COFF executable is 0x210, so only
+        * legacy boot loaders will execute this jmp.
+        */
+       jmp     preferred_addr
+
+       .org 0x210
        mov     %rcx, %rdi
        mov     %rdx, %rsi
        call    efi_main
-       popq    %rsi
-       cmpq    $0,%rax
-       je      preferred_addr
        movq    %rax,%rsi
-       call    1f
+       cmpq    $0,%rax
+       jne     2f
 1:
+       /* EFI init failed, so hang. */
+       hlt
+       jmp     1b
+2:
+       call    3f
+3:
        popq    %rax
-       subq    $1b, %rax
+       subq    $3b, %rax
        subq    BP_pref_address(%rsi), %rax
        add     BP_code32_start(%esi), %eax
        leaq    preferred_addr(%rax), %rax

diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/boot/compressed/relocs.c
index d3c0b02..fb7117a 100644 (file)
--- a/arch/x86/boot/compressed/relocs.c
+++ b/arch/x86/boot/compressed/relocs.c
@@ -403,13 +403,11 @@ static void print_absolute_symbols(void)
        for (i = 0; i < ehdr.e_shnum; i++) {
                struct section *sec = &secs[i];
                char *sym_strtab;
-               Elf32_Sym *sh_symtab;
                int j;
 
                if (sec->shdr.sh_type != SHT_SYMTAB) {
                        continue;
                }
-               sh_symtab = sec->symtab;
                sym_strtab = sec->link->strtab;
                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) {
                        Elf32_Sym *sym;

diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index ed54976..24443a3 100644 (file)
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -205,8 +205,13 @@ int main(int argc, char ** argv)
        put_unaligned_le32(file_sz, &buf[pe_header + 0x50]);
 
 #ifdef CONFIG_X86_32
-       /* Address of entry point */
-       put_unaligned_le32(i, &buf[pe_header + 0x28]);
+       /*
+        * Address of entry point.
+        *
+        * The EFI stub entry point is +16 bytes from the start of
+        * the .text section.
+        */
+       put_unaligned_le32(i + 16, &buf[pe_header + 0x28]);
 
        /* .text size */
        put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]);
@@ -217,9 +222,11 @@ int main(int argc, char ** argv)
        /*
         * Address of entry point. startup_32 is at the beginning and
         * the 64-bit entry point (startup_64) is always 512 bytes
-        * after.
+        * after. The EFI stub entry point is 16 bytes after that, as
+        * the first instruction allows legacy loaders to jump over
+        * the EFI stub initialisation
         */
-       put_unaligned_le32(i + 512, &buf[pe_header + 0x28]);
+       put_unaligned_le32(i + 528, &buf[pe_header + 0x28]);
 
        /* .text size */
        put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]);

diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index 4824fb4..07b3a68 100644 (file)
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -294,8 +294,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
 
        /* OK, This is the point of no return */
        set_personality(PER_LINUX);
-       set_thread_flag(TIF_IA32);
-       current->mm->context.ia32_compat = 1;
+       set_personality_ia32(false);
 
        setup_new_exec(bprm);
 

diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index 3427b77..7ef7c30 100644 (file)
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -7,9 +7,9 @@
 #else
 # ifdef __i386__
 #  include "posix_types_32.h"
-# elif defined(__LP64__)
-#  include "posix_types_64.h"
-# else
+# elif defined(__ILP32__)
 #  include "posix_types_x32.h"
+# else
+#  include "posix_types_64.h"
 # endif
 #endif

diff --git a/arch/x86/include/asm/sigcontext.h b/arch/x86/include/asm/sigcontext.h
index 4a08538..5ca71c0 100644 (file)
--- a/arch/x86/include/asm/sigcontext.h
+++ b/arch/x86/include/asm/sigcontext.h
@@ -257,7 +257,7 @@ struct sigcontext {
        __u64 oldmask;
        __u64 cr2;
        struct _fpstate __user *fpstate;        /* zero when no FPU context */
-#ifndef __LP64__
+#ifdef __ILP32__
        __u32 __fpstate_pad;
 #endif
        __u64 reserved1[8];

diff --git a/arch/x86/include/asm/siginfo.h b/arch/x86/include/asm/siginfo.h
index fc1aa55..34c47b3 100644 (file)
--- a/arch/x86/include/asm/siginfo.h
+++ b/arch/x86/include/asm/siginfo.h
@@ -2,7 +2,13 @@
 #define _ASM_X86_SIGINFO_H
 
 #ifdef __x86_64__
-# define __ARCH_SI_PREAMBLE_SIZE       (4 * sizeof(int))
+# ifdef __ILP32__ /* x32 */
+typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
+#  define __ARCH_SI_CLOCK_T            __kernel_si_clock_t
+#  define __ARCH_SI_ATTRIBUTES         __attribute__((aligned(8)))
+# else /* x86-64 */
+#  define __ARCH_SI_PREAMBLE_SIZE      (4 * sizeof(int))
+# endif
 #endif
 
 #include <asm-generic/siginfo.h>

diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h
index 37cdc9d..4437001 100644 (file)
--- a/arch/x86/include/asm/unistd.h
+++ b/arch/x86/include/asm/unistd.h
@@ -63,10 +63,10 @@
 #else
 # ifdef __i386__
 #  include <asm/unistd_32.h>
-# elif defined(__LP64__)
-#  include <asm/unistd_64.h>
-# else
+# elif defined(__ILP32__)
 #  include <asm/unistd_x32.h>
+# else
+#  include <asm/unistd_64.h>
 # endif
 #endif
 

diff --git a/arch/x86/include/asm/word-at-a-time.h b/arch/x86/include/asm/word-at-a-time.h
index 6fe6767..e58f03b 100644 (file)
--- a/arch/x86/include/asm/word-at-a-time.h
+++ b/arch/x86/include/asm/word-at-a-time.h
@@ -43,4 +43,37 @@ static inline unsigned long has_zero(unsigned long a)
        return ((a - REPEAT_BYTE(0x01)) & ~a) & REPEAT_BYTE(0x80);
 }
 
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+       unsigned long ret, dummy;
+
+       asm(
+               "1:\tmov %2,%0\n"
+               "2:\n"
+               ".section .fixup,\"ax\"\n"
+               "3:\t"
+               "lea %2,%1\n\t"
+               "and %3,%1\n\t"
+               "mov (%1),%0\n\t"
+               "leal %2,%%ecx\n\t"
+               "andl %4,%%ecx\n\t"
+               "shll $3,%%ecx\n\t"
+               "shr %%cl,%0\n\t"
+               "jmp 2b\n"
+               ".previous\n"
+               _ASM_EXTABLE(1b, 3b)
+               :"=&r" (ret),"=&c" (dummy)
+               :"m" (*(unsigned long *)addr),
+                "i" (-sizeof(unsigned long)),
+                "i" (sizeof(unsigned long)-1));
+       return ret;
+}
+
 #endif /* _ASM_WORD_AT_A_TIME_H */

diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index baaca8d..764b66a 100644 (file)
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -195,6 +195,5 @@ extern struct x86_msi_ops x86_msi;
 
 extern void x86_init_noop(void);
 extern void x86_init_uint_noop(unsigned int unused);
-extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node);
 
 #endif

diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 103b6ab..146a49c 100644 (file)
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags;
 static char temp_stack[4096];
 #endif
 
+asmlinkage void acpi_enter_s3(void)
+{
+       acpi_enter_sleep_state(3, wake_sleep_flags);
+}
 /**
  * acpi_suspend_lowlevel - save kernel state
  *

diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h
index 416d4be..d68677a 100644 (file)
--- a/arch/x86/kernel/acpi/sleep.h
+++ b/arch/x86/kernel/acpi/sleep.h
@@ -3,12 +3,16 @@
  */
 
 #include <asm/trampoline.h>
+#include <linux/linkage.h>
 
 extern unsigned long saved_video_mode;
 extern long saved_magic;
 
 extern int wakeup_pmode_return;
 
+extern u8 wake_sleep_flags;
+extern asmlinkage void acpi_enter_s3(void);
+
 extern unsigned long acpi_copy_wakeup_routine(unsigned long);
 extern void wakeup_long64(void);
 

diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S
index 13ab720..7261083 100644 (file)
--- a/arch/x86/kernel/acpi/wakeup_32.S
+++ b/arch/x86/kernel/acpi/wakeup_32.S
@@ -74,9 +74,7 @@ restore_registers:
 ENTRY(do_suspend_lowlevel)
        call    save_processor_state
        call    save_registers
-       pushl   $3
-       call    acpi_enter_sleep_state
-       addl    $4, %esp
+       call    acpi_enter_s3
 
 #      In case of S3 failure, we'll emerge here.  Jump
 #      to ret_point to recover

diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S
index 8ea5164..014d1d2 100644 (file)
--- a/arch/x86/kernel/acpi/wakeup_64.S
+++ b/arch/x86/kernel/acpi/wakeup_64.S
@@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel)
        movq    %rsi, saved_rsi
 
        addq    $8, %rsp
-       movl    $3, %edi
-       xorl    %eax, %eax
-       call    acpi_enter_sleep_state
+       call    acpi_enter_s3
        /* in case something went wrong, restore the machine status and go on */
        jmp     resume_point
 

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 11544d8..edc2448 100644 (file)
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1637,9 +1637,11 @@ static int __init apic_verify(void)
        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 
        /* The BIOS may have set up the APIC at some other address */
-       rdmsr(MSR_IA32_APICBASE, l, h);
-       if (l & MSR_IA32_APICBASE_ENABLE)
-               mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+       if (boot_cpu_data.x86 >= 6) {
+               rdmsr(MSR_IA32_APICBASE, l, h);
+               if (l & MSR_IA32_APICBASE_ENABLE)
+                       mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+       }
 
        pr_info("Found and enabled local APIC!\n");
        return 0;
@@ -1657,13 +1659,15 @@ int __init apic_force_enable(unsigned long addr)
         * MSR. This can only be done in software for Intel P6 or later
         * and AMD K7 (Model > 1) or later.
         */
-       rdmsr(MSR_IA32_APICBASE, l, h);
-       if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-               pr_info("Local APIC disabled by BIOS -- reenabling.\n");
-               l &= ~MSR_IA32_APICBASE_BASE;
-               l |= MSR_IA32_APICBASE_ENABLE | addr;
-               wrmsr(MSR_IA32_APICBASE, l, h);
-               enabled_via_apicbase = 1;
+       if (boot_cpu_data.x86 >= 6) {
+               rdmsr(MSR_IA32_APICBASE, l, h);
+               if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+                       pr_info("Local APIC disabled by BIOS -- reenabling.\n");
+                       l &= ~MSR_IA32_APICBASE_BASE;
+                       l |= MSR_IA32_APICBASE_ENABLE | addr;
+                       wrmsr(MSR_IA32_APICBASE, l, h);
+                       enabled_via_apicbase = 1;
+               }
        }
        return apic_verify();
 }
@@ -2209,10 +2213,12 @@ static void lapic_resume(void)
                 * FIXME! This will be wrong if we ever support suspend on
                 * SMP! We'll need to do this as part of the CPU restore!
                 */
-               rdmsr(MSR_IA32_APICBASE, l, h);
-               l &= ~MSR_IA32_APICBASE_BASE;
-               l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
-               wrmsr(MSR_IA32_APICBASE, l, h);
+               if (boot_cpu_data.x86 >= 6) {
+                       rdmsr(MSR_IA32_APICBASE, l, h);
+                       l &= ~MSR_IA32_APICBASE_BASE;
+                       l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                       wrmsr(MSR_IA32_APICBASE, l, h);
+               }
        }
 
        maxlvt = lapic_get_maxlvt();

diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 899803e..23e7542 100644 (file)
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -207,8 +207,11 @@ static void __init map_csrs(void)
 
 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 {
-       c->phys_proc_id = node;
-       per_cpu(cpu_llc_id, smp_processor_id()) = node;
+
+       if (c->phys_proc_id != node) {
+               c->phys_proc_id = node;
+               per_cpu(cpu_llc_id, smp_processor_id()) = node;
+       }
 }
 
 static int __init numachip_system_init(void)

diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index 8a778db..991e315 100644 (file)
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
        if (x2apic_phys)
                return x2apic_enabled();
+       else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
+               (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
+               x2apic_enabled()) {
+               printk(KERN_DEBUG "System requires x2apic physical mode\n");
+               return 1;
+       }
        else
                return 0;
 }

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 0a44b90..146bb62 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -26,7 +26,8 @@
  *     contact AMD for precise details and a CPU swap.
  *
  *     See     http://www.multimania.com/poulot/k6bug.html
- *             http://www.amd.com/K6/k6docs/revgd.html
+ *     and     section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
+ *             (Publication # 21266  Issue Date: August 1998)
  *
  *     The following test is erm.. interesting. AMD neglected to up
  *     the chip setting when fixing the bug but they also tweaked some
@@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
                                "system stability may be impaired when more than 32 MB are used.\n");
                else
                        printk(KERN_CONT "probably OK (after B9730xxxx).\n");
-               printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
        }
 
        /* K6 with old style WHCR */
@@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
                node = per_cpu(cpu_llc_id, cpu);
 
        /*
-        * If core numbers are inconsistent, it's likely a multi-fabric platform,
-        * so invoke platform-specific handler
+        * On multi-fabric platform (e.g. Numascale NumaChip) a
+        * platform-specific handler needs to be called to fixup some
+        * IDs of the CPU.
         */
-       if (c->phys_proc_id != node)
+       if (x86_cpuinit.fixup_cpu_id)
                x86_cpuinit.fixup_cpu_id(c, node);
 
        if (!node_online(node)) {
@@ -579,6 +580,24 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                }
        }
 
+       /* re-enable TopologyExtensions if switched off by BIOS */
+       if ((c->x86 == 0x15) &&
+           (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
+           !cpu_has(c, X86_FEATURE_TOPOEXT)) {
+               u64 val;
+
+               if (!rdmsrl_amd_safe(0xc0011005, &val)) {
+                       val |= 1ULL << 54;
+                       wrmsrl_amd_safe(0xc0011005, val);
+                       rdmsrl(0xc0011005, val);
+                       if (val & (1ULL << 54)) {
+                               set_cpu_cap(c, X86_FEATURE_TOPOEXT);
+                               printk(KERN_INFO FW_INFO "CPU: Re-enabling "
+                                 "disabled Topology Extensions Support\n");
+                       }
+               }
+       }
+
        cpu_detect_cache_sizes(c);
 
        /* Multi core CPU? */

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 67e2583..cf79302 100644 (file)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1163,15 +1163,6 @@ static void dbg_restore_debug_regs(void)
 #endif /* ! CONFIG_KGDB */
 
 /*
- * Prints an error where the NUMA and configured core-number mismatch and the
- * platform didn't override this to fix it up
- */
-void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
-{
-       pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
-}
-
-/*
  * cpu_init() initializes state that is per-CPU. Some data is already
  * initialized (naturally) in the bootstrap process, such as the GDT
  * and IDT. We reload them nevertheless, this function acts as a

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 73d08ed..b8f3653 100644 (file)
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
        /*  check if @slot is already used or the index is already disabled */
        ret = amd_get_l3_disable_slot(nb, slot);
        if (ret >= 0)
-               return -EINVAL;
+               return -EEXIST;
 
        if (index > nb->l3_cache.indices)
                return -EINVAL;
 
        /* check whether the other slot has disabled the same index already */
        if (index == amd_get_l3_disable_slot(nb, !slot))
-               return -EINVAL;
+               return -EEXIST;
 
        amd_l3_disable_index(nb, cpu, slot, index);
 
@@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
        err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
        if (err) {
                if (err == -EEXIST)
-                       printk(KERN_WARNING "L3 disable slot %d in use!\n",
-                                           slot);
+                       pr_warning("L3 slot %d in use/index already disabled!\n",
+                                  slot);
                return err;
        }
        return count;

diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 7734bcb..2d6e649 100644 (file)
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk)
        if (tsk_used_math(tsk)) {
                if (HAVE_HWFP && tsk == current)
                        unlazy_fpu(tsk);
+               tsk->thread.fpu.last_cpu = ~0;
                return 0;
        }
 

diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 73465aa..8a2ce8f 100644 (file)
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 {
        struct cpuinfo_x86 *c = &cpu_data(cpu);
 
-       if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
-               pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
-               return -1;
-       }
-
        csig->rev = c->microcode;
        pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
 
@@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = {
 
 struct microcode_ops * __init init_amd_microcode(void)
 {
+       struct cpuinfo_x86 *c = &cpu_data(0);
+
+       if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
+               pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
+               return NULL;
+       }
+
        patch = (void *)get_zeroed_page(GFP_KERNEL);
        if (!patch)
                return NULL;

diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 87a0f86..c9bda6d 100644 (file)
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif)
        if (err)
                return err;
 
-       if (microcode_init_cpu(cpu) == UCODE_ERROR) {
-               sysfs_remove_group(&dev->kobj, &mc_attr_group);
+       if (microcode_init_cpu(cpu) == UCODE_ERROR)
                return -EINVAL;
-       }
 
        return err;
 }
@@ -528,11 +526,11 @@ static int __init microcode_init(void)
                microcode_ops = init_intel_microcode();
        else if (c->x86_vendor == X86_VENDOR_AMD)
                microcode_ops = init_amd_microcode();
-
-       if (!microcode_ops) {
+       else
                pr_err("no support for this CPU vendor\n");
+
+       if (!microcode_ops)
                return -ENODEV;
-       }
 
        microcode_pdev = platform_device_register_simple("microcode", -1,
                                                         NULL, 0);

diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index e9f265f..9cf71d0 100644 (file)
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -93,7 +93,6 @@ struct x86_init_ops x86_init __initdata = {
 struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
        .early_percpu_clock_init        = x86_init_noop,
        .setup_percpu_clockev           = setup_secondary_APIC_clock,
-       .fixup_cpu_id                   = x86_default_fixup_cpu_id,
 };
 
 static void default_nmi_init(void) { };

diff --git a/arch/x86/platform/geode/net5501.c b/arch/x86/platform/geode/net5501.c
index 66d377e..646e3b5 100644 (file)
--- a/arch/x86/platform/geode/net5501.c
+++ b/arch/x86/platform/geode/net5501.c
@@ -63,7 +63,7 @@ static struct gpio_led net5501_leds[] = {
                .name = "net5501:1",
                .gpio = 6,
                .default_trigger = "default-on",
-               .active_low = 1,
+               .active_low = 0,
        },
 };
 

diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index e0a3723..e31bcd8 100644 (file)
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -805,7 +805,7 @@ void intel_scu_devices_create(void)
                } else
                        i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
        }
-       intel_scu_notifier_post(SCU_AVAILABLE, 0L);
+       intel_scu_notifier_post(SCU_AVAILABLE, NULL);
 }
 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
 
@@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void)
 {
        int i;
 
-       intel_scu_notifier_post(SCU_DOWN, 0L);
+       intel_scu_notifier_post(SCU_DOWN, NULL);
 
        for (i = 0; i < ipc_next_dev; i++)
                platform_device_del(ipc_devs[i]);

diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 4f51beb..a8f8844 100644 (file)
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -261,7 +261,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 
 static bool __init xen_check_mwait(void)
 {
-#ifdef CONFIG_ACPI
+#if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \
+       !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE)
        struct xen_platform_op op = {
                .cmd                    = XENPF_set_processor_pminfo,
                .u.set_pminfo.id        = -1,
@@ -349,7 +350,6 @@ static void __init xen_init_cpuid_mask(void)
        /* Xen will set CR4.OSXSAVE if supported and not disabled by force */
        if ((cx & xsave_mask) != xsave_mask)
                cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
-
        if (xen_check_mwait())
                cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
 }

diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 5fac691..0503c0c 100644 (file)
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void)
 static void __init xen_filter_cpu_maps(void)
 {
        int i, rc;
+       unsigned int subtract = 0;
 
        if (!xen_initial_domain())
                return;
@@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void)
                } else {
                        set_cpu_possible(i, false);
                        set_cpu_present(i, false);
+                       subtract++;
                }
        }
+#ifdef CONFIG_HOTPLUG_CPU
+       /* This is akin to using 'nr_cpus' on the Linux command line.
+        * Which is OK as when we use 'dom0_max_vcpus=X' we can only
+        * have up to X, while nr_cpu_ids is greater than X. This
+        * normally is not a problem, except when CPU hotplugging
+        * is involved and then there might be more than X CPUs
+        * in the guest - which will not work as there is no
+        * hypercall to expand the max number of VCPUs an already
+        * running guest has. So cap it up to X. */
+       if (subtract)
+               nr_cpu_ids = nr_cpu_ids - subtract;
+#endif
+
 }
 
 static void __init xen_smp_prepare_boot_cpu(void)

diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S
index 79d7362..3e45aa0 100644 (file)
--- a/arch/x86/xen/xen-asm.S
+++ b/arch/x86/xen/xen-asm.S
@@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct)
 
        /* check for unmasked and pending */
        cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
-       jz 1f
+       jnz 1f
 2:     call check_events
 1:
 ENDPATCH(xen_restore_fl_direct)

diff --git a/arch/xtensa/include/asm/hardirq.h b/arch/xtensa/include/asm/hardirq.h
index 26664ce..91695a1 100644 (file)
--- a/arch/xtensa/include/asm/hardirq.h
+++ b/arch/xtensa/include/asm/hardirq.h
@@ -11,9 +11,6 @@
 #ifndef _XTENSA_HARDIRQ_H
 #define _XTENSA_HARDIRQ_H
 
-void ack_bad_irq(unsigned int irq);
-#define ack_bad_irq ack_bad_irq
-
 #include <asm-generic/hardirq.h>
 
 #endif /* _XTENSA_HARDIRQ_H */

diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index d04cd3a..4beb43c 100644 (file)
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -14,6 +14,7 @@
 #ifdef __KERNEL__
 #include <asm/byteorder.h>
 #include <asm/page.h>
+#include <linux/bug.h>
 #include <linux/kernel.h>
 
 #include <linux/types.h>

diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c
index b69b000..d78869a 100644 (file)
--- a/arch/xtensa/kernel/signal.c
+++ b/arch/xtensa/kernel/signal.c
@@ -496,6 +496,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
 
        if (signr > 0) {
+               int ret;
 
                /* Are we from a system call? */
 

diff --git a/drivers/acpi/power.c b/drivers/acpi/power.c
index 7049a7d..330bb4d 100644 (file)
--- a/drivers/acpi/power.c
+++ b/drivers/acpi/power.c
@@ -631,7 +631,7 @@ int acpi_power_get_inferred_state(struct acpi_device *device, int *state)
         * We know a device's inferred power state when all the resources
         * required for a given D-state are 'on'.
         */
-       for (i = ACPI_STATE_D0; i < ACPI_STATE_D3; i++) {
+       for (i = ACPI_STATE_D0; i < ACPI_STATE_D3_HOT; i++) {
                list = &device->power.states[i].resources;
                if (list->count < 1)
                        continue;

diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 767e2dc..7417267 100644 (file)
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -869,7 +869,7 @@ static int acpi_bus_get_power_flags(struct acpi_device *device)
        /*
         * Enumerate supported power management states
         */
-       for (i = ACPI_STATE_D0; i <= ACPI_STATE_D3; i++) {
+       for (i = ACPI_STATE_D0; i <= ACPI_STATE_D3_HOT; i++) {
                struct acpi_device_power_state *ps = &device->power.states[i];
                char object_name[5] = { '_', 'P', 'R', '0' + i, '\0' };
 
@@ -884,21 +884,18 @@ static int acpi_bus_get_power_flags(struct acpi_device *device)
                                acpi_bus_add_power_resource(ps->resources.handles[j]);
                }
 
-               /* The exist of _PR3 indicates D3Cold support */
-               if (i == ACPI_STATE_D3) {
-                       status = acpi_get_handle(device->handle, object_name, &handle);
-                       if (ACPI_SUCCESS(status))
-                               device->power.states[ACPI_STATE_D3_COLD].flags.valid = 1;
-               }
-
                /* Evaluate "_PSx" to see if we can do explicit sets */
                object_name[2] = 'S';
                status = acpi_get_handle(device->handle, object_name, &handle);
                if (ACPI_SUCCESS(status))
                        ps->flags.explicit_set = 1;
 
-               /* State is valid if we have some power control */
-               if (ps->resources.count || ps->flags.explicit_set)
+               /*
+                * State is valid if there are means to put the device into it.
+                * D3hot is only valid if _PR3 present.
+                */
+               if (ps->resources.count ||
+                   (ps->flags.explicit_set && i < ACPI_STATE_D3_HOT))
                        ps->flags.valid = 1;
 
                ps->power = -1; /* Unknown - driver assigned */

diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
index 1d661b5..eb6fd23 100644 (file)
--- a/drivers/acpi/sleep.c
+++ b/drivers/acpi/sleep.c
@@ -28,23 +28,33 @@
 #include "internal.h"
 #include "sleep.h"
 
+u8 wake_sleep_flags = ACPI_NO_OPTIONAL_METHODS;
 static unsigned int gts, bfs;
-module_param(gts, uint, 0644);
-module_param(bfs, uint, 0644);
-MODULE_PARM_DESC(gts, "Enable evaluation of _GTS on suspend.");
-MODULE_PARM_DESC(bfs, "Enable evaluation of _BFS on resume".);
-
-static u8 wake_sleep_flags(void)
+static int set_param_wake_flag(const char *val, struct kernel_param *kp)
 {
-       u8 flags = ACPI_NO_OPTIONAL_METHODS;
+       int ret = param_set_int(val, kp);
 
-       if (gts)
-               flags |= ACPI_EXECUTE_GTS;
-       if (bfs)
-               flags |= ACPI_EXECUTE_BFS;
+       if (ret)
+               return ret;
 
-       return flags;
+       if (kp->arg == (const char *)&gts) {
+               if (gts)
+                       wake_sleep_flags |= ACPI_EXECUTE_GTS;
+               else
+                       wake_sleep_flags &= ~ACPI_EXECUTE_GTS;
+       }
+       if (kp->arg == (const char *)&bfs) {
+               if (bfs)
+                       wake_sleep_flags |= ACPI_EXECUTE_BFS;
+               else
+                       wake_sleep_flags &= ~ACPI_EXECUTE_BFS;
+       }
+       return ret;
 }
+module_param_call(gts, set_param_wake_flag, param_get_int, &gts, 0644);
+module_param_call(bfs, set_param_wake_flag, param_get_int, &bfs, 0644);
+MODULE_PARM_DESC(gts, "Enable evaluation of _GTS on suspend.");
+MODULE_PARM_DESC(bfs, "Enable evaluation of _BFS on resume".);
 
 static u8 sleep_states[ACPI_S_STATE_COUNT];
 
@@ -263,7 +273,6 @@ static int acpi_suspend_enter(suspend_state_t pm_state)
 {
        acpi_status status = AE_OK;
        u32 acpi_state = acpi_target_sleep_state;
-       u8 flags = wake_sleep_flags();
        int error;
 
        ACPI_FLUSH_CPU_CACHE();
@@ -271,7 +280,7 @@ static int acpi_suspend_enter(suspend_state_t pm_state)
        switch (acpi_state) {
        case ACPI_STATE_S1:
                barrier();
-               status = acpi_enter_sleep_state(acpi_state, flags);
+               status = acpi_enter_sleep_state(acpi_state, wake_sleep_flags);
                break;
 
        case ACPI_STATE_S3:
@@ -286,7 +295,7 @@ static int acpi_suspend_enter(suspend_state_t pm_state)
        acpi_write_bit_register(ACPI_BITREG_SCI_ENABLE, 1);
 
        /* Reprogram control registers and execute _BFS */
-       acpi_leave_sleep_state_prep(acpi_state, flags);
+       acpi_leave_sleep_state_prep(acpi_state, wake_sleep_flags);
 
        /* ACPI 3.0 specs (P62) says that it's the responsibility
         * of the OSPM to clear the status bit [ implying that the
@@ -550,30 +559,27 @@ static int acpi_hibernation_begin(void)
 
 static int acpi_hibernation_enter(void)
 {
-       u8 flags = wake_sleep_flags();
        acpi_status status = AE_OK;
 
        ACPI_FLUSH_CPU_CACHE();
 
        /* This shouldn't return.  If it returns, we have a problem */
-       status = acpi_enter_sleep_state(ACPI_STATE_S4, flags);
+       status = acpi_enter_sleep_state(ACPI_STATE_S4, wake_sleep_flags);
        /* Reprogram control registers and execute _BFS */
-       acpi_leave_sleep_state_prep(ACPI_STATE_S4, flags);
+       acpi_leave_sleep_state_prep(ACPI_STATE_S4, wake_sleep_flags);
 
        return ACPI_SUCCESS(status) ? 0 : -EFAULT;
 }
 
 static void acpi_hibernation_leave(void)
 {
-       u8 flags = wake_sleep_flags();
-
        /*
         * If ACPI is not enabled by the BIOS and the boot kernel, we need to
         * enable it here.
         */
        acpi_enable();
        /* Reprogram control registers and execute _BFS */
-       acpi_leave_sleep_state_prep(ACPI_STATE_S4, flags);
+       acpi_leave_sleep_state_prep(ACPI_STATE_S4, wake_sleep_flags);
        /* Check the hardware signature */
        if (facs && s4_hardware_signature != facs->hardware_signature) {
                printk(KERN_EMERG "ACPI: Hardware changed while hibernated, "
@@ -828,12 +834,10 @@ static void acpi_power_off_prepare(void)
 
 static void acpi_power_off(void)
 {
-       u8 flags = wake_sleep_flags();
-
        /* acpi_sleep_prepare(ACPI_STATE_S5) should have already been called */
        printk(KERN_DEBUG "%s called\n", __func__);
        local_irq_disable();
-       acpi_enter_sleep_state(ACPI_STATE_S5, flags);
+       acpi_enter_sleep_state(ACPI_STATE_S5, wake_sleep_flags);
 }
 
 /*

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 79a1e9d..ebaf67e 100644 (file)
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -394,6 +394,8 @@ static const struct pci_device_id ahci_pci_tbl[] = {
          .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
        { PCI_DEVICE(0x1b4b, 0x9125),
          .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
+       { PCI_DEVICE(0x1b4b, 0x917a),
+         .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
        { PCI_DEVICE(0x1b4b, 0x91a3),
          .driver_data = board_ahci_yes_fbs },
 

diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 0c86c77..9e419e1 100644 (file)
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -280,6 +280,7 @@ static struct dev_pm_ops ahci_pm_ops = {
 
 static const struct of_device_id ahci_of_match[] = {
        { .compatible = "calxeda,hb-ahci", },
+       { .compatible = "snps,spear-ahci", },
        {},
 };
 MODULE_DEVICE_TABLE(of, ahci_of_match);

diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 28db50b..23763a1 100644 (file)
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -95,7 +95,7 @@ static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
 static void ata_dev_xfermask(struct ata_device *dev);
 static unsigned long ata_dev_blacklisted(const struct ata_device *dev);
 
-atomic_t ata_print_id = ATOMIC_INIT(1);
+atomic_t ata_print_id = ATOMIC_INIT(0);
 
 struct ata_force_param {
        const char      *name;

diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index c61316e..d1fbd59 100644 (file)
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -3501,7 +3501,8 @@ static int ata_count_probe_trials_cb(struct ata_ering_entry *ent, void *void_arg
        u64 now = get_jiffies_64();
        int *trials = void_arg;
 
-       if (ent->timestamp < now - min(now, interval))
+       if ((ent->eflags & ATA_EFLAG_OLD_ER) ||
+           (ent->timestamp < now - min(now, interval)))
                return -1;
 
        (*trials)++;

diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 93dabdc..2222635 100644 (file)
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -3399,7 +3399,8 @@ int ata_scsi_add_hosts(struct ata_host *host, struct scsi_host_template *sht)
                 */
                shost->max_host_blocked = 1;
 
-               rc = scsi_add_host(ap->scsi_host, &ap->tdev);
+               rc = scsi_add_host_with_dma(ap->scsi_host,
+                                               &ap->tdev, ap->host->dev);
                if (rc)
                        goto err_add;
        }
@@ -3838,18 +3839,25 @@ void ata_sas_port_stop(struct ata_port *ap)
 }
 EXPORT_SYMBOL_GPL(ata_sas_port_stop);
 
-int ata_sas_async_port_init(struct ata_port *ap)
+/**
+ * ata_sas_async_probe - simply schedule probing and return
+ * @ap: Port to probe
+ *
+ * For batch scheduling of probe for sas attached ata devices, assumes
+ * the port has already been through ata_sas_port_init()
+ */
+void ata_sas_async_probe(struct ata_port *ap)
 {
-       int rc = ap->ops->port_start(ap);
-
-       if (!rc) {
-               ap->print_id = atomic_inc_return(&ata_print_id);
-               __ata_port_probe(ap);
-       }
+       __ata_port_probe(ap);
+}
+EXPORT_SYMBOL_GPL(ata_sas_async_probe);
 
-       return rc;
+int ata_sas_sync_probe(struct ata_port *ap)
+{
+       return ata_port_probe(ap);
 }
-EXPORT_SYMBOL_GPL(ata_sas_async_port_init);
+EXPORT_SYMBOL_GPL(ata_sas_sync_probe);
+
 
 /**
  *     ata_sas_port_init - Initialize a SATA device
@@ -3866,12 +3874,10 @@ int ata_sas_port_init(struct ata_port *ap)
 {
        int rc = ap->ops->port_start(ap);
 
-       if (!rc) {
-               ap->print_id = atomic_inc_return(&ata_print_id);
-               rc = ata_port_probe(ap);
-       }
-
-       return rc;
+       if (rc)
+               return rc;
+       ap->print_id = atomic_inc_return(&ata_print_id);
+       return 0;
 }
 EXPORT_SYMBOL_GPL(ata_sas_port_init);
 

diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
index fc2db2a..3239517 100644 (file)
--- a/drivers/ata/pata_arasan_cf.c
+++ b/drivers/ata/pata_arasan_cf.c
@@ -943,9 +943,9 @@ static int arasan_cf_resume(struct device *dev)
 
        return 0;
 }
+#endif
 
 static SIMPLE_DEV_PM_OPS(arasan_cf_pm_ops, arasan_cf_suspend, arasan_cf_resume);
-#endif
 
 static struct platform_driver arasan_cf_driver = {
        .probe          = arasan_cf_probe,
@@ -953,9 +953,7 @@ static struct platform_driver arasan_cf_driver = {
        .driver         = {
                .name   = DRIVER_NAME,
                .owner  = THIS_MODULE,
-#ifdef CONFIG_PM
                .pm     = &arasan_cf_pm_ops,
-#endif
        },
 };
 

diff --git a/drivers/bcma/sprom.c b/drivers/bcma/sprom.c
index cdcf75c..3e2a600 100644 (file)
--- a/drivers/bcma/sprom.c
+++ b/drivers/bcma/sprom.c
@@ -404,16 +404,19 @@ int bcma_sprom_get(struct bcma_bus *bus)
                return -EOPNOTSUPP;
 
        if (!bcma_sprom_ext_available(bus)) {
+               bool sprom_onchip;
+
                /*
                 * External SPROM takes precedence so check
                 * on-chip OTP only when no external SPROM
                 * is present.
                 */
-               if (bcma_sprom_onchip_available(bus)) {
+               sprom_onchip = bcma_sprom_onchip_available(bus);
+               if (sprom_onchip) {
                        /* determine offset */
                        offset = bcma_sprom_onchip_offset(bus);
                }
-               if (!offset) {
+               if (!offset || !sprom_onchip) {
                        /*
                         * Maybe there is no SPROM on the device?
                         * Now we ask the arch code if there is some sprom

diff --git a/drivers/bluetooth/ath3k.c b/drivers/bluetooth/ath3k.c
index ae9edca..57fd867 100644 (file)
--- a/drivers/bluetooth/ath3k.c
+++ b/drivers/bluetooth/ath3k.c
@@ -75,6 +75,8 @@ static struct usb_device_id ath3k_table[] = {
        { USB_DEVICE(0x0CF3, 0x311D) },
        { USB_DEVICE(0x13d3, 0x3375) },
        { USB_DEVICE(0x04CA, 0x3005) },
+       { USB_DEVICE(0x13d3, 0x3362) },
+       { USB_DEVICE(0x0CF3, 0xE004) },
 
        /* Atheros AR5BBU12 with sflash firmware */
        { USB_DEVICE(0x0489, 0xE02C) },
@@ -94,6 +96,8 @@ static struct usb_device_id ath3k_blist_tbl[] = {
        { USB_DEVICE(0x0cf3, 0x311D), .driver_info = BTUSB_ATH3012 },
        { USB_DEVICE(0x13d3, 0x3375), .driver_info = BTUSB_ATH3012 },
        { USB_DEVICE(0x04ca, 0x3005), .driver_info = BTUSB_ATH3012 },
+       { USB_DEVICE(0x13d3, 0x3362), .driver_info = BTUSB_ATH3012 },
+       { USB_DEVICE(0x0cf3, 0xe004), .driver_info = BTUSB_ATH3012 },
 
        { }     /* Terminating entry */
 };

diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c
index 3311b81..9217121 100644 (file)
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
@@ -101,12 +101,16 @@ static struct usb_device_id btusb_table[] = {
        { USB_DEVICE(0x0c10, 0x0000) },
 
        /* Broadcom BCM20702A0 */
+       { USB_DEVICE(0x0489, 0xe042) },
        { USB_DEVICE(0x0a5c, 0x21e3) },
        { USB_DEVICE(0x0a5c, 0x21e6) },
        { USB_DEVICE(0x0a5c, 0x21e8) },
        { USB_DEVICE(0x0a5c, 0x21f3) },
        { USB_DEVICE(0x413c, 0x8197) },
 
+       /* Foxconn - Hon Hai */
+       { USB_DEVICE(0x0489, 0xe033) },
+
        { }     /* Terminating entry */
 };
 
@@ -133,6 +137,8 @@ static struct usb_device_id blacklist_table[] = {
        { USB_DEVICE(0x0cf3, 0x311d), .driver_info = BTUSB_ATH3012 },
        { USB_DEVICE(0x13d3, 0x3375), .driver_info = BTUSB_ATH3012 },
        { USB_DEVICE(0x04ca, 0x3005), .driver_info = BTUSB_ATH3012 },
+       { USB_DEVICE(0x13d3, 0x3362), .driver_info = BTUSB_ATH3012 },
+       { USB_DEVICE(0x0cf3, 0xe004), .driver_info = BTUSB_ATH3012 },
 
        /* Atheros AR5BBU12 with sflash firmware */
        { USB_DEVICE(0x0489, 0xe02c), .driver_info = BTUSB_IGNORE },

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 24aa714..b9a5158 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -2,3 +2,6 @@
 obj-$(CONFIG_CLKDEV_LOOKUP)    += clkdev.o
 obj-$(CONFIG_COMMON_CLK)       += clk.o clk-fixed-rate.o clk-gate.o \
                                   clk-mux.o clk-divider.o clk-fixed-factor.o
+# SoCs specific
+obj-$(CONFIG_ARCH_MXS)         += mxs/
+obj-$(CONFIG_PLAT_SPEAR)       += spear/

diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index 6db161f..c535cf8 100644 (file)
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -35,7 +35,12 @@ static DEFINE_MUTEX(clocks_mutex);
 static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
 {
        struct clk_lookup *p, *cl = NULL;
-       int match, best = 0;
+       int match, best_found = 0, best_possible = 0;
+
+       if (dev_id)
+               best_possible += 2;
+       if (con_id)
+               best_possible += 1;
 
        list_for_each_entry(p, &clocks, node) {
                match = 0;
@@ -50,10 +55,10 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id)
                        match += 1;
                }
 
-               if (match > best) {
+               if (match > best_found) {
                        cl = p;
-                       if (match != 3)
-                               best = match;
+                       if (match != best_possible)
+                               best_found = match;
                        else
                                break;
                }
@@ -89,6 +94,51 @@ void clk_put(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_put);
 
+static void devm_clk_release(struct device *dev, void *res)
+{
+       clk_put(*(struct clk **)res);
+}
+
+struct clk *devm_clk_get(struct device *dev, const char *id)
+{
+       struct clk **ptr, *clk;
+
+       ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
+       if (!ptr)
+               return ERR_PTR(-ENOMEM);
+
+       clk = clk_get(dev, id);
+       if (!IS_ERR(clk)) {
+               *ptr = clk;
+               devres_add(dev, ptr);
+       } else {
+               devres_free(ptr);
+       }
+
+       return clk;
+}
+EXPORT_SYMBOL(devm_clk_get);
+
+static int devm_clk_match(struct device *dev, void *res, void *data)
+{
+       struct clk **c = res;
+       if (!c || !*c) {
+               WARN_ON(!c || !*c);
+               return 0;
+       }
+       return *c == data;
+}
+
+void devm_clk_put(struct device *dev, struct clk *clk)
+{
+       int ret;
+
+       ret = devres_destroy(dev, devm_clk_release, devm_clk_match, clk);
+
+       WARN_ON(ret);
+}
+EXPORT_SYMBOL(devm_clk_put);
+
 void clkdev_add(struct clk_lookup *cl)
 {
        mutex_lock(&clocks_mutex);
@@ -116,8 +166,9 @@ struct clk_lookup_alloc {
        char    con_id[MAX_CON_ID];
 };
 
-struct clk_lookup * __init_refok
-clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
+static struct clk_lookup * __init_refok
+vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt,
+       va_list ap)
 {
        struct clk_lookup_alloc *cla;
 
@@ -132,16 +183,25 @@ clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
        }
 
        if (dev_fmt) {
-               va_list ap;
-
-               va_start(ap, dev_fmt);
                vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
                cla->cl.dev_id = cla->dev_id;
-               va_end(ap);
        }
 
        return &cla->cl;
 }
+
+struct clk_lookup * __init_refok
+clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
+{
+       struct clk_lookup *cl;
+       va_list ap;
+
+       va_start(ap, dev_fmt);
+       cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
+       va_end(ap);
+
+       return cl;
+}
 EXPORT_SYMBOL(clkdev_alloc);
 
 int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
@@ -173,3 +233,65 @@ void clkdev_drop(struct clk_lookup *cl)
        kfree(cl);
 }
 EXPORT_SYMBOL(clkdev_drop);
+
+/**
+ * clk_register_clkdev - register one clock lookup for a struct clk
+ * @clk: struct clk to associate with all clk_lookups
+ * @con_id: connection ID string on device
+ * @dev_id: format string describing device name
+ *
+ * con_id or dev_id may be NULL as a wildcard, just as in the rest of
+ * clkdev.
+ *
+ * To make things easier for mass registration, we detect error clks
+ * from a previous clk_register() call, and return the error code for
+ * those.  This is to permit this function to be called immediately
+ * after clk_register().
+ */
+int clk_register_clkdev(struct clk *clk, const char *con_id,
+       const char *dev_fmt, ...)
+{
+       struct clk_lookup *cl;
+       va_list ap;
+
+       if (IS_ERR(clk))
+               return PTR_ERR(clk);
+
+       va_start(ap, dev_fmt);
+       cl = vclkdev_alloc(clk, con_id, dev_fmt, ap);
+       va_end(ap);
+
+       if (!cl)
+               return -ENOMEM;
+
+       clkdev_add(cl);
+
+       return 0;
+}
+
+/**
+ * clk_register_clkdevs - register a set of clk_lookup for a struct clk
+ * @clk: struct clk to associate with all clk_lookups
+ * @cl: array of clk_lookup structures with con_id and dev_id pre-initialized
+ * @num: number of clk_lookup structures to register
+ *
+ * To make things easier for mass registration, we detect error clks
+ * from a previous clk_register() call, and return the error code for
+ * those.  This is to permit this function to be called immediately
+ * after clk_register().
+ */
+int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num)
+{
+       unsigned i;
+
+       if (IS_ERR(clk))
+               return PTR_ERR(clk);
+
+       for (i = 0; i < num; i++, cl++) {
+               cl->clk = clk;
+               clkdev_add(cl);
+       }
+
+       return 0;
+}
+EXPORT_SYMBOL(clk_register_clkdevs);

diff --git a/drivers/clk/mxs/Makefile b/drivers/clk/mxs/Makefile
new file mode 100644 (file)
index 0000000..7bedeec
--- /dev/null
+++ b/drivers/clk/mxs/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for mxs specific clk
+#
+
+obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o
+
+obj-$(CONFIG_SOC_IMX23) += clk-imx23.o
+obj-$(CONFIG_SOC_IMX28) += clk-imx28.o

diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c
new file mode 100644 (file)
index 0000000..90e1da9
--- /dev/null
+++ b/drivers/clk/mxs/clk-div.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include "clk.h"
+
+/**
+ * struct clk_div - mxs integer divider clock
+ * @divider: the parent class
+ * @ops: pointer to clk_ops of parent class
+ * @reg: register address
+ * @busy: busy bit shift
+ *
+ * The mxs divider clock is a subclass of basic clk_divider with an
+ * addtional busy bit.
+ */
+struct clk_div {
+       struct clk_divider divider;
+       const struct clk_ops *ops;
+       void __iomem *reg;
+       u8 busy;
+};
+
+static inline struct clk_div *to_clk_div(struct clk_hw *hw)
+{
+       struct clk_divider *divider = container_of(hw, struct clk_divider, hw);
+
+       return container_of(divider, struct clk_div, divider);
+}
+
+static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
+                                        unsigned long parent_rate)
+{
+       struct clk_div *div = to_clk_div(hw);
+
+       return div->ops->recalc_rate(&div->divider.hw, parent_rate);
+}
+
+static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long *prate)
+{
+       struct clk_div *div = to_clk_div(hw);
+
+       return div->ops->round_rate(&div->divider.hw, rate, prate);
+}
+
+static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
+                           unsigned long parent_rate)
+{
+       struct clk_div *div = to_clk_div(hw);
+       int ret;
+
+       ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate);
+       if (!ret)
+               ret = mxs_clk_wait(div->reg, div->busy);
+
+       return ret;
+}
+
+static struct clk_ops clk_div_ops = {
+       .recalc_rate = clk_div_recalc_rate,
+       .round_rate = clk_div_round_rate,
+       .set_rate = clk_div_set_rate,
+};
+
+struct clk *mxs_clk_div(const char *name, const char *parent_name,
+                       void __iomem *reg, u8 shift, u8 width, u8 busy)
+{
+       struct clk_div *div;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       div = kzalloc(sizeof(*div), GFP_KERNEL);
+       if (!div)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &clk_div_ops;
+       init.flags = CLK_SET_RATE_PARENT;
+       init.parent_names = (parent_name ? &parent_name: NULL);
+       init.num_parents = (parent_name ? 1 : 0);
+
+       div->reg = reg;
+       div->busy = busy;
+
+       div->divider.reg = reg;
+       div->divider.shift = shift;
+       div->divider.width = width;
+       div->divider.flags = CLK_DIVIDER_ONE_BASED;
+       div->divider.lock = &mxs_lock;
+       div->divider.hw.init = &init;
+       div->ops = &clk_divider_ops;
+
+       clk = clk_register(NULL, &div->divider.hw);
+       if (IS_ERR(clk))
+               kfree(div);
+
+       return clk;
+}

diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c
new file mode 100644 (file)
index 0000000..e6aa6b5
--- /dev/null
+++ b/drivers/clk/mxs/clk-frac.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "clk.h"
+
+/**
+ * struct clk_frac - mxs fractional divider clock
+ * @hw: clk_hw for the fractional divider clock
+ * @reg: register address
+ * @shift: the divider bit shift
+ * @width: the divider bit width
+ * @busy: busy bit shift
+ *
+ * The clock is an adjustable fractional divider with a busy bit to wait
+ * when the divider is adjusted.
+ */
+struct clk_frac {
+       struct clk_hw hw;
+       void __iomem *reg;
+       u8 shift;
+       u8 width;
+       u8 busy;
+};
+
+#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
+
+static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+       struct clk_frac *frac = to_clk_frac(hw);
+       u32 div;
+
+       div = readl_relaxed(frac->reg) >> frac->shift;
+       div &= (1 << frac->width) - 1;
+
+       return (parent_rate >> frac->width) * div;
+}
+
+static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *prate)
+{
+       struct clk_frac *frac = to_clk_frac(hw);
+       unsigned long parent_rate = *prate;
+       u32 div;
+       u64 tmp;
+
+       if (rate > parent_rate)
+               return -EINVAL;
+
+       tmp = rate;
+       tmp <<= frac->width;
+       do_div(tmp, parent_rate);
+       div = tmp;
+
+       if (!div)
+               return -EINVAL;
+
+       return (parent_rate >> frac->width) * div;
+}
+
+static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate,
+                            unsigned long parent_rate)
+{
+       struct clk_frac *frac = to_clk_frac(hw);
+       unsigned long flags;
+       u32 div, val;
+       u64 tmp;
+
+       if (rate > parent_rate)
+               return -EINVAL;
+
+       tmp = rate;
+       tmp <<= frac->width;
+       do_div(tmp, parent_rate);
+       div = tmp;
+
+       if (!div)
+               return -EINVAL;
+
+       spin_lock_irqsave(&mxs_lock, flags);
+
+       val = readl_relaxed(frac->reg);
+       val &= ~(((1 << frac->width) - 1) << frac->shift);
+       val |= div << frac->shift;
+       writel_relaxed(val, frac->reg);
+
+       spin_unlock_irqrestore(&mxs_lock, flags);
+
+       return mxs_clk_wait(frac->reg, frac->busy);
+}
+
+static struct clk_ops clk_frac_ops = {
+       .recalc_rate = clk_frac_recalc_rate,
+       .round_rate = clk_frac_round_rate,
+       .set_rate = clk_frac_set_rate,
+};
+
+struct clk *mxs_clk_frac(const char *name, const char *parent_name,
+                        void __iomem *reg, u8 shift, u8 width, u8 busy)
+{
+       struct clk_frac *frac;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       frac = kzalloc(sizeof(*frac), GFP_KERNEL);
+       if (!frac)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &clk_frac_ops;
+       init.flags = CLK_SET_RATE_PARENT;
+       init.parent_names = (parent_name ? &parent_name: NULL);
+       init.num_parents = (parent_name ? 1 : 0);
+
+       frac->reg = reg;
+       frac->shift = shift;
+       frac->width = width;
+       frac->busy = busy;
+       frac->hw.init = &init;
+
+       clk = clk_register(NULL, &frac->hw);
+       if (IS_ERR(clk))
+               kfree(frac);
+
+       return clk;
+}

diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
new file mode 100644 (file)
index 0000000..dcae112
--- /dev/null
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <mach/common.h>
+#include <mach/mx23.h>
+#include "clk.h"
+
+#define DIGCTRL                        MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
+#define CLKCTRL                        MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
+#define PLLCTRL0               (CLKCTRL + 0x0000)
+#define CPU                    (CLKCTRL + 0x0020)
+#define HBUS                   (CLKCTRL + 0x0030)
+#define XBUS                   (CLKCTRL + 0x0040)
+#define XTAL                   (CLKCTRL + 0x0050)
+#define PIX                    (CLKCTRL + 0x0060)
+#define SSP                    (CLKCTRL + 0x0070)
+#define GPMI                   (CLKCTRL + 0x0080)
+#define SPDIF                  (CLKCTRL + 0x0090)
+#define EMI                    (CLKCTRL + 0x00a0)
+#define SAIF                   (CLKCTRL + 0x00c0)
+#define TV                     (CLKCTRL + 0x00d0)
+#define ETM                    (CLKCTRL + 0x00e0)
+#define FRAC                   (CLKCTRL + 0x00f0)
+#define CLKSEQ                 (CLKCTRL + 0x0110)
+
+#define BP_CPU_INTERRUPT_WAIT  12
+#define BP_CLKSEQ_BYPASS_SAIF  0
+#define BP_CLKSEQ_BYPASS_SSP   5
+#define BP_SAIF_DIV_FRAC_EN    16
+#define BP_FRAC_IOFRAC         24
+
+static void __init clk_misc_init(void)
+{
+       u32 val;
+
+       /* Gate off cpu clock in WFI for power saving */
+       __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
+
+       /* Clear BYPASS for SAIF */
+       __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ);
+
+       /* SAIF has to use frac div for functional operation */
+       val = readl_relaxed(SAIF);
+       val |= 1 << BP_SAIF_DIV_FRAC_EN;
+       writel_relaxed(val, SAIF);
+
+       /*
+        * Source ssp clock from ref_io than ref_xtal,
+        * as ref_xtal only provides 24 MHz as maximum.
+        */
+       __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ);
+
+       /*
+        * 480 MHz seems too high to be ssp clock source directly,
+        * so set frac to get a 288 MHz ref_io.
+        */
+       __mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC);
+       __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
+}
+
+static struct clk_lookup uart_lookups[] __initdata = {
+       { .dev_id = "duart", },
+       { .dev_id = "mxs-auart.0", },
+       { .dev_id = "mxs-auart.1", },
+       { .dev_id = "8006c000.serial", },
+       { .dev_id = "8006e000.serial", },
+       { .dev_id = "80070000.serial", },
+};
+
+static struct clk_lookup hbus_lookups[] __initdata = {
+       { .dev_id = "mxs-dma-apbh", },
+       { .dev_id = "80004000.dma-apbh", },
+};
+
+static struct clk_lookup xbus_lookups[] __initdata = {
+       { .dev_id = "duart", .con_id = "apb_pclk"},
+       { .dev_id = "mxs-dma-apbx", },
+       { .dev_id = "80024000.dma-apbx", },
+};
+
+static struct clk_lookup ssp_lookups[] __initdata = {
+       { .dev_id = "mxs-mmc.0", },
+       { .dev_id = "mxs-mmc.1", },
+       { .dev_id = "80010000.ssp", },
+       { .dev_id = "80034000.ssp", },
+};
+
+static struct clk_lookup lcdif_lookups[] __initdata = {
+       { .dev_id = "imx23-fb", },
+       { .dev_id = "80030000.lcdif", },
+};
+
+static struct clk_lookup gpmi_lookups[] __initdata = {
+       { .dev_id = "imx23-gpmi-nand", },
+       { .dev_id = "8000c000.gpmi", },
+};
+
+static const char *sel_pll[]  __initconst = { "pll", "ref_xtal", };
+static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
+static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
+static const char *sel_io[]   __initconst = { "ref_io", "ref_xtal", };
+static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
+static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
+
+enum imx23_clk {
+       ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel,
+       lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll,
+       cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
+       emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
+       clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
+       lcdif, etm, usb, usb_pwr,
+       clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static enum imx23_clk clks_init_on[] __initdata = {
+       cpu, hbus, xbus, emi, uart,
+};
+
+int __init mx23_clocks_init(void)
+{
+       int i;
+
+       clk_misc_init();
+
+       clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
+       clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
+       clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
+       clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
+       clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
+       clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
+       clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
+       clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
+       clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
+       clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
+       clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
+       clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
+       clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
+       clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
+       clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
+       clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
+       clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
+       clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
+       clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
+       clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
+       clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
+       clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
+       clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
+       clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
+       clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
+       clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
+       clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
+       clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
+       clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
+       clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
+       clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
+       clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
+       clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
+       clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
+       clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
+       clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
+       clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
+       clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
+       clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
+       clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
+       clks[usb] = mxs_clk_gate("usb", "usb_pwr", DIGCTRL, 2);
+       clks[usb_pwr] = clk_register_gate(NULL, "usb_pwr", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
+
+       for (i = 0; i < ARRAY_SIZE(clks); i++)
+               if (IS_ERR(clks[i])) {
+                       pr_err("i.MX23 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clks[i]));
+                       return PTR_ERR(clks[i]);
+               }
+
+       clk_register_clkdev(clks[clk32k], NULL, "timrot");
+       clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
+       clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
+       clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
+       clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups));
+       clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
+       clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
+
+       for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+               clk_prepare_enable(clks[clks_init_on[i]]);
+
+       mxs_timer_init(MX23_INT_TIMER0);
+
+       return 0;
+}

diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
new file mode 100644 (file)
index 0000000..b2a3257
--- /dev/null
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <mach/common.h>
+#include <mach/mx28.h>
+#include "clk.h"
+
+#define CLKCTRL                        MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
+#define PLL0CTRL0              (CLKCTRL + 0x0000)
+#define PLL1CTRL0              (CLKCTRL + 0x0020)
+#define PLL2CTRL0              (CLKCTRL + 0x0040)
+#define CPU                    (CLKCTRL + 0x0050)
+#define HBUS                   (CLKCTRL + 0x0060)
+#define XBUS                   (CLKCTRL + 0x0070)
+#define XTAL                   (CLKCTRL + 0x0080)
+#define SSP0                   (CLKCTRL + 0x0090)
+#define SSP1                   (CLKCTRL + 0x00a0)
+#define SSP2                   (CLKCTRL + 0x00b0)
+#define SSP3                   (CLKCTRL + 0x00c0)
+#define GPMI                   (CLKCTRL + 0x00d0)
+#define SPDIF                  (CLKCTRL + 0x00e0)
+#define EMI                    (CLKCTRL + 0x00f0)
+#define SAIF0                  (CLKCTRL + 0x0100)
+#define SAIF1                  (CLKCTRL + 0x0110)
+#define LCDIF                  (CLKCTRL + 0x0120)
+#define ETM                    (CLKCTRL + 0x0130)
+#define ENET                   (CLKCTRL + 0x0140)
+#define FLEXCAN                        (CLKCTRL + 0x0160)
+#define FRAC0                  (CLKCTRL + 0x01b0)
+#define FRAC1                  (CLKCTRL + 0x01c0)
+#define CLKSEQ                 (CLKCTRL + 0x01d0)
+
+#define BP_CPU_INTERRUPT_WAIT  12
+#define BP_SAIF_DIV_FRAC_EN    16
+#define BP_ENET_DIV_TIME       21
+#define BP_ENET_SLEEP          31
+#define BP_CLKSEQ_BYPASS_SAIF0 0
+#define BP_CLKSEQ_BYPASS_SSP0  3
+#define BP_FRAC0_IO1FRAC       16
+#define BP_FRAC0_IO0FRAC       24
+
+#define DIGCTRL                        MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
+#define BP_SAIF_CLKMUX         10
+
+/*
+ * HW_SAIF_CLKMUX_SEL:
+ *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
+ *             clock pins selected for SAIF1 input clocks.
+ *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
+ *             SAIF0 clock inputs selected for SAIF1 input clocks.
+ *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
+ *             clocks.
+ *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
+ *             clocks.
+ */
+int mxs_saif_clkmux_select(unsigned int clkmux)
+{
+       if (clkmux > 0x3)
+               return -EINVAL;
+
+       __mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL);
+       __mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL);
+
+       return 0;
+}
+
+static void __init clk_misc_init(void)
+{
+       u32 val;
+
+       /* Gate off cpu clock in WFI for power saving */
+       __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
+
+       /* 0 is a bad default value for a divider */
+       __mxs_setl(1 << BP_ENET_DIV_TIME, ENET);
+
+       /* Clear BYPASS for SAIF */
+       __mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ);
+
+       /* SAIF has to use frac div for functional operation */
+       val = readl_relaxed(SAIF0);
+       val |= 1 << BP_SAIF_DIV_FRAC_EN;
+       writel_relaxed(val, SAIF0);
+
+       val = readl_relaxed(SAIF1);
+       val |= 1 << BP_SAIF_DIV_FRAC_EN;
+       writel_relaxed(val, SAIF1);
+
+       /* Extra fec clock setting */
+       val = readl_relaxed(ENET);
+       val &= ~(1 << BP_ENET_SLEEP);
+       writel_relaxed(val, ENET);
+
+       /*
+        * Source ssp clock from ref_io than ref_xtal,
+        * as ref_xtal only provides 24 MHz as maximum.
+        */
+       __mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ);
+
+       /*
+        * 480 MHz seems too high to be ssp clock source directly,
+        * so set frac0 to get a 288 MHz ref_io0.
+        */
+       val = readl_relaxed(FRAC0);
+       val &= ~(0x3f << BP_FRAC0_IO0FRAC);
+       val |= 30 << BP_FRAC0_IO0FRAC;
+       writel_relaxed(val, FRAC0);
+}
+
+static struct clk_lookup uart_lookups[] __initdata = {
+       { .dev_id = "duart", },
+       { .dev_id = "mxs-auart.0", },
+       { .dev_id = "mxs-auart.1", },
+       { .dev_id = "mxs-auart.2", },
+       { .dev_id = "mxs-auart.3", },
+       { .dev_id = "mxs-auart.4", },
+       { .dev_id = "8006a000.serial", },
+       { .dev_id = "8006c000.serial", },
+       { .dev_id = "8006e000.serial", },
+       { .dev_id = "80070000.serial", },
+       { .dev_id = "80072000.serial", },
+       { .dev_id = "80074000.serial", },
+};
+
+static struct clk_lookup hbus_lookups[] __initdata = {
+       { .dev_id = "mxs-dma-apbh", },
+       { .dev_id = "80004000.dma-apbh", },
+};
+
+static struct clk_lookup xbus_lookups[] __initdata = {
+       { .dev_id = "duart", .con_id = "apb_pclk"},
+       { .dev_id = "mxs-dma-apbx", },
+       { .dev_id = "80024000.dma-apbx", },
+};
+
+static struct clk_lookup ssp0_lookups[] __initdata = {
+       { .dev_id = "mxs-mmc.0", },
+       { .dev_id = "80010000.ssp", },
+};
+
+static struct clk_lookup ssp1_lookups[] __initdata = {
+       { .dev_id = "mxs-mmc.1", },
+       { .dev_id = "80012000.ssp", },
+};
+
+static struct clk_lookup ssp2_lookups[] __initdata = {
+       { .dev_id = "mxs-mmc.2", },
+       { .dev_id = "80014000.ssp", },
+};
+
+static struct clk_lookup ssp3_lookups[] __initdata = {
+       { .dev_id = "mxs-mmc.3", },
+       { .dev_id = "80016000.ssp", },
+};
+
+static struct clk_lookup lcdif_lookups[] __initdata = {
+       { .dev_id = "imx28-fb", },
+       { .dev_id = "80030000.lcdif", },
+};
+
+static struct clk_lookup gpmi_lookups[] __initdata = {
+       { .dev_id = "imx28-gpmi-nand", },
+       { .dev_id = "8000c000.gpmi", },
+};
+
+static struct clk_lookup fec_lookups[] __initdata = {
+       { .dev_id = "imx28-fec.0", },
+       { .dev_id = "imx28-fec.1", },
+       { .dev_id = "800f0000.ethernet", },
+       { .dev_id = "800f4000.ethernet", },
+};
+
+static struct clk_lookup can0_lookups[] __initdata = {
+       { .dev_id = "flexcan.0", },
+       { .dev_id = "80032000.can", },
+};
+
+static struct clk_lookup can1_lookups[] __initdata = {
+       { .dev_id = "flexcan.1", },
+       { .dev_id = "80034000.can", },
+};
+
+static struct clk_lookup saif0_lookups[] __initdata = {
+       { .dev_id = "mxs-saif.0", },
+       { .dev_id = "80042000.saif", },
+};
+
+static struct clk_lookup saif1_lookups[] __initdata = {
+       { .dev_id = "mxs-saif.1", },
+       { .dev_id = "80046000.saif", },
+};
+
+static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
+static const char *sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
+static const char *sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
+static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
+static const char *sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
+static const char *sel_pll0[] __initconst = { "pll0", "ref_xtal", };
+static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
+static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
+static const char *ptp_sels[] __initconst = { "ref_xtal", "pll0", };
+
+enum imx28_clk {
+       ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
+       ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
+       ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
+       lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
+       ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
+       emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
+       clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
+       ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
+       fec, can0, can1, usb0, usb1, usb0_pwr, usb1_pwr, enet_out,
+       clk_max
+};
+
+static struct clk *clks[clk_max];
+
+static enum imx28_clk clks_init_on[] __initdata = {
+       cpu, hbus, xbus, emi, uart,
+};
+
+int __init mx28_clocks_init(void)
+{
+       int i;
+
+       clk_misc_init();
+
+       clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
+       clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
+       clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
+       clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
+       clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
+       clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
+       clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 2);
+       clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 3);
+       clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
+       clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
+       clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
+       clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
+       clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
+       clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
+       clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
+       clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
+       clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
+       clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
+       clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
+       clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
+       clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
+       clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
+       clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
+       clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
+       clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
+       clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
+       clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
+       clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
+       clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
+       clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
+       clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
+       clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
+       clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
+       clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
+       clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
+       clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
+       clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27);
+       clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
+       clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);
+       clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
+       clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
+       clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
+       clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4);
+       clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
+       clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
+       clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
+       clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
+       clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
+       clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
+       clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
+       clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
+       clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
+       clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
+       clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);
+       clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);
+       clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
+       clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
+       clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
+       clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
+       clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
+       clks[usb0] = mxs_clk_gate("usb0", "usb0_pwr", DIGCTRL, 2);
+       clks[usb1] = mxs_clk_gate("usb1", "usb1_pwr", DIGCTRL, 16);
+       clks[usb0_pwr] = clk_register_gate(NULL, "usb0_pwr", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
+       clks[usb1_pwr] = clk_register_gate(NULL, "usb1_pwr", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
+       clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
+
+       for (i = 0; i < ARRAY_SIZE(clks); i++)
+               if (IS_ERR(clks[i])) {
+                       pr_err("i.MX28 clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clks[i]));
+                       return PTR_ERR(clks[i]);
+               }
+
+       clk_register_clkdev(clks[clk32k], NULL, "timrot");
+       clk_register_clkdev(clks[enet_out], NULL, "enet_out");
+       clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
+       clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
+       clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
+       clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups));
+       clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups));
+       clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups));
+       clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups));
+       clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
+       clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups));
+       clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups));
+       clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
+       clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
+       clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
+       clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
+
+       for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+               clk_prepare_enable(clks[clks_init_on[i]]);
+
+       mxs_timer_init(MX28_INT_TIMER0);
+
+       return 0;
+}

diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c
new file mode 100644 (file)
index 0000000..fadae41
--- /dev/null
+++ b/drivers/clk/mxs/clk-pll.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "clk.h"
+
+/**
+ * struct clk_pll - mxs pll clock
+ * @hw: clk_hw for the pll
+ * @base: base address of the pll
+ * @power: the shift of power bit
+ * @rate: the clock rate of the pll
+ *
+ * The mxs pll is a fixed rate clock with power and gate control,
+ * and the shift of gate bit is always 31.
+ */
+struct clk_pll {
+       struct clk_hw hw;
+       void __iomem *base;
+       u8 power;
+       unsigned long rate;
+};
+
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
+
+static int clk_pll_prepare(struct clk_hw *hw)
+{
+       struct clk_pll *pll = to_clk_pll(hw);
+
+       writel_relaxed(1 << pll->power, pll->base + SET);
+
+       udelay(10);
+
+       return 0;
+}
+
+static void clk_pll_unprepare(struct clk_hw *hw)
+{
+       struct clk_pll *pll = to_clk_pll(hw);
+
+       writel_relaxed(1 << pll->power, pll->base + CLR);
+}
+
+static int clk_pll_enable(struct clk_hw *hw)
+{
+       struct clk_pll *pll = to_clk_pll(hw);
+
+       writel_relaxed(1 << 31, pll->base + CLR);
+
+       return 0;
+}
+
+static void clk_pll_disable(struct clk_hw *hw)
+{
+       struct clk_pll *pll = to_clk_pll(hw);
+
+       writel_relaxed(1 << 31, pll->base + SET);
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
+                                        unsigned long parent_rate)
+{
+       struct clk_pll *pll = to_clk_pll(hw);
+
+       return pll->rate;
+}
+
+static const struct clk_ops clk_pll_ops = {
+       .prepare = clk_pll_prepare,
+       .unprepare = clk_pll_unprepare,
+       .enable = clk_pll_enable,
+       .disable = clk_pll_disable,
+       .recalc_rate = clk_pll_recalc_rate,
+};
+
+struct clk *mxs_clk_pll(const char *name, const char *parent_name,
+                       void __iomem *base, u8 power, unsigned long rate)
+{
+       struct clk_pll *pll;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &clk_pll_ops;
+       init.flags = 0;
+       init.parent_names = (parent_name ? &parent_name: NULL);
+       init.num_parents = (parent_name ? 1 : 0);
+
+       pll->base = base;
+       pll->rate = rate;
+       pll->power = power;
+       pll->hw.init = &init;
+
+       clk = clk_register(NULL, &pll->hw);
+       if (IS_ERR(clk))
+               kfree(pll);
+
+       return clk;
+}

diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c
new file mode 100644 (file)
index 0000000..4adeed6
--- /dev/null
+++ b/drivers/clk/mxs/clk-ref.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "clk.h"
+
+/**
+ * struct clk_ref - mxs reference clock
+ * @hw: clk_hw for the reference clock
+ * @reg: register address
+ * @idx: the index of the reference clock within the same register
+ *
+ * The mxs reference clock sources from pll.  Every 4 reference clocks share
+ * one register space, and @idx is used to identify them.  Each reference
+ * clock has a gate control and a fractional * divider.  The rate is calculated
+ * as pll rate  * (18 / FRAC), where FRAC = 18 ~ 35.
+ */
+struct clk_ref {
+       struct clk_hw hw;
+       void __iomem *reg;
+       u8 idx;
+};
+
+#define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw)
+
+static int clk_ref_enable(struct clk_hw *hw)
+{
+       struct clk_ref *ref = to_clk_ref(hw);
+
+       writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
+
+       return 0;
+}
+
+static void clk_ref_disable(struct clk_hw *hw)
+{
+       struct clk_ref *ref = to_clk_ref(hw);
+
+       writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
+}
+
+static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
+                                        unsigned long parent_rate)
+{
+       struct clk_ref *ref = to_clk_ref(hw);
+       u64 tmp = parent_rate;
+       u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f;
+
+       tmp *= 18;
+       do_div(tmp, frac);
+
+       return tmp;
+}
+
+static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long *prate)
+{
+       unsigned long parent_rate = *prate;
+       u64 tmp = parent_rate;
+       u8 frac;
+
+       tmp = tmp * 18 + rate / 2;
+       do_div(tmp, rate);
+       frac = tmp;
+
+       if (frac < 18)
+               frac = 18;
+       else if (frac > 35)
+               frac = 35;
+
+       tmp = parent_rate;
+       tmp *= 18;
+       do_div(tmp, frac);
+
+       return tmp;
+}
+
+static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate,
+                           unsigned long parent_rate)
+{
+       struct clk_ref *ref = to_clk_ref(hw);
+       unsigned long flags;
+       u64 tmp = parent_rate;
+       u32 val;
+       u8 frac, shift = ref->idx * 8;
+
+       tmp = tmp * 18 + rate / 2;
+       do_div(tmp, rate);
+       frac = tmp;
+
+       if (frac < 18)
+               frac = 18;
+       else if (frac > 35)
+               frac = 35;
+
+       spin_lock_irqsave(&mxs_lock, flags);
+
+       val = readl_relaxed(ref->reg);
+       val &= ~(0x3f << shift);
+       val |= frac << shift;
+       writel_relaxed(val, ref->reg);
+
+       spin_unlock_irqrestore(&mxs_lock, flags);
+
+       return 0;
+}
+
+static const struct clk_ops clk_ref_ops = {
+       .enable         = clk_ref_enable,
+       .disable        = clk_ref_disable,
+       .recalc_rate    = clk_ref_recalc_rate,
+       .round_rate     = clk_ref_round_rate,
+       .set_rate       = clk_ref_set_rate,
+};
+
+struct clk *mxs_clk_ref(const char *name, const char *parent_name,
+                       void __iomem *reg, u8 idx)
+{
+       struct clk_ref *ref;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       ref = kzalloc(sizeof(*ref), GFP_KERNEL);
+       if (!ref)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &clk_ref_ops;
+       init.flags = 0;
+       init.parent_names = (parent_name ? &parent_name: NULL);
+       init.num_parents = (parent_name ? 1 : 0);
+
+       ref->reg = reg;
+       ref->idx = idx;
+       ref->hw.init = &init;
+
+       clk = clk_register(NULL, &ref->hw);
+       if (IS_ERR(clk))
+               kfree(ref);
+
+       return clk;
+}

diff --git a/drivers/clk/mxs/clk.c b/drivers/clk/mxs/clk.c
new file mode 100644 (file)
index 0000000..b24d560
--- /dev/null
+++ b/drivers/clk/mxs/clk.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/spinlock.h>
+
+DEFINE_SPINLOCK(mxs_lock);
+
+int mxs_clk_wait(void __iomem *reg, u8 shift)
+{
+       unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+       while (readl_relaxed(reg) & (1 << shift))
+               if (time_after(jiffies, timeout))
+                       return -ETIMEDOUT;
+
+       return 0;
+}

diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
new file mode 100644 (file)
index 0000000..81421e2
--- /dev/null
+++ b/drivers/clk/mxs/clk.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MXS_CLK_H
+#define __MXS_CLK_H
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+
+#define SET    0x4
+#define CLR    0x8
+
+extern spinlock_t mxs_lock;
+
+int mxs_clk_wait(void __iomem *reg, u8 shift);
+
+struct clk *mxs_clk_pll(const char *name, const char *parent_name,
+                       void __iomem *base, u8 power, unsigned long rate);
+
+struct clk *mxs_clk_ref(const char *name, const char *parent_name,
+                       void __iomem *reg, u8 idx);
+
+struct clk *mxs_clk_div(const char *name, const char *parent_name,
+                       void __iomem *reg, u8 shift, u8 width, u8 busy);
+
+struct clk *mxs_clk_frac(const char *name, const char *parent_name,
+                        void __iomem *reg, u8 shift, u8 width, u8 busy);
+
+static inline struct clk *mxs_clk_fixed(const char *name, int rate)
+{
+       return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+}
+
+static inline struct clk *mxs_clk_gate(const char *name,
+                       const char *parent_name, void __iomem *reg, u8 shift)
+{
+       return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT,
+                                reg, shift, CLK_GATE_SET_TO_DISABLE,
+                                &mxs_lock);
+}
+
+static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
+               u8 shift, u8 width, const char **parent_names, int num_parents)
+{
+       return clk_register_mux(NULL, name, parent_names, num_parents,
+                               CLK_SET_RATE_PARENT, reg, shift, width,
+                               0, &mxs_lock);
+}
+
+static inline struct clk *mxs_clk_fixed_factor(const char *name,
+               const char *parent_name, unsigned int mult, unsigned int div)
+{
+       return clk_register_fixed_factor(NULL, name, parent_name,
+                                        CLK_SET_RATE_PARENT, mult, div);
+}
+
+#endif /* __MXS_CLK_H */

diff --git a/drivers/clk/spear/Makefile b/drivers/clk/spear/Makefile
new file mode 100644 (file)
index 0000000..3358860
--- /dev/null
+++ b/drivers/clk/spear/Makefile
@@ -0,0 +1,8 @@
+#
+# SPEAr Clock specific Makefile
+#
+
+obj-y  += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
+
+obj-$(CONFIG_ARCH_SPEAR3XX)    += spear3xx_clock.o
+obj-$(CONFIG_ARCH_SPEAR6XX)    += spear6xx_clock.o

diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c
new file mode 100644 (file)
index 0000000..af34074
--- /dev/null
+++ b/drivers/clk/spear/clk-aux-synth.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Auxiliary Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-aux-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+/*
+ * DOC: Auxiliary Synthesizer clock
+ *
+ * Aux synth gives rate for different values of eq, x and y
+ *
+ * Fout from synthesizer can be given from two equations:
+ * Fout1 = (Fin * X/Y)/2               EQ1
+ * Fout2 = Fin * X/Y                   EQ2
+ */
+
+#define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw)
+
+static struct aux_clk_masks default_aux_masks = {
+       .eq_sel_mask = AUX_EQ_SEL_MASK,
+       .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+       .eq1_mask = AUX_EQ1_SEL,
+       .eq2_mask = AUX_EQ2_SEL,
+       .xscale_sel_mask = AUX_XSCALE_MASK,
+       .xscale_sel_shift = AUX_XSCALE_SHIFT,
+       .yscale_sel_mask = AUX_YSCALE_MASK,
+       .yscale_sel_shift = AUX_YSCALE_SHIFT,
+       .enable_bit = AUX_SYNT_ENB,
+};
+
+static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate,
+               int index)
+{
+       struct clk_aux *aux = to_clk_aux(hw);
+       struct aux_rate_tbl *rtbl = aux->rtbl;
+       u8 eq = rtbl[index].eq ? 1 : 2;
+
+       return (((prate / 10000) * rtbl[index].xscale) /
+                       (rtbl[index].yscale * eq)) * 10000;
+}
+
+static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
+               unsigned long *prate)
+{
+       struct clk_aux *aux = to_clk_aux(hw);
+       int unused;
+
+       return clk_round_rate_index(hw, drate, *prate, aux_calc_rate,
+                       aux->rtbl_cnt, &unused);
+}
+
+static unsigned long clk_aux_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       struct clk_aux *aux = to_clk_aux(hw);
+       unsigned int num = 1, den = 1, val, eqn;
+       unsigned long flags = 0;
+
+       if (aux->lock)
+               spin_lock_irqsave(aux->lock, flags);
+
+       val = readl_relaxed(aux->reg);
+
+       if (aux->lock)
+               spin_unlock_irqrestore(aux->lock, flags);
+
+       eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask;
+       if (eqn == aux->masks->eq1_mask)
+               den = 2;
+
+       /* calculate numerator */
+       num = (val >> aux->masks->xscale_sel_shift) &
+               aux->masks->xscale_sel_mask;
+
+       /* calculate denominator */
+       den *= (val >> aux->masks->yscale_sel_shift) &
+               aux->masks->yscale_sel_mask;
+
+       if (!den)
+               return 0;
+
+       return (((parent_rate / 10000) * num) / den) * 10000;
+}
+
+/* Configures new clock rate of aux */
+static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate,
+                               unsigned long prate)
+{
+       struct clk_aux *aux = to_clk_aux(hw);
+       struct aux_rate_tbl *rtbl = aux->rtbl;
+       unsigned long val, flags = 0;
+       int i;
+
+       clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt,
+                       &i);
+
+       if (aux->lock)
+               spin_lock_irqsave(aux->lock, flags);
+
+       val = readl_relaxed(aux->reg) &
+               ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift);
+       val |= (rtbl[i].eq & aux->masks->eq_sel_mask) <<
+               aux->masks->eq_sel_shift;
+       val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift);
+       val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) <<
+               aux->masks->xscale_sel_shift;
+       val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift);
+       val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) <<
+               aux->masks->yscale_sel_shift;
+       writel_relaxed(val, aux->reg);
+
+       if (aux->lock)
+               spin_unlock_irqrestore(aux->lock, flags);
+
+       return 0;
+}
+
+static struct clk_ops clk_aux_ops = {
+       .recalc_rate = clk_aux_recalc_rate,
+       .round_rate = clk_aux_round_rate,
+       .set_rate = clk_aux_set_rate,
+};
+
+struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
+               const char *parent_name, unsigned long flags, void __iomem *reg,
+               struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
+               u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
+{
+       struct clk_aux *aux;
+       struct clk_init_data init;
+       struct clk *clk;
+
+       if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
+               pr_err("Invalid arguments passed");
+               return ERR_PTR(-EINVAL);
+       }
+
+       aux = kzalloc(sizeof(*aux), GFP_KERNEL);
+       if (!aux) {
+               pr_err("could not allocate aux clk\n");
+               return ERR_PTR(-ENOMEM);
+       }
+
+       /* struct clk_aux assignments */
+       if (!masks)
+               aux->masks = &default_aux_masks;
+       else
+               aux->masks = masks;
+
+       aux->reg = reg;
+       aux->rtbl = rtbl;
+       aux->rtbl_cnt = rtbl_cnt;
+       aux->lock = lock;
+       aux->hw.init = &init;
+
+       init.name = aux_name;
+       init.ops = &clk_aux_ops;
+       init.flags = flags;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       clk = clk_register(NULL, &aux->hw);
+       if (IS_ERR_OR_NULL(clk))
+               goto free_aux;
+
+       if (gate_name) {
+               struct clk *tgate_clk;
+
+               tgate_clk = clk_register_gate(NULL, gate_name, aux_name, 0, reg,
+                               aux->masks->enable_bit, 0, lock);
+               if (IS_ERR_OR_NULL(tgate_clk))
+                       goto free_aux;
+
+               if (gate_clk)
+                       *gate_clk = tgate_clk;
+       }
+
+       return clk;
+
+free_aux:
+       kfree(aux);
+       pr_err("clk register failed\n");
+
+       return NULL;
+}

diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
new file mode 100644 (file)
index 0000000..4dbdb3f
--- /dev/null
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Fractional Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-frac-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define DIV_FACTOR_MASK                0x1FFFF
+
+/*
+ * DOC: Fractional Synthesizer clock
+ *
+ * Fout from synthesizer can be given from below equation:
+ *
+ * Fout= Fin/2*div (division factor)
+ * div is 17 bits:-
+ *     0-13 (fractional part)
+ *     14-16 (integer part)
+ *     div is (16-14 bits).(13-0 bits) (in binary)
+ *
+ *     Fout = Fin/(2 * div)
+ *     Fout = ((Fin / 10000)/(2 * div)) * 10000
+ *     Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
+ *     Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
+ *
+ * div << 14 simply 17 bit value written at register.
+ * Max error due to scaling down by 10000 is 10 KHz
+ */
+
+#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw)
+
+static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate,
+               int index)
+{
+       struct clk_frac *frac = to_clk_frac(hw);
+       struct frac_rate_tbl *rtbl = frac->rtbl;
+
+       prate /= 10000;
+       prate <<= 14;
+       prate /= (2 * rtbl[index].div);
+       prate *= 10000;
+
+       return prate;
+}
+
+static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate,
+               unsigned long *prate)
+{
+       struct clk_frac *frac = to_clk_frac(hw);
+       int unused;
+
+       return clk_round_rate_index(hw, drate, *prate, frac_calc_rate,
+                       frac->rtbl_cnt, &unused);
+}
+
+static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       struct clk_frac *frac = to_clk_frac(hw);
+       unsigned long flags = 0;
+       unsigned int div = 1, val;
+
+       if (frac->lock)
+               spin_lock_irqsave(frac->lock, flags);
+
+       val = readl_relaxed(frac->reg);
+
+       if (frac->lock)
+               spin_unlock_irqrestore(frac->lock, flags);
+
+       div = val & DIV_FACTOR_MASK;
+
+       if (!div)
+               return 0;
+
+       parent_rate = parent_rate / 10000;
+
+       parent_rate = (parent_rate << 14) / (2 * div);
+       return parent_rate * 10000;
+}
+
+/* Configures new clock rate of frac */
+static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate,
+                               unsigned long prate)
+{
+       struct clk_frac *frac = to_clk_frac(hw);
+       struct frac_rate_tbl *rtbl = frac->rtbl;
+       unsigned long flags = 0, val;
+       int i;
+
+       clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt,
+                       &i);
+
+       if (frac->lock)
+               spin_lock_irqsave(frac->lock, flags);
+
+       val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK;
+       val |= rtbl[i].div & DIV_FACTOR_MASK;
+       writel_relaxed(val, frac->reg);
+
+       if (frac->lock)
+               spin_unlock_irqrestore(frac->lock, flags);
+
+       return 0;
+}
+
+struct clk_ops clk_frac_ops = {
+       .recalc_rate = clk_frac_recalc_rate,
+       .round_rate = clk_frac_round_rate,
+       .set_rate = clk_frac_set_rate,
+};
+
+struct clk *clk_register_frac(const char *name, const char *parent_name,
+               unsigned long flags, void __iomem *reg,
+               struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock)
+{
+       struct clk_init_data init;
+       struct clk_frac *frac;
+       struct clk *clk;
+
+       if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
+               pr_err("Invalid arguments passed");
+               return ERR_PTR(-EINVAL);
+       }
+
+       frac = kzalloc(sizeof(*frac), GFP_KERNEL);
+       if (!frac) {
+               pr_err("could not allocate frac clk\n");
+               return ERR_PTR(-ENOMEM);
+       }
+
+       /* struct clk_frac assignments */
+       frac->reg = reg;
+       frac->rtbl = rtbl;
+       frac->rtbl_cnt = rtbl_cnt;
+       frac->lock = lock;
+       frac->hw.init = &init;
+
+       init.name = name;
+       init.ops = &clk_frac_ops;
+       init.flags = flags;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       clk = clk_register(NULL, &frac->hw);
+       if (!IS_ERR_OR_NULL(clk))
+               return clk;
+
+       pr_err("clk register failed\n");
+       kfree(frac);
+
+       return NULL;
+}

diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c
new file mode 100644 (file)
index 0000000..b471c97
--- /dev/null
+++ b/drivers/clk/spear/clk-gpt-synth.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * General Purpose Timer Synthesizer clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-gpt-synth: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+#define GPT_MSCALE_MASK                0xFFF
+#define GPT_NSCALE_SHIFT       12
+#define GPT_NSCALE_MASK                0xF
+
+/*
+ * DOC: General Purpose Timer Synthesizer clock
+ *
+ * Calculates gpt synth clk rate for different values of mscale and nscale
+ *
+ * Fout= Fin/((2 ^ (N+1)) * (M+1))
+ */
+
+#define to_clk_gpt(_hw) container_of(_hw, struct clk_gpt, hw)
+
+static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate,
+               int index)
+{
+       struct clk_gpt *gpt = to_clk_gpt(hw);
+       struct gpt_rate_tbl *rtbl = gpt->rtbl;
+
+       prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1));
+
+       return prate;
+}
+
+static long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate,
+               unsigned long *prate)
+{
+       struct clk_gpt *gpt = to_clk_gpt(hw);
+       int unused;
+
+       return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate,
+                       gpt->rtbl_cnt, &unused);
+}
+
+static unsigned long clk_gpt_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       struct clk_gpt *gpt = to_clk_gpt(hw);
+       unsigned long flags = 0;
+       unsigned int div = 1, val;
+
+       if (gpt->lock)
+               spin_lock_irqsave(gpt->lock, flags);
+
+       val = readl_relaxed(gpt->reg);
+
+       if (gpt->lock)
+               spin_unlock_irqrestore(gpt->lock, flags);
+
+       div += val & GPT_MSCALE_MASK;
+       div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
+
+       if (!div)
+               return 0;
+
+       return parent_rate / div;
+}
+
+/* Configures new clock rate of gpt */
+static int clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate,
+                               unsigned long prate)
+{
+       struct clk_gpt *gpt = to_clk_gpt(hw);
+       struct gpt_rate_tbl *rtbl = gpt->rtbl;
+       unsigned long flags = 0, val;
+       int i;
+
+       clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt,
+                       &i);
+
+       if (gpt->lock)
+               spin_lock_irqsave(gpt->lock, flags);
+
+       val = readl(gpt->reg) & ~GPT_MSCALE_MASK;
+       val &= ~(GPT_NSCALE_MASK << GPT_NSCALE_SHIFT);
+
+       val |= rtbl[i].mscale & GPT_MSCALE_MASK;
+       val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT;
+
+       writel_relaxed(val, gpt->reg);
+
+       if (gpt->lock)
+               spin_unlock_irqrestore(gpt->lock, flags);
+
+       return 0;
+}
+
+static struct clk_ops clk_gpt_ops = {
+       .recalc_rate = clk_gpt_recalc_rate,
+       .round_rate = clk_gpt_round_rate,
+       .set_rate = clk_gpt_set_rate,
+};
+
+struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
+               long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
+               rtbl_cnt, spinlock_t *lock)
+{
+       struct clk_init_data init;
+       struct clk_gpt *gpt;
+       struct clk *clk;
+
+       if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
+               pr_err("Invalid arguments passed");
+               return ERR_PTR(-EINVAL);
+       }
+
+       gpt = kzalloc(sizeof(*gpt), GFP_KERNEL);
+       if (!gpt) {
+               pr_err("could not allocate gpt clk\n");
+               return ERR_PTR(-ENOMEM);
+       }
+
+       /* struct clk_gpt assignments */
+       gpt->reg = reg;
+       gpt->rtbl = rtbl;
+       gpt->rtbl_cnt = rtbl_cnt;
+       gpt->lock = lock;
+       gpt->hw.init = &init;
+
+       init.name = name;
+       init.ops = &clk_gpt_ops;
+       init.flags = flags;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+
+       clk = clk_register(NULL, &gpt->hw);
+       if (!IS_ERR_OR_NULL(clk))
+               return clk;
+
+       pr_err("clk register failed\n");
+       kfree(gpt);
+
+       return NULL;
+}

diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c
new file mode 100644 (file)
index 0000000..dcd4bdf
--- /dev/null
+++ b/drivers/clk/spear/clk-vco-pll.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * VCO-PLL clock implementation
+ */
+
+#define pr_fmt(fmt) "clk-vco-pll: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include "clk.h"
+
+/*
+ * DOC: VCO-PLL clock
+ *
+ * VCO and PLL rate are derived from following equations:
+ *
+ * In normal mode
+ * vco = (2 * M[15:8] * Fin)/N
+ *
+ * In Dithered mode
+ * vco = (2 * M[15:0] * Fin)/(256 * N)
+ *
+ * pll_rate = pll/2^p
+ *
+ * vco and pll are very closely bound to each other, "vco needs to program:
+ * mode, m & n" and "pll needs to program p", both share common enable/disable
+ * logic.
+ *
+ * clk_register_vco_pll() registers instances of both vco & pll.
+ * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its
+ * set_rate to vco. A single rate table exists for both the clocks, which
+ * configures m, n and p.
+ */
+
+/* PLL_CTR register masks */
+#define PLL_MODE_NORMAL                0
+#define PLL_MODE_FRACTION      1
+#define PLL_MODE_DITH_DSM      2
+#define PLL_MODE_DITH_SSM      3
+#define PLL_MODE_MASK          3
+#define PLL_MODE_SHIFT         3
+#define PLL_ENABLE             2
+
+#define PLL_LOCK_SHIFT         0
+#define PLL_LOCK_MASK          1
+
+/* PLL FRQ register masks */
+#define PLL_NORM_FDBK_M_MASK   0xFF
+#define PLL_NORM_FDBK_M_SHIFT  24
+#define PLL_DITH_FDBK_M_MASK   0xFFFF
+#define PLL_DITH_FDBK_M_SHIFT  16
+#define PLL_DIV_P_MASK         0x7
+#define PLL_DIV_P_SHIFT                8
+#define PLL_DIV_N_MASK         0xFF
+#define PLL_DIV_N_SHIFT                0
+
+#define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw)
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
+
+/* Calculates pll clk rate for specific value of mode, m, n and p */
+static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
+               unsigned long prate, int index, unsigned long *pll_rate)
+{
+       unsigned long rate = prate;
+       unsigned int mode;
+
+       mode = rtbl[index].mode ? 256 : 1;
+       rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));
+
+       if (pll_rate)
+               *pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
+
+       return rate * 10000;
+}
+
+static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
+                               unsigned long *prate, int *index)
+{
+       struct clk_pll *pll = to_clk_pll(hw);
+       unsigned long prev_rate, vco_prev_rate, rate = 0;
+       unsigned long vco_parent_rate =
+               __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
+
+       if (!prate) {
+               pr_err("%s: prate is must for pll clk\n", __func__);
+               return -EINVAL;
+       }
+
+       for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) {
+               prev_rate = rate;
+               vco_prev_rate = *prate;
+               *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
+                               &rate);
+               if (drate < rate) {
+                       /* previous clock was best */
+                       if (*index) {
+                               rate = prev_rate;
+                               *prate = vco_prev_rate;
+                               (*index)--;
+                       }
+                       break;
+               }
+       }
+
+       return rate;
+}
+
+static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
+                               unsigned long *prate)
+{
+       int unused;
+
+       return clk_pll_round_rate_index(hw, drate, prate, &unused);
+}
+
+static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long
+               parent_rate)
+{
+       struct clk_pll *pll = to_clk_pll(hw);
+       unsigned long flags = 0;
+       unsigned int p;
+
+       if (pll->vco->lock)
+               spin_lock_irqsave(pll->vco->lock, flags);
+
+       p = readl_relaxed(pll->vco->cfg_reg);
+
+       if (pll->vco->lock)
+               spin_unlock_irqrestore(pll->vco->lock, flags);
+
+       p = (p >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
+
+       return parent_rate / (1 << p);
+}
+
+static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+                               unsigned long prate)
+{
+       struct clk_pll *pll = to_clk_pll(hw);
+       struct pll_rate_tbl *rtbl = pll->vco->rtbl;
+       unsigned long flags = 0, val;
+       int i;
+
+       clk_pll_round_rate_index(hw, drate, NULL, &i);
+
+       if (pll->vco->lock)
+               spin_lock_irqsave(pll->vco->lock, flags);
+
+       val = readl_relaxed(pll->vco->cfg_reg);
+       val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT);
+       val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
+       writel_relaxed(val, pll->vco->cfg_reg);
+
+       if (pll->vco->lock)
+               spin_unlock_irqrestore(pll->vco->lock, flags);
+
+       return 0;
+}
+
+static struct clk_ops clk_pll_ops = {
+       .recalc_rate = clk_pll_recalc_rate,
+       .round_rate = clk_pll_round_rate,
+       .set_rate = clk_pll_set_rate,
+};
+
+static inline unsigned long vco_calc_rate(struct clk_hw *hw,
+               unsigned long prate, int index)
+{
+       struct clk_vco *vco = to_clk_vco(hw);
+
+       return pll_calc_rate(vco->rtbl, prate, index, NULL);
+}
+
+static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
+               unsigned long *prate)
+{
+       struct clk_vco *vco = to_clk_vco(hw);
+       int unused;
+
+       return clk_round_rate_index(hw, drate, *prate, vco_calc_rate,
+                       vco->rtbl_cnt, &unused);
+}
+
+static unsigned long clk_vco_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       struct clk_vco *vco = to_clk_vco(hw);
+       unsigned long flags = 0;
+       unsigned int num = 2, den = 0, val, mode = 0;
+
+       if (vco->lock)
+               spin_lock_irqsave(vco->lock, flags);
+
+       mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK;
+
+       val = readl_relaxed(vco->cfg_reg);
+
+       if (vco->lock)
+               spin_unlock_irqrestore(vco->lock, flags);
+
+       den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
+
+       /* calculate numerator & denominator */
+       if (!mode) {
+               /* Normal mode */
+               num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
+       } else {
+               /* Dithered mode */
+               num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
+               den *= 256;
+       }
+
+       if (!den) {
+               WARN(1, "%s: denominator can't be zero\n", __func__);
+               return 0;
+       }
+
+       return (((parent_rate / 10000) * num) / den) * 10000;
+}
+
+/* Configures new clock rate of vco */
+static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate,
+                               unsigned long prate)
+{
+       struct clk_vco *vco = to_clk_vco(hw);
+       struct pll_rate_tbl *rtbl = vco->rtbl;
+       unsigned long flags = 0, val;
+       int i;
+
+       clk_round_rate_index(hw, drate, prate, vco_calc_rate, vco->rtbl_cnt,
+                       &i);
+
+       if (vco->lock)
+               spin_lock_irqsave(vco->lock, flags);
+
+       val = readl_relaxed(vco->mode_reg);
+       val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
+       val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
+       writel_relaxed(val, vco->mode_reg);
+
+       val = readl_relaxed(vco->cfg_reg);
+       val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT);
+       val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
+
+       val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT);
+       if (rtbl[i].mode)
+               val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
+                       PLL_DITH_FDBK_M_SHIFT;
+       else
+               val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
+                       PLL_NORM_FDBK_M_SHIFT;
+
+       writel_relaxed(val, vco->cfg_reg);
+
+       if (vco->lock)
+               spin_unlock_irqrestore(vco->lock, flags);
+
+       return 0;
+}
+
+static struct clk_ops clk_vco_ops = {
+       .recalc_rate = clk_vco_recalc_rate,
+       .round_rate = clk_vco_round_rate,
+       .set_rate = clk_vco_set_rate,
+};
+
+struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
+               const char *vco_gate_name, const char *parent_name,
+               unsigned long flags, void __iomem *mode_reg, void __iomem
+               *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
+               spinlock_t *lock, struct clk **pll_clk,
+               struct clk **vco_gate_clk)
+{
+       struct clk_vco *vco;
+       struct clk_pll *pll;
+       struct clk *vco_clk, *tpll_clk, *tvco_gate_clk;
+       struct clk_init_data vco_init, pll_init;
+       const char **vco_parent_name;
+
+       if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg ||
+                       !rtbl || !rtbl_cnt) {
+               pr_err("Invalid arguments passed");
+               return ERR_PTR(-EINVAL);
+       }
+
+       vco = kzalloc(sizeof(*vco), GFP_KERNEL);
+       if (!vco) {
+               pr_err("could not allocate vco clk\n");
+               return ERR_PTR(-ENOMEM);
+       }
+
+       pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+       if (!pll) {
+               pr_err("could not allocate pll clk\n");
+               goto free_vco;
+       }
+
+       /* struct clk_vco assignments */
+       vco->mode_reg = mode_reg;
+       vco->cfg_reg = cfg_reg;
+       vco->rtbl = rtbl;
+       vco->rtbl_cnt = rtbl_cnt;
+       vco->lock = lock;
+       vco->hw.init = &vco_init;
+
+       pll->vco = vco;
+       pll->hw.init = &pll_init;
+
+       if (vco_gate_name) {
+               tvco_gate_clk = clk_register_gate(NULL, vco_gate_name,
+                               parent_name, 0, mode_reg, PLL_ENABLE, 0, lock);
+               if (IS_ERR_OR_NULL(tvco_gate_clk))
+                       goto free_pll;
+
+               if (vco_gate_clk)
+                       *vco_gate_clk = tvco_gate_clk;
+               vco_parent_name = &vco_gate_name;
+       } else {
+               vco_parent_name = &parent_name;
+       }
+
+       vco_init.name = vco_name;
+       vco_init.ops = &clk_vco_ops;
+       vco_init.flags = flags;
+       vco_init.parent_names = vco_parent_name;
+       vco_init.num_parents = 1;
+
+       pll_init.name = pll_name;
+       pll_init.ops = &clk_pll_ops;
+       pll_init.flags = CLK_SET_RATE_PARENT;
+       pll_init.parent_names = &vco_name;
+       pll_init.num_parents = 1;
+
+       vco_clk = clk_register(NULL, &vco->hw);
+       if (IS_ERR_OR_NULL(vco_clk))
+               goto free_pll;
+
+       tpll_clk = clk_register(NULL, &pll->hw);
+       if (IS_ERR_OR_NULL(tpll_clk))
+               goto free_pll;
+
+       if (pll_clk)
+               *pll_clk = tpll_clk;
+
+       return vco_clk;
+
+free_pll:
+       kfree(pll);
+free_vco:
+       kfree(vco);
+
+       pr_err("Failed to register vco pll clock\n");
+
+       return ERR_PTR(-ENOMEM);
+}

diff --git a/drivers/clk/spear/clk.c b/drivers/clk/spear/clk.c
new file mode 100644 (file)
index 0000000..376d4e5
--- /dev/null
+++ b/drivers/clk/spear/clk.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * SPEAr clk - Common routines
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/types.h>
+#include "clk.h"
+
+long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
+               unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
+               int *index)
+{
+       unsigned long prev_rate, rate = 0;
+
+       for (*index = 0; *index < rtbl_cnt; (*index)++) {
+               prev_rate = rate;
+               rate = calc_rate(hw, parent_rate, *index);
+               if (drate < rate) {
+                       /* previous clock was best */
+                       if (*index) {
+                               rate = prev_rate;
+                               (*index)--;
+                       }
+                       break;
+               }
+       }
+
+       return rate;
+}

diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h
new file mode 100644 (file)
index 0000000..3321c46
--- /dev/null
+++ b/drivers/clk/spear/clk.h
@@ -0,0 +1,134 @@
+/*
+ * Clock framework definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __SPEAR_CLK_H
+#define __SPEAR_CLK_H
+
+#include <linux/clk-provider.h>
+#include <linux/spinlock_types.h>
+#include <linux/types.h>
+
+/* Auxiliary Synth clk */
+/* Default masks */
+#define AUX_EQ_SEL_SHIFT       30
+#define AUX_EQ_SEL_MASK                1
+#define AUX_EQ1_SEL            0
+#define AUX_EQ2_SEL            1
+#define AUX_XSCALE_SHIFT       16
+#define AUX_XSCALE_MASK                0xFFF
+#define AUX_YSCALE_SHIFT       0
+#define AUX_YSCALE_MASK                0xFFF
+#define AUX_SYNT_ENB           31
+
+struct aux_clk_masks {
+       u32 eq_sel_mask;
+       u32 eq_sel_shift;
+       u32 eq1_mask;
+       u32 eq2_mask;
+       u32 xscale_sel_mask;
+       u32 xscale_sel_shift;
+       u32 yscale_sel_mask;
+       u32 yscale_sel_shift;
+       u32 enable_bit;
+};
+
+struct aux_rate_tbl {
+       u16 xscale;
+       u16 yscale;
+       u8 eq;
+};
+
+struct clk_aux {
+       struct                  clk_hw hw;
+       void __iomem            *reg;
+       struct aux_clk_masks    *masks;
+       struct aux_rate_tbl     *rtbl;
+       u8                      rtbl_cnt;
+       spinlock_t              *lock;
+};
+
+/* Fractional Synth clk */
+struct frac_rate_tbl {
+       u32 div;
+};
+
+struct clk_frac {
+       struct                  clk_hw hw;
+       void __iomem            *reg;
+       struct frac_rate_tbl    *rtbl;
+       u8                      rtbl_cnt;
+       spinlock_t              *lock;
+};
+
+/* GPT clk */
+struct gpt_rate_tbl {
+       u16 mscale;
+       u16 nscale;
+};
+
+struct clk_gpt {
+       struct                  clk_hw hw;
+       void __iomem            *reg;
+       struct gpt_rate_tbl     *rtbl;
+       u8                      rtbl_cnt;
+       spinlock_t              *lock;
+};
+
+/* VCO-PLL clk */
+struct pll_rate_tbl {
+       u8 mode;
+       u16 m;
+       u8 n;
+       u8 p;
+};
+
+struct clk_vco {
+       struct                  clk_hw hw;
+       void __iomem            *mode_reg;
+       void __iomem            *cfg_reg;
+       struct pll_rate_tbl     *rtbl;
+       u8                      rtbl_cnt;
+       spinlock_t              *lock;
+};
+
+struct clk_pll {
+       struct                  clk_hw hw;
+       struct clk_vco          *vco;
+       const char              *parent[1];
+       spinlock_t              *lock;
+};
+
+typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
+               int index);
+
+/* clk register routines */
+struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
+               const char *parent_name, unsigned long flags, void __iomem *reg,
+               struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
+               u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
+struct clk *clk_register_frac(const char *name, const char *parent_name,
+               unsigned long flags, void __iomem *reg,
+               struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock);
+struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
+               long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8
+               rtbl_cnt, spinlock_t *lock);
+struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
+               const char *vco_gate_name, const char *parent_name,
+               unsigned long flags, void __iomem *mode_reg, void __iomem
+               *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
+               spinlock_t *lock, struct clk **pll_clk,
+               struct clk **vco_gate_clk);
+
+long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
+               unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
+               int *index);
+
+#endif /* __SPEAR_CLK_H */

diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
new file mode 100644 (file)
index 0000000..440bb3e
--- /dev/null
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -0,0 +1,612 @@
+/*
+ * SPEAr3xx machines clock framework source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/spinlock_types.h>
+#include <mach/misc_regs.h>
+#include "clk.h"
+
+static DEFINE_SPINLOCK(_lock);
+
+#define PLL1_CTR                       (MISC_BASE + 0x008)
+#define PLL1_FRQ                       (MISC_BASE + 0x00C)
+#define PLL2_CTR                       (MISC_BASE + 0x014)
+#define PLL2_FRQ                       (MISC_BASE + 0x018)
+#define PLL_CLK_CFG                    (MISC_BASE + 0x020)
+       /* PLL_CLK_CFG register masks */
+       #define MCTR_CLK_SHIFT          28
+       #define MCTR_CLK_MASK           3
+
+#define CORE_CLK_CFG                   (MISC_BASE + 0x024)
+       /* CORE CLK CFG register masks */
+       #define GEN_SYNTH2_3_CLK_SHIFT  18
+       #define GEN_SYNTH2_3_CLK_MASK   1
+
+       #define HCLK_RATIO_SHIFT        10
+       #define HCLK_RATIO_MASK         2
+       #define PCLK_RATIO_SHIFT        8
+       #define PCLK_RATIO_MASK         2
+
+#define PERIP_CLK_CFG                  (MISC_BASE + 0x028)
+       /* PERIP_CLK_CFG register masks */
+       #define UART_CLK_SHIFT          4
+       #define UART_CLK_MASK           1
+       #define FIRDA_CLK_SHIFT         5
+       #define FIRDA_CLK_MASK          2
+       #define GPT0_CLK_SHIFT          8
+       #define GPT1_CLK_SHIFT          11
+       #define GPT2_CLK_SHIFT          12
+       #define GPT_CLK_MASK            1
+
+#define PERIP1_CLK_ENB                 (MISC_BASE + 0x02C)
+       /* PERIP1_CLK_ENB register masks */
+       #define UART_CLK_ENB            3
+       #define SSP_CLK_ENB             5
+       #define I2C_CLK_ENB             7
+       #define JPEG_CLK_ENB            8
+       #define FIRDA_CLK_ENB           10
+       #define GPT1_CLK_ENB            11
+       #define GPT2_CLK_ENB            12
+       #define ADC_CLK_ENB             15
+       #define RTC_CLK_ENB             17
+       #define GPIO_CLK_ENB            18
+       #define DMA_CLK_ENB             19
+       #define SMI_CLK_ENB             21
+       #define GMAC_CLK_ENB            23
+       #define USBD_CLK_ENB            24
+       #define USBH_CLK_ENB            25
+       #define C3_CLK_ENB              31
+
+#define RAS_CLK_ENB                    (MISC_BASE + 0x034)
+       #define RAS_AHB_CLK_ENB         0
+       #define RAS_PLL1_CLK_ENB        1
+       #define RAS_APB_CLK_ENB         2
+       #define RAS_32K_CLK_ENB         3
+       #define RAS_24M_CLK_ENB         4
+       #define RAS_48M_CLK_ENB         5
+       #define RAS_PLL2_CLK_ENB        7
+       #define RAS_SYNT0_CLK_ENB       8
+       #define RAS_SYNT1_CLK_ENB       9
+       #define RAS_SYNT2_CLK_ENB       10
+       #define RAS_SYNT3_CLK_ENB       11
+
+#define PRSC0_CLK_CFG                  (MISC_BASE + 0x044)
+#define PRSC1_CLK_CFG                  (MISC_BASE + 0x048)
+#define PRSC2_CLK_CFG                  (MISC_BASE + 0x04C)
+#define AMEM_CLK_CFG                   (MISC_BASE + 0x050)
+       #define AMEM_CLK_ENB            0
+
+#define CLCD_CLK_SYNT                  (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT                 (MISC_BASE + 0x060)
+#define UART_CLK_SYNT                  (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT                  (MISC_BASE + 0x068)
+#define GEN0_CLK_SYNT                  (MISC_BASE + 0x06C)
+#define GEN1_CLK_SYNT                  (MISC_BASE + 0x070)
+#define GEN2_CLK_SYNT                  (MISC_BASE + 0x074)
+#define GEN3_CLK_SYNT                  (MISC_BASE + 0x078)
+
+/* pll rate configuration table, in ascending order of rates */
+static struct pll_rate_tbl pll_rtbl[] = {
+       {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
+       {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
+       {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
+};
+
+/* aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl aux_rtbl[] = {
+       /* For PLL1 = 332 MHz */
+       {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
+       {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
+       {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
+       {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
+};
+
+/* gpt rate configuration table, in ascending order of rates */
+static struct gpt_rate_tbl gpt_rtbl[] = {
+       /* For pll1 = 332 MHz */
+       {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
+       {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
+       {.mscale = 1, .nscale = 0}, /* 83 MHz */
+};
+
+/* clock parents */
+static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
+static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
+};
+static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", };
+static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", };
+static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
+static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
+static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
+       "pll2_clk", };
+
+#ifdef CONFIG_MACH_SPEAR300
+static void __init spear300_clk_init(void)
+{
+       struct clk *clk;
+
+       clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
+                       1, 1);
+       clk_register_clkdev(clk, NULL, "60000000.clcd");
+
+       clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "94000000.flash");
+
+       clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "70000000.sdhci");
+
+       clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "a9000000.gpio");
+
+       clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "a0000000.kbd");
+}
+#endif
+
+/* array of all spear 310 clock lookups */
+#ifdef CONFIG_MACH_SPEAR310
+static void __init spear310_clk_init(void)
+{
+       struct clk *clk;
+
+       clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, "emi", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "44000000.flash");
+
+       clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "tdm");
+
+       clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "b2000000.serial");
+
+       clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "b2080000.serial");
+
+       clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "b2100000.serial");
+
+       clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "b2180000.serial");
+
+       clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "b2200000.serial");
+}
+#endif
+
+/* array of all spear 320 clock lookups */
+#ifdef CONFIG_MACH_SPEAR320
+       #define SMII_PCLK_SHIFT                         18
+       #define SMII_PCLK_MASK                          2
+       #define SMII_PCLK_VAL_PAD                       0x0
+       #define SMII_PCLK_VAL_PLL2                      0x1
+       #define SMII_PCLK_VAL_SYNTH0                    0x2
+       #define SDHCI_PCLK_SHIFT                        15
+       #define SDHCI_PCLK_MASK                         1
+       #define SDHCI_PCLK_VAL_48M                      0x0
+       #define SDHCI_PCLK_VAL_SYNTH3                   0x1
+       #define I2S_REF_PCLK_SHIFT                      8
+       #define I2S_REF_PCLK_MASK                       1
+       #define I2S_REF_PCLK_SYNTH_VAL                  0x1
+       #define I2S_REF_PCLK_PLL2_VAL                   0x0
+       #define UART1_PCLK_SHIFT                        6
+       #define UART1_PCLK_MASK                         1
+       #define SPEAR320_UARTX_PCLK_VAL_SYNTH1          0x0
+       #define SPEAR320_UARTX_PCLK_VAL_APB             0x1
+
+static const char *i2s_ref_parents[] = { "ras_pll2_clk",
+       "ras_gen2_synth_gate_clk", };
+static const char *sdhci_parents[] = { "ras_pll3_48m_clk",
+       "ras_gen3_synth_gate_clk",
+};
+static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
+       "ras_gen0_synth_gate_clk", };
+static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk",
+};
+
+static void __init spear320_clk_init(void)
+{
+       struct clk *clk;
+
+       clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
+                       CLK_IS_ROOT, 125000000);
+       clk_register_clkdev(clk, "smii_125m_pad", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
+                       1, 1);
+       clk_register_clkdev(clk, NULL, "90000000.clcd");
+
+       clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, "emi", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "4c000000.flash");
+
+       clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "a7000000.i2c");
+
+       clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, "pwm", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "a5000000.spi");
+
+       clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "a6000000.spi");
+
+       clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "c_can_platform.0");
+
+       clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "c_can_platform.1");
+
+       clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "i2s");
+
+       clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
+                       ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG,
+                       I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "i2s_ref_clk", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1,
+                       4);
+       clk_register_clkdev(clk, "i2s_sclk", NULL);
+
+       clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
+                       ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                       SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                       &_lock);
+       clk_register_clkdev(clk, NULL, "a9300000.serial");
+
+       clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
+                       ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG,
+                       SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "70000000.sdhci");
+
+       clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
+                       ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
+                       SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "smii_pclk");
+
+       clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
+       clk_register_clkdev(clk, NULL, "smii");
+
+       clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
+                       ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG,
+                       UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "a3000000.serial");
+
+       clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
+                       ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                       SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                       &_lock);
+       clk_register_clkdev(clk, NULL, "a4000000.serial");
+
+       clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
+                       ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                       SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                       &_lock);
+       clk_register_clkdev(clk, NULL, "a9100000.serial");
+
+       clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
+                       ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                       SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                       &_lock);
+       clk_register_clkdev(clk, NULL, "a9200000.serial");
+
+       clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
+                       ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                       SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                       &_lock);
+       clk_register_clkdev(clk, NULL, "60000000.serial");
+
+       clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
+                       ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG,
+                       SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0,
+                       &_lock);
+       clk_register_clkdev(clk, NULL, "60100000.serial");
+}
+#endif
+
+void __init spear3xx_clk_init(void)
+{
+       struct clk *clk, *clk1;
+
+       clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+       clk_register_clkdev(clk, "apb_pclk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
+                       32000);
+       clk_register_clkdev(clk, "osc_32k_clk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
+                       24000000);
+       clk_register_clkdev(clk, "osc_24m_clk", NULL);
+
+       /* clock derived from 32 KHz osc clk */
+       clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
+                       PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "fc900000.rtc");
+
+       /* clock derived from 24 MHz osc clk */
+       clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
+                       48000000);
+       clk_register_clkdev(clk, "pll3_48m_clk", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "fc880000.wdt");
+
+       clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
+                       "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
+                       ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+       clk_register_clkdev(clk, "vco1_clk", NULL);
+       clk_register_clkdev(clk1, "pll1_clk", NULL);
+
+       clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
+                       "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
+                       ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+       clk_register_clkdev(clk, "vco2_clk", NULL);
+       clk_register_clkdev(clk1, "pll2_clk", NULL);
+
+       /* clock derived from pll1 clk */
+       clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
+       clk_register_clkdev(clk, "cpu_clk", NULL);
+
+       clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
+                       CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
+                       HCLK_RATIO_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "ahb_clk", NULL);
+
+       clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
+                       "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "uart_synth_clk", NULL);
+       clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
+
+       clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
+                       ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG,
+                       UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "uart0_mux_clk", NULL);
+
+       clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0,
+                       PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "d0000000.serial");
+
+       clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
+                       "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "firda_synth_clk", NULL);
+       clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
+
+       clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
+                       ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
+                       FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "firda_mux_clk", NULL);
+
+       clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
+                       PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "firda");
+
+       /* gpt clocks */
+       clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
+                       gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+       clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
+                       ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG,
+                       GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "gpt0");
+
+       clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
+                       gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+       clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents,
+                       ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG,
+                       GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
+       clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
+                       PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "gpt1");
+
+       clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
+                       gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+       clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
+                       ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
+                       GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
+       clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
+                       PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "gpt2");
+
+       /* general synths clocks */
+       clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk",
+                       "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "gen0_synth_clk", NULL);
+       clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL);
+
+       clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk",
+                       "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "gen1_synth_clk", NULL);
+       clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL);
+
+       clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents,
+                       ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
+                       GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
+                       &_lock);
+       clk_register_clkdev(clk, "gen2_3_parent_clk", NULL);
+
+       clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk",
+                       "gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "gen2_synth_clk", NULL);
+       clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL);
+
+       clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk",
+                       "gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "gen3_synth_clk", NULL);
+       clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL);
+
+       /* clock derived from pll3 clk */
+       clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0,
+                       PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "usbh_clk", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, "usbh.0_clk", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, "usbh.1_clk", NULL);
+
+       clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
+                       PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "designware_udc");
+
+       /* clock derived from ahb clk */
+       clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
+                       1);
+       clk_register_clkdev(clk, "ahbmult2_clk", NULL);
+
+       clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
+                       ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
+                       MCTR_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "ddr_clk", NULL);
+
+       clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
+                       CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
+                       PCLK_RATIO_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "apb_clk", NULL);
+
+       clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
+                       AMEM_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "amem_clk", NULL);
+
+       clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       C3_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "c3_clk");
+
+       clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       DMA_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "fc400000.dma");
+
+       clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       GMAC_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "e0800000.eth");
+
+       clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       I2C_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "d0180000.i2c");
+
+       clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       JPEG_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "jpeg");
+
+       clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       SMI_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "fc000000.flash");
+
+       /* clock derived from apb clk */
+       clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       ADC_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "adc");
+
+       clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       GPIO_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "fc980000.gpio");
+
+       clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       SSP_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "d0100000.spi");
+
+       /* RAS clk enable */
+       clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
+                       RAS_AHB_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_ahb_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
+                       RAS_APB_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_apb_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
+                       RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_32k_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
+                       RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_24m_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
+                       RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_pll1_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
+                       RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_pll2_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0,
+                       RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk",
+                       "gen0_synth_gate_clk", 0, RAS_CLK_ENB,
+                       RAS_SYNT0_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk",
+                       "gen1_synth_gate_clk", 0, RAS_CLK_ENB,
+                       RAS_SYNT1_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk",
+                       "gen2_synth_gate_clk", 0, RAS_CLK_ENB,
+                       RAS_SYNT2_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL);
+
+       clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk",
+                       "gen3_synth_gate_clk", 0, RAS_CLK_ENB,
+                       RAS_SYNT3_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL);
+
+       if (of_machine_is_compatible("st,spear300"))
+               spear300_clk_init();
+       else if (of_machine_is_compatible("st,spear310"))
+               spear310_clk_init();
+       else if (of_machine_is_compatible("st,spear320"))
+               spear320_clk_init();
+}

diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
new file mode 100644 (file)
index 0000000..f9a20b3
--- /dev/null
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -0,0 +1,342 @@
+/*
+ * SPEAr6xx machines clock framework source file
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/misc_regs.h>
+#include "clk.h"
+
+static DEFINE_SPINLOCK(_lock);
+
+#define PLL1_CTR                       (MISC_BASE + 0x008)
+#define PLL1_FRQ                       (MISC_BASE + 0x00C)
+#define PLL2_CTR                       (MISC_BASE + 0x014)
+#define PLL2_FRQ                       (MISC_BASE + 0x018)
+#define PLL_CLK_CFG                    (MISC_BASE + 0x020)
+       /* PLL_CLK_CFG register masks */
+       #define MCTR_CLK_SHIFT          28
+       #define MCTR_CLK_MASK           3
+
+#define CORE_CLK_CFG                   (MISC_BASE + 0x024)
+       /* CORE CLK CFG register masks */
+       #define HCLK_RATIO_SHIFT        10
+       #define HCLK_RATIO_MASK         2
+       #define PCLK_RATIO_SHIFT        8
+       #define PCLK_RATIO_MASK         2
+
+#define PERIP_CLK_CFG                  (MISC_BASE + 0x028)
+       /* PERIP_CLK_CFG register masks */
+       #define CLCD_CLK_SHIFT          2
+       #define CLCD_CLK_MASK           2
+       #define UART_CLK_SHIFT          4
+       #define UART_CLK_MASK           1
+       #define FIRDA_CLK_SHIFT         5
+       #define FIRDA_CLK_MASK          2
+       #define GPT0_CLK_SHIFT          8
+       #define GPT1_CLK_SHIFT          10
+       #define GPT2_CLK_SHIFT          11
+       #define GPT3_CLK_SHIFT          12
+       #define GPT_CLK_MASK            1
+
+#define PERIP1_CLK_ENB                 (MISC_BASE + 0x02C)
+       /* PERIP1_CLK_ENB register masks */
+       #define UART0_CLK_ENB           3
+       #define UART1_CLK_ENB           4
+       #define SSP0_CLK_ENB            5
+       #define SSP1_CLK_ENB            6
+       #define I2C_CLK_ENB             7
+       #define JPEG_CLK_ENB            8
+       #define FSMC_CLK_ENB            9
+       #define FIRDA_CLK_ENB           10
+       #define GPT2_CLK_ENB            11
+       #define GPT3_CLK_ENB            12
+       #define GPIO2_CLK_ENB           13
+       #define SSP2_CLK_ENB            14
+       #define ADC_CLK_ENB             15
+       #define GPT1_CLK_ENB            11
+       #define RTC_CLK_ENB             17
+       #define GPIO1_CLK_ENB           18
+       #define DMA_CLK_ENB             19
+       #define SMI_CLK_ENB             21
+       #define CLCD_CLK_ENB            22
+       #define GMAC_CLK_ENB            23
+       #define USBD_CLK_ENB            24
+       #define USBH0_CLK_ENB           25
+       #define USBH1_CLK_ENB           26
+
+#define PRSC0_CLK_CFG                  (MISC_BASE + 0x044)
+#define PRSC1_CLK_CFG                  (MISC_BASE + 0x048)
+#define PRSC2_CLK_CFG                  (MISC_BASE + 0x04C)
+
+#define CLCD_CLK_SYNT                  (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT                 (MISC_BASE + 0x060)
+#define UART_CLK_SYNT                  (MISC_BASE + 0x064)
+
+/* vco rate configuration table, in ascending order of rates */
+static struct pll_rate_tbl pll_rtbl[] = {
+       {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
+       {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
+       {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
+};
+
+/* aux rate configuration table, in ascending order of rates */
+static struct aux_rate_tbl aux_rtbl[] = {
+       /* For PLL1 = 332 MHz */
+       {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
+       {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
+       {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
+};
+
+static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", };
+static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
+};
+static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
+static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", };
+static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
+static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", };
+static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
+       "pll2_clk", };
+
+/* gpt rate configuration table, in ascending order of rates */
+static struct gpt_rate_tbl gpt_rtbl[] = {
+       /* For pll1 = 332 MHz */
+       {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
+       {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
+       {.mscale = 1, .nscale = 0}, /* 83 MHz */
+};
+
+void __init spear6xx_clk_init(void)
+{
+       struct clk *clk, *clk1;
+
+       clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+       clk_register_clkdev(clk, "apb_pclk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
+                       32000);
+       clk_register_clkdev(clk, "osc_32k_clk", NULL);
+
+       clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT,
+                       30000000);
+       clk_register_clkdev(clk, "osc_30m_clk", NULL);
+
+       /* clock derived from 32 KHz osc clk */
+       clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
+                       PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "rtc-spear");
+
+       /* clock derived from 30 MHz osc clk */
+       clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0,
+                       48000000);
+       clk_register_clkdev(clk, "pll3_48m_clk", NULL);
+
+       clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
+                       0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
+                       &_lock, &clk1, NULL);
+       clk_register_clkdev(clk, "vco1_clk", NULL);
+       clk_register_clkdev(clk1, "pll1_clk", NULL);
+
+       clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
+                       "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
+                       ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
+       clk_register_clkdev(clk, "vco2_clk", NULL);
+       clk_register_clkdev(clk1, "pll2_clk", NULL);
+
+       clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
+                       1);
+       clk_register_clkdev(clk, NULL, "wdt");
+
+       /* clock derived from pll1 clk */
+       clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
+       clk_register_clkdev(clk, "cpu_clk", NULL);
+
+       clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
+                       CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
+                       HCLK_RATIO_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "ahb_clk", NULL);
+
+       clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
+                       "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "uart_synth_clk", NULL);
+       clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
+
+       clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents,
+                       ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
+                       UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "uart_mux_clk", NULL);
+
+       clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0,
+                       PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "d0000000.serial");
+
+       clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0,
+                       PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "d0080000.serial");
+
+       clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk",
+                       "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "firda_synth_clk", NULL);
+       clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL);
+
+       clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents,
+                       ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
+                       FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "firda_mux_clk", NULL);
+
+       clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0,
+                       PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "firda");
+
+       clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk",
+                       "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl,
+                       ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
+       clk_register_clkdev(clk, "clcd_synth_clk", NULL);
+       clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL);
+
+       clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents,
+                       ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
+                       CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "clcd_mux_clk", NULL);
+
+       clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0,
+                       PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "clcd");
+
+       /* gpt clocks */
+       clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
+                       gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+       clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL);
+
+       clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents,
+                       ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
+                       GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "gpt0");
+
+       clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents,
+                       ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
+                       GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
+
+       clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
+                       PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "gpt1");
+
+       clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
+                       gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+       clk_register_clkdev(clk, "gpt2_synth_clk", NULL);
+
+       clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents,
+                       ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
+                       GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
+
+       clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
+                       PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "gpt2");
+
+       clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
+                       gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
+       clk_register_clkdev(clk, "gpt3_synth_clk", NULL);
+
+       clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents,
+                       ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
+                       GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
+
+       clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
+                       PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "gpt3");
+
+       /* clock derived from pll3 clk */
+       clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0,
+                       PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "usbh.0_clk");
+
+       clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0,
+                       PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "usbh.1_clk");
+
+       clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0,
+                       PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "designware_udc");
+
+       /* clock derived from ahb clk */
+       clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
+                       1);
+       clk_register_clkdev(clk, "ahbmult2_clk", NULL);
+
+       clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
+                       ARRAY_SIZE(ddr_parents),
+                       0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0,
+                       &_lock);
+       clk_register_clkdev(clk, "ddr_clk", NULL);
+
+       clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
+                       CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
+                       PCLK_RATIO_MASK, 0, &_lock);
+       clk_register_clkdev(clk, "apb_clk", NULL);
+
+       clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       DMA_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "fc400000.dma");
+
+       clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       FSMC_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "d1800000.flash");
+
+       clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       GMAC_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "gmac");
+
+       clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       I2C_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "d0200000.i2c");
+
+       clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       JPEG_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "jpeg");
+
+       clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
+                       SMI_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "fc000000.flash");
+
+       /* clock derived from apb clk */
+       clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       ADC_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "adc");
+
+       clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
+       clk_register_clkdev(clk, NULL, "f0100000.gpio");
+
+       clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       GPIO1_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "fc980000.gpio");
+
+       clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       GPIO2_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "d8100000.gpio");
+
+       clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       SSP0_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "ssp-pl022.0");
+
+       clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       SSP1_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "ssp-pl022.1");
+
+       clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
+                       SSP2_CLK_ENB, 0, &_lock);
+       clk_register_clkdev(clk, NULL, "ssp-pl022.2");
+}

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index c301a8e..3d704ab 100644 (file)
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -1429,6 +1429,7 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
                         * signal
                         */
                        release_phy_channel(plchan);
+                       plchan->phychan_hold = 0;
                }
                /* Dequeue jobs and free LLIs */
                if (plchan->at) {

diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index 7aa58d2..445fdf8 100644 (file)
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -221,10 +221,6 @@ static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
 
        vdbg_dump_regs(atchan);
 
-       /* clear any pending interrupt */
-       while (dma_readl(atdma, EBCISR))
-               cpu_relax();
-
        channel_writel(atchan, SADDR, 0);
        channel_writel(atchan, DADDR, 0);
        channel_writel(atchan, CTRLA, 0);

diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index a45b5d2..bb787d8 100644 (file)
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -571,11 +571,14 @@ static void imxdma_tasklet(unsigned long data)
        if (desc->desc.callback)
                desc->desc.callback(desc->desc.callback_param);
 
-       dma_cookie_complete(&desc->desc);
-
-       /* If we are dealing with a cyclic descriptor keep it on ld_active */
+       /* If we are dealing with a cyclic descriptor keep it on ld_active
+        * and dont mark the descripor as complete.
+        * Only in non-cyclic cases it would be marked as complete
+        */
        if (imxdma_chan_is_doing_cyclic(imxdmac))
                goto out;
+       else
+               dma_cookie_complete(&desc->desc);
 
        /* Free 2D slot if it was an interleaved transfer */
        if (imxdmac->enabled_2d) {

diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index d3e38e2..fddccae 100644 (file)
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -322,7 +322,8 @@ struct sdma_engine {
        struct sdma_context_data        *context;
        dma_addr_t                      context_phys;
        struct dma_device               dma_device;
-       struct clk                      *clk;
+       struct clk                      *clk_ipg;
+       struct clk                      *clk_ahb;
        struct mutex                    channel_0_lock;
        struct sdma_script_start_addrs  *script_addrs;
 };
@@ -859,7 +860,8 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
        sdmac->peripheral_type = data->peripheral_type;
        sdmac->event_id0 = data->dma_request;
 
-       clk_enable(sdmac->sdma->clk);
+       clk_enable(sdmac->sdma->clk_ipg);
+       clk_enable(sdmac->sdma->clk_ahb);
 
        ret = sdma_request_channel(sdmac);
        if (ret)
@@ -896,7 +898,8 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
 
        dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
 
-       clk_disable(sdma->clk);
+       clk_disable(sdma->clk_ipg);
+       clk_disable(sdma->clk_ahb);
 }
 
 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
@@ -1169,12 +1172,14 @@ static void sdma_load_firmware(const struct firmware *fw, void *context)
        addr = (void *)header + header->script_addrs_start;
        ram_code = (void *)header + header->ram_code_start;
 
-       clk_enable(sdma->clk);
+       clk_enable(sdma->clk_ipg);
+       clk_enable(sdma->clk_ahb);
        /* download the RAM image for SDMA */
        sdma_load_script(sdma, ram_code,
                        header->ram_code_size,
                        addr->ram_code_start_addr);
-       clk_disable(sdma->clk);
+       clk_disable(sdma->clk_ipg);
+       clk_disable(sdma->clk_ahb);
 
        sdma_add_scripts(sdma, addr);
 
@@ -1216,7 +1221,8 @@ static int __init sdma_init(struct sdma_engine *sdma)
                return -ENODEV;
        }
 
-       clk_enable(sdma->clk);
+       clk_enable(sdma->clk_ipg);
+       clk_enable(sdma->clk_ahb);
 
        /* Be sure SDMA has not started yet */
        writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
@@ -1269,12 +1275,14 @@ static int __init sdma_init(struct sdma_engine *sdma)
        /* Initializes channel's priorities */
        sdma_set_channel_priority(&sdma->channel[0], 7);
 
-       clk_disable(sdma->clk);
+       clk_disable(sdma->clk_ipg);
+       clk_disable(sdma->clk_ahb);
 
        return 0;
 
 err_dma_alloc:
-       clk_disable(sdma->clk);
+       clk_disable(sdma->clk_ipg);
+       clk_disable(sdma->clk_ahb);
        dev_err(sdma->dev, "initialisation failed with %d\n", ret);
        return ret;
 }
@@ -1313,12 +1321,21 @@ static int __init sdma_probe(struct platform_device *pdev)
                goto err_request_region;
        }
 
-       sdma->clk = clk_get(&pdev->dev, NULL);
-       if (IS_ERR(sdma->clk)) {
-               ret = PTR_ERR(sdma->clk);
+       sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+       if (IS_ERR(sdma->clk_ipg)) {
+               ret = PTR_ERR(sdma->clk_ipg);
                goto err_clk;
        }
 
+       sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
+       if (IS_ERR(sdma->clk_ahb)) {
+               ret = PTR_ERR(sdma->clk_ahb);
+               goto err_clk;
+       }
+
+       clk_prepare(sdma->clk_ipg);
+       clk_prepare(sdma->clk_ahb);
+
        sdma->regs = ioremap(iores->start, resource_size(iores));
        if (!sdma->regs) {
                ret = -ENOMEM;
@@ -1426,7 +1443,6 @@ err_alloc:
 err_request_irq:
        iounmap(sdma->regs);
 err_ioremap:
-       clk_put(sdma->clk);
 err_clk:
        release_mem_region(iores->start, resource_size(iores));
 err_request_region:

diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 62e3f8e..5ec7204 100644 (file)
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1715,7 +1715,7 @@ static int __init ipu_probe(struct platform_device *pdev)
        }
 
        /* Make sure IPU HSP clock is running */
-       clk_enable(ipu_data.ipu_clk);
+       clk_prepare_enable(ipu_data.ipu_clk);
 
        /* Disable all interrupts */
        idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
@@ -1747,7 +1747,7 @@ static int __init ipu_probe(struct platform_device *pdev)
 err_idmac_init:
 err_attach_irq:
        ipu_irq_detach_irq(&ipu_data, pdev);
-       clk_disable(ipu_data.ipu_clk);
+       clk_disable_unprepare(ipu_data.ipu_clk);
        clk_put(ipu_data.ipu_clk);
 err_clk_get:
        iounmap(ipu_data.reg_ic);
@@ -1765,7 +1765,7 @@ static int __exit ipu_remove(struct platform_device *pdev)
 
        ipu_idmac_exit(ipu);
        ipu_irq_detach_irq(ipu, pdev);
-       clk_disable(ipu->ipu_clk);
+       clk_disable_unprepare(ipu->ipu_clk);
        clk_put(ipu->ipu_clk);
        iounmap(ipu->reg_ic);
        iounmap(ipu->reg_ipu);

diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index c81ef7e..655d4ce 100644 (file)
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -201,10 +201,6 @@ static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
 
 static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
 {
-       struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan);
-
-       mxs_dma_enable_chan(mxs_chan);
-
        return dma_cookie_assign(tx);
 }
 
@@ -558,9 +554,9 @@ static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
 
 static void mxs_dma_issue_pending(struct dma_chan *chan)
 {
-       /*
-        * Nothing to do. We only have a single descriptor.
-        */
+       struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
+
+       mxs_dma_enable_chan(mxs_chan);
 }
 
 static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)

diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 282caf1..2ee6e23 100644 (file)
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2225,12 +2225,9 @@ static inline void free_desc_list(struct list_head *list)
 {
        struct dma_pl330_dmac *pdmac;
        struct dma_pl330_desc *desc;
-       struct dma_pl330_chan *pch;
+       struct dma_pl330_chan *pch = NULL;
        unsigned long flags;
 
-       if (list_empty(list))
-               return;
-
        /* Finish off the work list */
        list_for_each_entry(desc, list, node) {
                dma_async_tx_callback callback;
@@ -2247,6 +2244,10 @@ static inline void free_desc_list(struct list_head *list)
                desc->pchan = NULL;
        }
 
+       /* pch will be unset if list was empty */
+       if (!pch)
+               return;
+
        pdmac = pch->dmac;
 
        spin_lock_irqsave(&pdmac->pool_lock, flags);
@@ -2257,12 +2258,9 @@ static inline void free_desc_list(struct list_head *list)
 static inline void handle_cyclic_desc_list(struct list_head *list)
 {
        struct dma_pl330_desc *desc;
-       struct dma_pl330_chan *pch;
+       struct dma_pl330_chan *pch = NULL;
        unsigned long flags;
 
-       if (list_empty(list))
-               return;
-
        list_for_each_entry(desc, list, node) {
                dma_async_tx_callback callback;
 
@@ -2274,6 +2272,10 @@ static inline void handle_cyclic_desc_list(struct list_head *list)
                        callback(desc->txd.callback_param);
        }
 
+       /* pch will be unset if list was empty */
+       if (!pch)
+               return;
+
        spin_lock_irqsave(&pch->lock, flags);
        list_splice_tail_init(list, &pch->work_list);
        spin_unlock_irqrestore(&pch->lock, flags);
@@ -2926,8 +2928,11 @@ pl330_probe(struct amba_device *adev, const struct amba_id *id)
        INIT_LIST_HEAD(&pd->channels);
 
        /* Initialize channel parameters */
-       num_chan = max(pdat ? pdat->nr_valid_peri : (u8)pi->pcfg.num_peri,
-                       (u8)pi->pcfg.num_chan);
+       if (pdat)
+               num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan);
+       else
+               num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan);
+
        pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
 
        for (i = 0; i < num_chan; i++) {

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index bdd41d4..2ed1ac3 100644 (file)
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -18,6 +18,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/err.h>
 #include <linux/amba/bus.h>
+#include <linux/regulator/consumer.h>
 
 #include <plat/ste_dma40.h>
 
@@ -69,6 +70,22 @@ enum d40_command {
 };
 
 /*
+ * enum d40_events - The different Event Enables for the event lines.
+ *
+ * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
+ * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
+ * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
+ * @D40_ROUND_EVENTLINE: Status check for event line.
+ */
+
+enum d40_events {
+       D40_DEACTIVATE_EVENTLINE        = 0,
+       D40_ACTIVATE_EVENTLINE          = 1,
+       D40_SUSPEND_REQ_EVENTLINE       = 2,
+       D40_ROUND_EVENTLINE             = 3
+};
+
+/*
  * These are the registers that has to be saved and later restored
  * when the DMA hw is powered off.
  * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
@@ -870,8 +887,8 @@ static void d40_save_restore_registers(struct d40_base *base, bool save)
 }
 #endif
 
-static int d40_channel_execute_command(struct d40_chan *d40c,
-                                      enum d40_command command)
+static int __d40_execute_command_phy(struct d40_chan *d40c,
+                                    enum d40_command command)
 {
        u32 status;
        int i;
@@ -880,6 +897,12 @@ static int d40_channel_execute_command(struct d40_chan *d40c,
        unsigned long flags;
        u32 wmask;
 
+       if (command == D40_DMA_STOP) {
+               ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
+               if (ret)
+                       return ret;
+       }
+
        spin_lock_irqsave(&d40c->base->execmd_lock, flags);
 
        if (d40c->phy_chan->num % 2 == 0)
@@ -973,67 +996,109 @@ static void d40_term_all(struct d40_chan *d40c)
                }
 
        d40c->pending_tx = 0;
-       d40c->busy = false;
 }
 
-static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
-                                  u32 event, int reg)
+static void __d40_config_set_event(struct d40_chan *d40c,
+                                  enum d40_events event_type, u32 event,
+                                  int reg)
 {
        void __iomem *addr = chan_base(d40c) + reg;
        int tries;
+       u32 status;
+
+       switch (event_type) {
+
+       case D40_DEACTIVATE_EVENTLINE:
 
-       if (!enable) {
                writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
                       | ~D40_EVENTLINE_MASK(event), addr);
-               return;
-       }
+               break;
+
+       case D40_SUSPEND_REQ_EVENTLINE:
+               status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
+                         D40_EVENTLINE_POS(event);
+
+               if (status == D40_DEACTIVATE_EVENTLINE ||
+                   status == D40_SUSPEND_REQ_EVENTLINE)
+                       break;
 
+               writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
+                      | ~D40_EVENTLINE_MASK(event), addr);
+
+               for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
+
+                       status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
+                                 D40_EVENTLINE_POS(event);
+
+                       cpu_relax();
+                       /*
+                        * Reduce the number of bus accesses while
+                        * waiting for the DMA to suspend.
+                        */
+                       udelay(3);
+
+                       if (status == D40_DEACTIVATE_EVENTLINE)
+                               break;
+               }
+
+               if (tries == D40_SUSPEND_MAX_IT) {
+                       chan_err(d40c,
+                               "unable to stop the event_line chl %d (log: %d)"
+                               "status %x\n", d40c->phy_chan->num,
+                                d40c->log_num, status);
+               }
+               break;
+
+       case D40_ACTIVATE_EVENTLINE:
        /*
         * The hardware sometimes doesn't register the enable when src and dst
         * event lines are active on the same logical channel.  Retry to ensure
         * it does.  Usually only one retry is sufficient.
         */
-       tries = 100;
-       while (--tries) {
-               writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
-                      | ~D40_EVENTLINE_MASK(event), addr);
+               tries = 100;
+               while (--tries) {
+                       writel((D40_ACTIVATE_EVENTLINE <<
+                               D40_EVENTLINE_POS(event)) |
+                               ~D40_EVENTLINE_MASK(event), addr);
 
-               if (readl(addr) & D40_EVENTLINE_MASK(event))
-                       break;
-       }
+                       if (readl(addr) & D40_EVENTLINE_MASK(event))
+                               break;
+               }
 
-       if (tries != 99)
-               dev_dbg(chan2dev(d40c),
-                       "[%s] workaround enable S%cLNK (%d tries)\n",
-                       __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
-                       100 - tries);
+               if (tries != 99)
+                       dev_dbg(chan2dev(d40c),
+                               "[%s] workaround enable S%cLNK (%d tries)\n",
+                               __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
+                               100 - tries);
 
-       WARN_ON(!tries);
-}
+               WARN_ON(!tries);
+               break;
 
-static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
-{
-       unsigned long flags;
+       case D40_ROUND_EVENTLINE:
+               BUG();
+               break;
 
-       spin_lock_irqsave(&d40c->phy_chan->lock, flags);
+       }
+}
 
+static void d40_config_set_event(struct d40_chan *d40c,
+                                enum d40_events event_type)
+{
        /* Enable event line connected to device (or memcpy) */
        if ((d40c->dma_cfg.dir ==  STEDMA40_PERIPH_TO_MEM) ||
            (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
                u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
 
-               __d40_config_set_event(d40c, do_enable, event,
+               __d40_config_set_event(d40c, event_type, event,
                                       D40_CHAN_REG_SSLNK);
        }
 
        if (d40c->dma_cfg.dir !=  STEDMA40_PERIPH_TO_MEM) {
                u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
 
-               __d40_config_set_event(d40c, do_enable, event,
+               __d40_config_set_event(d40c, event_type, event,
                                       D40_CHAN_REG_SDLNK);
        }
-
-       spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
 }
 
 static u32 d40_chan_has_events(struct d40_chan *d40c)
@@ -1047,6 +1112,64 @@ static u32 d40_chan_has_events(struct d40_chan *d40c)
        return val;
 }
 
+static int
+__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
+{
+       unsigned long flags;
+       int ret = 0;
+       u32 active_status;
+       void __iomem *active_reg;
+
+       if (d40c->phy_chan->num % 2 == 0)
+               active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
+       else
+               active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
+
+
+       spin_lock_irqsave(&d40c->phy_chan->lock, flags);
+
+       switch (command) {
+       case D40_DMA_STOP:
+       case D40_DMA_SUSPEND_REQ:
+
+               active_status = (readl(active_reg) &
+                                D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
+                                D40_CHAN_POS(d40c->phy_chan->num);
+
+               if (active_status == D40_DMA_RUN)
+                       d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
+               else
+                       d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
+
+               if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
+                       ret = __d40_execute_command_phy(d40c, command);
+
+               break;
+
+       case D40_DMA_RUN:
+
+               d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
+               ret = __d40_execute_command_phy(d40c, command);
+               break;
+
+       case D40_DMA_SUSPENDED:
+               BUG();
+               break;
+       }
+
+       spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
+       return ret;
+}
+
+static int d40_channel_execute_command(struct d40_chan *d40c,
+                                      enum d40_command command)
+{
+       if (chan_is_logical(d40c))
+               return __d40_execute_command_log(d40c, command);
+       else
+               return __d40_execute_command_phy(d40c, command);
+}
+
 static u32 d40_get_prmo(struct d40_chan *d40c)
 {
        static const unsigned int phy_map[] = {
@@ -1149,15 +1272,7 @@ static int d40_pause(struct d40_chan *d40c)
        spin_lock_irqsave(&d40c->lock, flags);
 
        res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
-       if (res == 0) {
-               if (chan_is_logical(d40c)) {
-                       d40_config_set_event(d40c, false);
-                       /* Resume the other logical channels if any */
-                       if (d40_chan_has_events(d40c))
-                               res = d40_channel_execute_command(d40c,
-                                                                 D40_DMA_RUN);
-               }
-       }
+
        pm_runtime_mark_last_busy(d40c->base->dev);
        pm_runtime_put_autosuspend(d40c->base->dev);
        spin_unlock_irqrestore(&d40c->lock, flags);
@@ -1174,45 +1289,17 @@ static int d40_resume(struct d40_chan *d40c)
 
        spin_lock_irqsave(&d40c->lock, flags);
        pm_runtime_get_sync(d40c->base->dev);
-       if (d40c->base->rev == 0)
-               if (chan_is_logical(d40c)) {
-                       res = d40_channel_execute_command(d40c,
-                                                         D40_DMA_SUSPEND_REQ);
-                       goto no_suspend;
-               }
 
        /* If bytes left to transfer or linked tx resume job */
-       if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
-
-               if (chan_is_logical(d40c))
-                       d40_config_set_event(d40c, true);
-
+       if (d40_residue(d40c) || d40_tx_is_linked(d40c))
                res = d40_channel_execute_command(d40c, D40_DMA_RUN);
-       }
 
-no_suspend:
        pm_runtime_mark_last_busy(d40c->base->dev);
        pm_runtime_put_autosuspend(d40c->base->dev);
        spin_unlock_irqrestore(&d40c->lock, flags);
        return res;
 }
 
-static int d40_terminate_all(struct d40_chan *chan)
-{
-       unsigned long flags;
-       int ret = 0;
-
-       ret = d40_pause(chan);
-       if (!ret && chan_is_physical(chan))
-               ret = d40_channel_execute_command(chan, D40_DMA_STOP);
-
-       spin_lock_irqsave(&chan->lock, flags);
-       d40_term_all(chan);
-       spin_unlock_irqrestore(&chan->lock, flags);
-
-       return ret;
-}
-
 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 {
        struct d40_chan *d40c = container_of(tx->chan,
@@ -1232,20 +1319,6 @@ static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
 
 static int d40_start(struct d40_chan *d40c)
 {
-       if (d40c->base->rev == 0) {
-               int err;
-
-               if (chan_is_logical(d40c)) {
-                       err = d40_channel_execute_command(d40c,
-                                                         D40_DMA_SUSPEND_REQ);
-                       if (err)
-                               return err;
-               }
-       }
-
-       if (chan_is_logical(d40c))
-               d40_config_set_event(d40c, true);
-
        return d40_channel_execute_command(d40c, D40_DMA_RUN);
 }
 
@@ -1258,10 +1331,10 @@ static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
        d40d = d40_first_queued(d40c);
 
        if (d40d != NULL) {
-               if (!d40c->busy)
+               if (!d40c->busy) {
                        d40c->busy = true;
-
-               pm_runtime_get_sync(d40c->base->dev);
+                       pm_runtime_get_sync(d40c->base->dev);
+               }
 
                /* Remove from queue */
                d40_desc_remove(d40d);
@@ -1388,8 +1461,8 @@ static void dma_tasklet(unsigned long data)
 
        return;
 
- err:
-       /* Rescue manoeuvre if receiving double interrupts */
+err:
+       /* Rescue manouver if receiving double interrupts */
        if (d40c->pending_tx > 0)
                d40c->pending_tx--;
        spin_unlock_irqrestore(&d40c->lock, flags);
@@ -1770,7 +1843,6 @@ static int d40_config_memcpy(struct d40_chan *d40c)
        return 0;
 }
 
-
 static int d40_free_dma(struct d40_chan *d40c)
 {
 
@@ -1806,43 +1878,18 @@ static int d40_free_dma(struct d40_chan *d40c)
        }
 
        pm_runtime_get_sync(d40c->base->dev);
-       res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
+       res = d40_channel_execute_command(d40c, D40_DMA_STOP);
        if (res) {
-               chan_err(d40c, "suspend failed\n");
+               chan_err(d40c, "stop failed\n");
                goto out;
        }
 
-       if (chan_is_logical(d40c)) {
-               /* Release logical channel, deactivate the event line */
+       d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
 
-               d40_config_set_event(d40c, false);
+       if (chan_is_logical(d40c))
                d40c->base->lookup_log_chans[d40c->log_num] = NULL;
-
-               /*
-                * Check if there are more logical allocation
-                * on this phy channel.
-                */
-               if (!d40_alloc_mask_free(phy, is_src, event)) {
-                       /* Resume the other logical channels if any */
-                       if (d40_chan_has_events(d40c)) {
-                               res = d40_channel_execute_command(d40c,
-                                                                 D40_DMA_RUN);
-                               if (res)
-                                       chan_err(d40c,
-                                               "Executing RUN command\n");
-                       }
-                       goto out;
-               }
-       } else {
-               (void) d40_alloc_mask_free(phy, is_src, 0);
-       }
-
-       /* Release physical channel */
-       res = d40_channel_execute_command(d40c, D40_DMA_STOP);
-       if (res) {
-               chan_err(d40c, "Failed to stop channel\n");
-               goto out;
-       }
+       else
+               d40c->base->lookup_phy_chans[phy->num] = NULL;
 
        if (d40c->busy) {
                pm_runtime_mark_last_busy(d40c->base->dev);
@@ -1852,7 +1899,6 @@ static int d40_free_dma(struct d40_chan *d40c)
        d40c->busy = false;
        d40c->phy_chan = NULL;
        d40c->configured = false;
-       d40c->base->lookup_phy_chans[phy->num] = NULL;
 out:
 
        pm_runtime_mark_last_busy(d40c->base->dev);
@@ -2070,7 +2116,7 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
        if (sg_next(&sg_src[sg_len - 1]) == sg_src)
                desc->cyclic = true;
 
-       if (direction != DMA_NONE) {
+       if (direction != DMA_TRANS_NONE) {
                dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
 
                if (direction == DMA_DEV_TO_MEM)
@@ -2371,6 +2417,31 @@ static void d40_issue_pending(struct dma_chan *chan)
        spin_unlock_irqrestore(&d40c->lock, flags);
 }
 
+static void d40_terminate_all(struct dma_chan *chan)
+{
+       unsigned long flags;
+       struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
+       int ret;
+
+       spin_lock_irqsave(&d40c->lock, flags);
+
+       pm_runtime_get_sync(d40c->base->dev);
+       ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
+       if (ret)
+               chan_err(d40c, "Failed to stop channel\n");
+
+       d40_term_all(d40c);
+       pm_runtime_mark_last_busy(d40c->base->dev);
+       pm_runtime_put_autosuspend(d40c->base->dev);
+       if (d40c->busy) {
+               pm_runtime_mark_last_busy(d40c->base->dev);
+               pm_runtime_put_autosuspend(d40c->base->dev);
+       }
+       d40c->busy = false;
+
+       spin_unlock_irqrestore(&d40c->lock, flags);
+}
+
 static int
 dma40_config_to_halfchannel(struct d40_chan *d40c,
                            struct stedma40_half_channel_info *info,
@@ -2551,7 +2622,8 @@ static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
        switch (cmd) {
        case DMA_TERMINATE_ALL:
-               return d40_terminate_all(d40c);
+               d40_terminate_all(chan);
+               return 0;
        case DMA_PAUSE:
                return d40_pause(d40c);
        case DMA_RESUME:
@@ -2908,6 +2980,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
        dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
                 rev, res->start);
 
+       if (rev < 2) {
+               d40_err(&pdev->dev, "hardware revision: %d is not supported",
+                       rev);
+               goto failure;
+       }
+
        plat_data = pdev->dev.platform_data;
 
        /* Count the number of logical channels in use */
@@ -2998,6 +3076,7 @@ failure:
 
        if (base) {
                kfree(base->lcla_pool.alloc_map);
+               kfree(base->reg_val_backup_chan);
                kfree(base->lookup_log_chans);
                kfree(base->lookup_phy_chans);
                kfree(base->phy_res);

diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index 8d3d490..51e8e53 100644 (file)
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -62,8 +62,6 @@
 #define D40_SREG_ELEM_LOG_LIDX_MASK    (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
 
 /* Link register */
-#define D40_DEACTIVATE_EVENTLINE       0x0
-#define D40_ACTIVATE_EVENTLINE         0x1
 #define D40_EVENTLINE_POS(i)           (2 * i)
 #define D40_EVENTLINE_MASK(i)          (0x3 << D40_EVENTLINE_POS(i))
 

diff --git a/drivers/firmware/efivars.c b/drivers/firmware/efivars.c
index d25599f..47408e8 100644 (file)
--- a/drivers/firmware/efivars.c
+++ b/drivers/firmware/efivars.c
@@ -191,6 +191,190 @@ utf16_strncmp(const efi_char16_t *a, const efi_char16_t *b, size_t len)
        }
 }
 
+static bool
+validate_device_path(struct efi_variable *var, int match, u8 *buffer,
+                    unsigned long len)
+{
+       struct efi_generic_dev_path *node;
+       int offset = 0;
+
+       node = (struct efi_generic_dev_path *)buffer;
+
+       if (len < sizeof(*node))
+               return false;
+
+       while (offset <= len - sizeof(*node) &&
+              node->length >= sizeof(*node) &&
+               node->length <= len - offset) {
+               offset += node->length;
+
+               if ((node->type == EFI_DEV_END_PATH ||
+                    node->type == EFI_DEV_END_PATH2) &&
+                   node->sub_type == EFI_DEV_END_ENTIRE)
+                       return true;
+
+               node = (struct efi_generic_dev_path *)(buffer + offset);
+       }
+
+       /*
+        * If we're here then either node->length pointed past the end
+        * of the buffer or we reached the end of the buffer without
+        * finding a device path end node.
+        */
+       return false;
+}
+
+static bool
+validate_boot_order(struct efi_variable *var, int match, u8 *buffer,
+                   unsigned long len)
+{
+       /* An array of 16-bit integers */
+       if ((len % 2) != 0)
+               return false;
+
+       return true;
+}
+
+static bool
+validate_load_option(struct efi_variable *var, int match, u8 *buffer,
+                    unsigned long len)
+{
+       u16 filepathlength;
+       int i, desclength = 0, namelen;
+
+       namelen = utf16_strnlen(var->VariableName, sizeof(var->VariableName));
+
+       /* Either "Boot" or "Driver" followed by four digits of hex */
+       for (i = match; i < match+4; i++) {
+               if (var->VariableName[i] > 127 ||
+                   hex_to_bin(var->VariableName[i] & 0xff) < 0)
+                       return true;
+       }
+
+       /* Reject it if there's 4 digits of hex and then further content */
+       if (namelen > match + 4)
+               return false;
+
+       /* A valid entry must be at least 8 bytes */
+       if (len < 8)
+               return false;
+
+       filepathlength = buffer[4] | buffer[5] << 8;
+
+       /*
+        * There's no stored length for the description, so it has to be
+        * found by hand
+        */
+       desclength = utf16_strsize((efi_char16_t *)(buffer + 6), len - 6) + 2;
+
+       /* Each boot entry must have a descriptor */
+       if (!desclength)
+               return false;
+
+       /*
+        * If the sum of the length of the description, the claimed filepath
+        * length and the original header are greater than the length of the
+        * variable, it's malformed
+        */
+       if ((desclength + filepathlength + 6) > len)
+               return false;
+
+       /*
+        * And, finally, check the filepath
+        */
+       return validate_device_path(var, match, buffer + desclength + 6,
+                                   filepathlength);
+}
+
+static bool
+validate_uint16(struct efi_variable *var, int match, u8 *buffer,
+               unsigned long len)
+{
+       /* A single 16-bit integer */
+       if (len != 2)
+               return false;
+
+       return true;
+}
+
+static bool
+validate_ascii_string(struct efi_variable *var, int match, u8 *buffer,
+                     unsigned long len)
+{
+       int i;
+
+       for (i = 0; i < len; i++) {
+               if (buffer[i] > 127)
+                       return false;
+
+               if (buffer[i] == 0)
+                       return true;
+       }
+
+       return false;
+}
+
+struct variable_validate {
+       char *name;
+       bool (*validate)(struct efi_variable *var, int match, u8 *data,
+                        unsigned long len);
+};
+
+static const struct variable_validate variable_validate[] = {
+       { "BootNext", validate_uint16 },
+       { "BootOrder", validate_boot_order },
+       { "DriverOrder", validate_boot_order },
+       { "Boot*", validate_load_option },
+       { "Driver*", validate_load_option },
+       { "ConIn", validate_device_path },
+       { "ConInDev", validate_device_path },
+       { "ConOut", validate_device_path },
+       { "ConOutDev", validate_device_path },
+       { "ErrOut", validate_device_path },
+       { "ErrOutDev", validate_device_path },
+       { "Timeout", validate_uint16 },
+       { "Lang", validate_ascii_string },
+       { "PlatformLang", validate_ascii_string },
+       { "", NULL },
+};
+
+static bool
+validate_var(struct efi_variable *var, u8 *data, unsigned long len)
+{
+       int i;
+       u16 *unicode_name = var->VariableName;
+
+       for (i = 0; variable_validate[i].validate != NULL; i++) {
+               const char *name = variable_validate[i].name;
+               int match;
+
+               for (match = 0; ; match++) {
+                       char c = name[match];
+                       u16 u = unicode_name[match];
+
+                       /* All special variables are plain ascii */
+                       if (u > 127)
+                               return true;
+
+                       /* Wildcard in the matching name means we've matched */
+                       if (c == '*')
+                               return variable_validate[i].validate(var,
+                                                            match, data, len);
+
+                       /* Case sensitive match */
+                       if (c != u)
+                               break;
+
+                       /* Reached the end of the string while matching */
+                       if (!c)
+                               return variable_validate[i].validate(var,
+                                                            match, data, len);
+               }
+       }
+
+       return true;
+}
+
 static efi_status_t
 get_var_data_locked(struct efivars *efivars, struct efi_variable *var)
 {
@@ -324,6 +508,12 @@ efivar_store_raw(struct efivar_entry *entry, const char *buf, size_t count)
                return -EINVAL;
        }
 
+       if ((new_var->Attributes & ~EFI_VARIABLE_MASK) != 0 ||
+           validate_var(new_var, new_var->Data, new_var->DataSize) == false) {
+               printk(KERN_ERR "efivars: Malformed variable content\n");
+               return -EINVAL;
+       }
+
        spin_lock(&efivars->lock);
        status = efivars->ops->set_variable(new_var->VariableName,
                                            &new_var->VendorGuid,
@@ -626,6 +816,12 @@ static ssize_t efivar_create(struct file *filp, struct kobject *kobj,
        if (!capable(CAP_SYS_ADMIN))
                return -EACCES;
 
+       if ((new_var->Attributes & ~EFI_VARIABLE_MASK) != 0 ||
+           validate_var(new_var, new_var->Data, new_var->DataSize) == false) {
+               printk(KERN_ERR "efivars: Malformed variable content\n");
+               return -EINVAL;
+       }
+
        spin_lock(&efivars->lock);
 
        /*

diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 5689ce6..fc3ace3 100644 (file)
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -64,6 +64,7 @@ struct pxa_gpio_chip {
        unsigned long   irq_mask;
        unsigned long   irq_edge_rise;
        unsigned long   irq_edge_fall;
+       int (*set_wake)(unsigned int gpio, unsigned int on);
 
 #ifdef CONFIG_PM
        unsigned long   saved_gplr;
@@ -269,7 +270,8 @@ static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
                                (value ? GPSR_OFFSET : GPCR_OFFSET));
 }
 
-static int __devinit pxa_init_gpio_chip(int gpio_end)
+static int __devinit pxa_init_gpio_chip(int gpio_end,
+                                       int (*set_wake)(unsigned int, unsigned int))
 {
        int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
        struct pxa_gpio_chip *chips;
@@ -285,6 +287,7 @@ static int __devinit pxa_init_gpio_chip(int gpio_end)
 
                sprintf(chips[i].label, "gpio-%d", i);
                chips[i].regbase = gpio_reg_base + BANK_OFF(i);
+               chips[i].set_wake = set_wake;
 
                c->base  = gpio;
                c->label = chips[i].label;
@@ -412,6 +415,17 @@ static void pxa_mask_muxed_gpio(struct irq_data *d)
        writel_relaxed(gfer, c->regbase + GFER_OFFSET);
 }
 
+static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
+{
+       int gpio = pxa_irq_to_gpio(d->irq);
+       struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
+
+       if (c->set_wake)
+               return c->set_wake(gpio, on);
+       else
+               return 0;
+}
+
 static void pxa_unmask_muxed_gpio(struct irq_data *d)
 {
        int gpio = pxa_irq_to_gpio(d->irq);
@@ -427,6 +441,7 @@ static struct irq_chip pxa_muxed_gpio_chip = {
        .irq_mask       = pxa_mask_muxed_gpio,
        .irq_unmask     = pxa_unmask_muxed_gpio,
        .irq_set_type   = pxa_gpio_irq_type,
+       .irq_set_wake   = pxa_gpio_set_wake,
 };
 
 static int pxa_gpio_nums(void)
@@ -471,6 +486,7 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
        struct pxa_gpio_chip *c;
        struct resource *res;
        struct clk *clk;
+       struct pxa_gpio_platform_data *info;
        int gpio, irq, ret;
        int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
 
@@ -516,7 +532,8 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
        }
 
        /* Initialize GPIO chips */
-       pxa_init_gpio_chip(pxa_last_gpio);
+       info = dev_get_platdata(&pdev->dev);
+       pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
 
        /* clear all GPIO edge detects */
        for_each_gpio_chip(gpio, c) {

diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index 392ce71..1dffa83 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -149,22 +149,12 @@ static int exynos_drm_gem_map_pages(struct drm_gem_object *obj,
        unsigned long pfn;
 
        if (exynos_gem_obj->flags & EXYNOS_BO_NONCONTIG) {
-               unsigned long usize = buf->size;
-
                if (!buf->pages)
                        return -EINTR;
 
-               while (usize > 0) {
-                       pfn = page_to_pfn(buf->pages[page_offset++]);
-                       vm_insert_mixed(vma, f_vaddr, pfn);
-                       f_vaddr += PAGE_SIZE;
-                       usize -= PAGE_SIZE;
-               }
-
-               return 0;
-       }
-
-       pfn = (buf->dma_addr >> PAGE_SHIFT) + page_offset;
+               pfn = page_to_pfn(buf->pages[page_offset++]);
+       } else
+               pfn = (buf->dma_addr >> PAGE_SHIFT) + page_offset;
 
        return vm_insert_mixed(vma, f_vaddr, pfn);
 }
@@ -524,6 +514,8 @@ static int exynos_drm_gem_mmap_buffer(struct file *filp,
                if (!buffer->pages)
                        return -EINVAL;
 
+               vma->vm_flags |= VM_MIXEDMAP;
+
                do {
                        ret = vm_insert_page(vma, uaddr, buffer->pages[i++]);
                        if (ret) {
@@ -710,7 +702,6 @@ int exynos_drm_gem_dumb_destroy(struct drm_file *file_priv,
 int exynos_drm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 {
        struct drm_gem_object *obj = vma->vm_private_data;
-       struct exynos_drm_gem_obj *exynos_gem_obj = to_exynos_gem_obj(obj);
        struct drm_device *dev = obj->dev;
        unsigned long f_vaddr;
        pgoff_t page_offset;
@@ -722,21 +713,10 @@ int exynos_drm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 
        mutex_lock(&dev->struct_mutex);
 
-       /*
-        * allocate all pages as desired size if user wants to allocate
-        * physically non-continuous memory.
-        */
-       if (exynos_gem_obj->flags & EXYNOS_BO_NONCONTIG) {
-               ret = exynos_drm_gem_get_pages(obj);
-               if (ret < 0)
-                       goto err;
-       }
-
        ret = exynos_drm_gem_map_pages(obj, vma, f_vaddr, page_offset);
        if (ret < 0)
                DRM_ERROR("failed to map pages.\n");
 
-err:
        mutex_unlock(&dev->struct_mutex);
 
        return convert_to_vm_err_msg(ret);

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b505b70..e6162a1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1224,6 +1224,9 @@ static int i915_emon_status(struct seq_file *m, void *unused)
        unsigned long temp, chipset, gfx;
        int ret;
 
+       if (!IS_GEN5(dev))
+               return -ENODEV;
+
        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
                return ret;

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 785f67f..ba60f3c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1701,6 +1701,9 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv)
        unsigned long diffms;
        u32 count;
 
+       if (dev_priv->info->gen != 5)
+               return;
+
        getrawmonotonic(&now);
        diff1 = timespec_sub(now, dev_priv->last_time2);
 
@@ -2121,12 +2124,14 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
                    (unsigned long) dev);
 
-       spin_lock(&mchdev_lock);
-       i915_mch_dev = dev_priv;
-       dev_priv->mchdev_lock = &mchdev_lock;
-       spin_unlock(&mchdev_lock);
+       if (IS_GEN5(dev)) {
+               spin_lock(&mchdev_lock);
+               i915_mch_dev = dev_priv;
+               dev_priv->mchdev_lock = &mchdev_lock;
+               spin_unlock(&mchdev_lock);
 
-       ips_ping_for_i915_load();
+               ips_ping_for_i915_load();
+       }
 
        return 0;
 

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index f51a696..de43194 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1133,6 +1133,11 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                        return -EINVAL;
                }
 
+               if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
+                       DRM_DEBUG("execbuf with %u cliprects\n",
+                                 args->num_cliprects);
+                       return -EINVAL;
+               }
                cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
                                    GFP_KERNEL);
                if (cliprects == NULL) {
@@ -1404,7 +1409,8 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data,
        struct drm_i915_gem_exec_object2 *exec2_list = NULL;
        int ret;
 
-       if (args->buffer_count < 1) {
+       if (args->buffer_count < 1 ||
+           args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
                DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
                return -EINVAL;
        }

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4bb1ef..9d24d65 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -568,6 +568,7 @@
 #define   CM0_MASK_SHIFT          16
 #define   CM0_IZ_OPT_DISABLE      (1<<6)
 #define   CM0_ZR_OPT_DISABLE      (1<<5)
+#define          CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
 #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
 #define   CM0_COLOR_EVICT_DISABLE (1<<3)
 #define   CM0_DEPTH_WRITE_DISABLE (1<<1)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 4d3d736..90b9793 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -430,8 +430,8 @@ intel_crt_detect(struct drm_connector *connector, bool force)
 {
        struct drm_device *dev = connector->dev;
        struct intel_crt *crt = intel_attached_crt(connector);
-       struct drm_crtc *crtc;
        enum drm_connector_status status;
+       struct intel_load_detect_pipe tmp;
 
        if (I915_HAS_HOTPLUG(dev)) {
                if (intel_crt_detect_hotplug(connector)) {
@@ -450,23 +450,16 @@ intel_crt_detect(struct drm_connector *connector, bool force)
                return connector->status;
 
        /* for pre-945g platforms use load detect */
-       crtc = crt->base.base.crtc;
-       if (crtc && crtc->enabled) {
-               status = intel_crt_load_detect(crt);
-       } else {
-               struct intel_load_detect_pipe tmp;
-
-               if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
-                                              &tmp)) {
-                       if (intel_crt_detect_ddc(connector))
-                               status = connector_status_connected;
-                       else
-                               status = intel_crt_load_detect(crt);
-                       intel_release_load_detect_pipe(&crt->base, connector,
-                                                      &tmp);
-               } else
-                       status = connector_status_unknown;
-       }
+       if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
+                                      &tmp)) {
+               if (intel_crt_detect_ddc(connector))
+                       status = connector_status_connected;
+               else
+                       status = intel_crt_load_detect(crt);
+               intel_release_load_detect_pipe(&crt->base, connector,
+                                              &tmp);
+       } else
+               status = connector_status_unknown;
 
        return status;
 }

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5908cd5..1b1cf3b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7072,9 +7072,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
        struct drm_device *dev = crtc->dev;
        drm_i915_private_t *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       int pipe = intel_crtc->pipe;
-       int dpll_reg = DPLL(pipe);
-       int dpll = I915_READ(dpll_reg);
 
        if (HAS_PCH_SPLIT(dev))
                return;
@@ -7087,10 +7084,15 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
         * the manual case.
         */
        if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
+               int pipe = intel_crtc->pipe;
+               int dpll_reg = DPLL(pipe);
+               u32 dpll;
+
                DRM_DEBUG_DRIVER("downclocking LVDS\n");
 
                assert_panel_unlocked(dev_priv, pipe);
 
+               dpll = I915_READ(dpll_reg);
                dpll |= DISPLAY_RATE_SELECT_FPA1;
                I915_WRITE(dpll_reg, dpll);
                intel_wait_for_vblank(dev, pipe);
@@ -7098,7 +7100,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
                if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
                        DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
        }
-
 }
 
 /**

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index cae3e5f..2d7f47b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -136,7 +136,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
 
        val &= ~VIDEO_DIP_SELECT_MASK;
 
-       I915_WRITE(VIDEO_DIP_CTL, val | port | flags);
+       I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
 
        for (i = 0; i < len; i += 4) {
                I915_WRITE(VIDEO_DIP_DATA, *data);

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 30e2c82..9c71183 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -750,7 +750,7 @@ static const struct dmi_system_id intel_no_lvds[] = {
                .ident = "Hewlett-Packard t5745",
                .matches = {
                        DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
-                       DMI_MATCH(DMI_BOARD_NAME, "hp t5745"),
+                       DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
                },
        },
        {
@@ -758,7 +758,7 @@ static const struct dmi_system_id intel_no_lvds[] = {
                .ident = "Hewlett-Packard st5747",
                .matches = {
                        DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
-                       DMI_MATCH(DMI_BOARD_NAME, "hp st5747"),
+                       DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
                },
        },
        {

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f75806e..80fce51 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -401,6 +401,14 @@ static int init_render_ring(struct intel_ring_buffer *ring)
        if (INTEL_INFO(dev)->gen >= 6) {
                I915_WRITE(INSTPM,
                           INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
+
+               /* From the Sandybridge PRM, volume 1 part 3, page 24:
+                * "If this bit is set, STCunit will have LRA as replacement
+                *  policy. [...] This bit must be reset.  LRA replacement
+                *  policy is not supported."
+                */
+               I915_WRITE(CACHE_MODE_0,
+                          CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
        }
 
        return ret;

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index e36b171..232d77d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -731,6 +731,7 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
        uint16_t width, height;
        uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
        uint16_t h_sync_offset, v_sync_offset;
+       int mode_clock;
 
        width = mode->crtc_hdisplay;
        height = mode->crtc_vdisplay;
@@ -745,7 +746,11 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
        h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
        v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
 
-       dtd->part1.clock = mode->clock / 10;
+       mode_clock = mode->clock;
+       mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
+       mode_clock /= 10;
+       dtd->part1.clock = mode_clock;
+
        dtd->part1.h_active = width & 0xff;
        dtd->part1.h_blank = h_blank_len & 0xff;
        dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
@@ -996,7 +1001,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
        struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
        u32 sdvox;
        struct intel_sdvo_in_out_map in_out;
-       struct intel_sdvo_dtd input_dtd;
+       struct intel_sdvo_dtd input_dtd, output_dtd;
        int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
        int rate;
 
@@ -1021,20 +1026,13 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
                                          intel_sdvo->attached_output))
                return;
 
-       /* We have tried to get input timing in mode_fixup, and filled into
-        * adjusted_mode.
-        */
-       if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
-               input_dtd = intel_sdvo->input_dtd;
-       } else {
-               /* Set the output timing to the screen */
-               if (!intel_sdvo_set_target_output(intel_sdvo,
-                                                 intel_sdvo->attached_output))
-                       return;
-
-               intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
-               (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
-       }
+       /* lvds has a special fixed output timing. */
+       if (intel_sdvo->is_lvds)
+               intel_sdvo_get_dtd_from_mode(&output_dtd,
+                                            intel_sdvo->sdvo_lvds_fixed_mode);
+       else
+               intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
+       (void) intel_sdvo_set_output_timing(intel_sdvo, &output_dtd);
 
        /* Set the input timing to the screen. Assume always input 0. */
        if (!intel_sdvo_set_target_input(intel_sdvo))
@@ -1052,6 +1050,10 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
            !intel_sdvo_set_tv_format(intel_sdvo))
                return;
 
+       /* We have tried to get input timing in mode_fixup, and filled into
+        * adjusted_mode.
+        */
+       intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
        (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
 
        switch (pixel_multiplier) {

diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index 7814a76..284bd25 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -270,7 +270,7 @@ static bool nouveau_dsm_detect(void)
        struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
        struct pci_dev *pdev = NULL;
        int has_dsm = 0;
-       int has_optimus;
+       int has_optimus = 0;
        int vga_count = 0;
        bool guid_valid;
        int retval;

diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 80963d0..0be4a81 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -6156,10 +6156,14 @@ dcb_fake_connectors(struct nvbios *bios)
 
        /* heuristic: if we ever get a non-zero connector field, assume
         * that all the indices are valid and we don't need fake them.
+        *
+        * and, as usual, a blacklist of boards with bad bios data..
         */
-       for (i = 0; i < dcbt->entries; i++) {
-               if (dcbt->entry[i].connector)
-                       return;
+       if (!nv_match_device(bios->dev, 0x0392, 0x107d, 0x20a2)) {
+               for (i = 0; i < dcbt->entries; i++) {
+                       if (dcbt->entry[i].connector)
+                               return;
+               }
        }
 
        /* no useful connector info available, we need to make it up

diff --git a/drivers/gpu/drm/nouveau/nouveau_hdmi.c b/drivers/gpu/drm/nouveau/nouveau_hdmi.c
index 59ea1c1..c3de363 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_hdmi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hdmi.c
@@ -32,7 +32,9 @@ static bool
 hdmi_sor(struct drm_encoder *encoder)
 {
        struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
-       if (dev_priv->chipset < 0xa3)
+       if (dev_priv->chipset <  0xa3 ||
+           dev_priv->chipset == 0xaa ||
+           dev_priv->chipset == 0xac)
                return false;
        return true;
 }

diff --git a/drivers/gpu/drm/nouveau/nv10_gpio.c b/drivers/gpu/drm/nouveau/nv10_gpio.c
index 550ad3f..9d79180 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv10_gpio.c
+++ b/drivers/gpu/drm/nouveau/nv10_gpio.c
@@ -65,7 +65,7 @@ nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out)
        if (line < 10) {
                line = (line - 2) * 4;
                reg  = NV_PCRTC_GPIO_EXT;
-               mask = 0x00000003 << ((line - 2) * 4);
+               mask = 0x00000003;
                data = (dir << 1) | out;
        } else
        if (line < 14) {

diff --git a/drivers/gpu/drm/nouveau/nvc0_fb.c b/drivers/gpu/drm/nouveau/nvc0_fb.c
index 5bf5503..f704e94 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_fb.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fb.c
@@ -54,6 +54,11 @@ nvc0_mfb_isr(struct drm_device *dev)
                        nvc0_mfb_subp_isr(dev, unit, subp);
                units &= ~(1 << unit);
        }
+
+       /* we do something horribly wrong and upset PMFB a lot, so mask off
+        * interrupts from it after the first one until it's fixed
+        */
+       nv_mask(dev, 0x000640, 0x02000000, 0x00000000);
 }
 
 static void

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index b5ff1f7..af1054f 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -575,6 +575,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 
                if (rdev->family < CHIP_RV770)
                        pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
+               /* use frac fb div on APUs */
+               if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
+                       pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
        } else {
                pll->flags |= RADEON_PLL_LEGACY;
 
@@ -955,8 +958,8 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
                break;
        }
 
-       if (radeon_encoder->active_device &
-           (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
+       if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
+           (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
                struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
                struct drm_connector *connector =
                        radeon_get_connector_for_encoder(encoder);

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index ea7df16..5992502 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -241,8 +241,8 @@ int radeon_wb_init(struct radeon_device *rdev)
                                rdev->wb.use_event = true;
                }
        }
-       /* always use writeback/events on NI */
-       if (ASIC_IS_DCE5(rdev)) {
+       /* always use writeback/events on NI, APUs */
+       if (rdev->family >= CHIP_PALM) {
                rdev->wb.enabled = true;
                rdev->wb.use_event = true;
        }

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 8086c96..0a1d4bd 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -533,7 +533,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
                radeon_legacy_init_crtc(dev, radeon_crtc);
 }
 
-static const char *encoder_names[36] = {
+static const char *encoder_names[37] = {
        "NONE",
        "INTERNAL_LVDS",
        "INTERNAL_TMDS1",
@@ -570,6 +570,7 @@ static const char *encoder_names[36] = {
        "INTERNAL_UNIPHY2",
        "NUTMEG",
        "TRAVIS",
+       "INTERNAL_VCE"
 };
 
 static const char *connector_names[15] = {

diff --git a/drivers/hsi/clients/hsi_char.c b/drivers/hsi/clients/hsi_char.c
index 88a050d..3ad91f6 100644 (file)
--- a/drivers/hsi/clients/hsi_char.c
+++ b/drivers/hsi/clients/hsi_char.c
@@ -123,7 +123,7 @@ struct hsc_client_data {
 static unsigned int hsc_major;
 /* Maximum buffer size that hsi_char will accept from userspace */
 static unsigned int max_data_size = 0x1000;
-module_param(max_data_size, uint, S_IRUSR | S_IWUSR);
+module_param(max_data_size, uint, 0);
 MODULE_PARM_DESC(max_data_size, "max read/write data size [4,8..65536] (^2)");
 
 static void hsc_add_tail(struct hsc_channel *channel, struct hsi_msg *msg,

diff --git a/drivers/hsi/hsi.c b/drivers/hsi/hsi.c
index 4e2d79b..2d58f93 100644 (file)
--- a/drivers/hsi/hsi.c
+++ b/drivers/hsi/hsi.c
@@ -21,26 +21,13 @@
  */
 #include <linux/hsi/hsi.h>
 #include <linux/compiler.h>
-#include <linux/rwsem.h>
 #include <linux/list.h>
-#include <linux/spinlock.h>
 #include <linux/kobject.h>
 #include <linux/slab.h>
 #include <linux/string.h>
+#include <linux/notifier.h>
 #include "hsi_core.h"
 
-static struct device_type hsi_ctrl = {
-       .name   = "hsi_controller",
-};
-
-static struct device_type hsi_cl = {
-       .name   = "hsi_client",
-};
-
-static struct device_type hsi_port = {
-       .name   = "hsi_port",
-};
-
 static ssize_t modalias_show(struct device *dev,
                        struct device_attribute *a __maybe_unused, char *buf)
 {
@@ -54,8 +41,7 @@ static struct device_attribute hsi_bus_dev_attrs[] = {
 
 static int hsi_bus_uevent(struct device *dev, struct kobj_uevent_env *env)
 {
-       if (dev->type == &hsi_cl)
-               add_uevent_var(env, "MODALIAS=hsi:%s", dev_name(dev));
+       add_uevent_var(env, "MODALIAS=hsi:%s", dev_name(dev));
 
        return 0;
 }
@@ -80,12 +66,10 @@ static void hsi_client_release(struct device *dev)
 static void hsi_new_client(struct hsi_port *port, struct hsi_board_info *info)
 {
        struct hsi_client *cl;
-       unsigned long flags;
 
        cl = kzalloc(sizeof(*cl), GFP_KERNEL);
        if (!cl)
                return;
-       cl->device.type = &hsi_cl;
        cl->tx_cfg = info->tx_cfg;
        cl->rx_cfg = info->rx_cfg;
        cl->device.bus = &hsi_bus_type;
@@ -93,14 +77,11 @@ static void hsi_new_client(struct hsi_port *port, struct hsi_board_info *info)
        cl->device.release = hsi_client_release;
        dev_set_name(&cl->device, info->name);
        cl->device.platform_data = info->platform_data;
-       spin_lock_irqsave(&port->clock, flags);
-       list_add_tail(&cl->link, &port->clients);
-       spin_unlock_irqrestore(&port->clock, flags);
        if (info->archdata)
                cl->device.archdata = *info->archdata;
        if (device_register(&cl->device) < 0) {
                pr_err("hsi: failed to register client: %s\n", info->name);
-               kfree(cl);
+               put_device(&cl->device);
        }
 }
 
@@ -120,13 +101,6 @@ static void hsi_scan_board_info(struct hsi_controller *hsi)
 
 static int hsi_remove_client(struct device *dev, void *data __maybe_unused)
 {
-       struct hsi_client *cl = to_hsi_client(dev);
-       struct hsi_port *port = to_hsi_port(dev->parent);
-       unsigned long flags;
-
-       spin_lock_irqsave(&port->clock, flags);
-       list_del(&cl->link);
-       spin_unlock_irqrestore(&port->clock, flags);
        device_unregister(dev);
 
        return 0;
@@ -140,12 +114,17 @@ static int hsi_remove_port(struct device *dev, void *data __maybe_unused)
        return 0;
 }
 
-static void hsi_controller_release(struct device *dev __maybe_unused)
+static void hsi_controller_release(struct device *dev)
 {
+       struct hsi_controller *hsi = to_hsi_controller(dev);
+
+       kfree(hsi->port);
+       kfree(hsi);
 }
 
-static void hsi_port_release(struct device *dev __maybe_unused)
+static void hsi_port_release(struct device *dev)
 {
+       kfree(to_hsi_port(dev));
 }
 
 /**
@@ -170,20 +149,12 @@ int hsi_register_controller(struct hsi_controller *hsi)
        unsigned int i;
        int err;
 
-       hsi->device.type = &hsi_ctrl;
-       hsi->device.bus = &hsi_bus_type;
-       hsi->device.release = hsi_controller_release;
-       err = device_register(&hsi->device);
+       err = device_add(&hsi->device);
        if (err < 0)
                return err;
        for (i = 0; i < hsi->num_ports; i++) {
-               hsi->port[i].device.parent = &hsi->device;
-               hsi->port[i].device.bus = &hsi_bus_type;
-               hsi->port[i].device.release = hsi_port_release;
-               hsi->port[i].device.type = &hsi_port;
-               INIT_LIST_HEAD(&hsi->port[i].clients);
-               spin_lock_init(&hsi->port[i].clock);
-               err = device_register(&hsi->port[i].device);
+               hsi->port[i]->device.parent = &hsi->device;
+               err = device_add(&hsi->port[i]->device);
                if (err < 0)
                        goto out;
        }
@@ -192,7 +163,9 @@ int hsi_register_controller(struct hsi_controller *hsi)
 
        return 0;
 out:
-       hsi_unregister_controller(hsi);
+       while (i-- > 0)
+               device_del(&hsi->port[i]->device);
+       device_del(&hsi->device);
 
        return err;
 }
@@ -223,6 +196,29 @@ static inline int hsi_dummy_cl(struct hsi_client *cl __maybe_unused)
 }
 
 /**
+ * hsi_put_controller - Free an HSI controller
+ *
+ * @hsi: Pointer to the HSI controller to freed
+ *
+ * HSI controller drivers should only use this function if they need
+ * to free their allocated hsi_controller structures before a successful
+ * call to hsi_register_controller. Other use is not allowed.
+ */
+void hsi_put_controller(struct hsi_controller *hsi)
+{
+       unsigned int i;
+
+       if (!hsi)
+               return;
+
+       for (i = 0; i < hsi->num_ports; i++)
+               if (hsi->port && hsi->port[i])
+                       put_device(&hsi->port[i]->device);
+       put_device(&hsi->device);
+}
+EXPORT_SYMBOL_GPL(hsi_put_controller);
+
+/**
  * hsi_alloc_controller - Allocate an HSI controller and its ports
  * @n_ports: Number of ports on the HSI controller
  * @flags: Kernel allocation flags
@@ -232,55 +228,52 @@ static inline int hsi_dummy_cl(struct hsi_client *cl __maybe_unused)
 struct hsi_controller *hsi_alloc_controller(unsigned int n_ports, gfp_t flags)
 {
        struct hsi_controller   *hsi;
-       struct hsi_port         *port;
+       struct hsi_port         **port;
        unsigned int            i;
 
        if (!n_ports)
                return NULL;
 
-       port = kzalloc(sizeof(*port)*n_ports, flags);
-       if (!port)
-               return NULL;
        hsi = kzalloc(sizeof(*hsi), flags);
        if (!hsi)
-               goto out;
-       for (i = 0; i < n_ports; i++) {
-               dev_set_name(&port[i].device, "port%d", i);
-               port[i].num = i;
-               port[i].async = hsi_dummy_msg;
-               port[i].setup = hsi_dummy_cl;
-               port[i].flush = hsi_dummy_cl;
-               port[i].start_tx = hsi_dummy_cl;
-               port[i].stop_tx = hsi_dummy_cl;
-               port[i].release = hsi_dummy_cl;
-               mutex_init(&port[i].lock);
+               return NULL;
+       port = kzalloc(sizeof(*port)*n_ports, flags);
+       if (!port) {
+               kfree(hsi);
+               return NULL;
        }
        hsi->num_ports = n_ports;
        hsi->port = port;
+       hsi->device.release = hsi_controller_release;
+       device_initialize(&hsi->device);
+
+       for (i = 0; i < n_ports; i++) {
+               port[i] = kzalloc(sizeof(**port), flags);
+               if (port[i] == NULL)
+                       goto out;
+               port[i]->num = i;
+               port[i]->async = hsi_dummy_msg;
+               port[i]->setup = hsi_dummy_cl;
+               port[i]->flush = hsi_dummy_cl;
+               port[i]->start_tx = hsi_dummy_cl;
+               port[i]->stop_tx = hsi_dummy_cl;
+               port[i]->release = hsi_dummy_cl;
+               mutex_init(&port[i]->lock);
+               ATOMIC_INIT_NOTIFIER_HEAD(&port[i]->n_head);
+               dev_set_name(&port[i]->device, "port%d", i);
+               hsi->port[i]->device.release = hsi_port_release;
+               device_initialize(&hsi->port[i]->device);
+       }
 
        return hsi;
 out:
-       kfree(port);
+       hsi_put_controller(hsi);
 
        return NULL;
 }
 EXPORT_SYMBOL_GPL(hsi_alloc_controller);
 
 /**
- * hsi_free_controller - Free an HSI controller
- * @hsi: Pointer to HSI controller
- */
-void hsi_free_controller(struct hsi_controller *hsi)
-{
-       if (!hsi)
-               return;
-
-       kfree(hsi->port);
-       kfree(hsi);
-}
-EXPORT_SYMBOL_GPL(hsi_free_controller);
-
-/**
  * hsi_free_msg - Free an HSI message
  * @msg: Pointer to the HSI message
  *
@@ -414,37 +407,67 @@ void hsi_release_port(struct hsi_client *cl)
 }
 EXPORT_SYMBOL_GPL(hsi_release_port);
 
-static int hsi_start_rx(struct hsi_client *cl, void *data __maybe_unused)
+static int hsi_event_notifier_call(struct notifier_block *nb,
+                               unsigned long event, void *data __maybe_unused)
 {
-       if (cl->hsi_start_rx)
-               (*cl->hsi_start_rx)(cl);
+       struct hsi_client *cl = container_of(nb, struct hsi_client, nb);
+
+       (*cl->ehandler)(cl, event);
 
        return 0;
 }
 
-static int hsi_stop_rx(struct hsi_client *cl, void *data __maybe_unused)
+/**
+ * hsi_register_port_event - Register a client to receive port events
+ * @cl: HSI client that wants to receive port events
+ * @cb: Event handler callback
+ *
+ * Clients should register a callback to be able to receive
+ * events from the ports. Registration should happen after
+ * claiming the port.
+ * The handler can be called in interrupt context.
+ *
+ * Returns -errno on error, or 0 on success.
+ */
+int hsi_register_port_event(struct hsi_client *cl,
+                       void (*handler)(struct hsi_client *, unsigned long))
 {
-       if (cl->hsi_stop_rx)
-               (*cl->hsi_stop_rx)(cl);
+       struct hsi_port *port = hsi_get_port(cl);
 
-       return 0;
+       if (!handler || cl->ehandler)
+               return -EINVAL;
+       if (!hsi_port_claimed(cl))
+               return -EACCES;
+       cl->ehandler = handler;
+       cl->nb.notifier_call = hsi_event_notifier_call;
+
+       return atomic_notifier_chain_register(&port->n_head, &cl->nb);
 }
+EXPORT_SYMBOL_GPL(hsi_register_port_event);
 
-static int hsi_port_for_each_client(struct hsi_port *port, void *data,
-                               int (*fn)(struct hsi_client *cl, void *data))
+/**
+ * hsi_unregister_port_event - Stop receiving port events for a client
+ * @cl: HSI client that wants to stop receiving port events
+ *
+ * Clients should call this function before releasing their associated
+ * port.
+ *
+ * Returns -errno on error, or 0 on success.
+ */
+int hsi_unregister_port_event(struct hsi_client *cl)
 {
-       struct hsi_client *cl;
+       struct hsi_port *port = hsi_get_port(cl);
+       int err;
 
-       spin_lock(&port->clock);
-       list_for_each_entry(cl, &port->clients, link) {
-               spin_unlock(&port->clock);
-               (*fn)(cl, data);
-               spin_lock(&port->clock);
-       }
-       spin_unlock(&port->clock);
+       WARN_ON(!hsi_port_claimed(cl));
 
-       return 0;
+       err = atomic_notifier_chain_unregister(&port->n_head, &cl->nb);
+       if (!err)
+               cl->ehandler = NULL;
+
+       return err;
 }
+EXPORT_SYMBOL_GPL(hsi_unregister_port_event);
 
 /**
  * hsi_event -Notifies clients about port events
@@ -458,22 +481,12 @@ static int hsi_port_for_each_client(struct hsi_port *port, void *data,
  * Events:
  * HSI_EVENT_START_RX - Incoming wake line high
  * HSI_EVENT_STOP_RX - Incoming wake line down
+ *
+ * Returns -errno on error, or 0 on success.
  */
-void hsi_event(struct hsi_port *port, unsigned int event)
+int hsi_event(struct hsi_port *port, unsigned long event)
 {
-       int (*fn)(struct hsi_client *cl, void *data);
-
-       switch (event) {
-       case HSI_EVENT_START_RX:
-               fn = hsi_start_rx;
-               break;
-       case HSI_EVENT_STOP_RX:
-               fn = hsi_stop_rx;
-               break;
-       default:
-               return;
-       }
-       hsi_port_for_each_client(port, NULL, fn);
+       return atomic_notifier_call_chain(&port->n_head, event, NULL);
 }
 EXPORT_SYMBOL_GPL(hsi_event);
 

diff --git a/drivers/hwmon/ad7314.c b/drivers/hwmon/ad7314.c
index ce43642..f85ce70 100644 (file)
--- a/drivers/hwmon/ad7314.c
+++ b/drivers/hwmon/ad7314.c
@@ -47,7 +47,7 @@ struct ad7314_data {
        u16 rx ____cacheline_aligned;
 };
 
-static int ad7314_spi_read(struct ad7314_data *chip, s16 *data)
+static int ad7314_spi_read(struct ad7314_data *chip)
 {
        int ret;
 
@@ -57,9 +57,7 @@ static int ad7314_spi_read(struct ad7314_data *chip, s16 *data)
                return ret;
        }
 
-       *data = be16_to_cpu(chip->rx);
-
-       return ret;
+       return be16_to_cpu(chip->rx);
 }
 
 static ssize_t ad7314_show_temperature(struct device *dev,
@@ -70,12 +68,12 @@ static ssize_t ad7314_show_temperature(struct device *dev,
        s16 data;
        int ret;
 
-       ret = ad7314_spi_read(chip, &data);
+       ret = ad7314_spi_read(chip);
        if (ret < 0)
                return ret;
        switch (spi_get_device_id(chip->spi_dev)->driver_data) {
        case ad7314:
-               data = (data & AD7314_TEMP_MASK) >> AD7314_TEMP_OFFSET;
+               data = (ret & AD7314_TEMP_MASK) >> AD7314_TEMP_OFFSET;
                data = (data << 6) >> 6;
 
                return sprintf(buf, "%d\n", 250 * data);
@@ -86,7 +84,7 @@ static ssize_t ad7314_show_temperature(struct device *dev,
                 * with a sign bit - which is a 14 bit 2's complement
                 * register.  1lsb - 31.25 milli degrees centigrade
                 */
-               data &= ADT7301_TEMP_MASK;
+               data = ret & ADT7301_TEMP_MASK;
                data = (data << 2) >> 2;
 
                return sprintf(buf, "%d\n",

diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 0d3141f..b9d5123 100644 (file)
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -52,7 +52,7 @@ module_param_named(tjmax, force_tjmax, int, 0444);
 MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius");
 
 #define BASE_SYSFS_ATTR_NO     2       /* Sysfs Base attr no for coretemp */
-#define NUM_REAL_CORES         16      /* Number of Real cores per cpu */
+#define NUM_REAL_CORES         32      /* Number of Real cores per cpu */
 #define CORETEMP_NAME_LENGTH   17      /* String Length of attrs */
 #define MAX_CORE_ATTRS         4       /* Maximum no of basic attrs */
 #define TOTAL_ATTRS            (MAX_CORE_ATTRS + 1)
@@ -709,6 +709,10 @@ static void __cpuinit put_core_offline(unsigned int cpu)
 
        indx = TO_ATTR_NO(cpu);
 
+       /* The core id is too big, just return */
+       if (indx > MAX_CORE_DATA - 1)
+               return;
+
        if (pdata->core_data[indx] && pdata->core_data[indx]->cpu == cpu)
                coretemp_remove_core(pdata, &pdev->dev, indx);
 

diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
index 37a8fc9..e8e18ca 100644 (file)
--- a/drivers/hwmon/fam15h_power.c
+++ b/drivers/hwmon/fam15h_power.c
@@ -128,17 +128,20 @@ static bool __devinit fam15h_power_is_internal_node0(struct pci_dev *f4)
  * counter saturations resulting in bogus power readings.
  * We correct this value ourselves to cope with older BIOSes.
  */
+static DEFINE_PCI_DEVICE_TABLE(affected_device) = {
+       { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
+       { 0 }
+};
+
 static void __devinit tweak_runavg_range(struct pci_dev *pdev)
 {
        u32 val;
-       const struct pci_device_id affected_device = {
-               PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) };
 
        /*
         * let this quirk apply only to the current version of the
         * northbridge, since future versions may change the behavior
         */
-       if (!pci_match_id(&affected_device, pdev))
+       if (!pci_match_id(affected_device, pdev))
                return;
 
        pci_bus_read_config_dword(pdev->bus,

diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index f086131..c811289 100644 (file)
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -324,7 +324,7 @@ static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
 {
        long ret;
        ret = wait_event_timeout(pch_event,
-                       (adap->pch_event_flag != 0), msecs_to_jiffies(50));
+                       (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
 
        if (ret == 0) {
                pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
@@ -1063,6 +1063,6 @@ module_exit(pch_pci_exit);
 
 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
 MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.lapis-semi.com>");
+MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));

diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index dfb84b7..56bce9a 100644 (file)
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -51,6 +51,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_i2c.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <mach/irqs.h>
 #include <mach/hardware.h>
@@ -470,6 +471,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
        struct imx_i2c_struct *i2c_imx;
        struct resource *res;
        struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
+       struct pinctrl *pinctrl;
        void __iomem *base;
        resource_size_t res_size;
        int irq, bitrate;
@@ -520,6 +522,12 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
        i2c_imx->base                   = base;
        i2c_imx->res                    = res;
 
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
+               goto fail3;
+       }
+
        /* Get I2C clock */
        i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
        if (IS_ERR(i2c_imx->clk)) {

diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 3d471d5..7fa73ee 100644 (file)
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/jiffies.h>
 #include <linux/io.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <mach/common.h>
 
@@ -227,6 +228,7 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
                return -EINVAL;
 
        init_completion(&i2c->cmd_complete);
+       i2c->cmd_err = 0;
 
        flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
 
@@ -252,6 +254,9 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 
        if (i2c->cmd_err == -ENXIO)
                mxs_i2c_reset(i2c);
+       else
+               writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
+                               i2c->regs + MXS_I2C_QUEUECTRL_CLR);
 
        dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
 
@@ -299,8 +304,6 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
                    MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
                /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
                i2c->cmd_err = -EIO;
-       else
-               i2c->cmd_err = 0;
 
        is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
                MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
@@ -323,10 +326,15 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev)
        struct device *dev = &pdev->dev;
        struct mxs_i2c_dev *i2c;
        struct i2c_adapter *adap;
+       struct pinctrl *pinctrl;
        struct resource *res;
        resource_size_t res_size;
        int err, irq;
 
+       pinctrl = devm_pinctrl_get_select_default(dev);
+       if (IS_ERR(pinctrl))
+               return PTR_ERR(pinctrl);
+
        i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
        if (!i2c)
                return -ENOMEM;
@@ -384,8 +392,6 @@ static int __devexit mxs_i2c_remove(struct platform_device *pdev)
        if (ret)
                return -EBUSY;
 
-       writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
-                       i2c->regs + MXS_I2C_QUEUECTRL_CLR);
        writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 
        platform_set_drvdata(pdev, NULL);

diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c
index 04be9f8..eb8ad53 100644 (file)
--- a/drivers/i2c/busses/i2c-pnx.c
+++ b/drivers/i2c/busses/i2c-pnx.c
@@ -546,8 +546,7 @@ static int i2c_pnx_controller_suspend(struct platform_device *pdev,
 {
        struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
 
-       /* FIXME: shouldn't this be clk_disable? */
-       clk_enable(alg_data->clk);
+       clk_disable(alg_data->clk);
 
        return 0;
 }

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index e978635..55e5ea6 100644 (file)
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -516,6 +516,14 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
        if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
                return 0;
 
+       /*
+        * NACK interrupt is generated before the I2C controller generates the
+        * STOP condition on the bus. So wait for 2 clock periods before resetting
+        * the controller so that STOP condition has been delivered properly.
+        */
+       if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
+               udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
+
        tegra_i2c_init(i2c_dev);
        if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
                if (msg->flags & I2C_M_IGNORE_NAK)

diff --git a/drivers/infiniband/core/mad.c b/drivers/infiniband/core/mad.c
index 426bb76..b0d0bc8 100644 (file)
--- a/drivers/infiniband/core/mad.c
+++ b/drivers/infiniband/core/mad.c
@@ -1854,6 +1854,8 @@ static bool generate_unmatched_resp(struct ib_mad_private *recv,
                response->mad.mad.mad_hdr.method = IB_MGMT_METHOD_GET_RESP;
                response->mad.mad.mad_hdr.status =
                        cpu_to_be16(IB_MGMT_MAD_STATUS_UNSUPPORTED_METHOD_ATTRIB);
+               if (recv->mad.mad.mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
+                       response->mad.mad.mad_hdr.status |= IB_SMP_DIRECTION;
 
                return true;
        } else {
@@ -1869,6 +1871,7 @@ static void ib_mad_recv_done_handler(struct ib_mad_port_private *port_priv,
        struct ib_mad_list_head *mad_list;
        struct ib_mad_agent_private *mad_agent;
        int port_num;
+       int ret = IB_MAD_RESULT_SUCCESS;
 
        mad_list = (struct ib_mad_list_head *)(unsigned long)wc->wr_id;
        qp_info = mad_list->mad_queue->qp_info;
@@ -1952,8 +1955,6 @@ static void ib_mad_recv_done_handler(struct ib_mad_port_private *port_priv,
 local:
        /* Give driver "right of first refusal" on incoming MAD */
        if (port_priv->device->process_mad) {
-               int ret;
-
                ret = port_priv->device->process_mad(port_priv->device, 0,
                                                     port_priv->port_num,
                                                     wc, &recv->grh,
@@ -1981,7 +1982,8 @@ local:
                 * or via recv_handler in ib_mad_complete_recv()
                 */
                recv = NULL;
-       } else if (generate_unmatched_resp(recv, response)) {
+       } else if ((ret & IB_MAD_RESULT_SUCCESS) &&
+                  generate_unmatched_resp(recv, response)) {
                agent_send_response(&response->mad.mad, &recv->grh, wc,
                                    port_priv->device, port_num, qp_info->qp->qp_num);
        }

diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c
index 669673e..b948b6d 100644 (file)
--- a/drivers/infiniband/hw/mlx4/main.c
+++ b/drivers/infiniband/hw/mlx4/main.c
@@ -247,7 +247,7 @@ static int ib_link_query_port(struct ib_device *ibdev, u8 port,
                err = mlx4_MAD_IFC(to_mdev(ibdev), 1, 1, port,
                                   NULL, NULL, in_mad, out_mad);
                if (err)
-                       return err;
+                       goto out;
 
                /* Checking LinkSpeedActive for FDR-10 */
                if (out_mad->data[15] & 0x1)

diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
index 8081a0a..a4b14a4 100644 (file)
--- a/drivers/input/mouse/synaptics.c
+++ b/drivers/input/mouse/synaptics.c
@@ -274,7 +274,8 @@ static int synaptics_set_advanced_gesture_mode(struct psmouse *psmouse)
        static unsigned char param = 0xc8;
        struct synaptics_data *priv = psmouse->private;
 
-       if (!SYN_CAP_ADV_GESTURE(priv->ext_cap_0c))
+       if (!(SYN_CAP_ADV_GESTURE(priv->ext_cap_0c) ||
+             SYN_CAP_IMAGE_SENSOR(priv->ext_cap_0c)))
                return 0;
 
        if (psmouse_sliced_command(psmouse, SYN_QUE_MODEL))

diff --git a/drivers/md/bitmap.c b/drivers/md/bitmap.c
index 97e73e5..17e2b47 100644 (file)
--- a/drivers/md/bitmap.c
+++ b/drivers/md/bitmap.c
@@ -1727,8 +1727,7 @@ int bitmap_create(struct mddev *mddev)
        bitmap->chunkshift = (ffz(~mddev->bitmap_info.chunksize)
                              - BITMAP_BLOCK_SHIFT);
 
-       /* now that chunksize and chunkshift are set, we can use these macros */
-       chunks = (blocks + bitmap->chunkshift - 1) >>
+       chunks = (blocks + (1 << bitmap->chunkshift) - 1) >>
                        bitmap->chunkshift;
        pages = (chunks + PAGE_COUNTER_RATIO - 1) / PAGE_COUNTER_RATIO;
 

diff --git a/drivers/md/bitmap.h b/drivers/md/bitmap.h
index 55ca5ae..b44b0ab 100644 (file)
--- a/drivers/md/bitmap.h
+++ b/drivers/md/bitmap.h
@@ -101,9 +101,6 @@ typedef __u16 bitmap_counter_t;
 
 #define BITMAP_BLOCK_SHIFT 9
 
-/* how many blocks per chunk? (this is variable) */
-#define CHUNK_BLOCK_RATIO(bitmap) ((bitmap)->mddev->bitmap_info.chunksize >> BITMAP_BLOCK_SHIFT)
-
 #endif
 
 /*

diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c
index b0ba524..68965e6 100644 (file)
--- a/drivers/md/dm-raid.c
+++ b/drivers/md/dm-raid.c
@@ -859,7 +859,7 @@ static int analyse_superblocks(struct dm_target *ti, struct raid_set *rs)
        int ret;
        unsigned redundancy = 0;
        struct raid_dev *dev;
-       struct md_rdev *rdev, *freshest;
+       struct md_rdev *rdev, *tmp, *freshest;
        struct mddev *mddev = &rs->md;
 
        switch (rs->raid_type->level) {
@@ -877,7 +877,7 @@ static int analyse_superblocks(struct dm_target *ti, struct raid_set *rs)
        }
 
        freshest = NULL;
-       rdev_for_each(rdev, mddev) {
+       rdev_for_each_safe(rdev, tmp, mddev) {
                if (!rdev->meta_bdev)
                        continue;
 

diff --git a/drivers/md/md.c b/drivers/md/md.c
index b572e1e..477eb2e 100644 (file)
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -7560,14 +7560,14 @@ void md_check_recovery(struct mddev *mddev)
                 * any transients in the value of "sync_action".
                 */
                set_bit(MD_RECOVERY_RUNNING, &mddev->recovery);
-               clear_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
                /* Clear some bits that don't mean anything, but
                 * might be left set
                 */
                clear_bit(MD_RECOVERY_INTR, &mddev->recovery);
                clear_bit(MD_RECOVERY_DONE, &mddev->recovery);
 
-               if (test_bit(MD_RECOVERY_FROZEN, &mddev->recovery))
+               if (!test_and_clear_bit(MD_RECOVERY_NEEDED, &mddev->recovery) ||
+                   test_bit(MD_RECOVERY_FROZEN, &mddev->recovery))
                        goto unlock;
                /* no recovery is running.
                 * remove any failed drives, then
@@ -8140,7 +8140,8 @@ static int md_notify_reboot(struct notifier_block *this,
 
        for_each_mddev(mddev, tmp) {
                if (mddev_trylock(mddev)) {
-                       __md_stop_writes(mddev);
+                       if (mddev->pers)
+                               __md_stop_writes(mddev);
                        mddev->safemode = 2;
                        mddev_unlock(mddev);
                }

diff --git a/drivers/media/video/mx3_camera.c b/drivers/media/video/mx3_camera.c
index 93c35ef..e2e33df 100644 (file)
--- a/drivers/media/video/mx3_camera.c
+++ b/drivers/media/video/mx3_camera.c
@@ -508,7 +508,7 @@ static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam,
        /* ipu_csi_init_interface() */
        csi_reg_write(mx3_cam, conf, CSI_SENS_CONF);
 
-       clk_enable(mx3_cam->clk);
+       clk_prepare_enable(mx3_cam->clk);
        rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk);
        dev_dbg(icd->parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate);
        if (rate)
@@ -549,7 +549,7 @@ static void mx3_camera_remove_device(struct soc_camera_device *icd)
                *ichan = NULL;
        }
 
-       clk_disable(mx3_cam->clk);
+       clk_disable_unprepare(mx3_cam->clk);
 
        mx3_cam->icd = NULL;
 

diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
index c8aae66..7e96bb2 100644 (file)
--- a/drivers/mfd/omap-usb-host.c
+++ b/drivers/mfd/omap-usb-host.c
@@ -25,6 +25,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/spinlock.h>
+#include <plat/cpu.h>
 #include <plat/usb.h>
 #include <linux/pm_runtime.h>
 

diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index b2058b4..28ed52d 100644 (file)
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -136,7 +136,8 @@ struct mxcmci_host {
        u16                     rev_no;
        unsigned int            cmdat;
 
-       struct clk              *clk;
+       struct clk              *clk_ipg;
+       struct clk              *clk_per;
 
        int                     clock;
 
@@ -672,7 +673,7 @@ static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
 {
        unsigned int divider;
        int prescaler = 0;
-       unsigned int clk_in = clk_get_rate(host->clk);
+       unsigned int clk_in = clk_get_rate(host->clk_per);
 
        while (prescaler <= 0x800) {
                for (divider = 1; divider <= 0xF; divider++) {
@@ -900,12 +901,20 @@ static int mxcmci_probe(struct platform_device *pdev)
        host->res = r;
        host->irq = irq;
 
-       host->clk = clk_get(&pdev->dev, NULL);
-       if (IS_ERR(host->clk)) {
-               ret = PTR_ERR(host->clk);
+       host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+       if (IS_ERR(host->clk_ipg)) {
+               ret = PTR_ERR(host->clk_ipg);
                goto out_iounmap;
        }
-       clk_enable(host->clk);
+
+       host->clk_per = devm_clk_get(&pdev->dev, "per");
+       if (IS_ERR(host->clk_per)) {
+               ret = PTR_ERR(host->clk_per);
+               goto out_iounmap;
+       }
+
+       clk_prepare_enable(host->clk_per);
+       clk_prepare_enable(host->clk_ipg);
 
        mxcmci_softreset(host);
 
@@ -917,8 +926,8 @@ static int mxcmci_probe(struct platform_device *pdev)
                goto out_clk_put;
        }
 
-       mmc->f_min = clk_get_rate(host->clk) >> 16;
-       mmc->f_max = clk_get_rate(host->clk) >> 1;
+       mmc->f_min = clk_get_rate(host->clk_per) >> 16;
+       mmc->f_max = clk_get_rate(host->clk_per) >> 1;
 
        /* recommended in data sheet */
        writew(0x2db4, host->base + MMC_REG_READ_TO);
@@ -967,8 +976,8 @@ out_free_dma:
        if (host->dma)
                dma_release_channel(host->dma);
 out_clk_put:
-       clk_disable(host->clk);
-       clk_put(host->clk);
+       clk_disable_unprepare(host->clk_per);
+       clk_disable_unprepare(host->clk_ipg);
 out_iounmap:
        iounmap(host->base);
 out_free:
@@ -999,8 +1008,8 @@ static int mxcmci_remove(struct platform_device *pdev)
        if (host->dma)
                dma_release_channel(host->dma);
 
-       clk_disable(host->clk);
-       clk_put(host->clk);
+       clk_disable_unprepare(host->clk_per);
+       clk_disable_unprepare(host->clk_ipg);
 
        release_mem_region(host->res->start, resource_size(host->res));
 
@@ -1018,7 +1027,8 @@ static int mxcmci_suspend(struct device *dev)
 
        if (mmc)
                ret = mmc_suspend_host(mmc);
-       clk_disable(host->clk);
+       clk_disable_unprepare(host->clk_per);
+       clk_disable_unprepare(host->clk_ipg);
 
        return ret;
 }
@@ -1029,7 +1039,8 @@ static int mxcmci_resume(struct device *dev)
        struct mxcmci_host *host = mmc_priv(mmc);
        int ret = 0;
 
-       clk_enable(host->clk);
+       clk_prepare_enable(host->clk_per);
+       clk_prepare_enable(host->clk_ipg);
        if (mmc)
                ret = mmc_resume_host(mmc);
 

diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index b0f2ef9..bb03ddd 100644 (file)
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -39,6 +39,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/module.h>
 #include <linux/fsl/mxs-dma.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <mach/mxs.h>
 #include <mach/common.h>
@@ -363,6 +364,7 @@ static void mxs_mmc_bc(struct mxs_mmc_host *host)
                goto out;
 
        dmaengine_submit(desc);
+       dma_async_issue_pending(host->dmach);
        return;
 
 out:
@@ -403,6 +405,7 @@ static void mxs_mmc_ac(struct mxs_mmc_host *host)
                goto out;
 
        dmaengine_submit(desc);
+       dma_async_issue_pending(host->dmach);
        return;
 
 out:
@@ -531,6 +534,7 @@ static void mxs_mmc_adtc(struct mxs_mmc_host *host)
                goto out;
 
        dmaengine_submit(desc);
+       dma_async_issue_pending(host->dmach);
        return;
 out:
        dev_warn(mmc_dev(host->mmc),
@@ -679,6 +683,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
        struct mmc_host *mmc;
        struct resource *iores, *dmares, *r;
        struct mxs_mmc_platform_data *pdata;
+       struct pinctrl *pinctrl;
        int ret = 0, irq_err, irq_dma;
        dma_cap_mask_t mask;
 
@@ -716,6 +721,12 @@ static int mxs_mmc_probe(struct platform_device *pdev)
        host->irq = irq_err;
        host->sdio_irq_en = 0;
 
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
+               goto out_iounmap;
+       }
+
        host->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(host->clk)) {
                ret = PTR_ERR(host->clk);

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 8abdaf6..6b0e3f3 100644 (file)
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -24,6 +24,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
 #include <mach/esdhc.h>
 #include "sdhci-pltfm.h"
 #include "sdhci-esdhc.h"
@@ -68,7 +69,11 @@ struct pltfm_imx_data {
        int flags;
        u32 scratchpad;
        enum imx_esdhc_type devtype;
+       struct pinctrl *pinctrl;
        struct esdhc_platform_data boarddata;
+       struct clk *clk_ipg;
+       struct clk *clk_ahb;
+       struct clk *clk_per;
 };
 
 static struct platform_device_id imx_esdhc_devtype[] = {
@@ -437,7 +442,6 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
        struct sdhci_pltfm_host *pltfm_host;
        struct sdhci_host *host;
        struct esdhc_platform_data *boarddata;
-       struct clk *clk;
        int err;
        struct pltfm_imx_data *imx_data;
 
@@ -458,14 +462,35 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
        imx_data->devtype = pdev->id_entry->driver_data;
        pltfm_host->priv = imx_data;
 
-       clk = clk_get(mmc_dev(host->mmc), NULL);
-       if (IS_ERR(clk)) {
-               dev_err(mmc_dev(host->mmc), "clk err\n");
-               err = PTR_ERR(clk);
+       imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+       if (IS_ERR(imx_data->clk_ipg)) {
+               err = PTR_ERR(imx_data->clk_ipg);
                goto err_clk_get;
        }
-       clk_prepare_enable(clk);
-       pltfm_host->clk = clk;
+
+       imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
+       if (IS_ERR(imx_data->clk_ahb)) {
+               err = PTR_ERR(imx_data->clk_ahb);
+               goto err_clk_get;
+       }
+
+       imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
+       if (IS_ERR(imx_data->clk_per)) {
+               err = PTR_ERR(imx_data->clk_per);
+               goto err_clk_get;
+       }
+
+       pltfm_host->clk = imx_data->clk_per;
+
+       clk_prepare_enable(imx_data->clk_per);
+       clk_prepare_enable(imx_data->clk_ipg);
+       clk_prepare_enable(imx_data->clk_ahb);
+
+       imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(imx_data->pinctrl)) {
+               err = PTR_ERR(imx_data->pinctrl);
+               goto pin_err;
+       }
 
        host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 
@@ -558,8 +583,10 @@ no_card_detect_irq:
                gpio_free(boarddata->wp_gpio);
 no_card_detect_pin:
 no_board_data:
-       clk_disable_unprepare(pltfm_host->clk);
-       clk_put(pltfm_host->clk);
+pin_err:
+       clk_disable_unprepare(imx_data->clk_per);
+       clk_disable_unprepare(imx_data->clk_ipg);
+       clk_disable_unprepare(imx_data->clk_ahb);
 err_clk_get:
        kfree(imx_data);
 err_imx_data:
@@ -585,8 +612,10 @@ static int __devexit sdhci_esdhc_imx_remove(struct platform_device *pdev)
                gpio_free(boarddata->cd_gpio);
        }
 
-       clk_disable_unprepare(pltfm_host->clk);
-       clk_put(pltfm_host->clk);
+       clk_disable_unprepare(imx_data->clk_per);
+       clk_disable_unprepare(imx_data->clk_ipg);
+       clk_disable_unprepare(imx_data->clk_ahb);
+
        kfree(imx_data);
 
        sdhci_pltfm_free(pdev);

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 75b1dde..8478fd9 100644 (file)
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -24,6 +24,7 @@
 #include <linux/module.h>
 #include <linux/mtd/gpmi-nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/pinctrl/consumer.h>
 #include "gpmi-nand.h"
 
 /* add our owner bbt descriptor */
@@ -266,6 +267,7 @@ int start_dma_without_bch_irq(struct gpmi_nand_data *this,
        desc->callback          = dma_irq_callback;
        desc->callback_param    = this;
        dmaengine_submit(desc);
+       dma_async_issue_pending(get_dma_chan(this));
 
        /* Wait for the interrupt from the DMA block. */
        err = wait_for_completion_timeout(dma_c, msecs_to_jiffies(1000));
@@ -475,6 +477,7 @@ acquire_err:
 static int __devinit acquire_resources(struct gpmi_nand_data *this)
 {
        struct resources *res = &this->resources;
+       struct pinctrl *pinctrl;
        int ret;
 
        ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME);
@@ -493,6 +496,12 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this)
        if (ret)
                goto exit_dma_channels;
 
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
+               goto exit_pin;
+       }
+
        res->clock = clk_get(&this->pdev->dev, NULL);
        if (IS_ERR(res->clock)) {
                pr_err("can not get the clock\n");
@@ -502,6 +511,7 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this)
        return 0;
 
 exit_clock:
+exit_pin:
        release_dma_channels(this);
 exit_dma_channels:
        release_bch_irq(this);

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index cc0678a..9e374e9 100644 (file)
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -690,7 +690,7 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
        if (chip == -1) {
                /* Disable the NFC clock */
                if (host->clk_act) {
-                       clk_disable(host->clk);
+                       clk_disable_unprepare(host->clk);
                        host->clk_act = 0;
                }
                return;
@@ -698,7 +698,7 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 
        if (!host->clk_act) {
                /* Enable the NFC clock */
-               clk_enable(host->clk);
+               clk_prepare_enable(host->clk);
                host->clk_act = 1;
        }
 
@@ -1078,7 +1078,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
                goto eclk;
        }
 
-       clk_enable(host->clk);
+       clk_prepare_enable(host->clk);
        host->clk_act = 1;
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

diff --git a/drivers/net/arcnet/arc-rimi.c b/drivers/net/arcnet/arc-rimi.c
index 25197b6..b8b4c7b 100644 (file)
--- a/drivers/net/arcnet/arc-rimi.c
+++ b/drivers/net/arcnet/arc-rimi.c
@@ -89,16 +89,16 @@ static int __init arcrimi_probe(struct net_device *dev)
        BUGLVL(D_NORMAL) printk(VERSION);
        BUGLVL(D_NORMAL) printk("E-mail me if you actually test the RIM I driver, please!\n");
 
-       BUGMSG(D_NORMAL, "Given: node %02Xh, shmem %lXh, irq %d\n",
+       BUGLVL(D_NORMAL) printk("Given: node %02Xh, shmem %lXh, irq %d\n",
               dev->dev_addr[0], dev->mem_start, dev->irq);
 
        if (dev->mem_start <= 0 || dev->irq <= 0) {
-               BUGMSG(D_NORMAL, "No autoprobe for RIM I; you "
+               BUGLVL(D_NORMAL) printk("No autoprobe for RIM I; you "
                       "must specify the shmem and irq!\n");
                return -ENODEV;
        }
        if (dev->dev_addr[0] == 0) {
-               BUGMSG(D_NORMAL, "You need to specify your card's station "
+               BUGLVL(D_NORMAL) printk("You need to specify your card's station "
                       "ID!\n");
                return -ENODEV;
        }
@@ -109,7 +109,7 @@ static int __init arcrimi_probe(struct net_device *dev)
         * will be taken.
         */
        if (!request_mem_region(dev->mem_start, MIRROR_SIZE, "arcnet (90xx)")) {
-               BUGMSG(D_NORMAL, "Card memory already allocated\n");
+               BUGLVL(D_NORMAL) printk("Card memory already allocated\n");
                return -ENODEV;
        }
        return arcrimi_found(dev);

diff --git a/drivers/net/caif/caif_hsi.c b/drivers/net/caif/caif_hsi.c
index 9a66e2a..9c1c8cd 100644 (file)
--- a/drivers/net/caif/caif_hsi.c
+++ b/drivers/net/caif/caif_hsi.c
@@ -744,14 +744,14 @@ static void cfhsi_wake_up(struct work_struct *work)
                size_t fifo_occupancy = 0;
 
                /* Wakeup timeout */
-               dev_err(&cfhsi->ndev->dev, "%s: Timeout.\n",
+               dev_dbg(&cfhsi->ndev->dev, "%s: Timeout.\n",
                        __func__);
 
                /* Check FIFO to check if modem has sent something. */
                WARN_ON(cfhsi->dev->cfhsi_fifo_occupancy(cfhsi->dev,
                                        &fifo_occupancy));
 
-               dev_err(&cfhsi->ndev->dev, "%s: Bytes in FIFO: %u.\n",
+               dev_dbg(&cfhsi->ndev->dev, "%s: Bytes in FIFO: %u.\n",
                                __func__, (unsigned) fifo_occupancy);
 
                /* Check if we misssed the interrupt. */
@@ -1210,7 +1210,7 @@ int cfhsi_probe(struct platform_device *pdev)
 
 static void cfhsi_shutdown(struct cfhsi *cfhsi)
 {
-       u8 *tx_buf, *rx_buf;
+       u8 *tx_buf, *rx_buf, *flip_buf;
 
        /* Stop TXing */
        netif_tx_stop_all_queues(cfhsi->ndev);
@@ -1234,7 +1234,7 @@ static void cfhsi_shutdown(struct cfhsi *cfhsi)
        /* Store bufferes: will be freed later. */
        tx_buf = cfhsi->tx_buf;
        rx_buf = cfhsi->rx_buf;
-
+       flip_buf = cfhsi->rx_flip_buf;
        /* Flush transmit queues. */
        cfhsi_abort_tx(cfhsi);
 
@@ -1247,6 +1247,7 @@ static void cfhsi_shutdown(struct cfhsi *cfhsi)
        /* Free buffers. */
        kfree(tx_buf);
        kfree(rx_buf);
+       kfree(flip_buf);
 }
 
 int cfhsi_remove(struct platform_device *pdev)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 1efb083..38c0690 100644 (file)
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -35,6 +35,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
 
 #define DRV_NAME                       "flexcan"
 
@@ -927,11 +928,16 @@ static int __devinit flexcan_probe(struct platform_device *pdev)
        struct flexcan_priv *priv;
        struct resource *mem;
        struct clk *clk = NULL;
+       struct pinctrl *pinctrl;
        void __iomem *base;
        resource_size_t mem_size;
        int err, irq;
        u32 clock_freq = 0;
 
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl))
+               return PTR_ERR(pinctrl);
+
        if (pdev->dev.of_node) {
                const u32 *clock_freq_p;
 

diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_pro.c b/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
index 5234586..629c4ba 100644 (file)
--- a/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
@@ -875,6 +875,7 @@ static int pcan_usb_pro_init(struct peak_usb_device *dev)
                                            PCAN_USBPRO_INFO_FW,
                                            &fi, sizeof(fi));
                if (err) {
+                       kfree(usb_if);
                        dev_err(dev->netdev->dev.parent,
                                "unable to read %s firmware info (err %d)\n",
                                pcan_usb_pro.name, err);
@@ -885,6 +886,7 @@ static int pcan_usb_pro_init(struct peak_usb_device *dev)
                                            PCAN_USBPRO_INFO_BL,
                                            &bi, sizeof(bi));
                if (err) {
+                       kfree(usb_if);
                        dev_err(dev->netdev->dev.parent,
                                "unable to read %s bootloader info (err %d)\n",
                                pcan_usb_pro.name, err);

diff --git a/drivers/net/dummy.c b/drivers/net/dummy.c
index d5c6d92..442d91a 100644 (file)
--- a/drivers/net/dummy.c
+++ b/drivers/net/dummy.c
@@ -107,14 +107,14 @@ static int dummy_dev_init(struct net_device *dev)
        return 0;
 }
 
-static void dummy_dev_free(struct net_device *dev)
+static void dummy_dev_uninit(struct net_device *dev)
 {
        free_percpu(dev->dstats);
-       free_netdev(dev);
 }
 
 static const struct net_device_ops dummy_netdev_ops = {
        .ndo_init               = dummy_dev_init,
+       .ndo_uninit             = dummy_dev_uninit,
        .ndo_start_xmit         = dummy_xmit,
        .ndo_validate_addr      = eth_validate_addr,
        .ndo_set_rx_mode        = set_multicast_list,
@@ -128,7 +128,7 @@ static void dummy_setup(struct net_device *dev)
 
        /* Initialize the device structure. */
        dev->netdev_ops = &dummy_netdev_ops;
-       dev->destructor = dummy_dev_free;
+       dev->destructor = free_netdev;
 
        /* Fill in device structure with ethernet-generic values. */
        dev->tx_queue_len = 0;

diff --git a/drivers/net/ethernet/atheros/atlx/atl1.c b/drivers/net/ethernet/atheros/atlx/atl1.c
index 40ac414..c926857 100644 (file)
--- a/drivers/net/ethernet/atheros/atlx/atl1.c
+++ b/drivers/net/ethernet/atheros/atlx/atl1.c
@@ -2476,7 +2476,7 @@ static irqreturn_t atl1_intr(int irq, void *data)
                                        "pcie phy link down %x\n", status);
                        if (netif_running(adapter->netdev)) {   /* reset MAC */
                                iowrite32(0, adapter->hw.hw_addr + REG_IMR);
-                               schedule_work(&adapter->pcie_dma_to_rst_task);
+                               schedule_work(&adapter->reset_dev_task);
                                return IRQ_HANDLED;
                        }
                }
@@ -2488,7 +2488,7 @@ static irqreturn_t atl1_intr(int irq, void *data)
                                        "pcie DMA r/w error (status = 0x%x)\n",
                                        status);
                        iowrite32(0, adapter->hw.hw_addr + REG_IMR);
-                       schedule_work(&adapter->pcie_dma_to_rst_task);
+                       schedule_work(&adapter->reset_dev_task);
                        return IRQ_HANDLED;
                }
 
@@ -2633,10 +2633,10 @@ static void atl1_down(struct atl1_adapter *adapter)
        atl1_clean_rx_ring(adapter);
 }
 
-static void atl1_tx_timeout_task(struct work_struct *work)
+static void atl1_reset_dev_task(struct work_struct *work)
 {
        struct atl1_adapter *adapter =
-               container_of(work, struct atl1_adapter, tx_timeout_task);
+               container_of(work, struct atl1_adapter, reset_dev_task);
        struct net_device *netdev = adapter->netdev;
 
        netif_device_detach(netdev);
@@ -3038,12 +3038,10 @@ static int __devinit atl1_probe(struct pci_dev *pdev,
                    (unsigned long)adapter);
        adapter->phy_timer_pending = false;
 
-       INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
+       INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task);
 
        INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
 
-       INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
-
        err = register_netdev(netdev);
        if (err)
                goto err_common;

diff --git a/drivers/net/ethernet/atheros/atlx/atl1.h b/drivers/net/ethernet/atheros/atlx/atl1.h
index 109d6da..e04bf4d 100644 (file)
--- a/drivers/net/ethernet/atheros/atlx/atl1.h
+++ b/drivers/net/ethernet/atheros/atlx/atl1.h
@@ -758,9 +758,8 @@ struct atl1_adapter {
        u16 link_speed;
        u16 link_duplex;
        spinlock_t lock;
-       struct work_struct tx_timeout_task;
+       struct work_struct reset_dev_task;
        struct work_struct link_chg_task;
-       struct work_struct pcie_dma_to_rst_task;
 
        struct timer_list phy_config_timer;
        bool phy_timer_pending;

diff --git a/drivers/net/ethernet/atheros/atlx/atlx.c b/drivers/net/ethernet/atheros/atlx/atlx.c
index 3cd8837..c9e9dc5 100644 (file)
--- a/drivers/net/ethernet/atheros/atlx/atlx.c
+++ b/drivers/net/ethernet/atheros/atlx/atlx.c
@@ -194,7 +194,7 @@ static void atlx_tx_timeout(struct net_device *netdev)
 {
        struct atlx_adapter *adapter = netdev_priv(netdev);
        /* Do the reset outside of interrupt context */
-       schedule_work(&adapter->tx_timeout_task);
+       schedule_work(&adapter->reset_dev_task);
 }
 
 /*

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index ad95324..64392ec 100644 (file)
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -942,6 +942,12 @@ static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
        const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
                DCBX_E3B0_MAX_NUM_COS_PORT0;
 
+       if (pri >= max_num_of_cos) {
+               DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
+                  "parameter Illegal strict priority\n");
+           return -EINVAL;
+       }
+
        if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
                DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
                                   "parameter There can't be two COS's with "
@@ -949,12 +955,6 @@ static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
                return -EINVAL;
        }
 
-       if (pri > max_num_of_cos) {
-               DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
-                  "parameter Illegal strict priority\n");
-           return -EINVAL;
-       }
-
        sp_pri_to_cos[pri] = cos_entry;
        return 0;
 

diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 062ac33..ceeab8e 100644 (file)
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -879,8 +879,13 @@ static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
                if (sblk->status & SD_STATUS_LINK_CHG)
                        work_exists = 1;
        }
-       /* check for RX/TX work to do */
-       if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
+
+       /* check for TX work to do */
+       if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
+               work_exists = 1;
+
+       /* check for RX work to do */
+       if (tnapi->rx_rcb_prod_idx &&
            *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
                work_exists = 1;
 
@@ -6124,6 +6129,9 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
                        return work_done;
        }
 
+       if (!tnapi->rx_rcb_prod_idx)
+               return work_done;
+
        /* run RX thread, within the bounds set by NAPI.
         * All RX "locking" is done by ensuring outside
         * code synchronizes with tg3->napi.poll()
@@ -7567,6 +7575,12 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                 */
                switch (i) {
                default:
+                       if (tg3_flag(tp, ENABLE_RSS)) {
+                               tnapi->rx_rcb_prod_idx = NULL;
+                               break;
+                       }
+                       /* Fall through */
+               case 1:
                        tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
                        break;
                case 2:

diff --git a/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c b/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
index 63bfdd1..abb6ce7 100644 (file)
--- a/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
@@ -1150,6 +1150,48 @@ release_tpsram:
 }
 
 /**
+ * t3_synchronize_rx - wait for current Rx processing on a port to complete
+ * @adap: the adapter
+ * @p: the port
+ *
+ * Ensures that current Rx processing on any of the queues associated with
+ * the given port completes before returning.  We do this by acquiring and
+ * releasing the locks of the response queues associated with the port.
+ */
+static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
+{
+       int i;
+
+       for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
+               struct sge_rspq *q = &adap->sge.qs[i].rspq;
+
+               spin_lock_irq(&q->lock);
+               spin_unlock_irq(&q->lock);
+       }
+}
+
+static void cxgb_vlan_mode(struct net_device *dev, netdev_features_t features)
+{
+       struct port_info *pi = netdev_priv(dev);
+       struct adapter *adapter = pi->adapter;
+
+       if (adapter->params.rev > 0) {
+               t3_set_vlan_accel(adapter, 1 << pi->port_id,
+                                 features & NETIF_F_HW_VLAN_RX);
+       } else {
+               /* single control for all ports */
+               unsigned int i, have_vlans = features & NETIF_F_HW_VLAN_RX;
+
+               for_each_port(adapter, i)
+                       have_vlans |=
+                               adapter->port[i]->features & NETIF_F_HW_VLAN_RX;
+
+               t3_set_vlan_accel(adapter, 1, have_vlans);
+       }
+       t3_synchronize_rx(adapter, pi);
+}
+
+/**
  *     cxgb_up - enable the adapter
  *     @adapter: adapter being enabled
  *
@@ -1161,7 +1203,7 @@ release_tpsram:
  */
 static int cxgb_up(struct adapter *adap)
 {
-       int err;
+       int i, err;
 
        if (!(adap->flags & FULL_INIT_DONE)) {
                err = t3_check_fw_version(adap);
@@ -1198,6 +1240,9 @@ static int cxgb_up(struct adapter *adap)
                if (err)
                        goto out;
 
+               for_each_port(adap, i)
+                       cxgb_vlan_mode(adap->port[i], adap->port[i]->features);
+
                setup_rss(adap);
                if (!(adap->flags & NAPI_INIT))
                        init_napi(adap);
@@ -2508,48 +2553,6 @@ static int cxgb_set_mac_addr(struct net_device *dev, void *p)
        return 0;
 }
 
-/**
- * t3_synchronize_rx - wait for current Rx processing on a port to complete
- * @adap: the adapter
- * @p: the port
- *
- * Ensures that current Rx processing on any of the queues associated with
- * the given port completes before returning.  We do this by acquiring and
- * releasing the locks of the response queues associated with the port.
- */
-static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
-{
-       int i;
-
-       for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
-               struct sge_rspq *q = &adap->sge.qs[i].rspq;
-
-               spin_lock_irq(&q->lock);
-               spin_unlock_irq(&q->lock);
-       }
-}
-
-static void cxgb_vlan_mode(struct net_device *dev, netdev_features_t features)
-{
-       struct port_info *pi = netdev_priv(dev);
-       struct adapter *adapter = pi->adapter;
-
-       if (adapter->params.rev > 0) {
-               t3_set_vlan_accel(adapter, 1 << pi->port_id,
-                                 features & NETIF_F_HW_VLAN_RX);
-       } else {
-               /* single control for all ports */
-               unsigned int i, have_vlans = features & NETIF_F_HW_VLAN_RX;
-
-               for_each_port(adapter, i)
-                       have_vlans |=
-                               adapter->port[i]->features & NETIF_F_HW_VLAN_RX;
-
-               t3_set_vlan_accel(adapter, 1, have_vlans);
-       }
-       t3_synchronize_rx(adapter, pi);
-}
-
 static netdev_features_t cxgb_fix_features(struct net_device *dev,
        netdev_features_t features)
 {
@@ -3353,9 +3356,6 @@ static int __devinit init_one(struct pci_dev *pdev,
        err = sysfs_create_group(&adapter->port[0]->dev.kobj,
                                 &cxgb3_attr_group);
 
-       for_each_port(adapter, i)
-               cxgb_vlan_mode(adapter->port[i], adapter->port[i]->features);
-
        print_port_info(adapter, ai);
        return 0;
 

diff --git a/drivers/net/ethernet/dlink/dl2k.c b/drivers/net/ethernet/dlink/dl2k.c
index b2dc2c8..2e09edb 100644 (file)
--- a/drivers/net/ethernet/dlink/dl2k.c
+++ b/drivers/net/ethernet/dlink/dl2k.c
@@ -1259,55 +1259,21 @@ rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
 {
        int phy_addr;
        struct netdev_private *np = netdev_priv(dev);
-       struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
-
-       struct netdev_desc *desc;
-       int i;
+       struct mii_ioctl_data *miidata = if_mii(rq);
 
        phy_addr = np->phy_addr;
        switch (cmd) {
-       case SIOCDEVPRIVATE:
-               break;
-
-       case SIOCDEVPRIVATE + 1:
-               miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
+       case SIOCGMIIPHY:
+               miidata->phy_id = phy_addr;
                break;
-       case SIOCDEVPRIVATE + 2:
-               mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
+       case SIOCGMIIREG:
+               miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
                break;
-       case SIOCDEVPRIVATE + 3:
-               break;
-       case SIOCDEVPRIVATE + 4:
-               break;
-       case SIOCDEVPRIVATE + 5:
-               netif_stop_queue (dev);
+       case SIOCSMIIREG:
+               if (!capable(CAP_NET_ADMIN))
+                       return -EPERM;
+               mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
                break;
-       case SIOCDEVPRIVATE + 6:
-               netif_wake_queue (dev);
-               break;
-       case SIOCDEVPRIVATE + 7:
-               printk
-                   ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
-                    netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
-                    np->old_rx);
-               break;
-       case SIOCDEVPRIVATE + 8:
-               printk("TX ring:\n");
-               for (i = 0; i < TX_RING_SIZE; i++) {
-                       desc = &np->tx_ring[i];
-                       printk
-                           ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
-                            i,
-                            (u32) (np->tx_ring_dma + i * sizeof (*desc)),
-                            (u32)le64_to_cpu(desc->next_desc),
-                            (u32)le64_to_cpu(desc->status),
-                            (u32)(le64_to_cpu(desc->fraginfo) >> 32),
-                            (u32)le64_to_cpu(desc->fraginfo));
-                       printk ("\n");
-               }
-               printk ("\n");
-               break;
-
        default:
                return -EOPNOTSUPP;
        }

diff --git a/drivers/net/ethernet/dlink/dl2k.h b/drivers/net/ethernet/dlink/dl2k.h
index ba0adca..30c2da3 100644 (file)
--- a/drivers/net/ethernet/dlink/dl2k.h
+++ b/drivers/net/ethernet/dlink/dl2k.h
@@ -365,13 +365,6 @@ struct ioctl_data {
        char *data;
 };
 
-struct mii_data {
-       __u16 reserved;
-       __u16 reg_num;
-       __u16 in_value;
-       __u16 out_value;
-};
-
 /* The Rx and Tx buffer descriptors. */
 struct netdev_desc {
        __le64 next_desc;

diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c
index a12b3f5..4d3280a 100644 (file)
--- a/drivers/net/ethernet/freescale/fec.c
+++ b/drivers/net/ethernet/freescale/fec.c
@@ -48,6 +48,7 @@
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
 #include <linux/of_net.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <asm/cacheflush.h>
 
@@ -206,7 +207,8 @@ struct fec_enet_private {
 
        struct net_device *netdev;
 
-       struct clk *clk;
+       struct clk *clk_ipg;
+       struct clk *clk_ahb;
 
        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
        unsigned char *tx_bounce[TX_RING_SIZE];
@@ -1064,7 +1066,7 @@ static int fec_enet_mii_init(struct platform_device *pdev)
         * Reference Manual has an error on this, and gets fixed on i.MX6Q
         * document.
         */
-       fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000);
+       fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
        if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
                fep->phy_speed--;
        fep->phy_speed <<= 1;
@@ -1542,6 +1544,7 @@ fec_probe(struct platform_device *pdev)
        struct resource *r;
        const struct of_device_id *of_id;
        static int dev_id;
+       struct pinctrl *pinctrl;
 
        of_id = of_match_device(fec_dt_ids, &pdev->dev);
        if (of_id)
@@ -1609,12 +1612,26 @@ fec_probe(struct platform_device *pdev)
                }
        }
 
-       fep->clk = clk_get(&pdev->dev, NULL);
-       if (IS_ERR(fep->clk)) {
-               ret = PTR_ERR(fep->clk);
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
+               goto failed_pin;
+       }
+
+       fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+       if (IS_ERR(fep->clk_ipg)) {
+               ret = PTR_ERR(fep->clk_ipg);
+               goto failed_clk;
+       }
+
+       fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
+       if (IS_ERR(fep->clk_ahb)) {
+               ret = PTR_ERR(fep->clk_ahb);
                goto failed_clk;
        }
-       clk_prepare_enable(fep->clk);
+
+       clk_prepare_enable(fep->clk_ahb);
+       clk_prepare_enable(fep->clk_ipg);
 
        ret = fec_enet_init(ndev);
        if (ret)
@@ -1637,8 +1654,9 @@ failed_register:
        fec_enet_mii_remove(fep);
 failed_mii_init:
 failed_init:
-       clk_disable_unprepare(fep->clk);
-       clk_put(fep->clk);
+       clk_disable_unprepare(fep->clk_ahb);
+       clk_disable_unprepare(fep->clk_ipg);
+failed_pin:
 failed_clk:
        for (i = 0; i < FEC_IRQ_NUM; i++) {
                irq = platform_get_irq(pdev, i);
@@ -1670,8 +1688,8 @@ fec_drv_remove(struct platform_device *pdev)
                if (irq > 0)
                        free_irq(irq, ndev);
        }
-       clk_disable_unprepare(fep->clk);
-       clk_put(fep->clk);
+       clk_disable_unprepare(fep->clk_ahb);
+       clk_disable_unprepare(fep->clk_ipg);
        iounmap(fep->hwp);
        free_netdev(ndev);
 
@@ -1695,7 +1713,8 @@ fec_suspend(struct device *dev)
                fec_stop(ndev);
                netif_device_detach(ndev);
        }
-       clk_disable_unprepare(fep->clk);
+       clk_disable_unprepare(fep->clk_ahb);
+       clk_disable_unprepare(fep->clk_ipg);
 
        return 0;
 }
@@ -1706,7 +1725,8 @@ fec_resume(struct device *dev)
        struct net_device *ndev = dev_get_drvdata(dev);
        struct fec_enet_private *fep = netdev_priv(ndev);
 
-       clk_prepare_enable(fep->clk);
+       clk_prepare_enable(fep->clk_ahb);
+       clk_prepare_enable(fep->clk_ipg);
        if (netif_running(ndev)) {
                fec_restart(ndev, fep->full_duplex);
                netif_device_attach(ndev);

diff --git a/drivers/net/ethernet/freescale/ucc_geth.c b/drivers/net/ethernet/freescale/ucc_geth.c
index 17a46e7..9ac14f8 100644 (file)
--- a/drivers/net/ethernet/freescale/ucc_geth.c
+++ b/drivers/net/ethernet/freescale/ucc_geth.c
@@ -116,10 +116,10 @@ static struct ucc_geth_info ugeth_primary_info = {
        .maxGroupAddrInHash = 4,
        .maxIndAddrInHash = 4,
        .prel = 7,
-       .maxFrameLength = 1518,
+       .maxFrameLength = 1518+16, /* Add extra bytes for VLANs etc. */
        .minFrameLength = 64,
-       .maxD1Length = 1520,
-       .maxD2Length = 1520,
+       .maxD1Length = 1520+16, /* Add extra bytes for VLANs etc. */
+       .maxD2Length = 1520+16, /* Add extra bytes for VLANs etc. */
        .vlantype = 0x8100,
        .ecamptr = ((uint32_t) NULL),
        .eventRegMask = UCCE_OTHER,

diff --git a/drivers/net/ethernet/freescale/ucc_geth.h b/drivers/net/ethernet/freescale/ucc_geth.h
index 2e395a2..f71b3e7 100644 (file)
--- a/drivers/net/ethernet/freescale/ucc_geth.h
+++ b/drivers/net/ethernet/freescale/ucc_geth.h
@@ -877,7 +877,7 @@ struct ucc_geth_hardware_statistics {
 
 /* Driver definitions */
 #define TX_BD_RING_LEN                          0x10
-#define RX_BD_RING_LEN                          0x10
+#define RX_BD_RING_LEN                          0x20
 
 #define TX_RING_MOD_MASK(size)                  (size-1)
 #define RX_RING_MOD_MASK(size)                  (size-1)

diff --git a/drivers/net/ethernet/ibm/ehea/ehea_main.c b/drivers/net/ethernet/ibm/ehea/ehea_main.c
index 3516e17..c9069a2 100644 (file)
--- a/drivers/net/ethernet/ibm/ehea/ehea_main.c
+++ b/drivers/net/ethernet/ibm/ehea/ehea_main.c
@@ -290,16 +290,18 @@ static void ehea_update_bcmc_registrations(void)
 
                                arr[i].adh = adapter->handle;
                                arr[i].port_id = port->logical_port_id;
-                               arr[i].reg_type = EHEA_BCMC_SCOPE_ALL |
-                                                 EHEA_BCMC_MULTICAST |
+                               arr[i].reg_type = EHEA_BCMC_MULTICAST |
                                                  EHEA_BCMC_UNTAGGED;
+                               if (mc_entry->macaddr == 0)
+                                       arr[i].reg_type |= EHEA_BCMC_SCOPE_ALL;
                                arr[i++].macaddr = mc_entry->macaddr;
 
                                arr[i].adh = adapter->handle;
                                arr[i].port_id = port->logical_port_id;
-                               arr[i].reg_type = EHEA_BCMC_SCOPE_ALL |
-                                                 EHEA_BCMC_MULTICAST |
+                               arr[i].reg_type = EHEA_BCMC_MULTICAST |
                                                  EHEA_BCMC_VLANID_ALL;
+                               if (mc_entry->macaddr == 0)
+                                       arr[i].reg_type |= EHEA_BCMC_SCOPE_ALL;
                                arr[i++].macaddr = mc_entry->macaddr;
                                num_registrations -= 2;
                        }
@@ -1838,8 +1840,9 @@ static u64 ehea_multicast_reg_helper(struct ehea_port *port, u64 mc_mac_addr,
        u64 hret;
        u8 reg_type;
 
-       reg_type = EHEA_BCMC_SCOPE_ALL | EHEA_BCMC_MULTICAST
-                | EHEA_BCMC_UNTAGGED;
+       reg_type = EHEA_BCMC_MULTICAST | EHEA_BCMC_UNTAGGED;
+       if (mc_mac_addr == 0)
+               reg_type |= EHEA_BCMC_SCOPE_ALL;
 
        hret = ehea_h_reg_dereg_bcmc(port->adapter->handle,
                                     port->logical_port_id,
@@ -1847,8 +1850,9 @@ static u64 ehea_multicast_reg_helper(struct ehea_port *port, u64 mc_mac_addr,
        if (hret)
                goto out;
 
-       reg_type = EHEA_BCMC_SCOPE_ALL | EHEA_BCMC_MULTICAST
-                | EHEA_BCMC_VLANID_ALL;
+       reg_type = EHEA_BCMC_MULTICAST | EHEA_BCMC_VLANID_ALL;
+       if (mc_mac_addr == 0)
+               reg_type |= EHEA_BCMC_SCOPE_ALL;
 
        hret = ehea_h_reg_dereg_bcmc(port->adapter->handle,
                                     port->logical_port_id,
@@ -1898,7 +1902,7 @@ static void ehea_allmulti(struct net_device *dev, int enable)
                                netdev_err(dev,
                                           "failed enabling IFF_ALLMULTI\n");
                }
-       } else
+       } else {
                if (!enable) {
                        /* Disable ALLMULTI */
                        hret = ehea_multicast_reg_helper(port, 0, H_DEREG_BCMC);
@@ -1908,6 +1912,7 @@ static void ehea_allmulti(struct net_device *dev, int enable)
                                netdev_err(dev,
                                           "failed disabling IFF_ALLMULTI\n");
                }
+       }
 }
 
 static void ehea_add_multicast_entry(struct ehea_port *port, u8 *mc_mac_addr)
@@ -1941,11 +1946,7 @@ static void ehea_set_multicast_list(struct net_device *dev)
        struct netdev_hw_addr *ha;
        int ret;
 
-       if (port->promisc) {
-               ehea_promiscuous(dev, 1);
-               return;
-       }
-       ehea_promiscuous(dev, 0);
+       ehea_promiscuous(dev, !!(dev->flags & IFF_PROMISC));
 
        if (dev->flags & IFF_ALLMULTI) {
                ehea_allmulti(dev, 1);
@@ -2463,6 +2464,7 @@ static int ehea_down(struct net_device *dev)
                return 0;
 
        ehea_drop_multicast_list(dev);
+       ehea_allmulti(dev, 0);
        ehea_broadcast_reg_helper(port, H_DEREG_BCMC);
 
        ehea_free_interrupts(dev);
@@ -3261,6 +3263,7 @@ static int __devinit ehea_probe_adapter(struct platform_device *dev,
        struct ehea_adapter *adapter;
        const u64 *adapter_handle;
        int ret;
+       int i;
 
        if (!dev || !dev->dev.of_node) {
                pr_err("Invalid ibmebus device probed\n");
@@ -3314,17 +3317,9 @@ static int __devinit ehea_probe_adapter(struct platform_device *dev,
        tasklet_init(&adapter->neq_tasklet, ehea_neq_tasklet,
                     (unsigned long)adapter);
 
-       ret = ibmebus_request_irq(adapter->neq->attr.ist1,
-                                 ehea_interrupt_neq, IRQF_DISABLED,
-                                 "ehea_neq", adapter);
-       if (ret) {
-               dev_err(&dev->dev, "requesting NEQ IRQ failed\n");
-               goto out_kill_eq;
-       }
-
        ret = ehea_create_device_sysfs(dev);
        if (ret)
-               goto out_free_irq;
+               goto out_kill_eq;
 
        ret = ehea_setup_ports(adapter);
        if (ret) {
@@ -3332,15 +3327,28 @@ static int __devinit ehea_probe_adapter(struct platform_device *dev,
                goto out_rem_dev_sysfs;
        }
 
+       ret = ibmebus_request_irq(adapter->neq->attr.ist1,
+                                 ehea_interrupt_neq, IRQF_DISABLED,
+                                 "ehea_neq", adapter);
+       if (ret) {
+               dev_err(&dev->dev, "requesting NEQ IRQ failed\n");
+               goto out_shutdown_ports;
+       }
+
+
        ret = 0;
        goto out;
 
+out_shutdown_ports:
+       for (i = 0; i < EHEA_MAX_PORTS; i++)
+               if (adapter->port[i]) {
+                       ehea_shutdown_single_port(adapter->port[i]);
+                       adapter->port[i] = NULL;
+               }
+
 out_rem_dev_sysfs:
        ehea_remove_device_sysfs(dev);
 
-out_free_irq:
-       ibmebus_free_irq(adapter->neq->attr.ist1, adapter);
-
 out_kill_eq:
        ehea_destroy_eq(adapter->neq);
 

diff --git a/drivers/net/ethernet/ibm/ehea/ehea_phyp.h b/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
index 52c456e..8364815 100644 (file)
--- a/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
+++ b/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
@@ -450,7 +450,7 @@ u64 ehea_h_modify_ehea_port(const u64 adapter_handle, const u16 port_num,
                            void *cb_addr);
 
 #define H_REGBCMC_PN            EHEA_BMASK_IBM(48, 63)
-#define H_REGBCMC_REGTYPE       EHEA_BMASK_IBM(61, 63)
+#define H_REGBCMC_REGTYPE       EHEA_BMASK_IBM(60, 63)
 #define H_REGBCMC_MACADDR       EHEA_BMASK_IBM(16, 63)
 #define H_REGBCMC_VLANID        EHEA_BMASK_IBM(52, 63)
 

diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index 64c7644..b461c24 100644 (file)
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -1310,10 +1310,6 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
 
                if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
                        oem_reg |= HV_OEM_BITS_LPLU;
-
-               /* Set Restart auto-neg to activate the bits */
-               if (!hw->phy.ops.check_reset_block(hw))
-                       oem_reg |= HV_OEM_BITS_RESTART_AN;
        } else {
                if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
                               E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
@@ -1324,6 +1320,11 @@ static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
                        oem_reg |= HV_OEM_BITS_LPLU;
        }
 
+       /* Set Restart auto-neg to activate the bits */
+       if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
+           !hw->phy.ops.check_reset_block(hw))
+               oem_reg |= HV_OEM_BITS_RESTART_AN;
+
        ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
 
 release:
@@ -3682,7 +3683,11 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
 
        if (hw->mac.type >= e1000_pchlan) {
                e1000_oem_bits_config_ich8lan(hw, false);
-               e1000_phy_hw_reset_ich8lan(hw);
+
+               /* Reset PHY to activate OEM bits on 82577/8 */
+               if (hw->mac.type == e1000_pchlan)
+                       e1000e_phy_hw_reset_generic(hw);
+
                ret_val = hw->phy.ops.acquire(hw);
                if (ret_val)
                        return;

diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 19ab215..9520a6a 100644 (file)
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -3799,7 +3799,7 @@ static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
        /* fire an unusual interrupt on the test handler */
        ew32(ICS, E1000_ICS_RXSEQ);
        e1e_flush();
-       msleep(50);
+       msleep(100);
 
        e1000_irq_disable(adapter);
 

diff --git a/drivers/net/ethernet/intel/e1000e/param.c b/drivers/net/ethernet/intel/e1000e/param.c
index ff796e4..16adeb9 100644 (file)
--- a/drivers/net/ethernet/intel/e1000e/param.c
+++ b/drivers/net/ethernet/intel/e1000e/param.c
@@ -106,7 +106,7 @@ E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
 /*
  * Interrupt Throttle Rate (interrupts/sec)
  *
- * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
+ * Valid Range: 100-100000 or one of: 0=off, 1=dynamic, 3=dynamic conservative
  */
 E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
 #define DEFAULT_ITR 3
@@ -344,53 +344,60 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
 
                if (num_InterruptThrottleRate > bd) {
                        adapter->itr = InterruptThrottleRate[bd];
-                       switch (adapter->itr) {
-                       case 0:
-                               e_info("%s turned off\n", opt.name);
-                               break;
-                       case 1:
-                               e_info("%s set to dynamic mode\n", opt.name);
-                               adapter->itr_setting = adapter->itr;
-                               adapter->itr = 20000;
-                               break;
-                       case 3:
-                               e_info("%s set to dynamic conservative mode\n",
-                                       opt.name);
-                               adapter->itr_setting = adapter->itr;
-                               adapter->itr = 20000;
-                               break;
-                       case 4:
-                               e_info("%s set to simplified (2000-8000 ints) "
-                                      "mode\n", opt.name);
-                               adapter->itr_setting = 4;
-                               break;
-                       default:
-                               /*
-                                * Save the setting, because the dynamic bits
-                                * change itr.
-                                */
-                               if (e1000_validate_option(&adapter->itr, &opt,
-                                                         adapter) &&
-                                   (adapter->itr == 3)) {
-                                       /*
-                                        * In case of invalid user value,
-                                        * default to conservative mode.
-                                        */
-                                       adapter->itr_setting = adapter->itr;
-                                       adapter->itr = 20000;
-                               } else {
-                                       /*
-                                        * Clear the lower two bits because
-                                        * they are used as control.
-                                        */
-                                       adapter->itr_setting =
-                                               adapter->itr & ~3;
-                               }
-                               break;
-                       }
+
+                       /*
+                        * Make sure a message is printed for non-special
+                        * values.  And in case of an invalid option, display
+                        * warning, use default and got through itr/itr_setting
+                        * adjustment logic below
+                        */
+                       if ((adapter->itr > 4) &&
+                           e1000_validate_option(&adapter->itr, &opt, adapter))
+                               adapter->itr = opt.def;
                } else {
-                       adapter->itr_setting = opt.def;
+                       /*
+                        * If no option specified, use default value and go
+                        * through the logic below to adjust itr/itr_setting
+                        */
+                       adapter->itr = opt.def;
+
+                       /*
+                        * Make sure a message is printed for non-special
+                        * default values
+                        */
+                       if (adapter->itr > 40)
+                               e_info("%s set to default %d\n", opt.name,
+                                      adapter->itr);
+               }
+
+               adapter->itr_setting = adapter->itr;
+               switch (adapter->itr) {
+               case 0:
+                       e_info("%s turned off\n", opt.name);
+                       break;
+               case 1:
+                       e_info("%s set to dynamic mode\n", opt.name);
+                       adapter->itr = 20000;
+                       break;
+               case 3:
+                       e_info("%s set to dynamic conservative mode\n",
+                              opt.name);
                        adapter->itr = 20000;
+                       break;
+               case 4:
+                       e_info("%s set to simplified (2000-8000 ints) mode\n",
+                              opt.name);
+                       break;
+               default:
+                       /*
+                        * Save the setting, because the dynamic bits
+                        * change itr.
+                        *
+                        * Clear the lower two bits because
+                        * they are used as control.
+                        */
+                       adapter->itr_setting &= ~3;
+                       break;
                }
        }
        { /* Interrupt Mode */

diff --git a/drivers/net/ethernet/intel/igbvf/netdev.c b/drivers/net/ethernet/intel/igbvf/netdev.c
index d61ca2a..8ec74b0 100644 (file)
--- a/drivers/net/ethernet/intel/igbvf/netdev.c
+++ b/drivers/net/ethernet/intel/igbvf/netdev.c
@@ -2731,14 +2731,14 @@ static int __devinit igbvf_probe(struct pci_dev *pdev,
                        netdev->addr_len);
        }
 
-       if (!is_valid_ether_addr(netdev->perm_addr)) {
+       if (!is_valid_ether_addr(netdev->dev_addr)) {
                dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
                        netdev->dev_addr);
                err = -EIO;
                goto err_hw_init;
        }
 
-       memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
+       memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
 
        setup_timer(&adapter->watchdog_timer, &igbvf_watchdog,
                    (unsigned long) adapter);

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c
index 77ea4b7..bc07933 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c
@@ -437,6 +437,7 @@ int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
         */
        if ((fh->fh_r_ctl == FC_RCTL_DD_SOL_DATA) &&
            (fctl & FC_FC_END_SEQ)) {
+               skb_linearize(skb);
                crc = (struct fcoe_crc_eof *)skb_put(skb, sizeof(*crc));
                crc->fcoe_eof = FC_EOF_T;
        }

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
index 027d7a7..ed1b47d 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
@@ -622,6 +622,16 @@ static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, int v_idx,
                if (adapter->hw.mac.type == ixgbe_mac_82599EB)
                        set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
 
+#ifdef IXGBE_FCOE
+               if (adapter->netdev->features & NETIF_F_FCOE_MTU) {
+                       struct ixgbe_ring_feature *f;
+                       f = &adapter->ring_feature[RING_F_FCOE];
+                       if ((rxr_idx >= f->mask) &&
+                           (rxr_idx < f->mask + f->indices))
+                               set_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state);
+               }
+
+#endif /* IXGBE_FCOE */
                /* apply Rx specific ring traits */
                ring->count = adapter->rx_ring_count;
                ring->queue_index = rxr_idx;

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 3e26b1f..88f6b2e 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -3154,14 +3154,6 @@ static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
                        set_ring_rsc_enabled(rx_ring);
                else
                        clear_ring_rsc_enabled(rx_ring);
-#ifdef IXGBE_FCOE
-               if (netdev->features & NETIF_F_FCOE_MTU) {
-                       struct ixgbe_ring_feature *f;
-                       f = &adapter->ring_feature[RING_F_FCOE];
-                       if ((i >= f->mask) && (i < f->mask + f->indices))
-                               set_bit(__IXGBE_RX_FCOE_BUFSZ, &rx_ring->state);
-               }
-#endif /* IXGBE_FCOE */
        }
 }
 
@@ -4836,7 +4828,9 @@ static int ixgbe_resume(struct pci_dev *pdev)
 
        pci_wake_from_d3(pdev, false);
 
+       rtnl_lock();
        err = ixgbe_init_interrupt_scheme(adapter);
+       rtnl_unlock();
        if (err) {
                e_dev_err("Cannot initialize interrupts for device\n");
                return err;
@@ -4879,10 +4873,6 @@ static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
        }
 
        ixgbe_clear_interrupt_scheme(adapter);
-#ifdef CONFIG_DCB
-       kfree(adapter->ixgbe_ieee_pfc);
-       kfree(adapter->ixgbe_ieee_ets);
-#endif
 
 #ifdef CONFIG_PM
        retval = pci_save_state(pdev);
@@ -4893,6 +4883,16 @@ static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
        if (wufc) {
                ixgbe_set_rx_mode(netdev);
 
+               /*
+                * enable the optics for both mult-speed fiber and
+                * 82599 SFP+ fiber as we can WoL.
+                */
+               if (hw->mac.ops.enable_tx_laser &&
+                   (hw->phy.multispeed_fiber ||
+                   (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
+                    hw->mac.type == ixgbe_mac_82599EB)))
+                       hw->mac.ops.enable_tx_laser(hw);
+
                /* turn on all-multi mode if wake on multicast is enabled */
                if (wufc & IXGBE_WUFC_MC) {
                        fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
@@ -7220,6 +7220,11 @@ static void __devexit ixgbe_remove(struct pci_dev *pdev)
 
        ixgbe_release_hw_control(adapter);
 
+#ifdef CONFIG_DCB
+       kfree(adapter->ixgbe_ieee_pfc);
+       kfree(adapter->ixgbe_ieee_ets);
+
+#endif
        iounmap(adapter->hw.hw_addr);
        pci_release_selected_regions(pdev, pci_select_bars(pdev,
                                     IORESOURCE_MEM));

diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index c9b504e..487a6c8 100644 (file)
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -2494,8 +2494,13 @@ static struct sk_buff *receive_copy(struct sky2_port *sky2,
                skb_copy_from_linear_data(re->skb, skb->data, length);
                skb->ip_summed = re->skb->ip_summed;
                skb->csum = re->skb->csum;
+               skb->rxhash = re->skb->rxhash;
+               skb->vlan_tci = re->skb->vlan_tci;
+
                pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
                                               length, PCI_DMA_FROMDEVICE);
+               re->skb->vlan_tci = 0;
+               re->skb->rxhash = 0;
                re->skb->ip_summed = CHECKSUM_NONE;
                skb_put(skb, length);
        }
@@ -2580,9 +2585,6 @@ static struct sk_buff *sky2_receive(struct net_device *dev,
        struct sk_buff *skb = NULL;
        u16 count = (status & GMR_FS_LEN) >> 16;
 
-       if (status & GMR_FS_VLAN)
-               count -= VLAN_HLEN;     /* Account for vlan tag */
-
        netif_printk(sky2, rx_status, KERN_DEBUG, dev,
                     "rx slot %u status 0x%x len %d\n",
                     sky2->rx_next, status, length);
@@ -2590,6 +2592,9 @@ static struct sk_buff *sky2_receive(struct net_device *dev,
        sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
        prefetch(sky2->rx_ring + sky2->rx_next);
 
+       if (vlan_tx_tag_present(re->skb))
+               count -= VLAN_HLEN;     /* Account for vlan tag */
+
        /* This chip has hardware problems that generates bogus status.
         * So do only marginal checking and expect higher level protocols
         * to handle crap frames.
@@ -2647,11 +2652,8 @@ static inline void sky2_tx_done(struct net_device *dev, u16 last)
 }
 
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
-                              u32 status, struct sk_buff *skb)
+                              struct sk_buff *skb)
 {
-       if (status & GMR_FS_VLAN)
-               __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
-
        if (skb->ip_summed == CHECKSUM_NONE)
                netif_receive_skb(skb);
        else
@@ -2705,6 +2707,14 @@ static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
        }
 }
 
+static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
+{
+       struct sk_buff *skb;
+
+       skb = sky2->rx_ring[sky2->rx_next].skb;
+       __vlan_hwaccel_put_tag(skb, be16_to_cpu(length));
+}
+
 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
 {
        struct sk_buff *skb;
@@ -2763,8 +2773,7 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
                        }
 
                        skb->protocol = eth_type_trans(skb, dev);
-
-                       sky2_skb_rx(sky2, status, skb);
+                       sky2_skb_rx(sky2, skb);
 
                        /* Stop after net poll weight */
                        if (++work_done >= to_do)
@@ -2772,11 +2781,11 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
                        break;
 
                case OP_RXVLAN:
-                       sky2->rx_tag = length;
+                       sky2_rx_tag(sky2, length);
                        break;
 
                case OP_RXCHKSVLAN:
-                       sky2->rx_tag = length;
+                       sky2_rx_tag(sky2, length);
                        /* fall through */
                case OP_RXCHKS:
                        if (likely(dev->features & NETIF_F_RXCSUM))

diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h
index ff6f58b..3c896ce 100644 (file)
--- a/drivers/net/ethernet/marvell/sky2.h
+++ b/drivers/net/ethernet/marvell/sky2.h
@@ -2241,7 +2241,6 @@ struct sky2_port {
        u16                  rx_pending;
        u16                  rx_data_size;
        u16                  rx_nfrags;
-       u16                  rx_tag;
 
        struct {
                unsigned long last;

diff --git a/drivers/net/ethernet/micrel/ks8851.c b/drivers/net/ethernet/micrel/ks8851.c
index c722aa6..f8dda00 100644 (file)
--- a/drivers/net/ethernet/micrel/ks8851.c
+++ b/drivers/net/ethernet/micrel/ks8851.c
@@ -889,16 +889,17 @@ static int ks8851_net_stop(struct net_device *dev)
        netif_stop_queue(dev);
 
        mutex_lock(&ks->lock);
+       /* turn off the IRQs and ack any outstanding */
+       ks8851_wrreg16(ks, KS_IER, 0x0000);
+       ks8851_wrreg16(ks, KS_ISR, 0xffff);
+       mutex_unlock(&ks->lock);
 
        /* stop any outstanding work */
        flush_work(&ks->irq_work);
        flush_work(&ks->tx_work);
        flush_work(&ks->rxctrl_work);
 
-       /* turn off the IRQs and ack any outstanding */
-       ks8851_wrreg16(ks, KS_IER, 0x0000);
-       ks8851_wrreg16(ks, KS_ISR, 0xffff);
-
+       mutex_lock(&ks->lock);
        /* shutdown RX process */
        ks8851_wrreg16(ks, KS_RXCR1, 0x0000);
 
@@ -907,6 +908,7 @@ static int ks8851_net_stop(struct net_device *dev)
 
        /* set powermode to soft power down to save power */
        ks8851_set_powermode(ks, PMECR_PM_SOFTDOWN);
+       mutex_unlock(&ks->lock);
 
        /* ensure any queued tx buffers are dumped */
        while (!skb_queue_empty(&ks->txq)) {
@@ -918,7 +920,6 @@ static int ks8851_net_stop(struct net_device *dev)
                dev_kfree_skb(txb);
        }
 
-       mutex_unlock(&ks->lock);
        return 0;
 }
 
@@ -1418,6 +1419,7 @@ static int __devinit ks8851_probe(struct spi_device *spi)
        struct net_device *ndev;
        struct ks8851_net *ks;
        int ret;
+       unsigned cider;
 
        ndev = alloc_etherdev(sizeof(struct ks8851_net));
        if (!ndev)
@@ -1484,8 +1486,8 @@ static int __devinit ks8851_probe(struct spi_device *spi)
        ks8851_soft_reset(ks, GRR_GSR);
 
        /* simple check for a valid chip being connected to the bus */
-
-       if ((ks8851_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
+       cider = ks8851_rdreg16(ks, KS_CIDER);
+       if ((cider & ~CIDER_REV_MASK) != CIDER_ID) {
                dev_err(&spi->dev, "failed to read device ID\n");
                ret = -ENODEV;
                goto err_id;
@@ -1516,15 +1518,14 @@ static int __devinit ks8851_probe(struct spi_device *spi)
        }
 
        netdev_info(ndev, "revision %d, MAC %pM, IRQ %d, %s EEPROM\n",
-                   CIDER_REV_GET(ks8851_rdreg16(ks, KS_CIDER)),
-                   ndev->dev_addr, ndev->irq,
+                   CIDER_REV_GET(cider), ndev->dev_addr, ndev->irq,
                    ks->rc_ccr & CCR_EEPROM ? "has" : "no");
 
        return 0;
 
 
 err_netdev:
-       free_irq(ndev->irq, ndev);
+       free_irq(ndev->irq, ks);
 
 err_id:
 err_irq:

diff --git a/drivers/net/ethernet/micrel/ks8851_mll.c b/drivers/net/ethernet/micrel/ks8851_mll.c
index b8104d9..5ffde23 100644 (file)
--- a/drivers/net/ethernet/micrel/ks8851_mll.c
+++ b/drivers/net/ethernet/micrel/ks8851_mll.c
@@ -40,7 +40,7 @@
 #define        DRV_NAME        "ks8851_mll"
 
 static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
-#define MAX_RECV_FRAMES                        32
+#define MAX_RECV_FRAMES                        255
 #define MAX_BUF_SIZE                   2048
 #define TX_BUF_SIZE                    2000
 #define RX_BUF_SIZE                    2000

diff --git a/drivers/net/ethernet/micrel/ksz884x.c b/drivers/net/ethernet/micrel/ksz884x.c
index ef723b1..eaf9ff0 100644 (file)
--- a/drivers/net/ethernet/micrel/ksz884x.c
+++ b/drivers/net/ethernet/micrel/ksz884x.c
@@ -5675,7 +5675,7 @@ static int netdev_set_mac_address(struct net_device *dev, void *addr)
                memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
        }
 
-       memcpy(dev->dev_addr, mac->sa_data, MAX_ADDR_LEN);
+       memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN);
 
        interrupt = hw_block_intr(hw);
 

diff --git a/drivers/net/ethernet/realtek/8139cp.c b/drivers/net/ethernet/realtek/8139cp.c
index abc7907..b3287c0 100644 (file)
--- a/drivers/net/ethernet/realtek/8139cp.c
+++ b/drivers/net/ethernet/realtek/8139cp.c
@@ -958,6 +958,11 @@ static inline void cp_start_hw (struct cp_private *cp)
        cpw8(Cmd, RxOn | TxOn);
 }
 
+static void cp_enable_irq(struct cp_private *cp)
+{
+       cpw16_f(IntrMask, cp_intr_mask);
+}
+
 static void cp_init_hw (struct cp_private *cp)
 {
        struct net_device *dev = cp->dev;
@@ -997,8 +1002,6 @@ static void cp_init_hw (struct cp_private *cp)
 
        cpw16(MultiIntr, 0);
 
-       cpw16_f(IntrMask, cp_intr_mask);
-
        cpw8_f(Cfg9346, Cfg9346_Lock);
 }
 
@@ -1130,6 +1133,8 @@ static int cp_open (struct net_device *dev)
        if (rc)
                goto err_out_hw;
 
+       cp_enable_irq(cp);
+
        netif_carrier_off(dev);
        mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
        netif_start_queue(dev);
@@ -2031,6 +2036,7 @@ static int cp_resume (struct pci_dev *pdev)
        /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
        cp_init_rings_index (cp);
        cp_init_hw (cp);
+       cp_enable_irq(cp);
        netif_start_queue (dev);
 
        spin_lock_irqsave (&cp->lock, flags);

diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c
index 4a69710..cd3defb 100644 (file)
--- a/drivers/net/ethernet/smsc/smsc911x.c
+++ b/drivers/net/ethernet/smsc/smsc911x.c
@@ -1166,10 +1166,8 @@ smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
 
 /* Quickly dumps bad packets */
 static void
-smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
+smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords)
 {
-       unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
-
        if (likely(pktwords >= 4)) {
                unsigned int timeout = 500;
                unsigned int val;
@@ -1233,7 +1231,7 @@ static int smsc911x_poll(struct napi_struct *napi, int budget)
                        continue;
                }
 
-               skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
+               skb = netdev_alloc_skb(dev, pktwords << 2);
                if (unlikely(!skb)) {
                        SMSC_WARN(pdata, rx_err,
                                  "Unable to allocate skb for rx packet");
@@ -1243,14 +1241,12 @@ static int smsc911x_poll(struct napi_struct *napi, int budget)
                        break;
                }
 
-               skb->data = skb->head;
-               skb_reset_tail_pointer(skb);
+               pdata->ops->rx_readfifo(pdata,
+                                (unsigned int *)skb->data, pktwords);
 
                /* Align IP on 16B boundary */
                skb_reserve(skb, NET_IP_ALIGN);
                skb_put(skb, pktlength - 4);
-               pdata->ops->rx_readfifo(pdata,
-                                (unsigned int *)skb->head, pktwords);
                skb->protocol = eth_type_trans(skb, dev);
                skb_checksum_none_assert(skb);
                netif_receive_skb(skb);
@@ -1565,7 +1561,7 @@ static int smsc911x_open(struct net_device *dev)
        smsc911x_reg_write(pdata, FIFO_INT, temp);
 
        /* set RX Data offset to 2 bytes for alignment */
-       smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
+       smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8));
 
        /* enable NAPI polling before enabling RX interrupts */
        napi_enable(&pdata->napi);
@@ -2382,7 +2378,6 @@ static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
        SET_NETDEV_DEV(dev, &pdev->dev);
 
        pdata = netdev_priv(dev);
-
        dev->irq = irq_res->start;
        irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
        pdata->ioaddr = ioremap_nocache(res->start, res_size);
@@ -2446,7 +2441,7 @@ static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
        if (retval) {
                SMSC_WARN(pdata, probe,
                          "Unable to claim requested irq: %d", dev->irq);
-               goto out_free_irq;
+               goto out_disable_resources;
        }
 
        retval = register_netdev(dev);

diff --git a/drivers/net/ethernet/sun/sungem.c b/drivers/net/ethernet/sun/sungem.c
index 558409f..4ba9690 100644 (file)
--- a/drivers/net/ethernet/sun/sungem.c
+++ b/drivers/net/ethernet/sun/sungem.c
@@ -2339,7 +2339,7 @@ static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
        netif_device_detach(dev);
 
        /* Switch off chip, remember WOL setting */
-       gp->asleep_wol = gp->wake_on_lan;
+       gp->asleep_wol = !!gp->wake_on_lan;
        gem_do_stop(dev, gp->asleep_wol);
 
        /* Unlock the network stack */

diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c
index 174a334..08aff1a 100644 (file)
--- a/drivers/net/ethernet/ti/davinci_emac.c
+++ b/drivers/net/ethernet/ti/davinci_emac.c
@@ -1511,7 +1511,7 @@ static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
 
 static int match_first_device(struct device *dev, void *data)
 {
-       return 1;
+       return !strncmp(dev_name(dev), "davinci_mdio", 12);
 }
 
 /**

diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index 2757c7d..e4e4708 100644 (file)
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -181,6 +181,11 @@ static inline int wait_for_user_access(struct davinci_mdio_data *data)
                __davinci_mdio_reset(data);
                return -EAGAIN;
        }
+
+       reg = __raw_readl(&regs->user[0].access);
+       if ((reg & USERACCESS_GO) == 0)
+               return 0;
+
        dev_err(data->dev, "timed out waiting for user access\n");
        return -ETIMEDOUT;
 }

diff --git a/drivers/net/ethernet/ti/tlan.c b/drivers/net/ethernet/ti/tlan.c
index 817ad3b..efd3669 100644 (file)
--- a/drivers/net/ethernet/ti/tlan.c
+++ b/drivers/net/ethernet/ti/tlan.c
@@ -228,7 +228,7 @@ tlan_get_skb(const struct tlan_list *tag)
        unsigned long addr;
 
        addr = tag->buffer[9].address;
-       addr |= (tag->buffer[8].address << 16) << 16;
+       addr |= ((unsigned long) tag->buffer[8].address << 16) << 16;
        return (struct sk_buff *) addr;
 }
 

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index cc83af0..44b8d2b 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -2,9 +2,7 @@
  * Definitions for Xilinx Axi Ethernet device driver.
  *
  * Copyright (c) 2009 Secret Lab Technologies, Ltd.
- * Copyright (c) 2010 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2012 Daniel Borkmann, <daniel.borkmann@tik.ee.ethz.ch>
- * Copyright (c) 2012 Ariane Keller, <ariane.keller@tik.ee.ethz.ch>
+ * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
  */
 
 #ifndef XILINX_AXIENET_H

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 2fcbeba..9c365e1 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -4,9 +4,9 @@
  * Copyright (c) 2008 Nissin Systems Co., Ltd.,  Yoshio Kashiwagi
  * Copyright (c) 2005-2008 DLA Systems,  David H. Lynch Jr. <dhlii@dlasys.net>
  * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
- * Copyright (c) 2010 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2012 Daniel Borkmann, <daniel.borkmann@tik.ee.ethz.ch>
- * Copyright (c) 2012 Ariane Keller, <ariane.keller@tik.ee.ethz.ch>
+ * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (c) 2010 - 2011 PetaLogix
+ * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
  *
  * This is a driver for the Xilinx Axi Ethernet which is used in the Virtex6
  * and Spartan6.

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
index d70b6e7..e90e1f4 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
@@ -2,9 +2,9 @@
  * MDIO bus driver for the Xilinx Axi Ethernet device
  *
  * Copyright (c) 2009 Secret Lab Technologies, Ltd.
- * Copyright (c) 2010 Xilinx, Inc. All rights reserved.
- * Copyright (c) 2012 Daniel Borkmann, <daniel.borkmann@tik.ee.ethz.ch>
- * Copyright (c) 2012 Ariane Keller, <ariane.keller@tik.ee.ethz.ch>
+ * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (c) 2010 - 2011 PetaLogix
+ * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
  */
 
 #include <linux/of_address.h>

diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c
index dd29478..2d59138 100644 (file)
--- a/drivers/net/hyperv/netvsc_drv.c
+++ b/drivers/net/hyperv/netvsc_drv.c
@@ -44,6 +44,7 @@ struct net_device_context {
        /* point back to our device context */
        struct hv_device *device_ctx;
        struct delayed_work dwork;
+       struct work_struct work;
 };
 
 
@@ -51,30 +52,22 @@ static int ring_size = 128;
 module_param(ring_size, int, S_IRUGO);
 MODULE_PARM_DESC(ring_size, "Ring buffer size (# of pages)");
 
-struct set_multicast_work {
-       struct work_struct work;
-       struct net_device *net;
-};
-
 static void do_set_multicast(struct work_struct *w)
 {
-       struct set_multicast_work *swk =
-               container_of(w, struct set_multicast_work, work);
-       struct net_device *net = swk->net;
-
-       struct net_device_context *ndevctx = netdev_priv(net);
+       struct net_device_context *ndevctx =
+               container_of(w, struct net_device_context, work);
        struct netvsc_device *nvdev;
        struct rndis_device *rdev;
 
        nvdev = hv_get_drvdata(ndevctx->device_ctx);
-       if (nvdev == NULL)
-               goto out;
+       if (nvdev == NULL || nvdev->ndev == NULL)
+               return;
 
        rdev = nvdev->extension;
        if (rdev == NULL)
-               goto out;
+               return;
 
-       if (net->flags & IFF_PROMISC)
+       if (nvdev->ndev->flags & IFF_PROMISC)
                rndis_filter_set_packet_filter(rdev,
                        NDIS_PACKET_TYPE_PROMISCUOUS);
        else
@@ -82,21 +75,13 @@ static void do_set_multicast(struct work_struct *w)
                        NDIS_PACKET_TYPE_BROADCAST |
                        NDIS_PACKET_TYPE_ALL_MULTICAST |
                        NDIS_PACKET_TYPE_DIRECTED);
-
-out:
-       kfree(w);
 }
 
 static void netvsc_set_multicast_list(struct net_device *net)
 {
-       struct set_multicast_work *swk =
-               kmalloc(sizeof(struct set_multicast_work), GFP_ATOMIC);
-       if (swk == NULL)
-               return;
+       struct net_device_context *net_device_ctx = netdev_priv(net);
 
-       swk->net = net;
-       INIT_WORK(&swk->work, do_set_multicast);
-       schedule_work(&swk->work);
+       schedule_work(&net_device_ctx->work);
 }
 
 static int netvsc_open(struct net_device *net)
@@ -125,6 +110,8 @@ static int netvsc_close(struct net_device *net)
 
        netif_tx_disable(net);
 
+       /* Make sure netvsc_set_multicast_list doesn't re-enable filter! */
+       cancel_work_sync(&net_device_ctx->work);
        ret = rndis_filter_close(device_obj);
        if (ret != 0)
                netdev_err(net, "unable to close device (ret %d).\n", ret);
@@ -335,6 +322,7 @@ static int netvsc_change_mtu(struct net_device *ndev, int mtu)
 
        nvdev->start_remove = true;
        cancel_delayed_work_sync(&ndevctx->dwork);
+       cancel_work_sync(&ndevctx->work);
        netif_tx_disable(ndev);
        rndis_filter_device_remove(hdev);
 
@@ -403,6 +391,7 @@ static int netvsc_probe(struct hv_device *dev,
        net_device_ctx->device_ctx = dev;
        hv_set_drvdata(dev, net);
        INIT_DELAYED_WORK(&net_device_ctx->dwork, netvsc_send_garp);
+       INIT_WORK(&net_device_ctx->work, do_set_multicast);
 
        net->netdev_ops = &device_ops;
 
@@ -456,6 +445,7 @@ static int netvsc_remove(struct hv_device *dev)
 
        ndev_ctx = netdev_priv(net);
        cancel_delayed_work_sync(&ndev_ctx->dwork);
+       cancel_work_sync(&ndev_ctx->work);
 
        /* Stop outbound asap */
        netif_tx_disable(net);

diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index f08c85a..5ac46f5 100644 (file)
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -40,6 +40,7 @@ MODULE_LICENSE("GPL");
 #define IP1001_PHASE_SEL_MASK          3       /* IP1001 RX/TXPHASE_SEL */
 #define IP1001_APS_ON                  11      /* IP1001 APS Mode  bit */
 #define IP101A_G_APS_ON                        2       /* IP101A/G APS Mode bit */
+#define IP101A_G_IRQ_CONF_STATUS       0x11    /* Conf Info IRQ & Status Reg */
 
 static int ip175c_config_init(struct phy_device *phydev)
 {
@@ -185,6 +186,15 @@ static int ip175c_config_aneg(struct phy_device *phydev)
        return 0;
 }
 
+static int ip101a_g_ack_interrupt(struct phy_device *phydev)
+{
+       int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
+       if (err < 0)
+               return err;
+
+       return 0;
+}
+
 static struct phy_driver ip175c_driver = {
        .phy_id         = 0x02430d80,
        .name           = "ICPlus IP175C",
@@ -204,7 +214,6 @@ static struct phy_driver ip1001_driver = {
        .phy_id_mask    = 0x0ffffff0,
        .features       = PHY_GBIT_FEATURES | SUPPORTED_Pause |
                          SUPPORTED_Asym_Pause,
-       .flags          = PHY_HAS_INTERRUPT,
        .config_init    = &ip1001_config_init,
        .config_aneg    = &genphy_config_aneg,
        .read_status    = &genphy_read_status,
@@ -220,6 +229,7 @@ static struct phy_driver ip101a_g_driver = {
        .features       = PHY_BASIC_FEATURES | SUPPORTED_Pause |
                          SUPPORTED_Asym_Pause,
        .flags          = PHY_HAS_INTERRUPT,
+       .ack_interrupt  = ip101a_g_ack_interrupt,
        .config_init    = &ip101a_g_config_init,
        .config_aneg    = &genphy_config_aneg,
        .read_status    = &genphy_read_status,

diff --git a/drivers/net/ppp/ppp_generic.c b/drivers/net/ppp/ppp_generic.c
index 33f8c51..21d7151 100644 (file)
--- a/drivers/net/ppp/ppp_generic.c
+++ b/drivers/net/ppp/ppp_generic.c
@@ -235,7 +235,7 @@ struct ppp_net {
 /* Prototypes. */
 static int ppp_unattached_ioctl(struct net *net, struct ppp_file *pf,
                        struct file *file, unsigned int cmd, unsigned long arg);
-static int ppp_xmit_process(struct ppp *ppp);
+static void ppp_xmit_process(struct ppp *ppp);
 static void ppp_send_frame(struct ppp *ppp, struct sk_buff *skb);
 static void ppp_push(struct ppp *ppp);
 static void ppp_channel_push(struct channel *pch);
@@ -969,8 +969,7 @@ ppp_start_xmit(struct sk_buff *skb, struct net_device *dev)
        put_unaligned_be16(proto, pp);
 
        skb_queue_tail(&ppp->file.xq, skb);
-       if (!ppp_xmit_process(ppp))
-               netif_stop_queue(dev);
+       ppp_xmit_process(ppp);
        return NETDEV_TX_OK;
 
  outf:
@@ -1048,11 +1047,10 @@ static void ppp_setup(struct net_device *dev)
  * Called to do any work queued up on the transmit side
  * that can now be done.
  */
-static int
+static void
 ppp_xmit_process(struct ppp *ppp)
 {
        struct sk_buff *skb;
-       int ret = 0;
 
        ppp_xmit_lock(ppp);
        if (!ppp->closing) {
@@ -1062,13 +1060,12 @@ ppp_xmit_process(struct ppp *ppp)
                        ppp_send_frame(ppp, skb);
                /* If there's no work left to do, tell the core net
                   code that we can accept some more. */
-               if (!ppp->xmit_pending && !skb_peek(&ppp->file.xq)) {
+               if (!ppp->xmit_pending && !skb_peek(&ppp->file.xq))
                        netif_wake_queue(ppp->dev);
-                       ret = 1;
-               }
+               else
+                       netif_stop_queue(ppp->dev);
        }
        ppp_xmit_unlock(ppp);
-       return ret;
 }
 
 static inline struct sk_buff *

diff --git a/drivers/net/usb/asix.c b/drivers/net/usb/asix.c
index 5ee032c..42b5151 100644 (file)
--- a/drivers/net/usb/asix.c
+++ b/drivers/net/usb/asix.c
@@ -355,7 +355,7 @@ static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
        u32 packet_len;
        u32 padbytes = 0xffff0000;
 
-       padlen = ((skb->len + 4) % 512) ? 0 : 4;
+       padlen = ((skb->len + 4) & (dev->maxpacket - 1)) ? 0 : 4;
 
        if ((!skb_cloned(skb)) &&
            ((headroom + tailroom) >= (4 + padlen))) {
@@ -377,7 +377,7 @@ static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
        cpu_to_le32s(&packet_len);
        skb_copy_to_linear_data(skb, &packet_len, sizeof(packet_len));
 
-       if ((skb->len % 512) == 0) {
+       if (padlen) {
                cpu_to_le32s(&padbytes);
                memcpy(skb_tail_pointer(skb), &padbytes, sizeof(padbytes));
                skb_put(skb, sizeof(padbytes));

diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 552d24b..d316503 100644 (file)
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -365,6 +365,27 @@ static const struct driver_info    qmi_wwan_force_int4 = {
        .data           = BIT(4), /* interface whitelist bitmap */
 };
 
+/* Sierra Wireless provide equally useless interface descriptors
+ * Devices in QMI mode can be switched between two different
+ * configurations:
+ *   a) USB interface #8 is QMI/wwan
+ *   b) USB interfaces #8, #19 and #20 are QMI/wwan
+ *
+ * Both configurations provide a number of other interfaces (serial++),
+ * some of which have the same endpoint configuration as we expect, so
+ * a whitelist or blacklist is necessary.
+ *
+ * FIXME: The below whitelist should include BIT(20).  It does not
+ * because I cannot get it to work...
+ */
+static const struct driver_info        qmi_wwan_sierra = {
+       .description    = "Sierra Wireless wwan/QMI device",
+       .flags          = FLAG_WWAN,
+       .bind           = qmi_wwan_bind_gobi,
+       .unbind         = qmi_wwan_unbind_shared,
+       .manage_power   = qmi_wwan_manage_power,
+       .data           = BIT(8) | BIT(19), /* interface whitelist bitmap */
+};
 
 #define HUAWEI_VENDOR_ID       0x12D1
 #define QMI_GOBI_DEVICE(vend, prod) \
@@ -445,6 +466,15 @@ static const struct usb_device_id products[] = {
                .bInterfaceProtocol = 0xff,
                .driver_info        = (unsigned long)&qmi_wwan_force_int4,
        },
+       {       /* Sierra Wireless MC77xx in QMI mode */
+               .match_flags        = USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_INT_INFO,
+               .idVendor           = 0x1199,
+               .idProduct          = 0x68a2,
+               .bInterfaceClass    = 0xff,
+               .bInterfaceSubClass = 0xff,
+               .bInterfaceProtocol = 0xff,
+               .driver_info        = (unsigned long)&qmi_wwan_sierra,
+       },
        {QMI_GOBI_DEVICE(0x05c6, 0x9212)},      /* Acer Gobi Modem Device */
        {QMI_GOBI_DEVICE(0x03f0, 0x1f1d)},      /* HP un2400 Gobi Modem Device */
        {QMI_GOBI_DEVICE(0x03f0, 0x371d)},      /* HP un2430 Mobile Broadband Module */

diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c
index 187d01c..00103a8 100644 (file)
--- a/drivers/net/usb/smsc75xx.c
+++ b/drivers/net/usb/smsc75xx.c
@@ -98,7 +98,7 @@ static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
 
        if (unlikely(ret < 0))
                netdev_warn(dev->net,
-                       "Failed to read register index 0x%08x", index);
+                       "Failed to read reg index 0x%08x: %d", index, ret);
 
        le32_to_cpus(buf);
        *data = *buf;
@@ -128,7 +128,7 @@ static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
 
        if (unlikely(ret < 0))
                netdev_warn(dev->net,
-                       "Failed to write register index 0x%08x", index);
+                       "Failed to write reg index 0x%08x: %d", index, ret);
 
        kfree(buf);
 
@@ -171,7 +171,7 @@ static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
        idx &= dev->mii.reg_num_mask;
        addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
                | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
-               | MII_ACCESS_READ;
+               | MII_ACCESS_READ | MII_ACCESS_BUSY;
        ret = smsc75xx_write_reg(dev, MII_ACCESS, addr);
        check_warn_goto_done(ret, "Error writing MII_ACCESS");
 
@@ -210,7 +210,7 @@ static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
        idx &= dev->mii.reg_num_mask;
        addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
                | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
-               | MII_ACCESS_WRITE;
+               | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
        ret = smsc75xx_write_reg(dev, MII_ACCESS, addr);
        check_warn_goto_done(ret, "Error writing MII_ACCESS");
 
@@ -508,9 +508,10 @@ static int smsc75xx_link_reset(struct usbnet *dev)
        u16 lcladv, rmtadv;
        int ret;
 
-       /* clear interrupt status */
+       /* read and write to clear phy interrupt status */
        ret = smsc75xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
        check_warn_return(ret, "Error reading PHY_INT_SRC");
+       smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC, 0xffff);
 
        ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
        check_warn_return(ret, "Error writing INT_STS");
@@ -643,7 +644,7 @@ static int smsc75xx_set_mac_address(struct usbnet *dev)
 
 static int smsc75xx_phy_initialize(struct usbnet *dev)
 {
-       int bmcr, timeout = 0;
+       int bmcr, ret, timeout = 0;
 
        /* Initialize MII structure */
        dev->mii.dev = dev->net;
@@ -651,6 +652,7 @@ static int smsc75xx_phy_initialize(struct usbnet *dev)
        dev->mii.mdio_write = smsc75xx_mdio_write;
        dev->mii.phy_id_mask = 0x1f;
        dev->mii.reg_num_mask = 0x1f;
+       dev->mii.supports_gmii = 1;
        dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
 
        /* reset phy and wait for reset to complete */
@@ -661,7 +663,7 @@ static int smsc75xx_phy_initialize(struct usbnet *dev)
                bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
                check_warn_return(bmcr, "Error reading MII_BMCR");
                timeout++;
-       } while ((bmcr & MII_BMCR) && (timeout < 100));
+       } while ((bmcr & BMCR_RESET) && (timeout < 100));
 
        if (timeout >= 100) {
                netdev_warn(dev->net, "timeout on PHY Reset");
@@ -671,10 +673,13 @@ static int smsc75xx_phy_initialize(struct usbnet *dev)
        smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
                ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
                ADVERTISE_PAUSE_ASYM);
+       smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
+               ADVERTISE_1000FULL);
 
-       /* read to clear */
-       smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
-       check_warn_return(bmcr, "Error reading PHY_INT_SRC");
+       /* read and write to clear phy interrupt status */
+       ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
+       check_warn_return(ret, "Error reading PHY_INT_SRC");
+       smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
 
        smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
                PHY_INT_MASK_DEFAULT);
@@ -946,6 +951,14 @@ static int smsc75xx_reset(struct usbnet *dev)
        ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
        check_warn_return(ret, "Failed to write INT_EP_CTL: %d", ret);
 
+       /* allow mac to detect speed and duplex from phy */
+       ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
+       check_warn_return(ret, "Failed to read MAC_CR: %d", ret);
+
+       buf |= (MAC_CR_ADD | MAC_CR_ASD);
+       ret = smsc75xx_write_reg(dev, MAC_CR, buf);
+       check_warn_return(ret, "Failed to write MAC_CR: %d", ret);
+
        ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
        check_warn_return(ret, "Failed to read MAC_TX: %d", ret);
 
@@ -1051,6 +1064,7 @@ static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
        dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
        dev->net->flags |= IFF_MULTICAST;
        dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
+       dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
        return 0;
 }
 
@@ -1211,7 +1225,7 @@ static const struct driver_info smsc75xx_info = {
        .rx_fixup       = smsc75xx_rx_fixup,
        .tx_fixup       = smsc75xx_tx_fixup,
        .status         = smsc75xx_status,
-       .flags          = FLAG_ETHER | FLAG_SEND_ZLP,
+       .flags          = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
 };
 
 static const struct usb_device_id products[] = {

diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c
index 5f19f84..94ae669 100644 (file)
--- a/drivers/net/usb/smsc95xx.c
+++ b/drivers/net/usb/smsc95xx.c
@@ -1017,6 +1017,7 @@ static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
        dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
        dev->net->flags |= IFF_MULTICAST;
        dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
+       dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
        return 0;
 }
 
@@ -1191,7 +1192,7 @@ static const struct driver_info smsc95xx_info = {
        .rx_fixup       = smsc95xx_rx_fixup,
        .tx_fixup       = smsc95xx_tx_fixup,
        .status         = smsc95xx_status,
-       .flags          = FLAG_ETHER | FLAG_SEND_ZLP,
+       .flags          = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
 };
 
 static const struct usb_device_id products[] = {

diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
index b7b3f5b..2d927fb 100644 (file)
--- a/drivers/net/usb/usbnet.c
+++ b/drivers/net/usb/usbnet.c
@@ -210,6 +210,7 @@ static int init_status (struct usbnet *dev, struct usb_interface *intf)
                } else {
                        usb_fill_int_urb(dev->interrupt, dev->udev, pipe,
                                buf, maxp, intr_complete, dev, period);
+                       dev->interrupt->transfer_flags |= URB_FREE_BUFFER;
                        dev_dbg(&intf->dev,
                                "status ep%din, %d bytes period %d\n",
                                usb_pipeendpoint(pipe), maxp, period);
@@ -1443,7 +1444,7 @@ usbnet_probe (struct usb_interface *udev, const struct usb_device_id *prod)
 
        status = register_netdev (net);
        if (status)
-               goto out3;
+               goto out4;
        netif_info(dev, probe, dev->net,
                   "register '%s' at usb-%s-%s, %s, %pM\n",
                   udev->dev.driver->name,
@@ -1461,6 +1462,8 @@ usbnet_probe (struct usb_interface *udev, const struct usb_device_id *prod)
 
        return 0;
 
+out4:
+       usb_free_urb(dev->interrupt);
 out3:
        if (info->unbind)
                info->unbind (dev, udev);

diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index 4de2760..af8acc8 100644 (file)
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -626,16 +626,15 @@ static netdev_tx_t start_xmit(struct sk_buff *skb, struct net_device *dev)
        /* This can happen with OOM and indirect buffers. */
        if (unlikely(capacity < 0)) {
                if (likely(capacity == -ENOMEM)) {
-                       if (net_ratelimit()) {
+                       if (net_ratelimit())
                                dev_warn(&dev->dev,
                                         "TX queue failure: out of memory\n");
-                       } else {
+               } else {
                        dev->stats.tx_fifo_errors++;
                        if (net_ratelimit())
                                dev_warn(&dev->dev,
                                         "Unexpected TX queue failure: %d\n",
                                         capacity);
-                       }
                }
                dev->stats.tx_dropped++;
                kfree_skb(skb);

diff --git a/drivers/net/wan/farsync.c b/drivers/net/wan/farsync.c
index ebb9f24..1a62318 100644 (file)
--- a/drivers/net/wan/farsync.c
+++ b/drivers/net/wan/farsync.c
@@ -2483,6 +2483,7 @@ fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
                pr_err("Control memory remap failed\n");
                pci_release_regions(pdev);
                pci_disable_device(pdev);
+               iounmap(card->mem);
                kfree(card);
                return -ENODEV;
        }

diff --git a/drivers/net/wireless/ath/ath5k/ahb.c b/drivers/net/wireless/ath/ath5k/ahb.c
index 8faa129..aec33cc 100644 (file)
--- a/drivers/net/wireless/ath/ath5k/ahb.c
+++ b/drivers/net/wireless/ath/ath5k/ahb.c
@@ -19,6 +19,7 @@
 #include <linux/nl80211.h>
 #include <linux/platform_device.h>
 #include <linux/etherdevice.h>
+#include <linux/export.h>
 #include <ar231x_platform.h>
 #include "ath5k.h"
 #include "debug.h"
@@ -119,7 +120,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
        if (res == NULL) {
                dev_err(&pdev->dev, "no IRQ resource found\n");
                ret = -ENXIO;
-               goto err_out;
+               goto err_iounmap;
        }
 
        irq = res->start;
@@ -128,7 +129,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
        if (hw == NULL) {
                dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
                ret = -ENOMEM;
-               goto err_out;
+               goto err_iounmap;
        }
 
        ah = hw->priv;
@@ -185,6 +186,8 @@ static int ath_ahb_probe(struct platform_device *pdev)
  err_free_hw:
        ieee80211_free_hw(hw);
        platform_set_drvdata(pdev, NULL);
+ err_iounmap:
+        iounmap(mem);
  err_out:
        return ret;
 }
@@ -217,6 +220,7 @@ static int ath_ahb_remove(struct platform_device *pdev)
        }
 
        ath5k_deinit_ah(ah);
+       iounmap(ah->iobase);
        platform_set_drvdata(pdev, NULL);
        ieee80211_free_hw(hw);
 

diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index d7d8e91..aba0880 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -869,7 +869,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
        ar5008_hw_set_channel_regs(ah, chan);
        ar5008_hw_init_chain_masks(ah);
        ath9k_olc_init(ah);
-       ath9k_hw_apply_txpower(ah, chan);
+       ath9k_hw_apply_txpower(ah, chan, false);
 
        /* Write analog registers */
        if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 59647a3..3d400e8 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -54,7 +54,7 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val)
 
        if (val) {
                ah->paprd_table_write_done = true;
-               ath9k_hw_apply_txpower(ah, chan);
+               ath9k_hw_apply_txpower(ah, chan, false);
        }
 
        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index bc992b2..deb6cfb 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -694,7 +694,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
        ar9003_hw_override_ini(ah);
        ar9003_hw_set_channel_regs(ah, chan);
        ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
-       ath9k_hw_apply_txpower(ah, chan);
+       ath9k_hw_apply_txpower(ah, chan, false);
 
        if (AR_SREV_9462(ah)) {
                if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,

diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index f272236..b34e8b2 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -824,6 +824,8 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
                        regulatory->max_power_level = ratesArray[i];
        }
 
+       ath9k_hw_update_regulatory_maxpower(ah);
+
        if (test)
                return;
 

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 6c69e4e..fa84e37 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1454,7 +1454,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
                return false;
        }
        ath9k_hw_set_clockrate(ah);
-       ath9k_hw_apply_txpower(ah, chan);
+       ath9k_hw_apply_txpower(ah, chan, false);
        ath9k_hw_rfbus_done(ah);
 
        if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
@@ -2652,7 +2652,8 @@ static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
        return ah->eep_ops->get_eeprom(ah, gain_param);
 }
 
-void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
+void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
+                           bool test)
 {
        struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
        struct ieee80211_channel *channel;
@@ -2673,7 +2674,7 @@ void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan)
 
        ah->eep_ops->set_txpower(ah, chan,
                                 ath9k_regd_get_ctl(reg, chan),
-                                ant_reduction, new_pwr, false);
+                                ant_reduction, new_pwr, test);
 }
 
 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
@@ -2686,7 +2687,7 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
        if (test)
                channel->max_power = MAX_RATE_POWER / 2;
 
-       ath9k_hw_apply_txpower(ah, chan);
+       ath9k_hw_apply_txpower(ah, chan, test);
 
        if (test)
                channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index aa1680a..e88f182 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -985,7 +985,8 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 /* PHY */
 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
                                   u32 *coef_mantissa, u32 *coef_exponent);
-void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
+void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
+                           bool test);
 
 /*
  * Code Specific to AR5008, AR9001 or AR9002,

diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 2504ab0..798ea57 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -1548,6 +1548,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
        struct ath_hw *ah = sc->sc_ah;
        struct ath_common *common = ath9k_hw_common(ah);
        struct ieee80211_conf *conf = &hw->conf;
+       bool reset_channel = false;
 
        ath9k_ps_wakeup(sc);
        mutex_lock(&sc->mutex);
@@ -1556,6 +1557,12 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
                sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
                if (sc->ps_idle)
                        ath_cancel_work(sc);
+               else
+                       /*
+                        * The chip needs a reset to properly wake up from
+                        * full sleep
+                        */
+                       reset_channel = ah->chip_fullsleep;
        }
 
        /*
@@ -1584,7 +1591,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
                }
        }
 
-       if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+       if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
                struct ieee80211_channel *curchan = hw->conf.channel;
                int pos = curchan->hw_value;
                int old_pos = -1;

diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 834e6bc..23eaa1b 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -1820,6 +1820,7 @@ static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
        struct ath_frame_info *fi = get_frame_info(skb);
        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
        struct ath_buf *bf;
+       int fragno;
        u16 seqno;
 
        bf = ath_tx_get_buffer(sc);
@@ -1831,9 +1832,16 @@ static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
        ATH_TXBUF_RESET(bf);
 
        if (tid) {
+               fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
                seqno = tid->seq_next;
                hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
-               INCR(tid->seq_next, IEEE80211_SEQ_MAX);
+
+               if (fragno)
+                       hdr->seq_ctrl |= cpu_to_le16(fragno);
+
+               if (!ieee80211_has_morefrags(hdr->frame_control))
+                       INCR(tid->seq_next, IEEE80211_SEQ_MAX);
+
                bf->bf_state.seqno = seqno;
        }
 

diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index c79e663..e4d6dc2 100644 (file)
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -4827,8 +4827,14 @@ static int b43_op_start(struct ieee80211_hw *hw)
  out_mutex_unlock:
        mutex_unlock(&wl->mutex);
 
-       /* reload configuration */
-       b43_op_config(hw, ~0);
+       /*
+        * Configuration may have been overwritten during initialization.
+        * Reload the configuration, but only if initialization was
+        * successful. Reloading the configuration after a failed init
+        * may hang the system.
+        */
+       if (!err)
+               b43_op_config(hw, ~0);
 
        return err;
 }

diff --git a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c
index 4688904..758c115 100644 (file)
--- a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c
@@ -108,9 +108,15 @@ static inline int brcmf_sdioh_f0_write_byte(struct brcmf_sdio_dev *sdiodev,
                        sdio_release_host(sdfunc);
                }
        } else if (regaddr == SDIO_CCCR_ABORT) {
+               sdfunc = kmemdup(sdiodev->func[0], sizeof(struct sdio_func),
+                                GFP_KERNEL);
+               if (!sdfunc)
+                       return -ENOMEM;
+               sdfunc->num = 0;
                sdio_claim_host(sdfunc);
                sdio_writeb(sdfunc, *byte, regaddr, &err_ret);
                sdio_release_host(sdfunc);
+               kfree(sdfunc);
        } else if (regaddr < 0xF0) {
                brcmf_dbg(ERROR, "F0 Wr:0x%02x: write disallowed\n", regaddr);
                err_ret = -EPERM;
@@ -486,7 +492,7 @@ static int brcmf_ops_sdio_probe(struct sdio_func *func,
                        kfree(bus_if);
                        return -ENOMEM;
                }
-               sdiodev->func[0] = func->card->sdio_func[0];
+               sdiodev->func[0] = func;
                sdiodev->func[1] = func;
                sdiodev->bus_if = bus_if;
                bus_if->bus_priv.sdio = sdiodev;

diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
index 2bf5dda..eb3829b 100644 (file)
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
@@ -574,6 +574,8 @@ struct brcmf_sdio {
 
        struct task_struct *dpc_tsk;
        struct completion dpc_wait;
+       struct list_head dpc_tsklst;
+       spinlock_t dpc_tl_lock;
 
        struct semaphore sdsem;
 
@@ -2594,29 +2596,58 @@ clkwait:
        return resched;
 }
 
+static inline void brcmf_sdbrcm_adddpctsk(struct brcmf_sdio *bus)
+{
+       struct list_head *new_hd;
+       unsigned long flags;
+
+       if (in_interrupt())
+               new_hd = kzalloc(sizeof(struct list_head), GFP_ATOMIC);
+       else
+               new_hd = kzalloc(sizeof(struct list_head), GFP_KERNEL);
+       if (new_hd == NULL)
+               return;
+
+       spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+       list_add_tail(new_hd, &bus->dpc_tsklst);
+       spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+}
+
 static int brcmf_sdbrcm_dpc_thread(void *data)
 {
        struct brcmf_sdio *bus = (struct brcmf_sdio *) data;
+       struct list_head *cur_hd, *tmp_hd;
+       unsigned long flags;
 
        allow_signal(SIGTERM);
        /* Run until signal received */
        while (1) {
                if (kthread_should_stop())
                        break;
-               if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
-                       /* Call bus dpc unless it indicated down
-                       (then clean stop) */
-                       if (bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN) {
-                               if (brcmf_sdbrcm_dpc(bus))
-                                       complete(&bus->dpc_wait);
-                       } else {
+
+               if (list_empty(&bus->dpc_tsklst))
+                       if (wait_for_completion_interruptible(&bus->dpc_wait))
+                               break;
+
+               spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+               list_for_each_safe(cur_hd, tmp_hd, &bus->dpc_tsklst) {
+                       spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+
+                       if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
                                /* after stopping the bus, exit thread */
                                brcmf_sdbrcm_bus_stop(bus->sdiodev->dev);
                                bus->dpc_tsk = NULL;
                                break;
                        }
-               } else
-                       break;
+
+                       if (brcmf_sdbrcm_dpc(bus))
+                               brcmf_sdbrcm_adddpctsk(bus);
+
+                       spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+                       list_del(cur_hd);
+                       kfree(cur_hd);
+               }
+               spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
        }
        return 0;
 }
@@ -2669,8 +2700,10 @@ static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt)
        /* Schedule DPC if needed to send queued packet(s) */
        if (!bus->dpc_sched) {
                bus->dpc_sched = true;
-               if (bus->dpc_tsk)
+               if (bus->dpc_tsk) {
+                       brcmf_sdbrcm_adddpctsk(bus);
                        complete(&bus->dpc_wait);
+               }
        }
 
        return ret;
@@ -3514,8 +3547,10 @@ void brcmf_sdbrcm_isr(void *arg)
                brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
 
        bus->dpc_sched = true;
-       if (bus->dpc_tsk)
+       if (bus->dpc_tsk) {
+               brcmf_sdbrcm_adddpctsk(bus);
                complete(&bus->dpc_wait);
+       }
 }
 
 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
@@ -3559,8 +3594,10 @@ static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
                                bus->ipend = true;
 
                                bus->dpc_sched = true;
-                               if (bus->dpc_tsk)
+                               if (bus->dpc_tsk) {
+                                       brcmf_sdbrcm_adddpctsk(bus);
                                        complete(&bus->dpc_wait);
+                               }
                        }
                }
 
@@ -3897,6 +3934,8 @@ void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
        }
        /* Initialize DPC thread */
        init_completion(&bus->dpc_wait);
+       INIT_LIST_HEAD(&bus->dpc_tsklst);
+       spin_lock_init(&bus->dpc_tl_lock);
        bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
                                   bus, "brcmf_dpc");
        if (IS_ERR(bus->dpc_tsk)) {

diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.c b/drivers/net/wireless/brcm80211/brcmsmac/main.c
index 231ddf4..b4d9279 100644 (file)
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
@@ -847,8 +847,7 @@ brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
         */
        if (!(txs->status & TX_STATUS_AMPDU)
            && (txs->status & TX_STATUS_INTERMEDIATE)) {
-               wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
-                         __func__);
+               BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n");
                return false;
        }
 
@@ -7614,6 +7613,7 @@ brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
 {
        int len_mpdu;
        struct ieee80211_rx_status rx_status;
+       struct ieee80211_hdr *hdr;
 
        memset(&rx_status, 0, sizeof(rx_status));
        prep_mac80211_status(wlc, rxh, p, &rx_status);
@@ -7623,6 +7623,13 @@ brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
        skb_pull(p, D11_PHY_HDR_LEN);
        __skb_trim(p, len_mpdu);
 
+       /* unmute transmit */
+       if (wlc->hw->suspended_fifos) {
+               hdr = (struct ieee80211_hdr *)p->data;
+               if (ieee80211_is_beacon(hdr->frame_control))
+                       brcms_b_mute(wlc->hw, false);
+       }
+
        memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
        ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
 }

diff --git a/drivers/net/wireless/ipw2x00/ipw2200.c b/drivers/net/wireless/ipw2x00/ipw2200.c
index 2b02257..1779db3 100644 (file)
--- a/drivers/net/wireless/ipw2x00/ipw2200.c
+++ b/drivers/net/wireless/ipw2x00/ipw2200.c
@@ -2191,6 +2191,7 @@ static int __ipw_send_cmd(struct ipw_priv *priv, struct host_cmd *cmd)
 {
        int rc = 0;
        unsigned long flags;
+       unsigned long now, end;
 
        spin_lock_irqsave(&priv->lock, flags);
        if (priv->status & STATUS_HCMD_ACTIVE) {
@@ -2232,10 +2233,20 @@ static int __ipw_send_cmd(struct ipw_priv *priv, struct host_cmd *cmd)
        }
        spin_unlock_irqrestore(&priv->lock, flags);
 
+       now = jiffies;
+       end = now + HOST_COMPLETE_TIMEOUT;
+again:
        rc = wait_event_interruptible_timeout(priv->wait_command_queue,
                                              !(priv->
                                                status & STATUS_HCMD_ACTIVE),
-                                             HOST_COMPLETE_TIMEOUT);
+                                             end - now);
+       if (rc < 0) {
+               now = jiffies;
+               if (time_before(now, end))
+                       goto again;
+               rc = 0;
+       }
+
        if (rc == 0) {
                spin_lock_irqsave(&priv->lock, flags);
                if (priv->status & STATUS_HCMD_ACTIVE) {

diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c
index 5b0d888..8d80e23 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-1000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-1000.c
@@ -46,8 +46,8 @@
 #include "iwl-prph.h"
 
 /* Highest firmware API version supported */
-#define IWL1000_UCODE_API_MAX 6
-#define IWL100_UCODE_API_MAX 6
+#define IWL1000_UCODE_API_MAX 5
+#define IWL100_UCODE_API_MAX 5
 
 /* Oldest version we won't warn about */
 #define IWL1000_UCODE_API_OK 5
@@ -226,5 +226,5 @@ const struct iwl_cfg iwl100_bg_cfg = {
        IWL_DEVICE_100,
 };
 
-MODULE_FIRMWARE(IWL1000_MODULE_FIRMWARE(IWL1000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL100_MODULE_FIRMWARE(IWL100_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL1000_MODULE_FIRMWARE(IWL1000_UCODE_API_OK));
+MODULE_FIRMWARE(IWL100_MODULE_FIRMWARE(IWL100_UCODE_API_OK));

diff --git a/drivers/net/wireless/iwlwifi/iwl-2000.c b/drivers/net/wireless/iwlwifi/iwl-2000.c
index 5635b9e..ea10862 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-2000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-2000.c
@@ -51,10 +51,10 @@
 #define IWL135_UCODE_API_MAX 6
 
 /* Oldest version we won't warn about */
-#define IWL2030_UCODE_API_OK 5
-#define IWL2000_UCODE_API_OK 5
-#define IWL105_UCODE_API_OK 5
-#define IWL135_UCODE_API_OK 5
+#define IWL2030_UCODE_API_OK 6
+#define IWL2000_UCODE_API_OK 6
+#define IWL105_UCODE_API_OK 6
+#define IWL135_UCODE_API_OK 6
 
 /* Lowest firmware API version supported */
 #define IWL2030_UCODE_API_MIN 5
@@ -328,7 +328,7 @@ const struct iwl_cfg iwl135_bgn_cfg = {
        .ht_params = &iwl2000_ht_params,
 };
 
-MODULE_FIRMWARE(IWL2000_MODULE_FIRMWARE(IWL2000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL2030_MODULE_FIRMWARE(IWL2030_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL105_MODULE_FIRMWARE(IWL105_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL135_MODULE_FIRMWARE(IWL135_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL2000_MODULE_FIRMWARE(IWL2000_UCODE_API_OK));
+MODULE_FIRMWARE(IWL2030_MODULE_FIRMWARE(IWL2030_UCODE_API_OK));
+MODULE_FIRMWARE(IWL105_MODULE_FIRMWARE(IWL105_UCODE_API_OK));
+MODULE_FIRMWARE(IWL135_MODULE_FIRMWARE(IWL135_UCODE_API_OK));

diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index a805e97..de0920c 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -51,6 +51,10 @@
 #define IWL5000_UCODE_API_MAX 5
 #define IWL5150_UCODE_API_MAX 2
 
+/* Oldest version we won't warn about */
+#define IWL5000_UCODE_API_OK 5
+#define IWL5150_UCODE_API_OK 2
+
 /* Lowest firmware API version supported */
 #define IWL5000_UCODE_API_MIN 1
 #define IWL5150_UCODE_API_MIN 1
@@ -326,6 +330,7 @@ static const struct iwl_ht_params iwl5000_ht_params = {
 #define IWL_DEVICE_5000                                                \
        .fw_name_pre = IWL5000_FW_PRE,                          \
        .ucode_api_max = IWL5000_UCODE_API_MAX,                 \
+       .ucode_api_ok = IWL5000_UCODE_API_OK,                   \
        .ucode_api_min = IWL5000_UCODE_API_MIN,                 \
        .max_inst_size = IWLAGN_RTC_INST_SIZE,                  \
        .max_data_size = IWLAGN_RTC_DATA_SIZE,                  \
@@ -371,6 +376,7 @@ const struct iwl_cfg iwl5350_agn_cfg = {
        .name = "Intel(R) WiMAX/WiFi Link 5350 AGN",
        .fw_name_pre = IWL5000_FW_PRE,
        .ucode_api_max = IWL5000_UCODE_API_MAX,
+       .ucode_api_ok = IWL5000_UCODE_API_OK,
        .ucode_api_min = IWL5000_UCODE_API_MIN,
        .max_inst_size = IWLAGN_RTC_INST_SIZE,
        .max_data_size = IWLAGN_RTC_DATA_SIZE,
@@ -386,6 +392,7 @@ const struct iwl_cfg iwl5350_agn_cfg = {
 #define IWL_DEVICE_5150                                                \
        .fw_name_pre = IWL5150_FW_PRE,                          \
        .ucode_api_max = IWL5150_UCODE_API_MAX,                 \
+       .ucode_api_ok = IWL5150_UCODE_API_OK,                   \
        .ucode_api_min = IWL5150_UCODE_API_MIN,                 \
        .max_inst_size = IWLAGN_RTC_INST_SIZE,                  \
        .max_data_size = IWLAGN_RTC_DATA_SIZE,                  \
@@ -409,5 +416,5 @@ const struct iwl_cfg iwl5150_abg_cfg = {
        IWL_DEVICE_5150,
 };
 
-MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_OK));
+MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_OK));

diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c
index 64060cd..f0c9150 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-6000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c
@@ -53,6 +53,8 @@
 /* Oldest version we won't warn about */
 #define IWL6000_UCODE_API_OK 4
 #define IWL6000G2_UCODE_API_OK 5
+#define IWL6050_UCODE_API_OK 5
+#define IWL6000G2B_UCODE_API_OK 6
 
 /* Lowest firmware API version supported */
 #define IWL6000_UCODE_API_MIN 4
@@ -388,7 +390,7 @@ const struct iwl_cfg iwl6005_2agn_mow2_cfg = {
 #define IWL_DEVICE_6030                                                \
        .fw_name_pre = IWL6030_FW_PRE,                          \
        .ucode_api_max = IWL6000G2_UCODE_API_MAX,               \
-       .ucode_api_ok = IWL6000G2_UCODE_API_OK,                 \
+       .ucode_api_ok = IWL6000G2B_UCODE_API_OK,                \
        .ucode_api_min = IWL6000G2_UCODE_API_MIN,               \
        .max_inst_size = IWL60_RTC_INST_SIZE,                   \
        .max_data_size = IWL60_RTC_DATA_SIZE,                   \
@@ -557,6 +559,6 @@ const struct iwl_cfg iwl6000_3agn_cfg = {
 };
 
 MODULE_FIRMWARE(IWL6000_MODULE_FIRMWARE(IWL6000_UCODE_API_OK));
-MODULE_FIRMWARE(IWL6050_MODULE_FIRMWARE(IWL6050_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL6005_MODULE_FIRMWARE(IWL6000G2_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL6030_MODULE_FIRMWARE(IWL6000G2_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL6050_MODULE_FIRMWARE(IWL6050_UCODE_API_OK));
+MODULE_FIRMWARE(IWL6005_MODULE_FIRMWARE(IWL6000G2_UCODE_API_OK));
+MODULE_FIRMWARE(IWL6030_MODULE_FIRMWARE(IWL6000G2B_UCODE_API_OK));

diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index f1226db..2a9a16f 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -863,7 +863,6 @@ static void iwl_bg_run_time_calib_work(struct work_struct *work)
 
 void iwlagn_prepare_restart(struct iwl_priv *priv)
 {
-       struct iwl_rxon_context *ctx;
        bool bt_full_concurrent;
        u8 bt_ci_compliance;
        u8 bt_load;
@@ -872,8 +871,6 @@ void iwlagn_prepare_restart(struct iwl_priv *priv)
 
        lockdep_assert_held(&priv->mutex);
 
-       for_each_context(priv, ctx)
-               ctx->vif = NULL;
        priv->is_open = 0;
 
        /*

diff --git a/drivers/net/wireless/iwlwifi/iwl-fh.h b/drivers/net/wireless/iwlwifi/iwl-fh.h
index 9020809..74bce97 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-fh.h
+++ b/drivers/net/wireless/iwlwifi/iwl-fh.h
@@ -104,15 +104,29 @@
  * (see struct iwl_tfd_frame).  These 16 pointer registers are offset by 0x04
  * bytes from one another.  Each TFD circular buffer in DRAM must be 256-byte
  * aligned (address bits 0-7 must be 0).
+ * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
+ * for them are in different places.
  *
  * Bit fields in each pointer register:
  *  27-0: TFD CB physical base address [35:8], must be 256-byte aligned
  */
-#define FH_MEM_CBBC_LOWER_BOUND          (FH_MEM_LOWER_BOUND + 0x9D0)
-#define FH_MEM_CBBC_UPPER_BOUND          (FH_MEM_LOWER_BOUND + 0xA10)
-
-/* Find TFD CB base pointer for given queue (range 0-15). */
-#define FH_MEM_CBBC_QUEUE(x)  (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
+#define FH_MEM_CBBC_0_15_LOWER_BOUND           (FH_MEM_LOWER_BOUND + 0x9D0)
+#define FH_MEM_CBBC_0_15_UPPER_BOUND           (FH_MEM_LOWER_BOUND + 0xA10)
+#define FH_MEM_CBBC_16_19_LOWER_BOUND          (FH_MEM_LOWER_BOUND + 0xBF0)
+#define FH_MEM_CBBC_16_19_UPPER_BOUND          (FH_MEM_LOWER_BOUND + 0xC00)
+#define FH_MEM_CBBC_20_31_LOWER_BOUND          (FH_MEM_LOWER_BOUND + 0xB20)
+#define FH_MEM_CBBC_20_31_UPPER_BOUND          (FH_MEM_LOWER_BOUND + 0xB80)
+
+/* Find TFD CB base pointer for given queue */
+static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl)
+{
+       if (chnl < 16)
+               return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
+       if (chnl < 20)
+               return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
+       WARN_ON_ONCE(chnl >= 32);
+       return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
+}
 
 
 /**

diff --git a/drivers/net/wireless/iwlwifi/iwl-mac80211.c b/drivers/net/wireless/iwlwifi/iwl-mac80211.c
index b6805f8..c24a713 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-mac80211.c
+++ b/drivers/net/wireless/iwlwifi/iwl-mac80211.c
@@ -1244,6 +1244,7 @@ static int iwlagn_mac_add_interface(struct ieee80211_hw *hw,
        struct iwl_rxon_context *tmp, *ctx = NULL;
        int err;
        enum nl80211_iftype viftype = ieee80211_vif_type_p2p(vif);
+       bool reset = false;
 
        IWL_DEBUG_MAC80211(priv, "enter: type %d, addr %pM\n",
                           viftype, vif->addr);
@@ -1265,6 +1266,13 @@ static int iwlagn_mac_add_interface(struct ieee80211_hw *hw,
                        tmp->interface_modes | tmp->exclusive_interface_modes;
 
                if (tmp->vif) {
+                       /* On reset we need to add the same interface again */
+                       if (tmp->vif == vif) {
+                               reset = true;
+                               ctx = tmp;
+                               break;
+                       }
+
                        /* check if this busy context is exclusive */
                        if (tmp->exclusive_interface_modes &
                                                BIT(tmp->vif->type)) {
@@ -1291,7 +1299,7 @@ static int iwlagn_mac_add_interface(struct ieee80211_hw *hw,
        ctx->vif = vif;
 
        err = iwl_setup_interface(priv, ctx);
-       if (!err)
+       if (!err || reset)
                goto out;
 
        ctx->vif = NULL;

diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index 75dc20b..3b10692 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -223,12 +223,33 @@
 #define SCD_AIT                        (SCD_BASE + 0x0c)
 #define SCD_TXFACT             (SCD_BASE + 0x10)
 #define SCD_ACTIVE             (SCD_BASE + 0x14)
-#define SCD_QUEUE_WRPTR(x)     (SCD_BASE + 0x18 + (x) * 4)
-#define SCD_QUEUE_RDPTR(x)     (SCD_BASE + 0x68 + (x) * 4)
 #define SCD_QUEUECHAIN_SEL     (SCD_BASE + 0xe8)
 #define SCD_AGGR_SEL           (SCD_BASE + 0x248)
 #define SCD_INTERRUPT_MASK     (SCD_BASE + 0x108)
-#define SCD_QUEUE_STATUS_BITS(x)       (SCD_BASE + 0x10c + (x) * 4)
+
+static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
+{
+       if (chnl < 20)
+               return SCD_BASE + 0x18 + chnl * 4;
+       WARN_ON_ONCE(chnl >= 32);
+       return SCD_BASE + 0x284 + (chnl - 20) * 4;
+}
+
+static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl)
+{
+       if (chnl < 20)
+               return SCD_BASE + 0x68 + chnl * 4;
+       WARN_ON_ONCE(chnl >= 32);
+       return SCD_BASE + 0x2B4 + (chnl - 20) * 4;
+}
+
+static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
+{
+       if (chnl < 20)
+               return SCD_BASE + 0x10c + chnl * 4;
+       WARN_ON_ONCE(chnl >= 32);
+       return SCD_BASE + 0x384 + (chnl - 20) * 4;
+}
 
 /*********************** END TX SCHEDULER *************************************/
 

diff --git a/drivers/net/wireless/libertas/cfg.c b/drivers/net/wireless/libertas/cfg.c
index 3fa1ece..2fa879b 100644 (file)
--- a/drivers/net/wireless/libertas/cfg.c
+++ b/drivers/net/wireless/libertas/cfg.c
@@ -103,7 +103,7 @@ static const u32 cipher_suites[] = {
  * Convert NL80211's auth_type to the one from Libertas, see chapter 5.9.1
  * in the firmware spec
  */
-static u8 lbs_auth_to_authtype(enum nl80211_auth_type auth_type)
+static int lbs_auth_to_authtype(enum nl80211_auth_type auth_type)
 {
        int ret = -ENOTSUPP;
 
@@ -1411,7 +1411,12 @@ static int lbs_cfg_connect(struct wiphy *wiphy, struct net_device *dev,
                goto done;
        }
 
-       lbs_set_authtype(priv, sme);
+       ret = lbs_set_authtype(priv, sme);
+       if (ret == -ENOTSUPP) {
+               wiphy_err(wiphy, "unsupported authtype 0x%x\n", sme->auth_type);
+               goto done;
+       }
+
        lbs_set_radio(priv, preamble, 1);
 
        /* Do the actual association */

diff --git a/drivers/net/wireless/mwifiex/pcie.h b/drivers/net/wireless/mwifiex/pcie.h
index 445ff21..2f218f9 100644 (file)
--- a/drivers/net/wireless/mwifiex/pcie.h
+++ b/drivers/net/wireless/mwifiex/pcie.h
@@ -48,15 +48,15 @@
 #define PCIE_HOST_INT_STATUS_MASK                      0xC3C
 #define PCIE_SCRATCH_2_REG                             0xC40
 #define PCIE_SCRATCH_3_REG                             0xC44
-#define PCIE_SCRATCH_4_REG                             0xCC0
-#define PCIE_SCRATCH_5_REG                             0xCC4
-#define PCIE_SCRATCH_6_REG                             0xCC8
-#define PCIE_SCRATCH_7_REG                             0xCCC
-#define PCIE_SCRATCH_8_REG                             0xCD0
-#define PCIE_SCRATCH_9_REG                             0xCD4
-#define PCIE_SCRATCH_10_REG                            0xCD8
-#define PCIE_SCRATCH_11_REG                            0xCDC
-#define PCIE_SCRATCH_12_REG                            0xCE0
+#define PCIE_SCRATCH_4_REG                             0xCD0
+#define PCIE_SCRATCH_5_REG                             0xCD4
+#define PCIE_SCRATCH_6_REG                             0xCD8
+#define PCIE_SCRATCH_7_REG                             0xCDC
+#define PCIE_SCRATCH_8_REG                             0xCE0
+#define PCIE_SCRATCH_9_REG                             0xCE4
+#define PCIE_SCRATCH_10_REG                            0xCE8
+#define PCIE_SCRATCH_11_REG                            0xCEC
+#define PCIE_SCRATCH_12_REG                            0xCF0
 
 #define CPU_INTR_DNLD_RDY                              BIT(0)
 #define CPU_INTR_DOOR_BELL                             BIT(1)

diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 288b035..cc15fdb 100644 (file)
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -1941,6 +1941,7 @@ void rtl_pci_disconnect(struct pci_dev *pdev)
                rtl_deinit_deferred_work(hw);
                rtlpriv->intf_ops->adapter_stop(hw);
        }
+       rtlpriv->cfg->ops->disable_interrupt(hw);
 
        /*deinit rfkill */
        rtl_deinit_rfkill(hw);

diff --git a/drivers/net/wireless/wl1251/main.c b/drivers/net/wireless/wl1251/main.c
index 41302c7..d1afb8e 100644 (file)
--- a/drivers/net/wireless/wl1251/main.c
+++ b/drivers/net/wireless/wl1251/main.c
@@ -479,6 +479,7 @@ static void wl1251_op_stop(struct ieee80211_hw *hw)
        cancel_work_sync(&wl->irq_work);
        cancel_work_sync(&wl->tx_work);
        cancel_work_sync(&wl->filter_work);
+       cancel_delayed_work_sync(&wl->elp_work);
 
        mutex_lock(&wl->mutex);
 

diff --git a/drivers/net/wireless/wl1251/sdio.c b/drivers/net/wireless/wl1251/sdio.c
index f786942..1b851f6 100644 (file)
--- a/drivers/net/wireless/wl1251/sdio.c
+++ b/drivers/net/wireless/wl1251/sdio.c
@@ -315,8 +315,8 @@ static void __devexit wl1251_sdio_remove(struct sdio_func *func)
 
        if (wl->irq)
                free_irq(wl->irq, wl);
-       kfree(wl_sdio);
        wl1251_free_hw(wl);
+       kfree(wl_sdio);
 
        sdio_claim_host(func);
        sdio_release_irq(func);

diff --git a/drivers/of/address.c b/drivers/of/address.c
index 66d96f1..7e262a6 100644 (file)
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -1,4 +1,5 @@
 
+#include <linux/device.h>
 #include <linux/io.h>
 #include <linux/ioport.h>
 #include <linux/module.h>

diff --git a/drivers/of/base.c b/drivers/of/base.c
index 5806449..d9bfd49 100644 (file)
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1260,3 +1260,44 @@ int of_alias_get_id(struct device_node *np, const char *stem)
        return id;
 }
 EXPORT_SYMBOL_GPL(of_alias_get_id);
+
+const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
+                              u32 *pu)
+{
+       const void *curv = cur;
+
+       if (!prop)
+               return NULL;
+
+       if (!cur) {
+               curv = prop->value;
+               goto out_val;
+       }
+
+       curv += sizeof(*cur);
+       if (curv >= prop->value + prop->length)
+               return NULL;
+
+out_val:
+       *pu = be32_to_cpup(curv);
+       return curv;
+}
+EXPORT_SYMBOL_GPL(of_prop_next_u32);
+
+const char *of_prop_next_string(struct property *prop, const char *cur)
+{
+       const void *curv = cur;
+
+       if (!prop)
+               return NULL;
+
+       if (!cur)
+               return prop->value;
+
+       curv += strlen(cur) + 1;
+       if (curv >= prop->value + prop->length)
+               return NULL;
+
+       return curv;
+}
+EXPORT_SYMBOL_GPL(of_prop_next_string);

diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 083a49f..165274c 100644 (file)
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_UNICORE32) += setup-bus.o setup-irq.o
 obj-$(CONFIG_PARISC) += setup-bus.o
 obj-$(CONFIG_SUPERH) += setup-bus.o setup-irq.o
 obj-$(CONFIG_PPC) += setup-bus.o
+obj-$(CONFIG_FRV) += setup-bus.o
 obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
 obj-$(CONFIG_X86_VISWS) += setup-irq.o
 obj-$(CONFIG_MN10300) += setup-bus.o

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 0f150f2..1929c0c 100644 (file)
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -200,7 +200,7 @@ static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
                return PCI_D1;
        case ACPI_STATE_D2:
                return PCI_D2;
-       case ACPI_STATE_D3:
+       case ACPI_STATE_D3_HOT:
                return PCI_D3hot;
        case ACPI_STATE_D3_COLD:
                return PCI_D3cold;
@@ -223,7 +223,7 @@ static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
                [PCI_D0] = ACPI_STATE_D0,
                [PCI_D1] = ACPI_STATE_D1,
                [PCI_D2] = ACPI_STATE_D2,
-               [PCI_D3hot] = ACPI_STATE_D3,
+               [PCI_D3hot] = ACPI_STATE_D3_HOT,
                [PCI_D3cold] = ACPI_STATE_D3
        };
        int error = -EINVAL;

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index abfb964..a54a931 100644 (file)
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -4,7 +4,6 @@
 
 config PINCTRL
        bool
-       depends on EXPERIMENTAL
 
 if PINCTRL
 
@@ -27,6 +26,19 @@ config DEBUG_PINCTRL
        help
          Say Y here to add some extra checks and diagnostics to PINCTRL calls.
 
+config PINCTRL_IMX
+       bool
+       select PINMUX
+       select PINCONF
+
+config PINCTRL_IMX6Q
+       bool "IMX6Q pinctrl driver"
+       depends on OF
+       depends on SOC_IMX6Q
+       select PINCTRL_IMX
+       help
+         Say Y here to enable the imx6q pinctrl driver
+
 config PINCTRL_PXA3xx
        bool
        select PINMUX
@@ -37,6 +49,21 @@ config PINCTRL_MMP2
        select PINCTRL_PXA3xx
        select PINCONF
 
+config PINCTRL_MXS
+       bool
+
+config PINCTRL_IMX23
+       bool
+       select PINMUX
+       select PINCONF
+       select PINCTRL_MXS
+
+config PINCTRL_IMX28
+       bool
+       select PINMUX
+       select PINCONF
+       select PINCTRL_MXS
+
 config PINCTRL_PXA168
        bool "PXA168 pin controller driver"
        depends on ARCH_MMP
@@ -84,6 +111,8 @@ config PINCTRL_COH901
          COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
          ports of 8 GPIO pins each.
 
+source "drivers/pinctrl/spear/Kconfig"
+
 endmenu
 
 endif

diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6d4150b..c9b0be5 100644 (file)
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,9 +5,17 @@ ccflags-$(CONFIG_DEBUG_PINCTRL)        += -DDEBUG
 obj-$(CONFIG_PINCTRL)          += core.o
 obj-$(CONFIG_PINMUX)           += pinmux.o
 obj-$(CONFIG_PINCONF)          += pinconf.o
+ifeq ($(CONFIG_OF),y)
+obj-$(CONFIG_PINCTRL)          += devicetree.o
+endif
 obj-$(CONFIG_GENERIC_PINCONF)  += pinconf-generic.o
+obj-$(CONFIG_PINCTRL_IMX)      += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX6Q)    += pinctrl-imx6q.o
 obj-$(CONFIG_PINCTRL_PXA3xx)   += pinctrl-pxa3xx.o
 obj-$(CONFIG_PINCTRL_MMP2)     += pinctrl-mmp2.o
+obj-$(CONFIG_PINCTRL_MXS)      += pinctrl-mxs.o
+obj-$(CONFIG_PINCTRL_IMX23)    += pinctrl-imx23.o
+obj-$(CONFIG_PINCTRL_IMX28)    += pinctrl-imx28.o
 obj-$(CONFIG_PINCTRL_PXA168)   += pinctrl-pxa168.o
 obj-$(CONFIG_PINCTRL_PXA910)   += pinctrl-pxa910.o
 obj-$(CONFIG_PINCTRL_SIRF)     += pinctrl-sirf.o
@@ -16,3 +24,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)  += pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)     += pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)   += pinctrl-coh901.o
+
+obj-$(CONFIG_PLAT_SPEAR)       += spear/

diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index df6296c..c3b331b 100644 (file)
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -23,9 +23,11 @@
 #include <linux/sysfs.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/machine.h>
 #include "core.h"
+#include "devicetree.h"
 #include "pinmux.h"
 #include "pinconf.h"
 
@@ -41,11 +43,13 @@ struct pinctrl_maps {
        unsigned num_maps;
 };
 
+static bool pinctrl_dummy_state;
+
 /* Mutex taken by all entry points */
 DEFINE_MUTEX(pinctrl_mutex);
 
 /* Global list of pin control devices (struct pinctrl_dev) */
-static LIST_HEAD(pinctrldev_list);
+LIST_HEAD(pinctrldev_list);
 
 /* List of pin controller handles (struct pinctrl) */
 static LIST_HEAD(pinctrl_list);
@@ -59,6 +63,19 @@ static LIST_HEAD(pinctrl_maps);
                        _i_ < _maps_node_->num_maps; \
                        i++, _map_ = &_maps_node_->maps[_i_])
 
+/**
+ * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
+ *
+ * Usually this function is called by platforms without pinctrl driver support
+ * but run with some shared drivers using pinctrl APIs.
+ * After calling this function, the pinctrl core will return successfully
+ * with creating a dummy state for the driver to keep going smoothly.
+ */
+void pinctrl_provide_dummies(void)
+{
+       pinctrl_dummy_state = true;
+}
+
 const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
 {
        /* We're not allowed to register devices without name */
@@ -124,6 +141,25 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
 }
 
 /**
+ * pin_get_name_from_id() - look up a pin name from a pin id
+ * @pctldev: the pin control device to lookup the pin on
+ * @name: the name of the pin to look up
+ */
+const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
+{
+       const struct pin_desc *desc;
+
+       desc = pin_desc_get(pctldev, pin);
+       if (desc == NULL) {
+               dev_err(pctldev->dev, "failed to get pin(%d) name\n",
+                       pin);
+               return NULL;
+       }
+
+       return desc->name;
+}
+
+/**
  * pin_is_valid() - check if pin exists on controller
  * @pctldev: the pin control device to check the pin on
  * @pin: pin to check, use the local pin controller index number
@@ -255,7 +291,8 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
  *
  * Find the pin controller handling a certain GPIO pin from the pinspace of
  * the GPIO subsystem, return the device and the matching GPIO range. Returns
- * negative if the GPIO range could not be found in any device.
+ * -EPROBE_DEFER if the GPIO range could not be found in any device since it
+ * may still have not been registered.
  */
 static int pinctrl_get_device_gpio_range(unsigned gpio,
                                         struct pinctrl_dev **outdev,
@@ -275,7 +312,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
                }
        }
 
-       return -EINVAL;
+       return -EPROBE_DEFER;
 }
 
 /**
@@ -318,9 +355,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
                               const char *pin_group)
 {
        const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+       unsigned ngroups = pctlops->get_groups_count(pctldev);
        unsigned group_selector = 0;
 
-       while (pctlops->list_groups(pctldev, group_selector) >= 0) {
+       while (group_selector < ngroups) {
                const char *gname = pctlops->get_group_name(pctldev,
                                                            group_selector);
                if (!strcmp(gname, pin_group)) {
@@ -360,7 +398,7 @@ int pinctrl_request_gpio(unsigned gpio)
        ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
        if (ret) {
                mutex_unlock(&pinctrl_mutex);
-               return -EINVAL;
+               return ret;
        }
 
        /* Convert to the pin controllers number space */
@@ -516,11 +554,14 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
 
        setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
        if (setting->pctldev == NULL) {
-               dev_err(p->dev, "unknown pinctrl device %s in map entry",
+               dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
                        map->ctrl_dev_name);
                kfree(setting);
-               /* Eventually, this should trigger deferred probe */
-               return -ENODEV;
+               /*
+                * OK let us guess that the driver is not there yet, and
+                * let's defer obtaining this pinctrl handle to later...
+                */
+               return -EPROBE_DEFER;
        }
 
        switch (map->type) {
@@ -579,6 +620,13 @@ static struct pinctrl *create_pinctrl(struct device *dev)
        }
        p->dev = dev;
        INIT_LIST_HEAD(&p->states);
+       INIT_LIST_HEAD(&p->dt_maps);
+
+       ret = pinctrl_dt_to_map(p);
+       if (ret < 0) {
+               kfree(p);
+               return ERR_PTR(ret);
+       }
 
        devname = dev_name(dev);
 
@@ -662,6 +710,8 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
                kfree(state);
        }
 
+       pinctrl_dt_free_maps(p);
+
        if (inlist)
                list_del(&p->node);
        kfree(p);
@@ -685,8 +735,18 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p,
        struct pinctrl_state *state;
 
        state = find_state(p, name);
-       if (!state)
-               return ERR_PTR(-ENODEV);
+       if (!state) {
+               if (pinctrl_dummy_state) {
+                       /* create dummy state */
+                       dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
+                               name);
+                       state = create_state(p, name);
+                       if (IS_ERR(state))
+                               return state;
+               } else {
+                       return ERR_PTR(-ENODEV);
+               }
+       }
 
        return state;
 }
@@ -787,15 +847,63 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
 }
 EXPORT_SYMBOL_GPL(pinctrl_select_state);
 
+static void devm_pinctrl_release(struct device *dev, void *res)
+{
+       pinctrl_put(*(struct pinctrl **)res);
+}
+
 /**
- * pinctrl_register_mappings() - register a set of pin controller mappings
- * @maps: the pincontrol mappings table to register. This should probably be
- *     marked with __initdata so it can be discarded after boot. This
- *     function will perform a shallow copy for the mapping entries.
- * @num_maps: the number of maps in the mapping table
+ * struct devm_pinctrl_get() - Resource managed pinctrl_get()
+ * @dev: the device to obtain the handle for
+ *
+ * If there is a need to explicitly destroy the returned struct pinctrl,
+ * devm_pinctrl_put() should be used, rather than plain pinctrl_put().
  */
-int pinctrl_register_mappings(struct pinctrl_map const *maps,
-                             unsigned num_maps)
+struct pinctrl *devm_pinctrl_get(struct device *dev)
+{
+       struct pinctrl **ptr, *p;
+
+       ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
+       if (!ptr)
+               return ERR_PTR(-ENOMEM);
+
+       p = pinctrl_get(dev);
+       if (!IS_ERR(p)) {
+               *ptr = p;
+               devres_add(dev, ptr);
+       } else {
+               devres_free(ptr);
+       }
+
+       return p;
+}
+EXPORT_SYMBOL_GPL(devm_pinctrl_get);
+
+static int devm_pinctrl_match(struct device *dev, void *res, void *data)
+{
+       struct pinctrl **p = res;
+
+       return *p == data;
+}
+
+/**
+ * devm_pinctrl_put() - Resource managed pinctrl_put()
+ * @p: the pinctrl handle to release
+ *
+ * Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
+ * this function will not need to be called and the resource management
+ * code will ensure that the resource is freed.
+ */
+void devm_pinctrl_put(struct pinctrl *p)
+{
+       WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
+                              devm_pinctrl_match, p));
+       pinctrl_put(p);
+}
+EXPORT_SYMBOL_GPL(devm_pinctrl_put);
+
+int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
+                        bool dup, bool locked)
 {
        int i, ret;
        struct pinctrl_maps *maps_node;
@@ -829,13 +937,13 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
                case PIN_MAP_TYPE_MUX_GROUP:
                        ret = pinmux_validate_map(&maps[i], i);
                        if (ret < 0)
-                               return 0;
+                               return ret;
                        break;
                case PIN_MAP_TYPE_CONFIGS_PIN:
                case PIN_MAP_TYPE_CONFIGS_GROUP:
                        ret = pinconf_validate_map(&maps[i], i);
                        if (ret < 0)
-                               return 0;
+                               return ret;
                        break;
                default:
                        pr_err("failed to register map %s (%d): invalid type given\n",
@@ -851,20 +959,52 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
        }
 
        maps_node->num_maps = num_maps;
-       maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL);
-       if (!maps_node->maps) {
-               pr_err("failed to duplicate mapping table\n");
-               kfree(maps_node);
-               return -ENOMEM;
+       if (dup) {
+               maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
+                                         GFP_KERNEL);
+               if (!maps_node->maps) {
+                       pr_err("failed to duplicate mapping table\n");
+                       kfree(maps_node);
+                       return -ENOMEM;
+               }
+       } else {
+               maps_node->maps = maps;
        }
 
-       mutex_lock(&pinctrl_mutex);
+       if (!locked)
+               mutex_lock(&pinctrl_mutex);
        list_add_tail(&maps_node->node, &pinctrl_maps);
-       mutex_unlock(&pinctrl_mutex);
+       if (!locked)
+               mutex_unlock(&pinctrl_mutex);
 
        return 0;
 }
 
+/**
+ * pinctrl_register_mappings() - register a set of pin controller mappings
+ * @maps: the pincontrol mappings table to register. This should probably be
+ *     marked with __initdata so it can be discarded after boot. This
+ *     function will perform a shallow copy for the mapping entries.
+ * @num_maps: the number of maps in the mapping table
+ */
+int pinctrl_register_mappings(struct pinctrl_map const *maps,
+                             unsigned num_maps)
+{
+       return pinctrl_register_map(maps, num_maps, true, false);
+}
+
+void pinctrl_unregister_map(struct pinctrl_map const *map)
+{
+       struct pinctrl_maps *maps_node;
+
+       list_for_each_entry(maps_node, &pinctrl_maps, node) {
+               if (maps_node->maps == map) {
+                       list_del(&maps_node->node);
+                       return;
+               }
+       }
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -906,15 +1046,17 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
 {
        struct pinctrl_dev *pctldev = s->private;
        const struct pinctrl_ops *ops = pctldev->desc->pctlops;
-       unsigned selector = 0;
+       unsigned ngroups, selector = 0;
 
+       ngroups = ops->get_groups_count(pctldev);
        mutex_lock(&pinctrl_mutex);
 
        seq_puts(s, "registered pin groups:\n");
-       while (ops->list_groups(pctldev, selector) >= 0) {
+       while (selector < ngroups) {
                const unsigned *pins;
                unsigned num_pins;
                const char *gname = ops->get_group_name(pctldev, selector);
+               const char *pname;
                int ret;
                int i;
 
@@ -924,10 +1066,14 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
                        seq_printf(s, "%s [ERROR GETTING PINS]\n",
                                   gname);
                else {
-                       seq_printf(s, "group: %s, pins = [ ", gname);
-                       for (i = 0; i < num_pins; i++)
-                               seq_printf(s, "%d ", pins[i]);
-                       seq_puts(s, "]\n");
+                       seq_printf(s, "group: %s\n", gname);
+                       for (i = 0; i < num_pins; i++) {
+                               pname = pin_get_name(pctldev, pins[i]);
+                               if (WARN_ON(!pname))
+                                       return -EINVAL;
+                               seq_printf(s, "pin %d (%s)\n", pins[i], pname);
+                       }
+                       seq_puts(s, "\n");
                }
                selector++;
        }
@@ -1226,11 +1372,14 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
        const struct pinctrl_ops *ops = pctldev->desc->pctlops;
 
        if (!ops ||
-           !ops->list_groups ||
+           !ops->get_groups_count ||
            !ops->get_group_name ||
            !ops->get_group_pins)
                return -EINVAL;
 
+       if (ops->dt_node_to_map && !ops->dt_free_map)
+               return -EINVAL;
+
        return 0;
 }
 
@@ -1268,37 +1417,29 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
        /* check core ops for sanity */
        ret = pinctrl_check_ops(pctldev);
        if (ret) {
-               pr_err("%s pinctrl ops lacks necessary functions\n",
-                       pctldesc->name);
+               dev_err(dev, "pinctrl ops lacks necessary functions\n");
                goto out_err;
        }
 
        /* If we're implementing pinmuxing, check the ops for sanity */
        if (pctldesc->pmxops) {
                ret = pinmux_check_ops(pctldev);
-               if (ret) {
-                       pr_err("%s pinmux ops lacks necessary functions\n",
-                              pctldesc->name);
+               if (ret)
                        goto out_err;
-               }
        }
 
        /* If we're implementing pinconfig, check the ops for sanity */
        if (pctldesc->confops) {
                ret = pinconf_check_ops(pctldev);
-               if (ret) {
-                       pr_err("%s pin config ops lacks necessary functions\n",
-                              pctldesc->name);
+               if (ret)
                        goto out_err;
-               }
        }
 
        /* Register all the pins */
-       pr_debug("try to register %d pins on %s...\n",
-                pctldesc->npins, pctldesc->name);
+       dev_dbg(dev, "try to register %d pins ...\n",  pctldesc->npins);
        ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
        if (ret) {
-               pr_err("error during pin registration\n");
+               dev_err(dev, "error during pin registration\n");
                pinctrl_free_pindescs(pctldev, pctldesc->pins,
                                      pctldesc->npins);
                goto out_err;
@@ -1313,8 +1454,15 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
                struct pinctrl_state *s =
                        pinctrl_lookup_state_locked(pctldev->p,
                                                    PINCTRL_STATE_DEFAULT);
-               if (!IS_ERR(s))
-                       pinctrl_select_state_locked(pctldev->p, s);
+               if (IS_ERR(s)) {
+                       dev_dbg(dev, "failed to lookup the default state\n");
+               } else {
+                       ret = pinctrl_select_state_locked(pctldev->p, s);
+                       if (ret) {
+                               dev_err(dev,
+                                       "failed to select default state\n");
+                       }
+               }
        }
 
        mutex_unlock(&pinctrl_mutex);

diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 17ecf65..1f40ff6 100644 (file)
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -52,12 +52,15 @@ struct pinctrl_dev {
  * @dev: the device using this pin control handle
  * @states: a list of states for this device
  * @state: the current state
+ * @dt_maps: the mapping table chunks dynamically parsed from device tree for
+ *     this device, if any
  */
 struct pinctrl {
        struct list_head node;
        struct device *dev;
        struct list_head states;
        struct pinctrl_state *state;
+       struct list_head dt_maps;
 };
 
 /**
@@ -100,7 +103,8 @@ struct pinctrl_setting_configs {
  * struct pinctrl_setting - an individual mux or config setting
  * @node: list node for struct pinctrl_settings's @settings field
  * @type: the type of setting
- * @pctldev: pin control device handling to be programmed
+ * @pctldev: pin control device handling to be programmed. Not used for
+ *   PIN_MAP_TYPE_DUMMY_STATE.
  * @data: Data specific to the setting type
  */
 struct pinctrl_setting {
@@ -144,6 +148,7 @@ struct pin_desc {
 
 struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
 int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
+const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
 int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
                               const char *pin_group);
 
@@ -153,4 +158,9 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
        return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
 }
 
+int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
+                        bool dup, bool locked);
+void pinctrl_unregister_map(struct pinctrl_map const *map);
+
 extern struct mutex pinctrl_mutex;
+extern struct list_head pinctrldev_list;

diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
new file mode 100644 (file)
index 0000000..fcb1de4
--- /dev/null
+++ b/drivers/pinctrl/devicetree.c
@@ -0,0 +1,249 @@
+/*
+ * Device tree integration for the pin control subsystem
+ *
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "devicetree.h"
+
+/**
+ * struct pinctrl_dt_map - mapping table chunk parsed from device tree
+ * @node: list node for struct pinctrl's @dt_maps field
+ * @pctldev: the pin controller that allocated this struct, and will free it
+ * @maps: the mapping table entries
+ */
+struct pinctrl_dt_map {
+       struct list_head node;
+       struct pinctrl_dev *pctldev;
+       struct pinctrl_map *map;
+       unsigned num_maps;
+};
+
+static void dt_free_map(struct pinctrl_dev *pctldev,
+                    struct pinctrl_map *map, unsigned num_maps)
+{
+       if (pctldev) {
+               struct pinctrl_ops *ops = pctldev->desc->pctlops;
+               ops->dt_free_map(pctldev, map, num_maps);
+       } else {
+               /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
+               kfree(map);
+       }
+}
+
+void pinctrl_dt_free_maps(struct pinctrl *p)
+{
+       struct pinctrl_dt_map *dt_map, *n1;
+
+       list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
+               pinctrl_unregister_map(dt_map->map);
+               list_del(&dt_map->node);
+               dt_free_map(dt_map->pctldev, dt_map->map,
+                           dt_map->num_maps);
+               kfree(dt_map);
+       }
+
+       of_node_put(p->dev->of_node);
+}
+
+static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
+                                  struct pinctrl_dev *pctldev,
+                                  struct pinctrl_map *map, unsigned num_maps)
+{
+       int i;
+       struct pinctrl_dt_map *dt_map;
+
+       /* Initialize common mapping table entry fields */
+       for (i = 0; i < num_maps; i++) {
+               map[i].dev_name = dev_name(p->dev);
+               map[i].name = statename;
+               if (pctldev)
+                       map[i].ctrl_dev_name = dev_name(pctldev->dev);
+       }
+
+       /* Remember the converted mapping table entries */
+       dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
+       if (!dt_map) {
+               dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
+               dt_free_map(pctldev, map, num_maps);
+               return -ENOMEM;
+       }
+
+       dt_map->pctldev = pctldev;
+       dt_map->map = map;
+       dt_map->num_maps = num_maps;
+       list_add_tail(&dt_map->node, &p->dt_maps);
+
+       return pinctrl_register_map(map, num_maps, false, true);
+}
+
+static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
+{
+       struct pinctrl_dev *pctldev;
+
+       list_for_each_entry(pctldev, &pinctrldev_list, node)
+               if (pctldev->dev->of_node == np)
+                       return pctldev;
+
+       return NULL;
+}
+
+static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
+                               struct device_node *np_config)
+{
+       struct device_node *np_pctldev;
+       struct pinctrl_dev *pctldev;
+       struct pinctrl_ops *ops;
+       int ret;
+       struct pinctrl_map *map;
+       unsigned num_maps;
+
+       /* Find the pin controller containing np_config */
+       np_pctldev = of_node_get(np_config);
+       for (;;) {
+               np_pctldev = of_get_next_parent(np_pctldev);
+               if (!np_pctldev || of_node_is_root(np_pctldev)) {
+                       dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
+                               np_config->full_name);
+                       of_node_put(np_pctldev);
+                       /* OK let's just assume this will appear later then */
+                       return -EPROBE_DEFER;
+               }
+               pctldev = find_pinctrl_by_of_node(np_pctldev);
+               if (pctldev)
+                       break;
+       }
+       of_node_put(np_pctldev);
+
+       /*
+        * Call pinctrl driver to parse device tree node, and
+        * generate mapping table entries
+        */
+       ops = pctldev->desc->pctlops;
+       if (!ops->dt_node_to_map) {
+               dev_err(p->dev, "pctldev %s doesn't support DT\n",
+                       dev_name(pctldev->dev));
+               return -ENODEV;
+       }
+       ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
+       if (ret < 0)
+               return ret;
+
+       /* Stash the mapping table chunk away for later use */
+       return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
+}
+
+static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
+{
+       struct pinctrl_map *map;
+
+       map = kzalloc(sizeof(*map), GFP_KERNEL);
+       if (!map) {
+               dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
+               return -ENOMEM;
+       }
+
+       /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
+       map->type = PIN_MAP_TYPE_DUMMY_STATE;
+
+       return dt_remember_or_free_map(p, statename, NULL, map, 1);
+}
+
+int pinctrl_dt_to_map(struct pinctrl *p)
+{
+       struct device_node *np = p->dev->of_node;
+       int state, ret;
+       char *propname;
+       struct property *prop;
+       const char *statename;
+       const __be32 *list;
+       int size, config;
+       phandle phandle;
+       struct device_node *np_config;
+
+       /* CONFIG_OF enabled, p->dev not instantiated from DT */
+       if (!np) {
+               dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
+               return 0;
+       }
+
+       /* We may store pointers to property names within the node */
+       of_node_get(np);
+
+       /* For each defined state ID */
+       for (state = 0; ; state++) {
+               /* Retrieve the pinctrl-* property */
+               propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
+               prop = of_find_property(np, propname, &size);
+               kfree(propname);
+               if (!prop)
+                       break;
+               list = prop->value;
+               size /= sizeof(*list);
+
+               /* Determine whether pinctrl-names property names the state */
+               ret = of_property_read_string_index(np, "pinctrl-names",
+                                                   state, &statename);
+               /*
+                * If not, statename is just the integer state ID. But rather
+                * than dynamically allocate it and have to free it later,
+                * just point part way into the property name for the string.
+                */
+               if (ret < 0) {
+                       /* strlen("pinctrl-") == 8 */
+                       statename = prop->name + 8;
+               }
+
+               /* For every referenced pin configuration node in it */
+               for (config = 0; config < size; config++) {
+                       phandle = be32_to_cpup(list++);
+
+                       /* Look up the pin configuration node */
+                       np_config = of_find_node_by_phandle(phandle);
+                       if (!np_config) {
+                               dev_err(p->dev,
+                                       "prop %s index %i invalid phandle\n",
+                                       prop->name, config);
+                               ret = -EINVAL;
+                               goto err;
+                       }
+
+                       /* Parse the node */
+                       ret = dt_to_map_one_config(p, statename, np_config);
+                       of_node_put(np_config);
+                       if (ret < 0)
+                               goto err;
+               }
+
+               /* No entries in DT? Generate a dummy state table entry */
+               if (!size) {
+                       ret = dt_remember_dummy_state(p, statename);
+                       if (ret < 0)
+                               goto err;
+               }
+       }
+
+       return 0;
+
+err:
+       pinctrl_dt_free_maps(p);
+       return ret;
+}

diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h
new file mode 100644 (file)
index 0000000..760bc49
--- /dev/null
+++ b/drivers/pinctrl/devicetree.h
@@ -0,0 +1,35 @@
+/*
+ * Internal interface to pinctrl device tree integration
+ *
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef CONFIG_OF
+
+void pinctrl_dt_free_maps(struct pinctrl *p);
+int pinctrl_dt_to_map(struct pinctrl *p);
+
+#else
+
+static inline int pinctrl_dt_to_map(struct pinctrl *p)
+{
+       return 0;
+}
+
+static inline void pinctrl_dt_free_maps(struct pinctrl *p)
+{
+}
+
+#endif

diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 7321e86..7ce139e 100644 (file)
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -28,11 +28,17 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
        const struct pinconf_ops *ops = pctldev->desc->confops;
 
        /* We must be able to read out pin status */
-       if (!ops->pin_config_get && !ops->pin_config_group_get)
+       if (!ops->pin_config_get && !ops->pin_config_group_get) {
+               dev_err(pctldev->dev,
+                       "pinconf must be able to read out pin status\n");
                return -EINVAL;
+       }
        /* We have to be able to config the pins in SOME way */
-       if (!ops->pin_config_set && !ops->pin_config_group_set)
+       if (!ops->pin_config_set && !ops->pin_config_group_set) {
+               dev_err(pctldev->dev,
+                       "pinconf has to be able to set a pins config\n");
                return -EINVAL;
+       }
        return 0;
 }
 
@@ -379,8 +385,16 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
 
 void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
 {
+       struct pinctrl_dev *pctldev;
+       const struct pinconf_ops *confops;
        int i;
 
+       pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
+       if (pctldev)
+               confops = pctldev->desc->confops;
+       else
+               confops = NULL;
+
        switch (map->type) {
        case PIN_MAP_TYPE_CONFIGS_PIN:
                seq_printf(s, "pin ");
@@ -394,8 +408,15 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
 
        seq_printf(s, "%s\n", map->data.configs.group_or_pin);
 
-       for (i = 0; i < map->data.configs.num_configs; i++)
-               seq_printf(s, "config %08lx\n", map->data.configs.configs[i]);
+       for (i = 0; i < map->data.configs.num_configs; i++) {
+               seq_printf(s, "config ");
+               if (confops && confops->pin_config_config_dbg_show)
+                       confops->pin_config_config_dbg_show(pctldev, s,
+                                               map->data.configs.configs[i]);
+               else
+                       seq_printf(s, "%08lx", map->data.configs.configs[i]);
+               seq_printf(s, "\n");
+       }
 }
 
 void pinconf_show_setting(struct seq_file *s,
@@ -403,6 +424,7 @@ void pinconf_show_setting(struct seq_file *s,
 {
        struct pinctrl_dev *pctldev = setting->pctldev;
        const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
+       const struct pinconf_ops *confops = pctldev->desc->confops;
        struct pin_desc *desc;
        int i;
 
@@ -428,8 +450,15 @@ void pinconf_show_setting(struct seq_file *s,
         * FIXME: We should really get the pin controler to dump the config
         * values, so they can be decoded to something meaningful.
         */
-       for (i = 0; i < setting->data.configs.num_configs; i++)
-               seq_printf(s, " %08lx", setting->data.configs.configs[i]);
+       for (i = 0; i < setting->data.configs.num_configs; i++) {
+               seq_printf(s, " ");
+               if (confops && confops->pin_config_config_dbg_show)
+                       confops->pin_config_config_dbg_show(pctldev, s,
+                               setting->data.configs.configs[i]);
+               else
+                       seq_printf(s, "%08lx",
+                                  setting->data.configs.configs[i]);
+       }
 
        seq_printf(s, "\n");
 }
@@ -448,10 +477,14 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
 static int pinconf_pins_show(struct seq_file *s, void *what)
 {
        struct pinctrl_dev *pctldev = s->private;
+       const struct pinconf_ops *ops = pctldev->desc->confops;
        unsigned i, pin;
 
+       if (!ops || !ops->pin_config_get)
+               return 0;
+
        seq_puts(s, "Pin config settings per pin\n");
-       seq_puts(s, "Format: pin (name): pinmux setting array\n");
+       seq_puts(s, "Format: pin (name): configs\n");
 
        mutex_lock(&pinctrl_mutex);
 
@@ -495,17 +528,18 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
        struct pinctrl_dev *pctldev = s->private;
        const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
        const struct pinconf_ops *ops = pctldev->desc->confops;
+       unsigned ngroups = pctlops->get_groups_count(pctldev);
        unsigned selector = 0;
 
        if (!ops || !ops->pin_config_group_get)
                return 0;
 
        seq_puts(s, "Pin config settings per pin group\n");
-       seq_puts(s, "Format: group (name): pinmux setting array\n");
+       seq_puts(s, "Format: group (name): configs\n");
 
        mutex_lock(&pinctrl_mutex);
 
-       while (pctlops->list_groups(pctldev, selector) >= 0) {
+       while (selector < ngroups) {
                const char *gname = pctlops->get_group_name(pctldev, selector);
 
                seq_printf(s, "%u (%s):", selector, gname);

diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 54510de..e3ed8cb 100644 (file)
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -19,11 +19,6 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
                          struct pinctrl_setting *setting);
 void pinconf_free_setting(struct pinctrl_setting const *setting);
 int pinconf_apply_setting(struct pinctrl_setting const *setting);
-void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
-void pinconf_show_setting(struct seq_file *s,
-                         struct pinctrl_setting const *setting);
-void pinconf_init_device_debugfs(struct dentry *devroot,
-                                struct pinctrl_dev *pctldev);
 
 /*
  * You will only be interested in these if you're using PINCONF
@@ -61,6 +56,18 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
        return 0;
 }
 
+#endif
+
+#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
+
+void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
+void pinconf_show_setting(struct seq_file *s,
+                         struct pinctrl_setting const *setting);
+void pinconf_init_device_debugfs(struct dentry *devroot,
+                                struct pinctrl_dev *pctldev);
+
+#else
+
 static inline void pinconf_show_map(struct seq_file *s,
                                    struct pinctrl_map const *map)
 {

diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 0797eba..55697a5 100644 (file)
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -174,7 +174,7 @@ struct u300_gpio_confdata {
 
 
 /* Initial configuration */
-static const struct __initdata u300_gpio_confdata
+static const struct __initconst u300_gpio_confdata
 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
        /* Port 0, pins 0-7 */
        {
@@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
        }
 };
 
-static const struct __initdata u300_gpio_confdata
+static const struct __initconst u300_gpio_confdata
 bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
        /* Port 0, pins 0-7 */
        {

diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
new file mode 100644 (file)
index 0000000..8faf613
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -0,0 +1,627 @@
+/*
+ * Core driver for the imx pin controller
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+
+#include "core.h"
+#include "pinctrl-imx.h"
+
+#define IMX_PMX_DUMP(info, p, m, c, n)         \
+{                                              \
+       int i, j;                               \
+       printk("Format: Pin Mux Config\n");     \
+       for (i = 0; i < n; i++) {               \
+               j = p[i];                       \
+               printk("%s %d 0x%lx\n",         \
+                       info->pins[j].name,     \
+                       m[i], c[i]);            \
+       }                                       \
+}
+
+/* The bits in CONFIG cell defined in binding doc*/
+#define IMX_NO_PAD_CTL 0x80000000      /* no pin config need */
+#define IMX_PAD_SION 0x40000000                /* set SION */
+
+/**
+ * @dev: a pointer back to containing device
+ * @base: the offset to the controller in virtual memory
+ */
+struct imx_pinctrl {
+       struct device *dev;
+       struct pinctrl_dev *pctl;
+       void __iomem *base;
+       const struct imx_pinctrl_soc_info *info;
+};
+
+static const struct imx_pin_reg *imx_find_pin_reg(
+                               const struct imx_pinctrl_soc_info *info,
+                               unsigned pin, bool is_mux, unsigned mux)
+{
+       const struct imx_pin_reg *pin_reg = NULL;
+       int i;
+
+       for (i = 0; i < info->npin_regs; i++) {
+               pin_reg = &info->pin_regs[i];
+               if (pin_reg->pid != pin)
+                       continue;
+               if (!is_mux)
+                       break;
+               else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
+                       break;
+       }
+
+       if (!pin_reg) {
+               dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
+                       info->pins[pin].name);
+               return NULL;
+       }
+
+       return pin_reg;
+}
+
+static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
+                               const struct imx_pinctrl_soc_info *info,
+                               const char *name)
+{
+       const struct imx_pin_group *grp = NULL;
+       int i;
+
+       for (i = 0; i < info->ngroups; i++) {
+               if (!strcmp(info->groups[i].name, name)) {
+                       grp = &info->groups[i];
+                       break;
+               }
+       }
+
+       return grp;
+}
+
+static int imx_get_groups_count(struct pinctrl_dev *pctldev)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+       return info->ngroups;
+}
+
+static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
+                                      unsigned selector)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+       return info->groups[selector].name;
+}
+
+static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
+                              const unsigned **pins,
+                              unsigned *npins)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+       if (selector >= info->ngroups)
+               return -EINVAL;
+
+       *pins = info->groups[selector].pins;
+       *npins = info->groups[selector].npins;
+
+       return 0;
+}
+
+static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+                  unsigned offset)
+{
+       seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
+                       struct device_node *np,
+                       struct pinctrl_map **map, unsigned *num_maps)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+       const struct imx_pin_group *grp;
+       struct pinctrl_map *new_map;
+       struct device_node *parent;
+       int map_num = 1;
+       int i;
+
+       /*
+        * first find the group of this node and check if we need create
+        * config maps for pins
+        */
+       grp = imx_pinctrl_find_group_by_name(info, np->name);
+       if (!grp) {
+               dev_err(info->dev, "unable to find group for node %s\n",
+                       np->name);
+               return -EINVAL;
+       }
+
+       for (i = 0; i < grp->npins; i++) {
+               if (!(grp->configs[i] & IMX_NO_PAD_CTL))
+                       map_num++;
+       }
+
+       new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
+       if (!new_map)
+               return -ENOMEM;
+
+       *map = new_map;
+       *num_maps = map_num;
+
+       /* create mux map */
+       parent = of_get_parent(np);
+       if (!parent)
+               return -EINVAL;
+       new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+       new_map[0].data.mux.function = parent->name;
+       new_map[0].data.mux.group = np->name;
+       of_node_put(parent);
+
+       /* create config map */
+       new_map++;
+       for (i = 0; i < grp->npins; i++) {
+               if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
+                       new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
+                       new_map[i].data.configs.group_or_pin =
+                                       pin_get_name(pctldev, grp->pins[i]);
+                       new_map[i].data.configs.configs = &grp->configs[i];
+                       new_map[i].data.configs.num_configs = 1;
+               }
+       }
+
+       dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
+               new_map->data.mux.function, new_map->data.mux.group, map_num);
+
+       return 0;
+}
+
+static void imx_dt_free_map(struct pinctrl_dev *pctldev,
+                               struct pinctrl_map *map, unsigned num_maps)
+{
+       int i;
+
+       for (i = 0; i < num_maps; i++)
+               kfree(map);
+}
+
+static struct pinctrl_ops imx_pctrl_ops = {
+       .get_groups_count = imx_get_groups_count,
+       .get_group_name = imx_get_group_name,
+       .get_group_pins = imx_get_group_pins,
+       .pin_dbg_show = imx_pin_dbg_show,
+       .dt_node_to_map = imx_dt_node_to_map,
+       .dt_free_map = imx_dt_free_map,
+
+};
+
+static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
+                          unsigned group)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+       const struct imx_pin_reg *pin_reg;
+       const unsigned *pins, *mux;
+       unsigned int npins, pin_id;
+       int i;
+
+       /*
+        * Configure the mux mode for each pin in the group for a specific
+        * function.
+        */
+       pins = info->groups[group].pins;
+       npins = info->groups[group].npins;
+       mux = info->groups[group].mux_mode;
+
+       WARN_ON(!pins || !npins || !mux);
+
+       dev_dbg(ipctl->dev, "enable function %s group %s\n",
+               info->functions[selector].name, info->groups[group].name);
+
+       for (i = 0; i < npins; i++) {
+               pin_id = pins[i];
+
+               pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
+               if (!pin_reg)
+                       return -EINVAL;
+
+               if (!pin_reg->mux_reg) {
+                       dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
+                               info->pins[pin_id].name);
+                       return -EINVAL;
+               }
+
+               writel(mux[i], ipctl->base + pin_reg->mux_reg);
+               dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+                       pin_reg->mux_reg, mux[i]);
+
+               /* some pins also need select input setting, set it if found */
+               if (pin_reg->input_reg) {
+                       writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
+                       dev_dbg(ipctl->dev,
+                               "==>select_input: offset 0x%x val 0x%x\n",
+                               pin_reg->input_reg, pin_reg->input_val);
+               }
+       }
+
+       return 0;
+}
+
+static void imx_pmx_disable(struct pinctrl_dev *pctldev, unsigned func_selector,
+                           unsigned group_selector)
+{
+       /* nothing to do here */
+}
+
+static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+       return info->nfunctions;
+}
+
+static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
+                                         unsigned selector)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+       return info->functions[selector].name;
+}
+
+static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
+                              const char * const **groups,
+                              unsigned * const num_groups)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+       *groups = info->functions[selector].groups;
+       *num_groups = info->functions[selector].num_groups;
+
+       return 0;
+}
+
+static struct pinmux_ops imx_pmx_ops = {
+       .get_functions_count = imx_pmx_get_funcs_count,
+       .get_function_name = imx_pmx_get_func_name,
+       .get_function_groups = imx_pmx_get_groups,
+       .enable = imx_pmx_enable,
+       .disable = imx_pmx_disable,
+};
+
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
+                            unsigned pin_id, unsigned long *config)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+       const struct imx_pin_reg *pin_reg;
+
+       pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
+       if (!pin_reg)
+               return -EINVAL;
+
+       if (!pin_reg->conf_reg) {
+               dev_err(info->dev, "Pin(%s) does not support config function\n",
+                       info->pins[pin_id].name);
+               return -EINVAL;
+       }
+
+       *config = readl(ipctl->base + pin_reg->conf_reg);
+
+       return 0;
+}
+
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+                            unsigned pin_id, unsigned long config)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+       const struct imx_pin_reg *pin_reg;
+
+       pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
+       if (!pin_reg)
+               return -EINVAL;
+
+       if (!pin_reg->conf_reg) {
+               dev_err(info->dev, "Pin(%s) does not support config function\n",
+                       info->pins[pin_id].name);
+               return -EINVAL;
+       }
+
+       dev_dbg(ipctl->dev, "pinconf set pin %s\n",
+               info->pins[pin_id].name);
+
+       writel(config, ipctl->base + pin_reg->conf_reg);
+       dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+               pin_reg->conf_reg, config);
+
+       return 0;
+}
+
+static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+                                  struct seq_file *s, unsigned pin_id)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+       const struct imx_pin_reg *pin_reg;
+       unsigned long config;
+
+       pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
+       if (!pin_reg || !pin_reg->conf_reg) {
+               seq_printf(s, "N/A");
+               return;
+       }
+
+       config = readl(ipctl->base + pin_reg->conf_reg);
+       seq_printf(s, "0x%lx", config);
+}
+
+static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+                                        struct seq_file *s, unsigned group)
+{
+       struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+       const struct imx_pinctrl_soc_info *info = ipctl->info;
+       struct imx_pin_group *grp;
+       unsigned long config;
+       const char *name;
+       int i, ret;
+
+       if (group > info->ngroups)
+               return;
+
+       seq_printf(s, "\n");
+       grp = &info->groups[group];
+       for (i = 0; i < grp->npins; i++) {
+               name = pin_get_name(pctldev, grp->pins[i]);
+               ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
+               if (ret)
+                       return;
+               seq_printf(s, "%s: 0x%lx", name, config);
+       }
+}
+
+struct pinconf_ops imx_pinconf_ops = {
+       .pin_config_get = imx_pinconf_get,
+       .pin_config_set = imx_pinconf_set,
+       .pin_config_dbg_show = imx_pinconf_dbg_show,
+       .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc imx_pinctrl_desc = {
+       .pctlops = &imx_pctrl_ops,
+       .pmxops = &imx_pmx_ops,
+       .confops = &imx_pinconf_ops,
+       .owner = THIS_MODULE,
+};
+
+/* decode pin id and mux from pin function id got from device tree*/
+static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
+                               unsigned int pin_func_id, unsigned int *pin_id,
+                               unsigned int *mux)
+{
+       if (pin_func_id > info->npin_regs)
+               return -EINVAL;
+
+       *pin_id = info->pin_regs[pin_func_id].pid;
+       *mux = info->pin_regs[pin_func_id].mux_mode;
+
+       return 0;
+}
+
+static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
+                               struct imx_pin_group *grp,
+                               struct imx_pinctrl_soc_info *info,
+                               u32 index)
+{
+       unsigned int pin_func_id;
+       int ret, size;
+       const const __be32 *list;
+       int i, j;
+       u32 config;
+
+       dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
+       /* Initialise group */
+       grp->name = np->name;
+
+       /*
+        * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
+        * do sanity check and calculate pins number
+        */
+       list = of_get_property(np, "fsl,pins", &size);
+       /* we do not check return since it's safe node passed down */
+       size /= sizeof(*list);
+       if (!size || size % 2) {
+               dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
+               return -EINVAL;
+       }
+
+       grp->npins = size / 2;
+       grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+                               GFP_KERNEL);
+       grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+                               GFP_KERNEL);
+       grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
+                               GFP_KERNEL);
+       for (i = 0, j = 0; i < size; i += 2, j++) {
+               pin_func_id = be32_to_cpu(*list++);
+               ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
+                                       &grp->pins[j], &grp->mux_mode[j]);
+               if (ret) {
+                       dev_err(info->dev, "get invalid pin function id\n");
+                       return -EINVAL;
+               }
+               /* SION bit is in mux register */
+               config = be32_to_cpu(*list++);
+               if (config & IMX_PAD_SION)
+                       grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
+               grp->configs[j] = config & ~IMX_PAD_SION;
+       }
+
+#ifdef DEBUG
+       IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
+#endif
+       return 0;
+}
+
+static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
+                       struct imx_pinctrl_soc_info *info, u32 index)
+{
+       struct device_node *child;
+       struct imx_pmx_func *func;
+       struct imx_pin_group *grp;
+       int ret;
+       static u32 grp_index;
+       u32 i = 0;
+
+       dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+
+       func = &info->functions[index];
+
+       /* Initialise function */
+       func->name = np->name;
+       func->num_groups = of_get_child_count(np);
+       if (func->num_groups <= 0) {
+               dev_err(info->dev, "no groups defined\n");
+               return -EINVAL;
+       }
+       func->groups = devm_kzalloc(info->dev,
+                       func->num_groups * sizeof(char *), GFP_KERNEL);
+
+       for_each_child_of_node(np, child) {
+               func->groups[i] = child->name;
+               grp = &info->groups[grp_index++];
+               ret = imx_pinctrl_parse_groups(child, grp, info, i++);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev,
+                               struct imx_pinctrl_soc_info *info)
+{
+       struct device_node *np = pdev->dev.of_node;
+       struct device_node *child;
+       int ret;
+       u32 nfuncs = 0;
+       u32 i = 0;
+
+       if (!np)
+               return -ENODEV;
+
+       nfuncs = of_get_child_count(np);
+       if (nfuncs <= 0) {
+               dev_err(&pdev->dev, "no functions defined\n");
+               return -EINVAL;
+       }
+
+       info->nfunctions = nfuncs;
+       info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
+                                       GFP_KERNEL);
+       if (!info->functions)
+               return -ENOMEM;
+
+       info->ngroups = 0;
+       for_each_child_of_node(np, child)
+               info->ngroups += of_get_child_count(child);
+       info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
+                                       GFP_KERNEL);
+       if (!info->groups)
+               return -ENOMEM;
+
+       for_each_child_of_node(np, child) {
+               ret = imx_pinctrl_parse_functions(child, info, i++);
+               if (ret) {
+                       dev_err(&pdev->dev, "failed to parse function\n");
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+int __devinit imx_pinctrl_probe(struct platform_device *pdev,
+                               struct imx_pinctrl_soc_info *info)
+{
+       struct imx_pinctrl *ipctl;
+       struct resource *res;
+       int ret;
+
+       if (!info || !info->pins || !info->npins
+                 || !info->pin_regs || !info->npin_regs) {
+               dev_err(&pdev->dev, "wrong pinctrl info\n");
+               return -EINVAL;
+       }
+       info->dev = &pdev->dev;
+
+       /* Create state holders etc for this driver */
+       ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+       if (!ipctl)
+               return -ENOMEM;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!res)
+               return -ENOENT;
+
+       ipctl->base = devm_request_and_ioremap(&pdev->dev, res);
+       if (!ipctl->base)
+               return -EBUSY;
+
+       imx_pinctrl_desc.name = dev_name(&pdev->dev);
+       imx_pinctrl_desc.pins = info->pins;
+       imx_pinctrl_desc.npins = info->npins;
+
+       ret = imx_pinctrl_probe_dt(pdev, info);
+       if (ret) {
+               dev_err(&pdev->dev, "fail to probe dt properties\n");
+               return ret;
+       }
+
+       ipctl->info = info;
+       ipctl->dev = info->dev;
+       platform_set_drvdata(pdev, ipctl);
+       ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
+       if (!ipctl->pctl) {
+               dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
+               return -EINVAL;
+       }
+
+       dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
+
+       return 0;
+}
+
+int __devexit imx_pinctrl_remove(struct platform_device *pdev)
+{
+       struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+       pinctrl_unregister(ipctl->pctl);
+
+       return 0;
+}

diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
new file mode 100644 (file)
index 0000000..9b65e78
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -0,0 +1,106 @@
+/*
+ * IMX pinmux core definitions
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DRIVERS_PINCTRL_IMX_H
+#define __DRIVERS_PINCTRL_IMX_H
+
+struct platform_device;
+
+/**
+ * struct imx_pin_group - describes an IMX pin group
+ * @name: the name of this specific pin group
+ * @pins: an array of discrete physical pins used in this group, taken
+ *     from the driver-local pin enumeration space
+ * @npins: the number of pins in this group array, i.e. the number of
+ *     elements in .pins so we can iterate over that array
+ * @mux_mode: the mux mode for each pin in this group. The size of this
+ *     array is the same as pins.
+ * @configs: the config for each pin in this group. The size of this
+ *     array is the same as pins.
+ */
+struct imx_pin_group {
+       const char *name;
+       unsigned int *pins;
+       unsigned npins;
+       unsigned int *mux_mode;
+       unsigned long *configs;
+};
+
+/**
+ * struct imx_pmx_func - describes IMX pinmux functions
+ * @name: the name of this specific function
+ * @groups: corresponding pin groups
+ * @num_groups: the number of groups
+ */
+struct imx_pmx_func {
+       const char *name;
+       const char **groups;
+       unsigned num_groups;
+};
+
+/**
+ * struct imx_pin_reg - describe a pin reg map
+ * The last 3 members are used for select input setting
+ * @pid: pin id
+ * @mux_reg: mux register offset
+ * @conf_reg: config register offset
+ * @mux_mode: mux mode
+ * @input_reg: select input register offset for this mux if any
+ *  0 if no select input setting needed.
+ * @input_val: the value set to select input register
+ */
+struct imx_pin_reg {
+       u16 pid;
+       u16 mux_reg;
+       u16 conf_reg;
+       u8 mux_mode;
+       u16 input_reg;
+       u8 input_val;
+};
+
+struct imx_pinctrl_soc_info {
+       struct device *dev;
+       const struct pinctrl_pin_desc *pins;
+       unsigned int npins;
+       const struct imx_pin_reg *pin_regs;
+       unsigned int npin_regs;
+       struct imx_pin_group *groups;
+       unsigned int ngroups;
+       struct imx_pmx_func *functions;
+       unsigned int nfunctions;
+};
+
+#define NO_MUX         0x0
+#define NO_PAD         0x0
+
+#define IMX_PIN_REG(id, conf, mux, mode, input, val)   \
+       {                                               \
+               .pid = id,                              \
+               .conf_reg = conf,                       \
+               .mux_reg = mux,                         \
+               .mux_mode  = mode,                      \
+               .input_reg = input,                     \
+               .input_val = val,                       \
+       }
+
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+#define PAD_CTL_MASK(len)      ((1 << len) - 1)
+#define IMX_MUX_MASK   0x7
+#define IOMUXC_CONFIG_SION     (0x1 << 4)
+
+int imx_pinctrl_probe(struct platform_device *pdev,
+                       struct imx_pinctrl_soc_info *info);
+int imx_pinctrl_remove(struct platform_device *pdev);
+#endif /* __DRIVERS_PINCTRL_IMX_H */

diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c
new file mode 100644 (file)
index 0000000..75d3eff
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx23.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mxs.h"
+
+enum imx23_pin_enum {
+       GPMI_D00        = PINID(0, 0),
+       GPMI_D01        = PINID(0, 1),
+       GPMI_D02        = PINID(0, 2),
+       GPMI_D03        = PINID(0, 3),
+       GPMI_D04        = PINID(0, 4),
+       GPMI_D05        = PINID(0, 5),
+       GPMI_D06        = PINID(0, 6),
+       GPMI_D07        = PINID(0, 7),
+       GPMI_D08        = PINID(0, 8),
+       GPMI_D09        = PINID(0, 9),
+       GPMI_D10        = PINID(0, 10),
+       GPMI_D11        = PINID(0, 11),
+       GPMI_D12        = PINID(0, 12),
+       GPMI_D13        = PINID(0, 13),
+       GPMI_D14        = PINID(0, 14),
+       GPMI_D15        = PINID(0, 15),
+       GPMI_CLE        = PINID(0, 16),
+       GPMI_ALE        = PINID(0, 17),
+       GPMI_CE2N       = PINID(0, 18),
+       GPMI_RDY0       = PINID(0, 19),
+       GPMI_RDY1       = PINID(0, 20),
+       GPMI_RDY2       = PINID(0, 21),
+       GPMI_RDY3       = PINID(0, 22),
+       GPMI_WPN        = PINID(0, 23),
+       GPMI_WRN        = PINID(0, 24),
+       GPMI_RDN        = PINID(0, 25),
+       AUART1_CTS      = PINID(0, 26),
+       AUART1_RTS      = PINID(0, 27),
+       AUART1_RX       = PINID(0, 28),
+       AUART1_TX       = PINID(0, 29),
+       I2C_SCL         = PINID(0, 30),
+       I2C_SDA         = PINID(0, 31),
+       LCD_D00         = PINID(1, 0),
+       LCD_D01         = PINID(1, 1),
+       LCD_D02         = PINID(1, 2),
+       LCD_D03         = PINID(1, 3),
+       LCD_D04         = PINID(1, 4),
+       LCD_D05         = PINID(1, 5),
+       LCD_D06         = PINID(1, 6),
+       LCD_D07         = PINID(1, 7),
+       LCD_D08         = PINID(1, 8),
+       LCD_D09         = PINID(1, 9),
+       LCD_D10         = PINID(1, 10),
+       LCD_D11         = PINID(1, 11),
+       LCD_D12         = PINID(1, 12),
+       LCD_D13         = PINID(1, 13),
+       LCD_D14         = PINID(1, 14),
+       LCD_D15         = PINID(1, 15),
+       LCD_D16         = PINID(1, 16),
+       LCD_D17         = PINID(1, 17),
+       LCD_RESET       = PINID(1, 18),
+       LCD_RS          = PINID(1, 19),
+       LCD_WR          = PINID(1, 20),
+       LCD_CS          = PINID(1, 21),
+       LCD_DOTCK       = PINID(1, 22),
+       LCD_ENABLE      = PINID(1, 23),
+       LCD_HSYNC       = PINID(1, 24),
+       LCD_VSYNC       = PINID(1, 25),
+       PWM0            = PINID(1, 26),
+       PWM1            = PINID(1, 27),
+       PWM2            = PINID(1, 28),
+       PWM3            = PINID(1, 29),
+       PWM4            = PINID(1, 30),
+       SSP1_CMD        = PINID(2, 0),
+       SSP1_DETECT     = PINID(2, 1),
+       SSP1_DATA0      = PINID(2, 2),
+       SSP1_DATA1      = PINID(2, 3),
+       SSP1_DATA2      = PINID(2, 4),
+       SSP1_DATA3      = PINID(2, 5),
+       SSP1_SCK        = PINID(2, 6),
+       ROTARYA         = PINID(2, 7),
+       ROTARYB         = PINID(2, 8),
+       EMI_A00         = PINID(2, 9),
+       EMI_A01         = PINID(2, 10),
+       EMI_A02         = PINID(2, 11),
+       EMI_A03         = PINID(2, 12),
+       EMI_A04         = PINID(2, 13),
+       EMI_A05         = PINID(2, 14),
+       EMI_A06         = PINID(2, 15),
+       EMI_A07         = PINID(2, 16),
+       EMI_A08         = PINID(2, 17),
+       EMI_A09         = PINID(2, 18),
+       EMI_A10         = PINID(2, 19),
+       EMI_A11         = PINID(2, 20),
+       EMI_A12         = PINID(2, 21),
+       EMI_BA0         = PINID(2, 22),
+       EMI_BA1         = PINID(2, 23),
+       EMI_CASN        = PINID(2, 24),
+       EMI_CE0N        = PINID(2, 25),
+       EMI_CE1N        = PINID(2, 26),
+       GPMI_CE1N       = PINID(2, 27),
+       GPMI_CE0N       = PINID(2, 28),
+       EMI_CKE         = PINID(2, 29),
+       EMI_RASN        = PINID(2, 30),
+       EMI_WEN         = PINID(2, 31),
+       EMI_D00         = PINID(3, 0),
+       EMI_D01         = PINID(3, 1),
+       EMI_D02         = PINID(3, 2),
+       EMI_D03         = PINID(3, 3),
+       EMI_D04         = PINID(3, 4),
+       EMI_D05         = PINID(3, 5),
+       EMI_D06         = PINID(3, 6),
+       EMI_D07         = PINID(3, 7),
+       EMI_D08         = PINID(3, 8),
+       EMI_D09         = PINID(3, 9),
+       EMI_D10         = PINID(3, 10),
+       EMI_D11         = PINID(3, 11),
+       EMI_D12         = PINID(3, 12),
+       EMI_D13         = PINID(3, 13),
+       EMI_D14         = PINID(3, 14),
+       EMI_D15         = PINID(3, 15),
+       EMI_DQM0        = PINID(3, 16),
+       EMI_DQM1        = PINID(3, 17),
+       EMI_DQS0        = PINID(3, 18),
+       EMI_DQS1        = PINID(3, 19),
+       EMI_CLK         = PINID(3, 20),
+       EMI_CLKN        = PINID(3, 21),
+};
+
+static const struct pinctrl_pin_desc imx23_pins[] = {
+       MXS_PINCTRL_PIN(GPMI_D00),
+       MXS_PINCTRL_PIN(GPMI_D01),
+       MXS_PINCTRL_PIN(GPMI_D02),
+       MXS_PINCTRL_PIN(GPMI_D03),
+       MXS_PINCTRL_PIN(GPMI_D04),
+       MXS_PINCTRL_PIN(GPMI_D05),
+       MXS_PINCTRL_PIN(GPMI_D06),
+       MXS_PINCTRL_PIN(GPMI_D07),
+       MXS_PINCTRL_PIN(GPMI_D08),
+       MXS_PINCTRL_PIN(GPMI_D09),
+       MXS_PINCTRL_PIN(GPMI_D10),
+       MXS_PINCTRL_PIN(GPMI_D11),
+       MXS_PINCTRL_PIN(GPMI_D12),
+       MXS_PINCTRL_PIN(GPMI_D13),
+       MXS_PINCTRL_PIN(GPMI_D14),
+       MXS_PINCTRL_PIN(GPMI_D15),
+       MXS_PINCTRL_PIN(GPMI_CLE),
+       MXS_PINCTRL_PIN(GPMI_ALE),
+       MXS_PINCTRL_PIN(GPMI_CE2N),
+       MXS_PINCTRL_PIN(GPMI_RDY0),
+       MXS_PINCTRL_PIN(GPMI_RDY1),
+       MXS_PINCTRL_PIN(GPMI_RDY2),
+       MXS_PINCTRL_PIN(GPMI_RDY3),
+       MXS_PINCTRL_PIN(GPMI_WPN),
+       MXS_PINCTRL_PIN(GPMI_WRN),
+       MXS_PINCTRL_PIN(GPMI_RDN),
+       MXS_PINCTRL_PIN(AUART1_CTS),
+       MXS_PINCTRL_PIN(AUART1_RTS),
+       MXS_PINCTRL_PIN(AUART1_RX),
+       MXS_PINCTRL_PIN(AUART1_TX),
+       MXS_PINCTRL_PIN(I2C_SCL),
+       MXS_PINCTRL_PIN(I2C_SDA),
+       MXS_PINCTRL_PIN(LCD_D00),
+       MXS_PINCTRL_PIN(LCD_D01),
+       MXS_PINCTRL_PIN(LCD_D02),
+       MXS_PINCTRL_PIN(LCD_D03),
+       MXS_PINCTRL_PIN(LCD_D04),
+       MXS_PINCTRL_PIN(LCD_D05),
+       MXS_PINCTRL_PIN(LCD_D06),
+       MXS_PINCTRL_PIN(LCD_D07),
+       MXS_PINCTRL_PIN(LCD_D08),
+       MXS_PINCTRL_PIN(LCD_D09),
+       MXS_PINCTRL_PIN(LCD_D10),
+       MXS_PINCTRL_PIN(LCD_D11),
+       MXS_PINCTRL_PIN(LCD_D12),
+       MXS_PINCTRL_PIN(LCD_D13),
+       MXS_PINCTRL_PIN(LCD_D14),
+       MXS_PINCTRL_PIN(LCD_D15),
+       MXS_PINCTRL_PIN(LCD_D16),
+       MXS_PINCTRL_PIN(LCD_D17),
+       MXS_PINCTRL_PIN(LCD_RESET),
+       MXS_PINCTRL_PIN(LCD_RS),
+       MXS_PINCTRL_PIN(LCD_WR),
+       MXS_PINCTRL_PIN(LCD_CS),
+       MXS_PINCTRL_PIN(LCD_DOTCK),
+       MXS_PINCTRL_PIN(LCD_ENABLE),
+       MXS_PINCTRL_PIN(LCD_HSYNC),
+       MXS_PINCTRL_PIN(LCD_VSYNC),
+       MXS_PINCTRL_PIN(PWM0),
+       MXS_PINCTRL_PIN(PWM1),
+       MXS_PINCTRL_PIN(PWM2),
+       MXS_PINCTRL_PIN(PWM3),
+       MXS_PINCTRL_PIN(PWM4),
+       MXS_PINCTRL_PIN(SSP1_CMD),
+       MXS_PINCTRL_PIN(SSP1_DETECT),
+       MXS_PINCTRL_PIN(SSP1_DATA0),
+       MXS_PINCTRL_PIN(SSP1_DATA1),
+       MXS_PINCTRL_PIN(SSP1_DATA2),
+       MXS_PINCTRL_PIN(SSP1_DATA3),
+       MXS_PINCTRL_PIN(SSP1_SCK),
+       MXS_PINCTRL_PIN(ROTARYA),
+       MXS_PINCTRL_PIN(ROTARYB),
+       MXS_PINCTRL_PIN(EMI_A00),
+       MXS_PINCTRL_PIN(EMI_A01),
+       MXS_PINCTRL_PIN(EMI_A02),
+       MXS_PINCTRL_PIN(EMI_A03),
+       MXS_PINCTRL_PIN(EMI_A04),
+       MXS_PINCTRL_PIN(EMI_A05),
+       MXS_PINCTRL_PIN(EMI_A06),
+       MXS_PINCTRL_PIN(EMI_A07),
+       MXS_PINCTRL_PIN(EMI_A08),
+       MXS_PINCTRL_PIN(EMI_A09),
+       MXS_PINCTRL_PIN(EMI_A10),
+       MXS_PINCTRL_PIN(EMI_A11),
+       MXS_PINCTRL_PIN(EMI_A12),
+       MXS_PINCTRL_PIN(EMI_BA0),
+       MXS_PINCTRL_PIN(EMI_BA1),
+       MXS_PINCTRL_PIN(EMI_CASN),
+       MXS_PINCTRL_PIN(EMI_CE0N),
+       MXS_PINCTRL_PIN(EMI_CE1N),
+       MXS_PINCTRL_PIN(GPMI_CE1N),
+       MXS_PINCTRL_PIN(GPMI_CE0N),
+       MXS_PINCTRL_PIN(EMI_CKE),
+       MXS_PINCTRL_PIN(EMI_RASN),
+       MXS_PINCTRL_PIN(EMI_WEN),
+       MXS_PINCTRL_PIN(EMI_D00),
+       MXS_PINCTRL_PIN(EMI_D01),
+       MXS_PINCTRL_PIN(EMI_D02),
+       MXS_PINCTRL_PIN(EMI_D03),
+       MXS_PINCTRL_PIN(EMI_D04),
+       MXS_PINCTRL_PIN(EMI_D05),
+       MXS_PINCTRL_PIN(EMI_D06),
+       MXS_PINCTRL_PIN(EMI_D07),
+       MXS_PINCTRL_PIN(EMI_D08),
+       MXS_PINCTRL_PIN(EMI_D09),
+       MXS_PINCTRL_PIN(EMI_D10),
+       MXS_PINCTRL_PIN(EMI_D11),
+       MXS_PINCTRL_PIN(EMI_D12),
+       MXS_PINCTRL_PIN(EMI_D13),
+       MXS_PINCTRL_PIN(EMI_D14),
+       MXS_PINCTRL_PIN(EMI_D15),
+       MXS_PINCTRL_PIN(EMI_DQM0),
+       MXS_PINCTRL_PIN(EMI_DQM1),
+       MXS_PINCTRL_PIN(EMI_DQS0),
+       MXS_PINCTRL_PIN(EMI_DQS1),
+       MXS_PINCTRL_PIN(EMI_CLK),
+       MXS_PINCTRL_PIN(EMI_CLKN),
+};
+
+static struct mxs_regs imx23_regs = {
+       .muxsel = 0x100,
+       .drive = 0x200,
+       .pull = 0x400,
+};
+
+static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
+       .regs = &imx23_regs,
+       .pins = imx23_pins,
+       .npins = ARRAY_SIZE(imx23_pins),
+};
+
+static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
+{
+       return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
+}
+
+static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
+       { .compatible = "fsl,imx23-pinctrl", },
+       { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
+
+static struct platform_driver imx23_pinctrl_driver = {
+       .driver = {
+               .name = "imx23-pinctrl",
+               .owner = THIS_MODULE,
+               .of_match_table = imx23_pinctrl_of_match,
+       },
+       .probe = imx23_pinctrl_probe,
+       .remove = __devexit_p(mxs_pinctrl_remove),
+};
+
+static int __init imx23_pinctrl_init(void)
+{
+       return platform_driver_register(&imx23_pinctrl_driver);
+}
+arch_initcall(imx23_pinctrl_init);
+
+static void __exit imx23_pinctrl_exit(void)
+{
+       platform_driver_unregister(&imx23_pinctrl_driver);
+}
+module_exit(imx23_pinctrl_exit);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
+MODULE_LICENSE("GPL v2");

diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c
new file mode 100644 (file)
index 0000000..b973026
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx28.c
@@ -0,0 +1,421 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-mxs.h"
+
+enum imx28_pin_enum {
+       GPMI_D00        = PINID(0, 0),
+       GPMI_D01        = PINID(0, 1),
+       GPMI_D02        = PINID(0, 2),
+       GPMI_D03        = PINID(0, 3),
+       GPMI_D04        = PINID(0, 4),
+       GPMI_D05        = PINID(0, 5),
+       GPMI_D06        = PINID(0, 6),
+       GPMI_D07        = PINID(0, 7),
+       GPMI_CE0N       = PINID(0, 16),
+       GPMI_CE1N       = PINID(0, 17),
+       GPMI_CE2N       = PINID(0, 18),
+       GPMI_CE3N       = PINID(0, 19),
+       GPMI_RDY0       = PINID(0, 20),
+       GPMI_RDY1       = PINID(0, 21),
+       GPMI_RDY2       = PINID(0, 22),
+       GPMI_RDY3       = PINID(0, 23),
+       GPMI_RDN        = PINID(0, 24),
+       GPMI_WRN        = PINID(0, 25),
+       GPMI_ALE        = PINID(0, 26),
+       GPMI_CLE        = PINID(0, 27),
+       GPMI_RESETN     = PINID(0, 28),
+       LCD_D00         = PINID(1, 0),
+       LCD_D01         = PINID(1, 1),
+       LCD_D02         = PINID(1, 2),
+       LCD_D03         = PINID(1, 3),
+       LCD_D04         = PINID(1, 4),
+       LCD_D05         = PINID(1, 5),
+       LCD_D06         = PINID(1, 6),
+       LCD_D07         = PINID(1, 7),
+       LCD_D08         = PINID(1, 8),
+       LCD_D09         = PINID(1, 9),
+       LCD_D10         = PINID(1, 10),
+       LCD_D11         = PINID(1, 11),
+       LCD_D12         = PINID(1, 12),
+       LCD_D13         = PINID(1, 13),
+       LCD_D14         = PINID(1, 14),
+       LCD_D15         = PINID(1, 15),
+       LCD_D16         = PINID(1, 16),
+       LCD_D17         = PINID(1, 17),
+       LCD_D18         = PINID(1, 18),
+       LCD_D19         = PINID(1, 19),
+       LCD_D20         = PINID(1, 20),
+       LCD_D21         = PINID(1, 21),
+       LCD_D22         = PINID(1, 22),
+       LCD_D23         = PINID(1, 23),
+       LCD_RD_E        = PINID(1, 24),
+       LCD_WR_RWN      = PINID(1, 25),
+       LCD_RS          = PINID(1, 26),
+       LCD_CS          = PINID(1, 27),
+       LCD_VSYNC       = PINID(1, 28),
+       LCD_HSYNC       = PINID(1, 29),
+       LCD_DOTCLK      = PINID(1, 30),
+       LCD_ENABLE      = PINID(1, 31),
+       SSP0_DATA0      = PINID(2, 0),
+       SSP0_DATA1      = PINID(2, 1),
+       SSP0_DATA2      = PINID(2, 2),
+       SSP0_DATA3      = PINID(2, 3),
+       SSP0_DATA4      = PINID(2, 4),
+       SSP0_DATA5      = PINID(2, 5),
+       SSP0_DATA6      = PINID(2, 6),
+       SSP0_DATA7      = PINID(2, 7),
+       SSP0_CMD        = PINID(2, 8),
+       SSP0_DETECT     = PINID(2, 9),
+       SSP0_SCK        = PINID(2, 10),
+       SSP1_SCK        = PINID(2, 12),
+       SSP1_CMD        = PINID(2, 13),
+       SSP1_DATA0      = PINID(2, 14),
+       SSP1_DATA3      = PINID(2, 15),
+       SSP2_SCK        = PINID(2, 16),
+       SSP2_MOSI       = PINID(2, 17),
+       SSP2_MISO       = PINID(2, 18),
+       SSP2_SS0        = PINID(2, 19),
+       SSP2_SS1        = PINID(2, 20),
+       SSP2_SS2        = PINID(2, 21),
+       SSP3_SCK        = PINID(2, 24),
+       SSP3_MOSI       = PINID(2, 25),
+       SSP3_MISO       = PINID(2, 26),
+       SSP3_SS0        = PINID(2, 27),
+       AUART0_RX       = PINID(3, 0),
+       AUART0_TX       = PINID(3, 1),
+       AUART0_CTS      = PINID(3, 2),
+       AUART0_RTS      = PINID(3, 3),
+       AUART1_RX       = PINID(3, 4),
+       AUART1_TX       = PINID(3, 5),
+       AUART1_CTS      = PINID(3, 6),
+       AUART1_RTS      = PINID(3, 7),
+       AUART2_RX       = PINID(3, 8),
+       AUART2_TX       = PINID(3, 9),
+       AUART2_CTS      = PINID(3, 10),
+       AUART2_RTS      = PINID(3, 11),
+       AUART3_RX       = PINID(3, 12),
+       AUART3_TX       = PINID(3, 13),
+       AUART3_CTS      = PINID(3, 14),
+       AUART3_RTS      = PINID(3, 15),
+       PWM0            = PINID(3, 16),
+       PWM1            = PINID(3, 17),
+       PWM2            = PINID(3, 18),
+       SAIF0_MCLK      = PINID(3, 20),
+       SAIF0_LRCLK     = PINID(3, 21),
+       SAIF0_BITCLK    = PINID(3, 22),
+       SAIF0_SDATA0    = PINID(3, 23),
+       I2C0_SCL        = PINID(3, 24),
+       I2C0_SDA        = PINID(3, 25),
+       SAIF1_SDATA0    = PINID(3, 26),
+       SPDIF           = PINID(3, 27),
+       PWM3            = PINID(3, 28),
+       PWM4            = PINID(3, 29),
+       LCD_RESET       = PINID(3, 30),
+       ENET0_MDC       = PINID(4, 0),
+       ENET0_MDIO      = PINID(4, 1),
+       ENET0_RX_EN     = PINID(4, 2),
+       ENET0_RXD0      = PINID(4, 3),
+       ENET0_RXD1      = PINID(4, 4),
+       ENET0_TX_CLK    = PINID(4, 5),
+       ENET0_TX_EN     = PINID(4, 6),
+       ENET0_TXD0      = PINID(4, 7),
+       ENET0_TXD1      = PINID(4, 8),
+       ENET0_RXD2      = PINID(4, 9),
+       ENET0_RXD3      = PINID(4, 10),
+       ENET0_TXD2      = PINID(4, 11),
+       ENET0_TXD3      = PINID(4, 12),
+       ENET0_RX_CLK    = PINID(4, 13),
+       ENET0_COL       = PINID(4, 14),
+       ENET0_CRS       = PINID(4, 15),
+       ENET_CLK        = PINID(4, 16),
+       JTAG_RTCK       = PINID(4, 20),
+       EMI_D00         = PINID(5, 0),
+       EMI_D01         = PINID(5, 1),
+       EMI_D02         = PINID(5, 2),
+       EMI_D03         = PINID(5, 3),
+       EMI_D04         = PINID(5, 4),
+       EMI_D05         = PINID(5, 5),
+       EMI_D06         = PINID(5, 6),
+       EMI_D07         = PINID(5, 7),
+       EMI_D08         = PINID(5, 8),
+       EMI_D09         = PINID(5, 9),
+       EMI_D10         = PINID(5, 10),
+       EMI_D11         = PINID(5, 11),
+       EMI_D12         = PINID(5, 12),
+       EMI_D13         = PINID(5, 13),
+       EMI_D14         = PINID(5, 14),
+       EMI_D15         = PINID(5, 15),
+       EMI_ODT0        = PINID(5, 16),
+       EMI_DQM0        = PINID(5, 17),
+       EMI_ODT1        = PINID(5, 18),
+       EMI_DQM1        = PINID(5, 19),
+       EMI_DDR_OPEN_FB = PINID(5, 20),
+       EMI_CLK         = PINID(5, 21),
+       EMI_DQS0        = PINID(5, 22),
+       EMI_DQS1        = PINID(5, 23),
+       EMI_DDR_OPEN    = PINID(5, 26),
+       EMI_A00         = PINID(6, 0),
+       EMI_A01         = PINID(6, 1),
+       EMI_A02         = PINID(6, 2),
+       EMI_A03         = PINID(6, 3),
+       EMI_A04         = PINID(6, 4),
+       EMI_A05         = PINID(6, 5),
+       EMI_A06         = PINID(6, 6),
+       EMI_A07         = PINID(6, 7),
+       EMI_A08         = PINID(6, 8),
+       EMI_A09         = PINID(6, 9),
+       EMI_A10         = PINID(6, 10),
+       EMI_A11         = PINID(6, 11),
+       EMI_A12         = PINID(6, 12),
+       EMI_A13         = PINID(6, 13),
+       EMI_A14         = PINID(6, 14),
+       EMI_BA0         = PINID(6, 16),
+       EMI_BA1         = PINID(6, 17),
+       EMI_BA2         = PINID(6, 18),
+       EMI_CASN        = PINID(6, 19),
+       EMI_RASN        = PINID(6, 20),
+       EMI_WEN         = PINID(6, 21),
+       EMI_CE0N        = PINID(6, 22),
+       EMI_CE1N        = PINID(6, 23),
+       EMI_CKE         = PINID(6, 24),
+};
+
+static const struct pinctrl_pin_desc imx28_pins[] = {
+       MXS_PINCTRL_PIN(GPMI_D00),
+       MXS_PINCTRL_PIN(GPMI_D01),
+       MXS_PINCTRL_PIN(GPMI_D02),
+       MXS_PINCTRL_PIN(GPMI_D03),
+       MXS_PINCTRL_PIN(GPMI_D04),
+       MXS_PINCTRL_PIN(GPMI_D05),
+       MXS_PINCTRL_PIN(GPMI_D06),
+       MXS_PINCTRL_PIN(GPMI_D07),
+       MXS_PINCTRL_PIN(GPMI_CE0N),
+       MXS_PINCTRL_PIN(GPMI_CE1N),
+       MXS_PINCTRL_PIN(GPMI_CE2N),
+       MXS_PINCTRL_PIN(GPMI_CE3N),
+       MXS_PINCTRL_PIN(GPMI_RDY0),
+       MXS_PINCTRL_PIN(GPMI_RDY1),
+       MXS_PINCTRL_PIN(GPMI_RDY2),
+       MXS_PINCTRL_PIN(GPMI_RDY3),
+       MXS_PINCTRL_PIN(GPMI_RDN),
+       MXS_PINCTRL_PIN(GPMI_WRN),
+       MXS_PINCTRL_PIN(GPMI_ALE),
+       MXS_PINCTRL_PIN(GPMI_CLE),
+       MXS_PINCTRL_PIN(GPMI_RESETN),
+       MXS_PINCTRL_PIN(LCD_D00),
+       MXS_PINCTRL_PIN(LCD_D01),
+       MXS_PINCTRL_PIN(LCD_D02),
+       MXS_PINCTRL_PIN(LCD_D03),
+       MXS_PINCTRL_PIN(LCD_D04),
+       MXS_PINCTRL_PIN(LCD_D05),
+       MXS_PINCTRL_PIN(LCD_D06),
+       MXS_PINCTRL_PIN(LCD_D07),
+       MXS_PINCTRL_PIN(LCD_D08),
+       MXS_PINCTRL_PIN(LCD_D09),
+       MXS_PINCTRL_PIN(LCD_D10),
+       MXS_PINCTRL_PIN(LCD_D11),
+       MXS_PINCTRL_PIN(LCD_D12),
+       MXS_PINCTRL_PIN(LCD_D13),
+       MXS_PINCTRL_PIN(LCD_D14),
+       MXS_PINCTRL_PIN(LCD_D15),
+       MXS_PINCTRL_PIN(LCD_D16),
+       MXS_PINCTRL_PIN(LCD_D17),
+       MXS_PINCTRL_PIN(LCD_D18),
+       MXS_PINCTRL_PIN(LCD_D19),
+       MXS_PINCTRL_PIN(LCD_D20),
+       MXS_PINCTRL_PIN(LCD_D21),
+       MXS_PINCTRL_PIN(LCD_D22),
+       MXS_PINCTRL_PIN(LCD_D23),
+       MXS_PINCTRL_PIN(LCD_RD_E),
+       MXS_PINCTRL_PIN(LCD_WR_RWN),
+       MXS_PINCTRL_PIN(LCD_RS),
+       MXS_PINCTRL_PIN(LCD_CS),
+       MXS_PINCTRL_PIN(LCD_VSYNC),
+       MXS_PINCTRL_PIN(LCD_HSYNC),
+       MXS_PINCTRL_PIN(LCD_DOTCLK),
+       MXS_PINCTRL_PIN(LCD_ENABLE),
+       MXS_PINCTRL_PIN(SSP0_DATA0),
+       MXS_PINCTRL_PIN(SSP0_DATA1),
+       MXS_PINCTRL_PIN(SSP0_DATA2),
+       MXS_PINCTRL_PIN(SSP0_DATA3),
+       MXS_PINCTRL_PIN(SSP0_DATA4),
+       MXS_PINCTRL_PIN(SSP0_DATA5),
+       MXS_PINCTRL_PIN(SSP0_DATA6),
+       MXS_PINCTRL_PIN(SSP0_DATA7),
+       MXS_PINCTRL_PIN(SSP0_CMD),
+       MXS_PINCTRL_PIN(SSP0_DETECT),
+       MXS_PINCTRL_PIN(SSP0_SCK),
+       MXS_PINCTRL_PIN(SSP1_SCK),
+       MXS_PINCTRL_PIN(SSP1_CMD),
+       MXS_PINCTRL_PIN(SSP1_DATA0),
+       MXS_PINCTRL_PIN(SSP1_DATA3),
+       MXS_PINCTRL_PIN(SSP2_SCK),
+       MXS_PINCTRL_PIN(SSP2_MOSI),
+       MXS_PINCTRL_PIN(SSP2_MISO),
+       MXS_PINCTRL_PIN(SSP2_SS0),
+       MXS_PINCTRL_PIN(SSP2_SS1),
+       MXS_PINCTRL_PIN(SSP2_SS2),
+       MXS_PINCTRL_PIN(SSP3_SCK),
+       MXS_PINCTRL_PIN(SSP3_MOSI),
+       MXS_PINCTRL_PIN(SSP3_MISO),
+       MXS_PINCTRL_PIN(SSP3_SS0),
+       MXS_PINCTRL_PIN(AUART0_RX),
+       MXS_PINCTRL_PIN(AUART0_TX),
+       MXS_PINCTRL_PIN(AUART0_CTS),
+       MXS_PINCTRL_PIN(AUART0_RTS),
+       MXS_PINCTRL_PIN(AUART1_RX),
+       MXS_PINCTRL_PIN(AUART1_TX),
+       MXS_PINCTRL_PIN(AUART1_CTS),
+       MXS_PINCTRL_PIN(AUART1_RTS),
+       MXS_PINCTRL_PIN(AUART2_RX),
+       MXS_PINCTRL_PIN(AUART2_TX),
+       MXS_PINCTRL_PIN(AUART2_CTS),
+       MXS_PINCTRL_PIN(AUART2_RTS),
+       MXS_PINCTRL_PIN(AUART3_RX),
+       MXS_PINCTRL_PIN(AUART3_TX),
+       MXS_PINCTRL_PIN(AUART3_CTS),
+       MXS_PINCTRL_PIN(AUART3_RTS),
+       MXS_PINCTRL_PIN(PWM0),
+       MXS_PINCTRL_PIN(PWM1),
+       MXS_PINCTRL_PIN(PWM2),
+       MXS_PINCTRL_PIN(SAIF0_MCLK),
+       MXS_PINCTRL_PIN(SAIF0_LRCLK),
+       MXS_PINCTRL_PIN(SAIF0_BITCLK),
+       MXS_PINCTRL_PIN(SAIF0_SDATA0),
+       MXS_PINCTRL_PIN(I2C0_SCL),
+       MXS_PINCTRL_PIN(I2C0_SDA),
+       MXS_PINCTRL_PIN(SAIF1_SDATA0),
+       MXS_PINCTRL_PIN(SPDIF),
+       MXS_PINCTRL_PIN(PWM3),
+       MXS_PINCTRL_PIN(PWM4),
+       MXS_PINCTRL_PIN(LCD_RESET),
+       MXS_PINCTRL_PIN(ENET0_MDC),
+       MXS_PINCTRL_PIN(ENET0_MDIO),
+       MXS_PINCTRL_PIN(ENET0_RX_EN),
+       MXS_PINCTRL_PIN(ENET0_RXD0),
+       MXS_PINCTRL_PIN(ENET0_RXD1),
+       MXS_PINCTRL_PIN(ENET0_TX_CLK),
+       MXS_PINCTRL_PIN(ENET0_TX_EN),
+       MXS_PINCTRL_PIN(ENET0_TXD0),
+       MXS_PINCTRL_PIN(ENET0_TXD1),
+       MXS_PINCTRL_PIN(ENET0_RXD2),
+       MXS_PINCTRL_PIN(ENET0_RXD3),
+       MXS_PINCTRL_PIN(ENET0_TXD2),
+       MXS_PINCTRL_PIN(ENET0_TXD3),
+       MXS_PINCTRL_PIN(ENET0_RX_CLK),
+       MXS_PINCTRL_PIN(ENET0_COL),
+       MXS_PINCTRL_PIN(ENET0_CRS),
+       MXS_PINCTRL_PIN(ENET_CLK),
+       MXS_PINCTRL_PIN(JTAG_RTCK),
+       MXS_PINCTRL_PIN(EMI_D00),
+       MXS_PINCTRL_PIN(EMI_D01),
+       MXS_PINCTRL_PIN(EMI_D02),
+       MXS_PINCTRL_PIN(EMI_D03),
+       MXS_PINCTRL_PIN(EMI_D04),
+       MXS_PINCTRL_PIN(EMI_D05),
+       MXS_PINCTRL_PIN(EMI_D06),
+       MXS_PINCTRL_PIN(EMI_D07),
+       MXS_PINCTRL_PIN(EMI_D08),
+       MXS_PINCTRL_PIN(EMI_D09),
+       MXS_PINCTRL_PIN(EMI_D10),
+       MXS_PINCTRL_PIN(EMI_D11),
+       MXS_PINCTRL_PIN(EMI_D12),
+       MXS_PINCTRL_PIN(EMI_D13),
+       MXS_PINCTRL_PIN(EMI_D14),
+       MXS_PINCTRL_PIN(EMI_D15),
+       MXS_PINCTRL_PIN(EMI_ODT0),
+       MXS_PINCTRL_PIN(EMI_DQM0),
+       MXS_PINCTRL_PIN(EMI_ODT1),
+       MXS_PINCTRL_PIN(EMI_DQM1),
+       MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
+       MXS_PINCTRL_PIN(EMI_CLK),
+       MXS_PINCTRL_PIN(EMI_DQS0),
+       MXS_PINCTRL_PIN(EMI_DQS1),
+       MXS_PINCTRL_PIN(EMI_DDR_OPEN),
+       MXS_PINCTRL_PIN(EMI_A00),
+       MXS_PINCTRL_PIN(EMI_A01),
+       MXS_PINCTRL_PIN(EMI_A02),
+       MXS_PINCTRL_PIN(EMI_A03),
+       MXS_PINCTRL_PIN(EMI_A04),
+       MXS_PINCTRL_PIN(EMI_A05),
+       MXS_PINCTRL_PIN(EMI_A06),
+       MXS_PINCTRL_PIN(EMI_A07),
+       MXS_PINCTRL_PIN(EMI_A08),
+       MXS_PINCTRL_PIN(EMI_A09),
+       MXS_PINCTRL_PIN(EMI_A10),
+       MXS_PINCTRL_PIN(EMI_A11),
+       MXS_PINCTRL_PIN(EMI_A12),
+       MXS_PINCTRL_PIN(EMI_A13),
+       MXS_PINCTRL_PIN(EMI_A14),
+       MXS_PINCTRL_PIN(EMI_BA0),
+       MXS_PINCTRL_PIN(EMI_BA1),
+       MXS_PINCTRL_PIN(EMI_BA2),
+       MXS_PINCTRL_PIN(EMI_CASN),
+       MXS_PINCTRL_PIN(EMI_RASN),
+       MXS_PINCTRL_PIN(EMI_WEN),
+       MXS_PINCTRL_PIN(EMI_CE0N),
+       MXS_PINCTRL_PIN(EMI_CE1N),
+       MXS_PINCTRL_PIN(EMI_CKE),
+};
+
+static struct mxs_regs imx28_regs = {
+       .muxsel = 0x100,
+       .drive = 0x300,
+       .pull = 0x600,
+};
+
+static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
+       .regs = &imx28_regs,
+       .pins = imx28_pins,
+       .npins = ARRAY_SIZE(imx28_pins),
+};
+
+static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
+{
+       return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
+}
+
+static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
+       { .compatible = "fsl,imx28-pinctrl", },
+       { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
+
+static struct platform_driver imx28_pinctrl_driver = {
+       .driver = {
+               .name = "imx28-pinctrl",
+               .owner = THIS_MODULE,
+               .of_match_table = imx28_pinctrl_of_match,
+       },
+       .probe = imx28_pinctrl_probe,
+       .remove = __devexit_p(mxs_pinctrl_remove),
+};
+
+static int __init imx28_pinctrl_init(void)
+{
+       return platform_driver_register(&imx28_pinctrl_driver);
+}
+arch_initcall(imx28_pinctrl_init);
+
+static void __exit imx28_pinctrl_exit(void)
+{
+       platform_driver_unregister(&imx28_pinctrl_driver);
+}
+module_exit(imx28_pinctrl_exit);
+
+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
+MODULE_LICENSE("GPL v2");

diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
new file mode 100644 (file)
index 0000000..7737d4d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -0,0 +1,2331 @@
+/*
+ * imx6q pinctrl driver based on imx pinmux core
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro, Inc.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx6q_pads {
+       MX6Q_PAD_SD2_DAT1 = 0,
+       MX6Q_PAD_SD2_DAT2 = 1,
+       MX6Q_PAD_SD2_DAT0 = 2,
+       MX6Q_PAD_RGMII_TXC = 3,
+       MX6Q_PAD_RGMII_TD0 = 4,
+       MX6Q_PAD_RGMII_TD1 = 5,
+       MX6Q_PAD_RGMII_TD2 = 6,
+       MX6Q_PAD_RGMII_TD3 = 7,
+       MX6Q_PAD_RGMII_RX_CTL = 8,
+       MX6Q_PAD_RGMII_RD0 = 9,
+       MX6Q_PAD_RGMII_TX_CTL = 10,
+       MX6Q_PAD_RGMII_RD1 = 11,
+       MX6Q_PAD_RGMII_RD2 = 12,
+       MX6Q_PAD_RGMII_RD3 = 13,
+       MX6Q_PAD_RGMII_RXC = 14,
+       MX6Q_PAD_EIM_A25 = 15,
+       MX6Q_PAD_EIM_EB2 = 16,
+       MX6Q_PAD_EIM_D16 = 17,
+       MX6Q_PAD_EIM_D17 = 18,
+       MX6Q_PAD_EIM_D18 = 19,
+       MX6Q_PAD_EIM_D19 = 20,
+       MX6Q_PAD_EIM_D20 = 21,
+       MX6Q_PAD_EIM_D21 = 22,
+       MX6Q_PAD_EIM_D22 = 23,
+       MX6Q_PAD_EIM_D23 = 24,
+       MX6Q_PAD_EIM_EB3 = 25,
+       MX6Q_PAD_EIM_D24 = 26,
+       MX6Q_PAD_EIM_D25 = 27,
+       MX6Q_PAD_EIM_D26 = 28,
+       MX6Q_PAD_EIM_D27 = 29,
+       MX6Q_PAD_EIM_D28 = 30,
+       MX6Q_PAD_EIM_D29 = 31,
+       MX6Q_PAD_EIM_D30 = 32,
+       MX6Q_PAD_EIM_D31 = 33,
+       MX6Q_PAD_EIM_A24 = 34,
+       MX6Q_PAD_EIM_A23 = 35,
+       MX6Q_PAD_EIM_A22 = 36,
+       MX6Q_PAD_EIM_A21 = 37,
+       MX6Q_PAD_EIM_A20 = 38,
+       MX6Q_PAD_EIM_A19 = 39,
+       MX6Q_PAD_EIM_A18 = 40,
+       MX6Q_PAD_EIM_A17 = 41,
+       MX6Q_PAD_EIM_A16 = 42,
+       MX6Q_PAD_EIM_CS0 = 43,
+       MX6Q_PAD_EIM_CS1 = 44,
+       MX6Q_PAD_EIM_OE = 45,
+       MX6Q_PAD_EIM_RW = 46,
+       MX6Q_PAD_EIM_LBA = 47,
+       MX6Q_PAD_EIM_EB0 = 48,
+       MX6Q_PAD_EIM_EB1 = 49,
+       MX6Q_PAD_EIM_DA0 = 50,
+       MX6Q_PAD_EIM_DA1 = 51,
+       MX6Q_PAD_EIM_DA2 = 52,
+       MX6Q_PAD_EIM_DA3 = 53,
+       MX6Q_PAD_EIM_DA4 = 54,
+       MX6Q_PAD_EIM_DA5 = 55,
+       MX6Q_PAD_EIM_DA6 = 56,
+       MX6Q_PAD_EIM_DA7 = 57,
+       MX6Q_PAD_EIM_DA8 = 58,
+       MX6Q_PAD_EIM_DA9 = 59,
+       MX6Q_PAD_EIM_DA10 = 60,
+       MX6Q_PAD_EIM_DA11 = 61,
+       MX6Q_PAD_EIM_DA12 = 62,
+       MX6Q_PAD_EIM_DA13 = 63,
+       MX6Q_PAD_EIM_DA14 = 64,
+       MX6Q_PAD_EIM_DA15 = 65,
+       MX6Q_PAD_EIM_WAIT = 66,
+       MX6Q_PAD_EIM_BCLK = 67,
+       MX6Q_PAD_DI0_DISP_CLK = 68,
+       MX6Q_PAD_DI0_PIN15 = 69,
+       MX6Q_PAD_DI0_PIN2 = 70,
+       MX6Q_PAD_DI0_PIN3 = 71,
+       MX6Q_PAD_DI0_PIN4 = 72,
+       MX6Q_PAD_DISP0_DAT0 = 73,
+       MX6Q_PAD_DISP0_DAT1 = 74,
+       MX6Q_PAD_DISP0_DAT2 = 75,
+       MX6Q_PAD_DISP0_DAT3 = 76,
+       MX6Q_PAD_DISP0_DAT4 = 77,
+       MX6Q_PAD_DISP0_DAT5 = 78,
+       MX6Q_PAD_DISP0_DAT6 = 79,
+       MX6Q_PAD_DISP0_DAT7 = 80,
+       MX6Q_PAD_DISP0_DAT8 = 81,
+       MX6Q_PAD_DISP0_DAT9 = 82,
+       MX6Q_PAD_DISP0_DAT10 = 83,
+       MX6Q_PAD_DISP0_DAT11 = 84,
+       MX6Q_PAD_DISP0_DAT12 = 85,
+       MX6Q_PAD_DISP0_DAT13 = 86,
+       MX6Q_PAD_DISP0_DAT14 = 87,
+       MX6Q_PAD_DISP0_DAT15 = 88,
+       MX6Q_PAD_DISP0_DAT16 = 89,
+       MX6Q_PAD_DISP0_DAT17 = 90,
+       MX6Q_PAD_DISP0_DAT18 = 91,
+       MX6Q_PAD_DISP0_DAT19 = 92,
+       MX6Q_PAD_DISP0_DAT20 = 93,
+       MX6Q_PAD_DISP0_DAT21 = 94,
+       MX6Q_PAD_DISP0_DAT22 = 95,
+       MX6Q_PAD_DISP0_DAT23 = 96,
+       MX6Q_PAD_ENET_MDIO = 97,
+       MX6Q_PAD_ENET_REF_CLK = 98,
+       MX6Q_PAD_ENET_RX_ER = 99,
+       MX6Q_PAD_ENET_CRS_DV = 100,
+       MX6Q_PAD_ENET_RXD1 = 101,
+       MX6Q_PAD_ENET_RXD0 = 102,
+       MX6Q_PAD_ENET_TX_EN = 103,
+       MX6Q_PAD_ENET_TXD1 = 104,
+       MX6Q_PAD_ENET_TXD0 = 105,
+       MX6Q_PAD_ENET_MDC = 106,
+       MX6Q_PAD_DRAM_D40 = 107,
+       MX6Q_PAD_DRAM_D41 = 108,
+       MX6Q_PAD_DRAM_D42 = 109,
+       MX6Q_PAD_DRAM_D43 = 110,
+       MX6Q_PAD_DRAM_D44 = 111,
+       MX6Q_PAD_DRAM_D45 = 112,
+       MX6Q_PAD_DRAM_D46 = 113,
+       MX6Q_PAD_DRAM_D47 = 114,
+       MX6Q_PAD_DRAM_SDQS5 = 115,
+       MX6Q_PAD_DRAM_DQM5 = 116,
+       MX6Q_PAD_DRAM_D32 = 117,
+       MX6Q_PAD_DRAM_D33 = 118,
+       MX6Q_PAD_DRAM_D34 = 119,
+       MX6Q_PAD_DRAM_D35 = 120,
+       MX6Q_PAD_DRAM_D36 = 121,
+       MX6Q_PAD_DRAM_D37 = 122,
+       MX6Q_PAD_DRAM_D38 = 123,
+       MX6Q_PAD_DRAM_D39 = 124,
+       MX6Q_PAD_DRAM_DQM4 = 125,
+       MX6Q_PAD_DRAM_SDQS4 = 126,
+       MX6Q_PAD_DRAM_D24 = 127,
+       MX6Q_PAD_DRAM_D25 = 128,
+       MX6Q_PAD_DRAM_D26 = 129,
+       MX6Q_PAD_DRAM_D27 = 130,
+       MX6Q_PAD_DRAM_D28 = 131,
+       MX6Q_PAD_DRAM_D29 = 132,
+       MX6Q_PAD_DRAM_SDQS3 = 133,
+       MX6Q_PAD_DRAM_D30 = 134,
+       MX6Q_PAD_DRAM_D31 = 135,
+       MX6Q_PAD_DRAM_DQM3 = 136,
+       MX6Q_PAD_DRAM_D16 = 137,
+       MX6Q_PAD_DRAM_D17 = 138,
+       MX6Q_PAD_DRAM_D18 = 139,
+       MX6Q_PAD_DRAM_D19 = 140,
+       MX6Q_PAD_DRAM_D20 = 141,
+       MX6Q_PAD_DRAM_D21 = 142,
+       MX6Q_PAD_DRAM_D22 = 143,
+       MX6Q_PAD_DRAM_SDQS2 = 144,
+       MX6Q_PAD_DRAM_D23 = 145,
+       MX6Q_PAD_DRAM_DQM2 = 146,
+       MX6Q_PAD_DRAM_A0 = 147,
+       MX6Q_PAD_DRAM_A1 = 148,
+       MX6Q_PAD_DRAM_A2 = 149,
+       MX6Q_PAD_DRAM_A3 = 150,
+       MX6Q_PAD_DRAM_A4 = 151,
+       MX6Q_PAD_DRAM_A5 = 152,
+       MX6Q_PAD_DRAM_A6 = 153,
+       MX6Q_PAD_DRAM_A7 = 154,
+       MX6Q_PAD_DRAM_A8 = 155,
+       MX6Q_PAD_DRAM_A9 = 156,
+       MX6Q_PAD_DRAM_A10 = 157,
+       MX6Q_PAD_DRAM_A11 = 158,
+       MX6Q_PAD_DRAM_A12 = 159,
+       MX6Q_PAD_DRAM_A13 = 160,
+       MX6Q_PAD_DRAM_A14 = 161,
+       MX6Q_PAD_DRAM_A15 = 162,
+       MX6Q_PAD_DRAM_CAS = 163,
+       MX6Q_PAD_DRAM_CS0 = 164,
+       MX6Q_PAD_DRAM_CS1 = 165,
+       MX6Q_PAD_DRAM_RAS = 166,
+       MX6Q_PAD_DRAM_RESET = 167,
+       MX6Q_PAD_DRAM_SDBA0 = 168,
+       MX6Q_PAD_DRAM_SDBA1 = 169,
+       MX6Q_PAD_DRAM_SDCLK_0 = 170,
+       MX6Q_PAD_DRAM_SDBA2 = 171,
+       MX6Q_PAD_DRAM_SDCKE0 = 172,
+       MX6Q_PAD_DRAM_SDCLK_1 = 173,
+       MX6Q_PAD_DRAM_SDCKE1 = 174,
+       MX6Q_PAD_DRAM_SDODT0 = 175,
+       MX6Q_PAD_DRAM_SDODT1 = 176,
+       MX6Q_PAD_DRAM_SDWE = 177,
+       MX6Q_PAD_DRAM_D0 = 178,
+       MX6Q_PAD_DRAM_D1 = 179,
+       MX6Q_PAD_DRAM_D2 = 180,
+       MX6Q_PAD_DRAM_D3 = 181,
+       MX6Q_PAD_DRAM_D4 = 182,
+       MX6Q_PAD_DRAM_D5 = 183,
+       MX6Q_PAD_DRAM_SDQS0 = 184,
+       MX6Q_PAD_DRAM_D6 = 185,
+       MX6Q_PAD_DRAM_D7 = 186,
+       MX6Q_PAD_DRAM_DQM0 = 187,
+       MX6Q_PAD_DRAM_D8 = 188,
+       MX6Q_PAD_DRAM_D9 = 189,
+       MX6Q_PAD_DRAM_D10 = 190,
+       MX6Q_PAD_DRAM_D11 = 191,
+       MX6Q_PAD_DRAM_D12 = 192,
+       MX6Q_PAD_DRAM_D13 = 193,
+       MX6Q_PAD_DRAM_D14 = 194,
+       MX6Q_PAD_DRAM_SDQS1 = 195,
+       MX6Q_PAD_DRAM_D15 = 196,
+       MX6Q_PAD_DRAM_DQM1 = 197,
+       MX6Q_PAD_DRAM_D48 = 198,
+       MX6Q_PAD_DRAM_D49 = 199,
+       MX6Q_PAD_DRAM_D50 = 200,
+       MX6Q_PAD_DRAM_D51 = 201,
+       MX6Q_PAD_DRAM_D52 = 202,
+       MX6Q_PAD_DRAM_D53 = 203,
+       MX6Q_PAD_DRAM_D54 = 204,
+       MX6Q_PAD_DRAM_D55 = 205,
+       MX6Q_PAD_DRAM_SDQS6 = 206,
+       MX6Q_PAD_DRAM_DQM6 = 207,
+       MX6Q_PAD_DRAM_D56 = 208,
+       MX6Q_PAD_DRAM_SDQS7 = 209,
+       MX6Q_PAD_DRAM_D57 = 210,
+       MX6Q_PAD_DRAM_D58 = 211,
+       MX6Q_PAD_DRAM_D59 = 212,
+       MX6Q_PAD_DRAM_D60 = 213,
+       MX6Q_PAD_DRAM_DQM7 = 214,
+       MX6Q_PAD_DRAM_D61 = 215,
+       MX6Q_PAD_DRAM_D62 = 216,
+       MX6Q_PAD_DRAM_D63 = 217,
+       MX6Q_PAD_KEY_COL0 = 218,
+       MX6Q_PAD_KEY_ROW0 = 219,
+       MX6Q_PAD_KEY_COL1 = 220,
+       MX6Q_PAD_KEY_ROW1 = 221,
+       MX6Q_PAD_KEY_COL2 = 222,
+       MX6Q_PAD_KEY_ROW2 = 223,
+       MX6Q_PAD_KEY_COL3 = 224,
+       MX6Q_PAD_KEY_ROW3 = 225,
+       MX6Q_PAD_KEY_COL4 = 226,
+       MX6Q_PAD_KEY_ROW4 = 227,
+       MX6Q_PAD_GPIO_0 = 228,
+       MX6Q_PAD_GPIO_1 = 229,
+       MX6Q_PAD_GPIO_9 = 230,
+       MX6Q_PAD_GPIO_3 = 231,
+       MX6Q_PAD_GPIO_6 = 232,
+       MX6Q_PAD_GPIO_2 = 233,
+       MX6Q_PAD_GPIO_4 = 234,
+       MX6Q_PAD_GPIO_5 = 235,
+       MX6Q_PAD_GPIO_7 = 236,
+       MX6Q_PAD_GPIO_8 = 237,
+       MX6Q_PAD_GPIO_16 = 238,
+       MX6Q_PAD_GPIO_17 = 239,
+       MX6Q_PAD_GPIO_18 = 240,
+       MX6Q_PAD_GPIO_19 = 241,
+       MX6Q_PAD_CSI0_PIXCLK = 242,
+       MX6Q_PAD_CSI0_MCLK = 243,
+       MX6Q_PAD_CSI0_DATA_EN = 244,
+       MX6Q_PAD_CSI0_VSYNC = 245,
+       MX6Q_PAD_CSI0_DAT4 = 246,
+       MX6Q_PAD_CSI0_DAT5 = 247,
+       MX6Q_PAD_CSI0_DAT6 = 248,
+       MX6Q_PAD_CSI0_DAT7 = 249,
+       MX6Q_PAD_CSI0_DAT8 = 250,
+       MX6Q_PAD_CSI0_DAT9 = 251,
+       MX6Q_PAD_CSI0_DAT10 = 252,
+       MX6Q_PAD_CSI0_DAT11 = 253,
+       MX6Q_PAD_CSI0_DAT12 = 254,
+       MX6Q_PAD_CSI0_DAT13 = 255,
+       MX6Q_PAD_CSI0_DAT14 = 256,
+       MX6Q_PAD_CSI0_DAT15 = 257,
+       MX6Q_PAD_CSI0_DAT16 = 258,
+       MX6Q_PAD_CSI0_DAT17 = 259,
+       MX6Q_PAD_CSI0_DAT18 = 260,
+       MX6Q_PAD_CSI0_DAT19 = 261,
+       MX6Q_PAD_JTAG_TMS = 262,
+       MX6Q_PAD_JTAG_MOD = 263,
+       MX6Q_PAD_JTAG_TRSTB = 264,
+       MX6Q_PAD_JTAG_TDI = 265,
+       MX6Q_PAD_JTAG_TCK = 266,
+       MX6Q_PAD_JTAG_TDO = 267,
+       MX6Q_PAD_LVDS1_TX3_P = 268,
+       MX6Q_PAD_LVDS1_TX2_P = 269,
+       MX6Q_PAD_LVDS1_CLK_P = 270,
+       MX6Q_PAD_LVDS1_TX1_P = 271,
+       MX6Q_PAD_LVDS1_TX0_P = 272,
+       MX6Q_PAD_LVDS0_TX3_P = 273,
+       MX6Q_PAD_LVDS0_CLK_P = 274,
+       MX6Q_PAD_LVDS0_TX2_P = 275,
+       MX6Q_PAD_LVDS0_TX1_P = 276,
+       MX6Q_PAD_LVDS0_TX0_P = 277,
+       MX6Q_PAD_TAMPER = 278,
+       MX6Q_PAD_PMIC_ON_REQ = 279,
+       MX6Q_PAD_PMIC_STBY_REQ = 280,
+       MX6Q_PAD_POR_B = 281,
+       MX6Q_PAD_BOOT_MODE1 = 282,
+       MX6Q_PAD_RESET_IN_B = 283,
+       MX6Q_PAD_BOOT_MODE0 = 284,
+       MX6Q_PAD_TEST_MODE = 285,
+       MX6Q_PAD_SD3_DAT7 = 286,
+       MX6Q_PAD_SD3_DAT6 = 287,
+       MX6Q_PAD_SD3_DAT5 = 288,
+       MX6Q_PAD_SD3_DAT4 = 289,
+       MX6Q_PAD_SD3_CMD = 290,
+       MX6Q_PAD_SD3_CLK = 291,
+       MX6Q_PAD_SD3_DAT0 = 292,
+       MX6Q_PAD_SD3_DAT1 = 293,
+       MX6Q_PAD_SD3_DAT2 = 294,
+       MX6Q_PAD_SD3_DAT3 = 295,
+       MX6Q_PAD_SD3_RST = 296,
+       MX6Q_PAD_NANDF_CLE = 297,
+       MX6Q_PAD_NANDF_ALE = 298,
+       MX6Q_PAD_NANDF_WP_B = 299,
+       MX6Q_PAD_NANDF_RB0 = 300,
+       MX6Q_PAD_NANDF_CS0 = 301,
+       MX6Q_PAD_NANDF_CS1 = 302,
+       MX6Q_PAD_NANDF_CS2 = 303,
+       MX6Q_PAD_NANDF_CS3 = 304,
+       MX6Q_PAD_SD4_CMD = 305,
+       MX6Q_PAD_SD4_CLK = 306,
+       MX6Q_PAD_NANDF_D0 = 307,
+       MX6Q_PAD_NANDF_D1 = 308,
+       MX6Q_PAD_NANDF_D2 = 309,
+       MX6Q_PAD_NANDF_D3 = 310,
+       MX6Q_PAD_NANDF_D4 = 311,
+       MX6Q_PAD_NANDF_D5 = 312,
+       MX6Q_PAD_NANDF_D6 = 313,
+       MX6Q_PAD_NANDF_D7 = 314,
+       MX6Q_PAD_SD4_DAT0 = 315,
+       MX6Q_PAD_SD4_DAT1 = 316,
+       MX6Q_PAD_SD4_DAT2 = 317,
+       MX6Q_PAD_SD4_DAT3 = 318,
+       MX6Q_PAD_SD4_DAT4 = 319,
+       MX6Q_PAD_SD4_DAT5 = 320,
+       MX6Q_PAD_SD4_DAT6 = 321,
+       MX6Q_PAD_SD4_DAT7 = 322,
+       MX6Q_PAD_SD1_DAT1 = 323,
+       MX6Q_PAD_SD1_DAT0 = 324,
+       MX6Q_PAD_SD1_DAT3 = 325,
+       MX6Q_PAD_SD1_CMD = 326,
+       MX6Q_PAD_SD1_DAT2 = 327,
+       MX6Q_PAD_SD1_CLK = 328,
+       MX6Q_PAD_SD2_CLK = 329,
+       MX6Q_PAD_SD2_CMD = 330,
+       MX6Q_PAD_SD2_DAT3 = 331,
+};
+
+/* imx6q register maps */
+static struct imx_pin_reg imx6q_pin_regs[] = {
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
+       IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
+       IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
+       IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
+       IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
+       IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
+       IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
+       IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
+       IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
+       IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
+       IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
+       IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
+       IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
+       IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
+       IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
+       IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
+       IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+       IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
+       IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
+       IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
+       IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
+       IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
+       IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
+       IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
+       IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
+       IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
+       IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
+       IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
+       IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
+       IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
+       IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
+       IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
+       IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
+       IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
+       IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
+       IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
+       IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
+       IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
+       IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
+       IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
+       IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
+       IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
+       IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
+       IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
+       IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
+       IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
+       IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
+       IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
+       IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
+       IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
+       IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
+       IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
+       IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
+       IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
+       IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
+       IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
+       IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
+       IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
+       IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
+       IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
+       IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
+       IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
+       IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
+       IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
+       IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
+       IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
+       IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
+       IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
+       IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
+       IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
+       IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
+       IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
+       IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
+       IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
+       IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
+       IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
+       IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
+       IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
+       IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
+       IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
+       IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
+};
+
+static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
+       .pins = imx6q_pinctrl_pads,
+       .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
+       .pin_regs = imx6q_pin_regs,
+       .npin_regs = ARRAY_SIZE(imx6q_pin_regs),
+};
+
+static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = {
+       { .compatible = "fsl,imx6q-iomuxc", },
+       { /* sentinel */ }
+};
+
+static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev)
+{
+       return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
+}
+
+static struct platform_driver imx6q_pinctrl_driver = {
+       .driver = {
+               .name = "imx6q-pinctrl",
+               .owner = THIS_MODULE,
+               .of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
+       },
+       .probe = imx6q_pinctrl_probe,
+       .remove = __devexit_p(imx_pinctrl_remove),
+};
+
+static int __init imx6q_pinctrl_init(void)
+{
+       return platform_driver_register(&imx6q_pinctrl_driver);
+}
+arch_initcall(imx6q_pinctrl_init);
+
+static void __exit imx6q_pinctrl_exit(void)
+{
+       platform_driver_unregister(&imx6q_pinctrl_driver);
+}
+module_exit(imx6q_pinctrl_exit);
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
+MODULE_LICENSE("GPL v2");

diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
new file mode 100644 (file)
index 0000000..93cd959
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -0,0 +1,508 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include "core.h"
+#include "pinctrl-mxs.h"
+
+#define SUFFIX_LEN     4
+
+struct mxs_pinctrl_data {
+       struct device *dev;
+       struct pinctrl_dev *pctl;
+       void __iomem *base;
+       struct mxs_pinctrl_soc_data *soc;
+};
+
+static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+       return d->soc->ngroups;
+}
+
+static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
+                                     unsigned group)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+       return d->soc->groups[group].name;
+}
+
+static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
+                             const unsigned **pins, unsigned *num_pins)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+       *pins = d->soc->groups[group].pins;
+       *num_pins = d->soc->groups[group].npins;
+
+       return 0;
+}
+
+static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+                            unsigned offset)
+{
+       seq_printf(s, " %s", dev_name(pctldev->dev));
+}
+
+static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
+                             struct device_node *np,
+                             struct pinctrl_map **map, unsigned *num_maps)
+{
+       struct pinctrl_map *new_map;
+       char *group;
+       unsigned new_num;
+       unsigned long config = 0;
+       unsigned long *pconfig;
+       int length = strlen(np->name) + SUFFIX_LEN;
+       u32 val;
+       int ret;
+
+       ret = of_property_read_u32(np, "fsl,drive-strength", &val);
+       if (!ret)
+               config = val | MA_PRESENT;
+       ret = of_property_read_u32(np, "fsl,voltage", &val);
+       if (!ret)
+               config |= val << VOL_SHIFT | VOL_PRESENT;
+       ret = of_property_read_u32(np, "fsl,pull-up", &val);
+       if (!ret)
+               config |= val << PULL_SHIFT | PULL_PRESENT;
+
+       new_num = config ? 2 : 1;
+       new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
+       if (!new_map)
+               return -ENOMEM;
+
+       new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+       new_map[0].data.mux.function = np->name;
+
+       /* Compose group name */
+       group = kzalloc(length, GFP_KERNEL);
+       if (!group)
+               return -ENOMEM;
+       of_property_read_u32(np, "reg", &val);
+       snprintf(group, length, "%s.%d", np->name, val);
+       new_map[0].data.mux.group = group;
+
+       if (config) {
+               pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
+               if (!pconfig) {
+                       ret = -ENOMEM;
+                       goto free;
+               }
+
+               new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+               new_map[1].data.configs.group_or_pin = group;
+               new_map[1].data.configs.configs = pconfig;
+               new_map[1].data.configs.num_configs = 1;
+       }
+
+       *map = new_map;
+       *num_maps = new_num;
+
+       return 0;
+
+free:
+       kfree(new_map);
+       return ret;
+}
+
+static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
+                           struct pinctrl_map *map, unsigned num_maps)
+{
+       int i;
+
+       for (i = 0; i < num_maps; i++) {
+               if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
+                       kfree(map[i].data.mux.group);
+               if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+                       kfree(map[i].data.configs.configs);
+       }
+
+       kfree(map);
+}
+
+static struct pinctrl_ops mxs_pinctrl_ops = {
+       .get_groups_count = mxs_get_groups_count,
+       .get_group_name = mxs_get_group_name,
+       .get_group_pins = mxs_get_group_pins,
+       .pin_dbg_show = mxs_pin_dbg_show,
+       .dt_node_to_map = mxs_dt_node_to_map,
+       .dt_free_map = mxs_dt_free_map,
+};
+
+static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+       return d->soc->nfunctions;
+}
+
+static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+                                            unsigned function)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+       return d->soc->functions[function].name;
+}
+
+static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+                                      unsigned group,
+                                      const char * const **groups,
+                                      unsigned * const num_groups)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+       *groups = d->soc->functions[group].groups;
+       *num_groups = d->soc->functions[group].ngroups;
+
+       return 0;
+}
+
+static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
+                             unsigned group)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+       struct mxs_group *g = &d->soc->groups[group];
+       void __iomem *reg;
+       u8 bank, shift;
+       u16 pin;
+       int i;
+
+       for (i = 0; i < g->npins; i++) {
+               bank = PINID_TO_BANK(g->pins[i]);
+               pin = PINID_TO_PIN(g->pins[i]);
+               reg = d->base + d->soc->regs->muxsel;
+               reg += bank * 0x20 + pin / 16 * 0x10;
+               shift = pin % 16 * 2;
+
+               writel(0x3 << shift, reg + CLR);
+               writel(g->muxsel[i] << shift, reg + SET);
+       }
+
+       return 0;
+}
+
+static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev,
+                               unsigned function, unsigned group)
+{
+       /* Nothing to do here */
+}
+
+static struct pinmux_ops mxs_pinmux_ops = {
+       .get_functions_count = mxs_pinctrl_get_funcs_count,
+       .get_function_name = mxs_pinctrl_get_func_name,
+       .get_function_groups = mxs_pinctrl_get_func_groups,
+       .enable = mxs_pinctrl_enable,
+       .disable = mxs_pinctrl_disable,
+};
+
+static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
+                          unsigned pin, unsigned long *config)
+{
+       return -ENOTSUPP;
+}
+
+static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
+                          unsigned pin, unsigned long config)
+{
+       return -ENOTSUPP;
+}
+
+static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
+                                unsigned group, unsigned long *config)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+
+       *config = d->soc->groups[group].config;
+
+       return 0;
+}
+
+static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
+                                unsigned group, unsigned long config)
+{
+       struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
+       struct mxs_group *g = &d->soc->groups[group];
+       void __iomem *reg;
+       u8 ma, vol, pull, bank, shift;
+       u16 pin;
+       int i;
+
+       ma = CONFIG_TO_MA(config);
+       vol = CONFIG_TO_VOL(config);
+       pull = CONFIG_TO_PULL(config);
+
+       for (i = 0; i < g->npins; i++) {
+               bank = PINID_TO_BANK(g->pins[i]);
+               pin = PINID_TO_PIN(g->pins[i]);
+
+               /* drive */
+               reg = d->base + d->soc->regs->drive;
+               reg += bank * 0x40 + pin / 8 * 0x10;
+
+               /* mA */
+               if (config & MA_PRESENT) {
+                       shift = pin % 8 * 4;
+                       writel(0x3 << shift, reg + CLR);
+                       writel(ma << shift, reg + SET);
+               }
+
+               /* vol */
+               if (config & VOL_PRESENT) {
+                       shift = pin % 8 * 4 + 2;
+                       if (vol)
+                               writel(1 << shift, reg + SET);
+                       else
+                               writel(1 << shift, reg + CLR);
+               }
+
+               /* pull */
+               if (config & PULL_PRESENT) {
+                       reg = d->base + d->soc->regs->pull;
+                       reg += bank * 0x10;
+                       shift = pin;
+                       if (pull)
+                               writel(1 << shift, reg + SET);
+                       else
+                               writel(1 << shift, reg + CLR);
+               }
+       }
+
+       /* cache the config value for mxs_pinconf_group_get() */
+       g->config = config;
+
+       return 0;
+}
+
+static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+                                struct seq_file *s, unsigned pin)
+{
+       /* Not support */
+}
+
+static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+                                      struct seq_file *s, unsigned group)
+{
+       unsigned long config;
+
+       if (!mxs_pinconf_group_get(pctldev, group, &config))
+               seq_printf(s, "0x%lx", config);
+}
+
+struct pinconf_ops mxs_pinconf_ops = {
+       .pin_config_get = mxs_pinconf_get,
+       .pin_config_set = mxs_pinconf_set,
+       .pin_config_group_get = mxs_pinconf_group_get,
+       .pin_config_group_set = mxs_pinconf_group_set,
+       .pin_config_dbg_show = mxs_pinconf_dbg_show,
+       .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
+};
+
+static struct pinctrl_desc mxs_pinctrl_desc = {
+       .pctlops = &mxs_pinctrl_ops,
+       .pmxops = &mxs_pinmux_ops,
+       .confops = &mxs_pinconf_ops,
+       .owner = THIS_MODULE,
+};
+
+static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
+                                            struct device_node *np, int idx,
+                                            const char **out_name)
+{
+       struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
+       struct mxs_group *g = &d->soc->groups[idx];
+       struct property *prop;
+       const char *propname = "fsl,pinmux-ids";
+       char *group;
+       int length = strlen(np->name) + SUFFIX_LEN;
+       int i;
+       u32 val;
+
+       group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
+       if (!group)
+               return -ENOMEM;
+       of_property_read_u32(np, "reg", &val);
+       snprintf(group, length, "%s.%d", np->name, val);
+       g->name = group;
+
+       prop = of_find_property(np, propname, &length);
+       if (!prop)
+               return -EINVAL;
+       g->npins = length / sizeof(u32);
+
+       g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
+                              GFP_KERNEL);
+       if (!g->pins)
+               return -ENOMEM;
+
+       g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
+                                GFP_KERNEL);
+       if (!g->muxsel)
+               return -ENOMEM;
+
+       of_property_read_u32_array(np, propname, g->pins, g->npins);
+       for (i = 0; i < g->npins; i++) {
+               g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
+               g->pins[i] = MUXID_TO_PINID(g->pins[i]);
+       }
+
+       *out_name = g->name;
+
+       return 0;
+}
+
+static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
+                                         struct mxs_pinctrl_data *d)
+{
+       struct mxs_pinctrl_soc_data *soc = d->soc;
+       struct device_node *np = pdev->dev.of_node;
+       struct device_node *child;
+       struct mxs_function *f;
+       const char *fn, *fnull = "";
+       int i = 0, idxf = 0, idxg = 0;
+       int ret;
+       u32 val;
+
+       child = of_get_next_child(np, NULL);
+       if (!child) {
+               dev_err(&pdev->dev, "no group is defined\n");
+               return -ENOENT;
+       }
+
+       /* Count total functions and groups */
+       fn = fnull;
+       for_each_child_of_node(np, child) {
+               /* Skip pure pinconf node */
+               if (of_property_read_u32(child, "reg", &val))
+                       continue;
+               if (strcmp(fn, child->name)) {
+                       fn = child->name;
+                       soc->nfunctions++;
+               }
+               soc->ngroups++;
+       }
+
+       soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
+                                     sizeof(*soc->functions), GFP_KERNEL);
+       if (!soc->functions)
+               return -ENOMEM;
+
+       soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
+                                  sizeof(*soc->groups), GFP_KERNEL);
+       if (!soc->groups)
+               return -ENOMEM;
+
+       /* Count groups for each function */
+       fn = fnull;
+       f = &soc->functions[idxf];
+       for_each_child_of_node(np, child) {
+               if (of_property_read_u32(child, "reg", &val))
+                       continue;
+               if (strcmp(fn, child->name)) {
+                       f = &soc->functions[idxf++];
+                       f->name = fn = child->name;
+               }
+               f->ngroups++;
+       };
+
+       /* Get groups for each function */
+       idxf = 0;
+       fn = fnull;
+       for_each_child_of_node(np, child) {
+               if (of_property_read_u32(child, "reg", &val))
+                       continue;
+               if (strcmp(fn, child->name)) {
+                       f = &soc->functions[idxf++];
+                       f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
+                                                sizeof(*f->groups),
+                                                GFP_KERNEL);
+                       if (!f->groups)
+                               return -ENOMEM;
+                       fn = child->name;
+                       i = 0;
+               }
+               ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
+                                             &f->groups[i++]);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
+                               struct mxs_pinctrl_soc_data *soc)
+{
+       struct device_node *np = pdev->dev.of_node;
+       struct mxs_pinctrl_data *d;
+       int ret;
+
+       d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
+       if (!d)
+               return -ENOMEM;
+
+       d->dev = &pdev->dev;
+       d->soc = soc;
+
+       d->base = of_iomap(np, 0);
+       if (!d->base)
+               return -EADDRNOTAVAIL;
+
+       mxs_pinctrl_desc.pins = d->soc->pins;
+       mxs_pinctrl_desc.npins = d->soc->npins;
+       mxs_pinctrl_desc.name = dev_name(&pdev->dev);
+
+       platform_set_drvdata(pdev, d);
+
+       ret = mxs_pinctrl_probe_dt(pdev, d);
+       if (ret) {
+               dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
+               goto err;
+       }
+
+       d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
+       if (!d->pctl) {
+               dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
+               ret = -EINVAL;
+               goto err;
+       }
+
+       return 0;
+
+err:
+       iounmap(d->base);
+       return ret;
+}
+EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
+
+int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
+{
+       struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
+
+       pinctrl_unregister(d->pctl);
+       iounmap(d->base);
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);

diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/pinctrl-mxs.h
new file mode 100644 (file)
index 0000000..fdd88d0
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __PINCTRL_MXS_H
+#define __PINCTRL_MXS_H
+
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#define SET    0x4
+#define CLR    0x8
+#define TOG    0xc
+
+#define MXS_PINCTRL_PIN(pin)   PINCTRL_PIN(pin, #pin)
+#define PINID(bank, pin)       ((bank) * 32 + (pin))
+
+/*
+ * pinmux-id bit field definitions
+ *
+ * bank:       15..12  (4)
+ * pin:                11..4   (8)
+ * muxsel:     3..0    (4)
+ */
+#define MUXID_TO_PINID(m)      PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
+#define MUXID_TO_MUXSEL(m)     ((m) & 0xf)
+
+#define PINID_TO_BANK(p)       ((p) >> 5)
+#define PINID_TO_PIN(p)                ((p) % 32)
+
+/*
+ * pin config bit field definitions
+ *
+ * pull-up:    6..5    (2)
+ * voltage:    4..3    (2)
+ * mA:         2..0    (3)
+ *
+ * MSB of each field is presence bit for the config.
+ */
+#define PULL_PRESENT           (1 << 6)
+#define PULL_SHIFT             5
+#define VOL_PRESENT            (1 << 4)
+#define VOL_SHIFT              3
+#define MA_PRESENT             (1 << 2)
+#define MA_SHIFT               0
+#define CONFIG_TO_PULL(c)      ((c) >> PULL_SHIFT & 0x1)
+#define CONFIG_TO_VOL(c)       ((c) >> VOL_SHIFT & 0x1)
+#define CONFIG_TO_MA(c)                ((c) >> MA_SHIFT & 0x3)
+
+struct mxs_function {
+       const char *name;
+       const char **groups;
+       unsigned ngroups;
+};
+
+struct mxs_group {
+       const char *name;
+       unsigned int *pins;
+       unsigned npins;
+       u8 *muxsel;
+       u8 config;
+};
+
+struct mxs_regs {
+       u16 muxsel;
+       u16 drive;
+       u16 pull;
+};
+
+struct mxs_pinctrl_soc_data {
+       const struct mxs_regs *regs;
+       const struct pinctrl_pin_desc *pins;
+       unsigned npins;
+       struct mxs_function *functions;
+       unsigned nfunctions;
+       struct mxs_group *groups;
+       unsigned ngroups;
+};
+
+int mxs_pinctrl_probe(struct platform_device *pdev,
+                     struct mxs_pinctrl_soc_data *soc);
+int mxs_pinctrl_remove(struct platform_device *pdev);
+
+#endif /* __PINCTRL_MXS_H */

diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 079dce0..7644e42 100644 (file)
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -25,20 +25,18 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
        .pin_base       = 0,
 };
 
-static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector)
+static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
 {
        struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-       if (selector >= info->num_grps)
-               return -EINVAL;
-       return 0;
+
+       return info->num_grps;
 }
 
 static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
                                         unsigned selector)
 {
        struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-       if (selector >= info->num_grps)
-               return NULL;
+
        return info->grps[selector].name;
 }
 
@@ -48,25 +46,23 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
                                 unsigned *num_pins)
 {
        struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-       if (selector >= info->num_grps)
-               return -EINVAL;
+
        *pins = info->grps[selector].pins;
        *num_pins = info->grps[selector].npins;
        return 0;
 }
 
 static struct pinctrl_ops pxa3xx_pctrl_ops = {
-       .list_groups    = pxa3xx_list_groups,
+       .get_groups_count = pxa3xx_get_groups_count,
        .get_group_name = pxa3xx_get_group_name,
        .get_group_pins = pxa3xx_get_group_pins,
 };
 
-static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func)
+static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
 {
        struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-       if (func >= info->num_funcs)
-               return -EINVAL;
-       return 0;
+
+       return info->num_funcs;
 }
 
 static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
@@ -170,7 +166,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
 }
 
 static struct pinmux_ops pxa3xx_pmx_ops = {
-       .list_functions         = pxa3xx_pmx_list_func,
+       .get_functions_count    = pxa3xx_pmx_get_funcs_count,
        .get_function_name      = pxa3xx_pmx_get_func_name,
        .get_function_groups    = pxa3xx_pmx_get_groups,
        .enable                 = pxa3xx_pmx_enable,

diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 6b3534c..ba15b1a 100644 (file)
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -853,18 +853,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
        SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 };
 
-static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
 {
-       if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-               return -EINVAL;
-       return 0;
+       return ARRAY_SIZE(sirfsoc_pin_groups);
 }
 
 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
                                       unsigned selector)
 {
-       if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-               return NULL;
        return sirfsoc_pin_groups[selector].name;
 }
 
@@ -872,8 +868,6 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector
                               const unsigned **pins,
                               unsigned *num_pins)
 {
-       if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
-               return -EINVAL;
        *pins = sirfsoc_pin_groups[selector].pins;
        *num_pins = sirfsoc_pin_groups[selector].num_pins;
        return 0;
@@ -886,7 +880,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
 }
 
 static struct pinctrl_ops sirfsoc_pctrl_ops = {
-       .list_groups = sirfsoc_list_groups,
+       .get_groups_count = sirfsoc_get_groups_count,
        .get_group_name = sirfsoc_get_group_name,
        .get_group_pins = sirfsoc_get_group_pins,
        .pin_dbg_show = sirfsoc_pin_dbg_show,
@@ -1033,11 +1027,9 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector
        sirfsoc_pinmux_endisable(spmx, selector, false);
 }
 
-static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector)
+static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
 {
-       if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions))
-               return -EINVAL;
-       return 0;
+       return ARRAY_SIZE(sirfsoc_pmx_functions);
 }
 
 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
@@ -1074,9 +1066,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
 }
 
 static struct pinmux_ops sirfsoc_pinmux_ops = {
-       .list_functions = sirfsoc_pinmux_list_funcs,
        .enable = sirfsoc_pinmux_enable,
        .disable = sirfsoc_pinmux_disable,
+       .get_functions_count = sirfsoc_pinmux_get_funcs_count,
        .get_function_name = sirfsoc_pinmux_get_func_name,
        .get_function_groups = sirfsoc_pinmux_get_groups,
        .gpio_request_enable = sirfsoc_pinmux_request_gpio,

diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 9b32968..2c98fba 100644 (file)
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -23,9 +23,11 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/pinconf.h>
+#include <linux/slab.h>
 
 #include <mach/pinconf-tegra.h>
 
@@ -53,15 +55,11 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
        writel(val, pmx->regs[bank] + reg);
 }
 
-static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev,
-                                    unsigned group)
+static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 {
        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-       if (group >= pmx->soc->ngroups)
-               return -EINVAL;
-
-       return 0;
+       return pmx->soc->ngroups;
 }
 
 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -69,9 +67,6 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 {
        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-       if (group >= pmx->soc->ngroups)
-               return NULL;
-
        return pmx->soc->groups[group].name;
 }
 
@@ -82,9 +77,6 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 {
        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-       if (group >= pmx->soc->ngroups)
-               return -EINVAL;
-
        *pins = pmx->soc->groups[group].pins;
        *num_pins = pmx->soc->groups[group].npins;
 
@@ -98,22 +90,221 @@ static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
        seq_printf(s, " " DRIVER_NAME);
 }
 
+static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
+                      unsigned *num_maps, unsigned reserve)
+{
+       unsigned old_num = *reserved_maps;
+       unsigned new_num = *num_maps + reserve;
+       struct pinctrl_map *new_map;
+
+       if (old_num >= new_num)
+               return 0;
+
+       new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
+       if (!new_map)
+               return -ENOMEM;
+
+       memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
+
+       *map = new_map;
+       *reserved_maps = new_num;
+
+       return 0;
+}
+
+static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
+                      unsigned *num_maps, const char *group,
+                      const char *function)
+{
+       if (*num_maps == *reserved_maps)
+               return -ENOSPC;
+
+       (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
+       (*map)[*num_maps].data.mux.group = group;
+       (*map)[*num_maps].data.mux.function = function;
+       (*num_maps)++;
+
+       return 0;
+}
+
+static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
+                          unsigned *num_maps, const char *group,
+                          unsigned long *configs, unsigned num_configs)
+{
+       unsigned long *dup_configs;
+
+       if (*num_maps == *reserved_maps)
+               return -ENOSPC;
+
+       dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
+                             GFP_KERNEL);
+       if (!dup_configs)
+               return -ENOMEM;
+
+       (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
+       (*map)[*num_maps].data.configs.group_or_pin = group;
+       (*map)[*num_maps].data.configs.configs = dup_configs;
+       (*map)[*num_maps].data.configs.num_configs = num_configs;
+       (*num_maps)++;
+
+       return 0;
+}
+
+static int add_config(unsigned long **configs, unsigned *num_configs,
+                     unsigned long config)
+{
+       unsigned old_num = *num_configs;
+       unsigned new_num = old_num + 1;
+       unsigned long *new_configs;
+
+       new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
+                              GFP_KERNEL);
+       if (!new_configs)
+               return -ENOMEM;
+
+       new_configs[old_num] = config;
+
+       *configs = new_configs;
+       *num_configs = new_num;
+
+       return 0;
+}
+
+void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                              struct pinctrl_map *map, unsigned num_maps)
+{
+       int i;
+
+       for (i = 0; i < num_maps; i++)
+               if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
+                       kfree(map[i].data.configs.configs);
+
+       kfree(map);
+}
+
+static const struct cfg_param {
+       const char *property;
+       enum tegra_pinconf_param param;
+} cfg_params[] = {
+       {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
+       {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
+       {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
+       {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
+       {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
+       {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
+       {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
+       {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
+       {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
+       {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
+       {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
+       {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
+       {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
+};
+
+int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
+                                   struct pinctrl_map **map,
+                                   unsigned *reserved_maps,
+                                   unsigned *num_maps)
+{
+       int ret, i;
+       const char *function;
+       u32 val;
+       unsigned long config;
+       unsigned long *configs = NULL;
+       unsigned num_configs = 0;
+       unsigned reserve;
+       struct property *prop;
+       const char *group;
+
+       ret = of_property_read_string(np, "nvidia,function", &function);
+       if (ret < 0)
+               function = NULL;
+
+       for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
+               ret = of_property_read_u32(np, cfg_params[i].property, &val);
+               if (!ret) {
+                       config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
+                       ret = add_config(&configs, &num_configs, config);
+                       if (ret < 0)
+                               goto exit;
+               }
+       }
+
+       reserve = 0;
+       if (function != NULL)
+               reserve++;
+       if (num_configs)
+               reserve++;
+       ret = of_property_count_strings(np, "nvidia,pins");
+       if (ret < 0)
+               goto exit;
+       reserve *= ret;
+
+       ret = reserve_map(map, reserved_maps, num_maps, reserve);
+       if (ret < 0)
+               goto exit;
+
+       of_property_for_each_string(np, "nvidia,pins", prop, group) {
+               if (function) {
+                       ret = add_map_mux(map, reserved_maps, num_maps,
+                                         group, function);
+                       if (ret < 0)
+                               goto exit;
+               }
+
+               if (num_configs) {
+                       ret = add_map_configs(map, reserved_maps, num_maps,
+                                             group, configs, num_configs);
+                       if (ret < 0)
+                               goto exit;
+               }
+       }
+
+       ret = 0;
+
+exit:
+       kfree(configs);
+       return ret;
+}
+
+int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                struct device_node *np_config,
+                                struct pinctrl_map **map, unsigned *num_maps)
+{
+       unsigned reserved_maps;
+       struct device_node *np;
+       int ret;
+
+       reserved_maps = 0;
+       *map = NULL;
+       *num_maps = 0;
+
+       for_each_child_of_node(np_config, np) {
+               ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps,
+                                                     num_maps);
+               if (ret < 0) {
+                       tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
 static struct pinctrl_ops tegra_pinctrl_ops = {
-       .list_groups = tegra_pinctrl_list_groups,
+       .get_groups_count = tegra_pinctrl_get_groups_count,
        .get_group_name = tegra_pinctrl_get_group_name,
        .get_group_pins = tegra_pinctrl_get_group_pins,
        .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
+       .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
+       .dt_free_map = tegra_pinctrl_dt_free_map,
 };
 
-static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev,
-                                   unsigned function)
+static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 {
        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-       if (function >= pmx->soc->nfunctions)
-               return -EINVAL;
-
-       return 0;
+       return pmx->soc->nfunctions;
 }
 
 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
@@ -121,9 +312,6 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 {
        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-       if (function >= pmx->soc->nfunctions)
-               return NULL;
-
        return pmx->soc->functions[function].name;
 }
 
@@ -134,9 +322,6 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 {
        struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 
-       if (function >= pmx->soc->nfunctions)
-               return -EINVAL;
-
        *groups = pmx->soc->functions[function].groups;
        *num_groups = pmx->soc->functions[function].ngroups;
 
@@ -151,8 +336,6 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
        int i;
        u32 val;
 
-       if (group >= pmx->soc->ngroups)
-               return -EINVAL;
        g = &pmx->soc->groups[group];
 
        if (g->mux_reg < 0)
@@ -180,8 +363,6 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
        const struct tegra_pingroup *g;
        u32 val;
 
-       if (group >= pmx->soc->ngroups)
-               return;
        g = &pmx->soc->groups[group];
 
        if (g->mux_reg < 0)
@@ -194,7 +375,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
 }
 
 static struct pinmux_ops tegra_pinmux_ops = {
-       .list_functions = tegra_pinctrl_list_funcs,
+       .get_functions_count = tegra_pinctrl_get_funcs_count,
        .get_function_name = tegra_pinctrl_get_func_name,
        .get_function_groups = tegra_pinctrl_get_func_groups,
        .enable = tegra_pinctrl_enable,
@@ -324,8 +505,6 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
        s16 reg;
        u32 val, mask;
 
-       if (group >= pmx->soc->ngroups)
-               return -EINVAL;
        g = &pmx->soc->groups[group];
 
        ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
@@ -353,8 +532,6 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
        s16 reg;
        u32 val, mask;
 
-       if (group >= pmx->soc->ngroups)
-               return -EINVAL;
        g = &pmx->soc->groups[group];
 
        ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);

diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 26eb8cc..05d0299 100644 (file)
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -836,18 +836,14 @@ static const struct u300_pin_group u300_pin_groups[] = {
        },
 };
 
-static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
+static int u300_get_groups_count(struct pinctrl_dev *pctldev)
 {
-       if (selector >= ARRAY_SIZE(u300_pin_groups))
-               return -EINVAL;
-       return 0;
+       return ARRAY_SIZE(u300_pin_groups);
 }
 
 static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
                                       unsigned selector)
 {
-       if (selector >= ARRAY_SIZE(u300_pin_groups))
-               return NULL;
        return u300_pin_groups[selector].name;
 }
 
@@ -855,8 +851,6 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
                               const unsigned **pins,
                               unsigned *num_pins)
 {
-       if (selector >= ARRAY_SIZE(u300_pin_groups))
-               return -EINVAL;
        *pins = u300_pin_groups[selector].pins;
        *num_pins = u300_pin_groups[selector].num_pins;
        return 0;
@@ -869,7 +863,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 }
 
 static struct pinctrl_ops u300_pctrl_ops = {
-       .list_groups = u300_list_groups,
+       .get_groups_count = u300_get_groups_count,
        .get_group_name = u300_get_group_name,
        .get_group_pins = u300_get_group_pins,
        .pin_dbg_show = u300_pin_dbg_show,
@@ -991,11 +985,9 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
        u300_pmx_endisable(upmx, selector, false);
 }
 
-static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 {
-       if (selector >= ARRAY_SIZE(u300_pmx_functions))
-               return -EINVAL;
-       return 0;
+       return ARRAY_SIZE(u300_pmx_functions);
 }
 
 static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
@@ -1014,7 +1006,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 }
 
 static struct pinmux_ops u300_pmx_ops = {
-       .list_functions = u300_pmx_list_funcs,
+       .get_functions_count = u300_pmx_get_funcs_count,
        .get_function_name = u300_pmx_get_func_name,
        .get_function_groups = u300_pmx_get_groups,
        .enable = u300_pmx_enable,

diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 4e62783..220fa49 100644 (file)
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -33,22 +33,26 @@
 int pinmux_check_ops(struct pinctrl_dev *pctldev)
 {
        const struct pinmux_ops *ops = pctldev->desc->pmxops;
+       unsigned nfuncs;
        unsigned selector = 0;
 
        /* Check that we implement required operations */
-       if (!ops->list_functions ||
+       if (!ops ||
+           !ops->get_functions_count ||
            !ops->get_function_name ||
            !ops->get_function_groups ||
            !ops->enable ||
-           !ops->disable)
+           !ops->disable) {
+               dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
                return -EINVAL;
-
+       }
        /* Check that all functions registered have names */
-       while (ops->list_functions(pctldev, selector) >= 0) {
+       nfuncs = ops->get_functions_count(pctldev);
+       while (selector < nfuncs) {
                const char *fname = ops->get_function_name(pctldev,
                                                           selector);
                if (!fname) {
-                       pr_err("pinmux ops has no name for function%u\n",
+                       dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
                                selector);
                        return -EINVAL;
                }
@@ -85,20 +89,23 @@ static int pin_request(struct pinctrl_dev *pctldev,
        const struct pinmux_ops *ops = pctldev->desc->pmxops;
        int status = -EINVAL;
 
-       dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner);
-
        desc = pin_desc_get(pctldev, pin);
        if (desc == NULL) {
                dev_err(pctldev->dev,
-                       "pin is not registered so it cannot be requested\n");
+                       "pin %d is not registered so it cannot be requested\n",
+                       pin);
                goto out;
        }
 
+       dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
+               pin, desc->name, owner);
+
        if (gpio_range) {
                /* There's no need to support multiple GPIO requests */
                if (desc->gpio_owner) {
                        dev_err(pctldev->dev,
-                               "pin already requested\n");
+                               "pin %s already requested by %s; cannot claim for %s\n",
+                               desc->name, desc->gpio_owner, owner);
                        goto out;
                }
 
@@ -106,7 +113,8 @@ static int pin_request(struct pinctrl_dev *pctldev,
        } else {
                if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
                        dev_err(pctldev->dev,
-                               "pin already requested\n");
+                               "pin %s already requested by %s; cannot claim for %s\n",
+                               desc->name, desc->mux_owner, owner);
                        goto out;
                }
 
@@ -139,8 +147,7 @@ static int pin_request(struct pinctrl_dev *pctldev,
                status = 0;
 
        if (status) {
-               dev_err(pctldev->dev, "->request on device %s failed for pin %d\n",
-                      pctldev->desc->name, pin);
+               dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
                module_put(pctldev->owner);
        }
 
@@ -157,7 +164,7 @@ out_free_pin:
 out:
        if (status)
                dev_err(pctldev->dev, "pin-%d (%s) status %d\n",
-                      pin, owner, status);
+                       pin, owner, status);
 
        return status;
 }
@@ -287,10 +294,11 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
                                        const char *function)
 {
        const struct pinmux_ops *ops = pctldev->desc->pmxops;
+       unsigned nfuncs = ops->get_functions_count(pctldev);
        unsigned selector = 0;
 
        /* See if this pctldev has this function */
-       while (ops->list_functions(pctldev, selector) >= 0) {
+       while (selector < nfuncs) {
                const char *fname = ops->get_function_name(pctldev,
                                                           selector);
 
@@ -319,18 +327,32 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
        const unsigned *pins;
        unsigned num_pins;
 
-       setting->data.mux.func =
-               pinmux_func_name_to_selector(pctldev, map->data.mux.function);
-       if (setting->data.mux.func < 0)
-               return setting->data.mux.func;
+       if (!pmxops) {
+               dev_err(pctldev->dev, "does not support mux function\n");
+               return -EINVAL;
+       }
+
+       ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function);
+       if (ret < 0) {
+               dev_err(pctldev->dev, "invalid function %s in map table\n",
+                       map->data.mux.function);
+               return ret;
+       }
+       setting->data.mux.func = ret;
 
        ret = pmxops->get_function_groups(pctldev, setting->data.mux.func,
                                          &groups, &num_groups);
-       if (ret < 0)
+       if (ret < 0) {
+               dev_err(pctldev->dev, "can't query groups for function %s\n",
+                       map->data.mux.function);
                return ret;
-       if (!num_groups)
+       }
+       if (!num_groups) {
+               dev_err(pctldev->dev,
+                       "function %s can't be selected on any group\n",
+                       map->data.mux.function);
                return -EINVAL;
-
+       }
        if (map->data.mux.group) {
                bool found = false;
                group = map->data.mux.group;
@@ -340,15 +362,23 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
                                break;
                        }
                }
-               if (!found)
+               if (!found) {
+                       dev_err(pctldev->dev,
+                               "invalid group \"%s\" for function \"%s\"\n",
+                               group, map->data.mux.function);
                        return -EINVAL;
+               }
        } else {
                group = groups[0];
        }
 
-       setting->data.mux.group = pinctrl_get_group_selector(pctldev, group);
-       if (setting->data.mux.group < 0)
-               return setting->data.mux.group;
+       ret = pinctrl_get_group_selector(pctldev, group);
+       if (ret < 0) {
+               dev_err(pctldev->dev, "invalid group %s in map table\n",
+                       map->data.mux.group);
+               return ret;
+       }
+       setting->data.mux.group = ret;
 
        ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins,
                                      &num_pins);
@@ -364,7 +394,7 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
                ret = pin_request(pctldev, pins[i], map->dev_name, NULL);
                if (ret) {
                        dev_err(pctldev->dev,
-                               "could not get request pin %d on device %s\n",
+                               "could not request pin %d on device %s\n",
                                pins[i], pinctrl_dev_get_name(pctldev));
                        /* On error release all taken pins */
                        i--; /* this pin just failed */
@@ -477,11 +507,15 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
 {
        struct pinctrl_dev *pctldev = s->private;
        const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
+       unsigned nfuncs;
        unsigned func_selector = 0;
 
-       mutex_lock(&pinctrl_mutex);
+       if (!pmxops)
+               return 0;
 
-       while (pmxops->list_functions(pctldev, func_selector) >= 0) {
+       mutex_lock(&pinctrl_mutex);
+       nfuncs = pmxops->get_functions_count(pctldev);
+       while (func_selector < nfuncs) {
                const char *func = pmxops->get_function_name(pctldev,
                                                          func_selector);
                const char * const *groups;
@@ -515,6 +549,9 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
        const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
        unsigned i, pin;
 
+       if (!pmxops)
+               return 0;
+
        seq_puts(s, "Pinmux settings per pin\n");
        seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
 

diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
index 6fc4700..d1a98b1 100644 (file)
--- a/drivers/pinctrl/pinmux.h
+++ b/drivers/pinctrl/pinmux.h
@@ -31,12 +31,6 @@ void pinmux_free_setting(struct pinctrl_setting const *setting);
 int pinmux_enable_setting(struct pinctrl_setting const *setting);
 void pinmux_disable_setting(struct pinctrl_setting const *setting);
 
-void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
-void pinmux_show_setting(struct seq_file *s,
-                        struct pinctrl_setting const *setting);
-void pinmux_init_device_debugfs(struct dentry *devroot,
-                               struct pinctrl_dev *pctldev);
-
 #else
 
 static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
@@ -89,6 +83,18 @@ static inline void pinmux_disable_setting(
 {
 }
 
+#endif
+
+#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
+
+void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
+void pinmux_show_setting(struct seq_file *s,
+                        struct pinctrl_setting const *setting);
+void pinmux_init_device_debugfs(struct dentry *devroot,
+                               struct pinctrl_dev *pctldev);
+
+#else
+
 static inline void pinmux_show_map(struct seq_file *s,
                                   struct pinctrl_map const *map)
 {

diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
new file mode 100644 (file)
index 0000000..6a2596b
--- /dev/null
+++ b/drivers/pinctrl/spear/Kconfig
@@ -0,0 +1,34 @@
+#
+# ST Microelectronics SPEAr PINCTRL drivers
+#
+
+if PLAT_SPEAR
+
+config PINCTRL_SPEAR
+       bool
+       depends on OF
+       select PINMUX
+       help
+         This enables pin control drivers for SPEAr Platform
+
+config PINCTRL_SPEAR3XX
+       bool
+       depends on ARCH_SPEAR3XX
+       select PINCTRL_SPEAR
+
+config PINCTRL_SPEAR300
+       bool "ST Microelectronics SPEAr300 SoC pin controller driver"
+       depends on MACH_SPEAR300
+       select PINCTRL_SPEAR3XX
+
+config PINCTRL_SPEAR310
+       bool "ST Microelectronics SPEAr310 SoC pin controller driver"
+       depends on MACH_SPEAR310
+       select PINCTRL_SPEAR3XX
+
+config PINCTRL_SPEAR320
+       bool "ST Microelectronics SPEAr320 SoC pin controller driver"
+       depends on MACH_SPEAR320
+       select PINCTRL_SPEAR3XX
+
+endif

diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
new file mode 100644 (file)
index 0000000..15dcb85
--- /dev/null
+++ b/drivers/pinctrl/spear/Makefile
@@ -0,0 +1,7 @@
+# SPEAr pinmux support
+
+obj-$(CONFIG_PINCTRL_SPEAR)    += pinctrl-spear.o
+obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
+obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
+obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
+obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o

diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
new file mode 100644 (file)
index 0000000..5ae50aa
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -0,0 +1,354 @@
+/*
+ * Driver for the ST Microelectronics SPEAr pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * Inspired from:
+ * - U300 Pinctl drivers
+ * - Tegra Pinctl drivers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "pinctrl-spear.h"
+
+#define DRIVER_NAME "spear-pinmux"
+
+static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
+{
+       return readl_relaxed(pmx->vbase + reg);
+}
+
+static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
+{
+       writel_relaxed(val, pmx->vbase + reg);
+}
+
+static int set_mode(struct spear_pmx *pmx, int mode)
+{
+       struct spear_pmx_mode *pmx_mode = NULL;
+       int i;
+       u32 val;
+
+       if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
+               return -EINVAL;
+
+       for (i = 0; i < pmx->machdata->npmx_modes; i++) {
+               if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
+                       pmx_mode = pmx->machdata->pmx_modes[i];
+                       break;
+               }
+       }
+
+       if (!pmx_mode)
+               return -EINVAL;
+
+       val = pmx_readl(pmx, pmx_mode->reg);
+       val &= ~pmx_mode->mask;
+       val |= pmx_mode->val;
+       pmx_writel(pmx, val, pmx_mode->reg);
+
+       pmx->machdata->mode = pmx_mode->mode;
+       dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
+                       pmx_mode->name ? pmx_mode->name : "no_name",
+                       pmx_mode->reg);
+
+       return 0;
+}
+
+void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
+{
+       struct spear_pingroup *pgroup;
+       struct spear_modemux *modemux;
+       int i, j, group;
+
+       for (group = 0; group < machdata->ngroups; group++) {
+               pgroup = machdata->groups[group];
+
+               for (i = 0; i < pgroup->nmodemuxs; i++) {
+                       modemux = &pgroup->modemuxs[i];
+
+                       for (j = 0; j < modemux->nmuxregs; j++)
+                               if (modemux->muxregs[j].reg == 0xFFFF)
+                                       modemux->muxregs[j].reg = reg;
+               }
+       }
+}
+
+static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+       return pmx->machdata->ngroups;
+}
+
+static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+               unsigned group)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+       return pmx->machdata->groups[group]->name;
+}
+
+static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+               unsigned group, const unsigned **pins, unsigned *num_pins)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+       *pins = pmx->machdata->groups[group]->pins;
+       *num_pins = pmx->machdata->groups[group]->npins;
+
+       return 0;
+}
+
+static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
+               struct seq_file *s, unsigned offset)
+{
+       seq_printf(s, " " DRIVER_NAME);
+}
+
+int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                struct device_node *np_config,
+                                struct pinctrl_map **map, unsigned *num_maps)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+       struct device_node *np;
+       struct property *prop;
+       const char *function, *group;
+       int ret, index = 0, count = 0;
+
+       /* calculate number of maps required */
+       for_each_child_of_node(np_config, np) {
+               ret = of_property_read_string(np, "st,function", &function);
+               if (ret < 0)
+                       return ret;
+
+               ret = of_property_count_strings(np, "st,pins");
+               if (ret < 0)
+                       return ret;
+
+               count += ret;
+       }
+
+       if (!count) {
+               dev_err(pmx->dev, "No child nodes passed via DT\n");
+               return -ENODEV;
+       }
+
+       *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
+       if (!*map)
+               return -ENOMEM;
+
+       for_each_child_of_node(np_config, np) {
+               of_property_read_string(np, "st,function", &function);
+               of_property_for_each_string(np, "st,pins", prop, group) {
+                       (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
+                       (*map)[index].data.mux.group = group;
+                       (*map)[index].data.mux.function = function;
+                       index++;
+               }
+       }
+
+       *num_maps = count;
+
+       return 0;
+}
+
+void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+               struct pinctrl_map *map, unsigned num_maps)
+{
+       kfree(map);
+}
+
+static struct pinctrl_ops spear_pinctrl_ops = {
+       .get_groups_count = spear_pinctrl_get_groups_cnt,
+       .get_group_name = spear_pinctrl_get_group_name,
+       .get_group_pins = spear_pinctrl_get_group_pins,
+       .pin_dbg_show = spear_pinctrl_pin_dbg_show,
+       .dt_node_to_map = spear_pinctrl_dt_node_to_map,
+       .dt_free_map = spear_pinctrl_dt_free_map,
+};
+
+static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+       return pmx->machdata->nfunctions;
+}
+
+static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+               unsigned function)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+       return pmx->machdata->functions[function]->name;
+}
+
+static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+               unsigned function, const char *const **groups,
+               unsigned * const ngroups)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+       *groups = pmx->machdata->functions[function]->groups;
+       *ngroups = pmx->machdata->functions[function]->ngroups;
+
+       return 0;
+}
+
+static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
+               unsigned function, unsigned group, bool enable)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+       const struct spear_pingroup *pgroup;
+       const struct spear_modemux *modemux;
+       struct spear_muxreg *muxreg;
+       u32 val, temp;
+       int i, j;
+       bool found = false;
+
+       pgroup = pmx->machdata->groups[group];
+
+       for (i = 0; i < pgroup->nmodemuxs; i++) {
+               modemux = &pgroup->modemuxs[i];
+
+               /* SoC have any modes */
+               if (pmx->machdata->modes_supported) {
+                       if (!(pmx->machdata->mode & modemux->modes))
+                               continue;
+               }
+
+               found = true;
+               for (j = 0; j < modemux->nmuxregs; j++) {
+                       muxreg = &modemux->muxregs[j];
+
+                       val = pmx_readl(pmx, muxreg->reg);
+                       val &= ~muxreg->mask;
+
+                       if (enable)
+                               temp = muxreg->val;
+                       else
+                               temp = ~muxreg->val;
+
+                       val |= temp;
+                       pmx_writel(pmx, val, muxreg->reg);
+               }
+       }
+
+       if (!found) {
+               dev_err(pmx->dev, "pinmux group: %s not supported\n",
+                               pgroup->name);
+               return -ENODEV;
+       }
+
+       return 0;
+}
+
+static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
+               unsigned group)
+{
+       return spear_pinctrl_endisable(pctldev, function, group, true);
+}
+
+static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
+               unsigned function, unsigned group)
+{
+       spear_pinctrl_endisable(pctldev, function, group, false);
+}
+
+static struct pinmux_ops spear_pinmux_ops = {
+       .get_functions_count = spear_pinctrl_get_funcs_count,
+       .get_function_name = spear_pinctrl_get_func_name,
+       .get_function_groups = spear_pinctrl_get_func_groups,
+       .enable = spear_pinctrl_enable,
+       .disable = spear_pinctrl_disable,
+};
+
+static struct pinctrl_desc spear_pinctrl_desc = {
+       .name = DRIVER_NAME,
+       .pctlops = &spear_pinctrl_ops,
+       .pmxops = &spear_pinmux_ops,
+       .owner = THIS_MODULE,
+};
+
+int __devinit spear_pinctrl_probe(struct platform_device *pdev,
+               struct spear_pinctrl_machdata *machdata)
+{
+       struct device_node *np = pdev->dev.of_node;
+       struct resource *res;
+       struct spear_pmx *pmx;
+
+       if (!machdata)
+               return -ENODEV;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!res)
+               return -EINVAL;
+
+       pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
+       if (!pmx) {
+               dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
+               return -ENOMEM;
+       }
+
+       pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+       if (!pmx->vbase) {
+               dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
+               return -ENODEV;
+       }
+
+       pmx->dev = &pdev->dev;
+       pmx->machdata = machdata;
+
+       /* configure mode, if supported by SoC */
+       if (machdata->modes_supported) {
+               int mode = 0;
+
+               if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
+                       dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
+                       return -EINVAL;
+               }
+
+               if (set_mode(pmx, mode)) {
+                       dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
+                                       mode);
+                       return -EINVAL;
+               }
+       }
+
+       platform_set_drvdata(pdev, pmx);
+
+       spear_pinctrl_desc.pins = machdata->pins;
+       spear_pinctrl_desc.npins = machdata->npins;
+
+       pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
+       if (IS_ERR(pmx->pctl)) {
+               dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+               return PTR_ERR(pmx->pctl);
+       }
+
+       return 0;
+}
+
+int __devexit spear_pinctrl_remove(struct platform_device *pdev)
+{
+       struct spear_pmx *pmx = platform_get_drvdata(pdev);
+
+       pinctrl_unregister(pmx->pctl);
+
+       return 0;
+}

diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
new file mode 100644 (file)
index 0000000..47a6b5b
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -0,0 +1,142 @@
+/*
+ * Driver header file for the ST Microelectronics SPEAr pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PINMUX_SPEAR_H__
+#define __PINMUX_SPEAR_H__
+
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/types.h>
+
+struct platform_device;
+struct device;
+
+/**
+ * struct spear_pmx_mode - SPEAr pmx mode
+ * @name: name of pmx mode
+ * @mode: mode id
+ * @reg: register for configuring this mode
+ * @mask: mask of this mode in reg
+ * @val: val to be configured at reg after doing (val & mask)
+ */
+struct spear_pmx_mode {
+       const char *const name;
+       u16 mode;
+       u16 reg;
+       u16 mask;
+       u32 val;
+};
+
+/**
+ * struct spear_muxreg - SPEAr mux reg configuration
+ * @reg: register offset
+ * @mask: mask bits
+ * @val: val to be written on mask bits
+ */
+struct spear_muxreg {
+       u16 reg;
+       u32 mask;
+       u32 val;
+};
+
+/**
+ * struct spear_modemux - SPEAr mode mux configuration
+ * @modes: mode ids supported by this group of muxregs
+ * @nmuxregs: number of muxreg configurations to be done for modes
+ * @muxregs: array of muxreg configurations to be done for modes
+ */
+struct spear_modemux {
+       u16 modes;
+       u8 nmuxregs;
+       struct spear_muxreg *muxregs;
+};
+
+/**
+ * struct spear_pingroup - SPEAr pin group configurations
+ * @name: name of pin group
+ * @pins: array containing pin numbers
+ * @npins: size of pins array
+ * @modemuxs: array of modemux configurations for this pin group
+ * @nmodemuxs: size of array modemuxs
+ *
+ * A representation of a group of pins in the SPEAr pin controller. Each group
+ * allows some parameter or parameters to be configured.
+ */
+struct spear_pingroup {
+       const char *name;
+       const unsigned *pins;
+       unsigned npins;
+       struct spear_modemux *modemuxs;
+       unsigned nmodemuxs;
+};
+
+/**
+ * struct spear_function - SPEAr pinctrl mux function
+ * @name: The name of the function, exported to pinctrl core.
+ * @groups: An array of pin groups that may select this function.
+ * @ngroups: The number of entries in @groups.
+ */
+struct spear_function {
+       const char *name;
+       const char *const *groups;
+       unsigned ngroups;
+};
+
+/**
+ * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
+ *     configuration
+ * @pins: An array describing all pins the pin controller affects.
+ *     All pins which are also GPIOs must be listed first within the *array,
+ *     and be numbered identically to the GPIO controller's *numbering.
+ * @npins: The numbmer of entries in @pins.
+ * @functions: An array describing all mux functions the SoC supports.
+ * @nfunctions: The numbmer of entries in @functions.
+ * @groups: An array describing all pin groups the pin SoC supports.
+ * @ngroups: The numbmer of entries in @groups.
+ *
+ * @modes_supported: Does SoC support modes
+ * @mode: mode configured from probe
+ * @pmx_modes: array of modes supported by SoC
+ * @npmx_modes: number of entries in pmx_modes.
+ */
+struct spear_pinctrl_machdata {
+       const struct pinctrl_pin_desc *pins;
+       unsigned npins;
+       struct spear_function **functions;
+       unsigned nfunctions;
+       struct spear_pingroup **groups;
+       unsigned ngroups;
+
+       bool modes_supported;
+       u16 mode;
+       struct spear_pmx_mode **pmx_modes;
+       unsigned npmx_modes;
+};
+
+/**
+ * struct spear_pmx - SPEAr pinctrl mux
+ * @dev: pointer to struct dev of platform_device registered
+ * @pctl: pointer to struct pinctrl_dev
+ * @machdata: pointer to SoC or machine specific structure
+ * @vbase: virtual base address of pinmux controller
+ */
+struct spear_pmx {
+       struct device *dev;
+       struct pinctrl_dev *pctl;
+       struct spear_pinctrl_machdata *machdata;
+       void __iomem *vbase;
+};
+
+/* exported routines */
+void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
+int __devinit spear_pinctrl_probe(struct platform_device *pdev,
+               struct spear_pinctrl_machdata *machdata);
+int __devexit spear_pinctrl_remove(struct platform_device *pdev);
+#endif /* __PINMUX_SPEAR_H__ */

diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
new file mode 100644 (file)
index 0000000..9c82a35
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -0,0 +1,708 @@
+/*
+ * Driver for the ST Microelectronics SPEAr300 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear300-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                 0x00
+#define MODE_CONFIG_REG                        0x04
+
+/* modes */
+#define NAND_MODE                      (1 << 0)
+#define NOR_MODE                       (1 << 1)
+#define PHOTO_FRAME_MODE               (1 << 2)
+#define LEND_IP_PHONE_MODE             (1 << 3)
+#define HEND_IP_PHONE_MODE             (1 << 4)
+#define LEND_WIFI_PHONE_MODE           (1 << 5)
+#define HEND_WIFI_PHONE_MODE           (1 << 6)
+#define ATA_PABX_WI2S_MODE             (1 << 7)
+#define ATA_PABX_I2S_MODE              (1 << 8)
+#define CAML_LCDW_MODE                 (1 << 9)
+#define CAMU_LCD_MODE                  (1 << 10)
+#define CAMU_WLCD_MODE                 (1 << 11)
+#define CAML_LCD_MODE                  (1 << 12)
+
+static struct spear_pmx_mode pmx_mode_nand = {
+       .name = "nand",
+       .mode = NAND_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x00,
+};
+
+static struct spear_pmx_mode pmx_mode_nor = {
+       .name = "nor",
+       .mode = NOR_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x01,
+};
+
+static struct spear_pmx_mode pmx_mode_photo_frame = {
+       .name = "photo frame mode",
+       .mode = PHOTO_FRAME_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x02,
+};
+
+static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
+       .name = "lend ip phone mode",
+       .mode = LEND_IP_PHONE_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x03,
+};
+
+static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
+       .name = "hend ip phone mode",
+       .mode = HEND_IP_PHONE_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x04,
+};
+
+static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
+       .name = "lend wifi phone mode",
+       .mode = LEND_WIFI_PHONE_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x05,
+};
+
+static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
+       .name = "hend wifi phone mode",
+       .mode = HEND_WIFI_PHONE_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x06,
+};
+
+static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
+       .name = "ata pabx wi2s mode",
+       .mode = ATA_PABX_WI2S_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x07,
+};
+
+static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
+       .name = "ata pabx i2s mode",
+       .mode = ATA_PABX_I2S_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x08,
+};
+
+static struct spear_pmx_mode pmx_mode_caml_lcdw = {
+       .name = "caml lcdw mode",
+       .mode = CAML_LCDW_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x0C,
+};
+
+static struct spear_pmx_mode pmx_mode_camu_lcd = {
+       .name = "camu lcd mode",
+       .mode = CAMU_LCD_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x0D,
+};
+
+static struct spear_pmx_mode pmx_mode_camu_wlcd = {
+       .name = "camu wlcd mode",
+       .mode = CAMU_WLCD_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0xE,
+};
+
+static struct spear_pmx_mode pmx_mode_caml_lcd = {
+       .name = "caml lcd mode",
+       .mode = CAML_LCD_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x0000000F,
+       .val = 0x0F,
+};
+
+static struct spear_pmx_mode *spear300_pmx_modes[] = {
+       &pmx_mode_nand,
+       &pmx_mode_nor,
+       &pmx_mode_photo_frame,
+       &pmx_mode_lend_ip_phone,
+       &pmx_mode_hend_ip_phone,
+       &pmx_mode_lend_wifi_phone,
+       &pmx_mode_hend_wifi_phone,
+       &pmx_mode_ata_pabx_wi2s,
+       &pmx_mode_ata_pabx_i2s,
+       &pmx_mode_caml_lcdw,
+       &pmx_mode_camu_lcd,
+       &pmx_mode_camu_wlcd,
+       &pmx_mode_caml_lcd,
+};
+
+/* fsmc_2chips_pins */
+static const unsigned fsmc_2chips_pins[] = { 1, 97 };
+static struct spear_muxreg fsmc_2chips_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_FIRDA_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux fsmc_2chips_modemux[] = {
+       {
+               .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
+                       ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
+               .muxregs = fsmc_2chips_muxreg,
+               .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
+       },
+};
+
+static struct spear_pingroup fsmc_2chips_pingroup = {
+       .name = "fsmc_2chips_grp",
+       .pins = fsmc_2chips_pins,
+       .npins = ARRAY_SIZE(fsmc_2chips_pins),
+       .modemuxs = fsmc_2chips_modemux,
+       .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
+};
+
+/* fsmc_4chips_pins */
+static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
+static struct spear_muxreg fsmc_4chips_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux fsmc_4chips_modemux[] = {
+       {
+               .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
+                       ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
+               .muxregs = fsmc_4chips_muxreg,
+               .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
+       },
+};
+
+static struct spear_pingroup fsmc_4chips_pingroup = {
+       .name = "fsmc_4chips_grp",
+       .pins = fsmc_4chips_pins,
+       .npins = ARRAY_SIZE(fsmc_4chips_pins),
+       .modemuxs = fsmc_4chips_modemux,
+       .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
+};
+static struct spear_function fsmc_function = {
+       .name = "fsmc",
+       .groups = fsmc_grps,
+       .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* clcd_lcdmode_pins */
+static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
+static struct spear_muxreg clcd_lcdmode_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux clcd_lcdmode_modemux[] = {
+       {
+               .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                       CAMU_LCD_MODE | CAML_LCD_MODE,
+               .muxregs = clcd_lcdmode_muxreg,
+               .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
+       },
+};
+
+static struct spear_pingroup clcd_lcdmode_pingroup = {
+       .name = "clcd_lcdmode_grp",
+       .pins = clcd_lcdmode_pins,
+       .npins = ARRAY_SIZE(clcd_lcdmode_pins),
+       .modemuxs = clcd_lcdmode_modemux,
+       .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
+};
+
+/* clcd_pfmode_pins */
+static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
+static struct spear_muxreg clcd_pfmode_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_2_3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux clcd_pfmode_modemux[] = {
+       {
+               .modes = PHOTO_FRAME_MODE,
+               .muxregs = clcd_pfmode_muxreg,
+               .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
+       },
+};
+
+static struct spear_pingroup clcd_pfmode_pingroup = {
+       .name = "clcd_pfmode_grp",
+       .pins = clcd_pfmode_pins,
+       .npins = ARRAY_SIZE(clcd_pfmode_pins),
+       .modemuxs = clcd_pfmode_modemux,
+       .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
+};
+
+static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
+};
+static struct spear_function clcd_function = {
+       .name = "clcd",
+       .groups = clcd_grps,
+       .ngroups = ARRAY_SIZE(clcd_grps),
+};
+
+/* tdm_pins */
+static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
+static struct spear_muxreg tdm_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux tdm_modemux[] = {
+       {
+               .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                       HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
+                       | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
+                       | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                       | CAMU_WLCD_MODE | CAML_LCD_MODE,
+               .muxregs = tdm_muxreg,
+               .nmuxregs = ARRAY_SIZE(tdm_muxreg),
+       },
+};
+
+static struct spear_pingroup tdm_pingroup = {
+       .name = "tdm_grp",
+       .pins = tdm_pins,
+       .npins = ARRAY_SIZE(tdm_pins),
+       .modemuxs = tdm_modemux,
+       .nmodemuxs = ARRAY_SIZE(tdm_modemux),
+};
+
+static const char *const tdm_grps[] = { "tdm_grp" };
+static struct spear_function tdm_function = {
+       .name = "tdm",
+       .groups = tdm_grps,
+       .ngroups = ARRAY_SIZE(tdm_grps),
+};
+
+/* i2c_clk_pins */
+static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
+static struct spear_muxreg i2c_clk_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux i2c_clk_modemux[] = {
+       {
+               .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
+                       LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                       ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
+                       | CAML_LCD_MODE,
+               .muxregs = i2c_clk_muxreg,
+               .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
+       },
+};
+
+static struct spear_pingroup i2c_clk_pingroup = {
+       .name = "i2c_clk_grp_grp",
+       .pins = i2c_clk_pins,
+       .npins = ARRAY_SIZE(i2c_clk_pins),
+       .modemuxs = i2c_clk_modemux,
+       .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
+};
+
+static const char *const i2c_grps[] = { "i2c_clk_grp" };
+static struct spear_function i2c_function = {
+       .name = "i2c1",
+       .groups = i2c_grps,
+       .ngroups = ARRAY_SIZE(i2c_grps),
+};
+
+/* caml_pins */
+static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
+static struct spear_muxreg caml_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux caml_modemux[] = {
+       {
+               .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
+               .muxregs = caml_muxreg,
+               .nmuxregs = ARRAY_SIZE(caml_muxreg),
+       },
+};
+
+static struct spear_pingroup caml_pingroup = {
+       .name = "caml_grp",
+       .pins = caml_pins,
+       .npins = ARRAY_SIZE(caml_pins),
+       .modemuxs = caml_modemux,
+       .nmodemuxs = ARRAY_SIZE(caml_modemux),
+};
+
+/* camu_pins */
+static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
+static struct spear_muxreg camu_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux camu_modemux[] = {
+       {
+               .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
+               .muxregs = camu_muxreg,
+               .nmuxregs = ARRAY_SIZE(camu_muxreg),
+       },
+};
+
+static struct spear_pingroup camu_pingroup = {
+       .name = "camu_grp",
+       .pins = camu_pins,
+       .npins = ARRAY_SIZE(camu_pins),
+       .modemuxs = camu_modemux,
+       .nmodemuxs = ARRAY_SIZE(camu_modemux),
+};
+
+static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
+static struct spear_function cam_function = {
+       .name = "cam",
+       .groups = cam_grps,
+       .ngroups = ARRAY_SIZE(cam_grps),
+};
+
+/* dac_pins */
+static const unsigned dac_pins[] = { 43, 44 };
+static struct spear_muxreg dac_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux dac_modemux[] = {
+       {
+               .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                       | CAMU_WLCD_MODE | CAML_LCD_MODE,
+               .muxregs = dac_muxreg,
+               .nmuxregs = ARRAY_SIZE(dac_muxreg),
+       },
+};
+
+static struct spear_pingroup dac_pingroup = {
+       .name = "dac_grp",
+       .pins = dac_pins,
+       .npins = ARRAY_SIZE(dac_pins),
+       .modemuxs = dac_modemux,
+       .nmodemuxs = ARRAY_SIZE(dac_modemux),
+};
+
+static const char *const dac_grps[] = { "dac_grp" };
+static struct spear_function dac_function = {
+       .name = "dac",
+       .groups = dac_grps,
+       .ngroups = ARRAY_SIZE(dac_grps),
+};
+
+/* i2s_pins */
+static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
+static struct spear_muxreg i2s_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux i2s_modemux[] = {
+       {
+               .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
+                       | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+                       ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+                       | CAMU_WLCD_MODE | CAML_LCD_MODE,
+               .muxregs = i2s_muxreg,
+               .nmuxregs = ARRAY_SIZE(i2s_muxreg),
+       },
+};
+
+static struct spear_pingroup i2s_pingroup = {
+       .name = "i2s_grp",
+       .pins = i2s_pins,
+       .npins = ARRAY_SIZE(i2s_pins),
+       .modemuxs = i2s_modemux,
+       .nmodemuxs = ARRAY_SIZE(i2s_modemux),
+};
+
+static const char *const i2s_grps[] = { "i2s_grp" };
+static struct spear_function i2s_function = {
+       .name = "i2s",
+       .groups = i2s_grps,
+       .ngroups = ARRAY_SIZE(i2s_grps),
+};
+
+/* sdhci_4bit_pins */
+static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
+static struct spear_muxreg sdhci_4bit_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+                       PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+                       PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux sdhci_4bit_modemux[] = {
+       {
+               .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                       HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
+                       HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
+                       CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
+               .muxregs = sdhci_4bit_muxreg,
+               .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
+       },
+};
+
+static struct spear_pingroup sdhci_4bit_pingroup = {
+       .name = "sdhci_4bit_grp",
+       .pins = sdhci_4bit_pins,
+       .npins = ARRAY_SIZE(sdhci_4bit_pins),
+       .modemuxs = sdhci_4bit_modemux,
+       .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
+};
+
+/* sdhci_8bit_pins */
+static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
+       33 };
+static struct spear_muxreg sdhci_8bit_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+                       PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+                       PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux sdhci_8bit_modemux[] = {
+       {
+               .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+                       HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
+                       HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
+                       CAMU_WLCD_MODE | CAML_LCD_MODE,
+               .muxregs = sdhci_8bit_muxreg,
+               .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
+       },
+};
+
+static struct spear_pingroup sdhci_8bit_pingroup = {
+       .name = "sdhci_8bit_grp",
+       .pins = sdhci_8bit_pins,
+       .npins = ARRAY_SIZE(sdhci_8bit_pins),
+       .modemuxs = sdhci_8bit_modemux,
+       .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
+};
+
+static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
+static struct spear_function sdhci_function = {
+       .name = "sdhci",
+       .groups = sdhci_grps,
+       .ngroups = ARRAY_SIZE(sdhci_grps),
+};
+
+/* gpio1_0_to_3_pins */
+static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
+static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux gpio1_0_to_3_modemux[] = {
+       {
+               .modes = PHOTO_FRAME_MODE,
+               .muxregs = gpio1_0_to_3_muxreg,
+               .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
+       },
+};
+
+static struct spear_pingroup gpio1_0_to_3_pingroup = {
+       .name = "gpio1_0_to_3_grp",
+       .pins = gpio1_0_to_3_pins,
+       .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
+       .modemuxs = gpio1_0_to_3_modemux,
+       .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
+};
+
+/* gpio1_4_to_7_pins */
+static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
+
+static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux gpio1_4_to_7_modemux[] = {
+       {
+               .modes = PHOTO_FRAME_MODE,
+               .muxregs = gpio1_4_to_7_muxreg,
+               .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
+       },
+};
+
+static struct spear_pingroup gpio1_4_to_7_pingroup = {
+       .name = "gpio1_4_to_7_grp",
+       .pins = gpio1_4_to_7_pins,
+       .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
+       .modemuxs = gpio1_4_to_7_modemux,
+       .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
+};
+
+static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
+};
+static struct spear_function gpio1_function = {
+       .name = "gpio1",
+       .groups = gpio1_grps,
+       .ngroups = ARRAY_SIZE(gpio1_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear300_pingroups[] = {
+       SPEAR3XX_COMMON_PINGROUPS,
+       &fsmc_2chips_pingroup,
+       &fsmc_4chips_pingroup,
+       &clcd_lcdmode_pingroup,
+       &clcd_pfmode_pingroup,
+       &tdm_pingroup,
+       &i2c_clk_pingroup,
+       &caml_pingroup,
+       &camu_pingroup,
+       &dac_pingroup,
+       &i2s_pingroup,
+       &sdhci_4bit_pingroup,
+       &sdhci_8bit_pingroup,
+       &gpio1_0_to_3_pingroup,
+       &gpio1_4_to_7_pingroup,
+};
+
+/* functions */
+static struct spear_function *spear300_functions[] = {
+       SPEAR3XX_COMMON_FUNCTIONS,
+       &fsmc_function,
+       &clcd_function,
+       &tdm_function,
+       &i2c_function,
+       &cam_function,
+       &dac_function,
+       &i2s_function,
+       &sdhci_function,
+       &gpio1_function,
+};
+
+static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
+       {
+               .compatible = "st,spear300-pinmux",
+       },
+       {},
+};
+
+static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
+{
+       int ret;
+
+       spear3xx_machdata.groups = spear300_pingroups;
+       spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
+       spear3xx_machdata.functions = spear300_functions;
+       spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
+
+       spear3xx_machdata.modes_supported = true;
+       spear3xx_machdata.pmx_modes = spear300_pmx_modes;
+       spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
+
+       pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+       ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
+{
+       return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear300_pinctrl_driver = {
+       .driver = {
+               .name = DRIVER_NAME,
+               .owner = THIS_MODULE,
+               .of_match_table = spear300_pinctrl_of_match,
+       },
+       .probe = spear300_pinctrl_probe,
+       .remove = __devexit_p(spear300_pinctrl_remove),
+};
+
+static int __init spear300_pinctrl_init(void)
+{
+       return platform_driver_register(&spear300_pinctrl_driver);
+}
+arch_initcall(spear300_pinctrl_init);
+
+static void __exit spear300_pinctrl_exit(void)
+{
+       platform_driver_unregister(&spear300_pinctrl_driver);
+}
+module_exit(spear300_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);

diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
new file mode 100644 (file)
index 0000000..1a97076
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -0,0 +1,431 @@
+/*
+ * Driver for the ST Microelectronics SPEAr310 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear310-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                 0x08
+
+/* emi_cs_0_to_5_pins */
+static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
+static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux emi_cs_0_to_5_modemux[] = {
+       {
+               .muxregs = emi_cs_0_to_5_muxreg,
+               .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
+       },
+};
+
+static struct spear_pingroup emi_cs_0_to_5_pingroup = {
+       .name = "emi_cs_0_to_5_grp",
+       .pins = emi_cs_0_to_5_pins,
+       .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
+       .modemuxs = emi_cs_0_to_5_modemux,
+       .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
+};
+
+static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
+static struct spear_function emi_cs_0_to_5_function = {
+       .name = "emi",
+       .groups = emi_cs_0_to_5_grps,
+       .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
+};
+
+/* uart1_pins */
+static const unsigned uart1_pins[] = { 0, 1 };
+static struct spear_muxreg uart1_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_FIRDA_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux uart1_modemux[] = {
+       {
+               .muxregs = uart1_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_muxreg),
+       },
+};
+
+static struct spear_pingroup uart1_pingroup = {
+       .name = "uart1_grp",
+       .pins = uart1_pins,
+       .npins = ARRAY_SIZE(uart1_pins),
+       .modemuxs = uart1_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart1_modemux),
+};
+
+static const char *const uart1_grps[] = { "uart1_grp" };
+static struct spear_function uart1_function = {
+       .name = "uart1",
+       .groups = uart1_grps,
+       .ngroups = ARRAY_SIZE(uart1_grps),
+};
+
+/* uart2_pins */
+static const unsigned uart2_pins[] = { 43, 44 };
+static struct spear_muxreg uart2_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux uart2_modemux[] = {
+       {
+               .muxregs = uart2_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart2_muxreg),
+       },
+};
+
+static struct spear_pingroup uart2_pingroup = {
+       .name = "uart2_grp",
+       .pins = uart2_pins,
+       .npins = ARRAY_SIZE(uart2_pins),
+       .modemuxs = uart2_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart2_modemux),
+};
+
+static const char *const uart2_grps[] = { "uart2_grp" };
+static struct spear_function uart2_function = {
+       .name = "uart2",
+       .groups = uart2_grps,
+       .ngroups = ARRAY_SIZE(uart2_grps),
+};
+
+/* uart3_pins */
+static const unsigned uart3_pins[] = { 37, 38 };
+static struct spear_muxreg uart3_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux uart3_modemux[] = {
+       {
+               .muxregs = uart3_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart3_muxreg),
+       },
+};
+
+static struct spear_pingroup uart3_pingroup = {
+       .name = "uart3_grp",
+       .pins = uart3_pins,
+       .npins = ARRAY_SIZE(uart3_pins),
+       .modemuxs = uart3_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart3_modemux),
+};
+
+static const char *const uart3_grps[] = { "uart3_grp" };
+static struct spear_function uart3_function = {
+       .name = "uart3",
+       .groups = uart3_grps,
+       .ngroups = ARRAY_SIZE(uart3_grps),
+};
+
+/* uart4_pins */
+static const unsigned uart4_pins[] = { 39, 40 };
+static struct spear_muxreg uart4_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux uart4_modemux[] = {
+       {
+               .muxregs = uart4_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart4_muxreg),
+       },
+};
+
+static struct spear_pingroup uart4_pingroup = {
+       .name = "uart4_grp",
+       .pins = uart4_pins,
+       .npins = ARRAY_SIZE(uart4_pins),
+       .modemuxs = uart4_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart4_modemux),
+};
+
+static const char *const uart4_grps[] = { "uart4_grp" };
+static struct spear_function uart4_function = {
+       .name = "uart4",
+       .groups = uart4_grps,
+       .ngroups = ARRAY_SIZE(uart4_grps),
+};
+
+/* uart5_pins */
+static const unsigned uart5_pins[] = { 41, 42 };
+static struct spear_muxreg uart5_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux uart5_modemux[] = {
+       {
+               .muxregs = uart5_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart5_muxreg),
+       },
+};
+
+static struct spear_pingroup uart5_pingroup = {
+       .name = "uart5_grp",
+       .pins = uart5_pins,
+       .npins = ARRAY_SIZE(uart5_pins),
+       .modemuxs = uart5_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart5_modemux),
+};
+
+static const char *const uart5_grps[] = { "uart5_grp" };
+static struct spear_function uart5_function = {
+       .name = "uart5",
+       .groups = uart5_grps,
+       .ngroups = ARRAY_SIZE(uart5_grps),
+};
+
+/* fsmc_pins */
+static const unsigned fsmc_pins[] = { 34, 35, 36 };
+static struct spear_muxreg fsmc_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_CS_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux fsmc_modemux[] = {
+       {
+               .muxregs = fsmc_muxreg,
+               .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
+       },
+};
+
+static struct spear_pingroup fsmc_pingroup = {
+       .name = "fsmc_grp",
+       .pins = fsmc_pins,
+       .npins = ARRAY_SIZE(fsmc_pins),
+       .modemuxs = fsmc_modemux,
+       .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_grp" };
+static struct spear_function fsmc_function = {
+       .name = "fsmc",
+       .groups = fsmc_grps,
+       .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* rs485_0_pins */
+static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
+static struct spear_muxreg rs485_0_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux rs485_0_modemux[] = {
+       {
+               .muxregs = rs485_0_muxreg,
+               .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
+       },
+};
+
+static struct spear_pingroup rs485_0_pingroup = {
+       .name = "rs485_0_grp",
+       .pins = rs485_0_pins,
+       .npins = ARRAY_SIZE(rs485_0_pins),
+       .modemuxs = rs485_0_modemux,
+       .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
+};
+
+static const char *const rs485_0_grps[] = { "rs485_0" };
+static struct spear_function rs485_0_function = {
+       .name = "rs485_0",
+       .groups = rs485_0_grps,
+       .ngroups = ARRAY_SIZE(rs485_0_grps),
+};
+
+/* rs485_1_pins */
+static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
+static struct spear_muxreg rs485_1_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux rs485_1_modemux[] = {
+       {
+               .muxregs = rs485_1_muxreg,
+               .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
+       },
+};
+
+static struct spear_pingroup rs485_1_pingroup = {
+       .name = "rs485_1_grp",
+       .pins = rs485_1_pins,
+       .npins = ARRAY_SIZE(rs485_1_pins),
+       .modemuxs = rs485_1_modemux,
+       .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
+};
+
+static const char *const rs485_1_grps[] = { "rs485_1" };
+static struct spear_function rs485_1_function = {
+       .name = "rs485_1",
+       .groups = rs485_1_grps,
+       .ngroups = ARRAY_SIZE(rs485_1_grps),
+};
+
+/* tdm_pins */
+static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
+static struct spear_muxreg tdm_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_modemux tdm_modemux[] = {
+       {
+               .muxregs = tdm_muxreg,
+               .nmuxregs = ARRAY_SIZE(tdm_muxreg),
+       },
+};
+
+static struct spear_pingroup tdm_pingroup = {
+       .name = "tdm_grp",
+       .pins = tdm_pins,
+       .npins = ARRAY_SIZE(tdm_pins),
+       .modemuxs = tdm_modemux,
+       .nmodemuxs = ARRAY_SIZE(tdm_modemux),
+};
+
+static const char *const tdm_grps[] = { "tdm_grp" };
+static struct spear_function tdm_function = {
+       .name = "tdm",
+       .groups = tdm_grps,
+       .ngroups = ARRAY_SIZE(tdm_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear310_pingroups[] = {
+       SPEAR3XX_COMMON_PINGROUPS,
+       &emi_cs_0_to_5_pingroup,
+       &uart1_pingroup,
+       &uart2_pingroup,
+       &uart3_pingroup,
+       &uart4_pingroup,
+       &uart5_pingroup,
+       &fsmc_pingroup,
+       &rs485_0_pingroup,
+       &rs485_1_pingroup,
+       &tdm_pingroup,
+};
+
+/* functions */
+static struct spear_function *spear310_functions[] = {
+       SPEAR3XX_COMMON_FUNCTIONS,
+       &emi_cs_0_to_5_function,
+       &uart1_function,
+       &uart2_function,
+       &uart3_function,
+       &uart4_function,
+       &uart5_function,
+       &fsmc_function,
+       &rs485_0_function,
+       &rs485_1_function,
+       &tdm_function,
+};
+
+static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
+       {
+               .compatible = "st,spear310-pinmux",
+       },
+       {},
+};
+
+static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
+{
+       int ret;
+
+       spear3xx_machdata.groups = spear310_pingroups;
+       spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
+       spear3xx_machdata.functions = spear310_functions;
+       spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
+
+       pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+       spear3xx_machdata.modes_supported = false;
+
+       ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
+{
+       return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear310_pinctrl_driver = {
+       .driver = {
+               .name = DRIVER_NAME,
+               .owner = THIS_MODULE,
+               .of_match_table = spear310_pinctrl_of_match,
+       },
+       .probe = spear310_pinctrl_probe,
+       .remove = __devexit_p(spear310_pinctrl_remove),
+};
+
+static int __init spear310_pinctrl_init(void)
+{
+       return platform_driver_register(&spear310_pinctrl_driver);
+}
+arch_initcall(spear310_pinctrl_init);
+
+static void __exit spear310_pinctrl_exit(void)
+{
+       platform_driver_unregister(&spear310_pinctrl_driver);
+}
+module_exit(spear310_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);

diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
new file mode 100644 (file)
index 0000000..de726e6
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -0,0 +1,3468 @@
+/*
+ * Driver for the ST Microelectronics SPEAr320 pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "pinctrl-spear3xx.h"
+
+#define DRIVER_NAME "spear320-pinmux"
+
+/* addresses */
+#define PMX_CONFIG_REG                 0x0C
+#define MODE_CONFIG_REG                        0x10
+#define MODE_EXT_CONFIG_REG            0x18
+
+/* modes */
+#define AUTO_NET_SMII_MODE     (1 << 0)
+#define AUTO_NET_MII_MODE      (1 << 1)
+#define AUTO_EXP_MODE          (1 << 2)
+#define SMALL_PRINTERS_MODE    (1 << 3)
+#define EXTENDED_MODE          (1 << 4)
+
+static struct spear_pmx_mode pmx_mode_auto_net_smii = {
+       .name = "Automation Networking SMII mode",
+       .mode = AUTO_NET_SMII_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x00000007,
+       .val = 0x0,
+};
+
+static struct spear_pmx_mode pmx_mode_auto_net_mii = {
+       .name = "Automation Networking MII mode",
+       .mode = AUTO_NET_MII_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x00000007,
+       .val = 0x1,
+};
+
+static struct spear_pmx_mode pmx_mode_auto_exp = {
+       .name = "Automation Expanded mode",
+       .mode = AUTO_EXP_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x00000007,
+       .val = 0x2,
+};
+
+static struct spear_pmx_mode pmx_mode_small_printers = {
+       .name = "Small Printers mode",
+       .mode = SMALL_PRINTERS_MODE,
+       .reg = MODE_CONFIG_REG,
+       .mask = 0x00000007,
+       .val = 0x3,
+};
+
+static struct spear_pmx_mode pmx_mode_extended = {
+       .name = "extended mode",
+       .mode = EXTENDED_MODE,
+       .reg = MODE_EXT_CONFIG_REG,
+       .mask = 0x00000001,
+       .val = 0x1,
+};
+
+static struct spear_pmx_mode *spear320_pmx_modes[] = {
+       &pmx_mode_auto_net_smii,
+       &pmx_mode_auto_net_mii,
+       &pmx_mode_auto_exp,
+       &pmx_mode_small_printers,
+       &pmx_mode_extended,
+};
+
+/* Extended mode registers and their offsets */
+#define EXT_CTRL_REG                           0x0018
+       #define MII_MDIO_MASK                   (1 << 4)
+       #define MII_MDIO_10_11_VAL              0
+       #define MII_MDIO_81_VAL                 (1 << 4)
+       #define EMI_FSMC_DYNAMIC_MUX_MASK       (1 << 5)
+       #define MAC_MODE_MII                    0
+       #define MAC_MODE_RMII                   1
+       #define MAC_MODE_SMII                   2
+       #define MAC_MODE_SS_SMII                3
+       #define MAC_MODE_MASK                   0x3
+       #define MAC1_MODE_SHIFT                 16
+       #define MAC2_MODE_SHIFT                 18
+
+#define IP_SEL_PAD_0_9_REG                     0x00A4
+       #define PMX_PL_0_1_MASK                 (0x3F << 0)
+       #define PMX_UART2_PL_0_1_VAL            0x0
+       #define PMX_I2C2_PL_0_1_VAL             (0x4 | (0x4 << 3))
+
+       #define PMX_PL_2_3_MASK                 (0x3F << 6)
+       #define PMX_I2C2_PL_2_3_VAL             0x0
+       #define PMX_UART6_PL_2_3_VAL            ((0x1 << 6) | (0x1 << 9))
+       #define PMX_UART1_ENH_PL_2_3_VAL        ((0x4 << 6) | (0x4 << 9))
+
+       #define PMX_PL_4_5_MASK                 (0x3F << 12)
+       #define PMX_UART5_PL_4_5_VAL            ((0x1 << 12) | (0x1 << 15))
+       #define PMX_UART1_ENH_PL_4_5_VAL        ((0x4 << 12) | (0x4 << 15))
+       #define PMX_PL_5_MASK                   (0x7 << 15)
+       #define PMX_TOUCH_Y_PL_5_VAL            0x0
+
+       #define PMX_PL_6_7_MASK                 (0x3F << 18)
+       #define PMX_PL_6_MASK                   (0x7 << 18)
+       #define PMX_PL_7_MASK                   (0x7 << 21)
+       #define PMX_UART4_PL_6_7_VAL            ((0x1 << 18) | (0x1 << 21))
+       #define PMX_PWM_3_PL_6_VAL              (0x2 << 18)
+       #define PMX_PWM_2_PL_7_VAL              (0x2 << 21)
+       #define PMX_UART1_ENH_PL_6_7_VAL        ((0x4 << 18) | (0x4 << 21))
+
+       #define PMX_PL_8_9_MASK                 (0x3F << 24)
+       #define PMX_UART3_PL_8_9_VAL            ((0x1 << 24) | (0x1 << 27))
+       #define PMX_PWM_0_1_PL_8_9_VAL          ((0x2 << 24) | (0x2 << 27))
+       #define PMX_I2C1_PL_8_9_VAL             ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_10_19_REG                   0x00A8
+       #define PMX_PL_10_11_MASK               (0x3F << 0)
+       #define PMX_SMII_PL_10_11_VAL           0
+       #define PMX_RMII_PL_10_11_VAL           ((0x4 << 0) | (0x4 << 3))
+
+       #define PMX_PL_12_MASK                  (0x7 << 6)
+       #define PMX_PWM3_PL_12_VAL              0
+       #define PMX_SDHCI_CD_PL_12_VAL          (0x4 << 6)
+
+       #define PMX_PL_13_14_MASK               (0x3F << 9)
+       #define PMX_PL_13_MASK                  (0x7 << 9)
+       #define PMX_PL_14_MASK                  (0x7 << 12)
+       #define PMX_SSP2_PL_13_14_15_16_VAL     0
+       #define PMX_UART4_PL_13_14_VAL          ((0x1 << 9) | (0x1 << 12))
+       #define PMX_RMII_PL_13_14_VAL           ((0x4 << 9) | (0x4 << 12))
+       #define PMX_PWM2_PL_13_VAL              (0x2 << 9)
+       #define PMX_PWM1_PL_14_VAL              (0x2 << 12)
+
+       #define PMX_PL_15_MASK                  (0x7 << 15)
+       #define PMX_PWM0_PL_15_VAL              (0x2 << 15)
+       #define PMX_PL_15_16_MASK               (0x3F << 15)
+       #define PMX_UART3_PL_15_16_VAL          ((0x1 << 15) | (0x1 << 18))
+       #define PMX_RMII_PL_15_16_VAL           ((0x4 << 15) | (0x4 << 18))
+
+       #define PMX_PL_17_18_MASK               (0x3F << 21)
+       #define PMX_SSP1_PL_17_18_19_20_VAL     0
+       #define PMX_RMII_PL_17_18_VAL           ((0x4 << 21) | (0x4 << 24))
+
+       #define PMX_PL_19_MASK                  (0x7 << 27)
+       #define PMX_I2C2_PL_19_VAL              (0x1 << 27)
+       #define PMX_RMII_PL_19_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_20_29_REG                   0x00AC
+       #define PMX_PL_20_MASK                  (0x7 << 0)
+       #define PMX_I2C2_PL_20_VAL              (0x1 << 0)
+       #define PMX_RMII_PL_20_VAL              (0x4 << 0)
+
+       #define PMX_PL_21_TO_27_MASK            (0x1FFFFF << 3)
+       #define PMX_SMII_PL_21_TO_27_VAL        0
+       #define PMX_RMII_PL_21_TO_27_VAL        ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
+
+       #define PMX_PL_28_29_MASK               (0x3F << 24)
+       #define PMX_PL_28_MASK                  (0x7 << 24)
+       #define PMX_PL_29_MASK                  (0x7 << 27)
+       #define PMX_UART1_PL_28_29_VAL          0
+       #define PMX_PWM_3_PL_28_VAL             (0x4 << 24)
+       #define PMX_PWM_2_PL_29_VAL             (0x4 << 27)
+
+#define IP_SEL_PAD_30_39_REG                   0x00B0
+       #define PMX_PL_30_31_MASK               (0x3F << 0)
+       #define PMX_CAN1_PL_30_31_VAL           (0)
+       #define PMX_PL_30_MASK                  (0x7 << 0)
+       #define PMX_PL_31_MASK                  (0x7 << 3)
+       #define PMX_PWM1_EXT_PL_30_VAL          (0x4 << 0)
+       #define PMX_PWM0_EXT_PL_31_VAL          (0x4 << 3)
+       #define PMX_UART1_ENH_PL_31_VAL         (0x3 << 3)
+
+       #define PMX_PL_32_33_MASK               (0x3F << 6)
+       #define PMX_CAN0_PL_32_33_VAL           0
+       #define PMX_UART1_ENH_PL_32_33_VAL      ((0x3 << 6) | (0x3 << 9))
+       #define PMX_SSP2_PL_32_33_VAL           ((0x4 << 6) | (0x4 << 9))
+
+       #define PMX_PL_34_MASK                  (0x7 << 12)
+       #define PMX_PWM2_PL_34_VAL              0
+       #define PMX_UART1_ENH_PL_34_VAL         (0x2 << 12)
+       #define PMX_SSP2_PL_34_VAL              (0x4 << 12)
+
+       #define PMX_PL_35_MASK                  (0x7 << 15)
+       #define PMX_I2S_REF_CLK_PL_35_VAL       0
+       #define PMX_UART1_ENH_PL_35_VAL         (0x2 << 15)
+       #define PMX_SSP2_PL_35_VAL              (0x4 << 15)
+
+       #define PMX_PL_36_MASK                  (0x7 << 18)
+       #define PMX_TOUCH_X_PL_36_VAL           0
+       #define PMX_UART1_ENH_PL_36_VAL         (0x2 << 18)
+       #define PMX_SSP1_PL_36_VAL              (0x4 << 18)
+
+       #define PMX_PL_37_38_MASK               (0x3F << 21)
+       #define PMX_PWM0_1_PL_37_38_VAL         0
+       #define PMX_UART5_PL_37_38_VAL          ((0x2 << 21) | (0x2 << 24))
+       #define PMX_SSP1_PL_37_38_VAL           ((0x4 << 21) | (0x4 << 24))
+
+       #define PMX_PL_39_MASK                  (0x7 << 27)
+       #define PMX_I2S_PL_39_VAL               0
+       #define PMX_UART4_PL_39_VAL             (0x2 << 27)
+       #define PMX_SSP1_PL_39_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_40_49_REG                   0x00B4
+       #define PMX_PL_40_MASK                  (0x7 << 0)
+       #define PMX_I2S_PL_40_VAL               0
+       #define PMX_UART4_PL_40_VAL             (0x2 << 0)
+       #define PMX_PWM3_PL_40_VAL              (0x4 << 0)
+
+       #define PMX_PL_41_42_MASK               (0x3F << 3)
+       #define PMX_PL_41_MASK                  (0x7 << 3)
+       #define PMX_PL_42_MASK                  (0x7 << 6)
+       #define PMX_I2S_PL_41_42_VAL            0
+       #define PMX_UART3_PL_41_42_VAL          ((0x2 << 3) | (0x2 << 6))
+       #define PMX_PWM2_PL_41_VAL              (0x4 << 3)
+       #define PMX_PWM1_PL_42_VAL              (0x4 << 6)
+
+       #define PMX_PL_43_MASK                  (0x7 << 9)
+       #define PMX_SDHCI_PL_43_VAL             0
+       #define PMX_UART1_ENH_PL_43_VAL         (0x2 << 9)
+       #define PMX_PWM0_PL_43_VAL              (0x4 << 9)
+
+       #define PMX_PL_44_45_MASK               (0x3F << 12)
+       #define PMX_SDHCI_PL_44_45_VAL  0
+       #define PMX_UART1_ENH_PL_44_45_VAL      ((0x2 << 12) | (0x2 << 15))
+       #define PMX_SSP2_PL_44_45_VAL           ((0x4 << 12) | (0x4 << 15))
+
+       #define PMX_PL_46_47_MASK               (0x3F << 18)
+       #define PMX_SDHCI_PL_46_47_VAL  0
+       #define PMX_FSMC_EMI_PL_46_47_VAL       ((0x2 << 18) | (0x2 << 21))
+       #define PMX_SSP2_PL_46_47_VAL           ((0x4 << 18) | (0x4 << 21))
+
+       #define PMX_PL_48_49_MASK               (0x3F << 24)
+       #define PMX_SDHCI_PL_48_49_VAL  0
+       #define PMX_FSMC_EMI_PL_48_49_VAL       ((0x2 << 24) | (0x2 << 27))
+       #define PMX_SSP1_PL_48_49_VAL           ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_50_59_REG                   0x00B8
+       #define PMX_PL_50_51_MASK               (0x3F << 0)
+       #define PMX_EMI_PL_50_51_VAL            ((0x2 << 0) | (0x2 << 3))
+       #define PMX_SSP1_PL_50_51_VAL           ((0x4 << 0) | (0x4 << 3))
+       #define PMX_PL_50_MASK                  (0x7 << 0)
+       #define PMX_PL_51_MASK                  (0x7 << 3)
+       #define PMX_SDHCI_PL_50_VAL             0
+       #define PMX_SDHCI_CD_PL_51_VAL          0
+
+       #define PMX_PL_52_53_MASK               (0x3F << 6)
+       #define PMX_FSMC_PL_52_53_VAL           0
+       #define PMX_EMI_PL_52_53_VAL            ((0x2 << 6) | (0x2 << 9))
+       #define PMX_UART3_PL_52_53_VAL          ((0x4 << 6) | (0x4 << 9))
+
+       #define PMX_PL_54_55_56_MASK            (0x1FF << 12)
+       #define PMX_FSMC_EMI_PL_54_55_56_VAL    ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
+
+       #define PMX_PL_57_MASK                  (0x7 << 21)
+       #define PMX_FSMC_PL_57_VAL              0
+       #define PMX_PWM3_PL_57_VAL              (0x4 << 21)
+
+       #define PMX_PL_58_59_MASK               (0x3F << 24)
+       #define PMX_PL_58_MASK                  (0x7 << 24)
+       #define PMX_PL_59_MASK                  (0x7 << 27)
+       #define PMX_FSMC_EMI_PL_58_59_VAL       ((0x2 << 24) | (0x2 << 27))
+       #define PMX_PWM2_PL_58_VAL              (0x4 << 24)
+       #define PMX_PWM1_PL_59_VAL              (0x4 << 27)
+
+#define IP_SEL_PAD_60_69_REG                   0x00BC
+       #define PMX_PL_60_MASK                  (0x7 << 0)
+       #define PMX_FSMC_PL_60_VAL              0
+       #define PMX_PWM0_PL_60_VAL              (0x4 << 0)
+
+       #define PMX_PL_61_TO_64_MASK            (0xFFF << 3)
+       #define PMX_FSMC_PL_61_TO_64_VAL        ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
+       #define PMX_SSP2_PL_61_TO_64_VAL        ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
+
+       #define PMX_PL_65_TO_68_MASK            (0xFFF << 15)
+       #define PMX_FSMC_PL_65_TO_68_VAL        ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
+       #define PMX_SSP1_PL_65_TO_68_VAL        ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
+
+       #define PMX_PL_69_MASK                  (0x7 << 27)
+       #define PMX_CLCD_PL_69_VAL              (0)
+       #define PMX_EMI_PL_69_VAL               (0x2 << 27)
+       #define PMX_SPP_PL_69_VAL               (0x3 << 27)
+       #define PMX_UART5_PL_69_VAL             (0x4 << 27)
+
+#define IP_SEL_PAD_70_79_REG                   0x00C0
+       #define PMX_PL_70_MASK                  (0x7 << 0)
+       #define PMX_CLCD_PL_70_VAL              (0)
+       #define PMX_FSMC_EMI_PL_70_VAL          (0x2 << 0)
+       #define PMX_SPP_PL_70_VAL               (0x3 << 0)
+       #define PMX_UART5_PL_70_VAL             (0x4 << 0)
+
+       #define PMX_PL_71_72_MASK               (0x3F << 3)
+       #define PMX_CLCD_PL_71_72_VAL           (0)
+       #define PMX_FSMC_EMI_PL_71_72_VAL       ((0x2 << 3) | (0x2 << 6))
+       #define PMX_SPP_PL_71_72_VAL            ((0x3 << 3) | (0x3 << 6))
+       #define PMX_UART4_PL_71_72_VAL          ((0x4 << 3) | (0x4 << 6))
+
+       #define PMX_PL_73_MASK                  (0x7 << 9)
+       #define PMX_CLCD_PL_73_VAL              (0)
+       #define PMX_FSMC_EMI_PL_73_VAL          (0x2 << 9)
+       #define PMX_SPP_PL_73_VAL               (0x3 << 9)
+       #define PMX_UART3_PL_73_VAL             (0x4 << 9)
+
+       #define PMX_PL_74_MASK                  (0x7 << 12)
+       #define PMX_CLCD_PL_74_VAL              (0)
+       #define PMX_EMI_PL_74_VAL               (0x2 << 12)
+       #define PMX_SPP_PL_74_VAL               (0x3 << 12)
+       #define PMX_UART3_PL_74_VAL             (0x4 << 12)
+
+       #define PMX_PL_75_76_MASK               (0x3F << 15)
+       #define PMX_CLCD_PL_75_76_VAL           (0)
+       #define PMX_EMI_PL_75_76_VAL            ((0x2 << 15) | (0x2 << 18))
+       #define PMX_SPP_PL_75_76_VAL            ((0x3 << 15) | (0x3 << 18))
+       #define PMX_I2C2_PL_75_76_VAL           ((0x4 << 15) | (0x4 << 18))
+
+       #define PMX_PL_77_78_79_MASK            (0x1FF << 21)
+       #define PMX_CLCD_PL_77_78_79_VAL        (0)
+       #define PMX_EMI_PL_77_78_79_VAL         ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
+       #define PMX_SPP_PL_77_78_79_VAL         ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
+       #define PMX_RS485_PL_77_78_79_VAL       ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_80_89_REG                   0x00C4
+       #define PMX_PL_80_TO_85_MASK            (0x3FFFF << 0)
+       #define PMX_CLCD_PL_80_TO_85_VAL        0
+       #define PMX_MII2_PL_80_TO_85_VAL        ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
+       #define PMX_EMI_PL_80_TO_85_VAL         ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
+       #define PMX_SPP_PL_80_TO_85_VAL         ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
+       #define PMX_UART1_ENH_PL_80_TO_85_VAL   ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
+
+       #define PMX_PL_86_87_MASK               (0x3F << 18)
+       #define PMX_PL_86_MASK                  (0x7 << 18)
+       #define PMX_PL_87_MASK                  (0x7 << 21)
+       #define PMX_CLCD_PL_86_87_VAL           0
+       #define PMX_MII2_PL_86_87_VAL           ((0x1 << 18) | (0x1 << 21))
+       #define PMX_EMI_PL_86_87_VAL            ((0x2 << 18) | (0x2 << 21))
+       #define PMX_PWM3_PL_86_VAL              (0x4 << 18)
+       #define PMX_PWM2_PL_87_VAL              (0x4 << 21)
+
+       #define PMX_PL_88_89_MASK               (0x3F << 24)
+       #define PMX_CLCD_PL_88_89_VAL           0
+       #define PMX_MII2_PL_88_89_VAL           ((0x1 << 24) | (0x1 << 27))
+       #define PMX_EMI_PL_88_89_VAL            ((0x2 << 24) | (0x2 << 27))
+       #define PMX_UART6_PL_88_89_VAL          ((0x3 << 24) | (0x3 << 27))
+       #define PMX_PWM0_1_PL_88_89_VAL         ((0x4 << 24) | (0x4 << 27))
+
+#define IP_SEL_PAD_90_99_REG                   0x00C8
+       #define PMX_PL_90_91_MASK               (0x3F << 0)
+       #define PMX_CLCD_PL_90_91_VAL           0
+       #define PMX_MII2_PL_90_91_VAL           ((0x1 << 0) | (0x1 << 3))
+       #define PMX_EMI1_PL_90_91_VAL           ((0x2 << 0) | (0x2 << 3))
+       #define PMX_UART5_PL_90_91_VAL          ((0x3 << 0) | (0x3 << 3))
+       #define PMX_SSP2_PL_90_91_VAL           ((0x4 << 0) | (0x4 << 3))
+
+       #define PMX_PL_92_93_MASK               (0x3F << 6)
+       #define PMX_CLCD_PL_92_93_VAL           0
+       #define PMX_MII2_PL_92_93_VAL           ((0x1 << 6) | (0x1 << 9))
+       #define PMX_EMI1_PL_92_93_VAL           ((0x2 << 6) | (0x2 << 9))
+       #define PMX_UART4_PL_92_93_VAL          ((0x3 << 6) | (0x3 << 9))
+       #define PMX_SSP2_PL_92_93_VAL           ((0x4 << 6) | (0x4 << 9))
+
+       #define PMX_PL_94_95_MASK               (0x3F << 12)
+       #define PMX_CLCD_PL_94_95_VAL           0
+       #define PMX_MII2_PL_94_95_VAL           ((0x1 << 12) | (0x1 << 15))
+       #define PMX_EMI1_PL_94_95_VAL           ((0x2 << 12) | (0x2 << 15))
+       #define PMX_UART3_PL_94_95_VAL          ((0x3 << 12) | (0x3 << 15))
+       #define PMX_SSP1_PL_94_95_VAL           ((0x4 << 12) | (0x4 << 15))
+
+       #define PMX_PL_96_97_MASK               (0x3F << 18)
+       #define PMX_CLCD_PL_96_97_VAL           0
+       #define PMX_MII2_PL_96_97_VAL           ((0x1 << 18) | (0x1 << 21))
+       #define PMX_EMI1_PL_96_97_VAL           ((0x2 << 18) | (0x2 << 21))
+       #define PMX_I2C2_PL_96_97_VAL           ((0x3 << 18) | (0x3 << 21))
+       #define PMX_SSP1_PL_96_97_VAL           ((0x4 << 18) | (0x4 << 21))
+
+       #define PMX_PL_98_MASK                  (0x7 << 24)
+       #define PMX_CLCD_PL_98_VAL              0
+       #define PMX_I2C1_PL_98_VAL              (0x2 << 24)
+       #define PMX_UART3_PL_98_VAL             (0x4 << 24)
+
+       #define PMX_PL_99_MASK                  (0x7 << 27)
+       #define PMX_SDHCI_PL_99_VAL             0
+       #define PMX_I2C1_PL_99_VAL              (0x2 << 27)
+       #define PMX_UART3_PL_99_VAL             (0x4 << 27)
+
+#define IP_SEL_MIX_PAD_REG                     0x00CC
+       #define PMX_PL_100_101_MASK             (0x3F << 0)
+       #define PMX_SDHCI_PL_100_101_VAL        0
+       #define PMX_UART4_PL_100_101_VAL        ((0x4 << 0) | (0x4 << 3))
+
+       #define PMX_SSP1_PORT_SEL_MASK          (0x7 << 8)
+       #define PMX_SSP1_PORT_94_TO_97_VAL      0
+       #define PMX_SSP1_PORT_65_TO_68_VAL      (0x1 << 8)
+       #define PMX_SSP1_PORT_48_TO_51_VAL      (0x2 << 8)
+       #define PMX_SSP1_PORT_36_TO_39_VAL      (0x3 << 8)
+       #define PMX_SSP1_PORT_17_TO_20_VAL      (0x4 << 8)
+
+       #define PMX_SSP2_PORT_SEL_MASK          (0x7 << 11)
+       #define PMX_SSP2_PORT_90_TO_93_VAL      0
+       #define PMX_SSP2_PORT_61_TO_64_VAL      (0x1 << 11)
+       #define PMX_SSP2_PORT_44_TO_47_VAL      (0x2 << 11)
+       #define PMX_SSP2_PORT_32_TO_35_VAL      (0x3 << 11)
+       #define PMX_SSP2_PORT_13_TO_16_VAL      (0x4 << 11)
+
+       #define PMX_UART1_ENH_PORT_SEL_MASK             (0x3 << 14)
+       #define PMX_UART1_ENH_PORT_81_TO_85_VAL         0
+       #define PMX_UART1_ENH_PORT_44_45_34_36_VAL      (0x1 << 14)
+       #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL      (0x2 << 14)
+       #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL         (0x3 << 14)
+
+       #define PMX_UART3_PORT_SEL_MASK         (0x7 << 16)
+       #define PMX_UART3_PORT_94_VAL           0
+       #define PMX_UART3_PORT_73_VAL           (0x1 << 16)
+       #define PMX_UART3_PORT_52_VAL           (0x2 << 16)
+       #define PMX_UART3_PORT_41_VAL           (0x3 << 16)
+       #define PMX_UART3_PORT_15_VAL           (0x4 << 16)
+       #define PMX_UART3_PORT_8_VAL            (0x5 << 16)
+       #define PMX_UART3_PORT_99_VAL           (0x6 << 16)
+
+       #define PMX_UART4_PORT_SEL_MASK         (0x7 << 19)
+       #define PMX_UART4_PORT_92_VAL           0
+       #define PMX_UART4_PORT_71_VAL           (0x1 << 19)
+       #define PMX_UART4_PORT_39_VAL           (0x2 << 19)
+       #define PMX_UART4_PORT_13_VAL           (0x3 << 19)
+       #define PMX_UART4_PORT_6_VAL            (0x4 << 19)
+       #define PMX_UART4_PORT_101_VAL          (0x5 << 19)
+
+       #define PMX_UART5_PORT_SEL_MASK         (0x3 << 22)
+       #define PMX_UART5_PORT_90_VAL           0
+       #define PMX_UART5_PORT_69_VAL           (0x1 << 22)
+       #define PMX_UART5_PORT_37_VAL           (0x2 << 22)
+       #define PMX_UART5_PORT_4_VAL            (0x3 << 22)
+
+       #define PMX_UART6_PORT_SEL_MASK         (0x1 << 24)
+       #define PMX_UART6_PORT_88_VAL           0
+       #define PMX_UART6_PORT_2_VAL            (0x1 << 24)
+
+       #define PMX_I2C1_PORT_SEL_MASK          (0x1 << 25)
+       #define PMX_I2C1_PORT_8_9_VAL           0
+       #define PMX_I2C1_PORT_98_99_VAL         (0x1 << 25)
+
+       #define PMX_I2C2_PORT_SEL_MASK          (0x3 << 26)
+       #define PMX_I2C2_PORT_96_97_VAL         0
+       #define PMX_I2C2_PORT_75_76_VAL         (0x1 << 26)
+       #define PMX_I2C2_PORT_19_20_VAL         (0x2 << 26)
+       #define PMX_I2C2_PORT_2_3_VAL           (0x3 << 26)
+       #define PMX_I2C2_PORT_0_1_VAL           (0x4 << 26)
+
+       #define PMX_SDHCI_CD_PORT_SEL_MASK      (0x1 << 29)
+       #define PMX_SDHCI_CD_PORT_12_VAL        0
+       #define PMX_SDHCI_CD_PORT_51_VAL        (0x1 << 29)
+
+/* Pad multiplexing for CLCD device */
+static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
+       79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
+       97 };
+static struct spear_muxreg clcd_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_60_69_REG,
+               .mask = PMX_PL_69_MASK,
+               .val = PMX_CLCD_PL_69_VAL,
+       }, {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                       PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                       PMX_PL_77_78_79_MASK,
+               .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
+                       PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
+                       PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
+       }, {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                       PMX_PL_88_89_MASK,
+               .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
+                       PMX_CLCD_PL_88_89_VAL,
+       }, {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                       PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
+               .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
+                       PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
+                       PMX_CLCD_PL_98_VAL,
+       },
+};
+
+static struct spear_modemux clcd_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = clcd_muxreg,
+               .nmuxregs = ARRAY_SIZE(clcd_muxreg),
+       },
+};
+
+static struct spear_pingroup clcd_pingroup = {
+       .name = "clcd_grp",
+       .pins = clcd_pins,
+       .npins = ARRAY_SIZE(clcd_pins),
+       .modemuxs = clcd_modemux,
+       .nmodemuxs = ARRAY_SIZE(clcd_modemux),
+};
+
+static const char *const clcd_grps[] = { "clcd_grp" };
+static struct spear_function clcd_function = {
+       .name = "clcd",
+       .groups = clcd_grps,
+       .ngroups = ARRAY_SIZE(clcd_grps),
+};
+
+/* Pad multiplexing for EMI (Parallel NOR flash) device */
+static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
+       57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
+       75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
+       93, 94, 95, 96, 97 };
+static struct spear_muxreg emi_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg emi_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+               .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
+       }, {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
+                       PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
+               .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
+                       PMX_FSMC_EMI_PL_54_55_56_VAL |
+                       PMX_FSMC_EMI_PL_58_59_VAL,
+       }, {
+               .reg = IP_SEL_PAD_60_69_REG,
+               .mask = PMX_PL_69_MASK,
+               .val = PMX_EMI_PL_69_VAL,
+       }, {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                       PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                       PMX_PL_77_78_79_MASK,
+               .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+                       PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
+                       PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
+       }, {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                       PMX_PL_88_89_MASK,
+               .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
+                       PMX_EMI_PL_88_89_VAL,
+       }, {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                       PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+               .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
+                       PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
+       }, {
+               .reg = EXT_CTRL_REG,
+               .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
+               .val = EMI_FSMC_DYNAMIC_MUX_MASK,
+       },
+};
+
+static struct spear_modemux emi_modemux[] = {
+       {
+               .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+               .muxregs = emi_muxreg,
+               .nmuxregs = ARRAY_SIZE(emi_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = emi_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
+       },
+};
+
+static struct spear_pingroup emi_pingroup = {
+       .name = "emi_grp",
+       .pins = emi_pins,
+       .npins = ARRAY_SIZE(emi_pins),
+       .modemuxs = emi_modemux,
+       .nmodemuxs = ARRAY_SIZE(emi_modemux),
+};
+
+static const char *const emi_grps[] = { "emi_grp" };
+static struct spear_function emi_function = {
+       .name = "emi",
+       .groups = emi_grps,
+       .ngroups = ARRAY_SIZE(emi_grps),
+};
+
+/* Pad multiplexing for FSMC (NAND flash) device */
+static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
+       61, 62, 63, 64, 65, 66, 67, 68 };
+static struct spear_muxreg fsmc_8bit_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
+                       PMX_PL_57_MASK | PMX_PL_58_59_MASK,
+               .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
+                       PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
+       }, {
+               .reg = IP_SEL_PAD_60_69_REG,
+               .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
+                       PMX_PL_65_TO_68_MASK,
+               .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
+                       PMX_FSMC_PL_65_TO_68_VAL,
+       }, {
+               .reg = EXT_CTRL_REG,
+               .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
+               .val = EMI_FSMC_DYNAMIC_MUX_MASK,
+       },
+};
+
+static struct spear_modemux fsmc_8bit_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = fsmc_8bit_muxreg,
+               .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
+       },
+};
+
+static struct spear_pingroup fsmc_8bit_pingroup = {
+       .name = "fsmc_8bit_grp",
+       .pins = fsmc_8bit_pins,
+       .npins = ARRAY_SIZE(fsmc_8bit_pins),
+       .modemuxs = fsmc_8bit_modemux,
+       .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
+};
+
+static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
+       57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
+static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg fsmc_16bit_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
+               .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
+       }, {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
+               .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
+                       PMX_FSMC_EMI_PL_73_VAL,
+       }
+};
+
+static struct spear_modemux fsmc_16bit_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = fsmc_8bit_muxreg,
+               .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
+       }, {
+               .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+               .muxregs = fsmc_16bit_autoexp_muxreg,
+               .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = fsmc_16bit_muxreg,
+               .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
+       },
+};
+
+static struct spear_pingroup fsmc_16bit_pingroup = {
+       .name = "fsmc_16bit_grp",
+       .pins = fsmc_16bit_pins,
+       .npins = ARRAY_SIZE(fsmc_16bit_pins),
+       .modemuxs = fsmc_16bit_modemux,
+       .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
+};
+
+static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
+static struct spear_function fsmc_function = {
+       .name = "fsmc",
+       .groups = fsmc_grps,
+       .ngroups = ARRAY_SIZE(fsmc_grps),
+};
+
+/* Pad multiplexing for SPP device */
+static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+       80, 81, 82, 83, 84, 85 };
+static struct spear_muxreg spp_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_60_69_REG,
+               .mask = PMX_PL_69_MASK,
+               .val = PMX_SPP_PL_69_VAL,
+       }, {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
+                       PMX_PL_74_MASK | PMX_PL_75_76_MASK |
+                       PMX_PL_77_78_79_MASK,
+               .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
+                       PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
+                       PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
+       }, {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_80_TO_85_MASK,
+               .val = PMX_SPP_PL_80_TO_85_VAL,
+       },
+};
+
+static struct spear_modemux spp_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = spp_muxreg,
+               .nmuxregs = ARRAY_SIZE(spp_muxreg),
+       },
+};
+
+static struct spear_pingroup spp_pingroup = {
+       .name = "spp_grp",
+       .pins = spp_pins,
+       .npins = ARRAY_SIZE(spp_pins),
+       .modemuxs = spp_modemux,
+       .nmodemuxs = ARRAY_SIZE(spp_modemux),
+};
+
+static const char *const spp_grps[] = { "spp_grp" };
+static struct spear_function spp_function = {
+       .name = "spp",
+       .groups = spp_grps,
+       .ngroups = ARRAY_SIZE(spp_grps),
+};
+
+/* Pad multiplexing for SDHCI device */
+static const unsigned sdhci_led_pins[] = { 34 };
+static struct spear_muxreg sdhci_led_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_CS_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg sdhci_led_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_34_MASK,
+               .val = PMX_PWM2_PL_34_VAL,
+       },
+};
+
+static struct spear_modemux sdhci_led_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+               .muxregs = sdhci_led_muxreg,
+               .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = sdhci_led_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
+       },
+};
+
+static struct spear_pingroup sdhci_led_pingroup = {
+       .name = "sdhci_led_grp",
+       .pins = sdhci_led_pins,
+       .npins = ARRAY_SIZE(sdhci_led_pins),
+       .modemuxs = sdhci_led_modemux,
+       .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
+};
+
+static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
+       50};
+static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+static struct spear_muxreg sdhci_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg sdhci_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
+                       PMX_PL_48_49_MASK,
+               .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
+                       PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
+       }, {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_50_MASK,
+               .val = PMX_SDHCI_PL_50_VAL,
+       }, {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_99_MASK,
+               .val = PMX_SDHCI_PL_99_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_PL_100_101_MASK,
+               .val = PMX_SDHCI_PL_100_101_VAL,
+       },
+};
+
+static struct spear_muxreg sdhci_cd_12_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_12_MASK,
+               .val = PMX_SDHCI_CD_PL_12_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
+               .val = PMX_SDHCI_CD_PORT_12_VAL,
+       },
+};
+
+static struct spear_muxreg sdhci_cd_51_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_51_MASK,
+               .val = PMX_SDHCI_CD_PL_51_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
+               .val = PMX_SDHCI_CD_PORT_51_VAL,
+       },
+};
+
+#define pmx_sdhci_common_modemux                                       \
+       {                                                               \
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |       \
+                       SMALL_PRINTERS_MODE | EXTENDED_MODE,            \
+               .muxregs = sdhci_muxreg,                                \
+               .nmuxregs = ARRAY_SIZE(sdhci_muxreg),                   \
+       }, {                                                            \
+               .modes = EXTENDED_MODE,                                 \
+               .muxregs = sdhci_ext_muxreg,                            \
+               .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg),               \
+       }
+
+static struct spear_modemux sdhci_modemux[][3] = {
+       {
+               /* select pin 12 for cd */
+               pmx_sdhci_common_modemux,
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = sdhci_cd_12_muxreg,
+                       .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
+               },
+       }, {
+               /* select pin 51 for cd */
+               pmx_sdhci_common_modemux,
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = sdhci_cd_51_muxreg,
+                       .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
+               },
+       }
+};
+
+static struct spear_pingroup sdhci_pingroup[] = {
+       {
+               .name = "sdhci_cd_12_grp",
+               .pins = sdhci_cd_12_pins,
+               .npins = ARRAY_SIZE(sdhci_cd_12_pins),
+               .modemuxs = sdhci_modemux[0],
+               .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
+       }, {
+               .name = "sdhci_cd_51_grp",
+               .pins = sdhci_cd_51_pins,
+               .npins = ARRAY_SIZE(sdhci_cd_51_pins),
+               .modemuxs = sdhci_modemux[1],
+               .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
+       },
+};
+
+static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
+       "sdhci_led_grp" };
+
+static struct spear_function sdhci_function = {
+       .name = "sdhci",
+       .groups = sdhci_grps,
+       .ngroups = ARRAY_SIZE(sdhci_grps),
+};
+
+/* Pad multiplexing for I2S device */
+static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
+static struct spear_muxreg i2s_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_CS_MASK,
+               .val = 0,
+       }, {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg i2s_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
+               .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
+               .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
+       },
+};
+
+static struct spear_modemux i2s_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+               .muxregs = i2s_muxreg,
+               .nmuxregs = ARRAY_SIZE(i2s_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = i2s_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
+       },
+};
+
+static struct spear_pingroup i2s_pingroup = {
+       .name = "i2s_grp",
+       .pins = i2s_pins,
+       .npins = ARRAY_SIZE(i2s_pins),
+       .modemuxs = i2s_modemux,
+       .nmodemuxs = ARRAY_SIZE(i2s_modemux),
+};
+
+static const char *const i2s_grps[] = { "i2s_grp" };
+static struct spear_function i2s_function = {
+       .name = "i2s",
+       .groups = i2s_grps,
+       .ngroups = ARRAY_SIZE(i2s_grps),
+};
+
+/* Pad multiplexing for UART1 device */
+static const unsigned uart1_pins[] = { 28, 29 };
+static struct spear_muxreg uart1_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg uart1_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_20_29_REG,
+               .mask = PMX_PL_28_29_MASK,
+               .val = PMX_UART1_PL_28_29_VAL,
+       },
+};
+
+static struct spear_modemux uart1_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                       | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+               .muxregs = uart1_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = uart1_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
+       },
+};
+
+static struct spear_pingroup uart1_pingroup = {
+       .name = "uart1_grp",
+       .pins = uart1_pins,
+       .npins = ARRAY_SIZE(uart1_pins),
+       .modemuxs = uart1_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart1_modemux),
+};
+
+static const char *const uart1_grps[] = { "uart1_grp" };
+static struct spear_function uart1_function = {
+       .name = "uart1",
+       .groups = uart1_grps,
+       .ngroups = ARRAY_SIZE(uart1_grps),
+};
+
+/* Pad multiplexing for UART1 Modem device */
+static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
+static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
+static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
+static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
+
+static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
+               .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
+                       PMX_UART1_ENH_PL_6_7_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+               .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
+       },
+};
+
+static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
+                       PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
+                       PMX_PL_35_MASK | PMX_PL_36_MASK,
+               .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
+                       PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+                       PMX_UART1_ENH_PL_36_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+               .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
+       },
+};
+
+static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
+                       PMX_SSP_CS_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
+               .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
+                       PMX_UART1_ENH_PL_36_VAL,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+               .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+               .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
+       },
+};
+
+static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_80_TO_85_MASK,
+               .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
+               .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART1_ENH_PORT_SEL_MASK,
+               .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
+       },
+};
+
+static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = uart1_modem_ext_2_to_7_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
+       },
+};
+
+static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
+       {
+               .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
+               .muxregs = uart1_modem_31_to_36_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = uart1_modem_ext_31_to_36_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
+       },
+};
+
+static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
+       {
+               .modes = AUTO_EXP_MODE | EXTENDED_MODE,
+               .muxregs = uart1_modem_34_to_45_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = uart1_modem_ext_34_to_45_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
+       },
+};
+
+static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = uart1_modem_ext_80_to_85_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
+       },
+};
+
+static struct spear_pingroup uart1_modem_pingroup[] = {
+       {
+               .name = "uart1_modem_2_to_7_grp",
+               .pins = uart1_modem_2_to_7_pins,
+               .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
+               .modemuxs = uart1_modem_2_to_7_modemux,
+               .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
+       }, {
+               .name = "uart1_modem_31_to_36_grp",
+               .pins = uart1_modem_31_to_36_pins,
+               .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
+               .modemuxs = uart1_modem_31_to_36_modemux,
+               .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
+       }, {
+               .name = "uart1_modem_34_to_45_grp",
+               .pins = uart1_modem_34_to_45_pins,
+               .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
+               .modemuxs = uart1_modem_34_to_45_modemux,
+               .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
+       }, {
+               .name = "uart1_modem_80_to_85_grp",
+               .pins = uart1_modem_80_to_85_pins,
+               .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
+               .modemuxs = uart1_modem_80_to_85_modemux,
+               .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
+       },
+};
+
+static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
+       "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
+       "uart1_modem_80_to_85_grp" };
+static struct spear_function uart1_modem_function = {
+       .name = "uart1_modem",
+       .groups = uart1_modem_grps,
+       .ngroups = ARRAY_SIZE(uart1_modem_grps),
+};
+
+/* Pad multiplexing for UART2 device */
+static const unsigned uart2_pins[] = { 0, 1 };
+static struct spear_muxreg uart2_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_FIRDA_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg uart2_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_0_1_MASK,
+               .val = PMX_UART2_PL_0_1_VAL,
+       },
+};
+
+static struct spear_modemux uart2_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                       | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+               .muxregs = uart2_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart2_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = uart2_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
+       },
+};
+
+static struct spear_pingroup uart2_pingroup = {
+       .name = "uart2_grp",
+       .pins = uart2_pins,
+       .npins = ARRAY_SIZE(uart2_pins),
+       .modemuxs = uart2_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart2_modemux),
+};
+
+static const char *const uart2_grps[] = { "uart2_grp" };
+static struct spear_function uart2_function = {
+       .name = "uart2",
+       .groups = uart2_grps,
+       .ngroups = ARRAY_SIZE(uart2_grps),
+};
+
+/* Pad multiplexing for uart3 device */
+static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
+       { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
+
+static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_8_9_MASK,
+               .val = PMX_UART3_PL_8_9_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART3_PORT_SEL_MASK,
+               .val = PMX_UART3_PORT_8_VAL,
+       },
+};
+
+static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_15_16_MASK,
+               .val = PMX_UART3_PL_15_16_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART3_PORT_SEL_MASK,
+               .val = PMX_UART3_PORT_15_VAL,
+       },
+};
+
+static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_41_42_MASK,
+               .val = PMX_UART3_PL_41_42_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART3_PORT_SEL_MASK,
+               .val = PMX_UART3_PORT_41_VAL,
+       },
+};
+
+static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_52_53_MASK,
+               .val = PMX_UART3_PL_52_53_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART3_PORT_SEL_MASK,
+               .val = PMX_UART3_PORT_52_VAL,
+       },
+};
+
+static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
+               .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART3_PORT_SEL_MASK,
+               .val = PMX_UART3_PORT_73_VAL,
+       },
+};
+
+static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_94_95_MASK,
+               .val = PMX_UART3_PL_94_95_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART3_PORT_SEL_MASK,
+               .val = PMX_UART3_PORT_94_VAL,
+       },
+};
+
+static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
+               .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART3_PORT_SEL_MASK,
+               .val = PMX_UART3_PORT_99_VAL,
+       },
+};
+
+static struct spear_modemux uart3_modemux[][1] = {
+       {
+               /* Select signals on pins 8_9 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart3_ext_8_9_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
+               },
+       }, {
+               /* Select signals on pins 15_16 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart3_ext_15_16_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
+               },
+       }, {
+               /* Select signals on pins 41_42 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart3_ext_41_42_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
+               },
+       }, {
+               /* Select signals on pins 52_53 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart3_ext_52_53_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
+               },
+       }, {
+               /* Select signals on pins 73_74 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart3_ext_73_74_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
+               },
+       }, {
+               /* Select signals on pins 94_95 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart3_ext_94_95_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
+               },
+       }, {
+               /* Select signals on pins 98_99 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart3_ext_98_99_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
+               },
+       },
+};
+
+static struct spear_pingroup uart3_pingroup[] = {
+       {
+               .name = "uart3_8_9_grp",
+               .pins = uart3_pins[0],
+               .npins = ARRAY_SIZE(uart3_pins[0]),
+               .modemuxs = uart3_modemux[0],
+               .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
+       }, {
+               .name = "uart3_15_16_grp",
+               .pins = uart3_pins[1],
+               .npins = ARRAY_SIZE(uart3_pins[1]),
+               .modemuxs = uart3_modemux[1],
+               .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
+       }, {
+               .name = "uart3_41_42_grp",
+               .pins = uart3_pins[2],
+               .npins = ARRAY_SIZE(uart3_pins[2]),
+               .modemuxs = uart3_modemux[2],
+               .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
+       }, {
+               .name = "uart3_52_53_grp",
+               .pins = uart3_pins[3],
+               .npins = ARRAY_SIZE(uart3_pins[3]),
+               .modemuxs = uart3_modemux[3],
+               .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
+       }, {
+               .name = "uart3_73_74_grp",
+               .pins = uart3_pins[4],
+               .npins = ARRAY_SIZE(uart3_pins[4]),
+               .modemuxs = uart3_modemux[4],
+               .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
+       }, {
+               .name = "uart3_94_95_grp",
+               .pins = uart3_pins[5],
+               .npins = ARRAY_SIZE(uart3_pins[5]),
+               .modemuxs = uart3_modemux[5],
+               .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
+       }, {
+               .name = "uart3_98_99_grp",
+               .pins = uart3_pins[6],
+               .npins = ARRAY_SIZE(uart3_pins[6]),
+               .modemuxs = uart3_modemux[6],
+               .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
+       },
+};
+
+static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
+       "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
+       "uart3_94_95_grp", "uart3_98_99_grp" };
+
+static struct spear_function uart3_function = {
+       .name = "uart3",
+       .groups = uart3_grps,
+       .ngroups = ARRAY_SIZE(uart3_grps),
+};
+
+/* Pad multiplexing for uart4 device */
+static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
+       { 71, 72 }, { 92, 93 }, { 100, 101 } };
+
+static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_6_7_MASK,
+               .val = PMX_UART4_PL_6_7_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART4_PORT_SEL_MASK,
+               .val = PMX_UART4_PORT_6_VAL,
+       },
+};
+
+static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_13_14_MASK,
+               .val = PMX_UART4_PL_13_14_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART4_PORT_SEL_MASK,
+               .val = PMX_UART4_PORT_13_VAL,
+       },
+};
+
+static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_39_MASK,
+               .val = PMX_UART4_PL_39_VAL,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_40_MASK,
+               .val = PMX_UART4_PL_40_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART4_PORT_SEL_MASK,
+               .val = PMX_UART4_PORT_39_VAL,
+       },
+};
+
+static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_71_72_MASK,
+               .val = PMX_UART4_PL_71_72_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART4_PORT_SEL_MASK,
+               .val = PMX_UART4_PORT_71_VAL,
+       },
+};
+
+static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_92_93_MASK,
+               .val = PMX_UART4_PL_92_93_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART4_PORT_SEL_MASK,
+               .val = PMX_UART4_PORT_92_VAL,
+       },
+};
+
+static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
+       {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_PL_100_101_MASK |
+                       PMX_UART4_PORT_SEL_MASK,
+               .val = PMX_UART4_PL_100_101_VAL |
+                       PMX_UART4_PORT_101_VAL,
+       },
+};
+
+static struct spear_modemux uart4_modemux[][1] = {
+       {
+               /* Select signals on pins 6_7 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart4_ext_6_7_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
+               },
+       }, {
+               /* Select signals on pins 13_14 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart4_ext_13_14_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
+               },
+       }, {
+               /* Select signals on pins 39_40 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart4_ext_39_40_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
+               },
+       }, {
+               /* Select signals on pins 71_72 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart4_ext_71_72_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
+               },
+       }, {
+               /* Select signals on pins 92_93 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart4_ext_92_93_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
+               },
+       }, {
+               /* Select signals on pins 100_101_ */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart4_ext_100_101_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
+               },
+       },
+};
+
+static struct spear_pingroup uart4_pingroup[] = {
+       {
+               .name = "uart4_6_7_grp",
+               .pins = uart4_pins[0],
+               .npins = ARRAY_SIZE(uart4_pins[0]),
+               .modemuxs = uart4_modemux[0],
+               .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
+       }, {
+               .name = "uart4_13_14_grp",
+               .pins = uart4_pins[1],
+               .npins = ARRAY_SIZE(uart4_pins[1]),
+               .modemuxs = uart4_modemux[1],
+               .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
+       }, {
+               .name = "uart4_39_40_grp",
+               .pins = uart4_pins[2],
+               .npins = ARRAY_SIZE(uart4_pins[2]),
+               .modemuxs = uart4_modemux[2],
+               .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
+       }, {
+               .name = "uart4_71_72_grp",
+               .pins = uart4_pins[3],
+               .npins = ARRAY_SIZE(uart4_pins[3]),
+               .modemuxs = uart4_modemux[3],
+               .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
+       }, {
+               .name = "uart4_92_93_grp",
+               .pins = uart4_pins[4],
+               .npins = ARRAY_SIZE(uart4_pins[4]),
+               .modemuxs = uart4_modemux[4],
+               .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
+       }, {
+               .name = "uart4_100_101_grp",
+               .pins = uart4_pins[5],
+               .npins = ARRAY_SIZE(uart4_pins[5]),
+               .modemuxs = uart4_modemux[5],
+               .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
+       },
+};
+
+static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
+       "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
+       "uart4_100_101_grp" };
+
+static struct spear_function uart4_function = {
+       .name = "uart4",
+       .groups = uart4_grps,
+       .ngroups = ARRAY_SIZE(uart4_grps),
+};
+
+/* Pad multiplexing for uart5 device */
+static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
+       { 90, 91 } };
+
+static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_I2C_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_4_5_MASK,
+               .val = PMX_UART5_PL_4_5_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART5_PORT_SEL_MASK,
+               .val = PMX_UART5_PORT_4_VAL,
+       },
+};
+
+static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_37_38_MASK,
+               .val = PMX_UART5_PL_37_38_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART5_PORT_SEL_MASK,
+               .val = PMX_UART5_PORT_37_VAL,
+       },
+};
+
+static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_60_69_REG,
+               .mask = PMX_PL_69_MASK,
+               .val = PMX_UART5_PL_69_VAL,
+       }, {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_70_MASK,
+               .val = PMX_UART5_PL_70_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART5_PORT_SEL_MASK,
+               .val = PMX_UART5_PORT_69_VAL,
+       },
+};
+
+static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_90_91_MASK,
+               .val = PMX_UART5_PL_90_91_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART5_PORT_SEL_MASK,
+               .val = PMX_UART5_PORT_90_VAL,
+       },
+};
+
+static struct spear_modemux uart5_modemux[][1] = {
+       {
+               /* Select signals on pins 4_5 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart5_ext_4_5_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
+               },
+       }, {
+               /* Select signals on pins 37_38 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart5_ext_37_38_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
+               },
+       }, {
+               /* Select signals on pins 69_70 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart5_ext_69_70_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
+               },
+       }, {
+               /* Select signals on pins 90_91 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart5_ext_90_91_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
+               },
+       },
+};
+
+static struct spear_pingroup uart5_pingroup[] = {
+       {
+               .name = "uart5_4_5_grp",
+               .pins = uart5_pins[0],
+               .npins = ARRAY_SIZE(uart5_pins[0]),
+               .modemuxs = uart5_modemux[0],
+               .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
+       }, {
+               .name = "uart5_37_38_grp",
+               .pins = uart5_pins[1],
+               .npins = ARRAY_SIZE(uart5_pins[1]),
+               .modemuxs = uart5_modemux[1],
+               .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
+       }, {
+               .name = "uart5_69_70_grp",
+               .pins = uart5_pins[2],
+               .npins = ARRAY_SIZE(uart5_pins[2]),
+               .modemuxs = uart5_modemux[2],
+               .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
+       }, {
+               .name = "uart5_90_91_grp",
+               .pins = uart5_pins[3],
+               .npins = ARRAY_SIZE(uart5_pins[3]),
+               .modemuxs = uart5_modemux[3],
+               .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
+       },
+};
+
+static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
+       "uart5_69_70_grp", "uart5_90_91_grp" };
+static struct spear_function uart5_function = {
+       .name = "uart5",
+       .groups = uart5_grps,
+       .ngroups = ARRAY_SIZE(uart5_grps),
+};
+
+/* Pad multiplexing for uart6 device */
+static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
+static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_2_3_MASK,
+               .val = PMX_UART6_PL_2_3_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART6_PORT_SEL_MASK,
+               .val = PMX_UART6_PORT_2_VAL,
+       },
+};
+
+static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_88_89_MASK,
+               .val = PMX_UART6_PL_88_89_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_UART6_PORT_SEL_MASK,
+               .val = PMX_UART6_PORT_88_VAL,
+       },
+};
+
+static struct spear_modemux uart6_modemux[][1] = {
+       {
+               /* Select signals on pins 2_3 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart6_ext_2_3_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
+               },
+       }, {
+               /* Select signals on pins 88_89 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = uart6_ext_88_89_muxreg,
+                       .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
+               },
+       },
+};
+
+static struct spear_pingroup uart6_pingroup[] = {
+       {
+               .name = "uart6_2_3_grp",
+               .pins = uart6_pins[0],
+               .npins = ARRAY_SIZE(uart6_pins[0]),
+               .modemuxs = uart6_modemux[0],
+               .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
+       }, {
+               .name = "uart6_88_89_grp",
+               .pins = uart6_pins[1],
+               .npins = ARRAY_SIZE(uart6_pins[1]),
+               .modemuxs = uart6_modemux[1],
+               .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
+       },
+};
+
+static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
+static struct spear_function uart6_function = {
+       .name = "uart6",
+       .groups = uart6_grps,
+       .ngroups = ARRAY_SIZE(uart6_grps),
+};
+
+/* UART - RS485 pmx */
+static const unsigned rs485_pins[] = { 77, 78, 79 };
+static struct spear_muxreg rs485_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_77_78_79_MASK,
+               .val = PMX_RS485_PL_77_78_79_VAL,
+       },
+};
+
+static struct spear_modemux rs485_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = rs485_muxreg,
+               .nmuxregs = ARRAY_SIZE(rs485_muxreg),
+       },
+};
+
+static struct spear_pingroup rs485_pingroup = {
+       .name = "rs485_grp",
+       .pins = rs485_pins,
+       .npins = ARRAY_SIZE(rs485_pins),
+       .modemuxs = rs485_modemux,
+       .nmodemuxs = ARRAY_SIZE(rs485_modemux),
+};
+
+static const char *const rs485_grps[] = { "rs485_grp" };
+static struct spear_function rs485_function = {
+       .name = "rs485",
+       .groups = rs485_grps,
+       .ngroups = ARRAY_SIZE(rs485_grps),
+};
+
+/* Pad multiplexing for Touchscreen device */
+static const unsigned touchscreen_pins[] = { 5, 36 };
+static struct spear_muxreg touchscreen_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg touchscreen_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_5_MASK,
+               .val = PMX_TOUCH_Y_PL_5_VAL,
+       }, {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_36_MASK,
+               .val = PMX_TOUCH_X_PL_36_VAL,
+       },
+};
+
+static struct spear_modemux touchscreen_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
+               .muxregs = touchscreen_muxreg,
+               .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = touchscreen_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
+       },
+};
+
+static struct spear_pingroup touchscreen_pingroup = {
+       .name = "touchscreen_grp",
+       .pins = touchscreen_pins,
+       .npins = ARRAY_SIZE(touchscreen_pins),
+       .modemuxs = touchscreen_modemux,
+       .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
+};
+
+static const char *const touchscreen_grps[] = { "touchscreen_grp" };
+static struct spear_function touchscreen_function = {
+       .name = "touchscreen",
+       .groups = touchscreen_grps,
+       .ngroups = ARRAY_SIZE(touchscreen_grps),
+};
+
+/* Pad multiplexing for CAN device */
+static const unsigned can0_pins[] = { 32, 33 };
+static struct spear_muxreg can0_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg can0_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_32_33_MASK,
+               .val = PMX_CAN0_PL_32_33_VAL,
+       },
+};
+
+static struct spear_modemux can0_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                       | EXTENDED_MODE,
+               .muxregs = can0_muxreg,
+               .nmuxregs = ARRAY_SIZE(can0_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = can0_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
+       },
+};
+
+static struct spear_pingroup can0_pingroup = {
+       .name = "can0_grp",
+       .pins = can0_pins,
+       .npins = ARRAY_SIZE(can0_pins),
+       .modemuxs = can0_modemux,
+       .nmodemuxs = ARRAY_SIZE(can0_modemux),
+};
+
+static const char *const can0_grps[] = { "can0_grp" };
+static struct spear_function can0_function = {
+       .name = "can0",
+       .groups = can0_grps,
+       .ngroups = ARRAY_SIZE(can0_grps),
+};
+
+static const unsigned can1_pins[] = { 30, 31 };
+static struct spear_muxreg can1_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg can1_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_30_31_MASK,
+               .val = PMX_CAN1_PL_30_31_VAL,
+       },
+};
+
+static struct spear_modemux can1_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
+                       | EXTENDED_MODE,
+               .muxregs = can1_muxreg,
+               .nmuxregs = ARRAY_SIZE(can1_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = can1_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
+       },
+};
+
+static struct spear_pingroup can1_pingroup = {
+       .name = "can1_grp",
+       .pins = can1_pins,
+       .npins = ARRAY_SIZE(can1_pins),
+       .modemuxs = can1_modemux,
+       .nmodemuxs = ARRAY_SIZE(can1_modemux),
+};
+
+static const char *const can1_grps[] = { "can1_grp" };
+static struct spear_function can1_function = {
+       .name = "can1",
+       .groups = can1_grps,
+       .ngroups = ARRAY_SIZE(can1_grps),
+};
+
+/* Pad multiplexing for PWM0_1 device */
+static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
+       { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
+
+static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_8_9_MASK,
+               .val = PMX_PWM_0_1_PL_8_9_VAL,
+       },
+};
+
+static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
+               .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
+       },
+};
+
+static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
+               .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
+       },
+};
+
+static struct spear_muxreg pwm0_1_net_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_37_38_MASK,
+               .val = PMX_PWM0_1_PL_37_38_VAL,
+       },
+};
+
+static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
+               .val = PMX_PWM1_PL_42_VAL |
+                       PMX_PWM0_PL_43_VAL,
+       },
+};
+
+static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_59_MASK,
+               .val = PMX_PWM1_PL_59_VAL,
+       }, {
+               .reg = IP_SEL_PAD_60_69_REG,
+               .mask = PMX_PL_60_MASK,
+               .val = PMX_PWM0_PL_60_VAL,
+       },
+};
+
+static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_88_89_MASK,
+               .val = PMX_PWM0_1_PL_88_89_VAL,
+       },
+};
+
+static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm0_1_pin_8_9_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
+       },
+};
+
+static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
+       {
+               .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+               .muxregs = pwm0_1_autoexpsmallpri_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm0_1_pin_14_15_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
+       },
+};
+
+static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm0_1_pin_30_31_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
+       },
+};
+
+static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+               .muxregs = pwm0_1_net_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm0_1_pin_37_38_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
+       },
+};
+
+static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm0_1_pin_42_43_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
+       },
+};
+
+static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm0_1_pin_59_60_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
+       },
+};
+
+static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm0_1_pin_88_89_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
+       },
+};
+
+static struct spear_pingroup pwm0_1_pingroup[] = {
+       {
+               .name = "pwm0_1_pin_8_9_grp",
+               .pins = pwm0_1_pins[0],
+               .npins = ARRAY_SIZE(pwm0_1_pins[0]),
+               .modemuxs = pwm0_1_pin_8_9_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
+       }, {
+               .name = "pwm0_1_pin_14_15_grp",
+               .pins = pwm0_1_pins[1],
+               .npins = ARRAY_SIZE(pwm0_1_pins[1]),
+               .modemuxs = pwm0_1_pin_14_15_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
+       }, {
+               .name = "pwm0_1_pin_30_31_grp",
+               .pins = pwm0_1_pins[2],
+               .npins = ARRAY_SIZE(pwm0_1_pins[2]),
+               .modemuxs = pwm0_1_pin_30_31_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
+       }, {
+               .name = "pwm0_1_pin_37_38_grp",
+               .pins = pwm0_1_pins[3],
+               .npins = ARRAY_SIZE(pwm0_1_pins[3]),
+               .modemuxs = pwm0_1_pin_37_38_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
+       }, {
+               .name = "pwm0_1_pin_42_43_grp",
+               .pins = pwm0_1_pins[4],
+               .npins = ARRAY_SIZE(pwm0_1_pins[4]),
+               .modemuxs = pwm0_1_pin_42_43_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
+       }, {
+               .name = "pwm0_1_pin_59_60_grp",
+               .pins = pwm0_1_pins[5],
+               .npins = ARRAY_SIZE(pwm0_1_pins[5]),
+               .modemuxs = pwm0_1_pin_59_60_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
+       }, {
+               .name = "pwm0_1_pin_88_89_grp",
+               .pins = pwm0_1_pins[6],
+               .npins = ARRAY_SIZE(pwm0_1_pins[6]),
+               .modemuxs = pwm0_1_pin_88_89_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
+       },
+};
+
+static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
+       "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
+       "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
+};
+
+static struct spear_function pwm0_1_function = {
+       .name = "pwm0_1",
+       .groups = pwm0_1_grps,
+       .ngroups = ARRAY_SIZE(pwm0_1_grps),
+};
+
+/* Pad multiplexing for PWM2 device */
+static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
+       { 58 }, { 87 } };
+static struct spear_muxreg pwm2_net_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_CS_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg pwm2_pin_7_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_7_MASK,
+               .val = PMX_PWM_2_PL_7_VAL,
+       },
+};
+
+static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg pwm2_pin_13_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_13_MASK,
+               .val = PMX_PWM2_PL_13_VAL,
+       },
+};
+
+static struct spear_muxreg pwm2_pin_29_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN1_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_20_29_REG,
+               .mask = PMX_PL_29_MASK,
+               .val = PMX_PWM_2_PL_29_VAL,
+       },
+};
+
+static struct spear_muxreg pwm2_pin_34_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_CS_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_34_MASK,
+               .val = PMX_PWM2_PL_34_VAL,
+       },
+};
+
+static struct spear_muxreg pwm2_pin_41_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_41_MASK,
+               .val = PMX_PWM2_PL_41_VAL,
+       },
+};
+
+static struct spear_muxreg pwm2_pin_58_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_58_MASK,
+               .val = PMX_PWM2_PL_58_VAL,
+       },
+};
+
+static struct spear_muxreg pwm2_pin_87_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_87_MASK,
+               .val = PMX_PWM2_PL_87_VAL,
+       },
+};
+
+static struct spear_modemux pwm2_pin_7_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
+               .muxregs = pwm2_net_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm2_pin_7_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
+       },
+};
+static struct spear_modemux pwm2_pin_13_modemux[] = {
+       {
+               .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
+               .muxregs = pwm2_autoexpsmallpri_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm2_pin_13_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
+       },
+};
+static struct spear_modemux pwm2_pin_29_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm2_pin_29_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
+       },
+};
+static struct spear_modemux pwm2_pin_34_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm2_pin_34_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
+       },
+};
+
+static struct spear_modemux pwm2_pin_41_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm2_pin_41_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
+       },
+};
+
+static struct spear_modemux pwm2_pin_58_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm2_pin_58_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
+       },
+};
+
+static struct spear_modemux pwm2_pin_87_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm2_pin_87_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
+       },
+};
+
+static struct spear_pingroup pwm2_pingroup[] = {
+       {
+               .name = "pwm2_pin_7_grp",
+               .pins = pwm2_pins[0],
+               .npins = ARRAY_SIZE(pwm2_pins[0]),
+               .modemuxs = pwm2_pin_7_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
+       }, {
+               .name = "pwm2_pin_13_grp",
+               .pins = pwm2_pins[1],
+               .npins = ARRAY_SIZE(pwm2_pins[1]),
+               .modemuxs = pwm2_pin_13_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
+       }, {
+               .name = "pwm2_pin_29_grp",
+               .pins = pwm2_pins[2],
+               .npins = ARRAY_SIZE(pwm2_pins[2]),
+               .modemuxs = pwm2_pin_29_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
+       }, {
+               .name = "pwm2_pin_34_grp",
+               .pins = pwm2_pins[3],
+               .npins = ARRAY_SIZE(pwm2_pins[3]),
+               .modemuxs = pwm2_pin_34_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
+       }, {
+               .name = "pwm2_pin_41_grp",
+               .pins = pwm2_pins[4],
+               .npins = ARRAY_SIZE(pwm2_pins[4]),
+               .modemuxs = pwm2_pin_41_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
+       }, {
+               .name = "pwm2_pin_58_grp",
+               .pins = pwm2_pins[5],
+               .npins = ARRAY_SIZE(pwm2_pins[5]),
+               .modemuxs = pwm2_pin_58_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
+       }, {
+               .name = "pwm2_pin_87_grp",
+               .pins = pwm2_pins[6],
+               .npins = ARRAY_SIZE(pwm2_pins[6]),
+               .modemuxs = pwm2_pin_87_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
+       },
+};
+
+static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
+       "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
+       "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
+static struct spear_function pwm2_function = {
+       .name = "pwm2",
+       .groups = pwm2_grps,
+       .ngroups = ARRAY_SIZE(pwm2_grps),
+};
+
+/* Pad multiplexing for PWM3 device */
+static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
+       { 86 } };
+static struct spear_muxreg pwm3_pin_6_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_6_MASK,
+               .val = PMX_PWM_3_PL_6_VAL,
+       },
+};
+
+static struct spear_muxreg pwm3_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg pwm3_pin_12_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_12_MASK,
+               .val = PMX_PWM3_PL_12_VAL,
+       },
+};
+
+static struct spear_muxreg pwm3_pin_28_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_GPIO_PIN0_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_20_29_REG,
+               .mask = PMX_PL_28_MASK,
+               .val = PMX_PWM_3_PL_28_VAL,
+       },
+};
+
+static struct spear_muxreg pwm3_pin_40_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_40_MASK,
+               .val = PMX_PWM3_PL_40_VAL,
+       },
+};
+
+static struct spear_muxreg pwm3_pin_57_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_57_MASK,
+               .val = PMX_PWM3_PL_57_VAL,
+       },
+};
+
+static struct spear_muxreg pwm3_pin_86_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_86_MASK,
+               .val = PMX_PWM3_PL_86_VAL,
+       },
+};
+
+static struct spear_modemux pwm3_pin_6_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm3_pin_6_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
+       },
+};
+
+static struct spear_modemux pwm3_pin_12_modemux[] = {
+       {
+               .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
+                       AUTO_NET_SMII_MODE | EXTENDED_MODE,
+               .muxregs = pwm3_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm3_pin_12_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
+       },
+};
+
+static struct spear_modemux pwm3_pin_28_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm3_pin_28_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
+       },
+};
+
+static struct spear_modemux pwm3_pin_40_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm3_pin_40_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
+       },
+};
+
+static struct spear_modemux pwm3_pin_57_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm3_pin_57_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
+       },
+};
+
+static struct spear_modemux pwm3_pin_86_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = pwm3_pin_86_muxreg,
+               .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
+       },
+};
+
+static struct spear_pingroup pwm3_pingroup[] = {
+       {
+               .name = "pwm3_pin_6_grp",
+               .pins = pwm3_pins[0],
+               .npins = ARRAY_SIZE(pwm3_pins[0]),
+               .modemuxs = pwm3_pin_6_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
+       }, {
+               .name = "pwm3_pin_12_grp",
+               .pins = pwm3_pins[1],
+               .npins = ARRAY_SIZE(pwm3_pins[1]),
+               .modemuxs = pwm3_pin_12_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
+       }, {
+               .name = "pwm3_pin_28_grp",
+               .pins = pwm3_pins[2],
+               .npins = ARRAY_SIZE(pwm3_pins[2]),
+               .modemuxs = pwm3_pin_28_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
+       }, {
+               .name = "pwm3_pin_40_grp",
+               .pins = pwm3_pins[3],
+               .npins = ARRAY_SIZE(pwm3_pins[3]),
+               .modemuxs = pwm3_pin_40_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
+       }, {
+               .name = "pwm3_pin_57_grp",
+               .pins = pwm3_pins[4],
+               .npins = ARRAY_SIZE(pwm3_pins[4]),
+               .modemuxs = pwm3_pin_57_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
+       }, {
+               .name = "pwm3_pin_86_grp",
+               .pins = pwm3_pins[5],
+               .npins = ARRAY_SIZE(pwm3_pins[5]),
+               .modemuxs = pwm3_pin_86_modemux,
+               .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
+       },
+};
+
+static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
+       "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
+       "pwm3_pin_86_grp" };
+static struct spear_function pwm3_function = {
+       .name = "pwm3",
+       .groups = pwm3_grps,
+       .ngroups = ARRAY_SIZE(pwm3_grps),
+};
+
+/* Pad multiplexing for SSP1 device */
+static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
+       { 65, 68 }, { 94, 97 } };
+static struct spear_muxreg ssp1_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+               .val = PMX_SSP1_PL_17_18_19_20_VAL,
+       }, {
+               .reg = IP_SEL_PAD_20_29_REG,
+               .mask = PMX_PL_20_MASK,
+               .val = PMX_SSP1_PL_17_18_19_20_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP1_PORT_SEL_MASK,
+               .val = PMX_SSP1_PORT_17_TO_20_VAL,
+       },
+};
+
+static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
+               .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
+                       PMX_SSP1_PL_39_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP1_PORT_SEL_MASK,
+               .val = PMX_SSP1_PORT_36_TO_39_VAL,
+       },
+};
+
+static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_48_49_MASK,
+               .val = PMX_SSP1_PL_48_49_VAL,
+       }, {
+               .reg = IP_SEL_PAD_50_59_REG,
+               .mask = PMX_PL_50_51_MASK,
+               .val = PMX_SSP1_PL_50_51_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP1_PORT_SEL_MASK,
+               .val = PMX_SSP1_PORT_48_TO_51_VAL,
+       },
+};
+
+static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_60_69_REG,
+               .mask = PMX_PL_65_TO_68_MASK,
+               .val = PMX_SSP1_PL_65_TO_68_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP1_PORT_SEL_MASK,
+               .val = PMX_SSP1_PORT_65_TO_68_VAL,
+       },
+};
+
+static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+               .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP1_PORT_SEL_MASK,
+               .val = PMX_SSP1_PORT_94_TO_97_VAL,
+       },
+};
+
+static struct spear_modemux ssp1_17_20_modemux[] = {
+       {
+               .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
+                       EXTENDED_MODE,
+               .muxregs = ssp1_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp1_ext_17_20_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
+       },
+};
+
+static struct spear_modemux ssp1_36_39_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp1_ext_36_39_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
+       },
+};
+
+static struct spear_modemux ssp1_48_51_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp1_ext_48_51_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
+       },
+};
+static struct spear_modemux ssp1_65_68_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp1_ext_65_68_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
+       },
+};
+
+static struct spear_modemux ssp1_94_97_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp1_ext_94_97_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
+       },
+};
+
+static struct spear_pingroup ssp1_pingroup[] = {
+       {
+               .name = "ssp1_17_20_grp",
+               .pins = ssp1_pins[0],
+               .npins = ARRAY_SIZE(ssp1_pins[0]),
+               .modemuxs = ssp1_17_20_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
+       }, {
+               .name = "ssp1_36_39_grp",
+               .pins = ssp1_pins[1],
+               .npins = ARRAY_SIZE(ssp1_pins[1]),
+               .modemuxs = ssp1_36_39_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
+       }, {
+               .name = "ssp1_48_51_grp",
+               .pins = ssp1_pins[2],
+               .npins = ARRAY_SIZE(ssp1_pins[2]),
+               .modemuxs = ssp1_48_51_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
+       }, {
+               .name = "ssp1_65_68_grp",
+               .pins = ssp1_pins[3],
+               .npins = ARRAY_SIZE(ssp1_pins[3]),
+               .modemuxs = ssp1_65_68_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
+       }, {
+               .name = "ssp1_94_97_grp",
+               .pins = ssp1_pins[4],
+               .npins = ARRAY_SIZE(ssp1_pins[4]),
+               .modemuxs = ssp1_94_97_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
+       },
+};
+
+static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
+       "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
+};
+static struct spear_function ssp1_function = {
+       .name = "ssp1",
+       .groups = ssp1_grps,
+       .ngroups = ARRAY_SIZE(ssp1_grps),
+};
+
+/* Pad multiplexing for SSP2 device */
+static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
+       { 61, 64 }, { 90, 93 } };
+static struct spear_muxreg ssp2_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
+               .val = PMX_SSP2_PL_13_14_15_16_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP2_PORT_SEL_MASK,
+               .val = PMX_SSP2_PORT_13_TO_16_VAL,
+       },
+};
+
+static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
+                       PMX_GPIO_PIN5_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_30_39_REG,
+               .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
+               .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
+                       PMX_SSP2_PL_35_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP2_PORT_SEL_MASK,
+               .val = PMX_SSP2_PORT_32_TO_35_VAL,
+       },
+};
+
+static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_40_49_REG,
+               .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
+               .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP2_PORT_SEL_MASK,
+               .val = PMX_SSP2_PORT_44_TO_47_VAL,
+       },
+};
+
+static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_60_69_REG,
+               .mask = PMX_PL_61_TO_64_MASK,
+               .val = PMX_SSP2_PL_61_TO_64_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP2_PORT_SEL_MASK,
+               .val = PMX_SSP2_PORT_61_TO_64_VAL,
+       },
+};
+
+static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
+               .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_SSP2_PORT_SEL_MASK,
+               .val = PMX_SSP2_PORT_90_TO_93_VAL,
+       },
+};
+
+static struct spear_modemux ssp2_13_16_modemux[] = {
+       {
+               .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
+               .muxregs = ssp2_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
+       }, {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp2_ext_13_16_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
+       },
+};
+
+static struct spear_modemux ssp2_32_35_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp2_ext_32_35_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
+       },
+};
+
+static struct spear_modemux ssp2_44_47_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp2_ext_44_47_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
+       },
+};
+
+static struct spear_modemux ssp2_61_64_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp2_ext_61_64_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
+       },
+};
+
+static struct spear_modemux ssp2_90_93_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = ssp2_ext_90_93_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
+       },
+};
+
+static struct spear_pingroup ssp2_pingroup[] = {
+       {
+               .name = "ssp2_13_16_grp",
+               .pins = ssp2_pins[0],
+               .npins = ARRAY_SIZE(ssp2_pins[0]),
+               .modemuxs = ssp2_13_16_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
+       }, {
+               .name = "ssp2_32_35_grp",
+               .pins = ssp2_pins[1],
+               .npins = ARRAY_SIZE(ssp2_pins[1]),
+               .modemuxs = ssp2_32_35_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
+       }, {
+               .name = "ssp2_44_47_grp",
+               .pins = ssp2_pins[2],
+               .npins = ARRAY_SIZE(ssp2_pins[2]),
+               .modemuxs = ssp2_44_47_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
+       }, {
+               .name = "ssp2_61_64_grp",
+               .pins = ssp2_pins[3],
+               .npins = ARRAY_SIZE(ssp2_pins[3]),
+               .modemuxs = ssp2_61_64_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
+       }, {
+               .name = "ssp2_90_93_grp",
+               .pins = ssp2_pins[4],
+               .npins = ARRAY_SIZE(ssp2_pins[4]),
+               .modemuxs = ssp2_90_93_modemux,
+               .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
+       },
+};
+
+static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
+       "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
+static struct spear_function ssp2_function = {
+       .name = "ssp2",
+       .groups = ssp2_grps,
+       .ngroups = ARRAY_SIZE(ssp2_grps),
+};
+
+/* Pad multiplexing for cadence mii2 as mii device */
+static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
+       90, 91, 92, 93, 94, 95, 96, 97 };
+static struct spear_muxreg mii2_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_80_89_REG,
+               .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
+                       PMX_PL_88_89_MASK,
+               .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
+                       PMX_MII2_PL_88_89_VAL,
+       }, {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
+                       PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
+               .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
+                       PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
+       }, {
+               .reg = EXT_CTRL_REG,
+               .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                       (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                       MII_MDIO_MASK,
+               .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
+                       (MAC_MODE_MII << MAC1_MODE_SHIFT) |
+                       MII_MDIO_81_VAL,
+       },
+};
+
+static struct spear_modemux mii2_modemux[] = {
+       {
+               .modes = EXTENDED_MODE,
+               .muxregs = mii2_muxreg,
+               .nmuxregs = ARRAY_SIZE(mii2_muxreg),
+       },
+};
+
+static struct spear_pingroup mii2_pingroup = {
+       .name = "mii2_grp",
+       .pins = mii2_pins,
+       .npins = ARRAY_SIZE(mii2_pins),
+       .modemuxs = mii2_modemux,
+       .nmodemuxs = ARRAY_SIZE(mii2_modemux),
+};
+
+static const char *const mii2_grps[] = { "mii2_grp" };
+static struct spear_function mii2_function = {
+       .name = "mii2",
+       .groups = mii2_grps,
+       .ngroups = ARRAY_SIZE(mii2_grps),
+};
+
+/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
+static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
+       21, 22, 23, 24, 25, 26, 27 };
+static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
+static struct spear_muxreg mii0_1_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       },
+};
+
+static struct spear_muxreg smii0_1_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_10_11_MASK,
+               .val = PMX_SMII_PL_10_11_VAL,
+       }, {
+               .reg = IP_SEL_PAD_20_29_REG,
+               .mask = PMX_PL_21_TO_27_MASK,
+               .val = PMX_SMII_PL_21_TO_27_VAL,
+       }, {
+               .reg = EXT_CTRL_REG,
+               .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                       (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                       MII_MDIO_MASK,
+               .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
+                       | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
+                       | MII_MDIO_10_11_VAL,
+       },
+};
+
+static struct spear_muxreg rmii0_1_ext_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
+                       PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
+               .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
+                       PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
+                       PMX_RMII_PL_19_VAL,
+       }, {
+               .reg = IP_SEL_PAD_20_29_REG,
+               .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
+               .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
+       }, {
+               .reg = EXT_CTRL_REG,
+               .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
+                       (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
+                       MII_MDIO_MASK,
+               .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
+                       | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
+                       | MII_MDIO_10_11_VAL,
+       },
+};
+
+static struct spear_modemux mii0_1_modemux[][2] = {
+       {
+               /* configure as smii */
+               {
+                       .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
+                               SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                       .muxregs = mii0_1_muxreg,
+                       .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
+               }, {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = smii0_1_ext_muxreg,
+                       .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
+               },
+       }, {
+               /* configure as rmii */
+               {
+                       .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
+                               SMALL_PRINTERS_MODE | EXTENDED_MODE,
+                       .muxregs = mii0_1_muxreg,
+                       .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
+               }, {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = rmii0_1_ext_muxreg,
+                       .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
+               },
+       },
+};
+
+static struct spear_pingroup mii0_1_pingroup[] = {
+       {
+               .name = "smii0_1_grp",
+               .pins = smii0_1_pins,
+               .npins = ARRAY_SIZE(smii0_1_pins),
+               .modemuxs = mii0_1_modemux[0],
+               .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
+       }, {
+               .name = "rmii0_1_grp",
+               .pins = rmii0_1_pins,
+               .npins = ARRAY_SIZE(rmii0_1_pins),
+               .modemuxs = mii0_1_modemux[1],
+               .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
+       },
+};
+
+static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
+static struct spear_function mii0_1_function = {
+       .name = "mii0_1",
+       .groups = mii0_1_grps,
+       .ngroups = ARRAY_SIZE(mii0_1_grps),
+};
+
+/* Pad multiplexing for i2c1 device */
+static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
+static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_SSP_CS_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_8_9_MASK,
+               .val = PMX_I2C1_PL_8_9_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_I2C1_PORT_SEL_MASK,
+               .val = PMX_I2C1_PORT_8_9_VAL,
+       },
+};
+
+static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
+               .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_I2C1_PORT_SEL_MASK,
+               .val = PMX_I2C1_PORT_98_99_VAL,
+       },
+};
+
+static struct spear_modemux i2c1_modemux[][1] = {
+       {
+               /* Select signals on pins 8-9 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = i2c1_ext_8_9_muxreg,
+                       .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
+               },
+       }, {
+               /* Select signals on pins 98-99 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = i2c1_ext_98_99_muxreg,
+                       .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
+               },
+       },
+};
+
+static struct spear_pingroup i2c1_pingroup[] = {
+       {
+               .name = "i2c1_8_9_grp",
+               .pins = i2c1_pins[0],
+               .npins = ARRAY_SIZE(i2c1_pins[0]),
+               .modemuxs = i2c1_modemux[0],
+               .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
+       }, {
+               .name = "i2c1_98_99_grp",
+               .pins = i2c1_pins[1],
+               .npins = ARRAY_SIZE(i2c1_pins[1]),
+               .modemuxs = i2c1_modemux[1],
+               .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
+       },
+};
+
+static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
+static struct spear_function i2c1_function = {
+       .name = "i2c1",
+       .groups = i2c1_grps,
+       .ngroups = ARRAY_SIZE(i2c1_grps),
+};
+
+/* Pad multiplexing for i2c2 device */
+static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
+       { 75, 76 }, { 96, 97 } };
+static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_FIRDA_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_0_1_MASK,
+               .val = PMX_I2C2_PL_0_1_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_I2C2_PORT_SEL_MASK,
+               .val = PMX_I2C2_PORT_0_1_VAL,
+       },
+};
+
+static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_UART0_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_0_9_REG,
+               .mask = PMX_PL_2_3_MASK,
+               .val = PMX_I2C2_PL_2_3_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_I2C2_PORT_SEL_MASK,
+               .val = PMX_I2C2_PORT_2_3_VAL,
+       },
+};
+
+static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
+       {
+               .reg = PMX_CONFIG_REG,
+               .mask = PMX_MII_MASK,
+               .val = 0,
+       }, {
+               .reg = IP_SEL_PAD_10_19_REG,
+               .mask = PMX_PL_19_MASK,
+               .val = PMX_I2C2_PL_19_VAL,
+       }, {
+               .reg = IP_SEL_PAD_20_29_REG,
+               .mask = PMX_PL_20_MASK,
+               .val = PMX_I2C2_PL_20_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_I2C2_PORT_SEL_MASK,
+               .val = PMX_I2C2_PORT_19_20_VAL,
+       },
+};
+
+static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_70_79_REG,
+               .mask = PMX_PL_75_76_MASK,
+               .val = PMX_I2C2_PL_75_76_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_I2C2_PORT_SEL_MASK,
+               .val = PMX_I2C2_PORT_75_76_VAL,
+       },
+};
+
+static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
+       {
+               .reg = IP_SEL_PAD_90_99_REG,
+               .mask = PMX_PL_96_97_MASK,
+               .val = PMX_I2C2_PL_96_97_VAL,
+       }, {
+               .reg = IP_SEL_MIX_PAD_REG,
+               .mask = PMX_I2C2_PORT_SEL_MASK,
+               .val = PMX_I2C2_PORT_96_97_VAL,
+       },
+};
+
+static struct spear_modemux i2c2_modemux[][1] = {
+       {
+               /* Select signals on pins 0_1 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = i2c2_ext_0_1_muxreg,
+                       .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
+               },
+       }, {
+               /* Select signals on pins 2_3 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = i2c2_ext_2_3_muxreg,
+                       .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
+               },
+       }, {
+               /* Select signals on pins 19_20 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = i2c2_ext_19_20_muxreg,
+                       .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
+               },
+       }, {
+               /* Select signals on pins 75_76 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = i2c2_ext_75_76_muxreg,
+                       .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
+               },
+       }, {
+               /* Select signals on pins 96_97 */
+               {
+                       .modes = EXTENDED_MODE,
+                       .muxregs = i2c2_ext_96_97_muxreg,
+                       .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
+               },
+       },
+};
+
+static struct spear_pingroup i2c2_pingroup[] = {
+       {
+               .name = "i2c2_0_1_grp",
+               .pins = i2c2_pins[0],
+               .npins = ARRAY_SIZE(i2c2_pins[0]),
+               .modemuxs = i2c2_modemux[0],
+               .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
+       }, {
+               .name = "i2c2_2_3_grp",
+               .pins = i2c2_pins[1],
+               .npins = ARRAY_SIZE(i2c2_pins[1]),
+               .modemuxs = i2c2_modemux[1],
+               .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
+       }, {
+               .name = "i2c2_19_20_grp",
+               .pins = i2c2_pins[2],
+               .npins = ARRAY_SIZE(i2c2_pins[2]),
+               .modemuxs = i2c2_modemux[2],
+               .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
+       }, {
+               .name = "i2c2_75_76_grp",
+               .pins = i2c2_pins[3],
+               .npins = ARRAY_SIZE(i2c2_pins[3]),
+               .modemuxs = i2c2_modemux[3],
+               .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
+       }, {
+               .name = "i2c2_96_97_grp",
+               .pins = i2c2_pins[4],
+               .npins = ARRAY_SIZE(i2c2_pins[4]),
+               .modemuxs = i2c2_modemux[4],
+               .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
+       },
+};
+
+static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
+       "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
+static struct spear_function i2c2_function = {
+       .name = "i2c2",
+       .groups = i2c2_grps,
+       .ngroups = ARRAY_SIZE(i2c2_grps),
+};
+
+/* pingroups */
+static struct spear_pingroup *spear320_pingroups[] = {
+       SPEAR3XX_COMMON_PINGROUPS,
+       &clcd_pingroup,
+       &emi_pingroup,
+       &fsmc_8bit_pingroup,
+       &fsmc_16bit_pingroup,
+       &spp_pingroup,
+       &sdhci_led_pingroup,
+       &sdhci_pingroup[0],
+       &sdhci_pingroup[1],
+       &i2s_pingroup,
+       &uart1_pingroup,
+       &uart1_modem_pingroup[0],
+       &uart1_modem_pingroup[1],
+       &uart1_modem_pingroup[2],
+       &uart1_modem_pingroup[3],
+       &uart2_pingroup,
+       &uart3_pingroup[0],
+       &uart3_pingroup[1],
+       &uart3_pingroup[2],
+       &uart3_pingroup[3],
+       &uart3_pingroup[4],
+       &uart3_pingroup[5],
+       &uart3_pingroup[6],
+       &uart4_pingroup[0],
+       &uart4_pingroup[1],
+       &uart4_pingroup[2],
+       &uart4_pingroup[3],
+       &uart4_pingroup[4],
+       &uart4_pingroup[5],
+       &uart5_pingroup[0],
+       &uart5_pingroup[1],
+       &uart5_pingroup[2],
+       &uart5_pingroup[3],
+       &uart6_pingroup[0],
+       &uart6_pingroup[1],
+       &rs485_pingroup,
+       &touchscreen_pingroup,
+       &can0_pingroup,
+       &can1_pingroup,
+       &pwm0_1_pingroup[0],
+       &pwm0_1_pingroup[1],
+       &pwm0_1_pingroup[2],
+       &pwm0_1_pingroup[3],
+       &pwm0_1_pingroup[4],
+       &pwm0_1_pingroup[5],
+       &pwm0_1_pingroup[6],
+       &pwm2_pingroup[0],
+       &pwm2_pingroup[1],
+       &pwm2_pingroup[2],
+       &pwm2_pingroup[3],
+       &pwm2_pingroup[4],
+       &pwm2_pingroup[5],
+       &pwm2_pingroup[6],
+       &pwm3_pingroup[0],
+       &pwm3_pingroup[1],
+       &pwm3_pingroup[2],
+       &pwm3_pingroup[3],
+       &pwm3_pingroup[4],
+       &pwm3_pingroup[5],
+       &ssp1_pingroup[0],
+       &ssp1_pingroup[1],
+       &ssp1_pingroup[2],
+       &ssp1_pingroup[3],
+       &ssp1_pingroup[4],
+       &ssp2_pingroup[0],
+       &ssp2_pingroup[1],
+       &ssp2_pingroup[2],
+       &ssp2_pingroup[3],
+       &ssp2_pingroup[4],
+       &mii2_pingroup,
+       &mii0_1_pingroup[0],
+       &mii0_1_pingroup[1],
+       &i2c1_pingroup[0],
+       &i2c1_pingroup[1],
+       &i2c2_pingroup[0],
+       &i2c2_pingroup[1],
+       &i2c2_pingroup[2],
+       &i2c2_pingroup[3],
+       &i2c2_pingroup[4],
+};
+
+/* functions */
+static struct spear_function *spear320_functions[] = {
+       SPEAR3XX_COMMON_FUNCTIONS,
+       &clcd_function,
+       &emi_function,
+       &fsmc_function,
+       &spp_function,
+       &sdhci_function,
+       &i2s_function,
+       &uart1_function,
+       &uart1_modem_function,
+       &uart2_function,
+       &uart3_function,
+       &uart4_function,
+       &uart5_function,
+       &uart6_function,
+       &rs485_function,
+       &touchscreen_function,
+       &can0_function,
+       &can1_function,
+       &pwm0_1_function,
+       &pwm2_function,
+       &pwm3_function,
+       &ssp1_function,
+       &ssp2_function,
+       &mii2_function,
+       &mii0_1_function,
+       &i2c1_function,
+       &i2c2_function,
+};
+
+static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
+       {
+               .compatible = "st,spear320-pinmux",
+       },
+       {},
+};
+
+static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
+{
+       int ret;
+
+       spear3xx_machdata.groups = spear320_pingroups;
+       spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
+       spear3xx_machdata.functions = spear320_functions;
+       spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
+
+       spear3xx_machdata.modes_supported = true;
+       spear3xx_machdata.pmx_modes = spear320_pmx_modes;
+       spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
+
+       pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+
+       ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
+static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
+{
+       return spear_pinctrl_remove(pdev);
+}
+
+static struct platform_driver spear320_pinctrl_driver = {
+       .driver = {
+               .name = DRIVER_NAME,
+               .owner = THIS_MODULE,
+               .of_match_table = spear320_pinctrl_of_match,
+       },
+       .probe = spear320_pinctrl_probe,
+       .remove = __devexit_p(spear320_pinctrl_remove),
+};
+
+static int __init spear320_pinctrl_init(void)
+{
+       return platform_driver_register(&spear320_pinctrl_driver);
+}
+arch_initcall(spear320_pinctrl_init);
+
+static void __exit spear320_pinctrl_exit(void)
+{
+       platform_driver_unregister(&spear320_pinctrl_driver);
+}
+module_exit(spear320_pinctrl_exit);
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);

diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
new file mode 100644 (file)
index 0000000..832049a
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -0,0 +1,588 @@
+/*
+ * Driver for the ST Microelectronics SPEAr3xx pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-spear3xx.h"
+
+/* pins */
+static const struct pinctrl_pin_desc spear3xx_pins[] = {
+       PINCTRL_PIN(0, "PLGPIO0"),
+       PINCTRL_PIN(1, "PLGPIO1"),
+       PINCTRL_PIN(2, "PLGPIO2"),
+       PINCTRL_PIN(3, "PLGPIO3"),
+       PINCTRL_PIN(4, "PLGPIO4"),
+       PINCTRL_PIN(5, "PLGPIO5"),
+       PINCTRL_PIN(6, "PLGPIO6"),
+       PINCTRL_PIN(7, "PLGPIO7"),
+       PINCTRL_PIN(8, "PLGPIO8"),
+       PINCTRL_PIN(9, "PLGPIO9"),
+       PINCTRL_PIN(10, "PLGPIO10"),
+       PINCTRL_PIN(11, "PLGPIO11"),
+       PINCTRL_PIN(12, "PLGPIO12"),
+       PINCTRL_PIN(13, "PLGPIO13"),
+       PINCTRL_PIN(14, "PLGPIO14"),
+       PINCTRL_PIN(15, "PLGPIO15"),
+       PINCTRL_PIN(16, "PLGPIO16"),
+       PINCTRL_PIN(17, "PLGPIO17"),
+       PINCTRL_PIN(18, "PLGPIO18"),
+       PINCTRL_PIN(19, "PLGPIO19"),
+       PINCTRL_PIN(20, "PLGPIO20"),
+       PINCTRL_PIN(21, "PLGPIO21"),
+       PINCTRL_PIN(22, "PLGPIO22"),
+       PINCTRL_PIN(23, "PLGPIO23"),
+       PINCTRL_PIN(24, "PLGPIO24"),
+       PINCTRL_PIN(25, "PLGPIO25"),
+       PINCTRL_PIN(26, "PLGPIO26"),
+       PINCTRL_PIN(27, "PLGPIO27"),
+       PINCTRL_PIN(28, "PLGPIO28"),
+       PINCTRL_PIN(29, "PLGPIO29"),
+       PINCTRL_PIN(30, "PLGPIO30"),
+       PINCTRL_PIN(31, "PLGPIO31"),
+       PINCTRL_PIN(32, "PLGPIO32"),
+       PINCTRL_PIN(33, "PLGPIO33"),
+       PINCTRL_PIN(34, "PLGPIO34"),
+       PINCTRL_PIN(35, "PLGPIO35"),
+       PINCTRL_PIN(36, "PLGPIO36"),
+       PINCTRL_PIN(37, "PLGPIO37"),
+       PINCTRL_PIN(38, "PLGPIO38"),
+       PINCTRL_PIN(39, "PLGPIO39"),
+       PINCTRL_PIN(40, "PLGPIO40"),
+       PINCTRL_PIN(41, "PLGPIO41"),
+       PINCTRL_PIN(42, "PLGPIO42"),
+       PINCTRL_PIN(43, "PLGPIO43"),
+       PINCTRL_PIN(44, "PLGPIO44"),
+       PINCTRL_PIN(45, "PLGPIO45"),
+       PINCTRL_PIN(46, "PLGPIO46"),
+       PINCTRL_PIN(47, "PLGPIO47"),
+       PINCTRL_PIN(48, "PLGPIO48"),
+       PINCTRL_PIN(49, "PLGPIO49"),
+       PINCTRL_PIN(50, "PLGPIO50"),
+       PINCTRL_PIN(51, "PLGPIO51"),
+       PINCTRL_PIN(52, "PLGPIO52"),
+       PINCTRL_PIN(53, "PLGPIO53"),
+       PINCTRL_PIN(54, "PLGPIO54"),
+       PINCTRL_PIN(55, "PLGPIO55"),
+       PINCTRL_PIN(56, "PLGPIO56"),
+       PINCTRL_PIN(57, "PLGPIO57"),
+       PINCTRL_PIN(58, "PLGPIO58"),
+       PINCTRL_PIN(59, "PLGPIO59"),
+       PINCTRL_PIN(60, "PLGPIO60"),
+       PINCTRL_PIN(61, "PLGPIO61"),
+       PINCTRL_PIN(62, "PLGPIO62"),
+       PINCTRL_PIN(63, "PLGPIO63"),
+       PINCTRL_PIN(64, "PLGPIO64"),
+       PINCTRL_PIN(65, "PLGPIO65"),
+       PINCTRL_PIN(66, "PLGPIO66"),
+       PINCTRL_PIN(67, "PLGPIO67"),
+       PINCTRL_PIN(68, "PLGPIO68"),
+       PINCTRL_PIN(69, "PLGPIO69"),
+       PINCTRL_PIN(70, "PLGPIO70"),
+       PINCTRL_PIN(71, "PLGPIO71"),
+       PINCTRL_PIN(72, "PLGPIO72"),
+       PINCTRL_PIN(73, "PLGPIO73"),
+       PINCTRL_PIN(74, "PLGPIO74"),
+       PINCTRL_PIN(75, "PLGPIO75"),
+       PINCTRL_PIN(76, "PLGPIO76"),
+       PINCTRL_PIN(77, "PLGPIO77"),
+       PINCTRL_PIN(78, "PLGPIO78"),
+       PINCTRL_PIN(79, "PLGPIO79"),
+       PINCTRL_PIN(80, "PLGPIO80"),
+       PINCTRL_PIN(81, "PLGPIO81"),
+       PINCTRL_PIN(82, "PLGPIO82"),
+       PINCTRL_PIN(83, "PLGPIO83"),
+       PINCTRL_PIN(84, "PLGPIO84"),
+       PINCTRL_PIN(85, "PLGPIO85"),
+       PINCTRL_PIN(86, "PLGPIO86"),
+       PINCTRL_PIN(87, "PLGPIO87"),
+       PINCTRL_PIN(88, "PLGPIO88"),
+       PINCTRL_PIN(89, "PLGPIO89"),
+       PINCTRL_PIN(90, "PLGPIO90"),
+       PINCTRL_PIN(91, "PLGPIO91"),
+       PINCTRL_PIN(92, "PLGPIO92"),
+       PINCTRL_PIN(93, "PLGPIO93"),
+       PINCTRL_PIN(94, "PLGPIO94"),
+       PINCTRL_PIN(95, "PLGPIO95"),
+       PINCTRL_PIN(96, "PLGPIO96"),
+       PINCTRL_PIN(97, "PLGPIO97"),
+       PINCTRL_PIN(98, "PLGPIO98"),
+       PINCTRL_PIN(99, "PLGPIO99"),
+       PINCTRL_PIN(100, "PLGPIO100"),
+       PINCTRL_PIN(101, "PLGPIO101"),
+};
+
+/* firda_pins */
+static const unsigned firda_pins[] = { 0, 1 };
+static struct spear_muxreg firda_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_FIRDA_MASK,
+               .val = PMX_FIRDA_MASK,
+       },
+};
+
+static struct spear_modemux firda_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = firda_muxreg,
+               .nmuxregs = ARRAY_SIZE(firda_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_firda_pingroup = {
+       .name = "firda_grp",
+       .pins = firda_pins,
+       .npins = ARRAY_SIZE(firda_pins),
+       .modemuxs = firda_modemux,
+       .nmodemuxs = ARRAY_SIZE(firda_modemux),
+};
+
+static const char *const firda_grps[] = { "firda_grp" };
+struct spear_function spear3xx_firda_function = {
+       .name = "firda",
+       .groups = firda_grps,
+       .ngroups = ARRAY_SIZE(firda_grps),
+};
+
+/* i2c_pins */
+static const unsigned i2c_pins[] = { 4, 5 };
+static struct spear_muxreg i2c_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_I2C_MASK,
+               .val = PMX_I2C_MASK,
+       },
+};
+
+static struct spear_modemux i2c_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = i2c_muxreg,
+               .nmuxregs = ARRAY_SIZE(i2c_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_i2c_pingroup = {
+       .name = "i2c0_grp",
+       .pins = i2c_pins,
+       .npins = ARRAY_SIZE(i2c_pins),
+       .modemuxs = i2c_modemux,
+       .nmodemuxs = ARRAY_SIZE(i2c_modemux),
+};
+
+static const char *const i2c_grps[] = { "i2c0_grp" };
+struct spear_function spear3xx_i2c_function = {
+       .name = "i2c0",
+       .groups = i2c_grps,
+       .ngroups = ARRAY_SIZE(i2c_grps),
+};
+
+/* ssp_cs_pins */
+static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
+static struct spear_muxreg ssp_cs_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_SSP_CS_MASK,
+               .val = PMX_SSP_CS_MASK,
+       },
+};
+
+static struct spear_modemux ssp_cs_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = ssp_cs_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_ssp_cs_pingroup = {
+       .name = "ssp_cs_grp",
+       .pins = ssp_cs_pins,
+       .npins = ARRAY_SIZE(ssp_cs_pins),
+       .modemuxs = ssp_cs_modemux,
+       .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
+};
+
+static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
+struct spear_function spear3xx_ssp_cs_function = {
+       .name = "ssp_cs",
+       .groups = ssp_cs_grps,
+       .ngroups = ARRAY_SIZE(ssp_cs_grps),
+};
+
+/* ssp_pins */
+static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
+static struct spear_muxreg ssp_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_SSP_MASK,
+               .val = PMX_SSP_MASK,
+       },
+};
+
+static struct spear_modemux ssp_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = ssp_muxreg,
+               .nmuxregs = ARRAY_SIZE(ssp_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_ssp_pingroup = {
+       .name = "ssp0_grp",
+       .pins = ssp_pins,
+       .npins = ARRAY_SIZE(ssp_pins),
+       .modemuxs = ssp_modemux,
+       .nmodemuxs = ARRAY_SIZE(ssp_modemux),
+};
+
+static const char *const ssp_grps[] = { "ssp0_grp" };
+struct spear_function spear3xx_ssp_function = {
+       .name = "ssp0",
+       .groups = ssp_grps,
+       .ngroups = ARRAY_SIZE(ssp_grps),
+};
+
+/* mii_pins */
+static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+       21, 22, 23, 24, 25, 26, 27 };
+static struct spear_muxreg mii_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_MII_MASK,
+               .val = PMX_MII_MASK,
+       },
+};
+
+static struct spear_modemux mii_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = mii_muxreg,
+               .nmuxregs = ARRAY_SIZE(mii_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_mii_pingroup = {
+       .name = "mii0_grp",
+       .pins = mii_pins,
+       .npins = ARRAY_SIZE(mii_pins),
+       .modemuxs = mii_modemux,
+       .nmodemuxs = ARRAY_SIZE(mii_modemux),
+};
+
+static const char *const mii_grps[] = { "mii0_grp" };
+struct spear_function spear3xx_mii_function = {
+       .name = "mii0",
+       .groups = mii_grps,
+       .ngroups = ARRAY_SIZE(mii_grps),
+};
+
+/* gpio0_pin0_pins */
+static const unsigned gpio0_pin0_pins[] = { 28 };
+static struct spear_muxreg gpio0_pin0_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_GPIO_PIN0_MASK,
+               .val = PMX_GPIO_PIN0_MASK,
+       },
+};
+
+static struct spear_modemux gpio0_pin0_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = gpio0_pin0_muxreg,
+               .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
+       .name = "gpio0_pin0_grp",
+       .pins = gpio0_pin0_pins,
+       .npins = ARRAY_SIZE(gpio0_pin0_pins),
+       .modemuxs = gpio0_pin0_modemux,
+       .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
+};
+
+/* gpio0_pin1_pins */
+static const unsigned gpio0_pin1_pins[] = { 29 };
+static struct spear_muxreg gpio0_pin1_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_GPIO_PIN1_MASK,
+               .val = PMX_GPIO_PIN1_MASK,
+       },
+};
+
+static struct spear_modemux gpio0_pin1_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = gpio0_pin1_muxreg,
+               .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
+       .name = "gpio0_pin1_grp",
+       .pins = gpio0_pin1_pins,
+       .npins = ARRAY_SIZE(gpio0_pin1_pins),
+       .modemuxs = gpio0_pin1_modemux,
+       .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
+};
+
+/* gpio0_pin2_pins */
+static const unsigned gpio0_pin2_pins[] = { 30 };
+static struct spear_muxreg gpio0_pin2_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_GPIO_PIN2_MASK,
+               .val = PMX_GPIO_PIN2_MASK,
+       },
+};
+
+static struct spear_modemux gpio0_pin2_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = gpio0_pin2_muxreg,
+               .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
+       .name = "gpio0_pin2_grp",
+       .pins = gpio0_pin2_pins,
+       .npins = ARRAY_SIZE(gpio0_pin2_pins),
+       .modemuxs = gpio0_pin2_modemux,
+       .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
+};
+
+/* gpio0_pin3_pins */
+static const unsigned gpio0_pin3_pins[] = { 31 };
+static struct spear_muxreg gpio0_pin3_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_GPIO_PIN3_MASK,
+               .val = PMX_GPIO_PIN3_MASK,
+       },
+};
+
+static struct spear_modemux gpio0_pin3_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = gpio0_pin3_muxreg,
+               .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
+       .name = "gpio0_pin3_grp",
+       .pins = gpio0_pin3_pins,
+       .npins = ARRAY_SIZE(gpio0_pin3_pins),
+       .modemuxs = gpio0_pin3_modemux,
+       .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
+};
+
+/* gpio0_pin4_pins */
+static const unsigned gpio0_pin4_pins[] = { 32 };
+static struct spear_muxreg gpio0_pin4_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_GPIO_PIN4_MASK,
+               .val = PMX_GPIO_PIN4_MASK,
+       },
+};
+
+static struct spear_modemux gpio0_pin4_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = gpio0_pin4_muxreg,
+               .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
+       .name = "gpio0_pin4_grp",
+       .pins = gpio0_pin4_pins,
+       .npins = ARRAY_SIZE(gpio0_pin4_pins),
+       .modemuxs = gpio0_pin4_modemux,
+       .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
+};
+
+/* gpio0_pin5_pins */
+static const unsigned gpio0_pin5_pins[] = { 33 };
+static struct spear_muxreg gpio0_pin5_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_GPIO_PIN5_MASK,
+               .val = PMX_GPIO_PIN5_MASK,
+       },
+};
+
+static struct spear_modemux gpio0_pin5_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = gpio0_pin5_muxreg,
+               .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
+       .name = "gpio0_pin5_grp",
+       .pins = gpio0_pin5_pins,
+       .npins = ARRAY_SIZE(gpio0_pin5_pins),
+       .modemuxs = gpio0_pin5_modemux,
+       .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
+};
+
+static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
+       "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
+};
+struct spear_function spear3xx_gpio0_function = {
+       .name = "gpio0",
+       .groups = gpio0_grps,
+       .ngroups = ARRAY_SIZE(gpio0_grps),
+};
+
+/* uart0_ext_pins */
+static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
+static struct spear_muxreg uart0_ext_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_UART0_MODEM_MASK,
+               .val = PMX_UART0_MODEM_MASK,
+       },
+};
+
+static struct spear_modemux uart0_ext_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = uart0_ext_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_uart0_ext_pingroup = {
+       .name = "uart0_ext_grp",
+       .pins = uart0_ext_pins,
+       .npins = ARRAY_SIZE(uart0_ext_pins),
+       .modemuxs = uart0_ext_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
+};
+
+static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
+struct spear_function spear3xx_uart0_ext_function = {
+       .name = "uart0_ext",
+       .groups = uart0_ext_grps,
+       .ngroups = ARRAY_SIZE(uart0_ext_grps),
+};
+
+/* uart0_pins */
+static const unsigned uart0_pins[] = { 2, 3 };
+static struct spear_muxreg uart0_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_UART0_MASK,
+               .val = PMX_UART0_MASK,
+       },
+};
+
+static struct spear_modemux uart0_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = uart0_muxreg,
+               .nmuxregs = ARRAY_SIZE(uart0_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_uart0_pingroup = {
+       .name = "uart0_grp",
+       .pins = uart0_pins,
+       .npins = ARRAY_SIZE(uart0_pins),
+       .modemuxs = uart0_modemux,
+       .nmodemuxs = ARRAY_SIZE(uart0_modemux),
+};
+
+static const char *const uart0_grps[] = { "uart0_grp" };
+struct spear_function spear3xx_uart0_function = {
+       .name = "uart0",
+       .groups = uart0_grps,
+       .ngroups = ARRAY_SIZE(uart0_grps),
+};
+
+/* timer_0_1_pins */
+static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
+static struct spear_muxreg timer_0_1_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_TIMER_0_1_MASK,
+               .val = PMX_TIMER_0_1_MASK,
+       },
+};
+
+static struct spear_modemux timer_0_1_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = timer_0_1_muxreg,
+               .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_timer_0_1_pingroup = {
+       .name = "timer_0_1_grp",
+       .pins = timer_0_1_pins,
+       .npins = ARRAY_SIZE(timer_0_1_pins),
+       .modemuxs = timer_0_1_modemux,
+       .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
+};
+
+static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
+struct spear_function spear3xx_timer_0_1_function = {
+       .name = "timer_0_1",
+       .groups = timer_0_1_grps,
+       .ngroups = ARRAY_SIZE(timer_0_1_grps),
+};
+
+/* timer_2_3_pins */
+static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
+static struct spear_muxreg timer_2_3_muxreg[] = {
+       {
+               .reg = -1,
+               .mask = PMX_TIMER_2_3_MASK,
+               .val = PMX_TIMER_2_3_MASK,
+       },
+};
+
+static struct spear_modemux timer_2_3_modemux[] = {
+       {
+               .modes = ~0,
+               .muxregs = timer_2_3_muxreg,
+               .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
+       },
+};
+
+struct spear_pingroup spear3xx_timer_2_3_pingroup = {
+       .name = "timer_2_3_grp",
+       .pins = timer_2_3_pins,
+       .npins = ARRAY_SIZE(timer_2_3_pins),
+       .modemuxs = timer_2_3_modemux,
+       .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
+};
+
+static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
+struct spear_function spear3xx_timer_2_3_function = {
+       .name = "timer_2_3",
+       .groups = timer_2_3_grps,
+       .ngroups = ARRAY_SIZE(timer_2_3_grps),
+};
+
+struct spear_pinctrl_machdata spear3xx_machdata = {
+       .pins = spear3xx_pins,
+       .npins = ARRAY_SIZE(spear3xx_pins),
+};

diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
new file mode 100644 (file)
index 0000000..5d5fdd8
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -0,0 +1,92 @@
+/*
+ * Header file for the ST Microelectronics SPEAr3xx pinmux
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PINMUX_SPEAR3XX_H__
+#define __PINMUX_SPEAR3XX_H__
+
+#include "pinctrl-spear.h"
+
+/* pad mux declarations */
+#define PMX_FIRDA_MASK         (1 << 14)
+#define PMX_I2C_MASK           (1 << 13)
+#define PMX_SSP_CS_MASK                (1 << 12)
+#define PMX_SSP_MASK           (1 << 11)
+#define PMX_MII_MASK           (1 << 10)
+#define PMX_GPIO_PIN0_MASK     (1 << 9)
+#define PMX_GPIO_PIN1_MASK     (1 << 8)
+#define PMX_GPIO_PIN2_MASK     (1 << 7)
+#define PMX_GPIO_PIN3_MASK     (1 << 6)
+#define PMX_GPIO_PIN4_MASK     (1 << 5)
+#define PMX_GPIO_PIN5_MASK     (1 << 4)
+#define PMX_UART0_MODEM_MASK   (1 << 3)
+#define PMX_UART0_MASK         (1 << 2)
+#define PMX_TIMER_2_3_MASK     (1 << 1)
+#define PMX_TIMER_0_1_MASK     (1 << 0)
+
+extern struct spear_pingroup spear3xx_firda_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup;
+extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup;
+extern struct spear_pingroup spear3xx_i2c_pingroup;
+extern struct spear_pingroup spear3xx_mii_pingroup;
+extern struct spear_pingroup spear3xx_ssp_cs_pingroup;
+extern struct spear_pingroup spear3xx_ssp_pingroup;
+extern struct spear_pingroup spear3xx_timer_0_1_pingroup;
+extern struct spear_pingroup spear3xx_timer_2_3_pingroup;
+extern struct spear_pingroup spear3xx_uart0_ext_pingroup;
+extern struct spear_pingroup spear3xx_uart0_pingroup;
+
+#define SPEAR3XX_COMMON_PINGROUPS              \
+       &spear3xx_firda_pingroup,               \
+       &spear3xx_gpio0_pin0_pingroup,          \
+       &spear3xx_gpio0_pin1_pingroup,          \
+       &spear3xx_gpio0_pin2_pingroup,          \
+       &spear3xx_gpio0_pin3_pingroup,          \
+       &spear3xx_gpio0_pin4_pingroup,          \
+       &spear3xx_gpio0_pin5_pingroup,          \
+       &spear3xx_i2c_pingroup,                 \
+       &spear3xx_mii_pingroup,                 \
+       &spear3xx_ssp_cs_pingroup,              \
+       &spear3xx_ssp_pingroup,                 \
+       &spear3xx_timer_0_1_pingroup,           \
+       &spear3xx_timer_2_3_pingroup,           \
+       &spear3xx_uart0_ext_pingroup,           \
+       &spear3xx_uart0_pingroup
+
+extern struct spear_function spear3xx_firda_function;
+extern struct spear_function spear3xx_gpio0_function;
+extern struct spear_function spear3xx_i2c_function;
+extern struct spear_function spear3xx_mii_function;
+extern struct spear_function spear3xx_ssp_cs_function;
+extern struct spear_function spear3xx_ssp_function;
+extern struct spear_function spear3xx_timer_0_1_function;
+extern struct spear_function spear3xx_timer_2_3_function;
+extern struct spear_function spear3xx_uart0_ext_function;
+extern struct spear_function spear3xx_uart0_function;
+
+#define SPEAR3XX_COMMON_FUNCTIONS              \
+       &spear3xx_firda_function,               \
+       &spear3xx_gpio0_function,               \
+       &spear3xx_i2c_function,                 \
+       &spear3xx_mii_function,                 \
+       &spear3xx_ssp_cs_function,              \
+       &spear3xx_ssp_function,                 \
+       &spear3xx_timer_0_1_function,           \
+       &spear3xx_timer_2_3_function,           \
+       &spear3xx_uart0_ext_function,           \
+       &spear3xx_uart0_function
+
+extern struct spear_pinctrl_machdata spear3xx_machdata;
+
+#endif /* __PINMUX_SPEAR3XX_H__ */

diff --git a/drivers/platform/x86/acerhdf.c b/drivers/platform/x86/acerhdf.c
index bc8384c..639db4d 100644 (file)
--- a/drivers/platform/x86/acerhdf.c
+++ b/drivers/platform/x86/acerhdf.c
@@ -50,7 +50,7 @@
  */
 #undef START_IN_KERNEL_MODE
 
-#define DRV_VER "0.5.24"
+#define DRV_VER "0.5.26"
 
 /*
  * According to the Atom N270 datasheet,
@@ -83,8 +83,8 @@ static int kernelmode;
 #endif
 
 static unsigned int interval = 10;
-static unsigned int fanon = 63000;
-static unsigned int fanoff = 58000;
+static unsigned int fanon = 60000;
+static unsigned int fanoff = 53000;
 static unsigned int verbose;
 static unsigned int fanstate = ACERHDF_FAN_AUTO;
 static char force_bios[16];
@@ -150,6 +150,8 @@ static const struct bios_settings_t bios_tbl[] = {
        {"Acer", "AOA150", "v0.3308", 0x55, 0x58, {0x20, 0x00} },
        {"Acer", "AOA150", "v0.3309", 0x55, 0x58, {0x20, 0x00} },
        {"Acer", "AOA150", "v0.3310", 0x55, 0x58, {0x20, 0x00} },
+       /* LT1005u */
+       {"Acer", "LT-10Q", "v0.3310", 0x55, 0x58, {0x20, 0x00} },
        /* Acer 1410 */
        {"Acer", "Aspire 1410", "v0.3108", 0x55, 0x58, {0x9e, 0x00} },
        {"Acer", "Aspire 1410", "v0.3113", 0x55, 0x58, {0x9e, 0x00} },
@@ -161,6 +163,7 @@ static const struct bios_settings_t bios_tbl[] = {
        {"Acer", "Aspire 1410", "v1.3303", 0x55, 0x58, {0x9e, 0x00} },
        {"Acer", "Aspire 1410", "v1.3308", 0x55, 0x58, {0x9e, 0x00} },
        {"Acer", "Aspire 1410", "v1.3310", 0x55, 0x58, {0x9e, 0x00} },
+       {"Acer", "Aspire 1410", "v1.3314", 0x55, 0x58, {0x9e, 0x00} },
        /* Acer 1810xx */
        {"Acer", "Aspire 1810TZ", "v0.3108", 0x55, 0x58, {0x9e, 0x00} },
        {"Acer", "Aspire 1810T",  "v0.3108", 0x55, 0x58, {0x9e, 0x00} },
@@ -183,29 +186,44 @@ static const struct bios_settings_t bios_tbl[] = {
        {"Acer", "Aspire 1810TZ", "v1.3310", 0x55, 0x58, {0x9e, 0x00} },
        {"Acer", "Aspire 1810T",  "v1.3310", 0x55, 0x58, {0x9e, 0x00} },
        {"Acer", "Aspire 1810TZ", "v1.3314", 0x55, 0x58, {0x9e, 0x00} },
+       {"Acer", "Aspire 1810T",  "v1.3314", 0x55, 0x58, {0x9e, 0x00} },
        /* Acer 531 */
+       {"Acer", "AO531h", "v0.3104", 0x55, 0x58, {0x20, 0x00} },
        {"Acer", "AO531h", "v0.3201", 0x55, 0x58, {0x20, 0x00} },
+       {"Acer", "AO531h", "v0.3304", 0x55, 0x58, {0x20, 0x00} },
+       /* Acer 751 */
+       {"Acer", "AO751h", "V0.3212", 0x55, 0x58, {0x21, 0x00} },
+       /* Acer 1825 */
+       {"Acer", "Aspire 1825PTZ", "V1.3118", 0x55, 0x58, {0x9e, 0x00} },
+       {"Acer", "Aspire 1825PTZ", "V1.3127", 0x55, 0x58, {0x9e, 0x00} },
+       /* Acer TravelMate 7730 */
+       {"Acer", "TravelMate 7730G", "v0.3509", 0x55, 0x58, {0xaf, 0x00} },
        /* Gateway */
-       {"Gateway", "AOA110", "v0.3103", 0x55, 0x58, {0x21, 0x00} },
-       {"Gateway", "AOA150", "v0.3103", 0x55, 0x58, {0x20, 0x00} },
-       {"Gateway", "LT31",   "v1.3103", 0x55, 0x58, {0x9e, 0x00} },
-       {"Gateway", "LT31",   "v1.3201", 0x55, 0x58, {0x9e, 0x00} },
-       {"Gateway", "LT31",   "v1.3302", 0x55, 0x58, {0x9e, 0x00} },
+       {"Gateway", "AOA110", "v0.3103",  0x55, 0x58, {0x21, 0x00} },
+       {"Gateway", "AOA150", "v0.3103",  0x55, 0x58, {0x20, 0x00} },
+       {"Gateway", "LT31",   "v1.3103",  0x55, 0x58, {0x9e, 0x00} },
+       {"Gateway", "LT31",   "v1.3201",  0x55, 0x58, {0x9e, 0x00} },
+       {"Gateway", "LT31",   "v1.3302",  0x55, 0x58, {0x9e, 0x00} },
+       {"Gateway", "LT31",   "v1.3303t", 0x55, 0x58, {0x9e, 0x00} },
        /* Packard Bell */
-       {"Packard Bell", "DOA150", "v0.3104", 0x55, 0x58, {0x21, 0x00} },
-       {"Packard Bell", "DOA150", "v0.3105", 0x55, 0x58, {0x20, 0x00} },
-       {"Packard Bell", "AOA110", "v0.3105", 0x55, 0x58, {0x21, 0x00} },
-       {"Packard Bell", "AOA150", "v0.3105", 0x55, 0x58, {0x20, 0x00} },
-       {"Packard Bell", "DOTMU",  "v1.3303", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMU",  "v0.3120", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMU",  "v0.3108", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMU",  "v0.3113", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMU",  "v0.3115", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMU",  "v0.3117", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMU",  "v0.3119", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMU",  "v1.3204", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMA",  "v1.3201", 0x55, 0x58, {0x9e, 0x00} },
-       {"Packard Bell", "DOTMA",  "v1.3302", 0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOA150",  "v0.3104",  0x55, 0x58, {0x21, 0x00} },
+       {"Packard Bell", "DOA150",  "v0.3105",  0x55, 0x58, {0x20, 0x00} },
+       {"Packard Bell", "AOA110",  "v0.3105",  0x55, 0x58, {0x21, 0x00} },
+       {"Packard Bell", "AOA150",  "v0.3105",  0x55, 0x58, {0x20, 0x00} },
+       {"Packard Bell", "ENBFT",   "V1.3118",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "ENBFT",   "V1.3127",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMU",   "v1.3303",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMU",   "v0.3120",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMU",   "v0.3108",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMU",   "v0.3113",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMU",   "v0.3115",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMU",   "v0.3117",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMU",   "v0.3119",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMU",   "v1.3204",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMA",   "v1.3201",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMA",   "v1.3302",  0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTMA",   "v1.3303t", 0x55, 0x58, {0x9e, 0x00} },
+       {"Packard Bell", "DOTVR46", "v1.3308",  0x55, 0x58, {0x9e, 0x00} },
        /* pewpew-terminator */
        {"", "", "", 0, 0, {0, 0} }
 };
@@ -701,15 +719,20 @@ MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Peter Feuerer");
 MODULE_DESCRIPTION("Aspire One temperature and fan driver");
 MODULE_ALIAS("dmi:*:*Acer*:pnAOA*:");
+MODULE_ALIAS("dmi:*:*Acer*:pnAO751h*:");
 MODULE_ALIAS("dmi:*:*Acer*:pnAspire*1410*:");
 MODULE_ALIAS("dmi:*:*Acer*:pnAspire*1810*:");
+MODULE_ALIAS("dmi:*:*Acer*:pnAspire*1825PTZ:");
 MODULE_ALIAS("dmi:*:*Acer*:pnAO531*:");
+MODULE_ALIAS("dmi:*:*Acer*:TravelMate*7730G:");
 MODULE_ALIAS("dmi:*:*Gateway*:pnAOA*:");
 MODULE_ALIAS("dmi:*:*Gateway*:pnLT31*:");
 MODULE_ALIAS("dmi:*:*Packard*Bell*:pnAOA*:");
 MODULE_ALIAS("dmi:*:*Packard*Bell*:pnDOA*:");
 MODULE_ALIAS("dmi:*:*Packard*Bell*:pnDOTMU*:");
+MODULE_ALIAS("dmi:*:*Packard*Bell*:pnENBFT*:");
 MODULE_ALIAS("dmi:*:*Packard*Bell*:pnDOTMA*:");
+MODULE_ALIAS("dmi:*:*Packard*Bell*:pnDOTVR46*:");
 
 module_init(acerhdf_init);
 module_exit(acerhdf_exit);

diff --git a/drivers/platform/x86/dell-laptop.c b/drivers/platform/x86/dell-laptop.c
index a05fc9c..e6c08ee 100644 (file)
--- a/drivers/platform/x86/dell-laptop.c
+++ b/drivers/platform/x86/dell-laptop.c
@@ -212,6 +212,7 @@ static struct dmi_system_id __devinitdata dell_quirks[] = {
                },
                .driver_data = &quirk_dell_vostro_v130,
        },
+       { }
 };
 
 static struct calling_interface_buffer *buffer;

diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c
index f7ba316..0ffdb3c 100644 (file)
--- a/drivers/platform/x86/intel_ips.c
+++ b/drivers/platform/x86/intel_ips.c
@@ -1565,7 +1565,7 @@ static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id)
                ips->poll_turbo_status = true;
 
        if (!ips_get_i915_syms(ips)) {
-               dev_err(&dev->dev, "failed to get i915 symbols, graphics turbo disabled\n");
+               dev_info(&dev->dev, "failed to get i915 symbols, graphics turbo disabled until i915 loads\n");
                ips->gpu_turbo_enabled = false;
        } else {
                dev_dbg(&dev->dev, "graphics turbo enabled\n");

diff --git a/drivers/platform/x86/intel_mid_powerbtn.c b/drivers/platform/x86/intel_mid_powerbtn.c
index 0a3594c..bcbad84 100644 (file)
--- a/drivers/platform/x86/intel_mid_powerbtn.c
+++ b/drivers/platform/x86/intel_mid_powerbtn.c
@@ -78,7 +78,7 @@ static int __devinit mfld_pb_probe(struct platform_device *pdev)
 
        input_set_capability(input, EV_KEY, KEY_POWER);
 
-       error = request_threaded_irq(irq, NULL, mfld_pb_isr, 0,
+       error = request_threaded_irq(irq, NULL, mfld_pb_isr, IRQF_NO_SUSPEND,
                        DRIVER_NAME, input);
        if (error) {
                dev_err(&pdev->dev, "Unable to request irq %d for mfld power"

diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index cd188ab..c293d0c 100644 (file)
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -902,6 +902,7 @@ read_rtc:
                }
                ds1307->nvram->attr.name = "nvram";
                ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
+               sysfs_bin_attr_init(ds1307->nvram);
                ds1307->nvram->read = ds1307_nvram_read,
                ds1307->nvram->write = ds1307_nvram_write,
                ds1307->nvram->size = chip->nvram_size;

diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c
index d93a960..891cd6c 100644 (file)
--- a/drivers/rtc/rtc-imxdi.c
+++ b/drivers/rtc/rtc-imxdi.c
@@ -405,7 +405,7 @@ static int dryice_rtc_probe(struct platform_device *pdev)
        imxdi->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(imxdi->clk))
                return PTR_ERR(imxdi->clk);
-       clk_enable(imxdi->clk);
+       clk_prepare_enable(imxdi->clk);
 
        /*
         * Initialize dryice hardware
@@ -470,7 +470,7 @@ static int dryice_rtc_probe(struct platform_device *pdev)
        return 0;
 
 err:
-       clk_disable(imxdi->clk);
+       clk_disable_unprepare(imxdi->clk);
        clk_put(imxdi->clk);
 
        return rc;
@@ -487,7 +487,7 @@ static int __devexit dryice_rtc_remove(struct platform_device *pdev)
 
        rtc_device_unregister(imxdi->rtc);
 
-       clk_disable(imxdi->clk);
+       clk_disable_unprepare(imxdi->clk);
        clk_put(imxdi->clk);
 
        return 0;

diff --git a/drivers/rtc/rtc-mpc5121.c b/drivers/rtc/rtc-mpc5121.c
index 42f5f82..029e421 100644 (file)
--- a/drivers/rtc/rtc-mpc5121.c
+++ b/drivers/rtc/rtc-mpc5121.c
@@ -360,12 +360,11 @@ static int __devinit mpc5121_rtc_probe(struct platform_device *op)
                                                &mpc5200_rtc_ops, THIS_MODULE);
        }
 
-       rtc->rtc->uie_unsupported = 1;
-
        if (IS_ERR(rtc->rtc)) {
                err = PTR_ERR(rtc->rtc);
                goto out_free_irq;
        }
+       rtc->rtc->uie_unsupported = 1;
 
        return 0;
 

diff --git a/drivers/s390/net/qeth_core_main.c b/drivers/s390/net/qeth_core_main.c
index 120955c..8334dad 100644 (file)
--- a/drivers/s390/net/qeth_core_main.c
+++ b/drivers/s390/net/qeth_core_main.c
@@ -1672,7 +1672,8 @@ static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
 {
        QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
 
-       if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
+       if (prcd[74] == 0xF0 && prcd[75] == 0xF0 &&
+           (prcd[76] == 0xF5 || prcd[76] == 0xF6)) {
                card->info.blkt.time_total = 250;
                card->info.blkt.inter_packet = 5;
                card->info.blkt.inter_packet_jumbo = 15;
@@ -4540,7 +4541,8 @@ static void qeth_determine_capabilities(struct qeth_card *card)
                goto out_offline;
        }
        qeth_configure_unitaddr(card, prcd);
-       qeth_configure_blkt_default(card, prcd);
+       if (ddev_offline)
+               qeth_configure_blkt_default(card, prcd);
        kfree(prcd);
 
        rc = qdio_get_ssqd_desc(ddev, &card->ssqd);

diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c
index e002cd4..467dc38 100644 (file)
--- a/drivers/scsi/ipr.c
+++ b/drivers/scsi/ipr.c
@@ -4549,8 +4549,12 @@ static int ipr_ata_slave_alloc(struct scsi_device *sdev)
        ENTER;
        if (sdev->sdev_target)
                sata_port = sdev->sdev_target->hostdata;
-       if (sata_port)
+       if (sata_port) {
                rc = ata_sas_port_init(sata_port->ap);
+               if (rc == 0)
+                       rc = ata_sas_sync_probe(sata_port->ap);
+       }
+
        if (rc)
                ipr_slave_destroy(sdev);
 

diff --git a/drivers/scsi/libfc/fc_lport.c b/drivers/scsi/libfc/fc_lport.c
index ef9560d..cc83b66 100644 (file)
--- a/drivers/scsi/libfc/fc_lport.c
+++ b/drivers/scsi/libfc/fc_lport.c
@@ -1742,17 +1742,19 @@ void fc_lport_flogi_resp(struct fc_seq *sp, struct fc_frame *fp,
 
        mfs = ntohs(flp->fl_csp.sp_bb_data) &
                FC_SP_BB_DATA_MASK;
-       if (mfs >= FC_SP_MIN_MAX_PAYLOAD &&
-           mfs <= lport->mfs) {
-               lport->mfs = mfs;
-               fc_host_maxframe_size(lport->host) = mfs;
-       } else {
+
+       if (mfs < FC_SP_MIN_MAX_PAYLOAD || mfs > FC_SP_MAX_MAX_PAYLOAD) {
                FC_LPORT_DBG(lport, "FLOGI bad mfs:%hu response, "
                             "lport->mfs:%hu\n", mfs, lport->mfs);
                fc_lport_error(lport, fp);
                goto err;
        }
 
+       if (mfs <= lport->mfs) {
+               lport->mfs = mfs;
+               fc_host_maxframe_size(lport->host) = mfs;
+       }
+
        csp_flags = ntohs(flp->fl_csp.sp_features);
        r_a_tov = ntohl(flp->fl_csp.sp_r_a_tov);
        e_d_tov = ntohl(flp->fl_csp.sp_e_d_tov);

diff --git a/drivers/scsi/libsas/sas_ata.c b/drivers/scsi/libsas/sas_ata.c
index bc0cecc..441d88a 100644 (file)
--- a/drivers/scsi/libsas/sas_ata.c
+++ b/drivers/scsi/libsas/sas_ata.c
@@ -546,11 +546,12 @@ static struct ata_port_info sata_port_info = {
        .port_ops = &sas_sata_ops
 };
 
-int sas_ata_init_host_and_port(struct domain_device *found_dev)
+int sas_ata_init(struct domain_device *found_dev)
 {
        struct sas_ha_struct *ha = found_dev->port->ha;
        struct Scsi_Host *shost = ha->core.shost;
        struct ata_port *ap;
+       int rc;
 
        ata_host_init(&found_dev->sata_dev.ata_host,
                      ha->dev,
@@ -567,8 +568,11 @@ int sas_ata_init_host_and_port(struct domain_device *found_dev)
        ap->private_data = found_dev;
        ap->cbl = ATA_CBL_SATA;
        ap->scsi_host = shost;
-       /* publish initialized ata port */
-       smp_wmb();
+       rc = ata_sas_port_init(ap);
+       if (rc) {
+               ata_sas_port_destroy(ap);
+               return rc;
+       }
        found_dev->sata_dev.ap = ap;
 
        return 0;
@@ -648,18 +652,13 @@ static void sas_get_ata_command_set(struct domain_device *dev)
 void sas_probe_sata(struct asd_sas_port *port)
 {
        struct domain_device *dev, *n;
-       int err;
 
        mutex_lock(&port->ha->disco_mutex);
-       list_for_each_entry_safe(dev, n, &port->disco_list, disco_list_node) {
+       list_for_each_entry(dev, &port->disco_list, disco_list_node) {
                if (!dev_is_sata(dev))
                        continue;
 
-               err = sas_ata_init_host_and_port(dev);
-               if (err)
-                       sas_fail_probe(dev, __func__, err);
-               else
-                       ata_sas_async_port_init(dev->sata_dev.ap);
+               ata_sas_async_probe(dev->sata_dev.ap);
        }
        mutex_unlock(&port->ha->disco_mutex);
 
@@ -718,18 +717,6 @@ static void async_sas_ata_eh(void *data, async_cookie_t cookie)
        sas_put_device(dev);
 }
 
-static bool sas_ata_dev_eh_valid(struct domain_device *dev)
-{
-       struct ata_port *ap;
-
-       if (!dev_is_sata(dev))
-               return false;
-       ap = dev->sata_dev.ap;
-       /* consume fully initialized ata ports */
-       smp_rmb();
-       return !!ap;
-}
-
 void sas_ata_strategy_handler(struct Scsi_Host *shost)
 {
        struct sas_ha_struct *sas_ha = SHOST_TO_SAS_HA(shost);
@@ -753,7 +740,7 @@ void sas_ata_strategy_handler(struct Scsi_Host *shost)
 
                spin_lock(&port->dev_list_lock);
                list_for_each_entry(dev, &port->dev_list, dev_list_node) {
-                       if (!sas_ata_dev_eh_valid(dev))
+                       if (!dev_is_sata(dev))
                                continue;
                        async_schedule_domain(async_sas_ata_eh, dev, &async);
                }

diff --git a/drivers/scsi/libsas/sas_discover.c b/drivers/scsi/libsas/sas_discover.c
index 3646796..629a086 100644 (file)
--- a/drivers/scsi/libsas/sas_discover.c
+++ b/drivers/scsi/libsas/sas_discover.c
@@ -72,6 +72,7 @@ static int sas_get_port_device(struct asd_sas_port *port)
        struct asd_sas_phy *phy;
        struct sas_rphy *rphy;
        struct domain_device *dev;
+       int rc = -ENODEV;
 
        dev = sas_alloc_device();
        if (!dev)
@@ -110,9 +111,16 @@ static int sas_get_port_device(struct asd_sas_port *port)
 
        sas_init_dev(dev);
 
+       dev->port = port;
        switch (dev->dev_type) {
-       case SAS_END_DEV:
        case SATA_DEV:
+               rc = sas_ata_init(dev);
+               if (rc) {
+                       rphy = NULL;
+                       break;
+               }
+               /* fall through */
+       case SAS_END_DEV:
                rphy = sas_end_device_alloc(port->port);
                break;
        case EDGE_DEV:
@@ -131,19 +139,14 @@ static int sas_get_port_device(struct asd_sas_port *port)
 
        if (!rphy) {
                sas_put_device(dev);
-               return -ENODEV;
+               return rc;
        }
 
-       spin_lock_irq(&port->phy_list_lock);
-       list_for_each_entry(phy, &port->phy_list, port_phy_el)
-               sas_phy_set_target(phy, dev);
-       spin_unlock_irq(&port->phy_list_lock);
        rphy->identify.phy_identifier = phy->phy->identify.phy_identifier;
        memcpy(dev->sas_addr, port->attached_sas_addr, SAS_ADDR_SIZE);
        sas_fill_in_rphy(dev, rphy);
        sas_hash_addr(dev->hashed_sas_addr, dev->sas_addr);
        port->port_dev = dev;
-       dev->port = port;
        dev->linkrate = port->linkrate;
        dev->min_linkrate = port->linkrate;
        dev->max_linkrate = port->linkrate;
@@ -155,6 +158,7 @@ static int sas_get_port_device(struct asd_sas_port *port)
        sas_device_set_phy(dev, port->port);
 
        dev->rphy = rphy;
+       get_device(&dev->rphy->dev);
 
        if (dev_is_sata(dev) || dev->dev_type == SAS_END_DEV)
                list_add_tail(&dev->disco_list_node, &port->disco_list);
@@ -164,6 +168,11 @@ static int sas_get_port_device(struct asd_sas_port *port)
                spin_unlock_irq(&port->dev_list_lock);
        }
 
+       spin_lock_irq(&port->phy_list_lock);
+       list_for_each_entry(phy, &port->phy_list, port_phy_el)
+               sas_phy_set_target(phy, dev);
+       spin_unlock_irq(&port->phy_list_lock);
+
        return 0;
 }
 
@@ -205,8 +214,7 @@ void sas_notify_lldd_dev_gone(struct domain_device *dev)
 static void sas_probe_devices(struct work_struct *work)
 {
        struct domain_device *dev, *n;
-       struct sas_discovery_event *ev =
-               container_of(work, struct sas_discovery_event, work);
+       struct sas_discovery_event *ev = to_sas_discovery_event(work);
        struct asd_sas_port *port = ev->port;
 
        clear_bit(DISCE_PROBE, &port->disc.pending);
@@ -255,6 +263,9 @@ void sas_free_device(struct kref *kref)
 {
        struct domain_device *dev = container_of(kref, typeof(*dev), kref);
 
+       put_device(&dev->rphy->dev);
+       dev->rphy = NULL;
+
        if (dev->parent)
                sas_put_device(dev->parent);
 
@@ -291,8 +302,7 @@ static void sas_unregister_common_dev(struct asd_sas_port *port, struct domain_d
 static void sas_destruct_devices(struct work_struct *work)
 {
        struct domain_device *dev, *n;
-       struct sas_discovery_event *ev =
-               container_of(work, struct sas_discovery_event, work);
+       struct sas_discovery_event *ev = to_sas_discovery_event(work);
        struct asd_sas_port *port = ev->port;
 
        clear_bit(DISCE_DESTRUCT, &port->disc.pending);
@@ -302,7 +312,6 @@ static void sas_destruct_devices(struct work_struct *work)
 
                sas_remove_children(&dev->rphy->dev);
                sas_rphy_delete(dev->rphy);
-               dev->rphy = NULL;
                sas_unregister_common_dev(port, dev);
        }
 }
@@ -314,11 +323,11 @@ void sas_unregister_dev(struct asd_sas_port *port, struct domain_device *dev)
                /* this rphy never saw sas_rphy_add */
                list_del_init(&dev->disco_list_node);
                sas_rphy_free(dev->rphy);
-               dev->rphy = NULL;
                sas_unregister_common_dev(port, dev);
+               return;
        }
 
-       if (dev->rphy && !test_and_set_bit(SAS_DEV_DESTROY, &dev->state)) {
+       if (!test_and_set_bit(SAS_DEV_DESTROY, &dev->state)) {
                sas_rphy_unlink(dev->rphy);
                list_move_tail(&dev->disco_list_node, &port->destroy_list);
                sas_discover_event(dev->port, DISCE_DESTRUCT);
@@ -377,8 +386,7 @@ static void sas_discover_domain(struct work_struct *work)
 {
        struct domain_device *dev;
        int error = 0;
-       struct sas_discovery_event *ev =
-               container_of(work, struct sas_discovery_event, work);
+       struct sas_discovery_event *ev = to_sas_discovery_event(work);
        struct asd_sas_port *port = ev->port;
 
        clear_bit(DISCE_DISCOVER_DOMAIN, &port->disc.pending);
@@ -419,8 +427,6 @@ static void sas_discover_domain(struct work_struct *work)
 
        if (error) {
                sas_rphy_free(dev->rphy);
-               dev->rphy = NULL;
-
                list_del_init(&dev->disco_list_node);
                spin_lock_irq(&port->dev_list_lock);
                list_del_init(&dev->dev_list_node);
@@ -437,8 +443,7 @@ static void sas_discover_domain(struct work_struct *work)
 static void sas_revalidate_domain(struct work_struct *work)
 {
        int res = 0;
-       struct sas_discovery_event *ev =
-               container_of(work, struct sas_discovery_event, work);
+       struct sas_discovery_event *ev = to_sas_discovery_event(work);
        struct asd_sas_port *port = ev->port;
        struct sas_ha_struct *ha = port->ha;
 
@@ -466,21 +471,25 @@ static void sas_revalidate_domain(struct work_struct *work)
 
 /* ---------- Events ---------- */
 
-static void sas_chain_work(struct sas_ha_struct *ha, struct work_struct *work)
+static void sas_chain_work(struct sas_ha_struct *ha, struct sas_work *sw)
 {
-       /* chained work is not subject to SA_HA_DRAINING or SAS_HA_REGISTERED */
-       scsi_queue_work(ha->core.shost, work);
+       /* chained work is not subject to SA_HA_DRAINING or
+        * SAS_HA_REGISTERED, because it is either submitted in the
+        * workqueue, or known to be submitted from a context that is
+        * not racing against draining
+        */
+       scsi_queue_work(ha->core.shost, &sw->work);
 }
 
 static void sas_chain_event(int event, unsigned long *pending,
-                           struct work_struct *work,
+                           struct sas_work *sw,
                            struct sas_ha_struct *ha)
 {
        if (!test_and_set_bit(event, pending)) {
                unsigned long flags;
 
                spin_lock_irqsave(&ha->state_lock, flags);
-               sas_chain_work(ha, work);
+               sas_chain_work(ha, sw);
                spin_unlock_irqrestore(&ha->state_lock, flags);
        }
 }
@@ -519,7 +528,7 @@ void sas_init_disc(struct sas_discovery *disc, struct asd_sas_port *port)
 
        disc->pending = 0;
        for (i = 0; i < DISC_NUM_EVENTS; i++) {
-               INIT_WORK(&disc->disc_work[i].work, sas_event_fns[i]);
+               INIT_SAS_WORK(&disc->disc_work[i].work, sas_event_fns[i]);
                disc->disc_work[i].port = port;
        }
 }

diff --git a/drivers/scsi/libsas/sas_event.c b/drivers/scsi/libsas/sas_event.c
index 16639bb..4e4292d 100644 (file)
--- a/drivers/scsi/libsas/sas_event.c
+++ b/drivers/scsi/libsas/sas_event.c
@@ -27,19 +27,21 @@
 #include "sas_internal.h"
 #include "sas_dump.h"
 
-void sas_queue_work(struct sas_ha_struct *ha, struct work_struct *work)
+void sas_queue_work(struct sas_ha_struct *ha, struct sas_work *sw)
 {
        if (!test_bit(SAS_HA_REGISTERED, &ha->state))
                return;
 
-       if (test_bit(SAS_HA_DRAINING, &ha->state))
-               list_add(&work->entry, &ha->defer_q);
-       else
-               scsi_queue_work(ha->core.shost, work);
+       if (test_bit(SAS_HA_DRAINING, &ha->state)) {
+               /* add it to the defer list, if not already pending */
+               if (list_empty(&sw->drain_node))
+                       list_add(&sw->drain_node, &ha->defer_q);
+       } else
+               scsi_queue_work(ha->core.shost, &sw->work);
 }
 
 static void sas_queue_event(int event, unsigned long *pending,
-                           struct work_struct *work,
+                           struct sas_work *work,
                            struct sas_ha_struct *ha)
 {
        if (!test_and_set_bit(event, pending)) {
@@ -55,7 +57,7 @@ static void sas_queue_event(int event, unsigned long *pending,
 void __sas_drain_work(struct sas_ha_struct *ha)
 {
        struct workqueue_struct *wq = ha->core.shost->work_q;
-       struct work_struct *w, *_w;
+       struct sas_work *sw, *_sw;
 
        set_bit(SAS_HA_DRAINING, &ha->state);
        /* flush submitters */
@@ -66,9 +68,9 @@ void __sas_drain_work(struct sas_ha_struct *ha)
 
        spin_lock_irq(&ha->state_lock);
        clear_bit(SAS_HA_DRAINING, &ha->state);
-       list_for_each_entry_safe(w, _w, &ha->defer_q, entry) {
-               list_del_init(&w->entry);
-               sas_queue_work(ha, w);
+       list_for_each_entry_safe(sw, _sw, &ha->defer_q, drain_node) {
+               list_del_init(&sw->drain_node);
+               sas_queue_work(ha, sw);
        }
        spin_unlock_irq(&ha->state_lock);
 }
@@ -151,7 +153,7 @@ int sas_init_events(struct sas_ha_struct *sas_ha)
        int i;
 
        for (i = 0; i < HA_NUM_EVENTS; i++) {
-               INIT_WORK(&sas_ha->ha_events[i].work, sas_ha_event_fns[i]);
+               INIT_SAS_WORK(&sas_ha->ha_events[i].work, sas_ha_event_fns[i]);
                sas_ha->ha_events[i].ha = sas_ha;
        }
 

diff --git a/drivers/scsi/libsas/sas_expander.c b/drivers/scsi/libsas/sas_expander.c
index 05acd9e..caa0525 100644 (file)
--- a/drivers/scsi/libsas/sas_expander.c
+++ b/drivers/scsi/libsas/sas_expander.c
@@ -202,6 +202,7 @@ static void sas_set_ex_phy(struct domain_device *dev, int phy_id, void *rsp)
        u8 sas_addr[SAS_ADDR_SIZE];
        struct smp_resp *resp = rsp;
        struct discover_resp *dr = &resp->disc;
+       struct sas_ha_struct *ha = dev->port->ha;
        struct expander_device *ex = &dev->ex_dev;
        struct ex_phy *phy = &ex->ex_phy[phy_id];
        struct sas_rphy *rphy = dev->rphy;
@@ -209,6 +210,8 @@ static void sas_set_ex_phy(struct domain_device *dev, int phy_id, void *rsp)
        char *type;
 
        if (new_phy) {
+               if (WARN_ON_ONCE(test_bit(SAS_HA_ATA_EH_ACTIVE, &ha->state)))
+                       return;
                phy->phy = sas_phy_alloc(&rphy->dev, phy_id);
 
                /* FIXME: error_handling */
@@ -233,6 +236,8 @@ static void sas_set_ex_phy(struct domain_device *dev, int phy_id, void *rsp)
        memcpy(sas_addr, phy->attached_sas_addr, SAS_ADDR_SIZE);
 
        phy->attached_dev_type = to_dev_type(dr);
+       if (test_bit(SAS_HA_ATA_EH_ACTIVE, &ha->state))
+               goto out;
        phy->phy_id = phy_id;
        phy->linkrate = dr->linkrate;
        phy->attached_sata_host = dr->attached_sata_host;
@@ -240,7 +245,14 @@ static void sas_set_ex_phy(struct domain_device *dev, int phy_id, void *rsp)
        phy->attached_sata_ps   = dr->attached_sata_ps;
        phy->attached_iproto = dr->iproto << 1;
        phy->attached_tproto = dr->tproto << 1;
-       memcpy(phy->attached_sas_addr, dr->attached_sas_addr, SAS_ADDR_SIZE);
+       /* help some expanders that fail to zero sas_address in the 'no
+        * device' case
+        */
+       if (phy->attached_dev_type == NO_DEVICE ||
+           phy->linkrate < SAS_LINK_RATE_1_5_GBPS)
+               memset(phy->attached_sas_addr, 0, SAS_ADDR_SIZE);
+       else
+               memcpy(phy->attached_sas_addr, dr->attached_sas_addr, SAS_ADDR_SIZE);
        phy->attached_phy_id = dr->attached_phy_id;
        phy->phy_change_count = dr->change_count;
        phy->routing_attr = dr->routing_attr;
@@ -266,6 +278,7 @@ static void sas_set_ex_phy(struct domain_device *dev, int phy_id, void *rsp)
                        return;
                }
 
+ out:
        switch (phy->attached_dev_type) {
        case SATA_PENDING:
                type = "stp pending";
@@ -304,7 +317,15 @@ static void sas_set_ex_phy(struct domain_device *dev, int phy_id, void *rsp)
        else
                return;
 
-       SAS_DPRINTK("ex %016llx phy%02d:%c:%X attached: %016llx (%s)\n",
+       /* if the attached device type changed and ata_eh is active,
+        * make sure we run revalidation when eh completes (see:
+        * sas_enable_revalidation)
+        */
+       if (test_bit(SAS_HA_ATA_EH_ACTIVE, &ha->state))
+               set_bit(DISCE_REVALIDATE_DOMAIN, &dev->port->disc.pending);
+
+       SAS_DPRINTK("%sex %016llx phy%02d:%c:%X attached: %016llx (%s)\n",
+                   test_bit(SAS_HA_ATA_EH_ACTIVE, &ha->state) ? "ata: " : "",
                    SAS_ADDR(dev->sas_addr), phy->phy_id,
                    sas_route_char(dev, phy), phy->linkrate,
                    SAS_ADDR(phy->attached_sas_addr), type);
@@ -776,13 +797,16 @@ static struct domain_device *sas_ex_discover_end_dev(
                if (res)
                        goto out_free;
 
+               sas_init_dev(child);
+               res = sas_ata_init(child);
+               if (res)
+                       goto out_free;
                rphy = sas_end_device_alloc(phy->port);
-               if (unlikely(!rphy))
+               if (!rphy)
                        goto out_free;
 
-               sas_init_dev(child);
-
                child->rphy = rphy;
+               get_device(&rphy->dev);
 
                list_add_tail(&child->disco_list_node, &parent->port->disco_list);
 
@@ -806,6 +830,7 @@ static struct domain_device *sas_ex_discover_end_dev(
                sas_init_dev(child);
 
                child->rphy = rphy;
+               get_device(&rphy->dev);
                sas_fill_in_rphy(child, rphy);
 
                list_add_tail(&child->disco_list_node, &parent->port->disco_list);
@@ -830,8 +855,6 @@ static struct domain_device *sas_ex_discover_end_dev(
 
  out_list_del:
        sas_rphy_free(child->rphy);
-       child->rphy = NULL;
-
        list_del(&child->disco_list_node);
        spin_lock_irq(&parent->port->dev_list_lock);
        list_del(&child->dev_list_node);
@@ -911,6 +934,7 @@ static struct domain_device *sas_ex_discover_expander(
        }
        port = parent->port;
        child->rphy = rphy;
+       get_device(&rphy->dev);
        edev = rphy_to_expander_device(rphy);
        child->dev_type = phy->attached_dev_type;
        kref_get(&parent->kref);
@@ -934,6 +958,7 @@ static struct domain_device *sas_ex_discover_expander(
 
        res = sas_discover_expander(child);
        if (res) {
+               sas_rphy_delete(rphy);
                spin_lock_irq(&parent->port->dev_list_lock);
                list_del(&child->dev_list_node);
                spin_unlock_irq(&parent->port->dev_list_lock);
@@ -1718,9 +1743,17 @@ static int sas_find_bcast_phy(struct domain_device *dev, int *phy_id,
                int phy_change_count = 0;
 
                res = sas_get_phy_change_count(dev, i, &phy_change_count);
-               if (res)
-                       goto out;
-               else if (phy_change_count != ex->ex_phy[i].phy_change_count) {
+               switch (res) {
+               case SMP_RESP_PHY_VACANT:
+               case SMP_RESP_NO_PHY:
+                       continue;
+               case SMP_RESP_FUNC_ACC:
+                       break;
+               default:
+                       return res;
+               }
+
+               if (phy_change_count != ex->ex_phy[i].phy_change_count) {
                        if (update)
                                ex->ex_phy[i].phy_change_count =
                                        phy_change_count;
@@ -1728,8 +1761,7 @@ static int sas_find_bcast_phy(struct domain_device *dev, int *phy_id,
                        return 0;
                }
        }
-out:
-       return res;
+       return 0;
 }
 
 static int sas_get_ex_change_count(struct domain_device *dev, int *ecc)

diff --git a/drivers/scsi/libsas/sas_init.c b/drivers/scsi/libsas/sas_init.c
index 120bff6..10cb5ae 100644 (file)
--- a/drivers/scsi/libsas/sas_init.c
+++ b/drivers/scsi/libsas/sas_init.c
@@ -94,8 +94,7 @@ void sas_hash_addr(u8 *hashed, const u8 *sas_addr)
 
 void sas_hae_reset(struct work_struct *work)
 {
-       struct sas_ha_event *ev =
-               container_of(work, struct sas_ha_event, work);
+       struct sas_ha_event *ev = to_sas_ha_event(work);
        struct sas_ha_struct *ha = ev->ha;
 
        clear_bit(HAE_RESET, &ha->pending);
@@ -369,14 +368,14 @@ static void sas_phy_release(struct sas_phy *phy)
 
 static void phy_reset_work(struct work_struct *work)
 {
-       struct sas_phy_data *d = container_of(work, typeof(*d), reset_work);
+       struct sas_phy_data *d = container_of(work, typeof(*d), reset_work.work);
 
        d->reset_result = transport_sas_phy_reset(d->phy, d->hard_reset);
 }
 
 static void phy_enable_work(struct work_struct *work)
 {
-       struct sas_phy_data *d = container_of(work, typeof(*d), enable_work);
+       struct sas_phy_data *d = container_of(work, typeof(*d), enable_work.work);
 
        d->enable_result = sas_phy_enable(d->phy, d->enable);
 }
@@ -389,8 +388,8 @@ static int sas_phy_setup(struct sas_phy *phy)
                return -ENOMEM;
 
        mutex_init(&d->event_lock);
-       INIT_WORK(&d->reset_work, phy_reset_work);
-       INIT_WORK(&d->enable_work, phy_enable_work);
+       INIT_SAS_WORK(&d->reset_work, phy_reset_work);
+       INIT_SAS_WORK(&d->enable_work, phy_enable_work);
        d->phy = phy;
        phy->hostdata = d;
 

diff --git a/drivers/scsi/libsas/sas_internal.h b/drivers/scsi/libsas/sas_internal.h
index f05c638..507e4cf 100644 (file)
--- a/drivers/scsi/libsas/sas_internal.h
+++ b/drivers/scsi/libsas/sas_internal.h
@@ -45,10 +45,10 @@ struct sas_phy_data {
        struct mutex event_lock;
        int hard_reset;
        int reset_result;
-       struct work_struct reset_work;
+       struct sas_work reset_work;
        int enable;
        int enable_result;
-       struct work_struct enable_work;
+       struct sas_work enable_work;
 };
 
 void sas_scsi_recover_host(struct Scsi_Host *shost);
@@ -80,7 +80,7 @@ void sas_porte_broadcast_rcvd(struct work_struct *work);
 void sas_porte_link_reset_err(struct work_struct *work);
 void sas_porte_timer_event(struct work_struct *work);
 void sas_porte_hard_reset(struct work_struct *work);
-void sas_queue_work(struct sas_ha_struct *ha, struct work_struct *work);
+void sas_queue_work(struct sas_ha_struct *ha, struct sas_work *sw);
 
 int sas_notify_lldd_dev_found(struct domain_device *);
 void sas_notify_lldd_dev_gone(struct domain_device *);

diff --git a/drivers/scsi/libsas/sas_phy.c b/drivers/scsi/libsas/sas_phy.c
index dcfd4a9..521422e 100644 (file)
--- a/drivers/scsi/libsas/sas_phy.c
+++ b/drivers/scsi/libsas/sas_phy.c
@@ -32,8 +32,7 @@
 
 static void sas_phye_loss_of_signal(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
 
        clear_bit(PHYE_LOSS_OF_SIGNAL, &phy->phy_events_pending);
@@ -43,8 +42,7 @@ static void sas_phye_loss_of_signal(struct work_struct *work)
 
 static void sas_phye_oob_done(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
 
        clear_bit(PHYE_OOB_DONE, &phy->phy_events_pending);
@@ -53,8 +51,7 @@ static void sas_phye_oob_done(struct work_struct *work)
 
 static void sas_phye_oob_error(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
        struct sas_ha_struct *sas_ha = phy->ha;
        struct asd_sas_port *port = phy->port;
@@ -85,8 +82,7 @@ static void sas_phye_oob_error(struct work_struct *work)
 
 static void sas_phye_spinup_hold(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
        struct sas_ha_struct *sas_ha = phy->ha;
        struct sas_internal *i =
@@ -127,14 +123,12 @@ int sas_register_phys(struct sas_ha_struct *sas_ha)
                phy->error = 0;
                INIT_LIST_HEAD(&phy->port_phy_el);
                for (k = 0; k < PORT_NUM_EVENTS; k++) {
-                       INIT_WORK(&phy->port_events[k].work,
-                                 sas_port_event_fns[k]);
+                       INIT_SAS_WORK(&phy->port_events[k].work, sas_port_event_fns[k]);
                        phy->port_events[k].phy = phy;
                }
 
                for (k = 0; k < PHY_NUM_EVENTS; k++) {
-                       INIT_WORK(&phy->phy_events[k].work,
-                                 sas_phy_event_fns[k]);
+                       INIT_SAS_WORK(&phy->phy_events[k].work, sas_phy_event_fns[k]);
                        phy->phy_events[k].phy = phy;
                }
 
@@ -144,8 +138,7 @@ int sas_register_phys(struct sas_ha_struct *sas_ha)
                spin_lock_init(&phy->sas_prim_lock);
                phy->frame_rcvd_size = 0;
 
-               phy->phy = sas_phy_alloc(&sas_ha->core.shost->shost_gendev,
-                                        i);
+               phy->phy = sas_phy_alloc(&sas_ha->core.shost->shost_gendev, i);
                if (!phy->phy)
                        return -ENOMEM;
 

diff --git a/drivers/scsi/libsas/sas_port.c b/drivers/scsi/libsas/sas_port.c
index eb19c01..e884a8c 100644 (file)
--- a/drivers/scsi/libsas/sas_port.c
+++ b/drivers/scsi/libsas/sas_port.c
@@ -123,7 +123,7 @@ static void sas_form_port(struct asd_sas_phy *phy)
        spin_unlock_irqrestore(&sas_ha->phy_port_lock, flags);
 
        if (!port->port) {
-               port->port = sas_port_alloc(phy->phy->dev.parent, phy->id);
+               port->port = sas_port_alloc(phy->phy->dev.parent, port->id);
                BUG_ON(!port->port);
                sas_port_add(port->port);
        }
@@ -208,8 +208,7 @@ void sas_deform_port(struct asd_sas_phy *phy, int gone)
 
 void sas_porte_bytes_dmaed(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
 
        clear_bit(PORTE_BYTES_DMAED, &phy->port_events_pending);
@@ -219,8 +218,7 @@ void sas_porte_bytes_dmaed(struct work_struct *work)
 
 void sas_porte_broadcast_rcvd(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
        unsigned long flags;
        u32 prim;
@@ -237,8 +235,7 @@ void sas_porte_broadcast_rcvd(struct work_struct *work)
 
 void sas_porte_link_reset_err(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
 
        clear_bit(PORTE_LINK_RESET_ERR, &phy->port_events_pending);
@@ -248,8 +245,7 @@ void sas_porte_link_reset_err(struct work_struct *work)
 
 void sas_porte_timer_event(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
 
        clear_bit(PORTE_TIMER_EVENT, &phy->port_events_pending);
@@ -259,8 +255,7 @@ void sas_porte_timer_event(struct work_struct *work)
 
 void sas_porte_hard_reset(struct work_struct *work)
 {
-       struct asd_sas_event *ev =
-               container_of(work, struct asd_sas_event, work);
+       struct asd_sas_event *ev = to_asd_sas_event(work);
        struct asd_sas_phy *phy = ev->phy;
 
        clear_bit(PORTE_HARD_RESET, &phy->port_events_pending);

diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c
index ead6405..5dfd749 100644 (file)
--- a/drivers/scsi/scsi_lib.c
+++ b/drivers/scsi/scsi_lib.c
@@ -1638,7 +1638,7 @@ struct request_queue *__scsi_alloc_queue(struct Scsi_Host *shost,
                                         request_fn_proc *request_fn)
 {
        struct request_queue *q;
-       struct device *dev = shost->shost_gendev.parent;
+       struct device *dev = shost->dma_dev;
 
        q = blk_init_queue(request_fn, NULL);
        if (!q)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 3ed7483..00c0240 100644 (file)
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -74,7 +74,7 @@ config SPI_ATMEL
          This selects a driver for the Atmel SPI Controller, present on
          many AT32 (AVR32) and AT91 (ARM) chips.
 
-config SPI_BFIN
+config SPI_BFIN5XX
        tristate "SPI controller driver for ADI Blackfin5xx"
        depends on BLACKFIN
        help

diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index a1d48e0..9d75d21 100644 (file)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_SPI_ATMEL)                       += spi-atmel.o
 obj-$(CONFIG_SPI_ATH79)                        += spi-ath79.o
 obj-$(CONFIG_SPI_AU1550)               += spi-au1550.o
 obj-$(CONFIG_SPI_BCM63XX)              += spi-bcm63xx.o
-obj-$(CONFIG_SPI_BFIN)                 += spi-bfin5xx.o
+obj-$(CONFIG_SPI_BFIN5XX)              += spi-bfin5xx.o
 obj-$(CONFIG_SPI_BFIN_SPORT)           += spi-bfin-sport.o
 obj-$(CONFIG_SPI_BITBANG)              += spi-bitbang.o
 obj-$(CONFIG_SPI_BUTTERFLY)            += spi-butterfly.o

diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index f01b264..7491971 100644 (file)
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -1,7 +1,7 @@
 /*
  * Broadcom BCM63xx SPI controller support
  *
- * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
  * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -30,6 +30,8 @@
 #include <linux/spi/spi.h>
 #include <linux/completion.h>
 #include <linux/err.h>
+#include <linux/workqueue.h>
+#include <linux/pm_runtime.h>
 
 #include <bcm63xx_dev_spi.h>
 
@@ -37,8 +39,6 @@
 #define DRV_VER                "0.1.2"
 
 struct bcm63xx_spi {
-       spinlock_t              lock;
-       int                     stopping;
        struct completion       done;
 
        void __iomem            *regs;
@@ -96,17 +96,12 @@ static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
        {   391000, SPI_CLK_0_391MHZ }
 };
 
-static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
-                                     struct spi_transfer *t)
+static int bcm63xx_spi_check_transfer(struct spi_device *spi,
+                                       struct spi_transfer *t)
 {
-       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
        u8 bits_per_word;
-       u8 clk_cfg, reg;
-       u32 hz;
-       int i;
 
        bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
-       hz = (t) ? t->speed_hz : spi->max_speed_hz;
        if (bits_per_word != 8) {
                dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
                        __func__, bits_per_word);
@@ -119,6 +114,19 @@ static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
                return -EINVAL;
        }
 
+       return 0;
+}
+
+static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
+                                     struct spi_transfer *t)
+{
+       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
+       u32 hz;
+       u8 clk_cfg, reg;
+       int i;
+
+       hz = (t) ? t->speed_hz : spi->max_speed_hz;
+
        /* Find the closest clock configuration */
        for (i = 0; i < SPI_CLK_MASK; i++) {
                if (hz <= bcm63xx_spi_freq_table[i][0]) {
@@ -139,8 +147,6 @@ static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
        bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
        dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
                clk_cfg, hz);
-
-       return 0;
 }
 
 /* the spi->mode bits understood by this driver: */
@@ -153,9 +159,6 @@ static int bcm63xx_spi_setup(struct spi_device *spi)
 
        bs = spi_master_get_devdata(spi->master);
 
-       if (bs->stopping)
-               return -ESHUTDOWN;
-
        if (!spi->bits_per_word)
                spi->bits_per_word = 8;
 
@@ -165,7 +168,7 @@ static int bcm63xx_spi_setup(struct spi_device *spi)
                return -EINVAL;
        }
 
-       ret = bcm63xx_spi_setup_transfer(spi, NULL);
+       ret = bcm63xx_spi_check_transfer(spi, NULL);
        if (ret < 0) {
                dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
                        spi->mode & ~MODEBITS);
@@ -190,28 +193,29 @@ static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
        bs->remaining_bytes -= size;
 }
 
-static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
+static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi,
+                                       struct spi_transfer *t)
 {
        struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
        u16 msg_ctl;
        u16 cmd;
 
+       /* Disable the CMD_DONE interrupt */
+       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
+
        dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
                t->tx_buf, t->rx_buf, t->len);
 
        /* Transmitter is inhibited */
        bs->tx_ptr = t->tx_buf;
        bs->rx_ptr = t->rx_buf;
-       init_completion(&bs->done);
 
        if (t->tx_buf) {
                bs->remaining_bytes = t->len;
                bcm63xx_spi_fill_tx_fifo(bs);
        }
 
-       /* Enable the command done interrupt which
-        * we use to determine completion of a command */
-       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
+       init_completion(&bs->done);
 
        /* Fill in the Message control register */
        msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
@@ -230,33 +234,76 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
        cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
        cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
        bcm_spi_writew(bs, cmd, SPI_CMD);
-       wait_for_completion(&bs->done);
 
-       /* Disable the CMD_DONE interrupt */
-       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
+       /* Enable the CMD_DONE interrupt */
+       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 
        return t->len - bs->remaining_bytes;
 }
 
-static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
+static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
 {
-       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
-       struct spi_transfer *t;
-       int ret = 0;
+       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 
-       if (unlikely(list_empty(&m->transfers)))
-               return -EINVAL;
+       pm_runtime_get_sync(&bs->pdev->dev);
 
-       if (bs->stopping)
-               return -ESHUTDOWN;
+       return 0;
+}
+
+static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
+{
+       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
+
+       pm_runtime_put(&bs->pdev->dev);
+
+       return 0;
+}
+
+static int bcm63xx_spi_transfer_one(struct spi_master *master,
+                                       struct spi_message *m)
+{
+       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
+       struct spi_transfer *t;
+       struct spi_device *spi = m->spi;
+       int status = 0;
+       unsigned int timeout = 0;
 
        list_for_each_entry(t, &m->transfers, transfer_list) {
-               ret += bcm63xx_txrx_bufs(spi, t);
-       }
+               unsigned int len = t->len;
+               u8 rx_tail;
 
-       m->complete(m->context);
+               status = bcm63xx_spi_check_transfer(spi, t);
+               if (status < 0)
+                       goto exit;
 
-       return ret;
+               /* configure adapter for a new transfer */
+               bcm63xx_spi_setup_transfer(spi, t);
+
+               while (len) {
+                       /* send the data */
+                       len -= bcm63xx_txrx_bufs(spi, t);
+
+                       timeout = wait_for_completion_timeout(&bs->done, HZ);
+                       if (!timeout) {
+                               status = -ETIMEDOUT;
+                               goto exit;
+                       }
+
+                       /* read out all data */
+                       rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
+
+                       /* Read out all the data */
+                       if (rx_tail)
+                               memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
+               }
+
+               m->actual_length += t->len;
+       }
+exit:
+       m->status = status;
+       spi_finalize_current_message(master);
+
+       return 0;
 }
 
 /* This driver supports single master mode only. Hence
@@ -267,39 +314,15 @@ static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
        struct spi_master *master = (struct spi_master *)dev_id;
        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
        u8 intr;
-       u16 cmd;
 
        /* Read interupts and clear them immediately */
        intr = bcm_spi_readb(bs, SPI_INT_STATUS);
        bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
        bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 
-       /* A tansfer completed */
-       if (intr & SPI_INTR_CMD_DONE) {
-               u8 rx_tail;
-
-               rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
-
-               /* Read out all the data */
-               if (rx_tail)
-                       memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
-
-               /* See if there is more data to send */
-               if (bs->remaining_bytes > 0) {
-                       bcm63xx_spi_fill_tx_fifo(bs);
-
-                       /* Start the transfer */
-                       bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
-                                      SPI_MSG_CTL);
-                       cmd = bcm_spi_readw(bs, SPI_CMD);
-                       cmd |= SPI_CMD_START_IMMEDIATE;
-                       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
-                       bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
-                       bcm_spi_writew(bs, cmd, SPI_CMD);
-               } else {
-                       complete(&bs->done);
-               }
-       }
+       /* A transfer completed */
+       if (intr & SPI_INTR_CMD_DONE)
+               complete(&bs->done);
 
        return IRQ_HANDLED;
 }
@@ -345,7 +368,6 @@ static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
        }
 
        bs = spi_master_get_devdata(master);
-       init_completion(&bs->done);
 
        platform_set_drvdata(pdev, master);
        bs->pdev = pdev;
@@ -379,12 +401,13 @@ static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
        master->bus_num = pdata->bus_num;
        master->num_chipselect = pdata->num_chipselect;
        master->setup = bcm63xx_spi_setup;
-       master->transfer = bcm63xx_transfer;
+       master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
+       master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
+       master->transfer_one_message = bcm63xx_spi_transfer_one;
+       master->mode_bits = MODEBITS;
        bs->speed_hz = pdata->speed_hz;
-       bs->stopping = 0;
        bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
        bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
-       spin_lock_init(&bs->lock);
 
        /* Initialize hardware */
        clk_enable(bs->clk);
@@ -418,18 +441,16 @@ static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
        struct spi_master *master = platform_get_drvdata(pdev);
        struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 
+       spi_unregister_master(master);
+
        /* reset spi block */
        bcm_spi_writeb(bs, 0, SPI_INT_MASK);
-       spin_lock(&bs->lock);
-       bs->stopping = 1;
 
        /* HW shutdown */
        clk_disable(bs->clk);
        clk_put(bs->clk);
 
-       spin_unlock(&bs->lock);
        platform_set_drvdata(pdev, 0);
-       spi_unregister_master(master);
 
        return 0;
 }

diff --git a/drivers/spi/spi-bfin-sport.c b/drivers/spi/spi-bfin-sport.c
index 248a2cc..1fe5119 100644 (file)
--- a/drivers/spi/spi-bfin-sport.c
+++ b/drivers/spi/spi-bfin-sport.c
@@ -252,19 +252,15 @@ static void
 bfin_sport_spi_restore_state(struct bfin_sport_spi_master_data *drv_data)
 {
        struct bfin_sport_spi_slave_data *chip = drv_data->cur_chip;
-       unsigned int bits = (drv_data->ops == &bfin_sport_transfer_ops_u8 ? 7 : 15);
 
        bfin_sport_spi_disable(drv_data);
        dev_dbg(drv_data->dev, "restoring spi ctl state\n");
 
        bfin_write(&drv_data->regs->tcr1, chip->ctl_reg);
-       bfin_write(&drv_data->regs->tcr2, bits);
        bfin_write(&drv_data->regs->tclkdiv, chip->baud);
-       bfin_write(&drv_data->regs->tfsdiv, bits);
        SSYNC();
 
        bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS));
-       bfin_write(&drv_data->regs->rcr2, bits);
        SSYNC();
 
        bfin_sport_spi_cs_active(chip);
@@ -420,11 +416,15 @@ bfin_sport_spi_pump_transfers(unsigned long data)
        drv_data->cs_change = transfer->cs_change;
 
        /* Bits per word setup */
-       bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word;
-       if (bits_per_word == 8)
-               drv_data->ops = &bfin_sport_transfer_ops_u8;
-       else
+       bits_per_word = transfer->bits_per_word ? :
+               message->spi->bits_per_word ? : 8;
+       if (bits_per_word % 16 == 0)
                drv_data->ops = &bfin_sport_transfer_ops_u16;
+       else
+               drv_data->ops = &bfin_sport_transfer_ops_u8;
+       bfin_write(&drv_data->regs->tcr2, bits_per_word - 1);
+       bfin_write(&drv_data->regs->tfsdiv, bits_per_word - 1);
+       bfin_write(&drv_data->regs->rcr2, bits_per_word - 1);
 
        drv_data->state = RUNNING_STATE;
 
@@ -598,11 +598,12 @@ bfin_sport_spi_setup(struct spi_device *spi)
                        }
                        chip->cs_chg_udelay = chip_info->cs_chg_udelay;
                        chip->idle_tx_val = chip_info->idle_tx_val;
-                       spi->bits_per_word = chip_info->bits_per_word;
                }
        }
 
-       if (spi->bits_per_word != 8 && spi->bits_per_word != 16) {
+       if (spi->bits_per_word % 8) {
+               dev_err(&spi->dev, "%d bits_per_word is not supported\n",
+                               spi->bits_per_word);
                ret = -EINVAL;
                goto error;
        }

diff --git a/drivers/spi/spi-bfin5xx.c b/drivers/spi/spi-bfin5xx.c
index 3b83ff8..9bb4d4a 100644 (file)
--- a/drivers/spi/spi-bfin5xx.c
+++ b/drivers/spi/spi-bfin5xx.c
@@ -396,7 +396,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
                /* last read */
                if (drv_data->rx) {
                        dev_dbg(&drv_data->pdev->dev, "last read\n");
-                       if (n_bytes % 2) {
+                       if (!(n_bytes % 2)) {
                                u16 *buf = (u16 *)drv_data->rx;
                                for (loop = 0; loop < n_bytes / 2; loop++)
                                        *buf++ = bfin_read(&drv_data->regs->rdbr);
@@ -424,7 +424,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
        if (drv_data->rx && drv_data->tx) {
                /* duplex */
                dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
-               if (n_bytes % 2) {
+               if (!(n_bytes % 2)) {
                        u16 *buf = (u16 *)drv_data->rx;
                        u16 *buf2 = (u16 *)drv_data->tx;
                        for (loop = 0; loop < n_bytes / 2; loop++) {
@@ -442,7 +442,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
        } else if (drv_data->rx) {
                /* read */
                dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
-               if (n_bytes % 2) {
+               if (!(n_bytes % 2)) {
                        u16 *buf = (u16 *)drv_data->rx;
                        for (loop = 0; loop < n_bytes / 2; loop++) {
                                *buf++ = bfin_read(&drv_data->regs->rdbr);
@@ -458,7 +458,7 @@ static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
        } else if (drv_data->tx) {
                /* write */
                dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
-               if (n_bytes % 2) {
+               if (!(n_bytes % 2)) {
                        u16 *buf = (u16 *)drv_data->tx;
                        for (loop = 0; loop < n_bytes / 2; loop++) {
                                bfin_read(&drv_data->regs->rdbr);
@@ -587,6 +587,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
        if (message->state == DONE_STATE) {
                dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
                message->status = 0;
+               bfin_spi_flush(drv_data);
                bfin_spi_giveback(drv_data);
                return;
        }
@@ -870,8 +871,10 @@ static void bfin_spi_pump_transfers(unsigned long data)
                message->actual_length += drv_data->len_in_bytes;
                /* Move to next transfer of this msg */
                message->state = bfin_spi_next_transfer(drv_data);
-               if (drv_data->cs_change)
+               if (drv_data->cs_change && message->state != DONE_STATE) {
+                       bfin_spi_flush(drv_data);
                        bfin_spi_cs_deactive(drv_data, chip);
+               }
        }
 
        /* Schedule next transfer tasklet */
@@ -1026,7 +1029,6 @@ static int bfin_spi_setup(struct spi_device *spi)
                chip->cs_chg_udelay = chip_info->cs_chg_udelay;
                chip->idle_tx_val = chip_info->idle_tx_val;
                chip->pio_interrupt = chip_info->pio_interrupt;
-               spi->bits_per_word = chip_info->bits_per_word;
        } else {
                /* force a default base state */
                chip->ctl_reg &= bfin_ctl_reg;

diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index 6db2887..e805507 100644 (file)
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -545,13 +545,12 @@ static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
  * in case of failure.
  */
 static struct dma_async_tx_descriptor *
-ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
+ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
 {
        struct spi_transfer *t = espi->current_msg->state;
        struct dma_async_tx_descriptor *txd;
        enum dma_slave_buswidth buswidth;
        struct dma_slave_config conf;
-       enum dma_transfer_direction slave_dirn;
        struct scatterlist *sg;
        struct sg_table *sgt;
        struct dma_chan *chan;
@@ -567,14 +566,13 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
        memset(&conf, 0, sizeof(conf));
        conf.direction = dir;
 
-       if (dir == DMA_FROM_DEVICE) {
+       if (dir == DMA_DEV_TO_MEM) {
                chan = espi->dma_rx;
                buf = t->rx_buf;
                sgt = &espi->rx_sgt;
 
                conf.src_addr = espi->sspdr_phys;
                conf.src_addr_width = buswidth;
-               slave_dirn = DMA_DEV_TO_MEM;
        } else {
                chan = espi->dma_tx;
                buf = t->tx_buf;
@@ -582,7 +580,6 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
 
                conf.dst_addr = espi->sspdr_phys;
                conf.dst_addr_width = buswidth;
-               slave_dirn = DMA_MEM_TO_DEV;
        }
 
        ret = dmaengine_slave_config(chan, &conf);
@@ -633,8 +630,7 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
        if (!nents)
                return ERR_PTR(-ENOMEM);
 
-       txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents,
-                                       slave_dirn, DMA_CTRL_ACK);
+       txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK);
        if (!txd) {
                dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
                return ERR_PTR(-ENOMEM);
@@ -651,12 +647,12 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
  * unmapped.
  */
 static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
-                                 enum dma_data_direction dir)
+                                 enum dma_transfer_direction dir)
 {
        struct dma_chan *chan;
        struct sg_table *sgt;
 
-       if (dir == DMA_FROM_DEVICE) {
+       if (dir == DMA_DEV_TO_MEM) {
                chan = espi->dma_rx;
                sgt = &espi->rx_sgt;
        } else {
@@ -677,16 +673,16 @@ static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
        struct spi_message *msg = espi->current_msg;
        struct dma_async_tx_descriptor *rxd, *txd;
 
-       rxd = ep93xx_spi_dma_prepare(espi, DMA_FROM_DEVICE);
+       rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM);
        if (IS_ERR(rxd)) {
                dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
                msg->status = PTR_ERR(rxd);
                return;
        }
 
-       txd = ep93xx_spi_dma_prepare(espi, DMA_TO_DEVICE);
+       txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV);
        if (IS_ERR(txd)) {
-               ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE);
+               ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
                dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd));
                msg->status = PTR_ERR(txd);
                return;
@@ -705,8 +701,8 @@ static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
 
        wait_for_completion(&espi->wait);
 
-       ep93xx_spi_dma_finish(espi, DMA_TO_DEVICE);
-       ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE);
+       ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV);
+       ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
 }
 
 /**

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 570f220..47877d6 100644 (file)
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -37,6 +37,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <mach/spi.h>
 
@@ -85,7 +86,8 @@ struct spi_imx_data {
        struct completion xfer_done;
        void __iomem *base;
        int irq;
-       struct clk *clk;
+       struct clk *clk_per;
+       struct clk *clk_ipg;
        unsigned long spi_clk;
 
        unsigned int count;
@@ -758,6 +760,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
        struct spi_master *master;
        struct spi_imx_data *spi_imx;
        struct resource *res;
+       struct pinctrl *pinctrl;
        int i, ret, num_cs;
 
        if (!np && !mxc_platform_info) {
@@ -845,15 +848,28 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
                goto out_iounmap;
        }
 
-       spi_imx->clk = clk_get(&pdev->dev, NULL);
-       if (IS_ERR(spi_imx->clk)) {
-               dev_err(&pdev->dev, "unable to get clock\n");
-               ret = PTR_ERR(spi_imx->clk);
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
                goto out_free_irq;
        }
 
-       clk_enable(spi_imx->clk);
-       spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
+       spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+       if (IS_ERR(spi_imx->clk_ipg)) {
+               ret = PTR_ERR(spi_imx->clk_ipg);
+               goto out_free_irq;
+       }
+
+       spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
+       if (IS_ERR(spi_imx->clk_per)) {
+               ret = PTR_ERR(spi_imx->clk_per);
+               goto out_free_irq;
+       }
+
+       clk_prepare_enable(spi_imx->clk_per);
+       clk_prepare_enable(spi_imx->clk_ipg);
+
+       spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
 
        spi_imx->devtype_data->reset(spi_imx);
 
@@ -871,8 +887,8 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
        return ret;
 
 out_clk_put:
-       clk_disable(spi_imx->clk);
-       clk_put(spi_imx->clk);
+       clk_disable_unprepare(spi_imx->clk_per);
+       clk_disable_unprepare(spi_imx->clk_ipg);
 out_free_irq:
        free_irq(spi_imx->irq, spi_imx);
 out_iounmap:
@@ -900,8 +916,8 @@ static int __devexit spi_imx_remove(struct platform_device *pdev)
        spi_bitbang_stop(&spi_imx->bitbang);
 
        writel(0, spi_imx->base + MXC_CSPICTRL);
-       clk_disable(spi_imx->clk);
-       clk_put(spi_imx->clk);
+       clk_disable_unprepare(spi_imx->clk_per);
+       clk_disable_unprepare(spi_imx->clk_ipg);
        free_irq(spi_imx->irq, spi_imx);
        iounmap(spi_imx->base);
 

diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 09c925a..400ae21 100644 (file)
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -1667,9 +1667,15 @@ static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
        /* cpsdvsr = 254 & scr = 255 */
        min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
 
-       if (!((freq <= max_tclk) && (freq >= min_tclk))) {
+       if (freq > max_tclk)
+               dev_warn(&pl022->adev->dev,
+                       "Max speed that can be programmed is %d Hz, you requested %d\n",
+                       max_tclk, freq);
+
+       if (freq < min_tclk) {
                dev_err(&pl022->adev->dev,
-                       "controller data is incorrect: out of range frequency");
+                       "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
+                       freq, min_tclk);
                return -EINVAL;
        }
 
@@ -1681,26 +1687,37 @@ static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
                while (scr <= SCR_MAX) {
                        tmp = spi_rate(rate, cpsdvsr, scr);
 
-                       if (tmp > freq)
+                       if (tmp > freq) {
+                               /* we need lower freq */
                                scr++;
+                               continue;
+                       }
+
                        /*
-                        * If found exact value, update and break.
-                        * If found more closer value, update and continue.
+                        * If found exact value, mark found and break.
+                        * If found more closer value, update and break.
                         */
-                       else if ((tmp == freq) || (tmp > best_freq)) {
+                       if (tmp > best_freq) {
                                best_freq = tmp;
                                best_cpsdvsr = cpsdvsr;
                                best_scr = scr;
 
                                if (tmp == freq)
-                                       break;
+                                       found = 1;
                        }
-                       scr++;
+                       /*
+                        * increased scr will give lower rates, which are not
+                        * required
+                        */
+                       break;
                }
                cpsdvsr += 2;
                scr = SCR_MIN;
        }
 
+       WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
+                       freq);
+
        clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
        clk_freq->scr = (u8) (best_scr & 0xFF);
        dev_dbg(&pl022->adev->dev,
@@ -1823,9 +1840,12 @@ static int pl022_setup(struct spi_device *spi)
        } else
                chip->cs_control = chip_info->cs_control;
 
-       if (bits <= 3) {
-               /* PL022 doesn't support less than 4-bits */
+       /* Check bits per word with vendor specific range */
+       if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
                status = -ENOTSUPP;
+               dev_err(&spi->dev, "illegal data size for this controller!\n");
+               dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
+                               pl022->vendor->max_bpw);
                goto err_config_params;
        } else if (bits <= 8) {
                dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
@@ -1838,20 +1858,10 @@ static int pl022_setup(struct spi_device *spi)
                chip->read = READING_U16;
                chip->write = WRITING_U16;
        } else {
-               if (pl022->vendor->max_bpw >= 32) {
-                       dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
-                       chip->n_bytes = 4;
-                       chip->read = READING_U32;
-                       chip->write = WRITING_U32;
-               } else {
-                       dev_err(&spi->dev,
-                               "illegal data size for this controller!\n");
-                       dev_err(&spi->dev,
-                               "a standard pl022 can only handle "
-                               "1 <= n <= 16 bit words\n");
-                       status = -ENOTSUPP;
-                       goto err_config_params;
-               }
+               dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
+               chip->n_bytes = 4;
+               chip->read = READING_U32;
+               chip->write = WRITING_U32;
        }
 
        /* Now Initialize all register settings required for this chip */

diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c
index 400df8c..d91751f 100644 (file)
--- a/drivers/staging/octeon/ethernet-rx.c
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -36,6 +36,7 @@
 #include <linux/prefetch.h>
 #include <linux/ratelimit.h>
 #include <linux/smp.h>
+#include <linux/interrupt.h>
 #include <net/dst.h>
 #ifdef CONFIG_XFRM
 #include <linux/xfrm.h>

diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c
index 56d74dc..91a97b3 100644 (file)
--- a/drivers/staging/octeon/ethernet-tx.c
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -32,6 +32,7 @@
 #include <linux/ip.h>
 #include <linux/ratelimit.h>
 #include <linux/string.h>
+#include <linux/interrupt.h>
 #include <net/dst.h>
 #ifdef CONFIG_XFRM
 #include <linux/xfrm.h>

diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c
index 9112cd8..60cba81 100644 (file)
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -31,6 +31,7 @@
 #include <linux/etherdevice.h>
 #include <linux/phy.h>
 #include <linux/slab.h>
+#include <linux/interrupt.h>
 
 #include <net/dst.h>
 

diff --git a/drivers/staging/ozwpan/ozpd.c b/drivers/staging/ozwpan/ozpd.c
index 2b45d3d..04cd57f 100644 (file)
--- a/drivers/staging/ozwpan/ozpd.c
+++ b/drivers/staging/ozwpan/ozpd.c
@@ -383,8 +383,6 @@ static void oz_tx_frame_free(struct oz_pd *pd, struct oz_tx_frame *f)
                pd->tx_pool = &f->link;
                pd->tx_pool_count++;
                f = 0;
-       } else {
-               kfree(f);
        }
        spin_unlock_bh(&pd->tx_frame_lock);
        if (f)

diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c
index 7862513..9cf29fc 100644 (file)
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -79,10 +79,6 @@
 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
 
-#define OMAP343X_CTRL_REGADDR(reg) \
-       OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
-
-
 /* Forward Declarations: */
 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
@@ -418,19 +414,27 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
 
                /* Assert RST1 i.e only the RST only for DSP megacell */
                if (!status) {
+                       /*
+                        * XXX: ioremapping  MUST be removed once ctrl
+                        * function is made available.
+                        */
+                       void __iomem *ctrl = ioremap(OMAP343X_CTRL_BASE, SZ_4K);
+                       if (!ctrl)
+                               return -ENOMEM;
+
                        (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
                                        OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
                                        OMAP2_RM_RSTCTRL);
                        /* Mask address with 1K for compatibility */
                        __raw_writel(dsp_addr & OMAP3_IVA2_BOOTADDR_MASK,
-                                       OMAP343X_CTRL_REGADDR(
-                                       OMAP343X_CONTROL_IVA2_BOOTADDR));
+                                       ctrl + OMAP343X_CONTROL_IVA2_BOOTADDR);
                        /*
                         * Set bootmode to self loop if dsp_debug flag is true
                         */
                        __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
-                                       OMAP343X_CTRL_REGADDR(
-                                       OMAP343X_CONTROL_IVA2_BOOTMOD));
+                                       ctrl + OMAP343X_CONTROL_IVA2_BOOTMOD);
+
+                       iounmap(ctrl);
                }
        }
        if (!status) {

diff --git a/drivers/staging/tidspbridge/core/wdt.c b/drivers/staging/tidspbridge/core/wdt.c
index 70055c8..870f934 100644 (file)
--- a/drivers/staging/tidspbridge/core/wdt.c
+++ b/drivers/staging/tidspbridge/core/wdt.c
@@ -53,7 +53,10 @@ int dsp_wdt_init(void)
        int ret = 0;
 
        dsp_wdt.sm_wdt = NULL;
-       dsp_wdt.reg_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_WDT3_BASE);
+       dsp_wdt.reg_base = ioremap(OMAP34XX_WDT3_BASE, SZ_4K);
+       if (!dsp_wdt.reg_base)
+               return -ENOMEM;
+
        tasklet_init(&dsp_wdt.wdt3_tasklet, dsp_wdt_dpc, 0);
 
        dsp_wdt.fclk = clk_get(NULL, "wdt3_fck");
@@ -99,6 +102,9 @@ void dsp_wdt_exit(void)
        dsp_wdt.fclk = NULL;
        dsp_wdt.iclk = NULL;
        dsp_wdt.sm_wdt = NULL;
+
+       if (dsp_wdt.reg_base)
+               iounmap(dsp_wdt.reg_base);
        dsp_wdt.reg_base = NULL;
 }
 

diff --git a/drivers/staging/zcache/Kconfig b/drivers/staging/zcache/Kconfig
index 3ed2c8f..7048e01 100644 (file)
--- a/drivers/staging/zcache/Kconfig
+++ b/drivers/staging/zcache/Kconfig
@@ -2,7 +2,7 @@ config ZCACHE
        bool "Dynamic compression of swap pages and clean pagecache pages"
        # X86 dependency is because zsmalloc uses non-portable pte/tlb
        # functions
-       depends on (CLEANCACHE || FRONTSWAP) && CRYPTO && X86
+       depends on (CLEANCACHE || FRONTSWAP) && CRYPTO=y && X86
        select ZSMALLOC
        select CRYPTO_LZO
        default n

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 3d569cd..062ef8c 100644 (file)
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -52,6 +52,7 @@
 #include <linux/scatterlist.h>
 #include <linux/delay.h>
 #include <linux/types.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <asm/io.h>
 #include <asm/sizes.h>
@@ -1916,6 +1917,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
 {
        struct uart_amba_port *uap;
        struct vendor_data *vendor = id->data;
+       struct pinctrl *pinctrl;
        void __iomem *base;
        int i, ret;
 
@@ -1940,6 +1942,12 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
                goto free;
        }
 
+       pinctrl = devm_pinctrl_get_select_default(&dev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
+               goto unmap;
+       }
+
        uap->clk = clk_get(&dev->dev, NULL);
        if (IS_ERR(uap->clk)) {
                ret = PTR_ERR(uap->clk);

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index e7fecee..4ef7473 100644 (file)
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -47,6 +47,7 @@
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -204,7 +205,8 @@ struct imx_port {
        unsigned int            irda_inv_rx:1;
        unsigned int            irda_inv_tx:1;
        unsigned short          trcv_delay; /* transceiver delay */
-       struct clk              *clk;
+       struct clk              *clk_ipg;
+       struct clk              *clk_per;
        struct imx_uart_data    *devdata;
 };
 
@@ -672,7 +674,7 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
         * RFDIV is set such way to satisfy requested uartclk value
         */
        val = TXTL << 10 | RXTL;
-       ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
+       ufcr_rfdiv = (clk_get_rate(sport->clk_per) + sport->port.uartclk / 2)
                        / sport->port.uartclk;
 
        if(!ufcr_rfdiv)
@@ -1285,7 +1287,7 @@ imx_console_get_options(struct imx_port *sport, int *baud,
                else
                        ucfr_rfdiv = 6 - ucfr_rfdiv;
 
-               uartclk = clk_get_rate(sport->clk);
+               uartclk = clk_get_rate(sport->clk_per);
                uartclk /= ucfr_rfdiv;
 
                {       /*
@@ -1464,6 +1466,7 @@ static int serial_imx_probe(struct platform_device *pdev)
        void __iomem *base;
        int ret = 0;
        struct resource *res;
+       struct pinctrl *pinctrl;
 
        sport = kzalloc(sizeof(*sport), GFP_KERNEL);
        if (!sport)
@@ -1503,14 +1506,28 @@ static int serial_imx_probe(struct platform_device *pdev)
        sport->timer.function = imx_timeout;
        sport->timer.data     = (unsigned long)sport;
 
-       sport->clk = clk_get(&pdev->dev, "uart");
-       if (IS_ERR(sport->clk)) {
-               ret = PTR_ERR(sport->clk);
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
                goto unmap;
        }
-       clk_prepare_enable(sport->clk);
 
-       sport->port.uartclk = clk_get_rate(sport->clk);
+       sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+       if (IS_ERR(sport->clk_ipg)) {
+               ret = PTR_ERR(sport->clk_ipg);
+               goto unmap;
+       }
+
+       sport->clk_per = devm_clk_get(&pdev->dev, "per");
+       if (IS_ERR(sport->clk_per)) {
+               ret = PTR_ERR(sport->clk_per);
+               goto unmap;
+       }
+
+       clk_prepare_enable(sport->clk_per);
+       clk_prepare_enable(sport->clk_ipg);
+
+       sport->port.uartclk = clk_get_rate(sport->clk_per);
 
        imx_ports[sport->port.line] = sport;
 
@@ -1531,8 +1548,8 @@ deinit:
        if (pdata && pdata->exit)
                pdata->exit(pdev);
 clkput:
-       clk_disable_unprepare(sport->clk);
-       clk_put(sport->clk);
+       clk_disable_unprepare(sport->clk_per);
+       clk_disable_unprepare(sport->clk_ipg);
 unmap:
        iounmap(sport->port.membase);
 free:
@@ -1550,11 +1567,10 @@ static int serial_imx_remove(struct platform_device *pdev)
 
        platform_set_drvdata(pdev, NULL);
 
-       if (sport) {
-               uart_remove_one_port(&imx_reg, &sport->port);
-               clk_disable_unprepare(sport->clk);
-               clk_put(sport->clk);
-       }
+       uart_remove_one_port(&imx_reg, &sport->port);
+
+       clk_disable_unprepare(sport->clk_per);
+       clk_disable_unprepare(sport->clk_ipg);
 
        if (pdata && pdata->exit)
                pdata->exit(pdev);

diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 55fd362..7081600 100644 (file)
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -32,6 +32,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <asm/cacheflush.h>
 
@@ -678,6 +679,7 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev)
        u32 version;
        int ret = 0;
        struct resource *r;
+       struct pinctrl *pinctrl;
 
        s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
        if (!s) {
@@ -685,6 +687,12 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev)
                goto out;
        }
 
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
+               goto out_free;
+       }
+
        s->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(s->clk)) {
                ret = PTR_ERR(s->clk);

diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c
index 08ebe90..654755a 100644 (file)
--- a/drivers/tty/serial/pmac_zilog.c
+++ b/drivers/tty/serial/pmac_zilog.c
@@ -469,7 +469,7 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id)
        tty = NULL;
        if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
                if (!ZS_IS_OPEN(uap_a)) {
-                       pmz_debug("ChanA interrupt while open !\n");
+                       pmz_debug("ChanA interrupt while not open !\n");
                        goto skip_a;
                }
                write_zsreg(uap_a, R0, RES_H_IUS);
@@ -493,8 +493,8 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id)
        spin_lock(&uap_b->port.lock);
        tty = NULL;
        if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
-               if (!ZS_IS_OPEN(uap_a)) {
-                       pmz_debug("ChanB interrupt while open !\n");
+               if (!ZS_IS_OPEN(uap_b)) {
+                       pmz_debug("ChanB interrupt while not open !\n");
                        goto skip_b;
                }
                write_zsreg(uap_b, R0, RES_H_IUS);

diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c
index 86dd1e3..29ca20d 100644 (file)
--- a/drivers/tty/vt/keyboard.c
+++ b/drivers/tty/vt/keyboard.c
@@ -1085,15 +1085,21 @@ void vt_set_led_state(int console, int leds)
  *
  *     Handle console start. This is a wrapper for the VT layer
  *     so that we can keep kbd knowledge internal
+ *
+ *     FIXME: We eventually need to hold the kbd lock here to protect
+ *     the LED updating. We can't do it yet because fn_hold calls stop_tty
+ *     and start_tty under the kbd_event_lock, while normal tty paths
+ *     don't hold the lock. We probably need to split out an LED lock
+ *     but not during an -rc release!
  */
 void vt_kbd_con_start(int console)
 {
        struct kbd_struct * kbd = kbd_table + console;
-       unsigned long flags;
-       spin_lock_irqsave(&kbd_event_lock, flags);
+/*     unsigned long flags; */
+/*     spin_lock_irqsave(&kbd_event_lock, flags); */
        clr_vc_kbd_led(kbd, VC_SCROLLOCK);
        set_leds();
-       spin_unlock_irqrestore(&kbd_event_lock, flags);
+/*     spin_unlock_irqrestore(&kbd_event_lock, flags); */
 }
 
 /**
@@ -1102,22 +1108,28 @@ void vt_kbd_con_start(int console)
  *
  *     Handle console stop. This is a wrapper for the VT layer
  *     so that we can keep kbd knowledge internal
+ *
+ *     FIXME: We eventually need to hold the kbd lock here to protect
+ *     the LED updating. We can't do it yet because fn_hold calls stop_tty
+ *     and start_tty under the kbd_event_lock, while normal tty paths
+ *     don't hold the lock. We probably need to split out an LED lock
+ *     but not during an -rc release!
  */
 void vt_kbd_con_stop(int console)
 {
        struct kbd_struct * kbd = kbd_table + console;
-       unsigned long flags;
-       spin_lock_irqsave(&kbd_event_lock, flags);
+/*     unsigned long flags; */
+/*     spin_lock_irqsave(&kbd_event_lock, flags); */
        set_vc_kbd_led(kbd, VC_SCROLLOCK);
        set_leds();
-       spin_unlock_irqrestore(&kbd_event_lock, flags);
+/*     spin_unlock_irqrestore(&kbd_event_lock, flags); */
 }
 
 /*
  * This is the tasklet that updates LED state on all keyboards
  * attached to the box. The reason we use tasklet is that we
  * need to handle the scenario when keyboard handler is not
- * registered yet but we already getting updates form VT to
+ * registered yet but we already getting updates from the VT to
  * update led state.
  */
 static void kbd_bh(unsigned long dummy)

diff --git a/drivers/usb/class/cdc-wdm.c b/drivers/usb/class/cdc-wdm.c
index c6f6560..0bb2b32 100644 (file)
--- a/drivers/usb/class/cdc-wdm.c
+++ b/drivers/usb/class/cdc-wdm.c
@@ -157,8 +157,9 @@ static void wdm_out_callback(struct urb *urb)
        spin_lock(&desc->iuspin);
        desc->werr = urb->status;
        spin_unlock(&desc->iuspin);
-       clear_bit(WDM_IN_USE, &desc->flags);
        kfree(desc->outbuf);
+       desc->outbuf = NULL;
+       clear_bit(WDM_IN_USE, &desc->flags);
        wake_up(&desc->wait);
 }
 
@@ -338,7 +339,7 @@ static ssize_t wdm_write
        if (we < 0)
                return -EIO;
 
-       desc->outbuf = buf = kmalloc(count, GFP_KERNEL);
+       buf = kmalloc(count, GFP_KERNEL);
        if (!buf) {
                rv = -ENOMEM;
                goto outnl;
@@ -406,10 +407,12 @@ static ssize_t wdm_write
        req->wIndex = desc->inum;
        req->wLength = cpu_to_le16(count);
        set_bit(WDM_IN_USE, &desc->flags);
+       desc->outbuf = buf;
 
        rv = usb_submit_urb(desc->command, GFP_KERNEL);
        if (rv < 0) {
                kfree(buf);
+               desc->outbuf = NULL;
                clear_bit(WDM_IN_USE, &desc->flags);
                dev_err(&desc->intf->dev, "Tx URB error: %d\n", rv);
        } else {

diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c
index 622b4a4..57ed9e4 100644 (file)
--- a/drivers/usb/core/hcd-pci.c
+++ b/drivers/usb/core/hcd-pci.c
@@ -493,6 +493,15 @@ static int hcd_pci_suspend_noirq(struct device *dev)
 
        pci_save_state(pci_dev);
 
+       /*
+        * Some systems crash if an EHCI controller is in D3 during
+        * a sleep transition.  We have to leave such controllers in D0.
+        */
+       if (hcd->broken_pci_sleep) {
+               dev_dbg(dev, "Staying in PCI D0\n");
+               return retval;
+       }
+
        /* If the root hub is dead rather than suspended, disallow remote
         * wakeup.  usb_hc_died() should ensure that both hosts are marked as
         * dying, so we only need to check the primary roothub.

diff --git a/drivers/usb/gadget/dummy_hcd.c b/drivers/usb/gadget/dummy_hcd.c
index a6dfd21..170cbe8 100644 (file)
--- a/drivers/usb/gadget/dummy_hcd.c
+++ b/drivers/usb/gadget/dummy_hcd.c
@@ -927,7 +927,6 @@ static int dummy_udc_stop(struct usb_gadget *g,
 
        dum->driver = NULL;
 
-       dummy_pullup(&dum->gadget, 0);
        return 0;
 }
 

diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index a371e96..cb8c162 100644 (file)
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -2189,7 +2189,7 @@ unknown_cmnd:
                common->data_size_from_cmnd = 0;
                sprintf(unknown, "Unknown x%02x", common->cmnd[0]);
                reply = check_command(common, common->cmnd_size,
-                                     DATA_DIR_UNKNOWN, 0xff, 0, unknown);
+                                     DATA_DIR_UNKNOWN, ~0, 0, unknown);
                if (reply == 0) {
                        common->curlun->sense_data = SS_INVALID_COMMAND;
                        reply = -EINVAL;

diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index 4fac569..a896d73 100644 (file)
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -2579,7 +2579,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
                fsg->data_size_from_cmnd = 0;
                sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
                if ((reply = check_command(fsg, fsg->cmnd_size,
-                               DATA_DIR_UNKNOWN, 0xff, 0, unknown)) == 0) {
+                               DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
                        fsg->curlun->sense_data = SS_INVALID_COMMAND;
                        reply = -EINVAL;
                }

diff --git a/drivers/usb/gadget/udc-core.c b/drivers/usb/gadget/udc-core.c
index 2fa9865..e5e44f8 100644 (file)
--- a/drivers/usb/gadget/udc-core.c
+++ b/drivers/usb/gadget/udc-core.c
@@ -263,8 +263,8 @@ static void usb_gadget_remove_driver(struct usb_udc *udc)
 
        if (udc_is_newstyle(udc)) {
                udc->driver->disconnect(udc->gadget);
-               udc->driver->unbind(udc->gadget);
                usb_gadget_disconnect(udc->gadget);
+               udc->driver->unbind(udc->gadget);
                usb_gadget_udc_stop(udc->gadget, udc->driver);
        } else {
                usb_gadget_stop(udc->gadget, udc->driver);
@@ -415,9 +415,9 @@ static ssize_t usb_udc_softconn_store(struct device *dev,
                        usb_gadget_udc_start(udc->gadget, udc->driver);
                usb_gadget_connect(udc->gadget);
        } else if (sysfs_streq(buf, "disconnect")) {
+               usb_gadget_disconnect(udc->gadget);
                if (udc_is_newstyle(udc))
                        usb_gadget_udc_stop(udc->gadget, udc->driver);
-               usb_gadget_disconnect(udc->gadget);
        } else {
                dev_err(dev, "unsupported command '%s'\n", buf);
                return -EINVAL;

diff --git a/drivers/usb/gadget/uvc.h b/drivers/usb/gadget/uvc.h
index bc78c60..ca4e03a 100644 (file)
--- a/drivers/usb/gadget/uvc.h
+++ b/drivers/usb/gadget/uvc.h
@@ -28,7 +28,7 @@
 
 struct uvc_request_data
 {
-       unsigned int length;
+       __s32 length;
        __u8 data[60];
 };
 

diff --git a/drivers/usb/gadget/uvc_v4l2.c b/drivers/usb/gadget/uvc_v4l2.c
index f6e083b..54d7ca5 100644 (file)
--- a/drivers/usb/gadget/uvc_v4l2.c
+++ b/drivers/usb/gadget/uvc_v4l2.c
@@ -39,7 +39,7 @@ uvc_send_response(struct uvc_device *uvc, struct uvc_request_data *data)
        if (data->length < 0)
                return usb_ep_set_halt(cdev->gadget->ep0);
 
-       req->length = min(uvc->event_length, data->length);
+       req->length = min_t(unsigned int, uvc->event_length, data->length);
        req->zero = data->length < uvc->event_length;
        req->dma = DMA_ADDR_INVALID;
 

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a797d51..c778ffe 100644 (file)
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -32,7 +32,7 @@
 #define ULPI_VIEWPORT_OFFSET   0x170
 
 struct ehci_mxc_priv {
-       struct clk *usbclk, *ahbclk, *phy1clk;
+       struct clk *usbclk, *ahbclk, *phyclk;
        struct usb_hcd *hcd;
 };
 
@@ -166,31 +166,26 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
        }
 
        /* enable clocks */
-       priv->usbclk = clk_get(dev, "usb");
+       priv->usbclk = clk_get(dev, "ipg");
        if (IS_ERR(priv->usbclk)) {
                ret = PTR_ERR(priv->usbclk);
                goto err_clk;
        }
-       clk_enable(priv->usbclk);
+       clk_prepare_enable(priv->usbclk);
 
-       if (!cpu_is_mx35() && !cpu_is_mx25()) {
-               priv->ahbclk = clk_get(dev, "usb_ahb");
-               if (IS_ERR(priv->ahbclk)) {
-                       ret = PTR_ERR(priv->ahbclk);
-                       goto err_clk_ahb;
-               }
-               clk_enable(priv->ahbclk);
+       priv->ahbclk = clk_get(dev, "ahb");
+       if (IS_ERR(priv->ahbclk)) {
+               ret = PTR_ERR(priv->ahbclk);
+               goto err_clk_ahb;
        }
+       clk_prepare_enable(priv->ahbclk);
 
        /* "dr" device has its own clock on i.MX51 */
-       if (cpu_is_mx51() && (pdev->id == 0)) {
-               priv->phy1clk = clk_get(dev, "usb_phy1");
-               if (IS_ERR(priv->phy1clk)) {
-                       ret = PTR_ERR(priv->phy1clk);
-                       goto err_clk_phy;
-               }
-               clk_enable(priv->phy1clk);
-       }
+       priv->phyclk = clk_get(dev, "phy");
+       if (IS_ERR(priv->phyclk))
+               priv->phyclk = NULL;
+       if (priv->phyclk)
+               clk_prepare_enable(priv->phyclk);
 
 
        /* call platform specific init function */
@@ -265,17 +260,15 @@ err_add:
        if (pdata && pdata->exit)
                pdata->exit(pdev);
 err_init:
-       if (priv->phy1clk) {
-               clk_disable(priv->phy1clk);
-               clk_put(priv->phy1clk);
-       }
-err_clk_phy:
-       if (priv->ahbclk) {
-               clk_disable(priv->ahbclk);
-               clk_put(priv->ahbclk);
+       if (priv->phyclk) {
+               clk_disable_unprepare(priv->phyclk);
+               clk_put(priv->phyclk);
        }
+
+       clk_disable_unprepare(priv->ahbclk);
+       clk_put(priv->ahbclk);
 err_clk_ahb:
-       clk_disable(priv->usbclk);
+       clk_disable_unprepare(priv->usbclk);
        clk_put(priv->usbclk);
 err_clk:
        iounmap(hcd->regs);
@@ -307,15 +300,14 @@ static int __exit ehci_mxc_drv_remove(struct platform_device *pdev)
        usb_put_hcd(hcd);
        platform_set_drvdata(pdev, NULL);
 
-       clk_disable(priv->usbclk);
+       clk_disable_unprepare(priv->usbclk);
        clk_put(priv->usbclk);
-       if (priv->ahbclk) {
-               clk_disable(priv->ahbclk);
-               clk_put(priv->ahbclk);
-       }
-       if (priv->phy1clk) {
-               clk_disable(priv->phy1clk);
-               clk_put(priv->phy1clk);
+       clk_disable_unprepare(priv->ahbclk);
+       clk_put(priv->ahbclk);
+
+       if (priv->phyclk) {
+               clk_disable_unprepare(priv->phyclk);
+               clk_put(priv->phyclk);
        }
 
        kfree(priv);

diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 01bb724..fe8dc06 100644 (file)
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -144,6 +144,14 @@ static int ehci_pci_setup(struct usb_hcd *hcd)
                        hcd->has_tt = 1;
                        tdi_reset(ehci);
                }
+               if (pdev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK) {
+                       /* EHCI #1 or #2 on 6 Series/C200 Series chipset */
+                       if (pdev->device == 0x1c26 || pdev->device == 0x1c2d) {
+                               ehci_info(ehci, "broken D3 during system sleep on ASUS\n");
+                               hcd->broken_pci_sleep = 1;
+                               device_set_wakeup_capable(&pdev->dev, false);
+                       }
+               }
                break;
        case PCI_VENDOR_ID_TDI:
                if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {

diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 8618336..f214a80 100644 (file)
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -24,6 +24,7 @@
 #include <linux/gpio.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
+#include <linux/pm_runtime.h>
 
 #include <mach/usb_phy.h>
 #include <mach/iomap.h>
@@ -37,9 +38,7 @@ struct tegra_ehci_hcd {
        struct clk *emc_clk;
        struct usb_phy *transceiver;
        int host_resumed;
-       int bus_suspended;
        int port_resuming;
-       int power_down_on_bus_suspend;
        enum tegra_usb_phy_port_speed port_speed;
 };
 
@@ -273,120 +272,6 @@ static void tegra_ehci_restart(struct usb_hcd *hcd)
        up_write(&ehci_cf_port_reset_rwsem);
 }
 
-static int tegra_usb_suspend(struct usb_hcd *hcd)
-{
-       struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
-       struct ehci_regs __iomem *hw = tegra->ehci->regs;
-       unsigned long flags;
-
-       spin_lock_irqsave(&tegra->ehci->lock, flags);
-
-       tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
-       ehci_halt(tegra->ehci);
-       clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
-
-       spin_unlock_irqrestore(&tegra->ehci->lock, flags);
-
-       tegra_ehci_power_down(hcd);
-       return 0;
-}
-
-static int tegra_usb_resume(struct usb_hcd *hcd)
-{
-       struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
-       struct ehci_hcd *ehci = hcd_to_ehci(hcd);
-       struct ehci_regs __iomem *hw = ehci->regs;
-       unsigned long val;
-
-       set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
-       tegra_ehci_power_up(hcd);
-
-       if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
-               /* Wait for the phy to detect new devices
-                * before we restart the controller */
-               msleep(10);
-               goto restart;
-       }
-
-       /* Force the phy to keep data lines in suspend state */
-       tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
-
-       /* Enable host mode */
-       tdi_reset(ehci);
-
-       /* Enable Port Power */
-       val = readl(&hw->port_status[0]);
-       val |= PORT_POWER;
-       writel(val, &hw->port_status[0]);
-       udelay(10);
-
-       /* Check if the phy resume from LP0. When the phy resume from LP0
-        * USB register will be reset. */
-       if (!readl(&hw->async_next)) {
-               /* Program the field PTC based on the saved speed mode */
-               val = readl(&hw->port_status[0]);
-               val &= ~PORT_TEST(~0);
-               if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
-                       val |= PORT_TEST_FORCE;
-               else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
-                       val |= PORT_TEST(6);
-               else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
-                       val |= PORT_TEST(7);
-               writel(val, &hw->port_status[0]);
-               udelay(10);
-
-               /* Disable test mode by setting PTC field to NORMAL_OP */
-               val = readl(&hw->port_status[0]);
-               val &= ~PORT_TEST(~0);
-               writel(val, &hw->port_status[0]);
-               udelay(10);
-       }
-
-       /* Poll until CCS is enabled */
-       if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
-                                                PORT_CONNECT, 2000)) {
-               pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
-               goto restart;
-       }
-
-       /* Poll until PE is enabled */
-       if (handshake(ehci, &hw->port_status[0], PORT_PE,
-                                                PORT_PE, 2000)) {
-               pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
-               goto restart;
-       }
-
-       /* Clear the PCI status, to avoid an interrupt taken upon resume */
-       val = readl(&hw->status);
-       val |= STS_PCD;
-       writel(val, &hw->status);
-
-       /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
-       val = readl(&hw->port_status[0]);
-       if ((val & PORT_POWER) && (val & PORT_PE)) {
-               val |= PORT_SUSPEND;
-               writel(val, &hw->port_status[0]);
-
-               /* Wait until port suspend completes */
-               if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
-                                                        PORT_SUSPEND, 1000)) {
-                       pr_err("%s: timeout waiting for PORT_SUSPEND\n",
-                                                               __func__);
-                       goto restart;
-               }
-       }
-
-       tegra_ehci_phy_restore_end(tegra->phy);
-       return 0;
-
-restart:
-       if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
-               tegra_ehci_phy_restore_end(tegra->phy);
-
-       tegra_ehci_restart(hcd);
-       return 0;
-}
-
 static void tegra_ehci_shutdown(struct usb_hcd *hcd)
 {
        struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
@@ -434,36 +319,6 @@ static int tegra_ehci_setup(struct usb_hcd *hcd)
        return retval;
 }
 
-#ifdef CONFIG_PM
-static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
-{
-       struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
-       int error_status = 0;
-
-       error_status = ehci_bus_suspend(hcd);
-       if (!error_status && tegra->power_down_on_bus_suspend) {
-               tegra_usb_suspend(hcd);
-               tegra->bus_suspended = 1;
-       }
-
-       return error_status;
-}
-
-static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
-{
-       struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
-
-       if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
-               tegra_usb_resume(hcd);
-               tegra->bus_suspended = 0;
-       }
-
-       tegra_usb_phy_preresume(tegra->phy);
-       tegra->port_resuming = 1;
-       return ehci_bus_resume(hcd);
-}
-#endif
-
 struct temp_buffer {
        void *kmalloc_ptr;
        void *old_xfer_buffer;
@@ -574,8 +429,8 @@ static const struct hc_driver tegra_ehci_hc_driver = {
        .hub_control            = tegra_ehci_hub_control,
        .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
 #ifdef CONFIG_PM
-       .bus_suspend            = tegra_ehci_bus_suspend,
-       .bus_resume             = tegra_ehci_bus_resume,
+       .bus_suspend            = ehci_bus_suspend,
+       .bus_resume             = ehci_bus_resume,
 #endif
        .relinquish_port        = ehci_relinquish_port,
        .port_handed_over       = ehci_port_handed_over,
@@ -603,11 +458,187 @@ static int setup_vbus_gpio(struct platform_device *pdev)
                dev_err(&pdev->dev, "can't enable vbus\n");
                return err;
        }
-       gpio_set_value(gpio, 1);
 
        return err;
 }
 
+#ifdef CONFIG_PM
+
+static int controller_suspend(struct device *dev)
+{
+       struct tegra_ehci_hcd *tegra =
+                       platform_get_drvdata(to_platform_device(dev));
+       struct ehci_hcd *ehci = tegra->ehci;
+       struct usb_hcd *hcd = ehci_to_hcd(ehci);
+       struct ehci_regs __iomem *hw = ehci->regs;
+       unsigned long flags;
+
+       if (time_before(jiffies, ehci->next_statechange))
+               msleep(10);
+
+       spin_lock_irqsave(&ehci->lock, flags);
+
+       tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
+       ehci_halt(ehci);
+       clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+       spin_unlock_irqrestore(&ehci->lock, flags);
+
+       tegra_ehci_power_down(hcd);
+       return 0;
+}
+
+static int controller_resume(struct device *dev)
+{
+       struct tegra_ehci_hcd *tegra =
+                       platform_get_drvdata(to_platform_device(dev));
+       struct ehci_hcd *ehci = tegra->ehci;
+       struct usb_hcd *hcd = ehci_to_hcd(ehci);
+       struct ehci_regs __iomem *hw = ehci->regs;
+       unsigned long val;
+
+       set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+       tegra_ehci_power_up(hcd);
+
+       if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
+               /* Wait for the phy to detect new devices
+                * before we restart the controller */
+               msleep(10);
+               goto restart;
+       }
+
+       /* Force the phy to keep data lines in suspend state */
+       tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
+
+       /* Enable host mode */
+       tdi_reset(ehci);
+
+       /* Enable Port Power */
+       val = readl(&hw->port_status[0]);
+       val |= PORT_POWER;
+       writel(val, &hw->port_status[0]);
+       udelay(10);
+
+       /* Check if the phy resume from LP0. When the phy resume from LP0
+        * USB register will be reset. */
+       if (!readl(&hw->async_next)) {
+               /* Program the field PTC based on the saved speed mode */
+               val = readl(&hw->port_status[0]);
+               val &= ~PORT_TEST(~0);
+               if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
+                       val |= PORT_TEST_FORCE;
+               else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
+                       val |= PORT_TEST(6);
+               else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
+                       val |= PORT_TEST(7);
+               writel(val, &hw->port_status[0]);
+               udelay(10);
+
+               /* Disable test mode by setting PTC field to NORMAL_OP */
+               val = readl(&hw->port_status[0]);
+               val &= ~PORT_TEST(~0);
+               writel(val, &hw->port_status[0]);
+               udelay(10);
+       }
+
+       /* Poll until CCS is enabled */
+       if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
+                                                PORT_CONNECT, 2000)) {
+               pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
+               goto restart;
+       }
+
+       /* Poll until PE is enabled */
+       if (handshake(ehci, &hw->port_status[0], PORT_PE,
+                                                PORT_PE, 2000)) {
+               pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
+               goto restart;
+       }
+
+       /* Clear the PCI status, to avoid an interrupt taken upon resume */
+       val = readl(&hw->status);
+       val |= STS_PCD;
+       writel(val, &hw->status);
+
+       /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
+       val = readl(&hw->port_status[0]);
+       if ((val & PORT_POWER) && (val & PORT_PE)) {
+               val |= PORT_SUSPEND;
+               writel(val, &hw->port_status[0]);
+
+               /* Wait until port suspend completes */
+               if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
+                                                        PORT_SUSPEND, 1000)) {
+                       pr_err("%s: timeout waiting for PORT_SUSPEND\n",
+                                                               __func__);
+                       goto restart;
+               }
+       }
+
+       tegra_ehci_phy_restore_end(tegra->phy);
+       goto done;
+
+ restart:
+       if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
+               tegra_ehci_phy_restore_end(tegra->phy);
+
+       tegra_ehci_restart(hcd);
+
+ done:
+       tegra_usb_phy_preresume(tegra->phy);
+       tegra->port_resuming = 1;
+       return 0;
+}
+
+static int tegra_ehci_suspend(struct device *dev)
+{
+       struct tegra_ehci_hcd *tegra =
+                       platform_get_drvdata(to_platform_device(dev));
+       struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
+       int rc = 0;
+
+       /*
+        * When system sleep is supported and USB controller wakeup is
+        * implemented: If the controller is runtime-suspended and the
+        * wakeup setting needs to be changed, call pm_runtime_resume().
+        */
+       if (HCD_HW_ACCESSIBLE(hcd))
+               rc = controller_suspend(dev);
+       return rc;
+}
+
+static int tegra_ehci_resume(struct device *dev)
+{
+       int rc;
+
+       rc = controller_resume(dev);
+       if (rc == 0) {
+               pm_runtime_disable(dev);
+               pm_runtime_set_active(dev);
+               pm_runtime_enable(dev);
+       }
+       return rc;
+}
+
+static int tegra_ehci_runtime_suspend(struct device *dev)
+{
+       return controller_suspend(dev);
+}
+
+static int tegra_ehci_runtime_resume(struct device *dev)
+{
+       return controller_resume(dev);
+}
+
+static const struct dev_pm_ops tegra_ehci_pm_ops = {
+       .suspend        = tegra_ehci_suspend,
+       .resume         = tegra_ehci_resume,
+       .runtime_suspend = tegra_ehci_runtime_suspend,
+       .runtime_resume = tegra_ehci_runtime_resume,
+};
+
+#endif
+
 static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
 
 static int tegra_ehci_probe(struct platform_device *pdev)
@@ -722,7 +753,6 @@ static int tegra_ehci_probe(struct platform_device *pdev)
        }
 
        tegra->host_resumed = 1;
-       tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
        tegra->ehci = hcd_to_ehci(hcd);
 
        irq = platform_get_irq(pdev, 0);
@@ -746,6 +776,14 @@ static int tegra_ehci_probe(struct platform_device *pdev)
                goto fail;
        }
 
+       pm_runtime_set_active(&pdev->dev);
+       pm_runtime_get_noresume(&pdev->dev);
+
+       /* Don't skip the pm_runtime_forbid call if wakeup isn't working */
+       /* if (!pdata->power_down_on_bus_suspend) */
+               pm_runtime_forbid(&pdev->dev);
+       pm_runtime_enable(&pdev->dev);
+       pm_runtime_put_sync(&pdev->dev);
        return err;
 
 fail:
@@ -772,33 +810,6 @@ fail_hcd:
        return err;
 }
 
-#ifdef CONFIG_PM
-static int tegra_ehci_resume(struct platform_device *pdev)
-{
-       struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
-       struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
-
-       if (tegra->bus_suspended)
-               return 0;
-
-       return tegra_usb_resume(hcd);
-}
-
-static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
-{
-       struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
-       struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
-
-       if (tegra->bus_suspended)
-               return 0;
-
-       if (time_before(jiffies, tegra->ehci->next_statechange))
-               msleep(10);
-
-       return tegra_usb_suspend(hcd);
-}
-#endif
-
 static int tegra_ehci_remove(struct platform_device *pdev)
 {
        struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
@@ -807,6 +818,10 @@ static int tegra_ehci_remove(struct platform_device *pdev)
        if (tegra == NULL || hcd == NULL)
                return -EINVAL;
 
+       pm_runtime_get_sync(&pdev->dev);
+       pm_runtime_disable(&pdev->dev);
+       pm_runtime_put_noidle(&pdev->dev);
+
 #ifdef CONFIG_USB_OTG_UTILS
        if (tegra->transceiver) {
                otg_set_host(tegra->transceiver->otg, NULL);
@@ -847,13 +862,12 @@ static struct of_device_id tegra_ehci_of_match[] __devinitdata = {
 static struct platform_driver tegra_ehci_driver = {
        .probe          = tegra_ehci_probe,
        .remove         = tegra_ehci_remove,
-#ifdef CONFIG_PM
-       .suspend        = tegra_ehci_suspend,
-       .resume         = tegra_ehci_resume,
-#endif
        .shutdown       = tegra_ehci_hcd_shutdown,
        .driver         = {
                .name   = "tegra-ehci",
                .of_match_table = tegra_ehci_of_match,
+#ifdef CONFIG_PM
+               .pm     = &tegra_ehci_pm_ops,
+#endif
        }
 };

diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 97ab975..768b4b5 100644 (file)
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -386,7 +386,7 @@ static int davinci_musb_init(struct musb *musb)
        usb_nop_xceiv_register();
        musb->xceiv = usb_get_transceiver();
        if (!musb->xceiv)
-               return -ENODEV;
+               goto unregister;
 
        musb->mregs += DAVINCI_BASE_OFFSET;
 
@@ -444,6 +444,7 @@ static int davinci_musb_init(struct musb *musb)
 
 fail:
        usb_put_transceiver(musb->xceiv);
+unregister:
        usb_nop_xceiv_unregister();
        return -ENODEV;
 }

diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 93de517..f4a40f0 100644 (file)
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -449,7 +449,7 @@ struct musb {
         * We added this flag to forcefully disable double
         * buffering until we get it working.
         */
-       unsigned                double_buffer_not_ok:1 __deprecated;
+       unsigned                double_buffer_not_ok:1;
 
        struct musb_hdrc_config *config;
 

diff --git a/drivers/usb/otg/gpio_vbus.c b/drivers/usb/otg/gpio_vbus.c
index 3ece43a..a0a2178 100644 (file)
--- a/drivers/usb/otg/gpio_vbus.c
+++ b/drivers/usb/otg/gpio_vbus.c
@@ -96,7 +96,7 @@ static void gpio_vbus_work(struct work_struct *work)
        struct gpio_vbus_data *gpio_vbus =
                container_of(work, struct gpio_vbus_data, work);
        struct gpio_vbus_mach_info *pdata = gpio_vbus->dev->platform_data;
-       int gpio;
+       int gpio, status;
 
        if (!gpio_vbus->phy.otg->gadget)
                return;
@@ -108,7 +108,9 @@ static void gpio_vbus_work(struct work_struct *work)
         */
        gpio = pdata->gpio_pullup;
        if (is_vbus_powered(pdata)) {
+               status = USB_EVENT_VBUS;
                gpio_vbus->phy.state = OTG_STATE_B_PERIPHERAL;
+               gpio_vbus->phy.last_event = status;
                usb_gadget_vbus_connect(gpio_vbus->phy.otg->gadget);
 
                /* drawing a "unit load" is *always* OK, except for OTG */
@@ -117,6 +119,9 @@ static void gpio_vbus_work(struct work_struct *work)
                /* optionally enable D+ pullup */
                if (gpio_is_valid(gpio))
                        gpio_set_value(gpio, !pdata->gpio_pullup_inverted);
+
+               atomic_notifier_call_chain(&gpio_vbus->phy.notifier,
+                                          status, gpio_vbus->phy.otg->gadget);
        } else {
                /* optionally disable D+ pullup */
                if (gpio_is_valid(gpio))
@@ -125,7 +130,12 @@ static void gpio_vbus_work(struct work_struct *work)
                set_vbus_draw(gpio_vbus, 0);
 
                usb_gadget_vbus_disconnect(gpio_vbus->phy.otg->gadget);
+               status = USB_EVENT_NONE;
                gpio_vbus->phy.state = OTG_STATE_B_IDLE;
+               gpio_vbus->phy.last_event = status;
+
+               atomic_notifier_call_chain(&gpio_vbus->phy.notifier,
+                                          status, gpio_vbus->phy.otg->gadget);
        }
 }
 
@@ -287,6 +297,9 @@ static int __init gpio_vbus_probe(struct platform_device *pdev)
                        irq, err);
                goto err_irq;
        }
+
+       ATOMIC_INIT_NOTIFIER_HEAD(&gpio_vbus->phy.notifier);
+
        INIT_WORK(&gpio_vbus->work, gpio_vbus_work);
 
        gpio_vbus->vbus_draw = regulator_get(&pdev->dev, "vbus_draw");

diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c
index f0da2c3..1f21d2a 100644 (file)
--- a/drivers/vhost/net.c
+++ b/drivers/vhost/net.c
@@ -238,7 +238,7 @@ static void handle_tx(struct vhost_net *net)
 
                                vq->heads[vq->upend_idx].len = len;
                                ubuf->callback = vhost_zerocopy_callback;
-                               ubuf->arg = vq->ubufs;
+                               ubuf->ctx = vq->ubufs;
                                ubuf->desc = vq->upend_idx;
                                msg.msg_control = ubuf;
                                msg.msg_controllen = sizeof(ubuf);

diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 947f00d..51e4c1e 100644 (file)
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -1598,10 +1598,9 @@ void vhost_ubuf_put_and_wait(struct vhost_ubuf_ref *ubufs)
        kfree(ubufs);
 }
 
-void vhost_zerocopy_callback(void *arg)
+void vhost_zerocopy_callback(struct ubuf_info *ubuf)
 {
-       struct ubuf_info *ubuf = arg;
-       struct vhost_ubuf_ref *ubufs = ubuf->arg;
+       struct vhost_ubuf_ref *ubufs = ubuf->ctx;
        struct vhost_virtqueue *vq = ubufs->vq;
 
        /* set len = 1 to mark this desc buffers done DMA */

diff --git a/drivers/vhost/vhost.h b/drivers/vhost/vhost.h
index 8dcf4cc..8de1fd5 100644 (file)
--- a/drivers/vhost/vhost.h
+++ b/drivers/vhost/vhost.h
@@ -188,7 +188,7 @@ bool vhost_enable_notify(struct vhost_dev *, struct vhost_virtqueue *);
 
 int vhost_log_write(struct vhost_virtqueue *vq, struct vhost_log *log,
                    unsigned int log_num, u64 len);
-void vhost_zerocopy_callback(void *arg);
+void vhost_zerocopy_callback(struct ubuf_info *);
 int vhost_zerocopy_signal_used(struct vhost_virtqueue *vq);
 
 #define vq_err(vq, fmt, ...) do {                                  \

diff --git a/drivers/video/bfin-lq035q1-fb.c b/drivers/video/bfin-lq035q1-fb.c
index 86922ac..353c02f 100644 (file)
--- a/drivers/video/bfin-lq035q1-fb.c
+++ b/drivers/video/bfin-lq035q1-fb.c
@@ -13,6 +13,7 @@
 #include <linux/errno.h>
 #include <linux/string.h>
 #include <linux/fb.h>
+#include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/types.h>

diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index f135dbe..caad368 100644 (file)
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -131,7 +131,9 @@ struct imxfb_rgb {
 struct imxfb_info {
        struct platform_device  *pdev;
        void __iomem            *regs;
-       struct clk              *clk;
+       struct clk              *clk_ipg;
+       struct clk              *clk_ahb;
+       struct clk              *clk_per;
 
        /*
         * These are the addresses we mapped
@@ -340,7 +342,7 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 
        pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
 
-       lcd_clk = clk_get_rate(fbi->clk);
+       lcd_clk = clk_get_rate(fbi->clk_per);
 
        tmp = var->pixclock * (unsigned long long)lcd_clk;
 
@@ -455,11 +457,17 @@ static int imxfb_bl_update_status(struct backlight_device *bl)
 
        fbi->pwmr = (fbi->pwmr & ~0xFF) | brightness;
 
-       if (bl->props.fb_blank != FB_BLANK_UNBLANK)
-               clk_enable(fbi->clk);
+       if (bl->props.fb_blank != FB_BLANK_UNBLANK) {
+               clk_prepare_enable(fbi->clk_ipg);
+               clk_prepare_enable(fbi->clk_ahb);
+               clk_prepare_enable(fbi->clk_per);
+       }
        writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
-       if (bl->props.fb_blank != FB_BLANK_UNBLANK)
-               clk_disable(fbi->clk);
+       if (bl->props.fb_blank != FB_BLANK_UNBLANK) {
+               clk_disable_unprepare(fbi->clk_per);
+               clk_disable_unprepare(fbi->clk_ahb);
+               clk_disable_unprepare(fbi->clk_ipg);
+       }
 
        return 0;
 }
@@ -522,7 +530,9 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
         */
        writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR);
 
-       clk_enable(fbi->clk);
+       clk_prepare_enable(fbi->clk_ipg);
+       clk_prepare_enable(fbi->clk_ahb);
+       clk_prepare_enable(fbi->clk_per);
 
        if (fbi->backlight_power)
                fbi->backlight_power(1);
@@ -539,7 +549,9 @@ static void imxfb_disable_controller(struct imxfb_info *fbi)
        if (fbi->lcd_power)
                fbi->lcd_power(0);
 
-       clk_disable(fbi->clk);
+       clk_disable_unprepare(fbi->clk_per);
+       clk_disable_unprepare(fbi->clk_ipg);
+       clk_disable_unprepare(fbi->clk_ahb);
 
        writel(0, fbi->regs + LCDC_RMCR);
 }
@@ -770,10 +782,21 @@ static int __init imxfb_probe(struct platform_device *pdev)
                goto failed_req;
        }
 
-       fbi->clk = clk_get(&pdev->dev, NULL);
-       if (IS_ERR(fbi->clk)) {
-               ret = PTR_ERR(fbi->clk);
-               dev_err(&pdev->dev, "unable to get clock: %d\n", ret);
+       fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+       if (IS_ERR(fbi->clk_ipg)) {
+               ret = PTR_ERR(fbi->clk_ipg);
+               goto failed_getclock;
+       }
+
+       fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
+       if (IS_ERR(fbi->clk_ahb)) {
+               ret = PTR_ERR(fbi->clk_ahb);
+               goto failed_getclock;
+       }
+
+       fbi->clk_per = devm_clk_get(&pdev->dev, "per");
+       if (IS_ERR(fbi->clk_per)) {
+               ret = PTR_ERR(fbi->clk_per);
                goto failed_getclock;
        }
 
@@ -858,7 +881,6 @@ failed_platform_init:
 failed_map:
        iounmap(fbi->regs);
 failed_ioremap:
-       clk_put(fbi->clk);
 failed_getclock:
        release_mem_region(res->start, resource_size(res));
 failed_req:
@@ -895,8 +917,6 @@ static int __devexit imxfb_remove(struct platform_device *pdev)
 
        iounmap(fbi->regs);
        release_mem_region(res->start, resource_size(res));
-       clk_disable(fbi->clk);
-       clk_put(fbi->clk);
 
        platform_set_drvdata(pdev, NULL);
 

diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 4a89f88..6c6bc57 100644 (file)
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -45,6 +45,7 @@
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
+#include <linux/pinctrl/consumer.h>
 #include <mach/mxsfb.h>
 
 #define REG_SET        4
@@ -756,6 +757,7 @@ static int __devinit mxsfb_probe(struct platform_device *pdev)
        struct mxsfb_info *host;
        struct fb_info *fb_info;
        struct fb_modelist *modelist;
+       struct pinctrl *pinctrl;
        int i, ret;
 
        if (!pdata) {
@@ -793,6 +795,12 @@ static int __devinit mxsfb_probe(struct platform_device *pdev)
 
        host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
 
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
+               goto error_getpin;
+       }
+
        host->clk = clk_get(&host->pdev->dev, NULL);
        if (IS_ERR(host->clk)) {
                ret = PTR_ERR(host->clk);
@@ -848,6 +856,7 @@ error_init_fb:
 error_pseudo_pallette:
        clk_put(host->clk);
 error_getclock:
+error_getpin:
        iounmap(host->base);
 error_ioremap:
        framebuffer_release(fb_info);

diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index a3b6a74..1cc61a7 100644 (file)
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -138,7 +138,7 @@ static int __devinit mxc_w1_probe(struct platform_device *pdev)
                goto failed_ioremap;
        }
 
-       clk_enable(mdev->clk);
+       clk_prepare_enable(mdev->clk);
        __raw_writeb(mdev->clkdiv, mdev->regs + MXC_W1_TIME_DIVIDER);
 
        mdev->bus_master.data = mdev;
@@ -178,7 +178,7 @@ static int __devexit mxc_w1_remove(struct platform_device *pdev)
 
        iounmap(mdev->regs);
        release_mem_region(res->start, resource_size(res));
-       clk_disable(mdev->clk);
+       clk_disable_unprepare(mdev->clk);
        clk_put(mdev->clk);
 
        platform_set_drvdata(pdev, NULL);

diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
index cbc7cee..9f13b89 100644 (file)
--- a/drivers/watchdog/hpwdt.c
+++ b/drivers/watchdog/hpwdt.c
@@ -435,16 +435,16 @@ static void hpwdt_start(void)
 {
        reload = SECS_TO_TICKS(soft_margin);
        iowrite16(reload, hpwdt_timer_reg);
-       iowrite16(0x85, hpwdt_timer_con);
+       iowrite8(0x85, hpwdt_timer_con);
 }
 
 static void hpwdt_stop(void)
 {
        unsigned long data;
 
-       data = ioread16(hpwdt_timer_con);
+       data = ioread8(hpwdt_timer_con);
        data &= 0xFE;
-       iowrite16(data, hpwdt_timer_con);
+       iowrite8(data, hpwdt_timer_con);
 }
 
 static void hpwdt_ping(void)

diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index 7a2b734..bcfab2b 100644 (file)
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -121,7 +121,7 @@ static void imx2_wdt_start(void)
 {
        if (!test_and_set_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
                /* at our first start we enable clock and do initialisations */
-               clk_enable(imx2_wdt.clk);
+               clk_prepare_enable(imx2_wdt.clk);
 
                imx2_wdt_setup();
        } else  /* delete the timer that pings the watchdog after close */

diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index 4b33acd..0a8a17c 100644 (file)
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -274,7 +274,7 @@ static unsigned int cpu_from_evtchn(unsigned int evtchn)
 
 static bool pirq_check_eoi_map(unsigned irq)
 {
-       return test_bit(irq, pirq_eoi_map);
+       return test_bit(pirq_from_irq(irq), pirq_eoi_map);
 }
 
 static bool pirq_needs_eoi_flag(unsigned irq)

diff --git a/drivers/xen/xen-acpi-processor.c b/drivers/xen/xen-acpi-processor.c
index 174b565..0b48579 100644 (file)
--- a/drivers/xen/xen-acpi-processor.c
+++ b/drivers/xen/xen-acpi-processor.c
@@ -128,7 +128,10 @@ static int push_cxx_to_hypervisor(struct acpi_processor *_pr)
                        pr_debug("     C%d: %s %d uS\n",
                                 cx->type, cx->desc, (u32)cx->latency);
                }
-       } else
+       } else if (ret != -EINVAL)
+               /* EINVAL means the ACPI ID is incorrect - meaning the ACPI
+                * table is referencing a non-existing CPU - which can happen
+                * with broken ACPI tables. */
                pr_err(DRV_NAME "(CX): Hypervisor error (%d) for ACPI CPU%u\n",
                       ret, _pr->acpi_id);
 

diff --git a/fs/autofs4/autofs_i.h b/fs/autofs4/autofs_i.h
index eb1cc92..908e184 100644 (file)
--- a/fs/autofs4/autofs_i.h
+++ b/fs/autofs4/autofs_i.h
@@ -110,7 +110,6 @@ struct autofs_sb_info {
        int sub_version;
        int min_proto;
        int max_proto;
-       int compat_daemon;
        unsigned long exp_timeout;
        unsigned int type;
        int reghost_enabled;
@@ -270,6 +269,17 @@ int autofs4_fill_super(struct super_block *, void *, int);
 struct autofs_info *autofs4_new_ino(struct autofs_sb_info *);
 void autofs4_clean_ino(struct autofs_info *);
 
+static inline int autofs_prepare_pipe(struct file *pipe)
+{
+       if (!pipe->f_op || !pipe->f_op->write)
+               return -EINVAL;
+       if (!S_ISFIFO(pipe->f_dentry->d_inode->i_mode))
+               return -EINVAL;
+       /* We want a packet pipe */
+       pipe->f_flags |= O_DIRECT;
+       return 0;
+}
+
 /* Queue management functions */
 
 int autofs4_wait(struct autofs_sb_info *,struct dentry *, enum autofs_notify);

diff --git a/fs/autofs4/dev-ioctl.c b/fs/autofs4/dev-ioctl.c
index 9dacb85..aa9103f 100644 (file)
--- a/fs/autofs4/dev-ioctl.c
+++ b/fs/autofs4/dev-ioctl.c
@@ -376,7 +376,7 @@ static int autofs_dev_ioctl_setpipefd(struct file *fp,
                        err = -EBADF;
                        goto out;
                }
-               if (!pipe->f_op || !pipe->f_op->write) {
+               if (autofs_prepare_pipe(pipe) < 0) {
                        err = -EPIPE;
                        fput(pipe);
                        goto out;
@@ -385,7 +385,6 @@ static int autofs_dev_ioctl_setpipefd(struct file *fp,
                sbi->pipefd = pipefd;
                sbi->pipe = pipe;
                sbi->catatonic = 0;
-               sbi->compat_daemon = is_compat_task();
        }
 out:
        mutex_unlock(&sbi->wq_mutex);

diff --git a/fs/autofs4/inode.c b/fs/autofs4/inode.c
index d8dc002..6e488eb 100644 (file)
--- a/fs/autofs4/inode.c
+++ b/fs/autofs4/inode.c
@@ -19,7 +19,6 @@
 #include <linux/parser.h>
 #include <linux/bitops.h>
 #include <linux/magic.h>
-#include <linux/compat.h>
 #include "autofs_i.h"
 #include <linux/module.h>
 
@@ -225,7 +224,6 @@ int autofs4_fill_super(struct super_block *s, void *data, int silent)
        set_autofs_type_indirect(&sbi->type);
        sbi->min_proto = 0;
        sbi->max_proto = 0;
-       sbi->compat_daemon = is_compat_task();
        mutex_init(&sbi->wq_mutex);
        mutex_init(&sbi->pipe_mutex);
        spin_lock_init(&sbi->fs_lock);
@@ -292,7 +290,7 @@ int autofs4_fill_super(struct super_block *s, void *data, int silent)
                printk("autofs: could not open pipe file descriptor\n");
                goto fail_dput;
        }
-       if (!pipe->f_op || !pipe->f_op->write)
+       if (autofs_prepare_pipe(pipe) < 0)
                goto fail_fput;
        sbi->pipe = pipe;
        sbi->pipefd = pipefd;

diff --git a/fs/autofs4/waitq.c b/fs/autofs4/waitq.c
index 9c098db..da8876d 100644 (file)
--- a/fs/autofs4/waitq.c
+++ b/fs/autofs4/waitq.c
@@ -91,24 +91,7 @@ static int autofs4_write(struct autofs_sb_info *sbi,
 
        return (bytes > 0);
 }
-
-/*
- * The autofs_v5 packet was misdesigned.
- *
- * The packets are identical on x86-32 and x86-64, but have different
- * alignment. Which means that 'sizeof()' will give different results.
- * Fix it up for the case of running 32-bit user mode on a 64-bit kernel.
- */
-static noinline size_t autofs_v5_packet_size(struct autofs_sb_info *sbi)
-{
-       size_t pktsz = sizeof(struct autofs_v5_packet);
-#if defined(CONFIG_X86_64) && defined(CONFIG_COMPAT)
-       if (sbi->compat_daemon > 0)
-               pktsz -= 4;
-#endif
-       return pktsz;
-}
-
+       
 static void autofs4_notify_daemon(struct autofs_sb_info *sbi,
                                 struct autofs_wait_queue *wq,
                                 int type)
@@ -172,7 +155,8 @@ static void autofs4_notify_daemon(struct autofs_sb_info *sbi,
        {
                struct autofs_v5_packet *packet = &pkt.v5_pkt.v5_packet;
 
-               pktsz = autofs_v5_packet_size(sbi);
+               pktsz = sizeof(*packet);
+
                packet->wait_queue_token = wq->wait_queue_token;
                packet->len = wq->name.len;
                memcpy(packet->name, wq->name.name, wq->name.len);

diff --git a/fs/btrfs/backref.c b/fs/btrfs/backref.c
index f4e9074..bcec067 100644 (file)
--- a/fs/btrfs/backref.c
+++ b/fs/btrfs/backref.c
@@ -22,6 +22,7 @@
 #include "ulist.h"
 #include "transaction.h"
 #include "delayed-ref.h"
+#include "locking.h"
 
 /*
  * this structure records all encountered refs on the way up to the root
@@ -893,18 +894,22 @@ static char *iref_to_path(struct btrfs_root *fs_root, struct btrfs_path *path,
        s64 bytes_left = size - 1;
        struct extent_buffer *eb = eb_in;
        struct btrfs_key found_key;
+       int leave_spinning = path->leave_spinning;
 
        if (bytes_left >= 0)
                dest[bytes_left] = '\0';
 
+       path->leave_spinning = 1;
        while (1) {
                len = btrfs_inode_ref_name_len(eb, iref);
                bytes_left -= len;
                if (bytes_left >= 0)
                        read_extent_buffer(eb, dest + bytes_left,
                                                (unsigned long)(iref + 1), len);
-               if (eb != eb_in)
+               if (eb != eb_in) {
+                       btrfs_tree_read_unlock_blocking(eb);
                        free_extent_buffer(eb);
+               }
                ret = inode_ref_info(parent, 0, fs_root, path, &found_key);
                if (ret > 0)
                        ret = -ENOENT;
@@ -919,8 +924,11 @@ static char *iref_to_path(struct btrfs_root *fs_root, struct btrfs_path *path,
                slot = path->slots[0];
                eb = path->nodes[0];
                /* make sure we can use eb after releasing the path */
-               if (eb != eb_in)
+               if (eb != eb_in) {
                        atomic_inc(&eb->refs);
+                       btrfs_tree_read_lock(eb);
+                       btrfs_set_lock_blocking_rw(eb, BTRFS_READ_LOCK);
+               }
                btrfs_release_path(path);
 
                iref = btrfs_item_ptr(eb, slot, struct btrfs_inode_ref);
@@ -931,6 +939,7 @@ static char *iref_to_path(struct btrfs_root *fs_root, struct btrfs_path *path,
        }
 
        btrfs_release_path(path);
+       path->leave_spinning = leave_spinning;
 
        if (ret)
                return ERR_PTR(ret);
@@ -1247,7 +1256,7 @@ static int iterate_irefs(u64 inum, struct btrfs_root *fs_root,
                                struct btrfs_path *path,
                                iterate_irefs_t *iterate, void *ctx)
 {
-       int ret;
+       int ret = 0;
        int slot;
        u32 cur;
        u32 len;
@@ -1259,7 +1268,8 @@ static int iterate_irefs(u64 inum, struct btrfs_root *fs_root,
        struct btrfs_inode_ref *iref;
        struct btrfs_key found_key;
 
-       while (1) {
+       while (!ret) {
+               path->leave_spinning = 1;
                ret = inode_ref_info(inum, parent ? parent+1 : 0, fs_root, path,
                                        &found_key);
                if (ret < 0)
@@ -1275,6 +1285,8 @@ static int iterate_irefs(u64 inum, struct btrfs_root *fs_root,
                eb = path->nodes[0];
                /* make sure we can use eb after releasing the path */
                atomic_inc(&eb->refs);
+               btrfs_tree_read_lock(eb);
+               btrfs_set_lock_blocking_rw(eb, BTRFS_READ_LOCK);
                btrfs_release_path(path);
 
                item = btrfs_item_nr(eb, slot);
@@ -1288,13 +1300,12 @@ static int iterate_irefs(u64 inum, struct btrfs_root *fs_root,
                                 (unsigned long long)found_key.objectid,
                                 (unsigned long long)fs_root->objectid);
                        ret = iterate(parent, iref, eb, ctx);
-                       if (ret) {
-                               free_extent_buffer(eb);
+                       if (ret)
                                break;
-                       }
                        len = sizeof(*iref) + name_len;
                        iref = (struct btrfs_inode_ref *)((char *)iref + len);
                }
+               btrfs_tree_read_unlock_blocking(eb);
                free_extent_buffer(eb);
        }
 
@@ -1414,6 +1425,8 @@ struct inode_fs_paths *init_ipath(s32 total_bytes, struct btrfs_root *fs_root,
 
 void free_ipath(struct inode_fs_paths *ipath)
 {
+       if (!ipath)
+               return;
        kfree(ipath->fspath);
        kfree(ipath);
 }

diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c
index e801f22..4106264 100644 (file)
--- a/fs/btrfs/ctree.c
+++ b/fs/btrfs/ctree.c
@@ -220,10 +220,12 @@ struct extent_buffer *btrfs_read_lock_root_node(struct btrfs_root *root)
  */
 static void add_root_to_dirty_list(struct btrfs_root *root)
 {
+       spin_lock(&root->fs_info->trans_lock);
        if (root->track_dirty && list_empty(&root->dirty_list)) {
                list_add(&root->dirty_list,
                         &root->fs_info->dirty_cowonly_roots);
        }
+       spin_unlock(&root->fs_info->trans_lock);
 }
 
 /*
@@ -723,7 +725,7 @@ int btrfs_realloc_node(struct btrfs_trans_handle *trans,
 
                cur = btrfs_find_tree_block(root, blocknr, blocksize);
                if (cur)
-                       uptodate = btrfs_buffer_uptodate(cur, gen);
+                       uptodate = btrfs_buffer_uptodate(cur, gen, 0);
                else
                        uptodate = 0;
                if (!cur || !uptodate) {
@@ -1358,7 +1360,12 @@ static noinline int reada_for_balance(struct btrfs_root *root,
                block1 = btrfs_node_blockptr(parent, slot - 1);
                gen = btrfs_node_ptr_generation(parent, slot - 1);
                eb = btrfs_find_tree_block(root, block1, blocksize);
-               if (eb && btrfs_buffer_uptodate(eb, gen))
+               /*
+                * if we get -eagain from btrfs_buffer_uptodate, we
+                * don't want to return eagain here.  That will loop
+                * forever
+                */
+               if (eb && btrfs_buffer_uptodate(eb, gen, 1) != 0)
                        block1 = 0;
                free_extent_buffer(eb);
        }
@@ -1366,7 +1373,7 @@ static noinline int reada_for_balance(struct btrfs_root *root,
                block2 = btrfs_node_blockptr(parent, slot + 1);
                gen = btrfs_node_ptr_generation(parent, slot + 1);
                eb = btrfs_find_tree_block(root, block2, blocksize);
-               if (eb && btrfs_buffer_uptodate(eb, gen))
+               if (eb && btrfs_buffer_uptodate(eb, gen, 1) != 0)
                        block2 = 0;
                free_extent_buffer(eb);
        }
@@ -1504,8 +1511,9 @@ read_block_for_search(struct btrfs_trans_handle *trans,
 
        tmp = btrfs_find_tree_block(root, blocknr, blocksize);
        if (tmp) {
-               if (btrfs_buffer_uptodate(tmp, 0)) {
-                       if (btrfs_buffer_uptodate(tmp, gen)) {
+               /* first we do an atomic uptodate check */
+               if (btrfs_buffer_uptodate(tmp, 0, 1) > 0) {
+                       if (btrfs_buffer_uptodate(tmp, gen, 1) > 0) {
                                /*
                                 * we found an up to date block without
                                 * sleeping, return
@@ -1523,8 +1531,9 @@ read_block_for_search(struct btrfs_trans_handle *trans,
                        free_extent_buffer(tmp);
                        btrfs_set_path_blocking(p);
 
+                       /* now we're allowed to do a blocking uptodate check */
                        tmp = read_tree_block(root, blocknr, blocksize, gen);
-                       if (tmp && btrfs_buffer_uptodate(tmp, gen)) {
+                       if (tmp && btrfs_buffer_uptodate(tmp, gen, 0) > 0) {
                                *eb_ret = tmp;
                                return 0;
                        }
@@ -1559,7 +1568,7 @@ read_block_for_search(struct btrfs_trans_handle *trans,
                 * and give up so that our caller doesn't loop forever
                 * on our EAGAINs.
                 */
-               if (!btrfs_buffer_uptodate(tmp, 0))
+               if (!btrfs_buffer_uptodate(tmp, 0, 0))
                        ret = -EIO;
                free_extent_buffer(tmp);
        }
@@ -4043,7 +4052,7 @@ again:
                        tmp = btrfs_find_tree_block(root, blockptr,
                                            btrfs_level_size(root, level - 1));
 
-                       if (tmp && btrfs_buffer_uptodate(tmp, gen)) {
+                       if (tmp && btrfs_buffer_uptodate(tmp, gen, 1) > 0) {
                                free_extent_buffer(tmp);
                                break;
                        }
@@ -4166,7 +4175,8 @@ next:
                                struct extent_buffer *cur;
                                cur = btrfs_find_tree_block(root, blockptr,
                                            btrfs_level_size(root, level - 1));
-                               if (!cur || !btrfs_buffer_uptodate(cur, gen)) {
+                               if (!cur ||
+                                   btrfs_buffer_uptodate(cur, gen, 1) <= 0) {
                                        slot++;
                                        if (cur)
                                                free_extent_buffer(cur);

diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
index 3f65a81..8fd7233 100644 (file)
--- a/fs/btrfs/ctree.h
+++ b/fs/btrfs/ctree.h
@@ -1078,7 +1078,7 @@ struct btrfs_fs_info {
         * is required instead of the faster short fsync log commits
         */
        u64 last_trans_log_full_commit;
-       unsigned long mount_opt:21;
+       unsigned long mount_opt;
        unsigned long compress_type:4;
        u64 max_inline;
        u64 alloc_start;

diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index 20196f4..a7ffc88 100644 (file)
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -323,7 +323,8 @@ static int csum_tree_block(struct btrfs_root *root, struct extent_buffer *buf,
  * in the wrong place.
  */
 static int verify_parent_transid(struct extent_io_tree *io_tree,
-                                struct extent_buffer *eb, u64 parent_transid)
+                                struct extent_buffer *eb, u64 parent_transid,
+                                int atomic)
 {
        struct extent_state *cached_state = NULL;
        int ret;
@@ -331,6 +332,9 @@ static int verify_parent_transid(struct extent_io_tree *io_tree,
        if (!parent_transid || btrfs_header_generation(eb) == parent_transid)
                return 0;
 
+       if (atomic)
+               return -EAGAIN;
+
        lock_extent_bits(io_tree, eb->start, eb->start + eb->len - 1,
                         0, &cached_state);
        if (extent_buffer_uptodate(eb) &&
@@ -372,7 +376,8 @@ static int btree_read_extent_buffer_pages(struct btrfs_root *root,
                ret = read_extent_buffer_pages(io_tree, eb, start,
                                               WAIT_COMPLETE,
                                               btree_get_extent, mirror_num);
-               if (!ret && !verify_parent_transid(io_tree, eb, parent_transid))
+               if (!ret && !verify_parent_transid(io_tree, eb,
+                                                  parent_transid, 0))
                        break;
 
                /*
@@ -383,17 +388,16 @@ static int btree_read_extent_buffer_pages(struct btrfs_root *root,
                if (test_bit(EXTENT_BUFFER_CORRUPT, &eb->bflags))
                        break;
 
-               if (!failed_mirror) {
-                       failed = 1;
-                       printk(KERN_ERR "failed mirror was %d\n", eb->failed_mirror);
-                       failed_mirror = eb->failed_mirror;
-               }
-
                num_copies = btrfs_num_copies(&root->fs_info->mapping_tree,
                                              eb->start, eb->len);
                if (num_copies == 1)
                        break;
 
+               if (!failed_mirror) {
+                       failed = 1;
+                       failed_mirror = eb->read_mirror;
+               }
+
                mirror_num++;
                if (mirror_num == failed_mirror)
                        mirror_num++;
@@ -564,7 +568,7 @@ struct extent_buffer *find_eb_for_page(struct extent_io_tree *tree,
 }
 
 static int btree_readpage_end_io_hook(struct page *page, u64 start, u64 end,
-                              struct extent_state *state)
+                              struct extent_state *state, int mirror)
 {
        struct extent_io_tree *tree;
        u64 found_start;
@@ -589,6 +593,7 @@ static int btree_readpage_end_io_hook(struct page *page, u64 start, u64 end,
        if (!reads_done)
                goto err;
 
+       eb->read_mirror = mirror;
        if (test_bit(EXTENT_BUFFER_IOERR, &eb->bflags)) {
                ret = -EIO;
                goto err;
@@ -652,7 +657,7 @@ static int btree_io_failed_hook(struct page *page, int failed_mirror)
 
        eb = (struct extent_buffer *)page->private;
        set_bit(EXTENT_BUFFER_IOERR, &eb->bflags);
-       eb->failed_mirror = failed_mirror;
+       eb->read_mirror = failed_mirror;
        if (test_and_clear_bit(EXTENT_BUFFER_READAHEAD, &eb->bflags))
                btree_readahead_hook(root, eb, eb->start, -EIO);
        return -EIO;    /* we fixed nothing */
@@ -1202,7 +1207,7 @@ static int __must_check find_and_setup_root(struct btrfs_root *tree_root,
        root->commit_root = NULL;
        root->node = read_tree_block(root, btrfs_root_bytenr(&root->root_item),
                                     blocksize, generation);
-       if (!root->node || !btrfs_buffer_uptodate(root->node, generation)) {
+       if (!root->node || !btrfs_buffer_uptodate(root->node, generation, 0)) {
                free_extent_buffer(root->node);
                root->node = NULL;
                return -EIO;
@@ -2254,9 +2259,9 @@ int open_ctree(struct super_block *sb,
                goto fail_sb_buffer;
        }
 
-       if (sectorsize < PAGE_SIZE) {
-               printk(KERN_WARNING "btrfs: Incompatible sector size "
-                      "found on %s\n", sb->s_id);
+       if (sectorsize != PAGE_SIZE) {
+               printk(KERN_WARNING "btrfs: Incompatible sector size(%lu) "
+                      "found on %s\n", (unsigned long)sectorsize, sb->s_id);
                goto fail_sb_buffer;
        }
 
@@ -3143,7 +3148,8 @@ int close_ctree(struct btrfs_root *root)
        return 0;
 }
 
-int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid)
+int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid,
+                         int atomic)
 {
        int ret;
        struct inode *btree_inode = buf->pages[0]->mapping->host;
@@ -3153,7 +3159,9 @@ int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid)
                return ret;
 
        ret = verify_parent_transid(&BTRFS_I(btree_inode)->io_tree, buf,
-                                   parent_transid);
+                                   parent_transid, atomic);
+       if (ret == -EAGAIN)
+               return ret;
        return !ret;
 }
 

diff --git a/fs/btrfs/disk-io.h b/fs/btrfs/disk-io.h
index a7ace1a..ab1830a 100644 (file)
--- a/fs/btrfs/disk-io.h
+++ b/fs/btrfs/disk-io.h
@@ -66,7 +66,8 @@ void btrfs_btree_balance_dirty(struct btrfs_root *root, unsigned long nr);
 void __btrfs_btree_balance_dirty(struct btrfs_root *root, unsigned long nr);
 void btrfs_free_fs_root(struct btrfs_fs_info *fs_info, struct btrfs_root *root);
 void btrfs_mark_buffer_dirty(struct extent_buffer *buf);
-int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid);
+int btrfs_buffer_uptodate(struct extent_buffer *buf, u64 parent_transid,
+                         int atomic);
 int btrfs_set_buffer_uptodate(struct extent_buffer *buf);
 int btrfs_read_buffer(struct extent_buffer *buf, u64 parent_transid);
 u32 btrfs_csum_data(struct btrfs_root *root, char *data, u32 seed, size_t len);

diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c
index 2b35f8d..49fd7b6 100644 (file)
--- a/fs/btrfs/extent-tree.c
+++ b/fs/btrfs/extent-tree.c
@@ -2301,6 +2301,7 @@ static noinline int run_clustered_refs(struct btrfs_trans_handle *trans,
 
                                if (ret) {
                                        printk(KERN_DEBUG "btrfs: run_delayed_extent_op returned %d\n", ret);
+                                       spin_lock(&delayed_refs->lock);
                                        return ret;
                                }
 
@@ -2331,6 +2332,7 @@ static noinline int run_clustered_refs(struct btrfs_trans_handle *trans,
 
                if (ret) {
                        printk(KERN_DEBUG "btrfs: run_one_delayed_ref returned %d\n", ret);
+                       spin_lock(&delayed_refs->lock);
                        return ret;
                }
 
@@ -3769,13 +3771,10 @@ again:
                 */
                if (current->journal_info)
                        return -EAGAIN;
-               ret = wait_event_interruptible(space_info->wait,
-                                              !space_info->flush);
-               /* Must have been interrupted, return */
-               if (ret) {
-                       printk(KERN_DEBUG "btrfs: %s returning -EINTR\n", __func__);
+               ret = wait_event_killable(space_info->wait, !space_info->flush);
+               /* Must have been killed, return */
+               if (ret)
                        return -EINTR;
-               }
 
                spin_lock(&space_info->lock);
        }
@@ -4215,8 +4214,8 @@ static void update_global_block_rsv(struct btrfs_fs_info *fs_info)
 
        num_bytes = calc_global_metadata_size(fs_info);
 
-       spin_lock(&block_rsv->lock);
        spin_lock(&sinfo->lock);
+       spin_lock(&block_rsv->lock);
 
        block_rsv->size = num_bytes;
 
@@ -4242,8 +4241,8 @@ static void update_global_block_rsv(struct btrfs_fs_info *fs_info)
                block_rsv->full = 1;
        }
 
-       spin_unlock(&sinfo->lock);
        spin_unlock(&block_rsv->lock);
+       spin_unlock(&sinfo->lock);
 }
 
 static void init_global_block_rsv(struct btrfs_fs_info *fs_info)
@@ -6569,7 +6568,7 @@ static noinline int do_walk_down(struct btrfs_trans_handle *trans,
                        goto skip;
        }
 
-       if (!btrfs_buffer_uptodate(next, generation)) {
+       if (!btrfs_buffer_uptodate(next, generation, 0)) {
                btrfs_tree_unlock(next);
                free_extent_buffer(next);
                next = NULL;

diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
index cd4b5e4..c9018a0 100644 (file)
--- a/fs/btrfs/extent_io.c
+++ b/fs/btrfs/extent_io.c
@@ -402,20 +402,28 @@ static int split_state(struct extent_io_tree *tree, struct extent_state *orig,
        return 0;
 }
 
+static struct extent_state *next_state(struct extent_state *state)
+{
+       struct rb_node *next = rb_next(&state->rb_node);
+       if (next)
+               return rb_entry(next, struct extent_state, rb_node);
+       else
+               return NULL;
+}
+
 /*
  * utility function to clear some bits in an extent state struct.
- * it will optionally wake up any one waiting on this state (wake == 1), or
- * forcibly remove the state from the tree (delete == 1).
+ * it will optionally wake up any one waiting on this state (wake == 1)
  *
  * If no bits are set on the state struct after clearing things, the
  * struct is freed and removed from the tree
  */
-static int clear_state_bit(struct extent_io_tree *tree,
-                           struct extent_state *state,
-                           int *bits, int wake)
+static struct extent_state *clear_state_bit(struct extent_io_tree *tree,
+                                           struct extent_state *state,
+                                           int *bits, int wake)
 {
+       struct extent_state *next;
        int bits_to_clear = *bits & ~EXTENT_CTLBITS;
-       int ret = state->state & bits_to_clear;
 
        if ((bits_to_clear & EXTENT_DIRTY) && (state->state & EXTENT_DIRTY)) {
                u64 range = state->end - state->start + 1;
@@ -427,6 +435,7 @@ static int clear_state_bit(struct extent_io_tree *tree,
        if (wake)
                wake_up(&state->wq);
        if (state->state == 0) {
+               next = next_state(state);
                if (state->tree) {
                        rb_erase(&state->rb_node, &tree->state);
                        state->tree = NULL;
@@ -436,8 +445,9 @@ static int clear_state_bit(struct extent_io_tree *tree,
                }
        } else {
                merge_state(tree, state);
+               next = next_state(state);
        }
-       return ret;
+       return next;
 }
 
 static struct extent_state *
@@ -476,7 +486,6 @@ int clear_extent_bit(struct extent_io_tree *tree, u64 start, u64 end,
        struct extent_state *state;
        struct extent_state *cached;
        struct extent_state *prealloc = NULL;
-       struct rb_node *next_node;
        struct rb_node *node;
        u64 last_end;
        int err;
@@ -528,14 +537,11 @@ hit_next:
        WARN_ON(state->end < start);
        last_end = state->end;
 
-       if (state->end < end && !need_resched())
-               next_node = rb_next(&state->rb_node);
-       else
-               next_node = NULL;
-
        /* the state doesn't have the wanted bits, go ahead */
-       if (!(state->state & bits))
+       if (!(state->state & bits)) {
+               state = next_state(state);
                goto next;
+       }
 
        /*
         *     | ---- desired range ---- |
@@ -593,16 +599,13 @@ hit_next:
                goto out;
        }
 
-       clear_state_bit(tree, state, &bits, wake);
+       state = clear_state_bit(tree, state, &bits, wake);
 next:
        if (last_end == (u64)-1)
                goto out;
        start = last_end + 1;
-       if (start <= end && next_node) {
-               state = rb_entry(next_node, struct extent_state,
-                                rb_node);
+       if (start <= end && state && !need_resched())
                goto hit_next;
-       }
        goto search_again;
 
 out:
@@ -2301,7 +2304,7 @@ static void end_bio_extent_readpage(struct bio *bio, int err)
        u64 start;
        u64 end;
        int whole_page;
-       int failed_mirror;
+       int mirror;
        int ret;
 
        if (err)
@@ -2340,20 +2343,18 @@ static void end_bio_extent_readpage(struct bio *bio, int err)
                }
                spin_unlock(&tree->lock);
 
+               mirror = (int)(unsigned long)bio->bi_bdev;
                if (uptodate && tree->ops && tree->ops->readpage_end_io_hook) {
                        ret = tree->ops->readpage_end_io_hook(page, start, end,
-                                                             state);
+                                                             state, mirror);
                        if (ret)
                                uptodate = 0;
                        else
                                clean_io_failure(start, page);
                }
 
-               if (!uptodate)
-                       failed_mirror = (int)(unsigned long)bio->bi_bdev;
-
                if (!uptodate && tree->ops && tree->ops->readpage_io_failed_hook) {
-                       ret = tree->ops->readpage_io_failed_hook(page, failed_mirror);
+                       ret = tree->ops->readpage_io_failed_hook(page, mirror);
                        if (!ret && !err &&
                            test_bit(BIO_UPTODATE, &bio->bi_flags))
                                uptodate = 1;
@@ -2368,8 +2369,7 @@ static void end_bio_extent_readpage(struct bio *bio, int err)
                         * can't handle the error it will return -EIO and we
                         * remain responsible for that page.
                         */
-                       ret = bio_readpage_error(bio, page, start, end,
-                                                       failed_mirror, NULL);
+                       ret = bio_readpage_error(bio, page, start, end, mirror, NULL);
                        if (ret == 0) {
                                uptodate =
                                        test_bit(BIO_UPTODATE, &bio->bi_flags);
@@ -4120,6 +4120,7 @@ struct extent_buffer *alloc_extent_buffer(struct extent_io_tree *tree,
                        if (atomic_inc_not_zero(&exists->refs)) {
                                spin_unlock(&mapping->private_lock);
                                unlock_page(p);
+                               page_cache_release(p);
                                mark_extent_buffer_accessed(exists);
                                goto free_eb;
                        }
@@ -4199,8 +4200,7 @@ free_eb:
                        unlock_page(eb->pages[i]);
        }
 
-       if (!atomic_dec_and_test(&eb->refs))
-               return exists;
+       WARN_ON(!atomic_dec_and_test(&eb->refs));
        btrfs_release_extent_buffer(eb);
        return exists;
 }
@@ -4462,7 +4462,7 @@ int read_extent_buffer_pages(struct extent_io_tree *tree,
        }
 
        clear_bit(EXTENT_BUFFER_IOERR, &eb->bflags);
-       eb->failed_mirror = 0;
+       eb->read_mirror = 0;
        atomic_set(&eb->io_pages, num_reads);
        for (i = start_i; i < num_pages; i++) {
                page = extent_buffer_page(eb, i);

diff --git a/fs/btrfs/extent_io.h b/fs/btrfs/extent_io.h
index faf10eb..b516c3b 100644 (file)
--- a/fs/btrfs/extent_io.h
+++ b/fs/btrfs/extent_io.h
@@ -79,7 +79,7 @@ struct extent_io_ops {
                                        u64 start, u64 end,
                                       struct extent_state *state);
        int (*readpage_end_io_hook)(struct page *page, u64 start, u64 end,
-                                   struct extent_state *state);
+                                   struct extent_state *state, int mirror);
        int (*writepage_end_io_hook)(struct page *page, u64 start, u64 end,
                                      struct extent_state *state, int uptodate);
        void (*set_bit_hook)(struct inode *inode, struct extent_state *state,
@@ -135,7 +135,7 @@ struct extent_buffer {
        spinlock_t refs_lock;
        atomic_t refs;
        atomic_t io_pages;
-       int failed_mirror;
+       int read_mirror;
        struct list_head leak_list;
        struct rcu_head rcu_head;
        pid_t lock_owner;

diff --git a/fs/btrfs/file.c b/fs/btrfs/file.c
index d83260d..53bf2d7 100644 (file)
--- a/fs/btrfs/file.c
+++ b/fs/btrfs/file.c
@@ -567,6 +567,7 @@ int btrfs_drop_extents(struct btrfs_trans_handle *trans, struct inode *inode,
        int extent_type;
        int recow;
        int ret;
+       int modify_tree = -1;
 
        if (drop_cache)
                btrfs_drop_extent_cache(inode, start, end - 1, 0);
@@ -575,10 +576,13 @@ int btrfs_drop_extents(struct btrfs_trans_handle *trans, struct inode *inode,
        if (!path)
                return -ENOMEM;
 
+       if (start >= BTRFS_I(inode)->disk_i_size)
+               modify_tree = 0;
+
        while (1) {
                recow = 0;
                ret = btrfs_lookup_file_extent(trans, root, path, ino,
-                                              search_start, -1);
+                                              search_start, modify_tree);
                if (ret < 0)
                        break;
                if (ret > 0 && path->slots[0] > 0 && search_start == start) {
@@ -634,7 +638,8 @@ next_slot:
                }
 
                search_start = max(key.offset, start);
-               if (recow) {
+               if (recow || !modify_tree) {
+                       modify_tree = -1;
                        btrfs_release_path(path);
                        continue;
                }

diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 115bc05..61b16c6 100644 (file)
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -1947,7 +1947,7 @@ static int btrfs_writepage_end_io_hook(struct page *page, u64 start, u64 end,
  * extent_io.c will try to find good copies for us.
  */
 static int btrfs_readpage_end_io_hook(struct page *page, u64 start, u64 end,
-                              struct extent_state *state)
+                              struct extent_state *state, int mirror)
 {
        size_t offset = start - ((u64)page->index << PAGE_CACHE_SHIFT);
        struct inode *inode = page->mapping->host;
@@ -4069,7 +4069,7 @@ static struct inode *new_simple_dir(struct super_block *s,
        BTRFS_I(inode)->dummy_inode = 1;
 
        inode->i_ino = BTRFS_EMPTY_SUBVOL_DIR_OBJECTID;
-       inode->i_op = &simple_dir_inode_operations;
+       inode->i_op = &btrfs_dir_ro_inode_operations;
        inode->i_fop = &simple_dir_operations;
        inode->i_mode = S_IFDIR | S_IRUGO | S_IWUSR | S_IXUGO;
        inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME;
@@ -4140,14 +4140,18 @@ struct inode *btrfs_lookup_dentry(struct inode *dir, struct dentry *dentry)
 static int btrfs_dentry_delete(const struct dentry *dentry)
 {
        struct btrfs_root *root;
+       struct inode *inode = dentry->d_inode;
 
-       if (!dentry->d_inode && !IS_ROOT(dentry))
-               dentry = dentry->d_parent;
+       if (!inode && !IS_ROOT(dentry))
+               inode = dentry->d_parent->d_inode;
 
-       if (dentry->d_inode) {
-               root = BTRFS_I(dentry->d_inode)->root;
+       if (inode) {
+               root = BTRFS_I(inode)->root;
                if (btrfs_root_refs(&root->root_item) == 0)
                        return 1;
+
+               if (btrfs_ino(inode) == BTRFS_EMPTY_SUBVOL_DIR_OBJECTID)
+                       return 1;
        }
        return 0;
 }
@@ -4188,7 +4192,6 @@ static int btrfs_real_readdir(struct file *filp, void *dirent,
        struct btrfs_path *path;
        struct list_head ins_list;
        struct list_head del_list;
-       struct qstr q;
        int ret;
        struct extent_buffer *leaf;
        int slot;
@@ -4279,7 +4282,6 @@ static int btrfs_real_readdir(struct file *filp, void *dirent,
 
                while (di_cur < di_total) {
                        struct btrfs_key location;
-                       struct dentry *tmp;
 
                        if (verify_dir_item(root, leaf, di))
                                break;
@@ -4300,35 +4302,15 @@ static int btrfs_real_readdir(struct file *filp, void *dirent,
                        d_type = btrfs_filetype_table[btrfs_dir_type(leaf, di)];
                        btrfs_dir_item_key_to_cpu(leaf, di, &location);
 
-                       q.name = name_ptr;
-                       q.len = name_len;
-                       q.hash = full_name_hash(q.name, q.len);
-                       tmp = d_lookup(filp->f_dentry, &q);
-                       if (!tmp) {
-                               struct btrfs_key *newkey;
-
-                               newkey = kzalloc(sizeof(struct btrfs_key),
-                                                GFP_NOFS);
-                               if (!newkey)
-                                       goto no_dentry;
-                               tmp = d_alloc(filp->f_dentry, &q);
-                               if (!tmp) {
-                                       kfree(newkey);
-                                       dput(tmp);
-                                       goto no_dentry;
-                               }
-                               memcpy(newkey, &location,
-                                      sizeof(struct btrfs_key));
-                               tmp->d_fsdata = newkey;
-                               tmp->d_flags |= DCACHE_NEED_LOOKUP;
-                               d_rehash(tmp);
-                               dput(tmp);
-                       } else {
-                               dput(tmp);
-                       }
-no_dentry:
+
                        /* is this a reference to our own snapshot? If so
-                        * skip it
+                        * skip it.
+                        *
+                        * In contrast to old kernels, we insert the snapshot's
+                        * dir item and dir index after it has been created, so
+                        * we won't find a reference to our own snapshot. We
+                        * still keep the following code for backward
+                        * compatibility.
                         */
                        if (location.type == BTRFS_ROOT_ITEM_KEY &&
                            location.objectid == root->root_key.objectid) {

diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c
index 18cc23d..14f8e1f 100644 (file)
--- a/fs/btrfs/ioctl.c
+++ b/fs/btrfs/ioctl.c
@@ -2262,7 +2262,10 @@ static long btrfs_ioctl_dev_info(struct btrfs_root *root, void __user *arg)
        di_args->bytes_used = dev->bytes_used;
        di_args->total_bytes = dev->total_bytes;
        memcpy(di_args->uuid, dev->uuid, sizeof(di_args->uuid));
-       strncpy(di_args->path, dev->name, sizeof(di_args->path));
+       if (dev->name)
+               strncpy(di_args->path, dev->name, sizeof(di_args->path));
+       else
+               di_args->path[0] = '\0';
 
 out:
        if (ret == 0 && copy_to_user(arg, di_args, sizeof(*di_args)))

diff --git a/fs/btrfs/ioctl.h b/fs/btrfs/ioctl.h
index 4f69028..086e6bd 100644 (file)
--- a/fs/btrfs/ioctl.h
+++ b/fs/btrfs/ioctl.h
@@ -252,7 +252,7 @@ struct btrfs_data_container {
 
 struct btrfs_ioctl_ino_path_args {
        __u64                           inum;           /* in */
-       __u32                           size;           /* in */
+       __u64                           size;           /* in */
        __u64                           reserved[4];
        /* struct btrfs_data_container  *fspath;           out */
        __u64                           fspath;         /* out */
@@ -260,7 +260,7 @@ struct btrfs_ioctl_ino_path_args {
 
 struct btrfs_ioctl_logical_ino_args {
        __u64                           logical;        /* in */
-       __u32                           size;           /* in */
+       __u64                           size;           /* in */
        __u64                           reserved[4];
        /* struct btrfs_data_container  *inodes;        out   */
        __u64                           inodes;

diff --git a/fs/btrfs/reada.c b/fs/btrfs/reada.c
index dc5d331..ac5d010 100644 (file)
--- a/fs/btrfs/reada.c
+++ b/fs/btrfs/reada.c
@@ -250,14 +250,12 @@ static struct reada_zone *reada_find_zone(struct btrfs_fs_info *fs_info,
                                          struct btrfs_bio *bbio)
 {
        int ret;
-       int looped = 0;
        struct reada_zone *zone;
        struct btrfs_block_group_cache *cache = NULL;
        u64 start;
        u64 end;
        int i;
 
-again:
        zone = NULL;
        spin_lock(&fs_info->reada_lock);
        ret = radix_tree_gang_lookup(&dev->reada_zones, (void **)&zone,
@@ -274,9 +272,6 @@ again:
                spin_unlock(&fs_info->reada_lock);
        }
 
-       if (looped)
-               return NULL;
-
        cache = btrfs_lookup_block_group(fs_info, logical);
        if (!cache)
                return NULL;
@@ -307,13 +302,15 @@ again:
        ret = radix_tree_insert(&dev->reada_zones,
                                (unsigned long)(zone->end >> PAGE_CACHE_SHIFT),
                                zone);
-       spin_unlock(&fs_info->reada_lock);
 
-       if (ret) {
+       if (ret == -EEXIST) {
                kfree(zone);
-               looped = 1;
-               goto again;
+               ret = radix_tree_gang_lookup(&dev->reada_zones, (void **)&zone,
+                                            logical >> PAGE_CACHE_SHIFT, 1);
+               if (ret == 1)
+                       kref_get(&zone->refcnt);
        }
+       spin_unlock(&fs_info->reada_lock);
 
        return zone;
 }
@@ -323,26 +320,26 @@ static struct reada_extent *reada_find_extent(struct btrfs_root *root,
                                              struct btrfs_key *top, int level)
 {
        int ret;
-       int looped = 0;
        struct reada_extent *re = NULL;
+       struct reada_extent *re_exist = NULL;
        struct btrfs_fs_info *fs_info = root->fs_info;
        struct btrfs_mapping_tree *map_tree = &fs_info->mapping_tree;
        struct btrfs_bio *bbio = NULL;
        struct btrfs_device *dev;
+       struct btrfs_device *prev_dev;
        u32 blocksize;
        u64 length;
        int nzones = 0;
        int i;
        unsigned long index = logical >> PAGE_CACHE_SHIFT;
 
-again:
        spin_lock(&fs_info->reada_lock);
        re = radix_tree_lookup(&fs_info->reada_tree, index);
        if (re)
                kref_get(&re->refcnt);
        spin_unlock(&fs_info->reada_lock);
 
-       if (re || looped)
+       if (re)
                return re;
 
        re = kzalloc(sizeof(*re), GFP_NOFS);
@@ -398,16 +395,31 @@ again:
        /* insert extent in reada_tree + all per-device trees, all or nothing */
        spin_lock(&fs_info->reada_lock);
        ret = radix_tree_insert(&fs_info->reada_tree, index, re);
+       if (ret == -EEXIST) {
+               re_exist = radix_tree_lookup(&fs_info->reada_tree, index);
+               BUG_ON(!re_exist);
+               kref_get(&re_exist->refcnt);
+               spin_unlock(&fs_info->reada_lock);
+               goto error;
+       }
        if (ret) {
                spin_unlock(&fs_info->reada_lock);
-               if (ret != -ENOMEM) {
-                       /* someone inserted the extent in the meantime */
-                       looped = 1;
-               }
                goto error;
        }
+       prev_dev = NULL;
        for (i = 0; i < nzones; ++i) {
                dev = bbio->stripes[i].dev;
+               if (dev == prev_dev) {
+                       /*
+                        * in case of DUP, just add the first zone. As both
+                        * are on the same device, there's nothing to gain
+                        * from adding both.
+                        * Also, it wouldn't work, as the tree is per device
+                        * and adding would fail with EEXIST
+                        */
+                       continue;
+               }
+               prev_dev = dev;
                ret = radix_tree_insert(&dev->reada_extents, index, re);
                if (ret) {
                        while (--i >= 0) {
@@ -450,9 +462,7 @@ error:
        }
        kfree(bbio);
        kfree(re);
-       if (looped)
-               goto again;
-       return NULL;
+       return re_exist;
 }
 
 static void reada_kref_dummy(struct kref *kr)

diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c
index 017281d..646ee21 100644 (file)
--- a/fs/btrfs/relocation.c
+++ b/fs/btrfs/relocation.c
@@ -1279,7 +1279,9 @@ static int __update_reloc_root(struct btrfs_root *root, int del)
                if (rb_node)
                        backref_tree_panic(rb_node, -EEXIST, node->bytenr);
        } else {
+               spin_lock(&root->fs_info->trans_lock);
                list_del_init(&root->root_list);
+               spin_unlock(&root->fs_info->trans_lock);
                kfree(node);
        }
        return 0;
@@ -3811,7 +3813,7 @@ restart:
 
                ret = btrfs_block_rsv_check(rc->extent_root, rc->block_rsv, 5);
                if (ret < 0) {
-                       if (ret != -EAGAIN) {
+                       if (ret != -ENOSPC) {
                                err = ret;
                                WARN_ON(1);
                                break;

diff --git a/fs/btrfs/scrub.c b/fs/btrfs/scrub.c
index bc015f7..2f3d6f9 100644 (file)
--- a/fs/btrfs/scrub.c
+++ b/fs/btrfs/scrub.c
@@ -998,6 +998,7 @@ static int scrub_setup_recheck_block(struct scrub_dev *sdev,
                        page = sblock->pagev + page_index;
                        page->logical = logical;
                        page->physical = bbio->stripes[mirror_index].physical;
+                       /* for missing devices, bdev is NULL */
                        page->bdev = bbio->stripes[mirror_index].dev->bdev;
                        page->mirror_num = mirror_index + 1;
                        page->page = alloc_page(GFP_NOFS);
@@ -1042,6 +1043,12 @@ static int scrub_recheck_block(struct btrfs_fs_info *fs_info,
                struct scrub_page *page = sblock->pagev + page_num;
                DECLARE_COMPLETION_ONSTACK(complete);
 
+               if (page->bdev == NULL) {
+                       page->io_error = 1;
+                       sblock->no_io_error_seen = 0;
+                       continue;
+               }
+
                BUG_ON(!page->page);
                bio = bio_alloc(GFP_NOFS, 1);
                if (!bio)
@@ -1257,12 +1264,6 @@ static int scrub_checksum_data(struct scrub_block *sblock)
        if (memcmp(csum, on_disk_csum, sdev->csum_size))
                fail = 1;
 
-       if (fail) {
-               spin_lock(&sdev->stat_lock);
-               ++sdev->stat.csum_errors;
-               spin_unlock(&sdev->stat_lock);
-       }
-
        return fail;
 }
 
@@ -1335,15 +1336,6 @@ static int scrub_checksum_tree_block(struct scrub_block *sblock)
        if (memcmp(calculated_csum, on_disk_csum, sdev->csum_size))
                ++crc_fail;
 
-       if (crc_fail || fail) {
-               spin_lock(&sdev->stat_lock);
-               if (crc_fail)
-                       ++sdev->stat.csum_errors;
-               if (fail)
-                       ++sdev->stat.verify_errors;
-               spin_unlock(&sdev->stat_lock);
-       }
-
        return fail || crc_fail;
 }
 

diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index 8d5d380..c5f8fca 100644 (file)
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -815,7 +815,6 @@ int btrfs_sync_fs(struct super_block *sb, int wait)
                return 0;
        }
 
-       btrfs_start_delalloc_inodes(root, 0);
        btrfs_wait_ordered_extents(root, 0, 0);
 
        trans = btrfs_start_transaction(root, 0);
@@ -1148,13 +1147,15 @@ static int btrfs_remount(struct super_block *sb, int *flags, char *data)
                if (ret)
                        goto restore;
        } else {
-               if (fs_info->fs_devices->rw_devices == 0)
+               if (fs_info->fs_devices->rw_devices == 0) {
                        ret = -EACCES;
                        goto restore;
+               }
 
-               if (btrfs_super_log_root(fs_info->super_copy) != 0)
+               if (btrfs_super_log_root(fs_info->super_copy) != 0) {
                        ret = -EINVAL;
                        goto restore;
+               }
 
                ret = btrfs_cleanup_fs_roots(fs_info);
                if (ret)

diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c
index 11b77a5..3642225 100644 (file)
--- a/fs/btrfs/transaction.c
+++ b/fs/btrfs/transaction.c
@@ -73,8 +73,10 @@ loop:
 
        cur_trans = root->fs_info->running_transaction;
        if (cur_trans) {
-               if (cur_trans->aborted)
+               if (cur_trans->aborted) {
+                       spin_unlock(&root->fs_info->trans_lock);
                        return cur_trans->aborted;
+               }
                atomic_inc(&cur_trans->use_count);
                atomic_inc(&cur_trans->num_writers);
                cur_trans->num_joined++;
@@ -1400,6 +1402,7 @@ int btrfs_commit_transaction(struct btrfs_trans_handle *trans,
        ret = commit_fs_roots(trans, root);
        if (ret) {
                mutex_unlock(&root->fs_info->tree_log_mutex);
+               mutex_unlock(&root->fs_info->reloc_mutex);
                goto cleanup_transaction;
        }
 
@@ -1411,6 +1414,7 @@ int btrfs_commit_transaction(struct btrfs_trans_handle *trans,
        ret = commit_cowonly_roots(trans, root);
        if (ret) {
                mutex_unlock(&root->fs_info->tree_log_mutex);
+               mutex_unlock(&root->fs_info->reloc_mutex);
                goto cleanup_transaction;
        }
 

diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
index d017283..eb1ae90 100644 (file)
--- a/fs/btrfs/tree-log.c
+++ b/fs/btrfs/tree-log.c
@@ -279,7 +279,7 @@ static int process_one_buffer(struct btrfs_root *log,
                                                log->fs_info->extent_root,
                                                eb->start, eb->len);
 
-       if (btrfs_buffer_uptodate(eb, gen)) {
+       if (btrfs_buffer_uptodate(eb, gen, 0)) {
                if (wc->write)
                        btrfs_write_tree_block(eb);
                if (wc->wait)

diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c
index 759d024..1411b99 100644 (file)
--- a/fs/btrfs/volumes.c
+++ b/fs/btrfs/volumes.c
@@ -3324,12 +3324,14 @@ static int __btrfs_alloc_chunk(struct btrfs_trans_handle *trans,
        stripe_size = devices_info[ndevs-1].max_avail;
        num_stripes = ndevs * dev_stripes;
 
-       if (stripe_size * num_stripes > max_chunk_size * ncopies) {
+       if (stripe_size * ndevs > max_chunk_size * ncopies) {
                stripe_size = max_chunk_size * ncopies;
-               do_div(stripe_size, num_stripes);
+               do_div(stripe_size, ndevs);
        }
 
        do_div(stripe_size, dev_stripes);
+
+       /* align to BTRFS_STRIPE_LEN */
        do_div(stripe_size, BTRFS_STRIPE_LEN);
        stripe_size *= BTRFS_STRIPE_LEN;
 
@@ -3805,10 +3807,11 @@ static int __btrfs_map_block(struct btrfs_mapping_tree *map_tree, int rw,
                else if (mirror_num)
                        stripe_index += mirror_num - 1;
                else {
+                       int old_stripe_index = stripe_index;
                        stripe_index = find_live_mirror(map, stripe_index,
                                              map->sub_stripes, stripe_index +
                                              current->pid % map->sub_stripes);
-                       mirror_num = stripe_index + 1;
+                       mirror_num = stripe_index - old_stripe_index + 1;
                }
        } else {
                /*
@@ -4350,8 +4353,10 @@ static int open_seed_devices(struct btrfs_root *root, u8 *fsid)
 
        ret = __btrfs_open_devices(fs_devices, FMODE_READ,
                                   root->fs_info->bdev_holder);
-       if (ret)
+       if (ret) {
+               free_fs_devices(fs_devices);
                goto out;
+       }
 
        if (!fs_devices->seeding) {
                __btrfs_close_devices(fs_devices);

diff --git a/fs/buffer.c b/fs/buffer.c
index 36d6665..351e18e 100644 (file)
--- a/fs/buffer.c
+++ b/fs/buffer.c
@@ -985,7 +985,6 @@ grow_dev_page(struct block_device *bdev, sector_t block,
        return page;
 
 failed:
-       BUG();
        unlock_page(page);
        page_cache_release(page);
        return NULL;

diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c
index d342128..ca6a379 100644 (file)
--- a/fs/cifs/cifsfs.c
+++ b/fs/cifs/cifsfs.c
@@ -370,13 +370,13 @@ cifs_show_options(struct seq_file *s, struct dentry *root)
                                   (int)(srcaddr->sa_family));
        }
 
-       seq_printf(s, ",uid=%d", cifs_sb->mnt_uid);
+       seq_printf(s, ",uid=%u", cifs_sb->mnt_uid);
        if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_OVERR_UID)
                seq_printf(s, ",forceuid");
        else
                seq_printf(s, ",noforceuid");
 
-       seq_printf(s, ",gid=%d", cifs_sb->mnt_gid);
+       seq_printf(s, ",gid=%u", cifs_sb->mnt_gid);
        if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_OVERR_GID)
                seq_printf(s, ",forcegid");
        else
@@ -434,11 +434,15 @@ cifs_show_options(struct seq_file *s, struct dentry *root)
                seq_printf(s, ",noperm");
        if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_STRICT_IO)
                seq_printf(s, ",strictcache");
+       if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_CIFS_BACKUPUID)
+               seq_printf(s, ",backupuid=%u", cifs_sb->mnt_backupuid);
+       if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_CIFS_BACKUPGID)
+               seq_printf(s, ",backupgid=%u", cifs_sb->mnt_backupgid);
 
-       seq_printf(s, ",rsize=%d", cifs_sb->rsize);
-       seq_printf(s, ",wsize=%d", cifs_sb->wsize);
+       seq_printf(s, ",rsize=%u", cifs_sb->rsize);
+       seq_printf(s, ",wsize=%u", cifs_sb->wsize);
        /* convert actimeo and display it in seconds */
-               seq_printf(s, ",actimeo=%lu", cifs_sb->actimeo / HZ);
+       seq_printf(s, ",actimeo=%lu", cifs_sb->actimeo / HZ);
 
        return 0;
 }

diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h
index d1389bb..6536535 100644 (file)
--- a/fs/cifs/cifsfs.h
+++ b/fs/cifs/cifsfs.h
@@ -125,5 +125,5 @@ extern long cifs_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
 extern const struct export_operations cifs_export_ops;
 #endif /* CONFIG_CIFS_NFSD_EXPORT */
 
-#define CIFS_VERSION   "1.77"
+#define CIFS_VERSION   "1.78"
 #endif                         /* _CIFSFS_H */

diff --git a/fs/cifs/cifssmb.c b/fs/cifs/cifssmb.c
index f52c5ab..da2f544 100644 (file)
--- a/fs/cifs/cifssmb.c
+++ b/fs/cifs/cifssmb.c
@@ -4844,8 +4844,12 @@ parse_DFS_referrals(TRANSACTION2_GET_DFS_REFER_RSP *pSMBr,
                max_len = data_end - temp;
                node->node_name = cifs_strndup_from_utf16(temp, max_len,
                                                is_unicode, nls_codepage);
-               if (!node->node_name)
+               if (!node->node_name) {
                        rc = -ENOMEM;
+                       goto parse_DFS_referrals_exit;
+               }
+
+               ref++;
        }
 
 parse_DFS_referrals_exit:

diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c
index f31dc9a..5dcc551 100644 (file)
--- a/fs/cifs/connect.c
+++ b/fs/cifs/connect.c
@@ -215,6 +215,8 @@ static const match_table_t cifs_mount_option_tokens = {
 
        { Opt_ignore, "cred" },
        { Opt_ignore, "credentials" },
+       { Opt_ignore, "cred=%s" },
+       { Opt_ignore, "credentials=%s" },
        { Opt_ignore, "guest" },
        { Opt_ignore, "rw" },
        { Opt_ignore, "ro" },
@@ -2183,6 +2185,7 @@ cifs_get_tcp_session(struct smb_vol *volume_info)
        tcp_ses->session_estab = false;
        tcp_ses->sequence_number = 0;
        tcp_ses->lstrp = jiffies;
+       spin_lock_init(&tcp_ses->req_lock);
        INIT_LIST_HEAD(&tcp_ses->tcp_ses_list);
        INIT_LIST_HEAD(&tcp_ses->smb_ses_list);
        INIT_DELAYED_WORK(&tcp_ses->echo, cifs_echo_request);
@@ -3228,10 +3231,6 @@ void cifs_setup_cifs_sb(struct smb_vol *pvolume_info,
 
        cifs_sb->mnt_uid = pvolume_info->linux_uid;
        cifs_sb->mnt_gid = pvolume_info->linux_gid;
-       if (pvolume_info->backupuid_specified)
-               cifs_sb->mnt_backupuid = pvolume_info->backupuid;
-       if (pvolume_info->backupgid_specified)
-               cifs_sb->mnt_backupgid = pvolume_info->backupgid;
        cifs_sb->mnt_file_mode = pvolume_info->file_mode;
        cifs_sb->mnt_dir_mode = pvolume_info->dir_mode;
        cFYI(1, "file mode: 0x%hx  dir mode: 0x%hx",
@@ -3262,10 +3261,14 @@ void cifs_setup_cifs_sb(struct smb_vol *pvolume_info,
                cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_RWPIDFORWARD;
        if (pvolume_info->cifs_acl)
                cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_CIFS_ACL;
-       if (pvolume_info->backupuid_specified)
+       if (pvolume_info->backupuid_specified) {
                cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_CIFS_BACKUPUID;
-       if (pvolume_info->backupgid_specified)
+               cifs_sb->mnt_backupuid = pvolume_info->backupuid;
+       }
+       if (pvolume_info->backupgid_specified) {
                cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_CIFS_BACKUPGID;
+               cifs_sb->mnt_backupgid = pvolume_info->backupgid;
+       }
        if (pvolume_info->override_uid)
                cifs_sb->mnt_cifs_flags |= CIFS_MOUNT_OVERR_UID;
        if (pvolume_info->override_gid)
@@ -3614,22 +3617,6 @@ cifs_get_volume_info(char *mount_data, const char *devname)
        return volume_info;
 }
 
-/* make sure ra_pages is a multiple of rsize */
-static inline unsigned int
-cifs_ra_pages(struct cifs_sb_info *cifs_sb)
-{
-       unsigned int reads;
-       unsigned int rsize_pages = cifs_sb->rsize / PAGE_CACHE_SIZE;
-
-       if (rsize_pages >= default_backing_dev_info.ra_pages)
-               return default_backing_dev_info.ra_pages;
-       else if (rsize_pages == 0)
-               return rsize_pages;
-
-       reads = default_backing_dev_info.ra_pages / rsize_pages;
-       return reads * rsize_pages;
-}
-
 int
 cifs_mount(struct cifs_sb_info *cifs_sb, struct smb_vol *volume_info)
 {
@@ -3717,7 +3704,7 @@ try_mount_again:
        cifs_sb->rsize = cifs_negotiate_rsize(tcon, volume_info);
 
        /* tune readahead according to rsize */
-       cifs_sb->bdi.ra_pages = cifs_ra_pages(cifs_sb);
+       cifs_sb->bdi.ra_pages = cifs_sb->rsize / PAGE_CACHE_SIZE;
 
 remote_path_check:
 #ifdef CONFIG_CIFS_DFS_UPCALL

diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c
index d172c8e..ec4e9a2 100644 (file)
--- a/fs/cifs/dir.c
+++ b/fs/cifs/dir.c
@@ -668,12 +668,19 @@ cifs_d_revalidate(struct dentry *direntry, struct nameidata *nd)
                        return 0;
                else {
                        /*
-                        * Forcibly invalidate automounting directory inodes
-                        * (remote DFS directories) so to have them
-                        * instantiated again for automount
+                        * If the inode wasn't known to be a dfs entry when
+                        * the dentry was instantiated, such as when created
+                        * via ->readdir(), it needs to be set now since the
+                        * attributes will have been updated by
+                        * cifs_revalidate_dentry().
                         */
-                       if (IS_AUTOMOUNT(direntry->d_inode))
-                               return 0;
+                       if (IS_AUTOMOUNT(direntry->d_inode) &&
+                          !(direntry->d_flags & DCACHE_NEED_AUTOMOUNT)) {
+                               spin_lock(&direntry->d_lock);
+                               direntry->d_flags |= DCACHE_NEED_AUTOMOUNT;
+                               spin_unlock(&direntry->d_lock);
+                       }
+
                        return 1;
                }
        }

diff --git a/fs/cifs/file.c b/fs/cifs/file.c
index fae765d..81725e9 100644 (file)
--- a/fs/cifs/file.c
+++ b/fs/cifs/file.c
@@ -2178,7 +2178,7 @@ cifs_iovec_write(struct file *file, const struct iovec *iov,
        unsigned long nr_pages, i;
        size_t copied, len, cur_len;
        ssize_t total_written = 0;
-       loff_t offset = *poffset;
+       loff_t offset;
        struct iov_iter it;
        struct cifsFileInfo *open_file;
        struct cifs_tcon *tcon;
@@ -2200,6 +2200,7 @@ cifs_iovec_write(struct file *file, const struct iovec *iov,
        cifs_sb = CIFS_SB(file->f_path.dentry->d_sb);
        open_file = file->private_data;
        tcon = tlink_tcon(open_file->tlink);
+       offset = *poffset;
 
        if (cifs_sb->mnt_cifs_flags & CIFS_MOUNT_RWPIDFORWARD)
                pid = open_file->pid;

diff --git a/fs/dcache.c b/fs/dcache.c
index b60ddc4..b80531c 100644 (file)
--- a/fs/dcache.c
+++ b/fs/dcache.c
@@ -141,18 +141,29 @@ int proc_nr_dentry(ctl_table *table, int write, void __user *buffer,
  * Compare 2 name strings, return 0 if they match, otherwise non-zero.
  * The strings are both count bytes long, and count is non-zero.
  */
+#ifdef CONFIG_DCACHE_WORD_ACCESS
+
+#include <asm/word-at-a-time.h>
+/*
+ * NOTE! 'cs' and 'scount' come from a dentry, so it has a
+ * aligned allocation for this particular component. We don't
+ * strictly need the load_unaligned_zeropad() safety, but it
+ * doesn't hurt either.
+ *
+ * In contrast, 'ct' and 'tcount' can be from a pathname, and do
+ * need the careful unaligned handling.
+ */
 static inline int dentry_cmp(const unsigned char *cs, size_t scount,
                                const unsigned char *ct, size_t tcount)
 {
-#ifdef CONFIG_DCACHE_WORD_ACCESS
        unsigned long a,b,mask;
 
        if (unlikely(scount != tcount))
                return 1;
 
        for (;;) {
-               a = *(unsigned long *)cs;
-               b = *(unsigned long *)ct;
+               a = load_unaligned_zeropad(cs);
+               b = load_unaligned_zeropad(ct);
                if (tcount < sizeof(unsigned long))
                        break;
                if (unlikely(a != b))
@@ -165,7 +176,13 @@ static inline int dentry_cmp(const unsigned char *cs, size_t scount,
        }
        mask = ~(~0ul << tcount*8);
        return unlikely(!!((a ^ b) & mask));
+}
+
 #else
+
+static inline int dentry_cmp(const unsigned char *cs, size_t scount,
+                               const unsigned char *ct, size_t tcount)
+{
        if (scount != tcount)
                return 1;
 
@@ -177,9 +194,10 @@ static inline int dentry_cmp(const unsigned char *cs, size_t scount,
                tcount--;
        } while (tcount);
        return 0;
-#endif
 }
 
+#endif
+
 static void __d_free(struct rcu_head *head)
 {
        struct dentry *dentry = container_of(head, struct dentry, d_u.d_rcu);

diff --git a/fs/dlm/lock.c b/fs/dlm/lock.c
index fa5c07d..4c58d4a 100644 (file)
--- a/fs/dlm/lock.c
+++ b/fs/dlm/lock.c
@@ -1737,6 +1737,18 @@ static int _can_be_granted(struct dlm_rsb *r, struct dlm_lkb *lkb, int now)
                return 1;
 
        /*
+        * Even if the convert is compat with all granted locks,
+        * QUECVT forces it behind other locks on the convert queue.
+        */
+
+       if (now && conv && (lkb->lkb_exflags & DLM_LKF_QUECVT)) {
+               if (list_empty(&r->res_convertqueue))
+                       return 1;
+               else
+                       goto out;
+       }
+
+       /*
         * The NOORDER flag is set to avoid the standard vms rules on grant
         * order.
         */

diff --git a/fs/eventpoll.c b/fs/eventpoll.c
index 739b098..c0b3c70 100644 (file)
--- a/fs/eventpoll.c
+++ b/fs/eventpoll.c
@@ -1663,8 +1663,10 @@ SYSCALL_DEFINE4(epoll_ctl, int, epfd, int, op, int, fd,
        if (op == EPOLL_CTL_ADD) {
                if (is_file_epoll(tfile)) {
                        error = -ELOOP;
-                       if (ep_loop_check(ep, tfile) != 0)
+                       if (ep_loop_check(ep, tfile) != 0) {
+                               clear_tfile_check_list();
                                goto error_tgt_fput;
+                       }
                } else
                        list_add(&tfile->f_tfile_llink, &tfile_check_list);
        }

diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index 6da1935..e1fb1d5 100644 (file)
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -1597,7 +1597,9 @@ static int parse_options(char *options, struct super_block *sb,
                         unsigned int *journal_ioprio,
                         int is_remount)
 {
+#ifdef CONFIG_QUOTA
        struct ext4_sb_info *sbi = EXT4_SB(sb);
+#endif
        char *p;
        substring_t args[MAX_OPT_ARGS];
        int token;

diff --git a/fs/gfs2/lock_dlm.c b/fs/gfs2/lock_dlm.c
index f8411bd..5f5e70e 100644 (file)
--- a/fs/gfs2/lock_dlm.c
+++ b/fs/gfs2/lock_dlm.c
@@ -200,10 +200,11 @@ static int make_mode(const unsigned int lmstate)
        return -1;
 }
 
-static u32 make_flags(const u32 lkid, const unsigned int gfs_flags,
+static u32 make_flags(struct gfs2_glock *gl, const unsigned int gfs_flags,
                      const int req)
 {
        u32 lkf = DLM_LKF_VALBLK;
+       u32 lkid = gl->gl_lksb.sb_lkid;
 
        if (gfs_flags & LM_FLAG_TRY)
                lkf |= DLM_LKF_NOQUEUE;
@@ -227,8 +228,11 @@ static u32 make_flags(const u32 lkid, const unsigned int gfs_flags,
                        BUG();
        }
 
-       if (lkid != 0) 
+       if (lkid != 0) {
                lkf |= DLM_LKF_CONVERT;
+               if (test_bit(GLF_BLOCKING, &gl->gl_flags))
+                       lkf |= DLM_LKF_QUECVT;
+       }
 
        return lkf;
 }
@@ -250,7 +254,7 @@ static int gdlm_lock(struct gfs2_glock *gl, unsigned int req_state,
        char strname[GDLM_STRNAME_BYTES] = "";
 
        req = make_mode(req_state);
-       lkf = make_flags(gl->gl_lksb.sb_lkid, flags, req);
+       lkf = make_flags(gl, flags, req);
        gfs2_glstats_inc(gl, GFS2_LKS_DCOUNT);
        gfs2_sbstats_inc(gl, GFS2_LKS_DCOUNT);
        if (gl->gl_lksb.sb_lkid) {

diff --git a/fs/hfsplus/catalog.c b/fs/hfsplus/catalog.c
index 4dfbfec..ec2a9c2 100644 (file)
--- a/fs/hfsplus/catalog.c
+++ b/fs/hfsplus/catalog.c
@@ -366,6 +366,10 @@ int hfsplus_rename_cat(u32 cnid,
        err = hfs_brec_find(&src_fd);
        if (err)
                goto out;
+       if (src_fd.entrylength > sizeof(entry) || src_fd.entrylength < 0) {
+               err = -EIO;
+               goto out;
+       }
 
        hfs_bnode_read(src_fd.bnode, &entry, src_fd.entryoffset,
                                src_fd.entrylength);

diff --git a/fs/hfsplus/dir.c b/fs/hfsplus/dir.c
index 88e155f..26b53fb 100644 (file)
--- a/fs/hfsplus/dir.c
+++ b/fs/hfsplus/dir.c
@@ -150,6 +150,11 @@ static int hfsplus_readdir(struct file *filp, void *dirent, filldir_t filldir)
                filp->f_pos++;
                /* fall through */
        case 1:
+               if (fd.entrylength > sizeof(entry) || fd.entrylength < 0) {
+                       err = -EIO;
+                       goto out;
+               }
+
                hfs_bnode_read(fd.bnode, &entry, fd.entryoffset,
                        fd.entrylength);
                if (be16_to_cpu(entry.type) != HFSPLUS_FOLDER_THREAD) {
@@ -181,6 +186,12 @@ static int hfsplus_readdir(struct file *filp, void *dirent, filldir_t filldir)
                        err = -EIO;
                        goto out;
                }
+
+               if (fd.entrylength > sizeof(entry) || fd.entrylength < 0) {
+                       err = -EIO;
+                       goto out;
+               }
+
                hfs_bnode_read(fd.bnode, &entry, fd.entryoffset,
                        fd.entrylength);
                type = be16_to_cpu(entry.type);

diff --git a/fs/hugetlbfs/inode.c b/fs/hugetlbfs/inode.c
index 28cf06e..001ef01 100644 (file)
--- a/fs/hugetlbfs/inode.c
+++ b/fs/hugetlbfs/inode.c
@@ -485,6 +485,7 @@ static struct inode *hugetlbfs_get_root(struct super_block *sb,
                inode->i_fop = &simple_dir_operations;
                /* directory inodes start off with i_nlink == 2 (for "." entry) */
                inc_nlink(inode);
+               lockdep_annotate_inode_mutex_key(inode);
        }
        return inode;
 }

diff --git a/fs/jbd2/commit.c b/fs/jbd2/commit.c
index 806525a..840f70f 100644 (file)
--- a/fs/jbd2/commit.c
+++ b/fs/jbd2/commit.c
@@ -723,7 +723,7 @@ start_journal_io:
        if (commit_transaction->t_need_data_flush &&
            (journal->j_fs_dev != journal->j_dev) &&
            (journal->j_flags & JBD2_BARRIER))
-               blkdev_issue_flush(journal->j_fs_dev, GFP_KERNEL, NULL);
+               blkdev_issue_flush(journal->j_fs_dev, GFP_NOFS, NULL);
 
        /* Done it all: now write the commit record asynchronously. */
        if (JBD2_HAS_INCOMPAT_FEATURE(journal,
@@ -859,7 +859,7 @@ wait_for_iobuf:
        if (JBD2_HAS_INCOMPAT_FEATURE(journal,
                                      JBD2_FEATURE_INCOMPAT_ASYNC_COMMIT) &&
            journal->j_flags & JBD2_BARRIER) {
-               blkdev_issue_flush(journal->j_dev, GFP_KERNEL, NULL);
+               blkdev_issue_flush(journal->j_dev, GFP_NOFS, NULL);
        }
 
        if (err)

diff --git a/fs/namei.c b/fs/namei.c
index 0062dd1..c427919 100644 (file)
--- a/fs/namei.c
+++ b/fs/namei.c
@@ -1429,7 +1429,7 @@ unsigned int full_name_hash(const unsigned char *name, unsigned int len)
        unsigned long hash = 0;
 
        for (;;) {
-               a = *(unsigned long *)name;
+               a = load_unaligned_zeropad(name);
                if (len < sizeof(unsigned long))
                        break;
                hash += a;
@@ -1459,7 +1459,7 @@ static inline unsigned long hash_name(const char *name, unsigned int *hashp)
        do {
                hash = (hash + a) * 9;
                len += sizeof(unsigned long);
-               a = *(unsigned long *)(name+len);
+               a = load_unaligned_zeropad(name+len);
                /* Do we have any NUL or '/' bytes in this word? */
                mask = has_zero(a) | has_zero(a ^ REPEAT_BYTE('/'));
        } while (!mask);

diff --git a/fs/nfs/blocklayout/blocklayout.c b/fs/nfs/blocklayout/blocklayout.c
index 9c94297..7f6a23f 100644 (file)
--- a/fs/nfs/blocklayout/blocklayout.c
+++ b/fs/nfs/blocklayout/blocklayout.c
@@ -38,6 +38,8 @@
 #include <linux/buffer_head.h> /* various write calls */
 #include <linux/prefetch.h>
 
+#include "../pnfs.h"
+#include "../internal.h"
 #include "blocklayout.h"
 
 #define NFSDBG_FACILITY        NFSDBG_PNFS_LD
@@ -868,7 +870,7 @@ nfs4_blk_get_deviceinfo(struct nfs_server *server, const struct nfs_fh *fh,
         * GETDEVICEINFO's maxcount
         */
        max_resp_sz = server->nfs_client->cl_session->fc_attrs.max_resp_sz;
-       max_pages = max_resp_sz >> PAGE_SHIFT;
+       max_pages = nfs_page_array_len(0, max_resp_sz);
        dprintk("%s max_resp_sz %u max_pages %d\n",
                __func__, max_resp_sz, max_pages);
 

diff --git a/fs/nfs/client.c b/fs/nfs/client.c
index da7b5e4..60f7e4e 100644 (file)
--- a/fs/nfs/client.c
+++ b/fs/nfs/client.c
@@ -1729,7 +1729,8 @@ error:
  */
 struct nfs_server *nfs_clone_server(struct nfs_server *source,
                                    struct nfs_fh *fh,
-                                   struct nfs_fattr *fattr)
+                                   struct nfs_fattr *fattr,
+                                   rpc_authflavor_t flavor)
 {
        struct nfs_server *server;
        struct nfs_fattr *fattr_fsinfo;
@@ -1758,7 +1759,7 @@ struct nfs_server *nfs_clone_server(struct nfs_server *source,
 
        error = nfs_init_server_rpcclient(server,
                        source->client->cl_timeout,
-                       source->client->cl_auth->au_flavor);
+                       flavor);
        if (error < 0)
                goto out_free_server;
        if (!IS_ERR(source->client_acl))

diff --git a/fs/nfs/dir.c b/fs/nfs/dir.c
index 4aaf031..8789210 100644 (file)
--- a/fs/nfs/dir.c
+++ b/fs/nfs/dir.c
@@ -1429,7 +1429,7 @@ static struct dentry *nfs_atomic_lookup(struct inode *dir, struct dentry *dentry
        }
 
        open_flags = nd->intent.open.flags;
-       attr.ia_valid = 0;
+       attr.ia_valid = ATTR_OPEN;
 
        ctx = create_nfs_open_context(dentry, open_flags);
        res = ERR_CAST(ctx);
@@ -1536,7 +1536,7 @@ static int nfs_open_revalidate(struct dentry *dentry, struct nameidata *nd)
        if (IS_ERR(ctx))
                goto out;
 
-       attr.ia_valid = 0;
+       attr.ia_valid = ATTR_OPEN;
        if (openflags & O_TRUNC) {
                attr.ia_valid |= ATTR_SIZE;
                attr.ia_size = 0;

diff --git a/fs/nfs/idmap.c b/fs/nfs/idmap.c
index b7f348b..ba3019f 100644 (file)
--- a/fs/nfs/idmap.c
+++ b/fs/nfs/idmap.c
@@ -554,12 +554,16 @@ static int rpc_pipefs_event(struct notifier_block *nb, unsigned long event,
        struct nfs_client *clp;
        int error = 0;
 
+       if (!try_module_get(THIS_MODULE))
+               return 0;
+
        while ((clp = nfs_get_client_for_event(sb->s_fs_info, event))) {
                error = __rpc_pipefs_event(clp, event, sb);
                nfs_put_client(clp);
                if (error)
                        break;
        }
+       module_put(THIS_MODULE);
        return error;
 }
 

diff --git a/fs/nfs/internal.h b/fs/nfs/internal.h
index 2476dc6..b777bda 100644 (file)
--- a/fs/nfs/internal.h
+++ b/fs/nfs/internal.h
@@ -165,7 +165,8 @@ extern struct nfs_server *nfs4_create_referral_server(struct nfs_clone_mount *,
 extern void nfs_free_server(struct nfs_server *server);
 extern struct nfs_server *nfs_clone_server(struct nfs_server *,
                                           struct nfs_fh *,
-                                          struct nfs_fattr *);
+                                          struct nfs_fattr *,
+                                          rpc_authflavor_t);
 extern void nfs_mark_client_ready(struct nfs_client *clp, int state);
 extern int nfs4_check_client_ready(struct nfs_client *clp);
 extern struct nfs_client *nfs4_set_ds_client(struct nfs_client* mds_clp,
@@ -186,10 +187,10 @@ static inline void nfs_fs_proc_exit(void)
 
 /* nfs4namespace.c */
 #ifdef CONFIG_NFS_V4
-extern struct vfsmount *nfs_do_refmount(struct dentry *dentry);
+extern struct vfsmount *nfs_do_refmount(struct rpc_clnt *client, struct dentry *dentry);
 #else
 static inline
-struct vfsmount *nfs_do_refmount(struct dentry *dentry)
+struct vfsmount *nfs_do_refmount(struct rpc_clnt *client, struct dentry *dentry)
 {
        return ERR_PTR(-ENOENT);
 }
@@ -234,7 +235,6 @@ extern const u32 nfs41_maxwrite_overhead;
 /* nfs4proc.c */
 #ifdef CONFIG_NFS_V4
 extern struct rpc_procinfo nfs4_procedures[];
-void nfs_fixup_secinfo_attributes(struct nfs_fattr *, struct nfs_fh *);
 #endif
 
 extern int nfs4_init_ds_session(struct nfs_client *clp);

diff --git a/fs/nfs/namespace.c b/fs/nfs/namespace.c
index 1807866..d51868e 100644 (file)
--- a/fs/nfs/namespace.c
+++ b/fs/nfs/namespace.c
@@ -148,66 +148,31 @@ rpc_authflavor_t nfs_find_best_sec(struct nfs4_secinfo_flavors *flavors)
        return pseudoflavor;
 }
 
-static int nfs_negotiate_security(const struct dentry *parent,
-                                 const struct dentry *dentry,
-                                 rpc_authflavor_t *flavor)
+static struct rpc_clnt *nfs_lookup_mountpoint(struct inode *dir,
+                                             struct qstr *name,
+                                             struct nfs_fh *fh,
+                                             struct nfs_fattr *fattr)
 {
-       struct page *page;
-       struct nfs4_secinfo_flavors *flavors;
-       int (*secinfo)(struct inode *, const struct qstr *, struct nfs4_secinfo_flavors *);
-       int ret = -EPERM;
-
-       secinfo = NFS_PROTO(parent->d_inode)->secinfo;
-       if (secinfo != NULL) {
-               page = alloc_page(GFP_KERNEL);
-               if (!page) {
-                       ret = -ENOMEM;
-                       goto out;
-               }
-               flavors = page_address(page);
-               ret = secinfo(parent->d_inode, &dentry->d_name, flavors);
-               *flavor = nfs_find_best_sec(flavors);
-               put_page(page);
-       }
-
-out:
-       return ret;
-}
-
-static int nfs_lookup_with_sec(struct nfs_server *server, struct dentry *parent,
-                              struct dentry *dentry, struct path *path,
-                              struct nfs_fh *fh, struct nfs_fattr *fattr,
-                              rpc_authflavor_t *flavor)
-{
-       struct rpc_clnt *clone;
-       struct rpc_auth *auth;
        int err;
 
-       err = nfs_negotiate_security(parent, path->dentry, flavor);
-       if (err < 0)
-               goto out;
-       clone  = rpc_clone_client(server->client);
-       auth   = rpcauth_create(*flavor, clone);
-       if (!auth) {
-               err = -EIO;
-               goto out_shutdown;
-       }
-       err = server->nfs_client->rpc_ops->lookup(clone, parent->d_inode,
-                                                 &path->dentry->d_name,
-                                                 fh, fattr);
-out_shutdown:
-       rpc_shutdown_client(clone);
-out:
-       return err;
+       if (NFS_PROTO(dir)->version == 4)
+               return nfs4_proc_lookup_mountpoint(dir, name, fh, fattr);
+
+       err = NFS_PROTO(dir)->lookup(NFS_SERVER(dir)->client, dir, name, fh, fattr);
+       if (err)
+               return ERR_PTR(err);
+       return rpc_clone_client(NFS_SERVER(dir)->client);
 }
 #else /* CONFIG_NFS_V4 */
-static inline int nfs_lookup_with_sec(struct nfs_server *server,
-                                     struct dentry *parent, struct dentry *dentry,
-                                     struct path *path, struct nfs_fh *fh,
-                                     struct nfs_fattr *fattr,
-                                     rpc_authflavor_t *flavor)
+static inline struct rpc_clnt *nfs_lookup_mountpoint(struct inode *dir,
+                                                    struct qstr *name,
+                                                    struct nfs_fh *fh,
+                                                    struct nfs_fattr *fattr)
 {
-       return -EPERM;
+       int err = NFS_PROTO(dir)->lookup(NFS_SERVER(dir)->client, dir, name, fh, fattr);
+       if (err)
+               return ERR_PTR(err);
+       return rpc_clone_client(NFS_SERVER(dir)->client);
 }
 #endif /* CONFIG_NFS_V4 */
 
@@ -226,12 +191,10 @@ static inline int nfs_lookup_with_sec(struct nfs_server *server,
 struct vfsmount *nfs_d_automount(struct path *path)
 {
        struct vfsmount *mnt;
-       struct nfs_server *server = NFS_SERVER(path->dentry->d_inode);
        struct dentry *parent;
        struct nfs_fh *fh = NULL;
        struct nfs_fattr *fattr = NULL;
-       int err;
-       rpc_authflavor_t flavor = RPC_AUTH_UNIX;
+       struct rpc_clnt *client;
 
        dprintk("--> nfs_d_automount()\n");
 
@@ -249,21 +212,19 @@ struct vfsmount *nfs_d_automount(struct path *path)
 
        /* Look it up again to get its attributes */
        parent = dget_parent(path->dentry);
-       err = server->nfs_client->rpc_ops->lookup(server->client, parent->d_inode,
-                                                 &path->dentry->d_name,
-                                                 fh, fattr);
-       if (err == -EPERM && NFS_PROTO(parent->d_inode)->secinfo != NULL)
-               err = nfs_lookup_with_sec(server, parent, path->dentry, path, fh, fattr, &flavor);
+       client = nfs_lookup_mountpoint(parent->d_inode, &path->dentry->d_name, fh, fattr);
        dput(parent);
-       if (err != 0) {
-               mnt = ERR_PTR(err);
+       if (IS_ERR(client)) {
+               mnt = ERR_CAST(client);
                goto out;
        }
 
        if (fattr->valid & NFS_ATTR_FATTR_V4_REFERRAL)
-               mnt = nfs_do_refmount(path->dentry);
+               mnt = nfs_do_refmount(client, path->dentry);
        else
-               mnt = nfs_do_submount(path->dentry, fh, fattr, flavor);
+               mnt = nfs_do_submount(path->dentry, fh, fattr, client->cl_auth->au_flavor);
+       rpc_shutdown_client(client);
+
        if (IS_ERR(mnt))
                goto out;
 

diff --git a/fs/nfs/nfs4_fs.h b/fs/nfs/nfs4_fs.h
index 97ecc86..8d75021 100644 (file)
--- a/fs/nfs/nfs4_fs.h
+++ b/fs/nfs/nfs4_fs.h
@@ -59,6 +59,7 @@ struct nfs_unique_id {
 
 #define NFS_SEQID_CONFIRMED 1
 struct nfs_seqid_counter {
+       ktime_t create_time;
        int owner_id;
        int flags;
        u32 counter;
@@ -204,6 +205,9 @@ struct nfs4_state_maintenance_ops {
 extern const struct dentry_operations nfs4_dentry_operations;
 extern const struct inode_operations nfs4_dir_inode_operations;
 
+/* nfs4namespace.c */
+struct rpc_clnt *nfs4_create_sec_client(struct rpc_clnt *, struct inode *, struct qstr *);
+
 /* nfs4proc.c */
 extern int nfs4_proc_setclientid(struct nfs_client *, u32, unsigned short, struct rpc_cred *, struct nfs4_setclientid_res *);
 extern int nfs4_proc_setclientid_confirm(struct nfs_client *, struct nfs4_setclientid_res *arg, struct rpc_cred *);
@@ -212,8 +216,11 @@ extern int nfs4_init_clientid(struct nfs_client *, struct rpc_cred *);
 extern int nfs41_init_clientid(struct nfs_client *, struct rpc_cred *);
 extern int nfs4_do_close(struct nfs4_state *state, gfp_t gfp_mask, int wait, bool roc);
 extern int nfs4_server_capabilities(struct nfs_server *server, struct nfs_fh *fhandle);
-extern int nfs4_proc_fs_locations(struct inode *dir, const struct qstr *name,
-               struct nfs4_fs_locations *fs_locations, struct page *page);
+extern int nfs4_proc_fs_locations(struct rpc_clnt *, struct inode *, const struct qstr *,
+                                 struct nfs4_fs_locations *, struct page *);
+extern struct rpc_clnt *nfs4_proc_lookup_mountpoint(struct inode *, struct qstr *,
+                           struct nfs_fh *, struct nfs_fattr *);
+extern int nfs4_proc_secinfo(struct inode *, const struct qstr *, struct nfs4_secinfo_flavors *);
 extern int nfs4_release_lockowner(struct nfs4_lock_state *);
 extern const struct xattr_handler *nfs4_xattr_handlers[];
 

diff --git a/fs/nfs/nfs4filelayoutdev.c b/fs/nfs/nfs4filelayoutdev.c
index a866bbd..c9cff9a 100644 (file)
--- a/fs/nfs/nfs4filelayoutdev.c
+++ b/fs/nfs/nfs4filelayoutdev.c
@@ -699,7 +699,7 @@ get_device_info(struct inode *inode, struct nfs4_deviceid *dev_id, gfp_t gfp_fla
         * GETDEVICEINFO's maxcount
         */
        max_resp_sz = server->nfs_client->cl_session->fc_attrs.max_resp_sz;
-       max_pages = max_resp_sz >> PAGE_SHIFT;
+       max_pages = nfs_page_array_len(0, max_resp_sz);
        dprintk("%s inode %p max_resp_sz %u max_pages %d\n",
                __func__, inode, max_resp_sz, max_pages);
 

diff --git a/fs/nfs/nfs4namespace.c b/fs/nfs/nfs4namespace.c
index 9c8eca3..a7f3ded 100644 (file)
--- a/fs/nfs/nfs4namespace.c
+++ b/fs/nfs/nfs4namespace.c
@@ -52,6 +52,30 @@ Elong:
 }
 
 /*
+ * return the path component of "<server>:<path>"
+ *  nfspath - the "<server>:<path>" string
+ *  end - one past the last char that could contain "<server>:"
+ * returns NULL on failure
+ */
+static char *nfs_path_component(const char *nfspath, const char *end)
+{
+       char *p;
+
+       if (*nfspath == '[') {
+               /* parse [] escaped IPv6 addrs */
+               p = strchr(nfspath, ']');
+               if (p != NULL && ++p < end && *p == ':')
+                       return p + 1;
+       } else {
+               /* otherwise split on first colon */
+               p = strchr(nfspath, ':');
+               if (p != NULL && p < end)
+                       return p + 1;
+       }
+       return NULL;
+}
+
+/*
  * Determine the mount path as a string
  */
 static char *nfs4_path(struct dentry *dentry, char *buffer, ssize_t buflen)
@@ -59,9 +83,9 @@ static char *nfs4_path(struct dentry *dentry, char *buffer, ssize_t buflen)
        char *limit;
        char *path = nfs_path(&limit, dentry, buffer, buflen);
        if (!IS_ERR(path)) {
-               char *colon = strchr(path, ':');
-               if (colon && colon < limit)
-                       path = colon + 1;
+               char *path_component = nfs_path_component(path, limit);
+               if (path_component)
+                       return path_component;
        }
        return path;
 }
@@ -108,6 +132,58 @@ static size_t nfs_parse_server_name(char *string, size_t len,
        return ret;
 }
 
+static rpc_authflavor_t nfs4_negotiate_security(struct inode *inode, struct qstr *name)
+{
+       struct page *page;
+       struct nfs4_secinfo_flavors *flavors;
+       rpc_authflavor_t flavor;
+       int err;
+
+       page = alloc_page(GFP_KERNEL);
+       if (!page)
+               return -ENOMEM;
+       flavors = page_address(page);
+
+       err = nfs4_proc_secinfo(inode, name, flavors);
+       if (err < 0) {
+               flavor = err;
+               goto out;
+       }
+
+       flavor = nfs_find_best_sec(flavors);
+
+out:
+       put_page(page);
+       return flavor;
+}
+
+/*
+ * Please call rpc_shutdown_client() when you are done with this client.
+ */
+struct rpc_clnt *nfs4_create_sec_client(struct rpc_clnt *clnt, struct inode *inode,
+                                       struct qstr *name)
+{
+       struct rpc_clnt *clone;
+       struct rpc_auth *auth;
+       rpc_authflavor_t flavor;
+
+       flavor = nfs4_negotiate_security(inode, name);
+       if (flavor < 0)
+               return ERR_PTR(flavor);
+
+       clone = rpc_clone_client(clnt);
+       if (IS_ERR(clone))
+               return clone;
+
+       auth = rpcauth_create(flavor, clone);
+       if (!auth) {
+               rpc_shutdown_client(clone);
+               clone = ERR_PTR(-EIO);
+       }
+
+       return clone;
+}
+
 static struct vfsmount *try_location(struct nfs_clone_mount *mountdata,
                                     char *page, char *page2,
                                     const struct nfs4_fs_location *location)
@@ -224,7 +300,7 @@ out:
  * @dentry - dentry of referral
  *
  */
-struct vfsmount *nfs_do_refmount(struct dentry *dentry)
+struct vfsmount *nfs_do_refmount(struct rpc_clnt *client, struct dentry *dentry)
 {
        struct vfsmount *mnt = ERR_PTR(-ENOMEM);
        struct dentry *parent;
@@ -250,7 +326,7 @@ struct vfsmount *nfs_do_refmount(struct dentry *dentry)
        dprintk("%s: getting locations for %s/%s\n",
                __func__, parent->d_name.name, dentry->d_name.name);
 
-       err = nfs4_proc_fs_locations(parent->d_inode, &dentry->d_name, fs_locations, page);
+       err = nfs4_proc_fs_locations(client, parent->d_inode, &dentry->d_name, fs_locations, page);
        dput(parent);
        if (err != 0 ||
            fs_locations->nlocations <= 0 ||

diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
index f82bde0..99650aa 100644 (file)
--- a/fs/nfs/nfs4proc.c
+++ b/fs/nfs/nfs4proc.c
@@ -838,7 +838,8 @@ static struct nfs4_opendata *nfs4_opendata_alloc(struct dentry *dentry,
        p->o_arg.open_flags = flags;
        p->o_arg.fmode = fmode & (FMODE_READ|FMODE_WRITE);
        p->o_arg.clientid = server->nfs_client->cl_clientid;
-       p->o_arg.id = sp->so_seqid.owner_id;
+       p->o_arg.id.create_time = ktime_to_ns(sp->so_seqid.create_time);
+       p->o_arg.id.uniquifier = sp->so_seqid.owner_id;
        p->o_arg.name = &dentry->d_name;
        p->o_arg.server = server;
        p->o_arg.bitmask = server->attr_bitmask;
@@ -1466,8 +1467,7 @@ static void nfs4_open_prepare(struct rpc_task *task, void *calldata)
                        goto unlock_no_action;
                rcu_read_unlock();
        }
-       /* Update sequence id. */
-       data->o_arg.id = sp->so_seqid.owner_id;
+       /* Update client id. */
        data->o_arg.clientid = sp->so_server->nfs_client->cl_clientid;
        if (data->o_arg.claim == NFS4_OPEN_CLAIM_PREVIOUS) {
                task->tk_msg.rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_OPEN_NOATTR];
@@ -1954,10 +1954,19 @@ static int nfs4_do_setattr(struct inode *inode, struct rpc_cred *cred,
        };
        int err;
        do {
-               err = nfs4_handle_exception(server,
-                               _nfs4_do_setattr(inode, cred, fattr, sattr, state),
-                               &exception);
+               err = _nfs4_do_setattr(inode, cred, fattr, sattr, state);
+               switch (err) {
+               case -NFS4ERR_OPENMODE:
+                       if (state && !(state->state & FMODE_WRITE)) {
+                               err = -EBADF;
+                               if (sattr->ia_valid & ATTR_OPEN)
+                                       err = -EACCES;
+                               goto out;
+                       }
+               }
+               err = nfs4_handle_exception(server, err, &exception);
        } while (exception.retry);
+out:
        return err;
 }
 
@@ -2368,8 +2377,9 @@ static int nfs4_proc_get_root(struct nfs_server *server, struct nfs_fh *fhandle,
  * Note that we'll actually follow the referral later when
  * we detect fsid mismatch in inode revalidation
  */
-static int nfs4_get_referral(struct inode *dir, const struct qstr *name,
-                            struct nfs_fattr *fattr, struct nfs_fh *fhandle)
+static int nfs4_get_referral(struct rpc_clnt *client, struct inode *dir,
+                            const struct qstr *name, struct nfs_fattr *fattr,
+                            struct nfs_fh *fhandle)
 {
        int status = -ENOMEM;
        struct page *page = NULL;
@@ -2382,7 +2392,7 @@ static int nfs4_get_referral(struct inode *dir, const struct qstr *name,
        if (locations == NULL)
                goto out;
 
-       status = nfs4_proc_fs_locations(dir, name, locations, page);
+       status = nfs4_proc_fs_locations(client, dir, name, locations, page);
        if (status != 0)
                goto out;
        /* Make sure server returned a different fsid for the referral */
@@ -2519,39 +2529,84 @@ static int _nfs4_proc_lookup(struct rpc_clnt *clnt, struct inode *dir,
        return status;
 }
 
-void nfs_fixup_secinfo_attributes(struct nfs_fattr *fattr, struct nfs_fh *fh)
+static void nfs_fixup_secinfo_attributes(struct nfs_fattr *fattr)
 {
-       memset(fh, 0, sizeof(struct nfs_fh));
-       fattr->fsid.major = 1;
        fattr->valid |= NFS_ATTR_FATTR_TYPE | NFS_ATTR_FATTR_MODE |
-               NFS_ATTR_FATTR_NLINK | NFS_ATTR_FATTR_FSID | NFS_ATTR_FATTR_MOUNTPOINT;
+               NFS_ATTR_FATTR_NLINK | NFS_ATTR_FATTR_MOUNTPOINT;
        fattr->mode = S_IFDIR | S_IRUGO | S_IXUGO;
        fattr->nlink = 2;
 }
 
-static int nfs4_proc_lookup(struct rpc_clnt *clnt, struct inode *dir, struct qstr *name,
-                           struct nfs_fh *fhandle, struct nfs_fattr *fattr)
+static int nfs4_proc_lookup_common(struct rpc_clnt **clnt, struct inode *dir,
+                                  struct qstr *name, struct nfs_fh *fhandle,
+                                  struct nfs_fattr *fattr)
 {
        struct nfs4_exception exception = { };
+       struct rpc_clnt *client = *clnt;
        int err;
        do {
-               int status;
-
-               status = _nfs4_proc_lookup(clnt, dir, name, fhandle, fattr);
-               switch (status) {
+               err = _nfs4_proc_lookup(client, dir, name, fhandle, fattr);
+               switch (err) {
                case -NFS4ERR_BADNAME:
-                       return -ENOENT;
+                       err = -ENOENT;
+                       goto out;
                case -NFS4ERR_MOVED:
-                       return nfs4_get_referral(dir, name, fattr, fhandle);
+                       err = nfs4_get_referral(client, dir, name, fattr, fhandle);
+                       goto out;
                case -NFS4ERR_WRONGSEC:
-                       nfs_fixup_secinfo_attributes(fattr, fhandle);
+                       err = -EPERM;
+                       if (client != *clnt)
+                               goto out;
+
+                       client = nfs4_create_sec_client(client, dir, name);
+                       if (IS_ERR(client))
+                               return PTR_ERR(client);
+
+                       exception.retry = 1;
+                       break;
+               default:
+                       err = nfs4_handle_exception(NFS_SERVER(dir), err, &exception);
                }
-               err = nfs4_handle_exception(NFS_SERVER(dir),
-                               status, &exception);
        } while (exception.retry);
+
+out:
+       if (err == 0)
+               *clnt = client;
+       else if (client != *clnt)
+               rpc_shutdown_client(client);
+
        return err;
 }
 
+static int nfs4_proc_lookup(struct rpc_clnt *clnt, struct inode *dir, struct qstr *name,
+                           struct nfs_fh *fhandle, struct nfs_fattr *fattr)
+{
+       int status;
+       struct rpc_clnt *client = NFS_CLIENT(dir);
+
+       status = nfs4_proc_lookup_common(&client, dir, name, fhandle, fattr);
+       if (client != NFS_CLIENT(dir)) {
+               rpc_shutdown_client(client);
+               nfs_fixup_secinfo_attributes(fattr);
+       }
+       return status;
+}
+
+struct rpc_clnt *
+nfs4_proc_lookup_mountpoint(struct inode *dir, struct qstr *name,
+                           struct nfs_fh *fhandle, struct nfs_fattr *fattr)
+{
+       int status;
+       struct rpc_clnt *client = rpc_clone_client(NFS_CLIENT(dir));
+
+       status = nfs4_proc_lookup_common(&client, dir, name, fhandle, fattr);
+       if (status < 0) {
+               rpc_shutdown_client(client);
+               return ERR_PTR(status);
+       }
+       return client;
+}
+
 static int _nfs4_proc_access(struct inode *inode, struct nfs_access_entry *entry)
 {
        struct nfs_server *server = NFS_SERVER(inode);
@@ -3619,16 +3674,16 @@ out:
        return ret;
 }
 
-static void nfs4_write_cached_acl(struct inode *inode, const char *buf, size_t acl_len)
+static void nfs4_write_cached_acl(struct inode *inode, struct page **pages, size_t pgbase, size_t acl_len)
 {
        struct nfs4_cached_acl *acl;
 
-       if (buf && acl_len <= PAGE_SIZE) {
+       if (pages && acl_len <= PAGE_SIZE) {
                acl = kmalloc(sizeof(*acl) + acl_len, GFP_KERNEL);
                if (acl == NULL)
                        goto out;
                acl->cached = 1;
-               memcpy(acl->data, buf, acl_len);
+               _copy_from_pages(acl->data, pages, pgbase, acl_len);
        } else {
                acl = kmalloc(sizeof(*acl), GFP_KERNEL);
                if (acl == NULL)
@@ -3661,7 +3716,6 @@ static ssize_t __nfs4_get_acl_uncached(struct inode *inode, void *buf, size_t bu
        struct nfs_getaclres res = {
                .acl_len = buflen,
        };
-       void *resp_buf;
        struct rpc_message msg = {
                .rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_GETACL],
                .rpc_argp = &args,
@@ -3675,24 +3729,27 @@ static ssize_t __nfs4_get_acl_uncached(struct inode *inode, void *buf, size_t bu
        if (npages == 0)
                npages = 1;
 
+       /* Add an extra page to handle the bitmap returned */
+       npages++;
+
        for (i = 0; i < npages; i++) {
                pages[i] = alloc_page(GFP_KERNEL);
                if (!pages[i])
                        goto out_free;
        }
-       if (npages > 1) {
-               /* for decoding across pages */
-               res.acl_scratch = alloc_page(GFP_KERNEL);
-               if (!res.acl_scratch)
-                       goto out_free;
-       }
+
+       /* for decoding across pages */
+       res.acl_scratch = alloc_page(GFP_KERNEL);
+       if (!res.acl_scratch)
+               goto out_free;
+
        args.acl_len = npages * PAGE_SIZE;
        args.acl_pgbase = 0;
+
        /* Let decode_getfacl know not to fail if the ACL data is larger than
         * the page we send as a guess */
        if (buf == NULL)
                res.acl_flags |= NFS4_ACL_LEN_REQUEST;
-       resp_buf = page_address(pages[0]);
 
        dprintk("%s  buf %p buflen %zu npages %d args.acl_len %zu\n",
                __func__, buf, buflen, npages, args.acl_len);
@@ -3703,9 +3760,9 @@ static ssize_t __nfs4_get_acl_uncached(struct inode *inode, void *buf, size_t bu
 
        acl_len = res.acl_len - res.acl_data_offset;
        if (acl_len > args.acl_len)
-               nfs4_write_cached_acl(inode, NULL, acl_len);
+               nfs4_write_cached_acl(inode, NULL, 0, acl_len);
        else
-               nfs4_write_cached_acl(inode, resp_buf + res.acl_data_offset,
+               nfs4_write_cached_acl(inode, pages, res.acl_data_offset,
                                      acl_len);
        if (buf) {
                ret = -ERANGE;
@@ -4558,7 +4615,9 @@ static int _nfs4_do_setlk(struct nfs4_state *state, int cmd, struct file_lock *f
 static int nfs4_lock_reclaim(struct nfs4_state *state, struct file_lock *request)
 {
        struct nfs_server *server = NFS_SERVER(state->inode);
-       struct nfs4_exception exception = { };
+       struct nfs4_exception exception = {
+               .inode = state->inode,
+       };
        int err;
 
        do {
@@ -4576,7 +4635,9 @@ static int nfs4_lock_reclaim(struct nfs4_state *state, struct file_lock *request
 static int nfs4_lock_expired(struct nfs4_state *state, struct file_lock *request)
 {
        struct nfs_server *server = NFS_SERVER(state->inode);
-       struct nfs4_exception exception = { };
+       struct nfs4_exception exception = {
+               .inode = state->inode,
+       };
        int err;
 
        err = nfs4_set_lock_state(state, request);
@@ -4676,6 +4737,7 @@ static int nfs4_proc_setlk(struct nfs4_state *state, int cmd, struct file_lock *
 {
        struct nfs4_exception exception = {
                .state = state,
+               .inode = state->inode,
        };
        int err;
 
@@ -4721,6 +4783,20 @@ nfs4_proc_lock(struct file *filp, int cmd, struct file_lock *request)
 
        if (state == NULL)
                return -ENOLCK;
+       /*
+        * Don't rely on the VFS having checked the file open mode,
+        * since it won't do this for flock() locks.
+        */
+       switch (request->fl_type & (F_RDLCK|F_WRLCK|F_UNLCK)) {
+       case F_RDLCK:
+               if (!(filp->f_mode & FMODE_READ))
+                       return -EBADF;
+               break;
+       case F_WRLCK:
+               if (!(filp->f_mode & FMODE_WRITE))
+                       return -EBADF;
+       }
+
        do {
                status = nfs4_proc_setlk(state, cmd, request);
                if ((status != -EAGAIN) || IS_SETLK(cmd))
@@ -4891,8 +4967,10 @@ static void nfs_fixup_referral_attributes(struct nfs_fattr *fattr)
        fattr->nlink = 2;
 }
 
-int nfs4_proc_fs_locations(struct inode *dir, const struct qstr *name,
-               struct nfs4_fs_locations *fs_locations, struct page *page)
+static int _nfs4_proc_fs_locations(struct rpc_clnt *client, struct inode *dir,
+                                  const struct qstr *name,
+                                  struct nfs4_fs_locations *fs_locations,
+                                  struct page *page)
 {
        struct nfs_server *server = NFS_SERVER(dir);
        u32 bitmask[2] = {
@@ -4926,11 +5004,26 @@ int nfs4_proc_fs_locations(struct inode *dir, const struct qstr *name,
        nfs_fattr_init(&fs_locations->fattr);
        fs_locations->server = server;
        fs_locations->nlocations = 0;
-       status = nfs4_call_sync(server->client, server, &msg, &args.seq_args, &res.seq_res, 0);
+       status = nfs4_call_sync(client, server, &msg, &args.seq_args, &res.seq_res, 0);
        dprintk("%s: returned status = %d\n", __func__, status);
        return status;
 }
 
+int nfs4_proc_fs_locations(struct rpc_clnt *client, struct inode *dir,
+                          const struct qstr *name,
+                          struct nfs4_fs_locations *fs_locations,
+                          struct page *page)
+{
+       struct nfs4_exception exception = { };
+       int err;
+       do {
+               err = nfs4_handle_exception(NFS_SERVER(dir),
+                               _nfs4_proc_fs_locations(client, dir, name, fs_locations, page),
+                               &exception);
+       } while (exception.retry);
+       return err;
+}
+
 static int _nfs4_proc_secinfo(struct inode *dir, const struct qstr *name, struct nfs4_secinfo_flavors *flavors)
 {
        int status;
@@ -4953,8 +5046,8 @@ static int _nfs4_proc_secinfo(struct inode *dir, const struct qstr *name, struct
        return status;
 }
 
-static int nfs4_proc_secinfo(struct inode *dir, const struct qstr *name,
-               struct nfs4_secinfo_flavors *flavors)
+int nfs4_proc_secinfo(struct inode *dir, const struct qstr *name,
+                     struct nfs4_secinfo_flavors *flavors)
 {
        struct nfs4_exception exception = { };
        int err;
@@ -5029,10 +5122,9 @@ int nfs4_proc_exchange_id(struct nfs_client *clp, struct rpc_cred *cred)
        nfs4_construct_boot_verifier(clp, &verifier);
 
        args.id_len = scnprintf(args.id, sizeof(args.id),
-                               "%s/%s.%s/%u",
+                               "%s/%s/%u",
                                clp->cl_ipaddr,
-                               init_utsname()->nodename,
-                               init_utsname()->domainname,
+                               clp->cl_rpcclient->cl_nodename,
                                clp->cl_rpcclient->cl_auth->au_flavor);
 
        res.server_scope = kzalloc(sizeof(struct server_scope), GFP_KERNEL);

diff --git a/fs/nfs/nfs4state.c b/fs/nfs/nfs4state.c
index 0f43414..7f0fcfc 100644 (file)
--- a/fs/nfs/nfs4state.c
+++ b/fs/nfs/nfs4state.c
@@ -393,6 +393,7 @@ nfs4_remove_state_owner_locked(struct nfs4_state_owner *sp)
 static void
 nfs4_init_seqid_counter(struct nfs_seqid_counter *sc)
 {
+       sc->create_time = ktime_get();
        sc->flags = 0;
        sc->counter = 0;
        spin_lock_init(&sc->lock);
@@ -434,13 +435,17 @@ nfs4_alloc_state_owner(struct nfs_server *server,
 static void
 nfs4_drop_state_owner(struct nfs4_state_owner *sp)
 {
-       if (!RB_EMPTY_NODE(&sp->so_server_node)) {
+       struct rb_node *rb_node = &sp->so_server_node;
+
+       if (!RB_EMPTY_NODE(rb_node)) {
                struct nfs_server *server = sp->so_server;
                struct nfs_client *clp = server->nfs_client;
 
                spin_lock(&clp->cl_lock);
-               rb_erase(&sp->so_server_node, &server->state_owners);
-               RB_CLEAR_NODE(&sp->so_server_node);
+               if (!RB_EMPTY_NODE(rb_node)) {
+                       rb_erase(rb_node, &server->state_owners);
+                       RB_CLEAR_NODE(rb_node);
+               }
                spin_unlock(&clp->cl_lock);
        }
 }
@@ -516,6 +521,14 @@ out:
 /**
  * nfs4_put_state_owner - Release a nfs4_state_owner
  * @sp: state owner data to release
+ *
+ * Note that we keep released state owners on an LRU
+ * list.
+ * This caches valid state owners so that they can be
+ * reused, to avoid the OPEN_CONFIRM on minor version 0.
+ * It also pins the uniquifier of dropped state owners for
+ * a while, to ensure that those state owner names are
+ * never reused.
  */
 void nfs4_put_state_owner(struct nfs4_state_owner *sp)
 {
@@ -525,15 +538,9 @@ void nfs4_put_state_owner(struct nfs4_state_owner *sp)
        if (!atomic_dec_and_lock(&sp->so_count, &clp->cl_lock))
                return;
 
-       if (!RB_EMPTY_NODE(&sp->so_server_node)) {
-               sp->so_expires = jiffies;
-               list_add_tail(&sp->so_lru, &server->state_owners_lru);
-               spin_unlock(&clp->cl_lock);
-       } else {
-               nfs4_remove_state_owner_locked(sp);
-               spin_unlock(&clp->cl_lock);
-               nfs4_free_state_owner(sp);
-       }
+       sp->so_expires = jiffies;
+       list_add_tail(&sp->so_lru, &server->state_owners_lru);
+       spin_unlock(&clp->cl_lock);
 }
 
 /**

diff --git a/fs/nfs/nfs4xdr.c b/fs/nfs/nfs4xdr.c
index c74fdb1..c54aae3 100644 (file)
--- a/fs/nfs/nfs4xdr.c
+++ b/fs/nfs/nfs4xdr.c
@@ -74,7 +74,7 @@ static int nfs4_stat_to_errno(int);
 /* lock,open owner id:
  * we currently use size 2 (u64) out of (NFS4_OPAQUE_LIMIT  >> 2)
  */
-#define open_owner_id_maxsz    (1 + 1 + 4)
+#define open_owner_id_maxsz    (1 + 2 + 1 + 1 + 2)
 #define lock_owner_id_maxsz    (1 + 1 + 4)
 #define decode_lockowner_maxsz (1 + XDR_QUADLEN(IDMAP_NAMESZ))
 #define compound_encode_hdr_maxsz      (3 + (NFS4_MAXTAGLEN >> 2))
@@ -1340,12 +1340,13 @@ static inline void encode_openhdr(struct xdr_stream *xdr, const struct nfs_opena
  */
        encode_nfs4_seqid(xdr, arg->seqid);
        encode_share_access(xdr, arg->fmode);
-       p = reserve_space(xdr, 32);
+       p = reserve_space(xdr, 36);
        p = xdr_encode_hyper(p, arg->clientid);
-       *p++ = cpu_to_be32(20);
+       *p++ = cpu_to_be32(24);
        p = xdr_encode_opaque_fixed(p, "open id:", 8);
        *p++ = cpu_to_be32(arg->server->s_dev);
-       xdr_encode_hyper(p, arg->id);
+       *p++ = cpu_to_be32(arg->id.uniquifier);
+       xdr_encode_hyper(p, arg->id.create_time);
 }
 
 static inline void encode_createmode(struct xdr_stream *xdr, const struct nfs_openargs *arg)
@@ -4257,8 +4258,6 @@ static int decode_getfattr_attrs(struct xdr_stream *xdr, uint32_t *bitmap,
        status = decode_attr_error(xdr, bitmap, &err);
        if (status < 0)
                goto xdr_error;
-       if (err == -NFS4ERR_WRONGSEC)
-               nfs_fixup_secinfo_attributes(fattr, fh);
 
        status = decode_attr_filehandle(xdr, bitmap, fh);
        if (status < 0)
@@ -4901,11 +4900,19 @@ static int decode_getacl(struct xdr_stream *xdr, struct rpc_rqst *req,
                 bitmap[3] = {0};
        struct kvec *iov = req->rq_rcv_buf.head;
        int status;
+       size_t page_len = xdr->buf->page_len;
 
        res->acl_len = 0;
        if ((status = decode_op_hdr(xdr, OP_GETATTR)) != 0)
                goto out;
+
        bm_p = xdr->p;
+       res->acl_data_offset = be32_to_cpup(bm_p) + 2;
+       res->acl_data_offset <<= 2;
+       /* Check if the acl data starts beyond the allocated buffer */
+       if (res->acl_data_offset > page_len)
+               return -ERANGE;
+
        if ((status = decode_attr_bitmap(xdr, bitmap)) != 0)
                goto out;
        if ((status = decode_attr_length(xdr, &attrlen, &savep)) != 0)
@@ -4915,28 +4922,24 @@ static int decode_getacl(struct xdr_stream *xdr, struct rpc_rqst *req,
                return -EIO;
        if (likely(bitmap[0] & FATTR4_WORD0_ACL)) {
                size_t hdrlen;
-               u32 recvd;
 
                /* The bitmap (xdr len + bitmaps) and the attr xdr len words
                 * are stored with the acl data to handle the problem of
                 * variable length bitmaps.*/
                xdr->p = bm_p;
-               res->acl_data_offset = be32_to_cpup(bm_p) + 2;
-               res->acl_data_offset <<= 2;
 
                /* We ignore &savep and don't do consistency checks on
                 * the attr length.  Let userspace figure it out.... */
                hdrlen = (u8 *)xdr->p - (u8 *)iov->iov_base;
                attrlen += res->acl_data_offset;
-               recvd = req->rq_rcv_buf.len - hdrlen;
-               if (attrlen > recvd) {
+               if (attrlen > page_len) {
                        if (res->acl_flags & NFS4_ACL_LEN_REQUEST) {
                                /* getxattr interface called with a NULL buf */
                                res->acl_len = attrlen;
                                goto out;
                        }
-                       dprintk("NFS: acl reply: attrlen %u > recvd %u\n",
-                                       attrlen, recvd);
+                       dprintk("NFS: acl reply: attrlen %u > page_len %zu\n",
+                                       attrlen, page_len);
                        return -EINVAL;
                }
                xdr_read_pages(xdr, attrlen);
@@ -5089,16 +5092,13 @@ out_err:
        return -EINVAL;
 }
 
-static int decode_secinfo(struct xdr_stream *xdr, struct nfs4_secinfo_res *res)
+static int decode_secinfo_common(struct xdr_stream *xdr, struct nfs4_secinfo_res *res)
 {
        struct nfs4_secinfo_flavor *sec_flavor;
        int status;
        __be32 *p;
        int i, num_flavors;
 
-       status = decode_op_hdr(xdr, OP_SECINFO);
-       if (status)
-               goto out;
        p = xdr_inline_decode(xdr, 4);
        if (unlikely(!p))
                goto out_overflow;
@@ -5124,6 +5124,7 @@ static int decode_secinfo(struct xdr_stream *xdr, struct nfs4_secinfo_res *res)
                res->flavors->num_flavors++;
        }
 
+       status = 0;
 out:
        return status;
 out_overflow:
@@ -5131,7 +5132,23 @@ out_overflow:
        return -EIO;
 }
 
+static int decode_secinfo(struct xdr_stream *xdr, struct nfs4_secinfo_res *res)
+{
+       int status = decode_op_hdr(xdr, OP_SECINFO);
+       if (status)
+               return status;
+       return decode_secinfo_common(xdr, res);
+}
+
 #if defined(CONFIG_NFS_V4_1)
+static int decode_secinfo_no_name(struct xdr_stream *xdr, struct nfs4_secinfo_res *res)
+{
+       int status = decode_op_hdr(xdr, OP_SECINFO_NO_NAME);
+       if (status)
+               return status;
+       return decode_secinfo_common(xdr, res);
+}
+
 static int decode_exchange_id(struct xdr_stream *xdr,
                              struct nfs41_exchange_id_res *res)
 {
@@ -6816,7 +6833,7 @@ static int nfs4_xdr_dec_secinfo_no_name(struct rpc_rqst *rqstp,
        status = decode_putrootfh(xdr);
        if (status)
                goto out;
-       status = decode_secinfo(xdr, res);
+       status = decode_secinfo_no_name(xdr, res);
 out:
        return status;
 }

diff --git a/fs/nfs/objlayout/objlayout.c b/fs/nfs/objlayout/objlayout.c
index 8d45f1c..595c5fc 100644 (file)
--- a/fs/nfs/objlayout/objlayout.c
+++ b/fs/nfs/objlayout/objlayout.c
@@ -604,7 +604,6 @@ int objlayout_get_deviceinfo(struct pnfs_layout_hdr *pnfslay,
 {
        struct objlayout_deviceinfo *odi;
        struct pnfs_device pd;
-       struct super_block *sb;
        struct page *page, **pages;
        u32 *p;
        int err;
@@ -623,7 +622,6 @@ int objlayout_get_deviceinfo(struct pnfs_layout_hdr *pnfslay,
        pd.pglen = PAGE_SIZE;
        pd.mincount = 0;
 
-       sb = pnfslay->plh_inode->i_sb;
        err = nfs4_proc_getdeviceinfo(NFS_SERVER(pnfslay->plh_inode), &pd);
        dprintk("%s nfs_getdeviceinfo returned %d\n", __func__, err);
        if (err)

diff --git a/fs/nfs/pnfs.c b/fs/nfs/pnfs.c
index b5d4515..38512bc 100644 (file)
--- a/fs/nfs/pnfs.c
+++ b/fs/nfs/pnfs.c
@@ -587,7 +587,7 @@ send_layoutget(struct pnfs_layout_hdr *lo,
 
        /* allocate pages for xdr post processing */
        max_resp_sz = server->nfs_client->cl_session->fc_attrs.max_resp_sz;
-       max_pages = max_resp_sz >> PAGE_SHIFT;
+       max_pages = nfs_page_array_len(0, max_resp_sz);
 
        pages = kcalloc(max_pages, sizeof(struct page *), gfp_flags);
        if (!pages)

diff --git a/fs/nfs/read.c b/fs/nfs/read.c
index 9a0e8ef..0a4be28 100644 (file)
--- a/fs/nfs/read.c
+++ b/fs/nfs/read.c
@@ -322,7 +322,7 @@ out_bad:
        while (!list_empty(res)) {
                data = list_entry(res->next, struct nfs_read_data, list);
                list_del(&data->list);
-               nfs_readdata_free(data);
+               nfs_readdata_release(data);
        }
        nfs_readpage_release(req);
        return -ENOMEM;

diff --git a/fs/nfs/super.c b/fs/nfs/super.c
index 37412f7..4ac7fca 100644 (file)
--- a/fs/nfs/super.c
+++ b/fs/nfs/super.c
@@ -2428,7 +2428,7 @@ nfs_xdev_mount(struct file_system_type *fs_type, int flags,
        dprintk("--> nfs_xdev_mount()\n");
 
        /* create a new volume representation */
-       server = nfs_clone_server(NFS_SB(data->sb), data->fh, data->fattr);
+       server = nfs_clone_server(NFS_SB(data->sb), data->fh, data->fattr, data->authflavor);
        if (IS_ERR(server)) {
                error = PTR_ERR(server);
                goto out_err_noserver;
@@ -2767,11 +2767,15 @@ static struct vfsmount *nfs_do_root_mount(struct file_system_type *fs_type,
        char *root_devname;
        size_t len;
 
-       len = strlen(hostname) + 3;
+       len = strlen(hostname) + 5;
        root_devname = kmalloc(len, GFP_KERNEL);
        if (root_devname == NULL)
                return ERR_PTR(-ENOMEM);
-       snprintf(root_devname, len, "%s:/", hostname);
+       /* Does hostname needs to be enclosed in brackets? */
+       if (strchr(hostname, ':'))
+               snprintf(root_devname, len, "[%s]:/", hostname);
+       else
+               snprintf(root_devname, len, "%s:/", hostname);
        root_mnt = vfs_kern_mount(fs_type, flags, root_devname, data);
        kfree(root_devname);
        return root_mnt;
@@ -2951,7 +2955,7 @@ nfs4_xdev_mount(struct file_system_type *fs_type, int flags,
        dprintk("--> nfs4_xdev_mount()\n");
 
        /* create a new volume representation */
-       server = nfs_clone_server(NFS_SB(data->sb), data->fh, data->fattr);
+       server = nfs_clone_server(NFS_SB(data->sb), data->fh, data->fattr, data->authflavor);
        if (IS_ERR(server)) {
                error = PTR_ERR(server);
                goto out_err_noserver;

diff --git a/fs/nfs/write.c b/fs/nfs/write.c
index 2c68818..c074623 100644 (file)
--- a/fs/nfs/write.c
+++ b/fs/nfs/write.c
@@ -682,7 +682,8 @@ static struct nfs_page *nfs_try_to_update_request(struct inode *inode,
                req->wb_bytes = rqend - req->wb_offset;
 out_unlock:
        spin_unlock(&inode->i_lock);
-       nfs_clear_request_commit(req);
+       if (req)
+               nfs_clear_request_commit(req);
        return req;
 out_flushme:
        spin_unlock(&inode->i_lock);
@@ -1018,7 +1019,7 @@ out_bad:
        while (!list_empty(res)) {
                data = list_entry(res->next, struct nfs_write_data, list);
                list_del(&data->list);
-               nfs_writedata_free(data);
+               nfs_writedata_release(data);
        }
        nfs_redirty_request(req);
        return -ENOMEM;

diff --git a/fs/nfsd/nfs4recover.c b/fs/nfsd/nfs4recover.c
index 4767429..ed3f920 100644 (file)
--- a/fs/nfsd/nfs4recover.c
+++ b/fs/nfsd/nfs4recover.c
@@ -577,7 +577,7 @@ cld_pipe_downcall(struct file *filp, const char __user *src, size_t mlen)
        struct cld_net *cn = nn->cld_net;
 
        if (mlen != sizeof(*cmsg)) {
-               dprintk("%s: got %lu bytes, expected %lu\n", __func__, mlen,
+               dprintk("%s: got %zu bytes, expected %zu\n", __func__, mlen,
                        sizeof(*cmsg));
                return -EINVAL;
        }

diff --git a/fs/pipe.c b/fs/pipe.c
index 25feaa3..fec5e4a 100644 (file)
--- a/fs/pipe.c
+++ b/fs/pipe.c
@@ -346,6 +346,16 @@ static const struct pipe_buf_operations anon_pipe_buf_ops = {
        .get = generic_pipe_buf_get,
 };
 
+static const struct pipe_buf_operations packet_pipe_buf_ops = {
+       .can_merge = 0,
+       .map = generic_pipe_buf_map,
+       .unmap = generic_pipe_buf_unmap,
+       .confirm = generic_pipe_buf_confirm,
+       .release = anon_pipe_buf_release,
+       .steal = generic_pipe_buf_steal,
+       .get = generic_pipe_buf_get,
+};
+
 static ssize_t
 pipe_read(struct kiocb *iocb, const struct iovec *_iov,
           unsigned long nr_segs, loff_t pos)
@@ -407,6 +417,13 @@ redo:
                        ret += chars;
                        buf->offset += chars;
                        buf->len -= chars;
+
+                       /* Was it a packet buffer? Clean up and exit */
+                       if (buf->flags & PIPE_BUF_FLAG_PACKET) {
+                               total_len = chars;
+                               buf->len = 0;
+                       }
+
                        if (!buf->len) {
                                buf->ops = NULL;
                                ops->release(pipe, buf);
@@ -459,6 +476,11 @@ redo:
        return ret;
 }
 
+static inline int is_packetized(struct file *file)
+{
+       return (file->f_flags & O_DIRECT) != 0;
+}
+
 static ssize_t
 pipe_write(struct kiocb *iocb, const struct iovec *_iov,
            unsigned long nr_segs, loff_t ppos)
@@ -593,6 +615,11 @@ redo2:
                        buf->ops = &anon_pipe_buf_ops;
                        buf->offset = 0;
                        buf->len = chars;
+                       buf->flags = 0;
+                       if (is_packetized(filp)) {
+                               buf->ops = &packet_pipe_buf_ops;
+                               buf->flags = PIPE_BUF_FLAG_PACKET;
+                       }
                        pipe->nrbufs = ++bufs;
                        pipe->tmp_page = NULL;
 
@@ -1013,7 +1040,7 @@ struct file *create_write_pipe(int flags)
                goto err_dentry;
        f->f_mapping = inode->i_mapping;
 
-       f->f_flags = O_WRONLY | (flags & O_NONBLOCK);
+       f->f_flags = O_WRONLY | (flags & (O_NONBLOCK | O_DIRECT));
        f->f_version = 0;
 
        return f;
@@ -1057,7 +1084,7 @@ int do_pipe_flags(int *fd, int flags)
        int error;
        int fdw, fdr;
 
-       if (flags & ~(O_CLOEXEC | O_NONBLOCK))
+       if (flags & ~(O_CLOEXEC | O_NONBLOCK | O_DIRECT))
                return -EINVAL;
 
        fw = create_write_pipe(flags);

diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
index 2b9a760..2d60492 100644 (file)
--- a/fs/proc/task_mmu.c
+++ b/fs/proc/task_mmu.c
@@ -597,9 +597,6 @@ static int clear_refs_pte_range(pmd_t *pmd, unsigned long addr,
                if (!page)
                        continue;
 
-               if (PageReserved(page))
-                       continue;
-
                /* Clear accessed and referenced bits. */
                ptep_test_and_clear_young(vma, addr, pte);
                ClearPageReferenced(page);

diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h
index eba6604..e8bcc47 100644 (file)
--- a/include/acpi/actypes.h
+++ b/include/acpi/actypes.h
@@ -499,9 +499,10 @@ typedef u64 acpi_integer;
 #define ACPI_STATE_D0                   (u8) 0
 #define ACPI_STATE_D1                   (u8) 1
 #define ACPI_STATE_D2                   (u8) 2
-#define ACPI_STATE_D3                   (u8) 3
-#define ACPI_STATE_D3_COLD              (u8) 4
-#define ACPI_D_STATES_MAX               ACPI_STATE_D3_COLD
+#define ACPI_STATE_D3_HOT               (u8) 3
+#define ACPI_STATE_D3                   (u8) 4
+#define ACPI_STATE_D3_COLD              ACPI_STATE_D3
+#define ACPI_D_STATES_MAX               ACPI_STATE_D3
 #define ACPI_D_STATE_COUNT              5
 
 #define ACPI_STATE_C0                   (u8) 0

diff --git a/include/asm-generic/siginfo.h b/include/asm-generic/siginfo.h
index 0dd4e87..5e5e386 100644 (file)
--- a/include/asm-generic/siginfo.h
+++ b/include/asm-generic/siginfo.h
@@ -35,6 +35,14 @@ typedef union sigval {
 #define __ARCH_SI_BAND_T long
 #endif
 
+#ifndef __ARCH_SI_CLOCK_T
+#define __ARCH_SI_CLOCK_T __kernel_clock_t
+#endif
+
+#ifndef __ARCH_SI_ATTRIBUTES
+#define __ARCH_SI_ATTRIBUTES
+#endif
+
 #ifndef HAVE_ARCH_SIGINFO_T
 
 typedef struct siginfo {
@@ -72,8 +80,8 @@ typedef struct siginfo {
                        __kernel_pid_t _pid;    /* which child */
                        __ARCH_SI_UID_T _uid;   /* sender's uid */
                        int _status;            /* exit code */
-                       __kernel_clock_t _utime;
-                       __kernel_clock_t _stime;
+                       __ARCH_SI_CLOCK_T _utime;
+                       __ARCH_SI_CLOCK_T _stime;
                } _sigchld;
 
                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
@@ -91,7 +99,7 @@ typedef struct siginfo {
                        int _fd;
                } _sigpoll;
        } _sifields;
-} siginfo_t;
+} __ARCH_SI_ATTRIBUTES siginfo_t;
 
 #endif
 

diff --git a/include/asm-generic/statfs.h b/include/asm-generic/statfs.h
index 0fd28e0..c749af9 100644 (file)
--- a/include/asm-generic/statfs.h
+++ b/include/asm-generic/statfs.h
@@ -15,7 +15,7 @@ typedef __kernel_fsid_t       fsid_t;
  * with a 10' pole.
  */
 #ifndef __statfs_word
-#if BITS_PER_LONG == 64
+#if __BITS_PER_LONG == 64
 #define __statfs_word long
 #else
 #define __statfs_word __u32

diff --git a/include/linux/clk.h b/include/linux/clk.h
index 0e078bd..ad5c43e 100644 (file)
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -101,6 +101,26 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
 struct clk *clk_get(struct device *dev, const char *id);
 
 /**
+ * devm_clk_get - lookup and obtain a managed reference to a clock producer.
+ * @dev: device for clock "consumer"
+ * @id: clock comsumer ID
+ *
+ * Returns a struct clk corresponding to the clock producer, or
+ * valid IS_ERR() condition containing errno.  The implementation
+ * uses @dev and @id to determine the clock consumer, and thereby
+ * the clock producer.  (IOW, @id may be identical strings, but
+ * clk_get may return different clock producers depending on @dev.)
+ *
+ * Drivers must assume that the clock source is not enabled.
+ *
+ * devm_clk_get should not be called from within interrupt context.
+ *
+ * The clock will automatically be freed when the device is unbound
+ * from the bus.
+ */
+struct clk *devm_clk_get(struct device *dev, const char *id);
+
+/**
  * clk_prepare - prepare a clock source
  * @clk: clock source
  *
@@ -206,6 +226,18 @@ unsigned long clk_get_rate(struct clk *clk);
  */
 void clk_put(struct clk *clk);
 
+/**
+ * devm_clk_put        - "free" a managed clock source
+ * @dev: device used to acuqire the clock
+ * @clk: clock source acquired with devm_clk_get()
+ *
+ * Note: drivers must ensure that all clk_enable calls made on this
+ * clock source are balanced by clk_disable calls prior to calling
+ * this function.
+ *
+ * clk_put should not be called from within interrupt context.
+ */
+void devm_clk_put(struct device *dev, struct clk *clk);
 
 /*
  * The remaining APIs are optional for machine class support.

diff --git a/include/linux/clkdev.h b/include/linux/clkdev.h
index d9a4fd0..a6a6f60 100644 (file)
--- a/include/linux/clkdev.h
+++ b/include/linux/clkdev.h
@@ -40,4 +40,7 @@ void clkdev_drop(struct clk_lookup *cl);
 void clkdev_add_table(struct clk_lookup *, size_t);
 int clk_add_alias(const char *, const char *, char *, struct device *);
 
+int clk_register_clkdev(struct clk *, const char *, const char *, ...);
+int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
+
 #endif

diff --git a/include/linux/efi.h b/include/linux/efi.h
index 88ec806..ec45ccd 100644 (file)
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -554,7 +554,18 @@ extern int __init efi_setup_pcdp_console(char *);
 #define EFI_VARIABLE_NON_VOLATILE       0x0000000000000001
 #define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x0000000000000002
 #define EFI_VARIABLE_RUNTIME_ACCESS     0x0000000000000004
-
+#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x0000000000000008
+#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x0000000000000010
+#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x0000000000000020
+#define EFI_VARIABLE_APPEND_WRITE      0x0000000000000040
+
+#define EFI_VARIABLE_MASK      (EFI_VARIABLE_NON_VOLATILE | \
+                               EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+                               EFI_VARIABLE_RUNTIME_ACCESS | \
+                               EFI_VARIABLE_HARDWARE_ERROR_RECORD | \
+                               EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \
+                               EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS | \
+                               EFI_VARIABLE_APPEND_WRITE)
 /*
  * The type of search to perform when calling boottime->locate_handle
  */

diff --git a/include/linux/gpio-pxa.h b/include/linux/gpio-pxa.h
index 05071ee..d755b28 100644 (file)
--- a/include/linux/gpio-pxa.h
+++ b/include/linux/gpio-pxa.h
@@ -13,4 +13,8 @@ extern int pxa_last_gpio;
 
 extern int pxa_irq_to_gpio(int irq);
 
+struct pxa_gpio_platform_data {
+       int (*gpio_set_wake)(unsigned int gpio, unsigned int on);
+};
+
 #endif /* __GPIO_PXA_H */

diff --git a/include/linux/hsi/hsi.h b/include/linux/hsi/hsi.h
index 4b17806..56fae86 100644 (file)
--- a/include/linux/hsi/hsi.h
+++ b/include/linux/hsi/hsi.h
@@ -26,9 +26,9 @@
 #include <linux/device.h>
 #include <linux/mutex.h>
 #include <linux/scatterlist.h>
-#include <linux/spinlock.h>
 #include <linux/list.h>
 #include <linux/module.h>
+#include <linux/notifier.h>
 
 /* HSI message ttype */
 #define HSI_MSG_READ   0
@@ -121,18 +121,18 @@ static inline int hsi_register_board_info(struct hsi_board_info const *info,
  * @device: Driver model representation of the device
  * @tx_cfg: HSI TX configuration
  * @rx_cfg: HSI RX configuration
- * @hsi_start_rx: Called after incoming wake line goes high
- * @hsi_stop_rx: Called after incoming wake line goes low
+ * @e_handler: Callback for handling port events (RX Wake High/Low)
+ * @pclaimed: Keeps tracks if the clients claimed its associated HSI port
+ * @nb: Notifier block for port events
  */
 struct hsi_client {
        struct device           device;
        struct hsi_config       tx_cfg;
        struct hsi_config       rx_cfg;
-       void                    (*hsi_start_rx)(struct hsi_client *cl);
-       void                    (*hsi_stop_rx)(struct hsi_client *cl);
        /* private: */
+       void                    (*ehandler)(struct hsi_client *, unsigned long);
        unsigned int            pclaimed:1;
-       struct list_head        link;
+       struct notifier_block   nb;
 };
 
 #define to_hsi_client(dev) container_of(dev, struct hsi_client, device)
@@ -147,6 +147,10 @@ static inline void *hsi_client_drvdata(struct hsi_client *cl)
        return dev_get_drvdata(&cl->device);
 }
 
+int hsi_register_port_event(struct hsi_client *cl,
+                       void (*handler)(struct hsi_client *, unsigned long));
+int hsi_unregister_port_event(struct hsi_client *cl);
+
 /**
  * struct hsi_client_driver - Driver associated to an HSI client
  * @driver: Driver model representation of the driver
@@ -214,8 +218,7 @@ void hsi_free_msg(struct hsi_msg *msg);
  * @start_tx: Callback to inform that a client wants to TX data
  * @stop_tx: Callback to inform that a client no longer wishes to TX data
  * @release: Callback to inform that a client no longer uses the port
- * @clients: List of hsi_clients using the port.
- * @clock: Lock to serialize access to the clients list.
+ * @n_head: Notifier chain for signaling port events to the clients.
  */
 struct hsi_port {
        struct device                   device;
@@ -231,14 +234,14 @@ struct hsi_port {
        int                             (*start_tx)(struct hsi_client *cl);
        int                             (*stop_tx)(struct hsi_client *cl);
        int                             (*release)(struct hsi_client *cl);
-       struct list_head                clients;
-       spinlock_t                      clock;
+       /* private */
+       struct atomic_notifier_head     n_head;
 };
 
 #define to_hsi_port(dev) container_of(dev, struct hsi_port, device)
 #define hsi_get_port(cl) to_hsi_port((cl)->device.parent)
 
-void hsi_event(struct hsi_port *port, unsigned int event);
+int hsi_event(struct hsi_port *port, unsigned long event);
 int hsi_claim_port(struct hsi_client *cl, unsigned int share);
 void hsi_release_port(struct hsi_client *cl);
 
@@ -270,13 +273,13 @@ struct hsi_controller {
        struct module           *owner;
        unsigned int            id;
        unsigned int            num_ports;
-       struct hsi_port         *port;
+       struct hsi_port         **port;
 };
 
 #define to_hsi_controller(dev) container_of(dev, struct hsi_controller, device)
 
 struct hsi_controller *hsi_alloc_controller(unsigned int n_ports, gfp_t flags);
-void hsi_free_controller(struct hsi_controller *hsi);
+void hsi_put_controller(struct hsi_controller *hsi);
 int hsi_register_controller(struct hsi_controller *hsi);
 void hsi_unregister_controller(struct hsi_controller *hsi);
 
@@ -294,7 +297,7 @@ static inline void *hsi_controller_drvdata(struct hsi_controller *hsi)
 static inline struct hsi_port *hsi_find_port_num(struct hsi_controller *hsi,
                                                        unsigned int num)
 {
-       return (num < hsi->num_ports) ? &hsi->port[num] : NULL;
+       return (num < hsi->num_ports) ? hsi->port[num] : NULL;
 }
 
 /*

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 7810406..b27cfcf 100644 (file)
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -49,6 +49,12 @@ typedef      void (*irq_preflow_handler_t)(struct irq_data *data);
  * IRQ_TYPE_LEVEL_LOW          - low level triggered
  * IRQ_TYPE_LEVEL_MASK         - Mask to filter out the level bits
  * IRQ_TYPE_SENSE_MASK         - Mask for all the above bits
+ * IRQ_TYPE_DEFAULT            - For use by some PICs to ask irq_set_type
+ *                               to setup the HW to a sane default (used
+ *                                by irqdomain map() callbacks to synchronize
+ *                                the HW state and SW flags for a newly
+ *                                allocated descriptor).
+ *
  * IRQ_TYPE_PROBE              - Special flag for probing in progress
  *
  * Bits which can be modified via irq_set/clear/modify_status_flags()
@@ -77,6 +83,7 @@ enum {
        IRQ_TYPE_LEVEL_LOW      = 0x00000008,
        IRQ_TYPE_LEVEL_MASK     = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
        IRQ_TYPE_SENSE_MASK     = 0x0000000f,
+       IRQ_TYPE_DEFAULT        = IRQ_TYPE_SENSE_MASK,
 
        IRQ_TYPE_PROBE          = 0x00000010,
 

diff --git a/include/linux/libata.h b/include/linux/libata.h
index 42378d6..e926df7 100644 (file)
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -996,7 +996,8 @@ extern int ata_sas_scsi_ioctl(struct ata_port *ap, struct scsi_device *dev,
 extern void ata_sas_port_destroy(struct ata_port *);
 extern struct ata_port *ata_sas_port_alloc(struct ata_host *,
                                           struct ata_port_info *, struct Scsi_Host *);
-extern int ata_sas_async_port_init(struct ata_port *);
+extern void ata_sas_async_probe(struct ata_port *ap);
+extern int ata_sas_sync_probe(struct ata_port *ap);
 extern int ata_sas_port_init(struct ata_port *);
 extern int ata_sas_port_start(struct ata_port *ap);
 extern void ata_sas_port_stop(struct ata_port *ap);

diff --git a/include/linux/netfilter_bridge.h b/include/linux/netfilter_bridge.h
index 0ddd161..31d2844 100644 (file)
--- a/include/linux/netfilter_bridge.h
+++ b/include/linux/netfilter_bridge.h
@@ -104,9 +104,18 @@ struct bridge_skb_cb {
        } daddr;
 };
 
+static inline void br_drop_fake_rtable(struct sk_buff *skb)
+{
+       struct dst_entry *dst = skb_dst(skb);
+
+       if (dst && (dst->flags & DST_FAKE_RTABLE))
+               skb_dst_drop(skb);
+}
+
 #else
 #define nf_bridge_maybe_copy_header(skb)       (0)
 #define nf_bridge_pad(skb)                     (0)
+#define br_drop_fake_rtable(skb)               do { } while (0)
 #endif /* CONFIG_BRIDGE_NETFILTER */
 
 #endif /* __KERNEL__ */

diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index bfd0d1b..7ba3551 100644 (file)
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -312,6 +312,11 @@ struct nfs4_layoutreturn {
        int rpc_status;
 };
 
+struct stateowner_id {
+       __u64   create_time;
+       __u32   uniquifier;
+};
+
 /*
  * Arguments to the open call.
  */
@@ -321,7 +326,7 @@ struct nfs_openargs {
        int                     open_flags;
        fmode_t                 fmode;
        __u64                   clientid;
-       __u64                   id;
+       struct stateowner_id    id;
        union {
                struct {
                        struct iattr *  attrs;    /* UNCHECKED, GUARDED */

diff --git a/include/linux/of.h b/include/linux/of.h
index fa7fb1d..2ec1083 100644 (file)
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -193,6 +193,17 @@ extern struct device_node *of_get_next_child(const struct device_node *node,
        for (child = of_get_next_child(parent, NULL); child != NULL; \
             child = of_get_next_child(parent, child))
 
+static inline int of_get_child_count(const struct device_node *np)
+{
+       struct device_node *child;
+       int num = 0;
+
+       for_each_child_of_node(np, child)
+               num++;
+
+       return num;
+}
+
 extern struct device_node *of_find_node_with_property(
        struct device_node *from, const char *prop_name);
 #define for_each_node_with_property(dn, prop_name) \
@@ -259,6 +270,37 @@ extern void of_detach_node(struct device_node *);
 #endif
 
 #define of_match_ptr(_ptr)     (_ptr)
+
+/*
+ * struct property *prop;
+ * const __be32 *p;
+ * u32 u;
+ *
+ * of_property_for_each_u32(np, "propname", prop, p, u)
+ *         printk("U32 value: %x\n", u);
+ */
+const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur,
+                              u32 *pu);
+#define of_property_for_each_u32(np, propname, prop, p, u)     \
+       for (prop = of_find_property(np, propname, NULL),       \
+               p = of_prop_next_u32(prop, NULL, &u);           \
+               p;                                              \
+               p = of_prop_next_u32(prop, p, &u))
+
+/*
+ * struct property *prop;
+ * const char *s;
+ *
+ * of_property_for_each_string(np, "propname", prop, s)
+ *         printk("String value: %s\n", s);
+ */
+const char *of_prop_next_string(struct property *prop, const char *cur);
+#define of_property_for_each_string(np, propname, prop, s)     \
+       for (prop = of_find_property(np, propname, NULL),       \
+               s = of_prop_next_string(prop, NULL);            \
+               s;                                              \
+               s = of_prop_next_string(prop, s))
+
 #else /* CONFIG_OF */
 
 static inline bool of_have_populated_dt(void)
@@ -269,6 +311,11 @@ static inline bool of_have_populated_dt(void)
 #define for_each_child_of_node(parent, child) \
        while (0)
 
+static inline int of_get_child_count(const struct device_node *np)
+{
+       return 0;
+}
+
 static inline int of_device_is_compatible(const struct device_node *device,
                                          const char *name)
 {
@@ -349,6 +396,10 @@ static inline int of_machine_is_compatible(const char *compat)
 
 #define of_match_ptr(_ptr)     NULL
 #define of_match_node(_matches, _node) NULL
+#define of_property_for_each_u32(np, propname, prop, p, u) \
+       while (0)
+#define of_property_for_each_string(np, propname, prop, s) \
+       while (0)
 #endif /* CONFIG_OF */
 
 /**

diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index 191e726..6dd96fb 100644 (file)
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -36,6 +36,9 @@ extern struct pinctrl_state * __must_check pinctrl_lookup_state(
                                                        const char *name);
 extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s);
 
+extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
+extern void devm_pinctrl_put(struct pinctrl *p);
+
 #else /* !CONFIG_PINCTRL */
 
 static inline int pinctrl_request_gpio(unsigned gpio)
@@ -79,6 +82,15 @@ static inline int pinctrl_select_state(struct pinctrl *p,
        return 0;
 }
 
+static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev)
+{
+       return NULL;
+}
+
+static inline void devm_pinctrl_put(struct pinctrl *p)
+{
+}
+
 #endif /* CONFIG_PINCTRL */
 
 static inline struct pinctrl * __must_check pinctrl_get_select(
@@ -113,6 +125,38 @@ static inline struct pinctrl * __must_check pinctrl_get_select_default(
        return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
 }
 
+static inline struct pinctrl * __must_check devm_pinctrl_get_select(
+                                       struct device *dev, const char *name)
+{
+       struct pinctrl *p;
+       struct pinctrl_state *s;
+       int ret;
+
+       p = devm_pinctrl_get(dev);
+       if (IS_ERR(p))
+               return p;
+
+       s = pinctrl_lookup_state(p, name);
+       if (IS_ERR(s)) {
+               devm_pinctrl_put(p);
+               return ERR_PTR(PTR_ERR(s));
+       }
+
+       ret = pinctrl_select_state(p, s);
+       if (ret < 0) {
+               devm_pinctrl_put(p);
+               return ERR_PTR(ret);
+       }
+
+       return p;
+}
+
+static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(
+                                       struct device *dev)
+{
+       return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT);
+}
+
 #ifdef CONFIG_PINCONF
 
 extern int pin_config_get(const char *dev_name, const char *name,

diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h
index e4d1de7..7d22ab0 100644 (file)
--- a/include/linux/pinctrl/machine.h
+++ b/include/linux/pinctrl/machine.h
@@ -154,7 +154,7 @@ struct pinctrl_map {
 
 extern int pinctrl_register_mappings(struct pinctrl_map const *map,
                                unsigned num_maps);
-
+extern void pinctrl_provide_dummies(void);
 #else
 
 static inline int pinctrl_register_mappings(struct pinctrl_map const *map,
@@ -163,5 +163,8 @@ static inline int pinctrl_register_mappings(struct pinctrl_map const *map,
        return 0;
 }
 
-#endif /* !CONFIG_PINMUX */
+static inline void pinctrl_provide_dummies(void)
+{
+}
+#endif /* !CONFIG_PINCTRL */
 #endif

diff --git a/include/linux/pinctrl/pinconf.h b/include/linux/pinctrl/pinconf.h
index ec431f0..e7a7201 100644 (file)
--- a/include/linux/pinctrl/pinconf.h
+++ b/include/linux/pinctrl/pinconf.h
@@ -25,7 +25,6 @@ struct seq_file;
  * @pin_config_get: get the config of a certain pin, if the requested config
  *     is not available on this controller this should return -ENOTSUPP
  *     and if it is available but disabled it should return -EINVAL
- * @pin_config_get: get the config of a certain pin
  * @pin_config_set: configure an individual pin
  * @pin_config_group_get: get configurations for an entire pin group
  * @pin_config_group_set: configure all pins in a group
@@ -33,6 +32,8 @@ struct seq_file;
  *     per-device info for a certain pin in debugfs
  * @pin_config_group_dbg_show: optional debugfs display hook that will provide
  *     per-device info for a certain group in debugfs
+ * @pin_config_config_dbg_show: optional debugfs display hook that will decode
+ *     and display a driver's pin configuration parameter
  */
 struct pinconf_ops {
 #ifdef CONFIG_GENERIC_PINCONF
@@ -56,6 +57,9 @@ struct pinconf_ops {
        void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev,
                                           struct seq_file *s,
                                           unsigned selector);
+       void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev,
+                                           struct seq_file *s,
+                                           unsigned long config);
 };
 
 #endif

diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 4e9f078..3b894a6 100644 (file)
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -21,9 +21,11 @@
 
 struct device;
 struct pinctrl_dev;
+struct pinctrl_map;
 struct pinmux_ops;
 struct pinconf_ops;
 struct gpio_chip;
+struct device_node;
 
 /**
  * struct pinctrl_pin_desc - boards/machines provide information on their
@@ -64,17 +66,24 @@ struct pinctrl_gpio_range {
 /**
  * struct pinctrl_ops - global pin control operations, to be implemented by
  * pin controller drivers.
- * @list_groups: list the number of selectable named groups available
- *     in this pinmux driver, the core will begin on 0 and call this
- *     repeatedly as long as it returns >= 0 to enumerate the groups
+ * @get_groups_count: Returns the count of total number of groups registered.
  * @get_group_name: return the group name of the pin group
  * @get_group_pins: return an array of pins corresponding to a certain
  *     group selector @pins, and the size of the array in @num_pins
  * @pin_dbg_show: optional debugfs display hook that will provide per-device
  *     info for a certain pin in debugfs
+ * @dt_node_to_map: parse a device tree "pin configuration node", and create
+ *     mapping table entries for it. These are returned through the @map and
+ *     @num_maps output parameters. This function is optional, and may be
+ *     omitted for pinctrl drivers that do not support device tree.
+ * @dt_free_map: free mapping table entries created via @dt_node_to_map. The
+ *     top-level @map pointer must be freed, along with any dynamically
+ *     allocated members of the mapping table entries themselves. This
+ *     function is optional, and may be omitted for pinctrl drivers that do
+ *     not support device tree.
  */
 struct pinctrl_ops {
-       int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector);
+       int (*get_groups_count) (struct pinctrl_dev *pctldev);
        const char *(*get_group_name) (struct pinctrl_dev *pctldev,
                                       unsigned selector);
        int (*get_group_pins) (struct pinctrl_dev *pctldev,
@@ -83,6 +92,11 @@ struct pinctrl_ops {
                               unsigned *num_pins);
        void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
                          unsigned offset);
+       int (*dt_node_to_map) (struct pinctrl_dev *pctldev,
+                              struct device_node *np_config,
+                              struct pinctrl_map **map, unsigned *num_maps);
+       void (*dt_free_map) (struct pinctrl_dev *pctldev,
+                            struct pinctrl_map *map, unsigned num_maps);
 };
 
 /**

diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h
index 47e9237..1818dcb 100644 (file)
--- a/include/linux/pinctrl/pinmux.h
+++ b/include/linux/pinctrl/pinmux.h
@@ -23,15 +23,14 @@ struct pinctrl_dev;
 /**
  * struct pinmux_ops - pinmux operations, to be implemented by pin controller
  * drivers that support pinmuxing
- * @request: called by the core to see if a certain pin can be made available
+ * @request: called by the core to see if a certain pin can be made
  *     available for muxing. This is called by the core to acquire the pins
  *     before selecting any actual mux setting across a function. The driver
  *     is allowed to answer "no" by returning a negative error code
  * @free: the reverse function of the request() callback, frees a pin after
  *     being requested
- * @list_functions: list the number of selectable named functions available
- *     in this pinmux driver, the core will begin on 0 and call this
- *     repeatedly as long as it returns >= 0 to enumerate mux settings
+ * @get_functions_count: returns number of selectable named functions available
+ *     in this pinmux driver
  * @get_function_name: return the function name of the muxing selector,
  *     called by the core to figure out which mux setting it shall map a
  *     certain device to
@@ -62,7 +61,7 @@ struct pinctrl_dev;
 struct pinmux_ops {
        int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
        int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
-       int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
+       int (*get_functions_count) (struct pinctrl_dev *pctldev);
        const char *(*get_function_name) (struct pinctrl_dev *pctldev,
                                          unsigned selector);
        int (*get_function_groups) (struct pinctrl_dev *pctldev,

diff --git a/include/linux/pipe_fs_i.h b/include/linux/pipe_fs_i.h
index 6d626ff..e1ac1ce 100644 (file)
--- a/include/linux/pipe_fs_i.h
+++ b/include/linux/pipe_fs_i.h
@@ -6,6 +6,7 @@
 #define PIPE_BUF_FLAG_LRU      0x01    /* page is on the LRU */
 #define PIPE_BUF_FLAG_ATOMIC   0x02    /* was atomically mapped */
 #define PIPE_BUF_FLAG_GIFT     0x04    /* page is a gift */
+#define PIPE_BUF_FLAG_PACKET   0x08    /* read() as a packet */
 
 /**
  *     struct pipe_buffer - a linux kernel pipe buffer

diff --git a/include/linux/seqlock.h b/include/linux/seqlock.h
index c6db9fb..600060e 100644 (file)
--- a/include/linux/seqlock.h
+++ b/include/linux/seqlock.h
@@ -141,7 +141,7 @@ static inline unsigned __read_seqcount_begin(const seqcount_t *s)
        unsigned ret;
 
 repeat:
-       ret = s->sequence;
+       ret = ACCESS_ONCE(s->sequence);
        if (unlikely(ret & 1)) {
                cpu_relax();
                goto repeat;
@@ -166,6 +166,27 @@ static inline unsigned read_seqcount_begin(const seqcount_t *s)
 }
 
 /**
+ * raw_seqcount_begin - begin a seq-read critical section
+ * @s: pointer to seqcount_t
+ * Returns: count to be passed to read_seqcount_retry
+ *
+ * raw_seqcount_begin opens a read critical section of the given seqcount.
+ * Validity of the critical section is tested by checking read_seqcount_retry
+ * function.
+ *
+ * Unlike read_seqcount_begin(), this function will not wait for the count
+ * to stabilize. If a writer is active when we begin, we will fail the
+ * read_seqcount_retry() instead of stabilizing at the beginning of the
+ * critical section.
+ */
+static inline unsigned raw_seqcount_begin(const seqcount_t *s)
+{
+       unsigned ret = ACCESS_ONCE(s->sequence);
+       smp_rmb();
+       return ret & ~1;
+}
+
+/**
  * __read_seqcount_retry - end a seq-read critical section (without barrier)
  * @s: pointer to seqcount_t
  * @start: count, from read_seqcount_begin

diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 70a3f8d..111f26b 100644 (file)
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -238,11 +238,12 @@ enum {
 /*
  * The callback notifies userspace to release buffers when skb DMA is done in
  * lower device, the skb last reference should be 0 when calling this.
- * The desc is used to track userspace buffer index.
+ * The ctx field is used to track device context.
+ * The desc field is used to track userspace buffer index.
  */
 struct ubuf_info {
-       void (*callback)(void *);
-       void *arg;
+       void (*callback)(struct ubuf_info *);
+       void *ctx;
        unsigned long desc;
 };
 
@@ -1019,7 +1020,7 @@ static inline void skb_queue_splice(const struct sk_buff_head *list,
 }
 
 /**
- *     skb_queue_splice - join two skb lists and reinitialise the emptied list
+ *     skb_queue_splice_init - join two skb lists and reinitialise the emptied list
  *     @list: the new list to add
  *     @head: the place to add it in the first list
  *
@@ -1050,7 +1051,7 @@ static inline void skb_queue_splice_tail(const struct sk_buff_head *list,
 }
 
 /**
- *     skb_queue_splice_tail - join two skb lists and reinitialise the emptied list
+ *     skb_queue_splice_tail_init - join two skb lists and reinitialise the emptied list
  *     @list: the new list to add
  *     @head: the place to add it in the first list
  *

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 98679b0..fa702ae 100644 (file)
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -254,7 +254,7 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  *     driver is finished with this message, it must call
  *     spi_finalize_current_message() so the subsystem can issue the next
  *     transfer
- * @prepare_transfer_hardware: there are currently no more messages on the
+ * @unprepare_transfer_hardware: there are currently no more messages on the
  *     queue so the subsystem notifies the driver that it may relax the
  *     hardware by issuing this call
  *

diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
index 5de4157..d28cc78 100644 (file)
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
@@ -126,6 +126,8 @@ struct usb_hcd {
        unsigned                wireless:1;     /* Wireless USB HCD */
        unsigned                authorized_default:1;
        unsigned                has_tt:1;       /* Integrated TT in root hub */
+       unsigned                broken_pci_sleep:1;     /* Don't put the
+                       controller in PCI-D3 for system sleep */
 
        unsigned int            irq;            /* irq allocated */
        void __iomem            *regs;          /* device memory/io */

diff --git a/include/linux/vm_event_item.h b/include/linux/vm_event_item.h
index 03b90cd..06f8e38 100644 (file)
--- a/include/linux/vm_event_item.h
+++ b/include/linux/vm_event_item.h
@@ -26,13 +26,14 @@ enum vm_event_item { PGPGIN, PGPGOUT, PSWPIN, PSWPOUT,
                PGFREE, PGACTIVATE, PGDEACTIVATE,
                PGFAULT, PGMAJFAULT,
                FOR_ALL_ZONES(PGREFILL),
-               FOR_ALL_ZONES(PGSTEAL),
+               FOR_ALL_ZONES(PGSTEAL_KSWAPD),
+               FOR_ALL_ZONES(PGSTEAL_DIRECT),
                FOR_ALL_ZONES(PGSCAN_KSWAPD),
                FOR_ALL_ZONES(PGSCAN_DIRECT),
 #ifdef CONFIG_NUMA
                PGSCAN_ZONE_RECLAIM_FAILED,
 #endif
-               PGINODESTEAL, SLABS_SCANNED, KSWAPD_STEAL, KSWAPD_INODESTEAL,
+               PGINODESTEAL, SLABS_SCANNED, KSWAPD_INODESTEAL,
                KSWAPD_LOW_WMARK_HIT_QUICKLY, KSWAPD_HIGH_WMARK_HIT_QUICKLY,
                KSWAPD_SKIP_CONGESTION_WAIT,
                PAGEOUTRUN, ALLOCSTALL, PGROTATED,

diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index 6822d25..db1c5df 100644 (file)
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -314,6 +314,7 @@ struct hci_conn {
 
        __u8            remote_cap;
        __u8            remote_auth;
+       bool            flush_key;
 
        unsigned int    sent;
 
@@ -980,7 +981,7 @@ int mgmt_discoverable(struct hci_dev *hdev, u8 discoverable);
 int mgmt_connectable(struct hci_dev *hdev, u8 connectable);
 int mgmt_write_scan_failed(struct hci_dev *hdev, u8 scan, u8 status);
 int mgmt_new_link_key(struct hci_dev *hdev, struct link_key *key,
-                     u8 persistent);
+                     bool persistent);
 int mgmt_device_connected(struct hci_dev *hdev, bdaddr_t *bdaddr, u8 link_type,
                          u8 addr_type, u32 flags, u8 *name, u8 name_len,
                          u8 *dev_class);

diff --git a/include/net/dst.h b/include/net/dst.h
index 59c5d18..bed833d 100644 (file)
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -36,7 +36,11 @@ struct dst_entry {
        struct net_device       *dev;
        struct  dst_ops         *ops;
        unsigned long           _metrics;
-       unsigned long           expires;
+       union {
+               unsigned long           expires;
+               /* point to where the dst_entry copied from */
+               struct dst_entry        *from;
+       };
        struct dst_entry        *path;
        struct neighbour __rcu  *_neighbour;
 #ifdef CONFIG_XFRM
@@ -55,6 +59,7 @@ struct dst_entry {
 #define DST_NOCACHE            0x0010
 #define DST_NOCOUNT            0x0020
 #define DST_NOPEER             0x0040
+#define DST_FAKE_RTABLE                0x0080
 
        short                   error;
        short                   obsolete;

diff --git a/include/net/ip6_fib.h b/include/net/ip6_fib.h
index b26bb81..0ae759a 100644 (file)
--- a/include/net/ip6_fib.h
+++ b/include/net/ip6_fib.h
@@ -123,6 +123,54 @@ static inline struct inet6_dev *ip6_dst_idev(struct dst_entry *dst)
        return ((struct rt6_info *)dst)->rt6i_idev;
 }
 
+static inline void rt6_clean_expires(struct rt6_info *rt)
+{
+       if (!(rt->rt6i_flags & RTF_EXPIRES) && rt->dst.from)
+               dst_release(rt->dst.from);
+
+       rt->rt6i_flags &= ~RTF_EXPIRES;
+       rt->dst.from = NULL;
+}
+
+static inline void rt6_set_expires(struct rt6_info *rt, unsigned long expires)
+{
+       if (!(rt->rt6i_flags & RTF_EXPIRES) && rt->dst.from)
+               dst_release(rt->dst.from);
+
+       rt->rt6i_flags |= RTF_EXPIRES;
+       rt->dst.expires = expires;
+}
+
+static inline void rt6_update_expires(struct rt6_info *rt, int timeout)
+{
+       if (!(rt->rt6i_flags & RTF_EXPIRES)) {
+               if (rt->dst.from)
+                       dst_release(rt->dst.from);
+               /* dst_set_expires relies on expires == 0 
+                * if it has not been set previously.
+                */
+               rt->dst.expires = 0;
+       }
+
+       dst_set_expires(&rt->dst, timeout);
+       rt->rt6i_flags |= RTF_EXPIRES;
+}
+
+static inline void rt6_set_from(struct rt6_info *rt, struct rt6_info *from)
+{
+       struct dst_entry *new = (struct dst_entry *) from;
+
+       if (!(rt->rt6i_flags & RTF_EXPIRES) && rt->dst.from) {
+               if (new == rt->dst.from)
+                       return;
+               dst_release(rt->dst.from);
+       }
+
+       rt->rt6i_flags &= ~RTF_EXPIRES;
+       rt->dst.from = new;
+       dst_hold(new);
+}
+
 struct fib6_walker_t {
        struct list_head lh;
        struct fib6_node *root, *node;

diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index 2bdee51..72522f0 100644 (file)
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -393,7 +393,7 @@ struct ip_vs_protocol {
 
        void (*exit)(struct ip_vs_protocol *pp);
 
-       void (*init_netns)(struct net *net, struct ip_vs_proto_data *pd);
+       int (*init_netns)(struct net *net, struct ip_vs_proto_data *pd);
 
        void (*exit_netns)(struct net *net, struct ip_vs_proto_data *pd);
 
@@ -1203,6 +1203,8 @@ ip_vs_lookup_real_service(struct net *net, int af, __u16 protocol,
 
 extern int ip_vs_use_count_inc(void);
 extern void ip_vs_use_count_dec(void);
+extern int ip_vs_register_nl_ioctl(void);
+extern void ip_vs_unregister_nl_ioctl(void);
 extern int ip_vs_control_init(void);
 extern void ip_vs_control_cleanup(void);
 extern struct ip_vs_dest *

diff --git a/include/net/red.h b/include/net/red.h
index 77d4c37..ef46058 100644 (file)
--- a/include/net/red.h
+++ b/include/net/red.h
@@ -245,7 +245,7 @@ static inline unsigned long red_calc_qavg_from_idle_time(const struct red_parms
         *
         * dummy packets as a burst after idle time, i.e.
         *
-        *      p->qavg *= (1-W)^m
+        *      v->qavg *= (1-W)^m
         *
         * This is an apparently overcomplicated solution (f.e. we have to
         * precompute a table to make this calculation in reasonable time)
@@ -279,7 +279,7 @@ static inline unsigned long red_calc_qavg_no_idle_time(const struct red_parms *p
                                                       unsigned int backlog)
 {
        /*
-        * NOTE: p->qavg is fixed point number with point at Wlog.
+        * NOTE: v->qavg is fixed point number with point at Wlog.
         * The formula below is equvalent to floating point
         * version:
         *
@@ -390,7 +390,7 @@ static inline void red_adaptative_algo(struct red_parms *p, struct red_vars *v)
        if (red_is_idling(v))
                qavg = red_calc_qavg_from_idle_time(p, v);
 
-       /* p->qavg is fixed point number with point at Wlog */
+       /* v->qavg is fixed point number with point at Wlog */
        qavg >>= p->Wlog;
 
        if (qavg > p->target_max && p->max_P <= MAX_P_MAX)

diff --git a/include/net/sock.h b/include/net/sock.h
index a6ba1f8..5a0a58a 100644 (file)
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -246,6 +246,7 @@ struct cg_proto;
   *    @sk_user_data: RPC layer private data
   *    @sk_sndmsg_page: cached page for sendmsg
   *    @sk_sndmsg_off: cached offset for sendmsg
+  *    @sk_peek_off: current peek_offset value
   *    @sk_send_head: front of stuff to transmit
   *    @sk_security: used by security modules
   *    @sk_mark: generic packet mark
@@ -1128,9 +1129,9 @@ sk_sockets_allocated_read_positive(struct sock *sk)
        struct proto *prot = sk->sk_prot;
 
        if (mem_cgroup_sockets_enabled && sk->sk_cgrp)
-               return percpu_counter_sum_positive(sk->sk_cgrp->sockets_allocated);
+               return percpu_counter_read_positive(sk->sk_cgrp->sockets_allocated);
 
-       return percpu_counter_sum_positive(prot->sockets_allocated);
+       return percpu_counter_read_positive(prot->sockets_allocated);
 }
 
 static inline int

diff --git a/include/scsi/libsas.h b/include/scsi/libsas.h
index 5f5ed1b..f4f1c96 100644 (file)
--- a/include/scsi/libsas.h
+++ b/include/scsi/libsas.h
@@ -217,11 +217,29 @@ struct domain_device {
        struct kref kref;
 };
 
-struct sas_discovery_event {
+struct sas_work {
+       struct list_head drain_node;
        struct work_struct work;
+};
+
+static inline void INIT_SAS_WORK(struct sas_work *sw, void (*fn)(struct work_struct *))
+{
+       INIT_WORK(&sw->work, fn);
+       INIT_LIST_HEAD(&sw->drain_node);
+}
+
+struct sas_discovery_event {
+       struct sas_work work;
        struct asd_sas_port *port;
 };
 
+static inline struct sas_discovery_event *to_sas_discovery_event(struct work_struct *work)
+{
+       struct sas_discovery_event *ev = container_of(work, typeof(*ev), work.work);
+
+       return ev;
+}
+
 struct sas_discovery {
        struct sas_discovery_event disc_work[DISC_NUM_EVENTS];
        unsigned long    pending;
@@ -244,7 +262,7 @@ struct asd_sas_port {
        struct list_head destroy_list;
        enum   sas_linkrate linkrate;
 
-       struct work_struct work;
+       struct sas_work work;
 
 /* public: */
        int id;
@@ -270,10 +288,17 @@ struct asd_sas_port {
 };
 
 struct asd_sas_event {
-       struct work_struct work;
+       struct sas_work work;
        struct asd_sas_phy *phy;
 };
 
+static inline struct asd_sas_event *to_asd_sas_event(struct work_struct *work)
+{
+       struct asd_sas_event *ev = container_of(work, typeof(*ev), work.work);
+
+       return ev;
+}
+
 /* The phy pretty much is controlled by the LLDD.
  * The class only reads those fields.
  */
@@ -333,10 +358,17 @@ struct scsi_core {
 };
 
 struct sas_ha_event {
-       struct work_struct work;
+       struct sas_work work;
        struct sas_ha_struct *ha;
 };
 
+static inline struct sas_ha_event *to_sas_ha_event(struct work_struct *work)
+{
+       struct sas_ha_event *ev = container_of(work, typeof(*ev), work.work);
+
+       return ev;
+}
+
 enum sas_ha_state {
        SAS_HA_REGISTERED,
        SAS_HA_DRAINING,

diff --git a/include/scsi/sas_ata.h b/include/scsi/sas_ata.h
index cdccd2e..77670e8 100644 (file)
--- a/include/scsi/sas_ata.h
+++ b/include/scsi/sas_ata.h
@@ -37,7 +37,7 @@ static inline int dev_is_sata(struct domain_device *dev)
 }
 
 int sas_get_ata_info(struct domain_device *dev, struct ex_phy *phy);
-int sas_ata_init_host_and_port(struct domain_device *found_dev);
+int sas_ata_init(struct domain_device *dev);
 void sas_ata_task_abort(struct sas_task *task);
 void sas_ata_strategy_handler(struct Scsi_Host *shost);
 void sas_ata_eh(struct Scsi_Host *shost, struct list_head *work_q,
@@ -52,7 +52,7 @@ static inline int dev_is_sata(struct domain_device *dev)
 {
        return 0;
 }
-static inline int sas_ata_init_host_and_port(struct domain_device *found_dev)
+static inline int sas_ata_init(struct domain_device *dev)
 {
        return 0;
 }

diff --git a/init/do_mounts.c b/init/do_mounts.c
index 0e93f92..42b0707 100644 (file)
--- a/init/do_mounts.c
+++ b/init/do_mounts.c
@@ -472,7 +472,7 @@ void __init change_floppy(char *fmt, ...)
 void __init mount_root(void)
 {
 #ifdef CONFIG_ROOT_NFS
-       if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) {
+       if (ROOT_DEV == Root_NFS) {
                if (mount_nfs_root())
                        return;
 

diff --git a/init/main.c b/init/main.c
index 9d454f0..44b2433 100644 (file)
--- a/init/main.c
+++ b/init/main.c
@@ -225,13 +225,9 @@ static int __init loglevel(char *str)
 
 early_param("loglevel", loglevel);
 
-/*
- * Unknown boot options get handed to init, unless they look like
- * unused parameters (modprobe will find them in /proc/cmdline).
- */
-static int __init unknown_bootoption(char *param, char *val)
+/* Change NUL term back to "=", to make "param" the whole string. */
+static int __init repair_env_string(char *param, char *val)
 {
-       /* Change NUL term back to "=", to make "param" the whole string. */
        if (val) {
                /* param=val or param="val"? */
                if (val == param+strlen(param)+1)
@@ -243,6 +239,16 @@ static int __init unknown_bootoption(char *param, char *val)
                } else
                        BUG();
        }
+       return 0;
+}
+
+/*
+ * Unknown boot options get handed to init, unless they look like
+ * unused parameters (modprobe will find them in /proc/cmdline).
+ */
+static int __init unknown_bootoption(char *param, char *val)
+{
+       repair_env_string(param, val);
 
        /* Handle obsolete-style parameters */
        if (obsolete_checksetup(param))
@@ -732,11 +738,6 @@ static char *initcall_level_names[] __initdata = {
        "late parameters",
 };
 
-static int __init ignore_unknown_bootoption(char *param, char *val)
-{
-       return 0;
-}
-
 static void __init do_initcall_level(int level)
 {
        extern const struct kernel_param __start___param[], __stop___param[];
@@ -747,7 +748,7 @@ static void __init do_initcall_level(int level)
                   static_command_line, __start___param,
                   __stop___param - __start___param,
                   level, level,
-                  ignore_unknown_bootoption);
+                  repair_env_string);
 
        for (fn = initcall_levels[level]; fn < initcall_levels[level+1]; fn++)
                do_one_initcall(*fn);

diff --git a/kernel/events/core.c b/kernel/events/core.c
index a6a9ec4..fd126f8 100644 (file)
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -3183,7 +3183,7 @@ static void perf_event_for_each(struct perf_event *event,
        perf_event_for_each_child(event, func);
        func(event);
        list_for_each_entry(sibling, &event->sibling_list, group_entry)
-               perf_event_for_each_child(event, func);
+               perf_event_for_each_child(sibling, func);
        mutex_unlock(&ctx->mutex);
 }
 

diff --git a/kernel/irq/debug.h b/kernel/irq/debug.h
index 97a8bfa..e75e29e 100644 (file)
--- a/kernel/irq/debug.h
+++ b/kernel/irq/debug.h
@@ -4,10 +4,10 @@
 
 #include <linux/kallsyms.h>
 
-#define P(f) if (desc->status_use_accessors & f) printk("%14s set\n", #f)
-#define PS(f) if (desc->istate & f) printk("%14s set\n", #f)
+#define ___P(f) if (desc->status_use_accessors & f) printk("%14s set\n", #f)
+#define ___PS(f) if (desc->istate & f) printk("%14s set\n", #f)
 /* FIXME */
-#define PD(f) do { } while (0)
+#define ___PD(f) do { } while (0)
 
 static inline void print_irq_desc(unsigned int irq, struct irq_desc *desc)
 {
@@ -23,23 +23,23 @@ static inline void print_irq_desc(unsigned int irq, struct irq_desc *desc)
                print_symbol("%s\n", (unsigned long)desc->action->handler);
        }
 
-       P(IRQ_LEVEL);
-       P(IRQ_PER_CPU);
-       P(IRQ_NOPROBE);
-       P(IRQ_NOREQUEST);
-       P(IRQ_NOTHREAD);
-       P(IRQ_NOAUTOEN);
+       ___P(IRQ_LEVEL);
+       ___P(IRQ_PER_CPU);
+       ___P(IRQ_NOPROBE);
+       ___P(IRQ_NOREQUEST);
+       ___P(IRQ_NOTHREAD);
+       ___P(IRQ_NOAUTOEN);
 
-       PS(IRQS_AUTODETECT);
-       PS(IRQS_REPLAY);
-       PS(IRQS_WAITING);
-       PS(IRQS_PENDING);
+       ___PS(IRQS_AUTODETECT);
+       ___PS(IRQS_REPLAY);
+       ___PS(IRQS_WAITING);
+       ___PS(IRQS_PENDING);
 
-       PD(IRQS_INPROGRESS);
-       PD(IRQS_DISABLED);
-       PD(IRQS_MASKED);
+       ___PD(IRQS_INPROGRESS);
+       ___PD(IRQS_DISABLED);
+       ___PD(IRQS_MASKED);
 }
 
-#undef P
-#undef PS
-#undef PD
+#undef ___P
+#undef ___PS
+#undef ___PD

diff --git a/kernel/power/swap.c b/kernel/power/swap.c
index 8742fd0..eef311a 100644 (file)
--- a/kernel/power/swap.c
+++ b/kernel/power/swap.c
@@ -51,6 +51,23 @@
 
 #define MAP_PAGE_ENTRIES       (PAGE_SIZE / sizeof(sector_t) - 1)
 
+/*
+ * Number of free pages that are not high.
+ */
+static inline unsigned long low_free_pages(void)
+{
+       return nr_free_pages() - nr_free_highpages();
+}
+
+/*
+ * Number of pages required to be kept free while writing the image. Always
+ * half of all available low pages before the writing starts.
+ */
+static inline unsigned long reqd_free_pages(void)
+{
+       return low_free_pages() / 2;
+}
+
 struct swap_map_page {
        sector_t entries[MAP_PAGE_ENTRIES];
        sector_t next_swap;
@@ -72,7 +89,7 @@ struct swap_map_handle {
        sector_t cur_swap;
        sector_t first_sector;
        unsigned int k;
-       unsigned long nr_free_pages, written;
+       unsigned long reqd_free_pages;
        u32 crc32;
 };
 
@@ -316,8 +333,7 @@ static int get_swap_writer(struct swap_map_handle *handle)
                goto err_rel;
        }
        handle->k = 0;
-       handle->nr_free_pages = nr_free_pages() >> 1;
-       handle->written = 0;
+       handle->reqd_free_pages = reqd_free_pages();
        handle->first_sector = handle->cur_swap;
        return 0;
 err_rel:
@@ -352,11 +368,11 @@ static int swap_write_page(struct swap_map_handle *handle, void *buf,
                handle->cur_swap = offset;
                handle->k = 0;
        }
-       if (bio_chain && ++handle->written > handle->nr_free_pages) {
+       if (bio_chain && low_free_pages() <= handle->reqd_free_pages) {
                error = hib_wait_on_bio_chain(bio_chain);
                if (error)
                        goto out;
-               handle->written = 0;
+               handle->reqd_free_pages = reqd_free_pages();
        }
  out:
        return error;
@@ -618,7 +634,7 @@ static int save_image_lzo(struct swap_map_handle *handle,
         * Adjust number of free pages after all allocations have been done.
         * We don't want to run out of pages when writing.
         */
-       handle->nr_free_pages = nr_free_pages() >> 1;
+       handle->reqd_free_pages = reqd_free_pages();
 
        /*
         * Start the CRC32 thread.

diff --git a/kernel/rcutree.c b/kernel/rcutree.c
index 1050d6d..d0c5baf 100644 (file)
--- a/kernel/rcutree.c
+++ b/kernel/rcutree.c
@@ -1820,7 +1820,6 @@ __call_rcu(struct rcu_head *head, void (*func)(struct rcu_head *rcu),
         * a quiescent state betweentimes.
         */
        local_irq_save(flags);
-       WARN_ON_ONCE(cpu_is_offline(smp_processor_id()));
        rdp = this_cpu_ptr(rsp->rda);
 
        /* Add the callback to our list. */

diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index 4603b9d..0533a68 100644 (file)
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -6405,16 +6405,26 @@ static void __sdt_free(const struct cpumask *cpu_map)
                struct sd_data *sdd = &tl->data;
 
                for_each_cpu(j, cpu_map) {
-                       struct sched_domain *sd = *per_cpu_ptr(sdd->sd, j);
-                       if (sd && (sd->flags & SD_OVERLAP))
-                               free_sched_groups(sd->groups, 0);
-                       kfree(*per_cpu_ptr(sdd->sd, j));
-                       kfree(*per_cpu_ptr(sdd->sg, j));
-                       kfree(*per_cpu_ptr(sdd->sgp, j));
+                       struct sched_domain *sd;
+
+                       if (sdd->sd) {
+                               sd = *per_cpu_ptr(sdd->sd, j);
+                               if (sd && (sd->flags & SD_OVERLAP))
+                                       free_sched_groups(sd->groups, 0);
+                               kfree(*per_cpu_ptr(sdd->sd, j));
+                       }
+
+                       if (sdd->sg)
+                               kfree(*per_cpu_ptr(sdd->sg, j));
+                       if (sdd->sgp)
+                               kfree(*per_cpu_ptr(sdd->sgp, j));
                }
                free_percpu(sdd->sd);
+               sdd->sd = NULL;
                free_percpu(sdd->sg);
+               sdd->sg = NULL;
                free_percpu(sdd->sgp);
+               sdd->sgp = NULL;
        }
 }
 

diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 0d97ebd..e955364 100644 (file)
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -784,7 +784,7 @@ account_entity_enqueue(struct cfs_rq *cfs_rq, struct sched_entity *se)
                update_load_add(&rq_of(cfs_rq)->load, se->load.weight);
 #ifdef CONFIG_SMP
        if (entity_is_task(se))
-               list_add_tail(&se->group_node, &rq_of(cfs_rq)->cfs_tasks);
+               list_add(&se->group_node, &rq_of(cfs_rq)->cfs_tasks);
 #endif
        cfs_rq->nr_running++;
 }
@@ -3215,6 +3215,8 @@ static int move_one_task(struct lb_env *env)
 
 static unsigned long task_h_load(struct task_struct *p);
 
+static const unsigned int sched_nr_migrate_break = 32;
+
 /*
  * move_tasks tries to move up to load_move weighted load from busiest to
  * this_rq, as part of a balancing operation within domain "sd".
@@ -3242,7 +3244,7 @@ static int move_tasks(struct lb_env *env)
 
                /* take a breather every nr_migrate tasks */
                if (env->loop > env->loop_break) {
-                       env->loop_break += sysctl_sched_nr_migrate;
+                       env->loop_break += sched_nr_migrate_break;
                        env->flags |= LBF_NEED_BREAK;
                        break;
                }
@@ -3252,7 +3254,7 @@ static int move_tasks(struct lb_env *env)
 
                load = task_h_load(p);
 
-               if (load < 16 && !env->sd->nr_balance_failed)
+               if (sched_feat(LB_MIN) && load < 16 && !env->sd->nr_balance_failed)
                        goto next;
 
                if ((load / 2) > env->load_move)
@@ -4407,7 +4409,7 @@ static int load_balance(int this_cpu, struct rq *this_rq,
                .dst_cpu        = this_cpu,
                .dst_rq         = this_rq,
                .idle           = idle,
-               .loop_break     = sysctl_sched_nr_migrate,
+               .loop_break     = sched_nr_migrate_break,
        };
 
        cpumask_copy(cpus, cpu_active_mask);
@@ -4445,10 +4447,10 @@ redo:
                 * correctly treated as an imbalance.
                 */
                env.flags |= LBF_ALL_PINNED;
-               env.load_move = imbalance;
-               env.src_cpu = busiest->cpu;
-               env.src_rq = busiest;
-               env.loop_max = busiest->nr_running;
+               env.load_move   = imbalance;
+               env.src_cpu     = busiest->cpu;
+               env.src_rq      = busiest;
+               env.loop_max    = min_t(unsigned long, sysctl_sched_nr_migrate, busiest->nr_running);
 
 more_balance:
                local_irq_save(flags);

diff --git a/kernel/sched/features.h b/kernel/sched/features.h
index e61fd73..de00a48 100644 (file)
--- a/kernel/sched/features.h
+++ b/kernel/sched/features.h
@@ -68,3 +68,4 @@ SCHED_FEAT(TTWU_QUEUE, true)
 
 SCHED_FEAT(FORCE_SD_OVERLAP, false)
 SCHED_FEAT(RT_RUNTIME_SHARE, true)
+SCHED_FEAT(LB_MIN, false)

diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c
index bf57abd..f113755 100644 (file)
--- a/kernel/time/tick-broadcast.c
+++ b/kernel/time/tick-broadcast.c
@@ -346,7 +346,8 @@ int tick_resume_broadcast(void)
                                                     tick_get_broadcast_mask());
                        break;
                case TICKDEV_MODE_ONESHOT:
-                       broadcast = tick_resume_broadcast_oneshot(bc);
+                       if (!cpumask_empty(tick_get_broadcast_mask()))
+                               broadcast = tick_resume_broadcast_oneshot(bc);
                        break;
                }
        }
@@ -373,6 +374,9 @@ static int tick_broadcast_set_event(ktime_t expires, int force)
 {
        struct clock_event_device *bc = tick_broadcast_device.evtdev;
 
+       if (bc->mode != CLOCK_EVT_MODE_ONESHOT)
+               clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT);
+
        return clockevents_program_event(bc, expires, force);
 }
 
@@ -531,7 +535,6 @@ void tick_broadcast_setup_oneshot(struct clock_event_device *bc)
                int was_periodic = bc->mode == CLOCK_EVT_MODE_PERIODIC;
 
                bc->event_handler = tick_handle_oneshot_broadcast;
-               clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT);
 
                /* Take the do_timer update */
                tick_do_timer_cpu = cpu;
@@ -549,6 +552,7 @@ void tick_broadcast_setup_oneshot(struct clock_event_device *bc)
                           to_cpumask(tmpmask));
 
                if (was_periodic && !cpumask_empty(to_cpumask(tmpmask))) {
+                       clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT);
                        tick_broadcast_init_next_event(to_cpumask(tmpmask),
                                                       tick_next_period);
                        tick_broadcast_set_event(tick_next_period, 1);
@@ -577,15 +581,10 @@ void tick_broadcast_switch_to_oneshot(void)
        raw_spin_lock_irqsave(&tick_broadcast_lock, flags);
 
        tick_broadcast_device.mode = TICKDEV_MODE_ONESHOT;
-
-       if (cpumask_empty(tick_get_broadcast_mask()))
-               goto end;
-
        bc = tick_broadcast_device.evtdev;
        if (bc)
                tick_broadcast_setup_oneshot(bc);
 
-end:
        raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags);
 }
 

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index ed7b5d1..2a22255 100644 (file)
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -4629,7 +4629,8 @@ static ssize_t
 rb_simple_read(struct file *filp, char __user *ubuf,
               size_t cnt, loff_t *ppos)
 {
-       struct ring_buffer *buffer = filp->private_data;
+       struct trace_array *tr = filp->private_data;
+       struct ring_buffer *buffer = tr->buffer;
        char buf[64];
        int r;
 
@@ -4647,7 +4648,8 @@ static ssize_t
 rb_simple_write(struct file *filp, const char __user *ubuf,
                size_t cnt, loff_t *ppos)
 {
-       struct ring_buffer *buffer = filp->private_data;
+       struct trace_array *tr = filp->private_data;
+       struct ring_buffer *buffer = tr->buffer;
        unsigned long val;
        int ret;
 
@@ -4734,7 +4736,7 @@ static __init int tracer_init_debugfs(void)
                          &trace_clock_fops);
 
        trace_create_file("tracing_on", 0644, d_tracer,
-                           global_trace.buffer, &rb_simple_fops);
+                           &global_trace, &rb_simple_fops);
 
 #ifdef CONFIG_DYNAMIC_FTRACE
        trace_create_file("dyn_ftrace_total_info", 0444, d_tracer,

diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
index 95059f0..f95d65d 100644 (file)
--- a/kernel/trace/trace.h
+++ b/kernel/trace/trace.h
@@ -836,11 +836,11 @@ extern const char *__stop___trace_bprintk_fmt[];
                     filter)
 #include "trace_entries.h"
 
-#ifdef CONFIG_FUNCTION_TRACER
+#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_FUNCTION_TRACER)
 int perf_ftrace_event_register(struct ftrace_event_call *call,
                               enum trace_reg type, void *data);
 #else
 #define perf_ftrace_event_register NULL
-#endif /* CONFIG_FUNCTION_TRACER */
+#endif
 
 #endif /* _LINUX_KERNEL_TRACE_H */

diff --git a/kernel/trace/trace_output.c b/kernel/trace/trace_output.c
index 859fae6..df611a0 100644 (file)
--- a/kernel/trace/trace_output.c
+++ b/kernel/trace/trace_output.c
@@ -652,6 +652,8 @@ int trace_print_lat_context(struct trace_iterator *iter)
 {
        u64 next_ts;
        int ret;
+       /* trace_find_next_entry will reset ent_size */
+       int ent_size = iter->ent_size;
        struct trace_seq *s = &iter->seq;
        struct trace_entry *entry = iter->ent,
                           *next_entry = trace_find_next_entry(iter, NULL,
@@ -660,6 +662,9 @@ int trace_print_lat_context(struct trace_iterator *iter)
        unsigned long abs_usecs = ns2usecs(iter->ts - iter->tr->time_start);
        unsigned long rel_usecs;
 
+       /* Restore the original ent_size */
+       iter->ent_size = ent_size;
+
        if (!next_entry)
                next_ts = iter->ts;
        rel_usecs = ns2usecs(next_ts - iter->ts);

diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index cd65cb1..5a16423 100644 (file)
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -532,7 +532,7 @@ static struct page *dequeue_huge_page_vma(struct hstate *h,
                                struct vm_area_struct *vma,
                                unsigned long address, int avoid_reserve)
 {
-       struct page *page;
+       struct page *page = NULL;
        struct mempolicy *mpol;
        nodemask_t *nodemask;
        struct zonelist *zonelist;

diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index b868def..31ab9c3 100644 (file)
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -2476,10 +2476,10 @@ struct mem_cgroup *try_get_mem_cgroup_from_page(struct page *page)
 static void __mem_cgroup_commit_charge(struct mem_cgroup *memcg,
                                       struct page *page,
                                       unsigned int nr_pages,
-                                      struct page_cgroup *pc,
                                       enum charge_type ctype,
                                       bool lrucare)
 {
+       struct page_cgroup *pc = lookup_page_cgroup(page);
        struct zone *uninitialized_var(zone);
        bool was_on_lru = false;
        bool anon;
@@ -2716,7 +2716,6 @@ static int mem_cgroup_charge_common(struct page *page, struct mm_struct *mm,
 {
        struct mem_cgroup *memcg = NULL;
        unsigned int nr_pages = 1;
-       struct page_cgroup *pc;
        bool oom = true;
        int ret;
 
@@ -2730,11 +2729,10 @@ static int mem_cgroup_charge_common(struct page *page, struct mm_struct *mm,
                oom = false;
        }
 
-       pc = lookup_page_cgroup(page);
        ret = __mem_cgroup_try_charge(mm, gfp_mask, nr_pages, &memcg, oom);
        if (ret == -ENOMEM)
                return ret;
-       __mem_cgroup_commit_charge(memcg, page, nr_pages, pc, ctype, false);
+       __mem_cgroup_commit_charge(memcg, page, nr_pages, ctype, false);
        return 0;
 }
 
@@ -2831,16 +2829,13 @@ static void
 __mem_cgroup_commit_charge_swapin(struct page *page, struct mem_cgroup *memcg,
                                        enum charge_type ctype)
 {
-       struct page_cgroup *pc;
-
        if (mem_cgroup_disabled())
                return;
        if (!memcg)
                return;
        cgroup_exclude_rmdir(&memcg->css);
 
-       pc = lookup_page_cgroup(page);
-       __mem_cgroup_commit_charge(memcg, page, 1, pc, ctype, true);
+       __mem_cgroup_commit_charge(memcg, page, 1, ctype, true);
        /*
         * Now swap is on-memory. This means this page may be
         * counted both as mem and swap....double count.
@@ -3298,14 +3293,13 @@ int mem_cgroup_prepare_migration(struct page *page,
         * page. In the case new page is migrated but not remapped, new page's
         * mapcount will be finally 0 and we call uncharge in end_migration().
         */
-       pc = lookup_page_cgroup(newpage);
        if (PageAnon(page))
                ctype = MEM_CGROUP_CHARGE_TYPE_MAPPED;
        else if (page_is_file_cache(page))
                ctype = MEM_CGROUP_CHARGE_TYPE_CACHE;
        else
                ctype = MEM_CGROUP_CHARGE_TYPE_SHMEM;
-       __mem_cgroup_commit_charge(memcg, newpage, 1, pc, ctype, false);
+       __mem_cgroup_commit_charge(memcg, newpage, 1, ctype, false);
        return ret;
 }
 
@@ -3392,8 +3386,7 @@ void mem_cgroup_replace_page_cache(struct page *oldpage,
         * the newpage may be on LRU(or pagevec for LRU) already. We lock
         * LRU while we overwrite pc->mem_cgroup.
         */
-       pc = lookup_page_cgroup(newpage);
-       __mem_cgroup_commit_charge(memcg, newpage, 1, pc, type, true);
+       __mem_cgroup_commit_charge(memcg, newpage, 1, type, true);
 }
 
 #ifdef CONFIG_DEBUG_VM

diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index cfb6c86..b195691 100644 (file)
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -1361,11 +1361,14 @@ SYSCALL_DEFINE4(migrate_pages, pid_t, pid, unsigned long, maxnode,
 
        mm = get_task_mm(task);
        put_task_struct(task);
-       if (mm)
-               err = do_migrate_pages(mm, old, new,
-                       capable(CAP_SYS_NICE) ? MPOL_MF_MOVE_ALL : MPOL_MF_MOVE);
-       else
+
+       if (!mm) {
                err = -EINVAL;
+               goto out;
+       }
+
+       err = do_migrate_pages(mm, old, new,
+               capable(CAP_SYS_NICE) ? MPOL_MF_MOVE_ALL : MPOL_MF_MOVE);
 
        mmput(mm);
 out:

diff --git a/mm/migrate.c b/mm/migrate.c
index 51c08a0..1107238 100644 (file)
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -1388,14 +1388,14 @@ SYSCALL_DEFINE6(move_pages, pid_t, pid, unsigned long, nr_pages,
        mm = get_task_mm(task);
        put_task_struct(task);
 
-       if (mm) {
-               if (nodes)
-                       err = do_pages_move(mm, task_nodes, nr_pages, pages,
-                                           nodes, status, flags);
-               else
-                       err = do_pages_stat(mm, nr_pages, pages, status);
-       } else
-               err = -EINVAL;
+       if (!mm)
+               return -EINVAL;
+
+       if (nodes)
+               err = do_pages_move(mm, task_nodes, nr_pages, pages,
+                                   nodes, status, flags);
+       else
+               err = do_pages_stat(mm, nr_pages, pages, status);
 
        mmput(mm);
        return err;

diff --git a/mm/nobootmem.c b/mm/nobootmem.c
index 24f0fc1..e53bb8a 100644 (file)
--- a/mm/nobootmem.c
+++ b/mm/nobootmem.c
@@ -298,13 +298,19 @@ void * __init __alloc_bootmem_node(pg_data_t *pgdat, unsigned long size,
        if (WARN_ON_ONCE(slab_is_available()))
                return kzalloc_node(size, GFP_NOWAIT, pgdat->node_id);
 
+again:
        ptr = __alloc_memory_core_early(pgdat->node_id, size, align,
                                         goal, -1ULL);
        if (ptr)
                return ptr;
 
-       return __alloc_memory_core_early(MAX_NUMNODES, size, align,
-                                        goal, -1ULL);
+       ptr = __alloc_memory_core_early(MAX_NUMNODES, size, align,
+                                       goal, -1ULL);
+       if (!ptr && goal) {
+               goal = 0;
+               goto again;
+       }
+       return ptr;
 }
 
 void * __init __alloc_bootmem_node_high(pg_data_t *pgdat, unsigned long size,

diff --git a/mm/swap_state.c b/mm/swap_state.c
index 9d3dd37..4c5ff7f 100644 (file)
--- a/mm/swap_state.c
+++ b/mm/swap_state.c
@@ -26,7 +26,7 @@
  */
 static const struct address_space_operations swap_aops = {
        .writepage      = swap_writepage,
-       .set_page_dirty = __set_page_dirty_nobuffers,
+       .set_page_dirty = __set_page_dirty_no_writeback,
        .migratepage    = migrate_page,
 };
 

diff --git a/mm/vmscan.c b/mm/vmscan.c
index 1a51868..33dc256 100644 (file)
--- a/mm/vmscan.c
+++ b/mm/vmscan.c
@@ -1568,9 +1568,14 @@ shrink_inactive_list(unsigned long nr_to_scan, struct mem_cgroup_zone *mz,
        reclaim_stat->recent_scanned[0] += nr_anon;
        reclaim_stat->recent_scanned[1] += nr_file;
 
-       if (current_is_kswapd())
-               __count_vm_events(KSWAPD_STEAL, nr_reclaimed);
-       __count_zone_vm_events(PGSTEAL, zone, nr_reclaimed);
+       if (global_reclaim(sc)) {
+               if (current_is_kswapd())
+                       __count_zone_vm_events(PGSTEAL_KSWAPD, zone,
+                                              nr_reclaimed);
+               else
+                       __count_zone_vm_events(PGSTEAL_DIRECT, zone,
+                                              nr_reclaimed);
+       }
 
        putback_inactive_pages(mz, &page_list);
 

diff --git a/mm/vmstat.c b/mm/vmstat.c
index f600557..7db1b9b 100644 (file)
--- a/mm/vmstat.c
+++ b/mm/vmstat.c
@@ -738,7 +738,8 @@ const char * const vmstat_text[] = {
        "pgmajfault",
 
        TEXTS_FOR_ZONES("pgrefill")
-       TEXTS_FOR_ZONES("pgsteal")
+       TEXTS_FOR_ZONES("pgsteal_kswapd")
+       TEXTS_FOR_ZONES("pgsteal_direct")
        TEXTS_FOR_ZONES("pgscan_kswapd")
        TEXTS_FOR_ZONES("pgscan_direct")
 
@@ -747,7 +748,6 @@ const char * const vmstat_text[] = {
 #endif
        "pginodesteal",
        "slabs_scanned",
-       "kswapd_steal",
        "kswapd_inodesteal",
        "kswapd_low_wmark_hit_quickly",
        "kswapd_high_wmark_hit_quickly",

diff --git a/net/ax25/af_ax25.c b/net/ax25/af_ax25.c
index 0906c19..9d9a6a3 100644 (file)
--- a/net/ax25/af_ax25.c
+++ b/net/ax25/af_ax25.c
@@ -2011,16 +2011,17 @@ static void __exit ax25_exit(void)
        proc_net_remove(&init_net, "ax25_route");
        proc_net_remove(&init_net, "ax25");
        proc_net_remove(&init_net, "ax25_calls");
-       ax25_rt_free();
-       ax25_uid_free();
-       ax25_dev_free();
 
-       ax25_unregister_sysctl();
        unregister_netdevice_notifier(&ax25_dev_notifier);
+       ax25_unregister_sysctl();
 
        dev_remove_pack(&ax25_packet_type);
 
        sock_unregister(PF_AX25);
        proto_unregister(&ax25_proto);
+
+       ax25_rt_free();
+       ax25_uid_free();
+       ax25_dev_free();
 }
 module_exit(ax25_exit);

diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index 92a857e..edfd61a 100644 (file)
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -1215,40 +1215,40 @@ struct link_key *hci_find_link_key(struct hci_dev *hdev, bdaddr_t *bdaddr)
        return NULL;
 }
 
-static int hci_persistent_key(struct hci_dev *hdev, struct hci_conn *conn,
+static bool hci_persistent_key(struct hci_dev *hdev, struct hci_conn *conn,
                                                u8 key_type, u8 old_key_type)
 {
        /* Legacy key */
        if (key_type < 0x03)
-               return 1;
+               return true;
 
        /* Debug keys are insecure so don't store them persistently */
        if (key_type == HCI_LK_DEBUG_COMBINATION)
-               return 0;
+               return false;
 
        /* Changed combination key and there's no previous one */
        if (key_type == HCI_LK_CHANGED_COMBINATION && old_key_type == 0xff)
-               return 0;
+               return false;
 
        /* Security mode 3 case */
        if (!conn)
-               return 1;
+               return true;
 
        /* Neither local nor remote side had no-bonding as requirement */
        if (conn->auth_type > 0x01 && conn->remote_auth > 0x01)
-               return 1;
+               return true;
 
        /* Local side had dedicated bonding as requirement */
        if (conn->auth_type == 0x02 || conn->auth_type == 0x03)
-               return 1;
+               return true;
 
        /* Remote side had dedicated bonding as requirement */
        if (conn->remote_auth == 0x02 || conn->remote_auth == 0x03)
-               return 1;
+               return true;
 
        /* If none of the above criteria match, then don't store the key
         * persistently */
-       return 0;
+       return false;
 }
 
 struct smp_ltk *hci_find_ltk(struct hci_dev *hdev, __le16 ediv, u8 rand[8])
@@ -1285,7 +1285,8 @@ int hci_add_link_key(struct hci_dev *hdev, struct hci_conn *conn, int new_key,
                     bdaddr_t *bdaddr, u8 *val, u8 type, u8 pin_len)
 {
        struct link_key *key, *old_key;
-       u8 old_key_type, persistent;
+       u8 old_key_type;
+       bool persistent;
 
        old_key = hci_find_link_key(hdev, bdaddr);
        if (old_key) {
@@ -1328,10 +1329,8 @@ int hci_add_link_key(struct hci_dev *hdev, struct hci_conn *conn, int new_key,
 
        mgmt_new_link_key(hdev, key, persistent);
 
-       if (!persistent) {
-               list_del(&key->list);
-               kfree(key);
-       }
+       if (conn)
+               conn->flush_key = !persistent;
 
        return 0;
 }

diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index b375310..6c06525 100644 (file)
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -1901,6 +1901,8 @@ static inline void hci_disconn_complete_evt(struct hci_dev *hdev, struct sk_buff
        }
 
        if (ev->status == 0) {
+               if (conn->type == ACL_LINK && conn->flush_key)
+                       hci_remove_link_key(hdev, &conn->dst);
                hci_proto_disconn_cfm(conn, ev->reason);
                hci_conn_del(conn);
        }
@@ -2311,6 +2313,7 @@ static inline void hci_cmd_complete_evt(struct hci_dev *hdev, struct sk_buff *sk
 
        case HCI_OP_USER_PASSKEY_NEG_REPLY:
                hci_cc_user_passkey_neg_reply(hdev, skb);
+               break;
 
        case HCI_OP_LE_SET_SCAN_PARAM:
                hci_cc_le_set_scan_param(hdev, skb);

diff --git a/net/bluetooth/mgmt.c b/net/bluetooth/mgmt.c
index 4ef275c..4bb03b1 100644 (file)
--- a/net/bluetooth/mgmt.c
+++ b/net/bluetooth/mgmt.c
@@ -2884,7 +2884,7 @@ int mgmt_write_scan_failed(struct hci_dev *hdev, u8 scan, u8 status)
        return 0;
 }
 
-int mgmt_new_link_key(struct hci_dev *hdev, struct link_key *key, u8 persistent)
+int mgmt_new_link_key(struct hci_dev *hdev, struct link_key *key, bool persistent)
 {
        struct mgmt_ev_new_link_key ev;
 

diff --git a/net/bridge/br_forward.c b/net/bridge/br_forward.c
index 61f6534..a2098e3 100644 (file)
--- a/net/bridge/br_forward.c
+++ b/net/bridge/br_forward.c
@@ -47,6 +47,7 @@ int br_dev_queue_push_xmit(struct sk_buff *skb)
                kfree_skb(skb);
        } else {
                skb_push(skb, ETH_HLEN);
+               br_drop_fake_rtable(skb);
                dev_queue_xmit(skb);
        }
 

diff --git a/net/bridge/br_netfilter.c b/net/bridge/br_netfilter.c
index dec4f38..d7f49b6 100644 (file)
--- a/net/bridge/br_netfilter.c
+++ b/net/bridge/br_netfilter.c
@@ -156,7 +156,7 @@ void br_netfilter_rtable_init(struct net_bridge *br)
        rt->dst.dev = br->dev;
        rt->dst.path = &rt->dst;
        dst_init_metrics(&rt->dst, br_dst_default_metrics, true);
-       rt->dst.flags   = DST_NOXFRM | DST_NOPEER;
+       rt->dst.flags   = DST_NOXFRM | DST_NOPEER | DST_FAKE_RTABLE;
        rt->dst.ops = &fake_dst_ops;
 }
 
@@ -694,11 +694,7 @@ static unsigned int br_nf_local_in(unsigned int hook, struct sk_buff *skb,
                                   const struct net_device *out,
                                   int (*okfn)(struct sk_buff *))
 {
-       struct rtable *rt = skb_rtable(skb);
-
-       if (rt && rt == bridge_parent_rtable(in))
-               skb_dst_drop(skb);
-
+       br_drop_fake_rtable(skb);
        return NF_ACCEPT;
 }
 

diff --git a/net/caif/chnl_net.c b/net/caif/chnl_net.c
index 20618dd..d09340e 100644 (file)
--- a/net/caif/chnl_net.c
+++ b/net/caif/chnl_net.c
@@ -103,6 +103,7 @@ static int chnl_recv_cb(struct cflayer *layr, struct cfpkt *pkt)
                skb->protocol = htons(ETH_P_IPV6);
                break;
        default:
+               kfree_skb(skb);
                priv->netdev->stats.rx_errors++;
                return -EINVAL;
        }
@@ -220,14 +221,16 @@ static int chnl_net_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
        if (skb->len > priv->netdev->mtu) {
                pr_warn("Size of skb exceeded MTU\n");
+               kfree_skb(skb);
                dev->stats.tx_errors++;
-               return -ENOSPC;
+               return NETDEV_TX_OK;
        }
 
        if (!priv->flowenabled) {
                pr_debug("dropping packets flow off\n");
+               kfree_skb(skb);
                dev->stats.tx_dropped++;
-               return NETDEV_TX_BUSY;
+               return NETDEV_TX_OK;
        }
 
        if (priv->conn_req.protocol == CAIFPROTO_DATAGRAM_LOOP)
@@ -242,7 +245,7 @@ static int chnl_net_start_xmit(struct sk_buff *skb, struct net_device *dev)
        result = priv->chnl.dn->transmit(priv->chnl.dn, pkt);
        if (result) {
                dev->stats.tx_dropped++;
-               return result;
+               return NETDEV_TX_OK;
        }
 
        /* Update statistics. */

diff --git a/net/core/dev.c b/net/core/dev.c
index c25d453..9bb8f87 100644 (file)
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -1409,14 +1409,34 @@ EXPORT_SYMBOL(register_netdevice_notifier);
  *     register_netdevice_notifier(). The notifier is unlinked into the
  *     kernel structures and may then be reused. A negative errno code
  *     is returned on a failure.
+ *
+ *     After unregistering unregister and down device events are synthesized
+ *     for all devices on the device list to the removed notifier to remove
+ *     the need for special case cleanup code.
  */
 
 int unregister_netdevice_notifier(struct notifier_block *nb)
 {
+       struct net_device *dev;
+       struct net *net;
        int err;
 
        rtnl_lock();
        err = raw_notifier_chain_unregister(&netdev_chain, nb);
+       if (err)
+               goto unlock;
+
+       for_each_net(net) {
+               for_each_netdev(net, dev) {
+                       if (dev->flags & IFF_UP) {
+                               nb->notifier_call(nb, NETDEV_GOING_DOWN, dev);
+                               nb->notifier_call(nb, NETDEV_DOWN, dev);
+                       }
+                       nb->notifier_call(nb, NETDEV_UNREGISTER, dev);
+                       nb->notifier_call(nb, NETDEV_UNREGISTER_BATCH, dev);
+               }
+       }
+unlock:
        rtnl_unlock();
        return err;
 }

diff --git a/net/core/drop_monitor.c b/net/core/drop_monitor.c
index 7f36b38..a7cad74 100644 (file)
--- a/net/core/drop_monitor.c
+++ b/net/core/drop_monitor.c
@@ -42,13 +42,14 @@ static void send_dm_alert(struct work_struct *unused);
  * netlink alerts
  */
 static int trace_state = TRACE_OFF;
-static DEFINE_SPINLOCK(trace_state_lock);
+static DEFINE_MUTEX(trace_state_mutex);
 
 struct per_cpu_dm_data {
        struct work_struct dm_alert_work;
-       struct sk_buff *skb;
+       struct sk_buff __rcu *skb;
        atomic_t dm_hit_count;
        struct timer_list send_timer;
+       int cpu;
 };
 
 struct dm_hw_stat_delta {
@@ -79,29 +80,53 @@ static void reset_per_cpu_data(struct per_cpu_dm_data *data)
        size_t al;
        struct net_dm_alert_msg *msg;
        struct nlattr *nla;
+       struct sk_buff *skb;
+       struct sk_buff *oskb = rcu_dereference_protected(data->skb, 1);
 
        al = sizeof(struct net_dm_alert_msg);
        al += dm_hit_limit * sizeof(struct net_dm_drop_point);
        al += sizeof(struct nlattr);
 
-       data->skb = genlmsg_new(al, GFP_KERNEL);
-       genlmsg_put(data->skb, 0, 0, &net_drop_monitor_family,
-                       0, NET_DM_CMD_ALERT);
-       nla = nla_reserve(data->skb, NLA_UNSPEC, sizeof(struct net_dm_alert_msg));
-       msg = nla_data(nla);
-       memset(msg, 0, al);
-       atomic_set(&data->dm_hit_count, dm_hit_limit);
+       skb = genlmsg_new(al, GFP_KERNEL);
+
+       if (skb) {
+               genlmsg_put(skb, 0, 0, &net_drop_monitor_family,
+                               0, NET_DM_CMD_ALERT);
+               nla = nla_reserve(skb, NLA_UNSPEC,
+                                 sizeof(struct net_dm_alert_msg));
+               msg = nla_data(nla);
+               memset(msg, 0, al);
+       } else
+               schedule_work_on(data->cpu, &data->dm_alert_work);
+
+       /*
+        * Don't need to lock this, since we are guaranteed to only
+        * run this on a single cpu at a time.
+        * Note also that we only update data->skb if the old and new skb
+        * pointers don't match.  This ensures that we don't continually call
+        * synchornize_rcu if we repeatedly fail to alloc a new netlink message.
+        */
+       if (skb != oskb) {
+               rcu_assign_pointer(data->skb, skb);
+
+               synchronize_rcu();
+
+               atomic_set(&data->dm_hit_count, dm_hit_limit);
+       }
+
 }
 
 static void send_dm_alert(struct work_struct *unused)
 {
        struct sk_buff *skb;
-       struct per_cpu_dm_data *data = &__get_cpu_var(dm_cpu_data);
+       struct per_cpu_dm_data *data = &get_cpu_var(dm_cpu_data);
+
+       WARN_ON_ONCE(data->cpu != smp_processor_id());
 
        /*
         * Grab the skb we're about to send
         */
-       skb = data->skb;
+       skb = rcu_dereference_protected(data->skb, 1);
 
        /*
         * Replace it with a new one
@@ -111,8 +136,10 @@ static void send_dm_alert(struct work_struct *unused)
        /*
         * Ship it!
         */
-       genlmsg_multicast(skb, 0, NET_DM_GRP_ALERT, GFP_KERNEL);
+       if (skb)
+               genlmsg_multicast(skb, 0, NET_DM_GRP_ALERT, GFP_KERNEL);
 
+       put_cpu_var(dm_cpu_data);
 }
 
 /*
@@ -123,9 +150,11 @@ static void send_dm_alert(struct work_struct *unused)
  */
 static void sched_send_work(unsigned long unused)
 {
-       struct per_cpu_dm_data *data =  &__get_cpu_var(dm_cpu_data);
+       struct per_cpu_dm_data *data =  &get_cpu_var(dm_cpu_data);
+
+       schedule_work_on(smp_processor_id(), &data->dm_alert_work);
 
-       schedule_work(&data->dm_alert_work);
+       put_cpu_var(dm_cpu_data);
 }
 
 static void trace_drop_common(struct sk_buff *skb, void *location)
@@ -134,8 +163,15 @@ static void trace_drop_common(struct sk_buff *skb, void *location)
        struct nlmsghdr *nlh;
        struct nlattr *nla;
        int i;
-       struct per_cpu_dm_data *data = &__get_cpu_var(dm_cpu_data);
+       struct sk_buff *dskb;
+       struct per_cpu_dm_data *data = &get_cpu_var(dm_cpu_data);
+
+
+       rcu_read_lock();
+       dskb = rcu_dereference(data->skb);
 
+       if (!dskb)
+               goto out;
 
        if (!atomic_add_unless(&data->dm_hit_count, -1, 0)) {
                /*
@@ -144,12 +180,13 @@ static void trace_drop_common(struct sk_buff *skb, void *location)
                goto out;
        }
 
-       nlh = (struct nlmsghdr *)data->skb->data;
+       nlh = (struct nlmsghdr *)dskb->data;
        nla = genlmsg_data(nlmsg_data(nlh));
        msg = nla_data(nla);
        for (i = 0; i < msg->entries; i++) {
                if (!memcmp(&location, msg->points[i].pc, sizeof(void *))) {
                        msg->points[i].count++;
+                       atomic_inc(&data->dm_hit_count);
                        goto out;
                }
        }
@@ -157,7 +194,7 @@ static void trace_drop_common(struct sk_buff *skb, void *location)
        /*
         * We need to create a new entry
         */
-       __nla_reserve_nohdr(data->skb, sizeof(struct net_dm_drop_point));
+       __nla_reserve_nohdr(dskb, sizeof(struct net_dm_drop_point));
        nla->nla_len += NLA_ALIGN(sizeof(struct net_dm_drop_point));
        memcpy(msg->points[msg->entries].pc, &location, sizeof(void *));
        msg->points[msg->entries].count = 1;
@@ -169,6 +206,8 @@ static void trace_drop_common(struct sk_buff *skb, void *location)
        }
 
 out:
+       rcu_read_unlock();
+       put_cpu_var(dm_cpu_data);
        return;
 }
 
@@ -213,7 +252,7 @@ static int set_all_monitor_traces(int state)
        struct dm_hw_stat_delta *new_stat = NULL;
        struct dm_hw_stat_delta *temp;
 
-       spin_lock(&trace_state_lock);
+       mutex_lock(&trace_state_mutex);
 
        if (state == trace_state) {
                rc = -EAGAIN;
@@ -252,7 +291,7 @@ static int set_all_monitor_traces(int state)
                rc = -EINPROGRESS;
 
 out_unlock:
-       spin_unlock(&trace_state_lock);
+       mutex_unlock(&trace_state_mutex);
 
        return rc;
 }
@@ -295,12 +334,12 @@ static int dropmon_net_event(struct notifier_block *ev_block,
 
                new_stat->dev = dev;
                new_stat->last_rx = jiffies;
-               spin_lock(&trace_state_lock);
+               mutex_lock(&trace_state_mutex);
                list_add_rcu(&new_stat->list, &hw_stats_list);
-               spin_unlock(&trace_state_lock);
+               mutex_unlock(&trace_state_mutex);
                break;
        case NETDEV_UNREGISTER:
-               spin_lock(&trace_state_lock);
+               mutex_lock(&trace_state_mutex);
                list_for_each_entry_safe(new_stat, tmp, &hw_stats_list, list) {
                        if (new_stat->dev == dev) {
                                new_stat->dev = NULL;
@@ -311,7 +350,7 @@ static int dropmon_net_event(struct notifier_block *ev_block,
                                }
                        }
                }
-               spin_unlock(&trace_state_lock);
+               mutex_unlock(&trace_state_mutex);
                break;
        }
 out:
@@ -367,13 +406,15 @@ static int __init init_net_drop_monitor(void)
 
        for_each_present_cpu(cpu) {
                data = &per_cpu(dm_cpu_data, cpu);
-               reset_per_cpu_data(data);
+               data->cpu = cpu;
                INIT_WORK(&data->dm_alert_work, send_dm_alert);
                init_timer(&data->send_timer);
                data->send_timer.data = cpu;
                data->send_timer.function = sched_send_work;
+               reset_per_cpu_data(data);
        }
 
+
        goto out;
 
 out_unreg:

diff --git a/net/core/net_namespace.c b/net/core/net_namespace.c
index 0e950fd..31a5ae5 100644 (file)
--- a/net/core/net_namespace.c
+++ b/net/core/net_namespace.c
@@ -83,21 +83,29 @@ assign:
 
 static int ops_init(const struct pernet_operations *ops, struct net *net)
 {
-       int err;
+       int err = -ENOMEM;
+       void *data = NULL;
+
        if (ops->id && ops->size) {
-               void *data = kzalloc(ops->size, GFP_KERNEL);
+               data = kzalloc(ops->size, GFP_KERNEL);
                if (!data)
-                       return -ENOMEM;
+                       goto out;
 
                err = net_assign_generic(net, *ops->id, data);
-               if (err) {
-                       kfree(data);
-                       return err;
-               }
+               if (err)
+                       goto cleanup;
        }
+       err = 0;
        if (ops->init)
-               return ops->init(net);
-       return 0;
+               err = ops->init(net);
+       if (!err)
+               return 0;
+
+cleanup:
+       kfree(data);
+
+out:
+       return err;
 }
 
 static void ops_free(const struct pernet_operations *ops, struct net *net)
@@ -448,12 +456,7 @@ static void __unregister_pernet_operations(struct pernet_operations *ops)
 static int __register_pernet_operations(struct list_head *list,
                                        struct pernet_operations *ops)
 {
-       int err = 0;
-       err = ops_init(ops, &init_net);
-       if (err)
-               ops_free(ops, &init_net);
-       return err;
-       
+       return ops_init(ops, &init_net);
 }
 
 static void __unregister_pernet_operations(struct pernet_operations *ops)

diff --git a/net/ieee802154/6lowpan.c b/net/ieee802154/6lowpan.c
index 3685158..840821b 100644 (file)
--- a/net/ieee802154/6lowpan.c
+++ b/net/ieee802154/6lowpan.c
@@ -1044,6 +1044,24 @@ static void lowpan_dev_free(struct net_device *dev)
        free_netdev(dev);
 }
 
+static struct wpan_phy *lowpan_get_phy(const struct net_device *dev)
+{
+       struct net_device *real_dev = lowpan_dev_info(dev)->real_dev;
+       return ieee802154_mlme_ops(real_dev)->get_phy(real_dev);
+}
+
+static u16 lowpan_get_pan_id(const struct net_device *dev)
+{
+       struct net_device *real_dev = lowpan_dev_info(dev)->real_dev;
+       return ieee802154_mlme_ops(real_dev)->get_pan_id(real_dev);
+}
+
+static u16 lowpan_get_short_addr(const struct net_device *dev)
+{
+       struct net_device *real_dev = lowpan_dev_info(dev)->real_dev;
+       return ieee802154_mlme_ops(real_dev)->get_short_addr(real_dev);
+}
+
 static struct header_ops lowpan_header_ops = {
        .create = lowpan_header_create,
 };
@@ -1053,6 +1071,12 @@ static const struct net_device_ops lowpan_netdev_ops = {
        .ndo_set_mac_address    = eth_mac_addr,
 };
 
+static struct ieee802154_mlme_ops lowpan_mlme = {
+       .get_pan_id = lowpan_get_pan_id,
+       .get_phy = lowpan_get_phy,
+       .get_short_addr = lowpan_get_short_addr,
+};
+
 static void lowpan_setup(struct net_device *dev)
 {
        pr_debug("(%s)\n", __func__);
@@ -1070,6 +1094,7 @@ static void lowpan_setup(struct net_device *dev)
 
        dev->netdev_ops         = &lowpan_netdev_ops;
        dev->header_ops         = &lowpan_header_ops;
+       dev->ml_priv            = &lowpan_mlme;
        dev->destructor         = lowpan_dev_free;
 }
 
@@ -1143,6 +1168,8 @@ static int lowpan_newlink(struct net *src_net, struct net_device *dev,
        list_add_tail(&entry->list, &lowpan_devices);
        mutex_unlock(&lowpan_dev_info(dev)->dev_list_mtx);
 
+       spin_lock_init(&flist_lock);
+
        register_netdevice(dev);
 
        return 0;
@@ -1152,11 +1179,20 @@ static void lowpan_dellink(struct net_device *dev, struct list_head *head)
 {
        struct lowpan_dev_info *lowpan_dev = lowpan_dev_info(dev);
        struct net_device *real_dev = lowpan_dev->real_dev;
-       struct lowpan_dev_record *entry;
-       struct lowpan_dev_record *tmp;
+       struct lowpan_dev_record *entry, *tmp;
+       struct lowpan_fragment *frame, *tframe;
 
        ASSERT_RTNL();
 
+       spin_lock(&flist_lock);
+       list_for_each_entry_safe(frame, tframe, &lowpan_fragments, list) {
+               del_timer(&frame->timer);
+               list_del(&frame->list);
+               dev_kfree_skb(frame->skb);
+               kfree(frame);
+       }
+       spin_unlock(&flist_lock);
+
        mutex_lock(&lowpan_dev_info(dev)->dev_list_mtx);
        list_for_each_entry_safe(entry, tmp, &lowpan_devices, list) {
                if (entry->ldev == dev) {

diff --git a/net/ipv4/inet_diag.c b/net/ipv4/inet_diag.c
index 8d25a1c..8f8db72 100644 (file)
--- a/net/ipv4/inet_diag.c
+++ b/net/ipv4/inet_diag.c
@@ -141,7 +141,7 @@ int inet_sk_diag_fill(struct sock *sk, struct inet_connection_sock *icsk,
                        goto rtattr_failure;
 
        if (icsk == NULL) {
-               r->idiag_rqueue = r->idiag_wqueue = 0;
+               handler->idiag_get_info(sk, r, NULL);
                goto out;
        }
 

diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c
index 8bb6ade..1272a88 100644 (file)
--- a/net/ipv4/tcp.c
+++ b/net/ipv4/tcp.c
@@ -3243,7 +3243,7 @@ void __init tcp_init(void)
 {
        struct sk_buff *skb = NULL;
        unsigned long limit;
-       int max_share, cnt;
+       int max_rshare, max_wshare, cnt;
        unsigned int i;
        unsigned long jiffy = jiffies;
 
@@ -3303,15 +3303,16 @@ void __init tcp_init(void)
        tcp_init_mem(&init_net);
        /* Set per-socket limits to no more than 1/128 the pressure threshold */
        limit = nr_free_buffer_pages() << (PAGE_SHIFT - 7);
-       max_share = min(4UL*1024*1024, limit);
+       max_wshare = min(4UL*1024*1024, limit);
+       max_rshare = min(6UL*1024*1024, limit);
 
        sysctl_tcp_wmem[0] = SK_MEM_QUANTUM;
        sysctl_tcp_wmem[1] = 16*1024;
-       sysctl_tcp_wmem[2] = max(64*1024, max_share);
+       sysctl_tcp_wmem[2] = max(64*1024, max_wshare);
 
        sysctl_tcp_rmem[0] = SK_MEM_QUANTUM;
        sysctl_tcp_rmem[1] = 87380;
-       sysctl_tcp_rmem[2] = max(87380, max_share);
+       sysctl_tcp_rmem[2] = max(87380, max_rshare);
 
        pr_info("Hash tables configured (established %u bind %u)\n",
                tcp_hashinfo.ehash_mask + 1, tcp_hashinfo.bhash_size);

diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c
index 9944c1d..257b617 100644 (file)
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
@@ -85,7 +85,7 @@ int sysctl_tcp_ecn __read_mostly = 2;
 EXPORT_SYMBOL(sysctl_tcp_ecn);
 int sysctl_tcp_dsack __read_mostly = 1;
 int sysctl_tcp_app_win __read_mostly = 31;
-int sysctl_tcp_adv_win_scale __read_mostly = 2;
+int sysctl_tcp_adv_win_scale __read_mostly = 1;
 EXPORT_SYMBOL(sysctl_tcp_adv_win_scale);
 
 int sysctl_tcp_stdurg __read_mostly;
@@ -335,6 +335,7 @@ static void tcp_grow_window(struct sock *sk, const struct sk_buff *skb)
                        incr = __tcp_grow_window(sk, skb);
 
                if (incr) {
+                       incr = max_t(int, incr, 2 * skb->len);
                        tp->rcv_ssthresh = min(tp->rcv_ssthresh + incr,
                                               tp->window_clamp);
                        inet_csk(sk)->icsk_ack.quick |= 1;
@@ -494,7 +495,7 @@ static inline void tcp_rcv_rtt_measure(struct tcp_sock *tp)
                goto new_measure;
        if (before(tp->rcv_nxt, tp->rcv_rtt_est.seq))
                return;
-       tcp_rcv_rtt_update(tp, jiffies - tp->rcv_rtt_est.time, 1);
+       tcp_rcv_rtt_update(tp, tcp_time_stamp - tp->rcv_rtt_est.time, 1);
 
 new_measure:
        tp->rcv_rtt_est.seq = tp->rcv_nxt + tp->rcv_wnd;
@@ -2867,11 +2868,14 @@ static inline void tcp_complete_cwr(struct sock *sk)
 
        /* Do not moderate cwnd if it's already undone in cwr or recovery. */
        if (tp->undo_marker) {
-               if (inet_csk(sk)->icsk_ca_state == TCP_CA_CWR)
+               if (inet_csk(sk)->icsk_ca_state == TCP_CA_CWR) {
                        tp->snd_cwnd = min(tp->snd_cwnd, tp->snd_ssthresh);
-               else /* PRR */
+                       tp->snd_cwnd_stamp = tcp_time_stamp;
+               } else if (tp->snd_ssthresh < TCP_INFINITE_SSTHRESH) {
+                       /* PRR algorithm. */
                        tp->snd_cwnd = tp->snd_ssthresh;
-               tp->snd_cwnd_stamp = tcp_time_stamp;
+                       tp->snd_cwnd_stamp = tcp_time_stamp;
+               }
        }
        tcp_ca_event(sk, CA_EVENT_COMPLETE_CWR);
 }

diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 376b2cf..7ac6423 100644 (file)
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -1096,6 +1096,7 @@ static void __pskb_trim_head(struct sk_buff *skb, int len)
        eat = min_t(int, len, skb_headlen(skb));
        if (eat) {
                __skb_pull(skb, eat);
+               skb->avail_size -= eat;
                len -= eat;
                if (!len)
                        return;

diff --git a/net/ipv4/udp_diag.c b/net/ipv4/udp_diag.c
index 8a949f1..a7f86a3 100644 (file)
--- a/net/ipv4/udp_diag.c
+++ b/net/ipv4/udp_diag.c
@@ -146,9 +146,17 @@ static int udp_diag_dump_one(struct sk_buff *in_skb, const struct nlmsghdr *nlh,
        return udp_dump_one(&udp_table, in_skb, nlh, req);
 }
 
+static void udp_diag_get_info(struct sock *sk, struct inet_diag_msg *r,
+               void *info)
+{
+       r->idiag_rqueue = sk_rmem_alloc_get(sk);
+       r->idiag_wqueue = sk_wmem_alloc_get(sk);
+}
+
 static const struct inet_diag_handler udp_diag_handler = {
        .dump            = udp_diag_dump,
        .dump_one        = udp_diag_dump_one,
+       .idiag_get_info  = udp_diag_get_info,
        .idiag_type      = IPPROTO_UDP,
 };
 
@@ -167,6 +175,7 @@ static int udplite_diag_dump_one(struct sk_buff *in_skb, const struct nlmsghdr *
 static const struct inet_diag_handler udplite_diag_handler = {
        .dump            = udplite_diag_dump,
        .dump_one        = udplite_diag_dump_one,
+       .idiag_get_info  = udp_diag_get_info,
        .idiag_type      = IPPROTO_UDPLITE,
 };
 

diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
index 6a3bb60..7d5cb97 100644 (file)
--- a/net/ipv6/addrconf.c
+++ b/net/ipv6/addrconf.c
@@ -803,8 +803,7 @@ static void ipv6_del_addr(struct inet6_ifaddr *ifp)
                                ip6_del_rt(rt);
                                rt = NULL;
                        } else if (!(rt->rt6i_flags & RTF_EXPIRES)) {
-                               rt->dst.expires = expires;
-                               rt->rt6i_flags |= RTF_EXPIRES;
+                               rt6_set_expires(rt, expires);
                        }
                }
                dst_release(&rt->dst);
@@ -1887,11 +1886,9 @@ void addrconf_prefix_rcv(struct net_device *dev, u8 *opt, int len, bool sllao)
                                rt = NULL;
                        } else if (addrconf_finite_timeout(rt_expires)) {
                                /* not infinity */
-                               rt->dst.expires = jiffies + rt_expires;
-                               rt->rt6i_flags |= RTF_EXPIRES;
+                               rt6_set_expires(rt, jiffies + rt_expires);
                        } else {
-                               rt->rt6i_flags &= ~RTF_EXPIRES;
-                               rt->dst.expires = 0;
+                               rt6_clean_expires(rt);
                        }
                } else if (valid_lft) {
                        clock_t expires = 0;

diff --git a/net/ipv6/ip6_fib.c b/net/ipv6/ip6_fib.c
index 5b27fbc..9371743 100644 (file)
--- a/net/ipv6/ip6_fib.c
+++ b/net/ipv6/ip6_fib.c
@@ -673,11 +673,10 @@ static int fib6_add_rt2node(struct fib6_node *fn, struct rt6_info *rt,
                                            &rt->rt6i_gateway)) {
                                if (!(iter->rt6i_flags & RTF_EXPIRES))
                                        return -EEXIST;
-                               iter->dst.expires = rt->dst.expires;
-                               if (!(rt->rt6i_flags & RTF_EXPIRES)) {
-                                       iter->rt6i_flags &= ~RTF_EXPIRES;
-                                       iter->dst.expires = 0;
-                               }
+                               if (!(rt->rt6i_flags & RTF_EXPIRES))
+                                       rt6_clean_expires(iter);
+                               else
+                                       rt6_set_expires(iter, rt->dst.expires);
                                return -EEXIST;
                        }
                }

diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c
index 3dcdb81..176b469 100644 (file)
--- a/net/ipv6/ndisc.c
+++ b/net/ipv6/ndisc.c
@@ -1264,8 +1264,7 @@ static void ndisc_router_discovery(struct sk_buff *skb)
        }
 
        if (rt)
-               rt->dst.expires = jiffies + (HZ * lifetime);
-
+               rt6_set_expires(rt, jiffies + (HZ * lifetime));
        if (ra_msg->icmph.icmp6_hop_limit) {
                in6_dev->cnf.hop_limit = ra_msg->icmph.icmp6_hop_limit;
                if (rt)

diff --git a/net/ipv6/route.c b/net/ipv6/route.c
index 3992e26..bc4888d 100644 (file)
--- a/net/ipv6/route.c
+++ b/net/ipv6/route.c
@@ -62,7 +62,7 @@
 #include <linux/sysctl.h>
 #endif
 
-static struct rt6_info *ip6_rt_copy(const struct rt6_info *ort,
+static struct rt6_info *ip6_rt_copy(struct rt6_info *ort,
                                    const struct in6_addr *dest);
 static struct dst_entry        *ip6_dst_check(struct dst_entry *dst, u32 cookie);
 static unsigned int     ip6_default_advmss(const struct dst_entry *dst);
@@ -285,6 +285,10 @@ static void ip6_dst_destroy(struct dst_entry *dst)
                rt->rt6i_idev = NULL;
                in6_dev_put(idev);
        }
+
+       if (!(rt->rt6i_flags & RTF_EXPIRES) && dst->from)
+               dst_release(dst->from);
+
        if (peer) {
                rt->rt6i_peer = NULL;
                inet_putpeer(peer);
@@ -329,8 +333,17 @@ static void ip6_dst_ifdown(struct dst_entry *dst, struct net_device *dev,
 
 static __inline__ int rt6_check_expired(const struct rt6_info *rt)
 {
-       return (rt->rt6i_flags & RTF_EXPIRES) &&
-               time_after(jiffies, rt->dst.expires);
+       struct rt6_info *ort = NULL;
+
+       if (rt->rt6i_flags & RTF_EXPIRES) {
+               if (time_after(jiffies, rt->dst.expires))
+                       return 1;
+       } else if (rt->dst.from) {
+               ort = (struct rt6_info *) rt->dst.from;
+               return (ort->rt6i_flags & RTF_EXPIRES) &&
+                       time_after(jiffies, ort->dst.expires);
+       }
+       return 0;
 }
 
 static inline int rt6_need_strict(const struct in6_addr *daddr)
@@ -620,12 +633,11 @@ int rt6_route_rcv(struct net_device *dev, u8 *opt, int len,
                                 (rt->rt6i_flags & ~RTF_PREF_MASK) | RTF_PREF(pref);
 
        if (rt) {
-               if (!addrconf_finite_timeout(lifetime)) {
-                       rt->rt6i_flags &= ~RTF_EXPIRES;
-               } else {
-                       rt->dst.expires = jiffies + HZ * lifetime;
-                       rt->rt6i_flags |= RTF_EXPIRES;
-               }
+               if (!addrconf_finite_timeout(lifetime))
+                       rt6_clean_expires(rt);
+               else
+                       rt6_set_expires(rt, jiffies + HZ * lifetime);
+
                dst_release(&rt->dst);
        }
        return 0;
@@ -730,7 +742,7 @@ int ip6_ins_rt(struct rt6_info *rt)
        return __ip6_ins_rt(rt, &info);
 }
 
-static struct rt6_info *rt6_alloc_cow(const struct rt6_info *ort,
+static struct rt6_info *rt6_alloc_cow(struct rt6_info *ort,
                                      const struct in6_addr *daddr,
                                      const struct in6_addr *saddr)
 {
@@ -954,10 +966,10 @@ struct dst_entry *ip6_blackhole_route(struct net *net, struct dst_entry *dst_ori
                rt->rt6i_idev = ort->rt6i_idev;
                if (rt->rt6i_idev)
                        in6_dev_hold(rt->rt6i_idev);
-               rt->dst.expires = 0;
 
                rt->rt6i_gateway = ort->rt6i_gateway;
-               rt->rt6i_flags = ort->rt6i_flags & ~RTF_EXPIRES;
+               rt->rt6i_flags = ort->rt6i_flags;
+               rt6_clean_expires(rt);
                rt->rt6i_metric = 0;
 
                memcpy(&rt->rt6i_dst, &ort->rt6i_dst, sizeof(struct rt6key));
@@ -1019,10 +1031,9 @@ static void ip6_link_failure(struct sk_buff *skb)
 
        rt = (struct rt6_info *) skb_dst(skb);
        if (rt) {
-               if (rt->rt6i_flags & RTF_CACHE) {
-                       dst_set_expires(&rt->dst, 0);
-                       rt->rt6i_flags |= RTF_EXPIRES;
-               } else if (rt->rt6i_node && (rt->rt6i_flags & RTF_DEFAULT))
+               if (rt->rt6i_flags & RTF_CACHE)
+                       rt6_update_expires(rt, 0);
+               else if (rt->rt6i_node && (rt->rt6i_flags & RTF_DEFAULT))
                        rt->rt6i_node->fn_sernum = -1;
        }
 }
@@ -1289,9 +1300,12 @@ int ip6_route_add(struct fib6_config *cfg)
        }
 
        rt->dst.obsolete = -1;
-       rt->dst.expires = (cfg->fc_flags & RTF_EXPIRES) ?
-                               jiffies + clock_t_to_jiffies(cfg->fc_expires) :
-                               0;
+
+       if (cfg->fc_flags & RTF_EXPIRES)
+               rt6_set_expires(rt, jiffies +
+                               clock_t_to_jiffies(cfg->fc_expires));
+       else
+               rt6_clean_expires(rt);
 
        if (cfg->fc_protocol == RTPROT_UNSPEC)
                cfg->fc_protocol = RTPROT_BOOT;
@@ -1736,8 +1750,8 @@ again:
                        features |= RTAX_FEATURE_ALLFRAG;
                        dst_metric_set(&rt->dst, RTAX_FEATURES, features);
                }
-               dst_set_expires(&rt->dst, net->ipv6.sysctl.ip6_rt_mtu_expires);
-               rt->rt6i_flags |= RTF_MODIFIED|RTF_EXPIRES;
+               rt6_update_expires(rt, net->ipv6.sysctl.ip6_rt_mtu_expires);
+               rt->rt6i_flags |= RTF_MODIFIED;
                goto out;
        }
 
@@ -1765,9 +1779,8 @@ again:
                 * which is 10 mins. After 10 mins the decreased pmtu is expired
                 * and detecting PMTU increase will be automatically happened.
                 */
-               dst_set_expires(&nrt->dst, net->ipv6.sysctl.ip6_rt_mtu_expires);
-               nrt->rt6i_flags |= RTF_DYNAMIC|RTF_EXPIRES;
-
+               rt6_update_expires(nrt, net->ipv6.sysctl.ip6_rt_mtu_expires);
+               nrt->rt6i_flags |= RTF_DYNAMIC;
                ip6_ins_rt(nrt);
        }
 out:
@@ -1799,7 +1812,7 @@ void rt6_pmtu_discovery(const struct in6_addr *daddr, const struct in6_addr *sad
  *     Misc support functions
  */
 
-static struct rt6_info *ip6_rt_copy(const struct rt6_info *ort,
+static struct rt6_info *ip6_rt_copy(struct rt6_info *ort,
                                    const struct in6_addr *dest)
 {
        struct net *net = dev_net(ort->dst.dev);
@@ -1819,10 +1832,14 @@ static struct rt6_info *ip6_rt_copy(const struct rt6_info *ort,
                if (rt->rt6i_idev)
                        in6_dev_hold(rt->rt6i_idev);
                rt->dst.lastuse = jiffies;
-               rt->dst.expires = 0;
 
                rt->rt6i_gateway = ort->rt6i_gateway;
-               rt->rt6i_flags = ort->rt6i_flags & ~RTF_EXPIRES;
+               rt->rt6i_flags = ort->rt6i_flags;
+               if ((ort->rt6i_flags & (RTF_DEFAULT | RTF_ADDRCONF)) ==
+                   (RTF_DEFAULT | RTF_ADDRCONF))
+                       rt6_set_from(rt, ort);
+               else
+                       rt6_clean_expires(rt);
                rt->rt6i_metric = 0;
 
 #ifdef CONFIG_IPV6_SUBTREES

diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c
index 86cfe60..98256cf 100644 (file)
--- a/net/ipv6/tcp_ipv6.c
+++ b/net/ipv6/tcp_ipv6.c
@@ -1383,6 +1383,10 @@ static struct sock * tcp_v6_syn_recv_sock(struct sock *sk, struct sk_buff *skb,
        tcp_mtup_init(newsk);
        tcp_sync_mss(newsk, dst_mtu(dst));
        newtp->advmss = dst_metric_advmss(dst);
+       if (tcp_sk(sk)->rx_opt.user_mss &&
+           tcp_sk(sk)->rx_opt.user_mss < newtp->advmss)
+               newtp->advmss = tcp_sk(sk)->rx_opt.user_mss;
+
        tcp_initialize_rcv_mss(newsk);
        if (tcp_rsk(req)->snt_synack)
                tcp_valid_rtt_meas(newsk,

diff --git a/net/key/af_key.c b/net/key/af_key.c
index 11dbb22..7e5d927 100644 (file)
--- a/net/key/af_key.c
+++ b/net/key/af_key.c
@@ -3480,7 +3480,7 @@ static int pfkey_send_migrate(const struct xfrm_selector *sel, u8 dir, u8 type,
 
        /* Addresses to be used by KM for negotiation, if ext is available */
        if (k != NULL && (set_sadb_kmaddress(skb, k) < 0))
-               return -EINVAL;
+               goto err;
 
        /* selector src */
        set_sadb_address(skb, sasize_sel, SADB_EXT_ADDRESS_SRC, sel);

diff --git a/net/l2tp/l2tp_ip.c b/net/l2tp/l2tp_ip.c
index 55670ec..6274f0b 100644 (file)
--- a/net/l2tp/l2tp_ip.c
+++ b/net/l2tp/l2tp_ip.c
@@ -232,7 +232,7 @@ static void l2tp_ip_close(struct sock *sk, long timeout)
 {
        write_lock_bh(&l2tp_ip_lock);
        hlist_del_init(&sk->sk_bind_node);
-       hlist_del_init(&sk->sk_node);
+       sk_del_node_init(sk);
        write_unlock_bh(&l2tp_ip_lock);
        sk_common_release(sk);
 }
@@ -271,7 +271,8 @@ static int l2tp_ip_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len)
            chk_addr_ret != RTN_MULTICAST && chk_addr_ret != RTN_BROADCAST)
                goto out;
 
-       inet->inet_rcv_saddr = inet->inet_saddr = addr->l2tp_addr.s_addr;
+       if (addr->l2tp_addr.s_addr)
+               inet->inet_rcv_saddr = inet->inet_saddr = addr->l2tp_addr.s_addr;
        if (chk_addr_ret == RTN_MULTICAST || chk_addr_ret == RTN_BROADCAST)
                inet->inet_saddr = 0;  /* Use device */
        sk_dst_reset(sk);
@@ -441,8 +442,9 @@ static int l2tp_ip_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *m
 
                daddr = lip->l2tp_addr.s_addr;
        } else {
+               rc = -EDESTADDRREQ;
                if (sk->sk_state != TCP_ESTABLISHED)
-                       return -EDESTADDRREQ;
+                       goto out;
 
                daddr = inet->inet_daddr;
                connected = 1;

diff --git a/net/mac80211/ibss.c b/net/mac80211/ibss.c
index 33fd8d9..cef7c29 100644 (file)
--- a/net/mac80211/ibss.c
+++ b/net/mac80211/ibss.c
@@ -457,8 +457,8 @@ static void ieee80211_rx_bss_info(struct ieee80211_sub_if_data *sdata,
                         * fall back to HT20 if we don't use or use
                         * the other extension channel
                         */
-                       if ((channel_type == NL80211_CHAN_HT40MINUS ||
-                            channel_type == NL80211_CHAN_HT40PLUS) &&
+                       if (!(channel_type == NL80211_CHAN_HT40MINUS ||
+                             channel_type == NL80211_CHAN_HT40PLUS) ||
                            channel_type != sdata->u.ibss.channel_type)
                                sta_ht_cap_new.cap &=
                                        ~IEEE80211_HT_CAP_SUP_WIDTH_20_40;

diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h
index d9798a3..db8fae5 100644 (file)
--- a/net/mac80211/ieee80211_i.h
+++ b/net/mac80211/ieee80211_i.h
@@ -1210,7 +1210,7 @@ void ieee80211_sta_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata,
                                  struct sk_buff *skb);
 void ieee80211_sta_reset_beacon_monitor(struct ieee80211_sub_if_data *sdata);
 void ieee80211_sta_reset_conn_monitor(struct ieee80211_sub_if_data *sdata);
-void ieee80211_mgd_teardown(struct ieee80211_sub_if_data *sdata);
+void ieee80211_mgd_stop(struct ieee80211_sub_if_data *sdata);
 
 /* IBSS code */
 void ieee80211_ibss_notify_scan_completed(struct ieee80211_local *local);

diff --git a/net/mac80211/iface.c b/net/mac80211/iface.c
index 401c01f..c20051b 100644 (file)
--- a/net/mac80211/iface.c
+++ b/net/mac80211/iface.c
@@ -486,6 +486,8 @@ static void ieee80211_do_stop(struct ieee80211_sub_if_data *sdata,
                /* free all potentially still buffered bcast frames */
                local->total_ps_buffered -= skb_queue_len(&sdata->u.ap.ps_bc_buf);
                skb_queue_purge(&sdata->u.ap.ps_bc_buf);
+       } else if (sdata->vif.type == NL80211_IFTYPE_STATION) {
+               ieee80211_mgd_stop(sdata);
        }
 
        if (going_down)
@@ -644,8 +646,6 @@ static void ieee80211_teardown_sdata(struct net_device *dev)
 
        if (ieee80211_vif_is_mesh(&sdata->vif))
                mesh_rmc_free(sdata);
-       else if (sdata->vif.type == NL80211_IFTYPE_STATION)
-               ieee80211_mgd_teardown(sdata);
 
        flushed = sta_info_flush(local, sdata);
        WARN_ON(flushed);

diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index f76da5b..20c680b 100644 (file)
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -3497,7 +3497,7 @@ int ieee80211_mgd_disassoc(struct ieee80211_sub_if_data *sdata,
        return 0;
 }
 
-void ieee80211_mgd_teardown(struct ieee80211_sub_if_data *sdata)
+void ieee80211_mgd_stop(struct ieee80211_sub_if_data *sdata)
 {
        struct ieee80211_if_managed *ifmgd = &sdata->u.mgd;
 

diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c
index bcfe8c7..d64e285 100644 (file)
--- a/net/mac80211/rx.c
+++ b/net/mac80211/rx.c
@@ -103,7 +103,7 @@ static void
 ieee80211_add_rx_radiotap_header(struct ieee80211_local *local,
                                 struct sk_buff *skb,
                                 struct ieee80211_rate *rate,
-                                int rtap_len)
+                                int rtap_len, bool has_fcs)
 {
        struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb);
        struct ieee80211_radiotap_header *rthdr;
@@ -134,7 +134,7 @@ ieee80211_add_rx_radiotap_header(struct ieee80211_local *local,
        }
 
        /* IEEE80211_RADIOTAP_FLAGS */
-       if (local->hw.flags & IEEE80211_HW_RX_INCLUDES_FCS)
+       if (has_fcs && (local->hw.flags & IEEE80211_HW_RX_INCLUDES_FCS))
                *pos |= IEEE80211_RADIOTAP_F_FCS;
        if (status->flag & (RX_FLAG_FAILED_FCS_CRC | RX_FLAG_FAILED_PLCP_CRC))
                *pos |= IEEE80211_RADIOTAP_F_BADFCS;
@@ -294,7 +294,8 @@ ieee80211_rx_monitor(struct ieee80211_local *local, struct sk_buff *origskb,
        }
 
        /* prepend radiotap information */
-       ieee80211_add_rx_radiotap_header(local, skb, rate, needed_headroom);
+       ieee80211_add_rx_radiotap_header(local, skb, rate, needed_headroom,
+                                        true);
 
        skb_reset_mac_header(skb);
        skb->ip_summed = CHECKSUM_UNNECESSARY;
@@ -2571,7 +2572,8 @@ static void ieee80211_rx_cooked_monitor(struct ieee80211_rx_data *rx,
                goto out_free_skb;
 
        /* prepend radiotap information */
-       ieee80211_add_rx_radiotap_header(local, skb, rate, needed_headroom);
+       ieee80211_add_rx_radiotap_header(local, skb, rate, needed_headroom,
+                                        false);
 
        skb_set_mac_header(skb, 0);
        skb->ip_summed = CHECKSUM_UNNECESSARY;

diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c
index 782a601..e76facc 100644 (file)
--- a/net/mac80211/tx.c
+++ b/net/mac80211/tx.c
@@ -1158,7 +1158,8 @@ ieee80211_tx_prepare(struct ieee80211_sub_if_data *sdata,
                tx->sta = rcu_dereference(sdata->u.vlan.sta);
                if (!tx->sta && sdata->dev->ieee80211_ptr->use_4addr)
                        return TX_DROP;
-       } else if (info->flags & IEEE80211_TX_CTL_INJECTED) {
+       } else if (info->flags & IEEE80211_TX_CTL_INJECTED ||
+                  tx->sdata->control_port_protocol == tx->skb->protocol) {
                tx->sta = sta_info_get_bss(sdata, hdr->addr1);
        }
        if (!tx->sta)

diff --git a/net/netfilter/ipvs/ip_vs_core.c b/net/netfilter/ipvs/ip_vs_core.c
index 2555816..00bdb1d 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_core.c
+++ b/net/netfilter/ipvs/ip_vs_core.c
@@ -1924,6 +1924,7 @@ protocol_fail:
 control_fail:
        ip_vs_estimator_net_cleanup(net);
 estimator_fail:
+       net->ipvs = NULL;
        return -ENOMEM;
 }
 
@@ -1936,6 +1937,7 @@ static void __net_exit __ip_vs_cleanup(struct net *net)
        ip_vs_control_net_cleanup(net);
        ip_vs_estimator_net_cleanup(net);
        IP_VS_DBG(2, "ipvs netns %d released\n", net_ipvs(net)->gen);
+       net->ipvs = NULL;
 }
 
 static void __net_exit __ip_vs_dev_cleanup(struct net *net)
@@ -1993,10 +1995,18 @@ static int __init ip_vs_init(void)
                goto cleanup_dev;
        }
 
+       ret = ip_vs_register_nl_ioctl();
+       if (ret < 0) {
+               pr_err("can't register netlink/ioctl.\n");
+               goto cleanup_hooks;
+       }
+
        pr_info("ipvs loaded.\n");
 
        return ret;
 
+cleanup_hooks:
+       nf_unregister_hooks(ip_vs_ops, ARRAY_SIZE(ip_vs_ops));
 cleanup_dev:
        unregister_pernet_device(&ipvs_core_dev_ops);
 cleanup_sub:
@@ -2012,6 +2022,7 @@ exit:
 
 static void __exit ip_vs_cleanup(void)
 {
+       ip_vs_unregister_nl_ioctl();
        nf_unregister_hooks(ip_vs_ops, ARRAY_SIZE(ip_vs_ops));
        unregister_pernet_device(&ipvs_core_dev_ops);
        unregister_pernet_subsys(&ipvs_core_ops);       /* free ip_vs struct */

diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c
index b3afe18..f558998 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_ctl.c
+++ b/net/netfilter/ipvs/ip_vs_ctl.c
@@ -3680,7 +3680,7 @@ int __net_init ip_vs_control_net_init_sysctl(struct net *net)
        return 0;
 }
 
-void __net_init ip_vs_control_net_cleanup_sysctl(struct net *net)
+void __net_exit ip_vs_control_net_cleanup_sysctl(struct net *net)
 {
        struct netns_ipvs *ipvs = net_ipvs(net);
 
@@ -3692,7 +3692,7 @@ void __net_init ip_vs_control_net_cleanup_sysctl(struct net *net)
 #else
 
 int __net_init ip_vs_control_net_init_sysctl(struct net *net) { return 0; }
-void __net_init ip_vs_control_net_cleanup_sysctl(struct net *net) { }
+void __net_exit ip_vs_control_net_cleanup_sysctl(struct net *net) { }
 
 #endif
 
@@ -3750,21 +3750,10 @@ void __net_exit ip_vs_control_net_cleanup(struct net *net)
        free_percpu(ipvs->tot_stats.cpustats);
 }
 
-int __init ip_vs_control_init(void)
+int __init ip_vs_register_nl_ioctl(void)
 {
-       int idx;
        int ret;
 
-       EnterFunction(2);
-
-       /* Initialize svc_table, ip_vs_svc_fwm_table, rs_table */
-       for(idx = 0; idx < IP_VS_SVC_TAB_SIZE; idx++)  {
-               INIT_LIST_HEAD(&ip_vs_svc_table[idx]);
-               INIT_LIST_HEAD(&ip_vs_svc_fwm_table[idx]);
-       }
-
-       smp_wmb();      /* Do we really need it now ? */
-
        ret = nf_register_sockopt(&ip_vs_sockopts);
        if (ret) {
                pr_err("cannot register sockopt.\n");
@@ -3776,28 +3765,47 @@ int __init ip_vs_control_init(void)
                pr_err("cannot register Generic Netlink interface.\n");
                goto err_genl;
        }
-
-       ret = register_netdevice_notifier(&ip_vs_dst_notifier);
-       if (ret < 0)
-               goto err_notf;
-
-       LeaveFunction(2);
        return 0;
 
-err_notf:
-       ip_vs_genl_unregister();
 err_genl:
        nf_unregister_sockopt(&ip_vs_sockopts);
 err_sock:
        return ret;
 }
 
+void ip_vs_unregister_nl_ioctl(void)
+{
+       ip_vs_genl_unregister();
+       nf_unregister_sockopt(&ip_vs_sockopts);
+}
+
+int __init ip_vs_control_init(void)
+{
+       int idx;
+       int ret;
+
+       EnterFunction(2);
+
+       /* Initialize svc_table, ip_vs_svc_fwm_table, rs_table */
+       for (idx = 0; idx < IP_VS_SVC_TAB_SIZE; idx++) {
+               INIT_LIST_HEAD(&ip_vs_svc_table[idx]);
+               INIT_LIST_HEAD(&ip_vs_svc_fwm_table[idx]);
+       }
+
+       smp_wmb();      /* Do we really need it now ? */
+
+       ret = register_netdevice_notifier(&ip_vs_dst_notifier);
+       if (ret < 0)
+               return ret;
+
+       LeaveFunction(2);
+       return 0;
+}
+
 
 void ip_vs_control_cleanup(void)
 {
        EnterFunction(2);
        unregister_netdevice_notifier(&ip_vs_dst_notifier);
-       ip_vs_genl_unregister();
-       nf_unregister_sockopt(&ip_vs_sockopts);
        LeaveFunction(2);
 }

diff --git a/net/netfilter/ipvs/ip_vs_ftp.c b/net/netfilter/ipvs/ip_vs_ftp.c
index 538d74e..e39f693 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_ftp.c
+++ b/net/netfilter/ipvs/ip_vs_ftp.c
@@ -439,6 +439,8 @@ static int __net_init __ip_vs_ftp_init(struct net *net)
        struct ip_vs_app *app;
        struct netns_ipvs *ipvs = net_ipvs(net);
 
+       if (!ipvs)
+               return -ENOENT;
        app = kmemdup(&ip_vs_ftp, sizeof(struct ip_vs_app), GFP_KERNEL);
        if (!app)
                return -ENOMEM;

diff --git a/net/netfilter/ipvs/ip_vs_lblc.c b/net/netfilter/ipvs/ip_vs_lblc.c
index 0f16283..caa4370 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_lblc.c
+++ b/net/netfilter/ipvs/ip_vs_lblc.c
@@ -551,6 +551,9 @@ static int __net_init __ip_vs_lblc_init(struct net *net)
 {
        struct netns_ipvs *ipvs = net_ipvs(net);
 
+       if (!ipvs)
+               return -ENOENT;
+
        if (!net_eq(net, &init_net)) {
                ipvs->lblc_ctl_table = kmemdup(vs_vars_table,
                                                sizeof(vs_vars_table),

diff --git a/net/netfilter/ipvs/ip_vs_lblcr.c b/net/netfilter/ipvs/ip_vs_lblcr.c
index eec797f..548bf37 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_lblcr.c
+++ b/net/netfilter/ipvs/ip_vs_lblcr.c
@@ -745,6 +745,9 @@ static int __net_init __ip_vs_lblcr_init(struct net *net)
 {
        struct netns_ipvs *ipvs = net_ipvs(net);
 
+       if (!ipvs)
+               return -ENOENT;
+
        if (!net_eq(net, &init_net)) {
                ipvs->lblcr_ctl_table = kmemdup(vs_vars_table,
                                                sizeof(vs_vars_table),

diff --git a/net/netfilter/ipvs/ip_vs_proto.c b/net/netfilter/ipvs/ip_vs_proto.c
index f843a88..ed835e6 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_proto.c
+++ b/net/netfilter/ipvs/ip_vs_proto.c
@@ -59,9 +59,6 @@ static int __used __init register_ip_vs_protocol(struct ip_vs_protocol *pp)
        return 0;
 }
 
-#if defined(CONFIG_IP_VS_PROTO_TCP) || defined(CONFIG_IP_VS_PROTO_UDP) || \
-    defined(CONFIG_IP_VS_PROTO_SCTP) || defined(CONFIG_IP_VS_PROTO_AH) || \
-    defined(CONFIG_IP_VS_PROTO_ESP)
 /*
  *     register an ipvs protocols netns related data
  */
@@ -81,12 +78,18 @@ register_ip_vs_proto_netns(struct net *net, struct ip_vs_protocol *pp)
        ipvs->proto_data_table[hash] = pd;
        atomic_set(&pd->appcnt, 0);     /* Init app counter */
 
-       if (pp->init_netns != NULL)
-               pp->init_netns(net, pd);
+       if (pp->init_netns != NULL) {
+               int ret = pp->init_netns(net, pd);
+               if (ret) {
+                       /* unlink an free proto data */
+                       ipvs->proto_data_table[hash] = pd->next;
+                       kfree(pd);
+                       return ret;
+               }
+       }
 
        return 0;
 }
-#endif
 
 /*
  *     unregister an ipvs protocol
@@ -316,22 +319,35 @@ ip_vs_tcpudp_debug_packet(int af, struct ip_vs_protocol *pp,
  */
 int __net_init ip_vs_protocol_net_init(struct net *net)
 {
+       int i, ret;
+       static struct ip_vs_protocol *protos[] = {
 #ifdef CONFIG_IP_VS_PROTO_TCP
-       register_ip_vs_proto_netns(net, &ip_vs_protocol_tcp);
+        &ip_vs_protocol_tcp,
 #endif
 #ifdef CONFIG_IP_VS_PROTO_UDP
-       register_ip_vs_proto_netns(net, &ip_vs_protocol_udp);
+       &ip_vs_protocol_udp,
 #endif
 #ifdef CONFIG_IP_VS_PROTO_SCTP
-       register_ip_vs_proto_netns(net, &ip_vs_protocol_sctp);
+       &ip_vs_protocol_sctp,
 #endif
 #ifdef CONFIG_IP_VS_PROTO_AH
-       register_ip_vs_proto_netns(net, &ip_vs_protocol_ah);
+       &ip_vs_protocol_ah,
 #endif
 #ifdef CONFIG_IP_VS_PROTO_ESP
-       register_ip_vs_proto_netns(net, &ip_vs_protocol_esp);
+       &ip_vs_protocol_esp,
 #endif
+       };
+
+       for (i = 0; i < ARRAY_SIZE(protos); i++) {
+               ret = register_ip_vs_proto_netns(net, protos[i]);
+               if (ret < 0)
+                       goto cleanup;
+       }
        return 0;
+
+cleanup:
+       ip_vs_protocol_net_cleanup(net);
+       return ret;
 }
 
 void __net_exit ip_vs_protocol_net_cleanup(struct net *net)

diff --git a/net/netfilter/ipvs/ip_vs_proto_sctp.c b/net/netfilter/ipvs/ip_vs_proto_sctp.c
index 1fbf7a2..9f3fb75 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_proto_sctp.c
+++ b/net/netfilter/ipvs/ip_vs_proto_sctp.c
@@ -1090,7 +1090,7 @@ out:
  *   timeouts is netns related now.
  * ---------------------------------------------
  */
-static void __ip_vs_sctp_init(struct net *net, struct ip_vs_proto_data *pd)
+static int __ip_vs_sctp_init(struct net *net, struct ip_vs_proto_data *pd)
 {
        struct netns_ipvs *ipvs = net_ipvs(net);
 
@@ -1098,6 +1098,9 @@ static void __ip_vs_sctp_init(struct net *net, struct ip_vs_proto_data *pd)
        spin_lock_init(&ipvs->sctp_app_lock);
        pd->timeout_table = ip_vs_create_timeout_table((int *)sctp_timeouts,
                                                        sizeof(sctp_timeouts));
+       if (!pd->timeout_table)
+               return -ENOMEM;
+       return 0;
 }
 
 static void __ip_vs_sctp_exit(struct net *net, struct ip_vs_proto_data *pd)

diff --git a/net/netfilter/ipvs/ip_vs_proto_tcp.c b/net/netfilter/ipvs/ip_vs_proto_tcp.c
index ef8641f..cd609cc 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_proto_tcp.c
+++ b/net/netfilter/ipvs/ip_vs_proto_tcp.c
@@ -677,7 +677,7 @@ void ip_vs_tcp_conn_listen(struct net *net, struct ip_vs_conn *cp)
  *   timeouts is netns related now.
  * ---------------------------------------------
  */
-static void __ip_vs_tcp_init(struct net *net, struct ip_vs_proto_data *pd)
+static int __ip_vs_tcp_init(struct net *net, struct ip_vs_proto_data *pd)
 {
        struct netns_ipvs *ipvs = net_ipvs(net);
 
@@ -685,7 +685,10 @@ static void __ip_vs_tcp_init(struct net *net, struct ip_vs_proto_data *pd)
        spin_lock_init(&ipvs->tcp_app_lock);
        pd->timeout_table = ip_vs_create_timeout_table((int *)tcp_timeouts,
                                                        sizeof(tcp_timeouts));
+       if (!pd->timeout_table)
+               return -ENOMEM;
        pd->tcp_state_table =  tcp_states;
+       return 0;
 }
 
 static void __ip_vs_tcp_exit(struct net *net, struct ip_vs_proto_data *pd)

diff --git a/net/netfilter/ipvs/ip_vs_proto_udp.c b/net/netfilter/ipvs/ip_vs_proto_udp.c
index f4b7262..2fedb2d 100644 (file)
--- a/net/netfilter/ipvs/ip_vs_proto_udp.c
+++ b/net/netfilter/ipvs/ip_vs_proto_udp.c
@@ -467,7 +467,7 @@ udp_state_transition(struct ip_vs_conn *cp, int direction,
        cp->timeout = pd->timeout_table[IP_VS_UDP_S_NORMAL];
 }
 
-static void __udp_init(struct net *net, struct ip_vs_proto_data *pd)
+static int __udp_init(struct net *net, struct ip_vs_proto_data *pd)
 {
        struct netns_ipvs *ipvs = net_ipvs(net);
 
@@ -475,6 +475,9 @@ static void __udp_init(struct net *net, struct ip_vs_proto_data *pd)
        spin_lock_init(&ipvs->udp_app_lock);
        pd->timeout_table = ip_vs_create_timeout_table((int *)udp_timeouts,
                                                        sizeof(udp_timeouts));
+       if (!pd->timeout_table)
+               return -ENOMEM;
+       return 0;
 }
 
 static void __udp_exit(struct net *net, struct ip_vs_proto_data *pd)

diff --git a/net/netfilter/xt_CT.c b/net/netfilter/xt_CT.c
index 59530e9..3746d8b 100644 (file)
--- a/net/netfilter/xt_CT.c
+++ b/net/netfilter/xt_CT.c
@@ -227,7 +227,7 @@ static int xt_ct_tg_check_v1(const struct xt_tgchk_param *par)
        }
 
 #ifdef CONFIG_NF_CONNTRACK_TIMEOUT
-       if (info->timeout) {
+       if (info->timeout[0]) {
                typeof(nf_ct_timeout_find_get_hook) timeout_find_get;
                struct nf_conn_timeout *timeout_ext;
 

diff --git a/net/phonet/pn_dev.c b/net/phonet/pn_dev.c
index 9b9a85e..bf5cf69 100644 (file)
--- a/net/phonet/pn_dev.c
+++ b/net/phonet/pn_dev.c
@@ -331,23 +331,6 @@ static int __net_init phonet_init_net(struct net *net)
 
 static void __net_exit phonet_exit_net(struct net *net)
 {
-       struct phonet_net *pnn = phonet_pernet(net);
-       struct net_device *dev;
-       unsigned i;
-
-       rtnl_lock();
-       for_each_netdev(net, dev)
-               phonet_device_destroy(dev);
-
-       for (i = 0; i < 64; i++) {
-               dev = pnn->routes.table[i];
-               if (dev) {
-                       rtm_phonet_notify(RTM_DELROUTE, dev, i);
-                       dev_put(dev);
-               }
-       }
-       rtnl_unlock();
-
        proc_net_remove(net, "phonet");
 }
 
@@ -361,7 +344,7 @@ static struct pernet_operations phonet_net_ops = {
 /* Initialize Phonet devices list */
 int __init phonet_device_init(void)
 {
-       int err = register_pernet_device(&phonet_net_ops);
+       int err = register_pernet_subsys(&phonet_net_ops);
        if (err)
                return err;
 
@@ -377,7 +360,7 @@ void phonet_device_exit(void)
 {
        rtnl_unregister_all(PF_PHONET);
        unregister_netdevice_notifier(&phonet_device_notifier);
-       unregister_pernet_device(&phonet_net_ops);
+       unregister_pernet_subsys(&phonet_net_ops);
        proc_net_remove(&init_net, "pnresource");
 }
 

diff --git a/net/sched/sch_gred.c b/net/sched/sch_gred.c
index 0b15236..8179494 100644 (file)
--- a/net/sched/sch_gred.c
+++ b/net/sched/sch_gred.c
@@ -565,11 +565,8 @@ static int gred_dump(struct Qdisc *sch, struct sk_buff *skb)
                opt.packets     = q->packetsin;
                opt.bytesin     = q->bytesin;
 
-               if (gred_wred_mode(table)) {
-                       q->vars.qidlestart =
-                               table->tab[table->def]->vars.qidlestart;
-                       q->vars.qavg = table->tab[table->def]->vars.qavg;
-               }
+               if (gred_wred_mode(table))
+                       gred_load_wred_set(table, q);
 
                opt.qave = red_calc_qavg(&q->parms, &q->vars, q->vars.qavg);
 

diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c
index 5da548f..ebd2296 100644 (file)
--- a/net/sched/sch_netem.c
+++ b/net/sched/sch_netem.c
@@ -408,10 +408,8 @@ static int netem_enqueue(struct sk_buff *skb, struct Qdisc *sch)
        if (q->corrupt && q->corrupt >= get_crandom(&q->corrupt_cor)) {
                if (!(skb = skb_unshare(skb, GFP_ATOMIC)) ||
                    (skb->ip_summed == CHECKSUM_PARTIAL &&
-                    skb_checksum_help(skb))) {
-                       sch->qstats.drops++;
-                       return NET_XMIT_DROP;
-               }
+                    skb_checksum_help(skb)))
+                       return qdisc_drop(skb, sch);
 
                skb->data[net_random() % skb_headlen(skb)] ^= 1<<(net_random() % 8);
        }

diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c
index 6797246..adf2990 100644 (file)
--- a/net/sunrpc/clnt.c
+++ b/net/sunrpc/clnt.c
@@ -176,16 +176,22 @@ rpc_setup_pipedir(struct rpc_clnt *clnt, const char *dir_name)
        return 0;
 }
 
-static int __rpc_pipefs_event(struct rpc_clnt *clnt, unsigned long event,
-                               struct super_block *sb)
+static inline int rpc_clnt_skip_event(struct rpc_clnt *clnt, unsigned long event)
+{
+       if (((event == RPC_PIPEFS_MOUNT) && clnt->cl_dentry) ||
+           ((event == RPC_PIPEFS_UMOUNT) && !clnt->cl_dentry))
+               return 1;
+       return 0;
+}
+
+static int __rpc_clnt_handle_event(struct rpc_clnt *clnt, unsigned long event,
+                                  struct super_block *sb)
 {
        struct dentry *dentry;
        int err = 0;
 
        switch (event) {
        case RPC_PIPEFS_MOUNT:
-               if (clnt->cl_program->pipe_dir_name == NULL)
-                       break;
                dentry = rpc_setup_pipedir_sb(sb, clnt,
                                              clnt->cl_program->pipe_dir_name);
                BUG_ON(dentry == NULL);
@@ -208,6 +214,20 @@ static int __rpc_pipefs_event(struct rpc_clnt *clnt, unsigned long event,
        return err;
 }
 
+static int __rpc_pipefs_event(struct rpc_clnt *clnt, unsigned long event,
+                               struct super_block *sb)
+{
+       int error = 0;
+
+       for (;; clnt = clnt->cl_parent) {
+               if (!rpc_clnt_skip_event(clnt, event))
+                       error = __rpc_clnt_handle_event(clnt, event, sb);
+               if (error || clnt == clnt->cl_parent)
+                       break;
+       }
+       return error;
+}
+
 static struct rpc_clnt *rpc_get_client_for_event(struct net *net, int event)
 {
        struct sunrpc_net *sn = net_generic(net, sunrpc_net_id);
@@ -215,10 +235,12 @@ static struct rpc_clnt *rpc_get_client_for_event(struct net *net, int event)
 
        spin_lock(&sn->rpc_client_lock);
        list_for_each_entry(clnt, &sn->all_clients, cl_clients) {
-               if (((event == RPC_PIPEFS_MOUNT) && clnt->cl_dentry) ||
-                   ((event == RPC_PIPEFS_UMOUNT) && !clnt->cl_dentry))
+               if (clnt->cl_program->pipe_dir_name == NULL)
+                       break;
+               if (rpc_clnt_skip_event(clnt, event))
+                       continue;
+               if (atomic_inc_not_zero(&clnt->cl_count) == 0)
                        continue;
-               atomic_inc(&clnt->cl_count);
                spin_unlock(&sn->rpc_client_lock);
                return clnt;
        }
@@ -257,6 +279,14 @@ void rpc_clients_notifier_unregister(void)
        return rpc_pipefs_notifier_unregister(&rpc_clients_block);
 }
 
+static void rpc_clnt_set_nodename(struct rpc_clnt *clnt, const char *nodename)
+{
+       clnt->cl_nodelen = strlen(nodename);
+       if (clnt->cl_nodelen > UNX_MAXNODENAME)
+               clnt->cl_nodelen = UNX_MAXNODENAME;
+       memcpy(clnt->cl_nodename, nodename, clnt->cl_nodelen);
+}
+
 static struct rpc_clnt * rpc_new_client(const struct rpc_create_args *args, struct rpc_xprt *xprt)
 {
        const struct rpc_program *program = args->program;
@@ -337,10 +367,7 @@ static struct rpc_clnt * rpc_new_client(const struct rpc_create_args *args, stru
        }
 
        /* save the nodename */
-       clnt->cl_nodelen = strlen(init_utsname()->nodename);
-       if (clnt->cl_nodelen > UNX_MAXNODENAME)
-               clnt->cl_nodelen = UNX_MAXNODENAME;
-       memcpy(clnt->cl_nodename, init_utsname()->nodename, clnt->cl_nodelen);
+       rpc_clnt_set_nodename(clnt, utsname()->nodename);
        rpc_register_client(clnt);
        return clnt;
 
@@ -499,6 +526,7 @@ rpc_clone_client(struct rpc_clnt *clnt)
        err = rpc_setup_pipedir(new, clnt->cl_program->pipe_dir_name);
        if (err != 0)
                goto out_no_path;
+       rpc_clnt_set_nodename(new, utsname()->nodename);
        if (new->cl_auth)
                atomic_inc(&new->cl_auth->au_count);
        atomic_inc(&clnt->cl_count);

diff --git a/net/sunrpc/rpc_pipe.c b/net/sunrpc/rpc_pipe.c
index 0af37fc..3b62cf2 100644 (file)
--- a/net/sunrpc/rpc_pipe.c
+++ b/net/sunrpc/rpc_pipe.c
@@ -1126,19 +1126,20 @@ rpc_fill_super(struct super_block *sb, void *data, int silent)
                return -ENOMEM;
        dprintk("RPC:   sending pipefs MOUNT notification for net %p%s\n", net,
                                                                NET_NAME(net));
+       sn->pipefs_sb = sb;
        err = blocking_notifier_call_chain(&rpc_pipefs_notifier_list,
                                           RPC_PIPEFS_MOUNT,
                                           sb);
        if (err)
                goto err_depopulate;
        sb->s_fs_info = get_net(net);
-       sn->pipefs_sb = sb;
        return 0;
 
 err_depopulate:
        blocking_notifier_call_chain(&rpc_pipefs_notifier_list,
                                           RPC_PIPEFS_UMOUNT,
                                           sb);
+       sn->pipefs_sb = NULL;
        __rpc_depopulate(root, files, RPCAUTH_lockd, RPCAUTH_RootEOF);
        return err;
 }

diff --git a/net/sunrpc/sunrpc_syms.c b/net/sunrpc/sunrpc_syms.c
index 8adfc88..3d6498a 100644 (file)
--- a/net/sunrpc/sunrpc_syms.c
+++ b/net/sunrpc/sunrpc_syms.c
@@ -75,20 +75,21 @@ static struct pernet_operations sunrpc_net_ops = {
 static int __init
 init_sunrpc(void)
 {
-       int err = register_rpc_pipefs();
+       int err = rpc_init_mempool();
        if (err)
                goto out;
-       err = rpc_init_mempool();
-       if (err)
-               goto out2;
        err = rpcauth_init_module();
        if (err)
-               goto out3;
+               goto out2;
 
        cache_initialize();
 
        err = register_pernet_subsys(&sunrpc_net_ops);
        if (err)
+               goto out3;
+
+       err = register_rpc_pipefs();
+       if (err)
                goto out4;
 #ifdef RPC_DEBUG
        rpc_register_sysctl();
@@ -98,11 +99,11 @@ init_sunrpc(void)
        return 0;
 
 out4:
-       rpcauth_remove_module();
+       unregister_pernet_subsys(&sunrpc_net_ops);
 out3:
-       rpc_destroy_mempool();
+       rpcauth_remove_module();
 out2:
-       unregister_rpc_pipefs();
+       rpc_destroy_mempool();
 out:
        return err;
 }

diff --git a/net/wireless/util.c b/net/wireless/util.c
index 1b7a08d..957f256 100644 (file)
--- a/net/wireless/util.c
+++ b/net/wireless/util.c
@@ -989,7 +989,7 @@ int cfg80211_can_change_interface(struct cfg80211_registered_device *rdev,
                        if (rdev->wiphy.software_iftypes & BIT(iftype))
                                continue;
                        for (j = 0; j < c->n_limits; j++) {
-                               if (!(limits[j].types & iftype))
+                               if (!(limits[j].types & BIT(iftype)))
                                        continue;
                                if (limits[j].max < num[iftype])
                                        goto cont;

diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index 8e730cc..44ddaa5 100644 (file)
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1100,6 +1100,10 @@ void handle_moddevtable(struct module *mod, struct elf_info *info,
        if (!sym->st_shndx || get_secindex(info, sym) >= info->num_sections)
                return;
 
+       /* We're looking for an object */
+       if (ELF_ST_TYPE(sym->st_info) != STT_OBJECT)
+               return;
+
        /* All our symbols are of form <prefix>__mod_XXX_device_table. */
        name = strstr(symname, "__mod_");
        if (!name)

diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index e65e354..818f90b 100644 (file)
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -6109,6 +6109,7 @@ static const struct alc_fixup alc269_fixups[] = {
 
 static const struct snd_pci_quirk alc269_fixup_tbl[] = {
        SND_PCI_QUIRK(0x103c, 0x1586, "HP", ALC269_FIXUP_MIC2_MUTE_LED),
+       SND_PCI_QUIRK(0x1043, 0x1427, "Asus Zenbook UX31E", ALC269VB_FIXUP_DMIC),
        SND_PCI_QUIRK(0x1043, 0x1a13, "Asus G73Jw", ALC269_FIXUP_ASUS_G73JW),
        SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC),
        SND_PCI_QUIRK(0x1043, 0x831a, "ASUS P901", ALC269_FIXUP_STEREO_DMIC),

diff --git a/sound/soc/blackfin/bf5xx-ssm2602.c b/sound/soc/blackfin/bf5xx-ssm2602.c
index df3ac73..b39ad35 100644 (file)
--- a/sound/soc/blackfin/bf5xx-ssm2602.c
+++ b/sound/soc/blackfin/bf5xx-ssm2602.c
@@ -99,6 +99,7 @@ static struct snd_soc_dai_link bf5xx_ssm2602_dai[] = {
                .platform_name = "bfin-i2s-pcm-audio",
                .codec_name = "ssm2602.0-001b",
                .ops = &bf5xx_ssm2602_ops,
+               .dai_fmt = BF5XX_SSM2602_DAIFMT,
        },
        {
                .name = "ssm2602",
@@ -108,6 +109,7 @@ static struct snd_soc_dai_link bf5xx_ssm2602_dai[] = {
                .platform_name = "bfin-i2s-pcm-audio",
                .codec_name = "ssm2602.0-001b",
                .ops = &bf5xx_ssm2602_ops,
+               .dai_fmt = BF5XX_SSM2602_DAIFMT,
        },
 };
 

diff --git a/sound/soc/codecs/cs42l73.c b/sound/soc/codecs/cs42l73.c
index 78979b3..07c44b7 100644 (file)
--- a/sound/soc/codecs/cs42l73.c
+++ b/sound/soc/codecs/cs42l73.c
@@ -929,6 +929,8 @@ static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq)
 
        /* MCLKX -> MCLK */
        mclkx_coeff = cs42l73_get_mclkx_coeff(freq);
+       if (mclkx_coeff < 0)
+               return mclkx_coeff;
 
        mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx /
                cs42l73_mclkx_coeffs[mclkx_coeff].ratio;

diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c
index 16d55f9..df1e07f 100644 (file)
--- a/sound/soc/codecs/tlv320aic23.c
+++ b/sound/soc/codecs/tlv320aic23.c
@@ -472,7 +472,7 @@ static int tlv320aic23_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 static int tlv320aic23_set_bias_level(struct snd_soc_codec *codec,
                                      enum snd_soc_bias_level level)
 {
-       u16 reg = snd_soc_read(codec, TLV320AIC23_PWR) & 0xff7f;
+       u16 reg = snd_soc_read(codec, TLV320AIC23_PWR) & 0x17f;
 
        switch (level) {
        case SND_SOC_BIAS_ON:
@@ -491,7 +491,7 @@ static int tlv320aic23_set_bias_level(struct snd_soc_codec *codec,
        case SND_SOC_BIAS_OFF:
                /* everything off, dac mute, inactive */
                snd_soc_write(codec, TLV320AIC23_ACTIVE, 0x0);
-               snd_soc_write(codec, TLV320AIC23_PWR, 0xffff);
+               snd_soc_write(codec, TLV320AIC23_PWR, 0x1ff);
                break;
        }
        codec->dapm.bias_level = level;

diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index 8c4c959..aa12c6b 100644 (file)
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -60,7 +60,7 @@ struct wm8350_jack_data {
 };
 
 struct wm8350_data {
-       struct snd_soc_codec codec;
+       struct wm8350 *wm8350;
        struct wm8350_output out1;
        struct wm8350_output out2;
        struct wm8350_jack_data hpl;
@@ -1309,7 +1309,7 @@ static void wm8350_hp_work(struct wm8350_data *priv,
                           struct wm8350_jack_data *jack,
                           u16 mask)
 {
-       struct wm8350 *wm8350 = priv->codec.control_data;
+       struct wm8350 *wm8350 = priv->wm8350;
        u16 reg;
        int report;
 
@@ -1342,7 +1342,7 @@ static void wm8350_hpr_work(struct work_struct *work)
 static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
 {
        struct wm8350_data *priv = data;
-       struct wm8350 *wm8350 = priv->codec.control_data;
+       struct wm8350 *wm8350 = priv->wm8350;
        struct wm8350_jack_data *jack = NULL;
 
        switch (irq - wm8350->irq_base) {
@@ -1427,7 +1427,7 @@ EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
 static irqreturn_t wm8350_mic_handler(int irq, void *data)
 {
        struct wm8350_data *priv = data;
-       struct wm8350 *wm8350 = priv->codec.control_data;
+       struct wm8350 *wm8350 = priv->wm8350;
        u16 reg;
        int report = 0;
 
@@ -1536,6 +1536,8 @@ static  int wm8350_codec_probe(struct snd_soc_codec *codec)
                return -ENOMEM;
        snd_soc_codec_set_drvdata(codec, priv);
 
+       priv->wm8350 = wm8350;
+
        for (i = 0; i < ARRAY_SIZE(supply_names); i++)
                priv->supplies[i].supply = supply_names[i];
 
@@ -1544,7 +1546,6 @@ static  int wm8350_codec_probe(struct snd_soc_codec *codec)
        if (ret != 0)
                return ret;
 
-       wm8350->codec.codec = codec;
        codec->control_data = wm8350;
 
        /* Put the codec into reset if it wasn't already */

diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 7c49642..6c1fe3a 100644 (file)
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -1000,61 +1000,170 @@ static void wm8994_update_class_w(struct snd_soc_codec *codec)
        }
 }
 
-static int late_enable_ev(struct snd_soc_dapm_widget *w,
-                         struct snd_kcontrol *kcontrol, int event)
+static int aif1clk_ev(struct snd_soc_dapm_widget *w,
+                     struct snd_kcontrol *kcontrol, int event)
 {
        struct snd_soc_codec *codec = w->codec;
-       struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+       struct wm8994 *control = codec->control_data;
+       int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
+       int dac;
+       int adc;
+       int val;
+
+       switch (control->type) {
+       case WM8994:
+       case WM8958:
+               mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
+               break;
+       default:
+               break;
+       }
 
        switch (event) {
        case SND_SOC_DAPM_PRE_PMU:
-               if (wm8994->aif1clk_enable) {
-                       snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
-                                           WM8994_AIF1CLK_ENA_MASK,
-                                           WM8994_AIF1CLK_ENA);
-                       wm8994->aif1clk_enable = 0;
-               }
-               if (wm8994->aif2clk_enable) {
-                       snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
-                                           WM8994_AIF2CLK_ENA_MASK,
-                                           WM8994_AIF2CLK_ENA);
-                       wm8994->aif2clk_enable = 0;
-               }
+               val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
+               if ((val & WM8994_AIF1ADCL_SRC) &&
+                   (val & WM8994_AIF1ADCR_SRC))
+                       adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
+               else if (!(val & WM8994_AIF1ADCL_SRC) &&
+                        !(val & WM8994_AIF1ADCR_SRC))
+                       adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
+               else
+                       adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
+                               WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
+
+               val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
+               if ((val & WM8994_AIF1DACL_SRC) &&
+                   (val & WM8994_AIF1DACR_SRC))
+                       dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
+               else if (!(val & WM8994_AIF1DACL_SRC) &&
+                        !(val & WM8994_AIF1DACR_SRC))
+                       dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
+               else
+                       dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
+                               WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
+
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
+                                   mask, adc);
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                                   mask, dac);
+               snd_soc_update_bits(codec, WM8994_CLOCKING_1,
+                                   WM8994_AIF1DSPCLK_ENA |
+                                   WM8994_SYSDSPCLK_ENA,
+                                   WM8994_AIF1DSPCLK_ENA |
+                                   WM8994_SYSDSPCLK_ENA);
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
+                                   WM8994_AIF1ADC1R_ENA |
+                                   WM8994_AIF1ADC1L_ENA |
+                                   WM8994_AIF1ADC2R_ENA |
+                                   WM8994_AIF1ADC2L_ENA);
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
+                                   WM8994_AIF1DAC1R_ENA |
+                                   WM8994_AIF1DAC1L_ENA |
+                                   WM8994_AIF1DAC2R_ENA |
+                                   WM8994_AIF1DAC2L_ENA);
                break;
-       }
 
-       /* We may also have postponed startup of DSP, handle that. */
-       wm8958_aif_ev(w, kcontrol, event);
+       case SND_SOC_DAPM_PRE_PMD:
+       case SND_SOC_DAPM_POST_PMD:
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                                   mask, 0);
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
+                                   mask, 0);
+
+               val = snd_soc_read(codec, WM8994_CLOCKING_1);
+               if (val & WM8994_AIF2DSPCLK_ENA)
+                       val = WM8994_SYSDSPCLK_ENA;
+               else
+                       val = 0;
+               snd_soc_update_bits(codec, WM8994_CLOCKING_1,
+                                   WM8994_SYSDSPCLK_ENA |
+                                   WM8994_AIF1DSPCLK_ENA, val);
+               break;
+       }
 
        return 0;
 }
 
-static int late_disable_ev(struct snd_soc_dapm_widget *w,
-                          struct snd_kcontrol *kcontrol, int event)
+static int aif2clk_ev(struct snd_soc_dapm_widget *w,
+                     struct snd_kcontrol *kcontrol, int event)
 {
        struct snd_soc_codec *codec = w->codec;
-       struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+       int dac;
+       int adc;
+       int val;
 
        switch (event) {
+       case SND_SOC_DAPM_PRE_PMU:
+               val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
+               if ((val & WM8994_AIF2ADCL_SRC) &&
+                   (val & WM8994_AIF2ADCR_SRC))
+                       adc = WM8994_AIF2ADCR_ENA;
+               else if (!(val & WM8994_AIF2ADCL_SRC) &&
+                        !(val & WM8994_AIF2ADCR_SRC))
+                       adc = WM8994_AIF2ADCL_ENA;
+               else
+                       adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
+
+
+               val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
+               if ((val & WM8994_AIF2DACL_SRC) &&
+                   (val & WM8994_AIF2DACR_SRC))
+                       dac = WM8994_AIF2DACR_ENA;
+               else if (!(val & WM8994_AIF2DACL_SRC) &&
+                        !(val & WM8994_AIF2DACR_SRC))
+                       dac = WM8994_AIF2DACL_ENA;
+               else
+                       dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
+
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
+                                   WM8994_AIF2ADCL_ENA |
+                                   WM8994_AIF2ADCR_ENA, adc);
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                                   WM8994_AIF2DACL_ENA |
+                                   WM8994_AIF2DACR_ENA, dac);
+               snd_soc_update_bits(codec, WM8994_CLOCKING_1,
+                                   WM8994_AIF2DSPCLK_ENA |
+                                   WM8994_SYSDSPCLK_ENA,
+                                   WM8994_AIF2DSPCLK_ENA |
+                                   WM8994_SYSDSPCLK_ENA);
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
+                                   WM8994_AIF2ADCL_ENA |
+                                   WM8994_AIF2ADCR_ENA,
+                                   WM8994_AIF2ADCL_ENA |
+                                   WM8994_AIF2ADCR_ENA);
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                                   WM8994_AIF2DACL_ENA |
+                                   WM8994_AIF2DACR_ENA,
+                                   WM8994_AIF2DACL_ENA |
+                                   WM8994_AIF2DACR_ENA);
+               break;
+
+       case SND_SOC_DAPM_PRE_PMD:
        case SND_SOC_DAPM_POST_PMD:
-               if (wm8994->aif1clk_disable) {
-                       snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
-                                           WM8994_AIF1CLK_ENA_MASK, 0);
-                       wm8994->aif1clk_disable = 0;
-               }
-               if (wm8994->aif2clk_disable) {
-                       snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
-                                           WM8994_AIF2CLK_ENA_MASK, 0);
-                       wm8994->aif2clk_disable = 0;
-               }
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                                   WM8994_AIF2DACL_ENA |
+                                   WM8994_AIF2DACR_ENA, 0);
+               snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
+                                   WM8994_AIF2ADCL_ENA |
+                                   WM8994_AIF2ADCR_ENA, 0);
+
+               val = snd_soc_read(codec, WM8994_CLOCKING_1);
+               if (val & WM8994_AIF1DSPCLK_ENA)
+                       val = WM8994_SYSDSPCLK_ENA;
+               else
+                       val = 0;
+               snd_soc_update_bits(codec, WM8994_CLOCKING_1,
+                                   WM8994_SYSDSPCLK_ENA |
+                                   WM8994_AIF2DSPCLK_ENA, val);
                break;
        }
 
        return 0;
 }
 
-static int aif1clk_ev(struct snd_soc_dapm_widget *w,
-                     struct snd_kcontrol *kcontrol, int event)
+static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
+                          struct snd_kcontrol *kcontrol, int event)
 {
        struct snd_soc_codec *codec = w->codec;
        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
@@ -1071,8 +1180,8 @@ static int aif1clk_ev(struct snd_soc_dapm_widget *w,
        return 0;
 }
 
-static int aif2clk_ev(struct snd_soc_dapm_widget *w,
-                     struct snd_kcontrol *kcontrol, int event)
+static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
+                          struct snd_kcontrol *kcontrol, int event)
 {
        struct snd_soc_codec *codec = w->codec;
        struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
@@ -1089,6 +1198,63 @@ static int aif2clk_ev(struct snd_soc_dapm_widget *w,
        return 0;
 }
 
+static int late_enable_ev(struct snd_soc_dapm_widget *w,
+                         struct snd_kcontrol *kcontrol, int event)
+{
+       struct snd_soc_codec *codec = w->codec;
+       struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+       switch (event) {
+       case SND_SOC_DAPM_PRE_PMU:
+               if (wm8994->aif1clk_enable) {
+                       aif1clk_ev(w, kcontrol, event);
+                       snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+                                           WM8994_AIF1CLK_ENA_MASK,
+                                           WM8994_AIF1CLK_ENA);
+                       wm8994->aif1clk_enable = 0;
+               }
+               if (wm8994->aif2clk_enable) {
+                       aif2clk_ev(w, kcontrol, event);
+                       snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+                                           WM8994_AIF2CLK_ENA_MASK,
+                                           WM8994_AIF2CLK_ENA);
+                       wm8994->aif2clk_enable = 0;
+               }
+               break;
+       }
+
+       /* We may also have postponed startup of DSP, handle that. */
+       wm8958_aif_ev(w, kcontrol, event);
+
+       return 0;
+}
+
+static int late_disable_ev(struct snd_soc_dapm_widget *w,
+                          struct snd_kcontrol *kcontrol, int event)
+{
+       struct snd_soc_codec *codec = w->codec;
+       struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
+
+       switch (event) {
+       case SND_SOC_DAPM_POST_PMD:
+               if (wm8994->aif1clk_disable) {
+                       snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
+                                           WM8994_AIF1CLK_ENA_MASK, 0);
+                       aif1clk_ev(w, kcontrol, event);
+                       wm8994->aif1clk_disable = 0;
+               }
+               if (wm8994->aif2clk_disable) {
+                       snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
+                                           WM8994_AIF2CLK_ENA_MASK, 0);
+                       aif2clk_ev(w, kcontrol, event);
+                       wm8994->aif2clk_disable = 0;
+               }
+               break;
+       }
+
+       return 0;
+}
+
 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
                      struct snd_kcontrol *kcontrol, int event)
 {
@@ -1385,9 +1551,9 @@ static const struct snd_kcontrol_new aif2dacr_src_mux =
        SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
 
 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
-SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
+SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
-SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
+SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
        SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 
 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
@@ -1416,8 +1582,10 @@ SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
 };
 
 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
-SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
-SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
+                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
+SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
+                   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
                   left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
@@ -1470,30 +1638,30 @@ SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
                    SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 
-SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
-SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
-SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
+SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
 
 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
-                    0, WM8994_POWER_MANAGEMENT_4, 9, 0),
+                    0, SND_SOC_NOPM, 9, 0),
 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
-                    0, WM8994_POWER_MANAGEMENT_4, 8, 0),
+                    0, SND_SOC_NOPM, 8, 0),
 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
-                     WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
+                     SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
-                     WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
+                     SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 
 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
-                    0, WM8994_POWER_MANAGEMENT_4, 11, 0),
+                    0, SND_SOC_NOPM, 11, 0),
 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
-                    0, WM8994_POWER_MANAGEMENT_4, 10, 0),
+                    0, SND_SOC_NOPM, 10, 0),
 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
-                     WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
+                     SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
-                     WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
+                     SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 
 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
@@ -1520,14 +1688,14 @@ SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
                   dac1r_mix, ARRAY_SIZE(dac1r_mix)),
 
 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
-                    WM8994_POWER_MANAGEMENT_4, 13, 0),
+                    SND_SOC_NOPM, 13, 0),
 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
-                    WM8994_POWER_MANAGEMENT_4, 12, 0),
+                    SND_SOC_NOPM, 12, 0),
 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
-                     WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
+                     SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
-                     WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
+                     SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
                      SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 
 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),

diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
index f13f288..6c028c4 100644 (file)
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -1035,7 +1035,7 @@ void wm_hubs_set_bias_level(struct snd_soc_codec *codec,
                            enum snd_soc_bias_level level)
 {
        struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
-       int val;
+       int mask, val;
 
        switch (level) {
        case SND_SOC_BIAS_STANDBY:
@@ -1047,6 +1047,13 @@ void wm_hubs_set_bias_level(struct snd_soc_codec *codec,
        case SND_SOC_BIAS_ON:
                /* Turn off any unneded single ended outputs */
                val = 0;
+               mask = 0;
+
+               if (hubs->lineout1_se)
+                       mask |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA;
+
+               if (hubs->lineout2_se)
+                       mask |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA;
 
                if (hubs->lineout1_se && hubs->lineout1n_ena)
                        val |= WM8993_LINEOUT1N_ENA;
@@ -1061,11 +1068,7 @@ void wm_hubs_set_bias_level(struct snd_soc_codec *codec,
                        val |= WM8993_LINEOUT2P_ENA;
 
                snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_3,
-                                   WM8993_LINEOUT1N_ENA |
-                                   WM8993_LINEOUT1P_ENA |
-                                   WM8993_LINEOUT2N_ENA |
-                                   WM8993_LINEOUT2P_ENA,
-                                   val);
+                                   mask, val);
 
                /* Remove the input clamps */
                snd_soc_update_bits(codec, WM8993_INPUTS_CLAMP_REG,

diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index 53f4fd8..7fd224b 100644 (file)
--- a/sound/soc/mxs/mxs-saif.c
+++ b/sound/soc/mxs/mxs-saif.c
@@ -25,6 +25,7 @@
 #include <linux/delay.h>
 #include <linux/time.h>
 #include <linux/fsl/mxs-dma.h>
+#include <linux/pinctrl/consumer.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -625,6 +626,7 @@ static int mxs_saif_probe(struct platform_device *pdev)
        struct resource *iores, *dmares;
        struct mxs_saif *saif;
        struct mxs_saif_platform_data *pdata;
+       struct pinctrl *pinctrl;
        int ret = 0;
 
        if (pdev->id >= ARRAY_SIZE(mxs_saif))
@@ -650,6 +652,12 @@ static int mxs_saif_probe(struct platform_device *pdev)
                saif->master_id = saif->id;
        }
 
+       pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+       if (IS_ERR(pinctrl)) {
+               ret = PTR_ERR(pinctrl);
+               return ret;
+       }
+
        saif->clk = clk_get(&pdev->dev, NULL);
        if (IS_ERR(saif->clk)) {
                ret = PTR_ERR(saif->clk);

diff --git a/sound/soc/omap/omap-pcm.c b/sound/soc/omap/omap-pcm.c
index a59bd35..5a649da 100644 (file)
--- a/sound/soc/omap/omap-pcm.c
+++ b/sound/soc/omap/omap-pcm.c
@@ -401,6 +401,10 @@ static int omap_pcm_new(struct snd_soc_pcm_runtime *rtd)
        }
 
 out:
+       /* free preallocated buffers in case of error */
+       if (ret)
+               omap_pcm_free_dma_buffers(pcm);
+
        return ret;
 }
 

diff --git a/sound/soc/samsung/s3c2412-i2s.c b/sound/soc/samsung/s3c2412-i2s.c
index 7218507..79fbeea 100644 (file)
--- a/sound/soc/samsung/s3c2412-i2s.c
+++ b/sound/soc/samsung/s3c2412-i2s.c
@@ -166,7 +166,7 @@ static struct snd_soc_dai_driver s3c2412_i2s_dai = {
 
 static __devinit int s3c2412_iis_dev_probe(struct platform_device *pdev)
 {
-       return snd_soc_register_dai(&pdev->dev, &s3c2412_i2s_dai);
+       return s3c_i2sv2_register_dai(&pdev->dev, -1, &s3c2412_i2s_dai);
 }
 
 static __devexit int s3c2412_iis_dev_remove(struct platform_device *pdev)

diff --git a/sound/soc/sh/fsi.c b/sound/soc/sh/fsi.c
index 378cc5b..74ed2df 100644 (file)
--- a/sound/soc/sh/fsi.c
+++ b/sound/soc/sh/fsi.c
@@ -1001,11 +1001,10 @@ static void fsi_dma_do_tasklet(unsigned long data)
        sg_dma_address(&sg) = buf;
        sg_dma_len(&sg) = len;
 
-       desc = chan->device->device_prep_slave_sg(chan, &sg, 1, dir,
-                                                 DMA_PREP_INTERRUPT |
-                                                 DMA_CTRL_ACK);
+       desc = dmaengine_prep_slave_sg(chan, &sg, 1, dir,
+                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
        if (!desc) {
-               dev_err(dai->dev, "device_prep_slave_sg() fail\n");
+               dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n");
                return;
        }
 

diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index accdcb7..c88d974 100644 (file)
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -3113,6 +3113,7 @@ int snd_soc_register_card(struct snd_soc_card *card)
                                 GFP_KERNEL);
        if (card->rtd == NULL)
                return -ENOMEM;
+       card->num_rtd = 0;
        card->rtd_aux = &card->rtd[card->num_links];
 
        for (i = 0; i < card->num_links; i++)
@@ -3624,10 +3625,10 @@ int snd_soc_of_parse_audio_routing(struct snd_soc_card *card,
        int i, ret;
 
        num_routes = of_property_count_strings(np, propname);
-       if (num_routes & 1) {
+       if (num_routes < 0 || num_routes & 1) {
                dev_err(card->dev,
-                       "Property '%s's length is not even\n",
-                       propname);
+                    "Property '%s' does not exist or its length is not even\n",
+                    propname);
                return -EINVAL;
        }
        num_routes /= 2;

diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
index 5cbd2d7..1bb6d4a 100644 (file)
--- a/sound/soc/soc-dapm.c
+++ b/sound/soc/soc-dapm.c
@@ -67,6 +67,7 @@ static int dapm_up_seq[] = {
        [snd_soc_dapm_out_drv] = 10,
        [snd_soc_dapm_hp] = 10,
        [snd_soc_dapm_spk] = 10,
+       [snd_soc_dapm_line] = 10,
        [snd_soc_dapm_post] = 11,
 };
 
@@ -75,6 +76,7 @@ static int dapm_down_seq[] = {
        [snd_soc_dapm_adc] = 1,
        [snd_soc_dapm_hp] = 2,
        [snd_soc_dapm_spk] = 2,
+       [snd_soc_dapm_line] = 2,
        [snd_soc_dapm_out_drv] = 2,
        [snd_soc_dapm_pga] = 4,
        [snd_soc_dapm_mixer_named_ctl] = 5,

diff --git a/tools/perf/Makefile b/tools/perf/Makefile
index 03059e7..9bf3fc7 100644 (file)
--- a/tools/perf/Makefile
+++ b/tools/perf/Makefile
@@ -234,8 +234,8 @@ endif
 
 export PERL_PATH
 
-FLEX = $(CROSS_COMPILE)flex
-BISON= $(CROSS_COMPILE)bison
+FLEX = flex
+BISON= bison
 
 $(OUTPUT)util/parse-events-flex.c: util/parse-events.l
        $(QUIET_FLEX)$(FLEX) --header-file=$(OUTPUT)util/parse-events-flex.h -t util/parse-events.l > $(OUTPUT)util/parse-events-flex.c

diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c
index 2e31743..cdae9b2 100644 (file)
--- a/tools/perf/builtin-report.c
+++ b/tools/perf/builtin-report.c
@@ -374,16 +374,23 @@ static int __cmd_report(struct perf_report *rep)
            (kernel_map->dso->hit &&
             (kernel_kmap->ref_reloc_sym == NULL ||
              kernel_kmap->ref_reloc_sym->addr == 0))) {
-               const struct dso *kdso = kernel_map->dso;
+               const char *desc =
+                   "As no suitable kallsyms nor vmlinux was found, kernel samples\n"
+                   "can't be resolved.";
+
+               if (kernel_map) {
+                       const struct dso *kdso = kernel_map->dso;
+                       if (!RB_EMPTY_ROOT(&kdso->symbols[MAP__FUNCTION])) {
+                               desc = "If some relocation was applied (e.g. "
+                                      "kexec) symbols may be misresolved.";
+                       }
+               }
 
                ui__warning(
 "Kernel address maps (/proc/{kallsyms,modules}) were restricted.\n\n"
 "Check /proc/sys/kernel/kptr_restrict before running 'perf record'.\n\n%s\n\n"
 "Samples in kernel modules can't be resolved as well.\n\n",
-                           RB_EMPTY_ROOT(&kdso->symbols[MAP__FUNCTION]) ?
-"As no suitable kallsyms nor vmlinux was found, kernel samples\n"
-"can't be resolved." :
-"If some relocation was applied (e.g. kexec) symbols may be misresolved.");
+               desc);
        }
 
        if (dump_trace) {

diff --git a/tools/perf/builtin-test.c b/tools/perf/builtin-test.c
index 1c5b980..223ffdc 100644 (file)
--- a/tools/perf/builtin-test.c
+++ b/tools/perf/builtin-test.c
@@ -851,6 +851,28 @@ static int test__checkevent_symbolic_name_modifier(struct perf_evlist *evlist)
        return test__checkevent_symbolic_name(evlist);
 }
 
+static int test__checkevent_exclude_host_modifier(struct perf_evlist *evlist)
+{
+       struct perf_evsel *evsel = list_entry(evlist->entries.next,
+                                             struct perf_evsel, node);
+
+       TEST_ASSERT_VAL("wrong exclude guest", !evsel->attr.exclude_guest);
+       TEST_ASSERT_VAL("wrong exclude host", evsel->attr.exclude_host);
+
+       return test__checkevent_symbolic_name(evlist);
+}
+
+static int test__checkevent_exclude_guest_modifier(struct perf_evlist *evlist)
+{
+       struct perf_evsel *evsel = list_entry(evlist->entries.next,
+                                             struct perf_evsel, node);
+
+       TEST_ASSERT_VAL("wrong exclude guest", evsel->attr.exclude_guest);
+       TEST_ASSERT_VAL("wrong exclude host", !evsel->attr.exclude_host);
+
+       return test__checkevent_symbolic_name(evlist);
+}
+
 static int test__checkevent_symbolic_alias_modifier(struct perf_evlist *evlist)
 {
        struct perf_evsel *evsel = list_entry(evlist->entries.next,
@@ -1091,6 +1113,14 @@ static struct test__event_st {
                .name  = "r1,syscalls:sys_enter_open:k,1:1:hp",
                .check = test__checkevent_list,
        },
+       {
+               .name  = "instructions:G",
+               .check = test__checkevent_exclude_host_modifier,
+       },
+       {
+               .name  = "instructions:H",
+               .check = test__checkevent_exclude_guest_modifier,
+       },
 };
 
 #define TEST__EVENTS_CNT (sizeof(test__events) / sizeof(struct test__event_st))

diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l
index 05d766e..1fcf1bb 100644 (file)
--- a/tools/perf/util/parse-events.l
+++ b/tools/perf/util/parse-events.l
@@ -54,7 +54,7 @@ num_dec               [0-9]+
 num_hex                0x[a-fA-F0-9]+
 num_raw_hex    [a-fA-F0-9]+
 name           [a-zA-Z_*?][a-zA-Z0-9_*?]*
-modifier_event [ukhp]{1,5}
+modifier_event [ukhpGH]{1,8}
 modifier_bp    [rwx]
 
 %%

diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c
index c0a028c..ab9867b 100644 (file)
--- a/tools/perf/util/symbol.c
+++ b/tools/perf/util/symbol.c
@@ -977,8 +977,9 @@ static Elf_Scn *elf_section_by_name(Elf *elf, GElf_Ehdr *ep,
  * And always look at the original dso, not at debuginfo packages, that
  * have the PLT data stripped out (shdr_rel_plt.sh_type == SHT_NOBITS).
  */
-static int dso__synthesize_plt_symbols(struct  dso *dso, struct map *map,
-                                      symbol_filter_t filter)
+static int
+dso__synthesize_plt_symbols(struct dso *dso, char *name, struct map *map,
+                           symbol_filter_t filter)
 {
        uint32_t nr_rel_entries, idx;
        GElf_Sym sym;
@@ -993,10 +994,7 @@ static int dso__synthesize_plt_symbols(struct  dso *dso, struct map *map,
        char sympltname[1024];
        Elf *elf;
        int nr = 0, symidx, fd, err = 0;
-       char name[PATH_MAX];
 
-       snprintf(name, sizeof(name), "%s%s",
-                symbol_conf.symfs, dso->long_name);
        fd = open(name, O_RDONLY);
        if (fd < 0)
                goto out;
@@ -1703,8 +1701,9 @@ restart:
                        continue;
 
                if (ret > 0) {
-                       int nr_plt = dso__synthesize_plt_symbols(dso, map,
-                                                                filter);
+                       int nr_plt;
+
+                       nr_plt = dso__synthesize_plt_symbols(dso, name, map, filter);
                        if (nr_plt > 0)
                                ret += nr_plt;
                        break;

diff --git a/tools/testing/ktest/ktest.pl b/tools/testing/ktest/ktest.pl
index 95d6a6f..4915408 100755 (executable)
--- a/tools/testing/ktest/ktest.pl
+++ b/tools/testing/ktest/ktest.pl
@@ -183,6 +183,9 @@ my %force_config;
 # do not force reboots on config problems
 my $no_reboot = 1;
 
+# reboot on success
+my $reboot_success = 0;
+
 my %option_map = (
     "MACHINE"                  => \$machine,
     "SSH_USER"                 => \$ssh_user,
@@ -2192,7 +2195,7 @@ sub run_bisect {
     }
 
     # Are we looking for where it worked, not failed?
-    if ($reverse_bisect) {
+    if ($reverse_bisect && $ret >= 0) {
        $ret = !$ret;
     }
 
@@ -3469,6 +3472,7 @@ for (my $i = 1; $i <= $opt{"NUM_TESTS"}; $i++) {
 
     # Do not reboot on failing test options
     $no_reboot = 1;
+    $reboot_success = 0;
 
     $iteration = $i;
 
@@ -3554,9 +3558,11 @@ for (my $i = 1; $i <= $opt{"NUM_TESTS"}; $i++) {
            die "failed to checkout $checkout";
     }
 
+    $no_reboot = 0;
+
     # A test may opt to not reboot the box
     if ($reboot_on_success) {
-       $no_reboot = 0;
+       $reboot_success = 1;
     }
 
     if ($test_type eq "bisect") {
@@ -3600,7 +3606,7 @@ for (my $i = 1; $i <= $opt{"NUM_TESTS"}; $i++) {
 
 if ($opt{"POWEROFF_ON_SUCCESS"}) {
     halt;
-} elsif ($opt{"REBOOT_ON_SUCCESS"} && !do_not_reboot) {
+} elsif ($opt{"REBOOT_ON_SUCCESS"} && !do_not_reboot && $reboot_success) {
     reboot_to_good;
 } elsif (defined($switch_to_good)) {
     # still need to get to the good kernel