struct clk_divider *divider = to_clk_divider(hw);
unsigned int val;
- val = clk_readl(divider->reg) >> divider->shift;
+ if (divider->flags & CLK_DIVIDER_WORD_REG)
+ val = clk_readw(divider->reg) >> divider->shift;
+ else
+ val = clk_readl(divider->reg) >> divider->shift;
val &= div_mask(divider->width);
return divider_recalc_rate(hw, parent_rate, val, divider->table,
val &= ~(div_mask(divider->width) << divider->shift);
}
val |= value << divider->shift;
- clk_writel(val, divider->reg);
+ if (divider->flags & CLK_DIVIDER_WORD_REG)
+ clk_writew(val, divider->reg);
+ else
+ clk_writel(val, divider->reg);
if (divider->lock)
spin_unlock_irqrestore(divider->lock, flags);
* CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
* except when the value read from the register is zero, the divisor is
* 2^width of the field.
+ * CLK_DIVIDER_WORD_REG - The driver use 16-bit access function for register.
+ * Usally 32-bit access.
*/
struct clk_divider {
struct clk_hw hw;
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+#define CLK_DIVIDER_WORD_REG BIT(7)
extern const struct clk_ops clk_divider_ops;
extern const struct clk_ops clk_divider_ro_ops;
#endif /* platform dependent I/O accessors */
+static inline u32 clk_readw(u32 __iomem *reg)
+{
+ return readw(reg);
+}
+
+static inline void clk_writew(u32 val, u32 __iomem *reg)
+{
+ writew(val, reg);
+}
+
#ifdef CONFIG_DEBUG_FS
struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
void *data, const struct file_operations *fops);