unsigned long get_cpu_clock(void);
-#define TIMER_FREQ get_cpu_clock() /* Timer input freq. */
+#define H8300_TIMER_FREQ get_cpu_clock() /* Timer input freq. */
-#define MODE_CS 0
-#define MODE_CED 1
+#define H8300_TMR8_CLKSRC 0
+#define H8300_TMR8_CLKEVTDEV 1
-#define DIV_8 0
-#define DIV_64 1
-#define DIC_8192 2
+#define H8300_TMR8_DIV_8 0
+#define H8300_TMR8_DIV_64 1
+#define H8300_TMR8_DIC_8192 2
struct h8300_timer8_config {
int mode;
struct h8300_timer16_config {
int rating;
- __u8 enable;
+ __u8 enb;
__u8 imfa;
__u8 imiea;
};
};
static struct h8300_timer8_config timer8_platform_data = {
- .mode = MODE_CS,
- .div = DIV_64,
+ .mode = H8300_TMR8_CLKSRC,
+ .div = H8300_TMR8_DIV_64,
.rating = 200,
};
};
static struct h8300_timer8_config timer8_platform_data = {
- .mode = MODE_CED,
- .div = DIV_8,
+ .mode = H8300_TMR8_CLKEVTDEV,
+ .div = H8300_TMR8_DIV_8,
.rating = 200,
};
struct timer8_priv *p = dev_id;
switch(p->mode) {
- case MODE_CS:
+ case H8300_TMR8_CLKSRC:
ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x20,
p->mapbase + _8TCSR);
p->total_cycles += 0x10000;
break;
- case MODE_CED:
+ case H8300_TMR8_CLKEVTDEV:
ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x40,
p->mapbase + _8TCSR);
p->flags |= FLAG_IRQCONTEXT;
p->mode = cfg->mode;
p->div = cfg->div;
switch(p->mode) {
- case MODE_CS:
+ case H8300_TMR8_CLKSRC:
p->clk.cs.name = pdev->name;
p->clk.cs.rating = cfg->rating;
p->clk.cs.read = timer8_clocksource_read;
clocksource_register_hz(&p->clk.cs,
get_cpu_clock() / div_rate[p->div]);
break;
- case MODE_CED:
+ case H8300_TMR8_CLKEVTDEV:
p->clk.ced.name = pdev->name;
p->clk.ced.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT;