drm/i915: don't save/restore panel fitter registers

AFAICT i9xx_pfit_disable() on the GMCH display crtc disable path in
i9xx_crtc_disable() will always disable the panel fitter by writing 0 to
PFIT_CONTROL. The register save will always save/restore 0. Also we
completely recompue both in intel_gmch_panel_fitting so there's no way
we depend upon leftover bits.

Move the PFIT_CONTROL and PFIT_PGM_RATIOS save/restore to UMS
code. While at it, save/restore them both under the same conditions.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
[danvet: Make it a bit clearer that we nowhere depend upon these
bits.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 26b6bf9..df2b7f1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -208,23 +208,17 @@ static void i915_save_display(struct drm_device *dev)
                if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
                        dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
        } else if (IS_VALLEYVIEW(dev)) {
-               dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
-
                dev_priv->regfile.saveBLC_HIST_CTL =
                        I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
                dev_priv->regfile.saveBLC_HIST_CTL_B =
                        I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
        } else {
                dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
-               dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
                dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
                if (IS_MOBILE(dev) && !IS_I830(dev))
                        dev_priv->regfile.saveLVDS = I915_READ(LVDS);
        }
 
-       if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
-               dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
-
        if (HAS_PCH_SPLIT(dev)) {
                dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
                dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
@@ -263,9 +257,6 @@ static void i915_restore_display(struct drm_device *dev)
        else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
                I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
 
-       if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
-               I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
-
        if (HAS_PCH_SPLIT(dev)) {
                I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
                I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
@@ -277,7 +268,6 @@ static void i915_restore_display(struct drm_device *dev)
                I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
                           dev_priv->regfile.saveBLC_HIST_CTL);
        } else {
-               I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
                I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
                I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
                I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);

diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
index 480da59..0e03c36 100644 (file)
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -270,6 +270,12 @@ void i915_save_display_reg(struct drm_device *dev)
        }
        /* FIXME: regfile.save TV & SDVO state */
 
+       /* Panel fitter */
+       if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
+               dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
+               dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
+       }
+
        /* Backlight */
        if (INTEL_INFO(dev)->gen <= 4)
                pci_read_config_byte(dev->pdev, PCI_LBPC,
@@ -315,6 +321,12 @@ void i915_restore_display_reg(struct drm_device *dev)
                I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
        }
 
+       /* Panel fitter */
+       if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
+               I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
+               I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
+       }
+
        /* Display port ratios (must be done before clock is set) */
        if (SUPPORTS_INTEGRATED_DP(dev)) {
                I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);