--- /dev/null
+#include <dt-bindings/interrupt-controller/sh_intc.h>
+
+/dts-v1/;
+/ {
+ model = "I/O DATA HDL-U";
+ compatible = "iodata,hdl-u";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&shintc>;
+ chosen {
+ stdout-path = &sci1;
+ };
+ aliases {
+ serial1 = &sci1;
+ };
+
+ oclk: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <22222222>;
+ };
+ pllclk: pllclk {
+ compatible = "renesas,sh7750-pll-clock";
+ clocks = <&oclk>;
+ #clock-cells = <0>;
+ renesas,mult = <12>;
+ reg = <0xffc00000 2>, <0xffc00008 4>;
+ };
+ iclk: iclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <6>;
+ clock-output-names = "ick";
+ };
+ bclk: bclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <3>;
+ clock-output-names = "bck";
+ };
+ fclk: fclk {
+ compatible = "renesas,sh7750-div-clock";
+ clocks = <&pllclk>;
+ #clock-cells = <0>;
+ reg = <0xffc00000 2>;
+ renesas,offset = <0>;
+ clock-output-names = "fck";
+ };
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "renesas,sh4", "renesas,sh";
+ clock-frequency = <266666666>;
+ };
+ };
+ memory@0c000000 {
+ device_type = "memory";
+ reg = <0x0c000000 0x4000000>;
+ };
+ shintc: interrupt-controller@ffd00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+
+ };
+ cpldintc: cpld@b0000000 {
+ compatible = "iodata,landisk-intc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xb0000000 8>;
+ interrupt-map=<0 &shintc 0 0>, <1 &shintc 1 0>,
+ <2 &shintc 2 0>, <3 &shintc 3 0>,
+ <4 &shintc 4 0>, <5 &shintc 5 0>,
+ <6 &shintc 6 0>, <7 &shintc 7 0>;
+ };
+
+ sci1: serial@ffe80000 {
+ compatible = "renesas,scif";
+ reg = <0xffe80000 0x100>;
+ interrupts = <evt2irq(0x700) 0
+ evt2irq(0x720) 0
+ evt2irq(0x740) 0
+ evt2irq(0x760) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ };
+ tmu: timer@ffd80008 {
+ compatible = "renesas,tmu";
+ reg = <0xffd80000 12>;
+ interrupts = <evt2irq(0x400) 0
+ evt2irq(0x420) 0
+ evt2irq(0x440) 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ renesas,channels-mask = <0x03>;
+ };
+
+ pci: pci-controller@fe200000 {
+ compatible = "renesas,sh7751-pci";
+ device_type = "pci";
+ ranges = <0x02000000 0x00000000 0xfd000000 0x01000000>,
+ <0x01000000 0x00000000 0xfe240000 0x00400000>;
+ reg = <0xfe200000 0x400>;
+ renesas,pcimem = <0xfd000000>;
+ renesas,pciio = <0xfe240000>;
+ interrupts = <evt2irq(0x2a0) 0
+ evt2irq(0x2c0) 0
+ evt2irq(0x2e0) 0
+ evt2irq(0x300) 0
+ evt2irq(0x320) 0
+ evt2irq(0x340) 0>;
+ };
+};