client/trunk/anago/bandai_lz93d50_x24c02.ag

   1 /*\r
   2 BANDAI FCG-3 + X24C02 style cartridge\r
   3 \r
   4 ドラゴンボールZII 激神フリーザ!!\r
   5         1991-08-10, DRAGON BALLZ-B ,LZ93D50+X24C02\r
   6 SDガンダム外伝 ナイトガンダム物語2\r
   7         1991-10-12, DRAGON BALLZ-B, LZ93D50+X24C02\r
   8 SDガンダム外伝 ナイトガンダム物語3\r
   9         1992-10-23, DRAGON BALLZ-B, LZ93D50+X24C02\r
  10 DATACH 本体\r
  11         1992-12-19, BA-BAR, LZ93D50P+X24C02 (Charcter RAM)\r
  12 クレヨンしんちゃん\r
  13         1993-08-27, DRAGON BALLZ-B, LZ93D50 (EEPROM なし)\r
  14 ろくでなしBLUES\r
  15         1993-10-29, DRAGON BALLZ-B, LZ93D50+X24C02\r
  16 */\r
  17 board <- {\r
  18         mappernum = 16, \r
  19         cpu_rom = {\r
  20                 size_base = 2 * mega, size_max = 2 * mega,\r
  21                 banksize = 0x4000\r
  22         }, \r
  23         cpu_ram = {\r
  24                 size_base = 0x0100, size_max = 0x0100,\r
  25                 banksize = 0x0100\r
  26         },\r
  27         ppu_rom = {\r
  28                 size_base = 2 * mega, size_max = 2 * mega,\r
  29                 banksize = 0x0400\r
  30         },\r
  31         ppu_ramfind = false,\r
  32         vram_mirrorfind = false\r
  33 };\r
  34 \r
  35 const register_offset = 0x8000;\r
  36 dofile("lz93d50.ai")\r
  37 /*\r
  38 =====================\r
  39 X24C02 frame sequence\r
  40 =====================\r
  41 <START>[slave address+RW]<A-ACK>[data]<D-ACK><STOP>\r
  42 \r
  43 <> is 1bit, [] is 8bit, A-ACK is address acknowledge, \r
  44 D-ACK is data acknowledge, R is 1, W is 0\r
  45 \r
  46 slave address 6:3 is 4'b0101, fixed\r
  47 slave address 2:0 is 3'b000, configurated by PCB\r
  48 \r
  49 8bit data send MSB to LSB (bit7 to bit0)\r
  50 \r
  51 --current address set--\r
  52 <START>[0x50,W]<A-ACK>[EEPROM address]<D-ACK><STOP>\r
  53 \r
  54 --current address read--\r
  55 <START>[0x50,R]<A-ACK>[EEPROM data]<D-ACK><STOP>\r
  56 \r
  57 --sequenctial read--\r
  58 <START>[0x50,R]<A-ACK>|[EEPROM data]<D-ACK>|<STOP>\r
  59                       |<- loop any times ->|\r
  60 \r
  61 after read operation, EEPROM address is incremented\r
  62 \r
  63 --page write---\r
  64 |<START>[0x50,W]<A-ACK>|[EEPROM address]<D-ACK>|[EEPROM data]<D-ACK>|<STOP>\r
  65 |<- loop A-ACK is H  ->|                       |<- loop 1to4times ->|\r
  66 \r
  67 After write operation, EEPROM controller is writing data, time is required of 2ms.\r
  68 duaring polling, A-ACK returns H. Retry operation.\r
  69 \r
  70 The page write count is different by the manufacturer.\r
  71 X24C01 and X24C02 are designed page write count is 4.\r
  72 */\r
  73 function cpu_ram_access(d, pagesize, banksize)\r
  74 {\r
  75         local I2C_WRITE = I2C_SEND_L;\r
  76         local I2C_READ = I2C_SEND_H;\r
  77 \r
  78         if(mode_is_read(d) == true){\r
  79                 //sequenctial read\r
  80                 i2c_address_set(d, 0x50, I2C_WRITE);\r
  81                 eeprom_address_set(d, 0);\r
  82 \r
  83                 i2c_address_set(d, 0x50, I2C_READ);\r
  84                 for(local i = 0; i < pagesize * banksize; i++){\r
  85                         for(local bit = 0; bit < 8; bit++){\r
  86                                 cpu_write(d, 0x800d, I2C_DIR_WRITE | I2C_CLOCK_L | I2C_SEND_H);\r
  87                                 cpu_write(d, 0x800d, I2C_DIR_READ | I2C_CLOCK_H | I2C_SEND_H);\r
  88                                 cpu_read_bit_msb(d, 0x6000, 4);\r
  89                         }\r
  90                         //send ack\r
  91                         send_bit(d, I2C_SEND_L);\r
  92                 }\r
  93                 i2c_stop(d);\r
  94         }else{\r
  95                 //page write. 4byte\r
  96                 for(local i = 0; i < pagesize * banksize; i+=4){\r
  97                         i2c_address_set(d, 0x50, I2C_WRITE);\r
  98                         eeprom_address_set(d, i);\r
  99                         for(local j = 0; j < 4; j++){\r
 100                                 for(local bit = 0; bit < 8; bit++){\r
 101                                         local n = I2C_SEND_L;\r
 102                                         if(cpu_fetch_bit_msb(d) != 0){\r
 103                                                 n = I2C_SEND_H;\r
 104                                         }\r
 105                                         send_bit(d, n);\r
 106                                 }\r
 107                                 i2c_ack_wait(d);\r
 108                         }\r
 109                         i2c_stop(d);\r
 110                 }\r
 111         }\r
 112 \r
 113 }\r