2 OUTPUT_FORMAT("elf32-bfin","elf32-bfin","elf32-bfin")
8 MEM_SDRAM (XW) : ORIGIN = 0x00000000, LENGTH = 128M
9 MEM_ASYNC_0 (XW) : ORIGIN = 0x20000000, LENGTH = 1M
10 MEM_ASYNC_1 (XW) : ORIGIN = 0x20100000, LENGTH = 1M
11 MEM_ASYNC_2 (XW) : ORIGIN = 0x20200000, LENGTH = 1M
12 MEM_ASYNC_3 (XW) : ORIGIN = 0x20300000, LENGTH = 1M
14 MEM_L1_DATA_A (W!X) : ORIGIN = 0xff800000, LENGTH = 32K
15 MEM_L1_DATA_B (W!X) : ORIGIN = 0xff900000, LENGTH = 16K
16 MEM_L1_CODE (XR) : ORIGIN = 0xffa00000, LENGTH = 48K
17 MEM_L1_SCRATCH (W!X) : ORIGIN = 0xffb00000, LENGTH = 4K
19 MEM_L2 : ORIGIN = 0xffe00000, LENGTH = 0 /* DUMMY */
21 MEM_SYSMMR (W!X) : ORIGIN = 0xffc00000, LENGTH = 2M
22 MEM_COREMMR (W!X) : ORIGIN = 0xffe00000, LENGTH = 2M
28 /* ADSP-BF533依存のSYSTEM MMR */
29 .bss.sysmmr (NOLOAD) : { *.o(PWRMGMT)}> MEM_SYSMMR
30 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(SYSRST)} > MEM_SYSMMR
31 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(WDOG)} > MEM_SYSMMR
32 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(RTC)} > MEM_SYSMMR
33 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(UART0)} > MEM_SYSMMR
34 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(SPI)} > MEM_SYSMMR
35 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(TIMER)} > MEM_SYSMMR
36 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0040); *.o(TMRCTL)} > MEM_SYSMMR
37 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(FLAGF)} > MEM_SYSMMR
38 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(SPORT0)} > MEM_SYSMMR
39 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(SPORT1)} > MEM_SYSMMR
40 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(EBIU)} > MEM_SYSMMR
41 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(DMATC)} > MEM_SYSMMR
42 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(DMA)} > MEM_SYSMMR
43 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x1000); *.o(PPI)} > MEM_SYSMMR
44 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0400); *.o(TWI)} > MEM_SYSMMR
45 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0080); *.o(TWIDATA)} > MEM_SYSMMR
46 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(FLAGG)} > MEM_SYSMMR
47 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100)+0x0100; *.o(FLAGH)} > MEM_SYSMMR
48 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x1000); *.o(UART1)} > MEM_SYSMMR
49 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0800)+0x0200; *.o(CANCTL0)} > MEM_SYSMMR
50 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0040); *.o(CANCTL1)} > MEM_SYSMMR
51 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0040); *.o(CANCTL2)} > MEM_SYSMMR
52 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(CANMBX)} > MEM_SYSMMR
53 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x1000); *.o(EMAC)} > MEM_SYSMMR
54 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(EMACR)} > MEM_SYSMMR
55 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0080); *.o(EMACT)} > MEM_SYSMMR
56 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0200); *.o(PORTFER)} > MEM_SYSMMR
57 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0100); *.o(HDMA0)} > MEM_SYSMMR
58 .bss.sysmmr (NOLOAD) : { . = ALIGN(0x0040); *.o(HDMA1)} > MEM_SYSMMR
60 /* Blackfin 共有のCORE MMR */
61 .bss.coremmr (NOLOAD) : { *.o(DMEMCTL)}> MEM_COREMMR
62 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(DCPLBA)}> MEM_COREMMR
63 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(DCPLBD)}> MEM_COREMMR
64 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(DTESTC)}> MEM_COREMMR
65 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(DTESTD)}> MEM_COREMMR
66 .bss.coremmr (NOLOAD) : { . = ALIGN(0x1000); *.o(IMEMCTL)}> MEM_COREMMR
67 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(ICPLBA)}> MEM_COREMMR
68 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(ICPLBD)}> MEM_COREMMR
69 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(ITESTC)}> MEM_COREMMR
70 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(ITESTD)}> MEM_COREMMR
71 .bss.coremmr (NOLOAD) : { . = ALIGN(0x1000); *.o(EVT)}> MEM_COREMMR
72 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(CEC)}> MEM_COREMMR
73 .bss.coremmr (NOLOAD) : { . = ALIGN(0x1000); *.o(CTMR)}> MEM_COREMMR
74 .bss.coremmr (NOLOAD) : { . = ALIGN(0x1000)+0x1000; *.o(DBG)}> MEM_COREMMR /* 1000飛ばす */
75 .bss.coremmr (NOLOAD) : { . = ALIGN(0x1000); *.o(TBCTL)}> MEM_COREMMR
76 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(TBUF)}> MEM_COREMMR
77 .bss.coremmr (NOLOAD) : { . = ALIGN(0x1000); *.o(WPICTL)}> MEM_COREMMR
78 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0040); *.o(WPIADDR)}> MEM_COREMMR
79 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0040); *.o(WPICNT)}> MEM_COREMMR
80 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(WPDCTL)}> MEM_COREMMR
81 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0040); *.o(WPDADDR)}> MEM_COREMMR
82 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0040); *.o(WPDCNT)}> MEM_COREMMR
83 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(WPSTAT)}> MEM_COREMMR
84 .bss.coremmr (NOLOAD) : { . = ALIGN(0x1000); *.o(PFCTL)}> MEM_COREMMR
85 .bss.coremmr (NOLOAD) : { . = ALIGN(0x0100); *.o(PFCNT)}> MEM_COREMMR
87 .comment 0 : { *(.comment) }
88 .debug 0 : { *(.debug) }
89 .line 0 : { *(.line) }
90 .debug_srcinfo 0 : { *(.debug_srcinfo) }
91 .debug_sfnames 0 : { *(.debug_sfnames) }
92 .debug_aranges 0 : { *(.debug_aranges) }
93 .debug_pubnames 0 : { *(.debug_pubnames) }