.text
.intel_syntax noprefix
-.global KeyBoard_Interrupt_asm,Timer_Interrupt_asm,INTERRUPT_NOTHING
+.global KeyBoard_Interrupt_asm,Timer_Interrupt_asm,INTERRUPT_NOTHING,Floppy_Interrupt_asm
INTERRUPT_NOTHING:
cli
iret
+Floppy_Interrupt_asm:
+ cli
+
+ pushad
+ push ds
+ push es
+ push fs
+ push gs
+
+ #mov eax,1
+ #push eax
+ #call fddIrqFlagSet
+
+ pop gs
+ pop fs
+ pop es
+ pop ds
+ popad
+
+ sti
+
+ iret
+
+
KeyBoard_Interrupt_asm:
cli
#include<scancode.h>
#include<Message.h>
#include<timer.h>
+#include<device.h>
#define UINT_MAX 0x100000000
struct msg_data kernel;
int kernelbuf[32];
+
void timer_interrupt( void )
{
/*count tick*/
LIBVANE = ../lib/libvanec.a ../lib/libvanego.a
FLAGS = -m32 -ffreestanding -fno-common -fno-builtin -fomit-frame-pointer -O2 -c
FLAGSC = -m32 -ffreestanding -fno-common -nostdlib -masm=intel -fno-builtin -fomit-frame-pointer -O2 -c
-LD = ld -Ttext 0x100000 -T linkerscript -melf_i386 --oformat elf32-i386 -o
+LD = ld -Ttext 0x100000 -melf_i386 --oformat elf32-i386 -o
FLAGSDEBUG = -ffreestanding -fno-common -nostdlib -fno-builtin -fomit-frame-pointer -O2 -c
file =boot.c
DEBUG_OBJ=../tmp/debug.o
TOOLS_C=tools.c
CMD_C=cmd_shell.c
TASK_S=Task.S
+DEVICE_C=device.c
#オブジェクト
-BOOT_OBJ=${BOOT_S:.S=.o} ${BOOT_C:.c=.o} ${VANE_S:.S=.o} ${KEYBOARD_C:.c=.o} ${STDIO_C:.c=.o} ${GDT_IDT_C:.c=.o} ${INTERRUPT_C:.c=.o} ${STRING_C:.c=.o} ${ASM_INTERRUPT_S:.S=.o} ${SCANCODE_C:.c=.o} ${MEMMAN_C:.c=.o} ${FAT_C:.c=.o} ${GRAPHIC_C:.c=.o} ${SYSTEM_C:.c=.o} ${MESSAGE_C:.c=.o} ${TIMER_C:.c=.o} ${TASK_C:.c=.o} ${TIME_C:.c=.o} ${SCAN_C:.c=.o} ${ENV_C:.c=.o} ${TOOLS_C:.c=.o} ${CMD_C:.c=.o} ${TASK_S:.S=.o}
+BOOT_OBJ=${BOOT_S:.S=.o} ${BOOT_C:.c=.o} ${VANE_S:.S=.o} ${KEYBOARD_C:.c=.o} ${STDIO_C:.c=.o} ${GDT_IDT_C:.c=.o} ${INTERRUPT_C:.c=.o} ${STRING_C:.c=.o} ${ASM_INTERRUPT_S:.S=.o} ${SCANCODE_C:.c=.o} ${MEMMAN_C:.c=.o} ${FAT_C:.c=.o} ${GRAPHIC_C:.c=.o} ${SYSTEM_C:.c=.o} ${MESSAGE_C:.c=.o} ${TIMER_C:.c=.o} ${TASK_C:.c=.o} ${TIME_C:.c=.o} ${SCAN_C:.c=.o} ${ENV_C:.c=.o} ${TOOLS_C:.c=.o} ${CMD_C:.c=.o} ${TASK_S:.S=.o} ${DEVICE_C:.c=.o}
kernel: ${BOOT_OBJ}
${LD} ${TARGET} ${BOOT_OBJ}
.text
.intel_syntax noprefix
-.global task_switch,switch_task,switch_task_2,toswitch
+.global task_switch,switch_task_2,toswitch
task_switch:
ljmp 5*8:0x0
RET
-
-# switch_task( src, dst )
-switch_task:
- pushad
- mov ebx, [esp+36] # src
-
- # Copy to previous task.
- mov eax, [esp+32]
- mov [ebx+40], eax # eax
- mov eax, [esp+28]
- mov [ebx+44], eax # ecx
- mov eax, [esp+24]
- mov [ebx+48], eax # edx
- mov eax, [esp+20]
- mov [ebx+52], eax # ebx
- mov eax, [esp+16]
- mov [ebx+56], eax # esp
- mov eax, [esp+12]
- mov [ebx+60], eax # ebp
- mov eax, [esp+8]
- mov [ebx+64], eax # esi
- mov eax, [esp+4]
- mov [ebx+68], eax # edi
- mov [ebx+72], es # es
- mov [ebx+76], cs # cs
- mov [ebx+80], ss # ss
- mov [ebx+84], ds # ds
- mov [ebx+88], fs # fs
- mov [ebx+92], gs # gs
-
- popad
-
- # Move to destination task.
- mov ebx, [esp+8]
- mov ecx, [ebx+44] # ecx
- mov edx, [ebx+48] # edx
- mov esp, [ebx+56] # esp
- mov ebp, [ebx+60] # ebp
- mov esi, [ebx+64] # esi
- mov edi, [ebx+68] # edi
- mov fs, [ebx+88] # fs
- mov gs, [ebx+92] # gs
- mov eax, [ebx+40] # eax
-
- push [ebx+80] # push ss
- push [ebx+56] # push esp
- push [ebx+36] # push eflags
- push [ebx+76] # push cs
- push [ebx+32] # push eip
- push [ebx+52] # push ebx
- mov es, [ebx+72] # es
- mov ds, [ebx+84] # ds
- pop ebx
- iretd
-back:
- ret
-
switch_task_2:
# Save
pushad
mov ebx, [esp+48]
mov [ebx+56], esp # ESP
+
.att_syntax noprefix
- movl $toswitch, %eax# 0x435
-.intel_syntax noprefix
+ movl $toswitch, %eax # 0x435 AT&T Syntax. meaning of EAX=&toswitch
+.intel_syntax noprefix
+
+ push eax
+ call toswitch
+
sub eax, 0x280000
-# hlt
+
mov [ebx+32], eax # EIP
+
# Restore
mov ebx, [esp+52]
mov esp, [ebx+56]
.global clear_state,asm_move_cursol,write_mem8,VESA_640_480_SET,VESA_Check,VESA_Check,scrn320
.global io_hlt,io_cli,io_sti,io_stihlt
-.global io_in8,io_in16,io_in32,io_out8,io_out16,io_out32
+.global io_in8,io_in16,io_in32,io_out8,io_out16,io_out32,io_load_esp
.global io_load_eflags,io_store_eflags,load_cr0,store_cr0,load_tr
.global farjmp
+io_load_esp:
+ MOV EAX,ESP
+ RET
+
farjmp:
JMP FAR [ESP+4]
RET
void hlt(void);
unsigned char stack[ 2 ][ 2048 ];
-
+memmgr *memman=(memmgr*)MEMMAN_ADDR;
/*!
load.S call this function
{
/*Common Settings*/
char cmd[100]={0};
- memmgr *memman=(memmgr*)MEMMAN_ADDR;
+
multiboot_info_t *mbi;
mbi = (multiboot_info_t *) addr;
printTASK("Setting IDT.....");
setupInterruptGate(DEF_IDT_INT_NUM_IRQ1,KeyBoard_Interrupt_asm);//Register Keyboard interrupt handler
setupInterruptGate(DEF_IDT_INT_NUM_IRQ0,Timer_Interrupt_asm);//Register Timer interrupt handler
+ setupInterruptGate( DEF_IDT_INT_NUM_IRQ6, Floppy_Interrupt_asm);//Register Floppy interrupt handler
idtr.size = NUM_IDT * sizeof( GATE_DESCRIPTOR );
idtr.base = ( GATE_DESCRIPTOR *)idt;
ClearScreen();
}else if(strcmp("switch",cmd)==0){
- //task_switch(memman);
- k_mktask( 1, task_a,memman);
- k_mktask( 2, task_b,memman);
+ k_mktask(task_a);
+ k_mktask(task_b);
switch_task_2( TASK_INFO_ADDR, TASK_INFO_ADDR + sizeof( TaskInfo ) );
-
+
}else if(strcmp("root",cmd)==0){
if(admin_flag==0){
admin_flag=1;
outPortByte( PORT_MASTER_PIC_IMR, (~PIC_IMR_MASK_IRQ0) & (~PIC_IMR_MASK_IRQ2 ) );
outPortByte( PORT_SLAVE_PIC_IMR, PIC_IMR_MASK_IRQ_ALL );
- outPortByte( PORT_MASTER_PIC_IMR, ( ~PIC_IMR_MASK_IRQ0 )
- & ( ~PIC_IMR_MASK_IRQ1 ) & ( ~PIC_IMR_MASK_IRQ2 ) );
- outPortByte( PORT_SLAVE_PIC_IMR, PIC_IMR_MASK_IRQ_ALL );
+ outPortByte( PORT_MASTER_PIC_IMR,
+ ( ~PIC_IMR_MASK_IRQ0 )
+ & ( ~PIC_IMR_MASK_IRQ1 )
+ & ( ~PIC_IMR_MASK_IRQ2 )
+ & ( ~PIC_IMR_MASK_IRQ6 ) );
+ outPortByte( PORT_SLAVE_PIC_IMR, PIC_IMR_MASK_IRQ_ALL );
enable();
}
--- /dev/null
+/*
+*Device Drivers for Kernel
+*(C) 2014 VOSystems.
+*/
+
+#include<device.h>
+#include<type.h>
+#include<stdio.h>
+
+#define True true
+#define False false
+
+/*FDD Driver*/
+inline unsigned char convertLBA2Sector( unsigned int lba )
+{
+ return( ( lba % DEF_FDD_SECTORS_PER_TRACK ) + 1 );
+}
+
+/*
+===================================================================================
+ Funtion :ConvertLBA2Head
+ Input :unsigned int lba
+ < logical block addressing format >
+ Output :void
+ Return :unsigned char
+ < head number of converted physical address chs >
+ Description :convert lba to head number
+===================================================================================
+*/
+inline unsigned char convertLBA2Head( unsigned int lba )
+{
+ return( ( lba / ( DEF_FDD_SECTORS_PER_TRACK ) ) % DEF_FDD_NUM_HEADS );
+}
+
+/*
+===================================================================================
+ Funtion :convertLBA2Track
+ Input :unsigned int lba
+ < logical block addressing format >
+ Output :void
+ Return :unsigned char
+ < cylinder number of converted physical address chs >
+ Description :convert lba to cylinder number
+===================================================================================
+*/
+inline unsigned char convertLBA2Track( unsigned int lba )
+{
+ return( lba / ( DEF_FDD_SECTORS_PER_TRACK * DEF_FDD_NUM_HEADS ) );
+}
+
+int initFdc0( unsigned char drive )
+{
+ int status;
+ unsigned char st0;
+ unsigned char pcn;
+
+ /*--------------------------------------------------------------------------*/
+ /* reset the controller */
+ /*--------------------------------------------------------------------------*/
+ writeFdc0Dor( DEF_FDC_DOR_RESET );
+
+ writeFdc0Dor( DEF_FDC_DOR_ENABLE );
+
+ /*--------------------------------------------------------------------------*/
+ /* wait irq after the controller resets */
+ /*--------------------------------------------------------------------------*/
+ //fddWaitIrq( );
+
+ /*--------------------------------------------------------------------------*/
+ /* issue sense interrupt status commands four times */
+ /*--------------------------------------------------------------------------*/
+ /* 1st drive */
+ status = readFdc0SenseInterruptStatus( &st0, &pcn );
+ /* 2nd drive */
+ status |= readFdc0SenseInterruptStatus( &st0, &pcn );
+ /* 3rd drive */
+ status |= readFdc0SenseInterruptStatus( &st0, &pcn );
+ /* 4th drive */
+ status |= readFdc0SenseInterruptStatus( &st0, &pcn );
+
+ if( DEF_FDD_OK != status )
+ {
+ return( DEF_FDD_ERROR );
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* steprate = 3ms, head unload time = 32ms, head load time = 32ms */
+ /*--------------------------------------------------------------------------*/
+ status = writeFd0CmdSpecify( DEF_FDD_STEP_RATE_500K_03,
+ DEF_FDD_HEAD_UNLOAD_TIME_500K_032,
+ DEF_FDD_HEAD_LOAD_TIME_500K_032,
+ False );
+
+ if( DEF_FDD_OK != status )
+ {
+ return( DEF_FDD_ERROR );
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* set data transfer rate to 500kbps( for 3.5 inch ) */
+ /*--------------------------------------------------------------------------*/
+ //writeFdc0Ccr( DEF_FDC_CCR_DRATE_500KBPS );
+
+ /*--------------------------------------------------------------------------*/
+ /* calibrate a head position */
+ /*--------------------------------------------------------------------------*/
+ status = writeFd0CmdRecalibrate( ( E_FDC_CMDS_1ST_PRM )drive );
+
+ if( DEF_FDD_OK != status )
+ {
+ return( DEF_FDD_ERROR );
+ }
+
+ return( status );
+}
+
+
+int writeFd0CmdSeek( E_FDC_CMDS_1ST_PRM drive,E_FDC_CMDS_1ST_PRM head,unsigned char cylinder)
+{
+ int i;
+ int status;
+ unsigned char st0;
+ unsigned char pcn;
+
+ /*--------------------------------------------------------------------------*/
+ /* retry seek */
+ /*--------------------------------------------------------------------------*/
+ for( i = 0 ; i < DEF_FDD_SEEK_RETRY ; i++ )
+ {
+ /*----------------------------------------------------------------------*/
+ /* issue seek command */
+ /*----------------------------------------------------------------------*/
+ status = writeFd0Command( FDC_CMD_SEEK );
+
+ status |= writeFd0Command( ( unsigned char )( drive | head ) );
+
+ status |= writeFd0Command( cylinder );
+
+ /*----------------------------------------------------------------------*/
+ /* wait irq of fdd */
+ /*----------------------------------------------------------------------*/
+ if( DEF_FDD_OK == status )
+ {
+ //fddWaitIrq( );
+ }else{
+ continue;
+ }
+
+ /*----------------------------------------------------------------------*/
+ /* read sense interrupt status */
+ /*----------------------------------------------------------------------*/
+ //status = fddReadSenseInterruptStatus( &st0, &pcn );
+
+ /*----------------------------------------------------------------------*/
+ /* if an error occurs, retry a seek */
+ /*----------------------------------------------------------------------*/
+ if( ( status != DEF_FDD_OK ) || ( ( st0 & DEF_FDC_ST0_IC ) != 0x00 ) )
+ {
+ continue;
+ }
+
+ /*----------------------------------------------------------------------*/
+ /* whether specified cylinder is sought for or not */
+ /*----------------------------------------------------------------------*/
+ if( cylinder == pcn )
+ {
+ /*------------------------------------------------------------------*/
+ /* seek operation is finished! */
+ /*------------------------------------------------------------------*/
+ return( status );
+ }
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* if the drive causes an error */
+ /*--------------------------------------------------------------------------*/
+ return( DEF_FDD_ERROR );
+}
+
+int readFdc0SenseInterruptStatus( unsigned char* st0, unsigned char* pcn )
+{
+ int status;
+
+ if( ( st0 == NULL ) || ( pcn == NULL ) )
+ {
+ return( DEF_FDD_ERROR );
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* issue sense intterup status command */
+ /*--------------------------------------------------------------------------*/
+ status = writeFd0Command( FDC_CMD_SENSE_INTERRUPT_STATUS );
+
+ /*--------------------------------------------------------------------------*/
+ /* read the results */
+ /*--------------------------------------------------------------------------*/
+
+ status |= readFd0Status( st0 );
+
+ status |= readFd0Status( pcn );
+
+ return( status );
+}
+
+int writeFd0CmdRecalibrate( E_FDC_CMDS_1ST_PRM drive )
+{
+ int i;
+ int status;
+ unsigned char st0;
+ unsigned char pcn;
+
+ /*--------------------------------------------------------------------------*/
+ /* start the morter before of a calibration */
+ /*--------------------------------------------------------------------------*/
+ //status = startFdc0Motor( drive );
+
+ if( DEF_FDD_OK == status )
+ {
+ /*----------------------------------------------------------------------*/
+ /* retry a calibration */
+ /*----------------------------------------------------------------------*/
+ for( i = 0 ; i < DEF_FDD_CALIBRATE_RETRY ; i++ )
+ {
+ /*------------------------------------------------------------------*/
+ /* issue recalibrate command */
+ /*------------------------------------------------------------------*/
+ status = writeFd0Command( FDC_CMD_RECALIBRATE );
+
+ status |= writeFd0Command( ( unsigned char )drive );
+
+ /*------------------------------------------------------------------*/
+ /* wait irq of fdd */
+ /*------------------------------------------------------------------*/
+ if( DEF_FDD_OK == status ){
+ //fddWaitIrq( );
+ }else{
+ continue;
+ }
+
+ /*------------------------------------------------------------------*/
+ /* read sense interrupt status */
+ /*------------------------------------------------------------------*/
+ //status = readFdc0SenseInterruptStatus( &st0, &pcn );
+
+ /*------------------------------------------------------------------*/
+ /* if an error occurs, retry a recalibration */
+ /*------------------------------------------------------------------*/
+ if( ( status != DEF_FDD_OK ) || ( ( st0 & DEF_FDC_ST0_IC ) != 0x00 ) )
+ {
+ continue;
+ }
+
+ /*------------------------------------------------------------------*/
+ /* whether head back to track 0 or not */
+ /*------------------------------------------------------------------*/
+ if( 0 == pcn )
+ {
+ /*--------------------------------------------------------------*/
+ /* stop the motor */
+ /*--------------------------------------------------------------*/
+ //status = stopFdc0Motor( drive );
+
+ return( status );
+ }
+ }
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* if the drive causes an error, stop the motor */
+ /*--------------------------------------------------------------------------*/
+ //status = stopFdc0Motor( drive );
+
+ return( DEF_FDD_ERROR );
+}
+
+
+inline void writeFdc0Dor( unsigned char dor )
+{
+ outPortByte( DEF_PORT_FDC0_DOR, dor );
+}
+
+inline unsigned char readFd0MSR( void )
+{
+ return( inPortByte( DEF_PORT_FDC0_MSR ) );
+}
+
+inline bool checkFdc0DriveBusy( E_FDD_DRIVE drive )
+{
+ unsigned char read_data;
+ unsigned char check_drive;
+
+ read_data = readFd0MSR( );
+
+ check_drive = ( unsigned char )( 0x01 << drive );
+
+ read_data &= DEF_FDC_MSR_MASK_DRIVE;
+
+ return( check_drive == ( check_drive & read_data ) );
+}
+
+int waitFdc0( void )
+{
+ int i;
+
+ for( i = 0 ; i < DEF_FDD_RETRY_COUNT ; i++ )
+ {
+ if( False == checkFdc0DriveBusy( E_FDD_DRIVE0 ) )
+ {
+ return( DEF_FDD_OK );
+ }
+ }
+
+ return( DEF_FDD_ERROR );
+}
+
+int writeFd0Command( unsigned char command )
+{
+ int i;
+ unsigned char msr;
+
+ for( i = 0 ; i < DEF_FDD_WRITE_CMD_RETRY ; i++ )
+ {
+ /*----------------------------------------------------------------------*/
+ /* check whether DIO = 0, RQM = 1 */
+ /*----------------------------------------------------------------------*/
+ msr = inPortByte( DEF_PORT_FDC0_MSR );
+ msr = msr & ( DEF_FDC_MSR_DIO | DEF_FDC_MSR_RQM );
+ if( DEF_FDC_MSR_RQM == msr )
+ {
+ outPortByte( DEF_PORT_FDC0_CMD, command );
+ return( DEF_FDD_OK );
+ }
+ }
+ return( DEF_FDD_ERROR );
+}
+
+int readFd0Status( unsigned char *data )
+{
+ int i;
+ unsigned char msr;
+
+ for( i = 0 ; i < DEF_FDD_READ_DATA_RETRY ; i++ )
+ {
+ msr = inPortByte( DEF_PORT_FDC0_MSR );
+ msr = msr & ( DEF_FDC_MSR_DIO | DEF_FDC_MSR_RQM );
+ if( DEF_FDC_MSR_RQM == msr )
+ {
+ *data = inPortByte( DEF_PORT_FDC0_STS );
+ return( DEF_FDD_OK );
+ }
+ }
+
+ return( DEF_FDD_ERROR );
+}
+
+int writeFd0CmdSpecify( unsigned char step_rate,unsigned char head_unload_time,unsigned char head_load_time,bool non_dma_mode)
+{
+ int status;
+ unsigned char parameter;
+
+ /*--------------------------------------------------------------------------*/
+ /* write SPECIFY command */
+ /*--------------------------------------------------------------------------*/
+ status = writeFd0Command( FDC_CMD_SPECIFY );
+
+ /*--------------------------------------------------------------------------*/
+ /* write srt and hut parameters */
+ /*--------------------------------------------------------------------------*/
+ parameter = ( step_rate << 4 ) & DEF_FDC_CMD_SPECIFY_MASK_SRT;
+
+ parameter |= ( head_unload_time << 0 ) & DEF_FDC_CMD_SPECIFY_MASK_HUT;
+
+ status |= writeFd0Command( parameter );
+
+ /*--------------------------------------------------------------------------*/
+ /* write hlt and non-dma mode */
+ /*--------------------------------------------------------------------------*/
+ parameter = ( head_load_time << 1 ) & DEF_FDC_CMD_SPECIFY_MASK_HLT;
+
+ if( non_dma_mode )
+ {
+ parameter |= DEF_FDC_CMD_SPECIFY_NDM;
+ }else{
+ parameter &= ~DEF_FDC_CMD_SPECIFY_NDM;
+ }
+
+ status |= writeFd0Command( parameter );
+
+ return( status );
+}
+
+int writeFdc0CmdReadData( E_FDC_CMDS_1ST_PRM drive,E_FDC_CMDS_1ST_PRM head,unsigned char track,unsigned char sector )
+{
+ int i;
+ int status;
+ unsigned char parameter;
+ unsigned char fdd_statuses[ DEF_FDC_NUM_STATUS ];
+ unsigned char st0; /* status of sense interrupt command */
+ unsigned char pcn; /* status of sense interrupt command */
+
+ /*--------------------------------------------------------------------------*/
+ /* write read data command */
+ /*--------------------------------------------------------------------------*/
+ status = writeFd0Command( FDC_CMD_READ_DATA );
+
+ /*--------------------------------------------------------------------------*/
+ /* write head and drive parameters */
+ /*--------------------------------------------------------------------------*/
+ parameter = ( unsigned char )( head | drive );
+
+ status |= writeFd0Command( parameter );
+
+ /*--------------------------------------------------------------------------*/
+ /* write specified track */
+ /*--------------------------------------------------------------------------*/
+ status |= writeFd0Command( track );
+
+ /*--------------------------------------------------------------------------*/
+ /* write specified drive */
+ /*--------------------------------------------------------------------------*/
+ status |= writeFd0Command( ( unsigned char )head >> 2 );
+
+ /*--------------------------------------------------------------------------*/
+ /* write specified sector */
+ /*--------------------------------------------------------------------------*/
+ if( DEF_FDD_SECTORS_PER_TRACK < sector )
+ {
+ sector = DEF_FDD_SECTORS_PER_TRACK;
+ }
+ status |= writeFd0Command( sector );
+
+ /*--------------------------------------------------------------------------*/
+ /* write sector size */
+ /*--------------------------------------------------------------------------*/
+ status |= writeFd0Command( ( unsigned char )FDC_CMD_SECTOR_SIZE_512 );
+
+ /*--------------------------------------------------------------------------*/
+ /* write length of track */
+ /*--------------------------------------------------------------------------*/
+ status |= writeFd0Command( DEF_FDD_SECTORS_PER_TRACK );
+
+ /*--------------------------------------------------------------------------*/
+ /* write gap3 length */
+ /*--------------------------------------------------------------------------*/
+ status |= writeFd0Command( ( unsigned char )FDC_CMD_GAP3_SIZE_3_5 );
+
+ /*--------------------------------------------------------------------------*/
+ /* write data length( special sector size ) */
+ /*--------------------------------------------------------------------------*/
+ status |= writeFd0Command( DEF_FDC_CMDS_PRM_DTL );
+
+ if( DEF_FDD_OK == status )
+ {
+ /*----------------------------------------------------------------------*/
+ /* wait until irq of fdd is fired */
+ /*----------------------------------------------------------------------*/
+ //fddWaitIrq( );
+
+ /*----------------------------------------------------------------------*/
+ /* read statuses */
+ /*----------------------------------------------------------------------*/
+ for( i = 0 ; i < DEF_FDC_NUM_STATUS ; i++ )
+ {
+ status |= readFd0Status( &fdd_statuses[ i ] );
+ }
+
+ if( DEF_FDD_OK != status )
+ {
+ return( status );
+ }
+
+ /*----------------------------------------------------------------------*/
+ /* issue sense interrupt status command and read its statuses */
+ /*----------------------------------------------------------------------*/
+ readFdc0SenseInterruptStatus( &st0, &pcn );
+ }
+
+ return( status );
+}
+
+
+int fddReadSector(unsigned char drive,unsigned int lba,unsigned char *trasfered_address,unsigned int data_length )
+{
+ unsigned char head;
+ unsigned char track;
+ unsigned char sector;
+ int status;
+
+ if( DEF_FDC_DOR_DRIVE3 < drive )
+ {
+ return( DEF_FDD_ERROR );
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* set up DMA controller for fdd */
+ /*--------------------------------------------------------------------------*/
+ status = initDMAforReadFDD( trasfered_address,
+ data_length - 1 );
+
+ /*--------------------------------------------------------------------------*/
+ /* start the motor of specified dirve */
+ /*--------------------------------------------------------------------------*/
+ //startFdc0Motor( drive );
+
+ /*--------------------------------------------------------------------------*/
+ /* convert lba to chs */
+ /*--------------------------------------------------------------------------*/
+ head = convertLBA2Head( lba );
+ track = convertLBA2Track( lba );
+ sector = convertLBA2Sector( lba );
+
+ /*--------------------------------------------------------------------------*/
+ /* seek specified track */
+ /*--------------------------------------------------------------------------*/
+ //status = fddSeek( drive, head, track );
+
+ if( status != DEF_FDD_OK )
+ {
+ return( status );
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* issue read data command to read a sector */
+ /*--------------------------------------------------------------------------*/
+ status = writeFdc0CmdReadData( drive, head, track, sector );
+
+ /*--------------------------------------------------------------------------*/
+ /* wait until irq of dma is fired */
+ /*--------------------------------------------------------------------------*/
+ //dmaWaitIrq( E_DMA_CHANNEL2 );
+
+ /*--------------------------------------------------------------------------*/
+ /* stop the motor of specified dirve */
+ /*--------------------------------------------------------------------------*/
+ //stopFdc0Motor( drive );
+
+ return( status );
+}
+
+int initDMAforReadFDD( unsigned char *phy_adr, unsigned int length )
+{
+ return( dmaInitDMA( E_DMA_TRANSFER_TYPE_WRITE,E_DMA_CHANNEL2,(void*)phy_adr,length ) );
+}
+
+int dmaInitDMA( E_DMA_TRANSFER_TYPE type,E_DMA_CHANNEL channel,void *phy_adr,unsigned int length )
+{
+ int status;
+ unsigned short trans_adr;
+
+ if( USHRT_MAX < length )
+ {
+ return( DEF_DMA_ERROR );
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* mask the channel */
+ /*--------------------------------------------------------------------------*/
+ dmaMaskChannel( channel );
+
+ if( DEF_DMA_OK != status ) return DEF_DMA_ERROR;
+
+ /*--------------------------------------------------------------------------*/
+ /* clear the flip flop of dmc1 */
+ /*--------------------------------------------------------------------------*/
+ status = dmaResetFlipFlop( E_DMA_CLASS_MASTER );
+
+ if( DEF_DMA_OK != status ) return DEF_DMA_ERROR;
+
+ /*--------------------------------------------------------------------------*/
+ /* set transfered address */
+ /*--------------------------------------------------------------------------*/
+ trans_adr = ( unsigned short )( ( unsigned int )phy_adr & DEF_DMAC_ADDRESS );
+ status = dmaSetAddress( channel, trans_adr );
+
+ if( DEF_DMA_OK != status ) return DEF_DMA_ERROR;
+
+ /*--------------------------------------------------------------------------*/
+ /* clear the flip flop of dmc1 again */
+ /*--------------------------------------------------------------------------*/
+ status = dmaResetFlipFlop( E_DMA_CLASS_MASTER );
+
+ if( DEF_DMA_OK != status ) return DEF_DMA_ERROR;
+
+ /*--------------------------------------------------------------------------*/
+ /* set the length of transfered data */
+ /*--------------------------------------------------------------------------*/
+ status = dmaSetCounter( channel, ( unsigned short )length );
+
+ if( DEF_DMA_OK != status ) return DEF_DMA_ERROR;
+
+ /*--------------------------------------------------------------------------*/
+ /* set transfer type */
+ /*--------------------------------------------------------------------------*/
+ switch( type )
+ {
+ case E_DMA_TRANSFER_TYPE_WRITE:
+ //status |= dmaSetWriteTransferMode( channel );
+ break;
+ case E_DMA_TRANSFER_TYPE_READ:
+ status |= dmaSetReadTransferMode( channel );
+ break;
+ default:
+ return( DEF_DMA_ERROR );
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* unmask the channel */
+ /*--------------------------------------------------------------------------*/
+ dmaUnmaskChannel( channel );
+
+ return( status );
+}
+
+/*DMA Drivers*/
+int dmaSetAddress( E_DMA_CHANNEL channel, unsigned short address )
+{
+ unsigned short port_address;
+
+ if( E_DMA_CHANNEL7 < channel )
+ {
+ return( DEF_DMA_ERROR );
+ }
+
+ switch( channel )
+ {
+ case E_DMA_CHANNEL0:
+ port_address = DEF_PORT_DMAC0_CH0_ADDRESS;
+ break;
+ case E_DMA_CHANNEL1:
+ port_address = DEF_PORT_DMAC0_CH1_ADDRESS;
+ break;
+ case E_DMA_CHANNEL2:
+ port_address = DEF_PORT_DMAC0_CH2_ADDRESS;
+ break;
+ case E_DMA_CHANNEL3:
+ port_address = DEF_PORT_DMAC0_CH3_ADDRESS;
+ break;
+ case E_DMA_CHANNEL4:
+ port_address = DEF_PORT_DMAC1_CH4_ADDRESS;
+ break;
+ case E_DMA_CHANNEL5:
+ port_address = DEF_PORT_DMAC1_CH5_ADDRESS;
+ break;
+ case E_DMA_CHANNEL6:
+ port_address = DEF_PORT_DMAC1_CH6_ADDRESS;
+ break;
+ case E_DMA_CHANNEL7:
+ port_address = DEF_PORT_DMAC1_CH7_ADDRESS;
+ break;
+ default:
+ return( DEF_DMA_ERROR );
+ break;
+ }
+
+ outPortByte( port_address, ( 0x00FF ) & address );
+ outPortByte( port_address, ( ( 0xFF00 ) & address ) >> 8 );
+
+ return( DEF_DMA_OK );
+}
+
+
+int dmaSetCounter( E_DMA_CHANNEL channel, unsigned short count )
+{
+ unsigned short port_address;
+
+ if( E_DMA_CHANNEL7 < channel )
+ {
+ return( DEF_DMA_ERROR );
+ }
+
+ switch( channel )
+ {
+ case E_DMA_CHANNEL0:
+ port_address = DEF_PORT_DMAC0_CH0_COUNTER;
+ break;
+ case E_DMA_CHANNEL1:
+ port_address = DEF_PORT_DMAC0_CH1_COUNTER;
+ break;
+ case E_DMA_CHANNEL2:
+ port_address = DEF_PORT_DMAC0_CH2_COUNTER;
+ break;
+ case E_DMA_CHANNEL3:
+ port_address = DEF_PORT_DMAC0_CH3_COUNTER;
+ break;
+ case E_DMA_CHANNEL4:
+ port_address = DEF_PORT_DMAC1_CH4_COUNTER;
+ break;
+ case E_DMA_CHANNEL5:
+ port_address = DEF_PORT_DMAC1_CH5_COUNTER;
+ break;
+ case E_DMA_CHANNEL6:
+ port_address = DEF_PORT_DMAC1_CH6_COUNTER;
+ break;
+ case E_DMA_CHANNEL7:
+ port_address = DEF_PORT_DMAC1_CH7_COUNTER;
+ break;
+ default:
+ return( DEF_DMA_ERROR );
+ }
+
+ outPortByte( port_address, ( 0x00FF ) & count );
+ outPortByte( port_address, ( ( 0xFF00 ) & count ) >> 8 );
+
+ return( DEF_DMA_OK );
+}
+
+int dmaSetPageAddress( E_DMA_CHANNEL channel, unsigned char page )
+{
+ unsigned short port_address;
+
+ if( E_DMA_CHANNEL7 < channel )
+ {
+ return( DEF_DMA_ERROR );
+ }
+
+ switch( channel )
+ {
+ case E_DMA_CHANNEL0:
+ port_address = DEF_PORT_DMAC_PAGE_CH0;
+ break;
+ case E_DMA_CHANNEL1:
+ port_address = DEF_PORT_DMAC_PAGE_CH1;
+ break;
+ case E_DMA_CHANNEL2:
+ port_address = DEF_PORT_DMAC_PAGE_CH2;
+ break;
+ case E_DMA_CHANNEL3:
+ port_address = DEF_PORT_DMAC_PAGE_CH3;
+ break;
+ case E_DMA_CHANNEL4:
+ /* exclusive for the connection to the slave */
+ return( DEF_DMA_OK );
+ break;
+ case E_DMA_CHANNEL5:
+ port_address = DEF_PORT_DMAC_PAGE_CH5;
+ break;
+ case E_DMA_CHANNEL6:
+ port_address = DEF_PORT_DMAC_PAGE_CH6;
+ break;
+ case E_DMA_CHANNEL7:
+ port_address = DEF_PORT_DMAC_PAGE_CH7;
+ break;
+ default:
+ return( DEF_DMA_ERROR );
+ }
+
+ outPortByte( port_address, page );
+
+ return( DEF_DMA_OK );
+}
+
+int dmaSetModeReg( E_DMA_CHANNEL channel, unsigned char mode )
+{
+ unsigned short port_address;
+
+ if( E_DMA_CHANNEL7 < channel )
+ {
+ return( DEF_DMA_ERROR );
+ }
+
+ switch( channel )
+ {
+ /*--------------------------------------------------------------------------*/
+ /* for slave */
+ /*--------------------------------------------------------------------------*/
+ case E_DMA_CHANNEL0:
+ case E_DMA_CHANNEL1:
+ case E_DMA_CHANNEL2:
+ case E_DMA_CHANNEL3:
+ port_address = DEF_PORT_DMAC0_MODE;
+ break;
+ /*--------------------------------------------------------------------------*/
+ /* for master */
+ /*--------------------------------------------------------------------------*/
+ case E_DMA_CHANNEL4:
+ case E_DMA_CHANNEL5:
+ case E_DMA_CHANNEL6:
+ case E_DMA_CHANNEL7:
+ port_address = DEF_PORT_DMAC1_MODE;
+ /* adjust channel value to mode register bit */
+ channel = ( E_DMA_CHANNEL )( channel - E_DMA_CHANNEL4 );
+ break;
+ default:
+ return( DEF_DMA_ERROR );
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* write value to mode register */
+ /*--------------------------------------------------------------------------*/
+ mode = mode | channel;
+ outPortByte( port_address, mode );
+
+ return( DEF_DMA_OK );
+}
+
+inline int dmaSetReadTransferMode( E_DMA_CHANNEL channel )
+{
+ unsigned char mode;
+
+ mode = DEF_DMAC_MODE_TRA_WRITE |
+ DEF_DMAC_MODE_MOD_SINGLE |
+ DEF_DMAC_MODE_AUTO_ENABLE;
+
+ return( dmaSetModeReg( channel, mode ) );
+}
+
+inline void dmaMaskChannel( E_DMA_CHANNEL channel )
+{
+ unsigned char bit_ch;
+ unsigned short port_address;
+
+ /*--------------------------------------------------------------------------*/
+ /* read current mask bit */
+ /*--------------------------------------------------------------------------*/
+ if( E_DMA_CHANNEL3 < channel )
+ {
+ bit_ch = inPortByte( DEF_PORT_DMAC0_ALL_MASK );
+ /* adjust mask bit for all mask register */
+ channel = channel - E_DMA_CHANNEL4;
+ port_address = DEF_PORT_DMAC0_ALL_MASK;
+ }else{
+ bit_ch = inPortByte( DEF_PORT_DMAC1_ALL_MASK );
+ port_address = DEF_PORT_DMAC1_ALL_MASK;
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* set designated channel bit */
+ /*--------------------------------------------------------------------------*/
+ bit_ch = bit_ch | ( 1 << channel );
+
+ outPortByte( port_address, bit_ch );
+}
+
+inline void dmaUnmaskChannel( E_DMA_CHANNEL channel )
+{
+ unsigned char bit_ch;
+ unsigned short port_address;
+
+ /*--------------------------------------------------------------------------*/
+ /* read current mask bit */
+ /*--------------------------------------------------------------------------*/
+ if( E_DMA_CHANNEL3 < channel )
+ {
+ bit_ch = inPortByte( DEF_PORT_DMAC0_ALL_MASK );
+ /* adjust mask bit for all mask register */
+ channel = channel - E_DMA_CHANNEL4;
+ port_address = DEF_PORT_DMAC0_ALL_MASK;
+ }
+ else
+ {
+ bit_ch = inPortByte( DEF_PORT_DMAC1_ALL_MASK );
+ port_address = DEF_PORT_DMAC1_ALL_MASK;
+ }
+
+ /*--------------------------------------------------------------------------*/
+ /* set designated channel bit */
+ /*--------------------------------------------------------------------------*/
+ bit_ch = bit_ch & ~( 1 << channel );
+
+ outPortByte( port_address, bit_ch );
+}
+
+int dmaResetFlipFlop( E_DMA_CLASS class )
+{
+ unsigned char port_address;
+
+ if( E_DMA_CLASS_SLAVE < class )
+ {
+ return( DEF_DMA_ERROR );
+ }
+
+ switch( class )
+ {
+ case E_DMA_CLASS_MASTER:
+ port_address = DEF_PORT_DMAC1_CLEAR_BP;
+ break;
+ case E_DMA_CLASS_SLAVE:
+ port_address = DEF_PORT_DMAC0_CLEAR_BP;
+ break;
+ default:
+ return( DEF_DMA_ERROR );
+ }
+
+ outPortByte( port_address, DEF_DMAC_CLR_DATA );
+
+ return( DEF_DMA_OK );
+}
+
+int dmaResetAllMask( E_DMA_CLASS class )
+{
+ BYTE port_address;
+
+ if( E_DMA_CLASS_SLAVE < class )
+ {
+ return( DEF_DMA_ERROR );
+ }
+
+ switch( class )
+ {
+ case E_DMA_CLASS_MASTER:
+ port_address = DEF_PORT_DMAC1_MASK_RESET;
+ break;
+ case E_DMA_CLASS_SLAVE:
+ port_address = DEF_PORT_DMAC0_MASK_RESET;
+ break;
+ default:
+ return( DEF_DMA_ERROR );
+ }
+
+ outPortByte( port_address, DEF_DMAC_CLR_DATA );
+
+ return( DEF_DMA_OK );
+}
+
+int dmaClearMaster( E_DMA_CLASS class )
+{
+ BYTE port_address;
+
+ if( E_DMA_CLASS_SLAVE < class )
+ {
+ return( DEF_DMA_ERROR );
+ }
+
+ switch( class )
+ {
+ case E_DMA_CLASS_MASTER:
+ port_address = DEF_PORT_DMAC1_MASTER_CLEAR;
+ break;
+ case E_DMA_CLASS_SLAVE:
+ port_address = DEF_PORT_DMAC0_MASTER_CLEAR;
+ break;
+ default:
+ return( DEF_DMA_ERROR );
+ }
+
+ outPortByte( port_address, DEF_DMAC_CLR_DATA );
+
+ return( DEF_DMA_OK );
+}
+++ /dev/null
-SECTIONS
-{
-
- .text :
- {
- _text_start = .;
- *(.text)
- _text_end = .;
- }
-
- .rodata :
- {
- _rodata_start = .;
- *(.rodata)
- _rodata_end = .;
- }
-
- .data :
- {
- _data_start = .;
- *(.data)
- _data_end = .;
- }
-
- .bss :
- {
- _bss_start = .;
- *(.bss)
- _bss_end = .;
- }
-}
#include<GDT_IDT.h>
#include<tools.h>
+extern memmgr* memman;
unsigned int esp_addr[TASK_INFO_TOTAL];
+task_manager taskmgr;
+task_status taskstate[TASK_INFO_TOTAL];
void task_a()
{
*cur_task = 0;
for( i = 0; i < TASK_INFO_TOTAL; ++i ){
zero_memory( t + i, sizeof( TaskInfo ) );
+ taskmgr.tasks[i]=&taskstate[i];//Tasks None
+ taskstate[i].status=DISUSE;
}
+ /*Kernel Task*/
+ taskstate[0].id=io_load_esp();
+ taskstate[0].status=NORMAL;
+ taskstate[0].run_level=KERNEL;
+ taskstate[0].request=NONERQ;
+ taskstate[0].parent_id=KERNEL;
+ esp_addr[0]=io_load_esp();
+
+ taskmgr.task_time=0;
+ taskmgr.task_num=1;//1 -> Kernel
}
-void k_mktask(unsigned task,void (*f)(),memmgr *memman)
+void k_mktask(void (*f)())
{
- int free=int_linear_search(esp_addr[512],0);
+ int free=int_linear_search(esp_addr[TASK_INFO_TOTAL],0);
+ if(free== -1)return;//stack address full
+
esp_addr[free]=k_malloc(memman,1);
- set_task(task,f,esp_addr[free]);
+ set_task(free,f,esp_addr[free]);
}
-void set_task( unsigned int task, void (*f)(), unsigned char* esp )
+void set_task( unsigned int task, void (*f)(), unsigned char* esp)
{
TaskInfo* t = (TaskInfo*)TASK_INFO_ADDR;
if( task > TASK_INFO_TOTAL ){
t->eip = -0x280000 + (unsigned int) f;
t->esp = (unsigned int) esp;
t->eflags = 0x00000202;
+
+ taskstate[task].id=esp;
+ taskstate[task].status=NORMAL;
+ taskstate[task].run_level=KERNEL;
+ taskstate[task].request=NONERQ;
+ taskstate[task].parent_id=KERNEL;
+ esp_addr[task]=esp;
}
unsigned int get_cur_task_num()
}
return -1;
}
+
+inline int uint_bit_database(unsigned int *src, int search, int mode)
+{
+ int ret=0;
+ if(mode==0){
+ //Change value
+ unsigned int x=*src,i;
+ for(i=0;i<=search;i++)x>>=1;
+ i=1;
+ if(x & 1U)i=0;
+ x&=i;
+ *src=x;
+
+ }else if(mode==1){
+ //search first zero
+ unsigned int count=0,x=*src;
+ while(x){
+ if(x & 1U){
+ ret=count;
+ break;
+ }
+ count++;
+ }
+ }else{
+ //num of 1
+ unsigned int count=0,x=*src;
+ while(x){
+ if(x & 1U)count++;
+ x>>=1;
+ }
+ ret=count;
+ }
+ return ret;
+}
#define DEF_IDT_INT_NUM_SYSC 0x30
#define DEF_IDT_INT_NUM_V86I 0x31
#define DEF_IDT_INT_NUM_V86O 0x32
+#define DEF_IDT_INT_NUM_IRQ6 38
#define DEF_IDT_INT_SELECTOR 0x08
void load_gdt(void);
void load_idt(void);
+#define AR_TSS32 0x0089
/*GDT Segment Descriptor*/
typedef struct
/*
-extern int timer_tick;
+*Interrupt Header
+*(C) 2014 VOSystems.
*/
#ifndef INTERRUPT_H
void INTERRUPT_NOTHING(void);
void out_virtual86mode_interrupt(void);
void in_virtual86mode_interrupt(void);
+void Floppy_Interrupt_asm(void);
void enter_interrupt(void);
void interrupt_done(void);
void enable();
void disable();
+
#endif
/*
-extern int timer_tick;
+*Interrupt Header
+*(C) 2014 VOSystems.
*/
#ifndef INTERRUPT_H
#define INTERRUPT_H
-struct timer
-{
- unsigned int count,timeout;
- struct msg *msg;
- unsigned int data;
-};
-
void Timer_Interrupt_asm(void);
void KeyBoard_Interrupt_asm(void);
void INTERRUPT_NOTHING(void);
void enable();
void disable();
+
#endif
void io_out8(int port, int data);
int io_load_eflags(void);
void io_store_eflags(int eflags);
+int io_load_esp(void);
int Check_VESA(void);
void ScreenVGA_Graphic(void);
/*Task.S*/
void task_switch(void);
void switch_task(int src,int dst);
-void switch_task_2();
+void switch_task_2(int src,int dst);
void toswitch(int eax);
#define cr() putchar('\n');
--- /dev/null
+/*
+*Device Driver for Kernel
+*(C) 2014 VOSystems.
+*/
+
+#ifndef _DEVICE_H_VANE_
+#define _DEVICE_H_VANE_
+
+#include<type.h>
+
+/*FDD Driver*/
+
+typedef enum
+{
+ E_FDD_DRIVE0 = 0x00000000,
+ E_FDD_DRIVE1 = 0x00000001,
+ E_FDD_DRIVE2 = 0x00000002,
+ E_FDD_DRIVE3 = 0x00000003
+} E_FDD_DRIVE;
+
+
+#define E_FDD_DRIVE0 0x00000000
+#define E_FDD_DRIVE1 0x00000001
+#define E_FDD_DRIVE2 0x00000002
+#define E_FDD_DRIVE3 0x00000003
+
+#define DEF_FDD_OK 0
+#define DEF_FDD_ERROR (-1)
+#define DEF_FDD_RETRY_COUNT 500
+
+#define DEF_FDD_WRITE_CMD_RETRY 500
+#define DEF_FDD_READ_DATA_RETRY 500
+
+#define DEF_FDC_NUM_STATUS 300
+
+typedef enum
+{
+ FDC_CMD_READ_TRACK = 0x02,
+ FDC_CMD_SPECIFY = 0x03,
+ FDC_CMD_SENSE_DRIVE_STATUS = 0x04,
+ FDC_CMD_WRITE_DATA = 0x05,
+ FDC_CMD_READ_DATA = 0x06,
+ FDC_CMD_RECALIBRATE = 0x07,
+ FDC_CMD_SENSE_INTERRUPT_STATUS = 0x08,
+ FDC_CMD_WRITE_DELETED_DATA = 0x09,
+ FDC_CMD_READ_ID = 0x0A,
+ FDC_CMD_READ_DELETED_DATA = 0x0C,
+ FDC_CMD_FORMAT_TRACK = 0x0D,
+ FDC_CMD_DUMPREG = 0x0E,
+ FDC_CMD_SEEK = 0x0F,
+ FDC_CMD_VERSION = 0x10,
+ FDC_CMD_SCAN_EQUAL = 0x11,
+ FDC_CMD_PERPENDICULAR_MODE = 0x12,
+ FDC_CMD_CONFIGURE = 0x13,
+ FDC_CMD_LOCK = 0x14,
+ FDC_CMD_VERIFY = 0x16,
+ FDC_CMD_SCAN_LOW_OR_EQUAL = 0x19,
+ FDC_CMD_SCAN_HIGH_OR_EQUAL = 0x1D,
+ FDC_CMD_RELATIVE_SEEK = 0x8F
+} E_FDC_CMDS;
+
+typedef enum
+{
+ FDC_CMD_EXT_SK = 0x20,
+ FDC_CMD_EXT_MF = 0x40,
+ FDC_CMD_EXT_MT = 0x80
+} E_FDC_CMDS_EXT;
+
+typedef enum
+{
+ FDC_CMD_1ST_PRM_DRIVE0 = 0x00,
+ FDC_CMD_1ST_PRM_DRIVE1 = 0x01,
+ FDC_CMD_1ST_PRM_DRIVE2 = 0x02,
+ FDC_CMD_1ST_PRM_DRIVE3 = 0x03,
+ FDC_CMD_1ST_PRM_HEAD0 = 0x00,
+ FDC_CMD_1ST_PRM_HEAD1 = 0x04
+} E_FDC_CMDS_1ST_PRM;
+
+typedef enum
+{
+ FDC_CMD_GAP3_SIZE_3_5 = 27,
+ FDC_CMD_GAP3_SIZE_5_25 = 32,
+ FDC_CMD_GAP3_SIZE_STD = 42
+} E_FDC_CMDS_GP3_SIZE;
+
+typedef enum
+{
+ FDC_CMD_SECTOR_SIZE_128 = 0,
+ FDC_CMD_SECTOR_SIZE_256 = 1,
+ FDC_CMD_SECTOR_SIZE_512 = 2,
+ FDC_CMD_SECTOR_SIZE_1024 = 3,
+ FDC_CMD_SECTOR_SIZE_2048 = 4,
+ FDC_CMD_SECTOR_SIZE_4096 = 5,
+ FDC_CMD_SECTOR_SIZE_8192 = 6,
+ FDC_CMD_SECTOR_SIZE_16384 = 7
+} E_FDC_CMDS_SECTOR_SIZE;
+
+#define DEF_FDC_CMD_SPECIFY_MASK_SRT ( 0x0F << 4 )
+#define DEF_FDC_CMD_SPECIFY_MASK_HUT ( 0x0F << 0 )
+#define DEF_FDC_CMD_SPECIFY_MASK_HLT ( 0x7F << 1 )
+#define DEF_FDC_CMD_SPECIFY_NDM 0x01
+
+#define DEF_FDC_CMDS_PRM_DTL 0xFF
+
+#define DEF_FDD_SECTORS_PER_TRACK 18
+
+#define DEF_FDD_CALIBRATE_RETRY 10
+
+#define DEF_FDC_ST0_IC 0xC0
+
+#define DEF_FDD_SEEK_RETRY 10
+
+#define DEF_FDD_STEP_RATE_500K_03 0xD /* 3msec */
+#define DEF_FDD_HEAD_UNLOAD_TIME_500K_032 0x2 /* 32mese */
+#define DEF_FDD_HEAD_LOAD_TIME_500K_032 0x10 /* 32msec */
+
+#define DEF_FDC_CCR_DRATE_500KBPS 0x00 /* 500Kbps */
+#define DEF_FDC_CCR_DRATE_300KBPS 0x01 /* 300Kbps */
+#define DEF_FDC_CCR_DRATE_250KBPS 0x02 /* 250Kbps */
+#define DEF_FDC_CCR_DRATE_1MBPS 0x03 /* 1Mbps */
+
+#define DEF_FDD_SECTORS_PER_TRACK 18
+#define DEF_FDD_NUM_HEADS 2
+
+#define DEF_PORT_FDC1_SRA 0x0370 /* status register A */
+#define DEF_PORT_FDC1_SRB 0x0371 /* status register B */
+#define DEF_PORT_FDC1_DOR 0x0372 /* Digital output register */
+#define DEF_PORT_FDC1_TAPE 0x0373 /* tapa drive register */
+#define DEF_PORT_FDC1_MSR 0x0374 /* main status register */
+#define DEF_PORT_FDC1_DRS 0x0374 /* data rate select register */
+#define DEF_PORT_FDC1_STS 0x0375 /* status register 0,1,2,3( ST0,1,2,3 ) */
+#define DEF_PORT_FDC1_DATA 0x0375 /* data( status ) register */
+#define DEF_PORT_FDC1_CMD 0x0375 /* command register */
+#define DEF_PORT_FDC1_RESERVED 0x0376 /* reserved */
+#define DEF_PORT_FDC1_DIR 0x0377 /* digital input register */
+#define DEF_PORT_FDC1_CCR 0x0377 /* configuration control register */
+
+/*Description :Floppy Disc Controller( 1st )*/
+#define DEF_PORT_FDC0_SRA 0x03F0 /* status register A */
+#define DEF_PORT_FDC0_SRB 0x03F1 /* status register B */
+#define DEF_PORT_FDC0_DOR 0x03F2 /* Digital output register */
+#define DEF_PORT_FDC0_TAPE 0x03F3 /* tapa drive register */
+#define DEF_PORT_FDC0_MSR 0x03F4 /* main status register */
+#define DEF_PORT_FDC0_DRS 0x03F4 /* data rate select register */
+#define DEF_PORT_FDC0_STS 0x03F5 /* status register 0,1,2,3( ST0,1,2,3 ) */
+#define DEF_PORT_FDC0_DATA 0x03F5 /* data( status ) register */
+#define DEF_PORT_FDC0_CMD 0x03F5 /* command register */
+#define DEF_PORT_FDC0_RESERVED 0x03F6 /* reserved */
+#define DEF_PORT_FDC0_DIR 0x03F7 /* digital input register */
+#define DEF_PORT_FDC0_CCR 0x03F7 /* configuration control register */
+
+#define DEF_FDC_DOR_DRIVE0 0x00 /* b00000000 */
+#define DEF_FDC_DOR_DRIVE1 0x01 /* b00000001 */
+#define DEF_FDC_DOR_DRIVE2 0x02 /* b00000010 */
+#define DEF_FDC_DOR_DRIVE3 0x03 /* b00000011 */
+
+#define DEF_FDC_DOR_ENABLE 0x04 /* b00000100 */
+
+#define DEF_FDC_DOR_DMA 0x08 /* b00001000 */
+#define DEF_FDC_DOR_MOTOR0 0x10 /* b00010000 */
+#define DEF_FDC_DOR_MOTOR1 0x20 /* b00100000 */
+#define DEF_FDC_DOR_MOTOR2 0x40 /* b01000000 */
+#define DEF_FDC_DOR_MOTOR3 0x80 /* b10000000 */
+
+#define DEF_FDC_DOR_RESET 0x00
+
+#define DEF_FDC_MSR_DRIVE0_BUSY 0x01 /* b00000001 */
+#define DEF_FDC_MSR_DRIVE1_BUSY 0x02 /* b00000010 */
+#define DEF_FDC_MSR_DRIVE2_BUSY 0x04 /* b00000100 */
+#define DEF_FDC_MSR_DRIVE3_BUSY 0x08 /* b00001000 */
+#define DEF_FDC_MSR_MASK_DRIVE 0x0F /* b00001111 */
+
+#define DEF_FDC_MSR_COMMAND_BUSY 0x10 /* b00010000 */
+#define DEF_FDC_MSR_NON_DMA 0x20 /* b00100000 */
+#define DEF_FDC_MSR_DIO 0x40 /* b01000000 */
+#define DEF_FDC_MSR_RQM 0x80 /* b10000000 */
+
+
+
+/*DMA Driver*/
+#define DEF_DMA_OK 0
+#define DEF_DMA_ERROR (-1)
+
+typedef enum
+{
+ E_DMA_CHANNEL0 = 0,
+ E_DMA_CHANNEL1 = 1,
+ E_DMA_CHANNEL2 = 2,
+ E_DMA_CHANNEL3 = 3,
+ E_DMA_CHANNEL4 = 4,
+ E_DMA_CHANNEL5 = 5,
+ E_DMA_CHANNEL6 = 6,
+ E_DMA_CHANNEL7 = 7
+}E_DMA_CHANNEL;
+
+typedef enum
+{
+ E_DMA_TRANSFER_TYPE_WRITE=0,
+ E_DMA_TRANSFER_TYPE_READ=1
+}E_DMA_TRANSFER_TYPE;
+
+typedef enum
+{
+ E_DMA_CLASS_MASTER = 0x00,
+ E_DMA_CLASS_SLAVE = 0x01
+}E_DMA_CLASS;
+
+#define DEF_DMAC_CLR_DATA 0xFF
+#define DEF_DMAC_ADDRESS 0xffffffcf
+
+/*DMAC0 Ports( Slave )*/
+#define DEF_PORT_DMAC0_STATUS 0x0008 /* status register */
+#define DEF_PORT_DMAC0_COMMAND 0x0008 /* command register */
+#define DEF_PORT_DMAC0_REQUEST 0x0009 /* request register */
+#define DEF_PORT_DMAC0_SINGLE_MASK 0x000A /* single mask register */
+#define DEF_PORT_DMAC0_MODE 0x000B /* mode register */
+#define DEF_PORT_DMAC0_CLEAR_BP 0x000C /* clear byte pointer register */
+#define DEF_PORT_DMAC0_TEMPORARY 0x000D /* temporary register */
+#define DEF_PORT_DMAC0_MASTER_CLEAR 0x000D /* master clear register */
+#define DEF_PORT_DMAC0_MASK_RESET 0x000E /* mask reset register */
+#define DEF_PORT_DMAC0_ALL_MASK 0x000F /* all mask register */
+
+/* DMAC1 Ports( Master ) */
+#define DEF_PORT_DMAC1_STATUS 0x00D0 /* status register */
+#define DEF_PORT_DMAC1_COMMAND 0x00D0 /* command register */
+#define DEF_PORT_DMAC1_REQUEST 0x00D2 /* request register */
+#define DEF_PORT_DMAC1_SINGLE_MASK 0x00D4 /* single mask register */
+#define DEF_PORT_DMAC1_MODE 0x00D6 /* mode Register */
+#define DEF_PORT_DMAC1_CLEAR_BP 0x00D8 /* clear byte pointer register */
+#define DEF_PORT_DMAC1_TEMPORARY 0x00DA /* temporary Register */
+#define DEF_PORT_DMAC1_MASTER_CLEAR 0x00DA /* master clear Register */
+#define DEF_PORT_DMAC1_MASK_RESET 0x00DC /* mask reset Register */
+#define DEF_PORT_DMAC1_ALL_MASK 0x00DE /* all mask Register */
+
+/* DMAC0 Ports( Slave ) */
+#define DEF_PORT_DMAC0_CH0_ADDRESS 0x0000 /* Channel 0 base address register */
+#define DEF_PORT_DMAC0_CH0_COUNTER 0x0001 /* Channel 0 base count register */
+#define DEF_PORT_DMAC0_CH1_ADDRESS 0x0002 /* Channel 1 base address register */
+#define DEF_PORT_DMAC0_CH1_COUNTER 0x0003 /* Channel 1 base count register */
+#define DEF_PORT_DMAC0_CH2_ADDRESS 0x0004 /* Channel 2 base address register */
+#define DEF_PORT_DMAC0_CH2_COUNTER 0x0005 /* Channel 2 base count register */
+#define DEF_PORT_DMAC0_CH3_ADDRESS 0x0006 /* Channel 3 base address register */
+#define DEF_PORT_DMAC0_CH3_COUNTER 0x0007 /* Channel 3 base count register */
+
+/* DMAC1 Ports( Master ) */
+#define DEF_PORT_DMAC1_CH4_ADDRESS 0x00C0 /* Channel 4 base address register */
+#define DEF_PORT_DMAC1_CH4_COUNTER 0x00C2 /* Channel 4 base count register */
+#define DEF_PORT_DMAC1_CH5_ADDRESS 0x00C4 /* Channel 5 base address register */
+#define DEF_PORT_DMAC1_CH5_COUNTER 0x00C6 /* Channel 5 base count register */
+#define DEF_PORT_DMAC1_CH6_ADDRESS 0x00C8 /* Channel 6 base address register */
+#define DEF_PORT_DMAC1_CH6_COUNTER 0x00CA /* Channel 6 base count register */
+#define DEF_PORT_DMAC1_CH7_ADDRESS 0x00CC /* Channel 7 base address register */
+#define DEF_PORT_DMAC1_CH7_COUNTER 0x00CE /* Channel 7 base count register */
+
+
+#define DEF_PORT_DMAC_PAGE_CH0_ORG 0x0080 /* channel 0 ( for original pc ) */
+#define DEF_PORT_DMAC_DIAG 0x0080 /* extra/diagnostic port */
+#define DEF_PORT_DMAC_PAGE_CH1_ORG 0x0081 /* channel 1 ( for original pc ) */
+#define DEF_PORT_DMAC_PAGE_CH2 0x0081 /* channel 2 ( for at ) */
+#define DEF_PORT_DMAC_PAGE_CH2_ORG 0x0082 /* channel 2 ( for original pc ) */
+#define DEF_PORT_DMAC_PAGE_CH3 0x0082 /* channel 3 ( for at ) */
+#define DEF_PORT_DMAC_PAGE_CH3_ORG 0x0083 /* channel 3 ( for original pc ) */
+#define DEF_PORT_DMAC_PAGE_CH1 0x0083 /* channel 1 ( for at ) */
+#define DEF_PORT_DMAC_EXTRA1 0x0084 /* reserved */
+#define DEF_PORT_DMAC_EXTRA2 0x0085 /* reserved */
+#define DEF_PORT_DMAC_EXTRA3 0x0086 /* reserved */
+#define DEF_PORT_DMAC_PAGE_CH0 0x0087 /* channel 0 ( for at ) */
+#define DEF_PORT_DMAC_EXTRA4 0x0088 /* reserved */
+#define DEF_PORT_DMAC_PAGE_CH6 0x0089 /* channel 6 ( for at ) */
+#define DEF_PORT_DMAC_PAGE_CH7 0x008A /* channel 7 ( for at ) */
+#define DEF_PORT_DMAC_PAGE_CH5 0x008B /* channel 8 ( for at ) */
+#define DEF_PORT_DMAC_EXTRA5 0x008C /* reserved */
+#define DEF_PORT_DMAC_EXTRA6 0x008D /* reserved */
+#define DEF_PORT_DMAC_EXTRA7 0x008E /* reserved */
+#define DEF_PORT_DMAC_PAGE_CH4 0x008F /* channel 4 ( for at ) / to slave */
+
+#define DEF_DMAC_COMMAND_REG_MMT 0x01
+#define DEF_DMAC_COMMAND_REG_ADHE 0x02
+#define DEF_DMAC_COMMAND_REG_COND 0x04
+#define DEF_DMAC_COMMAND_REG_COMP 0x08
+#define DEF_DMAC_COMMAND_REG_PRIO 0x10
+#define DEF_DMAC_COMMAND_REG_EXTW 0x20
+#define DEF_DMAC_COMMAND_REG_DRQP 0x40
+#define DEF_DMAC_COMMAND_REG_DACKP 0x80
+
+/* channel select */
+#define DEF_DMAC_MODE_MASK_SEL 0x03
+#define DEF_DMAC_MODE_SEL_CH0 0x00
+#define DEF_DMAC_MODE_SEL_CH1 0x01
+#define DEF_DMAC_MODE_SEL_CH2 0x02
+#define DEF_DMAC_MODE_SEL_CH3 0x03
+
+/* transfer type */
+#define DEF_DMAC_MODE_MASK_TRA 0x0C
+#define DEF_DMAC_MODE_TRA_VERIFY 0x00
+#define DEF_DMAC_MODE_TRA_WRITE 0x04
+#define DEF_DMAC_MODE_TRA_READ 0x08
+#define DEF_DMAC_MODE_TRA_ILLEGAL 0x0C
+
+/* automatic initialization */
+#define DEF_DMAC_MODE_AUTO_DISABLE 0x00
+#define DEF_DMAC_MODE_AUTO_ENABLE 0x10
+
+/* address increment */
+#define DEF_DMAC_MODE_DOWN_DEC 0x00
+#define DEF_DMAC_MODE_DOWN_INC 0x20
+
+/* transfer mode */
+#define DEF_DMAC_MODE_MASK_MOD 0xC0
+#define DEF_DMAC_MODE_MOD_ONDEMAND 0x00
+#define DEF_DMAC_MODE_MOD_SINGLE 0x40
+#define DEF_DMAC_MODE_MOD_BLOCK 0x80
+#define DEF_DMAC_MODE_MOD_CASCADE 0xC0
+
+/*Prototype*/
+/*FDD Driver*/
+int fddReadSector( unsigned char drive,unsigned int lba,unsigned char *trasfered_address,unsigned int data_length );
+inline unsigned char convertLBA2Sector( unsigned int lba );
+inline unsigned char convertLBA2Head( unsigned int lba );
+inline unsigned char convertLBA2Track( unsigned int lba );
+int initFdc0( unsigned char drive );
+int writeFd0CmdSeek( E_FDC_CMDS_1ST_PRM drive,E_FDC_CMDS_1ST_PRM head,unsigned char cylinder);
+int readFdc0SenseInterruptStatus( unsigned char* st0, unsigned char* pcn );
+int writeFd0CmdRecalibrate( E_FDC_CMDS_1ST_PRM drive );
+inline void writeFdc0Dor( unsigned char dor );
+inline bool checkFdc0DriveBusy( E_FDD_DRIVE drive );
+int waitFdc0( void );
+int writeFd0Command( unsigned char command );
+int readFd0Status( unsigned char *data );
+int writeFd0CmdSpecify( unsigned char step_rate,unsigned char head_unload_time,unsigned char head_load_time,bool non_dma_mode);
+int writeFdc0CmdReadData( E_FDC_CMDS_1ST_PRM drive,E_FDC_CMDS_1ST_PRM head,unsigned char track,unsigned char sector );
+int fddReadSector(unsigned char drive,unsigned int lba,unsigned char *trasfered_address,unsigned int data_length );
+int dmaInitDMA( E_DMA_TRANSFER_TYPE type,E_DMA_CHANNEL channel,void *phy_adr,unsigned int length );
+/*DMA Drivers*/
+int dmaSetAddress( E_DMA_CHANNEL channel, unsigned short address );
+int dmaSetCounter( E_DMA_CHANNEL channel, unsigned short count );
+int dmaSetPageAddress( E_DMA_CHANNEL channel, unsigned char page );
+int dmaSetModeReg( E_DMA_CHANNEL channel, unsigned char mode );
+inline int dmaSetReadTransferMode( E_DMA_CHANNEL channel );
+inline void dmaMaskChannel( E_DMA_CHANNEL channel );
+inline void dmaUnmaskChannel( E_DMA_CHANNEL channel );
+int dmaResetFlipFlop( E_DMA_CLASS class );
+int dmaResetAllMask( E_DMA_CLASS class );
+int dmaClearMaster( E_DMA_CLASS class );
+
+
+#endif
--- /dev/null
+/*
+*Device Driver for Kernel
+*(C) 2014 VOSystems.
+*/
+
+#ifndef _DEVICE_H_VANE_
+#define _DEVICE_H_VANE_
+
+#include<type.h>
+
+/*FDD Driver*/
+
+typedef enum
+{
+ E_FDD_DRIVE0 = 0x00000000,
+ E_FDD_DRIVE1 = 0x00000001,
+ E_FDD_DRIVE2 = 0x00000002,
+ E_FDD_DRIVE3 = 0x00000003
+} E_FDD_DRIVE;
+
+
+#define E_FDD_DRIVE0 0x00000000
+#define E_FDD_DRIVE1 0x00000001
+#define E_FDD_DRIVE2 0x00000002
+#define E_FDD_DRIVE3 0x00000003
+
+#define DEF_FDD_OK 0
+#define DEF_FDD_ERROR (-1)
+#define DEF_FDD_RETRY_COUNT 500
+
+#define DEF_FDD_WRITE_CMD_RETRY 500
+#define DEF_FDD_READ_DATA_RETRY 500
+
+#define DEF_FDC_NUM_STATUS 300
+
+typedef enum
+{
+ FDC_CMD_READ_TRACK = 0x02,
+ FDC_CMD_SPECIFY = 0x03,
+ FDC_CMD_SENSE_DRIVE_STATUS = 0x04,
+ FDC_CMD_WRITE_DATA = 0x05,
+ FDC_CMD_READ_DATA = 0x06,
+ FDC_CMD_RECALIBRATE = 0x07,
+ FDC_CMD_SENSE_INTERRUPT_STATUS = 0x08,
+ FDC_CMD_WRITE_DELETED_DATA = 0x09,
+ FDC_CMD_READ_ID = 0x0A,
+ FDC_CMD_READ_DELETED_DATA = 0x0C,
+ FDC_CMD_FORMAT_TRACK = 0x0D,
+ FDC_CMD_DUMPREG = 0x0E,
+ FDC_CMD_SEEK = 0x0F,
+ FDC_CMD_VERSION = 0x10,
+ FDC_CMD_SCAN_EQUAL = 0x11,
+ FDC_CMD_PERPENDICULAR_MODE = 0x12,
+ FDC_CMD_CONFIGURE = 0x13,
+ FDC_CMD_LOCK = 0x14,
+ FDC_CMD_VERIFY = 0x16,
+ FDC_CMD_SCAN_LOW_OR_EQUAL = 0x19,
+ FDC_CMD_SCAN_HIGH_OR_EQUAL = 0x1D,
+ FDC_CMD_RELATIVE_SEEK = 0x8F
+} E_FDC_CMDS;
+
+typedef enum
+{
+ FDC_CMD_EXT_SK = 0x20,
+ FDC_CMD_EXT_MF = 0x40,
+ FDC_CMD_EXT_MT = 0x80
+} E_FDC_CMDS_EXT;
+
+typedef enum
+{
+ FDC_CMD_1ST_PRM_DRIVE0 = 0x00,
+ FDC_CMD_1ST_PRM_DRIVE1 = 0x01,
+ FDC_CMD_1ST_PRM_DRIVE2 = 0x02,
+ FDC_CMD_1ST_PRM_DRIVE3 = 0x03,
+ FDC_CMD_1ST_PRM_HEAD0 = 0x00,
+ FDC_CMD_1ST_PRM_HEAD1 = 0x04
+} E_FDC_CMDS_1ST_PRM;
+
+typedef enum
+{
+ FDC_CMD_GAP3_SIZE_3_5 = 27,
+ FDC_CMD_GAP3_SIZE_5_25 = 32,
+ FDC_CMD_GAP3_SIZE_STD = 42
+} E_FDC_CMDS_GP3_SIZE;
+
+typedef enum
+{
+ FDC_CMD_SECTOR_SIZE_128 = 0,
+ FDC_CMD_SECTOR_SIZE_256 = 1,
+ FDC_CMD_SECTOR_SIZE_512 = 2,
+ FDC_CMD_SECTOR_SIZE_1024 = 3,
+ FDC_CMD_SECTOR_SIZE_2048 = 4,
+ FDC_CMD_SECTOR_SIZE_4096 = 5,
+ FDC_CMD_SECTOR_SIZE_8192 = 6,
+ FDC_CMD_SECTOR_SIZE_16384 = 7
+} E_FDC_CMDS_SECTOR_SIZE;
+
+#define DEF_FDC_CMD_SPECIFY_MASK_SRT ( 0x0F << 4 )
+#define DEF_FDC_CMD_SPECIFY_MASK_HUT ( 0x0F << 0 )
+#define DEF_FDC_CMD_SPECIFY_MASK_HLT ( 0x7F << 1 )
+#define DEF_FDC_CMD_SPECIFY_NDM 0x01
+
+#define DEF_FDC_CMDS_PRM_DTL 0xFF
+
+#define DEF_FDD_SECTORS_PER_TRACK 18
+
+#define DEF_FDD_CALIBRATE_RETRY 10
+
+#define DEF_FDC_ST0_IC 0xC0
+
+#define DEF_FDD_SEEK_RETRY 10
+
+#define DEF_FDD_STEP_RATE_500K_03 0xD /* 3msec */
+#define DEF_FDD_HEAD_UNLOAD_TIME_500K_032 0x2 /* 32mese */
+#define DEF_FDD_HEAD_LOAD_TIME_500K_032 0x10 /* 32msec */
+
+#define DEF_FDC_CCR_DRATE_500KBPS 0x00 /* 500Kbps */
+#define DEF_FDC_CCR_DRATE_300KBPS 0x01 /* 300Kbps */
+#define DEF_FDC_CCR_DRATE_250KBPS 0x02 /* 250Kbps */
+#define DEF_FDC_CCR_DRATE_1MBPS 0x03 /* 1Mbps */
+
+#define DEF_FDD_SECTORS_PER_TRACK 18
+#define DEF_FDD_NUM_HEADS 2
+
+#define DEF_PORT_FDC1_SRA 0x0370 /* status register A */
+#define DEF_PORT_FDC1_SRB 0x0371 /* status register B */
+#define DEF_PORT_FDC1_DOR 0x0372 /* Digital output register */
+#define DEF_PORT_FDC1_TAPE 0x0373 /* tapa drive register */
+#define DEF_PORT_FDC1_MSR 0x0374 /* main status register */
+#define DEF_PORT_FDC1_DRS 0x0374 /* data rate select register */
+#define DEF_PORT_FDC1_STS 0x0375 /* status register 0,1,2,3( ST0,1,2,3 ) */
+#define DEF_PORT_FDC1_DATA 0x0375 /* data( status ) register */
+#define DEF_PORT_FDC1_CMD 0x0375 /* command register */
+#define DEF_PORT_FDC1_RESERVED 0x0376 /* reserved */
+#define DEF_PORT_FDC1_DIR 0x0377 /* digital input register */
+#define DEF_PORT_FDC1_CCR 0x0377 /* configuration control register */
+
+/*Description :Floppy Disc Controller( 1st )*/
+#define DEF_PORT_FDC0_SRA 0x03F0 /* status register A */
+#define DEF_PORT_FDC0_SRB 0x03F1 /* status register B */
+#define DEF_PORT_FDC0_DOR 0x03F2 /* Digital output register */
+#define DEF_PORT_FDC0_TAPE 0x03F3 /* tapa drive register */
+#define DEF_PORT_FDC0_MSR 0x03F4 /* main status register */
+#define DEF_PORT_FDC0_DRS 0x03F4 /* data rate select register */
+#define DEF_PORT_FDC0_STS 0x03F5 /* status register 0,1,2,3( ST0,1,2,3 ) */
+#define DEF_PORT_FDC0_DATA 0x03F5 /* data( status ) register */
+#define DEF_PORT_FDC0_CMD 0x03F5 /* command register */
+#define DEF_PORT_FDC0_RESERVED 0x03F6 /* reserved */
+#define DEF_PORT_FDC0_DIR 0x03F7 /* digital input register */
+#define DEF_PORT_FDC0_CCR 0x03F7 /* configuration control register */
+
+#define DEF_FDC_DOR_DRIVE0 0x00 /* b00000000 */
+#define DEF_FDC_DOR_DRIVE1 0x01 /* b00000001 */
+#define DEF_FDC_DOR_DRIVE2 0x02 /* b00000010 */
+#define DEF_FDC_DOR_DRIVE3 0x03 /* b00000011 */
+
+#define DEF_FDC_DOR_ENABLE 0x04 /* b00000100 */
+
+#define DEF_FDC_DOR_DMA 0x08 /* b00001000 */
+#define DEF_FDC_DOR_MOTOR0 0x10 /* b00010000 */
+#define DEF_FDC_DOR_MOTOR1 0x20 /* b00100000 */
+#define DEF_FDC_DOR_MOTOR2 0x40 /* b01000000 */
+#define DEF_FDC_DOR_MOTOR3 0x80 /* b10000000 */
+
+#define DEF_FDC_DOR_RESET 0x00
+
+#define DEF_FDC_MSR_DRIVE0_BUSY 0x01 /* b00000001 */
+#define DEF_FDC_MSR_DRIVE1_BUSY 0x02 /* b00000010 */
+#define DEF_FDC_MSR_DRIVE2_BUSY 0x04 /* b00000100 */
+#define DEF_FDC_MSR_DRIVE3_BUSY 0x08 /* b00001000 */
+#define DEF_FDC_MSR_MASK_DRIVE 0x0F /* b00001111 */
+
+#define DEF_FDC_MSR_COMMAND_BUSY 0x10 /* b00010000 */
+#define DEF_FDC_MSR_NON_DMA 0x20 /* b00100000 */
+#define DEF_FDC_MSR_DIO 0x40 /* b01000000 */
+#define DEF_FDC_MSR_RQM 0x80 /* b10000000 */
+
+
+
+/*DMA Driver*/
+#define DEF_DMA_OK 0
+#define DEF_DMA_ERROR (-1)
+
+typedef enum
+{
+ E_DMA_CHANNEL0 = 0,
+ E_DMA_CHANNEL1 = 1,
+ E_DMA_CHANNEL2 = 2,
+ E_DMA_CHANNEL3 = 3,
+ E_DMA_CHANNEL4 = 4,
+ E_DMA_CHANNEL5 = 5,
+ E_DMA_CHANNEL6 = 6,
+ E_DMA_CHANNEL7 = 7
+}E_DMA_CHANNEL;
+
+typedef enum
+{
+ E_DMA_TRANSFER_TYPE_WRITE=0,
+ E_DMA_TRANSFER_TYPE_READ=1
+}E_DMA_TRANSFER_TYPE;
+
+typedef enum
+{
+ E_DMA_CLASS_MASTER = 0x00,
+ E_DMA_CLASS_SLAVE = 0x01
+}E_DMA_CLASS;
+
+#define DEF_DMAC_CLR_DATA 0xFF
+#define DEF_DMAC_ADDRESS 0xffffffcf
+
+/*DMAC0 Ports( Slave )*/
+#define DEF_PORT_DMAC0_STATUS 0x0008 /* status register */
+#define DEF_PORT_DMAC0_COMMAND 0x0008 /* command register */
+#define DEF_PORT_DMAC0_REQUEST 0x0009 /* request register */
+#define DEF_PORT_DMAC0_SINGLE_MASK 0x000A /* single mask register */
+#define DEF_PORT_DMAC0_MODE 0x000B /* mode register */
+#define DEF_PORT_DMAC0_CLEAR_BP 0x000C /* clear byte pointer register */
+#define DEF_PORT_DMAC0_TEMPORARY 0x000D /* temporary register */
+#define DEF_PORT_DMAC0_MASTER_CLEAR 0x000D /* master clear register */
+#define DEF_PORT_DMAC0_MASK_RESET 0x000E /* mask reset register */
+#define DEF_PORT_DMAC0_ALL_MASK 0x000F /* all mask register */
+
+/* DMAC1 Ports( Master ) */
+#define DEF_PORT_DMAC1_STATUS 0x00D0 /* status register */
+#define DEF_PORT_DMAC1_COMMAND 0x00D0 /* command register */
+#define DEF_PORT_DMAC1_REQUEST 0x00D2 /* request register */
+#define DEF_PORT_DMAC1_SINGLE_MASK 0x00D4 /* single mask register */
+#define DEF_PORT_DMAC1_MODE 0x00D6 /* mode Register */
+#define DEF_PORT_DMAC1_CLEAR_BP 0x00D8 /* clear byte pointer register */
+#define DEF_PORT_DMAC1_TEMPORARY 0x00DA /* temporary Register */
+#define DEF_PORT_DMAC1_MASTER_CLEAR 0x00DA /* master clear Register */
+#define DEF_PORT_DMAC1_MASK_RESET 0x00DC /* mask reset Register */
+#define DEF_PORT_DMAC1_ALL_MASK 0x00DE /* all mask Register */
+
+/* DMAC0 Ports( Slave ) */
+#define DEF_PORT_DMAC0_CH0_ADDRESS 0x0000 /* Channel 0 base address register */
+#define DEF_PORT_DMAC0_CH0_COUNTER 0x0001 /* Channel 0 base count register */
+#define DEF_PORT_DMAC0_CH1_ADDRESS 0x0002 /* Channel 1 base address register */
+#define DEF_PORT_DMAC0_CH1_COUNTER 0x0003 /* Channel 1 base count register */
+#define DEF_PORT_DMAC0_CH2_ADDRESS 0x0004 /* Channel 2 base address register */
+#define DEF_PORT_DMAC0_CH2_COUNTER 0x0005 /* Channel 2 base count register */
+#define DEF_PORT_DMAC0_CH3_ADDRESS 0x0006 /* Channel 3 base address register */
+#define DEF_PORT_DMAC0_CH3_COUNTER 0x0007 /* Channel 3 base count register */
+
+/* DMAC1 Ports( Master ) */
+#define DEF_PORT_DMAC1_CH4_ADDRESS 0x00C0 /* Channel 4 base address register */
+#define DEF_PORT_DMAC1_CH4_COUNTER 0x00C2 /* Channel 4 base count register */
+#define DEF_PORT_DMAC1_CH5_ADDRESS 0x00C4 /* Channel 5 base address register */
+#define DEF_PORT_DMAC1_CH5_COUNTER 0x00C6 /* Channel 5 base count register */
+#define DEF_PORT_DMAC1_CH6_ADDRESS 0x00C8 /* Channel 6 base address register */
+#define DEF_PORT_DMAC1_CH6_COUNTER 0x00CA /* Channel 6 base count register */
+#define DEF_PORT_DMAC1_CH7_ADDRESS 0x00CC /* Channel 7 base address register */
+#define DEF_PORT_DMAC1_CH7_COUNTER 0x00CE /* Channel 7 base count register */
+
+
+#define DEF_PORT_DMAC_PAGE_CH0_ORG 0x0080 /* channel 0 ( for original pc ) */
+#define DEF_PORT_DMAC_DIAG 0x0080 /* extra/diagnostic port */
+#define DEF_PORT_DMAC_PAGE_CH1_ORG 0x0081 /* channel 1 ( for original pc ) */
+#define DEF_PORT_DMAC_PAGE_CH2 0x0081 /* channel 2 ( for at ) */
+#define DEF_PORT_DMAC_PAGE_CH2_ORG 0x0082 /* channel 2 ( for original pc ) */
+#define DEF_PORT_DMAC_PAGE_CH3 0x0082 /* channel 3 ( for at ) */
+#define DEF_PORT_DMAC_PAGE_CH3_ORG 0x0083 /* channel 3 ( for original pc ) */
+#define DEF_PORT_DMAC_PAGE_CH1 0x0083 /* channel 1 ( for at ) */
+#define DEF_PORT_DMAC_EXTRA1 0x0084 /* reserved */
+#define DEF_PORT_DMAC_EXTRA2 0x0085 /* reserved */
+#define DEF_PORT_DMAC_EXTRA3 0x0086 /* reserved */
+#define DEF_PORT_DMAC_PAGE_CH0 0x0087 /* channel 0 ( for at ) */
+#define DEF_PORT_DMAC_EXTRA4 0x0088 /* reserved */
+#define DEF_PORT_DMAC_PAGE_CH6 0x0089 /* channel 6 ( for at ) */
+#define DEF_PORT_DMAC_PAGE_CH7 0x008A /* channel 7 ( for at ) */
+#define DEF_PORT_DMAC_PAGE_CH5 0x008B /* channel 8 ( for at ) */
+#define DEF_PORT_DMAC_EXTRA5 0x008C /* reserved */
+#define DEF_PORT_DMAC_EXTRA6 0x008D /* reserved */
+#define DEF_PORT_DMAC_EXTRA7 0x008E /* reserved */
+#define DEF_PORT_DMAC_PAGE_CH4 0x008F /* channel 4 ( for at ) / to slave */
+
+#define DEF_DMAC_COMMAND_REG_MMT 0x01
+#define DEF_DMAC_COMMAND_REG_ADHE 0x02
+#define DEF_DMAC_COMMAND_REG_COND 0x04
+#define DEF_DMAC_COMMAND_REG_COMP 0x08
+#define DEF_DMAC_COMMAND_REG_PRIO 0x10
+#define DEF_DMAC_COMMAND_REG_EXTW 0x20
+#define DEF_DMAC_COMMAND_REG_DRQP 0x40
+#define DEF_DMAC_COMMAND_REG_DACKP 0x80
+
+/* channel select */
+#define DEF_DMAC_MODE_MASK_SEL 0x03
+#define DEF_DMAC_MODE_SEL_CH0 0x00
+#define DEF_DMAC_MODE_SEL_CH1 0x01
+#define DEF_DMAC_MODE_SEL_CH2 0x02
+#define DEF_DMAC_MODE_SEL_CH3 0x03
+
+/* transfer type */
+#define DEF_DMAC_MODE_MASK_TRA 0x0C
+#define DEF_DMAC_MODE_TRA_VERIFY 0x00
+#define DEF_DMAC_MODE_TRA_WRITE 0x04
+#define DEF_DMAC_MODE_TRA_READ 0x08
+#define DEF_DMAC_MODE_TRA_ILLEGAL 0x0C
+
+/* automatic initialization */
+#define DEF_DMAC_MODE_AUTO_DISABLE 0x00
+#define DEF_DMAC_MODE_AUTO_ENABLE 0x10
+
+/* address increment */
+#define DEF_DMAC_MODE_DOWN_DEC 0x00
+#define DEF_DMAC_MODE_DOWN_INC 0x20
+
+/* transfer mode */
+#define DEF_DMAC_MODE_MASK_MOD 0xC0
+#define DEF_DMAC_MODE_MOD_ONDEMAND 0x00
+#define DEF_DMAC_MODE_MOD_SINGLE 0x40
+#define DEF_DMAC_MODE_MOD_BLOCK 0x80
+#define DEF_DMAC_MODE_MOD_CASCADE 0xC0
+
+/*Prototype*/
+/*FDD Driver*/
+int fddReadSector( unsigned char drive,unsigned int lba,unsigned char *trasfered_address,unsigned int data_length );
+inline unsigned char convertLBA2Sector( unsigned int lba );
+inline unsigned char convertLBA2Head( unsigned int lba );
+inline unsigned char convertLBA2Track( unsigned int lba );
+int initFdc0( unsigned char drive );
+int writeFd0CmdSeek( E_FDC_CMDS_1ST_PRM drive,E_FDC_CMDS_1ST_PRM head,unsigned char cylinder);
+int readFdc0SenseInterruptStatus( unsigned char* st0, unsigned char* pcn );
+int writeFd0CmdRecalibrate( E_FDC_CMDS_1ST_PRM drive );
+inline void writeFdc0Dor( unsigned char dor );
+inline bool checkFdc0DriveBusy( E_FDD_DRIVE drive );
+int waitFdc0( void );
+int writeFd0Command( unsigned char command );
+int readFd0Status( unsigned char *data );
+int writeFd0CmdSpecify( unsigned char step_rate,unsigned char head_unload_time,unsigned char head_load_time,bool non_dma_mode);
+int writeFdc0CmdReadData( E_FDC_CMDS_1ST_PRM drive,E_FDC_CMDS_1ST_PRM head,unsigned char track,unsigned char sector );
+int fddReadSector(unsigned char drive,unsigned int lba,unsigned char *trasfered_address,unsigned int data_length );
+int dmaInitDMA( E_DMA_TRANSFER_TYPE type,E_DMA_CHANNEL channel,void *phy_adr,unsigned int length );
+/*DMA Drivers*/
+int dmaSetAddress( E_DMA_CHANNEL channel, unsigned short address );
+int dmaSetCounter( E_DMA_CHANNEL channel, unsigned short count );
+int dmaSetPageAddress( E_DMA_CHANNEL channel, unsigned char page );
+int dmaSetModeReg( E_DMA_CHANNEL channel, unsigned char mode );
+inline int dmaSetReadTransferMode( E_DMA_CHANNEL channel );
+inline int dmaSetReadTransferMode( E_DMA_CHANNEL channel );
+inline void dmaMaskChannel( E_DMA_CHANNEL channel );
+inline void dmaUnmaskChannel( E_DMA_CHANNEL channel );
+int dmaResetFlipFlop( E_DMA_CLASS class );
+int dmaResetAllMask( E_DMA_CLASS class );
+int dmaClearMaster( E_DMA_CLASS class );
+
+
+#endif
#define EXCEPT 0x00000001 //Exception
#define ABNRML 0x00000002 //Abnormal
#define BADTCH 0x00000003 //Bad memory address touch
+#define DISUSE 0xffffffff //Dis use
/*Run Level Label*/
#define KERNEL 0x00000000 //Kernel Mode (Ling 0)
int status;
int run_level;
int request;
- int parent_id
+ int parent_id;
}task_status;
typedef struct
{
+ task_status* tasks[TASK_INFO_TOTAL];
+ int task_time;
+ int task_num;
+}task_manager;
+
+typedef struct
+{
unsigned int backlink;
unsigned int esp0; // Stack pointer. ( Privilage level 0 )
unsigned int ss0; // Stack segment. ( Privilage level 0 )
unsigned int get_cur_task_num();
//void switch_task( unsigned int task );
-void init_task();
-void set_task( unsigned int task, void (*f)(), unsigned char* esp );
-unsigned int get_cur_task_num();
-
void task_a();
void task_b();
#define TASK_INFO_ADDR 0x260000 // Address to the head of TaskInfo structure.
#define TASK_INFO_TOTAL 10 // Number of tasks.
+/*Status Label*/
+#define NORMAL 0x00000000 //Normal
+#define EXCEPT 0x00000001 //Exception
+#define ABNRML 0x00000002 //Abnormal
+#define BADTCH 0x00000003 //Bad memory address touch
+#define DISUSE 0xffffffff //Dis use
+
+/*Run Level Label*/
+#define KERNEL 0x00000000 //Kernel Mode (Ling 0)
+#define DRIVER 0x00000001 //Driver Mode
+#define SHELLS 0x00000002 //Shell Servers Mode
+#define APPPAR 0x00000003 //Parent Application
+#define APPCHI 0x00000004 //Child Application
+#define APPGAB 0x00000005 //Gabage Request Application
+
+/*Request Label*/
+#define NONERQ 0x00000000
+#define SYSCAL 0x00000001
+#define GABAGE 0x00000002
+
typedef struct
{
+ int id;
int status;
int run_level;
int request;
+ int parent_id;
}task_status;
typedef struct
{
+ task_status* tasks[TASK_INFO_TOTAL];
+ int task_time;
+ int task_num;
+}task_manager;
+
+typedef struct
+{
unsigned int backlink;
unsigned int esp0; // Stack pointer. ( Privilage level 0 )
unsigned int ss0; // Stack segment. ( Privilage level 0 )
typedef long long quad_t;
typedef unsigned long long u_quad_t;
-#endif
+#define size_bit(type) (sizeof(type)*4)
+
+typedef int bool;
+#define true 1
+#define false 0
+
+#define CHAR_BIT 8
+#define CHAR_MAX 127
+#define CHAR_MIN -128
+#define INT_MAX 32767
+#define INT_MIN -32768
+#define LONG_MAX 2147483647
+#define LONG_MIN -2147483648
+#define SCHAR_MAX 127
+#define SCHAR_MIN -128
+#define SHRT_MAX 32767
+#define SHRT_MIN -32768
+#define UCHAR_MAX 255
+#define UINT_MAX 4294967295
+#define ULONG_MAX 4294967295
+#define USHRT_MAX 65535
+
+#endif/*Include Guard*/
typedef unsigned long size_t;
typedef long long quad_t;
-typedef unsigned long long uquad_t;
+typedef unsigned long long u_quad_t;
-#endif
+#define size_bit(type) (sizeof(type)*4)
+
+typedef int bool;
+#define true 1
+#define false 0
+
+#define CHAR_BIT 8
+#define CHAR_MAX 127
+#define CHAR_MIN -128
+#define INT_MAX 32767
+#define INT_MIN -32768
+#define LONG_MAX 2147483647
+#define LONG_MIN -2147483648
+#define SCHAR_MAX 127
+#define SCHAR_MIN -128
+#define SHRT_MAX 32767
+#define SHRT_MIN -32768
+#define UCHAR_MAX 255
+#define UINT_MAX 4294967295
+#define ULONG_MAX 4294967295
+#define USHRT_MAX 65535
+
+char の最大値: 127
+ char の最小値: -128
+ int の最大値: 32767
+ int の最小値: -32768
+ long の最大値: 2147483647
+ long の最小値: -2147483648
+ signed char の最大値: 127
+ shigned char の最小値: -128
+ short の最大値: 32767
+ short の最小値: -32768
+ unsigned char の最大値: 255
+ unsigned int の最大値: 65535
+ unsigned long の最大値: 4294967295
+ unsigned short の最大値: 65535
+
+#endif/*Include Guard*/
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