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astoria-d [Sun, 20 Oct 2013 01:21:28 +0000 (10:21 +0900)]
sdram control clean up
astoria-d [Sat, 19 Oct 2013 11:54:59 +0000 (20:54 +0900)]
sdram integration ok
astoria-d [Sat, 19 Oct 2013 04:53:34 +0000 (13:53 +0900)]
sdram controller integration
astoria-d [Mon, 14 Oct 2013 01:31:36 +0000 (10:31 +0900)]
vga work...
astoria-d [Sat, 12 Oct 2013 10:04:35 +0000 (19:04 +0900)]
vga output working...
astoria-d [Sat, 12 Oct 2013 00:49:08 +0000 (09:49 +0900)]
test vga output working...
astoria-d [Sat, 12 Oct 2013 00:32:17 +0000 (09:32 +0900)]
Merge branch 'master' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga
astoria-d [Sat, 12 Oct 2013 00:31:57 +0000 (09:31 +0900)]
vga output ok!!
astoria-d [Tue, 8 Oct 2013 02:32:12 +0000 (11:32 +0900)]
test update
astoria-d [Tue, 8 Oct 2013 02:22:25 +0000 (11:22 +0900)]
jmp (ind) test added.
astoria-d [Tue, 8 Oct 2013 02:10:33 +0000 (11:10 +0900)]
a5 instruction test added.
astoria-d [Mon, 7 Oct 2013 08:27:46 +0000 (17:27 +0900)]
a4 instructions regression test added.
astoria-d [Mon, 7 Oct 2013 06:56:25 +0000 (15:56 +0900)]
a2, a3 instruction test added.
astoria-d [Mon, 7 Oct 2013 03:10:08 +0000 (12:10 +0900)]
tsx instruction supported.
astoria-d [Sun, 6 Oct 2013 04:49:41 +0000 (13:49 +0900)]
vga woring...
astoria-d [Sat, 5 Oct 2013 08:26:36 +0000 (17:26 +0900)]
vga test proj added. still working...
astoria-d [Sat, 5 Oct 2013 01:24:05 +0000 (10:24 +0900)]
ppu render debug pin added but cyclone ii runs short of output pin!
astoria-d [Sat, 5 Oct 2013 01:02:49 +0000 (10:02 +0900)]
oam data read was ok???
previsous changed didn't need. restored.
astoria-d [Sat, 5 Oct 2013 00:36:55 +0000 (09:36 +0900)]
ppu integration and bug fix
astoria-d [Fri, 4 Oct 2013 08:47:42 +0000 (17:47 +0900)]
regression test single byte inst test ok
astoria-d [Fri, 4 Oct 2013 07:32:36 +0000 (16:32 +0900)]
- ppu render ram write timing updated.
- code clean up
astoria-d [Fri, 4 Oct 2013 06:39:30 +0000 (15:39 +0900)]
regression test update
astoria-d [Fri, 4 Oct 2013 05:48:04 +0000 (14:48 +0900)]
regression test update
astoria-d [Fri, 4 Oct 2013 03:30:12 +0000 (12:30 +0900)]
regression test updated.
astoria-d [Wed, 2 Oct 2013 03:09:44 +0000 (12:09 +0900)]
regression test update
astoria-d [Tue, 1 Oct 2013 09:05:27 +0000 (18:05 +0900)]
regression test updated (print func ok.)
astoria-d [Tue, 1 Oct 2013 08:48:02 +0000 (17:48 +0900)]
regression test working...
astoria-d [Tue, 1 Oct 2013 01:40:44 +0000 (10:40 +0900)]
regression test created
astoria-d [Mon, 30 Sep 2013 09:55:20 +0000 (18:55 +0900)]
ppu integrated. still working...
astoria-d [Mon, 30 Sep 2013 07:10:24 +0000 (16:10 +0900)]
- input data latch invalid data latch bug fixed.
- debug pins added.
astoria-d [Mon, 30 Sep 2013 06:23:40 +0000 (15:23 +0900)]
modified input data latch to stop using latch, but use dff.
astoria-d [Mon, 30 Sep 2013 06:17:15 +0000 (15:17 +0900)]
segment size fixed
astoria-d [Mon, 30 Sep 2013 05:25:25 +0000 (14:25 +0900)]
Merge branch 'master' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga
astoria-d [Mon, 30 Sep 2013 05:24:31 +0000 (14:24 +0900)]
de1 env test case added.
astoria-d [Mon, 30 Sep 2013 04:44:11 +0000 (13:44 +0900)]
segment size modified
astoria-d [Mon, 30 Sep 2013 04:11:03 +0000 (13:11 +0900)]
merge updates
astoria-d [Mon, 30 Sep 2013 01:40:01 +0000 (10:40 +0900)]
- name tbl 0/1 write clock synchronized
astoria-d [Mon, 30 Sep 2013 01:21:10 +0000 (10:21 +0900)]
added .gitignore file
astoria-d [Sun, 29 Sep 2013 10:14:40 +0000 (19:14 +0900)]
async param test
astoria-d [Fri, 27 Sep 2013 01:53:40 +0000 (10:53 +0900)]
ram timing ctrl modified.
astoria-d [Fri, 27 Sep 2013 01:37:00 +0000 (10:37 +0900)]
- merge decoder updates
- testbench update
astoria-d [Thu, 26 Sep 2013 07:29:26 +0000 (16:29 +0900)]
test timing aligned.
astoria-d [Thu, 26 Sep 2013 06:45:49 +0000 (15:45 +0900)]
- decoder clean up
- clock synchronized ram integrated
- abs addr mode bug working...
astoria-d [Thu, 26 Sep 2013 05:46:53 +0000 (14:46 +0900)]
merge updates
astoria-d [Thu, 26 Sep 2013 02:27:53 +0000 (11:27 +0900)]
ram write timing changed
astoria-d [Thu, 26 Sep 2013 02:16:53 +0000 (11:16 +0900)]
- module structure reorganizezd
- chrrom to be clock synchronized
- ram to be clock synchronized (still working...)
astoria-d [Wed, 25 Sep 2013 10:21:42 +0000 (19:21 +0900)]
clean up
astoria-d [Wed, 25 Sep 2013 10:20:10 +0000 (19:20 +0900)]
status register bug fixed!!
astoria-d [Wed, 25 Sep 2013 09:34:23 +0000 (18:34 +0900)]
status reg test ok
astoria-d [Wed, 25 Sep 2013 05:31:13 +0000 (14:31 +0900)]
- ghdl env merge
- dual dff debug port added
- status debug working
astoria-d [Wed, 25 Sep 2013 04:32:27 +0000 (13:32 +0900)]
code merge
astoria-d [Wed, 25 Sep 2013 01:55:10 +0000 (10:55 +0900)]
wrong segment number fixed
astoria-d [Wed, 25 Sep 2013 01:50:42 +0000 (10:50 +0900)]
4k segment remapping added to test app.
astoria-d [Wed, 25 Sep 2013 01:27:57 +0000 (10:27 +0900)]
clean up
astoria-d [Wed, 25 Sep 2013 01:24:55 +0000 (10:24 +0900)]
code clean up
astoria-d [Wed, 25 Sep 2013 01:02:20 +0000 (10:02 +0900)]
module structure re-organized
astoria-d [Tue, 24 Sep 2013 10:33:32 +0000 (19:33 +0900)]
update
astoria-d [Tue, 24 Sep 2013 10:27:26 +0000 (19:27 +0900)]
update
astoria-d [Tue, 24 Sep 2013 09:39:48 +0000 (18:39 +0900)]
gate simulation debugging.
astoria-d [Tue, 24 Sep 2013 07:17:31 +0000 (16:17 +0900)]
update
astoria-d [Tue, 24 Sep 2013 06:44:17 +0000 (15:44 +0900)]
merge updates
astoria-d [Tue, 24 Sep 2013 06:33:11 +0000 (15:33 +0900)]
clean up. gate level simulation working!!!
astoria-d [Tue, 24 Sep 2013 05:57:21 +0000 (14:57 +0900)]
env clean up
astoria-d [Tue, 24 Sep 2013 05:47:00 +0000 (14:47 +0900)]
sync with ghdl env
astoria-d [Tue, 24 Sep 2013 05:10:31 +0000 (14:10 +0900)]
modelsim project added
astoria-d [Tue, 24 Sep 2013 03:07:00 +0000 (12:07 +0900)]
- base clock aligned with the DE1 board clock 50 MHz
- cpu/ppu/mem/vga clock adjusted due to above change
astoria-d [Tue, 24 Sep 2013 02:11:31 +0000 (11:11 +0900)]
- rom/ram instance moved to root module.
- address decoder shrinked and focused on chip select only.
astoria-d [Tue, 24 Sep 2013 01:34:24 +0000 (10:34 +0900)]
rom to be clk syncronized
astoria-d [Tue, 24 Sep 2013 00:36:43 +0000 (09:36 +0900)]
Merge branch 'master' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga
astoria-d [Mon, 23 Sep 2013 10:44:28 +0000 (19:44 +0900)]
update
astoria-d [Mon, 23 Sep 2013 10:43:47 +0000 (19:43 +0900)]
4k rom working
astoria-d [Mon, 23 Sep 2013 10:15:56 +0000 (19:15 +0900)]
test 4k rom ok
astoria-d [Mon, 23 Sep 2013 09:48:49 +0000 (18:48 +0900)]
update
astoria-d [Mon, 23 Sep 2013 09:45:34 +0000 (18:45 +0900)]
tool update
astoria-d [Mon, 23 Sep 2013 05:50:42 +0000 (14:50 +0900)]
quartus ii test env
astoria-d [Mon, 23 Sep 2013 05:02:31 +0000 (14:02 +0900)]
clean up
astoria-d [Mon, 23 Sep 2013 04:50:14 +0000 (13:50 +0900)]
rom/ram working
astoria-d [Sun, 22 Sep 2013 08:47:35 +0000 (17:47 +0900)]
quartus 13.0sp1 updated
astoria-d [Sun, 22 Sep 2013 03:15:19 +0000 (12:15 +0900)]
gate level simulator working...
astoria-d [Sat, 21 Sep 2013 11:05:16 +0000 (20:05 +0900)]
clean up
astoria-d [Sat, 21 Sep 2013 11:04:47 +0000 (20:04 +0900)]
gate level simulation evn set up ok
astoria-d [Sat, 21 Sep 2013 03:52:22 +0000 (12:52 +0900)]
modelsim env set up files clean up.
astoria-d [Sat, 21 Sep 2013 03:41:50 +0000 (12:41 +0900)]
update
astoria-d [Sat, 21 Sep 2013 03:40:36 +0000 (12:40 +0900)]
update
astoria-d [Sat, 21 Sep 2013 03:39:13 +0000 (12:39 +0900)]
gate level simulation update
astoria-d [Sat, 21 Sep 2013 03:28:50 +0000 (12:28 +0900)]
modelsim env setup ok!!
now rtl level simulation goes ok.
astoria-d [Fri, 20 Sep 2013 11:30:55 +0000 (20:30 +0900)]
still test environment set up
astoria-d [Fri, 20 Sep 2013 08:36:12 +0000 (17:36 +0900)]
- env update.
- model sim setting update.
astoria-d [Fri, 20 Sep 2013 06:22:26 +0000 (15:22 +0900)]
Merge branch 'master' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga
astoria-d [Thu, 19 Sep 2013 11:19:12 +0000 (20:19 +0900)]
- main testbench updated to simulate the real de1 environment
astoria-d [Thu, 19 Sep 2013 09:39:16 +0000 (18:39 +0900)]
component latch renamed due to quartus component name conflict.
astoria-d [Thu, 19 Sep 2013 09:17:15 +0000 (18:17 +0900)]
clock driver fixed
astoria-d [Thu, 19 Sep 2013 08:51:59 +0000 (17:51 +0900)]
- clock driver updated
- Makefile build order changed.
astoria-d [Thu, 19 Sep 2013 08:06:16 +0000 (17:06 +0900)]
clock divider modified to align with de1 board.
astoria-d [Thu, 19 Sep 2013 02:35:54 +0000 (11:35 +0900)]
unified common routines, code clean up etc.
astoria-d [Wed, 18 Sep 2013 09:25:25 +0000 (18:25 +0900)]
scroll attribute bug fix
astoria-d [Wed, 18 Sep 2013 09:01:16 +0000 (18:01 +0900)]
comment/todo added.
astoria-d [Wed, 18 Sep 2013 08:57:28 +0000 (17:57 +0900)]
scroll and attribute bug fix
astoria-d [Wed, 18 Sep 2013 08:04:36 +0000 (17:04 +0900)]
ppu scroll x display bug fix
astoria-d [Wed, 18 Sep 2013 06:25:07 +0000 (15:25 +0900)]
- scroll working...
- test case updated.
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