i915.c

   1 /*
   2  * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <errno.h>
  10 #include <string.h>
  11 #include <stdio.h>
  12 #include <sys/mman.h>
  13 #include <xf86drm.h>
  14 #include <i915_drm.h>
  15
  16 #include "drv_priv.h"
  17 #include "helpers.h"
  18 #include "util.h"
  19
  20 struct i915_device
  21 {
  22         int gen;
  23 };
  24
  25
  26 static int get_gen(int device_id)
  27 {
  28         const uint16_t gen3_ids[] = {0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  29                                      0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011};
  30         unsigned i;
  31         for(i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  32                 if (gen3_ids[i] == device_id)
  33                         return 3;
  34
  35         return 4;
  36 }
  37
  38 static int i915_init(struct driver *drv)
  39 {
  40         struct i915_device *i915_drv;
  41         drm_i915_getparam_t get_param;
  42         int device_id;
  43         int ret;
  44
  45         i915_drv = (struct i915_device*)malloc(sizeof(*i915_drv));
  46         if (!i915_drv)
  47                 return -1;
  48
  49         memset(&get_param, 0, sizeof(get_param));
  50         get_param.param = I915_PARAM_CHIPSET_ID;
  51         get_param.value = &device_id;
  52         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
  53         if (ret) {
  54                 fprintf(stderr, "drv: DRM_IOCTL_I915_GETPARAM failed\n");
  55                 free(i915_drv);
  56                 return -1;
  57         }
  58
  59         i915_drv->gen = get_gen(device_id);
  60
  61         drv->priv = i915_drv;
  62
  63         return 0;
  64 }
  65
  66 static void i915_close(struct driver *drv)
  67 {
  68         free(drv->priv);
  69         drv->priv = NULL;
  70 }
  71
  72 static void i915_align_dimensions(struct driver *drv, uint32_t tiling_mode,
  73                                   uint32_t *width, uint32_t *height, int bpp)
  74 {
  75         struct i915_device *i915_drv = (struct i915_device *)drv->priv;
  76         uint32_t width_alignment = 4, height_alignment = 4;
  77
  78         switch(tiling_mode) {
  79                 default:
  80                 case I915_TILING_NONE:
  81                         width_alignment = 64 / bpp;
  82                         break;
  83
  84                 case I915_TILING_X:
  85                         width_alignment = 512 / bpp;
  86                         height_alignment = 8;
  87                         break;
  88
  89                 case I915_TILING_Y:
  90                         if (i915_drv->gen == 3) {
  91                                 width_alignment = 512 / bpp;
  92                                 height_alignment = 8;
  93                         } else  {
  94                                 width_alignment = 128 / bpp;
  95                                 height_alignment = 32;
  96                         }
  97                         break;
  98         }
  99
 100         if (i915_drv->gen > 3) {
 101                 *width = ALIGN(*width, width_alignment);
 102                 *height = ALIGN(*height, height_alignment);
 103         } else {
 104                 uint32_t w;
 105                 for (w = width_alignment; w < *width;  w <<= 1)
 106                         ;
 107                 *width = w;
 108                 *height = ALIGN(*height, height_alignment);
 109         }
 110 }
 111
 112 static int i915_verify_dimensions(struct driver *drv, uint32_t stride,
 113                                   uint32_t height)
 114 {
 115         struct i915_device *i915_drv = (struct i915_device *)drv->priv;
 116         if (i915_drv->gen <= 3 && stride > 8192)
 117                 return 0;
 118
 119         return 1;
 120 }
 121
 122 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height,
 123                           uint32_t format, uint32_t flags)
 124 {
 125         struct driver *drv = bo->drv;
 126         int bpp = drv_stride_from_format(format, 1);
 127         struct drm_i915_gem_create gem_create;
 128         struct drm_i915_gem_set_tiling gem_set_tiling;
 129         uint32_t tiling_mode = I915_TILING_NONE;
 130         size_t size;
 131         int ret;
 132
 133         if (flags & (DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR |
 134                      DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN))
 135                 tiling_mode = I915_TILING_NONE;
 136         else if (flags & DRV_BO_USE_SCANOUT)
 137                 tiling_mode = I915_TILING_X;
 138         else if (flags & (DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 139                           DRV_BO_USE_HW_RENDER | DRV_BO_USE_SW_READ_RARELY |
 140                           DRV_BO_USE_HW_2D | DRV_BO_USE_SW_WRITE_RARELY))
 141                 tiling_mode = I915_TILING_Y;
 142
 143         i915_align_dimensions(drv, tiling_mode, &width, &height, bpp);
 144
 145         bo->strides[0] = width * bpp;
 146
 147         if (!i915_verify_dimensions(drv, bo->strides[0], height))
 148                 return EINVAL;
 149
 150         memset(&gem_create, 0, sizeof(gem_create));
 151         size = width * height * bpp;
 152         gem_create.size = size;
 153
 154         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 155         if (ret) {
 156                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed "
 157                                 "(size=%zu)\n", size);
 158                 return ret;
 159         }
 160         bo->handles[0].u32 = gem_create.handle;
 161         bo->sizes[0] = size;
 162         bo->offsets[0] = 0;
 163
 164         memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
 165         do {
 166                 gem_set_tiling.handle = bo->handles[0].u32;
 167                 gem_set_tiling.tiling_mode = tiling_mode;
 168                 gem_set_tiling.stride = bo->strides[0];
 169                 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GEM_SET_TILING,
 170                                &gem_set_tiling);
 171         } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
 172
 173         if (ret == -1) {
 174                 struct drm_gem_close gem_close;
 175                 gem_close.handle = bo->handles[0].u32;
 176                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed "
 177                                 "errno=%x (handle=%x, tiling=%x, stride=%x)\n",
 178                                 errno,
 179                                 gem_set_tiling.handle,
 180                                 gem_set_tiling.tiling_mode,
 181                                 gem_set_tiling.stride);
 182                 drmIoctl(drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 183                 return -errno;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static void *i915_bo_map(struct bo *bo)
 190 {
 191         int ret;
 192         struct drm_i915_gem_mmap_gtt gem_map;
 193
 194         memset(&gem_map, 0, sizeof(gem_map));
 195         gem_map.handle = bo->handles[0].u32;
 196
 197         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 198         if (ret) {
 199                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 200                 return MAP_FAILED;
 201         }
 202
 203         return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED,
 204                     bo->drv->fd, gem_map.offset);
 205 }
 206
 207 drv_format_t i915_resolve_format(drv_format_t format)
 208 {
 209         switch (format) {
 210                 case DRV_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 211                         /*HACK: See b/28671744 */
 212                         return DRV_FORMAT_XBGR8888;
 213                 case DRV_FORMAT_FLEX_YCbCr_420_888:
 214                         /*
 215                          * TODO(gurchetansingh) Implement YV12 with no tiling
 216                          * on Intel. See b/29335168
 217                          */
 218                         return DRV_FORMAT_YVU420;
 219                 default:
 220                         return format;
 221         }
 222 }
 223
 224 const struct backend backend_i915 =
 225 {
 226         .name = "i915",
 227         .init = i915_init,
 228         .close = i915_close,
 229         .bo_create = i915_bo_create,
 230         .bo_destroy = drv_gem_bo_destroy,
 231         .bo_map = i915_bo_map,
 232         .resolve_format = i915_resolve_format,
 233         .format_list = {
 234                 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 235                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 236                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 237                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 238                 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 239                                       DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
 240                                       DRV_BO_USE_SW_WRITE_OFTEN},
 241                 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 242                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 243                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 244                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 245                 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 246                                       DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
 247                                       DRV_BO_USE_SW_WRITE_OFTEN},
 248                 {DRV_FORMAT_XBGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 249                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 250                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 251                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 252                 {DRV_FORMAT_ABGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 253                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 254                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 255                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 256                 {DRV_FORMAT_XRGB1555, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 257                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 258                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 259                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 260                 {DRV_FORMAT_ARGB1555, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 261                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 262                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 263                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 264                 {DRV_FORMAT_RGB565,   DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 265                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 266                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 267                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 268                 {DRV_FORMAT_UYVY,     DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 269                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 270                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 271                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 272                 {DRV_FORMAT_UYVY,     DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 273                                       DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
 274                                       DRV_BO_USE_SW_WRITE_OFTEN},
 275                 {DRV_FORMAT_YUYV,     DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 276                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
 277                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
 278                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
 279                 {DRV_FORMAT_YUYV,     DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 280                                       DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
 281                                       DRV_BO_USE_SW_WRITE_OFTEN},
 282                 {DRV_FORMAT_R8,       DRV_BO_USE_SCANOUT | DRV_BO_USE_LINEAR |
 283                                       DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
 284                 {DRV_FORMAT_GR88,     DRV_BO_USE_SCANOUT | DRV_BO_USE_LINEAR |
 285                                       DRV_BO_USE_SW_READ_OFTEN | DRV_BO_USE_SW_WRITE_OFTEN},
 286         }
 287 };
 288
 289 #endif