1 ; MSP430FR5x6x.inc : MSP430FR5xxx and MSP430FR6xxx declarations (MSP430FR57xx excluded)
4 .IF DEVICE = "MSP430FR5948"
6 ; ----------------------------------------------------------------------
7 ; MSP430FR5948 Peripheral File Map
8 ; ----------------------------------------------------------------------
9 SFR_SFR .set 0100h ; Special function
10 PMM_SFR .set 0120h ; PMM
11 FRAM_SFR .set 0140h ; FRAM control
13 WDT_A_SFR .set 015Ch ; Watchdog
14 CS_SFR .set 0160h ; Clock System
15 SYS_SFR .set 0180h ; SYS
16 REF_SFR .set 01B0h ; REF
17 PA_SFR .set 0200h ; PORT1/2
18 PB_SFR .set 0220h ; PORT3/4
19 PJ_SFR .set 0320h ; PORTJ
24 CTIO0_SFR .set 0430h ; Capacitive Touch IO
26 CTIO1_SFR .set 0470h ; Capacitive Touch IO
29 DMA_CTRL_SFR .set 0500h
30 DMA_CHN0_SFR .set 0510h
31 DMA_CHN1_SFR .set 0520h
32 DMA_CHN2_SFR .set 0530h
33 MPU_SFR .set 05A0h ; memory protect unit
34 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
35 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
36 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
37 ADC12_B_SFR .set 0800h
41 ; ----------------------------------------------
42 ; MSP430FR5948 MEMORY MAP
43 ; ----------------------------------------------
44 ; 0000-0FFF = peripherals (4 KB)
45 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
46 ; 1800-187F = FRAM info D (128 B)
47 ; 1880-18FF = FRAM info C (128 B)
48 ; 1900-197F = FRAM info B (128 B)
49 ; 1980-19FF = FRAM info A (128 B)
50 ; 1A00-1AFF = FRAM TLV device descriptor info (256 B)
51 ; 1B00-1BFF = unused (256 B)
52 ; 1C00-23FF = RAM (2KB)
53 ; 23FF-43FF = unused (8kB)
54 ; 4400-FF7F = FRAM code memory (FRAM) (MSP430FR59x8/9)
55 ; 8000-FF7F = FRAM code memory (FRAM) (MSP430FR59x7/8/9)
56 ; FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
58 ; ----------------------------------------------
59 PAGESIZE .equ 512 ; MPU unit
60 ; ----------------------------------------------
62 ; ----------------------------------------------
64 ; ----------------------------------------------
65 ; FRAM ; INFO B, A, TLV
66 ; ----------------------------------------------
68 INFODSTART .equ 01800h
70 INFOCSTART .equ 01880h
72 INFOBSTART .equ 01900h
74 INFOASTART .equ 01980h
76 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
78 ; ----------------------------------------------
80 ; ----------------------------------------------
83 ; ----------------------------------------------
85 ; ----------------------------------------------
86 PROGRAMSTART .equ 04400h ; Code space start
87 FRAMEND .equ 0FFFFh ; 48 k FRAM
88 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
89 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
90 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
91 BSL_SIG1 .equ 0FF84h ;
92 BSL_SIG2 .equ 0FF86h ;
93 JTAG_PASSWORD .equ 0FF88h ; 256 bits max
94 IPE_SIG_VALID .equ 0FF88h ; one word
95 IPE_STR_PTR_SRC .equ 0FF8Ah ; one word
96 INTVECT .equ 0FFCCh ; FFCC-FFFF
97 BSL_PASSWORD .equ 0FFE0h ; 256 bits
98 ; ----------------------------------------------
100 ;;Start of JTAG and BSL signatures
101 ; .word 0FFFFh ; JTAG signature 1
102 ; .word 0FFFFh ; JTAG signature 2
103 ; .word 0FFFFh ; BSL signature 1, 5555h to disable BSL
104 ; .word 0FFFFh ; BSL signature 2
106 ; ----------------------------------------------
107 ; Interrupt Vectors and signatures - MSP430FR5948
108 ; ----------------------------------------------
110 ; .org INTVECT ; FFCC-FFFF 25 vectors + reset
111 ; .word reset ; $FFCC - AES
112 ; .word reset ; $FFCE - RTC_B
113 ; .word reset ; $FFD0 - I/O Port 4
114 ; .word reset ; $FFD2 - I/O Port 3
115 ; .word reset ; $FFD4 - TB2_1
116 ; .word reset ; $FFD6 - TB2_0
117 ; .word reset ; $FFD8 - I/O Port P2
118 ; .word reset ; $FFDA - TB1_1
119 ; .word reset ; $FFDC - TB1_0
120 ; .word reset ; $FFDE - I/O Port P1
123 ;; .org BSL_PASSWORD ;Start of BSL PASSWORD
124 ; .word reset ; $FFE0 - TA1_1
125 ; .word reset ; $FFE2 - TA1_0
126 ; .word reset ; $FFE4 - DMA
127 ; .word reset ; $FFE6 - eUSCI_A1
128 ; .word reset ; $FFE8 - TA0_1
129 ; .word reset ; $FFEA - TA0_0
130 ; .word reset ; $FFEC - ADC12_B
131 ; .word reset ; $FFEE - eUSCI_B0
132 ; .word reset ; $FFF0 - eUSCI_A0
133 ; .word reset ; $FFF2 - Watchdog
134 ; .word reset ; $FFF4 - TB0_1
135 ; .word reset ; $FFF6 - TB0_0
136 ; .word reset ; $FFF8 - COMP_D
137 ; .word reset ; $FFFA - userNMI
138 ; .word reset ; $FFFC - sysNMI
139 ; .word reset ; $FFFE - reset
142 ; ----------------------------------------------------------------------
143 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
144 ; ----------------------------------------------------------------------
145 RTCCTL01 .equ RTC_B_SFR + 00h
146 RTCCTL0 .equ RTC_B_SFR + 00h
147 RTCCTL1 .equ RTC_B_SFR + 01h
148 RTCCTL23 .equ RTC_B_SFR + 02h
149 RTCPS0CTL .equ RTC_B_SFR + 08h
150 RTCPS1CTL .equ RTC_B_SFR + 0Ah
151 RTCPS .equ RTC_B_SFR + 0Ch
152 RTCIV .equ RTC_B_SFR + 0Eh
153 RTCSEC .equ RTC_B_SFR + 10h
154 RTCMIN .equ RTC_B_SFR + 11h
155 RTCHOUR .equ RTC_B_SFR + 12h
156 RTCDOW .equ RTC_B_SFR + 13h
157 RTCDAY .equ RTC_B_SFR + 14h
158 RTCMON .equ RTC_B_SFR + 15h
159 RTCYEAR .equ RTC_B_SFR + 16h
165 .ENDIF ; MSP430FR5948
169 .IF DEVICE = "MSP430FR5969"
171 ; ----------------------------------------------------------------------
172 ; MSP430FR5969 Peripheral File Map
173 ; ----------------------------------------------------------------------
174 SFR_SFR .set 0100h ; Special function
175 PMM_SFR .set 0120h ; PMM
176 FRAM_SFR .set 0140h ; FRAM control
178 WDT_A_SFR .set 015Ch ; Watchdog
179 CS_SFR .set 0160h ; Clock System
180 SYS_SFR .set 0180h ; SYS
181 REF_SFR .set 01B0h ; REF
182 PA_SFR .set 0200h ; PORT1/2
183 PB_SFR .set 0220h ; PORT3/4
184 PJ_SFR .set 0320h ; PORTJ
189 CTIO0_SFR .set 0430h ; Capacitive Touch IO
191 CTIO1_SFR .set 0470h ; Capacitive Touch IO
194 DMA_CTRL_SFR .set 0500h
195 DMA_CHN0_SFR .set 0510h
196 DMA_CHN1_SFR .set 0520h
197 DMA_CHN2_SFR .set 0530h
198 MPU_SFR .set 05A0h ; memory protect unit
199 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
200 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
201 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
202 ADC12_B_SFR .set 0800h
203 COMP_E_SFR .set 08C0h
206 ; ----------------------------------------------
207 ; MSP430FR5969 MEMORY MAP
208 ; ----------------------------------------------
209 ; 0000-0FFF = peripherals (4 KB)
210 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
211 ; 1800-187F = FRAM info D (128 B)
212 ; 1880-18FF = FRAM info C (128 B)
213 ; 1900-197F = FRAM info B (128 B)
214 ; 1980-19FF = FRAM info A (128 B)
215 ; 1A00-1AFF = FRAM TLV device descriptor info (256 B)
216 ; 1B00-1BFF = unused (256 B)
217 ; 1C00-23FF = RAM (2KB)
218 ; 23FF-43FF = unused (8kB)
219 ; 4400-FF7F = FRAM code memory (FRAM) (MSP430FR59x8/9)
220 ; 8000-FF7F = FRAM code memory (FRAM) (MSP430FR59x7/8/9)
221 ; FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
222 ; 10000-13FFF = FRAM (MSP430FR59x9)
224 ; ----------------------------------------------
225 PAGESIZE .equ 512 ; MPU unit
226 ; ----------------------------------------------
228 ; ----------------------------------------------
230 ; ----------------------------------------------
231 ; FRAM ; INFO B, A, TLV
232 ; ----------------------------------------------
233 INFOSTART .equ 01800h
234 INFODSTART .equ 01800h
236 INFOCSTART .equ 01880h
238 INFOBSTART .equ 01900h
240 INFOASTART .equ 01980h
242 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
244 ; ----------------------------------------------
246 ; ----------------------------------------------
249 ; ----------------------------------------------
251 ; ----------------------------------------------
252 PROGRAMSTART .equ 04400h ; Code space start
253 FRAMEND .equ 0FFFFh ; 48 k FRAM
254 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
255 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
256 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
257 BSL_SIG1 .equ 0FF84h ;
258 BSL_SIG2 .equ 0FF86h ;
259 JTAG_PASSWORD .equ 0FF88h ; 256 bits max
260 IPE_SIG_VALID .equ 0FF88h ; one word
261 IPE_STR_PTR_SRC .equ 0FF8Ah ; one word
262 INTVECT .equ 0FFCCh ; FFCC-FFFF
263 BSL_PASSWORD .equ 0FFE0h ; 256 bits
264 ; ----------------------------------------------
267 ;;Start of JTAG and BSL signatures
268 ; .word 0FFFFh ; JTAG signature 1
269 ; .word 0FFFFh ; JTAG signature 2
270 ; .word 0FFFFh ; BSL signature 1, 5555h to disable BSL
271 ; .word 0FFFFh ; BSL signature 2
273 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
275 ; .org INTVECT ; FFCC-FFFF 25 vectors + reset
276 ; .word reset ; $FFCC - AES
277 ; .word reset ; $FFCE - RTC_B
278 ; .word reset ; $FFD0 - I/O Port 4
279 ; .word reset ; $FFD2 - I/O Port 3
280 ; .word reset ; $FFD4 - TB2_1
281 ; .word reset ; $FFD6 - TB2_0
282 ; .word reset ; $FFD8 - I/O Port P2
283 ; .word reset ; $FFDA - TB1_1
284 ; .word reset ; $FFDC - TB1_0
285 ; .word reset ; $FFDE - I/O Port P1
288 ;; .org BSL_PASSWORD ;Start of BSL PASSWORD
289 ; .word reset ; $FFE0 - TA1_1
290 ; .word reset ; $FFE2 - TA1_0
291 ; .word reset ; $FFE4 - DMA
292 ; .word reset ; $FFE6 - eUSCI_A1
293 ; .word reset ; $FFE8 - TA0_1
294 ; .word reset ; $FFEA - TA0_0
295 ; .word reset ; $FFEC - ADC12_B
296 ; .word reset ; $FFEE - eUSCI_B0
297 ; .word reset ; $FFF0 - eUSCI_A0
298 ; .word reset ; $FFF2 - Watchdog
299 ; .word reset ; $FFF4 - TB0_1
300 ; .word reset ; $FFF6 - TB0_0
301 ; .word reset ; $FFF8 - COMP_D
302 ; .word reset ; $FFFA - userNMI
303 ; .word reset ; $FFFC - sysNMI
304 ; .word reset ; $FFFE - reset
306 ; ----------------------------------------------------------------------
307 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
308 ; ----------------------------------------------------------------------
309 RTCCTL01 .equ RTC_B_SFR + 00h
310 RTCCTL0 .equ RTC_B_SFR + 00h
311 RTCCTL1 .equ RTC_B_SFR + 01h
312 RTCCTL23 .equ RTC_B_SFR + 02h
313 RTCPS0CTL .equ RTC_B_SFR + 08h
314 RTCPS1CTL .equ RTC_B_SFR + 0Ah
315 RTCPS .equ RTC_B_SFR + 0Ch
316 RTCIV .equ RTC_B_SFR + 0Eh
317 RTCSEC .equ RTC_B_SFR + 10h
318 RTCMIN .equ RTC_B_SFR + 11h
319 RTCHOUR .equ RTC_B_SFR + 12h
320 RTCDOW .equ RTC_B_SFR + 13h
321 RTCDAY .equ RTC_B_SFR + 14h
322 RTCMON .equ RTC_B_SFR + 15h
323 RTCYEAR .equ RTC_B_SFR + 16h
328 .ENDIF ; MSP430FR5969
335 .IF DEVICE = "MSP430FR5994"
337 ; ----------------------------------------------------------------------
338 ; MSP430FR5994 Peripheral File Map
339 ; ----------------------------------------------------------------------
340 SFR_SFR .set 0100h ; Special function
341 PMM_SFR .set 0120h ; PMM
342 FRAM_SFR .set 0140h ; FRAM control
345 WDT_A_SFR .set 015Ch ; Watchdog
346 CS_SFR .set 0160h ; Clock System
347 SYS_SFR .set 0180h ; SYS
348 REF_SFR .set 01B0h ; REF
349 PA_SFR .set 0200h ; PORT1/2
350 PB_SFR .set 0220h ; PORT3/4
351 PC_SFR .set 0240h ; PORT3/4
352 PD_SFR .set 0260h ; PORT3/4
353 PJ_SFR .set 0320h ; PORTJ
358 CTIO0_SFR .set 0430h ; Capacitive Touch IO
360 CTIO1_SFR .set 0470h ; Capacitive Touch IO
363 DMA_CTRL_SFR .set 0500h
364 DMA_CHN0_SFR .set 0510h
365 DMA_CHN1_SFR .set 0520h
366 DMA_CHN2_SFR .set 0530h
367 DMA_CHN3_SFR .set 0540h
368 DMA_CHN4_SFR .set 0550h
369 DMA_CHN5_SFR .set 0560h
370 MPU_SFR .set 05A0h ; memory protect unit
371 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
372 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
373 eUSCI_A2_SFR .set 0600h ; eUSCI_A1
374 eUSCI_A3_SFR .set 0620h ; eUSCI_A1
375 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
376 eUSCI_B1_SFR .set 0680h ; eUSCI_B0
377 eUSCI_B2_SFR .set 06C0h ; eUSCI_B0
378 eUSCI_B3_SFR .set 0700h ; eUSCI_B0
380 ADC12_B_SFR .set 0800h
381 COMP_E_SFR .set 08C0h
386 ; ----------------------------------------------
387 ; MSP430FR5994 MEMORY MAP
388 ; ----------------------------------------------
389 ; 000A-001F = tiny RAM
390 ; 0020-0FFF = peripherals (4 KB)
391 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
392 ; 1800-187F = FRAM info D (128 B)
393 ; 1880-18FF = FRAM info C (128 B)
394 ; 1900-197F = FRAM info B (128 B)
395 ; 1980-19FF = FRAM info A (128 B)
396 ; 1A00-1AFF = FRAM TLV device descriptor info (256 B)
397 ; 1B00-1BFF = unused (256 B)
398 ; 1C00-2BFF = RAM (4KB)
399 ; 2C00-3BFF = sharedRAM (4kB)
400 ; 4400-FF7F = FRAM code memory (FRAM) (MSP430FR59x8/9)
401 ; 8000-FF7F = FRAM code memory (FRAM) (MSP430FR59x7/8/9)
402 ; FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
404 ; ----------------------------------------------
405 PAGESIZE .equ 512 ; MPU unit
406 ; ----------------------------------------------
408 ; ----------------------------------------------
410 ; ----------------------------------------------
411 ; FRAM ; INFO B, A, TLV
412 ; ----------------------------------------------
413 INFOSTART .equ 01800h
414 INFODSTART .equ 01800h
416 INFOCSTART .equ 01880h
418 INFOBSTART .equ 01900h
420 INFOASTART .equ 01980h
422 TLVSTART .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
424 ; ----------------------------------------------
426 ; ----------------------------------------------
431 SharedRAMSTART .equ 02C00h
432 SharedRAMEND .equ 03BFFh
433 ; ----------------------------------------------
435 ; ----------------------------------------------
436 PROGRAMSTART .equ 04000h ; Code space start
437 FRAMEND .equ 043FFFh ; 256 k FRAM
438 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
439 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
440 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
441 BSL_SIG1 .equ 0FF84h ;
442 BSL_SIG2 .equ 0FF86h ;
443 JTAG_PASSWORD .equ 0FF88h ; 256 bits max
444 IPE_SIG_VALID .equ 0FF88h ; one word
445 IPE_STR_PTR_SRC .equ 0FF8Ah ; one word
446 INTVECT .equ 0FFB4h ; FFB4-FFFF
447 BSL_PASSWORD .equ 0FFE0h ; 256 bits
448 ; ----------------------------------------------
450 ;;Start of JTAG and BSL signatures
451 ; .word 0FFFFh ; JTAG signature 1
452 ; .word 0FFFFh ; JTAG signature 2
453 ; .word 0FFFFh ; BSL signature 1, 5555h to disable BSL
454 ; .word 0FFFFh ; BSL signature 2
456 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
458 ; .org INTVECT ; FFB4-FFFF 37 vectors + reset
459 ; .word reset ; 0FFB4h - LEA_Vec
460 ; .word reset ; 0FFB6h - P8_Vec
461 ; .word reset ; 0FFB8h - P7_Vec
462 ; .word reset ; 0FFBAh - eUSCI_B3_Vec
463 ; .word reset ; 0FFBCh - eUSCI_B2_Vec
464 ; .word reset ; 0FFBEh - eUSCI_B1_Vec
465 ; .word reset ; 0FFC0h - eUSCI_A3_Vec
466 ; .word reset ; 0FFC2h - eUSCI_A2_Vec
467 ; .word reset ; 0FFC4h - P6_Vec
468 ; .word reset ; 0FFC6h - P5_Vec
469 ; .word reset ; 0FFC8h - TA4_x_Vec
470 ; .word reset ; 0FFCAh - TA4_0_Vec
471 ; .word reset ; 0FFCCh - AES_Vec
472 ; .word reset ; 0FFCEh - RTC_C_Vec
473 ; .word reset ; 0FFD0h - P4_Vec=
474 ; .word reset ; 0FFD2h - P3_Vec=
475 ; .word reset ; 0FFD4h - TA3_x_Vec
476 ; .word reset ; 0FFD6h - TA3_0_Vec
477 ; .word reset ; 0FFD8h - P2_Vec
478 ; .word reset ; 0FFDAh - TA2_x_Vec
479 ; .word reset ; 0FFDCh - TA2_0_Vec
480 ; .word reset ; 0FFDEh - P1_Vec=
481 ;; .org BSL_PASSWORD ;Start of BSL PASSWORD
482 ; .word reset ; 0FFE0h - TA1_x_Vec
483 ; .word reset ; 0FFE2h - TA1_0_Vec
484 ; .word reset ; 0FFE4h - DMA_Vec
485 ; .word reset ; 0FFE6h - eUSCI_A1_Vec
486 ; .word reset ; 0FFE8h - TA0_x_Vec
487 ; .word reset ; 0FFEAh - TA0_0_Vec
488 ; .word reset ; 0FFECh - ADC12_B_Vec
489 ; .word reset ; 0FFEEh - eUSCI_B0_Vec
490 ; .word reset ; 0FFF0h - eUSCI_A0_Vec
491 ; .word reset ; 0FFF2h - WDT_Vec
492 ; .word reset ; 0FFF4h - TB0_x_Vec
493 ; .word reset ; 0FFF6h - TB0_0_Vec
494 ; .word reset ; 0FFF8h - COMP_E_Vec
495 ; .word reset ; 0FFFAh - U_NMI_Vec
496 ; .word reset ; 0FFFCh - S_NMI_Vec
497 ; .word reset ; 0FFFEh - RST_Vec
500 ; ----------------------------------------------------------------------
501 ; POWER ON RESET AND INITIALIZATION : PORT5/6
502 ; ----------------------------------------------------------------------
504 PCIN .equ PC_SFR + 00h ; Port C Input
505 PCOUT .equ PC_SFR + 02h ; Port C Output
506 PCDIR .equ PC_SFR + 04h ; Port C Direction
507 PCREN .equ PC_SFR + 06h ; Port C Resistor Enable
508 PCSEL0 .equ PC_SFR + 0Ah ; Port C Selection 0
509 PCSEL1 .equ PC_SFR + 0Ch ; Port C Selection 1
510 PCSELC .equ PC_SFR + 16h ; Port C Complement Selection
511 PCIES .equ PC_SFR + 18h ; Port C Interrupt Edge Select
512 PCIE .equ PC_SFR + 1Ah ; Port C Interrupt Enable
513 PCIFG .equ PC_SFR + 1Ch ; Port C Interrupt Flag
515 P5IN .equ PC_SFR + 00h ; Port 5 Input
516 P5OUT .equ PC_SFR + 02h ; Port 5 Output
517 P5DIR .equ PC_SFR + 04h ; Port 5 Direction
518 P5REN .equ PC_SFR + 06h ; Port 5 Resistor Enable
519 P5SEL0 .equ PC_SFR + 0Ah ; Port 5 Selection 0
520 P5SEL1 .equ PC_SFR + 0Ch ; Port 5 Selection 1
521 P5IV .equ PC_SFR + 0Eh ; Port 5 Interrupt Vector word
522 P5SELC .set PC_SFR + 16h ; Port 5 Complement Selection
523 P5IES .equ PC_SFR + 18h ; Port 5 Interrupt Edge Select
524 P5IE .equ PC_SFR + 1Ah ; Port 5 Interrupt Enable
525 P5IFG .equ PC_SFR + 1Ch ; Port 5 Interrupt Flag
527 P6IN .equ PC_SFR + 01h ; Port 6 Input
528 P6OUT .equ PC_SFR + 03h ; Port 6 Output
529 P6DIR .equ PC_SFR + 05h ; Port 6 Direction
530 P6REN .equ PC_SFR + 07h ; Port 6 Resistor Enable
531 P6SEL0 .equ PC_SFR + 0Bh ; Port 6 Selection 0
532 P6SEL1 .equ PC_SFR + 0Dh ; Port 6 Selection 1
533 P6SELC .set PC_SFR + 17h ; Port 6 Complement Selection
534 P6IES .equ PC_SFR + 19h ; Port 6 Interrupt Edge Select
535 P6IE .equ PC_SFR + 1Bh ; Port 6 Interrupt Enable
536 P6IFG .equ PC_SFR + 1Dh ; Port 6 Interrupt Flag
537 P6IV .equ PC_SFR + 1Eh ; Port 6 Interrupt Vector word
539 ; ----------------------------------------------------------------------
540 ; POWER ON RESET AND INITIALIZATION : PORT7/8
541 ; ----------------------------------------------------------------------
543 PDIN .equ PD_SFR + 00h ; Port D Input
544 PDOUT .equ PD_SFR + 02h ; Port D Output
545 PDDIR .equ PD_SFR + 04h ; Port D Direction
546 PDREN .equ PD_SFR + 06h ; Port D Resistor Enable
547 PDSEL0 .equ PD_SFR + 0Ah ; Port D Selection 0
548 PDSEL1 .equ PD_SFR + 0Ch ; Port D Selection 1
549 PDSELC .equ PD_SFR + 16h ; Port D Complement Selection
550 PDIES .equ PD_SFR + 18h ; Port D Interrupt Edge Select
551 PDIE .equ PD_SFR + 1Ah ; Port D Interrupt Enable
552 PDIFG .equ PD_SFR + 1Ch ; Port D Interrupt Flag
554 P7IN .equ PD_SFR + 00h ; Port 7 Input
555 P7OUT .equ PD_SFR + 02h ; Port 7 Output
556 P7DIR .equ PD_SFR + 04h ; Port 7 Direction
557 P7REN .equ PD_SFR + 06h ; Port 7 Resistor Enable
558 P7SEL0 .equ PD_SFR + 0Ah ; Port 7 Selection 0
559 P7SEL1 .equ PD_SFR + 0Ch ; Port 7 Selection 1
560 P7IV .equ PD_SFR + 0Eh ; Port 7 Interrupt Vector word
561 P7SELC .set PD_SFR + 16h ; Port 7 Complement Selection
562 P7IES .equ PD_SFR + 18h ; Port 7 Interrupt Edge Select
563 P7IE .equ PD_SFR + 1Ah ; Port 7 Interrupt Enable
564 P7IFG .equ PD_SFR + 1Ch ; Port 7 Interrupt Flag
566 P8IN .equ PD_SFR + 01h ; Port 8 Input
567 P8OUT .equ PD_SFR + 03h ; Port 8 Output
568 P8DIR .equ PD_SFR + 05h ; Port 8 Direction
569 P8REN .equ PD_SFR + 07h ; Port 8 Resistor Enable
570 P8SEL0 .equ PD_SFR + 0Bh ; Port 8 Selection 0
571 P8SEL1 .equ PD_SFR + 0Dh ; Port 8 Selection 1
572 P8SELC .set PD_SFR + 16h ; Port 8 Complement Selection
573 P8IES .equ PD_SFR + 19h ; Port 8 Interrupt Edge Select
574 P8IE .equ PD_SFR + 1Bh ; Port 8 Interrupt Enable
575 P8IFG .equ PD_SFR + 1Dh ; Port 8 Interrupt Flag
576 P8IV .equ PD_SFR + 1Eh ; Port 8 Interrupt Vector word
578 ; ----------------------------------------------------------------------
579 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
580 ; ----------------------------------------------------------------------
581 RTCCTL0_L .set RTC_C_SFR + 00h
582 RTCCTL0_H .set RTC_C_SFR + 01h
583 RTCCTL1 .set RTC_C_SFR + 02h
584 RTCCTL3 .set RTC_C_SFR + 03h
585 RTCOCAL .set RTC_C_SFR + 04h
586 RTCTCMP .set RTC_C_SFR + 06h
587 RTCPS0CTL .set RTC_C_SFR + 08h
588 RTCPS1CTL .set RTC_C_SFR + 0Ah
589 RTCPS .set RTC_C_SFR + 0Ch ; = RT1PS:RT0PS
590 RTCIV .set RTC_C_SFR + 0Eh
591 RTCSEC .set RTC_C_SFR + 10h
592 RTCCNT1 .set RTC_C_SFR + 10h
593 RTCMIN .set RTC_C_SFR + 11h
594 RTCCNT2 .set RTC_C_SFR + 11h
595 RTCHOUR .set RTC_C_SFR + 12h
596 RTCCNT3 .set RTC_C_SFR + 12h
597 RTCDOW .set RTC_C_SFR + 13h
598 RTCCNT4 .set RTC_C_SFR + 13h
599 RTCDAY .set RTC_C_SFR + 14h
600 RTCMON .set RTC_C_SFR + 15h
601 RTCYEAR .set RTC_C_SFR + 16h
606 .ENDIF ; MSP_EXP430FR5994
611 .IF DEVICE = "MSP430FR6989"
613 ; ----------------------------------------------------------------------
614 ; EXP430FR6989 Peripheral File Map
615 ; ----------------------------------------------------------------------
616 SFR_SFR .set 0100h ; Special function
617 PMM_SFR .set 0120h ; PMM
618 FRAM_SFR .set 0140h ; FRAM control
620 RAMC_SFR .set 0158h ; RAM controller
621 WDT_A_SFR .set 015Ch ; Watchdog
622 CS_SFR .set 0160h ; Clock System
623 SYS_SFR .set 0180h ; SYS
624 REF_SFR .set 01B0h ; shared REF
625 PA_SFR .set 0200h ; PORT1/2
626 PB_SFR .set 0220h ; PORT3/4
627 PC_SFR .set 0240h ; PORT5/6
628 PD_SFR .set 0260h ; PORT7/8
629 PE_SFR .set 0280h ; PORT9/10
630 PJ_SFR .set 0320h ; PORTJ
635 CTIO0_SFR .set 0430h ; Capacitive Touch IO
637 CTIO1_SFR .set 0470h ; Capacitive Touch IO
640 DMA_CTRL_SFR .set 0500h
641 DMA_CHN0_SFR .set 0510h
642 DMA_CHN1_SFR .set 0520h
643 DMA_CHN2_SFR .set 0530h
644 MPU_SFR .set 05A0h ; memory protect unit
645 eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
646 eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
647 eUSCI_B0_SFR .set 0640h ; eUSCI_B0
648 eUSCI_B1_SFR .set 0680h ; eUSCI_B1
649 ADC12_B_SFR .set 0800h
650 COMP_E_SFR .set 08C0h
655 ESI_RAM .set 0E00h ; 128 bytes
657 ; ----------------------------------------------
658 ; MSP430FR6989 MEMORY MAP
659 ; ----------------------------------------------
661 ; 0020-0FFF = peripherals (4 KB)
662 ; 1000-17FF = BootStrap Loader BSL0..3 (ROM 4x512 B)
663 ; 1800-187F = info D (FRAM 128 B)
664 ; 1880-18FF = info C (FRAM 128 B)
665 ; 1900-197F = info B (FRAM 128 B)
666 ; 1980-19FF = info A (FRAM 128 B)
667 ; 1A00-1AFF = TLV device descriptor info (FRAM 256 B)
668 ; 1B00-1BFF = Boot memory (ROM 256 B)
669 ; 1C00-23FF = RAM (2 KB)
671 ; 4400-FF7F = code memory (FRAM 47999 B)
672 ; FF80-FFFF = interrupt vectors (FRAM 128 B)
674 ; ----------------------------------------------
675 PAGESIZE .equ 512 ; MPU unit
676 ; ----------------------------------------------
677 ; FRAM ; INFO{D,C,B,A},TLV
678 ; ----------------------------------------------
679 INFOSTART .equ 01800h
680 INFODSTART .equ 01800h
682 INFOCSTART .equ 01880h
684 INFOBSTART .equ 01900h
686 INFOASTART .equ 01980h
688 TLVSTAT .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
690 ; ----------------------------------------------
692 ; ----------------------------------------------
695 ; ----------------------------------------------
697 ; ----------------------------------------------
698 PROGRAMSTART .equ 04400h ; Code space start
699 SIGNATURES .equ 0FF80h ; JTAG, BSL and IP Encapsulation signatures 1 and 2
700 JTAG_SIG1 .equ 0FF80h ; if 0, enable JTAG/SBW
701 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
702 BSL_SIG1 .equ 0FF84h ;
703 BSL_SIG2 .equ 0FF86h ;
704 JTAG_PASSWORD .equ 0FF86h ; up to 0FFC5h : 256 bits
705 INTVECT .equ 0FFC6h ; FFC6-FFFF
706 BSL_PASSWORD .equ 0FFE0h ; up to 0FFFFh : 256 bits
707 ; ----------------------------------------------
708 ; ----------------------------------------------
709 ; Interrupt Vectors and signatures - MSP430FR6989
710 ; ----------------------------------------------
713 ;;Start of JTAG and BSL signatures
714 ; .word 0FFFFh ; JTAG signature 1
715 ; .word 0FFFFh ; JTAG signature 2
716 ; .word 0FFFFh ; BSL signature 1, 5555h to disable BSL
717 ; .word 0FFFFh ; BSL signature 2
719 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
721 ; .org INTVECT ; FFC6-FFFF 28 vectors + reset
722 ; .word reset ; $FFC6 - AES
723 ; .word reset ; $FFC8 - RTC_C
724 ; .word reset ; $FFCA - LCD_C
725 ; .word reset ; $FFCC - I/O Port 4
726 ; .word reset ; $FFCE - I/O Port 3
727 ; .word reset ; $FFD0 - TA3_x
728 ; .word reset ; $FFD2 - TA3_0
729 ; .word reset ; $FFD4 - I/O Port P2
730 ; .word reset ; $FFD6 - TA2_x
731 ; .word reset ; $FFD8 - TA2_0
732 ; .word reset ; $FFDA - I/O Port P1
733 ; .word reset ; $FFDC - TA1_x
734 ; .word reset ; $FFDE - TA1_0
735 ;; .org BSL_PASSWORD ;Start of BSL PASSWORD
736 ; .word reset ; $FFE0 - DMA
737 ; .word reset ; $FFE2 - eUSCI_B1
738 ; .word reset ; $FFE4 - eUSCI_A1
739 ; .word reset ; $FFE6 - TA0_x
740 ; .word reset ; $FFE8 - TA0_0
741 ; .word reset ; $FFEA - ADC12_B
742 ; .word reset ; $FFEC - eUSCI_B0
743 ; .word reset ; $FFEE - eUSCI_A0
744 ; .word reset ; $FFF0 - Extended Scan IF
745 ; .word reset ; $FFF2 - Watchdog
746 ; .word reset ; $FFF4 - TB0_x
747 ; .word reset ; $FFF6 - TB0_0
748 ; .word reset ; $FFF8 - COMP_E
749 ; .word reset ; $FFFA - userNMI
750 ; .word reset ; $FFFC - sysNMI
751 ; .word reset ; $FFFE - reset
753 ; ----------------------------------------------------------------------
754 ; POWER ON RESET AND INITIALIZATION : PORT5/6
755 ; ----------------------------------------------------------------------
757 PCIN .set PC_SFR + 00h ; Port C Input
758 PCOUT .set PC_SFR + 02h ; Port C Output 1/0 or pullup/pulldown resistor
759 PCDIR .set PC_SFR + 04h ; Port C Direction
760 PCREN .set PC_SFR + 06h ; Port C Resistor Enable
761 PCSEL0 .set PC_SFR + 0Ah ; Port C Selection 0
762 PCSEL1 .set PC_SFR + 0Ch ; Port C Selection 1
763 PCSELC .set PC_SFR + 16h ; Port C Complement Selection
765 P5IN .set PC_SFR + 00h ; Port 5 Input */
766 P5OUT .set PC_SFR + 02h ; Port 5 Output
767 P5DIR .set PC_SFR + 04h ; Port 5 Direction
768 P5REN .set PC_SFR + 06h ; Port 5 Resistor Enable
769 P5SEL0 .set PC_SFR + 0Ah ; Port 5 Selection 0
770 P5SEL1 .set PC_SFR + 0Ch ; Port 5 Selection 1
771 P5SELC .set PC_SFR + 16h ; Port 5 Complement Selection
773 P6IN .set PC_SFR + 01h ; Port 6 Input */
774 P6OUT .set PC_SFR + 03h ; Port 6 Output
775 P6DIR .set PC_SFR + 05h ; Port 6 Direction
776 P6REN .set PC_SFR + 07h ; Port 6 Resistor Enable
777 P6SEL0 .set PC_SFR + 0Bh ; Port 6 Selection 0
778 P6SEL1 .set PC_SFR + 0Dh ; Port 6 Selection 1
779 P6SELC .set PC_SFR + 17h ; Port 6 Complement Selection
781 ; ----------------------------------------------------------------------
782 ; POWER ON RESET AND INITIALIZATION : PORT7/8
783 ; ----------------------------------------------------------------------
785 PDIN .set PD_SFR + 00h ; Port D Input
786 PDOUT .set PD_SFR + 02h ; Port D Output 1/0 or pullup/pulldown resistor
787 PDDIR .set PD_SFR + 04h ; Port D Direction
788 PDREN .set PD_SFR + 06h ; Port D Resistor Enable
789 PDSEL0 .set PD_SFR + 0Ah ; Port D Selection 0
790 PDSEL1 .set PD_SFR + 0Ch ; Port D Selection 1
791 PDSELC .set PD_SFR + 16h ; Port D Complement Selection
793 P7IN .set PD_SFR + 00h ; Port 7 Input */
794 P7OUT .set PD_SFR + 02h ; Port 7 Output
795 P7DIR .set PD_SFR + 04h ; Port 7 Direction
796 P7REN .set PD_SFR + 06h ; Port 7 Resistor Enable
797 P7SEL0 .set PD_SFR + 0Ah ; Port 7 Selection 0
798 P7SEL1 .set PD_SFR + 0Ch ; Port 7 Selection 1
799 P7SELC .set PD_SFR + 16h ; Port 7 Complement Selection
801 P8IN .set PD_SFR + 01h ; Port 8 Input */
802 P8OUT .set PD_SFR + 03h ; Port 8 Output
803 P8DIR .set PD_SFR + 05h ; Port 8 Direction
804 P8REN .set PD_SFR + 07h ; Port 8 Resistor Enable
805 P8SEL0 .set PD_SFR + 0Bh ; Port 8 Selection 0
806 P8SEL1 .set PD_SFR + 0Dh ; Port 8 Selection 1
807 P8SELC .set PD_SFR + 17h ; Port 8 Complement Selection
809 ; ----------------------------------------------------------------------
810 ; POWER ON RESET AND INITIALIZATION : PORT9/10
811 ; ----------------------------------------------------------------------
813 PEIN .set PE_SFR + 00h ; Port E Input
814 PEOUT .set PE_SFR + 02h ; Port E Output 1/0 or pullup/pulldown resistor
815 PEDIR .set PE_SFR + 04h ; Port E Direction
816 PEREN .set PE_SFR + 06h ; Port E Resistor Enable
817 PESEL0 .set PE_SFR + 0Ah ; Port E Selection 0
818 PESEL1 .set PE_SFR + 0Ch ; Port E Selection 1
819 PESELC .set PE_SFR + 16h ; Port E Complement Selection
821 P9IN .set PE_SFR + 00h ; Port 9 Input */
822 P9OUT .set PE_SFR + 02h ; Port 9 Output
823 P9DIR .set PE_SFR + 04h ; Port 9 Direction
824 P9REN .set PE_SFR + 06h ; Port 9 Resistor Enable
825 P9SEL0 .set PE_SFR + 0Ah ; Port 9 Selection 0
826 P9SEL1 .set PE_SFR + 0Ch ; Port 9 Selection 1
827 P9SELC .set PE_SFR + 16h ; Port 9 Complement Selection
829 P10IN .set PE_SFR + 01h ; Port 10 Input */
830 P10OUT .set PE_SFR + 03h ; Port 10 Output
831 P10DIR .set PE_SFR + 05h ; Port 10 Direction
832 P10REN .set PE_SFR + 07h ; Port 10 Resistor Enable
833 P10SEL0 .set PE_SFR + 0Bh ; Port 10 Selection 0
834 P10SEL1 .set PE_SFR + 0Dh ; Port 10 Selection 1
835 P10SELC .set PE_SFR + 17h ; Port 10 Complement Selection
837 ; ----------------------------------------------------------------------
838 ; POWER ON RESET AND INITIALIZATION : RTC_C REGISTERS
839 ; ----------------------------------------------------------------------
840 RTCCTL0_L .set RTC_C_SFR + 00h
841 RTCCTL0_H .set RTC_C_SFR + 01h
842 RTCCTL1 .set RTC_C_SFR + 02h
843 RTCCTL3 .set RTC_C_SFR + 03h
844 RTCOCAL .set RTC_C_SFR + 04h
845 RTCTCMP .set RTC_C_SFR + 06h
846 RTCPS0CTL .set RTC_C_SFR + 08h
847 RTCPS1CTL .set RTC_C_SFR + 0Ah
848 RTCPS .set RTC_C_SFR + 0Ch ; = RT1PS:RT0PS
849 RTCIV .set RTC_C_SFR + 0Eh
850 RTCSEC .set RTC_C_SFR + 10h
851 RTCCNT1 .set RTC_C_SFR + 10h
852 RTCMIN .set RTC_C_SFR + 11h
853 RTCCNT2 .set RTC_C_SFR + 11h
854 RTCHOUR .set RTC_C_SFR + 12h
855 RTCCNT3 .set RTC_C_SFR + 12h
856 RTCDOW .set RTC_C_SFR + 13h
857 RTCCNT4 .set RTC_C_SFR + 13h
858 RTCDAY .set RTC_C_SFR + 14h
859 RTCMON .set RTC_C_SFR + 15h
860 RTCYEAR .set RTC_C_SFR + 16h
865 .ENDIF ; MSP430FR6989
873 ;=======================================================================
875 ;=======================================================================
877 UCSWRST .equ 1 ; eUSCI Software Reset
878 UCTXIE .equ 2 ; eUSCI Transmit Interrupt Enable
879 UCRXIE .equ 1 ; eUSCI Receive Interrupt Enable
880 UCTXIFG .equ 2 ; eUSCI Transmit Interrupt Flag
881 UCRXIFG .equ 1 ; eUSCI Receive Interrupt Flag
884 ; ----------------------------------------------------------------------
885 ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
886 ; ----------------------------------------------------------------------
890 PM5CTL0 .set PMM_SFR + 10h ; Power mode 5 control register 0
893 ; ----------------------------------------------------------------------
894 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
895 ; ----------------------------------------------------------------------
897 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
899 ; WDTCTL Control Bits
901 WDTHOLD .equ 0080h ; WDT - Timer hold
902 WDTCNTCL .equ 0008h ; WDT timer counter clear
904 ; ----------------------------------------------------------------------
905 ; POWER ON RESET AND INITIALIZATION : PORT1/2
906 ; ----------------------------------------------------------------------
908 PAIN .equ PA_SFR + 00h ; Port A INput
909 PAOUT .equ PA_SFR + 02h ; Port A OUTput
910 PADIR .equ PA_SFR + 04h ; Port A DIRection
911 PAREN .equ PA_SFR + 06h ; Port A Resistor ENable
912 PASEL0 .equ PA_SFR + 0Ah ; Port A SELection 0
913 PASEL1 .equ PA_SFR + 0Ch ; Port A SELection 1
914 PASELC .equ PA_SFR + 16h ; Port A SELection Complement
915 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
916 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
917 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt FlaG
919 P1IN .equ PA_SFR + 00h ; Port 1 INput
920 P1OUT .equ PA_SFR + 02h ; Port 1 OUTput
921 P1DIR .equ PA_SFR + 04h ; Port 1 DIRection
922 P1REN .equ PA_SFR + 06h ; Port 1 Resistor ENable
923 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 SELection 0
924 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 SELection 1
925 P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement
926 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
927 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
928 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt FlaG
929 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
931 P2IN .equ PA_SFR + 01h ; Port 2 INput
932 P2OUT .equ PA_SFR + 03h ; Port 2 OUTput
933 P2DIR .equ PA_SFR + 05h ; Port 2 DIRection
934 P2REN .equ PA_SFR + 07h ; Port 2 Resistor ENable
935 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 SELection 0
936 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 SELection 1
937 P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement
938 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
939 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
940 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt FlaG
941 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
943 ; ----------------------------------------------------------------------
944 ; POWER ON RESET AND INITIALIZATION : PORT3/4
945 ; ----------------------------------------------------------------------
947 PBIN .equ PB_SFR + 00h ; Port B Input
948 PBOUT .equ PB_SFR + 02h ; Port B Output 1/0 or pullup/pulldown resistor
949 PBDIR .equ PB_SFR + 04h ; Port B Direction
950 PBREN .equ PB_SFR + 06h ; Port B Resistor Enable
951 PBSEL0 .equ PB_SFR + 0Ah ; Port B Selection 0
952 PBSEL1 .equ PB_SFR + 0Ch ; Port B Selection 1
953 PBSELC .equ PB_SFR + 16h ; Port B Complement Selection
954 PBIES .equ PB_SFR + 18h ; Port B Interrupt Edge Select
955 PBIE .equ PB_SFR + 1Ah ; Port B Interrupt Enable
956 PBIFG .equ PB_SFR + 1Ch ; Port B Interrupt Flag
958 P3IN .equ PB_SFR + 00h ; Port 3 Input */
959 P3OUT .equ PB_SFR + 02h ; Port 3 Output
960 P3DIR .equ PB_SFR + 04h ; Port 3 Direction
961 P3REN .equ PB_SFR + 06h ; Port 3 Resistor Enable
962 P3SEL0 .equ PB_SFR + 0Ah ; Port 3 Selection 0
963 P3SEL1 .equ PB_SFR + 0Ch ; Port 3 Selection 1
964 P3SELC .equ PB_SFR + 16h ; Port 3 Complement Selection
965 P3IES .equ PB_SFR + 18h ; Port 3 Interrupt Edge Select
966 P3IE .equ PB_SFR + 1Ah ; Port 3 Interrupt Enable
967 P3IFG .equ PB_SFR + 1Ch ; Port 3 Interrupt Flag
968 P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word
970 P4IN .equ PB_SFR + 01h ; Port 4 Input */
971 P4OUT .equ PB_SFR + 03h ; Port 4 Output
972 P4DIR .equ PB_SFR + 05h ; Port 4 Direction
973 P4REN .equ PB_SFR + 07h ; Port 4 Resistor Enable
974 P4SEL0 .equ PB_SFR + 0Bh ; Port 4 Selection 0
975 P4SEL1 .equ PB_SFR + 0Dh ; Port 4 Selection 1
976 P4SELC .equ PB_SFR + 17h ; Port 4 Complement Selection
977 P4IES .equ PB_SFR + 19h ; Port 4 Interrupt Edge Select
978 P4IE .equ PB_SFR + 1Bh ; Port 4 Interrupt Enable
979 P4IFG .equ PB_SFR + 1Dh ; Port 4 Interrupt Flag
980 P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word
982 ; ----------------------------------------------------------------------
983 ; POWER ON RESET AND INITIALIZATION : PORTJ
984 ; ----------------------------------------------------------------------
986 PJIN .equ PJ_SFR + 00h ; Port J INput
987 PJOUT .equ PJ_SFR + 02h ; Port J OUTput
988 PJDIR .equ PJ_SFR + 04h ; Port J DIRection
989 PJREN .equ PJ_SFR + 06h ; Port J Resistor ENable
990 PJSEL0 .equ PJ_SFR + 0Ah ; Port 2 SELection 0
991 PJSEL1 .equ PJ_SFR + 0Ch ; Port 2 SELection 1
992 PJSELC .equ PJ_SFR + 16h ; Port 2 SELection Complement; PJ 5-0 usage
994 ; ----------------------------------------------------------------------
996 ; ----------------------------------------------------------------------
997 FRCTL0 .set FRAM_SFR + 00h ; FRAM Controller Control 0
998 FRCTL0_H .set FRAM_SFR + 01h ; FRAM Controller Control 0 high byte
1000 ; ----------------------------------------------------------------------
1001 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
1002 ; ----------------------------------------------------------------------
1004 CSCTL0 .equ CS_SFR + 00h ; CS Control Register 0
1005 CSCTL0_H .equ CS_SFR + 01h ; CS Control Register 0 high byte
1006 CSCTL1 .equ CS_SFR + 02h ; CS Control Register 1
1007 CSCTL2 .equ CS_SFR + 04h ; CS Control Register 2
1008 CSCTL3 .equ CS_SFR + 06h ; CS Control Register 3
1010 ; CSCTL0 Control Bits
1011 CSKEY .equ 0A5h ; CS Password
1012 ; CSCTL1 Control Bits
1014 DCOFSEL0 .equ 0002h ; DCO frequency select Bit: 0
1015 DCOFSEL1 .equ 0004h ; DCO frequency select Bit: 1
1016 DCOFSEL2 .equ 0008h ; DCO frequency select Bit: 2
1017 DCOFSEL3 .equ 000Ch ; DCO frequency select Bit: 21
1018 ; CSCTL2 Control Bits
1019 SELA_LFXCLK .equ 0000h ; 0 : ACLK Source Select LFXCLK
1020 SELA_VLOCLK .equ 0100h ; 1 ACLK Source Select VLOCLK 10kHz
1021 SELS_DCOCLK .equ 0030h ; 3 : SMCLK Source Select DCOCLK
1022 SELM_DCOCLK .equ 0003h ; 3 : MCLK Source Select DCOCLK
1023 ; CSCTL3 Control Bits
1024 DIVA_0 .equ 0000h ; ACLK Source Divider 0
1025 DIVS_0 .equ 0000h ; SMCLK Source Divider 0
1026 DIVM_0 .equ 0000h ; MCLK Source Divider 0
1027 DIVA_2 .equ 0100h ; ACLK Source Divider 0
1028 DIVS_2 .equ 0010h ; SMCLK Source Divider 0
1029 DIVM_2 .equ 0001h ; MCLK Source Divider 0
1030 DIVA_4 .equ 0200h ; ACLK Source Divider 0
1031 DIVS_4 .equ 0020h ; SMCLK Source Divider 0
1032 DIVM_4 .equ 0002h ; MCLK Source Divider 0
1033 DIVA_8 .equ 0300h ; ACLK Source Divider 0
1034 DIVS_8 .equ 0030h ; SMCLK Source Divider 0
1035 DIVM_8 .equ 0003h ; MCLK Source Divider 0
1036 DIVA_16 .equ 0400h ; ACLK Source Divider 0
1037 DIVS_16 .equ 0040h ; SMCLK Source Divider 0
1038 DIVM_16 .equ 0004h ; MCLK Source Divider 0
1039 DIVA_32 .equ 0500h ; ACLK Source Divider 0
1040 DIVS_32 .equ 0050h ; SMCLK Source Divider 0
1041 DIVM_32 .equ 0005h ; MCLK Source Divider 0
1043 ; ----------------------------------------------------------------------
1044 ; POWER ON RESET AND INITIALIZATION : REF
1045 ; ----------------------------------------------------------------------
1047 REFCTL equ REF_SFR + 00h ; REF Shared Reference control register 0
1049 ; REFCTL0 Control Bits
1050 REFON equ 0001h ; REF Reference On
1051 REFTCOFF equ 0008h ; REF Temp.Sensor off
1053 ; ----------------------------------------------------------------------
1055 ; ----------------------------------------------------------------------
1057 MPY .equ MPY_SFR + 00h ; Multiply16 Unsigned/Operand 1 */
1058 MPYS .equ MPY_SFR + 02h ; Multiply16 signed/Operand 1
1059 MAC .equ MPY_SFR + 04h ; MultiplyAccumulate16 Unsigned/Operand 1 */
1060 MACS .equ MPY_SFR + 06h ; MultiplyAccumulate16 signed/Operand 1
1061 OP2 .equ MPY_SFR + 08h ; Operand2_16 */
1062 RESLO .equ MPY_SFR + 0Ah ; 16x16-bit result low - least significant word */
1063 RESHI .equ MPY_SFR + 0Ch ; 16x16-bit result high */
1064 SUMEXT .equ MPY_SFR + 0Eh ; 16x16-bit sum extension register
1065 MPY32L .equ MPY_SFR + 10h ; Multiply32 Unsigned/Operand 1
1066 MPY32H .equ MPY_SFR + 12h ; Multiply32 Unsigned/Operand 1
1067 MPYS32L .equ MPY_SFR + 14h ; Multiply32 signed/Operand 1
1068 MPYS32H .equ MPY_SFR + 16h ; Multiply32 signed/Operand 1
1069 MAC32L .equ MPY_SFR + 18h ; MultiplyAccumulate32 Unsigned/Operand 1
1070 MAC32H .equ MPY_SFR + 1Ah ; MultiplyAccumulate32 Unsigned/Operand 1
1071 MACS32L .equ MPY_SFR + 1Ch ; MultiplyAccumulate32 signed/Operand 1
1072 MACS32H .equ MPY_SFR + 1Eh ; MultiplyAccumulate32 signed/Operand 1
1073 OP2L .equ MPY_SFR + 20h ; Multiply32 Operand 2
1074 OP2H .equ MPY_SFR + 22h ; Multiply32 Operand 2
1075 RES0 .equ MPY_SFR + 24h ; 32x32-bit result 0 - least significant word */
1076 RES1 .equ MPY_SFR + 26h ; 32x32-bit result 1 */
1077 RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */
1078 RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
1079 MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
1082 ; ----------------------------------------------------------------------
1084 ; ----------------------------------------------------------------------
1087 TERMCTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
1088 TERMBRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
1089 TERMMCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
1090 TERMRXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
1091 TERMTXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
1092 TERMIE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
1093 TERMIFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
1097 SD_CTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
1098 SD_BRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
1099 SD_RXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer 8
1100 SD_TXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer 8
1101 SD_IFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
1104 ; ----------------------------------------------------------------------
1106 ; ----------------------------------------------------------------------
1109 TERMCTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
1110 TERMBRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
1111 TERMMCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
1112 TERMRXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
1113 TERMTXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
1114 TERMIE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
1115 TERMIFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
1119 SD_CTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
1120 SD_BRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
1121 SD_RXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer 8
1122 SD_TXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer 8
1123 SD_IFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
1127 ; ----------------------------------------------------------------------
1129 ; ----------------------------------------------------------------------
1131 SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; eUSCI_B0 Control Word Register 0
1132 SD_BRW .equ eUSCI_B0_SFR + 06h ; eUSCI_B0 Baud Word Rate 0
1133 SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; eUSCI_B0 Receive Buffer 8
1134 SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; eUSCI_B0 Transmit Buffer 8
1135 SD_IFG .equ eUSCI_B0_SFR + 2Ch ; eUSCI_B0 Interrupt Flags Register
1140 ; ----------------------------------------------------------------------
1141 ; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
1142 ; ----------------------------------------------------------------------
1144 SYSUNIV .equ SYS_SFR + 001Ah
1145 SYSSNIV .equ SYS_SFR + 001Ch
1146 SYSRSTIV .equ SYS_SFR + 001Eh