1 ------------------------------------------------------------------------------
2 -- Copyright (C) 2011, Kenichi Kurimoto
4 -- This program is free software; you can redistribute it and/or modify
5 -- it under the terms of the GNU General Public License as published by
6 -- the Free Software Foundation; either version 2 of the License, or
7 -- (at your option) any later version.
9 -- This program is distributed in the hope that it will be useful,
10 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- GNU General Public License for more details.
14 -- You should have received a copy of the GNU General Public License
15 -- along with this program; if not, write to the Free Software
16 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -----------------------------------------------------------------------------
20 -- Author: Kenichi Kurimoto
21 -- Description: AMBA slave interface and huffman decoder for jpeg decode
22 ------------------------------------------------------------------------------
25 use ieee.std_logic_1164.all;
26 use ieee.numeric_std.all;
31 use grlib.devices.all;
34 use techmap.gencomp.all;
41 memtech : integer := DEFMEMTECH;
42 shindex : integer := 0;
44 hmask : integer := 16#fff#;
46 pindex : integer := 0;
48 pmask : integer := 16#fff#;
49 mhindex : integer := 0;
50 chprot : integer := 3);
54 ahbsi : in ahb_slv_in_type;
55 ahbso : out ahb_slv_out_type;
56 apbi : in apb_slv_in_type;
57 apbo : out apb_slv_out_type;
58 kready : in std_logic;
59 kstrobe : out std_logic;
60 kdata : out std_logic_vector(11 downto 0);
61 kaddress : out std_logic_vector(5 downto 0);
62 jpg_setting : out jpg_set_type;
63 error : in std_logic_vector(2 downto 0);
64 startgen : out std_logic;
65 kstrobeq : out std_logic;
66 kdataq : out std_logic_vector(7 downto 0);
67 kaddq : out std_logic_vector(7 downto 0);
68 krddataq : in std_logic_vector(7 downto 0);
73 architecture rtl of huff is
75 constant shconfig : ahb_config_type := (
76 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, hirq),
77 4 => ahb_membar(haddr, '0', '0', hmask),
80 constant pconfig : apb_config_type := (
81 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
82 1 => apb_iobar(paddr, pmask));
84 constant fdepth : integer := 512;
86 constant const_4b4 : std_logic_vector(3 downto 0) := "0100";
87 constant const_4b5 : std_logic_vector(3 downto 0) := "0101";
88 constant const_4b6 : std_logic_vector(3 downto 0) := "0110";
89 constant const_6b8 : std_logic_vector(5 downto 0) := "001000";
90 constant const_u6b24 : UNSIGNED(5 downto 0) := "011000";
92 function sign_ex(data, bitnum : std_logic_vector) return std_logic_vector is
93 variable outb : std_logic_vector(11 downto 0);
94 variable minusjudge : std_logic;
95 variable tmp : integer;
98 if(bitnum = "0001")then
100 outb := "111111111111";
102 outb := "000000000001";
104 elsif(bitnum = "0010")then
105 if(data(1) = '0')then
106 tmp := to_integer(signed('1' & data(1 downto 0))) + 1;
107 outb := std_logic_vector(to_signed(tmp, 12));
109 tmp := to_integer(signed('0' & data(1 downto 0)));
110 outb := std_logic_vector(to_signed(tmp, 12));
112 elsif(bitnum = "0011")then
113 if(data(2) = '0')then
114 tmp := to_integer(signed('1' & data(2 downto 0))) + 1;
115 outb := std_logic_vector(to_signed(tmp, 12));
117 tmp := to_integer(signed('0' & data(2 downto 0)));
118 outb := std_logic_vector(to_signed(tmp, 12));
120 elsif(bitnum = "0100")then
121 if(data(3) = '0')then
122 tmp := to_integer(signed('1' & data(3 downto 0))) + 1;
123 outb := std_logic_vector(to_signed(tmp, 12));
125 tmp := to_integer(signed('0' & data(3 downto 0)));
126 outb := std_logic_vector(to_signed(tmp, 12));
128 elsif(bitnum = "0101")then
129 if(data(4) = '0')then
130 tmp := to_integer(signed('1' & data(4 downto 0))) + 1;
131 outb := std_logic_vector(to_signed(tmp, 12));
133 tmp := to_integer(signed('0' & data(4 downto 0)));
134 outb := std_logic_vector(to_signed(tmp, 12));
136 elsif(bitnum = "0110")then
137 if(data(5) = '0')then
138 tmp := to_integer(signed('1' & data(5 downto 0))) + 1;
139 outb := std_logic_vector(to_signed(tmp, 12));
141 tmp := to_integer(signed('0' & data(5 downto 0)));
142 outb := std_logic_vector(to_signed(tmp, 12));
144 elsif(bitnum = "0111")then
145 if(data(6) = '0')then
146 tmp := to_integer(signed('1' & data(6 downto 0))) + 1;
147 outb := std_logic_vector(to_signed(tmp, 12));
149 tmp := to_integer(signed('0' & data(6 downto 0)));
150 outb := std_logic_vector(to_signed(tmp, 12));
152 elsif(bitnum = "1000")then
153 if(data(7) = '0')then
154 tmp := to_integer(signed('1' & data(7 downto 0))) + 1;
155 outb := std_logic_vector(to_signed(tmp, 12));
157 tmp := to_integer(signed('0' & data(7 downto 0)));
158 outb := std_logic_vector(to_signed(tmp, 12));
160 elsif(bitnum = "1001")then
161 if(data(8) = '0')then
162 tmp := to_integer(signed('1' & data(8 downto 0))) + 1;
163 outb := std_logic_vector(to_signed(tmp, 12));
165 tmp := to_integer(signed('0' & data(8 downto 0)));
166 outb := std_logic_vector(to_signed(tmp, 12));
168 elsif(bitnum = "1010")then
169 if(data(9) = '0')then
170 tmp := to_integer(signed('1' & data(9 downto 0))) + 1;
171 outb := std_logic_vector(to_signed(tmp, 12));
173 tmp := to_integer(signed('0' & data(9 downto 0)));
174 outb := std_logic_vector(to_signed(tmp, 12));
176 elsif(bitnum = "1011")then
177 if(data(10) = '0')then
178 tmp := to_integer(signed('1' & data(10 downto 0))) + 1;
179 outb := std_logic_vector(to_signed(tmp, 12));
181 tmp := to_integer(signed('0' & data(10 downto 0)));
182 outb := std_logic_vector(to_signed(tmp, 12));
185 outb := (others => '0');
191 type fstate_type is (memwait, bytefetch, ffmemwait, ffcheck, markermode);
192 type dstate_type is (symreq, symcheck, valout, symng, symokvalng, serialwait, serialcheck, serialfinish, standby);
194 type ahbs_reg is record
199 getcache : std_logic;
200 rdacache : std_logic;
201 rddcache : std_logic;
204 getoffset : std_logic;
205 rdoffset : std_logic;
208 hreadyff : std_logic;
210 haddkeep : std_logic_vector(15 downto 0);
213 type apbs_reg is record
215 xmcumax : std_logic_vector(5 downto 0);
216 ymcumax : std_logic_vector(4 downto 0);
217 incaddy : std_logic_vector(15 downto 0);
218 incaddmcux : std_logic_vector(15 downto 0);
219 incaddmcuy : std_logic_vector(10 downto 0);
220 fbstartadd : std_logic_vector(31 downto 0);
221 through_bit : std_logic;
222 hardonly : std_logic;
225 type control_reg is record
226 fetch_state : fstate_type;
227 dec_state : dstate_type;
230 fifo_rp : std_logic_vector(8 downto 0);
231 fifo_wp : std_logic_vector(8 downto 0);
232 fetch_reg : std_logic_vector(31 downto 0);
233 marker_reg : std_logic_vector(7 downto 0);
234 valuebit : std_logic_vector(5 downto 0);
235 byteselect : std_logic_vector(1 downto 0);
236 reqbit_keep : std_logic_vector(3 downto 0);
237 valbit_keep : std_logic_vector(3 downto 0);
239 serial_counter : std_logic_vector(4 downto 0);
240 idcounter : std_logic_vector(3 downto 0);
241 memaddcnt : std_logic_vector(5 downto 0);
242 lastdc0 : std_logic_vector(11 downto 0);
243 lastdc1 : std_logic_vector(11 downto 0);
244 lastdc2 : std_logic_vector(11 downto 0);
245 byte3keep : std_logic_vector(23 downto 0);
247 capture : std_logic_vector(1 downto 0);
248 skipcnt : std_logic_vector(15 downto 0);
251 signal r, rin : control_reg;
252 signal read_en_fifo, write_en_fifo : std_logic;
253 signal read_pointer_fifo : std_logic_vector(8 downto 0);
254 signal write_pointer_fifo : std_logic_vector(8 downto 0);
255 signal data_out_fifo : std_logic_vector(31 downto 0);
256 signal data_in_fifo : std_logic_vector(31 downto 0);
258 signal dccacheadd : std_logic_vector(9 downto 0);
259 signal dccachedin : std_logic_vector(7 downto 0);
260 signal dccachedout : std_logic_vector(7 downto 0);
261 signal dccacheen,dccachewr : std_logic;
262 signal accacheadd : std_logic_vector(9 downto 0);
263 signal accachedin : std_logic_vector(11 downto 0);
264 signal accachedout : std_logic_vector(11 downto 0);
265 signal accacheen,accachewr : std_logic;
266 signal sermaxadd : std_logic_vector(6 downto 0);
267 signal sermaxdin : std_logic_vector(16 downto 0);
268 signal sermaxdout : std_logic_vector(16 downto 0);
269 signal sermaxen,sermaxwr : std_logic;
270 signal seroffadd : std_logic_vector(6 downto 0);
271 signal seroffdin : std_logic_vector(16 downto 0);
272 signal seroffdout : std_logic_vector(16 downto 0);
273 signal seroffen,seroffwr : std_logic;
274 signal servaladd : std_logic_vector(9 downto 0);
275 signal servaldin : std_logic_vector(7 downto 0);
276 signal servaldout : std_logic_vector(7 downto 0);
277 signal servalen,servalwr : std_logic;
279 signal debug_memaddcnt : std_logic_vector(5 downto 0);
282 ramscan : syncram_2p generic map(tech => memtech, abits => 9, dbits => 32,sepclk => 0)
283 port map( clk, read_en_fifo, read_pointer_fifo, data_out_fifo,
284 clk, write_en_fifo, write_pointer_fifo, data_in_fifo);
285 huffdccache : syncram generic map(tech => memtech, abits => 10, dbits => 8)
286 port map( clk, dccacheadd, dccachedin, dccachedout, dccacheen, dccachewr);
287 huffaccache : syncram generic map(tech => memtech, abits => 10, dbits => 12)
288 port map( clk, accacheadd, accachedin, accachedout, accacheen, accachewr);
289 serialmax : syncram generic map(tech => memtech, abits => 7, dbits => 17)
290 port map( clk, sermaxadd, sermaxdin, sermaxdout, sermaxen, sermaxwr);
291 serialoffset : syncram generic map(tech => memtech, abits => 7, dbits => 17)
292 port map( clk, seroffadd, seroffdin, seroffdout, seroffen, seroffwr);
293 serialval : syncram generic map(tech => memtech, abits => 10, dbits => 8)
294 port map( clk, servaladd, servaldin, servaldout, servalen, servalwr);
297 comb_fetch : process(r, rst, ahbsi, apbi, data_out_fifo, dccachedout, accachedout, sermaxdout, seroffdout, servaldout, kready, error, krddataq)
298 variable v : control_reg;
299 variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
300 variable vsready : std_logic;
301 variable write_point : integer;
302 variable read_point : integer;
303 variable num_ele : integer;
304 variable apbwrite : std_logic;
305 variable vprdata : std_logic_vector(31 downto 0);
306 variable vhrdata : std_logic_vector(31 downto 0);
307 variable vwriting :std_logic;
308 variable vreading : std_logic;
309 variable vdccacheadd : std_logic_vector(9 downto 0);
310 variable vdccachewr : std_logic;
311 variable vaccacheadd : std_logic_vector(9 downto 0);
312 variable vaccachewr : std_logic;
313 variable vsermaxadd : std_logic_vector(6 downto 0);
314 variable vsermaxwr : std_logic;
315 variable vseroffadd : std_logic_vector(6 downto 0);
316 variable vseroffwr : std_logic;
317 variable vservaladd : std_logic_vector(9 downto 0);
318 variable vservalwr : std_logic;
320 variable vbytedata : std_logic_vector(7 downto 0);
321 variable vinsertdata : std_logic_vector(7 downto 0);
322 variable vbyte0, vbyte1, vbyte2, vbyte3 : std_logic_vector(7 downto 0);
323 variable vfetching : std_logic;
325 variable vcache_symbit : std_logic_vector(4 downto 0);
326 variable vcache_runlength : std_logic_vector(3 downto 0);
327 variable vcache_valbit : std_logic_vector(3 downto 0);
329 variable vint_plusv : integer;
330 variable vint_minusv : integer;
332 variable vserial_symbit : std_logic_vector(4 downto 0);
333 variable vserial_runlength : std_logic_vector(3 downto 0);
334 variable vserial_valbit : std_logic_vector(3 downto 0);
335 variable vserial_tmpin : std_logic_vector(16 downto 0);
336 variable vserial_mask : std_logic_vector(16 downto 0);
337 variable vserial_judge : std_logic;
338 variable vserial_tmpadd : std_logic_vector(16 downto 0);
340 variable vintshift : integer;
341 variable vshiftnum : std_logic_vector(4 downto 0);
342 variable vint_valuebit : integer;
343 variable vint_valbkp : integer;
344 variable vint_sercnt : integer;
345 variable vshiftout : std_logic_vector(15 downto 0);
346 variable vtmpshiftout : std_logic_vector(31 downto 0);
347 variable vid : std_logic;
348 variable vcompid : std_logic_vector(1 downto 0);
349 variable vkstrobe : std_logic;
350 variable vkdata : std_logic_vector(11 downto 0);
351 variable vint_csymbit : integer;
352 variable vint_reqbitkp : integer;
353 variable vint_cvalbit : integer;
354 variable vint_sersym : integer;
355 variable vint_serval : integer;
357 variable vkaddq : std_logic_vector(7 downto 0);
358 variable vkrdq : std_logic;
359 variable vgetbyte : std_logic;
360 variable vstartgen : std_logic;
364 virq := (others => '0');
365 vdccachewr := '0'; vdccacheadd := (others => '0');
366 vaccachewr := '0'; vaccacheadd := (others => '0');
367 vsermaxwr := '0'; vsermaxadd := (others => '0');
368 vseroffwr := '0'; vseroffadd := (others => '0');
369 vservalwr := '0'; vservaladd := (others => '0');
370 vkaddq := (others => '0'); vkrdq := '0';
371 vserial_judge := '0';
372 vkstrobe := '0'; vstartgen := '0';
375 apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
376 vprdata := (others => '0');
377 case apbi.paddr(5 downto 2) is
379 if apbwrite = '1' then
380 v.preg.fbstartadd := apbi.pwdata(31 downto 0);
382 vprdata := r.preg.fbstartadd(31 downto 0);
384 if apbwrite = '1' then
385 v.preg.sampf := apbi.pwdata(22);
386 v.preg.ymcumax := apbi.pwdata(21 downto 17);
387 v.preg.xmcumax := apbi.pwdata(16 downto 11);
388 v.preg.incaddmcuy := apbi.pwdata(10 downto 0);
390 vprdata := "000000000" & r.preg.sampf & r.preg.ymcumax & r.preg.xmcumax & r.preg.incaddmcuy;
392 if apbwrite = '1' then
393 v.preg.incaddy := apbi.pwdata(31 downto 16);
394 v.preg.incaddmcux := apbi.pwdata(15 downto 0);
396 vprdata := r.preg.incaddy & r.preg.incaddmcux;
398 if apbwrite = '1' then
399 if apbi.pwdata(31) = '1' then
402 v.preg.through_bit := apbi.pwdata(15);
403 v.preg.hardonly := apbi.pwdata(14);
404 v.marker_reg := apbi.pwdata(23 downto 16);
406 vprdata := "00000000" & r.marker_reg & r.preg.through_bit & r.preg.hardonly &"00000000000000" ;
410 if(r.hreg.getcache = '1' or r.hreg.hreadyff = '0')then
411 if (r.hreg.haddkeep(15) = '1') then
413 vdccacheadd := r.hreg.haddkeep(11 downto 2);
416 vaccacheadd := r.hreg.haddkeep(11 downto 2);
419 vdccacheadd := ahbsi.haddr(11 downto 2);
420 vaccacheadd := ahbsi.haddr(11 downto 2);
422 if(r.hreg.getq = '1' or r.hreg.hreadyff = '0')then
423 vkaddq := r.hreg.haddkeep(9 downto 2);
425 vkaddq := ahbsi.haddr(9 downto 2);
428 if(r.hreg.getmax = '1' or r.hreg.hreadyff = '0')then
430 vsermaxadd := r.hreg.haddkeep(8 downto 2);
432 vsermaxadd := ahbsi.haddr(8 downto 2);
434 if(r.hreg.getoffset = '1' or r.hreg.hreadyff = '0')then
436 vseroffadd := r.hreg.haddkeep(8 downto 2);
438 vseroffadd := ahbsi.haddr(8 downto 2);
440 if(r.hreg.getval = '1' or r.hreg.hreadyff = '0')then
442 vservaladd := r.hreg.haddkeep(11 downto 2);
444 vservaladd := ahbsi.haddr(11 downto 2);
447 if(ahbsi.hready = '1' ) then
448 v.hreg.getscan := '0';
449 v.hreg.rdscan := '0';
452 v.hreg.getcache := '0';
453 v.hreg.rdacache := '0';
454 v.hreg.rddcache := '0';
455 v.hreg.getmax := '0';
457 v.hreg.getoffset := '0';
458 v.hreg.rdoffset := '0';
459 v.hreg.getval := '0';
462 v.hreg.hselff := ahbsi.hsel(shindex) and ahbsi.htrans(1);
463 vwriting := ahbsi.hwrite and v.hreg.hselff;
464 vreading := (not ahbsi.hwrite) and v.hreg.hselff;
465 if(ahbsi.haddr(19 downto 8) = "000000000000")then
466 if(vwriting = '1')then
467 v.hreg.getscan := '1';
468 elsif(vreading = '1')then
469 v.hreg.rdscan := '1';
472 if(ahbsi.haddr(15 downto 12) = "1100" )then
473 if(vwriting = '1')then
475 elsif(vreading = '1')then
479 if(ahbsi.haddr(15 downto 12) = "0100" or ahbsi.haddr(15 downto 12) = "0101")then
480 if(vwriting = '1')then
481 v.hreg.getcache := '1';
482 elsif(vreading = '1')then
483 v.hreg.rdacache := '1';
486 if(ahbsi.haddr(15 downto 12) = "1000" or ahbsi.haddr(15 downto 12) = "1001")then
487 if(vwriting = '1')then
488 v.hreg.getcache := '1';
489 elsif(vreading = '1')then
490 v.hreg.rddcache := '1';
493 if(ahbsi.haddr(15 downto 10) = "000001")then
494 if(vwriting = '1')then
495 v.hreg.getmax := '1';
496 elsif(vreading = '1')then
500 if(ahbsi.haddr(15 downto 10) = "000010")then
501 if(vwriting = '1')then
502 v.hreg.getoffset := '1';
503 elsif(vreading = '1')then
504 v.hreg.rdoffset := '1';
507 if(ahbsi.haddr(15 downto 13) = "001")then
508 if(vwriting = '1')then
509 v.hreg.getval := '1';
510 elsif(vreading = '1')then
514 v.hreg.haddkeep := ahbsi.haddr(15 downto 0);
517 if( v.hreg.getscan = '1' or v.hreg.getq = '1' or v.hreg.getcache = '1'
518 or v.hreg.getmax = '1' or v.hreg.getoffset = '1' or v.hreg.getval = '1')then
519 v.hreg.hreadyff := not(v.hreg.hselff and not ahbsi.hwrite);
520 v.hreg.getscan := v.hreg.getscan and v.hreg.hreadyff;
521 v.hreg.getq := v.hreg.getq and v.hreg.hreadyff;
522 v.hreg.getcache := v.hreg.getcache and v.hreg.hreadyff;
523 v.hreg.getmax := v.hreg.getmax and v.hreg.hreadyff;
524 v.hreg.getoffset := v.hreg.getoffset and v.hreg.hreadyff;
525 v.hreg.getval := v.hreg.getval and v.hreg.hreadyff;
528 -- FIFO # of element calculation
529 write_point := to_integer(unsigned(r.fifo_wp));
530 read_point := to_integer(unsigned(r.fifo_rp));
531 if (write_point >= read_point) then
532 num_ele := write_point - read_point;
534 num_ele := fdepth - read_point + write_point;
536 if num_ele > fdepth/2 then
543 vhrdata := vsready & "0000000000000000000000000000000";
544 if(r.hreg.rdscan = '1')then
545 vhrdata := data_out_fifo;
546 elsif(r.hreg.rdq ='1')then
547 vhrdata := "000000000000000000000000" &krddataq;
548 elsif(r.hreg.rdacache = '1')then
549 vhrdata := "00000000000000000000" & accachedout;
550 elsif(r.hreg.rddcache = '1')then
551 vhrdata := "000000000000000000000000" & dccachedout;
552 elsif(r.hreg.rdmax = '1')then
553 vhrdata := "000000000000000" & sermaxdout;
554 elsif(r.hreg.rdoffset = '1')then
555 vhrdata := "000000000000000" & seroffdout;
556 elsif(r.hreg.rdval = '1')then
557 vhrdata := "000000000000000000000000" & servaldout;
561 if r.hreg.getscan = '1' then
562 write_point := write_point + 1;
563 if write_point = fdepth then
567 v.fifo_wp := std_logic_vector(to_unsigned(write_point,9));
570 if((r.fetch_state = bytefetch and r.byteselect = "00" and num_ele >= 1 and unsigned(r.valuebit)<= const_u6b24)
571 or (r.fetch_state = ffcheck and r.byteselect = "00" and num_ele >= 1 and unsigned(r.valuebit)<= const_u6b24)) then
572 read_point := read_point + 1;
573 if read_point = fdepth then
576 v.byte3keep(23 downto 0) := data_out_fifo(23 downto 0);
578 v.fifo_rp := std_logic_vector(to_unsigned(read_point,9));
580 -- byte select from FIFO output
581 if(r.byteselect = "00") then
582 vbytedata := data_out_fifo(31 downto 24);
583 elsif(r.byteselect = "01") then
584 vbytedata := r.byte3keep(23 downto 16);
585 elsif(r.byteselect = "10") then
586 vbytedata := r.byte3keep(15 downto 8);
588 vbytedata := r.byte3keep(7 downto 0);
592 if((r.fetch_state = bytefetch and unsigned(r.valuebit) <= const_u6b24 )
593 or (r.fetch_state = ffcheck and unsigned(r.valuebit) <= const_u6b24))then
594 v.byteselect := v.byteselect + 1;
599 if(r.fetch_state = ffcheck) then
600 vinsertdata := "11111111";
602 vinsertdata := vbytedata;
605 -- byte fetching to 32bit fetch_register
606 if( (r.fetch_state = bytefetch and vbytedata /= "11111111" and unsigned(r.valuebit) <= const_u6b24 and r.preg.through_bit = '0' )
607 or (r.fetch_state = ffcheck and vbytedata = "00000000" and unsigned(r.valuebit) <= const_u6b24 and r.preg.through_bit = '0')) then
613 if(vfetching = '1') then
614 vbyte0 := vinsertdata;
615 vbyte1 := r.fetch_reg(7 downto 0);
616 vbyte2 := r.fetch_reg(15 downto 8);
617 vbyte3 := r.fetch_reg(23 downto 16);
619 vbyte0 := r.fetch_reg(7 downto 0);
620 vbyte1 := r.fetch_reg(15 downto 8);
621 vbyte2 := r.fetch_reg(23 downto 16);
622 vbyte3 := r.fetch_reg(31 downto 24);
624 v.fetch_reg := vbyte3 & vbyte2 & vbyte1 & vbyte0;
627 if(r.fetch_state = ffcheck and vbytedata /= "00000000" and r.preg.through_bit = '0') then
628 v.marker_reg := vbytedata;
630 if(r.marker_reg /= "00000000")then
634 -- Through bit & skip counter calculation
635 -- This part is for "motion"-JPEG".
636 -- It's not beautiful implementation, but.....
637 if(r.fetch_state = ffcheck and r.preg.through_bit = '1' and vbytedata = "11011010")then
641 if(r.capture = "10")then
642 v.skipcnt(15 downto 8) := vbytedata;
644 if(r.capture = "01")then
645 v.skipcnt(7 downto 0) := vbytedata;
647 if(r.cntdown = '1' and vgetbyte = '1')then
648 if(r.capture = "10")then
651 if(r.capture = "01")then
654 if(r.capture = "00")then
655 v.skipcnt := r.skipcnt - 1;
657 if(r.skipcnt = "0000000000000011")then
658 v.preg.through_bit := '0';
660 v.skipcnt := (others => '0');
664 -- State machine transition (fetch part)
665 case r.fetch_state is
667 if (num_ele /= 0 and unsigned(r.valuebit) <= const_u6b24) then
668 v.fetch_state := bytefetch;
671 if(r.byteselect = "11" and unsigned(r.valuebit) <= const_u6b24 and num_ele = 0 and vbytedata /= "11111111") then
672 v.fetch_state := memwait;
673 elsif( vbytedata = "11111111" and r.byteselect = "11" and num_ele = 0 and unsigned(r.valuebit) <= const_u6b24) then
674 v.fetch_state := ffmemwait;
675 elsif( vbytedata = "11111111" and unsigned(r.valuebit) <= const_u6b24 and (r.byteselect /= "11" or (r.byteselect = "11" and num_ele /= 0))) then
676 v.fetch_state := ffcheck;
679 if(num_ele /= 0) then
680 v.fetch_state := ffcheck;
683 if( (vbytedata = "00000000" and unsigned(r.valuebit) <=const_u6b24 and (r.byteselect /= "11" or num_ele /= 0))
684 or (r.preg.through_bit = '1' and unsigned(r.valuebit)<=const_u6b24 and (r.byteselect /= "11" or num_ele /= 0) )) then
685 v.fetch_state := bytefetch;
686 elsif( (vbytedata = "00000000" and unsigned(r.valuebit)<=const_u6b24 and (r.byteselect = "11" and num_ele = 0))
687 or( r.preg.through_bit = '1' and unsigned(r.valuebit)<=const_u6b24 and r.byteselect = "11" and num_ele = 0 )) then
688 v.fetch_state := memwait;
689 elsif ( vbytedata /= "00000000") then
690 v.fetch_state := markermode;
693 if(r.marker_reg = "00000000" and (r.byteselect /= "11" or( r.byteselect = "11" and num_ele /= 0))) then
694 v.fetch_state := bytefetch;
695 elsif(r.marker_reg = "00000000" and (r.byteselect = "11" and num_ele =0)) then
696 v.fetch_state := memwait;
698 if(r.preg.hardonly = '1' and r.marker_reg = x"D9")then
699 if(r.byteselect /= "11" or( r.byteselect = "11" and num_ele /= 0))then
700 v.marker_reg := "00000000";
701 v.preg.through_bit := '1';
702 elsif(r.byteselect = "11" and num_ele =0)then
703 v.marker_reg := "00000000";
704 v.preg.through_bit := '1';
710 -- cache, serial mem output
711 if(r.dcac = '1') then
712 vcache_symbit := "0" & dccachedout(7 downto 4);
713 vcache_valbit := dccachedout(3 downto 0);
714 vcache_runlength := "0000";
716 vcache_symbit := "0" & accachedout(11 downto 8);
717 vcache_runlength := accachedout(7 downto 4);
718 vcache_valbit := accachedout(3 downto 0);
720 vserial_symbit := r.serial_counter - "00010";
721 vserial_runlength := servaldout(7 downto 4);
722 vserial_valbit := servaldout(3 downto 0);
724 -- valuebit calculation
725 if(vfetching = '1') then
730 if(r.dec_state = symcheck) then
731 if(unsigned(r.reqbit_keep) >= unsigned(vcache_symbit) )then
732 vint_minusv := to_integer(unsigned(vcache_symbit));
736 elsif(r.dec_state = serialfinish) then
737 vint_minusv := to_integer(unsigned(vserial_symbit));
738 elsif(r.dec_state = valout) then
739 vint_minusv := to_integer(unsigned(r.valbit_keep));
744 v.valuebit := std_logic_vector(to_unsigned((to_integer(unsigned(r.valuebit)) + vint_plusv - vint_minusv), 6));
746 -- Padding bit for Markers
747 if(r.fetch_state = markermode or r.preg.through_bit = '1') then
748 if((r.valuebit = "000001" and r.fetch_reg(0) = '1')
749 or (r.valuebit = "000010" and r.fetch_reg(1 downto 0) = "11")
750 or (r.valuebit = "000011" and r.fetch_reg(2 downto 0) = "111")
751 or (r.valuebit = "000100" and r.fetch_reg(3 downto 0) = "1111")
752 or (r.valuebit = "000101" and r.fetch_reg(4 downto 0) = "11111")
753 or (r.valuebit = "000110" and r.fetch_reg(5 downto 0) = "111111")
754 or (r.valuebit = "000111" and r.fetch_reg(6 downto 0) = "1111111")) then
755 v.valuebit := "000000";
758 if(r.dec_state = symreq)then
759 if(r.valuebit >= const_6b8)then
760 v.reqbit_keep := "1000";
762 v.reqbit_keep := r.valuebit(3 downto 0);
766 -- valbit_keep register calculation
767 if(r.dec_state = serialfinish)then
768 v.valbit_keep := vserial_valbit;
769 elsif(r.dec_state = symcheck)then
770 v.valbit_keep := vcache_valbit;
773 -- shiftnum calculation
774 vint_valuebit := to_integer(unsigned(r.valuebit));
775 vint_valbkp := to_integer(unsigned(r.valbit_keep));
776 vint_sercnt := to_integer(unsigned(r.serial_counter));
779 if(r.dec_state = symreq)then
780 if(vint_valuebit >= 8)then
781 vintshift := vint_valuebit - 8;
785 elsif(r.dec_state = valout)then
786 vintshift := vint_valuebit - vint_valbkp;
787 elsif(r.dec_state = serialcheck)then
788 vintshift := 1 + vint_valuebit - vint_sercnt;
789 elsif(r.dec_state = serialwait)then
790 vintshift := 1 + vint_valuebit - vint_sercnt;
792 vshiftnum := std_logic_vector(to_unsigned(vintshift,5));
794 -- shifter instantiation
795 vtmpshiftout := std_logic_vector(shift_right(unsigned(r.fetch_reg), vintshift));
796 vshiftout := vtmpshiftout(15 downto 0);
799 v.memaddcnt := "000000";
800 elsif(((r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000") and vcache_runlength = "0000" and vcache_valbit = "0000")
801 or (r.dec_state = serialfinish and vserial_runlength = "0000" and vserial_valbit = "0000")) then
802 v.memaddcnt := "111111";
803 elsif(r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
804 v.memaddcnt := r.memaddcnt + vcache_runlength + "0001";
805 elsif(r.dec_state = serialfinish)then
806 v.memaddcnt := r.memaddcnt + vserial_runlength + "0001";
809 -- id, dcac calculation
810 if(r.dec_state = valout and r.memaddcnt = "000000")then
812 elsif(r.dec_state = valout and r.memaddcnt = "111111") then
816 if(r.dec_state = valout and r.memaddcnt = "111111") then
817 v.idcounter := r.idcounter + '1';
818 if(r.preg.sampf = '0')then
819 if(v.idcounter = "0110")then
820 v.idcounter := "0000";
823 if(v.idcounter = "1000")then
824 v.idcounter := "0000";
828 if(r.preg.sampf = '0')then
829 if(r.idcounter < const_4b4 )then
832 elsif(r.idcounter < const_4b5)then
840 if(r.idcounter < const_4b4)then
843 elsif(r.idcounter < const_4b6)then
853 if(r.dec_state = symreq)then
855 if(vint_valuebit >7)then
856 vdccacheadd := vid & '0' & vshiftout(7 downto 0);
857 elsif(vint_valuebit = 7)then
858 vdccacheadd := vid & "10" & vshiftout(6 downto 0);
859 elsif(vint_valuebit = 6)then
860 vdccacheadd := vid & "110" & vshiftout(5 downto 0);
861 elsif(vint_valuebit = 5)then
862 vdccacheadd := vid & "1110" & vshiftout(4 downto 0);
863 elsif(vint_valuebit = 4)then
864 vdccacheadd := vid & "11110" & vshiftout(3 downto 0);
865 elsif(vint_valuebit = 3)then
866 vdccacheadd := vid & "111110" & vshiftout(2 downto 0);
867 elsif(vint_valuebit = 2)then
868 vdccacheadd := vid & "1111110" & vshiftout(1 downto 0);
869 elsif(vint_valuebit = 1)then
870 vdccacheadd := vid & "11111110" & vshiftout(0);
874 if(vint_valuebit >7)then
875 vaccacheadd := vid & '0' & vshiftout(7 downto 0);
876 elsif(vint_valuebit = 7)then
877 vaccacheadd := vid & "10" & vshiftout(6 downto 0);
878 elsif(vint_valuebit = 6)then
879 vaccacheadd := vid & "110" & vshiftout(5 downto 0);
880 elsif(vint_valuebit = 5)then
881 vaccacheadd := vid & "1110" & vshiftout(4 downto 0);
882 elsif(vint_valuebit = 4)then
883 vaccacheadd := vid & "11110" & vshiftout(3 downto 0);
884 elsif(vint_valuebit = 3)then
885 vaccacheadd := vid & "111110" & vshiftout(2 downto 0);
886 elsif(vint_valuebit = 2)then
887 vaccacheadd := vid & "1111110" & vshiftout(1 downto 0);
888 elsif(vint_valuebit = 1)then
889 vaccacheadd := vid & "11111110" & vshiftout(0);
896 vserial_mask := "00000000000000000";
897 if(r.serial_counter = "01001")then
898 vserial_mask := "00000000011111111";
899 elsif(r.serial_counter = "01010")then
900 vserial_mask := "00000000111111111";
901 elsif(r.serial_counter = "01011")then
902 vserial_mask := "00000001111111111";
903 elsif(r.serial_counter = "01100")then
904 vserial_mask := "00000011111111111";
905 elsif(r.serial_counter = "01101")then
906 vserial_mask := "00000111111111111";
907 elsif(r.serial_counter = "01110")then
908 vserial_mask := "00001111111111111";
909 elsif(r.serial_counter = "01111")then
910 vserial_mask := "00011111111111111";
911 elsif(r.serial_counter = "10000")then
912 vserial_mask := "00111111111111111";
913 elsif(r.serial_counter = "10001")then
914 vserial_mask := "01111111111111111";
916 vserial_tmpin := ('0' & vshiftout) and vserial_mask;
917 if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
918 vsermaxadd := r.dcac & vid & r.serial_counter;
921 if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
922 vseroffadd := r.dcac & vid & r.serial_counter;
925 if(signed(vserial_tmpin) <= to_01(signed(sermaxdout)))then
926 vserial_judge := '1';
928 vserial_tmpadd := std_logic_vector(signed(vserial_tmpin) + signed(seroffdout));
929 if(r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
930 vservaladd := r.dcac & vid & vserial_tmpadd(7 downto 0);
932 if(r.dec_state = serialwait or r.dec_state = serialcheck or r.dec_state = serialfinish)then
936 if(r.dec_state = symreq)then
937 v.serial_counter := "01001";
938 elsif((r.dec_state = symcheck and vint_valuebit > 8)
939 or (r.dec_state = serialcheck and to_integer(unsigned(r.serial_counter))<= vint_valuebit)
940 or (r.dec_state = serialwait and to_integer(unsigned(r.serial_counter))<= vint_valuebit ))
941 or (r.dec_state = serialcheck and vserial_judge = '1')then
942 v.serial_counter := r.serial_counter + 1;
945 -- Sign extention & zigzag memory access
946 --debug_sign_exin <= vshiftout(10 downto 0);
947 vkdata := sign_ex(vshiftout(10 downto 0), r.valbit_keep );
948 if(r.dec_state = valout and r.dcac = '1')then
949 if(vcompid = "00")then
950 vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc0));
952 elsif(vcompid = "01")then
953 vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc1));
956 vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc2));
960 if(r.dec_state = valout)then
966 if(vstartgen = '1' or r.marker_reg = x"D9")then
967 v.lastdc0 := (others => '0');
968 v.lastdc1 := (others => '0');
969 v.lastdc2 := (others => '0');
972 -- Decord part state-machine
973 -- state = symreq, symcheck, valout, symng, symokvalng, serialwait, serialcheck, serialfinish, standby
974 vint_csymbit := 0; vint_reqbitkp := 0; vint_cvalbit := 0;
975 vint_sersym := 0; vint_serval := 0;
977 if notx(vcache_symbit) then
978 vint_csymbit := to_integer(unsigned(vcache_symbit));
980 if notx(r.reqbit_keep) then
981 vint_reqbitkp := to_integer(unsigned(r.reqbit_keep));
983 if notx(vcache_valbit) then
984 vint_cvalbit := to_integer(unsigned(vcache_valbit));
986 if notx(vserial_symbit) then
987 vint_sersym := to_integer(unsigned(vserial_symbit));
989 if notx(vserial_valbit) then
990 vint_serval := to_integer(unsigned(vserial_valbit));
995 if(kready = '1' and r.valuebit /= "000000")then
996 v.dec_state := symreq;
999 if(r.valuebit = "000000")then
1000 v.dec_state := symreq;
1002 v.dec_state := symcheck;
1005 if(vint_csymbit /= 0 and vint_csymbit <= vint_reqbitkp and vint_csymbit + vint_cvalbit <= vint_valuebit )then
1006 v.dec_state := valout;
1007 elsif(vint_csymbit /= 0 and vint_csymbit <= vint_reqbitkp and vint_csymbit + vint_cvalbit > vint_valuebit )then
1008 v.dec_state := symokvalng;
1009 elsif(vint_reqbitkp = 8 and vint_csymbit = 0 and vint_valuebit >= 9)then
1010 v.dec_state := serialcheck;
1011 elsif(vint_reqbitkp = 8 and vint_csymbit = 0 and vint_valuebit < 9)then
1012 v.dec_state := serialwait;
1013 elsif(vint_reqbitkp < 8 and (vint_csymbit = 0 or vint_csymbit > vint_reqbitkp))then
1014 v.dec_state := symng;
1017 if(vint_reqbitkp = vint_valuebit)then
1018 v.dec_state := symng;
1020 v.dec_state := symreq;
1023 if(r.memaddcnt = "111111")then
1024 v.dec_state := standby;
1026 v.dec_state := symreq;
1029 if(vint_valbkp <= vint_valuebit)then
1030 v.dec_state := valout;
1032 v.dec_state := symokvalng;
1035 if(vint_sercnt > vint_valuebit) then
1036 v.dec_state := serialwait;
1038 v.dec_state := serialcheck;
1041 if(vserial_judge = '1')then
1042 v.dec_state := serialfinish;
1043 elsif(vint_sercnt > vint_valuebit)then
1044 v.dec_state := serialwait;
1046 v.dec_state := serialcheck;
1048 when serialfinish =>
1049 if(vint_valuebit < vint_sersym + vint_serval)then
1050 v.dec_state := symokvalng;
1052 v.dec_state := valout;
1058 if rst = '0' or vstartgen = '1' then
1059 v.hreg.getscan := '0';
1060 v.hreg.rdscan := '0';
1063 v.hreg.getcache := '0';
1064 v.hreg.rdacache := '0';
1065 v.hreg.rddcache := '0';
1066 v.hreg.haddkeep := (others => '0');
1067 v.hreg.getmax := '0';
1068 v.hreg.rdmax := '0';
1069 v.hreg.getoffset := '0';
1070 v.hreg.rdoffset := '0';
1071 v.hreg.getval := '0';
1072 v.hreg.rdval := '0';
1073 v.fetch_state := memwait;
1074 v.dec_state := standby;
1075 v.fifo_rp := (others => '0');
1076 v.fifo_wp := (others => '0');
1077 v.fetch_reg := (others => '0');
1078 v.marker_reg := (others => '0');
1079 v.valuebit := (others => '0');
1080 v.byteselect := (others => '0');
1081 v.reqbit_keep := (others => '0');
1082 v.valbit_keep := (others => '0');
1084 v.serial_counter := (others => '0');
1085 v.idcounter := (others => '0');
1086 v.memaddcnt := (others => '0');
1087 v.lastdc0 := (others => '0');
1088 v.lastdc1 := (others => '0');
1089 v.lastdc2 := (others => '0');
1090 v.byte3keep := (others => '0');
1093 v.skipcnt := (others => '0');
1096 v.preg.sampf := '0';
1097 v.preg.xmcumax := (others => '0');
1098 v.preg.ymcumax := (others => '0');
1099 v.preg.incaddy := (others => '0');
1100 v.preg.incaddmcux := (others => '0');
1101 v.preg.incaddmcuy := (others => '0');
1102 v.preg.fbstartadd := (others => '0');
1103 v.preg.through_bit := '0';
1104 v.preg.hardonly := '0';
1110 write_en_fifo <= r.hreg.getscan;
1111 write_pointer_fifo <= r.fifo_wp;
1112 data_in_fifo <= ahbsi.hwdata;
1113 read_en_fifo <= '1';
1114 read_pointer_fifo <= r.fifo_rp;
1116 dccachedin <= ahbsi.hwdata(7 downto 0);
1117 dccacheadd <= vdccacheadd;
1119 dccachewr <= vdccachewr;
1120 accachedin <= ahbsi.hwdata(11 downto 0);
1121 accacheadd <= vaccacheadd;
1123 accachewr <= vaccachewr;
1124 sermaxdin <= ahbsi.hwdata(16 downto 0);
1125 sermaxadd <= vsermaxadd;
1127 sermaxwr <= vsermaxwr;
1128 seroffdin <= ahbsi.hwdata(16 downto 0);
1129 seroffadd <= vseroffadd;
1131 seroffwr <= vseroffwr;
1132 seroffdin <= ahbsi.hwdata(16 downto 0);
1133 servaladd <= vservaladd;
1135 servalwr <= vservalwr;
1136 servaldin <= ahbsi.hwdata(7 downto 0);
1138 jpg_setting.xmcumax <= r.preg.xmcumax;
1139 jpg_setting.ymcumax <= r.preg.ymcumax;
1140 jpg_setting.incaddy <= r.preg.incaddy;
1141 jpg_setting.incaddmcux <= r.preg.incaddmcux;
1142 jpg_setting.incaddmcuy <= r.preg.incaddmcuy;
1143 jpg_setting.fbstartadd <= r.preg.fbstartadd;
1144 startgen <= vstartgen;
1145 jpg_setting.samp_fact <= r.preg.sampf;
1147 kstrobeq <= r.hreg.getq;
1148 kdataq <= ahbsi.hwdata(7 downto 0);
1150 apbo.prdata <= vprdata;
1152 ahbso.hrdata <= vhrdata;
1155 kstrobe <= vkstrobe;
1156 kaddress <= r.memaddcnt;
1160 -- Workaround for ISE
1161 -- I don't know why ISE needs this.
1162 -- Quartus works correctly without this sentense
1163 debug_memaddcnt <= v.memaddcnt;
1168 apbo.pirq <= (others => '0');
1169 apbo.pindex <= pindex;
1170 apbo.pconfig <= pconfig;
1171 ahbso.hconfig <= shconfig;
1172 ahbso.hresp <= "00";
1173 ahbso.hsplit <= (others => '0');
1174 ahbso.hcache <= '0';
1175 ahbso.hready <= '1';
1176 ahbso.hindex <= shindex;
1181 if rising_edge(clk) then