workaround for xilinx trivial bug (huff.vhd)

diff --git a/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/.config b/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/.config
index 17dfd20..6f67869 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/.config
+++ b/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/.config
@@ -77,8 +77,12 @@ CONFIG_PROC_NUM=1
 # Integer unit                                           
 #
 CONFIG_IU_NWINDOWS=8
-# CONFIG_IU_V8MULDIV is not set
-# CONFIG_IU_BP is not set
+CONFIG_IU_V8MULDIV=y
+# CONFIG_IU_MUL_LATENCY_2 is not set
+# CONFIG_IU_MUL_LATENCY_4 is not set
+CONFIG_IU_MUL_LATENCY_5=y
+# CONFIG_IU_MUL_MAC is not set
+CONFIG_IU_BP=y
 # CONFIG_IU_SVT is not set
 CONFIG_IU_LDELAY=1
 CONFIG_IU_WATCHPOINTS=4

diff --git a/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/config.vhd b/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/config.vhd
index 8e5515f..df0776c 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/config.vhd
+++ b/grlib-gpl-1.0.22-b4095/designs/leon3-gr-xc3s-1500-mjpeg/config.vhd
@@ -30,9 +30,9 @@ package config is
   constant CFG_LEON3 : integer := 1;
   constant CFG_NCPU : integer := (1);
   constant CFG_NWIN : integer := (8);
-  constant CFG_V8 : integer := 0;
+  constant CFG_V8 : integer := 2;
   constant CFG_MAC : integer := 0;
-  constant CFG_BP : integer := 0;
+  constant CFG_BP : integer := 1;
   constant CFG_SVT : integer := 0;
   constant CFG_RSTADDR : integer := 16#00000#;
   constant CFG_LDDEL : integer := (1);

diff --git a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd
index 423acf6..8b1d546 100644 (file)
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd
@@ -181,18 +181,7 @@ begin
            tmp := to_integer(signed('0' & data(10 downto 0)));
            outb := std_logic_vector(to_signed(tmp, 12));
        end if;
---   elsif(bitnum = "1100")then
---       if(data(11) = '0)then
---           tmp := to_integer(signed('1' & data(11 downto 0))) + 1;
---           outb := std_logic_vector(to_signed(tmp, 12));
---       else
---           tmp := to_integer(signed('0' & data(11 downto 0)));
---           outb := std_logic_vector(to_signed(tmp, 12));
---       end if;
---   elsif(bitnum ="0000")then
---       outb := (others => '0');   
    else
---       report "sign extention over flow" severity note;
        outb := (others => '0');
    end if;
    
@@ -240,13 +229,11 @@ type control_reg is record
    hreg : ahbs_reg;
    fifo_rp : std_logic_vector(8 downto 0);
    fifo_wp : std_logic_vector(8 downto 0);
-   counter : std_logic_vector(1 downto 0);
    fetch_reg : std_logic_vector(31 downto 0);
    marker_reg : std_logic_vector(7 downto 0);
    valuebit : std_logic_vector(5 downto 0);
    byteselect : std_logic_vector(1 downto 0);
    reqbit_keep : std_logic_vector(3 downto 0);
-   runlength_keep : std_logic_vector(3 downto 0);
    valbit_keep : std_logic_vector(3 downto 0);
    dcac : std_logic;
    serial_counter : std_logic_vector(4 downto 0);
@@ -289,14 +276,7 @@ signal servaldin : std_logic_vector(7 downto 0);
 signal servaldout : std_logic_vector(7 downto 0);
 signal servalen,servalwr : std_logic;
 
-signal debug_shiftnum : std_logic_vector(4 downto 0);
-signal debug_sign_exin : std_logic_vector(10 downto 0);
-signal debug_serialin : std_logic_vector(16 downto 0);
-signal debug_vcache_symbit : std_logic_vector(4 downto 0);
-signal debug_vcache_runlength : std_logic_vector(3 downto 0);
-signal debug_vcache_valbit : std_logic_vector(3 downto 0);
-signal debug_va : std_logic;
-signal debug_fifoready : std_logic;
+signal debug_memaddcnt : std_logic_vector(5 downto 0);
 
 begin
    ramscan : syncram_2p generic map(tech => memtech, abits => 9, dbits => 32,sepclk => 0)
@@ -364,7 +344,6 @@ comb_fetch : process(r, rst, ahbsi, apbi, data_out_fifo, dccachedout, accachedou
    variable vint_sercnt : integer;
    variable vshiftout : std_logic_vector(15 downto 0);
    variable vtmpshiftout : std_logic_vector(31 downto 0);
-   variable va : std_logic;
    variable vid : std_logic;
    variable vcompid : std_logic_vector(1 downto 0);
    variable vkstrobe : std_logic;
@@ -559,7 +538,7 @@ end if;
     else 
         vsready := '1';
     end if;   
-    debug_fifoready <= vsready;
+
    
     vhrdata := vsready & "0000000000000000000000000000000";
     if(r.hreg.rdscan = '1')then
@@ -784,12 +763,10 @@ end if;
        end if;
    end if;
    
- -- runlength_keep valbit_keep register calculation
+ -- valbit_keep register calculation
    if(r.dec_state = serialfinish)then
-       v.runlength_keep := vserial_runlength;
        v.valbit_keep := vserial_valbit;
    elsif(r.dec_state = symcheck)then
-       v.runlength_keep := vcache_runlength;
        v.valbit_keep := vcache_valbit;
    end if;
  
@@ -815,28 +792,15 @@ end if;
    vshiftnum :=  std_logic_vector(to_unsigned(vintshift,5)); 
       
 -- shifter instantiation
-debug_shiftnum <= vshiftnum;
    vtmpshiftout := std_logic_vector(shift_right(unsigned(r.fetch_reg), vintshift));
    vshiftout := vtmpshiftout(15 downto 0);
    
--- write memory address generation
-   if (r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
-       va := '1';
-   else
-       va := '0';
-   end if;
-debug_va <= va;
-debug_vcache_symbit <= vcache_symbit;
-debug_vcache_runlength <= vcache_runlength;
-debug_vcache_valbit <= vcache_valbit;
-
---   if((va = '1' or r.dec_state = serialfinish) and r.memaddcnt = "111111")then
    if(r.dcac = '1')then
        v.memaddcnt := "000000";
-   elsif((va = '1' and vcache_runlength = "0000" and vcache_valbit = "0000")
+   elsif(((r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000") and vcache_runlength = "0000" and vcache_valbit = "0000")
          or (r.dec_state = serialfinish and vserial_runlength = "0000" and vserial_valbit = "0000")) then
        v.memaddcnt := "111111";
-   elsif(va = '1')then
+   elsif(r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
        v.memaddcnt := r.memaddcnt + vcache_runlength + "0001";
    elsif(r.dec_state = serialfinish)then
        v.memaddcnt := r.memaddcnt + vserial_runlength + "0001";
@@ -950,7 +914,6 @@ debug_vcache_valbit <= vcache_valbit;
        vserial_mask := "01111111111111111";
    end if;
    vserial_tmpin := ('0' & vshiftout) and vserial_mask;
-   debug_serialin <= vserial_tmpin;
    if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
        vsermaxadd := r.dcac & vid & r.serial_counter;
    end if;
@@ -980,7 +943,7 @@ debug_vcache_valbit <= vcache_valbit;
    end if;
    
  -- Sign extention & zigzag memory access
- debug_sign_exin <= vshiftout(10 downto 0);
+ --debug_sign_exin <= vshiftout(10 downto 0);
    vkdata := sign_ex(vshiftout(10 downto 0), r.valbit_keep );
    if(r.dec_state = valout and r.dcac = '1')then
        if(vcompid = "00")then
@@ -1111,13 +1074,11 @@ end if;
        v.dec_state := standby;
        v.fifo_rp := (others => '0');
        v.fifo_wp := (others => '0');
-       v.counter := (others => '0');
        v.fetch_reg := (others => '0');
        v.marker_reg := (others => '0');
        v.valuebit := (others => '0');
        v.byteselect := (others => '0');
        v.reqbit_keep := (others => '0');
-       v.runlength_keep := (others => '0');
        v.valbit_keep := (others => '0');
        v.dcac := '1';
        v.serial_counter := (others => '0');
@@ -1195,6 +1156,13 @@ end if;
    kaddress <= r.memaddcnt;
    kaddq <= vkaddq;
    krdq <= vkrdq;
+   
+ -- Workaround for ISE
+ -- I don't know why ISE needs this.
+ -- Quartus works correctly without this sentense
+   debug_memaddcnt <= v.memaddcnt;
+ 
+   
    end process;
    
    apbo.pirq <= (others => '0');