kready2 : in std_logic;
kstrobe2 : out std_logic;
kdata2 : out std_logic_vector(15 downto 0);
- error : out std_logic
+ error : out std_logic;
+ startgen : in std_logic
);
end;
yram1 : syncram generic map(tech => memtech, abits => 6, dbits => 16)
port map( clk, m1address, m1datain, m1dataout, m1enable, m1write);
-comb : process (r, rst, kstrobe1, kdata1, kready2, m0dataout, m1dataout)
+comb : process (r, rst, kstrobe1, kdata1, kready2, m0dataout, m1dataout, startgen)
variable v : control_reg;
variable vkready1 : std_logic;
variable verror : std_logic;
end if;
-- reset part
- if rst = '0' then
+ if rst = '0' or startgen = '1' then
v.swf := mem0;
v.swb := mem0;
v.mem0state := empty;
tmp := to_integer(signed('0' & data(10 downto 0)));
outb := std_logic_vector(to_signed(tmp, 12));
end if;
+-- elsif(bitnum = "1100")then
+-- if(data(11) = '0)then
+-- tmp := to_integer(signed('1' & data(11 downto 0))) + 1;
+-- outb := std_logic_vector(to_signed(tmp, 12));
+-- else
+-- tmp := to_integer(signed('0' & data(11 downto 0)));
+-- outb := std_logic_vector(to_signed(tmp, 12));
+-- end if;
+-- elsif(bitnum ="0000")then
+-- outb := (others => '0');
else
+-- report "sign extention over flow" severity note;
outb := (others => '0');
end if;
hreg : ahbs_reg;
fifo_rp : std_logic_vector(8 downto 0);
fifo_wp : std_logic_vector(8 downto 0);
+ counter : std_logic_vector(1 downto 0);
fetch_reg : std_logic_vector(31 downto 0);
marker_reg : std_logic_vector(7 downto 0);
valuebit : std_logic_vector(5 downto 0);
byteselect : std_logic_vector(1 downto 0);
reqbit_keep : std_logic_vector(3 downto 0);
+ runlength_keep : std_logic_vector(3 downto 0);
valbit_keep : std_logic_vector(3 downto 0);
dcac : std_logic;
serial_counter : std_logic_vector(4 downto 0);
signal servaldout : std_logic_vector(7 downto 0);
signal servalen,servalwr : std_logic;
-signal debug_memaddcnt : std_logic_vector(5 downto 0);
+signal debug_shiftnum : std_logic_vector(4 downto 0);
+signal debug_sign_exin : std_logic_vector(10 downto 0);
+signal debug_serialin : std_logic_vector(16 downto 0);
+signal debug_vcache_symbit : std_logic_vector(4 downto 0);
+signal debug_vcache_runlength : std_logic_vector(3 downto 0);
+signal debug_vcache_valbit : std_logic_vector(3 downto 0);
+signal debug_va : std_logic;
+signal debug_fifoready : std_logic;
begin
ramscan : syncram_2p generic map(tech => memtech, abits => 9, dbits => 32,sepclk => 0)
variable vint_sercnt : integer;
variable vshiftout : std_logic_vector(15 downto 0);
variable vtmpshiftout : std_logic_vector(31 downto 0);
+ variable va : std_logic;
variable vid : std_logic;
variable vcompid : std_logic_vector(1 downto 0);
variable vkstrobe : std_logic;
else
vsready := '1';
end if;
-
+ debug_fifoready <= vsready;
vhrdata := vsready & "0000000000000000000000000000000";
if(r.hreg.rdscan = '1')then
end if;
end if;
- -- valbit_keep register calculation
+ -- runlength_keep valbit_keep register calculation
if(r.dec_state = serialfinish)then
+ v.runlength_keep := vserial_runlength;
v.valbit_keep := vserial_valbit;
elsif(r.dec_state = symcheck)then
+ v.runlength_keep := vcache_runlength;
v.valbit_keep := vcache_valbit;
end if;
vshiftnum := std_logic_vector(to_unsigned(vintshift,5));
-- shifter instantiation
+debug_shiftnum <= vshiftnum;
vtmpshiftout := std_logic_vector(shift_right(unsigned(r.fetch_reg), vintshift));
vshiftout := vtmpshiftout(15 downto 0);
+-- write memory address generation
+ if (r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
+ va := '1';
+ else
+ va := '0';
+ end if;
+debug_va <= va;
+debug_vcache_symbit <= vcache_symbit;
+debug_vcache_runlength <= vcache_runlength;
+debug_vcache_valbit <= vcache_valbit;
+
+-- if((va = '1' or r.dec_state = serialfinish) and r.memaddcnt = "111111")then
if(r.dcac = '1')then
v.memaddcnt := "000000";
- elsif(((r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000") and vcache_runlength = "0000" and vcache_valbit = "0000")
+ elsif((va = '1' and vcache_runlength = "0000" and vcache_valbit = "0000")
or (r.dec_state = serialfinish and vserial_runlength = "0000" and vserial_valbit = "0000")) then
v.memaddcnt := "111111";
- elsif(r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
+ elsif(va = '1')then
v.memaddcnt := r.memaddcnt + vcache_runlength + "0001";
elsif(r.dec_state = serialfinish)then
v.memaddcnt := r.memaddcnt + vserial_runlength + "0001";
vserial_mask := "01111111111111111";
end if;
vserial_tmpin := ('0' & vshiftout) and vserial_mask;
+ debug_serialin <= vserial_tmpin;
if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
vsermaxadd := r.dcac & vid & r.serial_counter;
end if;
end if;
-- Sign extention & zigzag memory access
- --debug_sign_exin <= vshiftout(10 downto 0);
+ debug_sign_exin <= vshiftout(10 downto 0);
vkdata := sign_ex(vshiftout(10 downto 0), r.valbit_keep );
if(r.dec_state = valout and r.dcac = '1')then
if(vcompid = "00")then
v.hreg.rdoffset := '0';
v.hreg.getval := '0';
v.hreg.rdval := '0';
+ v.hreg.hselff := '0';
+ v.hreg.hreadyff := '0';
v.fetch_state := memwait;
v.dec_state := standby;
v.fifo_rp := (others => '0');
v.fifo_wp := (others => '0');
+ v.counter := (others => '0');
v.fetch_reg := (others => '0');
v.marker_reg := (others => '0');
v.valuebit := (others => '0');
v.byteselect := (others => '0');
v.reqbit_keep := (others => '0');
+ v.runlength_keep := (others => '0');
v.valbit_keep := (others => '0');
v.dcac := '1';
v.serial_counter := (others => '0');
kaddress <= r.memaddcnt;
kaddq <= vkaddq;
krdq <= vkrdq;
-
- -- Workaround for ISE
- -- I don't know why ISE needs this.
- -- Quartus works correctly without this sentense
- debug_memaddcnt <= v.memaddcnt;
-
-
end process;
apbo.pirq <= (others => '0');
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2011, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+-- Entity: huff
+-- File: huff.vhd
+-- Author: Kenichi Kurimoto
+-- Description: AMBA slave interface and huffman decoder for jpeg decode
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+library kuri;
+use kuri.mjpeg.all;
+
+entity huff is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ kready : in std_logic;
+ kstrobe : out std_logic;
+ kdata : out std_logic_vector(11 downto 0);
+ kaddress : out std_logic_vector(5 downto 0);
+ jpg_setting : out jpg_set_type;
+ error : in std_logic_vector(2 downto 0);
+ startgen : out std_logic;
+ kstrobeq : out std_logic;
+ kdataq : out std_logic_vector(7 downto 0);
+ kaddq : out std_logic_vector(7 downto 0);
+ krddataq : in std_logic_vector(7 downto 0);
+ krdq : out std_logic
+ );
+end;
+
+architecture rtl of huff is
+
+constant shconfig : ahb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, hirq),
+ 4 => ahb_membar(haddr, '0', '0', hmask),
+ others => zero32);
+
+constant pconfig : apb_config_type := (
+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
+ 1 => apb_iobar(paddr, pmask));
+
+constant fdepth : integer := 512;
+
+constant const_4b4 : std_logic_vector(3 downto 0) := "0100";
+constant const_4b5 : std_logic_vector(3 downto 0) := "0101";
+constant const_4b6 : std_logic_vector(3 downto 0) := "0110";
+constant const_6b8 : std_logic_vector(5 downto 0) := "001000";
+constant const_u6b24 : UNSIGNED(5 downto 0) := "011000";
+
+function sign_ex(data, bitnum : std_logic_vector) return std_logic_vector is
+ variable outb : std_logic_vector(11 downto 0);
+ variable minusjudge : std_logic;
+ variable tmp : integer;
+begin
+ minusjudge := '0';
+ if(bitnum = "0001")then
+ if(data(0) = '0')then
+ outb := "111111111111";
+ else
+ outb := "000000000001";
+ end if;
+ elsif(bitnum = "0010")then
+ if(data(1) = '0')then
+ tmp := to_integer(signed('1' & data(1 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(1 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "0011")then
+ if(data(2) = '0')then
+ tmp := to_integer(signed('1' & data(2 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(2 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "0100")then
+ if(data(3) = '0')then
+ tmp := to_integer(signed('1' & data(3 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(3 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "0101")then
+ if(data(4) = '0')then
+ tmp := to_integer(signed('1' & data(4 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(4 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "0110")then
+ if(data(5) = '0')then
+ tmp := to_integer(signed('1' & data(5 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(5 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "0111")then
+ if(data(6) = '0')then
+ tmp := to_integer(signed('1' & data(6 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(6 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "1000")then
+ if(data(7) = '0')then
+ tmp := to_integer(signed('1' & data(7 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(7 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "1001")then
+ if(data(8) = '0')then
+ tmp := to_integer(signed('1' & data(8 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(8 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "1010")then
+ if(data(9) = '0')then
+ tmp := to_integer(signed('1' & data(9 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(9 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+ elsif(bitnum = "1011")then
+ if(data(10) = '0')then
+ tmp := to_integer(signed('1' & data(10 downto 0))) + 1;
+ outb := std_logic_vector(to_signed(tmp, 12));
+ else
+ tmp := to_integer(signed('0' & data(10 downto 0)));
+ outb := std_logic_vector(to_signed(tmp, 12));
+ end if;
+-- elsif(bitnum = "1100")then
+-- if(data(11) = '0)then
+-- tmp := to_integer(signed('1' & data(11 downto 0))) + 1;
+-- outb := std_logic_vector(to_signed(tmp, 12));
+-- else
+-- tmp := to_integer(signed('0' & data(11 downto 0)));
+-- outb := std_logic_vector(to_signed(tmp, 12));
+-- end if;
+-- elsif(bitnum ="0000")then
+-- outb := (others => '0');
+ else
+-- report "sign extention over flow" severity note;
+ outb := (others => '0');
+ end if;
+
+ return(outb);
+end;
+
+type fstate_type is (memwait, bytefetch, ffmemwait, ffcheck, markermode);
+type dstate_type is (symreq, symcheck, valout, symng, symokvalng, serialwait, serialcheck, serialfinish, standby);
+
+type ahbs_reg is record
+ getscan : std_logic;
+ rdscan : std_logic;
+ getq : std_logic;
+ rdq : std_logic;
+ getcache : std_logic;
+ rdacache : std_logic;
+ rddcache : std_logic;
+ getmax : std_logic;
+ rdmax : std_logic;
+ getoffset : std_logic;
+ rdoffset : std_logic;
+ getval : std_logic;
+ rdval : std_logic;
+ hreadyff : std_logic;
+ hselff : std_logic;
+ haddkeep : std_logic_vector(15 downto 0);
+end record;
+
+type apbs_reg is record
+ sampf : std_logic;
+ xmcumax : std_logic_vector(5 downto 0);
+ ymcumax : std_logic_vector(4 downto 0);
+ incaddy : std_logic_vector(15 downto 0);
+ incaddmcux : std_logic_vector(15 downto 0);
+ incaddmcuy : std_logic_vector(10 downto 0);
+ fbstartadd : std_logic_vector(31 downto 0);
+ through_bit : std_logic;
+ hardonly : std_logic;
+end record;
+
+type control_reg is record
+ fetch_state : fstate_type;
+ dec_state : dstate_type;
+ preg : apbs_reg;
+ hreg : ahbs_reg;
+ fifo_rp : std_logic_vector(8 downto 0);
+ fifo_wp : std_logic_vector(8 downto 0);
+-- counter : std_logic_vector(1 downto 0);
+ fetch_reg : std_logic_vector(31 downto 0);
+ marker_reg : std_logic_vector(7 downto 0);
+ valuebit : std_logic_vector(5 downto 0);
+ byteselect : std_logic_vector(1 downto 0);
+ reqbit_keep : std_logic_vector(3 downto 0);
+-- runlength_keep : std_logic_vector(3 downto 0);
+ valbit_keep : std_logic_vector(3 downto 0);
+ dcac : std_logic;
+ serial_counter : std_logic_vector(4 downto 0);
+ idcounter : std_logic_vector(3 downto 0);
+ memaddcnt : std_logic_vector(5 downto 0);
+ lastdc0 : std_logic_vector(11 downto 0);
+ lastdc1 : std_logic_vector(11 downto 0);
+ lastdc2 : std_logic_vector(11 downto 0);
+ byte3keep : std_logic_vector(23 downto 0);
+ cntdown : std_logic;
+ capture : std_logic_vector(1 downto 0);
+ skipcnt : std_logic_vector(15 downto 0);
+end record;
+
+signal r, rin : control_reg;
+signal read_en_fifo, write_en_fifo : std_logic;
+signal read_pointer_fifo : std_logic_vector(8 downto 0);
+signal write_pointer_fifo : std_logic_vector(8 downto 0);
+signal data_out_fifo : std_logic_vector(31 downto 0);
+signal data_in_fifo : std_logic_vector(31 downto 0);
+
+signal dccacheadd : std_logic_vector(9 downto 0);
+signal dccachedin : std_logic_vector(7 downto 0);
+signal dccachedout : std_logic_vector(7 downto 0);
+signal dccacheen,dccachewr : std_logic;
+signal accacheadd : std_logic_vector(9 downto 0);
+signal accachedin : std_logic_vector(11 downto 0);
+signal accachedout : std_logic_vector(11 downto 0);
+signal accacheen,accachewr : std_logic;
+signal sermaxadd : std_logic_vector(6 downto 0);
+signal sermaxdin : std_logic_vector(16 downto 0);
+signal sermaxdout : std_logic_vector(16 downto 0);
+signal sermaxen,sermaxwr : std_logic;
+signal seroffadd : std_logic_vector(6 downto 0);
+signal seroffdin : std_logic_vector(16 downto 0);
+signal seroffdout : std_logic_vector(16 downto 0);
+signal seroffen,seroffwr : std_logic;
+signal servaladd : std_logic_vector(9 downto 0);
+signal servaldin : std_logic_vector(7 downto 0);
+signal servaldout : std_logic_vector(7 downto 0);
+signal servalen,servalwr : std_logic;
+
+signal debug_shiftnum : std_logic_vector(4 downto 0);
+signal debug_sign_exin : std_logic_vector(10 downto 0);
+signal debug_serialin : std_logic_vector(16 downto 0);
+signal debug_vcache_symbit : std_logic_vector(4 downto 0);
+signal debug_vcache_runlength : std_logic_vector(3 downto 0);
+signal debug_vcache_valbit : std_logic_vector(3 downto 0);
+signal debug_va : std_logic;
+signal debug_fifoready : std_logic;
+
+begin
+ ramscan : syncram_2p generic map(tech => memtech, abits => 9, dbits => 32,sepclk => 0)
+ port map( clk, read_en_fifo, read_pointer_fifo, data_out_fifo,
+ clk, write_en_fifo, write_pointer_fifo, data_in_fifo);
+ huffdccache : syncram generic map(tech => memtech, abits => 10, dbits => 8)
+ port map( clk, dccacheadd, dccachedin, dccachedout, dccacheen, dccachewr);
+ huffaccache : syncram generic map(tech => memtech, abits => 10, dbits => 12)
+ port map( clk, accacheadd, accachedin, accachedout, accacheen, accachewr);
+ serialmax : syncram generic map(tech => memtech, abits => 7, dbits => 17)
+ port map( clk, sermaxadd, sermaxdin, sermaxdout, sermaxen, sermaxwr);
+ serialoffset : syncram generic map(tech => memtech, abits => 7, dbits => 17)
+ port map( clk, seroffadd, seroffdin, seroffdout, seroffen, seroffwr);
+ serialval : syncram generic map(tech => memtech, abits => 10, dbits => 8)
+ port map( clk, servaladd, servaldin, servaldout, servalen, servalwr);
+
+
+comb_fetch : process(r, rst, ahbsi, apbi, data_out_fifo, dccachedout, accachedout, sermaxdout, seroffdout, servaldout, kready, error, krddataq)
+ variable v : control_reg;
+ variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
+ variable vsready : std_logic;
+ variable write_point : integer;
+ variable read_point : integer;
+ variable num_ele : integer;
+ variable apbwrite : std_logic;
+ variable vprdata : std_logic_vector(31 downto 0);
+ variable vhrdata : std_logic_vector(31 downto 0);
+ variable vwriting :std_logic;
+ variable vreading : std_logic;
+ variable vdccacheadd : std_logic_vector(9 downto 0);
+ variable vdccachewr : std_logic;
+ variable vaccacheadd : std_logic_vector(9 downto 0);
+ variable vaccachewr : std_logic;
+ variable vsermaxadd : std_logic_vector(6 downto 0);
+ variable vsermaxwr : std_logic;
+ variable vseroffadd : std_logic_vector(6 downto 0);
+ variable vseroffwr : std_logic;
+ variable vservaladd : std_logic_vector(9 downto 0);
+ variable vservalwr : std_logic;
+
+ variable vbytedata : std_logic_vector(7 downto 0);
+ variable vinsertdata : std_logic_vector(7 downto 0);
+ variable vbyte0, vbyte1, vbyte2, vbyte3 : std_logic_vector(7 downto 0);
+ variable vfetching : std_logic;
+
+ variable vcache_symbit : std_logic_vector(4 downto 0);
+ variable vcache_runlength : std_logic_vector(3 downto 0);
+ variable vcache_valbit : std_logic_vector(3 downto 0);
+
+ variable vint_plusv : integer;
+ variable vint_minusv : integer;
+
+ variable vserial_symbit : std_logic_vector(4 downto 0);
+ variable vserial_runlength : std_logic_vector(3 downto 0);
+ variable vserial_valbit : std_logic_vector(3 downto 0);
+ variable vserial_tmpin : std_logic_vector(16 downto 0);
+ variable vserial_mask : std_logic_vector(16 downto 0);
+ variable vserial_judge : std_logic;
+ variable vserial_tmpadd : std_logic_vector(16 downto 0);
+
+ variable vintshift : integer;
+ variable vshiftnum : std_logic_vector(4 downto 0);
+ variable vint_valuebit : integer;
+ variable vint_valbkp : integer;
+ variable vint_sercnt : integer;
+ variable vshiftout : std_logic_vector(15 downto 0);
+ variable vtmpshiftout : std_logic_vector(31 downto 0);
+-- variable va : std_logic;
+ variable vid : std_logic;
+ variable vcompid : std_logic_vector(1 downto 0);
+ variable vkstrobe : std_logic;
+ variable vkdata : std_logic_vector(11 downto 0);
+ variable vint_csymbit : integer;
+ variable vint_reqbitkp : integer;
+ variable vint_cvalbit : integer;
+ variable vint_sersym : integer;
+ variable vint_serval : integer;
+
+ variable vkaddq : std_logic_vector(7 downto 0);
+ variable vkrdq : std_logic;
+ variable vgetbyte : std_logic;
+ variable vstartgen : std_logic;
+ begin
+
+ v := r;
+ virq := (others => '0');
+ vdccachewr := '0'; vdccacheadd := (others => '0');
+ vaccachewr := '0'; vaccacheadd := (others => '0');
+ vsermaxwr := '0'; vsermaxadd := (others => '0');
+ vseroffwr := '0'; vseroffadd := (others => '0');
+ vservalwr := '0'; vservaladd := (others => '0');
+ vkaddq := (others => '0'); vkrdq := '0';
+ vserial_judge := '0';
+ vkstrobe := '0'; vstartgen := '0';
+
+-- apb controle part
+ apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
+ vprdata := (others => '0');
+ case apbi.paddr(5 downto 2) is
+ when "0000" =>
+ if apbwrite = '1' then
+ v.preg.fbstartadd := apbi.pwdata(31 downto 0);
+ end if;
+ vprdata := r.preg.fbstartadd(31 downto 0);
+ when "0001" =>
+ if apbwrite = '1' then
+ v.preg.sampf := apbi.pwdata(22);
+ v.preg.ymcumax := apbi.pwdata(21 downto 17);
+ v.preg.xmcumax := apbi.pwdata(16 downto 11);
+ v.preg.incaddmcuy := apbi.pwdata(10 downto 0);
+ end if;
+ vprdata := "000000000" & r.preg.sampf & r.preg.ymcumax & r.preg.xmcumax & r.preg.incaddmcuy;
+ when "0010" =>
+ if apbwrite = '1' then
+ v.preg.incaddy := apbi.pwdata(31 downto 16);
+ v.preg.incaddmcux := apbi.pwdata(15 downto 0);
+ end if;
+ vprdata := r.preg.incaddy & r.preg.incaddmcux;
+ when "0011" =>
+ if apbwrite = '1' then
+ if apbi.pwdata(31) = '1' then
+ vstartgen := '1';
+ end if;
+ v.preg.through_bit := apbi.pwdata(15);
+ v.preg.hardonly := apbi.pwdata(14);
+ v.marker_reg := apbi.pwdata(23 downto 16);
+ end if;
+ vprdata := "00000000" & r.marker_reg & r.preg.through_bit & r.preg.hardonly &"00000000000000" ;
+ when others =>
+ end case;
+
+if(r.hreg.getcache = '1' or r.hreg.hreadyff = '0')then
+ if (r.hreg.haddkeep(15) = '1') then
+ vdccachewr := '1';
+ vdccacheadd := r.hreg.haddkeep(11 downto 2);
+ else
+ vaccachewr := '1';
+ vaccacheadd := r.hreg.haddkeep(11 downto 2);
+ end if;
+else
+ vdccacheadd := ahbsi.haddr(11 downto 2);
+ vaccacheadd := ahbsi.haddr(11 downto 2);
+end if;
+if(r.hreg.getq = '1' or r.hreg.hreadyff = '0')then
+ vkaddq := r.hreg.haddkeep(9 downto 2);
+else
+ vkaddq := ahbsi.haddr(9 downto 2);
+ vkrdq := '1';
+end if;
+if(r.hreg.getmax = '1' or r.hreg.hreadyff = '0')then
+ vsermaxwr := '1';
+ vsermaxadd := r.hreg.haddkeep(8 downto 2);
+else
+ vsermaxadd := ahbsi.haddr(8 downto 2);
+end if;
+if(r.hreg.getoffset = '1' or r.hreg.hreadyff = '0')then
+ vseroffwr := '1';
+ vseroffadd := r.hreg.haddkeep(8 downto 2);
+else
+ vseroffadd := ahbsi.haddr(8 downto 2);
+end if;
+if(r.hreg.getval = '1' or r.hreg.hreadyff = '0')then
+ vservalwr := '1';
+ vservaladd := r.hreg.haddkeep(11 downto 2);
+else
+ vservaladd := ahbsi.haddr(11 downto 2);
+end if;
+
+if(ahbsi.hready = '1' ) then
+ v.hreg.getscan := '0';
+ v.hreg.rdscan := '0';
+ v.hreg.getq := '0';
+ v.hreg.rdq := '0';
+ v.hreg.getcache := '0';
+ v.hreg.rdacache := '0';
+ v.hreg.rddcache := '0';
+ v.hreg.getmax := '0';
+ v.hreg.rdmax := '0';
+ v.hreg.getoffset := '0';
+ v.hreg.rdoffset := '0';
+ v.hreg.getval := '0';
+ v.hreg.rdval := '0';
+
+ v.hreg.hselff := ahbsi.hsel(shindex) and ahbsi.htrans(1);
+ vwriting := ahbsi.hwrite and v.hreg.hselff;
+ vreading := (not ahbsi.hwrite) and v.hreg.hselff;
+ if(ahbsi.haddr(19 downto 8) = "000000000000")then
+ if(vwriting = '1')then
+ v.hreg.getscan := '1';
+ elsif(vreading = '1')then
+ v.hreg.rdscan := '1';
+ end if;
+ end if;
+ if(ahbsi.haddr(15 downto 12) = "1100" )then
+ if(vwriting = '1')then
+ v.hreg.getq := '1';
+ elsif(vreading = '1')then
+ v.hreg.rdq := '1';
+ end if;
+ end if;
+ if(ahbsi.haddr(15 downto 12) = "0100" or ahbsi.haddr(15 downto 12) = "0101")then
+ if(vwriting = '1')then
+ v.hreg.getcache := '1';
+ elsif(vreading = '1')then
+ v.hreg.rdacache := '1';
+ end if;
+ end if;
+ if(ahbsi.haddr(15 downto 12) = "1000" or ahbsi.haddr(15 downto 12) = "1001")then
+ if(vwriting = '1')then
+ v.hreg.getcache := '1';
+ elsif(vreading = '1')then
+ v.hreg.rddcache := '1';
+ end if;
+ end if;
+ if(ahbsi.haddr(15 downto 10) = "000001")then
+ if(vwriting = '1')then
+ v.hreg.getmax := '1';
+ elsif(vreading = '1')then
+ v.hreg.rdmax := '1';
+ end if;
+ end if;
+ if(ahbsi.haddr(15 downto 10) = "000010")then
+ if(vwriting = '1')then
+ v.hreg.getoffset := '1';
+ elsif(vreading = '1')then
+ v.hreg.rdoffset := '1';
+ end if;
+ end if;
+ if(ahbsi.haddr(15 downto 13) = "001")then
+ if(vwriting = '1')then
+ v.hreg.getval := '1';
+ elsif(vreading = '1')then
+ v.hreg.rdval := '1';
+ end if;
+ end if;
+ v.hreg.haddkeep := ahbsi.haddr(15 downto 0);
+end if;
+
+if( v.hreg.getscan = '1' or v.hreg.getq = '1' or v.hreg.getcache = '1'
+ or v.hreg.getmax = '1' or v.hreg.getoffset = '1' or v.hreg.getval = '1')then
+ v.hreg.hreadyff := not(v.hreg.hselff and not ahbsi.hwrite);
+ v.hreg.getscan := v.hreg.getscan and v.hreg.hreadyff;
+ v.hreg.getq := v.hreg.getq and v.hreg.hreadyff;
+ v.hreg.getcache := v.hreg.getcache and v.hreg.hreadyff;
+ v.hreg.getmax := v.hreg.getmax and v.hreg.hreadyff;
+ v.hreg.getoffset := v.hreg.getoffset and v.hreg.hreadyff;
+ v.hreg.getval := v.hreg.getval and v.hreg.hreadyff;
+end if;
+
+-- FIFO # of element calculation
+ write_point := to_integer(unsigned(r.fifo_wp));
+ read_point := to_integer(unsigned(r.fifo_rp));
+ if (write_point >= read_point) then
+ num_ele := write_point - read_point;
+ else
+ num_ele := fdepth - read_point + write_point;
+ end if;
+ if num_ele > fdepth/2 then
+ vsready := '0';
+ else
+ vsready := '1';
+ end if;
+ debug_fifoready <= vsready;
+
+ vhrdata := vsready & "0000000000000000000000000000000";
+ if(r.hreg.rdscan = '1')then
+ vhrdata := data_out_fifo;
+ elsif(r.hreg.rdq ='1')then
+ vhrdata := "000000000000000000000000" &krddataq;
+ elsif(r.hreg.rdacache = '1')then
+ vhrdata := "00000000000000000000" & accachedout;
+ elsif(r.hreg.rddcache = '1')then
+ vhrdata := "000000000000000000000000" & dccachedout;
+ elsif(r.hreg.rdmax = '1')then
+ vhrdata := "000000000000000" & sermaxdout;
+ elsif(r.hreg.rdoffset = '1')then
+ vhrdata := "000000000000000" & seroffdout;
+ elsif(r.hreg.rdval = '1')then
+ vhrdata := "000000000000000000000000" & servaldout;
+ end if;
+
+--FIFO writing
+ if r.hreg.getscan = '1' then
+ write_point := write_point + 1;
+ if write_point = fdepth then
+ write_point := 0;
+ end if;
+ end if;
+ v.fifo_wp := std_logic_vector(to_unsigned(write_point,9));
+
+--FIFO reading
+ if((r.fetch_state = bytefetch and r.byteselect = "00" and num_ele >= 1 and unsigned(r.valuebit)<= const_u6b24)
+ or (r.fetch_state = ffcheck and r.byteselect = "00" and num_ele >= 1 and unsigned(r.valuebit)<= const_u6b24)) then
+ read_point := read_point + 1;
+ if read_point = fdepth then
+ read_point := 0;
+ end if;
+ v.byte3keep(23 downto 0) := data_out_fifo(23 downto 0);
+ end if;
+ v.fifo_rp := std_logic_vector(to_unsigned(read_point,9));
+
+-- byte select from FIFO output
+ if(r.byteselect = "00") then
+ vbytedata := data_out_fifo(31 downto 24);
+ elsif(r.byteselect = "01") then
+ vbytedata := r.byte3keep(23 downto 16);
+ elsif(r.byteselect = "10") then
+ vbytedata := r.byte3keep(15 downto 8);
+ else
+ vbytedata := r.byte3keep(7 downto 0);
+ end if;
+
+ vgetbyte := '0';
+ if((r.fetch_state = bytefetch and unsigned(r.valuebit) <= const_u6b24 )
+ or (r.fetch_state = ffcheck and unsigned(r.valuebit) <= const_u6b24))then
+ v.byteselect := v.byteselect + 1;
+ vgetbyte := '1';
+ end if;
+
+--data FF
+ if(r.fetch_state = ffcheck) then
+ vinsertdata := "11111111";
+ else
+ vinsertdata := vbytedata;
+ end if;
+
+-- byte fetching to 32bit fetch_register
+ if( (r.fetch_state = bytefetch and vbytedata /= "11111111" and unsigned(r.valuebit) <= const_u6b24 and r.preg.through_bit = '0' )
+ or (r.fetch_state = ffcheck and vbytedata = "00000000" and unsigned(r.valuebit) <= const_u6b24 and r.preg.through_bit = '0')) then
+ vfetching := '1';
+ else
+ vfetching := '0';
+ end if;
+
+ if(vfetching = '1') then
+ vbyte0 := vinsertdata;
+ vbyte1 := r.fetch_reg(7 downto 0);
+ vbyte2 := r.fetch_reg(15 downto 8);
+ vbyte3 := r.fetch_reg(23 downto 16);
+ else
+ vbyte0 := r.fetch_reg(7 downto 0);
+ vbyte1 := r.fetch_reg(15 downto 8);
+ vbyte2 := r.fetch_reg(23 downto 16);
+ vbyte3 := r.fetch_reg(31 downto 24);
+ end if;
+ v.fetch_reg := vbyte3 & vbyte2 & vbyte1 & vbyte0;
+
+-- Marker register
+ if(r.fetch_state = ffcheck and vbytedata /= "00000000" and r.preg.through_bit = '0') then
+ v.marker_reg := vbytedata;
+ end if;
+ if(r.marker_reg /= "00000000")then
+ virq(hirq) := '1';
+ end if;
+
+-- Through bit & skip counter calculation
+-- This part is for "motion"-JPEG".
+-- It's not beautiful implementation, but.....
+ if(r.fetch_state = ffcheck and r.preg.through_bit = '1' and vbytedata = "11011010")then
+ v.cntdown := '1';
+ v.capture := "10";
+ end if;
+ if(r.capture = "10")then
+ v.skipcnt(15 downto 8) := vbytedata;
+ end if;
+ if(r.capture = "01")then
+ v.skipcnt(7 downto 0) := vbytedata;
+ end if;
+ if(r.cntdown = '1' and vgetbyte = '1')then
+ if(r.capture = "10")then
+ v.capture := "01";
+ end if;
+ if(r.capture = "01")then
+ v.capture := "00";
+ end if;
+ if(r.capture = "00")then
+ v.skipcnt := r.skipcnt - 1;
+ end if;
+ if(r.skipcnt = "0000000000000011")then
+ v.preg.through_bit := '0';
+ v.cntdown := '0';
+ v.skipcnt := (others => '0');
+ end if;
+ end if;
+
+-- State machine transition (fetch part)
+ case r.fetch_state is
+ when memwait =>
+ if (num_ele /= 0 and unsigned(r.valuebit) <= const_u6b24) then
+ v.fetch_state := bytefetch;
+ end if;
+ when bytefetch =>
+ if(r.byteselect = "11" and unsigned(r.valuebit) <= const_u6b24 and num_ele = 0 and vbytedata /= "11111111") then
+ v.fetch_state := memwait;
+ elsif( vbytedata = "11111111" and r.byteselect = "11" and num_ele = 0 and unsigned(r.valuebit) <= const_u6b24) then
+ v.fetch_state := ffmemwait;
+ elsif( vbytedata = "11111111" and unsigned(r.valuebit) <= const_u6b24 and (r.byteselect /= "11" or (r.byteselect = "11" and num_ele /= 0))) then
+ v.fetch_state := ffcheck;
+ end if;
+ when ffmemwait =>
+ if(num_ele /= 0) then
+ v.fetch_state := ffcheck;
+ end if;
+ when ffcheck =>
+ if( (vbytedata = "00000000" and unsigned(r.valuebit) <=const_u6b24 and (r.byteselect /= "11" or num_ele /= 0))
+ or (r.preg.through_bit = '1' and unsigned(r.valuebit)<=const_u6b24 and (r.byteselect /= "11" or num_ele /= 0) )) then
+ v.fetch_state := bytefetch;
+ elsif( (vbytedata = "00000000" and unsigned(r.valuebit)<=const_u6b24 and (r.byteselect = "11" and num_ele = 0))
+ or( r.preg.through_bit = '1' and unsigned(r.valuebit)<=const_u6b24 and r.byteselect = "11" and num_ele = 0 )) then
+ v.fetch_state := memwait;
+ elsif ( vbytedata /= "00000000") then
+ v.fetch_state := markermode;
+ end if;
+ when markermode =>
+ if(r.marker_reg = "00000000" and (r.byteselect /= "11" or( r.byteselect = "11" and num_ele /= 0))) then
+ v.fetch_state := bytefetch;
+ elsif(r.marker_reg = "00000000" and (r.byteselect = "11" and num_ele =0)) then
+ v.fetch_state := memwait;
+ end if;
+ if(r.preg.hardonly = '1' and r.marker_reg = x"D9")then
+ if(r.byteselect /= "11" or( r.byteselect = "11" and num_ele /= 0))then
+ v.marker_reg := "00000000";
+ v.preg.through_bit := '1';
+ elsif(r.byteselect = "11" and num_ele =0)then
+ v.marker_reg := "00000000";
+ v.preg.through_bit := '1';
+ end if;
+ end if;
+ when others =>
+ end case;
+
+ -- cache, serial mem output
+ if(r.dcac = '1') then
+ vcache_symbit := "0" & dccachedout(7 downto 4);
+ vcache_valbit := dccachedout(3 downto 0);
+ vcache_runlength := "0000";
+ else
+ vcache_symbit := "0" & accachedout(11 downto 8);
+ vcache_runlength := accachedout(7 downto 4);
+ vcache_valbit := accachedout(3 downto 0);
+ end if;
+ vserial_symbit := r.serial_counter - "00010";
+ vserial_runlength := servaldout(7 downto 4);
+ vserial_valbit := servaldout(3 downto 0);
+
+ -- valuebit calculation
+ if(vfetching = '1') then
+ vint_plusv := 8;
+ else
+ vint_plusv := 0;
+ end if;
+ if(r.dec_state = symcheck) then
+ if(unsigned(r.reqbit_keep) >= unsigned(vcache_symbit) )then
+ vint_minusv := to_integer(unsigned(vcache_symbit));
+ else
+ vint_minusv := 0;
+ end if;
+ elsif(r.dec_state = serialfinish) then
+ vint_minusv := to_integer(unsigned(vserial_symbit));
+ elsif(r.dec_state = valout) then
+ vint_minusv := to_integer(unsigned(r.valbit_keep));
+ else
+ vint_minusv := 0;
+ end if;
+
+ v.valuebit := std_logic_vector(to_unsigned((to_integer(unsigned(r.valuebit)) + vint_plusv - vint_minusv), 6));
+
+ -- Padding bit for Markers
+ if(r.fetch_state = markermode or r.preg.through_bit = '1') then
+ if((r.valuebit = "000001" and r.fetch_reg(0) = '1')
+ or (r.valuebit = "000010" and r.fetch_reg(1 downto 0) = "11")
+ or (r.valuebit = "000011" and r.fetch_reg(2 downto 0) = "111")
+ or (r.valuebit = "000100" and r.fetch_reg(3 downto 0) = "1111")
+ or (r.valuebit = "000101" and r.fetch_reg(4 downto 0) = "11111")
+ or (r.valuebit = "000110" and r.fetch_reg(5 downto 0) = "111111")
+ or (r.valuebit = "000111" and r.fetch_reg(6 downto 0) = "1111111")) then
+ v.valuebit := "000000";
+ end if;
+ end if;
+ if(r.dec_state = symreq)then
+ if(r.valuebit >= const_6b8)then
+ v.reqbit_keep := "1000";
+ else
+ v.reqbit_keep := r.valuebit(3 downto 0);
+ end if;
+ end if;
+
+ -- runlength_keep valbit_keep register calculation
+ if(r.dec_state = serialfinish)then
+ -- v.runlength_keep := vserial_runlength;
+ v.valbit_keep := vserial_valbit;
+ elsif(r.dec_state = symcheck)then
+ -- v.runlength_keep := vcache_runlength;
+ v.valbit_keep := vcache_valbit;
+ end if;
+
+ -- shiftnum calculation
+ vint_valuebit := to_integer(unsigned(r.valuebit));
+ vint_valbkp := to_integer(unsigned(r.valbit_keep));
+ vint_sercnt := to_integer(unsigned(r.serial_counter));
+ vintshift := 0;
+
+ if(r.dec_state = symreq)then
+ if(vint_valuebit >= 8)then
+ vintshift := vint_valuebit - 8;
+ else
+ vintshift := 0;
+ end if;
+ elsif(r.dec_state = valout)then
+ vintshift := vint_valuebit - vint_valbkp;
+ elsif(r.dec_state = serialcheck)then
+ vintshift := 1 + vint_valuebit - vint_sercnt;
+ elsif(r.dec_state = serialwait)then
+ vintshift := 1 + vint_valuebit - vint_sercnt;
+ end if;
+ vshiftnum := std_logic_vector(to_unsigned(vintshift,5));
+
+-- shifter instantiation
+debug_shiftnum <= vshiftnum;
+ vtmpshiftout := std_logic_vector(shift_right(unsigned(r.fetch_reg), vintshift));
+ vshiftout := vtmpshiftout(15 downto 0);
+
+-- write memory address generation
+-- if (r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
+-- va := '1';
+-- else
+-- va := '0';
+-- end if;
+--debug_va <= va;
+--debug_vcache_symbit <= vcache_symbit;
+--debug_vcache_runlength <= vcache_runlength;
+--debug_vcache_valbit <= vcache_valbit;
+
+
+ if(r.dcac = '1')then
+ v.memaddcnt := "000000";
+ elsif(((r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000") and vcache_runlength = "0000" and vcache_valbit = "0000")
+ or (r.dec_state = serialfinish and vserial_runlength = "0000" and vserial_valbit = "0000")) then
+ v.memaddcnt := "111111";
+ elsif(r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
+ v.memaddcnt := r.memaddcnt + vcache_runlength + "0001";
+ elsif(r.dec_state = serialfinish)then
+ v.memaddcnt := r.memaddcnt + vserial_runlength + "0001";
+ end if;
+
+-- id, dcac calculation
+ if(r.dec_state = valout and r.memaddcnt = "000000")then
+ v.dcac := '0';
+ elsif(r.dec_state = valout and r.memaddcnt = "111111") then
+ v.dcac := '1';
+ end if;
+
+ if(r.dec_state = valout and r.memaddcnt = "111111") then
+ v.idcounter := r.idcounter + '1';
+ if(r.preg.sampf = '0')then
+ if(v.idcounter = "0110")then
+ v.idcounter := "0000";
+ end if;
+ else
+ if(v.idcounter = "1000")then
+ v.idcounter := "0000";
+ end if;
+ end if;
+ end if;
+ if(r.preg.sampf = '0')then
+ if(r.idcounter < const_4b4 )then
+ vid := '0';
+ vcompid := "00";
+ elsif(r.idcounter < const_4b5)then
+ vid := '1';
+ vcompid := "01";
+ else
+ vid := '1';
+ vcompid := "10";
+ end if;
+ else
+ if(r.idcounter < const_4b4)then
+ vid := '0';
+ vcompid := "00";
+ elsif(r.idcounter < const_4b6)then
+ vid := '1';
+ vcompid := "01";
+ else
+ vid := '1';
+ vcompid := "10";
+ end if;
+ end if;
+
+-- cache access
+ if(r.dec_state = symreq)then
+ if(r.dcac = '1')then
+ if(vint_valuebit >7)then
+ vdccacheadd := vid & '0' & vshiftout(7 downto 0);
+ elsif(vint_valuebit = 7)then
+ vdccacheadd := vid & "10" & vshiftout(6 downto 0);
+ elsif(vint_valuebit = 6)then
+ vdccacheadd := vid & "110" & vshiftout(5 downto 0);
+ elsif(vint_valuebit = 5)then
+ vdccacheadd := vid & "1110" & vshiftout(4 downto 0);
+ elsif(vint_valuebit = 4)then
+ vdccacheadd := vid & "11110" & vshiftout(3 downto 0);
+ elsif(vint_valuebit = 3)then
+ vdccacheadd := vid & "111110" & vshiftout(2 downto 0);
+ elsif(vint_valuebit = 2)then
+ vdccacheadd := vid & "1111110" & vshiftout(1 downto 0);
+ elsif(vint_valuebit = 1)then
+ vdccacheadd := vid & "11111110" & vshiftout(0);
+ end if;
+ vdccachewr := '0';
+ else
+ if(vint_valuebit >7)then
+ vaccacheadd := vid & '0' & vshiftout(7 downto 0);
+ elsif(vint_valuebit = 7)then
+ vaccacheadd := vid & "10" & vshiftout(6 downto 0);
+ elsif(vint_valuebit = 6)then
+ vaccacheadd := vid & "110" & vshiftout(5 downto 0);
+ elsif(vint_valuebit = 5)then
+ vaccacheadd := vid & "1110" & vshiftout(4 downto 0);
+ elsif(vint_valuebit = 4)then
+ vaccacheadd := vid & "11110" & vshiftout(3 downto 0);
+ elsif(vint_valuebit = 3)then
+ vaccacheadd := vid & "111110" & vshiftout(2 downto 0);
+ elsif(vint_valuebit = 2)then
+ vaccacheadd := vid & "1111110" & vshiftout(1 downto 0);
+ elsif(vint_valuebit = 1)then
+ vaccacheadd := vid & "11111110" & vshiftout(0);
+ end if;
+ vaccachewr := '0';
+ end if;
+ end if;
+
+ -- Serial Part
+ vserial_mask := "00000000000000000";
+ if(r.serial_counter = "01001")then
+ vserial_mask := "00000000011111111";
+ elsif(r.serial_counter = "01010")then
+ vserial_mask := "00000000111111111";
+ elsif(r.serial_counter = "01011")then
+ vserial_mask := "00000001111111111";
+ elsif(r.serial_counter = "01100")then
+ vserial_mask := "00000011111111111";
+ elsif(r.serial_counter = "01101")then
+ vserial_mask := "00000111111111111";
+ elsif(r.serial_counter = "01110")then
+ vserial_mask := "00001111111111111";
+ elsif(r.serial_counter = "01111")then
+ vserial_mask := "00011111111111111";
+ elsif(r.serial_counter = "10000")then
+ vserial_mask := "00111111111111111";
+ elsif(r.serial_counter = "10001")then
+ vserial_mask := "01111111111111111";
+ end if;
+ vserial_tmpin := ('0' & vshiftout) and vserial_mask;
+ debug_serialin <= vserial_tmpin;
+ if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
+ vsermaxadd := r.dcac & vid & r.serial_counter;
+ end if;
+
+ if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
+ vseroffadd := r.dcac & vid & r.serial_counter;
+ end if;
+
+ if(signed(vserial_tmpin) <= to_01(signed(sermaxdout)))then
+ vserial_judge := '1';
+ end if;
+ vserial_tmpadd := std_logic_vector(signed(vserial_tmpin) + signed(seroffdout));
+ if(r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
+ vservaladd := r.dcac & vid & vserial_tmpadd(7 downto 0);
+ end if;
+ if(r.dec_state = serialwait or r.dec_state = serialcheck or r.dec_state = serialfinish)then
+ vservalwr := '0';
+ end if;
+
+ if(r.dec_state = symreq)then
+ v.serial_counter := "01001";
+ elsif((r.dec_state = symcheck and vint_valuebit > 8)
+ or (r.dec_state = serialcheck and to_integer(unsigned(r.serial_counter))<= vint_valuebit)
+ or (r.dec_state = serialwait and to_integer(unsigned(r.serial_counter))<= vint_valuebit ))
+ or (r.dec_state = serialcheck and vserial_judge = '1')then
+ v.serial_counter := r.serial_counter + 1;
+ end if;
+
+ -- Sign extention & zigzag memory access
+ debug_sign_exin <= vshiftout(10 downto 0);
+ vkdata := sign_ex(vshiftout(10 downto 0), r.valbit_keep );
+ if(r.dec_state = valout and r.dcac = '1')then
+ if(vcompid = "00")then
+ vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc0));
+ v.lastdc0 := vkdata;
+ elsif(vcompid = "01")then
+ vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc1));
+ v.lastdc1 := vkdata;
+ else
+ vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc2));
+ v.lastdc2 := vkdata;
+ end if;
+ end if;
+ if(r.dec_state = valout)then
+ vkstrobe := '1';
+ else
+ vkstrobe := '0';
+ end if;
+
+if(vstartgen = '1' or r.marker_reg = x"D9")then
+ v.lastdc0 := (others => '0');
+ v.lastdc1 := (others => '0');
+ v.lastdc2 := (others => '0');
+end if;
+
+-- Decord part state-machine
+-- state = symreq, symcheck, valout, symng, symokvalng, serialwait, serialcheck, serialfinish, standby
+ vint_csymbit := 0; vint_reqbitkp := 0; vint_cvalbit := 0;
+ vint_sersym := 0; vint_serval := 0;
+
+ if notx(vcache_symbit) then
+ vint_csymbit := to_integer(unsigned(vcache_symbit));
+ end if;
+ if notx(r.reqbit_keep) then
+ vint_reqbitkp := to_integer(unsigned(r.reqbit_keep));
+ end if;
+ if notx(vcache_valbit) then
+ vint_cvalbit := to_integer(unsigned(vcache_valbit));
+ end if;
+ if notx(vserial_symbit) then
+ vint_sersym := to_integer(unsigned(vserial_symbit));
+ end if;
+ if notx(vserial_valbit) then
+ vint_serval := to_integer(unsigned(vserial_valbit));
+ end if;
+
+ case r.dec_state is
+ when standby =>
+ if(kready = '1' and r.valuebit /= "000000")then
+ v.dec_state := symreq;
+ end if;
+ when symreq =>
+ if(r.valuebit = "000000")then
+ v.dec_state := symreq;
+ else
+ v.dec_state := symcheck;
+ end if;
+ when symcheck =>
+ if(vint_csymbit /= 0 and vint_csymbit <= vint_reqbitkp and vint_csymbit + vint_cvalbit <= vint_valuebit )then
+ v.dec_state := valout;
+ elsif(vint_csymbit /= 0 and vint_csymbit <= vint_reqbitkp and vint_csymbit + vint_cvalbit > vint_valuebit )then
+ v.dec_state := symokvalng;
+ elsif(vint_reqbitkp = 8 and vint_csymbit = 0 and vint_valuebit >= 9)then
+ v.dec_state := serialcheck;
+ elsif(vint_reqbitkp = 8 and vint_csymbit = 0 and vint_valuebit < 9)then
+ v.dec_state := serialwait;
+ elsif(vint_reqbitkp < 8 and (vint_csymbit = 0 or vint_csymbit > vint_reqbitkp))then
+ v.dec_state := symng;
+ end if;
+ when symng =>
+ if(vint_reqbitkp = vint_valuebit)then
+ v.dec_state := symng;
+ else
+ v.dec_state := symreq;
+ end if;
+ when valout =>
+ if(r.memaddcnt = "111111")then
+ v.dec_state := standby;
+ else
+ v.dec_state := symreq;
+ end if;
+ when symokvalng =>
+ if(vint_valbkp <= vint_valuebit)then
+ v.dec_state := valout;
+ else
+ v.dec_state := symokvalng;
+ end if;
+ when serialwait =>
+ if(vint_sercnt > vint_valuebit) then
+ v.dec_state := serialwait;
+ else
+ v.dec_state := serialcheck;
+ end if;
+ when serialcheck =>
+ if(vserial_judge = '1')then
+ v.dec_state := serialfinish;
+ elsif(vint_sercnt > vint_valuebit)then
+ v.dec_state := serialwait;
+ else
+ v.dec_state := serialcheck;
+ end if;
+ when serialfinish =>
+ if(vint_valuebit < vint_sersym + vint_serval)then
+ v.dec_state := symokvalng;
+ else
+ v.dec_state := valout;
+ end if;
+ when others =>
+ end case;
+
+-- reset part
+ if rst = '0' or vstartgen = '1' then
+ v.hreg.getscan := '0';
+ v.hreg.rdscan := '0';
+ v.hreg.getq := '0';
+ v.hreg.rdq := '0';
+ v.hreg.getcache := '0';
+ v.hreg.rdacache := '0';
+ v.hreg.rddcache := '0';
+ v.hreg.haddkeep := (others => '0');
+ v.hreg.getmax := '0';
+ v.hreg.rdmax := '0';
+ v.hreg.getoffset := '0';
+ v.hreg.rdoffset := '0';
+ v.hreg.getval := '0';
+ v.hreg.rdval := '0';
+ v.fetch_state := memwait;
+ v.dec_state := standby;
+ v.fifo_rp := (others => '0');
+ v.fifo_wp := (others => '0');
+ -- v.counter := (others => '0');
+ v.fetch_reg := (others => '0');
+ v.marker_reg := (others => '0');
+ v.valuebit := (others => '0');
+ v.byteselect := (others => '0');
+ v.reqbit_keep := (others => '0');
+ -- v.runlength_keep := (others => '0');
+ v.valbit_keep := (others => '0');
+ v.dcac := '1';
+ v.serial_counter := (others => '0');
+ v.idcounter := (others => '0');
+ v.memaddcnt := (others => '0');
+ v.lastdc0 := (others => '0');
+ v.lastdc1 := (others => '0');
+ v.lastdc2 := (others => '0');
+ v.byte3keep := (others => '0');
+ v.cntdown := '0';
+ v.capture := "00";
+ v.skipcnt := (others => '0');
+ end if;
+ if rst = '0' then
+ v.preg.sampf := '0';
+ v.preg.xmcumax := (others => '0');
+ v.preg.ymcumax := (others => '0');
+ v.preg.incaddy := (others => '0');
+ v.preg.incaddmcux := (others => '0');
+ v.preg.incaddmcuy := (others => '0');
+ v.preg.fbstartadd := (others => '0');
+ v.preg.through_bit := '0';
+ v.preg.hardonly := '0';
+ end if;
+
+
+-- signals
+ rin <= v;
+ write_en_fifo <= r.hreg.getscan;
+ write_pointer_fifo <= r.fifo_wp;
+ data_in_fifo <= ahbsi.hwdata;
+ read_en_fifo <= '1';
+ read_pointer_fifo <= r.fifo_rp;
+
+ dccachedin <= ahbsi.hwdata(7 downto 0);
+ dccacheadd <= vdccacheadd;
+ dccacheen <= '1';
+ dccachewr <= vdccachewr;
+ accachedin <= ahbsi.hwdata(11 downto 0);
+ accacheadd <= vaccacheadd;
+ accacheen <= '1';
+ accachewr <= vaccachewr;
+ sermaxdin <= ahbsi.hwdata(16 downto 0);
+ sermaxadd <= vsermaxadd;
+ sermaxen <= '1';
+ sermaxwr <= vsermaxwr;
+ seroffdin <= ahbsi.hwdata(16 downto 0);
+ seroffadd <= vseroffadd;
+ seroffen <= '1';
+ seroffwr <= vseroffwr;
+ seroffdin <= ahbsi.hwdata(16 downto 0);
+ servaladd <= vservaladd;
+ servalen <= '1';
+ servalwr <= vservalwr;
+ servaldin <= ahbsi.hwdata(7 downto 0);
+
+ jpg_setting.xmcumax <= r.preg.xmcumax;
+ jpg_setting.ymcumax <= r.preg.ymcumax;
+ jpg_setting.incaddy <= r.preg.incaddy;
+ jpg_setting.incaddmcux <= r.preg.incaddmcux;
+ jpg_setting.incaddmcuy <= r.preg.incaddmcuy;
+ jpg_setting.fbstartadd <= r.preg.fbstartadd;
+ startgen <= vstartgen;
+ jpg_setting.samp_fact <= r.preg.sampf;
+
+ kstrobeq <= r.hreg.getq;
+ kdataq <= ahbsi.hwdata(7 downto 0);
+
+ apbo.prdata <= vprdata;
+ ahbso.hirq <= virq;
+ ahbso.hrdata <= vhrdata;
+
+ kdata <= vkdata;
+ kstrobe <= vkstrobe;
+ kaddress <= r.memaddcnt;
+ kaddq <= vkaddq;
+ krdq <= vkrdq;
+ end process;
+
+ apbo.pirq <= (others => '0');
+ apbo.pindex <= pindex;
+ apbo.pconfig <= pconfig;
+ ahbso.hconfig <= shconfig;
+ ahbso.hresp <= "00";
+ ahbso.hsplit <= (others => '0');
+ ahbso.hcache <= '0';
+ ahbso.hready <= '1';
+ ahbso.hindex <= shindex;
+
+ -- registers
+ reg : process(clk)
+ begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+ end process;
+
+end;
port map(rst => rst, clk => clk, kready1 => kready1, kstrobe1 => kstrobe1, kaddress1 => kaddress1, kdata1 => kdata1, kready2 => kready2,
kstrobe2 => kstrobe2, kdata2 => kdata2, error =>error(0), samp_fact => jpg_setting.samp_fact,
kstrobeq1 => kstrobeq, kdataq1 => kdataq1, kdataq2 => kdataq2,
- kaddq => kaddq, krdq => krdq, krddataq => krddataq);
+ kaddq => kaddq, krdq => krdq, krddataq => krddataq, startgen => startgen);
dct1 : idct1
port map(rst => rst, clk => clk, ready1 => kready2, strobe1 => kstrobe2, coeffin => kdata2,
- quantin => kdataq2, outdata => kdata3, ready2 => kready3, strobe2 => kstrobe3);
+ quantin => kdataq2, outdata => kdata3, ready2 => kready3, strobe2 => kstrobe3, startgen => startgen);
dctmem2 : dctmem2cont
generic map(memtech => memtech)
port map(rst => rst, clk => clk, kready1 => kready3, kstrobe1 => kstrobe3, kdata1 => kdata3,
- kready2 => kready4, kstrobe2 => kstrobe4, kdata2 => kdata4, error => error(1) );
+ kready2 => kready4, kstrobe2 => kstrobe4, kdata2 => kdata4, error => error(1), startgen => startgen);
dct2 : idct2
port map(rst => rst, clk => clk, ready1 => kready4, strobe1 => kstrobe4, coeffin => kdata4,
- outdata => kdata5, ready2 => kready5, strobe2 => kstrobe5);
+ outdata => kdata5, ready2 => kready5, strobe2 => kstrobe5, startgen => startgen);
yccmem : yccmemcont
generic map(memtech => memtech)
port map(rst => rst, clk => clk, kready1 => kready5, kstrobe1 => kstrobe5, kdata1 => kdata5,
kready2 => kready6, kstrobe2 => kstrobe6, kdata2 => kdata6, samp_fact => jpg_setting.samp_fact,
- error => error(2));
+ error => error(2), startgen => startgen);
ycb : yccrgb
generic map(memtech => memtech, hirq => hirq, mhindex => mhindex,
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2011, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+-- Entity: huffdctycc
+-- File: huffdctycc.vhd
+-- Author: Kenichi Kurimoto
+-- Description: huffman decoder,2D-DCT,upsample,and YCbCr-RGB translation
+-- for jpeg decode
+------------------------------------------------------------------------------
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+library kuri;
+use kuri.mjpeg.all;
+
+entity huffdctycc is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ logan_sig : out std_logic_vector(31 downto 0)
+ );
+end;
+
+architecture rtl of huffdctycc is
+
+signal kready1, kready2, kready3, kready4, kready5, kready6,
+ kstrobe1, kstrobeq, kstrobe2, kstrobe3, kstrobe4, kstrobe5, kstrobe6: std_logic;
+signal kdata1 : std_logic_vector(11 downto 0);
+signal kaddress1 : std_logic_vector(5 downto 0);
+signal kdata2 : std_logic_vector(11 downto 0);
+signal kdataq1 : std_logic_vector(7 downto 0);
+signal kdataq2 : std_logic_vector(7 downto 0);
+signal kdata3 : std_logic_vector(15 downto 0);
+signal kdata4 : std_logic_vector(15 downto 0);
+signal kdata5 : std_logic_vector(7 downto 0);
+signal kdata6 : std_logic_vector(23 downto 0);
+signal error : std_logic_vector(2 downto 0);
+signal jpg_setting : jpg_set_type;
+signal startgen : std_logic;
+signal kaddq : std_logic_vector(7 downto 0);
+signal krdq : std_logic;
+signal krddataq : std_logic_vector(7 downto 0);
+
+signal count_r, count_rin :std_logic_vector(31 downto 0);
+
+signal logan_sig2 : std_logic_vector(31 downto 0);
+
+-- pragma translate_off
+file out_file1 : text open write_mode is "aft_huff.txt";
+file out_file2 : text open write_mode is "aft_huffmem.txt";
+file out_file3 : text open write_mode is "aft_dct1.txt";
+file out_file4 : text open write_mode is "aft_dctmem.txt";
+file out_file5 : text open write_mode is "aft_dct2.txt";
+file out_file6 : text open write_mode is "aft_yccmem.txt";
+-- pragma translate_on
+
+begin
+ huffman : huff
+ generic map(memtech => memtech,shindex => shindex , haddr => haddr, hmask => hmask,
+ hirq => hirq, pindex => pindex, paddr => paddr, pmask => pmask)
+ port map(rst => rst, clk => clk, ahbsi => ahbsi, ahbso => ahbso, apbi => apbi, apbo => apbo,
+ kready => kready1, kstrobe => kstrobe1, kdata => kdata1, kaddress => kaddress1, jpg_setting => jpg_setting,
+ error => error, startgen => startgen, kstrobeq => kstrobeq, kdataq => kdataq1,
+ kaddq => kaddq, krddataq => krddataq, krdq => krdq, logan_sig2 => logan_sig2);
+
+ dctmem1 : huffmemcont
+ generic map(memtech => memtech)
+ port map(rst => rst, clk => clk, kready1 => kready1, kstrobe1 => kstrobe1, kaddress1 => kaddress1, kdata1 => kdata1, kready2 => kready2,
+ kstrobe2 => kstrobe2, kdata2 => kdata2, error =>error(0), samp_fact => jpg_setting.samp_fact,
+ kstrobeq1 => kstrobeq, kdataq1 => kdataq1, kdataq2 => kdataq2,
+ kaddq => kaddq, krdq => krdq, krddataq => krddataq, startgen => startgen);
+
+ dct1 : idct1
+ port map(rst => rst, clk => clk, ready1 => kready2, strobe1 => kstrobe2, coeffin => kdata2,
+ quantin => kdataq2, outdata => kdata3, ready2 => kready3, strobe2 => kstrobe3, startgen => startgen);
+
+ dctmem2 : dctmem2cont
+ generic map(memtech => memtech)
+ port map(rst => rst, clk => clk, kready1 => kready3, kstrobe1 => kstrobe3, kdata1 => kdata3,
+ kready2 => kready4, kstrobe2 => kstrobe4, kdata2 => kdata4, error => error(1), startgen => startgen);
+
+ dct2 : idct2
+ port map(rst => rst, clk => clk, ready1 => kready4, strobe1 => kstrobe4, coeffin => kdata4,
+ outdata => kdata5, ready2 => kready5, strobe2 => kstrobe5, startgen => startgen);
+
+ yccmem : yccmemcont
+ generic map(memtech => memtech)
+ port map(rst => rst, clk => clk, kready1 => kready5, kstrobe1 => kstrobe5, kdata1 => kdata5,
+ kready2 => kready6, kstrobe2 => kstrobe6, kdata2 => kdata6, samp_fact => jpg_setting.samp_fact,
+ error => error(2), startgen => startgen);
+
+ ycb : yccrgb
+ generic map(memtech => memtech, hirq => hirq, mhindex => mhindex,
+ chprot => chprot)
+ port map(rst => rst, clk => clk, ahbmi => ahbmi, ahbmo => ahbmo, kready => kready6,
+ kstrobe => kstrobe6, kdata => kdata6, xmcumax => jpg_setting.xmcumax, ymcumax => jpg_setting.ymcumax,
+ incaddy => jpg_setting.incaddy, incaddmcux => jpg_setting.incaddmcux, incaddmcuy => jpg_setting.incaddmcuy,
+ fbstartadd => jpg_setting.fbstartadd, startgen => startgen);
+
+
+huffcounter : process(clk, rst, kstrobe1, kaddress1, count_r)
+ variable count_v :std_logic_vector(31 downto 0);
+begin
+ count_v := count_r;
+ if(kstrobe1 = '1' and kaddress1 = "111111") then
+ count_v := count_v + 1;
+ end if;
+ if (rst='0')then
+ count_v := (others=>'0');
+ end if;
+end process;
+
+reg :process(clk)
+begin
+ if rising_edge(clk) then
+ count_r <= count_rin;
+ end if;
+end process;
+
+logan_sig <= logan_sig2
+--logan_sig <= kstrobe2 & kdata2 & kstrobe1 & kaddress1 & kdata1 ;
+-- logan_sig <= count_r(16 downto 2) & kstrobe3 & kdata3 & kstrobe2 & kdata2 & kstrobe1 & kaddress1 & kdata1 ;
+
+-- 15 1 16 1 12 1 6 12
+
+
+
+
+-- pragma translate_off
+writeout : process(clk,kstrobe1, kstrobe2, kstrobe3, kstrobe4, kstrobe5,kstrobe6, kdata1, kdata2, kdata3,kdata4,kdata5,kdata6)
+variable lc1 : line;
+variable lc2 : line;
+variable lc3 : line;
+variable lc4 : line;
+variable lc5 : line;
+variable lc6 : line;
+variable data1 : std_logic_vector(11 downto 0);
+variable data2 : std_logic_vector(11 downto 0);
+variable data3 : std_logic_vector(15 downto 0);
+variable data4 : std_logic_vector(15 downto 0);
+variable data5 : std_logic_vector(7 downto 0);
+variable data6 : std_logic_vector(23 downto 0);
+
+begin
+ if rising_edge(clk)then
+ if (kstrobe1 = '1')then
+-- data1 := kdata1;
+ hwrite(lc1, kdata1, RIGHT, 3);
+ writeline(out_file1,lc1);
+ end if;
+ if (kstrobe2 = '1')then
+ hwrite(lc2, kdata2, RIGHT, 3);
+ writeline(out_file2,lc2);
+ end if;
+ if(kstrobe3 = '1')then
+ hwrite(lc3, kdata3, RIGHT, 4);
+ writeline(out_file3,lc3);
+ end if;
+ if (kstrobe4 = '1')then
+ hwrite(lc4, kdata4, RIGHT, 4);
+ writeline(out_file4,lc4);
+ end if;
+ if(kstrobe5 = '1')then
+ hwrite(lc5, kdata5, RIGHT, 2);
+ writeline(out_file5,lc5);
+ end if;
+ if(kstrobe6 = '1')then
+ hwrite(lc6, kdata6, RIGHT, 6);
+ writeline(out_file6, lc6);
+ end if;
+ end if;
+end process;
+-- pragma translate_on
+
+end;
+
kaddq : in std_logic_vector(7 downto 0);
krdq : in std_logic;
- krddataq : out std_logic_vector(7 downto 0)
+ krddataq : out std_logic_vector(7 downto 0);
+
+ startgen : in std_logic
);
end;
qram : syncram generic map(tech => memtech, abits => 8, dbits => 8)
port map( clk, qaddress, qdatain, qdataout, qenable, qwrite);
-comb : process (r, rst, kstrobe1, kaddress1, kdata1, kready2, m0dataout, m1dataout, kstrobeq1, kdataq1, kaddq, krdq)
+comb : process (r, rst, kstrobe1, kaddress1, kdata1, kready2, m0dataout, m1dataout, kstrobeq1, kdataq1, kaddq, krdq, samp_fact, startgen)
variable v : control_reg;
variable vkready1 : std_logic;
variable verror : std_logic;
-- reset part
- if rst = '0' then
+ if rst = '0' or startgen= '1' then
v.swf := mem0;
v.swb := mem0;
v.mem0state := fill0;
quantin : in std_logic_vector (7 downto 0);
outdata : out std_logic_vector (15 downto 0);
ready2 : in std_logic;
- strobe2 : out std_logic
+ strobe2 : out std_logic;
+ startgen : in std_logic
);
end idct1;
begin
-comb : process(r, rst, strobe1, ready2, coeffin, quantin)
+comb : process(r, rst, strobe1, ready2, coeffin, quantin, startgen)
variable v : all_reg;
variable node0 : std_logic_vector(20 downto 0);
variable node1 : node1_array;
end if;
-- reset part
- if rst = '0' then
+ if rst = '0' or startgen = '1' then
v.data_reg.inreg := (others => '0');
for i in 0 to 7 loop
v.data_reg.accumulator(i) := (others => '0');
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2011, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+-- Entity: idct1
+-- File: idct1.vhd
+-- Author: Kenichi Kurimoto
+-- Description: 1st IDCT calculation for jpeg decode
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.stdlib.all;
+
+entity idct1 is
+ port ( rst : in std_ulogic;
+ clk : in std_ulogic;
+ ready1 : out std_logic;
+ strobe1 : in std_logic;
+ coeffin : in std_logic_vector (11 downto 0);
+ quantin : in std_logic_vector (7 downto 0);
+ outdata : out std_logic_vector (15 downto 0);
+ ready2 : in std_logic;
+ strobe2 : out std_logic;
+ startgen : in std_logic
+ );
+end idct1;
+
+architecture rtl of idct1 is
+
+function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
+variable z : std_logic_vector(a'length + b'length -1 downto 0);
+begin
+ z := std_logic_vector(signed(a) * signed(b));
+ return(z);
+end;
+
+function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
+variable ex_a : std_logic_vector(a'length downto 0);
+variable ex_b : std_logic_vector(b'length downto 0);
+variable z1 : std_logic_vector(a'length downto 0);
+variable z2 : std_logic_vector(b'length downto 0);
+begin
+ ex_a := a(a'left) & a;
+ ex_b := b(b'left) & b;
+ if( a'length > b'length)then
+ z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z1);
+ else
+ z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z2);
+ end if;
+end;
+
+function round1(indata : std_logic_vector(34 downto 0)) return std_logic_vector is
+variable judge :std_logic;
+variable z : std_logic_vector(22 downto 0);
+begin
+ judge := indata(11);
+ if (judge = '0') then
+ z := indata(34 downto 12);
+ else
+ z := indata(34 downto 12) + 1;
+ end if;
+ return(z);
+end;
+
+function round2(indata : std_logic_vector(34 downto 0); pol : std_logic) return std_logic_vector is
+variable judge : std_logic;
+variable tmpdata : std_logic_vector(34 downto 0);
+variable z : std_logic_vector(22 downto 0);
+begin
+ if (pol = '1') then
+ tmpdata := (not indata) + 1 ;
+ else
+ tmpdata := indata;
+ end if;
+ judge := tmpdata(11);
+ if (judge = '1') then
+ z := tmpdata(34 downto 12) + 1;
+ else
+ z := tmpdata(34 downto 12);
+ end if;
+ return(z);
+end;
+
+function round3(indata : std_logic_vector(25 downto 0)) return std_logic_vector is
+variable judge : std_logic;
+variable z : std_logic_vector(15 downto 0);
+begin
+ judge := indata(4);
+ if (judge = '0') then
+ z := indata(20 downto 5);
+ else
+ z := indata(20 downto 5) + 1;
+ end if;
+ return(z);
+end;
+
+
+function mysigned_mul23x12(a,b : std_logic_vector) return std_logic_vector is
+variable sum : std_logic_vector(34 downto 0);
+variable p0 : std_logic_vector(34 downto 0);
+variable p1 : std_logic_vector(34 downto 0);
+variable p2 : std_logic_vector(34 downto 0);
+variable p3 : std_logic_vector(34 downto 0);
+variable p4 : std_logic_vector(34 downto 0);
+variable p5 : std_logic_vector(34 downto 0);
+variable p6 : std_logic_vector(34 downto 0);
+variable p7 : std_logic_vector(34 downto 0);
+variable p8 : std_logic_vector(34 downto 0);
+variable p9 : std_logic_vector(34 downto 0);
+variable p10 : std_logic_vector(34 downto 0);
+variable p11 : std_logic_vector(34 downto 0);
+variable plus_p : std_logic_vector(34 downto 0);
+begin
+ p0 := "000000000000" & not(a(22) and b(0))& (a(21) and b(0))& (a(20) and b(0))& (a(19) and b(0))
+ & (a(18) and b(0))& (a(17) and b(0))& (a(16) and b(0))& (a(15) and b(0))& (a(14) and b(0))
+ & (a(13) and b(0))& (a(12) and b(0))& (a(11) and b(0))& (a(10) and b(0))& (a(9) and b(0))& (a(8) and b(0))
+ & (a(7) and b(0)) & (a(6) and b(0))& (a(5) and b(0)) & (a(4) and b(0))
+ & (a(3) and b(0)) & (a(2) and b(0))& (a(1) and b(0)) & (a(0) and b(0));
+
+ p1 := "00000000000" & not(a(22) and b(1))& (a(21) and b(1))& (a(20) and b(1))& (a(19) and b(1))
+ & (a(18) and b(1))& (a(17) and b(1))& (a(16) and b(1))& (a(15) and b(1))& (a(14) and b(1))
+ & (a(13) and b(1))& (a(12) and b(1))& (a(11) and b(1))& (a(10) and b(1))& (a(9) and b(1))& (a(8) and b(1))
+ & (a(7) and b(1)) & (a(6) and b(1))& (a(5) and b(1)) & (a(4) and b(1))
+ & (a(3) and b(1)) & (a(2) and b(1))& (a(1) and b(1)) & (a(0) and b(1)) & '0';
+
+ p2 := "0000000000" & not(a(22) and b(2))& (a(21) and b(2))& (a(20) and b(2))& (a(19) and b(2))
+ & (a(18) and b(2))& (a(17) and b(2))& (a(16) and b(2))& (a(15) and b(2))& (a(14) and b(2))
+ & (a(13) and b(2))& (a(12) and b(2))& (a(11) and b(2))& (a(10) and b(2))& (a(9) and b(2))& (a(8) and b(2))
+ & (a(7) and b(2)) & (a(6) and b(2))& (a(5) and b(2)) & (a(4) and b(2))
+ & (a(3) and b(2)) & (a(2) and b(2))& (a(1) and b(2)) & (a(0) and b(2)) & "00";
+
+ p3 := "000000000" & not(a(22) and b(3))& (a(21) and b(3))& (a(20) and b(3))& (a(19) and b(3))
+ & (a(18) and b(3))& (a(17) and b(3))& (a(16) and b(3))& (a(15) and b(3))& (a(14) and b(3))
+ & (a(13) and b(3))& (a(12) and b(3))& (a(11) and b(3))& (a(10) and b(3))& (a(9) and b(3))& (a(8) and b(3))
+ & (a(7) and b(3)) & (a(6) and b(3))& (a(5) and b(3)) & (a(4) and b(3))
+ & (a(3) and b(3)) & (a(2) and b(3))& (a(1) and b(3)) & (a(0) and b(3)) & "000";
+
+ p4 := "00000000" & not(a(22) and b(4))& (a(21) and b(4))& (a(20) and b(4))& (a(19) and b(4))
+ & (a(18) and b(4))& (a(17) and b(4))& (a(16) and b(4))& (a(15) and b(4))& (a(14) and b(4))
+ & (a(13) and b(4))& (a(12) and b(4))& (a(11) and b(4))& (a(10) and b(4))& (a(9) and b(4))& (a(8) and b(4))
+ & (a(7) and b(4)) & (a(6) and b(4))& (a(5) and b(4)) & (a(4) and b(4))
+ & (a(3) and b(4)) & (a(2) and b(4))& (a(1) and b(4)) & (a(0) and b(4)) & "0000";
+
+ p5 := "0000000" & not(a(22) and b(5))& (a(21) and b(5))& (a(20) and b(5))& (a(19) and b(5))
+ & (a(18) and b(5))& (a(17) and b(5))& (a(16) and b(5))& (a(15) and b(5))& (a(14) and b(5))
+ & (a(13) and b(5))& (a(12) and b(5))& (a(11) and b(5))& (a(10) and b(5))& (a(9) and b(5))& (a(8) and b(5))
+ & (a(7) and b(5)) & (a(6) and b(5))& (a(5) and b(5)) & (a(4) and b(5))
+ & (a(3) and b(5)) & (a(2) and b(5))& (a(1) and b(5)) & (a(0) and b(5)) & "00000";
+
+ p6 := "000000" & not(a(22) and b(6))& (a(21) and b(6))& (a(20) and b(6))& (a(19) and b(6))
+ & (a(18) and b(6))& (a(17) and b(6))& (a(16) and b(6))& (a(15) and b(6))& (a(14) and b(6))
+ & (a(13) and b(6))& (a(12) and b(6))& (a(11) and b(6))& (a(10) and b(6))& (a(9) and b(6))& (a(8) and b(6))
+ & (a(7) and b(6)) & (a(6) and b(6))& (a(5) and b(6)) & (a(4) and b(6))
+ & (a(3) and b(6)) & (a(2) and b(6))& (a(1) and b(6)) & (a(0) and b(6)) & "000000";
+
+ p7 := "00000" & not(a(22) and b(7))& (a(21) and b(7))& (a(20) and b(7))& (a(19) and b(7))
+ & (a(18) and b(7))& (a(17) and b(7))& (a(16) and b(7))& (a(15) and b(7))& (a(14) and b(7))
+ & (a(13) and b(7))& (a(12) and b(7))& (a(11) and b(7))& (a(10) and b(7))& (a(9) and b(7))& (a(8) and b(7))
+ & (a(7) and b(7)) & (a(6) and b(7))& (a(5) and b(7)) & (a(4) and b(7))
+ & (a(3) and b(7)) & (a(2) and b(7))& (a(1) and b(7)) & (a(0) and b(7)) & "0000000";
+
+ p8 := "0000" & not(a(22) and b(8))& (a(21) and b(8))& (a(20) and b(8))& (a(19) and b(8))
+ & (a(18) and b(8))& (a(17) and b(8))& (a(16) and b(8))& (a(15) and b(8))& (a(14) and b(8))
+ & (a(13) and b(8))& (a(12) and b(8))& (a(11) and b(8))& (a(10) and b(8))& (a(9) and b(8))& (a(8) and b(8))
+ & (a(7) and b(8)) & (a(6) and b(8))& (a(5) and b(8)) & (a(4) and b(8))
+ & (a(3) and b(8)) & (a(2) and b(8))& (a(1) and b(8)) & (a(0) and b(8)) & "00000000";
+
+ p9 := "000" & not(a(22) and b(9))& (a(21) and b(9))& (a(20) and b(9))& (a(19) and b(9))
+ & (a(18) and b(9))& (a(17) and b(9))& (a(16) and b(9))& (a(15) and b(9))& (a(14) and b(9))
+ & (a(13) and b(9))& (a(12) and b(9))& (a(11) and b(9))& (a(10) and b(9))& (a(9) and b(9))& (a(8) and b(9))
+ & (a(7) and b(9)) & (a(6) and b(9))& (a(5) and b(9)) & (a(4) and b(9))
+ & (a(3) and b(9)) & (a(2) and b(9))& (a(1) and b(9)) & (a(0) and b(9)) & "000000000";
+
+ p10 := "00" & not(a(22) and b(10))& (a(21) and b(10))& (a(20) and b(10))& (a(19) and b(10))
+ & (a(18) and b(10))& (a(17) and b(10))& (a(16) and b(10))& (a(15) and b(10))& (a(14) and b(10))
+ & (a(13) and b(10))& (a(12) and b(10))& (a(11) and b(10))& (a(10) and b(10))& (a(9) and b(10))& (a(8) and b(10))
+ & (a(7) and b(10)) & (a(6) and b(10))& (a(5) and b(10)) & (a(4) and b(10))
+ & (a(3) and b(10)) & (a(2) and b(10))& (a(1) and b(10)) & (a(0) and b(10)) & "0000000000";
+
+ p11 := "1" & (a(22) and b(11))& not(a(21) and b(11))& not(a(20) and b(11))& not(a(19) and b(11))
+ & not(a(18) and b(11))& not(a(17) and b(11))& not(a(16) and b(11))& not(a(15) and b(11))& not(a(14) and b(11))
+ & not(a(13) and b(11))& not(a(12) and b(11))& not(a(11) and b(11))& not(a(10) and b(11))& not(a(9) and b(11))& not(a(8) and b(11))
+ & not(a(7) and b(11)) & not(a(6) and b(11))& not(a(5) and b(11)) & not(a(4) and b(11))
+ & not(a(3) and b(11)) & not(a(2) and b(11))& not(a(1) and b(11)) & not(a(0) and b(11)) & "00000000000";
+
+ plus_p := "000000000000" & "1" & "0000000000" & "1" & "00000000000"
+-- plus_p := "001111111111" & "1" & "0000000000" & "1" & "0000000000" &
+ sum := std_logic_vector((unsigned(p0) + unsigned(p1)) + (unsigned(p2) + unsigned(p3)) + (unsigned(p4)
+ + unsigned(p5)) + (unsigned(p6) + unsigned(p7)) + (unsigned(p8) + unsigned(p9)) + (unsigned(p10) + unsigned(p11)) + unsigned(plus_p) );
+ return(sum);
+end;
+
+
+
+
+subtype coeff23 is std_logic_vector(22 downto 0);
+type coeff_array1 is array(0 to 31) of coeff23;
+constant coeff_rom : coeff_array1 :=
+
+("01011010100000100111101","01011010100000100111101","01011010100000100111101","01011010100000100111101",
+ "01111101100010100110000","01101010011011011001100","01000111000111001110110","00011000111110001011100",
+ "01110110010000011011000","00110000111110111100011","11001111000001000011110","10001001101111100101001",
+ "01101010011011011001100","11100111000001110100100","10000010011101011010001","10111000111000110001010",
+ "01011010100000100111101","10100101011111011000100","10100101011111011000100","01011010100000100111101",
+ "01000111000111001110110","10000010011101011010001","00011000111110001011100","01101010011011011001100",
+ "00110000111110111100011","10001001101111100101001","01110110010000011011000","11001111000001000011110",
+ "00011000111110001011100","10111000111000110001010","01101010011011011001100","10000010011101011010001");
+
+type tablereg_type is array (0 to 3) of std_logic_vector(22 downto 0);
+type accumulator_type is array (0 to 7) of std_logic_vector(25 downto 0);
+type resultreg_type is array (0 to 7) of std_logic_vector(15 downto 0);
+
+type d_reg is record
+ inreg : std_logic_vector(11 downto 0);
+ accumulator : accumulator_type;
+ result_reg : resultreg_type;
+end record;
+
+type c_reg is record
+ counter : std_logic_vector(6 downto 0);
+end record;
+
+type all_reg is record
+ data_reg : d_reg;
+ control_reg : c_reg;
+end record;
+
+type node1_array is array (0 to 3) of std_logic_vector(22 downto 0);
+type node2_array is array (0 to 3) of std_logic_vector(34 downto 0);
+type node3_array is array (0 to 7) of std_logic_vector(22 downto 0);
+type node4_array is array (0 to 7) of std_logic_vector(25 downto 0);
+type node5_array is array (0 to 7) of std_logic_vector(26 downto 0);
+type node6_array is array (0 to 7) of std_logic_vector(15 downto 0);
+
+signal r, rin : all_reg;
+--signal sig_node1_0 : std_logic_vector(22 downto 0);
+--signal sig_node2_0 : std_logic_vector(34 downto 0);
+--signal sig_node3_0 : std_logic_vector(22 downto 0);
+--signal sig_node4_0 : std_logic_vector(25 downto 0);
+--signal sig_node5_0 : std_logic_vector(26 downto 0);
+--signal sig_node6_0 : std_logic_vector(15 downto 0);
+--signal sig_node1_1 : std_logic_vector(22 downto 0);
+--signal sig_node2_1 : std_logic_vector(34 downto 0);
+--signal sig_node3_6 : std_logic_vector(22 downto 0);
+--signal sig_node4_6 : std_logic_vector(25 downto 0);
+--signal sig_node5_6 : std_logic_vector(26 downto 0);
+--signal sig_node6_6 : std_logic_vector(15 downto 0);
+
+begin
+
+comb : process(r, rst, strobe1, ready2, coeffin, quantin, startgen)
+ variable v : all_reg;
+ variable node0 : std_logic_vector(20 downto 0);
+ variable node1 : node1_array;
+ variable node2 : node2_array;
+ variable node3 : node3_array;
+ variable node4 : node4_array;
+ variable node5 : node5_array;
+ variable node6 : node6_array;
+ variable pol : std_logic;
+ variable count_num : integer;
+ variable vstrobe2 : std_logic;
+ variable vready1 : std_logic;
+begin
+
+ v := r;
+ vstrobe2 := '0';
+ count_num := to_integer(unsigned(r.control_reg.counter));
+
+ node0 := mysigned_mul(coeffin, '0' & quantin);
+ v.data_reg.inreg := node0(11 downto 0);
+
+ case count_num is
+ when 2 | 10 | 18 | 26 | 34 | 42 | 50 | 58 =>
+ node1(0) := coeff_rom(4);
+ node1(1) := coeff_rom(5);
+ node1(2) := coeff_rom(6);
+ node1(3) := coeff_rom(7);
+ when 3 | 11 | 19 | 27 | 35 | 43 | 51 | 59 =>
+ node1(0) := coeff_rom(8);
+ node1(1) := coeff_rom(9);
+ node1(2) := coeff_rom(10);
+ node1(3) := coeff_rom(11);
+ when 4 | 12 | 20 | 28 | 36 | 44 | 52 | 60 =>
+ node1(0) := coeff_rom(12);
+ node1(1) := coeff_rom(13);
+ node1(2) := coeff_rom(14);
+ node1(3) := coeff_rom(15);
+ when 5 | 13 | 21 | 29 | 37 | 45 | 53 | 61 =>
+ node1(0) := coeff_rom(16);
+ node1(1) := coeff_rom(17);
+ node1(2) := coeff_rom(18);
+ node1(3) := coeff_rom(19);
+ when 6 | 14 | 22 | 30 | 38 | 46 | 54 | 62 =>
+ node1(0) := coeff_rom(20);
+ node1(1) := coeff_rom(21);
+ node1(2) := coeff_rom(22);
+ node1(3) := coeff_rom(23);
+ when 7 | 15 | 23 | 31 | 39 | 47 | 55 | 63 =>
+ node1(0) := coeff_rom(24);
+ node1(1) := coeff_rom(25);
+ node1(2) := coeff_rom(26);
+ node1(3) := coeff_rom(27);
+ when 8 | 16 | 24 | 32 | 40 | 48 | 56 | 64 =>
+ node1(0) := coeff_rom(28);
+ node1(1) := coeff_rom(29);
+ node1(2) := coeff_rom(30);
+ node1(3) := coeff_rom(31);
+ when others =>
+ node1(0) := coeff_rom(0);
+ node1(1) := coeff_rom(1);
+ node1(2) := coeff_rom(2);
+ node1(3) := coeff_rom(3);
+ end case;
+
+ for i in 0 to 3 loop
+ node2(i) := mysigned_mul23x12(node1(i), r.data_reg.inreg);
+ node3(i) := round1(node2(i));
+ end loop;
+
+-- when 3 | 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | ..... | 65
+-- when 2 4 6 8 10 12 14 16 18 20 22 64
+ if((count_num mod 2) = 0 and (count_num >= 2) and (count_num <= 64))then
+ pol := '1';
+ else
+ pol := '0';
+ end if;
+
+ node3(4) := round2(node2(3), pol);
+ node3(5) := round2(node2(2), pol);
+ node3(6) := round2(node2(1), pol);
+ node3(7) := round2(node2(0), pol);
+
+ if((count_num = 1) or (count_num = 9) or (count_num = 17) or (count_num = 25) or (count_num = 33) or (count_num = 41) or (count_num = 49) or (count_num = 57)) then
+ for i in 0 to 7 loop
+ node4(i) := (others => '0');
+ end loop;
+ else
+ for i in 0 to 7 loop
+ node4(i) := r.data_reg.accumulator(i);
+ end loop;
+ end if;
+
+ for i in 0 to 7 loop
+ node5(i) := mysigned_add(node3(i), node4(i));
+ v.data_reg.accumulator(i) := node5(i)(25 downto 0);
+ node6(i) := round3(r.data_reg.accumulator(i));
+ end loop;
+
+ if((count_num = 9) or (count_num = 17) or (count_num = 25) or (count_num = 33) or (count_num = 41) or (count_num = 49) or (count_num = 57) or (count_num = 65)) then
+ for i in 0 to 7 loop
+ v.data_reg.result_reg(i) := node6(i);
+ end loop;
+ else
+ for i in 0 to 6 loop
+ v.data_reg.result_reg(i) := r.data_reg.result_reg(i+1);
+ end loop;
+ v.data_reg.result_reg(7) := (others => '0');
+ end if;
+
+ if((count_num >= 10) and (count_num <= 73))then
+ vstrobe2 := '1';
+ end if;
+
+-- controller part
+ if ((count_num = 0 and strobe1 = '1') or count_num /= 0) then
+ v.control_reg.counter := std_logic_vector(to_unsigned(count_num + 1,7));
+ if(count_num = 73)then
+ v.control_reg.counter := (others => '0');
+ end if;
+ end if;
+ vready1 := '0';
+ if(ready2 = '1' and count_num <= 63) then
+ vready1 := '1';
+ end if;
+
+-- reset part
+ if rst = '0' or startgen = '1' then
+ v.data_reg.inreg := (others => '0');
+ for i in 0 to 7 loop
+ v.data_reg.accumulator(i) := (others => '0');
+ v.data_reg.result_reg(i) := (others => '0');
+ end loop;
+ v.control_reg.counter := (others => '0');
+ end if;
+
+-- signal
+ outdata <= r.data_reg.result_reg(0);
+ strobe2 <= vstrobe2;
+ ready1 <= vready1;
+ rin <= v;
+
+-- debug
+-- sig_node1_0 <= node1(0);
+-- sig_node2_0 <= node2(0);
+-- sig_node3_0 <= node3(0);
+-- sig_node4_0 <= node4(0);
+-- sig_node5_0 <= node5(0);
+-- sig_node6_0 <= node6(0);
+-- sig_node1_1 <= node1(1);
+-- sig_node2_1 <= node2(1);
+-- sig_node3_6 <= node3(6);
+-- sig_node4_6 <= node4(6);
+-- sig_node5_6 <= node5(6);
+-- sig_node6_6 <= node6(6);
+end process;
+-- registers
+reg : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
+
+end rtl;
+
coeffin : in std_logic_vector (15 downto 0);
outdata : out std_logic_vector (7 downto 0);
ready2 : in std_logic;
- strobe2 : out std_logic
+ strobe2 : out std_logic;
+ startgen : in std_logic
);
end idct2;
begin
-comb : process(r, rst, strobe1, ready2, coeffin)
+comb : process(r, rst, strobe1, ready2, coeffin, startgen)
variable v : all_reg;
variable node1 : node1_array;
variable node2 : node2_array;
end if;
-- reset part
- if rst = '0' then
+ if rst = '0' or startgen = '1' then
+ v.data_reg.inreg := (others => '0');
for i in 0 to 7 loop
v.data_reg.accumulator(i) := (others => '0');
v.data_reg.result_reg(i) := (others => '0');
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 2011, Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+-- Entity: idct2
+-- File: idct2.vhd
+-- Author: Kenichi Kurimoto
+-- Description: 2nd IDCT calculation for jpeg decode
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.stdlib.all;
+
+entity idct2 is
+ port ( rst : in std_ulogic;
+ clk : in std_ulogic;
+ ready1 : out std_logic;
+ strobe1 : in std_logic;
+ coeffin : in std_logic_vector (15 downto 0);
+ outdata : out std_logic_vector (7 downto 0);
+ ready2 : in std_logic;
+ strobe2 : out std_logic;
+ startgen : in std_logic
+ );
+end idct2;
+
+architecture rtl of idct2 is
+
+function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
+variable z : std_logic_vector(a'length + b'length -1 downto 0);
+begin
+ z := std_logic_vector(signed(a) * signed(b));
+ return(z);
+end;
+
+
+function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
+variable ex_a : std_logic_vector(a'length downto 0);
+variable ex_b : std_logic_vector(b'length downto 0);
+variable z1 : std_logic_vector(a'length downto 0);
+variable z2 : std_logic_vector(b'length downto 0);
+begin
+ ex_a := a(a'left) & a;
+ ex_b := b(b'left) & b;
+ if( a'length > b'length)then
+ z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z1);
+ else
+ z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
+ return(z2);
+ end if;
+end;
+
+function round1(indata : std_logic_vector(32 downto 0)) return std_logic_vector is
+variable judge :std_logic;
+variable z : std_logic_vector(14 downto 0);
+begin
+ judge := indata(17);
+ if (judge = '0') then
+ z := indata(32 downto 18);
+ else
+ z := indata(32 downto 18) + 1;
+ end if;
+ return(z);
+end;
+
+function round2(indata : std_logic_vector(32 downto 0); pol : std_logic) return std_logic_vector is
+variable judge : std_logic;
+variable tmpdata : std_logic_vector(32 downto 0);
+variable z : std_logic_vector(14 downto 0);
+begin
+ if (pol = '1') then
+ tmpdata := not indata + 1 ;
+ else
+ tmpdata := indata;
+ end if;
+ judge := tmpdata(17);
+ if (judge = '1') then
+ z := tmpdata(32 downto 18) + 1;
+ else
+ z := tmpdata(32 downto 18);
+ end if;
+ return(z);
+end;
+
+constant S_ZERO : SIGNED := "0000000000";
+constant S_TWOFIVEFIVE : SIGNED := "0011111111";
+
+function round3(indata : std_logic_vector(17 downto 0)) return std_logic_vector is
+variable judge : std_logic;
+variable z : std_logic_vector(12 downto 0);
+variable value : integer;
+begin
+ judge := indata(4);
+ value := 0;
+ if (judge = '0') then
+ z := indata(17 downto 5);
+ else
+ z := indata(17 downto 5) + 1;
+ end if;
+ if notx(z) then value := to_integer(signed(z)); end if;
+ if (value < -128) then
+ return("10000000");
+ end if;
+ if(value > 127) then
+ return("01111111");
+ end if;
+ return(z(7 downto 0));
+end;
+
+
+
+subtype coeff23 is std_logic_vector(16 downto 0);
+type coeff_array1 is array(0 to 31) of coeff23;
+constant coeff_rom : coeff_array1 :=
+
+("01011010100000101","01011010100000101","01011010100000101","01011010100000101",
+ "01111101100010101","01101010011011011","01000111000111010","00011000111110001",
+ "01110110010000011","00110000111111000","11001111000001001","10001001101111101",
+ "01101010011011011","11100111000001111","10000010011101100","10111000111000111",
+ "01011010100000101","10100101011111100","10100101011111100","01011010100000101",
+ "01000111000111010","10000010011101100","00011000111110001","01101010011011011",
+ "00110000111111000","10001001101111101","01110110010000011","11001111000001001",
+ "00011000111110001","10111000111000111","01101010011011011","10000010011101100");
+
+
+type tablereg_type is array (0 to 3) of std_logic_vector(16 downto 0);
+type accumulator_type is array (0 to 7) of std_logic_vector(17 downto 0);
+type resultreg_type is array (0 to 7) of std_logic_vector(7 downto 0);
+
+
+type d_reg is record
+ inreg : std_logic_vector(15 downto 0);
+ accumulator : accumulator_type;
+ result_reg : resultreg_type;
+end record;
+
+type c_reg is record
+ counter : std_logic_vector(6 downto 0);
+end record;
+
+type all_reg is record
+ data_reg : d_reg;
+ control_reg : c_reg;
+end record;
+
+type node1_array is array (0 to 3) of std_logic_vector(16 downto 0);
+type node2_array is array (0 to 3) of std_logic_vector(32 downto 0);
+type node3_array is array (0 to 7) of std_logic_vector(14 downto 0);
+type node4_array is array (0 to 7) of std_logic_vector(17 downto 0);
+type node5_array is array (0 to 7) of std_logic_vector(18 downto 0);
+type node6_array is array (0 to 7) of std_logic_vector(7 downto 0);
+
+signal r, rin : all_reg;
+--signal sig_node1_0 : std_logic_vector(16 downto 0);
+--signal sig_node2_0 : std_logic_vector(32 downto 0);
+--signal sig_node3_0 : std_logic_vector(14 downto 0);
+--signal sig_node4_0 : std_logic_vector(17 downto 0);
+--signal sig_node5_0 : std_logic_vector(18 downto 0);
+--signal sig_node6_0 : std_logic_vector(7 downto 0);
+--signal sig_node1_3 : std_logic_vector(16 downto 0);
+--signal sig_node2_3 : std_logic_vector(32 downto 0);
+--signal sig_node3_4 : std_logic_vector(14 downto 0);
+--signal sig_node4_4 : std_logic_vector(17 downto 0);
+--signal sig_node5_4 : std_logic_vector(18 downto 0);
+--signal sig_node6_4 : std_logic_vector(7 downto 0);
+
+
+begin
+
+comb : process(r, rst, strobe1, ready2, coeffin, startgen)
+ variable v : all_reg;
+ variable node1 : node1_array;
+ variable node2 : node2_array;
+ variable node3 : node3_array;
+ variable node4 : node4_array;
+ variable node5 : node5_array;
+ variable node6 : node6_array;
+ variable node7 : std_logic_vector(9 downto 0);
+ variable node8 : std_logic_vector(9 downto 0);
+ variable pol : std_logic;
+
+ variable count_num : integer;
+ variable vstrobe2 : std_logic;
+ variable vready1 : std_logic;
+begin
+
+ v := r;
+ vstrobe2 := '0';
+ count_num := to_integer(unsigned(r.control_reg.counter));
+
+ v.data_reg.inreg := coeffin;
+
+ case count_num is
+ when 2 | 10 | 18 | 26 | 34 | 42 | 50 | 58 =>
+ node1(0) := coeff_rom(4);
+ node1(1) := coeff_rom(5);
+ node1(2) := coeff_rom(6);
+ node1(3) := coeff_rom(7);
+ when 3 | 11 | 19 | 27 | 35 | 43 | 51 | 59 =>
+ node1(0) := coeff_rom(8);
+ node1(1) := coeff_rom(9);
+ node1(2) := coeff_rom(10);
+ node1(3) := coeff_rom(11);
+ when 4 | 12 | 20 | 28 | 36 | 44 | 52 | 60 =>
+ node1(0) := coeff_rom(12);
+ node1(1) := coeff_rom(13);
+ node1(2) := coeff_rom(14);
+ node1(3) := coeff_rom(15);
+ when 5 | 13 | 21 | 29 | 37 | 45 | 53 | 61 =>
+ node1(0) := coeff_rom(16);
+ node1(1) := coeff_rom(17);
+ node1(2) := coeff_rom(18);
+ node1(3) := coeff_rom(19);
+ when 6 | 14 | 22 | 30 | 38 | 46 | 54 | 62 =>
+ node1(0) := coeff_rom(20);
+ node1(1) := coeff_rom(21);
+ node1(2) := coeff_rom(22);
+ node1(3) := coeff_rom(23);
+ when 7 | 15 | 23 | 31 | 39 | 47 | 55 | 63 =>
+ node1(0) := coeff_rom(24);
+ node1(1) := coeff_rom(25);
+ node1(2) := coeff_rom(26);
+ node1(3) := coeff_rom(27);
+ when 8 | 16 | 24 | 32 | 40 | 48 | 56 | 64 =>
+ node1(0) := coeff_rom(28);
+ node1(1) := coeff_rom(29);
+ node1(2) := coeff_rom(30);
+ node1(3) := coeff_rom(31);
+ when others =>
+ node1(0) := coeff_rom(0);
+ node1(1) := coeff_rom(1);
+ node1(2) := coeff_rom(2);
+ node1(3) := coeff_rom(3);
+ end case;
+
+ for i in 0 to 3 loop
+ node2(i) := mysigned_mul(node1(i), r.data_reg.inreg);
+ node3(i) := round1(node2(i));
+ end loop;
+
+
+-- when 3 | 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | ..... | 65
+-- when 2 4 6 8 10 12 14 16 18 20 22 64
+
+ if((count_num mod 2) = 0 and (count_num >= 2) and (count_num <= 64))then
+ pol := '1';
+ else
+ pol := '0';
+ end if;
+
+ node3(4) := round2(node2(3), pol);
+ node3(5) := round2(node2(2), pol);
+ node3(6) := round2(node2(1), pol);
+ node3(7) := round2(node2(0), pol);
+
+ if((count_num = 1) or (count_num = 9) or (count_num = 17) or (count_num = 25) or (count_num = 33) or (count_num = 41) or (count_num = 49) or (count_num = 57)) then
+ for i in 0 to 7 loop
+ node4(i) := (others => '0');
+ end loop;
+ else
+ for i in 0 to 7 loop
+ node4(i) := r.data_reg.accumulator(i);
+ end loop;
+ end if;
+
+ for i in 0 to 7 loop
+ node5(i) := mysigned_add(node3(i), node4(i));
+ v.data_reg.accumulator(i) := node5(i)(17 downto 0);
+ node6(i) := round3(r.data_reg.accumulator(i));
+ end loop;
+
+ if((count_num = 9) or (count_num = 17) or (count_num = 25) or (count_num = 33) or (count_num = 41) or (count_num = 49) or (count_num = 57) or (count_num = 65)) then
+ for i in 0 to 7 loop
+ v.data_reg.result_reg(i) := node6(i);
+ end loop;
+ else
+ for i in 0 to 6 loop
+ v.data_reg.result_reg(i) := r.data_reg.result_reg(i+1);
+ end loop;
+ v.data_reg.result_reg(7) := (others => '0');
+ end if;
+
+ node7 := mysigned_add(r.data_reg.result_reg(0),"010000000");
+
+ if((count_num >= 10) and (count_num <= 73))then
+ vstrobe2 := '1';
+ end if;
+
+-- controller part
+ if ((count_num = 0 and strobe1 = '1') or count_num /= 0) then
+ v.control_reg.counter := std_logic_vector(to_unsigned(count_num + 1,7));
+ if(count_num = 73)then
+ v.control_reg.counter := (others => '0');
+ end if;
+ end if;
+ vready1 := '0';
+ if(ready2 = '1' and count_num <= 63)then
+ vready1 := '1';
+ end if;
+
+-- reset part
+ if rst = '0' or startgen = '1' then
+ v.data_reg.inreg := (others => '0');
+ for i in 0 to 7 loop
+ v.data_reg.accumulator(i) := (others => '0');
+ v.data_reg.result_reg(i) := (others => '0');
+ end loop;
+ v.control_reg.counter := (others => '0');
+ end if;
+
+-- signal
+ outdata <= node7(7 downto 0);
+ strobe2 <= vstrobe2;
+ ready1 <= vready1;
+ rin <= v;
+
+-- debug
+-- sig_node1_0 <= node1(0);
+-- sig_node2_0 <= node2(0);
+-- sig_node3_0 <= node3(0);
+-- sig_node4_0 <= node4(0);
+-- sig_node5_0 <= node5(0);
+-- sig_node6_0 <= node6(0);
+-- sig_node1_3 <= node1(3);
+-- sig_node2_3 <= node2(3);
+-- sig_node3_4 <= node3(4);
+-- sig_node4_4 <= node4(4);
+-- sig_node5_4 <= node5(4);
+-- sig_node6_4 <= node6(4);
+end process;
+
+-- registers
+reg : process(clk)
+begin
+ if rising_edge(clk) then
+ r <= rin;
+ end if;
+end process;
+
+end rtl;
+
kstrobe2 : out std_logic;
kdata2 : out std_logic_vector(11 downto 0);
error : out std_logic;
-
samp_fact : in std_logic;
kstrobeq1 : in std_logic;
kdataq1 : in std_logic_vector(7 downto 0);
- kdataq2 : out std_logic_vector(7 downto 0);
-
+ kdataq2 : out std_logic_vector(7 downto 0);
kaddq : in std_logic_vector(7 downto 0);
krdq : in std_logic;
- krddataq : out std_logic_vector(7 downto 0)
+ krddataq : out std_logic_vector(7 downto 0);
+ startgen : in std_logic
);
end component;
kready2 : in std_logic;
kstrobe2 : out std_logic;
kdata2 : out std_logic_vector(15 downto 0);
- error : out std_logic
+ error : out std_logic;
+ startgen : in std_logic
);
end component;
quantin : in std_logic_vector (7 downto 0);
outdata : out std_logic_vector (15 downto 0);
ready2 : in std_logic;
- strobe2 : out std_logic
+ strobe2 : out std_logic;
+ startgen : in std_logic
);
end component;
coeffin : in std_logic_vector (15 downto 0);
outdata : out std_logic_vector (7 downto 0);
ready2 : in std_logic;
- strobe2 : out std_logic
+ strobe2 : out std_logic;
+ startgen : in std_logic
);
end component;
kstrobe2 : out std_logic;
kdata2 : out std_logic_vector(23 downto 0);
samp_fact : in std_logic;
- error : out std_logic
+ error : out std_logic;
+ startgen : in std_logic
);
end component;
--- /dev/null
+------------------------------------------------------------------------------
+-- Copyright (C) 20011 , Kenichi Kurimoto
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+-----------------------------------------------------------------------------
+-- Entity: mjpeg package
+-- File: mjpeg.vhd
+-- Author: Kenichi Kurimoto
+-- Description: motion JPEG package
+------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library grlib;
+use grlib.stdlib.all;
+use grlib.amba.all;
+use grlib.devices.all;
+
+library techmap;
+use techmap.gencomp.all;
+
+package mjpeg is
+
+type jpg_set_type is record
+ samp_fact : std_logic;
+ xmcumax : std_logic_vector(5 downto 0);
+ ymcumax : std_logic_vector(4 downto 0);
+ incaddy : std_logic_vector(15 downto 0);
+ incaddmcux : std_logic_vector(15 downto 0);
+ incaddmcuy : std_logic_vector(10 downto 0);
+ fbstartadd : std_logic_vector(31 downto 0);
+end record;
+
+component huffdctycc is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ logan_sig : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component huff is
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ kready : in std_logic;
+ kstrobe : out std_logic;
+ kdata : out std_logic_vector(11 downto 0);
+ kaddress : out std_logic_vector(5 downto 0);
+ jpg_setting : out jpg_set_type;
+ error : in std_logic_vector(2 downto 0);
+ startgen : out std_logic;
+ kstrobeq : out std_logic;
+ kdataq : out std_logic_vector(7 downto 0);
+ kaddq : out std_logic_vector(7 downto 0);
+ krddataq : in std_logic_vector(7 downto 0);
+ krdq : out std_logic
+ );
+end component;
+
+component huffmemcont is
+ generic (
+ memtech : integer := DEFMEMTECH);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ kready1 : out std_logic;
+ kstrobe1 : in std_logic;
+ kaddress1 : in std_logic_vector(5 downto 0);
+ kdata1 : in std_logic_vector(11 downto 0);
+ kready2 : in std_logic;
+ kstrobe2 : out std_logic;
+ kdata2 : out std_logic_vector(11 downto 0);
+ error : out std_logic;
+ samp_fact : in std_logic;
+ kstrobeq1 : in std_logic;
+ kdataq1 : in std_logic_vector(7 downto 0);
+ kdataq2 : out std_logic_vector(7 downto 0);
+ kaddq : in std_logic_vector(7 downto 0);
+ krdq : in std_logic;
+ krddataq : out std_logic_vector(7 downto 0);
+ startgen : in std_logic
+ );
+end component;
+
+component dctmem1cont is
+ generic (
+ memtech : integer := DEFMEMTECH);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ kready1 : out std_logic;
+ kstrobe1 : in std_logic;
+ kdata1 : in std_logic_vector(11 downto 0);
+ kready2 : in std_logic;
+ kstrobe2 : out std_logic;
+ kdata2 : out std_logic_vector(11 downto 0);
+ error : out std_logic;
+ samp_fact : in std_logic;
+ kstrobeq1 : in std_logic;
+ kdataq1 : in std_logic_vector(7 downto 0);
+ kdataq2 : out std_logic_vector(7 downto 0)
+ );
+end component;
+
+component dctmem2cont is
+ generic (
+ memtech : integer := DEFMEMTECH);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ kready1 : out std_logic;
+ kstrobe1 : in std_logic;
+ kdata1 : in std_logic_vector(15 downto 0);
+ kready2 : in std_logic;
+ kstrobe2 : out std_logic;
+ kdata2 : out std_logic_vector(15 downto 0);
+ error : out std_logic;
+ startgen : in std_logic
+ );
+end component;
+
+component idct1 is
+ port ( rst : in std_ulogic;
+ clk : in std_ulogic;
+ ready1 : out std_logic;
+ strobe1 : in std_logic;
+ coeffin : in std_logic_vector (11 downto 0);
+ quantin : in std_logic_vector (7 downto 0);
+ outdata : out std_logic_vector (15 downto 0);
+ ready2 : in std_logic;
+ strobe2 : out std_logic;
+ startgen : in std_logic
+ );
+end component;
+
+component idct2 is
+ port ( rst : in std_ulogic;
+ clk : in std_ulogic;
+ ready1 : out std_logic;
+ strobe1 : in std_logic;
+ coeffin : in std_logic_vector (15 downto 0);
+ outdata : out std_logic_vector (7 downto 0);
+ ready2 : in std_logic;
+ strobe2 : out std_logic;
+ startgen : in std_logic
+ );
+end component;
+
+component yccambaif
+ generic (
+ memtech : integer := DEFMEMTECH;
+ shindex : integer := 0;
+ haddr : integer := 0;
+ hmask : integer := 16#fff#;
+ hirq : integer := 0;
+ pindex : integer := 0;
+ paddr : integer := 0;
+ pmask : integer := 16#fff#);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbsi : in ahb_slv_in_type;
+ ahbso : out ahb_slv_out_type;
+ apbi : in apb_slv_in_type;
+ apbo : out apb_slv_out_type;
+ kready : in std_logic;
+ kstrobe : out std_logic;
+ kdata : out std_logic_vector(11 downto 0);
+ samp_fact : out std_logic;
+ error : in std_logic_vector(2 downto 0);
+ xmcumax : out std_logic_vector(5 downto 0);
+ ymcumax : out std_logic_vector(4 downto 0);
+ incaddy : out std_logic_vector(15 downto 0);
+ incaddmcux : out std_logic_vector(15 downto 0);
+ incaddmcuy : out std_logic_vector(10 downto 0);
+ fbstartadd : out std_logic_vector(31 downto 0);
+ startgen : out std_logic;
+ kstrobeq : out std_logic;
+ kdataq : out std_logic_vector(7 downto 0)
+ );
+end component;
+
+component yccmemcont
+ generic (
+ memtech : integer := DEFMEMTECH);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ kready1 : out std_logic;
+ kstrobe1 : in std_logic;
+ kdata1 : in std_logic_vector(7 downto 0);
+ kready2 : in std_logic;
+ kstrobe2 : out std_logic;
+ kdata2 : out std_logic_vector(23 downto 0);
+ samp_fact : in std_logic;
+ error : out std_logic;
+ startgen : in std_logic
+ );
+end component;
+
+component yccrgb
+ generic (
+ memtech : integer := DEFMEMTECH;
+ hirq : integer := 0;
+ mhindex : integer := 0;
+ chprot : integer := 3);
+ port (
+ rst : in std_ulogic;
+ clk : in std_ulogic;
+ ahbmi : in ahb_mst_in_type;
+ ahbmo : out ahb_mst_out_type;
+ kready : out std_logic;
+ kstrobe : in std_logic;
+ kdata : in std_logic_vector(23 downto 0);
+ xmcumax : in std_logic_vector(5 downto 0);
+ ymcumax : in std_logic_vector(4 downto 0);
+ incaddy : in std_logic_vector(15 downto 0);
+ incaddmcux : in std_logic_vector(15 downto 0);
+ incaddmcuy : in std_logic_vector(10 downto 0);
+ fbstartadd : in std_logic_vector(31 downto 0);
+ startgen : in std_logic
+ );
+end component;
+
+end;
kstrobe2 : out std_logic;
kdata2 : out std_logic_vector(23 downto 0);
samp_fact : in std_logic;
- error : out std_logic
+ error : out std_logic;
+ startgen : in std_logic
);
end;
-- samp_fact = 0 -> 4:1:1
comb : process (r, rst, kstrobe1, kdata1, kready2, samp_fact, y0dataout, y1dataout,
- cb0dataout, cb1dataout, cr0dataout, cr1dataout)
+ cb0dataout, cb1dataout, cr0dataout, cr1dataout, startgen)
variable v : control_reg;
variable vkready1 : std_logic;
variable verror : std_logic;
end if;
-- reset part
- if rst = '0' then
+ if rst = '0' or startgen = '1' then
v.swf := mem0;
v.swb := mem0;
v.mem0state := empty;
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