alu sencsitivity list modified.

assertion added to the test.

diff --git a/simulation/cpu/alu/alu.vhd b/simulation/cpu/alu/alu.vhd
index 6441040..408b0be 100644 (file)
--- a/simulation/cpu/alu/alu.vhd
+++ b/simulation/cpu/alu/alu.vhd
@@ -35,7 +35,7 @@ begin
     adc_port : alu_adc port map (a, b, adc_o, cin, adc_cout, adc_n, adc_v, adc_z);
     and_port : alu_and port map (a, b, and_o, and_n, and_z);
 
-    p : process (a, b, m, cin, adc_o, and_o)
+    p : process (adc_o, adc_cout, adc_n, adc_v, adc_z, and_o, and_n, and_z)
     begin
     -- m is form of  "aaabbbcc"
     if m(1 downto 0) = "01" then

diff --git a/simulation/cpu/alu/testbench_alu.vhd b/simulation/cpu/alu/testbench_alu.vhd
index 0979a38..6ce192b 100644 (file)
--- a/simulation/cpu/alu/testbench_alu.vhd
+++ b/simulation/cpu/alu/testbench_alu.vhd
@@ -21,7 +21,7 @@ architecture stimulus of testbench_alu is
     end component;
     signal aa, bb, oo, mm : std_logic_vector (7 downto 0);
     signal ccin, ccout, nn, vv, zz, rreset : std_logic;
-    constant interval : time := 20 ns;
+    constant interval : time := 1 ns;
 begin
     dut : alu port map (aa, bb, mm, oo, ccin, ccout, nn, vv, zz, rreset);
 
@@ -43,6 +43,8 @@ begin
         mm <= "01100101";
         ccin <= '0';
         wait for interval;
+        assert (oo = x"e4" and ccout = '0' and vv = '1' ) 
+            report "adc error." severity failure;
 
         write(out_line, string'("adc test 2"));
         writeline(output, out_line);
@@ -51,6 +53,8 @@ begin
         mm <= "01100001";
         ccin <= '0';
         wait for interval;
+        assert (oo = x"04" and ccout = '1' and vv = '1' ) 
+            report "adc error." severity failure;
 
         write(out_line, string'("adc test 3"));
         writeline(output, out_line);
@@ -59,6 +63,8 @@ begin
         mm <= "01100001";
         ccin <= '0';
         wait for interval;
+        assert (oo = x"6f" and ccout = '1' and vv = '1' ) 
+            report "adc error." severity failure;
 
         write(out_line, string'("adc test 4"));
         writeline(output, out_line);
@@ -67,6 +73,9 @@ begin
         mm <= "01111101";
         ccin <= '0';
         wait for interval;
+        assert (oo = conv_std_logic_vector(10#160#, 8) and
+                ccout = '0' and vv = '1' ) 
+            report "adc error." severity failure;
 
         write(out_line, string'("adc test 5"));
         writeline(output, out_line);
@@ -75,6 +84,9 @@ begin
         mm <= "01111101";
         ccin <= '0';
         wait for interval;
+        assert (oo = conv_std_logic_vector(10#91#, 8) and 
+                ccout = '0' and vv = '0' ) 
+            report "adc error." severity failure;
 
         write(out_line, string'("adc test 6"));
         writeline(output, out_line);
@@ -83,6 +95,8 @@ begin
         mm <= "01111101";
         ccin <= '0';
         wait for interval;
+        assert (oo = x"09" and ccout = '1' and vv = '0' ) 
+            report "adc error." severity failure;
 
         write(out_line, string'("and test 1"));
         writeline(output, out_line);
@@ -91,6 +105,8 @@ begin
         mm <= "00100001";
         ccin <= '0';
         wait for interval;
+        assert (oo = x"50" and nn = '0' and zz = '0' ) 
+            report "adc error." severity failure;
 
         write(out_line, string'("and test 2"));
         writeline(output, out_line);
@@ -99,6 +115,8 @@ begin
         mm <= "00100001";
         ccin <= '0';
         wait for interval;
+        assert (oo = x"00" and nn = '0' and zz = '1' ) 
+            report "adc error." severity failure;
 
         write(out_line, string'("and test 3"));
         writeline(output, out_line);
@@ -107,8 +125,10 @@ begin
         mm <= "00100001";
         ccin <= '0';
         wait for interval;
+        assert (oo = x"aa" and nn = '1' and zz = '0' ) 
+            report "adc error." severity failure;
 
-        write(out_line, string'("test done"));
+        write(out_line, string'("test completed successfully."));
         writeline(output, out_line);
         wait;
     end process;