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authorastoria-d@fc <astoria-d@fc>
Mon, 3 Oct 2016 04:35:10 +0000 (13:35 +0900)
committerastoria-d@fc <astoria-d@fc>
Mon, 3 Oct 2016 04:35:10 +0000 (13:35 +0900)
de0_cv_nes/dummy-mos6502.vhd patch | blob | history
de0_cv_nes/simulation/modelsim/dummy-cpu.do [new file with mode: 0644] patch | blob

diff --git a/de0_cv_nes/dummy-mos6502.vhd b/de0_cv_nes/dummy-mos6502.vhd
index fc38edf..1f2e04a 100644 (file)
--- a/de0_cv_nes/dummy-mos6502.vhd
+++ b/de0_cv_nes/dummy-mos6502.vhd
@@ -426,12 +426,12 @@ end;
 \r
                     elsif (global_step_cnt = 5) then\r
                         --step4 = scroll test and ppu reg read test.\r
-                        if (scl_step_cnt = 0) then\r
+                        if (scl_step_cnt = 123) then\r
                             --x scroll pos=123\r
                             io_out(16#2005#, 123);\r
                         elsif (scl_step_cnt = 1 * cpu_io_multi) then\r
                             --y scroll pos=100\r
-                            io_out(16#2005#, 110);\r
+                            io_out(16#2005#, 100);\r
 \r
                         elsif (scl_step_cnt = 2 * cpu_io_multi) then\r
                             --read status reg.\r
diff --git a/de0_cv_nes/simulation/modelsim/dummy-cpu.do b/de0_cv_nes/simulation/modelsim/dummy-cpu.do
new file mode 100644 (file)
index 0000000..0bf6a9e
--- /dev/null
+++ b/de0_cv_nes/simulation/modelsim/dummy-cpu.do
@@ -0,0 +1,176 @@
+transcript on\r
+if {[file exists rtl_work]} {\r
+       vdel -lib rtl_work -all\r
+}\r
+vlib rtl_work\r
+vmap work rtl_work\r
+\r
+vcom -93 -work work {../../chip_selector.vhd}\r
+vcom -93 -work work {../../mem/ram.vhd}\r
+vcom -93 -work work {../../apu.vhd}\r
+\r
+vcom -93 -work work {../../mem/chr_rom.vhd}\r
+vcom -93 -work work {../../ppu/ppu.vhd}\r
+vcom -93 -work work {../../ppu/render.vhd}\r
+#vcom -93 -work work {../../dummy-ppu.vhd}\r
+\r
+vcom -93 -work work {../../dummy-mos6502.vhd}\r
+#vcom -93 -work work {../../dummy-smb-rom.vhd}\r
+#vcom -93 -work work {../../mem/prg_rom.vhd}\r
+#vcom -93 -work work {../../mos6502.vhd}\r
+\r
+vcom -93 -work work {../../de0_cv_nes.vhd}\r
+vcom -93 -work work {../../testbench_motones_sim.vhd}\r
+\r
+vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc"  testbench_motones_sim\r
+\r
+##script custom part...\r
+\r
+#run 450ms\r
+\r
+#################################### General.... ###########################################\r
+\r
+#add wave -label dbg_cnt -radix hex  sim:/testbench_motones_sim/sim_board/po_dbg_cnt;\r
+add wave -label po_exc_cnt -radix hex  sim:/testbench_motones_sim/sim_board/po_exc_cnt;\r
+add wave -label rst_n               sim:/testbench_motones_sim/sim_board/pi_rst_n;\r
+add wave -label wr_nmi_n            sim:/testbench_motones_sim/sim_board/wr_nmi_n;\r
+#add wave -label base_clk            sim:/testbench_motones_sim/sim_board/pi_base_clk;\r
+#add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en;\r
+add wave -label wr_cpu_en           sim:/testbench_motones_sim/sim_board/wr_cpu_en(0);\r
+add wave -label wr_oe_n             sim:/testbench_motones_sim/sim_board/wr_oe_n;\r
+add wave -label wr_we_n             sim:/testbench_motones_sim/sim_board/wr_we_n;\r
+add wave -label addr -radix hex     sim:/testbench_motones_sim/sim_board/wr_addr;\r
+add wave -label d_io -radix hex     sim:/testbench_motones_sim/sim_board/wr_d_io;\r
+\r
+##################################### CPU part.... ###########################################\r
+#\r
+##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg*;\r
+#add wave -divider cpu\r
+#\r
+#add wave -label reg_inst -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_inst;\r
+#add wave -label reg_acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_acc;\r
+#add wave -label reg_x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_x;\r
+#add wave -label reg_y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_y;\r
+#add wave -label reg_sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_sp;\r
+#add wave -label reg_status -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_status;\r
+#\r
+##add wave -divider internal_reg\r
+##add wave -label reg_main_cur_state  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_main_state;\r
+###add wave -label reg_sub_cur_state   sim:/testbench_motones_sim/sim_board/cpu_inst/reg_sub_state;\r
+##add wave -label reg_pc_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_pc_l;\r
+##add wave -label reg_pc_h -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_pc_h;\r
+##add wave -label reg_idl_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_idl_l;\r
+##add wave -label reg_idl_h -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_idl_h;\r
+##add wave -label reg_tmp_pg_crossed  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_tmp_pg_crossed;\r
+#\r
+#\r
+##################################### APU part.... ###########################################\r
+#add wave -divider apu\r
+#add wave -label wr_rdy  sim:/testbench_motones_sim/sim_board/wr_rdy;\r
+#add wave -label reg_dma_cur_state   sim:/testbench_motones_sim/sim_board/apu_inst/reg_dma_cur_state;\r
+#add wave -label reg_dma_addr -radix hex     sim:/testbench_motones_sim/sim_board/apu_inst/reg_dma_addr;\r
+##add wave -label pi_rnd_en  sim:/testbench_motones_sim/sim_board/apu_inst/pi_rnd_en;\r
+##add wave -label reg_dma_cnt sim:/testbench_motones_sim/sim_board/apu_inst/reg_dma_cnt;\r
+#\r
+#add wave -label reg_spr_ce_n  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_ce_n;\r
+#add wave -label reg_spr_rd_n  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_rd_n;\r
+#add wave -label reg_spr_wr_n  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_wr_n;\r
+#add wave -label reg_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_addr;\r
+#add wave -label reg_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/apu_inst/reg_spr_data;\r
+#\r
+#\r
+#\r
+#view structure\r
+#view signals\r
+#\r
+#run 25 us\r
+#wave zoom full\r
+#\r
+#run 900 us\r
+\r
+\r
+#################################### PPU part.... ###########################################\r
+add wave -divider ppu\r
+add wave -label pi_ce_n         -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ce_n;\r
+add wave -label ppu_ctrl        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_ctrl;\r
+add wave -label ppu_mask        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_mask;\r
+add wave -label ppu_status      -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/pi_ppu_status;\r
+add wave -label oam_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_addr;\r
+add wave -label oam_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_oam_data;\r
+add wave -label ppu_scroll_x    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_x;\r
+add wave -label ppu_scroll_y    -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_scroll_y;\r
+add wave -label ppu_addr        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_addr;\r
+add wave -label ppu_data        -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/reg_ppu_data;\r
+#add wave -label reg_v_cur_state            sim:/testbench_motones_sim/sim_board/ppu_inst/reg_v_cur_state;\r
+\r
+add wave -divider vram\r
+add wave -label v_rd_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_rd_n;\r
+add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_wr_n;\r
+add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
+add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
+\r
+add wave -divider render\r
+#add wave -label vga_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_x;\r
+#add wave -label vga_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_y;\r
+add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
+add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
+\r
+\r
+add wave -divider bg\r
+#add wave -label wr_rnd_en  sim:/testbench_motones_sim/sim_board/wr_rnd_en;\r
+add wave -label reg_v_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_v_cur_state;\r
+#add wave -label prf_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_x;\r
+#add wave -label prf_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_prf_y;\r
+\r
+add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_nt;\r
+add wave -label disp_attr   -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_disp_attr;\r
+add wave -label sft_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_l;\r
+add wave -label sft_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_sft_ptn_h;\r
+\r
+add wave -divider sprite\r
+add wave -label reg_s_oam_cur_state sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cur_state;\r
+add wave -label reg_s_oam_ce_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_ce_n;\r
+add wave -label reg_s_oam_rd_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_rd_n;\r
+add wave -label reg_s_oam_wr_n  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_wr_n;\r
+add wave -label reg_s_oam_addr -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_addr;\r
+add wave -label reg_s_oam_data -radix hex  sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_data;\r
+\r
+#add wave -label reg_s_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_s_oam_cpy_cnt;\r
+#add wave -label reg_p_oam_cpy_cnt   sim:/testbench_motones_sim/sim_board/render_inst/reg_p_oam_cpy_cnt;\r
+#add wave -label reg_spr_eval_cnt    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_eval_cnt;\r
+\r
+add wave -label wr_spr_ce_n  sim:/testbench_motones_sim/sim_board/wr_spr_ce_n;\r
+add wave -label wr_spr_rd_n  sim:/testbench_motones_sim/sim_board/wr_spr_rd_n;\r
+add wave -label wr_spr_wr_n  sim:/testbench_motones_sim/sim_board/wr_spr_wr_n;\r
+add wave -label wr_spr_addr -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_addr;\r
+add wave -label wr_spr_data -radix hex  sim:/testbench_motones_sim/sim_board/wr_spr_data;\r
+\r
+add wave -label reg_spr_y_tmp -radix hex    sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_y_tmp;\r
+add wave -label reg_spr_tile_tmp -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_tile_tmp;\r
+add wave -label reg_spr_attr -radix hex     sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_attr;\r
+add wave -label reg_spr_x -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_x;\r
+add wave -label reg_spr_ptn_sft_start -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_sft_start;\r
+add wave -label reg_spr_ptn_l -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_l;\r
+add wave -label reg_spr_ptn_h -radix hex        sim:/testbench_motones_sim/sim_board/render_inst/reg_spr_ptn_h;\r
+\r
+add wave -divider palette\r
+add wave -label plt_addr -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_addr;\r
+add wave -label plt_data -radix hex sim:/testbench_motones_sim/sim_board/render_inst/reg_plt_data;\r
+\r
+\r
+add wave -divider vga\r
+add wave -label h_sync_n       sim:/testbench_motones_sim/sim_board/po_h_sync_n;\r
+add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/po_v_sync_n;\r
+add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/po_r;\r
+add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/po_g;\r
+add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/po_b;\r
+\r
+\r
+\r
+view structure\r
+view signals\r
+\r
+run 25 us\r
+wave zoom full\r
+\r
+run 150us\r
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