- rx_dma_dsc0.next_descripter = &rx_dma_dsc1;
- rx_dma_dsc0.start_address = dummy_buffer0;
- rx_dma_dsc0.x_count = RXIF_BUFSIZE;
- rx_dma_dsc0.x_modify = sizeof(dummy_buffer0[0]);
- rx_dma_dsc0.config =
- 7 <<12 | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
- 7 << 8 | // NDSIZE, the # of element of the next descripter to fetch
- 0 << 7 | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
- 1 << 6 | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
- 1 << 5 | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
- 0 << 4 | // DMA2D, 0:Linear DMA, 1:2D DMA
- 2 << 2 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
- 1 << 1 | // WNR, 0:Read from memory, 1:Write to Memory
- 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
-
- rx_dma_dsc1.next_descripter = &rx_dma_dsc0;
- rx_dma_dsc1.start_address = dummy_buffer1;
- rx_dma_dsc1.x_count = RXIF_BUFSIZE;
- rx_dma_dsc1.x_modify = sizeof(dummy_buffer1[0]);
- rx_dma_dsc1.config =
- 7 <<12 | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
- 7 << 8 | // NDSIZE, the # of element of the next descripter to fetch
- 0 << 7 | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
- 1 << 6 | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
- 1 << 5 | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
- 0 << 4 | // DMA2D, 0:Linear DMA, 1:2D DMA
- 2 << 2 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
- 1 << 1 | // WNR, 0:Read from memory, 1:Write to Memory
- 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
-
+ rx_dma_dsc[0].next_descripter = &rx_dma_dsc[1];
+ rx_dma_dsc[0].start_address = rxif_buffer[0];
+ rx_dma_dsc[0].x_count = RXIF_BUFSIZE;
+ rx_dma_dsc[0].x_modify = sizeof(rxif_buffer[0][0]);
+ rx_dma_dsc[0].config =
+ FLOW_LARGE | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
+ NDSIZE_7 | // NDSIZE, the # of element of the next descripter to fetch
+ 1 << DI_EN_P | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
+ 0 << DI_SEL_P | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
+ 0 << RESTART_P | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
+ 0 << DMA2D_P | // DMA2D, 0:Linear DMA, 1:2D DMA
+ WDSIZE_32 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
+ 1 << WNR_P | // WNR, 0:Read from memory, 1:Write to Memory
+ 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
+
+ rx_dma_dsc[1].next_descripter = &rx_dma_dsc[0];
+ rx_dma_dsc[1].start_address = rxif_buffer[1];
+ rx_dma_dsc[1].x_count = RXIF_BUFSIZE;
+ rx_dma_dsc[1].x_modify = sizeof(rxif_buffer[1][0]);
+ rx_dma_dsc[1].config =
+ FLOW_LARGE | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
+ NDSIZE_7 | // NDSIZE, the # of element of the next descripter to fetch
+ 1 << DI_EN_P | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
+ 0 << DI_SEL_P | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
+ 0 << RESTART_P | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
+ 0 << DMA2D_P | // DMA2D, 0:Linear DMA, 1:2D DMA
+ WDSIZE_32 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
+ 1 << WNR_P | // WNR, 0:Read from memory, 1:Write to Memory
+ 1 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
+
+ // DMAコントローラの初期状態設定
+ // ここではDMAをイネーブルにしない。また、バッファクリアする
+ *pDMA1_CONFIG =
+ FLOW_LARGE | // FLOW, 0:Stop, 1:Auto buffer, 4:Desc array, 6:Desc List small, 7:Desc, List, Large
+ NDSIZE_7 | // NDSIZE, the # of element of the next descripter to fetch
+ 1 << DI_EN_P | // DI_EN, 0:No interrupt at the end, 1:Interrupt at the end
+ 0 << DI_SEL_P | // DI_SEL, 0:Interrupt at the end of outer loop, 1:Interrupt at the end of inter loop
+ 1 << RESTART_P | // RESTART, 0:Keep DMA FIFO before start, 1:Purge DMA FIFO before start
+ 0 << DMA2D_P | // DMA2D, 0:Linear DMA, 1:2D DMA
+ WDSIZE_32 | // WDSIZE, 0:8bit, 1:16bit, 2:32bit,3:reserved
+ 1 << WNR_P | // WNR, 0:Read from memory, 1:Write to Memory
+ 0 << 0 ; // DMA_EN, 0:Disable DMA, 1:Enable DMA
+ *pDMA1_NEXT_DESC_PTR = &rx_dma_dsc[0];
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