--- /dev/null
+MCU_164P = MCU=atmega164p TARGET=kazzo_mega164p PCB_REVISION=1
+MCU_16 = MCU=atmega16 TARGET=kazzo_mega16 PCB_REVISION=1
+MCU_168 = MCU=atmega168 TARGET=kazzo_mega168 PCB_REVISION=2
+SOURCE_ROOT = \
+ Makefile COPYING kazzo_test.exe kazzo_pcb_1.png kazzo_pcb_2.png \
+ readme.txt usbrequest.txt mcu16.txt mcu88.txt \
+ kazzo_mega16.hex kazzo_mega164p.hex kazzo_mega168.hex
+SOURCE_FIRMWARE = \
+ avr_main.c bus_access.c disk_access.c flashmemory.c mcu_program.c \
+ bus_access.h disk_access.h flashmemory.h kazzo_request.h kazzo_task.h type.h usbconfig.h mcu_program.h \
+ firmware.mak usbdrv/*
+SOURCE_ECHO = Makefile file.c hostecho.c ihex.c opendevice.c usbdevice.c \
+ file.h ihex.h opendevice.h usbdevice.h
+SOURCE_MODULE = reader_kazzo.c usb_device.c reader_kazzo.h reader_master.h usb_device.h
+WINDOWS_DRIVER = libusb0.dll kazzo.inf libusb0.sys
+
+all:
+ (cd firmware;make -f firmware.mak $(MCU_164P))
+ (cd firmware;make -f firmware.mak $(MCU_16))
+ (cd firmware;make -f firmware.mak $(MCU_168))
+ (cd hostecho;make)
+clean:
+ (cd firmware;make -f firmware.mak $(MCU_164P) clean)
+ (cd firmware;make -f firmware.mak $(MCU_16) clean)
+ (cd firmware;make -f firmware.mak $(MCU_168) clean)
+ (cd hostecho;make clean)
+p4p:
+ (cd firmware;make -f firmware.mak $(MCU_164P) program)
+p4f:
+ (cd firmware;make -f firmware.mak $(MCU_164P) fuse)
+package:
+ (cd ..; 7za a kazzo_xxx.zip \
+ $(addprefix kazzo/,$(SOURCE_ROOT)) \
+ $(addprefix kazzo/firmware/,$(SOURCE_FIRMWARE)) \
+ $(addprefix kazzo/hostecho/,$(SOURCE_ECHO)) \
+ $(addprefix kazzo/hostmodule/,$(SOURCE_MODULE)) \
+ $(addprefix kazzo/windows_driver/,$(WINDOWS_DRIVER)) \
+ )
--- /dev/null
+#include <avr/wdt.h>
+#include <avr/interrupt.h>
+#include <util/delay.h>
+#include <string.h>
+#include <avr/pgmspace.h>
+#include "usbdrv.h"
+#include "bus_access.h"
+#include "disk_access.h"
+#include "flashmemory.h"
+#include "mcu_program.h"
+#include "kazzo_request.h"
+
+//---- global variable ----
+#define REQUEST_NOP (0xee)
+static struct write_command{
+ enum request request;
+ uint16_t address, length, offset;
+}request_both_write, request_cpu_program, request_ppu_program;
+
+//---- function start ----
+/*static uint8_t cpu_buffer[FLASH_PACKET_SIZE];
+static uint8_t ppu_buffer[FLASH_PACKET_SIZE];*/
+uchar usbFunctionWrite(uchar *data, uchar len)
+{
+ static uint8_t cpu_buffer[FLASH_PACKET_SIZE];
+ static uint8_t ppu_buffer[FLASH_PACKET_SIZE];
+ const uint16_t length = (uint16_t) len;
+ uchar i;
+ //decode masked data
+ for(i = 0; i < len; i++){
+ data[i] ^= 0xa5;
+ }
+ switch(request_both_write.request){
+ case REQUEST_CPU_WRITE_6502:
+ cpu_write_6502(request_both_write.address + request_both_write.offset, length, data);
+ goto BOTH_NEXT;
+ case REQUEST_CPU_WRITE_FLASH:
+ cpu_write_flash(request_both_write.address + request_both_write.offset, length, data);
+ goto BOTH_NEXT;
+ case REQUEST_PPU_WRITE:
+ ppu_write(request_both_write.address + request_both_write.offset, length, data);
+ goto BOTH_NEXT;
+ BOTH_NEXT:{
+ request_both_write.offset += length;
+ uchar ret = request_both_write.offset == request_both_write.length;
+ if(ret){
+ request_both_write.request = REQUEST_NOP;
+ }
+ return ret;
+ }
+ default:
+ break;
+ }
+ switch(request_cpu_program.request){
+ case REQUEST_FLASH_PROGRAM:
+ case REQUEST_FLASH_CONFIG_SET:{
+ memcpy(cpu_buffer + request_cpu_program.offset, data, length);
+ request_cpu_program.offset += length;
+ uchar ret = request_cpu_program.offset == request_cpu_program.length;
+ if(ret){
+ if(request_cpu_program.request == REQUEST_FLASH_CONFIG_SET){
+ flash_cpu_config(cpu_buffer, request_cpu_program.length);
+ }else{
+ flash_cpu_program(request_cpu_program.address, request_cpu_program.length, cpu_buffer);
+ }
+ request_cpu_program.request = REQUEST_NOP;
+ }
+ return ret;}
+ default:
+ break;
+ }
+ switch(request_ppu_program.request){
+ case REQUEST_FLASH_PROGRAM:
+ case REQUEST_FLASH_CONFIG_SET:{
+ memcpy(ppu_buffer + request_ppu_program.offset, data, length);
+ request_ppu_program.offset += length;
+ uchar ret = request_ppu_program.offset == request_ppu_program.length;
+ if(ret){
+ if(request_ppu_program.request == REQUEST_FLASH_CONFIG_SET){
+ flash_ppu_config(ppu_buffer, request_cpu_program.length);
+ }else{
+ flash_ppu_program(request_ppu_program.address, request_ppu_program.length, ppu_buffer);
+ }
+ request_ppu_program.request = REQUEST_NOP;
+ }
+ return ret;}
+ default:
+ break;
+ }
+ return 1;
+}
+
+//static uint8_t readbuffer[READ_PACKET_SIZE];
+usbMsgLen_t usbFunctionSetup(uchar d[8])
+{
+ static uint8_t readbuffer[READ_PACKET_SIZE];
+ static uint8_t status[2];
+ usbRequest_t *rq = (void *)d;
+ struct write_command *write_command;
+
+ switch((enum request) rq->bRequest){
+ case REQUEST_ECHO:
+ readbuffer[0] = rq->wValue.bytes[0];
+ readbuffer[1] = rq->wValue.bytes[1];
+ readbuffer[2] = rq->wIndex.bytes[0];
+ readbuffer[3] = rq->wIndex.bytes[1];
+ usbMsgPtr = readbuffer;
+ return 4;
+ case REQUEST_PHI2_INIT:
+ flash_both_idle();
+ phi2_init();
+ return 0;
+ case REQUEST_CPU_READ:
+ cpu_read(rq->wValue.word, rq->wLength.word, readbuffer);
+ goto xxx_read;
+ case REQUEST_CPU_READ_6502:
+ cpu_read_6502(rq->wValue.word, rq->wLength.word, readbuffer);
+ goto xxx_read;
+ case REQUEST_PPU_READ:
+ ppu_read(rq->wValue.word, rq->wLength.word, readbuffer);
+ goto xxx_read;
+ case REQUEST_CPU_WRITE_6502: case REQUEST_CPU_WRITE_FLASH:
+ case REQUEST_PPU_WRITE:
+ write_command = &request_both_write;
+ goto xxx_write;
+ case REQUEST_FLASH_PROGRAM:
+ case REQUEST_FLASH_CONFIG_SET:
+ if(rq->wIndex.word == INDEX_CPU){
+ write_command = &request_cpu_program;
+ }else{
+ write_command = &request_ppu_program;
+ }
+ goto xxx_write;
+ xxx_write:
+ write_command->request = rq->bRequest;
+ write_command->length = rq->wLength.word;
+ write_command->address = rq->wValue.word;
+ write_command->offset = 0;
+ return USB_NO_MSG; //goto usbFunctionWrite
+/* case REQUEST_FLASH_BUFFER_GET:
+ if(rq->wIndex.word == INDEX_CPU){
+ usbMsgPtr = cpu_buffer;
+ }else{
+ usbMsgPtr = ppu_buffer;
+ }
+ return FLASH_PACKET_SIZE;*/
+ case REQUEST_DISK_STATUS_GET:
+ //usbMsgPtr = status;
+ return 0; //disk_status_get(status);
+ case REQUEST_DISK_READ:
+ disk_init(DISK_READ);
+ return 0;
+ case REQUEST_DISK_WRITE:
+ disk_init(DISK_WRITE);
+ return 0;
+ case REQUEST_FLASH_STATUS:
+ usbMsgPtr = status;
+ switch((enum index) rq->wIndex.word){
+ case INDEX_CPU:
+ status[0] = flash_cpu_status();
+ return 1;
+ case INDEX_PPU:
+ status[0] = flash_ppu_status();
+ return 1;
+ default:
+ status[0] = flash_cpu_status();
+ status[1] = flash_ppu_status();
+ return 2;
+ }
+ return 1;
+ case REQUEST_FLASH_DEVICE:
+ if(rq->wIndex.word == INDEX_CPU){
+ flash_cpu_device_get(status);
+ }else{
+ flash_ppu_device_get(status);
+ }
+ usbMsgPtr = status;
+ return 2;
+ case REQUEST_FLASH_ERASE:
+ if(rq->wIndex.word == INDEX_CPU){
+ flash_cpu_erase(rq->wValue.word);
+ }else{
+ flash_ppu_erase(rq->wValue.word);
+ }
+ return 0;
+ case REQUEST_VRAM_CONNECTION:
+ status[0] = vram_connection_get();
+ usbMsgPtr = status;
+ return 1;
+ case REQUEST_FIRMWARE_VERSION:{
+ __attribute__ ((section(".firmware.version")))
+ static const /*PROGMEM*/ char date[VERSION_STRING_SIZE] =
+#if PCB_REVISION == 1
+ "kazzo16"
+#endif
+#if PCB_REVISION == 2
+ "kazzo^8"
+#endif
+ " 0.1.3 / " __DATE__;
+ memcpy_P(readbuffer, date, rq->wLength.word);
+ goto xxx_read;}
+ case REQUEST_FIRMWARE_PROGRAM:{
+ void (*t)(uint8_t *buf, uint16_t address, uint16_t length);
+#if PCB_REVISION == 1
+ static const char signature[] = {'k', 'a', 'z', 'z', 'o', '1', '6'};
+#endif
+#if PCB_REVISION == 2
+ static const char signature[] = {'k', 'a', 'z', 'z', 'o', '^', '8'};
+#endif
+ const uint16_t address = rq->wValue.word;
+ const uint16_t length = rq->wIndex.word;
+ if(address >= 0x3800){
+ return 0;
+ }
+ if(((address & 0x3f00) == 0) && (length < 0x1800)){
+ return 0;
+ }
+ if(length + address > 0x3800){
+ return 0;
+ }
+ cpu_read(0x3780 - 0x2000 + 0x6000, sizeof(signature), readbuffer);
+ if(memcmp(readbuffer, signature, sizeof(signature)) == 0){
+ usbDeviceDisconnect();
+ memcpy_P(&t, &BOOTLOADER_ASSIGN.programmer, sizeof(BOOTLOADER_ASSIGN.programmer));
+ (*t)(readbuffer, address, length);
+ }
+ }return 0;
+ case REQUEST_FIRMWARE_DOWNLOAD:{
+ const /*PROGMEM*/ uint8_t *firm = (const /*PROGMEM*/ uint8_t *) rq->wValue.word;
+ memcpy_P(readbuffer, firm, rq->wLength.word);
+ }
+ goto xxx_read;
+ xxx_read:
+ usbMsgPtr = readbuffer;
+ return rq->wLength.word;
+ }
+ return 0;
+}
+
+int main(void)
+{
+ static const struct write_command wc_init = {
+ .request = REQUEST_NOP, .length = 0, .offset = 0
+ };
+ request_both_write = wc_init;
+ request_cpu_program = wc_init;
+ request_ppu_program = wc_init;
+
+ bus_init();
+ usbInit();
+ usbDeviceDisconnect();
+ {
+ uchar i;
+ i = 0;
+ while(--i){
+ wdt_reset();
+ _delay_ms(1);
+ }
+ }
+ usbDeviceConnect();
+ wdt_enable(WDTO_500MS);
+ sei();
+ for(;;){
+ wdt_reset();
+ usbPoll();
+ //disk_process();
+ flash_process();
+ }
+ return 0;
+}
--- /dev/null
+#include <util/delay.h>
+#include <avr/io.h>
+#include "type.h"
+#include "bus_access.h"
+
+//avr/io.h use many macros, I want use IO access by inline function...
+#define IO_DIRECTION(NAME) (DDR##NAME)
+#define IO_OUT(NAME) (PORT##NAME)
+#define IO_IN(NAME) (PIN##NAME)
+/*
+--------- assignment and functions for PCB revision 1.x --------
+*/
+#if PCB_REVISION == 1
+/* PAx: output only
+connected CPU and PPU databus*/
+#define ADDRESSBUS_A0_A7_DIR IO_DIRECTION(A)
+#define ADDRESSBUS_A0_A7_OUT IO_OUT(A)
+/* PBx: output/input
+connected address high latch(HC574), CPU and PPU databus*/
+#define DATABUS_DIR IO_DIRECTION(B)
+#define DATABUS_OUT IO_OUT(B)
+#define DATABUS_IN IO_IN(B)
+/*PCx: output ADDRESS_HIGH_LATCH connect HC574 clock pin, bus control signal
+VRAM_CS is input port this is design mistake!
+*/
+#define BUS_CONTROL_DIR IO_DIRECTION(C)
+#define BUS_CONTROL_OUT IO_OUT(C)
+enum iobit_bus_control{
+ CPU_PHI2 = 0, CPU_ROMCS, CPU_RW,
+ RESERVE_PPU_POS_A13, PPU_RD, PPU_WR,
+ VRAM_CS, ADDRESS_HIGH_LATCH
+};
+/*PDx: use input, empty pin is output*/
+#define USB_MISC_DIR IO_DIRECTION(D)
+#define USB_MISC_PULLUP IO_OUT(D)
+#define USB_MISC_IN IO_IN(D)
+enum iobit_usb_misc{
+ USB_DPLUS = 2, CPU_IRQ,
+ USB_DMINUS, VRAM_A10
+};
+#endif
+/*
+--------- assignment and functions for PCB revision 2.x --------
+*/
+#if PCB_REVISION == 2
+/* PBx: misc IO
+0:IO:USB D+ / PCINT0.vector.PCI0
+1:IO:USB D-
+2:I :VRAM A10
+3:I :VRAM CS# / MOSI
+4: O:Address Low Latch / MISO
+5: O:Address High Latch / SCK
+*/
+#define USB_MISC_DIR IO_DIRECTION(B)
+#define USB_MISC_PULLUP IO_OUT(B)
+#define USB_MISC_IN IO_IN(B)
+enum iobit_usb_misc{
+ USB_DPLUS = 0, USB_DMINUS,
+ VRAM_A10, VRAM_CS,
+ ADDRESS_LOW_LATCH, ADDRESS_HIGH_LATCH,
+ XTAL1, XTAL2
+};
+/* PCx: output; memory control + etc
+0:I :CPU IRQ# / PCINT8.vector.PCI1
+1: O:CPU PHI2
+2: O:CPU ROMCS#
+3: O:CPU R/W
+4: O:PPU RD#
+5: O:PPU WR#
+6:I :MCU RESET
+*/
+#define BUS_CONTROL_DIR IO_DIRECTION(C)
+#define BUS_CONTROL_OUT IO_OUT(C)
+enum iobit_bus_control{
+ CPU_IRQ = 0, CPU_PHI2, CPU_ROMCS, CPU_RW,
+ PPU_RD, PPU_WR
+};
+/*PD: IO; databus */
+#define DATABUS_DIR IO_DIRECTION(D)
+#define DATABUS_OUT IO_OUT(D)
+#define DATABUS_IN IO_IN(D)
+#endif
+
+enum databus_dir{
+ DATABUS_DIR_OUT = 0xff,
+ DATABUS_DIR_IN = 0
+};
+//when cpu_write_flash, phi2 must be low. when phi2 is high, mmc3 and vrc4 changes bank.
+enum {
+ BUS_CLOSE = ~(1 << CPU_PHI2),
+ ADDRESS_CLOSE = 0x3fff //CPU and PPU are mapped internal registers, cartridge closes buses
+};
+
+static inline uint8_t bit_get_negative(enum iobit_bus_control bit)
+{
+ uint8_t ret = (1 << bit);
+ return ~ret;
+}
+
+#if PCB_REVISION == 1
+/*
+address high databus assignment
+D0-D5: CPU and PPU A8-A13
+D6: CPU A14
+D7: PPU /A13
+*/
+static void address_set(uint16_t address)
+{
+ ADDRESSBUS_A0_A7_OUT = address & 0xff;
+ uint8_t high = (address & 0x7fff) >> 8; //mask A0-A14
+ if((address & (1 << 13)) == 0){ //if A13 == 0
+ high |= 0x80; //set /A13
+ }
+ DATABUS_OUT = high;
+ //phi2 pulse is needed mmc1
+ BUS_CONTROL_OUT = bit_get_negative(ADDRESS_HIGH_LATCH);
+ BUS_CONTROL_OUT = BUS_CLOSE;
+}
+
+void bus_init(void)
+{
+ ADDRESSBUS_A0_A7_DIR = 0xff;
+ DATABUS_DIR = DATABUS_DIR_OUT;
+ BUS_CONTROL_DIR = bit_get_negative(VRAM_CS); //VRAM_CS is input port
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ USB_MISC_DIR = (0b1100 << 4) | 0b0011; //empty pin use OUT
+ USB_MISC_PULLUP = (1 << CPU_IRQ) | (1 << VRAM_A10);
+ address_set(ADDRESS_CLOSE);
+}
+#endif
+#if PCB_REVISION == 2
+static void address_set(uint16_t address)
+{
+ const uint8_t portb = 0x05;
+ DATABUS_OUT = address & 0xff;
+ asm("cbi %0,%1" : :"M"(portb),"M"(ADDRESS_LOW_LATCH));
+ asm("sbi %0,%1" : :"M"(portb),"M"(ADDRESS_LOW_LATCH));
+ uint8_t high = (address & 0x7fff) >> 8; //mask A0-A14
+ if((address & (1 << 13)) == 0){ //if A13 == 0
+ high |= 0x80; //set /A13
+ }
+ DATABUS_OUT = high;
+ asm("cbi %0,%1" : :"M"(portb),"M"(ADDRESS_HIGH_LATCH));
+ asm("sbi %0,%1" : :"M"(portb),"M"(ADDRESS_HIGH_LATCH));
+ //phi2 pulse is needed mmc1
+ BUS_CONTROL_OUT = BUS_CLOSE | (1 << CPU_PHI2);
+ BUS_CONTROL_OUT = BUS_CLOSE;
+}
+void bus_init(void)
+{
+ DATABUS_DIR = DATABUS_DIR_OUT;
+ BUS_CONTROL_DIR = (1 << CPU_PHI2) | (1 << CPU_ROMCS) | (1 << CPU_RW) | (1 << PPU_RD) | (1 << PPU_WR);
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ USB_MISC_DIR = (1 << ADDRESS_HIGH_LATCH) | (1 << ADDRESS_LOW_LATCH);
+ USB_MISC_PULLUP = (1 << VRAM_A10)| (1 << VRAM_CS);
+ address_set(ADDRESS_CLOSE);
+}
+#endif
+
+/*
+make phi2 edge signal, this is needed by namcot mapper and RP2C33.
+*/
+void phi2_init(void)
+{
+ int i = 0x80;
+ while(i != 0){
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ BUS_CONTROL_OUT = BUS_CLOSE ^ (1 << CPU_PHI2);
+ i--;
+ }
+}
+
+//for RAM adapter DRAM refresh
+void phi2_update(void)
+{
+ static uint8_t i = 0;
+ uint8_t c = BUS_CLOSE;
+ if(i & 0b100){
+ c ^= 1 << CPU_PHI2;
+ }
+ BUS_CONTROL_OUT = c;
+ i += 1;
+}
+static inline void direction_write(void)
+{
+ DATABUS_DIR = DATABUS_DIR_OUT;
+ asm("nop");
+ asm("nop");
+ asm("nop");
+}
+
+static inline void direction_read(void)
+{
+ DATABUS_OUT = 0xff; //when input direction, pullup
+ DATABUS_DIR = DATABUS_DIR_IN;
+ asm("nop"); //wait for chaging port direction. do not remove.
+ asm("nop");
+ asm("nop");
+}
+//mmc5 ROM area need that phi2 is high
+void cpu_read(uint16_t address, uint16_t length, uint8_t *data)
+{
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ while(length != 0){
+ uint8_t c = BUS_CLOSE;
+ direction_write();
+ address_set(address);
+ if((address & 0x8000) != 0){
+ c &= bit_get_negative(CPU_ROMCS);
+// BUS_CONTROL_OUT = c;
+// BUS_CONTROL_OUT = bit_get_negative(CPU_ROMCS);
+ }
+ c |= 1 << CPU_PHI2;
+ BUS_CONTROL_OUT = c;
+ direction_read();
+ *data = DATABUS_IN;
+ data += 1;
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ address += 1;
+ length--;
+ }
+ direction_write();
+}
+
+void cpu_read_6502(uint16_t address, uint16_t length, uint8_t *data)
+{
+ while(length != 0){
+ //phi2 down
+/* uint8_t c = bit_get_negative(CPU_PHI2);
+ BUS_CONTROL_OUT = c;*/
+ uint8_t c = BUS_CLOSE;
+ //down -> up
+ direction_write();
+ address_set(address);
+ BUS_CONTROL_OUT = c;
+ clock_wait(1);
+
+ //phi2 up
+ c |= (1 << CPU_PHI2);
+ if((address & 0x8000) != 0){
+ c &= bit_get_negative(CPU_ROMCS);
+ }
+ BUS_CONTROL_OUT = c;
+ direction_read();
+ clock_wait(1);
+ *data = DATABUS_IN;
+ data += 1;
+
+ BUS_CONTROL_OUT = c;
+
+ //phi2 down, bus close
+ BUS_CONTROL_OUT = BUS_CLOSE;
+
+ address += 1;
+ length--;
+ }
+ address_set(ADDRESS_CLOSE);
+}
+
+void ppu_read(uint16_t address, uint16_t length, uint8_t *data)
+{
+ //BUS_CONTROL_OUT = BUS_CLOSE;
+ while(length != 0){
+ direction_write();
+ address_set(address);
+ BUS_CONTROL_OUT = bit_get_negative(PPU_RD) & bit_get_negative(CPU_PHI2);
+ direction_read();
+ *data = DATABUS_IN;
+ data += 1;
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ address += 1;
+ length--;
+ }
+ direction_write();
+}
+
+enum compare_status cpu_compare(uint16_t address, uint16_t length, const uint8_t *data)
+{
+ while(length != 0){
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ direction_write();
+ address_set(address);
+ BUS_CONTROL_OUT = bit_get_negative(CPU_ROMCS) | (1 << CPU_PHI2);
+ direction_read();
+ if(DATABUS_IN != *data){
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ direction_write();
+ return NG;
+ }
+ data += 1;
+ address += 1;
+ length--;
+ }
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ direction_write();
+ return OK;
+}
+enum compare_status ppu_compare(uint16_t address, uint16_t length, const uint8_t *data)
+{
+ while(length != 0){
+ direction_write();
+ address_set(address);
+ BUS_CONTROL_OUT = bit_get_negative(PPU_RD) & bit_get_negative(CPU_PHI2);;
+ direction_read();
+ if(DATABUS_IN != *data){
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ direction_write();
+ return NG;
+ }
+ data += 1;
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ address += 1;
+ length--;
+ }
+ direction_write();
+ return OK;
+}
+
+void cpu_write_6502_nowait(uint16_t address, uint16_t length, const uint8_t *data)
+{
+ while(length != 0){
+ uint8_t control;
+ address_set(address);
+
+ //phi2 down
+ control = bit_get_negative(CPU_RW) & bit_get_negative(CPU_PHI2);
+ BUS_CONTROL_OUT = control;
+
+ //phi2 up
+ control |= (1 << CPU_PHI2);
+ if((address & 0x8000) != 0){
+ control &= bit_get_negative(CPU_ROMCS);
+ }
+ BUS_CONTROL_OUT = control;
+
+ //data set
+ DATABUS_OUT = *data;
+ data++;
+
+ //phi2 down
+ control &= bit_get_negative(CPU_PHI2);
+ BUS_CONTROL_OUT = control;
+
+ //bus close
+ BUS_CONTROL_OUT = BUS_CLOSE;
+
+ address += 1;
+ length--;
+ }
+ address_set(ADDRESS_CLOSE);
+}
+
+/*
+/WE controlled write operation has busconflict
+PHI2 |-__________-
+R/W |----___-----
+/ROMCS|--_______---
+A0-A14|-<vaild address>-
+D0-D7 |--oo<i>**---
+o is dataout, i is datain, * is bus-confilict
+
+/CS controlled write operation is clean write cycle for flash memory
+PHI2 |-__________-
+R/W |--_______---
+/ROMCS|----___-----
+A0-A14|-<vaild address>-
+D0-D7 |----<iii>---
+*/
+static inline void cpu_write_flash_waveform(uint16_t address, uint8_t data)
+{
+ uint8_t control = bit_get_negative(CPU_PHI2);
+ address_set(address);
+ if(0){ //R/W = /WE controlled write operation
+ if((address & 0x8000) != 0){
+ control &= bit_get_negative(CPU_ROMCS);
+ BUS_CONTROL_OUT = control;
+ }
+ control &= bit_get_negative(CPU_RW);
+ BUS_CONTROL_OUT = control;
+ DATABUS_OUT = data;
+ control |= 1 << CPU_RW; //R/W close
+ BUS_CONTROL_OUT = control;
+ }else{ ///ROMCS = /CS controlled write operation
+ control &= bit_get_negative(CPU_RW);
+ BUS_CONTROL_OUT = control;
+ if((address & 0x8000) != 0){
+ control &= bit_get_negative(CPU_ROMCS);
+ BUS_CONTROL_OUT = control;
+ }
+ DATABUS_OUT = data;
+ control |= 1 << CPU_ROMCS;
+ BUS_CONTROL_OUT = control;
+ }
+ BUS_CONTROL_OUT = BUS_CLOSE;
+}
+void cpu_write_flash(uint16_t address, uint16_t length, const uint8_t *data)
+{
+ direction_write();
+ while(length != 0){
+ cpu_write_flash_waveform(address, *data);
+ data++;
+ address += 1;
+ length--;
+ }
+ address_set(ADDRESS_CLOSE);
+}
+
+void cpu_write_flash_order(const struct flash_order *t)
+{
+ int length = FLASH_PROGRAM_ORDER;
+ direction_write();
+ while(length != 0){
+ cpu_write_flash_waveform(t->address, t->data);
+ t++;
+ length--;
+ }
+ address_set(ADDRESS_CLOSE);
+}
+/*
+NTSC hardware timing
+Master clock fsc: 21.4772272 MHz
+CPU clock fsc/12: 1.789773MHz
+clock per second 12/fsc: 5.58*10**-7 sec, 0.55 us
+*/
+void cpu_write_6502(uint16_t address, uint16_t length, const uint8_t *data)
+{
+ while(length != 0){
+ uint8_t control;
+ address_set(address);
+
+ //phi2 down
+ control = bit_get_negative(CPU_RW) & bit_get_negative(CPU_PHI2);
+ BUS_CONTROL_OUT = control;
+ clock_wait(1);
+
+ //phi2 up
+ if((address & 0x8000) != 0){
+ control &= bit_get_negative(CPU_ROMCS);
+ }
+
+ control |= (1 << CPU_PHI2);
+ BUS_CONTROL_OUT = control;
+ //data set
+ DATABUS_OUT = *data;
+ data++;
+ clock_wait(1);
+
+ //phi2 down
+ control &= bit_get_negative(CPU_PHI2);
+ BUS_CONTROL_OUT = control;
+ if((address & 0x8000) != 0){
+ control &= bit_get_negative(CPU_ROMCS);
+ }
+ BUS_CONTROL_OUT = control;
+
+ //bus close
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ clock_wait(1);
+
+ address += 1;
+ length--;
+ }
+ address_set(ADDRESS_CLOSE);
+}
+
+static inline void ppu_write_waveform(uint16_t address, uint8_t data)
+{
+ address_set(address);//PPU charcter memory /CS open
+ BUS_CONTROL_OUT = bit_get_negative(PPU_WR) & bit_get_negative(CPU_PHI2);
+ DATABUS_OUT = data;
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ address_set(0x3fff); ///CS close, use pallete area. When address bus is 0x2000-0x2fff, some cartriges enable tilemap area.
+}
+void ppu_write(uint16_t address, uint16_t length, const uint8_t *data)
+{
+ while(length != 0){
+ ppu_write_waveform(address, *data);
+ data++;
+ address += 1;
+ length--;
+ }
+}
+
+void ppu_write_order(const struct flash_order *t)
+{
+ int length = FLASH_PROGRAM_ORDER;
+ while(length != 0){
+ ppu_write_waveform(t->address, t->data);
+ t++;
+ length--;
+ }
+}
+
+uint8_t vram_connection_get(void)
+{
+ uint8_t ret;
+ uint16_t address = 0x2000;
+ direction_write();
+ address_set(address);
+ ret = bit_get(USB_MISC_IN, VRAM_A10);
+ address += 1 << 10;
+
+ address_set(address);
+ ret |= bit_get(USB_MISC_IN, VRAM_A10) << 1;
+ address += 1 << 10;
+
+ address_set(address);
+ ret |= bit_get(USB_MISC_IN, VRAM_A10) << 2;
+ address += 1 << 10;
+
+ address_set(address);
+ ret |= bit_get(USB_MISC_IN, VRAM_A10) << 3;
+ address += 1 << 10;
+
+ return ret;
+}
+
+__attribute__ ((section(".bootloader.bus")))
+static void boot_address_set(uint16_t address)
+{
+#if PCB_REVISION == 1
+ ADDRESSBUS_A0_A7_OUT = address & 0xff;
+ uint8_t high = (address & 0x7fff) >> 8; //mask A0-A14
+ if((address & (1 << 13)) == 0){ //if A13 == 0
+ high |= 0x80; //set /A13
+ }
+ DATABUS_OUT = high;
+ BUS_CONTROL_OUT = bit_get_negative(ADDRESS_HIGH_LATCH) & bit_get_negative(CPU_PHI2);
+ BUS_CONTROL_OUT = BUS_CLOSE;
+#endif
+#if PCB_REVISION == 2
+ const uint8_t portb = 0x05;
+ DATABUS_OUT = address & 0xff;
+ asm("cbi %0,%1" : :"M"(portb),"M"(ADDRESS_LOW_LATCH));
+ asm("sbi %0,%1" : :"M"(portb),"M"(ADDRESS_LOW_LATCH));
+ uint8_t high = (address & 0x7fff) >> 8; //mask A0-A14
+ if((address & (1 << 13)) == 0){ //if A13 == 0
+ high |= 0x80; //set /A13
+ }
+ DATABUS_OUT = high;
+ asm("cbi %0,%1" : :"M"(portb),"M"(ADDRESS_HIGH_LATCH));
+ asm("sbi %0,%1" : :"M"(portb),"M"(ADDRESS_HIGH_LATCH));
+#endif
+}
+
+__attribute__ ((section(".bootloader.bus")))
+void mcu_programdata_read(uint16_t address, uint16_t length, uint8_t *data)
+{
+ while(length != 0){
+ direction_write();
+ if(address < 0x2000){ //PPU CHR-RAM
+ boot_address_set(address);
+ BUS_CONTROL_OUT = bit_get_negative(PPU_RD) & bit_get_negative(CPU_PHI2);
+ }else{ //CPU W-RAM
+ address &= 0x1fff;
+ address |= 0x6000;
+ boot_address_set(address);
+/* if((address & 0x8000) != 0){
+ BUS_CONTROL_OUT = bit_get_negative(CPU_ROMCS);
+ }*/
+ BUS_CONTROL_OUT = BUS_CLOSE | (1 << CPU_PHI2);
+ }
+ direction_read();
+ *data = DATABUS_IN;
+ data += 1;
+ BUS_CONTROL_OUT = BUS_CLOSE;
+ address += 1;
+ length--;
+ }
+ boot_address_set(ADDRESS_CLOSE);
+}
--- /dev/null
+#ifndef _BUS_ACCESS_H_
+#define _BUS_ACCESS_H_
+void bus_init(void);
+void phi2_init(void);
+void phi2_update(void);
+void cpu_read(uint16_t address, uint16_t length, uint8_t *data);
+void cpu_read_6502(uint16_t address, uint16_t length, uint8_t *data);
+void ppu_read(uint16_t address, uint16_t length, uint8_t *data);
+void cpu_write_6502(uint16_t address, uint16_t length, const uint8_t *data);
+void cpu_write_flash(uint16_t address, uint16_t length, const uint8_t *data);
+void ppu_write(uint16_t address, uint16_t length, const uint8_t *data);
+
+enum compare_status{
+ OK, NG
+};
+enum compare_status cpu_compare(uint16_t address, uint16_t length, const uint8_t *data);
+enum compare_status ppu_compare(uint16_t address, uint16_t length, const uint8_t *data);
+enum{
+ FLASH_PROGRAM_ORDER = 3
+};
+struct flash_order{
+ uint16_t address;
+ uint8_t data;
+};
+void cpu_write_flash_order(const struct flash_order *t);
+void ppu_write_order(const struct flash_order *t);
+uint8_t vram_connection_get(void);
+
+void mcu_programdata_read(uint16_t address, uint16_t length, uint8_t *data);
+
+#include <util/delay.h>
+static inline void clock_wait(double clock)
+{
+ _delay_us(clock * 0.55);
+}
+#endif
--- /dev/null
+#include <avr/interrupt.h>
+#include <util/delay.h>
+#include "bus_access.h"
+#include "disk_access.h"
+
+uint16_t disk_status_get(uint8_t *data)
+{
+ const uint16_t length = 2;
+ cpu_read(0x4030, length, data);
+ return length;
+}
+static enum sequence{
+ IDLE = 0,
+ INIT_MOTOR_STOP, INIT_BATTERY, INIT_MOTOR_START,
+ WAIT_READY,
+ READ_START, READING, READ_END
+} sequence = IDLE;
+
+void disk_init(enum DISK_REQUEST r)
+{
+ sequence = INIT_MOTOR_STOP;
+}
+
+enum disk_control{ //$4025 control bitfield assignment
+ MOTOR = 0, //0:stop, 1:work
+ TRANSFER_RESET, //1:do reset
+ DIRECTION, //0:write, 1:read
+ VRAM_MIRRORING,
+ BLOCK_END_MARK,
+ UNKOWN, //always 1
+ ACCESS_START,
+ INTERRUPT //0:off, 1:on
+};
+static inline uint8_t bit_set(enum disk_control bit)
+{
+ return 1 << bit;
+};
+enum{
+ BUFFER_ADDRESS = 0x0000,
+ DRQ_COUNT = 0x0400,
+ DISK_CONTROL = 0x4025
+};
+static void data_buffer_init(void)
+{
+ const uint8_t filldata[] = {
+ 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55,
+ 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55, 0xaa, 0x55
+ };
+ uint16_t address = BUFFER_ADDRESS;
+ while(address < BUFFER_ADDRESS + DRQ_COUNT){
+ ppu_write(address, sizeof(filldata), filldata);
+ address += sizeof(filldata);
+ }
+}
+
+static inline void motor_stop(void)
+{
+ uint8_t w;
+ w = bit_set(UNKOWN) | bit_set(DIRECTION) | bit_set(TRANSFER_RESET);
+ cpu_write_6502(DISK_CONTROL, 1, &w);
+}
+
+static inline void motor_start(void)
+{
+ uint8_t w;
+ w = bit_set(UNKOWN) | bit_set(DIRECTION) | bit_set(TRANSFER_RESET)| bit_set(MOTOR);
+ cpu_write_6502(DISK_CONTROL, 1, &w);
+ clock_wait(9);
+ w = bit_set(UNKOWN) | bit_set(DIRECTION) | bit_set(MOTOR);
+ cpu_write_6502(DISK_CONTROL, 1, &w);
+}
+
+volatile static uint16_t drq_count;
+void disk_process(void)
+{
+ const uint16_t status = 0x4032;
+ switch(sequence){
+ default:
+ case IDLE:
+ break;
+ case INIT_MOTOR_STOP:{
+ const uint8_t writebuf[] = {0, 0, 0, 0x83};
+ //GICR &= ~bit_set(INT1);
+ data_buffer_init();
+ //timer interrupt off, disk IO on
+ cpu_write_6502(0x4020, sizeof(writebuf), writebuf);
+ motor_stop();
+ _delay_ms(0x200);
+ sequence = INIT_BATTERY;
+ }break;
+ case INIT_BATTERY:{
+ motor_start();
+ _delay_ms(150);
+ uint8_t w = 0xff;
+ cpu_write_6502(0x4026, 1, &w);
+ sequence = INIT_MOTOR_START;
+ }
+ break;
+ case INIT_MOTOR_START:{
+ motor_stop();
+ motor_start();
+ sequence = WAIT_READY;
+ }break;
+ case WAIT_READY:{
+ uint8_t s;
+ cpu_read_6502(status, 1, &s);
+ if((s & 0b10) == 0b00){
+ sequence = READ_START;
+ }
+ }break;
+ case READ_START:{
+ uint8_t w;
+ _delay_ms(267 + 5);
+
+ w = bit_set(ACCESS_START) | bit_set(UNKOWN) | bit_set(VRAM_MIRRORING) | bit_set(DIRECTION) | bit_set(MOTOR);
+ cpu_write_6502(DISK_CONTROL, 1, &w);
+ clock_wait(21 - 1);
+ //DRQ enable
+ //MCU INT1 init
+// GICR |= bit_set(INT1);
+ drq_count = DRQ_COUNT;
+ //RP2C33 IRQ enable
+ w |= bit_set(INTERRUPT);
+ cpu_write_6502(DISK_CONTROL, 1, &w);
+ sequence = READING;
+ }break;
+ case READING:
+ if(drq_count == 0){
+ sequence = READ_END;
+ }
+ break;
+ case READ_END:{
+/* uint8_t w;
+ w = bit_set(ACCESS_START) | bit_set(UNKOWN) | bit_set(DIRECTION) | bit_set(MOTOR);
+ cpu_write_6502(DISK_CONTROL, 1, &w);*/
+// GICR &= ~bit_set(INT1);
+
+ sequence = IDLE;
+ }break;
+ }
+ uint8_t w[2];
+ w[0] = sequence;
+ w[1] = 0x55;
+ ppu_write(0x0aaa, 2, w);
+ phi2_update();
+}
+
+ISR(INT1_vect)
+{
+ static uint16_t buffer_pointer = BUFFER_ADDRESS;
+ uint8_t d;
+ cpu_read_6502(0x4031, 1, &d);
+ ppu_write(buffer_pointer++, 1, &d);
+ //cpu_write_6502(buffer_pointer++, 1, &d);
+ if(buffer_pointer >= BUFFER_ADDRESS + DRQ_COUNT){
+ buffer_pointer = 0;
+ }
+ drq_count -= 1;
+}
--- /dev/null
+#ifndef _DISK_ACCESS_H_
+#define _DISK_ACCESS_H_
+enum DISK_REQUEST{
+ DISK_READ, DISK_WRITE
+};
+uint16_t disk_status_get(uint8_t *data);
+void disk_init(enum DISK_REQUEST r);
+void disk_process(void);
+#endif
--- /dev/null
+F_CPU = 16000000
+#FORMAT = srec
+FORMAT = ihex
+#FORMAT = binary
+
+# Target file name (without extension).
+OBJDIR = ./$(TARGET)
+
+USBDRIVER = ./usbdrv
+SRC = avr_main.c bus_access.c flashmemory.c disk_access.c mcu_program.c $(addprefix $(USBDRIVER)/,usbdrv.c oddebug.c)
+
+ASRC = $(USBDRIVER)/usbdrvasm.S
+
+
+# Optimization level, can be [0, 1, 2, 3, s].
+OPT = 2
+
+# Debugging format.
+# Native formats for AVR-GCC's -g are dwarf-2 [default] or stabs.
+# AVR Studio 4.10 requires dwarf-2.
+# AVR [Extended] COFF format requires stabs, plus an avr-objcopy run.
+DEBUG = dwarf-2
+
+# List any extra directories to look for include files here.
+# Each directory must be seperated by a space.
+# Use forward slashes for directory separators.
+# For a directory that has spaces, enclose it in quotes.
+EXTRAINCDIRS = $(USBDRIVER)
+
+CSTANDARD = -std=gnu99
+CDEFS = -DF_CPU=$(F_CPU)UL -DDEBUG_LEVEL=0 -DPCB_REVISION=$(PCB_REVISION)
+ADEFS = -DF_CPU=$(F_CPU) -DDEBUG_LEVEL=0 -DPCB_REVISION=$(PCB_REVISION)
+CPPDEFS = -DF_CPU=$(F_CPU)UL
+
+#---------------- Compiler Options C ----------------
+# -g*: generate debugging information
+# -O*: optimization level
+# -f...: tuning, see GCC manual and avr-libc documentation
+# -Wall...: warning level
+# -Wa,...: tell GCC to pass this to the assembler.
+# -adhlns...: create assembler listing
+CFLAGS = -g$(DEBUG)
+CFLAGS += $(CDEFS)
+CFLAGS += -O$(OPT)
+CFLAGS += -funsigned-char
+CFLAGS += -funsigned-bitfields
+CFLAGS += -fpack-struct
+CFLAGS += -fshort-enums
+CFLAGS += -Wall -Werror
+CFLAGS += -Wstrict-prototypes
+#CFLAGS += -mshort-calls
+#CFLAGS += -fno-unit-at-a-time
+#CFLAGS += -Wundef
+#CFLAGS += -Wunreachable-code
+#CFLAGS += -Wsign-compare
+CFLAGS += -Wa,-adhlns=$(<:%.c=$(OBJDIR)/%.lst)
+CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS))
+CFLAGS += $(CSTANDARD)
+
+
+#---------------- Assembler Options ----------------
+# -Wa,...: tell GCC to pass this to the assembler.
+# -adhlns: create listing
+# -gstabs: have the assembler create line number information; note that
+# for use in COFF files, additional information about filenames
+# and function names needs to be present in the assembler source
+# files -- see avr-libc docs [FIXME: not yet described there]
+# -listing-cont-lines: Sets the maximum number of continuation lines of hex
+# dump that will be displayed for a given single line of source input.
+ASFLAGS = $(ADEFS) -Wa,-adhlns=$(<:%.S=$(OBJDIR)/%.lst),-gstabs,--listing-cont-lines=100
+
+#---------------- Library Options ----------------
+# Minimalistic printf version
+PRINTF_LIB_MIN = -Wl,-u,vfprintf -lprintf_min
+
+# Floating point printf version (requires MATH_LIB = -lm below)
+PRINTF_LIB_FLOAT = -Wl,-u,vfprintf -lprintf_flt
+
+# If this is left blank, then it will use the Standard printf version.
+PRINTF_LIB =
+#PRINTF_LIB = $(PRINTF_LIB_MIN)
+#PRINTF_LIB = $(PRINTF_LIB_FLOAT)
+
+
+# Minimalistic scanf version
+SCANF_LIB_MIN = -Wl,-u,vfscanf -lscanf_min
+
+# Floating point + %[ scanf version (requires MATH_LIB = -lm below)
+SCANF_LIB_FLOAT = -Wl,-u,vfscanf -lscanf_flt
+
+# If this is left blank, then it will use the Standard scanf version.
+SCANF_LIB =
+#SCANF_LIB = $(SCANF_LIB_MIN)
+#SCANF_LIB = $(SCANF_LIB_FLOAT)
+MATH_LIB = -lm
+
+# List any extra directories to look for libraries here.
+# Each directory must be seperated by a space.
+# Use forward slashes for directory separators.
+# For a directory that has spaces, enclose it in quotes.
+EXTRALIBDIRS =
+
+#---------------- External Memory Options ----------------
+# 64 KB of external RAM, starting after internal RAM (ATmega128!),
+# only used for heap (malloc()).
+#EXTMEMOPTS = -Wl,--section-start,.data=0x801100,--defsym=__heap_end=0x80ffff
+
+EXTMEMOPTS = -Wl,--section-start,.firmware.version=0x003780
+EXTMEMOPTS += -Wl,--section-start,.bootloader.version=0x003d00
+EXTMEMOPTS += -Wl,--section-start,.bootloader.bus=0x003d60
+EXTMEMOPTS += -Wl,--section-start,.bootloader.programmer=0x003e00
+
+#---------------- Linker Options ----------------
+# -Wl,...: tell GCC to pass this to linker.
+# -Map: create map file
+# --cref: add cross reference to map file
+LDFLAGS = -Wl,-Map=$(TARGET).map,--cref
+LDFLAGS += $(EXTMEMOPTS)
+LDFLAGS += $(patsubst %,-L%,$(EXTRALIBDIRS))
+LDFLAGS += $(PRINTF_LIB) $(SCANF_LIB) $(MATH_LIB)
+#LDFLAGS += -T linker_script.x
+
+#---------------- Programming Options (avrdude) ----------------
+# Programming hardware
+# Type: avrdude -c ?
+# to get a full listing.
+AVRDUDE_PROGRAMMER = stk500v2 #avrispv2 #
+
+# com1 = serial port. Use lpt1 to connect to parallel port.
+AVRDUDE_PORT = com3 # programmer connected to serial device
+
+AVRDUDE_WRITE_FLASH = -U flash:w:$(TARGET).hex
+#AVRDUDE_WRITE_EEPROM = -U eeprom:w:$(TARGET).eep
+AVRDUDE_WRITE_FUSE = -U lfuse:w:0xae:m -U hfuse:w:0xc9:m
+ifeq ($(MCU),atmega164p)
+ AVRDUDE_WRITE_FUSE = -U lfuse:w:0xee:m -U hfuse:w:0xd9:m
+endif
+# Uncomment the following if you do /not/ wish a verification to be
+# performed after programming the device.
+#AVRDUDE_NO_VERIFY = -V
+#AVRDUDE_ERASE_COUNTER = -y
+#AVRDUDE_VERBOSE = -v -v
+
+AVRDUDE_FLAGS = -p $(MCU) -P $(AVRDUDE_PORT) -c $(AVRDUDE_PROGRAMMER)
+AVRDUDE_FLAGS += $(AVRDUDE_NO_VERIFY)
+AVRDUDE_FLAGS += $(AVRDUDE_VERBOSE)
+AVRDUDE_FLAGS += $(AVRDUDE_ERASE_COUNTER)
+
+#---------------- Debugging Options ----------------
+# For simulavr only - target MCU frequency.
+DEBUG_MFREQ = $(F_CPU)
+
+# Set the DEBUG_UI to either gdb or insight.
+# DEBUG_UI = gdb
+DEBUG_UI = insight
+
+# Set the debugging back-end to either avarice, simulavr.
+DEBUG_BACKEND = avarice
+#DEBUG_BACKEND = simulavr
+
+# GDB Init Filename.
+GDBINIT_FILE = __avr_gdbinit
+
+# When using avarice settings for the JTAG
+JTAG_DEV = /dev/com1
+
+# Debugging port used to communicate between GDB / avarice / simulavr.
+DEBUG_PORT = 4242
+
+# Debugging host used to communicate between GDB / avarice / simulavr, normally
+# just set to localhost unless doing some sort of crazy debugging when
+# avarice is running on a different computer.
+DEBUG_HOST = localhost
+
+#============================================================================
+# Define programs and commands.
+SHELL = sh
+CC = avr-gcc
+OBJCOPY = avr-objcopy
+OBJDUMP = avr-objdump
+SIZE = avr-size
+AR = avr-ar rcs
+NM = avr-nm
+AVRDUDE = avrdude
+REMOVE = rm -f
+REMOVEDIR = rm -rf
+COPY = cp
+WINSHELL = cmd
+
+# Define Messages
+# English
+MSG_ERRORS_NONE = Errors: none
+MSG_BEGIN = -------- begin --------
+MSG_END = -------- end --------
+MSG_SIZE_BEFORE = Size before:
+MSG_SIZE_AFTER = Size after:
+MSG_COFF = Converting to AVR COFF:
+MSG_EXTENDED_COFF = Converting to AVR Extended COFF:
+MSG_FLASH = Creating load file for Flash:
+MSG_EEPROM = Creating load file for EEPROM:
+MSG_EXTENDED_LISTING = Creating Extended Listing:
+MSG_SYMBOL_TABLE = Creating Symbol Table:
+MSG_LINKING = Linking:
+MSG_COMPILING = Compiling C:
+MSG_COMPILING_CPP = Compiling C++:
+MSG_ASSEMBLING = Assembling:
+MSG_CLEANING = Cleaning project:
+MSG_CREATING_LIBRARY = Creating library:
+
+# Define all object files.
+OBJ = $(SRC:%.c=$(OBJDIR)/%.o) $(CPPSRC:%.cpp=$(OBJDIR)/%.o) $(ASRC:%.S=$(OBJDIR)/%.o)
+
+# Define all listing files.
+LST = $(SRC:%.c=$(OBJDIR)/%.lst) $(CPPSRC:%.cpp=$(OBJDIR)/%.lst) $(ASRC:%.S=$(OBJDIR)/%.lst)
+
+
+# Compiler flags to generate dependency files.
+GENDEPFLAGS = -MMD -MP -MF .dep/$(@F).d
+
+# Combine all necessary flags and optional flags.
+# Add target processor to flags.
+ALL_CFLAGS = -mmcu=$(MCU) -I. $(CFLAGS) $(GENDEPFLAGS)
+ALL_CPPFLAGS = -mmcu=$(MCU) -I. -x c++ $(CPPFLAGS) $(GENDEPFLAGS)
+ALL_ASFLAGS = -mmcu=$(MCU) -I. -x assembler-with-cpp $(ASFLAGS)
+
+
+# Default target.
+all: begin gccversion sizebefore build sizeafter end
+
+# Change the build target to build a HEX file or a library.
+build: elf hex eep lss sym
+#build: lib sr
+
+
+elf: $(TARGET).elf
+hex: ../$(TARGET).hex
+eep: $(TARGET).eep
+lss: $(TARGET).lss
+sym: $(TARGET).sym
+LIBNAME=lib$(TARGET).a
+lib: $(LIBNAME)
+
+sr: $(TARGET).hex fuse.sr
+ grep -e '^S[0-8]' $(TARGET).hex > $(TARGET).sr
+ cat fuse.sr >> $(TARGET).sr
+ grep -e '^S9' $(TARGET).hex >> $(TARGET).sr
+
+# Eye candy.
+# AVR Studio 3.x does not check make's exit code but relies on
+# the following magic strings to be generated by the compile job.
+begin:
+ @echo $(MSG_BEGIN)
+
+end:
+ @echo $(MSG_END)
+
+
+# Display size of file.
+HEXSIZE = $(SIZE) --target=$(FORMAT) $(TARGET).hex
+ELFSIZE = $(SIZE) --mcu=$(MCU) --format=avr $(TARGET).elf
+
+sizebefore:
+ @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_BEFORE); $(ELFSIZE); \
+ 2>/dev/null; echo; fi
+
+sizeafter:
+ @if test -f $(TARGET).elf; then echo; echo $(MSG_SIZE_AFTER); $(ELFSIZE); \
+ 2>/dev/null; echo; fi
+
+# Display compiler version information.
+gccversion :
+ @$(CC) --version
+
+
+
+# Program the device.
+program: $(TARGET).hex $(TARGET).eep
+ $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FLASH) $(AVRDUDE_WRITE_EEPROM)
+
+fuse:
+ $(AVRDUDE) $(AVRDUDE_FLAGS) $(AVRDUDE_WRITE_FUSE)
+# Generate avr-gdb config/init file which does the following:
+# define the reset signal, load the target file, connect to target, and set
+# a breakpoint at main().
+gdb-config:
+ @$(REMOVE) $(GDBINIT_FILE)
+ @echo define reset >> $(GDBINIT_FILE)
+ @echo SIGNAL SIGHUP >> $(GDBINIT_FILE)
+ @echo end >> $(GDBINIT_FILE)
+ @echo file $(TARGET).elf >> $(GDBINIT_FILE)
+ @echo target remote $(DEBUG_HOST):$(DEBUG_PORT) >> $(GDBINIT_FILE)
+ifeq ($(DEBUG_BACKEND),simulavr)
+ @echo load >> $(GDBINIT_FILE)
+endif
+ @echo break main >> $(GDBINIT_FILE)
+
+debug: gdb-config $(TARGET).elf
+ifeq ($(DEBUG_BACKEND), avarice)
+ @echo Starting AVaRICE - Press enter when "waiting to connect" message displays.
+ @$(WINSHELL) /c start avarice --jtag $(JTAG_DEV) --erase --program --file \
+ $(TARGET).elf $(DEBUG_HOST):$(DEBUG_PORT)
+ @$(WINSHELL) /c pause
+
+else
+ @$(WINSHELL) /c start simulavr --gdbserver --device $(MCU) --clock-freq \
+ $(DEBUG_MFREQ) --port $(DEBUG_PORT)
+endif
+ @$(WINSHELL) /c start avr-$(DEBUG_UI) --command=$(GDBINIT_FILE)
+
+# Convert ELF to COFF for use in debugging / simulating in AVR Studio or VMLAB.
+COFFCONVERT = $(OBJCOPY) --debugging
+COFFCONVERT += --change-section-address .data-0x800000
+COFFCONVERT += --change-section-address .bss-0x800000
+COFFCONVERT += --change-section-address .noinit-0x800000
+COFFCONVERT += --change-section-address .eeprom-0x810000
+
+coff: $(TARGET).elf
+ @echo
+ @echo $(MSG_COFF) $(TARGET).cof
+ $(COFFCONVERT) -O coff-avr $< $(TARGET).cof
+
+extcoff: $(TARGET).elf
+ @echo
+ @echo $(MSG_EXTENDED_COFF) $(TARGET).cof
+ $(COFFCONVERT) -O coff-ext-avr $< $(TARGET).cof
+
+# Create final output files (.hex, .eep) from ELF output file.
+%.hex: %.elf
+ @echo
+ @echo $(MSG_FLASH) $@
+ $(OBJCOPY) -O $(FORMAT) -R .eeprom $< $@
+# --gap-fill=0xff
+
+%.eep: %.elf
+ @echo
+ @echo $(MSG_EEPROM) $@
+ -$(OBJCOPY) -j .eeprom --set-section-flags=.eeprom="alloc,load" \
+ --change-section-lma .eeprom=0 --no-change-warnings -O $(FORMAT) $< $@ || exit 0
+
+# Create extended listing file from ELF output file.
+%.lss: %.elf
+ @echo
+ @echo $(MSG_EXTENDED_LISTING) $@
+ $(OBJDUMP) -h -S -z $< > $@
+
+# Create a symbol table from ELF output file.
+%.sym: %.elf
+ @echo
+ @echo $(MSG_SYMBOL_TABLE) $@
+ $(NM) -n $< > $@
+
+# Create library from object files.
+.SECONDARY : $(TARGET).a
+.PRECIOUS : $(OBJ)
+%.a: $(OBJ)
+ @echo
+ @echo $(MSG_CREATING_LIBRARY) $@
+ $(AR) $@ $(OBJ)
+
+
+# Link: create ELF output file from object files.
+.SECONDARY : $(TARGET).elf
+.PRECIOUS : $(OBJ)
+%.elf: $(OBJ)
+ @echo
+ @echo $(MSG_LINKING) $@
+ $(CC) $(ALL_CFLAGS) $^ --output $@ $(LDFLAGS)
+
+
+# Compile: create object files from C source files.
+$(OBJDIR)/%.o : %.c
+ @echo
+ @echo $(MSG_COMPILING) $<
+ $(CC) -c $(ALL_CFLAGS) $< -o $@
+
+
+# Compile: create object files from C++ source files.
+$(OBJDIR)/%.o : %.cpp
+ @echo
+ @echo $(MSG_COMPILING_CPP) $<
+ $(CC) -c $(ALL_CPPFLAGS) $< -o $@
+
+
+# Compile: create assembler files from C source files.
+%.s : %.c
+ $(CC) -S $(ALL_CFLAGS) $< -o $@
+
+
+# Compile: create assembler files from C++ source files.
+%.s : %.cpp
+ $(CC) -S $(ALL_CPPFLAGS) $< -o $@
+
+
+# Assemble: create object files from assembler source files.
+$(OBJDIR)/%.o : %.S
+ @echo
+ @echo $(MSG_ASSEMBLING) $<
+ $(CC) -c $(ALL_ASFLAGS) $< -o $@
+
+
+# Create preprocessed source for use in sending a bug report.
+%.i : %.c
+ $(CC) -E -mmcu=$(MCU) -I. $(CFLAGS) $< -o $@
+
+
+# Target: clean project.
+clean: begin clean_list end
+
+clean_list :
+ @echo
+ @echo $(MSG_CLEANING)
+ $(REMOVE) $(TARGET).hex
+ $(REMOVE) $(TARGET).eep
+ $(REMOVE) $(TARGET).cof
+ $(REMOVE) $(TARGET).elf
+ $(REMOVE) $(TARGET).map
+ $(REMOVE) $(TARGET).sym
+ $(REMOVE) $(TARGET).lss
+ $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.o)
+ $(REMOVE) $(SRC:%.c=$(OBJDIR)/%.lst)
+ $(REMOVE) $(SRC:.c=.s)
+ $(REMOVE) $(SRC:.c=.d)
+ $(REMOVE) $(SRC:.c=.i)
+ $(REMOVEDIR) .dep
+
+# Create object files directory
+$(shell mkdir -p $(OBJDIR)/usbdrv 2>/dev/null)
+
+# Include the dependency files.
+-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# Listing of phony targets.
+.PHONY : all begin finish end sizebefore sizeafter gccversion \
+build elf hex eep lss sym coff extcoff \
+clean clean_list program debug gdb-config
--- /dev/null
+#include <stdint.h>
+//#include <avr/interrupt.h>
+#include "kazzo_task.h"
+#include "bus_access.h"
+
+//---- global variable ----
+struct flash_seqence{
+ void (*const writer)(uint16_t address, uint16_t length, const uint8_t *data);
+ void (*const programmer)(const struct flash_order *t);
+ void (*const reader)(uint16_t address, uint16_t length, uint8_t *data);
+ enum compare_status (*const compare)(uint16_t address, uint16_t length, const uint8_t *data);
+ enum status{
+ IDLE = KAZZO_TASK_FLASH_IDLE,
+ ERASE, ERASE_WAIT,
+ PROGRAM, TOGGLE_FIRST, TOGGLE_CHECK
+ } status, request;
+ uint16_t command_000x, command_2aaa, command_5555;
+ uint8_t retry_enable;
+ uint16_t address, length, program_unit;
+ const uint8_t *data;
+ uint8_t toggle, retry_count;
+ struct flash_order program_command[FLASH_PROGRAM_ORDER];
+};
+static struct flash_seqence seqence_cpu = {
+ .status = IDLE, .reader = cpu_read,
+ .writer = cpu_write_flash, .programmer = cpu_write_flash_order,
+ .compare = cpu_compare
+};
+static struct flash_seqence seqence_ppu = {
+ .status = IDLE, .reader = ppu_read,
+ .writer = ppu_write, .programmer = ppu_write_order,
+ .compare = ppu_compare
+};
+
+//---- task registration ----
+uint8_t flash_cpu_status(void)
+{
+ return seqence_cpu.status;
+}
+uint8_t flash_ppu_status(void)
+{
+ return seqence_ppu.status;
+}
+void flash_both_idle(void)
+{
+ seqence_cpu.status = IDLE;
+ seqence_ppu.status = IDLE;
+}
+static inline uint16_t unpack_short_le(const uint8_t *t)
+{
+ uint16_t r = t[0];
+ r |= t[1] << 8;
+ return r;
+}
+static void config_set(const uint8_t *data, uint16_t length, struct flash_seqence *t)
+{
+ t->command_000x = unpack_short_le(data);
+ data += sizeof(uint16_t);
+ t->command_2aaa = unpack_short_le(data);
+ data += sizeof(uint16_t);
+ t->command_5555 = unpack_short_le(data);
+ data += sizeof(uint16_t);
+ t->program_unit = unpack_short_le(data);
+ data += sizeof(uint16_t);
+ if(length < 9){ //support client 0.6.0
+ t->retry_enable = 0;
+ }else{
+ t->retry_enable = *data;
+ }
+
+ t->program_command[0].address = t->command_5555;
+ t->program_command[0].data = 0xaa;
+ t->program_command[1].address = t->command_2aaa;
+ t->program_command[1].data = 0x55;
+ t->program_command[2].address = t->command_5555;
+ t->program_command[2].data = 0xa0;
+};
+void flash_cpu_config(const uint8_t *data, uint16_t length)
+{
+ config_set(data, length, &seqence_cpu);
+}
+void flash_ppu_config(const uint8_t *data, uint16_t length)
+{
+ config_set(data, length, &seqence_ppu);
+}
+
+static void program_assign(enum status status, uint16_t address, uint16_t length, const uint8_t *data, struct flash_seqence *t)
+{
+ if(0 && (t->program_unit != 1) && (t->status == PROGRAM)){ //W29C040 ¤ÎºÆ½ñ¤¹þ¤ß²ó¿ô¤ò¸º¤é¤·¤Æ¤ß¤ë
+ t->status = TOGGLE_FIRST;
+ }else{
+ t->status = status;
+ }
+ t->request = status;
+ t->address = address;
+ t->length = length;
+ t->data = data;
+ t->retry_count = 0;
+}
+void flash_cpu_program(uint16_t address, uint16_t length, const uint8_t *data)
+{
+ program_assign(PROGRAM, address, length, data, &seqence_cpu);
+}
+void flash_ppu_program(uint16_t address, uint16_t length, const uint8_t *data)
+{
+ program_assign(PROGRAM, address, length, data, &seqence_ppu);
+}
+#define NULL (0)
+void flash_cpu_erase(uint16_t address)
+{
+ //length ¤Ë unit ¤òÅϤ·¤Æ toggle check ¸å IDLE ¤Ë¤Ê¤ë¤è¤¦¤Ë¤¹¤ë
+ program_assign(ERASE, address, seqence_cpu.program_unit, NULL, &seqence_cpu);
+}
+void flash_ppu_erase(uint16_t address)
+{
+ program_assign(ERASE, address, seqence_ppu.program_unit, NULL, &seqence_ppu);
+}
+
+//---- command write ----
+struct flash_command{
+ enum {C2AAA, C5555, END} address;
+ uint8_t data;
+};
+static void command_execute(const struct flash_command *c, const struct flash_seqence *const t)
+{
+ while(c->address != END){
+ uint16_t addr = 0;
+ switch(c->address){
+ case C2AAA:
+ addr = t->command_2aaa;
+ break;
+ case C5555:
+ addr = t->command_5555;
+ break;
+ case END:
+ return;
+ }
+ t->writer(addr, 1, &c->data);
+ c++;
+ }
+}
+static void program(const struct flash_seqence *t)
+{
+/* static const struct flash_command c[] = {
+ {C5555, 0xaa}, {C2AAA, 0x55}, {C5555, 0xa0}, {END, 0}
+ };
+ command_execute(c, t);*/
+ t->programmer(t->program_command);
+ t->writer(t->address, t->program_unit, t->data);
+}
+
+static void erase(const struct flash_seqence *t)
+{
+ static const struct flash_command c[] = {
+ {C5555, 0xaa}, {C2AAA, 0x55}, {C5555, 0x80},
+ {C5555, 0xaa}, {C2AAA, 0x55}, {C5555, 0x10},
+ {END, 0}
+ };
+ command_execute(c, t);
+}
+
+static void device_get(const struct flash_seqence *t, uint8_t d[2])
+{
+ static const struct flash_command entry[] = {
+ {C5555, 0xaa}, {C2AAA, 0x55}, {C5555, 0x90}, {END, 0}
+ };
+ static const struct flash_command exit[] = {
+ {C5555, 0xaa}, {C2AAA, 0x55}, {C5555, 0xf0}, {END, 0}
+ };
+ command_execute(entry, t);
+ t->reader(t->command_000x, 1, d);
+ command_execute(entry, t);
+ t->reader(t->command_000x + 1, 1, d + 1);
+ command_execute(exit, t);
+}
+void flash_cpu_device_get(uint8_t d[2])
+{
+ device_get(&seqence_cpu, d);
+}
+void flash_ppu_device_get(uint8_t d[2])
+{
+ device_get(&seqence_ppu, d);
+}
+//---- status read ----
+static void toggle_first(struct flash_seqence *t)
+{
+ t->reader(t->address, 1, &t->toggle);
+ t->toggle &= 0x40;
+}
+static void toggle_check(struct flash_seqence *t)
+{
+ uint8_t d;
+ t->reader(t->address, 1, &d);
+ if(t->toggle == (d & 0x40)){
+ if((t->retry_enable != 0) && (t->request == PROGRAM) && (t->retry_count < 20)){
+ if(t->compare(t->address, t->program_unit, t->data) == NG){
+ t->retry_count += 1;
+ t->status = PROGRAM;
+ return;
+ }
+ }
+ t->retry_count = 0;
+ t->address += t->program_unit;
+ t->data += t->program_unit;
+ t->length -= t->program_unit;
+ if((t->length == 0) || (t->request == ERASE)){
+ t->status = IDLE;
+ }else{
+ t->status = PROGRAM;
+ }
+ }
+ t->toggle = d & 0x40;
+ if(0 && (d & 0x20)){ //polling DQ5, AM29F040B only
+ uint8_t d0, d1;
+ t->reader(t->address, 1, &d0);
+ t->reader(t->address, 1, &d1);
+ if((d0 & 0x40) == (d1 & 0x40)){
+ t->address += t->program_unit;
+ t->data += t->program_unit;
+ t->length -= t->program_unit;
+ if((t->length == 0) || (t->request == ERASE)){
+ t->status = IDLE;
+ }else{
+ t->status = PROGRAM;
+ }
+ }
+ }
+}
+
+static void erase_wait(struct flash_seqence *t)
+{
+ uint8_t d;
+ t->reader(t->address, 1, &d);
+ if(d == 0xff){
+ t->status = IDLE;
+ }
+}
+//---- task execute ----
+static void process(struct flash_seqence *s)
+{
+ switch(s->status){
+ case IDLE:
+ break;
+ case ERASE:
+ erase(s);
+ s->status = ERASE_WAIT;
+ break;
+ case ERASE_WAIT:
+ erase_wait(s);
+ break;
+ case PROGRAM:
+ if((s->program_unit != 1) || (*(s->data) != 0xff)){
+ program(s);
+ }
+ s->status = TOGGLE_FIRST;
+ break;
+ case TOGGLE_FIRST:
+ toggle_first(s);
+ s->status = TOGGLE_CHECK;
+ break;
+ case TOGGLE_CHECK:
+ toggle_check(s); //status is updated by function
+ break;
+ }
+
+}
+void flash_process(void)
+{
+ //for CPU and PPU dual programming
+ process(&seqence_cpu);
+ process(&seqence_ppu);
+}
--- /dev/null
+#ifndef _FLASHMEMORY_H_
+#define _FLASHMEMORY_H_
+void flash_both_idle(void);
+//cpu
+uint8_t flash_cpu_status(void);
+void flash_cpu_config(const uint8_t *data, uint16_t length);
+void flash_cpu_program(uint16_t address, uint16_t length, uint8_t *data);
+void flash_cpu_erase(uint16_t address);
+void flash_cpu_device_get(uint8_t d[2]);
+uint8_t flash_ppu_status(void);
+//ppu
+void flash_ppu_config(const uint8_t *data, uint16_t length);
+void flash_ppu_program(uint16_t address, uint16_t length, uint8_t *data);
+void flash_ppu_erase(uint16_t address);
+void flash_ppu_device_get(uint8_t d[2]);
+//task
+void flash_process(void);
+#endif
--- /dev/null
+#ifndef _KAZZO_REQUEST_H_
+#define _KAZZO_REQUEST_H_
+#define USB_CFG_VENDOR_ID 0xc0, 0x16
+#define USB_CFG_DEVICE_ID 0xdc, 0x05
+#define USB_CFG_DEVICE_VERSION 0x00, 0x01
+#define USB_CFG_VENDOR_NAME 'o', 'b', 'd', 'e', 'v', '.', 'a', 't'
+#define USB_CFG_VENDOR_NAME_LEN 8
+#define USB_CFG_DEVICE_NAME 'k', 'a', 'z', 'z', 'o'
+#define USB_CFG_DEVICE_NAME_LEN 5
+
+enum request{
+ REQUEST_ECHO = 0,
+ REQUEST_PHI2_INIT,
+ REQUEST_CPU_READ_6502, REQUEST_CPU_READ,
+ REQUEST_CPU_WRITE_6502, REQUEST_CPU_WRITE_FLASH,
+ REQUEST_PPU_READ, REQUEST_PPU_WRITE,
+ REQUEST_FLASH_STATUS, REQUEST_FLASH_CONFIG_SET,
+ REQUEST_FLASH_PROGRAM, REQUEST_FLASH_ERASE,
+ REQUEST_FLASH_DEVICE, //REQUEST_FLASH_BUFFER_GET,
+ REQUEST_VRAM_CONNECTION,
+
+ //future expanstion
+ REQUEST_DISK_STATUS_GET, REQUEST_DISK_READ, REQUEST_DISK_WRITE,
+
+ //bootloader control
+ REQUEST_FIRMWARE_VERSION = 0x80, REQUEST_FIRMWARE_PROGRAM,
+ REQUEST_FIRMWARE_DOWNLOAD
+};
+enum index{
+ INDEX_IMPLIED = 0, INDEX_CPU, INDEX_PPU, INDEX_BOTH
+};
+enum {
+ VERSION_STRING_SIZE = 0x20,
+// READ_PACKET_SIZE = 0x0100, //use macro to compare SPM_PAGESIZE
+ FLASH_PACKET_SIZE = 0x0100
+};
+#define READ_PACKET_SIZE (0x100)
+#endif
--- /dev/null
+#ifndef _KAZZO_TASK_H_
+#define _KAZZO_TASK_H_
+enum{
+ KAZZO_TASK_FLASH_IDLE = 0
+};
+#endif
--- /dev/null
+#include <stdint.h>
+#include <avr/boot.h>
+#include <avr/interrupt.h>
+#include <avr/pgmspace.h>
+#include <avr/wdt.h>
+#include "kazzo_request.h"
+#include "bus_access.h"
+#include "mcu_program.h"
+
+#if SPM_PAGESIZE > READ_PACKET_SIZE
+ #error READ_PACKET_SIZE is few capacity
+#endif
+/*
+firmware bootloader sequence
+- User insert a cartrige which has charcter RAM and CPU work RAM.
+- Host send new firmware image with REQUEST_PPU_WRITE and REQUEST_CPU_WRITE_6502.
+- Host receive and compare translated memory image.
+- Firmware reprogram by REQUEST_FIRMWARE_PROGRAM.
+
+MEGA164P-20[AP]U
+ISP programming -> REQUEST_FIRMWARE_PROGRAM -> flash memory is programmed 2 pages only...
+ISP programming -> power off->on -> REQUEST_FIRMWARE_PROGRAM -> flash memory is programmed all pages.
+*/
+//inline function is not needed section defination.
+//memcmp and memset are linked exteneded program area where cannot use when bootloader running.
+enum{
+ fillsize = 0x10
+};
+static inline int my_memcmp(const uint8_t *firm, const uint8_t fill)
+{
+#define CMP1(offset) if(firm[offset] != fill){return 1;}
+#define CMP4(i) CMP1(i+0) CMP1(i+1) CMP1(i+2) CMP1(i+3)
+ CMP4(0) CMP4(4) CMP4(8) CMP4(12)
+ return 0;
+#undef CMP4
+#undef CMP1
+}
+static inline int fillcmp(const uint8_t *firm, const uint8_t fill)
+{
+ int i;
+ for(i = 0; i < SPM_PAGESIZE; i += fillsize){
+ if(my_memcmp(firm, fill) != 0){
+ return 1;
+ }
+ firm += fillsize;
+ }
+ return 0;
+}
+__attribute__((noreturn))
+__attribute__ ((section(".bootloader.programmer")))
+static void mcu_data_program(uint8_t *buf, uint16_t address, uint16_t length)
+{
+ uint16_t offset = 0;
+ int page;
+ cli();
+ wdt_disable();
+
+ eeprom_busy_wait();
+ for(page = 0; page < length / SPM_PAGESIZE; page++){
+ mcu_programdata_read(offset, SPM_PAGESIZE, buf);
+ if((fillcmp(buf, 0) != 0) || (fillcmp(buf, 0xff) != 0)){
+ boot_page_erase(address);
+ boot_spm_busy_wait();
+ int i;
+ for(i = 0; i < SPM_PAGESIZE; i += 2){
+ //Set up little-endian word
+ uint16_t w = buf[i+0];
+ w |= buf[i+1] << 8;
+ boot_page_fill(i, w);
+ }
+ boot_page_write(address);
+ boot_spm_busy_wait();
+ }
+ offset += SPM_PAGESIZE;
+ address += SPM_PAGESIZE;
+ }
+ if(0){ //force re-turn power on. keep watchdog disable
+ boot_rww_enable();
+ sei();
+ wdt_enable(WDTO_500MS);
+ }
+endless: //wait watchdog interruptting reset
+ goto endless;
+}
+
+__attribute__ ((section(".bootloader.version")))
+const struct bootloader_assign BOOTLOADER_ASSIGN = {
+ .version = "kazzo loader 0.1.1",
+ .programmer = mcu_data_program
+};
+
--- /dev/null
+#ifndef _MCU_PROGRAM_H_
+#define _MCU_PROGRAM_H_
+struct bootloader_assign{
+ const char version[0x20];
+ __attribute__((noreturn))
+ void (*const programmer)(uint8_t *buf, uint16_t address, uint16_t length);
+};
+//__attribute__ ((section(".bootloader.version")))
+const struct bootloader_assign BOOTLOADER_ASSIGN;
+#endif
--- /dev/null
+#ifndef _TYPE_H_
+#define _TYPE_H_
+static inline uint8_t bit_to_data(uint8_t data, int bit)
+{
+ data &= 1;
+ return data << bit;
+}
+static inline uint8_t bit_get(uint8_t data, int bit)
+{
+ data >>= bit;
+ return data & 1;
+}
+#endif
--- /dev/null
+#ifndef __usbconfig_h_included__
+#define __usbconfig_h_included__
+
+#if PCB_REVISION == 1
+ #define USB_CFG_IOPORTNAME D
+ #define USB_CFG_DMINUS_BIT 4
+ #define USB_CFG_DPLUS_BIT 2
+ #define USB_CFG_CLOCK_KHZ (F_CPU/1000)
+ #define USB_CFG_CHECK_CRC 0
+#endif
+#if PCB_REVISION == 2
+ #define USB_CFG_IOPORTNAME B
+ #define USB_CFG_DMINUS_BIT 1
+ #define USB_CFG_DPLUS_BIT 0
+ #define USB_CFG_CLOCK_KHZ (F_CPU/1000)
+ #define USB_CFG_CHECK_CRC 0
+#endif
+
+#define USB_CFG_HAVE_INTRIN_ENDPOINT 0
+#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0
+#define USB_CFG_EP3_NUMBER 3
+#define USB_CFG_IMPLEMENT_HALT 0
+#define USB_CFG_SUPPRESS_INTR_CODE 0
+#define USB_CFG_INTR_POLL_INTERVAL 10
+#define USB_CFG_IS_SELF_POWERED 0
+#define USB_CFG_MAX_BUS_POWER 40
+#define USB_CFG_IMPLEMENT_FN_WRITE 1
+#define USB_CFG_IMPLEMENT_FN_READ 0
+#define USB_CFG_IMPLEMENT_FN_WRITEOUT 0
+/* Define this to 1 if you want to use interrupt-out (or bulk out) endpoints.
+ * You must implement the function usbFunctionWriteOut() which receives all
+ * interrupt/bulk data sent to any endpoint other than 0. The endpoint number
+ * can be found in 'usbRxToken'.
+ */
+#define USB_CFG_HAVE_FLOWCONTROL 0
+#define USB_CFG_LONG_TRANSFERS 1
+#define USB_COUNT_SOF 0
+#define USB_CFG_CHECK_DATA_TOGGLING 0
+#define USB_CFG_HAVE_MEASURE_FRAME_LENGTH 0
+#define USB_USE_FAST_CRC 0
+
+/* -------------------------- Device Description --------------------------- */
+/* Same as above for the device name. If you don't want a device name, undefine
+ * the macros. See the file USB-IDs-for-free.txt before you assign a name if
+ * you use a shared VID/PID.
+ */
+/*#define USB_CFG_SERIAL_NUMBER 'N', 'o', 'n', 'e' */
+/*#define USB_CFG_SERIAL_NUMBER_LEN 0 */
+/* Same as above for the serial number. If you don't want a serial number,
+ * undefine the macros.
+ * It may be useful to provide the serial number through other means than at
+ * compile time. See the section about descriptor properties below for how
+ * to fine tune control over USB descriptors such as the string descriptor
+ * for the serial number.
+ */
+#define USB_CFG_DEVICE_CLASS 0xff /* set to 0 if deferred to interface */
+#define USB_CFG_DEVICE_SUBCLASS 0
+#define USB_CFG_INTERFACE_CLASS 0
+#define USB_CFG_INTERFACE_SUBCLASS 0
+#define USB_CFG_INTERFACE_PROTOCOL 0
+
+/* ------------------- Fine Control over USB Descriptors ------------------- */
+/* If you don't want to use the driver's default USB descriptors, you can
+ * provide our own. These can be provided as (1) fixed length static data in
+ * flash memory, (2) fixed length static data in RAM or (3) dynamically at
+ * runtime in the function usbFunctionDescriptor(). See usbdrv.h for more
+ * information about this function.
+ * Descriptor handling is configured through the descriptor's properties. If
+ * no properties are defined or if they are 0, the default descriptor is used.
+ * Possible properties are:
+ * + USB_PROP_IS_DYNAMIC: The data for the descriptor should be fetched
+ * at runtime via usbFunctionDescriptor(). If the usbMsgPtr mechanism is
+ * used, the data is in FLASH by default. Add property USB_PROP_IS_RAM if
+ * you want RAM pointers.
+ * + USB_PROP_IS_RAM: The data returned by usbFunctionDescriptor() or found
+ * in static memory is in RAM, not in flash memory.
+ * + USB_PROP_LENGTH(len): If the data is in static memory (RAM or flash),
+ * the driver must know the descriptor's length. The descriptor itself is
+ * found at the address of a well known identifier (see below).
+ * List of static descriptor names (must be declared PROGMEM if in flash):
+ * char usbDescriptorDevice[];
+ * char usbDescriptorConfiguration[];
+ * char usbDescriptorHidReport[];
+ * char usbDescriptorString0[];
+ * int usbDescriptorStringVendor[];
+ * int usbDescriptorStringDevice[];
+ * int usbDescriptorStringSerialNumber[];
+ * Other descriptors can't be provided statically, they must be provided
+ * dynamically at runtime.
+ *
+ * Descriptor properties are or-ed or added together, e.g.:
+ * #define USB_CFG_DESCR_PROPS_DEVICE (USB_PROP_IS_RAM | USB_PROP_LENGTH(18))
+ *
+ * The following descriptors are defined:
+ * USB_CFG_DESCR_PROPS_DEVICE
+ * USB_CFG_DESCR_PROPS_CONFIGURATION
+ * USB_CFG_DESCR_PROPS_STRINGS
+ * USB_CFG_DESCR_PROPS_STRING_0
+ * USB_CFG_DESCR_PROPS_STRING_VENDOR
+ * USB_CFG_DESCR_PROPS_STRING_PRODUCT
+ * USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER
+ * USB_CFG_DESCR_PROPS_HID
+ * USB_CFG_DESCR_PROPS_HID_REPORT
+ * USB_CFG_DESCR_PROPS_UNKNOWN (for all descriptors not handled by the driver)
+ *
+ * Note about string descriptors: String descriptors are not just strings, they
+ * are Unicode strings prefixed with a 2 byte header. Example:
+ * int serialNumberDescriptor[] = {
+ * USB_STRING_DESCRIPTOR_HEADER(6),
+ * 'S', 'e', 'r', 'i', 'a', 'l'
+ * };
+ */
+
+#define USB_CFG_DESCR_PROPS_DEVICE 0
+#define USB_CFG_DESCR_PROPS_CONFIGURATION 0
+#define USB_CFG_DESCR_PROPS_STRINGS 0
+#define USB_CFG_DESCR_PROPS_STRING_0 0
+#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0
+#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0
+#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0
+#define USB_CFG_DESCR_PROPS_HID 0
+#define USB_CFG_DESCR_PROPS_HID_REPORT 0
+#define USB_CFG_DESCR_PROPS_UNKNOWN 0
+
+/* #define USB_INTR_CFG MCUCR */
+/* #define USB_INTR_CFG_CLR 0 */
+/* #define USB_INTR_ENABLE GIMSK */
+/* #define USB_INTR_ENABLE_BIT INT0 */
+/* #define USB_INTR_PENDING GIFR */
+#if PCB_REVISION == 1
+ #define USB_INTR_PENDING_BIT INTF0
+ #define USB_INTR_CFG_SET ((1 << ISC01) | (1 << ISC00) | (1 << ISC11)| (0 << ISC10))
+#endif
+#if PCB_REVISION == 2
+ #define USB_INTR_CFG PCICR
+ #define USB_INTR_CFG_SET (1 << PCIE0)
+ #define USB_INTR_CFG_CLR 0
+ #define USB_INTR_ENABLE PCMSK0
+ #define USB_INTR_ENABLE_BIT PCINT0
+ #define USB_INTR_PENDING PCIFR
+ #define USB_INTR_PENDING_BIT PCIF0
+//#define USB_INTR_VECTOR SIG_PIN_CHANGE0
+ #define USB_INTR_VECTOR PCINT0_vect
+#endif
+
+#endif /* __usbconfig_h_included__ */
--- /dev/null
+/* Name: asmcommon.inc
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-11-05
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id$
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file contains assembler code which is shared among the USB driver
+implementations for different CPU cocks. Since the code must be inserted
+in the middle of the module, it's split out into this file and #included.
+
+Jump destinations called from outside:
+ sofError: Called when no start sequence was found.
+ se0: Called when a package has been successfully received.
+ overflow: Called when receive buffer overflows.
+ doReturn: Called after sending data.
+
+Outside jump destinations used by this module:
+ waitForJ: Called to receive an already arriving packet.
+ sendAckAndReti:
+ sendNakAndReti:
+ sendCntAndReti:
+ usbSendAndReti:
+
+The following macros must be defined before this file is included:
+ .macro POP_STANDARD
+ .endm
+ .macro POP_RETI
+ .endm
+*/
+
+#define token x1
+
+overflow:
+ ldi x2, 1<<USB_INTR_PENDING_BIT
+ USB_STORE_PENDING(x2) ; clear any pending interrupts
+ignorePacket:
+ clr token
+ rjmp storeTokenAndReturn
+
+;----------------------------------------------------------------------------
+; Processing of received packet (numbers in brackets are cycles after center of SE0)
+;----------------------------------------------------------------------------
+;This is the only non-error exit point for the software receiver loop
+;we don't check any CRCs here because there is no time left.
+se0:
+ subi cnt, USB_BUFSIZE ;[5]
+ neg cnt ;[6]
+ sub YL, cnt ;[7]
+ sbci YH, 0 ;[8]
+ ldi x2, 1<<USB_INTR_PENDING_BIT ;[9]
+ USB_STORE_PENDING(x2) ;[10] clear pending intr and check flag later. SE0 should be over.
+ ld token, y ;[11]
+ cpi token, USBPID_DATA0 ;[13]
+ breq handleData ;[14]
+ cpi token, USBPID_DATA1 ;[15]
+ breq handleData ;[16]
+ lds shift, usbDeviceAddr;[17]
+ ldd x2, y+1 ;[19] ADDR and 1 bit endpoint number
+ lsl x2 ;[21] shift out 1 bit endpoint number
+ cpse x2, shift ;[22]
+ rjmp ignorePacket ;[23]
+/* only compute endpoint number in x3 if required later */
+#if USB_CFG_HAVE_INTRIN_ENDPOINT || USB_CFG_IMPLEMENT_FN_WRITEOUT
+ ldd x3, y+2 ;[24] endpoint number + crc
+ rol x3 ;[26] shift in LSB of endpoint
+#endif
+ cpi token, USBPID_IN ;[27]
+ breq handleIn ;[28]
+ cpi token, USBPID_SETUP ;[29]
+ breq handleSetupOrOut ;[30]
+ cpi token, USBPID_OUT ;[31]
+ brne ignorePacket ;[32] must be ack, nak or whatever
+; rjmp handleSetupOrOut ; fallthrough
+
+;Setup and Out are followed by a data packet two bit times (16 cycles) after
+;the end of SE0. The sync code allows up to 40 cycles delay from the start of
+;the sync pattern until the first bit is sampled. That's a total of 56 cycles.
+handleSetupOrOut: ;[32]
+#if USB_CFG_IMPLEMENT_FN_WRITEOUT /* if we have data for endpoint != 0, set usbCurrentTok to address */
+ andi x3, 0xf ;[32]
+ breq storeTokenAndReturn ;[33]
+ mov token, x3 ;[34] indicate that this is endpoint x OUT
+#endif
+storeTokenAndReturn:
+ sts usbCurrentTok, token;[35]
+doReturn:
+ POP_STANDARD ;[37] 12...16 cycles
+ USB_LOAD_PENDING(YL) ;[49]
+ sbrc YL, USB_INTR_PENDING_BIT;[50] check whether data is already arriving
+ rjmp waitForJ ;[51] save the pops and pushes -- a new interrupt is already pending
+sofError:
+ POP_RETI ;macro call
+ reti
+
+handleData:
+#if USB_CFG_CHECK_CRC
+ CRC_CLEANUP_AND_CHECK ; jumps to ignorePacket if CRC error
+#endif
+ lds shift, usbCurrentTok;[18]
+ tst shift ;[20]
+ breq doReturn ;[21]
+ lds x2, usbRxLen ;[22]
+ tst x2 ;[24]
+ brne sendNakAndReti ;[25]
+; 2006-03-11: The following two lines fix a problem where the device was not
+; recognized if usbPoll() was called less frequently than once every 4 ms.
+ cpi cnt, 4 ;[26] zero sized data packets are status phase only -- ignore and ack
+ brmi sendAckAndReti ;[27] keep rx buffer clean -- we must not NAK next SETUP
+#if USB_CFG_CHECK_DATA_TOGGLING
+ sts usbCurrentDataToken, token ; store for checking by C code
+#endif
+ sts usbRxLen, cnt ;[28] store received data, swap buffers
+ sts usbRxToken, shift ;[30]
+ lds x2, usbInputBufOffset;[32] swap buffers
+ ldi cnt, USB_BUFSIZE ;[34]
+ sub cnt, x2 ;[35]
+ sts usbInputBufOffset, cnt;[36] buffers now swapped
+ rjmp sendAckAndReti ;[38] 40 + 17 = 57 until SOP
+
+handleIn:
+;We don't send any data as long as the C code has not processed the current
+;input data and potentially updated the output data. That's more efficient
+;in terms of code size than clearing the tx buffers when a packet is received.
+ lds x1, usbRxLen ;[30]
+ cpi x1, 1 ;[32] negative values are flow control, 0 means "buffer free"
+ brge sendNakAndReti ;[33] unprocessed input packet?
+ ldi x1, USBPID_NAK ;[34] prepare value for usbTxLen
+#if USB_CFG_HAVE_INTRIN_ENDPOINT
+ andi x3, 0xf ;[35] x3 contains endpoint
+#if USB_CFG_SUPPRESS_INTR_CODE
+ brne sendNakAndReti ;[36]
+#else
+ brne handleIn1 ;[36]
+#endif
+#endif
+ lds cnt, usbTxLen ;[37]
+ sbrc cnt, 4 ;[39] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;[40] 42 + 16 = 58 until SOP
+ sts usbTxLen, x1 ;[41] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf) ;[43]
+ ldi YH, hi8(usbTxBuf) ;[44]
+ rjmp usbSendAndReti ;[45] 57 + 12 = 59 until SOP
+
+; Comment about when to set usbTxLen to USBPID_NAK:
+; We should set it back when we receive the ACK from the host. This would
+; be simple to implement: One static variable which stores whether the last
+; tx was for endpoint 0 or 1 and a compare in the receiver to distinguish the
+; ACK. However, we set it back immediately when we send the package,
+; assuming that no error occurs and the host sends an ACK. We save one byte
+; RAM this way and avoid potential problems with endless retries. The rest of
+; the driver assumes error-free transfers anyway.
+
+#if !USB_CFG_SUPPRESS_INTR_CODE && USB_CFG_HAVE_INTRIN_ENDPOINT /* placed here due to relative jump range */
+handleIn1: ;[38]
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+; 2006-06-10 as suggested by O.Tamura: support second INTR IN / BULK IN endpoint
+ cpi x3, USB_CFG_EP3_NUMBER;[38]
+ breq handleIn3 ;[39]
+#endif
+ lds cnt, usbTxLen1 ;[40]
+ sbrc cnt, 4 ;[42] all handshake tokens have bit 4 set
+ rjmp sendCntAndReti ;[43] 47 + 16 = 63 until SOP
+ sts usbTxLen1, x1 ;[44] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf1) ;[46]
+ ldi YH, hi8(usbTxBuf1) ;[47]
+ rjmp usbSendAndReti ;[48] 50 + 12 = 62 until SOP
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+handleIn3:
+ lds cnt, usbTxLen3 ;[41]
+ sbrc cnt, 4 ;[43]
+ rjmp sendCntAndReti ;[44] 49 + 16 = 65 until SOP
+ sts usbTxLen3, x1 ;[45] x1 == USBPID_NAK from above
+ ldi YL, lo8(usbTxBuf3) ;[47]
+ ldi YH, hi8(usbTxBuf3) ;[48]
+ rjmp usbSendAndReti ;[49] 51 + 12 = 63 until SOP
+#endif
+#endif
--- /dev/null
+/* Name: oddebug.c
+ * Project: AVR library
+ * Author: Christian Starkjohann
+ * Creation Date: 2005-01-16
+ * Tabsize: 4
+ * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: oddebug.c 692 2008-11-07 15:07:40Z cs $
+ */
+
+#include "oddebug.h"
+
+#if DEBUG_LEVEL > 0
+
+#warning "Never compile production devices with debugging enabled"
+
+static void uartPutc(char c)
+{
+ while(!(ODDBG_USR & (1 << ODDBG_UDRE))); /* wait for data register empty */
+ ODDBG_UDR = c;
+}
+
+static uchar hexAscii(uchar h)
+{
+ h &= 0xf;
+ if(h >= 10)
+ h += 'a' - (uchar)10 - '0';
+ h += '0';
+ return h;
+}
+
+static void printHex(uchar c)
+{
+ uartPutc(hexAscii(c >> 4));
+ uartPutc(hexAscii(c));
+}
+
+void odDebug(uchar prefix, uchar *data, uchar len)
+{
+ printHex(prefix);
+ uartPutc(':');
+ while(len--){
+ uartPutc(' ');
+ printHex(*data++);
+ }
+ uartPutc('\r');
+ uartPutc('\n');
+}
+
+#endif
--- /dev/null
+/* Name: oddebug.h
+ * Project: AVR library
+ * Author: Christian Starkjohann
+ * Creation Date: 2005-01-16
+ * Tabsize: 4
+ * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: oddebug.h 692 2008-11-07 15:07:40Z cs $
+ */
+
+#ifndef __oddebug_h_included__
+#define __oddebug_h_included__
+
+/*
+General Description:
+This module implements a function for debug logs on the serial line of the
+AVR microcontroller. Debugging can be configured with the define
+'DEBUG_LEVEL'. If this macro is not defined or defined to 0, all debugging
+calls are no-ops. If it is 1, DBG1 logs will appear, but not DBG2. If it is
+2, DBG1 and DBG2 logs will be printed.
+
+A debug log consists of a label ('prefix') to indicate which debug log created
+the output and a memory block to dump in hex ('data' and 'len').
+*/
+
+
+#ifndef F_CPU
+# define F_CPU 12000000 /* 12 MHz */
+#endif
+
+/* make sure we have the UART defines: */
+#include "usbportability.h"
+
+#ifndef uchar
+# define uchar unsigned char
+#endif
+
+#if DEBUG_LEVEL > 0 && !(defined TXEN || defined TXEN0) /* no UART in device */
+# warning "Debugging disabled because device has no UART"
+# undef DEBUG_LEVEL
+#endif
+
+#ifndef DEBUG_LEVEL
+# define DEBUG_LEVEL 0
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#if DEBUG_LEVEL > 0
+# define DBG1(prefix, data, len) odDebug(prefix, data, len)
+#else
+# define DBG1(prefix, data, len)
+#endif
+
+#if DEBUG_LEVEL > 1
+# define DBG2(prefix, data, len) odDebug(prefix, data, len)
+#else
+# define DBG2(prefix, data, len)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#if DEBUG_LEVEL > 0
+extern void odDebug(uchar prefix, uchar *data, uchar len);
+
+/* Try to find our control registers; ATMEL likes to rename these */
+
+#if defined UBRR
+# define ODDBG_UBRR UBRR
+#elif defined UBRRL
+# define ODDBG_UBRR UBRRL
+#elif defined UBRR0
+# define ODDBG_UBRR UBRR0
+#elif defined UBRR0L
+# define ODDBG_UBRR UBRR0L
+#endif
+
+#if defined UCR
+# define ODDBG_UCR UCR
+#elif defined UCSRB
+# define ODDBG_UCR UCSRB
+#elif defined UCSR0B
+# define ODDBG_UCR UCSR0B
+#endif
+
+#if defined TXEN
+# define ODDBG_TXEN TXEN
+#else
+# define ODDBG_TXEN TXEN0
+#endif
+
+#if defined USR
+# define ODDBG_USR USR
+#elif defined UCSRA
+# define ODDBG_USR UCSRA
+#elif defined UCSR0A
+# define ODDBG_USR UCSR0A
+#endif
+
+#if defined UDRE
+# define ODDBG_UDRE UDRE
+#else
+# define ODDBG_UDRE UDRE0
+#endif
+
+#if defined UDR
+# define ODDBG_UDR UDR
+#elif defined UDR0
+# define ODDBG_UDR UDR0
+#endif
+
+static inline void odDebugInit(void)
+{
+ ODDBG_UCR |= (1<<ODDBG_TXEN);
+ ODDBG_UBRR = F_CPU / (19200 * 16L) - 1;
+}
+#else
+# define odDebugInit()
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#endif /* __oddebug_h_included__ */
--- /dev/null
+/* Name: usbdrv.c
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2004-12-29
+ * Tabsize: 4
+ * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrv.c 763 2009-08-22 10:27:24Z cs $
+ */
+
+#include "usbportability.h"
+#include "usbdrv.h"
+#include "oddebug.h"
+
+/*
+General Description:
+This module implements the C-part of the USB driver. See usbdrv.h for a
+documentation of the entire driver.
+*/
+
+/* ------------------------------------------------------------------------- */
+
+/* raw USB registers / interface to assembler code: */
+uchar usbRxBuf[2*USB_BUFSIZE]; /* raw RX buffer: PID, 8 bytes data, 2 bytes CRC */
+uchar usbInputBufOffset; /* offset in usbRxBuf used for low level receiving */
+uchar usbDeviceAddr; /* assigned during enumeration, defaults to 0 */
+uchar usbNewDeviceAddr; /* device ID which should be set after status phase */
+uchar usbConfiguration; /* currently selected configuration. Administered by driver, but not used */
+volatile schar usbRxLen; /* = 0; number of bytes in usbRxBuf; 0 means free, -1 for flow control */
+uchar usbCurrentTok; /* last token received or endpoint number for last OUT token if != 0 */
+uchar usbRxToken; /* token for data we received; or endpont number for last OUT */
+volatile uchar usbTxLen = USBPID_NAK; /* number of bytes to transmit with next IN token or handshake token */
+uchar usbTxBuf[USB_BUFSIZE];/* data to transmit with next IN, free if usbTxLen contains handshake token */
+#if USB_COUNT_SOF
+volatile uchar usbSofCount; /* incremented by assembler module every SOF */
+#endif
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE
+usbTxStatus_t usbTxStatus1;
+# if USB_CFG_HAVE_INTRIN_ENDPOINT3
+usbTxStatus_t usbTxStatus3;
+# endif
+#endif
+#if USB_CFG_CHECK_DATA_TOGGLING
+uchar usbCurrentDataToken;/* when we check data toggling to ignore duplicate packets */
+#endif
+
+/* USB status registers / not shared with asm code */
+uchar *usbMsgPtr; /* data to transmit next -- ROM or RAM address */
+static usbMsgLen_t usbMsgLen = USB_NO_MSG; /* remaining number of bytes */
+static uchar usbMsgFlags; /* flag values see below */
+
+#define USB_FLG_MSGPTR_IS_ROM (1<<6)
+#define USB_FLG_USE_USER_RW (1<<7)
+
+/*
+optimizing hints:
+- do not post/pre inc/dec integer values in operations
+- assign value of USB_READ_FLASH() to register variables and don't use side effects in arg
+- use narrow scope for variables which should be in X/Y/Z register
+- assign char sized expressions to variables to force 8 bit arithmetics
+*/
+
+/* -------------------------- String Descriptors --------------------------- */
+
+#if USB_CFG_DESCR_PROPS_STRINGS == 0
+
+#if USB_CFG_DESCR_PROPS_STRING_0 == 0
+#undef USB_CFG_DESCR_PROPS_STRING_0
+#define USB_CFG_DESCR_PROPS_STRING_0 sizeof(usbDescriptorString0)
+PROGMEM char usbDescriptorString0[] = { /* language descriptor */
+ 4, /* sizeof(usbDescriptorString0): length of descriptor in bytes */
+ 3, /* descriptor type */
+ 0x09, 0x04, /* language index (0x0409 = US-English) */
+};
+#endif
+
+#if USB_CFG_DESCR_PROPS_STRING_VENDOR == 0 && USB_CFG_VENDOR_NAME_LEN
+#undef USB_CFG_DESCR_PROPS_STRING_VENDOR
+#define USB_CFG_DESCR_PROPS_STRING_VENDOR sizeof(usbDescriptorStringVendor)
+PROGMEM int usbDescriptorStringVendor[] = {
+ USB_STRING_DESCRIPTOR_HEADER(USB_CFG_VENDOR_NAME_LEN),
+ USB_CFG_VENDOR_NAME
+};
+#endif
+
+#if USB_CFG_DESCR_PROPS_STRING_PRODUCT == 0 && USB_CFG_DEVICE_NAME_LEN
+#undef USB_CFG_DESCR_PROPS_STRING_PRODUCT
+#define USB_CFG_DESCR_PROPS_STRING_PRODUCT sizeof(usbDescriptorStringDevice)
+PROGMEM int usbDescriptorStringDevice[] = {
+ USB_STRING_DESCRIPTOR_HEADER(USB_CFG_DEVICE_NAME_LEN),
+ USB_CFG_DEVICE_NAME
+};
+#endif
+
+#if USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER == 0 && USB_CFG_SERIAL_NUMBER_LEN
+#undef USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER
+#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER sizeof(usbDescriptorStringSerialNumber)
+PROGMEM int usbDescriptorStringSerialNumber[] = {
+ USB_STRING_DESCRIPTOR_HEADER(USB_CFG_SERIAL_NUMBER_LEN),
+ USB_CFG_SERIAL_NUMBER
+};
+#endif
+
+#endif /* USB_CFG_DESCR_PROPS_STRINGS == 0 */
+
+/* --------------------------- Device Descriptor --------------------------- */
+
+#if USB_CFG_DESCR_PROPS_DEVICE == 0
+#undef USB_CFG_DESCR_PROPS_DEVICE
+#define USB_CFG_DESCR_PROPS_DEVICE sizeof(usbDescriptorDevice)
+PROGMEM char usbDescriptorDevice[] = { /* USB device descriptor */
+ 18, /* sizeof(usbDescriptorDevice): length of descriptor in bytes */
+ USBDESCR_DEVICE, /* descriptor type */
+ 0x10, 0x01, /* USB version supported */
+ USB_CFG_DEVICE_CLASS,
+ USB_CFG_DEVICE_SUBCLASS,
+ 0, /* protocol */
+ 8, /* max packet size */
+ /* the following two casts affect the first byte of the constant only, but
+ * that's sufficient to avoid a warning with the default values.
+ */
+ (char)USB_CFG_VENDOR_ID,/* 2 bytes */
+ (char)USB_CFG_DEVICE_ID,/* 2 bytes */
+ USB_CFG_DEVICE_VERSION, /* 2 bytes */
+ USB_CFG_DESCR_PROPS_STRING_VENDOR != 0 ? 1 : 0, /* manufacturer string index */
+ USB_CFG_DESCR_PROPS_STRING_PRODUCT != 0 ? 2 : 0, /* product string index */
+ USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER != 0 ? 3 : 0, /* serial number string index */
+ 1, /* number of configurations */
+};
+#endif
+
+/* ----------------------- Configuration Descriptor ------------------------ */
+
+#if USB_CFG_DESCR_PROPS_HID_REPORT != 0 && USB_CFG_DESCR_PROPS_HID == 0
+#undef USB_CFG_DESCR_PROPS_HID
+#define USB_CFG_DESCR_PROPS_HID 9 /* length of HID descriptor in config descriptor below */
+#endif
+
+#if USB_CFG_DESCR_PROPS_CONFIGURATION == 0
+#undef USB_CFG_DESCR_PROPS_CONFIGURATION
+#define USB_CFG_DESCR_PROPS_CONFIGURATION sizeof(usbDescriptorConfiguration)
+PROGMEM char usbDescriptorConfiguration[] = { /* USB configuration descriptor */
+ 9, /* sizeof(usbDescriptorConfiguration): length of descriptor in bytes */
+ USBDESCR_CONFIG, /* descriptor type */
+ 18 + 7 * USB_CFG_HAVE_INTRIN_ENDPOINT + 7 * USB_CFG_HAVE_INTRIN_ENDPOINT3 +
+ (USB_CFG_DESCR_PROPS_HID & 0xff), 0,
+ /* total length of data returned (including inlined descriptors) */
+ 1, /* number of interfaces in this configuration */
+ 1, /* index of this configuration */
+ 0, /* configuration name string index */
+#if USB_CFG_IS_SELF_POWERED
+ (1 << 7) | USBATTR_SELFPOWER, /* attributes */
+#else
+ (1 << 7), /* attributes */
+#endif
+ USB_CFG_MAX_BUS_POWER/2, /* max USB current in 2mA units */
+/* interface descriptor follows inline: */
+ 9, /* sizeof(usbDescrInterface): length of descriptor in bytes */
+ USBDESCR_INTERFACE, /* descriptor type */
+ 0, /* index of this interface */
+ 0, /* alternate setting for this interface */
+ USB_CFG_HAVE_INTRIN_ENDPOINT + USB_CFG_HAVE_INTRIN_ENDPOINT3, /* endpoints excl 0: number of endpoint descriptors to follow */
+ USB_CFG_INTERFACE_CLASS,
+ USB_CFG_INTERFACE_SUBCLASS,
+ USB_CFG_INTERFACE_PROTOCOL,
+ 0, /* string index for interface */
+#if (USB_CFG_DESCR_PROPS_HID & 0xff) /* HID descriptor */
+ 9, /* sizeof(usbDescrHID): length of descriptor in bytes */
+ USBDESCR_HID, /* descriptor type: HID */
+ 0x01, 0x01, /* BCD representation of HID version */
+ 0x00, /* target country code */
+ 0x01, /* number of HID Report (or other HID class) Descriptor infos to follow */
+ 0x22, /* descriptor type: report */
+ USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH, 0, /* total length of report descriptor */
+#endif
+#if USB_CFG_HAVE_INTRIN_ENDPOINT /* endpoint descriptor for endpoint 1 */
+ 7, /* sizeof(usbDescrEndpoint) */
+ USBDESCR_ENDPOINT, /* descriptor type = endpoint */
+ (char)0x81, /* IN endpoint number 1 */
+ 0x03, /* attrib: Interrupt endpoint */
+ 8, 0, /* maximum packet size */
+ USB_CFG_INTR_POLL_INTERVAL, /* in ms */
+#endif
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3 /* endpoint descriptor for endpoint 3 */
+ 7, /* sizeof(usbDescrEndpoint) */
+ USBDESCR_ENDPOINT, /* descriptor type = endpoint */
+ (char)0x83, /* IN endpoint number 1 */
+ 0x03, /* attrib: Interrupt endpoint */
+ 8, 0, /* maximum packet size */
+ USB_CFG_INTR_POLL_INTERVAL, /* in ms */
+#endif
+};
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+static inline void usbResetDataToggling(void)
+{
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE
+ USB_SET_DATATOKEN1(USB_INITIAL_DATATOKEN); /* reset data toggling for interrupt endpoint */
+# if USB_CFG_HAVE_INTRIN_ENDPOINT3
+ USB_SET_DATATOKEN3(USB_INITIAL_DATATOKEN); /* reset data toggling for interrupt endpoint */
+# endif
+#endif
+}
+
+static inline void usbResetStall(void)
+{
+#if USB_CFG_IMPLEMENT_HALT && USB_CFG_HAVE_INTRIN_ENDPOINT
+ usbTxLen1 = USBPID_NAK;
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+ usbTxLen3 = USBPID_NAK;
+#endif
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if !USB_CFG_SUPPRESS_INTR_CODE
+#if USB_CFG_HAVE_INTRIN_ENDPOINT
+static void usbGenericSetInterrupt(uchar *data, uchar len, usbTxStatus_t *txStatus)
+{
+uchar *p;
+char i;
+
+#if USB_CFG_IMPLEMENT_HALT
+ if(usbTxLen1 == USBPID_STALL)
+ return;
+#endif
+ if(txStatus->len & 0x10){ /* packet buffer was empty */
+ txStatus->buffer[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */
+ }else{
+ txStatus->len = USBPID_NAK; /* avoid sending outdated (overwritten) interrupt data */
+ }
+ p = txStatus->buffer + 1;
+ i = len;
+ do{ /* if len == 0, we still copy 1 byte, but that's no problem */
+ *p++ = *data++;
+ }while(--i > 0); /* loop control at the end is 2 bytes shorter than at beginning */
+ usbCrc16Append(&txStatus->buffer[1], len);
+ txStatus->len = len + 4; /* len must be given including sync byte */
+ DBG2(0x21 + (((int)txStatus >> 3) & 3), txStatus->buffer, len + 3);
+}
+
+USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len)
+{
+ usbGenericSetInterrupt(data, len, &usbTxStatus1);
+}
+#endif
+
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len)
+{
+ usbGenericSetInterrupt(data, len, &usbTxStatus3);
+}
+#endif
+#endif /* USB_CFG_SUPPRESS_INTR_CODE */
+
+/* ------------------ utilities for code following below ------------------- */
+
+/* Use defines for the switch statement so that we can choose between an
+ * if()else if() and a switch/case based implementation. switch() is more
+ * efficient for a LARGE set of sequential choices, if() is better in all other
+ * cases.
+ */
+#if USB_CFG_USE_SWITCH_STATEMENT
+# define SWITCH_START(cmd) switch(cmd){{
+# define SWITCH_CASE(value) }break; case (value):{
+# define SWITCH_CASE2(v1,v2) }break; case (v1): case(v2):{
+# define SWITCH_CASE3(v1,v2,v3) }break; case (v1): case(v2): case(v3):{
+# define SWITCH_DEFAULT }break; default:{
+# define SWITCH_END }}
+#else
+# define SWITCH_START(cmd) {uchar _cmd = cmd; if(0){
+# define SWITCH_CASE(value) }else if(_cmd == (value)){
+# define SWITCH_CASE2(v1,v2) }else if(_cmd == (v1) || _cmd == (v2)){
+# define SWITCH_CASE3(v1,v2,v3) }else if(_cmd == (v1) || _cmd == (v2) || (_cmd == v3)){
+# define SWITCH_DEFAULT }else{
+# define SWITCH_END }}
+#endif
+
+#ifndef USB_RX_USER_HOOK
+#define USB_RX_USER_HOOK(data, len)
+#endif
+#ifndef USB_SET_ADDRESS_HOOK
+#define USB_SET_ADDRESS_HOOK()
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* We use if() instead of #if in the macro below because #if can't be used
+ * in macros and the compiler optimizes constant conditions anyway.
+ * This may cause problems with undefined symbols if compiled without
+ * optimizing!
+ */
+#define GET_DESCRIPTOR(cfgProp, staticName) \
+ if(cfgProp){ \
+ if((cfgProp) & USB_PROP_IS_RAM) \
+ flags = 0; \
+ if((cfgProp) & USB_PROP_IS_DYNAMIC){ \
+ len = usbFunctionDescriptor(rq); \
+ }else{ \
+ len = USB_PROP_LENGTH(cfgProp); \
+ usbMsgPtr = (uchar *)(staticName); \
+ } \
+ }
+
+/* usbDriverDescriptor() is similar to usbFunctionDescriptor(), but used
+ * internally for all types of descriptors.
+ */
+static inline usbMsgLen_t usbDriverDescriptor(usbRequest_t *rq)
+{
+usbMsgLen_t len = 0;
+uchar flags = USB_FLG_MSGPTR_IS_ROM;
+
+ SWITCH_START(rq->wValue.bytes[1])
+ SWITCH_CASE(USBDESCR_DEVICE) /* 1 */
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice)
+ SWITCH_CASE(USBDESCR_CONFIG) /* 2 */
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration)
+ SWITCH_CASE(USBDESCR_STRING) /* 3 */
+#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC
+ if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM)
+ flags = 0;
+ len = usbFunctionDescriptor(rq);
+#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */
+ SWITCH_START(rq->wValue.bytes[0])
+ SWITCH_CASE(0)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0)
+ SWITCH_CASE(1)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor)
+ SWITCH_CASE(2)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice)
+ SWITCH_CASE(3)
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber)
+ SWITCH_DEFAULT
+ if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
+ len = usbFunctionDescriptor(rq);
+ }
+ SWITCH_END
+#endif /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */
+#if USB_CFG_DESCR_PROPS_HID_REPORT /* only support HID descriptors if enabled */
+ SWITCH_CASE(USBDESCR_HID) /* 0x21 */
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18)
+ SWITCH_CASE(USBDESCR_HID_REPORT)/* 0x22 */
+ GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport)
+#endif
+ SWITCH_DEFAULT
+ if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
+ len = usbFunctionDescriptor(rq);
+ }
+ SWITCH_END
+ usbMsgFlags = flags;
+ return len;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* usbDriverSetup() is similar to usbFunctionSetup(), but it's used for
+ * standard requests instead of class and custom requests.
+ */
+static inline usbMsgLen_t usbDriverSetup(usbRequest_t *rq)
+{
+uchar len = 0, *dataPtr = usbTxBuf + 9; /* there are 2 bytes free space at the end of the buffer */
+uchar value = rq->wValue.bytes[0];
+#if USB_CFG_IMPLEMENT_HALT
+uchar index = rq->wIndex.bytes[0];
+#endif
+
+ dataPtr[0] = 0; /* default reply common to USBRQ_GET_STATUS and USBRQ_GET_INTERFACE */
+ SWITCH_START(rq->bRequest)
+ SWITCH_CASE(USBRQ_GET_STATUS) /* 0 */
+ uchar recipient = rq->bmRequestType & USBRQ_RCPT_MASK; /* assign arith ops to variables to enforce byte size */
+ if(USB_CFG_IS_SELF_POWERED && recipient == USBRQ_RCPT_DEVICE)
+ dataPtr[0] = USB_CFG_IS_SELF_POWERED;
+#if USB_CFG_IMPLEMENT_HALT
+ if(recipient == USBRQ_RCPT_ENDPOINT && index == 0x81) /* request status for endpoint 1 */
+ dataPtr[0] = usbTxLen1 == USBPID_STALL;
+#endif
+ dataPtr[1] = 0;
+ len = 2;
+#if USB_CFG_IMPLEMENT_HALT
+ SWITCH_CASE2(USBRQ_CLEAR_FEATURE, USBRQ_SET_FEATURE) /* 1, 3 */
+ if(value == 0 && index == 0x81){ /* feature 0 == HALT for endpoint == 1 */
+ usbTxLen1 = rq->bRequest == USBRQ_CLEAR_FEATURE ? USBPID_NAK : USBPID_STALL;
+ usbResetDataToggling();
+ }
+#endif
+ SWITCH_CASE(USBRQ_SET_ADDRESS) /* 5 */
+ usbNewDeviceAddr = value;
+ USB_SET_ADDRESS_HOOK();
+ SWITCH_CASE(USBRQ_GET_DESCRIPTOR) /* 6 */
+ len = usbDriverDescriptor(rq);
+ goto skipMsgPtrAssignment;
+ SWITCH_CASE(USBRQ_GET_CONFIGURATION) /* 8 */
+ dataPtr = &usbConfiguration; /* send current configuration value */
+ len = 1;
+ SWITCH_CASE(USBRQ_SET_CONFIGURATION) /* 9 */
+ usbConfiguration = value;
+ usbResetStall();
+ SWITCH_CASE(USBRQ_GET_INTERFACE) /* 10 */
+ len = 1;
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE
+ SWITCH_CASE(USBRQ_SET_INTERFACE) /* 11 */
+ usbResetDataToggling();
+ usbResetStall();
+#endif
+ SWITCH_DEFAULT /* 7=SET_DESCRIPTOR, 12=SYNC_FRAME */
+ /* Should we add an optional hook here? */
+ SWITCH_END
+ usbMsgPtr = dataPtr;
+skipMsgPtrAssignment:
+ return len;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* usbProcessRx() is called for every message received by the interrupt
+ * routine. It distinguishes between SETUP and DATA packets and processes
+ * them accordingly.
+ */
+static inline void usbProcessRx(uchar *data, uchar len)
+{
+usbRequest_t *rq = (void *)data;
+
+/* usbRxToken can be:
+ * 0x2d 00101101 (USBPID_SETUP for setup data)
+ * 0xe1 11100001 (USBPID_OUT: data phase of setup transfer)
+ * 0...0x0f for OUT on endpoint X
+ */
+ DBG2(0x10 + (usbRxToken & 0xf), data, len + 2); /* SETUP=1d, SETUP-DATA=11, OUTx=1x */
+ USB_RX_USER_HOOK(data, len)
+#if USB_CFG_IMPLEMENT_FN_WRITEOUT
+ if(usbRxToken < 0x10){ /* OUT to endpoint != 0: endpoint number in usbRxToken */
+ usbFunctionWriteOut(data, len);
+ return;
+ }
+#endif
+ if(usbRxToken == (uchar)USBPID_SETUP){
+ if(len != 8) /* Setup size must be always 8 bytes. Ignore otherwise. */
+ return;
+ usbMsgLen_t replyLen;
+ usbTxBuf[0] = USBPID_DATA0; /* initialize data toggling */
+ usbTxLen = USBPID_NAK; /* abort pending transmit */
+ usbMsgFlags = 0;
+ uchar type = rq->bmRequestType & USBRQ_TYPE_MASK;
+ if(type != USBRQ_TYPE_STANDARD){ /* standard requests are handled by driver */
+ replyLen = usbFunctionSetup(data);
+ }else{
+ replyLen = usbDriverSetup(rq);
+ }
+#if USB_CFG_IMPLEMENT_FN_READ || USB_CFG_IMPLEMENT_FN_WRITE
+ if(replyLen == USB_NO_MSG){ /* use user-supplied read/write function */
+ /* do some conditioning on replyLen, but on IN transfers only */
+ if((rq->bmRequestType & USBRQ_DIR_MASK) != USBRQ_DIR_HOST_TO_DEVICE){
+ if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */
+ replyLen = rq->wLength.bytes[0];
+ }else{
+ replyLen = rq->wLength.word;
+ }
+ }
+ usbMsgFlags = USB_FLG_USE_USER_RW;
+ }else /* The 'else' prevents that we limit a replyLen of USB_NO_MSG to the maximum transfer len. */
+#endif
+ if(sizeof(replyLen) < sizeof(rq->wLength.word)){ /* help compiler with optimizing */
+ if(!rq->wLength.bytes[1] && replyLen > rq->wLength.bytes[0]) /* limit length to max */
+ replyLen = rq->wLength.bytes[0];
+ }else{
+ if(replyLen > rq->wLength.word) /* limit length to max */
+ replyLen = rq->wLength.word;
+ }
+ usbMsgLen = replyLen;
+ }else{ /* usbRxToken must be USBPID_OUT, which means data phase of setup (control-out) */
+#if USB_CFG_IMPLEMENT_FN_WRITE
+ if(usbMsgFlags & USB_FLG_USE_USER_RW){
+ uchar rval = usbFunctionWrite(data, len);
+ if(rval == 0xff){ /* an error occurred */
+ usbTxLen = USBPID_STALL;
+ }else if(rval != 0){ /* This was the final package */
+ usbMsgLen = 0; /* answer with a zero-sized data packet */
+ }
+ }
+#endif
+ }
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* This function is similar to usbFunctionRead(), but it's also called for
+ * data handled automatically by the driver (e.g. descriptor reads).
+ */
+static uchar usbDeviceRead(uchar *data, uchar len)
+{
+ if(len > 0){ /* don't bother app with 0 sized reads */
+#if USB_CFG_IMPLEMENT_FN_READ
+ if(usbMsgFlags & USB_FLG_USE_USER_RW){
+ len = usbFunctionRead(data, len);
+ }else
+#endif
+ {
+ uchar i = len, *r = usbMsgPtr;
+ if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */
+ do{
+ uchar c = USB_READ_FLASH(r); /* assign to char size variable to enforce byte ops */
+ *data++ = c;
+ r++;
+ }while(--i);
+ }else{ /* RAM data */
+ do{
+ *data++ = *r++;
+ }while(--i);
+ }
+ usbMsgPtr = r;
+ }
+ }
+ return len;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* usbBuildTxBlock() is called when we have data to transmit and the
+ * interrupt routine's transmit buffer is empty.
+ */
+static inline void usbBuildTxBlock(void)
+{
+usbMsgLen_t wantLen;
+uchar len;
+
+ wantLen = usbMsgLen;
+ if(wantLen > 8)
+ wantLen = 8;
+ usbMsgLen -= wantLen;
+ usbTxBuf[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* DATA toggling */
+ len = usbDeviceRead(usbTxBuf + 1, wantLen);
+ if(len <= 8){ /* valid data packet */
+ usbCrc16Append(&usbTxBuf[1], len);
+ len += 4; /* length including sync byte */
+ if(len < 12) /* a partial package identifies end of message */
+ usbMsgLen = USB_NO_MSG;
+ }else{
+ len = USBPID_STALL; /* stall the endpoint */
+ usbMsgLen = USB_NO_MSG;
+ }
+ usbTxLen = len;
+ DBG2(0x20, usbTxBuf, len-1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static inline void usbHandleResetHook(uchar notResetState)
+{
+#ifdef USB_RESET_HOOK
+static uchar wasReset;
+uchar isReset = !notResetState;
+
+ if(wasReset != isReset){
+ USB_RESET_HOOK(isReset);
+ wasReset = isReset;
+ }
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+USB_PUBLIC void usbPoll(void)
+{
+schar len;
+uchar i;
+
+ len = usbRxLen - 3;
+ if(len >= 0){
+/* We could check CRC16 here -- but ACK has already been sent anyway. If you
+ * need data integrity checks with this driver, check the CRC in your app
+ * code and report errors back to the host. Since the ACK was already sent,
+ * retries must be handled on application level.
+ * unsigned crc = usbCrc16(buffer + 1, usbRxLen - 3);
+ */
+ usbProcessRx(usbRxBuf + USB_BUFSIZE + 1 - usbInputBufOffset, len);
+#if USB_CFG_HAVE_FLOWCONTROL
+ if(usbRxLen > 0) /* only mark as available if not inactivated */
+ usbRxLen = 0;
+#else
+ usbRxLen = 0; /* mark rx buffer as available */
+#endif
+ }
+ if(usbTxLen & 0x10){ /* transmit system idle */
+ if(usbMsgLen != USB_NO_MSG){ /* transmit data pending? */
+ usbBuildTxBlock();
+ }
+ }
+ for(i = 20; i > 0; i--){
+ uchar usbLineStatus = USBIN & USBMASK;
+ if(usbLineStatus != 0) /* SE0 has ended */
+ goto isNotReset;
+ }
+ /* RESET condition, called multiple times during reset */
+ usbNewDeviceAddr = 0;
+ usbDeviceAddr = 0;
+ usbResetStall();
+ DBG1(0xff, 0, 0);
+isNotReset:
+ usbHandleResetHook(i);
+}
+
+/* ------------------------------------------------------------------------- */
+
+USB_PUBLIC void usbInit(void)
+{
+#if USB_INTR_CFG_SET != 0
+/*
+In this enviroment.
+compiler: gcc version 4.3.2 (WinAVR 20090313)
+mcu target: mega164p
+gcc produces a bad object. This source is good. The easy way to fix this problem is rearrange it.
+*/
+ //USB_INTR_CFG |= USB_INTR_CFG_SET;
+ USB_INTR_CFG = USB_INTR_CFG_SET;
+#endif
+#if USB_INTR_CFG_CLR != 0
+ USB_INTR_CFG &= ~(USB_INTR_CFG_CLR);
+#endif
+ USB_INTR_ENABLE |= (1 << USB_INTR_ENABLE_BIT);
+ usbResetDataToggling();
+#if USB_CFG_HAVE_INTRIN_ENDPOINT && !USB_CFG_SUPPRESS_INTR_CODE
+ usbTxLen1 = USBPID_NAK;
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+ usbTxLen3 = USBPID_NAK;
+#endif
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
--- /dev/null
+/* Name: usbdrv.h
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2004-12-29
+ * Tabsize: 4
+ * Copyright: (c) 2005 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrv.h 769 2009-08-22 11:49:05Z cs $
+ */
+
+#ifndef __usbdrv_h_included__
+#define __usbdrv_h_included__
+#if !defined __ASSEMBLER__
+ #include "kazzo_request.h"
+#endif
+#include "usbconfig.h"
+#include "usbportability.h"
+
+/*
+Hardware Prerequisites:
+=======================
+USB lines D+ and D- MUST be wired to the same I/O port. We recommend that D+
+triggers the interrupt (best achieved by using INT0 for D+), but it is also
+possible to trigger the interrupt from D-. If D- is used, interrupts are also
+triggered by SOF packets. D- requires a pull-up of 1.5k to +3.5V (and the
+device must be powered at 3.5V) to identify as low-speed USB device. A
+pull-down or pull-up of 1M SHOULD be connected from D+ to +3.5V to prevent
+interference when no USB master is connected. If you use Zener diodes to limit
+the voltage on D+ and D-, you MUST use a pull-down resistor, not a pull-up.
+We use D+ as interrupt source and not D- because it does not trigger on
+keep-alive and RESET states. If you want to count keep-alive events with
+USB_COUNT_SOF, you MUST use D- as an interrupt source.
+
+As a compile time option, the 1.5k pull-up resistor on D- can be made
+switchable to allow the device to disconnect at will. See the definition of
+usbDeviceConnect() and usbDeviceDisconnect() further down in this file.
+
+Please adapt the values in usbconfig.h according to your hardware!
+
+The device MUST be clocked at exactly 12 MHz, 15 MHz, 16 MHz or 20 MHz
+or at 12.8 MHz resp. 16.5 MHz +/- 1%. See usbconfig-prototype.h for details.
+
+
+Limitations:
+============
+Robustness with respect to communication errors:
+The driver assumes error-free communication. It DOES check for errors in
+the PID, but does NOT check bit stuffing errors, SE0 in middle of a byte,
+token CRC (5 bit) and data CRC (16 bit). CRC checks can not be performed due
+to timing constraints: We must start sending a reply within 7 bit times.
+Bit stuffing and misplaced SE0 would have to be checked in real-time, but CPU
+performance does not permit that. The driver does not check Data0/Data1
+toggling, but application software can implement the check.
+
+Input characteristics:
+Since no differential receiver circuit is used, electrical interference
+robustness may suffer. The driver samples only one of the data lines with
+an ordinary I/O pin's input characteristics. However, since this is only a
+low speed USB implementation and the specification allows for 8 times the
+bit rate over the same hardware, we should be on the safe side. Even the spec
+requires detection of asymmetric states at high bit rate for SE0 detection.
+
+Number of endpoints:
+The driver supports the following endpoints:
+
+- Endpoint 0, the default control endpoint.
+- Any number of interrupt- or bulk-out endpoints. The data is sent to
+ usbFunctionWriteOut() and USB_CFG_IMPLEMENT_FN_WRITEOUT must be defined
+ to 1 to activate this feature. The endpoint number can be found in the
+ global variable 'usbRxToken'.
+- One default interrupt- or bulk-in endpoint. This endpoint is used for
+ interrupt- or bulk-in transfers which are not handled by any other endpoint.
+ You must define USB_CFG_HAVE_INTRIN_ENDPOINT in order to activate this
+ feature and call usbSetInterrupt() to send interrupt/bulk data.
+- One additional interrupt- or bulk-in endpoint. This was endpoint 3 in
+ previous versions of this driver but can now be configured to any endpoint
+ number. You must define USB_CFG_HAVE_INTRIN_ENDPOINT3 in order to activate
+ this feature and call usbSetInterrupt3() to send interrupt/bulk data. The
+ endpoint number can be set with USB_CFG_EP3_NUMBER.
+
+Please note that the USB standard forbids bulk endpoints for low speed devices!
+Most operating systems allow them anyway, but the AVR will spend 90% of the CPU
+time in the USB interrupt polling for bulk data.
+
+Maximum data payload:
+Data payload of control in and out transfers may be up to 254 bytes. In order
+to accept payload data of out transfers, you need to implement
+'usbFunctionWrite()'.
+
+USB Suspend Mode supply current:
+The USB standard limits power consumption to 500uA when the bus is in suspend
+mode. This is not a problem for self-powered devices since they don't need
+bus power anyway. Bus-powered devices can achieve this only by putting the
+CPU in sleep mode. The driver does not implement suspend handling by itself.
+However, the application may implement activity monitoring and wakeup from
+sleep. The host sends regular SE0 states on the bus to keep it active. These
+SE0 states can be detected by using D- as the interrupt source. Define
+USB_COUNT_SOF to 1 and use the global variable usbSofCount to check for bus
+activity.
+
+Operation without an USB master:
+The driver behaves neutral without connection to an USB master if D- reads
+as 1. To avoid spurious interrupts, we recommend a high impedance (e.g. 1M)
+pull-down or pull-up resistor on D+ (interrupt). If Zener diodes are used,
+use a pull-down. If D- becomes statically 0, the driver may block in the
+interrupt routine.
+
+Interrupt latency:
+The application must ensure that the USB interrupt is not disabled for more
+than 25 cycles (this is for 12 MHz, faster clocks allow longer latency).
+This implies that all interrupt routines must either be declared as "INTERRUPT"
+instead of "SIGNAL" (see "avr/signal.h") or that they are written in assembler
+with "sei" as the first instruction.
+
+Maximum interrupt duration / CPU cycle consumption:
+The driver handles all USB communication during the interrupt service
+routine. The routine will not return before an entire USB message is received
+and the reply is sent. This may be up to ca. 1200 cycles @ 12 MHz (= 100us) if
+the host conforms to the standard. The driver will consume CPU cycles for all
+USB messages, even if they address another (low-speed) device on the same bus.
+
+*/
+
+/* ------------------------------------------------------------------------- */
+/* --------------------------- Module Interface ---------------------------- */
+/* ------------------------------------------------------------------------- */
+
+#define USBDRV_VERSION 20090822
+/* This define uniquely identifies a driver version. It is a decimal number
+ * constructed from the driver's release date in the form YYYYMMDD. If the
+ * driver's behavior or interface changes, you can use this constant to
+ * distinguish versions. If it is not defined, the driver's release date is
+ * older than 2006-01-25.
+ */
+
+
+#ifndef USB_PUBLIC
+#define USB_PUBLIC
+#endif
+/* USB_PUBLIC is used as declaration attribute for all functions exported by
+ * the USB driver. The default is no attribute (see above). You may define it
+ * to static either in usbconfig.h or from the command line if you include
+ * usbdrv.c instead of linking against it. Including the C module of the driver
+ * directly in your code saves a couple of bytes in flash memory.
+ */
+
+#ifndef __ASSEMBLER__
+#ifndef uchar
+#define uchar unsigned char
+#endif
+#ifndef schar
+#define schar signed char
+#endif
+/* shortcuts for well defined 8 bit integer types */
+
+#if USB_CFG_LONG_TRANSFERS /* if more than 254 bytes transfer size required */
+# define usbMsgLen_t unsigned
+#else
+# define usbMsgLen_t uchar
+#endif
+/* usbMsgLen_t is the data type used for transfer lengths. By default, it is
+ * defined to uchar, allowing a maximum of 254 bytes (255 is reserved for
+ * USB_NO_MSG below). If the usbconfig.h defines USB_CFG_LONG_TRANSFERS to 1,
+ * a 16 bit data type is used, allowing up to 16384 bytes (the rest is used
+ * for flags in the descriptor configuration).
+ */
+#define USB_NO_MSG ((usbMsgLen_t)-1) /* constant meaning "no message" */
+
+struct usbRequest; /* forward declaration */
+
+USB_PUBLIC void usbInit(void);
+/* This function must be called before interrupts are enabled and the main
+ * loop is entered. We exepct that the PORT and DDR bits for D+ and D- have
+ * not been changed from their default status (which is 0). If you have changed
+ * them, set both back to 0 (configure them as input with no internal pull-up).
+ */
+USB_PUBLIC void usbPoll(void);
+/* This function must be called at regular intervals from the main loop.
+ * Maximum delay between calls is somewhat less than 50ms (USB timeout for
+ * accepting a Setup message). Otherwise the device will not be recognized.
+ * Please note that debug outputs through the UART take ~ 0.5ms per byte
+ * at 19200 bps.
+ */
+extern uchar *usbMsgPtr;
+/* This variable may be used to pass transmit data to the driver from the
+ * implementation of usbFunctionWrite(). It is also used internally by the
+ * driver for standard control requests.
+ */
+USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]);
+/* This function is called when the driver receives a SETUP transaction from
+ * the host which is not answered by the driver itself (in practice: class and
+ * vendor requests). All control transfers start with a SETUP transaction where
+ * the host communicates the parameters of the following (optional) data
+ * transfer. The SETUP data is available in the 'data' parameter which can
+ * (and should) be casted to 'usbRequest_t *' for a more user-friendly access
+ * to parameters.
+ *
+ * If the SETUP indicates a control-in transfer, you should provide the
+ * requested data to the driver. There are two ways to transfer this data:
+ * (1) Set the global pointer 'usbMsgPtr' to the base of the static RAM data
+ * block and return the length of the data in 'usbFunctionSetup()'. The driver
+ * will handle the rest. Or (2) return USB_NO_MSG in 'usbFunctionSetup()'. The
+ * driver will then call 'usbFunctionRead()' when data is needed. See the
+ * documentation for usbFunctionRead() for details.
+ *
+ * If the SETUP indicates a control-out transfer, the only way to receive the
+ * data from the host is through the 'usbFunctionWrite()' call. If you
+ * implement this function, you must return USB_NO_MSG in 'usbFunctionSetup()'
+ * to indicate that 'usbFunctionWrite()' should be used. See the documentation
+ * of this function for more information. If you just want to ignore the data
+ * sent by the host, return 0 in 'usbFunctionSetup()'.
+ *
+ * Note that calls to the functions usbFunctionRead() and usbFunctionWrite()
+ * are only done if enabled by the configuration in usbconfig.h.
+ */
+USB_PUBLIC usbMsgLen_t usbFunctionDescriptor(struct usbRequest *rq);
+/* You need to implement this function ONLY if you provide USB descriptors at
+ * runtime (which is an expert feature). It is very similar to
+ * usbFunctionSetup() above, but it is called only to request USB descriptor
+ * data. See the documentation of usbFunctionSetup() above for more info.
+ */
+#if USB_CFG_HAVE_INTRIN_ENDPOINT
+USB_PUBLIC void usbSetInterrupt(uchar *data, uchar len);
+/* This function sets the message which will be sent during the next interrupt
+ * IN transfer. The message is copied to an internal buffer and must not exceed
+ * a length of 8 bytes. The message may be 0 bytes long just to indicate the
+ * interrupt status to the host.
+ * If you need to transfer more bytes, use a control read after the interrupt.
+ */
+#define usbInterruptIsReady() (usbTxLen1 & 0x10)
+/* This macro indicates whether the last interrupt message has already been
+ * sent. If you set a new interrupt message before the old was sent, the
+ * message already buffered will be lost.
+ */
+#if USB_CFG_HAVE_INTRIN_ENDPOINT3
+USB_PUBLIC void usbSetInterrupt3(uchar *data, uchar len);
+#define usbInterruptIsReady3() (usbTxLen3 & 0x10)
+/* Same as above for endpoint 3 */
+#endif
+#endif /* USB_CFG_HAVE_INTRIN_ENDPOINT */
+#if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH /* simplified interface for backward compatibility */
+#define usbHidReportDescriptor usbDescriptorHidReport
+/* should be declared as: PROGMEM char usbHidReportDescriptor[]; */
+/* If you implement an HID device, you need to provide a report descriptor.
+ * The HID report descriptor syntax is a bit complex. If you understand how
+ * report descriptors are constructed, we recommend that you use the HID
+ * Descriptor Tool from usb.org, see http://www.usb.org/developers/hidpage/.
+ * Otherwise you should probably start with a working example.
+ */
+#endif /* USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH */
+#if USB_CFG_IMPLEMENT_FN_WRITE
+USB_PUBLIC uchar usbFunctionWrite(uchar *data, uchar len);
+/* This function is called by the driver to provide a control transfer's
+ * payload data (control-out). It is called in chunks of up to 8 bytes. The
+ * total count provided in the current control transfer can be obtained from
+ * the 'length' property in the setup data. If an error occurred during
+ * processing, return 0xff (== -1). The driver will answer the entire transfer
+ * with a STALL token in this case. If you have received the entire payload
+ * successfully, return 1. If you expect more data, return 0. If you don't
+ * know whether the host will send more data (you should know, the total is
+ * provided in the usbFunctionSetup() call!), return 1.
+ * NOTE: If you return 0xff for STALL, 'usbFunctionWrite()' may still be called
+ * for the remaining data. You must continue to return 0xff for STALL in these
+ * calls.
+ * In order to get usbFunctionWrite() called, define USB_CFG_IMPLEMENT_FN_WRITE
+ * to 1 in usbconfig.h and return 0xff in usbFunctionSetup()..
+ */
+#endif /* USB_CFG_IMPLEMENT_FN_WRITE */
+#if USB_CFG_IMPLEMENT_FN_READ
+USB_PUBLIC uchar usbFunctionRead(uchar *data, uchar len);
+/* This function is called by the driver to ask the application for a control
+ * transfer's payload data (control-in). It is called in chunks of up to 8
+ * bytes each. You should copy the data to the location given by 'data' and
+ * return the actual number of bytes copied. If you return less than requested,
+ * the control-in transfer is terminated. If you return 0xff, the driver aborts
+ * the transfer with a STALL token.
+ * In order to get usbFunctionRead() called, define USB_CFG_IMPLEMENT_FN_READ
+ * to 1 in usbconfig.h and return 0xff in usbFunctionSetup()..
+ */
+#endif /* USB_CFG_IMPLEMENT_FN_READ */
+
+extern uchar usbRxToken; /* may be used in usbFunctionWriteOut() below */
+#if USB_CFG_IMPLEMENT_FN_WRITEOUT
+USB_PUBLIC void usbFunctionWriteOut(uchar *data, uchar len);
+/* This function is called by the driver when data is received on an interrupt-
+ * or bulk-out endpoint. The endpoint number can be found in the global
+ * variable usbRxToken. You must define USB_CFG_IMPLEMENT_FN_WRITEOUT to 1 in
+ * usbconfig.h to get this function called.
+ */
+#endif /* USB_CFG_IMPLEMENT_FN_WRITEOUT */
+#ifdef USB_CFG_PULLUP_IOPORTNAME
+#define usbDeviceConnect() ((USB_PULLUP_DDR |= (1<<USB_CFG_PULLUP_BIT)), \
+ (USB_PULLUP_OUT |= (1<<USB_CFG_PULLUP_BIT)))
+#define usbDeviceDisconnect() ((USB_PULLUP_DDR &= ~(1<<USB_CFG_PULLUP_BIT)), \
+ (USB_PULLUP_OUT &= ~(1<<USB_CFG_PULLUP_BIT)))
+#else /* USB_CFG_PULLUP_IOPORTNAME */
+#define usbDeviceConnect() (USBDDR &= ~(1<<USBMINUS))
+#define usbDeviceDisconnect() (USBDDR |= (1<<USBMINUS))
+#endif /* USB_CFG_PULLUP_IOPORTNAME */
+/* The macros usbDeviceConnect() and usbDeviceDisconnect() (intended to look
+ * like a function) connect resp. disconnect the device from the host's USB.
+ * If the constants USB_CFG_PULLUP_IOPORT and USB_CFG_PULLUP_BIT are defined
+ * in usbconfig.h, a disconnect consists of removing the pull-up resisitor
+ * from D-, otherwise the disconnect is done by brute-force pulling D- to GND.
+ * This does not conform to the spec, but it works.
+ * Please note that the USB interrupt must be disabled while the device is
+ * in disconnected state, or the interrupt handler will hang! You can either
+ * turn off the USB interrupt selectively with
+ * USB_INTR_ENABLE &= ~(1 << USB_INTR_ENABLE_BIT)
+ * or use cli() to disable interrupts globally.
+ */
+extern unsigned usbCrc16(unsigned data, uchar len);
+#define usbCrc16(data, len) usbCrc16((unsigned)(data), len)
+/* This function calculates the binary complement of the data CRC used in
+ * USB data packets. The value is used to build raw transmit packets.
+ * You may want to use this function for data checksums or to verify received
+ * data. We enforce 16 bit calling conventions for compatibility with IAR's
+ * tiny memory model.
+ */
+extern unsigned usbCrc16Append(unsigned data, uchar len);
+#define usbCrc16Append(data, len) usbCrc16Append((unsigned)(data), len)
+/* This function is equivalent to usbCrc16() above, except that it appends
+ * the 2 bytes CRC (lowbyte first) in the 'data' buffer after reading 'len'
+ * bytes.
+ */
+#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH
+extern unsigned usbMeasureFrameLength(void);
+/* This function MUST be called IMMEDIATELY AFTER USB reset and measures 1/7 of
+ * the number of CPU cycles during one USB frame minus one low speed bit
+ * length. In other words: return value = 1499 * (F_CPU / 10.5 MHz)
+ * Since this is a busy wait, you MUST disable all interrupts with cli() before
+ * calling this function.
+ * This can be used to calibrate the AVR's RC oscillator.
+ */
+#endif
+extern uchar usbConfiguration;
+/* This value contains the current configuration set by the host. The driver
+ * allows setting and querying of this variable with the USB SET_CONFIGURATION
+ * and GET_CONFIGURATION requests, but does not use it otherwise.
+ * You may want to reflect the "configured" status with a LED on the device or
+ * switch on high power parts of the circuit only if the device is configured.
+ */
+#if USB_COUNT_SOF
+extern volatile uchar usbSofCount;
+/* This variable is incremented on every SOF packet. It is only available if
+ * the macro USB_COUNT_SOF is defined to a value != 0.
+ */
+#endif
+#if USB_CFG_CHECK_DATA_TOGGLING
+extern uchar usbCurrentDataToken;
+/* This variable can be checked in usbFunctionWrite() and usbFunctionWriteOut()
+ * to ignore duplicate packets.
+ */
+#endif
+
+#define USB_STRING_DESCRIPTOR_HEADER(stringLength) ((2*(stringLength)+2) | (3<<8))
+/* This macro builds a descriptor header for a string descriptor given the
+ * string's length. See usbdrv.c for an example how to use it.
+ */
+#if USB_CFG_HAVE_FLOWCONTROL
+extern volatile schar usbRxLen;
+#define usbDisableAllRequests() usbRxLen = -1
+/* Must be called from usbFunctionWrite(). This macro disables all data input
+ * from the USB interface. Requests from the host are answered with a NAK
+ * while they are disabled.
+ */
+#define usbEnableAllRequests() usbRxLen = 0
+/* May only be called if requests are disabled. This macro enables input from
+ * the USB interface after it has been disabled with usbDisableAllRequests().
+ */
+#define usbAllRequestsAreDisabled() (usbRxLen < 0)
+/* Use this macro to find out whether requests are disabled. It may be needed
+ * to ensure that usbEnableAllRequests() is never called when requests are
+ * enabled.
+ */
+#endif
+
+#define USB_SET_DATATOKEN1(token) usbTxBuf1[0] = token
+#define USB_SET_DATATOKEN3(token) usbTxBuf3[0] = token
+/* These two macros can be used by application software to reset data toggling
+ * for interrupt-in endpoints 1 and 3. Since the token is toggled BEFORE
+ * sending data, you must set the opposite value of the token which should come
+ * first.
+ */
+
+#endif /* __ASSEMBLER__ */
+
+
+/* ------------------------------------------------------------------------- */
+/* ----------------- Definitions for Descriptor Properties ----------------- */
+/* ------------------------------------------------------------------------- */
+/* This is advanced stuff. See usbconfig-prototype.h for more information
+ * about the various methods to define USB descriptors. If you do nothing,
+ * the default descriptors will be used.
+ */
+#define USB_PROP_IS_DYNAMIC (1 << 14)
+/* If this property is set for a descriptor, usbFunctionDescriptor() will be
+ * used to obtain the particular descriptor. Data directly returned via
+ * usbMsgPtr are FLASH data by default, combine (OR) with USB_PROP_IS_RAM to
+ * return RAM data.
+ */
+#define USB_PROP_IS_RAM (1 << 15)
+/* If this property is set for a descriptor, the data is read from RAM
+ * memory instead of Flash. The property is used for all methods to provide
+ * external descriptors.
+ */
+#define USB_PROP_LENGTH(len) ((len) & 0x3fff)
+/* If a static external descriptor is used, this is the total length of the
+ * descriptor in bytes.
+ */
+
+/* all descriptors which may have properties: */
+#ifndef USB_CFG_DESCR_PROPS_DEVICE
+#define USB_CFG_DESCR_PROPS_DEVICE 0
+#endif
+#ifndef USB_CFG_DESCR_PROPS_CONFIGURATION
+#define USB_CFG_DESCR_PROPS_CONFIGURATION 0
+#endif
+#ifndef USB_CFG_DESCR_PROPS_STRINGS
+#define USB_CFG_DESCR_PROPS_STRINGS 0
+#endif
+#ifndef USB_CFG_DESCR_PROPS_STRING_0
+#define USB_CFG_DESCR_PROPS_STRING_0 0
+#endif
+#ifndef USB_CFG_DESCR_PROPS_STRING_VENDOR
+#define USB_CFG_DESCR_PROPS_STRING_VENDOR 0
+#endif
+#ifndef USB_CFG_DESCR_PROPS_STRING_PRODUCT
+#define USB_CFG_DESCR_PROPS_STRING_PRODUCT 0
+#endif
+#ifndef USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER
+#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER 0
+#endif
+#ifndef USB_CFG_DESCR_PROPS_HID
+#define USB_CFG_DESCR_PROPS_HID 0
+#endif
+#if !(USB_CFG_DESCR_PROPS_HID_REPORT)
+# undef USB_CFG_DESCR_PROPS_HID_REPORT
+# if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH /* do some backward compatibility tricks */
+# define USB_CFG_DESCR_PROPS_HID_REPORT USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH
+# else
+# define USB_CFG_DESCR_PROPS_HID_REPORT 0
+# endif
+#endif
+#ifndef USB_CFG_DESCR_PROPS_UNKNOWN
+#define USB_CFG_DESCR_PROPS_UNKNOWN 0
+#endif
+
+/* ------------------ forward declaration of descriptors ------------------- */
+/* If you use external static descriptors, they must be stored in global
+ * arrays as declared below:
+ */
+#ifndef __ASSEMBLER__
+extern
+#if !(USB_CFG_DESCR_PROPS_DEVICE & USB_PROP_IS_RAM)
+PROGMEM
+#endif
+char usbDescriptorDevice[];
+
+extern
+#if !(USB_CFG_DESCR_PROPS_CONFIGURATION & USB_PROP_IS_RAM)
+PROGMEM
+#endif
+char usbDescriptorConfiguration[];
+
+extern
+#if !(USB_CFG_DESCR_PROPS_HID_REPORT & USB_PROP_IS_RAM)
+PROGMEM
+#endif
+char usbDescriptorHidReport[];
+
+extern
+#if !(USB_CFG_DESCR_PROPS_STRING_0 & USB_PROP_IS_RAM)
+PROGMEM
+#endif
+char usbDescriptorString0[];
+
+extern
+#if !(USB_CFG_DESCR_PROPS_STRING_VENDOR & USB_PROP_IS_RAM)
+PROGMEM
+#endif
+int usbDescriptorStringVendor[];
+
+extern
+#if !(USB_CFG_DESCR_PROPS_STRING_PRODUCT & USB_PROP_IS_RAM)
+PROGMEM
+#endif
+int usbDescriptorStringDevice[];
+
+extern
+#if !(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER & USB_PROP_IS_RAM)
+PROGMEM
+#endif
+int usbDescriptorStringSerialNumber[];
+
+#endif /* __ASSEMBLER__ */
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------ General Purpose Macros ------------------------- */
+/* ------------------------------------------------------------------------- */
+
+#define USB_CONCAT(a, b) a ## b
+#define USB_CONCAT_EXPANDED(a, b) USB_CONCAT(a, b)
+
+#define USB_OUTPORT(name) USB_CONCAT(PORT, name)
+#define USB_INPORT(name) USB_CONCAT(PIN, name)
+#define USB_DDRPORT(name) USB_CONCAT(DDR, name)
+/* The double-define trick above lets us concatenate strings which are
+ * defined by macros.
+ */
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------- Constant definitions -------------------------- */
+/* ------------------------------------------------------------------------- */
+
+#if !defined __ASSEMBLER__ && (!defined USB_CFG_VENDOR_ID || !defined USB_CFG_DEVICE_ID)
+#warning "You should define USB_CFG_VENDOR_ID and USB_CFG_DEVICE_ID in usbconfig.h"
+/* If the user has not defined IDs, we default to obdev's free IDs.
+ * See USB-IDs-for-free.txt for details.
+ */
+#endif
+
+/* make sure we have a VID and PID defined, byte order is lowbyte, highbyte */
+#ifndef USB_CFG_VENDOR_ID
+# define USB_CFG_VENDOR_ID 0xc0, 0x16 /* = 0x16c0 = 5824 = voti.nl */
+#endif
+
+#ifndef USB_CFG_DEVICE_ID
+# if USB_CFG_HID_REPORT_DESCRIPTOR_LENGTH
+# define USB_CFG_DEVICE_ID 0xdf, 0x05 /* = 0x5df = 1503, shared PID for HIDs */
+# elif USB_CFG_INTERFACE_CLASS == 2
+# define USB_CFG_DEVICE_ID 0xe1, 0x05 /* = 0x5e1 = 1505, shared PID for CDC Modems */
+# else
+# define USB_CFG_DEVICE_ID 0xdc, 0x05 /* = 0x5dc = 1500, obdev's free PID */
+# endif
+#endif
+
+/* Derive Output, Input and DataDirection ports from port names */
+#ifndef USB_CFG_IOPORTNAME
+#error "You must define USB_CFG_IOPORTNAME in usbconfig.h, see usbconfig-prototype.h"
+#endif
+
+#define USBOUT USB_OUTPORT(USB_CFG_IOPORTNAME)
+#define USB_PULLUP_OUT USB_OUTPORT(USB_CFG_PULLUP_IOPORTNAME)
+#define USBIN USB_INPORT(USB_CFG_IOPORTNAME)
+#define USBDDR USB_DDRPORT(USB_CFG_IOPORTNAME)
+#define USB_PULLUP_DDR USB_DDRPORT(USB_CFG_PULLUP_IOPORTNAME)
+
+#define USBMINUS USB_CFG_DMINUS_BIT
+#define USBPLUS USB_CFG_DPLUS_BIT
+#define USBIDLE (1<<USB_CFG_DMINUS_BIT) /* value representing J state */
+#define USBMASK ((1<<USB_CFG_DPLUS_BIT) | (1<<USB_CFG_DMINUS_BIT)) /* mask for USB I/O bits */
+
+/* defines for backward compatibility with older driver versions: */
+#define USB_CFG_IOPORT USB_OUTPORT(USB_CFG_IOPORTNAME)
+#ifdef USB_CFG_PULLUP_IOPORTNAME
+#define USB_CFG_PULLUP_IOPORT USB_OUTPORT(USB_CFG_PULLUP_IOPORTNAME)
+#endif
+
+#ifndef USB_CFG_EP3_NUMBER /* if not defined in usbconfig.h */
+#define USB_CFG_EP3_NUMBER 3
+#endif
+
+#ifndef USB_CFG_HAVE_INTRIN_ENDPOINT3
+#define USB_CFG_HAVE_INTRIN_ENDPOINT3 0
+#endif
+
+#define USB_BUFSIZE 11 /* PID, 8 bytes data, 2 bytes CRC */
+
+/* ----- Try to find registers and bits responsible for ext interrupt 0 ----- */
+
+#ifndef USB_INTR_CFG /* allow user to override our default */
+# if defined EICRA
+# define USB_INTR_CFG EICRA
+# else
+# define USB_INTR_CFG MCUCR
+# endif
+#endif
+#ifndef USB_INTR_CFG_SET /* allow user to override our default */
+# if defined(USB_COUNT_SOF) || defined(USB_SOF_HOOK)
+# define USB_INTR_CFG_SET (1 << ISC01) /* cfg for falling edge */
+ /* If any SOF logic is used, the interrupt must be wired to D- where
+ * we better trigger on falling edge
+ */
+# else
+# define USB_INTR_CFG_SET ((1 << ISC00) | (1 << ISC01)) /* cfg for rising edge */
+# endif
+#endif
+#ifndef USB_INTR_CFG_CLR /* allow user to override our default */
+# define USB_INTR_CFG_CLR 0 /* no bits to clear */
+#endif
+
+#ifndef USB_INTR_ENABLE /* allow user to override our default */
+# if defined GIMSK
+# define USB_INTR_ENABLE GIMSK
+# elif defined EIMSK
+# define USB_INTR_ENABLE EIMSK
+# else
+# define USB_INTR_ENABLE GICR
+# endif
+#endif
+#ifndef USB_INTR_ENABLE_BIT /* allow user to override our default */
+# define USB_INTR_ENABLE_BIT INT0
+#endif
+
+#ifndef USB_INTR_PENDING /* allow user to override our default */
+# if defined EIFR
+# define USB_INTR_PENDING EIFR
+# else
+# define USB_INTR_PENDING GIFR
+# endif
+#endif
+#ifndef USB_INTR_PENDING_BIT /* allow user to override our default */
+# define USB_INTR_PENDING_BIT INTF0
+#endif
+
+/*
+The defines above don't work for the following chips
+at90c8534: no ISC0?, no PORTB, can't find a data sheet
+at86rf401: no PORTB, no MCUCR etc, low clock rate
+atmega103: no ISC0? (maybe omission in header, can't find data sheet)
+atmega603: not defined in avr-libc
+at43usb320, at43usb355, at76c711: have USB anyway
+at94k: is different...
+
+at90s1200, attiny11, attiny12, attiny15, attiny28: these have no RAM
+*/
+
+/* ------------------------------------------------------------------------- */
+/* ----------------- USB Specification Constants and Types ----------------- */
+/* ------------------------------------------------------------------------- */
+
+/* USB Token values */
+#define USBPID_SETUP 0x2d
+#define USBPID_OUT 0xe1
+#define USBPID_IN 0x69
+#define USBPID_DATA0 0xc3
+#define USBPID_DATA1 0x4b
+
+#define USBPID_ACK 0xd2
+#define USBPID_NAK 0x5a
+#define USBPID_STALL 0x1e
+
+#ifndef USB_INITIAL_DATATOKEN
+#define USB_INITIAL_DATATOKEN USBPID_DATA1
+#endif
+
+#ifndef __ASSEMBLER__
+
+typedef struct usbTxStatus{
+ volatile uchar len;
+ uchar buffer[USB_BUFSIZE];
+}usbTxStatus_t;
+
+extern usbTxStatus_t usbTxStatus1, usbTxStatus3;
+#define usbTxLen1 usbTxStatus1.len
+#define usbTxBuf1 usbTxStatus1.buffer
+#define usbTxLen3 usbTxStatus3.len
+#define usbTxBuf3 usbTxStatus3.buffer
+
+
+typedef union usbWord{
+ unsigned word;
+ uchar bytes[2];
+}usbWord_t;
+
+typedef struct usbRequest{
+ uchar bmRequestType;
+ uchar bRequest;
+ usbWord_t wValue;
+ usbWord_t wIndex;
+ usbWord_t wLength;
+}usbRequest_t;
+/* This structure matches the 8 byte setup request */
+#endif
+
+/* bmRequestType field in USB setup:
+ * d t t r r r r r, where
+ * d ..... direction: 0=host->device, 1=device->host
+ * t ..... type: 0=standard, 1=class, 2=vendor, 3=reserved
+ * r ..... recipient: 0=device, 1=interface, 2=endpoint, 3=other
+ */
+
+/* USB setup recipient values */
+#define USBRQ_RCPT_MASK 0x1f
+#define USBRQ_RCPT_DEVICE 0
+#define USBRQ_RCPT_INTERFACE 1
+#define USBRQ_RCPT_ENDPOINT 2
+
+/* USB request type values */
+#define USBRQ_TYPE_MASK 0x60
+#define USBRQ_TYPE_STANDARD (0<<5)
+#define USBRQ_TYPE_CLASS (1<<5)
+#define USBRQ_TYPE_VENDOR (2<<5)
+
+/* USB direction values: */
+#define USBRQ_DIR_MASK 0x80
+#define USBRQ_DIR_HOST_TO_DEVICE (0<<7)
+#define USBRQ_DIR_DEVICE_TO_HOST (1<<7)
+
+/* USB Standard Requests */
+#define USBRQ_GET_STATUS 0
+#define USBRQ_CLEAR_FEATURE 1
+#define USBRQ_SET_FEATURE 3
+#define USBRQ_SET_ADDRESS 5
+#define USBRQ_GET_DESCRIPTOR 6
+#define USBRQ_SET_DESCRIPTOR 7
+#define USBRQ_GET_CONFIGURATION 8
+#define USBRQ_SET_CONFIGURATION 9
+#define USBRQ_GET_INTERFACE 10
+#define USBRQ_SET_INTERFACE 11
+#define USBRQ_SYNCH_FRAME 12
+
+/* USB descriptor constants */
+#define USBDESCR_DEVICE 1
+#define USBDESCR_CONFIG 2
+#define USBDESCR_STRING 3
+#define USBDESCR_INTERFACE 4
+#define USBDESCR_ENDPOINT 5
+#define USBDESCR_HID 0x21
+#define USBDESCR_HID_REPORT 0x22
+#define USBDESCR_HID_PHYS 0x23
+
+//#define USBATTR_BUSPOWER 0x80 // USB 1.1 does not define this value any more
+#define USBATTR_SELFPOWER 0x40
+#define USBATTR_REMOTEWAKE 0x20
+
+/* USB HID Requests */
+#define USBRQ_HID_GET_REPORT 0x01
+#define USBRQ_HID_GET_IDLE 0x02
+#define USBRQ_HID_GET_PROTOCOL 0x03
+#define USBRQ_HID_SET_REPORT 0x09
+#define USBRQ_HID_SET_IDLE 0x0a
+#define USBRQ_HID_SET_PROTOCOL 0x0b
+
+/* ------------------------------------------------------------------------- */
+
+#endif /* __usbdrv_h_included__ */
--- /dev/null
+/* Name: usbdrvasm.S
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-06-13
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id$
+ */
+
+/*
+General Description:
+This module is the assembler part of the USB driver. This file contains
+general code (preprocessor acrobatics and CRC computation) and then includes
+the file appropriate for the given clock rate.
+*/
+
+#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */
+#include "usbportability.h"
+#include "usbdrv.h" /* for common defs */
+
+/* register names */
+#define x1 r16
+#define x2 r17
+#define shift r18
+#define cnt r19
+#define x3 r20
+#define x4 r21
+#define x5 r22
+#define bitcnt x5
+#define phase x4
+#define leap x4
+
+/* Some assembler dependent definitions and declarations: */
+
+#ifdef __IAR_SYSTEMS_ASM__
+ extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset
+ extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen
+ extern usbTxBuf, usbTxStatus1, usbTxStatus3
+# if USB_COUNT_SOF
+ extern usbSofCount
+# endif
+ public usbCrc16
+ public usbCrc16Append
+
+ COMMON INTVEC
+# ifndef USB_INTR_VECTOR
+ ORG INT0_vect
+# else /* USB_INTR_VECTOR */
+ ORG USB_INTR_VECTOR
+# undef USB_INTR_VECTOR
+# endif /* USB_INTR_VECTOR */
+# define USB_INTR_VECTOR usbInterruptHandler
+ rjmp USB_INTR_VECTOR
+ RSEG CODE
+
+#else /* __IAR_SYSTEMS_ASM__ */
+
+# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */
+# define USB_INTR_VECTOR SIG_INTERRUPT0
+# endif
+ .text
+ .global USB_INTR_VECTOR
+ .type USB_INTR_VECTOR, @function
+ .global usbCrc16
+ .global usbCrc16Append
+#endif /* __IAR_SYSTEMS_ASM__ */
+
+
+#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */
+# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING
+# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg
+#else /* It's a memory address, use lds and sts */
+# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING
+# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg
+#endif
+
+#define usbTxLen1 usbTxStatus1
+#define usbTxBuf1 (usbTxStatus1 + 1)
+#define usbTxLen3 usbTxStatus3
+#define usbTxBuf3 (usbTxStatus3 + 1)
+
+
+;----------------------------------------------------------------------------
+; Utility functions
+;----------------------------------------------------------------------------
+
+#ifdef __IAR_SYSTEMS_ASM__
+/* Register assignments for usbCrc16 on IAR cc */
+/* Calling conventions on IAR:
+ * First parameter passed in r16/r17, second in r18/r19 and so on.
+ * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer)
+ * Result is passed in r16/r17
+ * In case of the "tiny" memory model, pointers are only 8 bit with no
+ * padding. We therefore pass argument 1 as "16 bit unsigned".
+ */
+RTMODEL "__rt_version", "3"
+/* The line above will generate an error if cc calling conventions change.
+ * The value "3" above is valid for IAR 4.10B/W32
+ */
+# define argLen r18 /* argument 2 */
+# define argPtrL r16 /* argument 1 */
+# define argPtrH r17 /* argument 1 */
+
+# define resCrcL r16 /* result */
+# define resCrcH r17 /* result */
+
+# define ptrL ZL
+# define ptrH ZH
+# define ptr Z
+# define byte r22
+# define bitCnt r19
+# define polyL r20
+# define polyH r21
+# define scratch r23
+
+#else /* __IAR_SYSTEMS_ASM__ */
+/* Register assignments for usbCrc16 on gcc */
+/* Calling conventions on gcc:
+ * First parameter passed in r24/r25, second in r22/23 and so on.
+ * Callee must preserve r1-r17, r28/r29
+ * Result is passed in r24/r25
+ */
+# define argLen r22 /* argument 2 */
+# define argPtrL r24 /* argument 1 */
+# define argPtrH r25 /* argument 1 */
+
+# define resCrcL r24 /* result */
+# define resCrcH r25 /* result */
+
+# define ptrL XL
+# define ptrH XH
+# define ptr x
+# define byte r18
+# define bitCnt r19
+# define polyL r20
+# define polyH r21
+# define scratch r23
+
+#endif
+
+#if USB_USE_FAST_CRC
+
+; This implementation is faster, but has bigger code size
+; Thanks to Slawomir Fras (BoskiDialer) for this code!
+; It implements the following C pseudo-code:
+; unsigned table(unsigned char x)
+; {
+; unsigned value;
+;
+; value = (unsigned)x << 6;
+; value ^= (unsigned)x << 7;
+; if(parity(x))
+; value ^= 0xc001;
+; return value;
+; }
+; unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen)
+; {
+; unsigned crc = 0xffff;
+;
+; while(argLen--)
+; crc = table(lo8(crc) ^ *argPtr++) ^ hi8(crc);
+; return ~crc;
+; }
+
+; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen);
+; argPtr r24+25 / r16+r17
+; argLen r22 / r18
+; temp variables:
+; byte r18 / r22
+; scratch r23
+; resCrc r24+r25 / r16+r17
+; ptr X / Z
+usbCrc16:
+ mov ptrL, argPtrL
+ mov ptrH, argPtrH
+ ldi resCrcL, 0xFF
+ ldi resCrcH, 0xFF
+ rjmp usbCrc16LoopTest
+usbCrc16ByteLoop:
+ ld byte, ptr+
+ eor resCrcL, byte ; resCrcL is now 'x' in table()
+ mov byte, resCrcL ; compute parity of 'x'
+ swap byte
+ eor byte, resCrcL
+ mov scratch, byte
+ lsr byte
+ lsr byte
+ eor byte, scratch
+ inc byte
+ lsr byte
+ andi byte, 1 ; byte is now parity(x)
+ mov scratch, resCrcL
+ mov resCrcL, resCrcH
+ eor resCrcL, byte ; low byte of if(parity(x)) value ^= 0xc001;
+ neg byte
+ andi byte, 0xc0
+ mov resCrcH, byte ; high byte of if(parity(x)) value ^= 0xc001;
+ clr byte
+ lsr scratch
+ ror byte
+ eor resCrcH, scratch
+ eor resCrcL, byte
+ lsr scratch
+ ror byte
+ eor resCrcH, scratch
+ eor resCrcL, byte
+usbCrc16LoopTest:
+ subi argLen, 1
+ brsh usbCrc16ByteLoop
+ com resCrcL
+ com resCrcH
+ ret
+
+#else /* USB_USE_FAST_CRC */
+
+; This implementation is slower, but has less code size
+;
+; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen);
+; argPtr r24+25 / r16+r17
+; argLen r22 / r18
+; temp variables:
+; byte r18 / r22
+; bitCnt r19
+; poly r20+r21
+; scratch r23
+; resCrc r24+r25 / r16+r17
+; ptr X / Z
+usbCrc16:
+ mov ptrL, argPtrL
+ mov ptrH, argPtrH
+ ldi resCrcL, 0
+ ldi resCrcH, 0
+ ldi polyL, lo8(0xa001)
+ ldi polyH, hi8(0xa001)
+ com argLen ; argLen = -argLen - 1: modified loop to ensure that carry is set
+ ldi bitCnt, 0 ; loop counter with starnd condition = end condition
+ rjmp usbCrcLoopEntry
+usbCrcByteLoop:
+ ld byte, ptr+
+ eor resCrcL, byte
+usbCrcBitLoop:
+ ror resCrcH ; carry is always set here (see brcs jumps to here)
+ ror resCrcL
+ brcs usbCrcNoXor
+ eor resCrcL, polyL
+ eor resCrcH, polyH
+usbCrcNoXor:
+ subi bitCnt, 224 ; (8 * 224) % 256 = 0; this loop iterates 8 times
+ brcs usbCrcBitLoop
+usbCrcLoopEntry:
+ subi argLen, -1
+ brcs usbCrcByteLoop
+usbCrcReady:
+ ret
+; Thanks to Reimar Doeffinger for optimizing this CRC routine!
+
+#endif /* USB_USE_FAST_CRC */
+
+; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len);
+usbCrc16Append:
+ rcall usbCrc16
+ st ptr+, resCrcL
+ st ptr+, resCrcH
+ ret
+
+#undef argLen
+#undef argPtrL
+#undef argPtrH
+#undef resCrcL
+#undef resCrcH
+#undef ptrL
+#undef ptrH
+#undef ptr
+#undef byte
+#undef bitCnt
+#undef polyL
+#undef polyH
+#undef scratch
+
+
+#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH
+#ifdef __IAR_SYSTEMS_ASM__
+/* Register assignments for usbMeasureFrameLength on IAR cc */
+/* Calling conventions on IAR:
+ * First parameter passed in r16/r17, second in r18/r19 and so on.
+ * Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer)
+ * Result is passed in r16/r17
+ * In case of the "tiny" memory model, pointers are only 8 bit with no
+ * padding. We therefore pass argument 1 as "16 bit unsigned".
+ */
+# define resL r16
+# define resH r17
+# define cnt16L r30
+# define cnt16H r31
+# define cntH r18
+
+#else /* __IAR_SYSTEMS_ASM__ */
+/* Register assignments for usbMeasureFrameLength on gcc */
+/* Calling conventions on gcc:
+ * First parameter passed in r24/r25, second in r22/23 and so on.
+ * Callee must preserve r1-r17, r28/r29
+ * Result is passed in r24/r25
+ */
+# define resL r24
+# define resH r25
+# define cnt16L r24
+# define cnt16H r25
+# define cntH r26
+#endif
+# define cnt16 cnt16L
+
+; extern unsigned usbMeasurePacketLength(void);
+; returns time between two idle strobes in multiples of 7 CPU clocks
+.global usbMeasureFrameLength
+usbMeasureFrameLength:
+ ldi cntH, 6 ; wait ~ 10 ms for D- == 0
+ clr cnt16L
+ clr cnt16H
+usbMFTime16:
+ dec cntH
+ breq usbMFTimeout
+usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe)
+ sbiw cnt16, 1 ;[0] [6]
+ breq usbMFTime16 ;[2]
+ sbic USBIN, USBMINUS ;[3]
+ rjmp usbMFWaitStrobe ;[4]
+usbMFWaitIdle: ; then wait until idle again
+ sbis USBIN, USBMINUS ;1 wait for D- == 1
+ rjmp usbMFWaitIdle ;2
+ ldi cnt16L, 1 ;1 represents cycles so far
+ clr cnt16H ;1
+usbMFWaitLoop:
+ in cntH, USBIN ;[0] [7]
+ adiw cnt16, 1 ;[1]
+ breq usbMFTimeout ;[3]
+ andi cntH, USBMASK ;[4]
+ brne usbMFWaitLoop ;[5]
+usbMFTimeout:
+#if resL != cnt16L
+ mov resL, cnt16L
+ mov resH, cnt16H
+#endif
+ ret
+
+#undef resL
+#undef resH
+#undef cnt16
+#undef cnt16L
+#undef cnt16H
+#undef cntH
+
+#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */
+
+;----------------------------------------------------------------------------
+; Now include the clock rate specific code
+;----------------------------------------------------------------------------
+
+#ifndef USB_CFG_CLOCK_KHZ
+# define USB_CFG_CLOCK_KHZ 12000
+#endif
+
+#if USB_CFG_CHECK_CRC /* separate dispatcher for CRC type modules */
+# if USB_CFG_CLOCK_KHZ == 18000
+# include "usbdrvasm18-crc.inc"
+# else
+# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!"
+# endif
+#else /* USB_CFG_CHECK_CRC */
+# if USB_CFG_CLOCK_KHZ == 12000
+# include "usbdrvasm12.inc"
+# elif USB_CFG_CLOCK_KHZ == 12800
+# include "usbdrvasm128.inc"
+# elif USB_CFG_CLOCK_KHZ == 15000
+# include "usbdrvasm15.inc"
+# elif USB_CFG_CLOCK_KHZ == 16000
+# include "usbdrvasm16.inc"
+# elif USB_CFG_CLOCK_KHZ == 16500
+# include "usbdrvasm165.inc"
+# elif USB_CFG_CLOCK_KHZ == 20000
+# include "usbdrvasm20.inc"
+# else
+# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!"
+# endif
+#endif /* USB_CFG_CHECK_CRC */
--- /dev/null
+/* Name: usbdrvasm.asm
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2006-03-01
+ * Tabsize: 4
+ * Copyright: (c) 2006 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id$
+ */
+
+/*
+General Description:
+The IAR compiler/assembler system prefers assembler files with file extension
+".asm". We simply provide this file as an alias for usbdrvasm.S.
+
+Thanks to Oleg Semyonov for his help with the IAR tools port!
+*/
+
+#include "usbdrvasm.S"
+
+end
--- /dev/null
+/* Name: usbdrvasm12.inc
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2004-12-29
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrvasm12.inc 740 2009-04-13 18:23:31Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 12 MHz version of the asssembler part of the USB driver. It
+requires a 12 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+
+
+Timing constraints according to spec (in bit times):
+timing subject min max CPUcycles
+---------------------------------------------------------------------------
+EOP of OUT/SETUP to sync pattern of DATA0 (both rx) 2 16 16-128
+EOP of IN to sync pattern of DATA0 (rx, then tx) 2 7.5 16-60
+DATAx (rx) to ACK/NAK/STALL (tx) 2 7.5 16-60
+*/
+
+;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
+;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
+;max allowable interrupt latency: 34 cycles -> max 25 cycles interrupt disable
+;max stack usage: [ret(2), YL, SREG, YH, shift, x1, x2, x3, cnt, x4] = 11 bytes
+;Numbers in brackets are maximum cycles since SOF.
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt
+ push YL ;2 [35] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;1 [37]
+ push YL ;2 [39]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK:
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push YH ;2 [2]
+ lds YL, usbInputBufOffset;2 [4]
+ clr YH ;1 [5]
+ subi YL, lo8(-(usbRxBuf));1 [6]
+ sbci YH, hi8(-(usbRxBuf));1 [7]
+
+ sbis USBIN, USBMINUS ;1 [8] we want two bits K [sample 1 cycle too early]
+ rjmp haveTwoBitsK ;2 [10]
+ pop YH ;2 [11] undo the push from before
+ rjmp waitForK ;2 [13] this was not the end of sync, retry
+haveTwoBitsK:
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+ push shift ;2 [16]
+ push x1 ;2 [12]
+ push x2 ;2 [14]
+
+ in x1, USBIN ;1 [17] <-- sample bit 0
+ ldi shift, 0xff ;1 [18]
+ bst x1, USBMINUS ;1 [19]
+ bld shift, 0 ;1 [20]
+ push x3 ;2 [22]
+ push cnt ;2 [24]
+
+ in x2, USBIN ;1 [25] <-- sample bit 1
+ ser x3 ;1 [26] [inserted init instruction]
+ eor x1, x2 ;1 [27]
+ bst x1, USBMINUS ;1 [28]
+ bld shift, 1 ;1 [29]
+ ldi cnt, USB_BUFSIZE;1 [30] [inserted init instruction]
+ rjmp rxbit2 ;2 [32]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+
+unstuff0: ;1 (branch taken)
+ andi x3, ~0x01 ;1 [15]
+ mov x1, x2 ;1 [16] x2 contains last sampled (stuffed) bit
+ in x2, USBIN ;1 [17] <-- sample bit 1 again
+ ori shift, 0x01 ;1 [18]
+ rjmp didUnstuff0 ;2 [20]
+
+unstuff1: ;1 (branch taken)
+ mov x2, x1 ;1 [21] x1 contains last sampled (stuffed) bit
+ andi x3, ~0x02 ;1 [22]
+ ori shift, 0x02 ;1 [23]
+ nop ;1 [24]
+ in x1, USBIN ;1 [25] <-- sample bit 2 again
+ rjmp didUnstuff1 ;2 [27]
+
+unstuff2: ;1 (branch taken)
+ andi x3, ~0x04 ;1 [29]
+ ori shift, 0x04 ;1 [30]
+ mov x1, x2 ;1 [31] x2 contains last sampled (stuffed) bit
+ nop ;1 [32]
+ in x2, USBIN ;1 [33] <-- sample bit 3
+ rjmp didUnstuff2 ;2 [35]
+
+unstuff3: ;1 (branch taken)
+ in x2, USBIN ;1 [34] <-- sample stuffed bit 3 [one cycle too late]
+ andi x3, ~0x08 ;1 [35]
+ ori shift, 0x08 ;1 [36]
+ rjmp didUnstuff3 ;2 [38]
+
+unstuff4: ;1 (branch taken)
+ andi x3, ~0x10 ;1 [40]
+ in x1, USBIN ;1 [41] <-- sample stuffed bit 4
+ ori shift, 0x10 ;1 [42]
+ rjmp didUnstuff4 ;2 [44]
+
+unstuff5: ;1 (branch taken)
+ andi x3, ~0x20 ;1 [48]
+ in x2, USBIN ;1 [49] <-- sample stuffed bit 5
+ ori shift, 0x20 ;1 [50]
+ rjmp didUnstuff5 ;2 [52]
+
+unstuff6: ;1 (branch taken)
+ andi x3, ~0x40 ;1 [56]
+ in x1, USBIN ;1 [57] <-- sample stuffed bit 6
+ ori shift, 0x40 ;1 [58]
+ rjmp didUnstuff6 ;2 [60]
+
+; extra jobs done during bit interval:
+; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs]
+; bit 1: se0 check
+; bit 2: overflow check
+; bit 3: recovery from delay [bit 0 tasks took too long]
+; bit 4: none
+; bit 5: none
+; bit 6: none
+; bit 7: jump, eor
+rxLoop:
+ eor x3, shift ;1 [0] reconstruct: x3 is 0 at bit locations we changed, 1 at others
+ in x1, USBIN ;1 [1] <-- sample bit 0
+ st y+, x3 ;2 [3] store data
+ ser x3 ;1 [4]
+ nop ;1 [5]
+ eor x2, x1 ;1 [6]
+ bst x2, USBMINUS;1 [7]
+ bld shift, 0 ;1 [8]
+ in x2, USBIN ;1 [9] <-- sample bit 1 (or possibly bit 0 stuffed)
+ andi x2, USBMASK ;1 [10]
+ breq se0 ;1 [11] SE0 check for bit 1
+ andi shift, 0xf9 ;1 [12]
+didUnstuff0:
+ breq unstuff0 ;1 [13]
+ eor x1, x2 ;1 [14]
+ bst x1, USBMINUS;1 [15]
+ bld shift, 1 ;1 [16]
+rxbit2:
+ in x1, USBIN ;1 [17] <-- sample bit 2 (or possibly bit 1 stuffed)
+ andi shift, 0xf3 ;1 [18]
+ breq unstuff1 ;1 [19] do remaining work for bit 1
+didUnstuff1:
+ subi cnt, 1 ;1 [20]
+ brcs overflow ;1 [21] loop control
+ eor x2, x1 ;1 [22]
+ bst x2, USBMINUS;1 [23]
+ bld shift, 2 ;1 [24]
+ in x2, USBIN ;1 [25] <-- sample bit 3 (or possibly bit 2 stuffed)
+ andi shift, 0xe7 ;1 [26]
+ breq unstuff2 ;1 [27]
+didUnstuff2:
+ eor x1, x2 ;1 [28]
+ bst x1, USBMINUS;1 [29]
+ bld shift, 3 ;1 [30]
+didUnstuff3:
+ andi shift, 0xcf ;1 [31]
+ breq unstuff3 ;1 [32]
+ in x1, USBIN ;1 [33] <-- sample bit 4
+ eor x2, x1 ;1 [34]
+ bst x2, USBMINUS;1 [35]
+ bld shift, 4 ;1 [36]
+didUnstuff4:
+ andi shift, 0x9f ;1 [37]
+ breq unstuff4 ;1 [38]
+ nop2 ;2 [40]
+ in x2, USBIN ;1 [41] <-- sample bit 5
+ eor x1, x2 ;1 [42]
+ bst x1, USBMINUS;1 [43]
+ bld shift, 5 ;1 [44]
+didUnstuff5:
+ andi shift, 0x3f ;1 [45]
+ breq unstuff5 ;1 [46]
+ nop2 ;2 [48]
+ in x1, USBIN ;1 [49] <-- sample bit 6
+ eor x2, x1 ;1 [50]
+ bst x2, USBMINUS;1 [51]
+ bld shift, 6 ;1 [52]
+didUnstuff6:
+ cpi shift, 0x02 ;1 [53]
+ brlo unstuff6 ;1 [54]
+ nop2 ;2 [56]
+ in x2, USBIN ;1 [57] <-- sample bit 7
+ eor x1, x2 ;1 [58]
+ bst x1, USBMINUS;1 [59]
+ bld shift, 7 ;1 [60]
+didUnstuff7:
+ cpi shift, 0x04 ;1 [61]
+ brsh rxLoop ;2 [63] loop control
+unstuff7:
+ andi x3, ~0x80 ;1 [63]
+ ori shift, 0x80 ;1 [64]
+ in x2, USBIN ;1 [65] <-- sample stuffed bit 7
+ nop ;1 [66]
+ rjmp didUnstuff7 ;2 [68]
+
+macro POP_STANDARD ; 12 cycles
+ pop cnt
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ endm
+macro POP_RETI ; 5 cycles
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+;----------------------------------------------------------------------------
+; Transmitting data
+;----------------------------------------------------------------------------
+
+txByteLoop:
+txBitloop:
+stuffN1Delay: ; [03]
+ ror shift ;[-5] [11] [59]
+ brcc doExorN1 ;[-4] [60]
+ subi x4, 1 ;[-3]
+ brne commonN1 ;[-2]
+ lsl shift ;[-1] compensate ror after rjmp stuffDelay
+ nop ;[00] stuffing consists of just waiting 8 cycles
+ rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear
+
+sendNakAndReti: ;0 [-19] 19 cycles until SOP
+ ldi x3, USBPID_NAK ;1 [-18]
+ rjmp usbSendX3 ;2 [-16]
+sendAckAndReti: ;0 [-19] 19 cycles until SOP
+ ldi x3, USBPID_ACK ;1 [-18]
+ rjmp usbSendX3 ;2 [-16]
+sendCntAndReti: ;0 [-17] 17 cycles until SOP
+ mov x3, cnt ;1 [-16]
+usbSendX3: ;0 [-16]
+ ldi YL, 20 ;1 [-15] 'x3' is R20
+ ldi YH, 0 ;1 [-14]
+ ldi cnt, 2 ;1 [-13]
+; rjmp usbSendAndReti fallthrough
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
+; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
+; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte
+;uses: x1...x2, x4, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x4 = bitstuff cnt]
+;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction)
+usbSendAndReti:
+ in x2, USBDDR ;[-12] 12 cycles until SOP
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS ;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ out USBDDR, x2 ;[-8] <--- acquire bus
+ in x1, USBOUT ;[-7] port mirror for tx loop
+ ldi shift, 0x40 ;[-6] sync byte is first byte sent (we enter loop after ror)
+ ldi x2, USBMASK ;[-5]
+ push x4 ;[-4]
+doExorN1:
+ eor x1, x2 ;[-2] [06] [62]
+ ldi x4, 6 ;[-1] [07] [63]
+commonN1:
+stuffN2Delay:
+ out USBOUT, x1 ;[00] [08] [64] <--- set bit
+ ror shift ;[01]
+ brcc doExorN2 ;[02]
+ subi x4, 1 ;[03]
+ brne commonN2 ;[04]
+ lsl shift ;[05] compensate ror after rjmp stuffDelay
+ rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear
+doExorN2:
+ eor x1, x2 ;[04] [12]
+ ldi x4, 6 ;[05] [13]
+commonN2:
+ nop ;[06] [14]
+ subi cnt, 171 ;[07] [15] trick: (3 * 171) & 0xff = 1
+ out USBOUT, x1 ;[08] [16] <--- set bit
+ brcs txBitloop ;[09] [25] [41]
+
+stuff6Delay:
+ ror shift ;[42] [50]
+ brcc doExor6 ;[43]
+ subi x4, 1 ;[44]
+ brne common6 ;[45]
+ lsl shift ;[46] compensate ror after rjmp stuffDelay
+ nop ;[47] stuffing consists of just waiting 8 cycles
+ rjmp stuff6Delay ;[48] after ror, C bit is reliably clear
+doExor6:
+ eor x1, x2 ;[45] [53]
+ ldi x4, 6 ;[46]
+common6:
+stuff7Delay:
+ ror shift ;[47] [55]
+ out USBOUT, x1 ;[48] <--- set bit
+ brcc doExor7 ;[49]
+ subi x4, 1 ;[50]
+ brne common7 ;[51]
+ lsl shift ;[52] compensate ror after rjmp stuffDelay
+ rjmp stuff7Delay ;[53] after ror, C bit is reliably clear
+doExor7:
+ eor x1, x2 ;[51] [59]
+ ldi x4, 6 ;[52]
+common7:
+ ld shift, y+ ;[53]
+ tst cnt ;[55]
+ out USBOUT, x1 ;[56] <--- set bit
+ brne txByteLoop ;[57]
+
+;make SE0:
+ cbr x1, USBMASK ;[58] prepare SE0 [spec says EOP may be 15 to 18 cycles]
+ lds x2, usbNewDeviceAddr;[59]
+ lsl x2 ;[61] we compare with left shifted address
+ subi YL, 2 + 20 ;[62] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;[63]
+ out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[01]
+ sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[03] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[04]
+ ori x1, USBIDLE ;[05]
+ in x2, USBDDR ;[06]
+ cbr x2, USBMASK ;[07] set both pins to input
+ mov x3, x1 ;[08]
+ cbr x3, USBMASK ;[09] configure no pullup on both pins
+ pop x4 ;[10]
+ nop2 ;[12]
+ nop2 ;[14]
+ out USBOUT, x1 ;[16] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[17] <-- release bus now
+ out USBOUT, x3 ;[18] <-- ensure no pull-up resistors are active
+ rjmp doReturn
--- /dev/null
+/* Name: usbdrvasm128.inc
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2008-10-11
+ * Tabsize: 4
+ * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbdrvasm128.inc 758 2009-08-06 10:12:54Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 12.8 MHz version of the USB driver. It is intended for use
+with the internal RC oscillator. Although 12.8 MHz is outside the guaranteed
+calibration range of the oscillator, almost all AVRs can reach this frequency.
+This version contains a phase locked loop in the receiver routine to cope with
+slight clock rate deviations of up to +/- 1%.
+
+See usbdrv.h for a description of the entire driver.
+
+LIMITATIONS
+===========
+Although it may seem very handy to save the crystal and use the internal
+RC oscillator of the CPU, this method (and this module) has some serious
+limitations:
+(1) The guaranteed calibration range of the oscillator is only 8.1 MHz.
+They typical range is 14.5 MHz and most AVRs can actually reach this rate.
+(2) Writing EEPROM and Flash may be unreliable (short data lifetime) since
+the write procedure is timed from the RC oscillator.
+(3) End Of Packet detection (SE0) should be in bit 1, bit it is only checked
+if bits 0 and 1 both read as 0 on D- and D+ read as 0 in the middle. This may
+cause problems with old hubs which delay SE0 by up to one cycle.
+(4) Code size is much larger than that of the other modules.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+
+Implementation notes:
+======================
+min frequency: 67 cycles for 8 bit -> 12.5625 MHz
+max frequency: 69.286 cycles for 8 bit -> 12.99 MHz
+nominal frequency: 12.77 MHz ( = sqrt(min * max))
+
+sampling positions: (next even number in range [+/- 0.5])
+cycle index range: 0 ... 66
+bits:
+.5, 8.875, 17.25, 25.625, 34, 42.375, 50.75, 59.125
+[0/1], [9], [17], [25/+26], [34], [+42/43], [51], [59]
+
+bit number: 0 1 2 3 4 5 6 7
+spare cycles 1 2 1 2 1 1 1 0
+
+operations to perform: duration cycle
+ ----------------
+ eor fix, shift 1 -> 00
+ andi phase, USBMASK 1 -> 08
+ breq se0 1 -> 16 (moved to 11)
+ st y+, data 2 -> 24, 25
+ mov data, fix 1 -> 33
+ ser data 1 -> 41
+ subi cnt, 1 1 -> 49
+ brcs overflow 1 -> 50
+
+layout of samples and operations:
+[##] = sample bit
+<##> = sample phase
+*##* = operation
+
+0: *00* [01] 02 03 04 <05> 06 07
+1: *08* [09] 10 11 12 <13> 14 15 *16*
+2: [17] 18 19 20 <21> 22 23
+3: *24* *25* [26] 27 28 29 <30> 31 32
+4: *33* [34] 35 36 37 <38> 39 40
+5: *41* [42] 43 44 45 <46> 47 48
+6: *49* *50* [51] 52 53 54 <55> 56 57 58
+7: [59] 60 61 62 <63> 64 65 66
+*****************************************************************************/
+
+/* we prefer positive expressions (do if condition) instead of negative
+ * (skip if condition), therefore use defines for skip instructions:
+ */
+#define ifioclr sbis
+#define ifioset sbic
+#define ifrclr sbrs
+#define ifrset sbrc
+
+/* The registers "fix" and "data" swap their meaning during the loop. Use
+ * defines to keep their name constant.
+ */
+#define fix x2
+#define data x1
+#undef phase /* phase has a default definition to x4 */
+#define phase x3
+
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG [sofError], YH, shift, x1, x2, x3, cnt, r0
+ push YL ;2 push only what is necessary to sync with edge ASAP
+ in YL, SREG ;1
+ push YL ;2
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS ;[0]
+ rjmp foundK ;[1]
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+
+foundK:
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 4 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push YH ;[2]
+ lds YL, usbInputBufOffset;[4]
+ clr YH ;[6]
+ subi YL, lo8(-(usbRxBuf));[7]
+ sbci YH, hi8(-(usbRxBuf));[8]
+
+ sbis USBIN, USBMINUS ;[9] we want two bits K [we want to sample at 8 + 4 - 1.5 = 10.5]
+ rjmp haveTwoBitsK ;[10]
+ pop YH ;[11] undo the push from before
+ rjmp waitForK ;[13] this was not the end of sync, retry
+haveTwoBitsK:
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+#define fix x2
+#define data x1
+
+ push shift ;[12]
+ push x1 ;[14]
+ push x2 ;[16]
+ ldi shift, 0x80 ;[18] prevent bit-unstuffing but init low bits to 0
+ ifioset USBIN, USBMINUS ;[19] [01] <--- bit 0 [10.5 + 8 = 18.5]
+ ori shift, 1<<0 ;[02]
+ push x3 ;[03]
+ push cnt ;[05]
+ push r0 ;[07]
+ ifioset USBIN, USBMINUS ;[09] <--- bit 1
+ ori shift, 1<<1 ;[10]
+ ser fix ;[11]
+ ldi cnt, USB_BUFSIZE ;[12]
+ mov data, shift ;[13]
+ lsl shift ;[14]
+ nop2 ;[15]
+ ifioset USBIN, USBMINUS ;[17] <--- bit 2
+ ori data, 3<<2 ;[18] store in bit 2 AND bit 3
+ eor shift, data ;[19] do nrzi decoding
+ andi data, 1<<3 ;[20]
+ in phase, USBIN ;[21] <- phase
+ brne jumpToEntryAfterSet ;[22] if USBMINS at bit 3 was 1
+ nop ;[23]
+ rjmp entryAfterClr ;[24]
+jumpToEntryAfterSet:
+ rjmp entryAfterSet ;[24]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+#undef fix
+#define fix x1
+#undef data
+#define data x2
+
+bit7IsSet:
+ ifrclr phase, USBMINUS ;[62] check phase only if D- changed
+ lpm ;[63]
+ in phase, USBIN ;[64] <- phase (one cycle too late)
+ ori shift, 1 << 7 ;[65]
+ nop ;[66]
+;;;;rjmp bit0AfterSet ; -> [00] == [67] moved block up to save jump
+bit0AfterSet:
+ eor fix, shift ;[00]
+#undef fix
+#define fix x2
+#undef data
+#define data x1 /* we now have result in data, fix is reset to 0xff */
+ ifioclr USBIN, USBMINUS ;[01] <--- sample 0
+ rjmp bit0IsClr ;[02]
+ andi shift, ~(7 << 0) ;[03]
+ breq unstuff0s ;[04]
+ in phase, USBIN ;[05] <- phase
+ rjmp bit1AfterSet ;[06]
+unstuff0s:
+ in phase, USBIN ;[06] <- phase (one cycle too late)
+ andi fix, ~(1 << 0) ;[07]
+ ifioclr USBIN, USBMINUS ;[00]
+ ifioset USBIN, USBPLUS ;[01]
+ rjmp bit0IsClr ;[02] executed if first expr false or second true
+se0AndStore: ; executed only if both bits 0
+ st y+, x1 ;[15/17] cycles after start of byte
+ rjmp se0 ;[17/19]
+
+bit0IsClr:
+ ifrset phase, USBMINUS ;[04] check phase only if D- changed
+ lpm ;[05]
+ in phase, USBIN ;[06] <- phase (one cycle too late)
+ ori shift, 1 << 0 ;[07]
+bit1AfterClr:
+ andi phase, USBMASK ;[08]
+ ifioset USBIN, USBMINUS ;[09] <--- sample 1
+ rjmp bit1IsSet ;[10]
+ breq se0AndStore ;[11] if D- was 0 in bits 0 AND 1 and D+ was 0 in between, we have SE0
+ andi shift, ~(7 << 1) ;[12]
+ in phase, USBIN ;[13] <- phase
+ breq unstuff1c ;[14]
+ rjmp bit2AfterClr ;[15]
+unstuff1c:
+ andi fix, ~(1 << 1) ;[16]
+ nop2 ;[08]
+ nop2 ;[10]
+bit1IsSet:
+ ifrclr phase, USBMINUS ;[12] check phase only if D- changed
+ lpm ;[13]
+ in phase, USBIN ;[14] <- phase (one cycle too late)
+ ori shift, 1 << 1 ;[15]
+ nop ;[16]
+bit2AfterSet:
+ ifioclr USBIN, USBMINUS ;[17] <--- sample 2
+ rjmp bit2IsClr ;[18]
+ andi shift, ~(7 << 2) ;[19]
+ breq unstuff2s ;[20]
+ in phase, USBIN ;[21] <- phase
+ rjmp bit3AfterSet ;[22]
+unstuff2s:
+ in phase, USBIN ;[22] <- phase (one cycle too late)
+ andi fix, ~(1 << 2) ;[23]
+ nop2 ;[16]
+ nop2 ;[18]
+bit2IsClr:
+ ifrset phase, USBMINUS ;[20] check phase only if D- changed
+ lpm ;[21]
+ in phase, USBIN ;[22] <- phase (one cycle too late)
+ ori shift, 1 << 2 ;[23]
+bit3AfterClr:
+ st y+, data ;[24]
+entryAfterClr:
+ ifioset USBIN, USBMINUS ;[26] <--- sample 3
+ rjmp bit3IsSet ;[27]
+ andi shift, ~(7 << 3) ;[28]
+ breq unstuff3c ;[29]
+ in phase, USBIN ;[30] <- phase
+ rjmp bit4AfterClr ;[31]
+unstuff3c:
+ in phase, USBIN ;[31] <- phase (one cycle too late)
+ andi fix, ~(1 << 3) ;[32]
+ nop2 ;[25]
+ nop2 ;[27]
+bit3IsSet:
+ ifrclr phase, USBMINUS ;[29] check phase only if D- changed
+ lpm ;[30]
+ in phase, USBIN ;[31] <- phase (one cycle too late)
+ ori shift, 1 << 3 ;[32]
+bit4AfterSet:
+ mov data, fix ;[33] undo this move by swapping defines
+#undef fix
+#define fix x1
+#undef data
+#define data x2
+ ifioclr USBIN, USBMINUS ;[34] <--- sample 4
+ rjmp bit4IsClr ;[35]
+ andi shift, ~(7 << 4) ;[36]
+ breq unstuff4s ;[37]
+ in phase, USBIN ;[38] <- phase
+ rjmp bit5AfterSet ;[39]
+unstuff4s:
+ in phase, USBIN ;[39] <- phase (one cycle too late)
+ andi fix, ~(1 << 4) ;[40]
+ nop2 ;[33]
+ nop2 ;[35]
+bit4IsClr:
+ ifrset phase, USBMINUS ;[37] check phase only if D- changed
+ lpm ;[38]
+ in phase, USBIN ;[39] <- phase (one cycle too late)
+ ori shift, 1 << 4 ;[40]
+bit5AfterClr:
+ ser data ;[41]
+ ifioset USBIN, USBMINUS ;[42] <--- sample 5
+ rjmp bit5IsSet ;[43]
+ andi shift, ~(7 << 5) ;[44]
+ breq unstuff5c ;[45]
+ in phase, USBIN ;[46] <- phase
+ rjmp bit6AfterClr ;[47]
+unstuff5c:
+ in phase, USBIN ;[47] <- phase (one cycle too late)
+ andi fix, ~(1 << 5) ;[48]
+ nop2 ;[41]
+ nop2 ;[43]
+bit5IsSet:
+ ifrclr phase, USBMINUS ;[45] check phase only if D- changed
+ lpm ;[46]
+ in phase, USBIN ;[47] <- phase (one cycle too late)
+ ori shift, 1 << 5 ;[48]
+bit6AfterSet:
+ subi cnt, 1 ;[49]
+ brcs jumpToOverflow ;[50]
+ ifioclr USBIN, USBMINUS ;[51] <--- sample 6
+ rjmp bit6IsClr ;[52]
+ andi shift, ~(3 << 6) ;[53]
+ cpi shift, 2 ;[54]
+ in phase, USBIN ;[55] <- phase
+ brlt unstuff6s ;[56]
+ rjmp bit7AfterSet ;[57]
+
+jumpToOverflow:
+ rjmp overflow
+
+unstuff6s:
+ andi fix, ~(1 << 6) ;[50]
+ lpm ;[51]
+bit6IsClr:
+ ifrset phase, USBMINUS ;[54] check phase only if D- changed
+ lpm ;[55]
+ in phase, USBIN ;[56] <- phase (one cycle too late)
+ ori shift, 1 << 6 ;[57]
+ nop ;[58]
+bit7AfterClr:
+ ifioset USBIN, USBMINUS ;[59] <--- sample 7
+ rjmp bit7IsSet ;[60]
+ andi shift, ~(1 << 7) ;[61]
+ cpi shift, 4 ;[62]
+ in phase, USBIN ;[63] <- phase
+ brlt unstuff7c ;[64]
+ rjmp bit0AfterClr ;[65] -> [00] == [67]
+unstuff7c:
+ andi fix, ~(1 << 7) ;[58]
+ nop ;[59]
+ rjmp bit7IsSet ;[60]
+
+bit7IsClr:
+ ifrset phase, USBMINUS ;[62] check phase only if D- changed
+ lpm ;[63]
+ in phase, USBIN ;[64] <- phase (one cycle too late)
+ ori shift, 1 << 7 ;[65]
+ nop ;[66]
+;;;;rjmp bit0AfterClr ; -> [00] == [67] moved block up to save jump
+bit0AfterClr:
+ eor fix, shift ;[00]
+#undef fix
+#define fix x2
+#undef data
+#define data x1 /* we now have result in data, fix is reset to 0xff */
+ ifioset USBIN, USBMINUS ;[01] <--- sample 0
+ rjmp bit0IsSet ;[02]
+ andi shift, ~(7 << 0) ;[03]
+ breq unstuff0c ;[04]
+ in phase, USBIN ;[05] <- phase
+ rjmp bit1AfterClr ;[06]
+unstuff0c:
+ in phase, USBIN ;[06] <- phase (one cycle too late)
+ andi fix, ~(1 << 0) ;[07]
+ ifioclr USBIN, USBMINUS ;[00]
+ ifioset USBIN, USBPLUS ;[01]
+ rjmp bit0IsSet ;[02] executed if first expr false or second true
+ rjmp se0AndStore ;[03] executed only if both bits 0
+bit0IsSet:
+ ifrclr phase, USBMINUS ;[04] check phase only if D- changed
+ lpm ;[05]
+ in phase, USBIN ;[06] <- phase (one cycle too late)
+ ori shift, 1 << 0 ;[07]
+bit1AfterSet:
+ andi shift, ~(7 << 1) ;[08] compensated by "ori shift, 1<<1" if bit1IsClr
+ ifioclr USBIN, USBMINUS ;[09] <--- sample 1
+ rjmp bit1IsClr ;[10]
+ breq unstuff1s ;[11]
+ nop2 ;[12] do not check for SE0 if bit 0 was 1
+ in phase, USBIN ;[14] <- phase (one cycle too late)
+ rjmp bit2AfterSet ;[15]
+unstuff1s:
+ in phase, USBIN ;[13] <- phase
+ andi fix, ~(1 << 1) ;[14]
+ lpm ;[07]
+ nop2 ;[10]
+bit1IsClr:
+ ifrset phase, USBMINUS ;[12] check phase only if D- changed
+ lpm ;[13]
+ in phase, USBIN ;[14] <- phase (one cycle too late)
+ ori shift, 1 << 1 ;[15]
+ nop ;[16]
+bit2AfterClr:
+ ifioset USBIN, USBMINUS ;[17] <--- sample 2
+ rjmp bit2IsSet ;[18]
+ andi shift, ~(7 << 2) ;[19]
+ breq unstuff2c ;[20]
+ in phase, USBIN ;[21] <- phase
+ rjmp bit3AfterClr ;[22]
+unstuff2c:
+ in phase, USBIN ;[22] <- phase (one cycle too late)
+ andi fix, ~(1 << 2) ;[23]
+ nop2 ;[16]
+ nop2 ;[18]
+bit2IsSet:
+ ifrclr phase, USBMINUS ;[20] check phase only if D- changed
+ lpm ;[21]
+ in phase, USBIN ;[22] <- phase (one cycle too late)
+ ori shift, 1 << 2 ;[23]
+bit3AfterSet:
+ st y+, data ;[24]
+entryAfterSet:
+ ifioclr USBIN, USBMINUS ;[26] <--- sample 3
+ rjmp bit3IsClr ;[27]
+ andi shift, ~(7 << 3) ;[28]
+ breq unstuff3s ;[29]
+ in phase, USBIN ;[30] <- phase
+ rjmp bit4AfterSet ;[31]
+unstuff3s:
+ in phase, USBIN ;[31] <- phase (one cycle too late)
+ andi fix, ~(1 << 3) ;[32]
+ nop2 ;[25]
+ nop2 ;[27]
+bit3IsClr:
+ ifrset phase, USBMINUS ;[29] check phase only if D- changed
+ lpm ;[30]
+ in phase, USBIN ;[31] <- phase (one cycle too late)
+ ori shift, 1 << 3 ;[32]
+bit4AfterClr:
+ mov data, fix ;[33] undo this move by swapping defines
+#undef fix
+#define fix x1
+#undef data
+#define data x2
+ ifioset USBIN, USBMINUS ;[34] <--- sample 4
+ rjmp bit4IsSet ;[35]
+ andi shift, ~(7 << 4) ;[36]
+ breq unstuff4c ;[37]
+ in phase, USBIN ;[38] <- phase
+ rjmp bit5AfterClr ;[39]
+unstuff4c:
+ in phase, USBIN ;[39] <- phase (one cycle too late)
+ andi fix, ~(1 << 4) ;[40]
+ nop2 ;[33]
+ nop2 ;[35]
+bit4IsSet:
+ ifrclr phase, USBMINUS ;[37] check phase only if D- changed
+ lpm ;[38]
+ in phase, USBIN ;[39] <- phase (one cycle too late)
+ ori shift, 1 << 4 ;[40]
+bit5AfterSet:
+ ser data ;[41]
+ ifioclr USBIN, USBMINUS ;[42] <--- sample 5
+ rjmp bit5IsClr ;[43]
+ andi shift, ~(7 << 5) ;[44]
+ breq unstuff5s ;[45]
+ in phase, USBIN ;[46] <- phase
+ rjmp bit6AfterSet ;[47]
+unstuff5s:
+ in phase, USBIN ;[47] <- phase (one cycle too late)
+ andi fix, ~(1 << 5) ;[48]
+ nop2 ;[41]
+ nop2 ;[43]
+bit5IsClr:
+ ifrset phase, USBMINUS ;[45] check phase only if D- changed
+ lpm ;[46]
+ in phase, USBIN ;[47] <- phase (one cycle too late)
+ ori shift, 1 << 5 ;[48]
+bit6AfterClr:
+ subi cnt, 1 ;[49]
+ brcs overflow ;[50]
+ ifioset USBIN, USBMINUS ;[51] <--- sample 6
+ rjmp bit6IsSet ;[52]
+ andi shift, ~(3 << 6) ;[53]
+ cpi shift, 2 ;[54]
+ in phase, USBIN ;[55] <- phase
+ brlt unstuff6c ;[56]
+ rjmp bit7AfterClr ;[57]
+unstuff6c:
+ andi fix, ~(1 << 6) ;[50]
+ lpm ;[51]
+bit6IsSet:
+ ifrclr phase, USBMINUS ;[54] check phase only if D- changed
+ lpm ;[55]
+ in phase, USBIN ;[56] <- phase (one cycle too late)
+ ori shift, 1 << 6 ;[57]
+bit7AfterSet:
+ ifioclr USBIN, USBMINUS ;[59] <--- sample 7
+ rjmp bit7IsClr ;[60]
+ andi shift, ~(1 << 7) ;[61]
+ cpi shift, 4 ;[62]
+ in phase, USBIN ;[63] <- phase
+ brlt unstuff7s ;[64]
+ rjmp bit0AfterSet ;[65] -> [00] == [67]
+unstuff7s:
+ andi fix, ~(1 << 7) ;[58]
+ nop ;[59]
+ rjmp bit7IsClr ;[60]
+
+macro POP_STANDARD ; 14 cycles
+ pop r0
+ pop cnt
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ endm
+macro POP_RETI ; 5 cycles
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+;----------------------------------------------------------------------------
+; Transmitting data
+;----------------------------------------------------------------------------
+
+txByteLoop:
+txBitloop:
+stuffN1Delay: ; [03]
+ ror shift ;[-5] [11] [63]
+ brcc doExorN1 ;[-4] [64]
+ subi x3, 1 ;[-3]
+ brne commonN1 ;[-2]
+ lsl shift ;[-1] compensate ror after rjmp stuffDelay
+ nop ;[00] stuffing consists of just waiting 8 cycles
+ rjmp stuffN1Delay ;[01] after ror, C bit is reliably clear
+
+sendNakAndReti:
+ ldi cnt, USBPID_NAK ;[-19]
+ rjmp sendCntAndReti ;[-18]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov r0, cnt ;[-16]
+ ldi YL, 0 ;[-15] R0 address is 0
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1) or USBOUT = 0x01
+; K = (D+ = 1), (D- = 0) or USBOUT = 0x02
+; Spec allows 7.5 bit times from EOP to SOP for replies (= 60 cycles)
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte
+;uses: x1...x3, shift, cnt, Y [x1 = mirror USBOUT, x2 = USBMASK, x3 = bitstuff cnt]
+;Numbers in brackets are time since first bit of sync pattern is sent (start of instruction)
+usbSendAndReti:
+ in x2, USBDDR ;[-10] 10 cycles until SOP
+ ori x2, USBMASK ;[-9]
+ sbi USBOUT, USBMINUS ;[-8] prepare idle state; D+ and D- must have been 0 (no pullups)
+ out USBDDR, x2 ;[-6] <--- acquire bus
+ in x1, USBOUT ;[-5] port mirror for tx loop
+ ldi shift, 0x40 ;[-4] sync byte is first byte sent (we enter loop after ror)
+ ldi x2, USBMASK ;[-3]
+doExorN1:
+ eor x1, x2 ;[-2] [06] [62]
+ ldi x3, 6 ;[-1] [07] [63]
+commonN1:
+stuffN2Delay:
+ out USBOUT, x1 ;[00] [08] [64] <--- set bit
+ ror shift ;[01]
+ brcc doExorN2 ;[02]
+ subi x3, 1 ;[03]
+ brne commonN2 ;[04]
+ lsl shift ;[05] compensate ror after rjmp stuffDelay
+ rjmp stuffN2Delay ;[06] after ror, C bit is reliably clear
+doExorN2:
+ eor x1, x2 ;[04] [12]
+ ldi x3, 6 ;[05] [13]
+commonN2:
+ nop2 ;[06] [14]
+ subi cnt, 171 ;[08] [16] trick: (3 * 171) & 0xff = 1
+ out USBOUT, x1 ;[09] [17] <--- set bit
+ brcs txBitloop ;[10] [27] [44]
+
+stuff6Delay:
+ ror shift ;[45] [53]
+ brcc doExor6 ;[46]
+ subi x3, 1 ;[47]
+ brne common6 ;[48]
+ lsl shift ;[49] compensate ror after rjmp stuffDelay
+ nop ;[50] stuffing consists of just waiting 8 cycles
+ rjmp stuff6Delay ;[51] after ror, C bit is reliably clear
+doExor6:
+ eor x1, x2 ;[48] [56]
+ ldi x3, 6 ;[49]
+common6:
+stuff7Delay:
+ ror shift ;[50] [58]
+ out USBOUT, x1 ;[51] <--- set bit
+ brcc doExor7 ;[52]
+ subi x3, 1 ;[53]
+ brne common7 ;[54]
+ lsl shift ;[55] compensate ror after rjmp stuffDelay
+ rjmp stuff7Delay ;[56] after ror, C bit is reliably clear
+doExor7:
+ eor x1, x2 ;[54] [62]
+ ldi x3, 6 ;[55]
+common7:
+ ld shift, y+ ;[56]
+ nop ;[58]
+ tst cnt ;[59]
+ out USBOUT, x1 ;[60] [00]<--- set bit
+ brne txByteLoop ;[61] [01]
+;make SE0:
+ cbr x1, USBMASK ;[02] prepare SE0 [spec says EOP may be 15 to 18 cycles]
+ lds x2, usbNewDeviceAddr;[03]
+ lsl x2 ;[05] we compare with left shifted address
+ subi YL, 2 + 0 ;[06] Only assign address on data packets, not ACK/NAK in r0
+ sbci YH, 0 ;[07]
+ out USBOUT, x1 ;[00] <-- out SE0 -- from now 2 bits = 16 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[01]
+ sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[03] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[04]
+ ori x1, USBIDLE ;[05]
+ in x2, USBDDR ;[06]
+ cbr x2, USBMASK ;[07] set both pins to input
+ mov x3, x1 ;[08]
+ cbr x3, USBMASK ;[09] configure no pullup on both pins
+ lpm ;[10]
+ lpm ;[13]
+ out USBOUT, x1 ;[16] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[17] <-- release bus now
+ out USBOUT, x3 ;[18] <-- ensure no pull-up resistors are active
+ rjmp doReturn
+
+
+
+/*****************************************************************************
+The following PHP script generates a code skeleton for the receiver routine:
+
+<?php
+
+function printCmdBuffer($thisBit)
+{
+global $cycle;
+
+ $nextBit = ($thisBit + 1) % 8;
+ $s = ob_get_contents();
+ ob_end_clean();
+ $s = str_replace("#", $thisBit, $s);
+ $s = str_replace("@", $nextBit, $s);
+ $lines = explode("\n", $s);
+ for($i = 0; $i < count($lines); $i++){
+ $s = $lines[$i];
+ if(ereg("\\[([0-9-][0-9])\\]", $s, $regs)){
+ $c = $cycle + (int)$regs[1];
+ $s = ereg_replace("\\[[0-9-][0-9]\\]", sprintf("[%02d]", $c), $s);
+ }
+ if(strlen($s) > 0)
+ echo "$s\n";
+ }
+}
+
+function printBit($isAfterSet, $bitNum)
+{
+ ob_start();
+ if($isAfterSet){
+?>
+ ifioclr USBIN, USBMINUS ;[00] <--- sample
+ rjmp bit#IsClr ;[01]
+ andi shift, ~(7 << #) ;[02]
+ breq unstuff#s ;[03]
+ in phase, USBIN ;[04] <- phase
+ rjmp bit@AfterSet ;[05]
+unstuff#s:
+ in phase, USBIN ;[05] <- phase (one cycle too late)
+ andi fix, ~(1 << #) ;[06]
+ nop2 ;[-1]
+ nop2 ;[01]
+bit#IsClr:
+ ifrset phase, USBMINUS ;[03] check phase only if D- changed
+ lpm ;[04]
+ in phase, USBIN ;[05] <- phase (one cycle too late)
+ ori shift, 1 << # ;[06]
+<?php
+ }else{
+?>
+ ifioset USBIN, USBMINUS ;[00] <--- sample
+ rjmp bit#IsSet ;[01]
+ andi shift, ~(7 << #) ;[02]
+ breq unstuff#c ;[03]
+ in phase, USBIN ;[04] <- phase
+ rjmp bit@AfterClr ;[05]
+unstuff#c:
+ in phase, USBIN ;[05] <- phase (one cycle too late)
+ andi fix, ~(1 << #) ;[06]
+ nop2 ;[-1]
+ nop2 ;[01]
+bit#IsSet:
+ ifrclr phase, USBMINUS ;[03] check phase only if D- changed
+ lpm ;[04]
+ in phase, USBIN ;[05] <- phase (one cycle too late)
+ ori shift, 1 << # ;[06]
+<?php
+ }
+ printCmdBuffer($bitNum);
+}
+
+$bitStartCycles = array(1, 9, 17, 26, 34, 42, 51, 59);
+for($i = 0; $i < 16; $i++){
+ $bit = $i % 8;
+ $emitClrCode = ($i + (int)($i / 8)) % 2;
+ $cycle = $bitStartCycles[$bit];
+ if($emitClrCode){
+ printf("bit%dAfterClr:\n", $bit);
+ }else{
+ printf("bit%dAfterSet:\n", $bit);
+ }
+ ob_start();
+ echo " ***** ;[-1]\n";
+ printCmdBuffer($bit);
+ printBit(!$emitClrCode, $bit);
+ if($i == 7)
+ echo "\n";
+}
+
+?>
+*****************************************************************************/
--- /dev/null
+/* Name: usbdrvasm15.inc
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: contributed by V. Bosch
+ * Creation Date: 2007-08-06
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm15.inc 740 2009-04-13 18:23:31Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 15 MHz version of the asssembler part of the USB driver. It
+requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+
+;----------------------------------------------------------------------------
+; order of registers pushed:
+; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4
+;----------------------------------------------------------------------------
+USB_INTR_VECTOR:
+ push YL ;2 push only what is necessary to sync with edge ASAP
+ in YL, SREG ;1
+ push YL ;2
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;
+; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+; sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+;-------------------------------------------------------------------------------
+; The following code results in a sampling window of < 1/4 bit
+; which meets the spec.
+;-------------------------------------------------------------------------------
+waitForK: ;-
+ sbis USBIN, USBMINUS ;1 [00] <-- sample
+ rjmp foundK ;2 [01]
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+ sbis USBIN, USBMINUS ; <-- sample
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+;------------------------------------------------------------------------------
+; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for
+; center sampling]
+; we have 1 bit time for setup purposes, then sample again.
+; Numbers in brackets are cycles from center of first sync (double K)
+; bit after the instruction
+;------------------------------------------------------------------------------
+foundK: ;- [02]
+ lds YL, usbInputBufOffset;2 [03+04] tx loop
+ push YH ;2 [05+06]
+ clr YH ;1 [07]
+ subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init]
+ push shift ;2 [10+11]
+ ser shift ;1 [12]
+ sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early)
+ rjmp haveTwoBitsK ;2 [00] [14]
+ pop shift ;2 [15+16] undo the push from before
+ pop YH ;2 [17+18] undo the push from before
+ rjmp waitForK ;2 [19+20] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 20 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK: ;- [01]
+ push x1 ;2 [02+03]
+ push x2 ;2 [04+05]
+ push x3 ;2 [06+07]
+ push bitcnt ;2 [08+09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 0
+ bst x1, USBMINUS ;1 [01]
+ bld shift, 0 ;1 [02]
+ push cnt ;2 [03+04]
+ ldi cnt, USB_BUFSIZE ;1 [05]
+ push x4 ;2 [06+07] tx loop
+ rjmp rxLoop ;2 [08]
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+unstuff0: ;- [07] (branch taken)
+ andi x3, ~0x01 ;1 [08]
+ mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit
+ in x2, USBIN ;1 [00] [10] <-- sample bit 1 again
+ andi x2, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 1
+ ori shift, 0x01 ;1 [03] 0b00000001
+ nop ;1 [04]
+ rjmp didUnstuff0 ;2 [05]
+;-----------------------------------------------------
+unstuff1: ;- [05] (branch taken)
+ mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit
+ andi x3, ~0x02 ;1 [07]
+ ori shift, 0x02 ;1 [08] 0b00000010
+ nop ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 2 again
+ andi x1, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 2
+ rjmp didUnstuff1 ;2 [03]
+;-----------------------------------------------------
+unstuff2: ;- [05] (branch taken)
+ andi x3, ~0x04 ;1 [06]
+ ori shift, 0x04 ;1 [07] 0b00000100
+ mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit
+ nop ;1 [09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 3
+ andi x2, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 3
+ rjmp didUnstuff2 ;2 [03]
+;-----------------------------------------------------
+unstuff3: ;- [00] [10] (branch taken)
+ in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late
+ andi x2, USBMASK ;1 [02]
+ breq se0Hop ;1 [03] SE0 check for stuffed bit 3
+ andi x3, ~0x08 ;1 [04]
+ ori shift, 0x08 ;1 [05] 0b00001000
+ rjmp didUnstuff3 ;2 [06]
+;----------------------------------------------------------------------------
+; extra jobs done during bit interval:
+;
+; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs],
+; overflow check, jump to the head of rxLoop
+; bit 1: SE0 check
+; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long]
+; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long]
+; bit 4: SE0 check, none
+; bit 5: SE0 check, none
+; bit 6: SE0 check, none
+; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others
+;----------------------------------------------------------------------------
+rxLoop: ;- [09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed)
+ andi x2, USBMASK ;1 [01]
+ brne SkipSe0Hop ;1 [02]
+se0Hop: ;- [02]
+ rjmp se0 ;2 [03] SE0 check for bit 1
+SkipSe0Hop: ;- [03]
+ ser x3 ;1 [04]
+ andi shift, 0xf9 ;1 [05] 0b11111001
+ breq unstuff0 ;1 [06]
+didUnstuff0: ;- [06]
+ eor x1, x2 ;1 [07]
+ bst x1, USBMINUS ;1 [08]
+ bld shift, 1 ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed)
+ andi x1, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 2
+ andi shift, 0xf3 ;1 [03] 0b11110011
+ breq unstuff1 ;1 [04] do remaining work for bit 1
+didUnstuff1: ;- [04]
+ eor x2, x1 ;1 [05]
+ bst x2, USBMINUS ;1 [06]
+ bld shift, 2 ;1 [07]
+ nop2 ;2 [08+09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed)
+ andi x2, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 3
+ andi shift, 0xe7 ;1 [03] 0b11100111
+ breq unstuff2 ;1 [04]
+didUnstuff2: ;- [04]
+ eor x1, x2 ;1 [05]
+ bst x1, USBMINUS ;1 [06]
+ bld shift, 3 ;1 [07]
+didUnstuff3: ;- [07]
+ andi shift, 0xcf ;1 [08] 0b11001111
+ breq unstuff3 ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 4
+ andi x1, USBMASK ;1 [01]
+ breq se0Hop ;1 [02] SE0 check for bit 4
+ eor x2, x1 ;1 [03]
+ bst x2, USBMINUS ;1 [04]
+ bld shift, 4 ;1 [05]
+didUnstuff4: ;- [05]
+ andi shift, 0x9f ;1 [06] 0b10011111
+ breq unstuff4 ;1 [07]
+ nop2 ;2 [08+09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 5
+ andi x2, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for bit 5
+ eor x1, x2 ;1 [03]
+ bst x1, USBMINUS ;1 [04]
+ bld shift, 5 ;1 [05]
+didUnstuff5: ;- [05]
+ andi shift, 0x3f ;1 [06] 0b00111111
+ breq unstuff5 ;1 [07]
+ nop2 ;2 [08+09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 6
+ andi x1, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for bit 6
+ eor x2, x1 ;1 [03]
+ bst x2, USBMINUS ;1 [04]
+ bld shift, 6 ;1 [05]
+didUnstuff6: ;- [05]
+ cpi shift, 0x02 ;1 [06] 0b00000010
+ brlo unstuff6 ;1 [07]
+ nop2 ;2 [08+09]
+ in x2, USBIN ;1 [00] [10] <-- sample bit 7
+ andi x2, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for bit 7
+ eor x1, x2 ;1 [03]
+ bst x1, USBMINUS ;1 [04]
+ bld shift, 7 ;1 [05]
+didUnstuff7: ;- [05]
+ cpi shift, 0x04 ;1 [06] 0b00000100
+ brlo unstuff7 ;1 [07]
+ eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others
+ nop ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample bit 0
+ st y+, x3 ;2 [01+02] store data
+ eor x2, x1 ;1 [03]
+ bst x2, USBMINUS ;1 [04]
+ bld shift, 0 ;1 [05]
+ subi cnt, 1 ;1 [06]
+ brcs overflow ;1 [07]
+ rjmp rxLoop ;2 [08]
+;-----------------------------------------------------
+unstuff4: ;- [08]
+ andi x3, ~0x10 ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4
+ andi x1, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for stuffed bit 4
+ ori shift, 0x10 ;1 [03]
+ rjmp didUnstuff4 ;2 [04]
+;-----------------------------------------------------
+unstuff5: ;- [08]
+ ori shift, 0x20 ;1 [09]
+ in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5
+ andi x2, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for stuffed bit 5
+ andi x3, ~0x20 ;1 [03]
+ rjmp didUnstuff5 ;2 [04]
+;-----------------------------------------------------
+unstuff6: ;- [08]
+ andi x3, ~0x40 ;1 [09]
+ in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6
+ andi x1, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for stuffed bit 6
+ ori shift, 0x40 ;1 [03]
+ rjmp didUnstuff6 ;2 [04]
+;-----------------------------------------------------
+unstuff7: ;- [08]
+ andi x3, ~0x80 ;1 [09]
+ in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7
+ andi x2, USBMASK ;1 [01]
+ breq se0 ;1 [02] SE0 check for stuffed bit 7
+ ori shift, 0x80 ;1 [03]
+ rjmp didUnstuff7 ;2 [04]
+
+macro POP_STANDARD ; 16 cycles
+ pop x4
+ pop cnt
+ pop bitcnt
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ endm
+macro POP_RETI ; 5 cycles
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+;---------------------------------------------------------------------------
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+;---------------------------------------------------------------------------
+bitstuffN: ;- [04]
+ eor x1, x4 ;1 [05]
+ clr x2 ;1 [06]
+ nop ;1 [07]
+ rjmp didStuffN ;1 [08]
+;---------------------------------------------------------------------------
+bitstuff6: ;- [04]
+ eor x1, x4 ;1 [05]
+ clr x2 ;1 [06]
+ rjmp didStuff6 ;1 [07]
+;---------------------------------------------------------------------------
+bitstuff7: ;- [02]
+ eor x1, x4 ;1 [03]
+ clr x2 ;1 [06]
+ nop ;1 [05]
+ rjmp didStuff7 ;1 [06]
+;---------------------------------------------------------------------------
+sendNakAndReti: ;- [-19]
+ ldi x3, USBPID_NAK ;1 [-18]
+ rjmp sendX3AndReti ;1 [-17]
+;---------------------------------------------------------------------------
+sendAckAndReti: ;- [-17]
+ ldi cnt, USBPID_ACK ;1 [-16]
+sendCntAndReti: ;- [-16]
+ mov x3, cnt ;1 [-15]
+sendX3AndReti: ;- [-15]
+ ldi YL, 20 ;1 [-14] x3==r20 address is 20
+ ldi YH, 0 ;1 [-13]
+ ldi cnt, 2 ;1 [-12]
+; rjmp usbSendAndReti fallthrough
+;---------------------------------------------------------------------------
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, btcnt, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+;We need not to match the transfer rate exactly because the spec demands
+;only 1.5% precision anyway.
+usbSendAndReti: ;- [-13] 13 cycles until SOP
+ in x2, USBDDR ;1 [-12]
+ ori x2, USBMASK ;1 [-11]
+ sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;1 [-08] port mirror for tx loop
+ out USBDDR, x2 ;1 [-07] <- acquire bus
+ ; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;1 [-06] exor mask
+ ldi shift, 0x80 ;1 [-05] sync byte is first byte sent
+ ldi bitcnt, 6 ;1 [-04]
+txBitLoop: ;- [-04] [06]
+ sbrs shift, 0 ;1 [-03] [07]
+ eor x1, x4 ;1 [-02] [08]
+ ror shift ;1 [-01] [09]
+didStuffN: ;- [09]
+ out USBOUT, x1 ;1 [00] [10] <-- out N
+ ror x2 ;1 [01]
+ cpi x2, 0xfc ;1 [02]
+ brcc bitstuffN ;1 [03]
+ dec bitcnt ;1 [04]
+ brne txBitLoop ;1 [05]
+ sbrs shift, 0 ;1 [06]
+ eor x1, x4 ;1 [07]
+ ror shift ;1 [08]
+didStuff6: ;- [08]
+ nop ;1 [09]
+ out USBOUT, x1 ;1 [00] [10] <-- out 6
+ ror x2 ;1 [01]
+ cpi x2, 0xfc ;1 [02]
+ brcc bitstuff6 ;1 [03]
+ sbrs shift, 0 ;1 [04]
+ eor x1, x4 ;1 [05]
+ ror shift ;1 [06]
+ ror x2 ;1 [07]
+didStuff7: ;- [07]
+ ldi bitcnt, 6 ;1 [08]
+ cpi x2, 0xfc ;1 [09]
+ out USBOUT, x1 ;1 [00] [10] <-- out 7
+ brcc bitstuff7 ;1 [01]
+ ld shift, y+ ;2 [02+03]
+ dec cnt ;1 [04]
+ brne txBitLoop ;1 [05]
+makeSE0:
+ cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles]
+ lds x2, usbNewDeviceAddr;2 [07+08]
+ lsl x2 ;1 [09] we compare with left shifted address
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle
+ subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;1 [02]
+ breq skipAddrAssign ;1 [03]
+ sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer
+;----------------------------------------------------------------------------
+;end of usbDeviceAddress transfer
+skipAddrAssign: ;- [03/04]
+ ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [05] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;1 [06]
+ ori x1, USBIDLE ;1 [07]
+ in x2, USBDDR ;1 [08]
+ cbr x2, USBMASK ;1 [09] set both pins to input
+ mov x3, x1 ;1 [10]
+ cbr x3, USBMASK ;1 [11] configure no pullup on both pins
+ ldi x4, 3 ;1 [12]
+se0Delay: ;- [12] [15]
+ dec x4 ;1 [13] [16]
+ brne se0Delay ;1 [14] [17]
+ nop2 ;2 [18+19]
+ out USBOUT, x1 ;1 [20] <--out J (idle) -- end of SE0 (EOP sig.)
+ out USBDDR, x2 ;1 [21] <--release bus now
+ out USBOUT, x3 ;1 [22] <--ensure no pull-up resistors are active
+ rjmp doReturn ;1 [23]
+;---------------------------------------------------------------------------
--- /dev/null
+/* Name: usbdrvasm16.inc
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-06-15
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm16.inc 760 2009-08-09 18:59:43Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 16 MHz version of the asssembler part of the USB driver. It
+requires a 16 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 16 MHz -> 10.6666666 cycles per bit, 85.333333333 cycles per byte
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
+ push YL ;[-25] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;[-23]
+ push YL ;[-22]
+ push YH ;[-20]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-15]
+ rjmp foundK ;[-14]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK: ;[-12]
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push bitcnt ;[-12]
+; [---] ;[-11]
+ lds YL, usbInputBufOffset;[-10]
+; [---] ;[-9]
+ clr YH ;[-8]
+ subi YL, lo8(-(usbRxBuf));[-7] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-6] [rx loop init]
+ push shift ;[-5]
+; [---] ;[-4]
+ ldi bitcnt, 0x55 ;[-3] [rx loop init]
+ sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
+ rjmp haveTwoBitsK ;[-1]
+ pop shift ;[0] undo the push from before
+ pop bitcnt ;[2] undo the push from before
+ rjmp waitForK ;[4] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 21 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK:
+ push x1 ;[1]
+ push x2 ;[3]
+ push x3 ;[5]
+ ldi shift, 0 ;[7]
+ ldi x3, 1<<4 ;[8] [rx loop init] first sample is inverse bit, compensate that
+ push x4 ;[9] == leap
+
+ in x1, USBIN ;[11] <-- sample bit 0
+ andi x1, USBMASK ;[12]
+ bst x1, USBMINUS ;[13]
+ bld shift, 7 ;[14]
+ push cnt ;[15]
+ ldi leap, 0 ;[17] [rx loop init]
+ ldi cnt, USB_BUFSIZE;[18] [rx loop init]
+ rjmp rxbit1 ;[19] arrives at [21]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+
+; duration of unstuffing code should be 10.66666667 cycles. We adjust "leap"
+; accordingly to approximate this value in the long run.
+
+unstuff6:
+ andi x2, USBMASK ;[03]
+ ori x3, 1<<6 ;[04] will not be shifted any more
+ andi shift, ~0x80;[05]
+ mov x1, x2 ;[06] sampled bit 7 is actually re-sampled bit 6
+ subi leap, -1 ;[07] total duration = 11 bits -> subtract 1/3
+ rjmp didUnstuff6 ;[08]
+
+unstuff7:
+ ori x3, 1<<7 ;[09] will not be shifted any more
+ in x2, USBIN ;[00] [10] re-sample bit 7
+ andi x2, USBMASK ;[01]
+ andi shift, ~0x80;[02]
+ subi leap, 2 ;[03] total duration = 10 bits -> add 1/3
+ rjmp didUnstuff7 ;[04]
+
+unstuffEven:
+ ori x3, 1<<6 ;[09] will be shifted right 6 times for bit 0
+ in x1, USBIN ;[00] [10]
+ andi shift, ~0x80;[01]
+ andi x1, USBMASK ;[02]
+ breq se0 ;[03]
+ subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3
+ nop2 ;[05]
+ rjmp didUnstuffE ;[06]
+
+unstuffOdd:
+ ori x3, 1<<5 ;[09] will be shifted right 4 times for bit 1
+ in x2, USBIN ;[00] [10]
+ andi shift, ~0x80;[01]
+ andi x2, USBMASK ;[02]
+ breq se0 ;[03]
+ subi leap, -1 ;[04] total duration = 11 bits -> subtract 1/3
+ nop2 ;[05]
+ rjmp didUnstuffO ;[06]
+
+rxByteLoop:
+ andi x1, USBMASK ;[03]
+ eor x2, x1 ;[04]
+ subi leap, 1 ;[05]
+ brpl skipLeap ;[06]
+ subi leap, -3 ;1 one leap cycle every 3rd byte -> 85 + 1/3 cycles per byte
+ nop ;1
+skipLeap:
+ subi x2, 1 ;[08]
+ ror shift ;[09]
+didUnstuff6:
+ cpi shift, 0xfc ;[10]
+ in x2, USBIN ;[00] [11] <-- sample bit 7
+ brcc unstuff6 ;[01]
+ andi x2, USBMASK ;[02]
+ eor x1, x2 ;[03]
+ subi x1, 1 ;[04]
+ ror shift ;[05]
+didUnstuff7:
+ cpi shift, 0xfc ;[06]
+ brcc unstuff7 ;[07]
+ eor x3, shift ;[08] reconstruct: x3 is 1 at bit locations we changed, 0 at others
+ st y+, x3 ;[09] store data
+rxBitLoop:
+ in x1, USBIN ;[00] [11] <-- sample bit 0/2/4
+ andi x1, USBMASK ;[01]
+ eor x2, x1 ;[02]
+ andi x3, 0x3f ;[03] topmost two bits reserved for 6 and 7
+ subi x2, 1 ;[04]
+ ror shift ;[05]
+ cpi shift, 0xfc ;[06]
+ brcc unstuffEven ;[07]
+didUnstuffE:
+ lsr x3 ;[08]
+ lsr x3 ;[09]
+rxbit1:
+ in x2, USBIN ;[00] [10] <-- sample bit 1/3/5
+ andi x2, USBMASK ;[01]
+ breq se0 ;[02]
+ eor x1, x2 ;[03]
+ subi x1, 1 ;[04]
+ ror shift ;[05]
+ cpi shift, 0xfc ;[06]
+ brcc unstuffOdd ;[07]
+didUnstuffO:
+ subi bitcnt, 0xab;[08] == addi 0x55, 0x55 = 0x100/3
+ brcs rxBitLoop ;[09]
+
+ subi cnt, 1 ;[10]
+ in x1, USBIN ;[00] [11] <-- sample bit 6
+ brcc rxByteLoop ;[01]
+ rjmp overflow
+
+macro POP_STANDARD ; 14 cycles
+ pop cnt
+ pop x4
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop bitcnt
+ endm
+macro POP_RETI ; 7 cycles
+ pop YH
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+
+bitstuffN:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6]
+ nop2 ;[7]
+ nop ;[9]
+ out USBOUT, x1 ;[10] <-- out
+ rjmp didStuffN ;[0]
+
+bitstuff6:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6] Carry is zero due to brcc
+ rol shift ;[7] compensate for ror shift at branch destination
+ rjmp didStuff6 ;[8]
+
+bitstuff7:
+ ldi x2, 0 ;[2] Carry is zero due to brcc
+ rjmp didStuff7 ;[3]
+
+
+sendNakAndReti:
+ ldi x3, USBPID_NAK ;[-18]
+ rjmp sendX3AndReti ;[-17]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov x3, cnt ;[-16]
+sendX3AndReti:
+ ldi YL, 20 ;[-15] x3==r20 address is 20
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, btcnt, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+;We don't match the transfer rate exactly (don't insert leap cycles every third
+;byte) because the spec demands only 1.5% precision anyway.
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-6] exor mask
+ ldi shift, 0x80 ;[-5] sync byte is first byte sent
+txByteLoop:
+ ldi bitcnt, 0x35 ;[-4] [6] binary 0011 0101
+txBitLoop:
+ sbrs shift, 0 ;[-3] [7]
+ eor x1, x4 ;[-2] [8]
+ out USBOUT, x1 ;[-1] [9] <-- out N
+ ror shift ;[0] [10]
+ ror x2 ;[1]
+didStuffN:
+ cpi x2, 0xfc ;[2]
+ brcc bitstuffN ;[3]
+ lsr bitcnt ;[4]
+ brcc txBitLoop ;[5]
+ brne txBitLoop ;[6]
+
+ sbrs shift, 0 ;[7]
+ eor x1, x4 ;[8]
+didStuff6:
+ out USBOUT, x1 ;[-1] [9] <-- out 6
+ ror shift ;[0] [10]
+ ror x2 ;[1]
+ cpi x2, 0xfc ;[2]
+ brcc bitstuff6 ;[3]
+ ror shift ;[4]
+didStuff7:
+ ror x2 ;[5]
+ sbrs x2, 7 ;[6]
+ eor x1, x4 ;[7]
+ nop ;[8]
+ cpi x2, 0xfc ;[9]
+ out USBOUT, x1 ;[-1][10] <-- out 7
+ brcc bitstuff7 ;[0] [11]
+ ld shift, y+ ;[1]
+ dec cnt ;[3]
+ brne txByteLoop ;[4]
+;make SE0:
+ cbr x1, USBMASK ;[5] prepare SE0 [spec says EOP may be 21 to 25 cycles]
+ lds x2, usbNewDeviceAddr;[6]
+ lsl x2 ;[8] we compare with left shifted address
+ subi YL, 20 + 2 ;[9] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;[10]
+ out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[0]
+ sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[2] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[3]
+ ori x1, USBIDLE ;[4]
+ in x2, USBDDR ;[5]
+ cbr x2, USBMASK ;[6] set both pins to input
+ mov x3, x1 ;[7]
+ cbr x3, USBMASK ;[8] configure no pullup on both pins
+ ldi x4, 4 ;[9]
+se0Delay:
+ dec x4 ;[10] [13] [16] [19]
+ brne se0Delay ;[11] [14] [17] [20]
+ out USBOUT, x1 ;[21] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[22] <-- release bus now
+ out USBOUT, x3 ;[23] <-- ensure no pull-up resistors are active
+ rjmp doReturn
--- /dev/null
+/* Name: usbdrvasm165.inc
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2007-04-22
+ * Tabsize: 4
+ * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm165.inc 740 2009-04-13 18:23:31Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 16.5 MHz version of the USB driver. It is intended for the
+ATTiny45 and similar controllers running on 16.5 MHz internal RC oscillator.
+This version contains a phase locked loop in the receiver routine to cope with
+slight clock rate deviations of up to +/- 1%.
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+;Software-receiver engine. Strict timing! Don't change unless you can preserve timing!
+;interrupt response time: 4 cycles + insn running = 7 max if interrupts always enabled
+;max allowable interrupt latency: 59 cycles -> max 52 cycles interrupt disable
+;max stack usage: [ret(2), r0, SREG, YL, YH, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 16.5 MHz -> 11 cycles per bit
+; 16.3125 MHz < F_CPU < 16.6875 MHz (+/- 1.1%)
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG [sofError], r0, YH, shift, x1, x2, x3, x4, cnt
+ push YL ;[-23] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;[-21]
+ push YL ;[-20]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-15]
+ rjmp foundK ;[-14]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK: ;[-12]
+;{3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for center sampling]
+;we have 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push r0 ;[-12]
+; [---] ;[-11]
+ push YH ;[-10]
+; [---] ;[-9]
+ lds YL, usbInputBufOffset;[-8]
+; [---] ;[-7]
+ clr YH ;[-6]
+ subi YL, lo8(-(usbRxBuf));[-5] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-4] [rx loop init]
+ mov r0, x2 ;[-3] [rx loop init]
+ sbis USBIN, USBMINUS ;[-2] we want two bits K (sample 2 cycles too early)
+ rjmp haveTwoBitsK ;[-1]
+ pop YH ;[0] undo the pushes from before
+ pop r0 ;[2]
+ rjmp waitForK ;[4] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 22 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK: ;[1]
+ push shift ;[1]
+ push x1 ;[3]
+ push x2 ;[5]
+ push x3 ;[7]
+ ldi shift, 0xff ;[9] [rx loop init]
+ ori x3, 0xff ;[10] [rx loop init] == ser x3, clear zero flag
+
+ in x1, USBIN ;[11] <-- sample bit 0
+ bst x1, USBMINUS ;[12]
+ bld shift, 0 ;[13]
+ push x4 ;[14] == phase
+; [---] ;[15]
+ push cnt ;[16]
+; [---] ;[17]
+ ldi phase, 0 ;[18] [rx loop init]
+ ldi cnt, USB_BUFSIZE;[19] [rx loop init]
+ rjmp rxbit1 ;[20]
+; [---] ;[21]
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+/*
+byte oriented operations done during loop:
+bit 0: store data
+bit 1: SE0 check
+bit 2: overflow check
+bit 3: catch up
+bit 4: rjmp to achieve conditional jump range
+bit 5: PLL
+bit 6: catch up
+bit 7: jump, fixup bitstuff
+; 87 [+ 2] cycles
+------------------------------------------------------------------
+*/
+continueWithBit5:
+ in x2, USBIN ;[055] <-- bit 5
+ eor r0, x2 ;[056]
+ or phase, r0 ;[057]
+ sbrc phase, USBMINUS ;[058]
+ lpm ;[059] optional nop3; modifies r0
+ in phase, USBIN ;[060] <-- phase
+ eor x1, x2 ;[061]
+ bst x1, USBMINUS ;[062]
+ bld shift, 5 ;[063]
+ andi shift, 0x3f ;[064]
+ in x1, USBIN ;[065] <-- bit 6
+ breq unstuff5 ;[066] *** unstuff escape
+ eor phase, x1 ;[067]
+ eor x2, x1 ;[068]
+ bst x2, USBMINUS ;[069]
+ bld shift, 6 ;[070]
+didUnstuff6: ;[ ]
+ in r0, USBIN ;[071] <-- phase
+ cpi shift, 0x02 ;[072]
+ brlo unstuff6 ;[073] *** unstuff escape
+didUnstuff5: ;[ ]
+ nop2 ;[074]
+; [---] ;[075]
+ in x2, USBIN ;[076] <-- bit 7
+ eor x1, x2 ;[077]
+ bst x1, USBMINUS ;[078]
+ bld shift, 7 ;[079]
+didUnstuff7: ;[ ]
+ eor r0, x2 ;[080]
+ or phase, r0 ;[081]
+ in r0, USBIN ;[082] <-- phase
+ cpi shift, 0x04 ;[083]
+ brsh rxLoop ;[084]
+; [---] ;[085]
+unstuff7: ;[ ]
+ andi x3, ~0x80 ;[085]
+ ori shift, 0x80 ;[086]
+ in x2, USBIN ;[087] <-- sample stuffed bit 7
+ nop ;[088]
+ rjmp didUnstuff7 ;[089]
+; [---] ;[090]
+ ;[080]
+
+unstuff5: ;[067]
+ eor phase, x1 ;[068]
+ andi x3, ~0x20 ;[069]
+ ori shift, 0x20 ;[070]
+ in r0, USBIN ;[071] <-- phase
+ mov x2, x1 ;[072]
+ nop ;[073]
+ nop2 ;[074]
+; [---] ;[075]
+ in x1, USBIN ;[076] <-- bit 6
+ eor r0, x1 ;[077]
+ or phase, r0 ;[078]
+ eor x2, x1 ;[079]
+ bst x2, USBMINUS ;[080]
+ bld shift, 6 ;[081] no need to check bitstuffing, we just had one
+ in r0, USBIN ;[082] <-- phase
+ rjmp didUnstuff5 ;[083]
+; [---] ;[084]
+ ;[074]
+
+unstuff6: ;[074]
+ andi x3, ~0x40 ;[075]
+ in x1, USBIN ;[076] <-- bit 6 again
+ ori shift, 0x40 ;[077]
+ nop2 ;[078]
+; [---] ;[079]
+ rjmp didUnstuff6 ;[080]
+; [---] ;[081]
+ ;[071]
+
+unstuff0: ;[013]
+ eor r0, x2 ;[014]
+ or phase, r0 ;[015]
+ andi x2, USBMASK ;[016] check for SE0
+ in r0, USBIN ;[017] <-- phase
+ breq didUnstuff0 ;[018] direct jump to se0 would be too long
+ andi x3, ~0x01 ;[019]
+ ori shift, 0x01 ;[020]
+ mov x1, x2 ;[021] mov existing sample
+ in x2, USBIN ;[022] <-- bit 1 again
+ rjmp didUnstuff0 ;[023]
+; [---] ;[024]
+ ;[014]
+
+unstuff1: ;[024]
+ eor r0, x1 ;[025]
+ or phase, r0 ;[026]
+ andi x3, ~0x02 ;[027]
+ in r0, USBIN ;[028] <-- phase
+ ori shift, 0x02 ;[029]
+ mov x2, x1 ;[030]
+ rjmp didUnstuff1 ;[031]
+; [---] ;[032]
+ ;[022]
+
+unstuff2: ;[035]
+ eor r0, x2 ;[036]
+ or phase, r0 ;[037]
+ andi x3, ~0x04 ;[038]
+ in r0, USBIN ;[039] <-- phase
+ ori shift, 0x04 ;[040]
+ mov x1, x2 ;[041]
+ rjmp didUnstuff2 ;[042]
+; [---] ;[043]
+ ;[033]
+
+unstuff3: ;[043]
+ in x2, USBIN ;[044] <-- bit 3 again
+ eor r0, x2 ;[045]
+ or phase, r0 ;[046]
+ andi x3, ~0x08 ;[047]
+ ori shift, 0x08 ;[048]
+ nop ;[049]
+ in r0, USBIN ;[050] <-- phase
+ rjmp didUnstuff3 ;[051]
+; [---] ;[052]
+ ;[042]
+
+unstuff4: ;[053]
+ andi x3, ~0x10 ;[054]
+ in x1, USBIN ;[055] <-- bit 4 again
+ ori shift, 0x10 ;[056]
+ rjmp didUnstuff4 ;[057]
+; [---] ;[058]
+ ;[048]
+
+rxLoop: ;[085]
+ eor x3, shift ;[086] reconstruct: x3 is 0 at bit locations we changed, 1 at others
+ in x1, USBIN ;[000] <-- bit 0
+ st y+, x3 ;[001]
+; [---] ;[002]
+ eor r0, x1 ;[003]
+ or phase, r0 ;[004]
+ eor x2, x1 ;[005]
+ in r0, USBIN ;[006] <-- phase
+ ser x3 ;[007]
+ bst x2, USBMINUS ;[008]
+ bld shift, 0 ;[009]
+ andi shift, 0xf9 ;[010]
+rxbit1: ;[ ]
+ in x2, USBIN ;[011] <-- bit 1
+ breq unstuff0 ;[012] *** unstuff escape
+ andi x2, USBMASK ;[013] SE0 check for bit 1
+didUnstuff0: ;[ ] Z only set if we detected SE0 in bitstuff
+ breq se0 ;[014]
+ eor r0, x2 ;[015]
+ or phase, r0 ;[016]
+ in r0, USBIN ;[017] <-- phase
+ eor x1, x2 ;[018]
+ bst x1, USBMINUS ;[019]
+ bld shift, 1 ;[020]
+ andi shift, 0xf3 ;[021]
+didUnstuff1: ;[ ]
+ in x1, USBIN ;[022] <-- bit 2
+ breq unstuff1 ;[023] *** unstuff escape
+ eor r0, x1 ;[024]
+ or phase, r0 ;[025]
+ subi cnt, 1 ;[026] overflow check
+ brcs overflow ;[027]
+ in r0, USBIN ;[028] <-- phase
+ eor x2, x1 ;[029]
+ bst x2, USBMINUS ;[030]
+ bld shift, 2 ;[031]
+ andi shift, 0xe7 ;[032]
+didUnstuff2: ;[ ]
+ in x2, USBIN ;[033] <-- bit 3
+ breq unstuff2 ;[034] *** unstuff escape
+ eor r0, x2 ;[035]
+ or phase, r0 ;[036]
+ eor x1, x2 ;[037]
+ bst x1, USBMINUS ;[038]
+ in r0, USBIN ;[039] <-- phase
+ bld shift, 3 ;[040]
+ andi shift, 0xcf ;[041]
+didUnstuff3: ;[ ]
+ breq unstuff3 ;[042] *** unstuff escape
+ nop ;[043]
+ in x1, USBIN ;[044] <-- bit 4
+ eor x2, x1 ;[045]
+ bst x2, USBMINUS ;[046]
+ bld shift, 4 ;[047]
+didUnstuff4: ;[ ]
+ eor r0, x1 ;[048]
+ or phase, r0 ;[049]
+ in r0, USBIN ;[050] <-- phase
+ andi shift, 0x9f ;[051]
+ breq unstuff4 ;[052] *** unstuff escape
+ rjmp continueWithBit5;[053]
+; [---] ;[054]
+
+macro POP_STANDARD ; 16 cycles
+ pop cnt
+ pop x4
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop YH
+ pop r0
+ endm
+macro POP_RETI ; 5 cycles
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+#include "asmcommon.inc"
+
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+
+bitstuff7:
+ eor x1, x4 ;[4]
+ ldi x2, 0 ;[5]
+ nop2 ;[6] C is zero (brcc)
+ rjmp didStuff7 ;[8]
+
+bitstuffN:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6]
+ lpm ;[7] 3 cycle NOP, modifies r0
+ out USBOUT, x1 ;[10] <-- out
+ rjmp didStuffN ;[0]
+
+#define bitStatus x3
+
+sendNakAndReti:
+ ldi cnt, USBPID_NAK ;[-19]
+ rjmp sendCntAndReti ;[-18]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov r0, cnt ;[-16]
+ ldi YL, 0 ;[-15] R0 address is 0
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-6] exor mask
+ ldi shift, 0x80 ;[-5] sync byte is first byte sent
+ ldi bitStatus, 0xff ;[-4] init bit loop counter, works for up to 12 bytes
+byteloop:
+bitloop:
+ sbrs shift, 0 ;[8] [-3]
+ eor x1, x4 ;[9] [-2]
+ out USBOUT, x1 ;[10] [-1] <-- out
+ ror shift ;[0]
+ ror x2 ;[1]
+didStuffN:
+ cpi x2, 0xfc ;[2]
+ brcc bitstuffN ;[3]
+ nop ;[4]
+ subi bitStatus, 37 ;[5] 256 / 7 ~=~ 37
+ brcc bitloop ;[6] when we leave the loop, bitStatus has almost the initial value
+ sbrs shift, 0 ;[7]
+ eor x1, x4 ;[8]
+ ror shift ;[9]
+didStuff7:
+ out USBOUT, x1 ;[10] <-- out
+ ror x2 ;[0]
+ cpi x2, 0xfc ;[1]
+ brcc bitstuff7 ;[2]
+ ld shift, y+ ;[3]
+ dec cnt ;[5]
+ brne byteloop ;[6]
+;make SE0:
+ cbr x1, USBMASK ;[7] prepare SE0 [spec says EOP may be 21 to 25 cycles]
+ lds x2, usbNewDeviceAddr;[8]
+ lsl x2 ;[10] we compare with left shifted address
+ out USBOUT, x1 ;[11] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ subi YL, 2 ;[0] Only assign address on data packets, not ACK/NAK in r0
+ sbci YH, 0 ;[1]
+ breq skipAddrAssign ;[2]
+ sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[5]
+ ori x1, USBIDLE ;[6]
+ in x2, USBDDR ;[7]
+ cbr x2, USBMASK ;[8] set both pins to input
+ mov x3, x1 ;[9]
+ cbr x3, USBMASK ;[10] configure no pullup on both pins
+ ldi x4, 4 ;[11]
+se0Delay:
+ dec x4 ;[12] [15] [18] [21]
+ brne se0Delay ;[13] [16] [19] [22]
+ out USBOUT, x1 ;[23] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[24] <-- release bus now
+ out USBOUT, x3 ;[25] <-- ensure no pull-up resistors are active
+ rjmp doReturn
+
--- /dev/null
+/* Name: usbdrvasm18.inc
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Lukas Schrittwieser (based on 20 MHz usbdrvasm20.inc by Jeroen Benschop)
+ * Creation Date: 2009-01-20
+ * Tabsize: 4
+ * Copyright: (c) 2008 by Lukas Schrittwieser and OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm18-crc.inc 740 2009-04-13 18:23:31Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 18 MHz version of the asssembler part of the USB driver. It
+requires a 18 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+
+;max stack usage: [ret(2), YL, SREG, YH, [sofError], bitcnt(x5), shift, x1, x2, x3, x4, cnt, ZL, ZH] = 14 bytes
+;nominal frequency: 18 MHz -> 12 cycles per bit
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+;register use in receive loop to receive the data bytes:
+; shift assembles the byte currently being received
+; x1 holds the D+ and D- line state
+; x2 holds the previous line state
+; cnt holds the number of bytes left in the receive buffer
+; x3 holds the higher crc byte (see algorithm below)
+; x4 is used as temporary register for the crc algorithm
+; x5 is used for unstuffing: when unstuffing the last received bit is inverted in shift (to prevent further
+; unstuffing calls. In the same time the corresponding bit in x5 is cleared to mark the bit as beening iverted
+; zl lower crc value and crc table index
+; zh used for crc table accesses
+
+;--------------------------------------------------------------------------------------------------------------
+; CRC mods:
+; table driven crc checker, Z points to table in prog space
+; ZL is the lower crc byte, x3 is the higher crc byte
+; x4 is used as temp register to store different results
+; the initialization of the crc register is not 0xFFFF but 0xFE54. This is because during the receipt of the
+; first data byte an virtual zero data byte is added to the crc register, this results in the correct initial
+; value of 0xFFFF at beginning of the second data byte before the first data byte is added to the crc.
+; The magic number 0xFE54 results form the crc table: At tabH[0x54] = 0xFF = crcH (required) and
+; tabL[0x54] = 0x01 -> crcL = 0x01 xor 0xFE = 0xFF
+; bitcnt is renamed to x5 and is used for unstuffing purposes, the unstuffing works like in the 12MHz version
+;--------------------------------------------------------------------------------------------------------------
+; CRC algorithm:
+; The crc register is formed by x3 (higher byte) and ZL (lower byte). The algorithm uses a 'reversed' form
+; i.e. that it takes the least significant bit first and shifts to the right. So in fact the highest order
+; bit seen from the polynomial devision point of view is the lsb of ZL. (If this sounds strange to you i
+; propose a research on CRC :-) )
+; Each data byte received is xored to ZL, the lower crc byte. This byte now builds the crc
+; table index. Next the new high byte is loaded from the table and stored in x4 until we have space in x3
+; (its destination).
+; Afterwards the lower table is loaded from the table and stored in ZL (the old index is overwritten as
+; we don't need it anymore. In fact this is a right shift by 8 bits.) Now the old crc high value is xored
+; to ZL, this is the second shift of the old crc value. Now x4 (the temp reg) is moved to x3 and the crc
+; calculation is done.
+; Prior to the first byte the two CRC register have to be initialized to 0xFFFF (as defined in usb spec)
+; however the crc engine also runs during the receipt of the first byte, therefore x3 and zl are initialized
+; to a magic number which results in a crc value of 0xFFFF after the first complete byte.
+;
+; This algorithm is split into the extra cycles of the different bits:
+; bit7: XOR the received byte to ZL
+; bit5: load the new high byte to x4
+; bit6: load the lower xor byte from the table, xor zl and x3, store result in zl (=the new crc low value)
+; move x4 (the new high byte) to x3, the crc value is ready
+;
+
+
+macro POP_STANDARD ; 18 cycles
+ pop ZH
+ pop ZL
+ pop cnt
+ pop x5
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop x4
+ endm
+macro POP_RETI ; 7 cycles
+ pop YH
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+macro CRC_CLEANUP_AND_CHECK
+ ; the last byte has already been xored with the lower crc byte, we have to do the table lookup and xor
+ ; x3 is the higher crc byte, zl the lower one
+ ldi ZH, hi8(usbCrcTableHigh);[+1] get the new high byte from the table
+ lpm x2, Z ;[+2][+3][+4]
+ ldi ZH, hi8(usbCrcTableLow);[+5] get the new low xor byte from the table
+ lpm ZL, Z ;[+6][+7][+8]
+ eor ZL, x3 ;[+7] xor the old high byte with the value from the table, x2:ZL now holds the crc value
+ cpi ZL, 0x01 ;[+8] if the crc is ok we have a fixed remainder value of 0xb001 in x2:ZL (see usb spec)
+ brne ignorePacket ;[+9] detected a crc fault -> paket is ignored and retransmitted by the host
+ cpi x2, 0xb0 ;[+10]
+ brne ignorePacket ;[+11] detected a crc fault -> paket is ignored and retransmitted by the host
+ endm
+
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG, YH, [sofError], x4, shift, x1, x2, x3, x5, cnt, ZL, ZH
+ push YL ;[-28] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;[-26]
+ push YL ;[-25]
+ push YH ;[-23]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-17]
+ rjmp foundK ;[-16]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK: ;[-15]
+;{3, 5} after falling D- edge, average delay: 4 cycles
+;bit0 should be at 30 (2.5 bits) for center sampling. Currently at 4 so 26 cylces till bit 0 sample
+;use 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push x4 ;[-14]
+; [---] ;[-13]
+ lds YL, usbInputBufOffset;[-12] used to toggle the two usb receive buffers
+; [---] ;[-11]
+ clr YH ;[-10]
+ subi YL, lo8(-(usbRxBuf));[-9] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-8] [rx loop init]
+ push shift ;[-7]
+; [---] ;[-6]
+ ldi shift, 0x80 ;[-5] the last bit is the end of byte marker for the pid receiver loop
+ clc ;[-4] the carry has to be clear for receipt of pid bit 0
+ sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early)
+ rjmp haveTwoBitsK ;[-2]
+ pop shift ;[-1] undo the push from before
+ pop x4 ;[1]
+ rjmp waitForK ;[3] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 24 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK:
+ push x1 ;[0]
+ push x2 ;[2]
+ push x3 ;[4] crc high byte
+ ldi x2, 1<<USBPLUS ;[6] [rx loop init] current line state is K state. D+=="1", D-=="0"
+ push x5 ;[7]
+ push cnt ;[9]
+ ldi cnt, USB_BUFSIZE ;[11]
+
+
+;--------------------------------------------------------------------------------------------------------------
+; receives the pid byte
+; there is no real unstuffing algorithm implemented here as a stuffing bit is impossible in the pid byte.
+; That's because the last four bits of the byte are the inverted of the first four bits. If we detect a
+; unstuffing condition something went wrong and abort
+; shift has to be initialized to 0x80
+;--------------------------------------------------------------------------------------------------------------
+
+; pid bit 0 - used for even more register saving (we need the z pointer)
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] filter only D+ and D- bits
+ eor x2, x1 ;[2] generate inverted of actual bit
+ sbrc x2, USBMINUS ;[3] if the bit is set we received a zero
+ sec ;[4]
+ ror shift ;[5] we perform no unstuffing check here as this is the first bit
+ mov x2, x1 ;[6]
+ push ZL ;[7]
+ ;[8]
+ push ZH ;[9]
+ ;[10]
+ ldi x3, 0xFE ;[11] x3 is the high order crc value
+
+
+bitloopPid:
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] filter only D+ and D- bits
+ breq nse0 ;[2] both lines are low so handle se0
+ eor x2, x1 ;[3] generate inverted of actual bit
+ sbrc x2, USBMINUS ;[4] set the carry if we received a zero
+ sec ;[5]
+ ror shift ;[6]
+ ldi ZL, 0x54 ;[7] ZL is the low order crc value
+ ser x4 ;[8] the is no bit stuffing check here as the pid bit can't be stuffed. if so
+ ; some error occured. In this case the paket is discarded later on anyway.
+ mov x2, x1 ;[9] prepare for the next cycle
+ brcc bitloopPid ;[10] while 0s drop out of shift we get the next bit
+ eor x4, shift ;[11] invert all bits in shift and store result in x4
+
+;--------------------------------------------------------------------------------------------------------------
+; receives data bytes and calculates the crc
+; the last USBIN state has to be in x2
+; this is only the first half, due to branch distanc limitations the second half of the loop is near the end
+; of this asm file
+;--------------------------------------------------------------------------------------------------------------
+
+rxDataStart:
+ in x1, USBIN ;[0] sample line state (note: a se0 check is not useful due to bit dribbling)
+ ser x5 ;[1] prepare the unstuff marker register
+ eor x2, x1 ;[2] generates the inverted of the actual bit
+ bst x2, USBMINUS ;[3] copy the bit from x2
+ bld shift, 0 ;[4] and store it in shift
+ mov x2, shift ;[5] make a copy of shift for unstuffing check
+ andi x2, 0xF9 ;[6] mask the last six bits, if we got six zeros (which are six ones in fact)
+ breq unstuff0 ;[7] then Z is set now and we branch to the unstuffing handler
+didunstuff0:
+ subi cnt, 1 ;[8] cannot use dec because it doesn't affect the carry flag
+ brcs nOverflow ;[9] Too many bytes received. Ignore packet
+ st Y+, x4 ;[10] store the last received byte
+ ;[11] st needs two cycles
+
+; bit1
+ in x2, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] check for se0 during bit 0
+ breq nse0 ;[2]
+ andi x2, USBMASK ;[3] check se0 during bit 1
+ breq nse0 ;[4]
+ eor x1, x2 ;[5]
+ bst x1, USBMINUS ;[6]
+ bld shift, 1 ;[7]
+ mov x1, shift ;[8]
+ andi x1, 0xF3 ;[9]
+ breq unstuff1 ;[10]
+didunstuff1:
+ nop ;[11]
+
+; bit2
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] check for se0 (as there is nothing else to do here
+ breq nOverflow ;[2]
+ eor x2, x1 ;[3] generates the inverted of the actual bit
+ bst x2, USBMINUS ;[4]
+ bld shift, 2 ;[5] store the bit
+ mov x2, shift ;[6]
+ andi x2, 0xE7 ;[7] if we have six zeros here (which means six 1 in the stream)
+ breq unstuff2 ;[8] the next bit is a stuffing bit
+didunstuff2:
+ nop2 ;[9]
+ ;[10]
+ nop ;[11]
+
+; bit3
+ in x2, USBIN ;[0] sample line state
+ andi x2, USBMASK ;[1] check for se0
+ breq nOverflow ;[2]
+ eor x1, x2 ;[3]
+ bst x1, USBMINUS ;[4]
+ bld shift, 3 ;[5]
+ mov x1, shift ;[6]
+ andi x1, 0xCF ;[7]
+ breq unstuff3 ;[8]
+didunstuff3:
+ nop ;[9]
+ rjmp rxDataBit4 ;[10]
+ ;[11]
+
+; the avr branch instructions allow an offset of +63 insturction only, so we need this
+; 'local copy' of se0
+nse0:
+ rjmp se0 ;[4]
+ ;[5]
+; the same same as for se0 is needed for overflow and StuffErr
+nOverflow:
+stuffErr:
+ rjmp overflow
+
+
+unstuff0: ;[8] this is the branch delay of breq unstuffX
+ andi x1, USBMASK ;[9] do an se0 check here (if the last crc byte ends with 5 one's we might end up here
+ breq didunstuff0 ;[10] event tough the message is complete -> jump back and store the byte
+ ori shift, 0x01 ;[11] invert the last received bit to prevent furhter unstuffing
+ in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
+ andi x5, 0xFE ;[1] mark this bit as inverted (will be corrected before storing shift)
+ eor x1, x2 ;[2] x1 and x2 have to be different because the stuff bit is always a zero
+ andi x1, USBMASK ;[3] mask the interesting bits
+ breq stuffErr ;[4] if the stuff bit is a 1-bit something went wrong
+ mov x1, x2 ;[5] the next bit expects the last state to be in x1
+ rjmp didunstuff0 ;[6]
+ ;[7] jump delay of rjmp didunstuffX
+
+unstuff1: ;[11] this is the jump delay of breq unstuffX
+ in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
+ ori shift, 0x02 ;[1] invert the last received bit to prevent furhter unstuffing
+ andi x5, 0xFD ;[2] mark this bit as inverted (will be corrected before storing shift)
+ eor x2, x1 ;[3] x1 and x2 have to be different because the stuff bit is always a zero
+ andi x2, USBMASK ;[4] mask the interesting bits
+ breq stuffErr ;[5] if the stuff bit is a 1-bit something went wrong
+ mov x2, x1 ;[6] the next bit expects the last state to be in x2
+ nop2 ;[7]
+ ;[8]
+ rjmp didunstuff1 ;[9]
+ ;[10] jump delay of rjmp didunstuffX
+
+unstuff2: ;[9] this is the jump delay of breq unstuffX
+ ori shift, 0x04 ;[10] invert the last received bit to prevent furhter unstuffing
+ andi x5, 0xFB ;[11] mark this bit as inverted (will be corrected before storing shift)
+ in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
+ eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
+ andi x1, USBMASK ;[2] mask the interesting bits
+ breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong
+ mov x1, x2 ;[4] the next bit expects the last state to be in x1
+ nop2 ;[5]
+ ;[6]
+ rjmp didunstuff2 ;[7]
+ ;[8] jump delay of rjmp didunstuffX
+
+unstuff3: ;[9] this is the jump delay of breq unstuffX
+ ori shift, 0x08 ;[10] invert the last received bit to prevent furhter unstuffing
+ andi x5, 0xF7 ;[11] mark this bit as inverted (will be corrected before storing shift)
+ in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
+ eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
+ andi x2, USBMASK ;[2] mask the interesting bits
+ breq stuffErr ;[3] if the stuff bit is a 1-bit something went wrong
+ mov x2, x1 ;[4] the next bit expects the last state to be in x2
+ nop2 ;[5]
+ ;[6]
+ rjmp didunstuff3 ;[7]
+ ;[8] jump delay of rjmp didunstuffX
+
+
+
+; the include has to be here due to branch distance restirctions
+#define __USE_CRC__
+#include "asmcommon.inc"
+
+
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+; 7.5 bit times is 90 cycles. ...there is plenty of time
+
+
+sendNakAndReti:
+ ldi x3, USBPID_NAK ;[-18]
+ rjmp sendX3AndReti ;[-17]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov x3, cnt ;[-16]
+sendX3AndReti:
+ ldi YL, 20 ;[-15] x3==r20 address is 20
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, btcnt, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-6] <- acquire bus
+ ldi x2, 0 ;[-6] init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-5] exor mask
+ ldi shift, 0x80 ;[-4] sync byte is first byte sent
+txByteLoop:
+ ldi bitcnt, 0x40 ;[-3]=[9] binary 01000000
+txBitLoop: ; the loop sends the first 7 bits of the byte
+ sbrs shift, 0 ;[-2]=[10] if we have to send a 1 don't change the line state
+ eor x1, x4 ;[-1]=[11]
+ out USBOUT, x1 ;[0]
+ ror shift ;[1]
+ ror x2 ;[2] transfers the last sent bit to the stuffing history
+didStuffN:
+ nop ;[3]
+ nop ;[4]
+ cpi x2, 0xfc ;[5] if we sent six consecutive ones
+ brcc bitstuffN ;[6]
+ lsr bitcnt ;[7]
+ brne txBitLoop ;[8] restart the loop while the 1 is still in the bitcount
+
+; transmit bit 7
+ sbrs shift, 0 ;[9]
+ eor x1, x4 ;[10]
+didStuff7:
+ ror shift ;[11]
+ out USBOUT, x1 ;[0] transfer bit 7 to the pins
+ ror x2 ;[1] move the bit into the stuffing history
+ cpi x2, 0xfc ;[2]
+ brcc bitstuff7 ;[3]
+ ld shift, y+ ;[4] get next byte to transmit
+ dec cnt ;[5] decrement byte counter
+ brne txByteLoop ;[7] if we have more bytes start next one
+ ;[8] branch delay
+
+;make SE0:
+ cbr x1, USBMASK ;[8] prepare SE0 [spec says EOP may be 25 to 30 cycles]
+ lds x2, usbNewDeviceAddr;[9]
+ lsl x2 ;[11] we compare with left shifted address
+ out USBOUT, x1 ;[0] <-- out SE0 -- from now 2 bits = 24 cycles until bus idle
+ subi YL, 20 + 2 ;[1] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;[2]
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[3]
+ sts usbDeviceAddr, x2 ; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[5] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[6]
+ ori x1, USBIDLE ;[7]
+ in x2, USBDDR ;[8]
+ cbr x2, USBMASK ;[9] set both pins to input
+ mov x3, x1 ;[10]
+ cbr x3, USBMASK ;[11] configure no pullup on both pins
+ ldi x4, 4 ;[12]
+se0Delay:
+ dec x4 ;[13] [16] [19] [22]
+ brne se0Delay ;[14] [17] [20] [23]
+ out USBOUT, x1 ;[24] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[25] <-- release bus now
+ out USBOUT, x3 ;[26] <-- ensure no pull-up resistors are active
+ rjmp doReturn
+
+bitstuffN:
+ eor x1, x4 ;[8] generate a zero
+ ldi x2, 0 ;[9] reset the bit stuffing history
+ nop2 ;[10]
+ out USBOUT, x1 ;[0] <-- send the stuffing bit
+ rjmp didStuffN ;[1]
+
+bitstuff7:
+ eor x1, x4 ;[5]
+ ldi x2, 0 ;[6] reset bit stuffing history
+ clc ;[7] fill a zero into the shift register
+ rol shift ;[8] compensate for ror shift at branch destination
+ rjmp didStuff7 ;[9]
+ ;[10] jump delay
+
+;--------------------------------------------------------------------------------------------------------------
+; receives data bytes and calculates the crc
+; second half of the data byte receiver loop
+; most parts of the crc algorithm are here
+;--------------------------------------------------------------------------------------------------------------
+
+nOverflow2:
+ rjmp overflow
+
+rxDataBit4:
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] check for se0
+ breq nOverflow2 ;[2]
+ eor x2, x1 ;[3]
+ bst x2, USBMINUS ;[4]
+ bld shift, 4 ;[5]
+ mov x2, shift ;[6]
+ andi x2, 0x9F ;[7]
+ breq unstuff4 ;[8]
+didunstuff4:
+ nop2 ;[9][10]
+ nop ;[11]
+
+; bit5
+ in x2, USBIN ;[0] sample line state
+ ldi ZH, hi8(usbCrcTableHigh);[1] use the table for the higher byte
+ eor x1, x2 ;[2]
+ bst x1, USBMINUS ;[3]
+ bld shift, 5 ;[4]
+ mov x1, shift ;[5]
+ andi x1, 0x3F ;[6]
+ breq unstuff5 ;[7]
+didunstuff5:
+ lpm x4, Z ;[8] load the higher crc xor-byte and store it for later use
+ ;[9] lpm needs 3 cycles
+ ;[10]
+ ldi ZH, hi8(usbCrcTableLow);[11] load the lower crc xor byte adress
+
+; bit6
+ in x1, USBIN ;[0] sample line state
+ eor x2, x1 ;[1]
+ bst x2, USBMINUS ;[2]
+ bld shift, 6 ;[3]
+ mov x2, shift ;[4]
+ andi x2, 0x7E ;[5]
+ breq unstuff6 ;[6]
+didunstuff6:
+ lpm ZL, Z ;[7] load the lower xor crc byte
+ ;[8] lpm needs 3 cycles
+ ;[9]
+ eor ZL, x3 ;[10] xor the old high crc byte with the low xor-byte
+ mov x3, x4 ;[11] move the new high order crc value from temp to its destination
+
+; bit7
+ in x2, USBIN ;[0] sample line state
+ eor x1, x2 ;[1]
+ bst x1, USBMINUS ;[2]
+ bld shift, 7 ;[3] now shift holds the complete but inverted data byte
+ mov x1, shift ;[4]
+ andi x1, 0xFC ;[5]
+ breq unstuff7 ;[6]
+didunstuff7:
+ eor x5, shift ;[7] x5 marks all bits which have not been inverted by the unstuffing subs
+ mov x4, x5 ;[8] keep a copy of the data byte it will be stored during next bit0
+ eor ZL, x4 ;[9] feed the actual byte into the crc algorithm
+ rjmp rxDataStart ;[10] next byte
+ ;[11] during the reception of the next byte this one will be fed int the crc algorithm
+
+unstuff4: ;[9] this is the jump delay of rjmp unstuffX
+ ori shift, 0x10 ;[10] invert the last received bit to prevent furhter unstuffing
+ andi x5, 0xEF ;[11] mark this bit as inverted (will be corrected before storing shift)
+ in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
+ eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
+ andi x1, USBMASK ;[2] mask the interesting bits
+ breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong
+ mov x1, x2 ;[4] the next bit expects the last state to be in x1
+ nop2 ;[5]
+ ;[6]
+ rjmp didunstuff4 ;[7]
+ ;[8] jump delay of rjmp didunstuffX
+
+unstuff5: ;[8] this is the jump delay of rjmp unstuffX
+ nop ;[9]
+ ori shift, 0x20 ;[10] invert the last received bit to prevent furhter unstuffing
+ andi x5, 0xDF ;[11] mark this bit as inverted (will be corrected before storing shift)
+ in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
+ eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
+ andi x2, USBMASK ;[2] mask the interesting bits
+ breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong
+ mov x2, x1 ;[4] the next bit expects the last state to be in x2
+ nop ;[5]
+ rjmp didunstuff5 ;[6]
+ ;[7] jump delay of rjmp didunstuffX
+
+unstuff6: ;[7] this is the jump delay of rjmp unstuffX
+ nop2 ;[8]
+ ;[9]
+ ori shift, 0x40 ;[10] invert the last received bit to prevent furhter unstuffing
+ andi x5, 0xBF ;[11] mark this bit as inverted (will be corrected before storing shift)
+ in x2, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
+ eor x1, x2 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
+ andi x1, USBMASK ;[2] mask the interesting bits
+ breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong
+ mov x1, x2 ;[4] the next bit expects the last state to be in x1
+ rjmp didunstuff6 ;[5]
+ ;[6] jump delay of rjmp didunstuffX
+
+unstuff7: ;[7] this is the jump delay of rjmp unstuffX
+ nop ;[8]
+ nop ;[9]
+ ori shift, 0x80 ;[10] invert the last received bit to prevent furhter unstuffing
+ andi x5, 0x7F ;[11] mark this bit as inverted (will be corrected before storing shift)
+ in x1, USBIN ;[0] we have some free cycles so we could check for bit stuffing errors
+ eor x2, x1 ;[1] x1 and x2 have to be different because the stuff bit is always a zero
+ andi x2, USBMASK ;[2] mask the interesting bits
+ breq stuffErr2 ;[3] if the stuff bit is a 1-bit something went wrong
+ mov x2, x1 ;[4] the next bit expects the last state to be in x2
+ rjmp didunstuff7 ;[5]
+ ;[6] jump delay of rjmp didunstuff7
+
+; local copy of the stuffErr desitnation for the second half of the receiver loop
+stuffErr2:
+ rjmp stuffErr
+
+;--------------------------------------------------------------------------------------------------------------
+; The crc table follows. It has to be aligned to enable a fast loading of the needed bytes.
+; There are two tables of 256 entries each, the low and the high byte table.
+; Table values were generated with the following C code:
+/*
+#include <stdio.h>
+int main (int argc, char **argv)
+{
+ int i, j;
+ for (i=0; i<512; i++){
+ unsigned short crc = i & 0xff;
+ for(j=0; j<8; j++) crc = (crc >> 1) ^ ((crc & 1) ? 0xa001 : 0);
+ if((i & 7) == 0) printf("\n.byte ");
+ printf("0x%02x, ", (i > 0xff ? (crc >> 8) : crc) & 0xff);
+ if(i == 255) printf("\n");
+ }
+ return 0;
+}
+
+// Use the following algorithm to compute CRC values:
+ushort computeCrc(uchar *msg, uchar msgLen)
+{
+ uchar i;
+ ushort crc = 0xffff;
+ for(i = 0; i < msgLen; i++)
+ crc = usbCrcTable16[lo8(crc) ^ msg[i]] ^ hi8(crc);
+ return crc;
+}
+*/
+
+.balign 256
+usbCrcTableLow:
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41
+.byte 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40
+
+; .balign 256
+usbCrcTableHigh:
+.byte 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2
+.byte 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04
+.byte 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E
+.byte 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8
+.byte 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A
+.byte 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC
+.byte 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6
+.byte 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10
+.byte 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32
+.byte 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4
+.byte 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE
+.byte 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38
+.byte 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA
+.byte 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C
+.byte 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26
+.byte 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0
+.byte 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62
+.byte 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4
+.byte 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE
+.byte 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68
+.byte 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA
+.byte 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C
+.byte 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76
+.byte 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0
+.byte 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92
+.byte 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54
+.byte 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E
+.byte 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98
+.byte 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A
+.byte 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C
+.byte 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86
+.byte 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40
+
--- /dev/null
+/* Name: usbdrvasm20.inc
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Jeroen Benschop
+ * Based on usbdrvasm16.inc from Christian Starkjohann
+ * Creation Date: 2008-03-05
+ * Tabsize: 4
+ * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $
+ */
+
+/* Do not link this file! Link usbdrvasm.S instead, which includes the
+ * appropriate implementation!
+ */
+
+/*
+General Description:
+This file is the 20 MHz version of the asssembler part of the USB driver. It
+requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC
+oscillator).
+
+See usbdrv.h for a description of the entire driver.
+
+Since almost all of this code is timing critical, don't change unless you
+really know what you are doing! Many parts require not only a maximum number
+of CPU cycles, but even an exact number of cycles!
+*/
+
+#define leap2 x3
+#ifdef __IAR_SYSTEMS_ASM__
+#define nextInst $+2
+#else
+#define nextInst .+0
+#endif
+
+;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
+;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte
+; Numbers in brackets are clocks counted from center of last sync bit
+; when instruction starts
+;register use in receive loop:
+; shift assembles the byte currently being received
+; x1 holds the D+ and D- line state
+; x2 holds the previous line state
+; x4 (leap) is used to add a leap cycle once every three bytes received
+; X3 (leap2) is used to add a leap cycle once every three stuff bits received
+; bitcnt is used to determine when a stuff bit is due
+; cnt holds the number of bytes left in the receive buffer
+
+USB_INTR_VECTOR:
+;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
+ push YL ;[-28] push only what is necessary to sync with edge ASAP
+ in YL, SREG ;[-26]
+ push YL ;[-25]
+ push YH ;[-23]
+;----------------------------------------------------------------------------
+; Synchronize with sync pattern:
+;----------------------------------------------------------------------------
+;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
+;sync up with J to K edge during sync pattern -- use fastest possible loops
+;The first part waits at most 1 bit long since we must be in sync pattern.
+;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
+;waitForJ, ensure that this prerequisite is met.
+waitForJ:
+ inc YL
+ sbis USBIN, USBMINUS
+ brne waitForJ ; just make sure we have ANY timeout
+waitForK:
+;The following code results in a sampling window of < 1/4 bit which meets the spec.
+ sbis USBIN, USBMINUS ;[-19]
+ rjmp foundK ;[-18]
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+ sbis USBIN, USBMINUS
+ rjmp foundK
+#if USB_COUNT_SOF
+ lds YL, usbSofCount
+ inc YL
+ sts usbSofCount, YL
+#endif /* USB_COUNT_SOF */
+#ifdef USB_SOF_HOOK
+ USB_SOF_HOOK
+#endif
+ rjmp sofError
+foundK: ;[-16]
+;{3, 5} after falling D- edge, average delay: 4 cycles
+;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample
+;use 1 bit time for setup purposes, then sample again. Numbers in brackets
+;are cycles from center of first sync (double K) bit after the instruction
+ push bitcnt ;[-16]
+; [---] ;[-15]
+ lds YL, usbInputBufOffset;[-14]
+; [---] ;[-13]
+ clr YH ;[-12]
+ subi YL, lo8(-(usbRxBuf));[-11] [rx loop init]
+ sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init]
+ push shift ;[-9]
+; [---] ;[-8]
+ ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected
+ nop2 ;[-6]
+; [---] ;[-5]
+ ldi bitcnt, 5 ;[-4] [rx loop init]
+ sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early)
+ rjmp haveTwoBitsK ;[-2]
+ pop shift ;[-1] undo the push from before
+ pop bitcnt ;[1]
+ rjmp waitForK ;[3] this was not the end of sync, retry
+; The entire loop from waitForK until rjmp waitForK above must not exceed two
+; bit times (= 27 cycles).
+
+;----------------------------------------------------------------------------
+; push more registers and initialize values while we sample the first bits:
+;----------------------------------------------------------------------------
+haveTwoBitsK:
+ push x1 ;[0]
+ push x2 ;[2]
+ push x3 ;[4] (leap2)
+ ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit
+ push x4 ;[7] == leap
+ ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received
+ push cnt ;[10]
+ ldi cnt, USB_BUFSIZE ;[12] [rx loop init]
+ ldi x2, 1<<USBPLUS ;[13] current line state is K state. D+=="1", D-=="0"
+bit0:
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] filter only D+ and D- bits
+ rjmp handleBit ;[2] make bit0 14 cycles long
+
+;----------------------------------------------------------------------------
+; Process bit7. However, bit 6 still may need unstuffing.
+;----------------------------------------------------------------------------
+
+b6checkUnstuff:
+ dec bitcnt ;[9]
+ breq unstuff6 ;[10]
+bit7:
+ subi cnt, 1 ;[11] cannot use dec becaus it does not affect the carry flag
+ brcs overflow ;[12] Too many bytes received. Ignore packet
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] filter only D+ and D- bits
+ cpse x1, x2 ;[2] when previous line state equals current line state, handle "1"
+ rjmp b7handle0 ;[3] when line state differs, handle "0"
+ sec ;[4]
+ ror shift ;[5] shift "1" into the data
+ st y+, shift ;[6] store the data into the buffer
+ ldi shift, 0x40 ;[7] reset data for receiving the next byte
+ subi leap, 0x55 ;[9] trick to introduce a leap cycle every 3 bytes
+ brcc nextInst ;[10 or 11] it will fail after 85 bytes. However low speed can only receive 11
+ dec bitcnt ;[11 or 12]
+ brne bit0 ;[12 or 13]
+ ldi x1, 1 ;[13 or 14] unstuffing bit 7
+ in bitcnt, USBIN ;[0] sample stuff bit
+ rjmp unstuff ;[1]
+
+b7handle0:
+ mov x2,x1 ;[5] Set x2 to current line state
+ ldi bitcnt, 6 ;[6]
+ lsr shift ;[7] shift "0" into the data
+ st y+, shift ;[8] store data into the buffer
+ ldi shift, 0x40 ;[10] reset data for receiving the next byte
+ subi leap, 0x55 ;[11] trick to introduce a leap cycle every 3 bytes
+ brcs bit0 ;[12] it will fail after 85 bytes. However low speed can only receive 11
+ rjmp bit0 ;[13]
+
+
+;----------------------------------------------------------------------------
+; Handle unstuff
+; x1==0xFF indicate unstuffing bit6
+;----------------------------------------------------------------------------
+
+unstuff6:
+ ldi x1,0xFF ;[12] indicate unstuffing bit 6
+ in bitcnt, USBIN ;[0] sample stuff bit
+ nop ;[1] fix timing
+unstuff: ;b0-5 b6 b7
+ mov x2,bitcnt ;[3] [2] [3] Set x2 to match line state
+ subi leap2, 0x55 ;[4] [3] [4] delay loop
+ brcs nextInst ;[5] [4] [5] add one cycle every three stuff bits
+ sbci leap2,0 ;[6] [5] [6]
+ ldi bitcnt,6 ;[7] [6] [7] reset bit stuff counter
+ andi x2, USBMASK ;[8] [7] [8] only keep D+ and D-
+ cpi x1,0 ;[9] [8] [9]
+ brmi bit7 ;[10] [9] [10] finished unstuffing bit6 When x1<0
+ breq bitloop ;[11] --- [11] finished unstuffing bit0-5 when x1=0
+ nop ;--- --- [12]
+ in x1, USBIN ;--- --- [0] sample line state for bit0
+ andi x1, USBMASK ;--- --- [1] filter only D+ and D- bits
+ rjmp handleBit ;--- --- [2] make bit0 14 cycles long
+
+;----------------------------------------------------------------------------
+; Receiver loop (numbers in brackets are cycles within byte after instr)
+;----------------------------------------------------------------------------
+bitloop:
+ in x1, USBIN ;[0] sample line state
+ andi x1, USBMASK ;[1] filter only D+ and D- bits
+ breq se0 ;[2] both lines are low so handle se0
+handleBit:
+ cpse x1, x2 ;[3] when previous line state equals current line state, handle "1"
+ rjmp handle0 ;[4] when line state differs, handle "0"
+ sec ;[5]
+ ror shift ;[6] shift "1" into the data
+ brcs b6checkUnstuff ;[7] When after shift C is set, next bit is bit7
+ nop2 ;[8]
+ dec bitcnt ;[10]
+ brne bitloop ;[11]
+ ldi x1,0 ;[12] indicate unstuff for bit other than bit6 or bit7
+ in bitcnt, USBIN ;[0] sample stuff bit
+ rjmp unstuff ;[1]
+
+handle0:
+ mov x2, x1 ;[6] Set x2 to current line state
+ ldi bitcnt, 6 ;[7] reset unstuff counter.
+ lsr shift ;[8] shift "0" into the data
+ brcs bit7 ;[9] When after shift C is set, next bit is bit7
+ nop ;[10]
+ rjmp bitloop ;[11]
+
+;----------------------------------------------------------------------------
+; End of receive loop. Now start handling EOP
+;----------------------------------------------------------------------------
+
+macro POP_STANDARD ; 14 cycles
+ pop cnt
+ pop x4
+ pop x3
+ pop x2
+ pop x1
+ pop shift
+ pop bitcnt
+ endm
+macro POP_RETI ; 7 cycles
+ pop YH
+ pop YL
+ out SREG, YL
+ pop YL
+ endm
+
+
+
+#include "asmcommon.inc"
+
+; USB spec says:
+; idle = J
+; J = (D+ = 0), (D- = 1)
+; K = (D+ = 1), (D- = 0)
+; Spec allows 7.5 bit times from EOP to SOP for replies
+; 7.5 bit times is 100 cycles. This implementation arrives a bit later at se0
+; then specified in the include file but there is plenty of time
+
+bitstuffN:
+ eor x1, x4 ;[8]
+ ldi x2, 0 ;[9]
+ nop2 ;[10]
+ out USBOUT, x1 ;[12] <-- out
+ rjmp didStuffN ;[0]
+
+bitstuff7:
+ eor x1, x4 ;[6]
+ ldi x2, 0 ;[7] Carry is zero due to brcc
+ rol shift ;[8] compensate for ror shift at branch destination
+ nop2 ;[9]
+ rjmp didStuff7 ;[11]
+
+sendNakAndReti:
+ ldi x3, USBPID_NAK ;[-18]
+ rjmp sendX3AndReti ;[-17]
+sendAckAndReti:
+ ldi cnt, USBPID_ACK ;[-17]
+sendCntAndReti:
+ mov x3, cnt ;[-16]
+sendX3AndReti:
+ ldi YL, 20 ;[-15] x3==r20 address is 20
+ ldi YH, 0 ;[-14]
+ ldi cnt, 2 ;[-13]
+; rjmp usbSendAndReti fallthrough
+
+;usbSend:
+;pointer to data in 'Y'
+;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
+;uses: x1...x4, btcnt, shift, cnt, Y
+;Numbers in brackets are time since first bit of sync pattern is sent
+;We don't match the transfer rate exactly (don't insert leap cycles every third
+;byte) because the spec demands only 1.5% precision anyway.
+usbSendAndReti: ; 12 cycles until SOP
+ in x2, USBDDR ;[-12]
+ ori x2, USBMASK ;[-11]
+ sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
+ in x1, USBOUT ;[-8] port mirror for tx loop
+ out USBDDR, x2 ;[-7] <- acquire bus
+; need not init x2 (bitstuff history) because sync starts with 0
+ ldi x4, USBMASK ;[-6] exor mask
+ ldi shift, 0x80 ;[-5] sync byte is first byte sent
+txByteLoop:
+ ldi bitcnt, 0x49 ;[-4] [10] binary 01001001
+txBitLoop:
+ sbrs shift, 0 ;[-3] [10] [11]
+ eor x1, x4 ;[-2] [11] [12]
+ out USBOUT, x1 ;[-1] [12] [13] <-- out N
+ ror shift ;[0] [13] [14]
+ ror x2 ;[1]
+didStuffN:
+ nop2 ;[2]
+ nop ;[4]
+ cpi x2, 0xfc ;[5]
+ brcc bitstuffN ;[6]
+ lsr bitcnt ;[7]
+ brcc txBitLoop ;[8]
+ brne txBitLoop ;[9]
+
+ sbrs shift, 0 ;[10]
+ eor x1, x4 ;[11]
+didStuff7:
+ out USBOUT, x1 ;[-1] [13] <-- out 7
+ ror shift ;[0] [14]
+ ror x2 ;[1]
+ nop ;[2]
+ cpi x2, 0xfc ;[3]
+ brcc bitstuff7 ;[4]
+ ld shift, y+ ;[5]
+ dec cnt ;[7]
+ brne txByteLoop ;[8]
+;make SE0:
+ cbr x1, USBMASK ;[9] prepare SE0 [spec says EOP may be 25 to 30 cycles]
+ lds x2, usbNewDeviceAddr;[10]
+ lsl x2 ;[12] we compare with left shifted address
+ out USBOUT, x1 ;[13] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
+ subi YL, 20 + 2 ;[0] Only assign address on data packets, not ACK/NAK in x3
+ sbci YH, 0 ;[1]
+;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
+;set address only after data packet was sent, not after handshake
+ breq skipAddrAssign ;[2]
+ sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
+skipAddrAssign:
+;end of usbDeviceAddress transfer
+ ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
+ USB_STORE_PENDING(x2) ;[5]
+ ori x1, USBIDLE ;[6]
+ in x2, USBDDR ;[7]
+ cbr x2, USBMASK ;[8] set both pins to input
+ mov x3, x1 ;[9]
+ cbr x3, USBMASK ;[10] configure no pullup on both pins
+ ldi x4, 5 ;[11]
+se0Delay:
+ dec x4 ;[12] [15] [18] [21] [24]
+ brne se0Delay ;[13] [16] [19] [22] [25]
+ out USBOUT, x1 ;[26] <-- out J (idle) -- end of SE0 (EOP signal)
+ out USBDDR, x2 ;[27] <-- release bus now
+ out USBOUT, x3 ;[28] <-- ensure no pull-up resistors are active
+ rjmp doReturn
--- /dev/null
+/* Name: usbportability.h
+ * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
+ * Author: Christian Starkjohann
+ * Creation Date: 2008-06-17
+ * Tabsize: 4
+ * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: usbportability.h 740 2009-04-13 18:23:31Z cs $
+ */
+
+/*
+General Description:
+This header is intended to contain all (or at least most of) the compiler
+and library dependent stuff. The C code is written for avr-gcc and avr-libc.
+The API of other development environments is converted to gcc's and avr-libc's
+API by means of defines.
+
+This header also contains all system includes since they depend on the
+development environment.
+
+Thanks to Oleg Semyonov for his help with the IAR tools port!
+*/
+
+#ifndef __usbportability_h_INCLUDED__
+#define __usbportability_h_INCLUDED__
+
+/* We check explicitly for IAR and CodeVision. Default is avr-gcc/avr-libc. */
+
+/* ------------------------------------------------------------------------- */
+#if defined __IAR_SYSTEMS_ICC__ || defined __IAR_SYSTEMS_ASM__ /* check for IAR */
+/* ------------------------------------------------------------------------- */
+
+#ifndef ENABLE_BIT_DEFINITIONS
+# define ENABLE_BIT_DEFINITIONS 1 /* Enable bit definitions */
+#endif
+
+/* Include IAR headers */
+#include <ioavr.h>
+#ifndef __IAR_SYSTEMS_ASM__
+# include <inavr.h>
+#endif
+
+#define __attribute__(arg) /* not supported on IAR */
+
+#ifdef __IAR_SYSTEMS_ASM__
+# define __ASSEMBLER__ /* IAR does not define standard macro for asm */
+#endif
+
+#ifdef __HAS_ELPM__
+# define PROGMEM __farflash
+#else
+# define PROGMEM __flash
+#endif
+
+#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr))
+
+/* The following definitions are not needed by the driver, but may be of some
+ * help if you port a gcc based project to IAR.
+ */
+#define cli() __disable_interrupt()
+#define sei() __enable_interrupt()
+#define wdt_reset() __watchdog_reset()
+#define _BV(x) (1 << (x))
+
+/* assembler compatibility macros */
+#define nop2 rjmp $+2 /* jump to next instruction */
+#define XL r26
+#define XH r27
+#define YL r28
+#define YH r29
+#define ZL r30
+#define ZH r31
+#define lo8(x) LOW(x)
+#define hi8(x) (((x)>>8) & 0xff) /* not HIGH to allow XLINK to make a proper range check */
+
+/* Depending on the device you use, you may get problems with the way usbdrv.h
+ * handles the differences between devices. Since IAR does not use #defines
+ * for MCU registers, we can't check for the existence of a particular
+ * register with an #ifdef. If the autodetection mechanism fails, include
+ * definitions for the required USB_INTR_* macros in your usbconfig.h. See
+ * usbconfig-prototype.h and usbdrv.h for details.
+ */
+
+/* ------------------------------------------------------------------------- */
+#elif __CODEVISIONAVR__ /* check for CodeVision AVR */
+/* ------------------------------------------------------------------------- */
+/* This port is not working (yet) */
+
+/* #define F_CPU _MCU_CLOCK_FREQUENCY_ seems to be defined automatically */
+
+#include <io.h>
+#include <delay.h>
+
+#define __attribute__(arg) /* not supported on IAR */
+
+#define PROGMEM __flash
+#define USB_READ_FLASH(addr) (*(PROGMEM char *)(addr))
+
+#ifndef __ASSEMBLER__
+static inline void cli(void)
+{
+ #asm("cli");
+}
+static inline void sei(void)
+{
+ #asm("sei");
+}
+#endif
+#define _delay_ms(t) delay_ms(t)
+#define _BV(x) (1 << (x))
+#define USB_CFG_USE_SWITCH_STATEMENT 1 /* macro for if() cascase fails for unknown reason */
+
+#define macro .macro
+#define endm .endmacro
+#define nop2 rjmp .+0 /* jump to next instruction */
+
+/* ------------------------------------------------------------------------- */
+#else /* default development environment is avr-gcc/avr-libc */
+/* ------------------------------------------------------------------------- */
+
+#include <avr/io.h>
+#ifdef __ASSEMBLER__
+# define _VECTOR(N) __vector_ ## N /* io.h does not define this for asm */
+#else
+# include <avr/pgmspace.h>
+#endif
+
+#define USB_READ_FLASH(addr) pgm_read_byte(addr)
+
+#define macro .macro
+#define endm .endm
+#define nop2 rjmp .+0 /* jump to next instruction */
+
+#endif /* development environment */
+
+/* for conveniecne, ensure that PRG_RDB exists */
+#ifndef PRG_RDB
+# define PRG_RDB(addr) USB_READ_FLASH(addr)
+#endif
+#endif /* __usbportability_h_INCLUDED__ */
--- /dev/null
+LIBUSB = d:/dev/LibUSB-Win32
+KAZZO = ../firmware
+
+OBJECT = opendevice.o hostecho.o usbdevice.o ihex.o file.o
+
+CC = gcc
+CFLAG = -I$(LIBUSB)/include -I$(KAZZO) -Wall -Werror
+CFLAG += -O2 -DDEBUG=0
+#CFLAG += -O0 -g -DDEBUG=1
+LIB = -L$(LIBUSB)/lib/gcc -lusb
+
+PROGRAM = ../kazzo_test.exe
+
+all: $(PROGRAM)
+
+.c.o:
+ $(CC) $(CFLAG) -c $<
+
+$(PROGRAM): $(OBJECT)
+ $(CC) -o $(PROGRAM) $(OBJECT) $(LIB)
+
+clean:
+ rm -f *.o $(PROGRAM)
+hostecho.o: $(KAZZO)/kazzo_request.h
--- /dev/null
+#include <assert.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <usb.h>
+#include <kazzo_request.h>
+#include "ihex.h"
+#include "file.h"
+#include "usbdevice.h"
+
+static void echo(usb_dev_handle *handle)
+{
+ char buffer[4];
+ int i, cnt;
+ srand(4649);
+ for(i = 0; i < 5000; i++){
+ int value = rand() & 0xffff, index = rand() & 0xffff;
+ int rxValue, rxIndex;
+ if((i+1) % 100 == 0){
+ fprintf(stderr, "\r%05d", i+1);
+ fflush(stderr);
+ }
+ cnt = usb_control_msg(
+ handle,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_IN,
+ REQUEST_ECHO, value,
+ index, buffer, sizeof(buffer), 4000
+ );
+ if(cnt < 0){
+ fprintf(stderr, "\nUSB error in iteration %d: %s\n", i, usb_strerror());
+ break;
+ }else if(cnt != 4){
+ fprintf(stderr, "\nerror in iteration %d: %d bytes received instead of 4\n", i, cnt);
+ break;
+ }
+ rxValue = ((int)buffer[0] & 0xff) | (((int)buffer[1] & 0xff) << 8);
+ rxIndex = ((int)buffer[2] & 0xff) | (((int)buffer[3] & 0xff) << 8);
+ if(rxValue != value || rxIndex != index){
+ fprintf(stderr, "\ndata error in iteration %d:\n", i);
+ fprintf(stderr, "rxValue = 0x%04x value = 0x%04x\n", rxValue, value);
+ fprintf(stderr, "rxIndex = 0x%04x index = 0x%04x\n", rxIndex, index);
+ }
+ }
+ printf("\nTest completed.\n");
+}
+
+static bool hex_load(const char *file, long firmsize, uint8_t *image)
+{
+ FILE *f;
+ char s[0x80];
+ f = fopen(file, "r");
+ if(f == NULL){
+ return false;
+ }
+ fseek(f, 0, SEEK_SET);
+
+ struct record *t = ihex_new();
+ bool ret = true;
+ while(fgets(s, 0x80, f) != NULL){
+ if(ihex_load(s, t) == false){
+ ret = false;
+ break;
+ }
+ ihex_write(t, firmsize, image);
+ }
+ ihex_destory(t);
+ return ret;
+}
+static void snrom_wram_open(usb_dev_handle *handle)
+{
+ uint8_t t[5];
+ t[0] = 0x80;
+ write_memory(handle, REQUEST_CPU_WRITE_6502, INDEX_IMPLIED, 0x8000, 1, t);
+ t[0] = 0, t[1] = 0, t[2] = 0, t[3] = 1, t[4] = 0;
+ write_memory(handle, REQUEST_CPU_WRITE_6502, INDEX_IMPLIED, 0x8000, sizeof(t), t);
+ t[0] = 0, t[1] = 0, t[2] = 0, t[3] = 0, t[4] = 0;
+ write_memory(handle, REQUEST_CPU_WRITE_6502, INDEX_IMPLIED, 0xe000, sizeof(t), t);
+ write_memory(handle, REQUEST_CPU_WRITE_6502, INDEX_IMPLIED, 0xa000, sizeof(t), t);
+}
+
+static void snrom_wram_close(usb_dev_handle *handle)
+{
+ const uint8_t t[5] = {0, 0, 0, 0, 1}; //lsb -> msb
+ write_memory(handle, REQUEST_CPU_WRITE_6502, INDEX_IMPLIED, 0xe000, sizeof(t), t);
+ write_memory(handle, REQUEST_CPU_WRITE_6502, INDEX_IMPLIED, 0xa000, sizeof(t), t);
+}
+
+static int cartridge_ram_transform(usb_dev_handle *handle, const uint8_t *firmware, enum request w, enum request r, long address, long length, bool dump)
+{
+ uint8_t *compare;
+ compare = malloc(length);
+ write_memory(handle, w, INDEX_IMPLIED, address, length, firmware);
+ read_memory(handle, r, INDEX_IMPLIED, address, length, compare);
+ int ret = memcmp(firmware, compare, length);
+ if(dump == true){
+ int i;
+ uint8_t *t = compare;
+ for(i = 0; i < length; i += 0x10){
+ int j;
+ printf("%06x:", i);
+ for(j = 0; j < 0x10; j++){
+ const char *safix;
+ switch(j){
+ case 7:
+ safix = "-";
+ break;
+ case 0x0f:
+ safix = "\n";
+ break;
+ default:
+ safix = " ";
+ break;
+ }
+ printf("%02x%s", *t, safix);
+ t++;
+ }
+ }
+ }
+ free(compare);
+ return ret;
+}
+static void firmware_update(usb_dev_handle *handle, const char *file)
+{
+ uint8_t *firmware;
+ const int firmsize = 0x3800;
+ assert(firmsize <= 0x3800);
+ firmware = malloc(firmsize);
+ memset(firmware, 0xff, firmsize);
+
+ if(hex_load(file, firmsize, firmware) == false){
+ puts("image open error!");
+ goto end;
+ }
+ snrom_wram_open(handle);
+
+ int ppu, cpu = 0;
+ ppu = cartridge_ram_transform(handle, firmware, REQUEST_PPU_WRITE, REQUEST_PPU_READ, 0x0000, 0x2000, false);
+ if(firmsize >= 0x2000){
+ cpu = cartridge_ram_transform(handle, firmware + 0x2000, REQUEST_CPU_WRITE_6502, REQUEST_CPU_READ, 0x6000, firmsize - 0x2000, false);
+ }
+ if((ppu == 0) && (cpu == 0)){
+// write_memory(handle, REQUEST_FIRMWARE_PROGRAM, firmsize, 0x2000, 0, firmware);
+ puts("USB connection will be disconnteced. This is normally.");
+ puts("Re-turn on kazzo's power.");
+ write_memory(handle, REQUEST_FIRMWARE_PROGRAM, firmsize, 0x0000, 0, firmware);
+ }else{
+ puts("firmware transform error!");
+ snrom_wram_close(handle);
+ }
+end:
+ free(firmware);
+}
+enum{
+ FIRM_VERSION_OFFSET = 0x3780,
+ BOOTLOADER_VERSION_OFFSET = 0x3d00
+};
+static void firmware_verify(usb_dev_handle *handle, const char *file)
+{
+ uint8_t *firmware, *compare;
+ const int firmsize = 0x3800;
+ assert(firmsize <= 0x3800);
+ firmware = malloc(firmsize);
+ compare = malloc(firmsize);
+ memset(compare, 0xff, firmsize);
+// if(buf_load(compare, file, firmsize) == false){
+ if(hex_load(file, firmsize, compare) == false){
+ puts("image open error!");
+ goto end;
+ }
+ read_memory(handle, REQUEST_FIRMWARE_DOWNLOAD, INDEX_IMPLIED, 0, firmsize, firmware);
+ if(memcmp(firmware, compare, firmsize) == 0){
+ puts("firmware compare ok!");
+ }else{
+ puts("firmware compare ng!");
+ printf("hex: %s\n", compare + FIRM_VERSION_OFFSET);
+ printf("avr: %s\n", firmware + FIRM_VERSION_OFFSET);
+ }
+end:
+ free(firmware);
+ free(compare);
+}
+static void firmware_download(usb_dev_handle *handle, const char *file)
+{
+ const int firmsize = 0x4000;
+ uint8_t *firmware = malloc(firmsize);
+ read_memory(handle, REQUEST_FIRMWARE_DOWNLOAD, INDEX_IMPLIED, 0, firmsize, firmware);
+ buf_save(firmware, file, firmsize);
+ puts(firmware + FIRM_VERSION_OFFSET);
+ free(firmware);
+}
+
+static void firmware_version(usb_dev_handle *handle)
+{
+ char version[VERSION_STRING_SIZE];
+ read_memory(handle, REQUEST_FIRMWARE_VERSION, INDEX_IMPLIED, 0, VERSION_STRING_SIZE, (uint8_t *) version);
+ puts(version);
+}
+
+static bool ppu_read(usb_dev_handle *handle, int seed)
+{
+ int i;
+ int ret = 0;
+ const int bufsize = 0x80;
+ uint8_t *t, *buf = malloc(bufsize);
+/* t = buf;
+ for(i = 0; i < bufsize; i++){
+ *t = i;
+ t++;
+ }
+ ret |= cartridge_ram_transform(handle, buf, REQUEST_PPU_WRITE, REQUEST_PPU_READ, 0x0000, bufsize, false);*/
+/* if(ret == 0){
+ puts("increment ok");
+ }else{
+ puts("increment ng");
+ }*/
+
+ t = buf;
+ srand(5555 * seed);
+ for(i = 0; i < bufsize; i++){
+ *t = rand() & 0xff;
+ t++;
+ }
+ ret |= cartridge_ram_transform(handle, buf, REQUEST_PPU_WRITE, REQUEST_PPU_READ, 0x0000, bufsize, false);
+/* if(ret == 0){
+ puts("ramdom ok");
+ }else{
+ puts("ramdom ng");
+ }*/
+ t = buf;
+ free(buf);
+ return ret == 0;
+}
+int main(int c, char **v)
+{
+ usb_init();
+ usb_dev_handle *handle = device_open();
+
+ if(handle == NULL){
+ return 0;
+ }
+ switch(c){
+ case 1:
+ echo(handle);
+ printf("work time %3.1f second\n", ((double) clock() / (double) CLOCKS_PER_SEC));
+ fflush(stdout);
+ system("pause");
+ break;
+ case 2:
+ firmware_version(handle);
+ break;
+ case 3:
+ switch(v[1][0]){
+ case 'w':
+ firmware_update(handle, v[2]);
+ break;
+ case 'r':
+ firmware_download(handle, v[2]);
+ break;
+ case 'v':
+ firmware_verify(handle, v[2]);
+ break;
+ case 'p':{
+ if(DEBUG == 0){
+ break;
+ }
+ int i = 0x1000;
+ const char *ret = "test ok";
+ while(i != 0){
+ if(ppu_read(handle, i) == false){
+ ret = "test ng";
+ break;
+ }
+ if((i+1) % 100 == 0){
+ fprintf(stderr, "\r%05d", i+1);
+ fflush(stderr);
+ }
+ i--;
+ }
+ puts(ret);
+ }break;
+ case 'd':
+ if(DEBUG == 1){
+ write_memory(handle, REQUEST_FIRMWARE_PROGRAM, 0x200, 0x0000, 0, NULL);
+ }
+ break;
+ }
+ break;
+ }
+ usb_close(handle);
+ return 0;
+}
--- /dev/null
+#include <stdio.h>
+#include "opendevice.h"
+
+enum{
+ MATCH_SUCCESS = 1,
+ MATCH_FAILED = 0,
+ MATCH_ABORT = -1
+};
+/* private interface: match text and p, return MATCH_SUCCESS, MATCH_FAILED, or MATCH_ABORT. */
+static int _shellStyleMatch(char *text, char *p)
+{
+ int last, matched, reverse;
+
+ for(; *p; text++, p++){
+ if(*text == 0 && *p != '*')
+ return MATCH_ABORT;
+ switch(*p){
+ case '\\':
+ /* Literal match with following character. */
+ p++;
+ /* FALLTHROUGH */
+ default:
+ if(*text != *p)
+ return MATCH_FAILED;
+ continue;
+ case '?':
+ /* Match anything. */
+ continue;
+ case '*':
+ while(*++p == '*')
+ /* Consecutive stars act just like one. */
+ continue;
+ if(*p == 0)
+ /* Trailing star matches everything. */
+ return MATCH_SUCCESS;
+ while(*text)
+ if((matched = _shellStyleMatch(text++, p)) != MATCH_FAILED)
+ return matched;
+ return MATCH_ABORT;
+ case '[':
+ reverse = p[1] == '^';
+ if(reverse) /* Inverted character class. */
+ p++;
+ matched = MATCH_FAILED;
+ if(p[1] == ']' || p[1] == '-')
+ if(*++p == *text)
+ matched = MATCH_SUCCESS;
+ for(last = *p; *++p && *p != ']'; last = *p)
+ if (*p == '-' && p[1] != ']' ? *text <= *++p && *text >= last : *text == *p)
+ matched = MATCH_SUCCESS;
+ if(matched == reverse)
+ return MATCH_FAILED;
+ continue;
+ }
+ }
+ return *text == 0;
+}
+
+/* public interface for shell style matching: returns 0 if fails, 1 if matches */
+static int shellStyleMatch(char *text, char *pattern)
+{
+ if(pattern == NULL) /* NULL pattern is synonymous to "*" */
+ return 1;
+ return _shellStyleMatch(text, pattern) == MATCH_SUCCESS;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int usbGetStringAscii(usb_dev_handle *dev, int index, char *buf, int buflen)
+{
+char buffer[256];
+int rval, i;
+
+ if((rval = usb_get_string_simple(dev, index, buf, buflen)) >= 0) /* use libusb version if it works */
+ return rval;
+ if((rval = usb_control_msg(dev, USB_ENDPOINT_IN, USB_REQ_GET_DESCRIPTOR, (USB_DT_STRING << 8) + index, 0x0409, buffer, sizeof(buffer), 5000)) < 0)
+ return rval;
+ if(buffer[1] != USB_DT_STRING){
+ *buf = 0;
+ return 0;
+ }
+ if((unsigned char)buffer[0] < rval)
+ rval = (unsigned char)buffer[0];
+ rval /= 2;
+ /* lossy conversion to ISO Latin1: */
+ for(i=1;i<rval;i++){
+ if(i > buflen) /* destination buffer overflow */
+ break;
+ buf[i-1] = buffer[2 * i];
+ if(buffer[2 * i + 1] != 0) /* outside of ISO Latin1 range */
+ buf[i-1] = '?';
+ }
+ buf[i-1] = 0;
+ return i-1;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int usbOpenDevice(
+ usb_dev_handle **device, int vendorID, char *vendorNamePattern,
+ int productID, char *productNamePattern,
+ char *serialNamePattern, FILE *printMatchingDevicesFp,
+ FILE *warningsFp
+)
+{
+ struct usb_bus *bus;
+ struct usb_device *dev;
+ usb_dev_handle *handle = NULL;
+ int errorCode = USBOPEN_ERR_NOTFOUND;
+
+ usb_find_busses();
+ usb_find_devices();
+ for(bus = usb_get_busses(); bus; bus = bus->next){
+ for(dev = bus->devices; dev; dev = dev->next){ /* iterate over all devices on all busses */
+ if((vendorID == 0 || dev->descriptor.idVendor == vendorID)
+ && (productID == 0 || dev->descriptor.idProduct == productID)){
+ char vendor[256], product[256], serial[256];
+ int len;
+ handle = usb_open(dev); /* we need to open the device in order to query strings */
+ if(!handle){
+ errorCode = USBOPEN_ERR_ACCESS;
+ if(warningsFp != NULL)
+ fprintf(warningsFp, "Warning: cannot open VID=0x%04x PID=0x%04x: %s\n", dev->descriptor.idVendor, dev->descriptor.idProduct, usb_strerror());
+ continue;
+ }
+ /* now check whether the names match: */
+ len = vendor[0] = 0;
+ if(dev->descriptor.iManufacturer > 0){
+ len = usbGetStringAscii(handle, dev->descriptor.iManufacturer, vendor, sizeof(vendor));
+ }
+ if(len < 0){
+ errorCode = USBOPEN_ERR_ACCESS;
+ if(warningsFp != NULL)
+ fprintf(warningsFp, "Warning: cannot query manufacturer for VID=0x%04x PID=0x%04x: %s\n", dev->descriptor.idVendor, dev->descriptor.idProduct, usb_strerror());
+ }else{
+ errorCode = USBOPEN_ERR_NOTFOUND;
+ /* printf("seen device from vendor ->%s<-\n", vendor); */
+ if(shellStyleMatch(vendor, vendorNamePattern)){
+ len = product[0] = 0;
+ if(dev->descriptor.iProduct > 0){
+ len = usbGetStringAscii(handle, dev->descriptor.iProduct, product, sizeof(product));
+ }
+ if(len < 0){
+ errorCode = USBOPEN_ERR_ACCESS;
+ if(warningsFp != NULL)
+ fprintf(warningsFp, "Warning: cannot query product for VID=0x%04x PID=0x%04x: %s\n", dev->descriptor.idVendor, dev->descriptor.idProduct, usb_strerror());
+ }else{
+ errorCode = USBOPEN_ERR_NOTFOUND;
+ /* printf("seen product ->%s<-\n", product); */
+ if(shellStyleMatch(product, productNamePattern)){
+ len = serial[0] = 0;
+ if(dev->descriptor.iSerialNumber > 0){
+ len = usbGetStringAscii(handle, dev->descriptor.iSerialNumber, serial, sizeof(serial));
+ }
+ if(len < 0){
+ errorCode = USBOPEN_ERR_ACCESS;
+ if(warningsFp != NULL)
+ fprintf(warningsFp, "Warning: cannot query serial for VID=0x%04x PID=0x%04x: %s\n", dev->descriptor.idVendor, dev->descriptor.idProduct, usb_strerror());
+ }
+ if(shellStyleMatch(serial, serialNamePattern)){
+ if(printMatchingDevicesFp != NULL){
+ if(serial[0] == 0){
+ fprintf(printMatchingDevicesFp, "VID=0x%04x PID=0x%04x vendor=\"%s\" product=\"%s\"\n", dev->descriptor.idVendor, dev->descriptor.idProduct, vendor, product);
+ }else{
+ fprintf(printMatchingDevicesFp, "VID=0x%04x PID=0x%04x vendor=\"%s\" product=\"%s\" serial=\"%s\"\n", dev->descriptor.idVendor, dev->descriptor.idProduct, vendor, product, serial);
+ }
+ }else{
+ break;
+ }
+ }
+ }
+ }
+ }
+ }
+ usb_close(handle);
+ handle = NULL;
+ }
+ }
+ if(handle) /* we have found a deice */
+ break;
+ }
+ if(handle != NULL){
+ errorCode = 0;
+ *device = handle;
+ }
+ if(printMatchingDevicesFp != NULL) /* never return an error for listing only */
+ errorCode = 0;
+ return errorCode;
+}
+
+/* ------------------------------------------------------------------------- */
--- /dev/null
+/* Name: opendevice.h
+ * Project: V-USB host-side library
+ * Author: Christian Starkjohann
+ * Creation Date: 2008-04-10
+ * Tabsize: 4
+ * Copyright: (c) 2008 by OBJECTIVE DEVELOPMENT Software GmbH
+ * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
+ * This Revision: $Id: opendevice.h 755 2009-08-03 17:01:21Z cs $
+ */
+
+/*
+General Description:
+This module offers additional functionality for host side drivers based on
+libusb or libusb-win32. It includes a function to find and open a device
+based on numeric IDs and textual description. It also includes a function to
+obtain textual descriptions from a device.
+
+To use this functionality, simply copy opendevice.c and opendevice.h into your
+project and add them to your Makefile. You may modify and redistribute these
+files according to the GNU General Public License (GPL) version 2 or 3.
+*/
+
+#ifndef __OPENDEVICE_H_INCLUDED__
+#define __OPENDEVICE_H_INCLUDED__
+
+#include <usb.h> /* this is libusb, see http://libusb.sourceforge.net/ */
+#include <stdio.h>
+
+int usbGetStringAscii(usb_dev_handle *dev, int index, char *buf, int buflen);
+/* This function gets a string descriptor from the device. 'index' is the
+ * string descriptor index. The string is returned in ISO Latin 1 encoding in
+ * 'buf' and it is terminated with a 0-character. The buffer size must be
+ * passed in 'buflen' to prevent buffer overflows. A libusb device handle
+ * must be given in 'dev'.
+ * Returns: The length of the string (excluding the terminating 0) or
+ * a negative number in case of an error. If there was an error, use
+ * usb_strerror() to obtain the error message.
+ */
+
+int usbOpenDevice(usb_dev_handle **device, int vendorID, char *vendorNamePattern, int productID, char *productNamePattern, char *serialNamePattern, FILE *printMatchingDevicesFp, FILE *warningsFp);
+/* This function iterates over all devices on all USB busses and searches for
+ * a device. Matching is done first by means of Vendor- and Product-ID (passed
+ * in 'vendorID' and 'productID'. An ID of 0 matches any numeric ID (wildcard).
+ * When a device matches by its IDs, matching by names is performed. Name
+ * matching can be done on textual vendor name ('vendorNamePattern'), product
+ * name ('productNamePattern') and serial number ('serialNamePattern'). A
+ * device matches only if all non-null pattern match. If you don't care about
+ * a string, pass NULL for the pattern. Patterns are Unix shell style pattern:
+ * '*' stands for 0 or more characters, '?' for one single character, a list
+ * of characters in square brackets for a single character from the list
+ * (dashes are allowed to specify a range) and if the lis of characters begins
+ * with a caret ('^'), it matches one character which is NOT in the list.
+ * Other parameters to the function: If 'warningsFp' is not NULL, warning
+ * messages are printed to this file descriptor with fprintf(). If
+ * 'printMatchingDevicesFp' is not NULL, no device is opened but matching
+ * devices are printed to the given file descriptor with fprintf().
+ * If a device is opened, the resulting USB handle is stored in '*device'. A
+ * pointer to a "usb_dev_handle *" type variable must be passed here.
+ * Returns: 0 on success, an error code (see defines below) on failure.
+ */
+
+/* usbOpenDevice() error codes: */
+#define USBOPEN_SUCCESS 0 /* no error */
+#define USBOPEN_ERR_ACCESS 1 /* not enough permissions to open device */
+#define USBOPEN_ERR_IO 2 /* I/O error */
+#define USBOPEN_ERR_NOTFOUND 3 /* device not found */
+
+
+/* Obdev's free USB IDs, see USB-IDs-for-free.txt for details */
+
+#define USB_VID_OBDEV_SHARED 5824 /* obdev's shared vendor ID */
+#define USB_PID_OBDEV_SHARED_CUSTOM 1500 /* shared PID for custom class devices */
+#define USB_PID_OBDEV_SHARED_HID 1503 /* shared PID for HIDs except mice & keyboards */
+#define USB_PID_OBDEV_SHARED_CDCACM 1505 /* shared PID for CDC Modem devices */
+#define USB_PID_OBDEV_SHARED_MIDI 1508 /* shared PID for MIDI class devices */
+
+#endif /* __OPENDEVICE_H_INCLUDED__ */
--- /dev/null
+#include <stdio.h>
+#include <stdint.h>
+#include <usb.h>
+#include <kazzo_request.h>
+#include "opendevice.h"
+#include "usbconfig.h"
+
+enum{
+ TIMEOUT = 4000
+};
+usb_dev_handle *device_open(void)
+{
+ usb_dev_handle *handle = NULL;
+ const unsigned char rawVid[2] = {USB_CFG_VENDOR_ID};
+ const unsigned char rawPid[2] = {USB_CFG_DEVICE_ID};
+ char vendor[] = {USB_CFG_VENDOR_NAME, 0};
+ char product[] = {USB_CFG_DEVICE_NAME, 0};
+ int vid, pid;
+
+ /* compute VID/PID from usbconfig.h so that there is a central source of information */
+ vid = (rawVid[1] << 8) | rawVid[0];
+ pid = (rawPid[1] << 8) | rawPid[0];
+
+ if(usbOpenDevice(&handle, vid, vendor, pid, product, NULL, NULL, NULL) == 0){
+ return handle;
+ }
+ fprintf(stderr, "Could not find USB device \"%s\" with vid=0x%x pid=0x%x\n", product, vid, pid);
+ return NULL;
+}
+
+//-------- read sequence --------
+static void device_read(usb_dev_handle *handle, enum request r, enum index index, long address, long length, uint8_t *data)
+{
+ int cnt = usb_control_msg(
+ handle,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_IN,
+ r, address,
+ index, data, length, TIMEOUT
+ );
+ if(cnt != length){
+ puts(__FUNCTION__);
+ puts(usb_strerror());
+ exit(1);
+ }
+}
+void read_memory(usb_dev_handle *handle, const enum request r, enum index index, long address, long length, uint8_t *data)
+{
+ const int packet = READ_PACKET_SIZE;
+ while(length >= packet){
+ device_read(handle, r, index, address, packet, data);
+ data += packet;
+ address += packet;
+ length -= packet;
+ }
+ if(length != 0){
+ device_read(handle, r, index, address, length, data);
+ }
+}
+//-------- write sequence --------
+/*
+When host send data that contains 0xff many times, v-usb losts some
+bits. To prevent losting bits, mask data xor 0xa5;
+*/
+static void device_write(usb_dev_handle *handle, enum request w, enum index index, long address, long length, const uint8_t *data)
+{
+ uint8_t *d = malloc(length);
+ int i;
+ memcpy(d, data, length);
+ for(i = 0; i < length; i++){
+ d[i] ^= 0xa5;
+ }
+ int cnt = usb_control_msg(
+ handle,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_ENDPOINT_OUT,
+ w, address,
+ index, d, length, TIMEOUT
+ );
+ if(0 && cnt != length){
+ puts(__FUNCTION__);
+ puts(usb_strerror());
+ exit(1);
+ }
+ free(d);
+}
+
+void write_memory(usb_dev_handle *handle, enum request r, enum index index, long address, long length, const uint8_t *data)
+{
+ //To accept length == 0, use do-while loop
+ do{
+ long l = length >= FLASH_PACKET_SIZE ? FLASH_PACKET_SIZE : length;
+ device_write(handle, r, index, address, l, data);
+ address += l;
+ data += l;
+ length -= l;
+ }while(length != 0);
+}
--- /dev/null
+#ifndef _USBDEVICE_H_
+#define _USBDEVICE_H_
+usb_dev_handle *device_open(void);
+void read_memory(usb_dev_handle *handle, const enum request r, enum index index, long address, long length, uint8_t *data);
+void write_memory(usb_dev_handle *handle, enum request r, enum index index, long address, long length, const uint8_t *data);
+#endif
--- /dev/null
+----AVR fusebit configuration----
+ATmega164P: low byte 0xee, high byte 0xd9, extended byte 0xff
+ CKDIV8:1 CKOUT:1 SUT:10 CKSEL:1110
+ OCDEN:1 JTAGEN:1 SPIEN:0 WDTON:1 EESAVE:1 BOOTSZ:00 BOOTRST:1
+ BODLEVEL:111
+ATmega16: low byte 0xae, high byte 0xc9
+ BODLEVEL:1 BODEN:0 SUT:10 CKSEL:1110
+ OCDEN:1 JTAGEN:1 SPIEN:0 CKOPT:0 EESAVE:1 BOOTSZ:00 BOOTRST:1
+
+----list of parts-----
+# |name
+-----+-------------------
+U1 |ATmega164P or ATmega16
+U2 |74HC574
+CN1 |type B female USB socket
+CN2 |3x2 pin header, 2.54 mm spacing
+CN3 |30x2 pin cartridge connector, 2.54 mm spacing
+R1,R2|68 ohm register
+R3 |1.5 kohm register
+R4 |30 kohm register
+D1,D2|3.6 V zener diode
+X1 |16.0 MHz ceramic resonator
+C1,C2|0.1uF ceramic capacitor
+CP1 |10uF electric capacitor
+JP1 |toggle switch
+JP2 |push switch
+
+----pin assignment----
+See the schematics file for switch, register, diode and capacitor connection.
+
+CN3: cartridge connector CN1: USB socket type B
+ +-----+ +---+ U1: ATmega164P (DIP)
+ GND| 1 31|+5V +5V|1 4|GND +--v--+
+ CPU A11| 2 32|CPU PHI2 D-|2 3|D+ D0| 1 40|A0
+ CPU A10| 3 33|CPU A12 +---+ D1| 2 39|A1
+ CPU A9| 4 34|CPU A13 CN2: ISP connector D2| 3 38|A2
+ CPU A8| 5 35|CPU A14 +---+ D3| 4 37|A3
+ CPU A7| 6 36|CPU D7 MISO|1 2|Vcc D4| 5 36|A4
+ CPU A6| 7 37|CPU D6 SCK|3 4|MOSI MOSI/D5| 6 35|A5
+ CPU A5| 8 38|CPU D5 Reset#|5 6|GND MISO/D6| 7 34|A6
+ CPU A4| 9 39|CPU D4 +---+ SCK/D7| 8 33|A7
+ CPU A3|10 40|CPU D3 U2: 74HC574 Reset#| 9 32|+5V
+ CPU A2|11 41|CPU D2 +--v--+ Vcc|10 31|GND
+ CPU A1|12 42|CPU D1 GND| 1 20|Vcc GND|11 30|+5V
+ CPU A0|13 43|CPU D0 D0| 2 19|A8 XTAL1|12 29|AHL
+ CPU R/W|14 44|CPU ROMCS# D1| 3 18|A9 XTAL2|13 28|VRAM CS#
+CPU IRQ#|15 45|SOUND IN D2| 4 17|A10 NC|14 27|PPU WR#
+ GND|16 46|SOUND OUT D3| 5 16|A11 NC|15 26|PPU RD#
+ PPU RD#|17 47|PPU WR# D4| 6 15|A12 USB D+|16 25|NC
+VRAM A10|18 48|VRAM CS# D5| 7 14|A13 CPU IRQ#|17 24|CPU R/W
+ PPU A6|19 49|PPU A13# D6| 8 13|CPU A14 USB D-|18 23|CPU ROMCS#
+ PPU A5|20 50|PPU A7 D7| 9 12|PPU A13# VRAM A10|19 22|CPU PHI2
+ PPU A4|21 51|PPU A8 GND|10 11|AHL NC|20 21|NC
+ PPU A3|22 52|PPU A9 +-----+ +-----+
+ PPU A2|23 53|PPU A10
+ PPU A1|24 54|PPU A11
+ PPU A0|25 55|PPU A12
+ PPU D0|26 56|PPU A13
+ PPU D1|27 57|PPU D7
+ PPU D2|28 58|PPU D6
+ PPU D3|29 59|PPU D5
+ +5V|30 60|PPU D4
+ +-----+
+
+----notice----
+- AHL is Address High Latch.
+- NC is No Connection.
+- # is negative logic signal.
+- D0-D7 are data buses.
+-- shared by U1, U2, CN3(CPU and PPU).
+-- D5-D7 are shared by ISP signal.
+- A0-A13 are address buses.
+-- A0-A7 are shared by U1, CN3(CPU and PPU)
+-- A8-A13 are shared by U2, CN3(CPU and PPU)
+- CPU A14 and PPU A13# are unique address buses.
+- U1 can substitute ATmega16.
+- SOUND IN and SOUND OUT have no connection.
+- If a power switch is unnecessary, short JP1.
+- If a reset switch is unnecessary, open JP2.
--- /dev/null
+----AVR fusebit configuration----
+ATmega168: low byte 0xee, high byte 0xdf, extended byte 0xff
+ CKDIV8:1 CKOUT:1 SUT:10 CKSEL:1110
+ RSTDISBL:1 DWEN:1 SPIEN:0 WDTON:1 EESAVE:1 BODLEVEL:111
+ BOOTSZ:11 BOOTRST:1
+
+----list of parts-----
+# |name
+-----+-------------------
+U1 |ATmega168(P)
+U2,U3|74HC574
+CN1 |type B female USB socket
+CN2 |3x2 pin header, 2.54 mm spacing
+CN3 |30x2 pin cardedge connector, 2.54 mm spacing
+CN4 |36x2 pin cardedge connector, 2.54 mm spacing
+R1,R2|68 ohm register
+R3 |1.5 kohm register
+R4 |30 kohm register
+D1,D2|3.6 V zener diode
+X1 |16.0 MHz ceramic resonator
+C1,C2,C3|0.1uF ceramic capacitor
+CP1 |10uF electric capacitor
+JP1 |toggle switch
+JP2 |push switch
+
+----pin assignment----
+See schematics for switch, register, diode and capacitor connection.
+
+ U1: ATmega168 (DIP) U2: 74HC574 CN1: USB socket type B
+ +--v--+ +--v--+ +---+
+ Reset#| 1 28|PPU WR# GND| 1 20|Vcc +5V|1 4|GND
+ D0| 2 27|PPU RD# D0| 2 19|A8 D-|2 3|D+
+ D1| 3 26|CPU R/W D1| 3 18|A9 +---+
+ D2| 4 25|CPU ROMCS# D2| 4 17|A10 CN2: ISP conncetor
+ D3| 5 24|CPU PHI2 D3| 5 16|A11 +---+
+ D4| 6 23|CPU IRQ# D4| 6 15|A12 MISO|1 2|Vcc
+ Vcc| 7 22|GND D5| 7 14|A13 SCK|3 4|MOSI
+ GND| 8 21|+5V D6| 8 13|CPU A14 Reset#|5 6|GND
+ XTAL1| 9 20|+5V D7| 9 12|PPU A13# +---+
+ XTAL2|10 19|SCK/AHL GND|10 11|AHL
+ D5|11 18|MISO/ALL +-----+
+ D6|12 17|MOSI/VRAM CS# U3: 74HC574
+ D7|13 16|VRAM A10 +--v--+
+ USB D+|14 15|USB D- GND| 1 20|Vcc
+ +-----+ D0| 2 19|A0
+ D1| 3 18|A1
+ D2| 4 17|A2
+ D3| 5 16|A3
+ D4| 6 15|A4
+ D5| 7 14|A5
+ D6| 8 13|A6
+ D7| 9 12|A7
+ GND|10 11|ALL
+ +-----+
+
+CN3: cartridge connector CN4: cartridge connector
+ +-----+ +-----+
+ GND| 1 31|+5V +5V|36 72|GND
+ CPU A11| 2 32|CPU PHI2 CIC S1|35 71|CIC CLOCK
+ CPU A10| 3 33|CPU A12 CIC S0|34 70|CIC S2
+ CPU A9| 4 34|CPU A13 PPU D3|33 69|PPU D4
+ CPU A8| 5 35|CPU A14 PPU D2|32 68|PPU D5
+ CPU A7| 6 36|CPU D7 PPU D1|31 67|PPU D6
+ CPU A6| 7 37|CPU D6 PPU D0|30 66|PPU D7
+ CPU A5| 8 38|CPU D5 PPU A0|29 65|PPU A13
+ CPU A4| 9 39|CPU D4 PPU A1|28 64|PPU A12
+ CPU A3|10 40|CPU D3 PPU A2|27 63|PPU A10
+ CPU A2|11 41|CPU D2 PPU A3|26 62|PPU A11
+ CPU A1|12 42|CPU D1 PPU A4|25 61|PPU A9
+ CPU A0|13 43|CPU D0 PPU A5|24 60|PPU A8
+ CPU R/W|14 44|CPU ROMCS# PPU A6|23 59|PPU A7
+CPU IRQ#|15 45|SOUND IN VRAM A10|22 58|PPU A13#
+ GND|16 46|SOUND OUT PPU RD#|21 57|VRAM CS#
+ PPU RD#|17 47|PPU WR# EXP 38|20 56|PPU WR#
+VRAM A10|18 48|VRAM CS# EXP 39|19 55|EXP 10
+ PPU A6|19 49|PPU A13# EXP 40|18 54|EXP 9
+ PPU A5|20 50|PPU A7 EXP 41|17 53|EXP 8
+ PPU A4|21 51|PPU A8 EXP 42|16 52|EXP 7
+ PPU A3|22 52|PPU A9 CPU IRQ#|15 51|EXP 6
+ PPU A2|23 53|PPU A10 CPU R/W|14 50|CPU ROMCS#
+ PPU A1|24 54|PPU A11 CPU A0|13 49|CPU D0
+ PPU A0|25 55|PPU A12 CPU A1|12 48|CPU D1
+ PPU D0|26 56|PPU A13 CPU A2|11 47|CPU D2
+ PPU D1|27 57|PPU D7 CPU A3|10 46|CPU D3
+ PPU D2|28 58|PPU D6 CPU A4| 9 45|CPU D4
+ PPU D3|29 59|PPU D5 CPU A5| 8 44|CPU D5
+ +5V|30 60|PPU D4 CPU A6| 7 43|CPU D6
+ +-----+ CPU A7| 6 42|CPU D7
+ CPU A8| 5 41|CPU A14
+ CPU A9| 4 40|CPU A13
+ CPU A10| 3 39|CPU A12
+ CPU A11| 2 38|CPU PHI2
+ GND| 1 37|Video CLOCK
+ +-----+
--- /dev/null
+famicom cartridge bus simulator 'kazzo'
+unagi development team / 2009.10.08
+firmware version 0.1.3 / 2010.03.13
+
+----features----
+- USB-to-PC communication
+- ROM cartridge read and write access
+- programming access for flash memory cartridge
+- composed of few, mostly off-the-shelf parts
+- firmware is powered by V-USB
+ http://www.obdev.at/products/vusb/index.html
+- firmware and host software are open source, licenced by GPL v2
+
+kazzo was named after the Japanese traditional fish '鰹'.
+
+----files----
+firmware/
+ firmware source code and Makefile. In order to complile, WinAVR
+ environment is required.
+hostecho/
+ source codes for kazzo_test.exe
+hostmodule/
+ module source codes for kazzo from 'unagi'
+windows_driver/
+ device driver for Windows
+kazzo_test.exe
+ loop back test client binary for Windows
+kazzo_mega16.hex kazzo_mega164p.hex kazzo_mega168.hex
+ firmware hex file written in Intel-Hex Record format
+kazzo_pcb_1.png
+ schematics graphic file for PCB 1.x
+ (note: U1 pin number is assigned as ATmega16 QFP.)
+kazzo_pcb_2.png
+ schematics graphic file for PCB 2.x
+mcu16.txt mcu88.txt
+ pin and fusebit assignments
+readme.txt
+ this file
+usbrequest.txt
+ directions on how to send USB request commands to kazzo.
+COPYING
+ GPL v2 licencing document
+
+Host software 'unagi' is not included in this package. unagi's binary
+and source codes are available from the official project page.
+http://unagi.sourceforge.jp/
+
+----hardware designs----
+Hardware designs has 2 revisions. Check each docments.
+ATmega16 or ATmega164P based design / PCB 1.x -> mcu16.txt
+ATmega168 or ATmega168P based design / PCB 2.x -> mcu88.txt
+
+PCB 2.x is a design to reduce the produce cost. The transfer rate is
+slower than PCB 1.x. Because ATmega168 uses PCINT port for interrupt.
+ATmega168 does not have empty IO pins. It's difficult to expansions.
+
+If you assemble kazzo by yourself, we recommend PCB 1.x. We will not stop
+supporting PCB 1.x.
+
--- /dev/null
+Famicom Cartridge Bus Simulator: 'kazzo'
+Firmware USB Request Reference version 0.1.3
+
+----Word Definitions----
+* CPU Memory Region
+The Famicom cartridge has two memory regions: CPU and PPU. The CPU
+memory region is connected to various memory and registers. The cart
+connects program memory (either ROM, RAM, or flash memory),
+memory-controlled registers, etc.
+
+* PPU Memory Region
+The cartridge connects character memory (again, either ROM, RAM, or
+flash memory) as a 'pattern table', nametable control signal (either
+controlled by hard-wired means or ASICs), etc.
+
+* Read/Programming Buffer
+The AVR has less RAM space compared to the host software. Therefore
+both the host software and firmware should send / request data in
+smaller chunks in order to prevent a buffer overflow.
+
+* Registered Task
+Sometimes the firmware is unable to finish processing requests
+momentarily. These requests are then treated as 'registered tasks.'
+These tasks include programming/erasing flash memory or accessing the
+FDS's disk drive. In this case, the host software will have to confirm
+the task's status.
+Please note that reading & writing on memory are not considered tasks,
+as they're processed by an interrupt request.
+
+* Read Buffer (1 region)
+Firmware sends 'read memory' data to the host software via a 'read
+buffer.'
+
+* Programming Buffer (2 regions)
+The host software sends the ROM image data, then the firmware saves
+data to the programming buffer and registers it as a programming task.
+
+* Future Expansion Assignment
+Reserved for future implementation. Otherwise the latest firmware
+version doesn't support this function at this time.
+
+----headerfile----
+The kazzo_request.h file assigns USB custom request numbers and
+defines the read/programming buffer size. Both firmware and host
+software have to share the same kazzo_request.h file.
+
+----request reference----
+REQUST_ECHO
+R/W: read
+Arguments:
+ wLength: must be set as a value of 4
+ wValue: set test data
+ wIndex: set test data
+Returns:
+ following 4 byte data.
+ data[0] wValue bit 0-7
+ data[1] wValue bit 8-15
+ data[2] wIndex bit 0-7
+ data[2] wIndex bit 8-15
+Description:
+This request is used as a communication test. The firmware sends &
+receives data in 4 byte chunks.
+
+REQUEST_PHI2_INIT
+R/W: write (immediate)
+Arguments: not used
+Returns: nothing
+Description:
+Intended for use with Namcot mappers, this request has two functions.
+First, it instructs the firmware to interrupt any registered tasks.
+Second, it initializes the mapper during the 'high' & 'low' states of
+the CPU's PHI2 signal, times 0x80.
+
+REQUEST_CPU_READ
+REQUEST_PPU_READ
+R/W: read
+Arguments:
+ wLength: read length
+ wValue: target address on current memory region
+ wIndex: not used
+Returns: read data
+Description:
+These requests send read cycle access to the buses of the either the
+CPU or PPU. The data is interpreted in sequential order. These
+waveforms are NOT simulated for the 6502 nor the RP2C02.
+
+REQUEST_CPU_READ_6502
+R/W: read
+Arguments:
+ wLength: read length
+ wValue: target address on current memory region
+ wIndex: not used
+Returns: read data
+Description:
+This request is similar to 'REQUEST_CPU_READ', but instead simulates a
+6502 CPU waveform @ 1.78MHz. Keep in mind that this is a fairly slow
+process. The host software is only used for debugging purposes.
+
+REQUEST_CPU_WRITE_6502
+REQUEST_CPU_WRITE_FLASH
+REQUEST_PPU_WRITE
+R/W: write (immediate)
+Arguments:
+ wLength: write length
+ wValue: target address on current memory region
+ wIndex: not used
+ bData: written data for current memory region
+Returns: nothing
+Description:
+These requests send write cycle access to the respective CPU / PPU
+buses. Data is sent in sequential order.
+- REQUEST_CPU_WRITE_6502's waveforms are simulated for the 6502.
+- REQUEST_PPU_WRITE and REQUEST_CPU_WRITE_FLASH waveforms are
+ customized for write cycles used in flash memory. Both requests are
+ not used for programming.
+- REQUEST_CPU_WRITE_FLASH is assigned for debugging.
+- REQUEST_PPU_WRITE is assigned for dectecting charcter ROM or RAM.
+
+REQUEST_FLASH_CONFIG_SET
+R/W: write (immediate)
+Arguments:
+ wLength: must be set as a value of 9 or 8
+ wValue: not used
+ wIndex: target memory region. INDEX_CPU or INDEX_PPU
+ bData: programmed data for current memory region
+ bData[0] bit0-7 for command address 0x0000 (c000x)
+ bData[1] bit8-15 for command address 0x0000 (c000x)
+ bData[2] bit0-7 for command address 0x2aaa (c2aaa)
+ bData[3] bit8-15 for command address 0x2aaa (c2aaa)
+ bData[4] bit0-7 for command address 0x5555 (c5555)
+ bData[5] bit8-15 for command address 0x5555 (c5555)
+ bData[6] bit0-7 for programming unit length
+ bData[7] bit8-15 for programming unit length
+ bData[8] programming retry flag (0:disable, 1: enable / if wLength is
+ 8, firmware set 0)
+Returns: nothing
+Description:
+This request defines flash memory command addresses for the target
+mapper and flash memory device. Please note that address (c000x) is
+reserved for future expansion, so currently that address has no effect.
+
+REQUEST_FLASH_PROGRAM
+R/W: write (task)
+Arguments:
+ wLength: programming length
+ wValue: target address on current memory region
+ wIndex: target memory region. INDEX_CPU or INDEX_PPU
+ bData: programming data for current memory region
+Returns: nothing
+Description:
+This request allows the host software to send programming data. The
+firmware then receives both data and registered programming tasks.
+Keep in mind that programming tasks uses command addresses. Thus if
+command addresses are not specifically defined, the programming task
+will not correctly function.
+
+REQUEST_DISK_STATUS_GET
+REQUEST_DISK_READ
+REQUEST_DISK_WRITE
+(For reference only, these are currently reserved for future expansion.)
+REQUEST_FLASH_STATUS
+R/W: read
+Arguments:
+ wLength: must be set as a value of 1 or 2
+ wValue: not used
+ wIndex: target memory region. INDEX_CPU, INDEX_PPU or INDEX_BOTH
+Returns:
+when wIndex is INDEX_CPU or INDEX_PPU:
+ data[0]: current memory region's flash programming task status
+when wIndex is INDEX_BOTH:
+ data[0]: CPU flash programming task status
+ data[1]: PPU flash programming task status
+Description:
+This request determines the flash programming task status for either
+the CPU or PPU individually.
+
+REQUEST_FLASH_DEVICE
+R/W: read
+Arguments:
+ wLength: must be set as a value of 2
+ wValue: not used
+ wIndex: target memory region. INDEX_CPU or INDEX_PPU
+Returns:
+ data[0]: flash memory device manufacturer code
+ data[1]: flash memory device device code
+Description:
+This request is reserved for future expansion. Soon, this will be used
+to retrieve the flash memory's product ID. Otherwise this does not
+function correctly at this time.
+
+REQUEST_FLASH_ERASE
+R/W: write (task)
+Arguments:
+ wLength: must be set as a value of 0
+ wValue: confirmed current region address during erase
+ wIndex: target memory region. INDEX_CPU or INDEX_PPU
+Returns: nothing
+Description:
+Firmware registers an 'erase task' on flash memory. The host software
+can retrieve the current progress status via the aforementioned
+REQUEST_FLASH_STATUS requests.
+
+REQUEST_VRAM_CONNECTION
+R/W: read
+Arguments:
+ wLength: must be set as a value of 1
+ wValue: not used
+ wIndex: not used
+Returns: data[0]: VRAM A10 connection data
+Description:
+The firmware sets the PPU's address bus and retrieves VRAM A10
+connection data, which is treated as a 4-bit value.
+
+bit0: address set 0x2000
+bit1: address set 0x2400
+bit2: address set 0x2800
+bit3: address set 0x2c00
+bit4-7: not used, set as 0.
+
+If a basic board utilizing a hardwired VRAM mirroring connection is
+being used, the following data is returned:
+0x00: nametable #0 only
+0x0f: nametable #1 only
+0x05: vertical mirroring
+0x09: horizonal mirroring
+
+REQUEST_FIRMWARE_VERSION
+R/W: read
+Arguments:
+ wLength: must be set as a value of 0x20
+ wValue: not used
+ wIndex: not used
+Returns: version infomation Null-terminated string
+Description:
+The firmware returns firmware version C-style string.
+
+REQUEST_FIRMWARE_PROGRAM
+R/W: write
+Arguments:
+ wLength: must be set as a value of 0
+ wValue: target programming address for AVR
+ wIndex: programming length
+Description:
+The firmware is programmed by bootloader. When the host send the
+request, USB connection will be disconnected. After disconnection,
+firmware programs new firmware via catrdige-placed W-RAM and CHR-RAM.
+The host have to send a firmware image to W-RAM (offset 0x2000 to
+0x3fff) and CHR-RAM (offset 0 to 0x1fff) on SNROM.
+
+REQUEST_FIRMWARE_DOWNLOAD
+R/W: read
+Arguments:
+ wLength: read length
+ wValue: target address for AVR
+ wIndex: not used
+Returns: read data
+Description:
+The firmware returns firmware image via read buffer.
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