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rtl sim started...
[motonesfpga/motonesfpga.git]
/
de0_cv_nes
/
de0_cv_nes.vhd
2016-09-08
astoria-d@fc
rtl sim started...
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commitdiff
2016-09-08
astoria-d@fc
new design work...
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2016-09-08
astoria-d@fc
new design work started.
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2016-09-05
astoria-d
more work. all codes must be written in synchronized...
ppu-work-160905
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2016-09-05
astoria-d
de1 integration. failed to display..
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2016-09-04
astoria-d
de0-cv integration ok.
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2016-08-28
astoria-d
fuck de0-cv. doesn't work at all!!!!
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2016-08-28
astoria-d
st ii clock counter enabled. bg not displayed again..
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2016-08-28
astoria-d
de0-cv integration ok, bg displayed on the test image.
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2016-08-27
astoria-d
de0-cv bg display ok. debug counter was disabled...
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2016-08-27
astoria-d
de0-cv latest merge
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2016-07-30
astoria-d
merge cpu test all
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2016-07-30
astoria-d
smb sprite is displayed!!
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2016-07-28
astoria-d
de0-cv integration, code clean up
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2016-07-17
astoria-d
fucking timing....
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2016-07-17
astoria-d
env catch up...
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2016-07-17
astoria-d
Merge branch 'ppu_test'
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2016-05-28
astoria-d
cpu clock counter debug added
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2016-05-22
astoria-d
nt_vmirror switch read from board sw.
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2016-05-20
astoria-d@office
st2 debugging...
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2016-05-20
astoria-d@office
signal trap ii set up
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2016-05-19
astoria-d@office
simulation env setup ok
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2016-05-18
astoria-d@office
first de0 cv nes image test ok!!!
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2016-05-18
astoria-d@office
LET flash test ok on de0 cv board!
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2016-05-18
astoria-d@office
de0 cv board on quartus ii 14.0
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