; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
-
;https://forth-standard.org/standard/core/ALIGNED
;C ALIGNED addr -- a-addr align given addr
FORTHWORD "ALIGNED"
; along with this program. If not, see <http://www.gnu.org/licenses/>.
- .IFNDEF ALIGNMENT
- .include "ADDON\ALIGNMENT.asm"
- .ENDIF
+ FORTHWORD "{ANS_COMP}"
+ mNEXT
+
.IFNDEF ARITHMETIC
.include "ADDON\ARITHMETIC.asm"
.ENDIF
+ .IFNDEF ALIGNMENT
+ .include "ADDON\ALIGNMENT.asm"
+ .ENDIF
.IFNDEF PORTABILITY
.include "ADDON\PORTABILITY.asm"
.ENDIF
;https://forth-standard.org/standard/core/OnePlus
;C 1+ n1/u1 -- n2/u2 add 1 to TOS
FORTHWORD "1+"
-ONEPLUS ADD #1,TOS
+ ADD #1,TOS
mNEXT
;https://forth-standard.org/standard/core/OneMinus
; along with this program. If not, see <http://www.gnu.org/licenses/>.
-;https://forth-standard.org/standard/core/NIP
-;CE NIP x1 x2 -- x2
- FORTHWORD "NIP"
-NIP ADD #2,PSP ; 1
- mNEXT ; 4
-
-;https://forth-standard.org/standard/core/StoD
-;C S>D n -- d single -> double prec.
- FORTHWORD "S>D"
-STOD: SUB #2,PSP
- MOV TOS,0(PSP)
- JMP ZEROLESS
-
.IFDEF MPY
;https://forth-standard.org/standard/core/UMTimes
--- /dev/null
+
+
+ .IFNDEF LOWERCASE
+ .WARNING "uncomment LOWERCASE ADD-ON to pass coretest COMPARE ADD-ON !"
+ .ENDIF
+
+
+;COMPARE ( c-addr1 u1 c-addr2 u2 -- n )
+;https://forth-standard.org/standard/string/COMPARE
+;Compare the string specified by c-addr1 u1 to the string specified by c-addr2 u2.
+;The strings are compared, beginning at the given addresses, character by character,
+;up to the length of the shorter string or until a difference is found.
+;If the two strings are identical, n is zero.
+;If the two strings are identical up to the length of the shorter string,
+; n is minus-one (-1) if u1 is less than u2 and one (1) otherwise.
+;If the two strings are not identical up to the length of the shorter string,
+; n is minus-one (-1) if the first non-matching character in the string specified by c-addr1 u1
+; has a lesser numeric value than the corresponding character in the string specified by c-addr2 u2 and one (1) otherwise.
+ FORTHWORD "COMPARE"
+COMPARE
+ MOV TOS,S ;1 u2 = S
+ MOV @PSP+,Y ;2 addr2 = Y
+ MOV @PSP+,T ;2 u1 = T
+ MOV @PSP+,X ;2 addr1 = X
+COMPAR1 MOV T,TOS ;1
+ ADD S,TOS ;1
+ JZ COMPEQUAL ;2 end of all successfull comparisons
+ SUB #1,T ;1
+ JN COMPLESS ;2 u1<u2
+ SUB #1,S ;1
+ JN COMPGREATER ;2 u2<u1
+ ADD #1,X ;1
+ CMP.B @Y+,-1(X) ;4 char1-char2
+ JZ COMPAR1 ;2 char1=char2 17~ loop
+ JHS COMPGREATER ;2 char1>char2
+COMPLESS ; char1<char2
+ MOV #-1,TOS ;1
+ MOV @IP+,PC ;4
+COMPGREATER
+ MOV #1,TOS ;1
+COMPEQUAL
+ MOV @IP+,PC ;4 20 words
+
+;[THEN]
+;https://forth-standard.org/standard/tools/BracketTHEN
+ FORTHWORDIMM "[THEN]" ; do nothing
+ mNEXT
+
+ONEMIN
+ SUB #1,TOS
+ mNEXT
+
+;[ELSE]
+;Compilation:
+;Perform the execution semantics given below.
+;Execution:
+;( "<spaces>name ..." -- )
+;Skipping leading spaces, parse and discard space-delimited words from the parse area,
+;including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN],
+;until the word [THEN] has been parsed and discarded.
+;If the parse area becomes exhausted, it is refilled as with REFILL.
+ FORTHWORDIMM "[ELSE]"
+BRACKETELSE
+ mDOCOL
+ .word lit,1 ; 1
+BRACKETELSE1 ; BEGIN
+BRACKETELSE2 ; BEGIN
+ .word FBLANK,WORDD,COUNT ; BL WORD COUNT
+ .word DUP,QBRAN,BRACKETELSE10 ; DUP WHILE
+ .word OVER,OVER ; 2DUP
+ .word XSQUOTE ; S" [IF]"
+ .byte 4,"[IF]" ;
+ .word COMPARE ; COMPARE
+ .word QZBRAN,BRACKETELSE3 ; 0= IF
+ .word TWODROP,ONEPLUS ; 2DROP 1+
+ .word BRAN,BRACKETELSE8 ; (ENDIF)
+BRACKETELSE3 ; ELSE
+ .word OVER,OVER ; OVER OVER
+ .word XSQUOTE ; S" [ELSE]"
+ .byte 6,"[ELSE]" ;
+ .word COMPARE ; COMPARE
+ .word QZBRAN,BRACKETELSE5 ; 0= IF
+ .word TWODROP,ONEMIN ; 2DROP 1-
+ .word DUP,QBRAN,BRACKETELSE4 ; DUP IF
+ .word ONEPLUS ; 1+
+BRACKETELSE4 ; THEN
+ .word BRAN,BRACKETELSE7 ; (ENDIF)
+BRACKETELSE5 ; ELSE
+ .word XSQUOTE ; S" [THEN]"
+ .byte 6,"[THEN]" ;
+ .word COMPARE ; COMPARE
+ .word QZBRAN,BRACKETELSE6 ; 0= IF
+ .word ONEMIN ; 1-
+BRACKETELSE6 ; THEN
+BRACKETELSE7 ; THEN
+BRACKETELSE8 ; THEN
+ .word QDUP ; ?DUP
+ .word QZBRAN,BRACKETELSE9 ; 0= IF
+ .word EXIT ; EXIT
+BRACKETELSE9 ; THEN
+ .word BRAN,BRACKETELSE2 ; REPEAT
+BRACKETELSE10 ;
+ .word TWODROP ; 2DROP
+ .word XSQUOTE ; CR ." ko " to show false branch of conditionnal compilation
+ .byte 4,13,107,111,32 ;
+ .word TYPE ;
+ .word FTIB,DUP,lit,TIB_SIZE ; REFILL
+ .word ACCEPT ; -- StringOrg len' (len' <= TIB_SIZE)
+ FORTHtoASM ;
+ MOV TOS,&SOURCE_LEN ; -- StringOrg len'
+ MOV @PSP+,&SOURCE_ADR ; -- len'
+ MOV @PSP+,TOS ;
+ MOV #0,&TOIN ;
+ MOV #BRACKETELSE1,IP ; AGAIN
+ mNEXT ; 78 words
+
+
+;[IF]
+;https://forth-standard.org/standard/tools/BracketIF
+;Compilation:
+;Perform the execution semantics given below.
+;Execution: ;( flag | flag "<spaces>name ..." -- )
+;If flag is true, do nothing. Otherwise, skipping leading spaces,
+; parse and discard space-delimited words from the parse area,
+; including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN],
+; until either the word [ELSE] or the word [THEN] has been parsed and discarded.
+;If the parse area becomes exhausted, it is refilled as with REFILL. [IF] is an immediate word.
+;An ambiguous condition exists if [IF] is POSTPONEd,
+; or if the end of the input buffer is reached and cannot be refilled before the terminating [ELSE] or [THEN] is parsed.
+ FORTHWORDIMM "[IF]" ; flag --
+ CMP #0,TOS
+ MOV @PSP+,TOS
+ JZ BRACKETELSE
+ mNEXT
+
+;[UNDEFINED]
+;https://forth-standard.org/standard/tools/BracketUNDEFINED
+;Compilation:
+;Perform the execution semantics given below.
+;Execution: ( "<spaces>name ..." -- flag )
+;Skip leading space delimiters. Parse name delimited by a space.
+;Return a false flag if name is the name of a word that can be found,
+;otherwise return a true flag.
+ FORTHWORDIMM "[UNDEFINED]"
+ mDOCOL
+ .word FBLANK,WORDD,FIND,NIP,ZEROEQUAL,EXIT
+
+;[DEFINED]
+;https://forth-standard.org/standard/tools/BracketDEFINED
+;Compilation:
+;Perform the execution semantics given below.
+;Execution:
+;( "<spaces>name ..." -- flag )
+;Skip leading space delimiters. Parse name delimited by a space.
+;Return a true flag if name is the name of a word that can be found,
+;otherwise return a false flag. [DEFINED] is an immediate word.
+
+ FORTHWORDIMM "[DEFINED]"
+ mDOCOL
+ .word FBLANK,WORDD,FIND,NIP,EXIT
+
+
+
+;;[THEN]
+;;https://forth-standard.org/standard/tools/BracketTHEN
+; FORTHWORDIMM ".ENDIF" ; do nothing
+; mNEXT
+;
+;ONEMIN
+; SUB #1,TOS
+; mNEXT
+;
+;;[ELSE]
+;;Compilation:
+;;Perform the execution semantics given below.
+;;Execution:
+;;( "<spaces>name ..." -- )
+;;Skipping leading spaces, parse and discard space-delimited words from the parse area,
+;;including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN],
+;;until the word [THEN] has been parsed and discarded.
+;;If the parse area becomes exhausted, it is refilled as with REFILL.
+; FORTHWORDIMM ".ELSE"
+;;BRACKETELSE
+; mDOCOL
+;BRACKETELSE
+; .word lit,1 ; 1
+;BRACKETELSE1 ; BEGIN
+;BRACKETELSE2 ; BEGIN
+; .word FBLANK,WORDD,COUNT ; BL WORD COUNT
+; .word DUP,QBRAN,BRACKETELSE10 ; DUP WHILE
+; .word OVER,OVER ; 2DUP
+; .word XSQUOTE ; S" [IF]"
+; .byte 6,".IFDEF" ;
+; .word COMPARE ; COMPARE
+; .word QZBRAN,BRACKETELSE21 ; 0= IF
+; .word TWODROP,ONEPLUS ; 2DROP 1+
+; .word BRAN,BRACKETELSE8 ; (ENDIF)
+;BRACKETELSE21
+; .word OVER,OVER ; 2DUP
+; .word XSQUOTE ; S" [IF]"
+; .byte 7,".IFNDEF" ;
+; .word COMPARE ; COMPARE
+; .word QZBRAN,BRACKETELSE3 ; 0= IF
+; .word TWODROP,ONEPLUS ; 2DROP 1+
+; .word BRAN,BRACKETELSE8 ; (ENDIF)
+;BRACKETELSE3 ; ELSE
+; .word OVER,OVER ; OVER OVER
+; .word XSQUOTE ; S" [ELSE]"
+; .byte 5,".ELSE" ;
+; .word COMPARE ; COMPARE
+; .word QZBRAN,BRACKETELSE5 ; 0= IF
+; .word TWODROP,ONEMIN ; 2DROP 1-
+; .word DUP,QBRAN,BRACKETELSE4 ; DUP IF
+; .word ONEPLUS ; 1+
+;BRACKETELSE4 ; THEN
+; .word BRAN,BRACKETELSE7 ; (ENDIF)
+;BRACKETELSE5 ; ELSE
+; .word XSQUOTE ; S" [THEN]"
+; .byte 6,".ENDIF" ;
+; .word COMPARE ; COMPARE
+; .word QZBRAN,BRACKETELSE6 ; 0= IF
+; .word ONEMIN ; 1-
+;BRACKETELSE6 ; THEN
+;BRACKETELSE7 ; THEN
+;BRACKETELSE8 ; THEN
+; .word QDUP ; ?DUP
+; .word QZBRAN,BRACKETELSE9 ; 0= IF
+; .word EXIT ; EXIT
+;BRACKETELSE9 ; THEN
+; .word BRAN,BRACKETELSE2 ; REPEAT
+;BRACKETELSE10 ;
+; .word TWODROP ; 2DROP
+; .word XSQUOTE ; CR ." ko " to show false branch of conditionnal compilation
+; .byte 4,13,"ko " ;
+; .word TYPE ;
+; .word FTIB,DUP,lit,TIB_SIZE ; REFILL
+; .word ACCEPT ; -- StringOrg len' (len' <= TIB_SIZE)
+; FORTHtoASM ;
+; MOV TOS,&SOURCE_LEN ; -- StringOrg len'
+; MOV @PSP+,&SOURCE_ADR ; -- len'
+; MOV @PSP+,TOS ;
+; MOV #0,&TOIN ;
+; MOV #BRACKETELSE1,IP ; AGAIN
+; mNEXT ; 78 words
+;
+;
+; FORTHWORDIMM ".IFDEF"
+; mDOCOL
+; .word FBLANK,WORDD,FIND,NIP
+; .WORD QBRAN,BRACKETELSE
+; .WORD EXIT
+;
+; FORTHWORDIMM ".IFNDEF"
+; mDOCOL
+; .word FBLANK,WORDD,FIND,NIP
+; .WORD QZBRAN,BRACKETELSE
+; .WORD EXIT
+
+
\ No newline at end of file
--- /dev/null
+; -*- coding: utf-8 -*-
+; http://patorjk.com/software/taag/#p=display&f=Banner&t=Fast Forth
+
+; Fast Forth For Texas Instrument MSP430FRxxxx FRAM devices
+; Copyright (C) <2015> <J.M. THOORENS>
+;
+; This program is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+;https://forth-standard.org/standard/core/DotR
+;CE .R
+
+;https://forth-standard.org/standard/core/Zerone
+;CE 0<>
+
+;https://forth-standard.org/standard/core/Zeromore
+;CE 0>
+
+;https://forth-standard.org/standard/core/TwotoR
+;CE 2>R
+
+;https://forth-standard.org/standard/core/TwoRfrom
+;CE 2R>
+
+;https://forth-standard.org/standard/core/TwoRFetch
+;CE 2R@
+
+;https://forth-standard.org/standard/core/ColonNONAME
+;CE :NONAME
+
+;https://forth-standard.org/standard/core/ne
+;CE <>
+
+;https://forth-standard.org/standard/core/qDO
+;CE ?DO
+
+;https://forth-standard.org/standard/core/ACTION-OF
+;CE ACTION-OF
+; STATE @ IF
+; POSTPONE ['] POSTPONE DEFER@
+; ELSE
+; ' DEFER@
+; THEN ; IMMEDIATE
+
+ FORTHWORDIMM "ACTION-OF"
+ mDOCOL
+ .word STATE,FETCH,QBRAN,AOF1
+ .word BRACKETTICK,COMMA,DEFER@,COMMA,EXIT
+AOF1 .word TICK,DEFER@,EXIT
+
+;https://forth-standard.org/standard/core/BUFFERColon
+;CE BUFFER:
+ FORTHWORD "BUFFER" ; ( u "<name>" -- ; -- addr )
+ mDOCOL
+ .word CREATE,ALLOT,EXIT
+
+;Z (C") -- c-addr run-time code for C"
+; get address and length of string.
+XCQUOTE: SUB #2,PSP ; 1 -- x TOS ; push old TOS on stack
+ MOV TOS,0(PSP) ; 3 -- TOS x ; and reserve one cell on stack
+ MOV IP,TOS ; 2 -- c-addr ;
+ MOV.B @IP+,W
+ ADD W,IP ; 1 -- addr u IP=addr+u=addr(end_of_string)
+ BIT #1,IP ; 1 -- addr u IP=addr+u Carry set/clear if odd/even
+ ADDC #0,IP ; 1 -- addr u IP=addr+u aligned
+ mNEXT ; 4 16~
+
+;https://forth-standard.org/standard/core/Cq
+;CE C"
+ FORTHWORDIMM "C\34" ; immediate
+CQUOTE: mDOCOL
+ .word lit,XCQUOTE,COMMA
+ .word BRAN,SQUOTE1
+
+;https://forth-standard.org/standard/core/CASE
+; CE CASE
+
+;https://forth-standard.org/standard/core/COMPILEComma
+;CE COMPILE,
+ FORTHWORD "COMPILE,"
+ MOV #COMMA,PC
+
+;https://forth-standard.org/standard/core/DEFERStore
+;C DEFER! xt CFA_DEFER -- ; store xt to the address after DODEFER
+ FORTHWORD "DEFER!"
+DEFERSTORE: MOV @PSP+,2(TOS) ; -- CFA_DEFER xt --> [CFA_DEFER+2]
+ MOV @PSP+,TOS ; --
+ mNEXT
+
+;https://forth-standard.org/standard/core/DEFERFetch
+;CE DEFER@
+ FORTHWORD "DEFER@"
+DEFER@ ADD #2,TOS
+ MNEXT
+
+;https://forth-standard.org/standard/core/ENDCASE
+;CE ENDCASE
+
+;https://forth-standard.org/standard/core/ENDOF
+;CE ENDOF
+
+;https://forth-standard.org/standard/core/HOLDS
+;CE HOLDS
+
+;https://forth-standard.org/standard/core/MARKER
+;CE MARKER
+
+;https://forth-standard.org/standard/core/OF
+;CE OF
+
+;https://forth-standard.org/standard/core/PARSE
+;CE PARSE
+
+;https://forth-standard.org/standard/core/PARSE-NAME
+;CE PARSE-NAME
+
+;https://forth-standard.org/standard/core/PICK
+;CE PICK
+
+;https://forth-standard.org/standard/core/REFILL
+;CE REFILL
+
+;https://forth-standard.org/standard/core/RESTORE-INPUT
+;CE RESTORE-INPUT
+
+;https://forth-standard.org/standard/core/ROLL
+;CE ROLL
+
+;https://forth-standard.org/standard/core/SAVE-INPUT
+;CE SAVE-INPUT
+
+;https://forth-standard.org/standard/core/SOURCE-ID
+;CE SOURCE-ID
+
+;https://forth-standard.org/standard/core/Seq
+;CE S\"
+
+;https://forth-standard.org/standard/core/TO
+;CE TO
+ FORTHWORD "TO"
+ MOV #IS,PC
+
+;https://forth-standard.org/standard/core/TRUE
+;CE TRUE
+
+;https://forth-standard.org/standard/core/TUCK
+;CE TUCK
+
+;https://forth-standard.org/standard/core/UDotR
+;CE U.R
+
+;https://forth-standard.org/standard/core/Umore
+;CE U>
+
+;https://forth-standard.org/standard/core/UNUSED
+;CE UNUSED
+
+;https://forth-standard.org/standard/core/VALUE
+;CE VALUE
+ FORTHWORD "VALUE"
+ MOV #CONSTANT,PC
+
+;https://forth-standard.org/standard/core/WITHIN
+;CE WITHIN
+
+;https://forth-standard.org/standard/core/BracketCOMPILE
+;CE [COMPILE]
+
+
; along with this program. If not, see <http://www.gnu.org/licenses/>.
+;https://forth-standard.org/standard/core/StoD
+;C S>D n -- d single -> double prec.
+ FORTHWORD "S>D"
+STOD: SUB #2,PSP
+ MOV TOS,0(PSP)
+ JMP ZEROLESS
+
;https://forth-standard.org/standard/core/TwoFetch
;C 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack
FORTHWORD "2@"
; along with this program. If not, see <http://www.gnu.org/licenses/>.
+ .IFNDEF UTILITY
+
+ .IFNDEF ANS_CORE_COMPLIANT
+
+;https://forth-standard.org/standard/core/MAX
+;C MAX n1 n2 -- n3 signed maximum
+ FORTHWORD "MAX"
+MAX: CMP @PSP,TOS ; n2-n1
+ JL SELn1 ; n2<n1
+SELn2: ADD #2,PSP
+ mNEXT
+
+;https://forth-standard.org/standard/core/MIN
+;C MIN n1 n2 -- n3 signed minimum
+ FORTHWORD "MIN"
+MIN: CMP @PSP,TOS ; n2-n1
+ JL SELn2 ; n2<n1
+SELn1: MOV @PSP+,TOS
+ mNEXT
+
+ .ENDIF ; ANS_CORE_COMPLIANT
+
+;https://forth-standard.org/standard/core/UDotR
+;X U.R u n -- display u unsigned in n width
+ FORTHWORD "U.R"
+UDOTR mDOCOL
+ .word TOR,LESSNUM,lit,0,NUM,NUMS,NUMGREATER
+ .word RFROM,OVER,MINUS,lit,0,MAX,SPACES,TYPE
+ .word EXIT
+
+;https://forth-standard.org/standard/tools/DUMP
+ FORTHWORD "DUMP"
+DUMP PUSH IP
+ PUSH &BASE
+ MOV #10h,&BASE
+ ADD @PSP,TOS ; compute end address
+ AND #0FFF0h,0(PSP) ; compute start address
+ ASMtoFORTH
+ .word SWAP,xdo ; generate line
+DUMP1 .word CR
+ .word II,lit,7,UDOTR,SPACE ; generate address
+ .word II,lit,10h,PLUS,II,xdo ; display 16 bytes
+DUMP2 .word II,CFETCH,lit,3,UDOTR
+ .word xloop,DUMP2
+ .word SPACE,SPACE
+ .word II,lit,10h,PLUS,II,xdo ; display 16 chars
+DUMP3 .word II,CFETCH
+ .word lit,7Eh,MIN,FBLANK,MAX,EMIT
+ .word xloop,DUMP3
+ .word lit,10h,xploop,DUMP1
+ .word RFROM,FBASE,STORE
+ .word EXIT
+
+ .ENDIF ; UTILITY
+
+ FORTHWORD "{SD_TOOLS}"
+ mNEXT
; read logical sector and dump it
; ----------------------------------;
- FORTHWORD "SECT_D" ; sector. -- don't forget to add decimal point to your sector number (if < 65536)
+ FORTHWORD "SECTOR" ; sector. -- don't forget to add decimal point to your sector number (if < 65536)
; ----------------------------------;
-SECT_D
+SECTOR
MOV TOS,X ; X = SectorH
MOV @PSP,W ; W = sectorL
CALL #readSectorWX ; W = SectorLO X = SectorHI
DisplaySector
mDOCOL ;
- .word UDDOT ; ud -- display the double number
+ .word LESSNUM,NUMS,NUMGREATER ; ud -- display the double number
+ .word TYPE,SPACE ;
.word lit,BUFFER,lit,200h,DUMP;
.word EXIT ;
; ----------------------------------;
; ----------------------------------;
; read first sector of Cluster and dump it
; ----------------------------------;
- FORTHWORD "CLUST_D" ; cluster. -- don't forget to add decimal point to your sector number (if < 65536)
+ FORTHWORD "CLUSTER" ; cluster. -- don't forget to add decimal point to your sector number (if < 65536)
; ----------------------------------;
MOV TOS,&ClusterH ;
MOV @PSP,&ClusterL ;
CALL #ComputeClusFrstSect ;
MOV &SectorL,0(PSP) ;
MOV &SectorH,TOS ;
- JMP SECT_D ;
+ JMP SECTOR ;
; ----------------------------------;
; dump FAT1 sector of last entry
; ----------------------------------;
- FORTHWORD "FAT_D" ;VWXY Display first FATsector
+ FORTHWORD "FAT" ;VWXY Display first FATsector
; ----------------------------------;
SUB #4,PSP ;
MOV TOS,2(PSP) ;
MOV &OrgFAT1,0(PSP) ;
MOV #0,TOS ; FATsectorHI = 0
- JMP SECT_D ;
+ JMP SECTOR ;
; ----------------------------------;
;; dump FAT1 sector of last entry
;; ----------------------------------;
-; FORTHWORD "FAT1_D" ; Display FATsector
+; FORTHWORD "FAT" ; Display FATsector
;; ----------------------------------;
; MOV &OrgFAT1,Y ;
-;FAT1_D_Next ;
+;FAT1_Next ;
; SUB #4,PSP ;
; MOV TOS,2(PSP) ; save TOS
; MOV Y,0(PSP) ;
; MOV #0,TOS ; FATsectorHI = 0
-; JMP SECT_D ;
+; JMP SECTOR ;
;; ----------------------------------;
;
;; dump FAT1 sector of last entry
;; ----------------------------------;
-; FORTHWORD "FAT2_D" ; Display FATsector
+; FORTHWORD "FAT2" ; Display FATsector
;; ----------------------------------;
; MOV &OrgFAT2,Y ;
-; JMP FAT1_D_Next ;
+; JMP FAT1_Next ;
;; ----------------------------------;
; dump DIR sector of opened file or first sector of current DIR by default
; ----------------------------------;
- FORTHWORD "DIR_D" ; Display DIR sector of CurrentHdl or CurrentDir sector by default
+ FORTHWORD "DIR" ; Display DIR sector of CurrentHdl or CurrentDir sector by default
; ----------------------------------;
SUB #4,PSP ;
MOV TOS,2(PSP) ; save TOS
; along with this program. If not, see <http://www.gnu.org/licenses/>.
+ FORTHWORD "{UTILITY}"
+ mNEXT
+
;https://forth-standard.org/standard/tools/DotS
-;X .S -- print <number> of cells and stack contents if not empty
- FORTHWORD ".S"
-DOTS mDOCOL
+ FORTHWORD ".S" ; -- print <depth> of Param Stack and stack contents if not empty
+DOTS MOV TOS,-2(PSP) ; -- TOS ( tos x x )
+ MOV PSP,TOS
+ SUB #2,TOS ; to take count that TOS is first cell
+ MOV TOS,-6(PSP) ; -- TOS ( tos x PSP )
+ MOV #PSTACK,TOS ; -- P0 ( tos x PSP )
+ SUB #2,TOS ; to take count that TOS is first cell
+DOTS1 MOV TOS,-4(PSP) ; -- S0 ( tos S0 SP )
+ SUB #6,PSP ; -- S0 SP S0
+ SUB @PSP,TOS ; -- S0 SP S0-SP
+ RRA TOS ; -- S0 SP #cells
+ mDOCOL
.word lit,'<',EMIT
- .word DEPTH,DOT
+ .word DOT ; display #cells
.word lit,08h,EMIT ; backspace
.word lit,'>',EMIT,SPACE
- .word SPFETCH,lit,PSTACK,ULESS
- .word QBRAN,DOTS2
- .word SPFETCH,lit,PSTACK-2,xdo
-DOTS1: .word II,FETCH,UDOT
- .word lit,-2
- .word xploop,DOTS1
-DOTS2: .word EXIT
+ .word OVER,OVER,GREATER
+ .word QZBRAN,STKDISPL1
+ .word DROP,DROP,EXIT
+STKDISPL1 .word xdo
+STKDISPL2 .word II,FETCH,UDOT
+ .word lit,2,xploop,STKDISPL2
+ .word EXIT
+
+
+ FORTHWORD ".RS" ; -- print <depth> of Return Stack and stack contents if not empty
+ MOV TOS,-2(PSP) ; -- TOS ( tos x x )
+ MOV RSP,-6(PSP) ; -- TOS ( tos x RSP )
+ MOV #RSTACK,TOS ; -- R0 ( tos x RSP )
+ JMP DOTS1
;https://forth-standard.org/standard/tools/q
;Z ? adr -- display the content of adr
MOV #UDOT,PC
;https://forth-standard.org/standard/tools/WORDS
-;X WORDS -- list all words in all dicts. 53 words
+;X WORDS -- list all words in first vocabulary in CONTEXT. 38 words
FORTHWORD "WORDS"
WORDS mDOCOL
+ .word CR
+ .word lit,3,SPACES
.SWITCH THREADS
.CASE 1
-; vvvvvvvv may be skipped vvvvvvvv
- .word CR ; type # of threads in vocabularies
- .word lit,3,SPACES
- .word XSQUOTE
- .byte 23,"monothread vocabularies"
- .word TYPE
-; ^^^^^^^^ may be skipped ^^^^^^^^
-
- .word LIT,CONTEXT
-WORDS1 .word DUP,CELLPLUS,SWAP
- .word FETCH,QDUP
- .word QBRAN,WORDS5
- .word CR
- .word lit,3,SPACES
-WORDS3 .word FETCH,QDUP
- .word QBRAN,WORDS4
- .word DUP,DUP,COUNT
- .word lit,07Fh,ANDD,TYPE
+;; vvvvvvvv may be skipped vvvvvvvv
+; .word XSQUOTE ; type # of threads in vocabularies
+; .byte 23,"monothread vocabularies"
+; .word TYPE
+; .word CR
+; .word lit,3,SPACES
+;; ^^^^^^^^ may be skipped ^^^^^^^^
+
+ .word LIT,CONTEXT,FETCH ; -- VOC_BODY
+WORDS1 .word FETCH ; -- NFA
+ .word QDUP ; -- 0 | -- NFA NFA
+ .word QBRAN,WORDS2 ; -- NFA
+ .word DUP,DUP,COUNT ; -- NFA NFA addr count
+ .word lit,07Fh,ANDD,TYPE ; -- NFA NFA
.word CFETCH,lit,0Fh,ANDD
.word lit,10h,SWAP,MINUS
- .word SPACES,lit,2,MINUS
- .word BRAN,WORDS3
-WORDS4 .word CR
+ .word SPACES
+ .word lit,2,MINUS ; NFA -- LFA
.word BRAN,WORDS1
-WORDS5 .word DROP
- .word EXIT
+WORDS2 .word EXIT ; --
.ELSECASE
-; vvvvvvvv may be skipped vvvvvvvv
- .word FBASE,FETCH
- .word LIT,0Ah,FBASE,STORE
- .word CR ; type # of threads in vocabularies
- .word lit,3,SPACES
- .word LIT,THREADS,DOT
- .word XSQUOTE
- .byte 20,"threads vocabularies"
- .word TYPE
- .word FBASE,STORE
-; ^^^^^^^^ may be skipped ^^^^^^^^
-
- .word LIT,CONTEXT
- ; BEGIN
-WORDS1 .word DUP,CELLPLUS,SWAP
- .word FETCH,QDUP
- .word QBRAN,WORDS6 ;
- .word CR
- .word lit,3,SPACES
-
- .word DUP,LIT,PAD ;
- .word LIT,THREADS,DUP,PLUS
+;; vvvvvvvv may be skipped vvvvvvvv
+; .word FBASE,FETCH
+; .word LIT,0Ah,FBASE,STORE
+; .word LIT,THREADS,DOT
+; .word XSQUOTE ; type # of threads in vocabularies
+; .byte 20,"threads vocabularies"
+; .word TYPE
+; .word FBASE,STORE
+; .word CR
+; .word lit,3,SPACES
+;; ^^^^^^^^ may be skipped ^^^^^^^^
+
+ .word LIT,CONTEXT,FETCH
+ .word PAD,LIT,THREADS,DUP,PLUS
.word MOVE
; BEGIN
WORDS2 .word LIT,0,DUP
- .word LIT,THREADS,DUP,PLUS ; I = ptr = thread*2
+ .word LIT,THREADS,DUP,PLUS ; I = ptr = thread*2
.word LIT,0
- .word xdo ; DO
+ .word xdo ; DO
WORDS3 .word DUP
- .word II,LIT,PAD,PLUS,FETCH ; old MAX NFA U< NFA ?
- .word ULESS,QBRAN,WORDS4 ; no
- .word DROP,DROP,II ; yes, replace old MAX of NFA by new MAX of NFA
- .word DUP,LIT,PAD,PLUS,FETCH ;
-WORDS4 .word LIT,2,xploop,WORDS3 ; 2 +LOOP
- .word QDUP ; MAX of NFA = 0 ?
+ .word II,PAD,PLUS,FETCH ; old MAX NFA U< NFA ?
+ .word ULESS,QBRAN,WORDS4 ; no
+ .word DROP,DROP,II ; yes, replace old MAX of NFA by new MAX of NFA
+ .word DUP,PAD,PLUS,FETCH ;
+WORDS4 .word LIT,2,xploop,WORDS3 ; 2 +LOOP
+ .word QDUP ; MAX of NFA = 0 ?
.word QBRAN,WORDS5 ; WHILE
- .word DUP,LIT,2,MINUS,FETCH ; replace NFA MAX by its [LFA]
- .word ROT,LIT,PAD,PLUS,STORE
- .word DUP,COUNT ; display NFA MAX in 10 chars format
+ .word DUP,LIT,2,MINUS,FETCH ; replace NFA MAX by its [LFA]
+ .word ROT,PAD,PLUS,STORE
+ .word DUP,COUNT ; display NFA MAX in 10 chars format
.word lit,07Fh,ANDD,TYPE
.word CFETCH,lit,0Fh,ANDD
.word lit,10h,SWAP,MINUS
.word SPACES
.word BRAN,WORDS2 ; REPEAT
-WORDS5 .word DROP,DROP
- .word CR
- .word BRAN,WORDS1 ; REPEAT
-WORDS6 .word DROP
+WORDS5 .word DROP
.word EXIT
.ENDCASE
@1800
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+84 12 D6 D7 40 E0 30 D8 03 41 4E 44 84 12 D6 D7
+00 F0 18 D9 05 41 4E 44 2E 42 84 12 D6 D7 40 F0
+90 C6 90 D6 36 D9 1A 42 BC 21 B2 F0 70 00 BC 21
+8A 10 3A F0 0F 00 82 DA BC 21 4A 3F 6A D8 03 52
+52 43 84 12 30 D9 00 10 4E D9 05 52 52 43 2E 42
+84 12 30 D9 40 10 5A D9 04 53 57 50 42 00 84 12
+30 D9 80 10 68 D9 03 52 52 41 84 12 30 D9 00 11
+76 D9 05 52 52 41 2E 42 84 12 30 D9 40 11 82 D9
+03 53 58 54 84 12 30 D9 80 11 00 00 04 50 55 53
+48 00 84 12 30 D9 00 12 9C D9 06 50 55 53 48 2E
+42 00 84 12 30 D9 40 12 F0 D8 04 43 41 4C 4C 00
+84 12 30 D9 80 12 34 C4 2C 00 90 D6 88 D7 D0 D9
+59 42 BC 21 5A 42 BD 21 82 4A BC 21 BE 90 00 15
+00 00 02 20 0A 89 02 3C 09 8A 0A 49 3A 90 10 00
+03 2C 5A 0E A8 3F 1A 53 0E 4A 87 12 8A C7 94 C9
+0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 30 CD
+AA D9 05 50 55 53 48 4D 84 12 C6 D9 00 15 12 DA
+04 50 4F 50 4D 00 84 12 C6 D9 00 17 90 C6 FC D5
+32 DA 82 43 BC 21 92 42 C4 21 BA 21 A2 53 C4 21
+92 53 C2 21 3E 40 2C 00 B0 12 2A C4 EE C9 02 CB
+E0 C5 AE CD 88 D7 58 DA 0A 4E 3E 4F 1A 83 2A 92
+CA 2F 8A 10 5A 06 6F 3F 90 D9 04 52 52 43 4D 00
+84 12 2C DA 50 00 6A DA 04 52 52 41 4D 00 84 12
+2C DA 50 01 78 DA 04 52 4C 41 4D 00 84 12 2C DA
+50 02 86 DA 04 52 52 55 4D 00 84 12 2C DA 50 03
+85 12 00 3C 94 DA 03 53 3E 3D 85 12 00 38 A6 DA
+02 53 3C 00 85 12 00 34 20 DA 03 30 3E 3D 85 12
+00 30 BA DA 02 30 3C 00 85 12 00 30 00 00 02 55
+3C 00 85 12 00 2C CE DA 03 55 3E 3D 85 12 00 28
+C4 DA 03 30 3C 3E 85 12 00 24 E2 DA 02 30 3D 00
+85 12 00 20 84 C8 02 49 46 00 1A 42 C4 21 8A 4E
+00 00 A2 53 C4 21 0E 4A 30 4D D8 DA 04 54 48 45
+4E 00 1A 42 C4 21 08 4E 3E 4F 09 48 29 53 0A 89
+0A 11 3A 90 00 02 68 2F 88 DA 00 00 30 4D A0 D8
+04 45 4C 53 45 00 1A 42 C4 21 BA 40 00 3C 00 00
+A2 53 C4 21 2F 83 8F 4A 00 00 E3 3F 0C DB 05 55
+4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C4 21 2A 83
+0A 89 0A 11 3A 90 00 FE 47 3B 3A F0 FF 03 08 DA
+89 48 00 00 A2 53 C4 21 30 4D 24 D9 05 41 47 41
+49 4E 87 12 A0 DA 54 DB 2A C4 00 00 05 57 48 49
+4C 45 87 12 FA DA 78 C4 2A C4 B0 DA 06 52 45 50
+45 41 54 00 87 12 A0 DA 54 DB 12 DB 2A C4 00 00
+03 4A 4D 50 87 12 A0 CD A0 DA 54 DB 2A C4 3E B0
+00 10 03 20 3E E0 00 04 30 4D 3E 90 00 34 06 28
+03 24 3E 40 00 34 30 4D 3E 40 00 38 30 4D 00 00
+04 3F 4A 4D 50 00 87 12 BE DB A0 CD 78 C4 54 DB
+2A C4 F4 DB 3D 41 08 4E 3E 4F 2A 48 0A 93 04 20
+98 42 C4 21 00 00 30 4D 88 43 00 00 A4 3F BA D9
+03 42 57 31 84 12 F2 DB 00 00 10 DC 03 42 57 32
+84 12 F2 DB 00 00 1C DC 03 42 57 33 84 12 F2 DB
+00 00 34 DC 3D 41 1A 42 C4 21 28 4E 08 93 08 20
+BA 4F 00 00 A2 53 C4 21 8E 4A 00 00 3E 4F 30 4D
+8E 43 00 00 61 3F 00 00 03 46 57 31 84 12 32 DC
+00 00 58 DC 03 46 57 32 84 12 32 DC 00 00 64 DC
+03 46 57 33 84 12 32 DC 00 00 70 DC 04 47 4F 54
+4F 00 87 12 A0 DA A0 CD C0 CB 2A C4 E0 DB 05 3F
+47 4F 54 4F 87 12 BE DB A0 CD C0 CB 2A C4
@FFDA
-C6 D2 C6 D2 C6 D2 C6 D2 C6 D2 6A C8 C6 D2 C6 D2
-C6 D2 C6 D2 C6 D2 C6 D2 C6 D2 C6 D2 C6 D2 C6 D2
-C6 D2 C6 D2 C6 D2
+36 D4 36 D4 36 D4 36 D4 36 D4 92 C8 36 D4 36 D4
+36 D4 36 D4 36 D4 36 D4 36 D4 36 D4 36 D4 36 D4
+36 D4 36 D4 36 D4
q
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr2433 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
+++ /dev/null
-
-FORTH vocabulary
- COLD WARM (WARM) WIPE RST_HERE RST_STATE PWR_HERE PWR_STATE
- MOVE LEAVE +LOOP LOOP DO REPEAT WHILE AGAIN
- UNTIL BEGIN THEN ELSE IF POSTPONE ['] IS
- IMMEDIATE ; : RECURSE ] [ DEFER DOES>
- CREATE CONSTANT VARIABLE \ ' ABORT" ABORT QUIT
- EVALUATE COUNT LITERAL , EXECUTE >NUMBER FIND WORD
- ." S" TYPE SPACES SPACE CR (CR) NOECHO
- ECHO EMIT (EMIT) ACCEPT KEY (KEY) C, ALLOT
- HERE . D. U. UD. SIGN HOLD #>
- #S # <# BL STATE BASE >IN J
- I UNLOOP U< > < = 0< 0=
- ABS NEGATE XOR OR AND - + C!
- C@ ! @ DEPTH R@ R> >R ROT
- OVER SWAP DROP ?DUP DUP LIT EXIT
-
-ASSEMBLER vocabulary
- ?GOTO GOTO FW3 FW2 FW1 BW3 BW2 BW1
- ?JMP JMP REPEAT WHILE AGAIN UNTIL ELSE THEN
- IF 0= 0<> U>= U< 0< 0>= S<
- S>= RRUM RLAM RRAM RRCM POPM PUSHM CALL
- PUSH.B PUSH SXT RRA.B RRA SWPB RRC.B RRC
- AND.B AND XOR.B XOR BIS.B BIS BIC.B BIC
- BIT.B BIT DADD.B DADD CMP.B CMP SUB.B SUB
- SUBC.B SUBC ADDC.B ADDC ADD.B ADD MOV.B MOV
- RETI LO2HI COLON ENDASM ENDCODE ASM CODE HI2LO
- ASSEMBLER
-
-VOCABULARY ADD-ON
- DEFINITIONS ONLY PREVIOUS ALSO FORTH VOCABULARY
-
-ANS_COMPLEMENT ADD-ON
- >BODY SOURCE .( ( DECIMAL HEX FILL +!
- [CHAR] CHAR CELL+ CELLS CHAR+ CHARS ALIGN ALIGNED
- 2OVER 2SWAP 2DROP 2DUP 2! 2@ */ */MOD
- MOD / /MOD * FM/MOD SM/REM UM/MOD M*
- UM* S>D NIP 2/ 2* MIN MAX 1-
- 1+ RSHIFT LSHIFT INVERT
-
-SD_CARD_LOADER ADD-ON
- LOAD" (ACCEPT)
-
-SD_CARD_READ_WRITE ADD-ON
- TERM2SD" SD_EMIT WRITE WRITE" READ READ" CLOSE DEL"
- CD"
-
-SD_TOOLS ADD-ON
- DIR_D FAT_D CLUST_D SECT_D DUMP U.R MIN
- MAX WORDS .S SP@ ?
-
--- /dev/null
+
+FORTH vocabulary
+----------------
+ASM CODE HI2LO COLD WARM (WARM) WIPE RST_HERE
+PWR_HERE RST_STATE PWR_STATE MOVE LEAVE +LOOP LOOP DO
+REPEAT WHILE AGAIN UNTIL BEGIN THEN ELSE IF
+; : DEFER DOES> CREATE CONSTANT VARIABLE POSTPONE
+RECURSE IMMEDIATE IS ['] ] [ \ '
+ABORT" ABORT QUIT EVALUATE COUNT LITERAL , EXECUTE
+>NUMBER FIND WORD ." S" TYPE SPACES SPACE
+CR (CR) NOECHO ECHO EMIT (EMIT) (ACCEPT) ACCEPT
+KEY (KEY) C, ALLOT HERE . D. U.
+SIGN HOLD #> #S # <# BL STATE
+BASE >IN CPL TIB PAD J I UNLOOP
+U< > < = 0> 0< 0= DABS
+ABS NEGATE XOR OR AND - + C!
+C@ ! @ DEPTH R@ R> >R ROT
+OVER SWAP NIP DROP ?DUP DUP LIT EXIT
+
+
+ASSEMBLER vocabulary
+--------------------
+?GOTO GOTO FW3 FW2 FW1 BW3 BW2 BW1
+?JMP JMP REPEAT WHILE AGAIN UNTIL ELSE THEN
+IF 0= 0<> U>= U< 0< 0>= S<
+S>= RRUM RLAM RRAM RRCM POPM PUSHM CALL
+PUSH.B PUSH SXT RRA.B RRA SWPB RRC.B RRC
+AND.B AND XOR.B XOR BIS.B BIS BIC.B BIC
+BIT.B BIT DADD.B DADD CMP.B CMP SUB.B SUB
+SUBC.B SUBC ADDC.B ADDC ADD.B ADD MOV.B MOV
+RETI LO2HI COLON ENDASM ENDCODE (SLEEP) SLEEP
+
+
+CONDCOMP ADD-ON
+---------------
+[DEFINED] [UNDEFINED] [IF] [ELSE] [THEN] COMPARE MARKER
+
+
+VOCABULARY ADD-ON
+-----------------
+DEFINITIONS ONLY PREVIOUS ALSO ASSEMBLER FORTH VOCABULARY
+
+
+ANS_COMPLEMENT ADD-ON
+---------------------
+>BODY SOURCE .( ( DECIMAL HEX FILL [CHAR]
+CHAR +! MIN MAX 2/ 2* 1- 1+
+RSHIFT LSHIFT INVERT 2OVER 2SWAP 2DROP 2DUP 2!
+2@ S>D CELL+ CELLS CHAR+ CHARS ALIGN ALIGNED
+*/ */MOD MOD / /MOD * FM/MOD SM/REM
+UM/MOD M* UM* {ANS_COMP}
+
+
+SD_CARD_LOADER ADD-ON
+---------------------
+LOAD" {SD_LOAD}
+
+
+SD_CARD_READ_WRITE ADD-ON
+-------------------------
+TERM2SD" SD_EMIT WRITE READ CLOSE DEL" WRITE" READ"
+
+
+UTILITY ADD-ON
+--------------
+DUMP U.R WORDS ? .RS .S {UTILITY}
+
+
+SD_TOOLS ADD-ON
+---------------
+DIR FAT CLUSTER SECTOR {SD_TOOLS}
+
+
+; a word within brackets [] is an immediate word. (other words may also be immediate)
+; a word doubled with another word between parentheses () is a DEFERred word, the first being initialised with the second.
+; when ADD-ONs are compiled into the kernel, their respective MARKER word identified with braces {} does nothing.
+
+; the words that are not commented are ANS94 compliant; search for their definition here: https://forth-standard.org/search
+
+
+FORTH WORDS
+
+ASM <word> -- used to begin an assembler word which is not interpretable by FORTH (because use of CALL ... RET).
+ this defined <word> must be ended with ENDASM.
+
+CODE <word> -- begins an assembler word interpretable by FORTH (MOV @IP+,PC instead of CALL ... RET)
+ this defined <word> must be ended with ENDCODE.
+
+HI2LO -- used to switch from a high level (FORTH) to low level (assembler) modes.
+
+COLD -- Software reset
+
+WARM -- DEFERred word initialized by default with (WARM)
+
+(WARM) -- performs a hot start
+
+WIPE -- resets the program memory to its original state before any add.
+
+RST_HERE -- defines the bound of the program memory protected against COLD or hardware reset.
+
+PWR_HERE -- defines the bound of the program memory protected against ON/OFF.
+
+RST_STATE -- remove all words defined after RST_HERE
+
+PWR_STATE -- remove all words defined after PWR_HERE
+
+MOVE
+LEAVE
++LOOP
+LOOP
+DO
+REPEAT
+WHILE
+AGAIN
+UNTIL
+BEGIN
+THEN
+ELSE
+IF
+;
+:
+DEFER
+DOES>
+CREATE
+CONSTANT
+VARIABLE
+POSTPONE
+RECURSE
+IMMEDIATE
+IS
+[']
+]
+[
+\
+'
+ABORT"
+ABORT
+QUIT
+EVALUATE
+COUNT
+LITERAL
+,
+EXECUTE
+>NUMBER
+FIND
+WORD
+."
+S"
+TYPE
+SPACES
+SPACE
+CR
+(CR)
+NOECHO
+ECHO
+EMIT
+(EMIT)
+(ACCEPT)
+ACCEPT
+KEY
+(KEY)
+C,
+ALLOT
+HERE
+.
+D.
+U.
+SIGN
+HOLD
+#>
+#S
+#
+<#
+BL
+STATE
+BASE
+>IN
+CPL -- size of terminal input buffer TIB
+TIB -- addr of terminal input buffer TIB
+PAD -- addr of PAD
+J
+I
+UNLOOP
+U<
+>
+<
+=
+0>
+0<
+0=
+DABS
+ABS
+NEGATE
+XOR
+OR
+AND
+-
++
+C!
+C@
+!
+@
+DEPTH
+R@
+R>
+>R
+ROT
+OVER
+SWAP
+NIP
+DROP
+?DUP
+DUP
+LIT -- execution part of LITERAL
+EXIT
+
+
+
+ASSEMBLER WORDS see: http://www.ece.utep.edu/courses/web3376/Notes_files/ee3376-isa.pdf
+ http://www.ti.com/lit/ug/slau367n/slau367n.pdf#page=158
+ howto.md for symbolic alias of registers, symbolic jumps (IF ELSE THEN...),..
+
+
+
+?GOTO used after a conditionnal to branch to a label FWx or BWx
+GOTO used as unconditionnal branch to a label FWx or BWx
+
+FW3 FORWARD branch destination n°3
+FW2
+FW1
+
+BW3 BACKWARD branch destination n°3
+BW2
+BW1
+
+?JMP used after a conditionnal to jump to a defined word
+JMP unconditionnal jump to a defined word
+
+REPEAT assembler version of the FORTH word REPEAT
+WHILE idem
+AGAIN idem
+UNTIL idem
+ELSE idem
+THEN idem
+IF idem
+
+0= conditionnal
+0<> conditionnal
+U>= conditionnal
+U< conditionnal
+0< conditionnal, to use only with ?JMP ?GOTO
+0>= conditionnal, to use only with IF UNTIL WHILE
+S< conditionnal
+S>= conditionnal
+
+RRUM used as : RRUM n,REG with 0 < n < 5
+RLAM same syntax
+RRAM same syntax
+RRCM same syntax
+POPM POP multiple registers, used as : POPM X,S to pop X,W,T,S
+PUSHM PUSH multiple registers, used as : PUSHM S,X to push S,T,W,X
+
+CALL see TI assembler
+PUSH.B
+PUSH
+SXT
+RRA.B
+RRA
+SWPB
+RRC.B
+RRC
+AND.B
+AND
+XOR.B
+XOR
+BIS.B
+BIS
+BIC.B
+BIC
+BIT.B
+BIT
+DADD.B
+DADD
+CMP.B
+CMP
+SUB.B
+SUB
+SUBC.B
+SUBC
+ADDC.B
+ADDC
+ADD.B
+ADD
+MOV.B
+MOV
+RETI
+
+LO2HI switch between low level and high level interpretation mode (counterpart of HI2LO), without saving IP.
+COLON PUSH IP then performs LO2HI, used as CODE <word> ... assembler cmd ... COLON ... FORTH words ... ;
+ENDASM to end an ASM definition
+ENDCODE to end a CODE definition
+(SLEEP) the default SLEEP definition
+SLEEP DEFERred word initialised with (SLEEP), which enables to create a background task.
+
+
+CONDCOMP ADD-ON
+---------------
+[DEFINED]
+[UNDEFINED]
+[IF]
+[ELSE]
+[THEN]
+COMPARE
+MARKER
.endcase
.byte STRLEN(name),name
- .align 2
+; .align 2
.ENDM
.endcase
.byte STRLEN(name)+128,name
- .align 2
+; .align 2
.ENDM
.endcase
.byte STRLEN(name),name
- .align 2
+; .align 2
.ENDM
; -------------------------------------------------------------------------------
; ANS complement for MSP430FRxxxx devices with hardware_MPY, to pass CORETEST.4th
+; when downloading to SD_CARD target, truncate filename ANS_COMP_HMPY.4th to ANS_COMP.4th
; -------------------------------------------------------------------------------
\ REGISTERS USAGE
-\ R4 to R7 must be saved before use and restored after
+\ rDODOES to rEXIT must be saved before use and restored after
\ scratch registers Y to S are free for use
\ under interrupt, IP is free for use
-\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, R7, R6, R5, R4
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT, rDOVAR, rDOCON, rDODOES
\ example : PUSHM IP,Y
\
-\ POPM order : R4, R5, R6, R7, Y, X, W, T, S, IP,TOS,PSP
+\ POPM order : rDODOES, rDOCON, rDOVAR, rEXIT, Y, X, W, T, S, IP,TOS,PSP
\ example : POPM Y,IP
\ ASSEMBLER conditionnal usage before IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
-\ ECHO ; if an error occurs, uncomment this line before new download to find it.
- \
-
CODE INVERT \ x1 -- x2 bitwise inversion
XOR #-1,TOS
MOV @IP+,PC
ENDCODE
\
-CODE RSHIFT \ x1 u -- x2 logical R shift u places
+CODE RSHIFT \ x1 u -- x2 logical rEXIT shift u places
MOV @PSP+,W
AND #$1F,TOS \ no need to shift more than 16
0<> IF
\ ARITHMETIC OPERATORS
\ --------------------
-CODE NIP \ a b c -- a c
-ADD #2,PSP
-MOV @IP+,PC
-ENDCODE
- \
-
-: S>D \ n -- d single -> double
- DUP 0<
-;
- \
-
CODE UM* \ u1 u2 -- udlo udhi unsigned 16x16->32 mult.
MOV @PSP,&MPY \ Load 1st operand
\ DOUBLE OPERATORS
\ ----------------------------------------------------------------------
+: S>D \ n -- d single -> double
+ DUP 0<
+;
+ \
+
CODE 2@ \ a-addr -- x1 x2 fetch 2 cells \ the lower address will appear on top of stack
SUB #2, PSP
MOV 2(TOS),0(PSP)
ENDCODE
\
-ECHO
; added ANS_COMPLEMENT: INVERT LSHIFT RSHIFT 1+ 1- MAX MIN 2* 2/ CHAR [CHAR] +! FILL HEX DECIMAL ( .( SOURCE >BODY
- ; ARITHMETIC: NIP S>D UM* M* UM/MOD SM/REM FM/MOD * /MOD / MOD */MOD */
+ ; ARITHMETIC: S>D UM* M* UM/MOD SM/REM FM/MOD * /MOD / MOD */MOD */
; DOUBLE: 2@ 2! 2DUP 2DROP 2SWAP 2OVER
; ALIGMENT: ALIGNED ALIGN
; PORTABIITY: CHARS CHAR+ CELLS CELL+
- \
-PWR_HERE ; to protect this app against a RESET, type: RST_HERE
+
+ ; v--- use backspaces before hit "CR" if you want decrease level of app protection
+PWR_HERE RST_HERE
\ No newline at end of file
; ----------------------------------------------------------------------------------
; ANS complement for MSP430FR4xxx devices without hardware_MPY, to pass CORETEST.4th
+; when downloading to SD_CARD target, truncate filename ANS_COMP_SMPY.4th to ANS_COMP.4th
; ----------------------------------------------------------------------------------
\ REGISTERS USAGE
-\ ECHO ; if an error occurs, uncomment this line before new download to find it.
- \
-
CODE INVERT \ x1 -- x2 bitwise inversion
XOR #-1,TOS
MOV @IP+,PC
\ ARITHMETIC OPERATORS
\ --------------------
-CODE NIP \ a b c -- a c
-ADD #2,PSP
-MOV @IP+,PC
-ENDCODE
- \
-
: S>D \ n -- d single -> double
DUP 0<
;
ENDCODE
\
-ECHO
-PWR_HERE ; to protect this app against a RESET, type: RST_HERE
+ ; added ANS_COMPLEMENT: INVERT LSHIFT RSHIFT 1+ 1- MAX MIN 2* 2/ CHAR [CHAR] +! FILL HEX DECIMAL ( .( SOURCE >BODY
+ ; ARITHMETIC: S>D UM* M* UM/MOD SM/REM FM/MOD * /MOD / MOD */MOD */
+ ; DOUBLE: 2@ 2! 2DUP 2DROP 2SWAP 2OVER
+ ; ALIGMENT: ALIGNED ALIGN
+ ; PORTABIITY: CHARS CHAR+ CELLS CELL+
- ; added : INVERT LSHIFT RSHIFT 1+ 1- MAX MIN 2* 2/ CHAR [CHAR] +! FILL HEX DECIMAL ( .( SOURCE >BODY
- ; added ARITHMETIC : NIP S>D M* UM/MOD SM/REM FM/MOD * /MOD / MOD */MOD */
- ; added DOUBLE : 2@ 2! 2DUP 2DROP 2SWAP 2OVER
- ; added ALIGMENT : ALIGNED ALIGN
- ; added PORTABIITY : CHARS CHAR+ CELLS CELL+
+ ; v--- use backspaces before hit "CR" if you want decrease level of app protection
+PWR_HERE RST_HERE
\ No newline at end of file
; ANS complement for MSP430FRxxxx devices with hardware_MPY, to pass CORETEST.4th
; -------------------------------------------------------------------------------
+PWR_STATE
+
CODE INVERT
XOR #-1,R14
MOV @R13+,R0
MOV @R13+,R0
ENDCODE
+[UNDEFINED] MAX [IF]
CODE MAX
CMP @R15,R14
S< ?GOTO FW1
FW1 MOV @R15+,R14
MOV @R13+,R0
ENDCODE
+[THEN]
CODE 2*
ADD R14,R14
MOV @R13+,R0
ENDCODE
-CODE NIP
-ADD #2,R15
-MOV @R13+,R0
-ENDCODE
-
: S>D
DUP 0<
;
ENDCODE
CODE HEX
-MOV #$10,&$1DDA
+MOV #$10,&BASE
MOV @R13+,R0
ENDCODE
+ \
CODE DECIMAL
-MOV #$0A,&$1DDA
+MOV #$0A,&BASE
MOV @R13+,R0
ENDCODE
-
+ \
: (
$29 WORD DROP
; IMMEDIATE
MOV @R13+,R0
ENDCODE
+PWR_HERE
ECHO
CR .( End of Core word set tests) CR
+\ \ ------------------------------------------------------------------------
+\ \ you must set ON compilation switch LOWERCASE to pass this test
+\ TESTING COMPARE
+\ : CMOVE MOVE ;
+\ : s1 S" abcdefghijklmnopqrstuvwxyz" ;
+\ : s6 S" 123456" ;
+\
+\ T{ s1 s1 COMPARE -> 0 }T
+\ T{ s1 PAD SWAP CMOVE -> }T \ Copy s1 to PAD
+\ T{ s1 PAD OVER COMPARE -> 0 }T
+\ T{ s1 PAD 6 COMPARE -> 1 }T
+\ T{ PAD 10 s1 COMPARE -> -1 }T
+\ T{ s1 PAD 0 COMPARE -> 1 }T
+\ T{ PAD 0 s1 COMPARE -> -1 }T
+\ T{ s1 s6 COMPARE -> 1 }T
+\ T{ s6 s1 COMPARE -> -1 }T
+\ : "abdde" S" abdde" ;
+\ : "abbde" S" abbde" ;
+\ : "abcdf" S" abcdf" ;
+\ : "abcdee" S" abcdee" ;
+\
+\ T{ s1 "abdde" COMPARE -> -1 }T
+\ T{ s1 "abbde" COMPARE -> 1 }T
+\ T{ s1 "abcdf" COMPARE -> -1 }T
+\ T{ s1 "abcdee" COMPARE -> 1 }T
+\
+\ : s11 S" 0abc" ;
+\ : s12 S" 0aBc" ;
+\
+\ T{ s11 s12 COMPARE -> 1 }T
+\ T{ s12 s11 COMPARE -> -1 }T
+
$0A BASE !
; ANS complement for MSP430FR4xxx devices without hardware_MPY, to pass CORETEST.4th
; ----------------------------------------------------------------------------------
+PWR_STATE
+
CODE INVERT
XOR #-1,R14
MOV @R13+,R0
MOV @R13+,R0
ENDCODE
+[UNDEFINED] MAX [IF]
CODE MAX
CMP @R15,R14
S< ?GOTO FW1
FW1 MOV @R15+,R14
MOV @R13+,R0
ENDCODE
+[THEN]
CODE 2*
ADD R14,R14
MOV @R13+,R0
ENDCODE
-CODE NIP
-ADD #2,R15
-MOV @R13+,R0
-ENDCODE
-
: S>D
DUP 0<
;
ENDCODE
CODE HEX
-MOV #$10,&$21DA
+MOV #$10,&BASE
MOV @R13+,R0
ENDCODE
CODE DECIMAL
-MOV #$0A,&$21DA
+MOV #$0A,&BASE
MOV @R13+,R0
ENDCODE
ENDCODE
+PWR_HERE
+
ECHO
; ===============================================================
CR .( End of Core word set tests) CR
-$0A BASE !
+\ ------------------------------------------------------------------------
+\ you must set ON compilation switch LOWERCASE to pass this test
+TESTING COMPARE
+: CMOVE MOVE ;
+: s1 S" abcdefghijklmnopqrstuvwxyz" ;
+: s6 S" 123456" ;
+
+T{ s1 s1 COMPARE -> 0 }T
+T{ s1 PAD SWAP CMOVE -> }T \ Copy s1 to PAD
+T{ s1 PAD OVER COMPARE -> 0 }T
+T{ s1 PAD 6 COMPARE -> 1 }T
+T{ PAD 10 s1 COMPARE -> -1 }T
+T{ s1 PAD 0 COMPARE -> 1 }T
+T{ PAD 0 s1 COMPARE -> -1 }T
+T{ s1 s6 COMPARE -> 1 }T
+T{ s6 s1 COMPARE -> -1 }T
+: "abdde" S" abdde" ;
+: "abbde" S" abbde" ;
+: "abcdf" S" abcdf" ;
+: "abcdee" S" abcdee" ;
+
+T{ s1 "abdde" COMPARE -> -1 }T
+T{ s1 "abbde" COMPARE -> 1 }T
+T{ s1 "abcdf" COMPARE -> -1 }T
+T{ s1 "abcdee" COMPARE -> 1 }T
+
+: s11 S" 0abc" ;
+: s12 S" 0aBc" ;
+
+T{ s11 s12 COMPARE -> 1 }T
+T{ s12 s11 COMPARE -> -1 }T
+$0A BASE !
+ECHO
; happy end of core test
+++ /dev/null
-; ------------------------
-; file name : coretest.4th
-; ------------------------
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ...
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-
-RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
-\ NOECHO ; if an error occurs, comment this line before new download to find it.
-
-
-\ From: John Hayes S1I
-\ Subject: tester.fr
-\ Date: Mon, 27 Nov 95 13:10:09 PST
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.1
-
-\ 22/1/09 The words { and } have been changed to T{ and }T respectively to
-\ agree with the Forth 200X file ttester.fs. This avoids clashes with
-\ locals using { ... } and the FSL use of }
-
-
-\ 13/05/14 jmt. added colorised error messages.
-
-
-
- 0 CONSTANT FALSE
--1 CONSTANT TRUE
-
-\ SET THE FOLLOWING FLAG TO TRUE FOR MORE VERBOSE OUTPUT; THIS MAY
-\ ALLOW YOU TO TELL WHICH TEST CAUSED YOUR SYSTEM TO HANG.
-VARIABLE VERBOSE
- FALSE VERBOSE !
-\ TRUE VERBOSE !
-
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
-
-VARIABLE ACTUAL-DEPTH \ STACK RECORD
-CREATE ACTUAL-RESULTS 20 CELLS ALLOT
-
-: T{ \ ( -- ) SYNTACTIC SUGAR.
- ;
-
-: -> \ ( ... -- ) RECORD DEPTH AND CONTENT OF STACK.
- DEPTH DUP ACTUAL-DEPTH ! \ RECORD DEPTH
- ?DUP IF \ IF THERE IS SOMETHING ON STACK
- 0 DO ACTUAL-RESULTS I CELLS + ! LOOP \ SAVE THEM
- THEN ;
-
-: }T \ ( ... -- ) COMPARE STACK (EXPECTED) CONTENTS WITH SAVED
- \ (ACTUAL) CONTENTS.
- DEPTH ACTUAL-DEPTH @ = IF \ IF DEPTHS MATCH
- DEPTH ?DUP IF \ IF THERE IS SOMETHING ON THE STACK
- 0 DO \ FOR EACH STACK ITEM
- ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
-\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF ABORT" INCORRECT RESULT: " THEN \ jmt : colorised message
- LOOP
- THEN
- ELSE \ DEPTH MISMATCH
-\ S" WRONG NUMBER OF RESULTS: " ERROR \ jmt
- ABORT" WRONG NUMBER OF RESULTS: " \ jmt : colorised message
- THEN ;
-
-: TESTING \ ( -- ) TALKING COMMENT.
- SOURCE VERBOSE @
- IF DUP >R TYPE CR R> >IN !
- ELSE >IN ! DROP [CHAR] * EMIT
- THEN ;
-
-\ From: John Hayes S1I
-\ Subject: core.fr
-\ Date: Mon, 27 Nov 95 13:10
-
-\ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY
-\ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS.
-\ VERSION 1.2
-\ THIS PROGRAM TESTS THE CORE WORDS OF AN ANS FORTH SYSTEM.
-\ THE PROGRAM ASSUMES A TWO'S COMPLEMENT IMPLEMENTATION WHERE
-\ THE RANGE OF SIGNED NUMBERS IS -2^(N-1) ... 2^(N-1)-1 AND
-\ THE RANGE OF UNSIGNED NUMBERS IS 0 ... 2^(N)-1.
-\ I HAVEN'T FIGURED OUT HOW TO TEST KEY, QUIT, ABORT, OR ABORT"...
-\ I ALSO HAVEN'T THOUGHT OF A WAY TO TEST ENVIRONMENT?...
-
-CR
-TESTING CORE WORDS
-HEX
-
-\ ------------------------------------------------------------------------
-TESTING BASIC ASSUMPTIONS
-
-T{ -> }T \ START WITH CLEAN SLATE
-( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
-T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
-T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
-T{ -1 BITSSET? -> 0 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING BOOLEANS: INVERT AND OR XOR
-
-T{ 0 0 AND -> 0 }T
-T{ 0 1 AND -> 0 }T
-T{ 1 0 AND -> 0 }T
-T{ 1 1 AND -> 1 }T
-
-T{ 0 INVERT 1 AND -> 1 }T
-T{ 1 INVERT 1 AND -> 0 }T
-
-0 CONSTANT 0S
-0 INVERT CONSTANT 1S
-
-T{ 0S INVERT -> 1S }T
-T{ 1S INVERT -> 0S }T
-
-T{ 0S 0S AND -> 0S }T
-T{ 0S 1S AND -> 0S }T
-T{ 1S 0S AND -> 0S }T
-T{ 1S 1S AND -> 1S }T
-
-T{ 0S 0S OR -> 0S }T
-T{ 0S 1S OR -> 1S }T
-T{ 1S 0S OR -> 1S }T
-T{ 1S 1S OR -> 1S }T
-
-T{ 0S 0S XOR -> 0S }T
-T{ 0S 1S XOR -> 1S }T
-T{ 1S 0S XOR -> 1S }T
-T{ 1S 1S XOR -> 0S }T
-
-\ ------------------------------------------------------------------------
-TESTING 2* 2/ LSHIFT RSHIFT
-
-( WE TRUST 1S, INVERT, AND BITSSET?; WE WILL CONFIRM RSHIFT LATER )
-1S 1 RSHIFT INVERT CONSTANT MSB
-T{ MSB BITSSET? -> 0 0 }T
-
-T{ 0S 2* -> 0S }T
-T{ 1 2* -> 2 }T
-T{ 4000 2* -> 8000 }T
-T{ 1S 2* 1 XOR -> 1S }T
-T{ MSB 2* -> 0S }T
-
-T{ 0S 2/ -> 0S }T
-T{ 1 2/ -> 0 }T
-T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
-T{ 1S 1 XOR 2/ -> 1S }T
-T{ MSB 2/ MSB AND -> MSB }T
-
-T{ 1 0 LSHIFT -> 1 }T
-T{ 1 1 LSHIFT -> 2 }T
-T{ 1 2 LSHIFT -> 4 }T
-T{ 1 F LSHIFT -> 8000 }T \ BIGGEST GUARANTEED SHIFT
-T{ 1S 1 LSHIFT 1 XOR -> 1S }T
-T{ MSB 1 LSHIFT -> 0 }T
-
-T{ 1 0 RSHIFT -> 1 }T
-T{ 1 1 RSHIFT -> 0 }T
-T{ 2 1 RSHIFT -> 1 }T
-T{ 4 2 RSHIFT -> 1 }T
-T{ 8000 F RSHIFT -> 1 }T \ BIGGEST
-T{ MSB 1 RSHIFT MSB AND -> 0 }T \ RSHIFT ZERO FILLS MSBS
-T{ MSB 1 RSHIFT 2* -> MSB }T
-
-\ ------------------------------------------------------------------------
-TESTING COMPARISONS: 0= = 0< < > U< MIN MAX
-0 INVERT CONSTANT MAX-UINT
-0 INVERT 1 RSHIFT CONSTANT MAX-INT
-0 INVERT 1 RSHIFT INVERT CONSTANT MIN-INT
-0 INVERT 1 RSHIFT CONSTANT MID-UINT
-0 INVERT 1 RSHIFT INVERT CONSTANT MID-UINT+1
-
-0S CONSTANT <FALSE>
-1S CONSTANT <TRUE>
-
-T{ 0 0= -> <TRUE> }T
-T{ 1 0= -> <FALSE> }T
-T{ 2 0= -> <FALSE> }T
-T{ -1 0= -> <FALSE> }T
-T{ MAX-UINT 0= -> <FALSE> }T
-T{ MIN-INT 0= -> <FALSE> }T
-T{ MAX-INT 0= -> <FALSE> }T
-
-T{ 0 0 = -> <TRUE> }T
-T{ 1 1 = -> <TRUE> }T
-T{ -1 -1 = -> <TRUE> }T
-T{ 1 0 = -> <FALSE> }T
-T{ -1 0 = -> <FALSE> }T
-T{ 0 1 = -> <FALSE> }T
-T{ 0 -1 = -> <FALSE> }T
-
-T{ 0 0< -> <FALSE> }T
-T{ -1 0< -> <TRUE> }T
-T{ MIN-INT 0< -> <TRUE> }T
-T{ 1 0< -> <FALSE> }T
-T{ MAX-INT 0< -> <FALSE> }T
-
-T{ 0 1 < -> <TRUE> }T
-T{ 1 2 < -> <TRUE> }T
-T{ -1 0 < -> <TRUE> }T
-T{ -1 1 < -> <TRUE> }T
-T{ MIN-INT 0 < -> <TRUE> }T
-T{ MIN-INT MAX-INT < -> <TRUE> }T
-T{ 0 MAX-INT < -> <TRUE> }T
-T{ 0 0 < -> <FALSE> }T
-T{ 1 1 < -> <FALSE> }T
-T{ 1 0 < -> <FALSE> }T
-T{ 2 1 < -> <FALSE> }T
-T{ 0 -1 < -> <FALSE> }T
-T{ 1 -1 < -> <FALSE> }T
-T{ 0 MIN-INT < -> <FALSE> }T
-T{ MAX-INT MIN-INT < -> <FALSE> }T
-T{ MAX-INT 0 < -> <FALSE> }T
-
-T{ 0 1 > -> <FALSE> }T
-T{ 1 2 > -> <FALSE> }T
-T{ -1 0 > -> <FALSE> }T
-T{ -1 1 > -> <FALSE> }T
-T{ MIN-INT 0 > -> <FALSE> }T
-T{ MIN-INT MAX-INT > -> <FALSE> }T
-T{ 0 MAX-INT > -> <FALSE> }T
-T{ 0 0 > -> <FALSE> }T
-T{ 1 1 > -> <FALSE> }T
-T{ 1 0 > -> <TRUE> }T
-T{ 2 1 > -> <TRUE> }T
-T{ 0 -1 > -> <TRUE> }T
-T{ 1 -1 > -> <TRUE> }T
-T{ 0 MIN-INT > -> <TRUE> }T
-T{ MAX-INT MIN-INT > -> <TRUE> }T
-T{ MAX-INT 0 > -> <TRUE> }T
-
-T{ 0 1 U< -> <TRUE> }T
-T{ 1 2 U< -> <TRUE> }T
-T{ 0 MID-UINT U< -> <TRUE> }T
-T{ 0 MAX-UINT U< -> <TRUE> }T
-T{ MID-UINT MAX-UINT U< -> <TRUE> }T
-T{ 0 0 U< -> <FALSE> }T
-T{ 1 1 U< -> <FALSE> }T
-T{ 1 0 U< -> <FALSE> }T
-T{ 2 1 U< -> <FALSE> }T
-T{ MID-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT 0 U< -> <FALSE> }T
-T{ MAX-UINT MID-UINT U< -> <FALSE> }T
-
-T{ 0 1 MIN -> 0 }T
-T{ 1 2 MIN -> 1 }T
-T{ -1 0 MIN -> -1 }T
-T{ -1 1 MIN -> -1 }T
-T{ MIN-INT 0 MIN -> MIN-INT }T
-T{ MIN-INT MAX-INT MIN -> MIN-INT }T
-T{ 0 MAX-INT MIN -> 0 }T
-T{ 0 0 MIN -> 0 }T
-T{ 1 1 MIN -> 1 }T
-T{ 1 0 MIN -> 0 }T
-T{ 2 1 MIN -> 1 }T
-T{ 0 -1 MIN -> -1 }T
-T{ 1 -1 MIN -> -1 }T
-T{ 0 MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT MIN-INT MIN -> MIN-INT }T
-T{ MAX-INT 0 MIN -> 0 }T
-
-T{ 0 1 MAX -> 1 }T
-T{ 1 2 MAX -> 2 }T
-T{ -1 0 MAX -> 0 }T
-T{ -1 1 MAX -> 1 }T
-T{ MIN-INT 0 MAX -> 0 }T
-T{ MIN-INT MAX-INT MAX -> MAX-INT }T
-T{ 0 MAX-INT MAX -> MAX-INT }T
-T{ 0 0 MAX -> 0 }T
-T{ 1 1 MAX -> 1 }T
-T{ 1 0 MAX -> 1 }T
-T{ 2 1 MAX -> 2 }T
-T{ 0 -1 MAX -> 0 }T
-T{ 1 -1 MAX -> 1 }T
-T{ 0 MIN-INT MAX -> 0 }T
-T{ MAX-INT MIN-INT MAX -> MAX-INT }T
-T{ MAX-INT 0 MAX -> MAX-INT }T
-
-\ ------------------------------------------------------------------------
-TESTING STACK OPS: 2DROP 2DUP 2OVER 2SWAP ?DUP DEPTH DROP DUP OVER ROT SWAP
-
-T{ 1 2 2DROP -> }T
-T{ 1 2 2DUP -> 1 2 1 2 }T
-T{ 1 2 3 4 2OVER -> 1 2 3 4 1 2 }T
-T{ 1 2 3 4 2SWAP -> 3 4 1 2 }T
-T{ 0 ?DUP -> 0 }T
-T{ 1 ?DUP -> 1 1 }T
-T{ -1 ?DUP -> -1 -1 }T
-T{ DEPTH -> 0 }T
-T{ 0 DEPTH -> 0 1 }T
-T{ 0 1 DEPTH -> 0 1 2 }T
-T{ 0 DROP -> }T
-T{ 1 2 DROP -> 1 }T
-T{ 1 DUP -> 1 1 }T
-T{ 1 2 OVER -> 1 2 1 }T
-T{ 1 2 3 ROT -> 2 3 1 }T
-T{ 1 2 SWAP -> 2 1 }T
-
-\ ------------------------------------------------------------------------
-TESTING >R R> R@
-
-T{ : GR1 >R R> ; -> }T
-T{ : GR2 >R R@ R> DROP ; -> }T
-T{ 123 GR1 -> 123 }T
-T{ 123 GR2 -> 123 }T
-T{ 1S GR1 -> 1S }T ( RETURN STACK HOLDS CELLS )
-
-\ ------------------------------------------------------------------------
-TESTING ADD/SUBTRACT: + - 1+ 1- ABS NEGATE
-
-T{ 0 5 + -> 5 }T
-T{ 5 0 + -> 5 }T
-T{ 0 -5 + -> -5 }T
-T{ -5 0 + -> -5 }T
-T{ 1 2 + -> 3 }T
-T{ 1 -2 + -> -1 }T
-T{ -1 2 + -> 1 }T
-T{ -1 -2 + -> -3 }T
-T{ -1 1 + -> 0 }T
-T{ MID-UINT 1 + -> MID-UINT+1 }T
-
-T{ 0 5 - -> -5 }T
-T{ 5 0 - -> 5 }T
-T{ 0 -5 - -> 5 }T
-T{ -5 0 - -> -5 }T
-T{ 1 2 - -> -1 }T
-T{ 1 -2 - -> 3 }T
-T{ -1 2 - -> -3 }T
-T{ -1 -2 - -> 1 }T
-T{ 0 1 - -> -1 }T
-T{ MID-UINT+1 1 - -> MID-UINT }T
-
-T{ 0 1+ -> 1 }T
-T{ -1 1+ -> 0 }T
-T{ 1 1+ -> 2 }T
-T{ MID-UINT 1+ -> MID-UINT+1 }T
-
-T{ 2 1- -> 1 }T
-T{ 1 1- -> 0 }T
-T{ 0 1- -> -1 }T
-T{ MID-UINT+1 1- -> MID-UINT }T
-
-T{ 0 NEGATE -> 0 }T
-T{ 1 NEGATE -> -1 }T
-T{ -1 NEGATE -> 1 }T
-T{ 2 NEGATE -> -2 }T
-T{ -2 NEGATE -> 2 }T
-
-T{ 0 ABS -> 0 }T
-T{ 1 ABS -> 1 }T
-T{ -1 ABS -> 1 }T
-T{ MIN-INT ABS -> MID-UINT+1 }T
-
-\ ------------------------------------------------------------------------
-TESTING MULTIPLY: S>D * M* UM*
-
-T{ 0 S>D -> 0 0 }T
-T{ 1 S>D -> 1 0 }T
-T{ 2 S>D -> 2 0 }T
-T{ -1 S>D -> -1 -1 }T
-T{ -2 S>D -> -2 -1 }T
-T{ MIN-INT S>D -> MIN-INT -1 }T
-T{ MAX-INT S>D -> MAX-INT 0 }T
-
-T{ 0 0 M* -> 0 S>D }T
-T{ 0 1 M* -> 0 S>D }T
-T{ 1 0 M* -> 0 S>D }T
-T{ 1 2 M* -> 2 S>D }T
-T{ 2 1 M* -> 2 S>D }T
-T{ 3 3 M* -> 9 S>D }T
-T{ -3 3 M* -> -9 S>D }T
-T{ 3 -3 M* -> -9 S>D }T
-T{ -3 -3 M* -> 9 S>D }T
-T{ 0 MIN-INT M* -> 0 S>D }T
-T{ 1 MIN-INT M* -> MIN-INT S>D }T
-T{ 2 MIN-INT M* -> 0 1S }T
-T{ 0 MAX-INT M* -> 0 S>D }T
-T{ 1 MAX-INT M* -> MAX-INT S>D }T
-T{ 2 MAX-INT M* -> MAX-INT 1 LSHIFT 0 }T
-T{ MIN-INT MIN-INT M* -> 0 MSB 1 RSHIFT }T
-T{ MAX-INT MIN-INT M* -> MSB MSB 2/ }T
-T{ MAX-INT MAX-INT M* -> 1 MSB 2/ INVERT }T
-
-T{ 0 0 * -> 0 }T \ TEST IDENTITIES
-T{ 0 1 * -> 0 }T
-T{ 1 0 * -> 0 }T
-T{ 1 2 * -> 2 }T
-T{ 2 1 * -> 2 }T
-T{ 3 3 * -> 9 }T
-T{ -3 3 * -> -9 }T
-T{ 3 -3 * -> -9 }T
-T{ -3 -3 * -> 9 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 * -> MID-UINT+1 }T
-T{ MID-UINT+1 2 RSHIFT 4 * -> MID-UINT+1 }T
-T{ MID-UINT+1 1 RSHIFT MID-UINT+1 OR 2 * -> MID-UINT+1 }T
-
-T{ 0 0 UM* -> 0 0 }T
-T{ 0 1 UM* -> 0 0 }T
-T{ 1 0 UM* -> 0 0 }T
-T{ 1 2 UM* -> 2 0 }T
-T{ 2 1 UM* -> 2 0 }T
-T{ 3 3 UM* -> 9 0 }T
-
-T{ MID-UINT+1 1 RSHIFT 2 UM* -> MID-UINT+1 0 }T
-T{ MID-UINT+1 2 UM* -> 0 1 }T
-T{ MID-UINT+1 4 UM* -> 0 2 }T
-T{ 1S 2 UM* -> 1S 1 LSHIFT 1 }T
-T{ MAX-UINT MAX-UINT UM* -> 1 1 INVERT }T
-
-\ ------------------------------------------------------------------------
-TESTING DIVIDE: FM/MOD SM/REM UM/MOD */ */MOD / /MOD MOD
-
-T{ 0 S>D 1 FM/MOD -> 0 0 }T
-T{ 1 S>D 1 FM/MOD -> 0 1 }T
-T{ 2 S>D 1 FM/MOD -> 0 2 }T
-T{ -1 S>D 1 FM/MOD -> 0 -1 }T
-T{ -2 S>D 1 FM/MOD -> 0 -2 }T
-T{ 0 S>D -1 FM/MOD -> 0 0 }T
-T{ 1 S>D -1 FM/MOD -> 0 -1 }T
-T{ 2 S>D -1 FM/MOD -> 0 -2 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -1 FM/MOD -> 0 2 }T
-T{ 2 S>D 2 FM/MOD -> 0 1 }T
-T{ -1 S>D -1 FM/MOD -> 0 1 }T
-T{ -2 S>D -2 FM/MOD -> 0 1 }T
-T{ 7 S>D 3 FM/MOD -> 1 2 }T
-T{ 7 S>D -3 FM/MOD -> -2 -3 }T
-T{ -7 S>D 3 FM/MOD -> 2 -3 }T
-T{ -7 S>D -3 FM/MOD -> -1 2 }T
-T{ MAX-INT S>D 1 FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT FM/MOD -> 0 1 }T
-T{ MIN-INT S>D MIN-INT FM/MOD -> 0 1 }T
-T{ 1S 1 4 FM/MOD -> 3 MAX-INT }T
-T{ 1 MIN-INT M* 1 FM/MOD -> 0 MIN-INT }T
-T{ 1 MIN-INT M* MIN-INT FM/MOD -> 0 1 }T
-T{ 2 MIN-INT M* 2 FM/MOD -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT FM/MOD -> 0 2 }T
-T{ 1 MAX-INT M* 1 FM/MOD -> 0 MAX-INT }T
-T{ 1 MAX-INT M* MAX-INT FM/MOD -> 0 1 }T
-T{ 2 MAX-INT M* 2 FM/MOD -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT FM/MOD -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT FM/MOD -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT FM/MOD -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT FM/MOD -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT FM/MOD -> 0 MAX-INT }T
-
-T{ 0 S>D 1 SM/REM -> 0 0 }T
-T{ 1 S>D 1 SM/REM -> 0 1 }T
-T{ 2 S>D 1 SM/REM -> 0 2 }T
-T{ -1 S>D 1 SM/REM -> 0 -1 }T
-T{ -2 S>D 1 SM/REM -> 0 -2 }T
-T{ 0 S>D -1 SM/REM -> 0 0 }T
-T{ 1 S>D -1 SM/REM -> 0 -1 }T
-T{ 2 S>D -1 SM/REM -> 0 -2 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -1 SM/REM -> 0 2 }T
-T{ 2 S>D 2 SM/REM -> 0 1 }T
-T{ -1 S>D -1 SM/REM -> 0 1 }T
-T{ -2 S>D -2 SM/REM -> 0 1 }T
-T{ 7 S>D 3 SM/REM -> 1 2 }T
-T{ 7 S>D -3 SM/REM -> 1 -2 }T
-T{ -7 S>D 3 SM/REM -> -1 -2 }T
-T{ -7 S>D -3 SM/REM -> -1 2 }T
-T{ MAX-INT S>D 1 SM/REM -> 0 MAX-INT }T
-T{ MIN-INT S>D 1 SM/REM -> 0 MIN-INT }T
-T{ MAX-INT S>D MAX-INT SM/REM -> 0 1 }T
-T{ MIN-INT S>D MIN-INT SM/REM -> 0 1 }T
-T{ 1S 1 4 SM/REM -> 3 MAX-INT }T
-T{ 2 MIN-INT M* 2 SM/REM -> 0 MIN-INT }T
-T{ 2 MIN-INT M* MIN-INT SM/REM -> 0 2 }T
-T{ 2 MAX-INT M* 2 SM/REM -> 0 MAX-INT }T
-T{ 2 MAX-INT M* MAX-INT SM/REM -> 0 2 }T
-T{ MIN-INT MIN-INT M* MIN-INT SM/REM -> 0 MIN-INT }T
-T{ MIN-INT MAX-INT M* MIN-INT SM/REM -> 0 MAX-INT }T
-T{ MIN-INT MAX-INT M* MAX-INT SM/REM -> 0 MIN-INT }T
-T{ MAX-INT MAX-INT M* MAX-INT SM/REM -> 0 MAX-INT }T
-
-T{ 0 0 1 UM/MOD -> 0 0 }T
-T{ 1 0 1 UM/MOD -> 0 1 }T
-T{ 1 0 2 UM/MOD -> 1 0 }T
-T{ 3 0 2 UM/MOD -> 1 1 }T
-T{ MAX-UINT 2 UM* 2 UM/MOD -> 0 MAX-UINT }T
-T{ MAX-UINT 2 UM* MAX-UINT UM/MOD -> 0 2 }T
-T{ MAX-UINT MAX-UINT UM* MAX-UINT UM/MOD -> 0 MAX-UINT }T
-
-: IFFLOORED
- [ -3 2 / -2 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-: IFSYM
- [ -3 2 / -1 = INVERT ] LITERAL IF POSTPONE \ THEN ;
-
-\ THE SYSTEM MIGHT DO EITHER FLOORED OR SYMMETRIC DIVISION.
-\ SINCE WE HAVE ALREADY TESTED M*, FM/MOD, AND SM/REM WE CAN USE THEM IN TEST.
-
-IFFLOORED : T/MOD >R S>D R> FM/MOD ;
-IFFLOORED : T/ T/MOD SWAP DROP ;
-IFFLOORED : TMOD T/MOD DROP ;
-IFFLOORED : T*/MOD >R M* R> FM/MOD ;
-IFFLOORED : T*/ T*/MOD SWAP DROP ;
-IFSYM : T/MOD >R S>D R> SM/REM ;
-IFSYM : T/ T/MOD SWAP DROP ;
-IFSYM : TMOD T/MOD DROP ;
-IFSYM : T*/MOD >R M* R> SM/REM ;
-IFSYM : T*/ T*/MOD SWAP DROP ;
-
-T{ 0 1 /MOD -> 0 1 T/MOD }T
-T{ 1 1 /MOD -> 1 1 T/MOD }T
-T{ 2 1 /MOD -> 2 1 T/MOD }T
-T{ -1 1 /MOD -> -1 1 T/MOD }T
-T{ -2 1 /MOD -> -2 1 T/MOD }T
-T{ 0 -1 /MOD -> 0 -1 T/MOD }T
-T{ 1 -1 /MOD -> 1 -1 T/MOD }T
-T{ 2 -1 /MOD -> 2 -1 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -1 /MOD -> -2 -1 T/MOD }T
-T{ 2 2 /MOD -> 2 2 T/MOD }T
-T{ -1 -1 /MOD -> -1 -1 T/MOD }T
-T{ -2 -2 /MOD -> -2 -2 T/MOD }T
-T{ 7 3 /MOD -> 7 3 T/MOD }T
-T{ 7 -3 /MOD -> 7 -3 T/MOD }T
-T{ -7 3 /MOD -> -7 3 T/MOD }T
-T{ -7 -3 /MOD -> -7 -3 T/MOD }T
-T{ MAX-INT 1 /MOD -> MAX-INT 1 T/MOD }T
-T{ MIN-INT 1 /MOD -> MIN-INT 1 T/MOD }T
-T{ MAX-INT MAX-INT /MOD -> MAX-INT MAX-INT T/MOD }T
-T{ MIN-INT MIN-INT /MOD -> MIN-INT MIN-INT T/MOD }T
-
-T{ 0 1 / -> 0 1 T/ }T
-T{ 1 1 / -> 1 1 T/ }T
-T{ 2 1 / -> 2 1 T/ }T
-T{ -1 1 / -> -1 1 T/ }T
-T{ -2 1 / -> -2 1 T/ }T
-T{ 0 -1 / -> 0 -1 T/ }T
-T{ 1 -1 / -> 1 -1 T/ }T
-T{ 2 -1 / -> 2 -1 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -1 / -> -2 -1 T/ }T
-T{ 2 2 / -> 2 2 T/ }T
-T{ -1 -1 / -> -1 -1 T/ }T
-T{ -2 -2 / -> -2 -2 T/ }T
-T{ 7 3 / -> 7 3 T/ }T
-T{ 7 -3 / -> 7 -3 T/ }T
-T{ -7 3 / -> -7 3 T/ }T
-T{ -7 -3 / -> -7 -3 T/ }T
-T{ MAX-INT 1 / -> MAX-INT 1 T/ }T
-T{ MIN-INT 1 / -> MIN-INT 1 T/ }T
-T{ MAX-INT MAX-INT / -> MAX-INT MAX-INT T/ }T
-T{ MIN-INT MIN-INT / -> MIN-INT MIN-INT T/ }T
-
-T{ 0 1 MOD -> 0 1 TMOD }T
-T{ 1 1 MOD -> 1 1 TMOD }T
-T{ 2 1 MOD -> 2 1 TMOD }T
-T{ -1 1 MOD -> -1 1 TMOD }T
-T{ -2 1 MOD -> -2 1 TMOD }T
-T{ 0 -1 MOD -> 0 -1 TMOD }T
-T{ 1 -1 MOD -> 1 -1 TMOD }T
-T{ 2 -1 MOD -> 2 -1 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -1 MOD -> -2 -1 TMOD }T
-T{ 2 2 MOD -> 2 2 TMOD }T
-T{ -1 -1 MOD -> -1 -1 TMOD }T
-T{ -2 -2 MOD -> -2 -2 TMOD }T
-T{ 7 3 MOD -> 7 3 TMOD }T
-T{ 7 -3 MOD -> 7 -3 TMOD }T
-T{ -7 3 MOD -> -7 3 TMOD }T
-T{ -7 -3 MOD -> -7 -3 TMOD }T
-T{ MAX-INT 1 MOD -> MAX-INT 1 TMOD }T
-T{ MIN-INT 1 MOD -> MIN-INT 1 TMOD }T
-T{ MAX-INT MAX-INT MOD -> MAX-INT MAX-INT TMOD }T
-T{ MIN-INT MIN-INT MOD -> MIN-INT MIN-INT TMOD }T
-
-T{ 0 2 1 */ -> 0 2 1 T*/ }T
-T{ 1 2 1 */ -> 1 2 1 T*/ }T
-T{ 2 2 1 */ -> 2 2 1 T*/ }T
-T{ -1 2 1 */ -> -1 2 1 T*/ }T
-T{ -2 2 1 */ -> -2 2 1 T*/ }T
-T{ 0 2 -1 */ -> 0 2 -1 T*/ }T
-T{ 1 2 -1 */ -> 1 2 -1 T*/ }T
-T{ 2 2 -1 */ -> 2 2 -1 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -1 */ -> -2 2 -1 T*/ }T
-T{ 2 2 2 */ -> 2 2 2 T*/ }T
-T{ -1 2 -1 */ -> -1 2 -1 T*/ }T
-T{ -2 2 -2 */ -> -2 2 -2 T*/ }T
-T{ 7 2 3 */ -> 7 2 3 T*/ }T
-T{ 7 2 -3 */ -> 7 2 -3 T*/ }T
-T{ -7 2 3 */ -> -7 2 3 T*/ }T
-T{ -7 2 -3 */ -> -7 2 -3 T*/ }T
-T{ MAX-INT 2 MAX-INT */ -> MAX-INT 2 MAX-INT T*/ }T
-T{ MIN-INT 2 MIN-INT */ -> MIN-INT 2 MIN-INT T*/ }T
-
-T{ 0 2 1 */MOD -> 0 2 1 T*/MOD }T
-T{ 1 2 1 */MOD -> 1 2 1 T*/MOD }T
-T{ 2 2 1 */MOD -> 2 2 1 T*/MOD }T
-T{ -1 2 1 */MOD -> -1 2 1 T*/MOD }T
-T{ -2 2 1 */MOD -> -2 2 1 T*/MOD }T
-T{ 0 2 -1 */MOD -> 0 2 -1 T*/MOD }T
-T{ 1 2 -1 */MOD -> 1 2 -1 T*/MOD }T
-T{ 2 2 -1 */MOD -> 2 2 -1 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -1 */MOD -> -2 2 -1 T*/MOD }T
-T{ 2 2 2 */MOD -> 2 2 2 T*/MOD }T
-T{ -1 2 -1 */MOD -> -1 2 -1 T*/MOD }T
-T{ -2 2 -2 */MOD -> -2 2 -2 T*/MOD }T
-T{ 7 2 3 */MOD -> 7 2 3 T*/MOD }T
-T{ 7 2 -3 */MOD -> 7 2 -3 T*/MOD }T
-T{ -7 2 3 */MOD -> -7 2 3 T*/MOD }T
-T{ -7 2 -3 */MOD -> -7 2 -3 T*/MOD }T
-T{ MAX-INT 2 MAX-INT */MOD -> MAX-INT 2 MAX-INT T*/MOD }T
-T{ MIN-INT 2 MIN-INT */MOD -> MIN-INT 2 MIN-INT T*/MOD }T
-
-\ ------------------------------------------------------------------------
-TESTING HERE , @ ! CELL+ CELLS C, C@ C! CHARS 2@ 2! ALIGN ALIGNED +! ALLOT
-
-HERE 1 ALLOT
-HERE
-CONSTANT 2NDA
-CONSTANT 1STA
-T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
-( MISSING TEST: NEGATIVE ALLOT )
-
-HERE 1 ,
-HERE 2 ,
-CONSTANT 2ND
-CONSTANT 1ST
-T{ 1ST 2ND U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1ST CELL+ -> 2ND }T \ ... BY ONE CELL
-T{ 1ST 1 CELLS + -> 2ND }T
-T{ 1ST @ 2ND @ -> 1 2 }T
-T{ 5 1ST ! -> }T
-T{ 1ST @ 2ND @ -> 5 2 }T
-T{ 6 2ND ! -> }T
-T{ 1ST @ 2ND @ -> 5 6 }T
-T{ 1ST 2@ -> 6 5 }T
-T{ 2 1 1ST 2! -> }T
-T{ 1ST 2@ -> 2 1 }T
-T{ 1S 1ST ! 1ST @ -> 1S }T \ CAN STORE CELL-WIDE VALUE
-
-HERE 1 C,
-HERE 2 C,
-CONSTANT 2NDC
-CONSTANT 1STC
-T{ 1STC 2NDC U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
-T{ 1STC CHAR+ -> 2NDC }T \ ... BY ONE CHAR
-T{ 1STC 1 CHARS + -> 2NDC }T
-T{ 1STC C@ 2NDC C@ -> 1 2 }T
-T{ 3 1STC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 2 }T
-T{ 4 2NDC C! -> }T
-T{ 1STC C@ 2NDC C@ -> 3 4 }T
-
-ALIGN 1 ALLOT HERE ALIGN HERE 3 CELLS ALLOT
-CONSTANT A-ADDR CONSTANT UA-ADDR
-T{ UA-ADDR ALIGNED -> A-ADDR }T
-T{ 1 A-ADDR C! A-ADDR C@ -> 1 }T
-T{ 1234 A-ADDR ! A-ADDR @ -> 1234 }T
-T{ 123 456 A-ADDR 2! A-ADDR 2@ -> 123 456 }T
-T{ 2 A-ADDR CHAR+ C! A-ADDR CHAR+ C@ -> 2 }T
-T{ 3 A-ADDR CELL+ C! A-ADDR CELL+ C@ -> 3 }T
-T{ 1234 A-ADDR CELL+ ! A-ADDR CELL+ @ -> 1234 }T
-T{ 123 456 A-ADDR CELL+ 2! A-ADDR CELL+ 2@ -> 123 456 }T
-
-: BITS ( X -- U )
- 0 SWAP BEGIN DUP WHILE DUP MSB AND IF >R 1+ R> THEN 2* REPEAT DROP ;
-( CHARACTERS >= 1 AU, <= SIZE OF CELL, >= 8 BITS )
-T{ 1 CHARS 1 < -> <FALSE> }T
-T{ 1 CHARS 1 CELLS > -> <FALSE> }T
-( TBD: HOW TO FIND NUMBER OF BITS? )
-
-( CELLS >= 1 AU, INTEGRAL MULTIPLE OF CHAR SIZE, >= 16 BITS )
-T{ 1 CELLS 1 < -> <FALSE> }T
-T{ 1 CELLS 1 CHARS MOD -> 0 }T
-T{ 1S BITS 10 < -> <FALSE> }T
-
-T{ 0 1ST ! -> }T
-T{ 1 1ST +! -> }T
-T{ 1ST @ -> 1 }T
-T{ -1 1ST +! 1ST @ -> 0 }T
-
-\ ------------------------------------------------------------------------
-TESTING CHAR [CHAR] [ ] BL S"
-
-T{ BL -> 20 }T
-T{ CHAR X -> 58 }T
-T{ CHAR HELLO -> 48 }T
-T{ : GC1 [CHAR] X ; -> }T
-T{ : GC2 [CHAR] HELLO ; -> }T
-T{ GC1 -> 58 }T
-T{ GC2 -> 48 }T
-T{ : GC3 [ GC1 ] LITERAL ; -> }T
-T{ GC3 -> 58 }T
-T{ : GC4 S" XY" ; -> }T
-T{ GC4 SWAP DROP -> 2 }T
-T{ GC4 DROP DUP C@ SWAP CHAR+ C@ -> 58 59 }T
-
-\ ------------------------------------------------------------------------
-TESTING ' ['] FIND EXECUTE IMMEDIATE COUNT LITERAL POSTPONE STATE
-
-T{ : GT1 123 ; -> }T
-T{ ' GT1 EXECUTE -> 123 }T
-T{ : GT2 ['] GT1 ; IMMEDIATE -> }T
-T{ GT2 EXECUTE -> 123 }T
-HERE 3 C, CHAR G C, CHAR T C, CHAR 1 C, CONSTANT GT1STRING
-HERE 3 C, CHAR G C, CHAR T C, CHAR 2 C, CONSTANT GT2STRING
-T{ GT1STRING FIND -> ' GT1 -1 }T
-T{ GT2STRING FIND -> ' GT2 1 }T
-( HOW TO SEARCH FOR NON-EXISTENT WORD? )
-T{ : GT3 GT2 LITERAL ; -> }T
-T{ GT3 -> ' GT1 }T
-T{ GT1STRING COUNT -> GT1STRING CHAR+ 3 }T
-
-T{ : GT4 POSTPONE GT1 ; IMMEDIATE -> }T
-T{ : GT5 GT4 ; -> }T
-T{ GT5 -> 123 }T
-T{ : GT6 345 ; IMMEDIATE -> }T
-T{ : GT7 POSTPONE GT6 ; -> }T
-T{ GT7 -> 345 }T
-
-T{ : GT8 STATE @ ; IMMEDIATE -> }T
-T{ GT8 -> 0 }T
-T{ : GT9 GT8 LITERAL ; -> }T
-T{ GT9 0= -> <FALSE> }T
-
-\ ------------------------------------------------------------------------
-TESTING IF ELSE THEN BEGIN WHILE REPEAT UNTIL RECURSE
-
-T{ : GI1 IF 123 THEN ; -> }T
-T{ : GI2 IF 123 ELSE 234 THEN ; -> }T
-T{ 0 GI1 -> }T
-T{ 1 GI1 -> 123 }T
-T{ -1 GI1 -> 123 }T
-T{ 0 GI2 -> 234 }T
-T{ 1 GI2 -> 123 }T
-T{ -1 GI1 -> 123 }T
-
-T{ : GI3 BEGIN DUP 5 < WHILE DUP 1+ REPEAT ; -> }T
-T{ 0 GI3 -> 0 1 2 3 4 5 }T
-T{ 4 GI3 -> 4 5 }T
-T{ 5 GI3 -> 5 }T
-T{ 6 GI3 -> 6 }T
-
-T{ : GI4 BEGIN DUP 1+ DUP 5 > UNTIL ; -> }T
-T{ 3 GI4 -> 3 4 5 6 }T
-T{ 5 GI4 -> 5 6 }T
-T{ 6 GI4 -> 6 7 }T
-
-T{ : GI5 BEGIN DUP 2 > WHILE DUP 5 < WHILE DUP 1+ REPEAT 123 ELSE 345 THEN ; -> }T
-T{ 1 GI5 -> 1 345 }T
-T{ 2 GI5 -> 2 345 }T
-T{ 3 GI5 -> 3 4 5 123 }T
-T{ 4 GI5 -> 4 5 123 }T
-T{ 5 GI5 -> 5 123 }T
-
-T{ : GI6 ( N -- 0,1,..N ) DUP IF DUP >R 1- RECURSE R> THEN ; -> }T
-T{ 0 GI6 -> 0 }T
-T{ 1 GI6 -> 0 1 }T
-T{ 2 GI6 -> 0 1 2 }T
-T{ 3 GI6 -> 0 1 2 3 }T
-T{ 4 GI6 -> 0 1 2 3 4 }T
-
-\ ------------------------------------------------------------------------
-TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
-
-T{ : GD1 DO I LOOP ; -> }T
-T{ 4 1 GD1 -> 1 2 3 }T
-T{ 2 -1 GD1 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD1 -> MID-UINT }T
-
-T{ : GD2 DO I -1 +LOOP ; -> }T
-T{ 1 4 GD2 -> 4 3 2 1 }T
-T{ -1 2 GD2 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD2 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD3 DO 1 0 DO J LOOP LOOP ; -> }T
-T{ 4 1 GD3 -> 1 2 3 }T
-T{ 2 -1 GD3 -> -1 0 1 }T
-T{ MID-UINT+1 MID-UINT GD3 -> MID-UINT }T
-
-T{ : GD4 DO 1 0 DO J LOOP -1 +LOOP ; -> }T
-T{ 1 4 GD4 -> 4 3 2 1 }T
-T{ -1 2 GD4 -> 2 1 0 -1 }T
-T{ MID-UINT MID-UINT+1 GD4 -> MID-UINT+1 MID-UINT }T
-
-T{ : GD5 123 SWAP 0 DO I 4 > IF DROP 234 LEAVE THEN LOOP ; -> }T
-T{ 1 GD5 -> 123 }T
-T{ 5 GD5 -> 123 }T
-T{ 6 GD5 -> 234 }T
-
-T{ : GD6 ( PAT: T{0 0}T,T{0 0}TT{1 0}TT{1 1}T,T{0 0}TT{1 0}TT{1 1}TT{2 0}TT{2 1}TT{2 2}T )
- 0 SWAP 0 DO
- I 1+ 0 DO I J + 3 = IF I UNLOOP I UNLOOP EXIT THEN 1+ LOOP
- LOOP ; -> }T
-T{ 1 GD6 -> 1 }T
-T{ 2 GD6 -> 3 }T
-T{ 3 GD6 -> 4 1 2 }T
-
-\ ------------------------------------------------------------------------
-TESTING DEFINING WORDS: : ; CONSTANT VARIABLE CREATE DOES> >BODY
-
-T{ 123 CONSTANT X123 -> }T
-T{ X123 -> 123 }T
-T{ : EQU CONSTANT ; -> }T
-T{ X123 EQU Y123 -> }T
-T{ Y123 -> 123 }T
-
-T{ VARIABLE V1 -> }T
-T{ 123 V1 ! -> }T
-T{ V1 @ -> 123 }T
-
-T{ : NOP : POSTPONE ; ; -> }T
-T{ NOP NOP1 NOP NOP2 -> }T
-T{ NOP1 -> }T
-T{ NOP2 -> }T
-
-T{ : DOES1 DOES> @ 1 + ; -> }T
-T{ : DOES2 DOES> @ 2 + ; -> }T
-T{ CREATE CR1 -> }T
-T{ CR1 -> HERE }T
-T{ ' CR1 >BODY -> HERE }T
-T{ 1 , -> }T
-T{ CR1 @ -> 1 }T
-T{ DOES1 -> }T
-T{ CR1 -> 2 }T
-T{ DOES2 -> }T
-T{ CR1 -> 3 }T
-
-T{ : WEIRD: CREATE DOES> 1 + DOES> 2 + ; -> }T
-T{ WEIRD: W1 -> }T
-T{ ' W1 >BODY -> HERE }T
-T{ W1 -> HERE 1 + }T
-T{ W1 -> HERE 2 + }T
-
-\ ------------------------------------------------------------------------
-TESTING EVALUATE
-
-: GE1 S" 123" ; IMMEDIATE
-: GE2 S" 123 1+" ; IMMEDIATE
-: GE3 S" : GE4 345 ;" ;
-: GE5 EVALUATE ; IMMEDIATE
-
-T{ GE1 EVALUATE -> 123 }T ( TEST EVALUATE IN INTERP. STATE )
-T{ GE2 EVALUATE -> 124 }T
-T{ GE3 EVALUATE -> }T
-T{ GE4 -> 345 }T
-
-T{ : GE6 GE1 GE5 ; -> }T ( TEST EVALUATE IN COMPILE STATE )
-T{ GE6 -> 123 }T
-T{ : GE7 GE2 GE5 ; -> }T
-T{ GE7 -> 124 }T
-
-\ ------------------------------------------------------------------------
-TESTING SOURCE >IN WORD
-
-: GS1 S" SOURCE" 2DUP EVALUATE
- >R SWAP >R = R> R> = ;
-T{ GS1 -> <TRUE> <TRUE> }T
-
-VARIABLE SCANS
-: RESCAN? -1 SCANS +! SCANS @ IF 0 >IN ! THEN ;
-
-T{ 2 SCANS !
-345 RESCAN?
--> 345 345 }T
-
-: GS2 5 SCANS ! S" 123 RESCAN?" EVALUATE ;
-T{ GS2 -> 123 123 123 123 123 }T
-
-: GS3 WORD COUNT SWAP C@ ;
-T{ BL GS3 HELLO -> 5 CHAR H }T
-T{ CHAR " GS3 GOODBYE" -> 7 CHAR G }T
-T{ BL GS3
-DROP -> 0 }T \ BLANK LINE RETURN ZERO-LENGTH STRING
-
-: GS4 SOURCE >IN ! DROP ;
-T{ GS4 123 456
--> }T
-
-\ ------------------------------------------------------------------------
-TESTING <# # #S #> HOLD SIGN BASE >NUMBER HEX DECIMAL
-
-: S= \ ( ADDR1 C1 ADDR2 C2 -- T/F ) COMPARE TWO STRINGS.
- >R SWAP R@ = IF \ MAKE SURE STRINGS HAVE SAME LENGTH
- R> ?DUP IF \ IF NON-EMPTY STRINGS
- 0 DO
- OVER C@ OVER C@ - IF
- 2DROP <FALSE> UNLOOP EXIT THEN
- SWAP CHAR+ SWAP CHAR+
- LOOP
- THEN
- 2DROP <TRUE> \ IF WE GET HERE, STRINGS MATCH
- ELSE
- R> DROP 2DROP <FALSE> \ LENGTHS MISMATCH
- THEN ;
-
-: GP1 <# 41 HOLD 42 HOLD 0 0 #> S" BA" S= ;
-T{ GP1 -> <TRUE> }T
-
-: GP2 <# -1 SIGN 0 SIGN -1 SIGN 0 0 #> S" --" S= ;
-T{ GP2 -> <TRUE> }T
-
-: GP3 <# 1 0 # # #> S" 01" S= ;
-T{ GP3 -> <TRUE> }T
-
-: GP4 <# 1 0 #S #> S" 1" S= ;
-T{ GP4 -> <TRUE> }T
-
-24 CONSTANT MAX-BASE \ BASE 2 .. 36
-: COUNT-BITS
- 0 0 INVERT BEGIN DUP WHILE >R 1+ R> 2* REPEAT DROP ;
-COUNT-BITS 2* CONSTANT #BITS-UD \ NUMBER OF BITS IN UD
-
-: GP5
- BASE @ <TRUE>
- MAX-BASE 1+ 2 DO \ FOR EACH POSSIBLE BASE
- I BASE ! \ TBD: ASSUMES BASE WORKS
- I 0 <# #S #> S" 10" S= AND
- LOOP
- SWAP BASE ! ;
-T{ GP5 -> <TRUE> }T
-
-: GP6
- BASE @ >R 2 BASE !
- MAX-UINT MAX-UINT <# #S #> \ MAXIMUM UD TO BINARY
- R> BASE ! \ S: C-ADDR U
- DUP #BITS-UD = SWAP
- 0 DO \ S: C-ADDR FLAG
- OVER C@ [CHAR] 1 = AND \ ALL ONES
- >R CHAR+ R>
- LOOP SWAP DROP ;
-T{ GP6 -> <TRUE> }T
-
-: GP7
- BASE @ >R MAX-BASE BASE !
- <TRUE>
- A 0 DO
- I 0 <# #S #>
- 1 = SWAP C@ I 30 + = AND AND
- LOOP
- MAX-BASE A DO
- I 0 <# #S #>
- 1 = SWAP C@ 41 I A - + = AND AND
- LOOP
- R> BASE ! ;
-
-T{ GP7 -> <TRUE> }T
-
-\ >NUMBER TESTS
-CREATE GN-BUF 0 C,
-: GN-STRING GN-BUF 1 ;
-: GN-CONSUMED GN-BUF CHAR+ 0 ;
-: GN' [CHAR] ' WORD CHAR+ C@ GN-BUF C! GN-STRING ;
-
-T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T
-T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T
-T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T
-T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE
-T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T
-T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T
-
-: >NUMBER-BASED
- BASE @ >R BASE ! >NUMBER R> BASE ! ;
-
-T{ 0 0 GN' 2' 10 >NUMBER-BASED -> 2 0 GN-CONSUMED }T
-T{ 0 0 GN' 2' 2 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' F' 10 >NUMBER-BASED -> F 0 GN-CONSUMED }T
-T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T
-T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T
-T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T
-
-: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO.
- BASE @ >R BASE !
- <# #S #>
- 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY
- R> BASE ! ;
-T{ 0 0 2 GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 2 GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP 2 GN1 -> MAX-UINT DUP 0 }T
-T{ 0 0 MAX-BASE GN1 -> 0 0 0 }T
-T{ MAX-UINT 0 MAX-BASE GN1 -> MAX-UINT 0 0 }T
-T{ MAX-UINT DUP MAX-BASE GN1 -> MAX-UINT DUP 0 }T
-
-: GN2 \ ( -- 16 10 )
- BASE @ >R HEX BASE @ DECIMAL BASE @ R> BASE ! ;
-T{ GN2 -> 10 A }T
-
-\ ------------------------------------------------------------------------
-TESTING FILL MOVE
-
-CREATE FBUF 00 C, 00 C, 00 C,
-CREATE SBUF 12 C, 34 C, 56 C,
-: SEEBUF FBUF C@ FBUF CHAR+ C@ FBUF CHAR+ CHAR+ C@ ;
-
-T{ FBUF 0 20 FILL -> }T
-T{ SEEBUF -> 00 00 00 }T
-
-T{ FBUF 1 20 FILL -> }T
-T{ SEEBUF -> 20 00 00 }T
-
-T{ FBUF 3 20 FILL -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ FBUF FBUF 3 CHARS MOVE -> }T \ BIZARRE SPECIAL CASE
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 0 CHARS MOVE -> }T
-T{ SEEBUF -> 20 20 20 }T
-
-T{ SBUF FBUF 1 CHARS MOVE -> }T
-T{ SEEBUF -> 12 20 20 }T
-
-T{ SBUF FBUF 3 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 56 }T
-
-T{ FBUF FBUF CHAR+ 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 12 34 }T
-
-T{ FBUF CHAR+ FBUF 2 CHARS MOVE -> }T
-T{ SEEBUF -> 12 34 34 }T
-
-\ ------------------------------------------------------------------------
-TESTING OUTPUT: . ." CR EMIT SPACE SPACES TYPE U.
-
-: OUTPUT-TEST
- ." YOU SHOULD SEE THE STANDARD GRAPHIC CHARACTERS:" CR
- 41 BL DO I EMIT LOOP CR
- 61 41 DO I EMIT LOOP CR
- 7F 61 DO I EMIT LOOP CR
- ." YOU SHOULD SEE 0-9 SEPARATED BY A SPACE:" CR
- 9 1+ 0 DO I . LOOP CR
- ." YOU SHOULD SEE 0-9 (WITH NO SPACES):" CR
- [CHAR] 9 1+ [CHAR] 0 DO I 0 SPACES EMIT LOOP CR
- ." YOU SHOULD SEE A-G SEPARATED BY A SPACE:" CR
- [CHAR] G 1+ [CHAR] A DO I EMIT SPACE LOOP CR
- ." YOU SHOULD SEE 0-5 SEPARATED BY TWO SPACES:" CR
- 5 1+ 0 DO I [CHAR] 0 + EMIT 2 SPACES LOOP CR
- ." YOU SHOULD SEE TWO SEPARATE LINES:" CR
- S" LINE 1" TYPE CR S" LINE 2" TYPE CR
- ." YOU SHOULD SEE THE NUMBER RANGES OF SIGNED AND UNSIGNED NUMBERS:" CR
- ." SIGNED: " MIN-INT . MAX-INT . CR
- ." UNSIGNED: " 0 U. MAX-UINT U. CR
-;
-
-T{ OUTPUT-TEST -> }T
-\ ------------------------------------------------------------------------
-TESTING INPUT: ACCEPT
-
-CREATE ABUF 80 CHARS ALLOT
-
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
- ABUF 80 ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
-
-T{ ACCEPT-TEST -> }T
-Vingt fois sur le métier remettez votre ouvrage, ... Boileau, L'Art poétique
-\ ------------------------------------------------------------------------
-TESTING DICTIONARY SEARCH RULES
-
-T{ : GDX 123 ; : GDX GDX 234 ; -> }T
-
-T{ GDX -> 123 234 }T
-
-CR .( End of Core word set tests) CR
-
-
-$0A BASE !
-ECHO
- ; end of core test
-PWR_HERE ; preserved against power OFF
! P2.6 - Switch SW2 <--- LCD contrast - (finger ;-)
!
!
-! GND - J1.2 <-------+---0V0----------> 1 LCD_Vss
-! VCC - J1.3 >------ | --3V6-----+----> 2 LCD_Vdd
+! GND - J2.1 <-------+---0V0----------> 1 LCD_Vss
+! VCC - J1.1 >------ | --3V6-----+----> 2 LCD_Vdd
! | |
! ___ 470n ---
! ^ ---
! P4.1 - LFXIN 32768Hz quartz
! P4.2 - LFXOUT 32768Hz quartz
!
+! VCC - J1.1 ----> VCC SD_CardAdapter
+! GND - J2.1 <---> GND SD_CardAdapter
+! P5.1 - UCB0 CLK J1.7 ----> CLK SD_CardAdapter (SCK)
+! P8.1 - J1.2 ----> CS SD_CardAdapter (Card Select)
+! P5.2 - UCB0 TXD/SIMO J2.15 ----> SDI SD_CardAdapter (MOSI)
+! P5.3 - UCB0 RXD/SOMI J2.14 <---- SDO SD_CardAdapter (MISO)
+! P8.0 - J1.6 <---- CD SD_CardAdapter (Card Detect)
+!
!
!
! P8.2 - Soft I2C_Master J1.9 ----> SDA software I2C Master
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
\ ******************************\
\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
\ ******************************\
-MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
XOR IP,X \ (new XOR old) Toggle bit (13)
BIT #BIT13,X \ X(13) = New_RC5_command
0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
THEN \
-XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
\ ******************************\
\ RC5_ComputeNewRC5word \
\ ******************************\
SUB #6,PSP
MOV TOS,4(PSP)
BEGIN
- BIT #$1000,&RTCCTL0 \ test RTCRDY flag
+ BIT.B #RTCRDY,&RTCCTL1 \ test RTCRDY flag
0<> UNTIL \ wait until RTCRDY high
MOV &RTCYEARL,2(PSP) \ year
MOV.B &RTCMON,TOS
2 U.R $2F EMIT .
;
\
-CODE DATE!
+: DATE!
+DEPTH 2 > IF
+ HI2LO
MOV TOS,&RTCYEARL \ year
MOV.B @PSP,&RTCMON \ month \ @PSP+ don't work because byte format !
MOV.B 2(PSP),&RTCDAY \ day \ @PSP+ don't work because byte format !
ADD #4,PSP
MOV @PSP+,TOS \
-COLON
+ LO2HI
+THEN
." we are on " DATE?
;
\
CODE TIME?
SUB #6,PSP
- MOV TOS,4(PSP) \ save TOS
+ MOV TOS,4(PSP) \ save TOS
BEGIN
- BIT #$1000,&RTCCTL0 \ test RTCRDY flag
- 0<> UNTIL \ wait until RTCRDY high
+ BIT.B #RTCRDY,&RTCCTL1 \
+ 0<> UNTIL \ wait until RTCRDY high
MOV.B &RTCSEC,TOS
- MOV TOS,2(PSP) \ seconds
+ MOV TOS,2(PSP) \ seconds
MOV.B &RTCMIN,TOS
- MOV TOS,0(PSP) \ minutes
- MOV.B &RTCHOUR,TOS \ hours
+ MOV TOS,0(PSP) \ minutes
+ MOV.B &RTCHOUR,TOS \ hours
COLON
2 U.R $3A EMIT
2 U.R $3A EMIT 2 U.R
;
\
: TIME!
+DEPTH 1 > IF
DEPTH 2 = IF 0 THEN \ to allow "hour min TIME!" scheme
HI2LO
MOV TOS,&RTCSEC \ seconds
ADD #4,PSP
MOV @PSP+,TOS \
LO2HI
+THEN
." it is " TIME?
;
\
ABUF ABUF 20 (ACCEPT) EVALUATE CR 3 SPACES DATE!
CR CR ." TIME (HMS or HM): "
ABUF ABUF 20 (ACCEPT) EVALUATE CR 3 SPACES TIME!
- CR
- PWR_STATE \ auto remove all this application !
+ CR
HI2LO
MOV #PSTACK,PSP \ to avoid stack empty error if lack of typed values.
MOV @RSP+,IP
MOV @IP+,PC
ENDCODE
-
\
-GET_TIME \ all words created by RTC.f are removed
+PWR_HERE
+ \
+GET_TIME
-\ how to test SD_CARD driver on your target (excepted MSP-EXP430FR4133 without hardware multiplier) :
+\ how to test SD_CARD driver on your launchpad:
-\ connect the launchpad to your PC on a free USB port
-\ on the launchpad remove the jumpers GND, RX, TX of programming port (don't remove TST, RST and VCC jumpers)
+\ remove the jumpers RX, TX of programming port (don't remove GND, TST, RST and VCC)
+\ wire PL2303TA/HXD: GND <-> GND, RX <-- TX, TX --> RX
+\ connect it to your PC on a free USB port
\ connect the PL2303TA/HXD cable to your PC on another free USB port
-\ wire PL2303TA/HXD to the programming port of your launchpad : GND <-> GND, RX <-- TX, TX --> RX
-\ start TERATERM, select PL2303TA/HXD port
\ configure TERATERM as indicated in forthMSP430FR.asm
-\ if you have a MSP-EXP430FR5994, program your launchpad with MSP_EXP430FR5994_3Mbds_SD_CARD.txt via TI interface:
-\ to do, drag and drop this file onto MSP430FR5994prog.bat
-\ else edit forthMSP430FR.asm with scite editor
+\ if you have a MSP-EXP430FR5994 launchpad, program it with MSP_EXP430FR5994_3Mbds_SD_CARD.txt
+\ to do, drag and drop this file onto prog.bat
+\ nothing else to do!
+
-\ with (SHIFT+F8), set param1 as your DEVICE and param2 as your TARGET
-\ uncomment your target,
+\ else edit forthMSP430FR.asm with scite editor
+\ uncomment your target, copy it
+\ paste it into (SHIFT+F8) param1
\ set DTC .equ 1
\ FREQUENCY .equ 16
\ THREADS .equ 16
\ TERMINALBAUDRATE .equ 3000000
\
-\ uncomment TERMINALXONXOFF
-\ LF_XTAL
+\ uncomment: CONDCOMP
\ MSP430ASSEMBLER
\ SD_CARD_LOADER
\ SD_CARD_READ_WRITE
-
-\ compile for your target (CTRL+0)
-\ then program your target via TI interface (CTRL+1).
-
-
-\ format FAT16 or FAT32 a SD_CARD memory (max 64GB)
-\ create folder \MISC on this SD_CARD memory (FastForth don't do yet)
-\ put it in the target SD slot wired as described in MSP430-FORTH\target.pat,
-
-\ type COLD from the console input to reset FAST FORTH,
-
-
-\ with Send_File.4th_to_SD_CARD_target.bat (or from scite editor, menu tools), send to SD_CARD:
-\ CORETSTH.4th
-\ TSTWORDS.4th
-
-\ with Send_File.4th_to_SD_CARD_target.bat, send to SD_CARD\MISC:
-\ TESTASM.4TH (don't forget to add path \MISC on the 2th window opened by TERATERM)
+\
+\ compile for your target (CTRL+0)
+\
+\ program your target via TI interface (CTRL+1)
+\
+\ then wire your SD_Card module as described in your MSP430-FORTH\target.pat file
-\ and if don't know how to do, double clic on this bat file.
-\ with Send_file.f_to_SD_CARD_target.bat, send to SD_CARD: (on SD_CARD files will have 4th extension)
-\ SD_TOOLS.f
-\ SD_TEST.f
-\ PROG10k.f
-\ RTC.f
+\ format FAT16 or FAT32 a SD_CARD memory (max 64GB) with "FRxxxx" in the disk name
+\ drag and drop \CONDCOMP\MISC folder on the root of this SD_CARD memory (FastForth doesn't do yet)
+\ put it in your target SD slot
+\ if no reset, type COLD from the console input (teraterm) to reset FAST FORTH
+\ with MSP430FR5xxx or MSP430FR6xxx targets, you can first set RTC:
+\ by downloading RTC.f with SendSourceFileToTarget.bat
+\ then terminal input asks you to type (with spaces) (DMY), then (HMS) (or (HM)),
+\ So, subsequent copied files will be dated:
-\ then, from input terminal (TERATERM),
-\ LOAD" RTC.4th", type (with spaces) Day Month Year, then type Hours Minutes Seconds (or Hours Minutes),
-\ LOAD" SD_TEST.4TH" that load this file.
+\ with CopySourceFileToTarget_SD_Card.bat (or better, from scite editor, menu tools):
+\ copy TESTASM.4TH to \MISC\TESTASM.4TH (add path \MISC in the window opened by TERATERM)
+\ copy TSTWORDS.4TH to \TSTWORDS.4TH
+\ copy CORETEST_xMPY.4TH to \CORETEST.4TH (x=S for FR4133, else x=H; suppr _xMPY in the window opened by TERATERM)
+\ copy SD_TOOLS.f to \SD_TOOLS.4TH
+\ copy SD_TEST.f to \SD_TEST.4TH
+\ copy PROG10k.f to \PROG10k.4TH
+\ copy RTC.f to \RTC.4TH ( doesn't work with if FR2xxx or FR4xxx)
-LOAD" SD_TOOLS.4TH"
-RST_HERE
-NOECHO
-\ we can see interest of preprocessing that allows the use of the PROGRAMSTART address, not recognized by FASTFORTH
-\ in the preprocessed file SD_TEST.4th, PROGRAMSTART will be replaced by its value.
-\ PROGRAMSTART is defined in \config\gema\MSP430FR_FastForth.pat
: SD_TEST
ECHO CR
." 4 Write a dump of the FORTH kernel to yourfile.txt" CR
." 5 append a dump of the FORTH kernel to yourfile.txt" CR
." 6 Load truc (test error)" CR
+ ." 7 Set date and time" CR
." your choice : "
KEY
48 -
DUP 1 =
IF .
-\ LOAD" COMPHMPY.4TH" \ bug, bug, bug: only 2th line is executed
-\ LOAD" CORETST1.4TH" \ why ?
- LOAD" CORETSTH.4TH" \ so CORETSTH.4TH is the sum of two previous files
+ LOAD" CORETEST.4TH"
ELSE DUP 2 =
IF .
- LOAD" Prog10k.4th"
+ LOAD" PROG10K.4TH"
ELSE DUP 3 =
IF .
- READ" Prog10k.4th"
+ READ" PROG10K.4TH"
BEGIN
- READ
- UNTIL
+ READ \ sequentially read 512 bytes
+ UNTIL \ prog10k.4TH is closed
ELSE DUP 4 =
IF .
- DEL" yourfile.txt"
- WRITE" yourfile.txt"
+ DEL" YOURFILE.TXT"
+ WRITE" YOURFILE.TXT"
['] SD_EMIT IS EMIT
PROGRAMSTART HERE OVER - DUMP
['] (EMIT) IS EMIT
CLOSE
ELSE DUP 5 =
IF .
- WRITE" yourfile.txt"
+ WRITE" YOURFILE.TXT"
['] SD_EMIT IS EMIT
PROGRAMSTART HERE OVER - DUMP
['] (EMIT) IS EMIT
ELSE DUP 6 =
IF .
LOAD" truc"
- ELSE
- DROP ." ?"
- CR ." loading TSTWORDS.4th..."
- LOAD" TSTWORDS.4TH"
+ ELSE DUP 7 =
+ IF .
+ LOAD" RTC.4TH"
+ ELSE
+ DROP ." ?"
+ CR ." loading TSTWORDS.4TH..."
+ LOAD" TSTWORDS.4TH"
+ THEN
THEN
THEN
THEN
THEN
THEN
THEN
- CR ." It's done..."
;
-PWR_HERE
+; It's done..."
SD_TEST
+++ /dev/null
-you have downloaded your copy of gitlab fast forth onto a folder shared and connected as virtual drive (A: or B: or ... or Y: or Z:)
- so config files.pat for the preprocessor gema.exe are in the folder \config\gema\
- and batch file are in the folder \config\scite\msp430_as\,
-you have installed the last version of teraterm,
-you have installed the last version of gema.exe in the folder \prog\gema\.
-
-finally, edit properties of these three shortcuts "send_file.f_to_target.bat", "send_file.4th_to_target.bat file" and
-process_file.f_to_file.4th.bat to change the drive letter B: as yours.
-
-before sending a file :
-=====================
- teraterm must be well configured, and its config must be saved,
- i.e. you must see the FAST FORTH prompt "ok" when you type <return> on the teraterm terminal. (you can then close the teraterm window).
-
-
-to send a file.f to a specific target :
-=====================================
- 1 clic on the what_you_want.f file example : utility.f
- 2 ctrl+clic on the what_you_want.pat file example : MSP_EXP430FR5969.pat (target = MSP_EXP430FR5969 launchpad)
- 3 release ctrl and clic
- 4 then drag and drop the what_you_want.f file onto the send_file.f_to_target.bat file
- - -
-the *.pat files are used by the preprocesor GEMA.exe to translate symbolic labels from *.f files in their values to *.4th files.
-
-to send a file.4th to any target :
-================================
- drag and drop the what_you_want.4th file onto the send_file.4th_to_target.bat file example : coretest.4th
- --- ---
-
-to preprocess file.f to file.4th (debug) :
-========================================
-do same as to send a file.f, but with process_file.f_to_file.4th.bat
-
-
-To send a file to be written on SD_CARD target, process with the specific SD_CARD_target.bat.
-When TERATERM ask you for file to send, you can add a path to the file to be written on SD_CARD.
-
-
-
-
-As these bat files are in fact shortcuts, you can define them to execute with hidden window.
-
-
-
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr2433 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr4133 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr5739 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr5969 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr5994 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
-a:\prog\MSP430Flasher\msp430flasher -e ERASE_TOTAL
\ No newline at end of file
+a:\prog\MSP430Flasher\msp430flasher -e ERASE_TOTAL
+pause
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr6989 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
--- /dev/null
+\ BOOT.4th
+
+\ SYSRSTIV decimal values for MSP430FR5994
+\ ----------------------------------------
+\ 00 No interrupt pending
+\ 02 Brownout (BOR)
+\ 04 RSTIFG RST/NMI (BOR)
+\ 06 PMMSWBOR software BOR (BOR)
+\ 08 LPMx.5 wake up (BOR)
+\ 10 Security violation (BOR)
+\ 12 Reserved
+\ 14 SVSHIFG SVSH event (BOR)
+\ 16 Reserved
+\ 18 Reserved
+\ 20 PMMSWPOR software POR (POR)
+\ 22 WDTIFG watchdog timeout (PUC)
+\ 24 WDTPW password violation (PUC)
+\ 26 FRCTLPW password violation (PUC)
+\ 28 Uncorrectable FRAM bit error detection (PUC)
+\ 30 Peripheral area fetch (PUC)
+\ 32 PMMPW PMM password violation (PUC)
+\ 34 MPUPW MPU password violation (PUC)
+\ 36 CSPW CS password violation (PUC)
+\ 38 MPUSEGIPIFG encapsulated IP memory segment violation (PUC)
+\ 40 MPUSEGIIFG information memory segment violation (PUC)
+\ 42 MPUSEG1IFG segment 1 memory violation (PUC)
+\ 44 MPUSEG2IFG segment 2 memory violation (PUC)
+\ 46 MPUSEG3IFG segment 3 memory violation (PUC)
+
+\ values added by FAST FORTH
+\ --------------------------
+\ 05 reset after compilation of FAST FORTH kernel
+\ -1 hardware DEEP RESET
+
+; ================
+; BOOTSTRAP
+; ================
+
+\ Causes of reset is kept in SYSRSTIV register. Their values are device specific.
+\ WARM displays the content of SYSRSTIV register.
+\ When BOOT.4TH is called by the FastForth bootstrap, ths SYSRSTIV value is on
+\ the paramater stack, ready to test:
+
+$05 = [IF] ; test cause of reset
+LOAD" SD_TEST.4TH"
+[THEN]
+ECHO ; in all case, don't forget to set ECHO !
--- /dev/null
+\ -*- coding: utf-8 -*-
+\ http://patorjk.com/software/taag/#p=display&f=Banner&t=Fast Forth
+
+\ Fast Forth For Texas Instrument MSP430FRxxxx FRAM devices
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY; without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+
+\ https://forth-standard.org/standard/core/HOLDS
+\ Adds the string represented by addr u to the pictured numeric output string
+\ compilation use: <# S" string" HOLDS #>
+\ free HOLDS chars space in the 32+2 bytes HOLD area = {24,21,0} chars with a 32 bits sized {hexa,decimal,binary} number.
+\ perfect to display all a line on LCD 2x20 chars...
+\ C HOLDS addr u --
+CODE HOLDS
+ MOV @PSP+,X \ 2
+ ADD TOS,X \ 1 src
+ MOV &HP,Y \ 3 dst
+BEGIN SUB #1,Y \ 1 dst-1
+ SUB #1,X \ 1 src-1
+ SUB #1,TOS \ 1 cnt-1
+U>= WHILE \ 2
+ MOV.B @X,0(Y) \ 4
+REPEAT \ 2
+ MOV Y,&HP \ 3
+ MOV @PSP+,TOS \ 2
+ NEXT \ 4 15 words
+ENDCODE
+
+
+\ https://forth-standard.org/standard/core/StoD
+\ Convert the number n to the double-cell number d with the same numerical value.
+CODE S>D \ n -- d
+SUB #2,PSP
+MOV TOS,0(PSP)
+BIT #$8000,TOS
+MOV #0,TOS
+0<> IF
+ SUB #1,TOS
+THEN
+NEXT
+ENDCODE
+ \
+
+\ https://forth-standard.org/standard/core/VALUE
+
+\ Skip leading space delimiters. Parse name delimited by a space.
+\ Create a definition for name with the execution semantics defined below,
+\ with an initial value equal to x.
+
+\ Place x on the stack. The value of x is that given when name was created,
+\ until the phrase x TO name is executed, causing a new value of x to be assigned to name.
+
+CODE VALUE
+ MOV #CONSTANT,PC
+ENDCODE
+
+CODE TO
+ MOV #IS,PC
+ENDCODE IMMEDIATE
+
+
+
+
+\ input: file size double word Sector_per_cluster {1,2,4,8,16,32,64}
+\ output cluster double word and cluster offset
+CODE SD_DIV \ SIZ_LO SIZ_HI SECPERCLU -- CLU_LO CLU_HI OFFSET
+MOV.B 3(PSP),Y \ Y = 0:CurSizeLOHi
+MOV.B @PSP,X \ X = 0:CurSizeHILo
+SWPB X \ X = CurSizeHIlo:0
+ADD Y,X \ X = CurSizeHIlo:CurSizeLOhi
+MOV.B 1(PSP),Y \ Y:X = CurSize / 256
+\ RRA Y \ Y = Sectors number_High
+\ RRC X \ X = Sectors number_Low
+
+MOV.B TOS,T \ T = divisor = SECPERCLU
+
+MOV #0,W \ 1 W = 0:REMlo = 0
+MOV #8,S \ 1 CNT
+\ RRA T \ 1 0>0:SPClo>C preshift one right DIVISOR
+BEGIN
+ RRA Y \ 1 0>SEC_HI>C
+ RRC X \ 1 C>SEC_LO>C
+ RRC.B W \ 1 C>REMlo>C
+ SUB #1,S \ CNT-1
+ RRA T \ 1 0>SPChi:SPClo>C
+U>= UNTIL
+BEGIN
+ RRA W \ 1 0>0:REMlo>C
+ SUB #1,S \ 1 CNT-1
+\ 0= UNTIL \ Y = OFFSET, S = CLU_LO, W = CLU_HI
+S< UNTIL \ Y = OFFSET, S = CLU_LO, W = CLU_HI
+MOV.B W,TOS \ -- xx xx REMlo
+MOV X,2(PSP) \ -- CLU_LO xx OFFSET
+MOV Y,0(PSP) \ -- CLU_LO CLU_HI OFFSET
+MOV @IP+,PC
+ENDCODE
+
+
+\ tests tools
+\ -----------
+ \
+
+VARIABLE >PAD \ declaration to do in start of source file
+PAD IS >PAD \ init >PAD, idem
+ \
+
+\ sample anything during an interrupt for example
+\ usage in ASSEMBLER WORD : ... LO2HI SAMPLE HI2LO ... if IP is already saved
+\ usage in ASSEMBLER WORD : ... PUSH IP LO2HI SAMPLE HI2LO MOV @RSP+,IP ... if IP is not already saved
+\ usage in FORTH WORD : ... SAMPLE ...
+
+CODE SAMPLE2PAD
+CMP #TIB,&>PAD \ 4 do nothing if [>PAD] = TIB
+0<> IF \ 2
+ MOV &>PAD,R6 \ 3 R6 = rDOVAR
+ MOV &TB0R,0(R6) \ 5 we want sample TB0R
+ MOV W,2(R6)
+ ADD #4,&>PAD \ 3
+ MOV #R>,R6 \ 2 RFROM ==> rDOVAR
+THEN \
+MOV @IP+,PC \ 4
+ENDCODE \ add LO2HI = 10 + 23 = 33 cycles ==> 4us @ 8MHz
+ \
+
+\ display samples, up to 42 samples
+CODE DISPLAY_S \ --
+CMP #PAD,&>PAD
+0= IF
+ NEXT
+THEN
+COLON
+CR
+>PAD @ PAD DO \ limit first --
+ I @ U.
+2 +LOOP
+PAD IS >PAD \ reset >PAD
+;
+ \
+
+
+
+
+DEFER TEST
+ \
+CODE NOOP \ compile MOV #NEXT,PC
+NEXT
+ENDCODE
+ \
+
+CODE SAMPLE. \ display what you want ( much slower than SAMPLE2PAD )
+ SUB #4,PSP
+ MOV TOS,2(PSP)
+ MOV &BASE,0(PSP)
+ MOV &GPFLAGS,TOS \ we want sample GPFLAGS
+ MOV #$10,&BASE
+ PUSHM S,Y
+ COLON
+ ." $" U.
+ BASE !
+ HI2LO
+ MOV @RSP+,IP
+ POPM Y,S
+ NEXT
+ENDCODE
+ \
+
+\ ' SAMPLE. IS TEST \ to start test
+\ ' NOOP IS TEST \ to stop test
+
+
--- /dev/null
+\ -*- coding: utf-8 -*-
+\
+\ Fast Forth For Texas Instrument MSP430FRxxxx FRAM devices
+\ Copyright (C) <2017> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY; without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+MARKER {CONDCOMP}
+ \
+
+
+
+
+\ COMPARE ( c-addr1 u1 c-addr2 u2 -- n )
+\ https://forth-standard.org/standard/string/COMPARE
+\ Compare the string specified by c-addr1 u1 to the string specified by c-addr2 u2.
+\ The strings are compared, beginning at the given addresses, character by character,
+\ up to the length of the shorter string or until a difference is found.
+\ If the two strings are identical, n is zero.
+\ If the two strings are identical up to the length of the shorter string,
+\ n is minus-one (-1) if u1 is less than u2 and one (1) otherwise.
+\ If the two strings are not identical up to the length of the shorter string,
+\ n is minus-one (-1) if the first non-matching character in the string specified by c-addr1 u1
+\ has a lesser numeric value than the corresponding character in the string specified by c-addr2 u2 and one (1) otherwise.
+CODE COMPARE
+ MOV TOS,S \ 1 u2 = S
+ MOV @PSP+,Y \ 2 addr2 = Y
+ MOV @PSP+,T \ 2 u1 = T
+ MOV @PSP+,X \ 2 addr1 = X
+BEGIN MOV T,TOS \ 1
+ ADD S,TOS \ 1
+ 0= ?GOTO FW3 \ 2 end of all successfull comparisons
+ SUB #1,S \ 1
+ 0< ?GOTO FW2 \ 2 u2<u1 ==> u1>u2
+ SUB #1,T \ 1
+ 0< ?GOTO FW1 \ 2 u1<u2
+ ADD #1,X \ 1
+ CMP.B @Y+,-1(X) \ 4 char1-char2
+0<> UNTIL \ 2 char1=char2 17~ loop
+ U< IF \ char1<char2
+FW1 MOV #-1,TOS \ 1
+ MOV @IP+,PC \ 4
+ THEN \ 2 char1>char2
+FW2 MOV #1,TOS \ 1
+FW3 MOV @IP+,PC \ 4 20 words
+ENDCODE
+ \
+
+\ [THEN]
+\ https://forth-standard.org/standard/tools/BracketTHEN
+: [THEN]
+; IMMEDIATE
+ \
+
+\ [ELSE]
+\ Compilation:
+\ Perform the execution semantics given below.
+\ Execution:
+\ ( "<spaces>name ..." -- )
+\ Skipping leading spaces, parse and discard space-delimited words from the parse area,
+\ including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN],
+\ until the word [THEN] has been parsed and discarded.
+\ If the parse area becomes exhausted, it is refilled as with REFILL.
+: [ELSE]
+1 \ -- level
+BEGIN
+ BEGIN BL WORD COUNT \ -- lvl adr len
+ DUP \ -- lvl adr len len
+ WHILE \ -- lvl adr len test len
+ OVER OVER \ -- lvl adr len adr len OVER OVER = 2DUP
+ S" [IF]" COMPARE \ -- lvl adr len flag
+ 0= IF \ -- lvl adr len
+ DROP DROP 1 + \ -- lvl+1
+ ELSE \ -- lvl adr len
+ OVER OVER \ -- lvl adr len adr len
+ S" [ELSE]" COMPARE
+ 0= IF \ -- lvl adr len
+ DROP DROP 1 - DUP \ -- lvl-1 lvl-1
+ IF 1 + \ -- lvl' = lvl
+ THEN \ -- lvl'
+ ELSE \ -- lvl adr len
+ S" [THEN]" COMPARE
+ 0= IF 1 - \ -- lvl' = lvl-1
+ THEN
+ THEN
+ THEN \ -- lvl'
+ ?DUP 0= IF
+ EXIT \ -- if lvl = 0
+ THEN \ -- lvl'
+ REPEAT
+ \ -- lvl adr len
+ DROP DROP \ -- lvl
+ CR ." ko "
+ TIB DUP TIB_SIZE \ refill TIB with next line
+ ACCEPT
+ HI2LO
+ MOV TOS,&SOURCE_LEN
+ MOV @PSP+,&SOURCE_ADR
+ MOV @PSP+,TOS
+ MOV #0,&>IN
+ LO2HI
+AGAIN \ -- lvl
+; IMMEDIATE
+ \
+
+\ [IF]
+\ https://forth-standard.org/standard/tools/BracketIF
+\ Compilation:
+\ Perform the execution semantics given below.
+\ Execution: ;( flag | flag "<spaces>name ..." -- )
+\ If flag is true, do nothing. Otherwise, skipping leading spaces,
+\ parse and discard space-delimited words from the parse area,
+\ including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN],
+\ until either the word [ELSE] or the word [THEN] has been parsed and discarded.
+\ If the parse area becomes exhausted, it is refilled as with REFILL. [IF] is an immediate word.
+\ An ambiguous condition exists if [IF] is POSTPONEd,
+\ or if the end of the input buffer is reached and cannot be refilled before the terminating [ELSE] or [THEN] is parsed.
+: [IF]
+0= IF POSTPONE [ELSE]
+THEN
+; IMMEDIATE
+ \
+
+\ [UNDEFINED]
+\ https://forth-standard.org/standard/tools/BracketUNDEFINED
+\ Compilation:
+\ Perform the execution semantics given below.
+\ Execution: ( "<spaces>name ..." -- flag )
+\ Skip leading space delimiters. Parse name delimited by a space.
+\ Return a false flag if name is the name of a word that can be found,
+\ otherwise return a true flag.
+: [UNDEFINED]
+ BL WORD FIND NIP 0=
+; IMMEDIATE
+ \
+
+\ [DEFINED]
+\ https://forth-standard.org/standard/tools/BracketDEFINED
+\ Compilation:
+\ Perform the execution semantics given below.
+\ Execution:
+\ ( "<spaces>name ..." -- flag )
+\ Skip leading space delimiters. Parse name delimited by a space.
+\ Return a true flag if name is the name of a word that can be found,
+\ otherwise return a false flag. [DEFINED] is an immediate word.
+: [DEFINED]
+ BL WORD FIND NIP
+; IMMEDIATE
+ \
+
+RST_HERE
; ------------------------
-; file name : coretst1.4th
+; file name : coretest.4th
; ------------------------
-ECHO ; if an error occurs, uncomment this line before new download to find it.
+RST_STATE ; so ANS_COMPLEMENT_xx_MPY is conserved ;
\ From: John Hayes S1I
: ACCEPT-TEST
CR ." PLEASE TYPE UP TO 80 CHARACTERS:" CR
-\ ABUF 80 ACCEPT
- ABUF 80 (ACCEPT) \ JMT: because ACCEPT is DEFERred to SD_ACCEPT
+ ABUF 80 ACCEPT
CR ." RECEIVED: " [CHAR] " EMIT
ABUF SWAP TYPE [CHAR] " EMIT CR
;
T{ ACCEPT-TEST -> }T
+Vingt fois sur le métier remettez votre ouvrage, ... Boileau, L'Art poétique
\ ------------------------------------------------------------------------
TESTING DICTIONARY SEARCH RULES
CR .( End of Core word set tests) CR
-$0A BASE !
+\ ------------------------------------------------------------------------
+\ you must set ON compilation switch LOWERCASE to pass this test
+TESTING COMPARE
+: CMOVE MOVE ;
+: s1 S" abcdefghijklmnopqrstuvwxyz" ;
+: s6 S" 123456" ;
+
+T{ s1 s1 COMPARE -> 0 }T
+T{ s1 PAD SWAP CMOVE -> }T \ Copy s1 to PAD
+T{ s1 PAD OVER COMPARE -> 0 }T
+T{ s1 PAD 6 COMPARE -> 1 }T
+T{ PAD 10 s1 COMPARE -> -1 }T
+T{ s1 PAD 0 COMPARE -> 1 }T
+T{ PAD 0 s1 COMPARE -> -1 }T
+T{ s1 s6 COMPARE -> 1 }T
+T{ s6 s1 COMPARE -> -1 }T
+: "abdde" S" abdde" ;
+: "abbde" S" abbde" ;
+: "abcdf" S" abcdf" ;
+: "abcdee" S" abcdee" ;
+
+T{ s1 "abdde" COMPARE -> -1 }T
+T{ s1 "abbde" COMPARE -> 1 }T
+T{ s1 "abcdf" COMPARE -> -1 }T
+T{ s1 "abcdee" COMPARE -> 1 }T
+
+: s11 S" 0abc" ;
+: s12 S" 0aBc" ;
+
+T{ s11 s12 COMPARE -> 1 }T
+T{ s12 s11 COMPARE -> -1 }T
- ; happy end of core test
+$0A BASE !
+ECHO
+ ; end of core test
+PWR_HERE ; preserved against power OFF ;
--- /dev/null
+! -*- coding: utf-8 -*-
+! ChipStick_FR2433.pat
+!
+! Fast Forth For M. Ken Boak "ChipStick"
+!
+! Copyright (C) <2016> <J.M. THOORENS>
+!
+! This program is free software: you can redistribute it and/or modify
+! it under the terms of the GNU General Public License as published by
+! the Free Software Foundation, either version 3 of the License, or
+! (at your option) any later version.
+!
+! This program is distributed in the hope that it will be useful,
+! but WITHOUT ANY WARRANTY; without even the implied warranty of
+! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+! GNU General Public License for more details.
+!
+! You should have received a copy of the GNU General Public License
+! along with this program. If not, see <http://www.gnu.org/licenses/>.
+!
+!
+!
+! ======================================================================
+! MSP430FR2433 Config
+! ======================================================================
+
+@define{@read{/config/gema/MSP430FR2433.pat}}
+@define{@read{/config/gema/MSP430FR2x4x_FastForth.pat}}
+@define{@read{/config/gema/FastForthREGtoTI.pat}}
+@define{@read{/config/gema/RemoveComments.pat}}
+
+! ---------------------------------------------------
+! CHIPSTICK_FR2433 <--> OUTPUT WORLD
+! ---------------------------------------------------
+! P3.1 - LED1
+!
+! P2.1 - PL2.2 - SW1
+! P2.0 - PL2.3 - SW2
+!
+! +--4k7-< DeepRST <-- GND
+! |
+! P1.4 - UCA0 TXD PL1.4 - <-+-> RX UARTtoUSB bridge
+! P1.5 - UCA0 RXD PL1.3 - <---- TX UARTtoUSB bridge
+! P3.2 - RTS PL1.2 - ----> CTS UARTtoUSB bridge (if TERMINALCTSRTS option)
+! -
+! P3.0 - PL1.7 - ----> /CS SPI_RAM
+! P1.1 - UCB0 CLK PL1.9 - ----> CLK SPI_RAM
+! P1.2 - UCB0 SIMO PL1.10 - ----> SI SPI_RAM
+! P1.3 - UCB0 SOMI PL2.10 - <---- S0 SPI_RAM
+!
+!
+! P1.1 - UCB0 CLK PL1.9 - ----> SD_CLK
+! P1.2 - UCB0 SIMO PL1.10 - ----> SD_SDI
+! P1.3 - UCB0 SOMI PL2.10 - <---- SD_SDO
+! P2.3 - PL1.6 - <---- SD_CD (Card Detect)
+! P2.2 - PL2.9 - ----> SD_CS (Card Select)
+!
+! P1.2 - UCB0 SDA PL1.10 - <---> SDA I2C Slave
+! P1.3 - UCB0 SCL PL2.10 - ----> SCL I2C Slave
+!
+! P2.2 - PL2.9 - ----> SCL I2C SoftMaster
+! P2.0 - PL2.3 - <---> SDA I2C SoftMaster
+!
+! P1.0 - UCB0 STE PL1.8 - <---- TSSOP32236 (IR RC5)
+
+
+! ============================================
+! FORTH I/O :
+! ============================================
+TERM_TX=\$10! ; P1.4 = TX
+TERM_RX=\$20! ; P1.5 = RX
+TERM_TXRX=\$30!
+
+TERM_REN=\$206!
+TERM_SEL=\$20C!
+TERM_IE=\$21A!
+TERM_IFG=\$21C!
+Deep_RST=\$10! ; = TX pin
+Deep_RST_IN=\$200! ; TERMINAL TX pin as FORTH Deep_RST
+
+RTS=4! ; P3.2
+CTS=1! ; P3.0
+HANDSHAKIN=\$220!
+HANDSHAKOUT=\$222!
+
+SD_CD=8! ; P2.3 as SD_CD
+SD_CS=4! ; P2.2 as SD_CS
+SD_CDIN=\$201!
+SD_CSOUT=\$203!
+SD_CSDIR=\$205!
+
+SD_SEL1=\$20C! ; to configure UCB0
+SD_REN=\$206! ; to configure pullup resistors
+SD_BUS=\$0E! ; pins P1.1 as UCB0CLK, P1.2 as UCB0SIMO & P1.3 as UCB0SOMI
+
+
+! ============================================
+! APPLICATION I/O :
+! ============================================
+LED1_OUT=\$222!
+LED1=\$02! P3.1
+
+SW1_IN=\$201!
+SW1=\$02! P2.1
+
+SW2_IN=\$201!
+SW2=\$01! P2.0
+
+
+IR_IN=\$200!
+IR_OUT=\$202!
+IR_DIR=\$204!
+IR_REN=\$208!
+IR_IES=\$218!
+IR_IE=\$21A!
+IR_IFG=\$21C!
+IR_Vec=\$FFDC! P1 int
+RC5_=RC5_!
+RC5=\$01! P1.0
+
+I2CSM_IN=\$201!
+I2CSM_OUT=\$203!
+I2CSM_DIR=\$205!
+I2CSM_REN=\$207!
+SMSDA=\$01! P2.0
+SMSCL=\$04! P2.2
+SM_BUS=\$05!
+
+I2CSMM_IN=\$201!
+I2CSMM_OUT=\$203!
+I2CSMM_DIR=\$205!
+I2CSMM_REN=\$207!
+SMMSDA=\$01! P2.0
+SMMSCL=\$04! P2.2
+SMM_BUS=\$05!
+
+I2CMM_IN=\$200!
+I2CMM_OUT=\$202!
+I2CMM_DIR=\$204!
+I2CMM_REN=\$206!
+I2CMM_SEL1=\$20C!
+I2CMM_Vec=\$FFE0!
+MMSDA=\$04! P1.2
+MMSCL=\$08! P1.3
+MM_BUS=\$0C!
+
+I2CM_IN=\$200!
+I2CM_OUT=\$202!
+I2CM_DIR=\$204!
+I2CM_REN=\$206!
+I2CM_SEL1=\$20C!
+I2CM_Vec=\$FFE0!
+MSDA=\$04! P1.2
+MSCL=\$08! P1.3
+M_BUS=\$0C!
+
+I2CS_IN=\$200!
+I2CS_OUT=\$202!
+I2CS_DIR=\$204!
+I2CS_REN=\$206!
+I2CS_SEL1=\$20C!
+I2CS_Vec=\$FFE0!
+SSDA=\$40! P1.2
+SSCL=\$80! P1.3
+S_BUS=\$C0!
+
--- /dev/null
+-1 SAVE_SYSRSTIV ! COLD
+\ download to unlock JTAG and BSL, for example
--- /dev/null
+! -*- coding: utf-8 -*-
+! MSP_EXP430FR4133.pat
+!
+! Fast Forth For Texas Instrument MSP_EXP430FR4133
+!
+! Copyright (C) <2016> <J.M. THOORENS>
+!
+! This program is free software: you can redistribute it and/or modify
+! it under the terms of the GNU General Public License as published by
+! the Free Software Foundation, either version 3 of the License, or
+! (at your option) any later version.
+!
+! This program is distributed in the hope that it will be useful,
+! but WITHOUT ANY WARRANTY; without even the implied warranty of
+! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+! GNU General Public License for more details.
+!
+! You should have received a copy of the GNU General Public License
+! along with this program. If not, see <http://www.gnu.org/licenses/>.
+!
+!
+!
+! ======================================================================
+! MSP430FR4133 Config
+! ======================================================================
+
+@define{@read{/config/gema/MSP430FR4133.pat}}
+@define{@read{/config/gema/MSP430FR2x4x_FastForth.pat}}
+@define{@read{/config/gema/FastForthREGtoTI.pat}}
+@define{@read{/config/gema/RemoveComments.pat}}
+
+! ======================================================================
+! MSP_EXP430FR4133 board
+! ======================================================================
+!
+! J101 eZ-FET <-> target
+! -----------------------
+! P1 <-> P2 - NC
+! P3 <-> P4 - TEST - TEST
+! P5 <-> P6 - RST - RST
+! P7 <-> P8 - TX1 - P1.0 UCA0 TXD ---> RX UARTtoUSB module
+! P9 <->P10 - RX1 - P1.1 UCA0 RXD <--- TX UARTtoUSB module
+! P11<->P12 - CTS - P2.4
+! P13<->P14 - RTS - P2.3
+! P15<->P16 - VCC - 3V3
+! P17<->P18 - 5V
+! P19<->P20 - GND - VSS
+!
+! Launchpad Header Left J1
+! ------------------------
+! P1 - 3V3
+! P2 - P8.1 ACLK/A9
+! P3 - P1.1 UCA0 RXD
+! P4 - P1.0 UCA0 TXD
+! P5 - P2.7
+! P6 - P8.0 SMCLK/A8
+! P7 - P5.1 UCB0 CLK
+! P8 - P2.5
+! P9 - P8.2 TA1CLK
+! P10- P8.3 TA1.2
+!
+! Launchpad Header Right J2
+! -------------------------
+! P1 - GND
+! P2 - P1.7 TA0.1/TDO/A7
+! P3 - P1.6 TA0.2/TDI/TCLK/A6
+! P4 - P5.0 UCB0STE
+! P5 - RST
+! P6 - P5.2 UCB0SIMO/UCB0SDA
+! P7 - P5.3 UCB0SOMI/UCB0SCL
+! P8 - P1.3 UCA0STE/A3
+! P9 - P1.4 MCLK/TCK/A4
+! P10- P1.5 TA0CLK/TMS/A5
+!
+! switch-keys:
+! S1 - P1.2
+! S2 - P2.6
+! S3 - RST
+!
+! LEDS:
+! LED1 - P1.0/TXD
+! LED2 - P4.0
+!
+! XTAL LF 32768 Hz
+! Y4 - P4.1 XIN
+! Y4 - P4.2 XOUT
+!
+! LCD
+! L0 - P7.0
+! L1 - P7.1
+! L2 - P7.2
+! L3 - P7.3
+! L4 - P7.4
+! L5 - P7.5
+! L6 - P7.6
+! L7 - P7.7
+! L8 - P3.0
+! L9 - P3.1
+! L10 - P3.2
+! L11 - P3.3
+! L12 - P3.4
+! L13 - P3.5
+! L14 - P3.6
+! L15 - P3.7
+! L16 - P6.0
+! L17 - P6.1
+! L18 - P6.2
+! L19 - P6.3
+! L20 - P6.4
+! L21 - P6.5
+! L22 - P6.6
+! L23 - P6.7
+! L24 - P2.0
+! L25 - P2.1
+! L26 - P2.2
+! L36 - P5.4
+! L37 - P5.5
+! L38 - P5.6
+! L39 - P5.7
+!
+!
+!
+!
+!
+!
+! ===================================================================================
+! in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
+! then wire VCC and GND of bridge onto J13 connector
+! ===================================================================================
+!
+! ---------------------------------------------------
+! MSP - MSP-EXP430FR4133 LAUNCHPAD <--> OUTPUT WORLD
+! ---------------------------------------------------
+!
+! +-4k7-< DeepRST <-- GND
+! |
+! P1.0 - UCA0 TXD J101.8 --+-> RX UARTtoUSB bridge
+! P1.1 - UCA0 RXD J101.10 <---- TX UARTtoUSB bridge
+! P2.3 - RTS J101.14 ----> CTS UARTtoUSB bridge (if TERMINALCTSRTS option)
+! VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
+! GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge)
+!
+! P1.0 - STRAP JP1 MUST BE REMOVED (LED red)
+! =========================
+!
+! P4.0 - LED green
+!
+! P1.2 - Switch SW1 <--- LCD contrast + (finger :-)
+! P2.6 - Switch SW2 <--- LCD contrast - (finger ;-)
+!
+!
+! GND - J2.1 <-------+---0V0----------> 1 LCD_Vss
+! VCC - J1.1 >------ | --3V6-----+----> 2 LCD_Vdd
+! | |
+! ___ 470n ---
+! ^ ---
+! / \ 1n4148 |
+! --- |
+! 100n | 2k2 |
+! P1.6 - TA0.2 J2.18 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+! P1.3 - J2.13 -------------------------> 4 LCD_RS
+! P1.4 - J2.12 -------------------------> 5 LCD_R/W
+! P1.5 - J2.11 -------------------------> 6 LCD_EN
+! P5.0 - J2.17 <------------------------> 11 LCD_DB4
+! P5.1 - J1.7 <------------------------> 12 LCD_DB5
+! P5.2 - J2.15 <------------------------> 13 LCD_DB5
+! P5.3 - J2.14 <------------------------> 14 LCD_DB7
+!
+!
+! P1.7 - J2.19 <---- OUT IR_Receiver (1 TSOP32236)
+!
+! P4.1 - LFXIN 32768Hz quartz
+! P4.2 - LFXOUT 32768Hz quartz
+!
+! VCC - J1.1 ----> VCC SD_CardAdapter
+! GND - J2.1 <---> GND SD_CardAdapter
+! P5.1 - UCB0 CLK J1.7 ----> CLK SD_CardAdapter (SCK)
+! P8.1 - J1.2 ----> CS SD_CardAdapter (Card Select)
+! P5.2 - UCB0 TXD/SIMO J2.15 ----> SDI SD_CardAdapter (MOSI)
+! P5.3 - UCB0 RXD/SOMI J2.14 <---- SDO SD_CardAdapter (MISO)
+! P8.0 - J1.6 <---- CD SD_CardAdapter (Card Detect)
+!
+!
+!
+! P8.2 - Soft I2C_Master J1.9 ----> SDA software I2C Master
+! P8.3 - Soft I2C_Master J1.10 <---> SCL software I2C Master
+
+
+! ============================================
+! FORTH I/O :
+! ============================================
+TERM_TX=1! ; P1.0 = TX
+TERM_RX=2! ; P1.1 = RX
+TERM_TXRX=3!
+
+TERM_REN=\$206!
+TERM_SEL=\$20C!
+TERM_IE=\$21A!
+TERM_IFG=\$21C!
+Deep_RST=1! ; = TX pin
+Deep_RST_IN=\$200! ; TERMINAL TX pin as FORTH Deep_RST
+
+RTS=8! ; P2.3
+CTS=\$10! ; P2.4
+HANDSHAKIN=\$201!
+HANDSHAKOUT=\$203!
+
+
+SD_CS=2! ; P8.1 as SD_CS
+SD_CD=1! ; P8.0 as SD_CD
+SD_CDIN=\$261!
+SD_CSOUT=\$263!
+SD_CSDIR=\$265!
+
+SD_SEL1=\$24C! ; to configure UCB0
+SD_REN=\$246! ; to configure pullup resistors
+SD_BUS=\$0E! ; pins P5.1 as UCB0CLK, P5.2 as UCB0SIMO & P5.3 as UCB0SOMI
+
+
+! ============================================
+! APPLICATION I/O :
+! ============================================
+!LEDs
+!----
+invert LED numbers because LED1=TXD !
+LED2_OUT=\$202!
+LED2=\$01! P1.0 red LED
+LED1_OUT=\$223!
+LED1=\$01! P4.0 green LED
+
+!switches
+!--------
+SW1_IN=\$200!
+SW1=\$04! P1.2 SW1
+SW2_IN=\$201!
+SW2=\$40! P2.6 SW2
+
+!LCD Vo driver
+!-------------
+LCDVo_DIR=\$204! P1.6 = LCDVo
+LCDVo_SEL=\$20A! SEL0
+LCDVo=\$40!
+! FR4133 hasn't TB0: let TA0 addresses for TA0.2=LCDVo on P1.6
+TB0CTL=\$300!
+TB0CCTL2=\$306!
+TB0CCR0=\$312!
+TB0CCR2=\$316!
+TB0EX0=\$320!
+
+!LCD command bus
+!---------------
+LCD_CMD_IN=\$200!
+LCD_CMD_OUT=\$202!
+LCD_CMD_DIR=\$204!
+LCD_CMD_REN=\$206!
+LCD_RS=\$08! P1.3 LCD_RS
+LCD_RW=\$10! P1.4 LCD_RW
+LCD_EN=\$20! P1.5 LCD_EN
+LCD_CMD=\$38!
+
+!LCD data bus
+!------------
+LCD_DB_IN=\$240!
+LCD_DB_OUT=\$242!
+LCD_DB_DIR=\$244!
+LCD_DB_REN=\$246!
+LCD_DB=\$0F! P5.0-3 LCD_DATA_BUS
+
+!IR_RC5 input
+!------------
+IR_IN=\$200!
+IR_OUT=\$202!
+IR_DIR=\$204!
+IR_REN=\$206!
+IR_IES=\$218!
+IR_IE=\$21A!
+IR_IFG=\$21C!
+IR_Vec=\$FFE6! P1 int
+RC5=\$80! P1.7 IR_RC5
+! replace TA0 addrs by TA1 addrs because TA0 used for LCDVo
+TA0CTL=\$340!
+TA0CCTL2=\$346!
+TA0R=\$350!
+TA0CCR0=\$352!
+TA0CCR2=\$356!
+TA0EX0=\$360!
+
+
+I2CSM_IN=\$261!
+I2CSM_OUT=\$263!
+I2CSM_DIR=\$265!
+I2CSM_REN=\$267!
+SMSDA=\$04! P8.2 SDA software MASTER
+SMSCL=\$08! P8.3 SCL software MASTER
+SM_BUS=\$0C!
+
+I2CSMM_IN=\$261!
+I2CSMM_OUT=\$263!
+I2CSMM_DIR=\$265!
+I2CSMM_REN=\$267!
+SMMSDA=\$04! P8.2 SDA software MULTI_MASTER
+SMMSCL=\$08! P8.3 SCL software MULTI_MASTER
+SMM_BUS=\$0C!
+
+I2CMM_IN=\$240!
+I2CMM_OUT=\$242!
+I2CMM_DIR=\$244!
+I2CMM_REN=\$246!
+I2CMM_SEL=\$24A! SEL0
+I2CMM_Vec=\$FFEA!
+MMSDA=\$04! P5.2 SDA hadware MULTI_MASTER
+MMSCL=\$08! P5.3 SCL hadware MULTI_MASTER
+MM_BUS=\$0C!
+
+I2CM_IN=\$240!
+I2CM_OUT=\$242!
+I2CM_DIR=\$244!
+I2CM_REN=\$246!
+I2CM_SEL=\$24A! SEL0
+I2CM_Vec=\$FFEA!
+MSDA=\$04! P5.2 SDA hadware MASTER
+MSCL=\$08! P5.3 SCL hadware MASTER
+M_BUS=\$0C!
+
+I2CS_IN=\$240!
+I2CS_OUT=\$242!
+I2CS_DIR=\$244!
+I2CS_REN=\$246!
+I2CS_SEL=\$24A! SEL0
+I2CS_Vec=\$FFEA!
+SSDA=\$04! P5.2 SDA hadware SLAVE
+SSCL=\$08! P5.3 SCL hadware SLAVE
+S_BUS=\$0C!
+
--- /dev/null
+! -*- coding: utf-8 -*-
+! MSP_EXP430FR5739.pat
+!
+! Fast Forth For Texas Instrument MSP_EXP430FR5739
+!
+! Copyright (C) <2016> <J.M. THOORENS>
+!
+! This program is free software: you can redistribute it and/or modify
+! it under the terms of the GNU General Public License as published by
+! the Free Software Foundation, either version 3 of the License, or
+! (at your option) any later version.
+!
+! This program is distributed in the hope that it will be useful,
+! but WITHOUT ANY WARRANTY; without even the implied warranty of
+! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+! GNU General Public License for more details.
+!
+! You should have received a copy of the GNU General Public License
+! along with this program. If not, see <http://www.gnu.org/licenses/>.
+!
+!
+!
+! ======================================================================
+! MSP430FR5739 Config
+! ======================================================================
+
+@define{@read{/config/gema/MSP430FR5739.pat}}
+@define{@read{/config/gema/MSP430FR57xx_FastForth.pat}}
+@define{@read{/config/gema/FastForthREGtoTI.pat}}
+@define{@read{/config/gema/RemoveComments.pat}}
+
+! ======================================================================
+! MSP_EXP430FR5739 board
+! ======================================================================
+
+! blue LEDs (Px.y ---> resistor ---> LED ---> GND)
+! PJ.0 - LED1
+! PJ.1 - LED2
+! PJ.2 - LED3
+! PJ.3 - LED4
+! P3.4 - LED5
+! P3.5 - LED6
+! P3.6 - LED7
+! P3.7 - LED8
+!
+! I/O pins on SV1:
+! P1.0 - SV1.1
+! P1.1 - SV1.2
+! P1.2 - SV1.3
+! P3.0 - SV1.4
+! P3.1 - SV1.5
+! P3.2 - SV1.6
+! P3.3 - SV1.7
+! P1.3 - SV1.8
+! P1.4 - SV1.9
+! P1.5 - SV1.10
+! P4.0 - SV1.11
+! GND - SV1.12
+!
+! I/O pins on SV2:
+! P1.7 - SV2.1
+! P1.6 - SV2.2
+! P3.7 - SV2.3
+! P3.6 - SV2.4
+! P3.5 - SV2.5
+! P3.4 - SV2.6
+! P2.2 - SV2.7
+! P2.1 - SV2.8
+! P2.6 - SV2.9
+! P2.5 - SV2.10
+! P2.0 - SV2.11
+! VCC - SV2.12
+!
+! I/O pins on RF:
+! GND - RF.1
+! VCC - RF.2
+! P2.0 - RF.3
+! P1.0 - RF.4
+! P2.6 - RF.5
+! P1.1 - RF.6
+! P2.5 - RF.7
+! P1.2 - RF.8
+! P2.7 - RF.9
+! P2.3 - RF.10
+! P4.0 - RF.11
+! GND - RF.12
+! P4.1 - RF.13
+! P2.4 - RF.14
+! P1.7 - RF.15
+! P2.2 - RF.16
+! P1.3 - RF.17
+! P1.6 - RF.18
+!
+! Accelerometer:
+! P2.7 - VS
+! P3.0 - XOUT
+! P3.1 - YOUT
+! P3.2 - ZOUT
+!
+! LDR and NTC:
+! P2.7 - VS
+! P3.3 - LDR
+! P1.4 - NTC
+!
+! RST - reset
+!
+! ======================================================================
+! MSP-EXP430FR5739 LAUNCHPAD <--> OUTPUT WORLD
+! ======================================================================
+!
+! P4.0 - Switch S1 <--- LCD contrast + (finger :-)
+! P4.1 - Switch S2 <--- LCD contrast - (finger :-)
+!
+! GND <-------+---0V0----------> 1 LCD_Vss
+! VCC >------ | --3V6-----+----> 2 LCD_Vdd
+! | |
+! |___ 470n ---
+! ^ | ---
+! / \ BAT54 |
+! --- |
+! 100n | 2k2 |
+! P1.5 - UCB0 CLK TB0.2 SV1.10 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+! P3.4 - SV2.6 -------------------------> 4 LCD_RS
+! P3.5 - SV2.5 -------------------------> 5 LCD_R/W
+! P3.6 - SV2.4 -------------------------> 6 LCD_EN
+! P1.0 - SV1.1 <------------------------> 11 LCD_DB4
+! P1.1 - SV1.2 <------------------------> 12 LCD_DB5
+! P1.2 - SV1.3 <------------------------> 13 LCD_DB5
+! P1.3 - SV1.8 <------------------------> 14 LCD_DB7
+!
+! PJ.4 - LFXI 32768Hz quartz
+! PJ.5 - LFXO 32768Hz quartz
+! PJ.6 - HFXI
+! PJ.7 - HFXO
+! +--4k7-< DeepRST <-- GND
+! |
+! P2.0 - UCA0 TXD SV2.11 --+-> RX UARTtoUSB bridge
+! P2.1 - UCA0 RXD SV2.8 <---- TX UARTtoUSB bridge
+! VCC - <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
+! GND - <---> GND (optional supply from UARTtoUSB bridge)
+!
+! VCC - RF.2
+! VSS - RF.1
+! P2.2 - RF.16 <---- CD SD_CardAdapter (Card Detect)
+! P2.3 - RF.10 ----> CS SD_CardAdapter (Card Select)
+! P2.4 - UCA1 CLK RF.14 ----> CLK SD_CardAdapter (SCK)
+! P2.5 - UCA1 TXD/SIMO RF.7 ----> SDI SD_CardAdapter (MOSI)
+! P2.6 - UCA1 RXD/SOMI RF.5 <---- SDO SD_CardAdapter (MISO)
+!
+! P2.7 - RF.9 <---- OUT IR_Receiver (1 TSOP32236)
+!
+! P1.7 - UCB0 SCL/SOMI SV2.1 <---> SCL I2C MASTER/SLAVE
+! P1.6 - UCB0 SDA/SIMO SV2.2 <---> SDA I2C MASTER/SLAVE
+
+! ============================================
+! FORTH I/O :
+! ============================================
+TERM_TX=1! ; P2.0 = TX
+TERM_RX=2! ; P2.1 = RX
+TERM_TXRX=3!
+
+TERM_REN=\$207!
+TERM_SEL=\$20D!
+TERM_IE=\$21B!
+TERM_IFG=\$21D!
+Deep_RST=1! ; = TX pin
+Deep_RST_IN=\$201! ; TERMINAL TX pin as FORTH Deep_RST
+
+RTS=4!
+CTS=8!
+HANDSHAKIN=\$201!
+HANDSHAKOUT=\$203!
+
+SD_CD=4! ; P2.2 as SD_CD
+SD_CS=8! ; P2.3 as SD_CS
+SD_CDIN=\$201!
+SD_CSOUT=\$203!
+SD_CSDIR=\$205!
+
+SD_SEL1=\$20D! ; to configure UCB0
+SD_REN=\$207! ; to configure pullup resistors
+SD_BUS=\$70! ; pins P2.4 as UCB0CLK, P2.5 as UCB0SIMO & P2.6 as UCB0SOMI
+
+
+! ============================================
+! APPLICATION I/O :
+! ============================================
+LED1_OUT=\$322!
+LED1=\$01! PJ.0
+
+LED2_OUT=\$322!
+LED2=\$02! PJ.1
+
+SW1_IN=\$221!
+SW1=\$01! P4.0
+
+SW2_IN=\$221!
+SW2=\$02! P4.1
+
+LCDVo_DIR=\$204!
+LCDVo_SEL=\$20A! SEL0
+LCDVo=\$20! P1.5
+
+LCD_CMD_IN=\$220!
+LCD_CMD_OUT=\$222!
+LCD_CMD_DIR=\$224!
+LCD_CMD_REN=\$226!
+LCD_RS=\$10! P3.4
+LCD_RW=\$20! P3.5
+LCD_EN=\$40! P3.6
+LCD_CMD=\$70!
+
+LCD_DB_IN=\$200!
+LCD_DB_OUT=\$202!
+LCD_DB_DIR=\$204!
+LCD_DB_REN=\$206!
+LCD_DB=\$0F! P1.0-3
+
+
+IR_IN=\$201!
+IR_OUT=\$203!
+IR_DIR=\$205!
+IR_REN=\$207!
+IR_IES=\$219!
+IR_IE=\$21B!
+IR_IFG=\$21D!
+RC5_=RC5_!
+RC5=\$40! P2.6
+IR_Vec=\$FFD8! P2 int
+
+I2CSM_IN=\$200!
+I2CSM_OUT=\$202!
+I2CSM_DIR=\$204!
+I2CSM_REN=\$206!
+SMSDA=\$40! P1.6
+SMSCL=\$80! P1.7
+SM_BUS=\$C0!
+
+I2CSMM_IN=\$200!
+I2CSMM_OUT=\$202!
+I2CSMM_DIR=\$204!
+I2CSMM_REN=\$206!
+SMMSDA=\$40! P1.6
+SMMSCL=\$80! P1.7
+SMM_BUS=\$C0!
+
+I2CMM_IN=\$200!
+I2CMM_OUT=\$202!
+I2CMM_DIR=\$204!
+I2CMM_REN=\$206!
+I2CMM_SEL=\$20C! SEL1
+I2CMM_Vec=\$FFEE!
+MMSDA=\$40! P1.6
+MMSCL=\$80! P1.7
+MM_BUS=\$C0!
+
+I2CM_IN=\$200!
+I2CM_OUT=\$202!
+I2CM_DIR=\$204!
+I2CM_REN=\$206!
+I2CM_SEL=\$20C!
+I2CM_Vec=\$FFEE!
+MSDA=\$40! P1.6
+MSCL=\$80! P1.7
+M_BUS=\$C0!
+
+I2CS_IN=\$200!
+I2CS_OUT=\$202!
+I2CS_DIR=\$204!
+I2CS_REN=\$206!
+I2CS_SEL=\$20C!
+I2CS_Vec=\$FFEE!
+SSDA=\$40! P1.6
+SSCL=\$80! P1.7
+S_BUS=\$C0!
+
--- /dev/null
+! -*- coding: utf-8 -*-
+! MSP_EXP430FR5969.pat
+!
+! Fast Forth For Texas Instrument MSP_EXP430FR5969
+!
+! Copyright (C) <2016> <J.M. THOORENS>
+!
+! This program is free software: you can redistribute it and/or modify
+! it under the terms of the GNU General Public License as published by
+! the Free Software Foundation, either version 3 of the License, or
+! (at your option) any later version.
+!
+! This program is distributed in the hope that it will be useful,
+! but WITHOUT ANY WARRANTY; without even the implied warranty of
+! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+! GNU General Public License for more details.
+!
+! You should have received a copy of the GNU General Public License
+! along with this program. If not, see <http://www.gnu.org/licenses/>.
+!
+!
+!
+! ======================================================================
+! MSP430FR5969 Config
+! ======================================================================
+
+@define{@read{/config/gema/MSP430FR5969.pat}}
+@define{@read{/config/gema/MSP430FR5x6x_FastForth.pat}}
+@define{@read{/config/gema/FastForthREGtoTI.pat}}
+@define{@read{/config/gema/RemoveComments.pat}}
+
+! ======================================================================
+! MSP_EXP430FR5969 board
+! ======================================================================
+
+! J3: JTAG
+! --------
+! P1 - TDO - PJ.0
+! P2 - V_debug
+! P3 - TDI - PJ.1
+! P4 - V_ext
+! P5 - TMS - PJ.2
+! P6 - NC
+! P7 - TCK - PJ.3
+! P8 - TEST - TEST
+! P9 - GND
+! P10- CTS - P4.0
+! P11- RST - RESET
+! P12- TX0 - P2.0
+! P13- RTS - P4.1
+! P14- RX0 - P2.1
+
+! Launchpad Header Left J4
+! ------------------------
+! P1 - VCC
+! P2 - P4.2
+! P3 - P2.6 UCA1 RX/SOMI
+! P4 - P2.5 UCA1 TX/SIMO
+! P5 - P4.3
+! P6 - P2.4 UCA1 CLK
+! P7 - P2.2 TB0.2 UCB0CLK
+! P8 - P3.4
+! P9 - P3.5
+! P10- P3.6
+
+! Launchpad Header Right J5
+! -------------------------
+! P11- P1.3
+! P12- P1.4
+! P13- P1.5
+! P14- P1.6 UCB0 SIMO/SDA
+! P15- P1.7 UCB0 SOMI/SCL
+! P16- RST
+! P17- NC
+! P18- P3.0
+! P19- P1.2
+! P20- GND
+
+! J13 eZ-FET <=> target
+! ---------------------------
+! P1 P2 NC NC
+! P3 <-> P4 TEST <-> TEST
+! P5 <-> P6 RST <-> RST
+! P7 P8 TX0 P2.0 (no strap)
+! P9 P10 RX0 P2.1 (no strap)
+! P11 P12 CTS P4.0 (no strap)
+! P13 P14 RTS P4.1 (no strap)
+! P15<->P16 V+ <-> VCC
+! P17 P18 5V (no strap)
+! P19---P20 GND-----VSS
+
+! J21 : external target
+! ---------------------
+! P1 - RX0 - P2.1
+! P2 - VCC
+! P3 - TEST - TEST
+! P4 - RST - RST
+! P5 - GND
+! P6 - TX0 - P2.0
+
+
+! -----------------------------------------------
+! MSP430FR5969 LAUNCHPAD <--> OUTPUT WORLD
+! -----------------------------------------------
+
+! J13 jumpers : device <-> eZ-FET
+! -------------------------------
+! P2 P1 NC NC
+! P4<->P3 TEST <-> TEST
+! P6<->P5 RST <-> RST
+! P8 P7 P2.0 TX0 (no jumper)
+! P10 P9 P2.1 RX0 (no jumper)
+! P12 P11 P4.0 CTS (no jumper)
+! P14 P13 P4.1 RTS (no jumper)
+! P16<->P15 VCC <-> V+
+! P18 P17 5V 5V (no jumper)
+! P20---P19 VSS-----GND
+
+! P4.6 - J6 - LED1 red
+! P1.0 - LED2 green
+!
+! P4.5 - Switch S1 <--- LCD contrast + (finger :-)
+! P1.1 - Switch S2 <--- LCD contrast - (finger ;-)
+!
+! GND - J1.2 <-------+---0V0----------> 1 LCD_Vss
+! VCC - J1.3 >------ | --3V6-----+----> 2 LCD_Vdd
+! | |
+! ___ 470n ---
+! ^ ---
+! / \ 1n4148 |
+! --- |
+! 100n | 2k2 |
+! P2.2 - UCB0 CLK TB0.2 J4.7 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+! P3.4 - J4.8 -------------------------> 4 LCD_RS
+! P3.5 - J4.9 -------------------------> 5 LCD_R/W
+! P3.6 - J4.10 -------------------------> 6 LCD_EN
+! PJ.0 - J3.1 <------------------------> 11 LCD_DB4
+! PJ.1 - J3.3 <------------------------> 12 LCD_DB5
+! PJ.2 - J3.5 <------------------------> 13 LCD_DB5
+! PJ.3 - J3.7 <------------------------> 14 LCD_DB7
+!
+! +--4k7-< DeepRST <-- GND
+! |
+! P2.0 - UCA0 TXD J13.8 <-+-> RX UARTtoUSB bridge
+! P2.1 - UCA0 RXD J13.10 <---- TX UARTtoUSB bridge
+! P4.1 - RTS J13.14 ----> CTS UARTtoUSB bridge (optional hardware control flow)
+! VCC - J13.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
+! GND - J13.20 <---> GND (optional supply from UARTtoUSB bridge)
+!
+! VCC - J11.1 ----> VCC SD_CardAdapter
+! GND - J12.3 <---> GND SD_CardAdapter
+! P2.4 - UCA1 CLK J4.6 ----> CLK SD_CardAdapter (SCK)
+! P4.3 - J4.5 ----> CS SD_CardAdapter (Card Select)
+! P2.5 - UCA1 TXD/SIMO J4.4 ----> SDI SD_CardAdapter (MOSI)
+! P2.6 - UCA1 RXD/SOMI J4.3 <---- SDO SD_CardAdapter (MISO)
+! P4.2 - J4.2 <---- CD SD_CardAdapter (Card Detect)
+!
+! P4.0 - J3.10 <---- OUT IR_Receiver (1 TSOP32236) ----┌───┐
+! VCC - J3.2 ----> VCC IR_Receiver (2 TSOP32236) ----│ ○ │
+! GND - J3.9 <---> GND IR_Receiver (3 TSOP32236) ----└───┘
+!
+! P1.2 - J5.19 <---> SDA I2C SOFTWARE MASTER
+! P1.3 - J5.11 <---> SCL I2C SOFTWARE MASTER
+! P1.4 - TB0.1 J5.12 <---> free
+! P1.5 - UCA0 CLK TB0.2 J5.13 <---> free
+! P1.7 - UCB0 SCL/SOMI J5.14 ----> SCL I2C MASTER/SLAVE
+! P1.6 - UCB0 SDA/SIMO J5.15 <---> SDA I2C MASTER/SLAVE
+! P3.0 - J5.7 <---- free
+!
+! PJ.4 - LFXI 32768Hz quartz
+! PJ.5 - LFXO 32768Hz quartz
+! PJ.6 - HFXI
+! PJ.7 - HFXO
+!
+! P2.3 - NC
+! P2.7 - NC
+! P3.1 - NC
+! P3.2 - NC
+! P3.3 - NC
+! P3.7 - NC
+! P4.4 - NC
+! P4.7 - NC
+
+! -------------+------+------+------+------++---+---+---+---+---------+
+! SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current | @ 8MHz
+! -------------+------+------+------+------++---+---+---+---+---------+
+! LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 160uA | default mode
+! LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | 115uA |
+! LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 0.9uA | 32768Hz XTAL is running
+! LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 0.6uA | 32768Hz XTAL is running
+! LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 0.5uA |
+! -------------+------+------+------+------++---+---+---+---+---------+
+
+! ============================================
+! FORTH I/O :
+! ============================================
+TERM_TX=1! ; P2.0 = TX
+TERM_RX=2! ; P2.1 = RX
+TERM_TXRX=3!
+
+TERM_REN=\$207!
+TERM_SEL=\$20D!
+TERM_IE=\$21B!
+TERM_IFG=\$21D!
+Deep_RST=1! ; = TX pin
+Deep_RST_IN=\$201! ; TERMINAL TX pin as FORTH Deep_RST
+
+RTS=2! ; P4.1
+CTS=1! ; P4.0
+HANDSHAKIN=\$221!
+HANDSHAKOUT=\$223!
+
+SD_CD=4! ; P4.2 as SD_CD
+SD_CS=8! ; P4.3 as SD_CS
+SD_CDIN=\$221!
+SD_CSOUT=\$223!
+SD_CSDIR=\$225!
+
+SD_SEL1=\$20D! ; to configure UCB0
+SD_REN=\$207! ; to configure pullup resistors
+SD_BUS=\$70! ; pins P2.4 as UCB0CLK, P2.5 as UCB0SIMO & P2.6 as UCB0SOMI
+
+
+! ============================================
+! APPLICATION I/O :
+! ============================================
+! init state : output low
+LED1_OUT=\$223
+LED1=\$40! P4.6
+
+! init state : output low
+LED2_OUT=\$202
+LED2=\$01! P1.0
+
+! init state : input with pullup resistor
+SW1_IN=\$221
+SW1=\$20! P4.5
+
+! init state : input with pullup resistor
+SW2_IN=\$200
+SW2=\$02! P1.1
+
+LCDVo_DIR=\$205! P2
+LCDVo_SEL=\$20B! SEL0
+LCDVo=\$04
+
+LCD_CMD_IN=\$220! P3
+LCD_CMD_OUT=\$222
+LCD_CMD_DIR=\$224
+LCD_CMD_REN=\$226
+LCD_RS=\$10
+LCD_RW=\$20
+LCD_EN=\$40
+LCD_CMD=\$70
+
+LCD_DB_IN=\$320! PJ
+LCD_DB_OUT=\$322
+LCD_DB_DIR=\$324
+LCD_DB_REN=\$326
+LCD_DB=\$0F
+
+
+IR_IN=\$221
+IR_OUT=\$223
+IR_DIR=\$225
+IR_REN=\$227
+IR_IES=\$239
+IR_IE=\$23B
+IR_IFG=\$23D
+IR_Vec=\$FFD0! P4 int
+RC5=\$01! P4.0
+
+I2CSM_IN=\$200
+I2CSM_OUT=\$202
+I2CSM_DIR=\$204
+I2CSM_REN=\$206
+SMSDA=\$04! P1.2
+SMSCL=\$08! P1.3
+SM_BUS=\$0C
+
+I2CSMM_IN=\$200
+I2CSMM_OUT=\$202
+I2CSMM_DIR=\$204
+I2CSMM_REN=\$206
+SMMSDA=\$04! P1.2
+SMMSCL=\$08! P1.3
+SMM_BUS=\$0C
+
+I2CMM_IN=\$200
+I2CMM_OUT=\$202
+I2CMM_DIR=\$204
+I2CMM_REN=\$206
+I2CMM_SEL=\$20C! SEL1
+I2CMM_Vec=\$FFEE! eUSCIB0_INT
+MMSDA=\$40! P1.6
+MMSCL=\$80! P1.7
+MM_BUS=\$C0
+
+I2CM_IN=\$200
+I2CM_OUT=\$202
+I2CM_DIR=\$204
+I2CM_REN=\$206
+I2CM_SEL=\$20C
+I2CM_Vec=\$FFEE! eUSCIB0_INT
+MSDA=\$40! P1.6
+MSCL=\$80! P1.7
+M_BUS=\$C0
+
+I2CS_IN=\$200
+I2CS_OUT=\$202
+I2CS_DIR=\$204
+I2CS_REN=\$206
+I2CS_SEL=\$20C
+I2CS_Vec=\$FFEE! eUSCIB0_INT
+SSDA=\$40! P1.6
+SSCL=\$80! P1.7
+S_BUS=\$C0
+
--- /dev/null
+! -*- coding: utf-8 -*-
+! MSP_EXP430FR5994.pat
+!
+! Fast Forth For Texas Instrument MSP_EXP430FR5994
+!
+! Copyright (C) <2016> <J.M. THOORENS>
+!
+! This program is free software: you can redistribute it and/or modify
+! it under the terms of the GNU General Public License as published by
+! the Free Software Foundation, either version 3 of the License, or
+! (at your option) any later version.
+!
+! This program is distributed in the hope that it will be useful,
+! but WITHOUT ANY WARRANTY; without even the implied warranty of
+! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+! GNU General Public License for more details.
+!
+! You should have received a copy of the GNU General Public License
+! along with this program. If not, see <http://www.gnu.org/licenses/>.
+!
+!
+!
+! ======================================================================
+! MSP430FR5994 Config
+! ======================================================================
+
+@define{@read{/config/gema/MSP430FR5994.pat}}
+@define{@read{/config/gema/MSP430FR5x6x_FastForth.pat}}
+@define{@read{/config/gema/FastForthREGtoTI.pat}}
+@define{@read{/config/gema/RemoveComments.pat}}
+
+! ======================================================================
+! MSP_EXP430FR5994 board
+! ======================================================================
+
+! J101 Target <---> eZ-FET
+! GND 14-13 GND
+! +5V 12-11
+! 3V3 10-9
+! P2.1 UCA0_RX 8-7 <---- TX UARTtoUSB bridge
+! +--4k7-< DeepRST <-- GND
+! |
+! P2.0 UCA0_TX 6-5 <-+-> RX UARTtoUSB bridge
+! /RST 4-3
+! TEST 2-1
+
+
+! P5.6 - sw1 <--- LCD contrast + (finger :-)
+! P5.5 - sw2 <--- LCD contrast - (finger ;-)
+! RST - sw3
+
+! P1.0 - led1 red
+! P1.1 - led2 green
+
+! J1 - left ext.
+! 3v3
+! P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236)
+! P6.1/UCA3RXD/UCA3SOMI -------------------------> 4 LCD_RS
+! P6.0/UCA3TXD/UCA3SIMO -------------------------> 5 LCD_R/W
+! P6.2/UCA3CLK -------------------------> 6 LCD_EN0
+! P1.3/TA1.2/UCB0STE/A3/C3
+! P5.2/UCB1CLK/TA4CLK
+! P6.3/UCA3STE
+! P7.1/UCB2SOMI/UCB2SCL ---> SCL I2C MASTER/SLAVE
+! P7.0/UCB2SIMO/UCB2SDA <--> SDA I2C MASTER/SLAVE
+
+! J3 - left int.
+! 5V
+! GND
+! P3.0/A12/C12 <------------------------> 11 LCD_DB4
+! P3.1/A13/C13 <------------------------> 12 LCD_DB5
+! P3.2/A14/C14 <------------------------> 13 LCD_DB5
+! P3.3/A15/C15 <------------------------> 14 LCD_DB7
+! P1.4/TB0.1/UCA0STE/A4/C4
+! P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+! P4.7
+! P8.0
+
+! J4 - right int.
+! P3.7/TB0.6
+! P3.6/TB0.5
+! P3.5/TB0.4/COUT
+! P3.4/TB0.3/SMCLK
+! P7.3/UCB2STE/TA4.1 RTS ----> CTS UARTtoUSB bridge (optional hardware control flow)
+! P2.6/TB0.1/UCA1RXD/UCA1SOMI
+! P2.5/TB0.0/UCA1TXD/UCA1SIMO
+! P4.3/A11
+! P4.2/A10
+! P4.1/A9
+
+! J2 - right ext.
+! GND
+! P5.7/UCA2STE/TA4.1/MCLK
+! P4.4/TB0.5
+! P5.3/UCB1STE
+! /RST
+! P5.0/UCB1SIMO/UCB1SDA
+! P5.1/UCB1SOMI/UCB1SCL
+! P8.3
+! P8.2 <--> SDA I2C SOFTWARE MASTER
+! P8.1 <--> SCL I2C SOFTWARE MASTER
+
+
+! SD_CARD
+! P7.2/UCB2CLK <--- SD_CD
+! P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 ---> SD_MOSI
+! P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 <--- SD_MISO
+! P4.0/A8 ---> SD_CS
+! P2.2/TB0.2/UCB0CLK ---> SD_CLK
+
+
+
+! XTAL LF 32768 Hz
+! PJ.4/LFXIN
+! PJ.5/LFXOUT
+
+! XTAL HF
+! PJ.6/HFXIN
+! PJ.7/HFXOUT
+
+! -----------------------------------------------
+! LCD config
+! -----------------------------------------------
+
+! <-------+---0V0----------> 1 LCD_Vss
+! >------ | --3V6-----+----> 2 LCD_Vdd
+! | |
+! |___ 470n ---
+! ^ | ---
+! / \ BAT54 |
+! --- |
+! 100n | 2k2 |
+! TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+! -------------------------> 4 LCD_RS
+! -------------------------> 5 LCD_R/W
+! -------------------------> 6 LCD_EN0
+! <------------------------> 11 LCD_DB4
+! <------------------------> 12 LCD_DB5
+! <------------------------> 13 LCD_DB5
+! <------------------------> 14 LCD_DB7
+
+
+
+
+! ============================================
+! FORTH I/O :
+! ============================================
+TERM_TX=1! ; P2.0 = TX
+TERM_RX=2! ; P2.1 = RX
+TERM_TXRX=3!
+
+TERM_REN=\$207!
+TERM_SEL=\$20D!
+TERM_IE=\$21B!
+TERM_IFG=\$21D!
+Deep_RST=1! ; = TX pin
+Deep_RST_IN=\$201! ; TERMINAL TX pin as FORTH Deep_RST
+
+RTS=4! ; P4.2
+CTS=2! ; P4.1
+HANDSHAKIN=\$221!
+HANDSHAKOUT=\$223!
+
+SD_CD=4! ; P7.2 as SD_CD
+SD_CDIN=\$260!
+
+SD_CS=1! ; P4.0 as SD_CS
+SD_CSOUT=\$223!
+SD_CSDIR=\$225!
+
+SD_SEL1=\$20C! ; word access, to configure UCB0
+SD_REN=\$206! ; word access, to configure pullup resistors
+SD_BUS=\$04C0! ; pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0SOMI
+
+
+! ============================================
+! APPLICATION I/O :
+! ============================================
+LED1_OUT=\$202!
+led1=1! P1.0
+
+LED2_OUT=\$202!
+led2=2! P1.1
+
+SW1_IN=\$240!
+SW1=\$40! P5.6
+
+SW2_IN=\$240!
+SW2=\$20! P5.5
+
+LCDVo_DIR=\$204!
+LCDVo_SEL=\$20A! SEL0
+LCDVo=\$20! P1.5
+
+LCD_CMD_IN=\$241!
+LCD_CMD_OUT=\$243!
+LCD_CMD_DIR=\$245!
+LCD_CMD_REN=\$247!
+LCD_RS=2! P6.1
+LCD_RW=1! P6.0
+LCD_EN=4! P6.2
+LCD_CMD=7!
+
+LCD_DB_IN=\$220!
+LCD_DB_OUT=\$222!
+LCD_DB_DIR=\$224!
+LCD_DB_REN=\$226!
+LCD_DB=\$0F! P3.3210
+
+
+IR_IN=\$200!
+IR_OUT=\$202!
+IR_DIR=\$204!
+IR_REN=\$206!
+IR_IES=\$208!
+IR_IE=\$20A!
+IR_IFG=\$20C!
+IR_Vec=\$FFDE! P1 int
+RC5_=RC5_!
+RC5=4! P1.2
+
+
+I2CSM_IN=\$261!
+I2CSM_OUT=\$263!
+I2CSM_DIR=\$265!
+I2CSM_REN=\$267!
+SMSDA=4! P8.2
+SMSCL=2! P8.1
+SM_BUS=6!
+
+I2CSMM_IN=\$261!
+I2CSMM_OUT=\$263!
+I2CSMM_DIR=\$265!
+I2CSMM_REN=\$267!
+SMMSDA=4! P8.2
+SMMSCL=2! P8.1
+SMM_BUS=6!
+
+I2CMM_IN=\$260!
+I2CMM_OUT=\$262!
+I2CMM_DIR=\$264!
+I2CMM_REN=\$266!
+I2CMM_SEL1=\$26C!
+I2CMM_Vec=\$FFBC! UCB2_Vec
+MMSDA=1! P7.0
+MMSCL=2! P7.1
+MM_BUS=3!
+
+I2CM_IN=\$260!
+I2CM_OUT=\$262!
+I2CM_DIR=\$264!
+I2CM_REN=\$266!
+I2CM_SEL1=\$26C!
+I2CM_Vec=\$FFBC!
+MSDA=1! P7.0
+MSCL=2! P7.1
+M_BUS=3!
+
+I2CS_IN=\$260!
+I2CS_OUT=\$262!
+I2CS_DIR=\$264!
+I2CS_REN=\$266!
+I2CS_SEL1=\$26C!
+I2CS_Vec=\$FFBC!
+SSDA=1! P7.0
+SSCL=2! P7.1
+S_BUS=3!
+
--- /dev/null
+! -*- coding: utf-8 -*-
+! MSP_EXP430FR6989.pat
+!
+! Fast Forth For Texas Instrument MSP_EXP430FR6989
+!
+! Copyright (C) <2016> <J.M. THOORENS>
+!
+! This program is free software: you can redistribute it and/or modify
+! it under the terms of the GNU General Public License as published by
+! the Free Software Foundation, either version 3 of the License, or
+! (at your option) any later version.
+!
+! This program is distributed in the hope that it will be useful,
+! but WITHOUT ANY WARRANTY; without even the implied warranty of
+! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+! GNU General Public License for more details.
+!
+! You should have received a copy of the GNU General Public License
+! along with this program. If not, see <http://www.gnu.org/licenses/>.
+!
+!
+!
+! ======================================================================
+! MSP430FR6989 Config
+! ======================================================================
+
+@define{@read{/config/gema/MSP430FR6989.pat}}
+@define{@read{/config/gema/MSP430FR5x6x_FastForth.pat}}
+@define{@read{/config/gema/FastForthREGtoTI.pat}}
+@define{@read{/config/gema/RemoveComments.pat}}
+
+! ======================================================================
+! MSP_EXP430FR6989 board
+! ======================================================================
+
+! ---------------------------------------------------
+! MSP - MSP-EXP430FR6989 LAUNCHPAD <--> OUTPUT WORLD
+! ---------------------------------------------------
+! P1.0 - LED1 red
+! P9.7 - LED2 green
+!
+! P1.1 - Switch S1 <--- LCD contrast + (finger :-)
+! P1.2 - Switch S2 <--- LCD contrast - (finger ;-)
+!
+! note : ESI1.1 = lowest left pin
+! note : ESI1.2 is not connected to 3.3V
+! GND J6.2 <-------+---0V0----------> 1 LCD_Vss
+! VCC J6.1 >------ | --3V3-----+----> 2 LCD_Vdd
+! | |
+! |___ 470n ---
+! ^ | ---
+! / \ BAT54 |
+! --- |
+! 100n | 2k2 |
+! P3.6 - UCA1 CLK TB0.2 J4.37 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+! P9.0/ESICH0 - ESI1.14 <------------------------> 11 LCD_DB4 brown
+! P9.1/ESICH1 - ESI1.13 <------------------------> 12 LCD_DB5 red
+! P9.2/ESICH2 - ESI1.12 <------------------------> 13 LCD_DB5 orange
+! P9.3/ESICH3 - ESI1.11 <------------------------> 14 LCD_DB7 yellow
+! P4.1 -------------------------> 4 LCD_RS yellow
+! P4.2 -------------------------> 5 LCD_R/W green
+! P4.3 -------------------------> 6 LCD_EN blue
+!
+! +--4k7-< DeepRST <-- GND
+! |
+! P3.4 - UCA1 TXD J101.8 <-+-> RX UARTtoUSB bridge
+! P3.5 - UCA1 RXD J101.10 <---- TX UARTtoUSB bridge
+! P3.0 - RTS J101.14 ----> CTS UARTtoUSB bridge (optional hardware control flow)
+! VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
+! GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge)
+!
+! VCC - J1.1 ----> VCC SD_CardAdapter
+! GND - J2.20 <---> GND SD_CardAdapter
+! P2.2 - UCA0 CLK J4.35 ----> CLK SD_CardAdapter (SCK)
+! P2.6 - J4.39 ----> CS SD_CardAdapter (Card Select)
+! P2.0 - UCA0 TXD/SIMO J1.8 ----> SDI SD_CardAdapter (MOSI)
+! P2.1 - UCA0 RXD/SOMI J2.19 <---- SDO SD_CardAdapter (MISO)
+! P2.7 - J4.40 <---- CD SD_CardAdapter (Card Detect)
+!
+! P4.0 - J1.10 <---- OUT IR_Receiver (1 TSOP32236)
+! VCC - J1.1 ----> VCC IR_Receiver (2 TSOP32236)
+! GND - J2.20 <---> GND IR_Receiver (3 TSOP32236)
+!
+! P1.3 - J4.34 <---> SDA software I2C Master
+! P1.5 - J2.18 ----> SCL software I2C Master
+!
+! P1.4 -UCB0 CLK TA1.0 J1.7 <---> free
+!
+! P1.6 -UCB0 SDA/SIMO J2.15 <---> SDA hardware I2C Master or Slave
+! P1.7 -UCB0 SCL/SOMI J2.14 ----> SCL hardware I2C Master or Slave
+!
+! P3.0 -UCB1 CLK J4.33 ----> free (if UARTtoUSB with software control flow)
+! P3.1 -UCB1 SDA/SIMO J4.32 <---> free (if UARTtoUSB with software control flow)
+! P3.2 -UCB1 SCL/SOMI J1.5 ----> free
+! P3.3 - TA1.1 J1.5 <---> free
+!
+! PJ.4 - LFXI 32768Hz quartz
+! PJ.5 - LFXO 32768Hz quartz
+! PJ.6 - HFXI
+! PJ.7 - HFXO
+
+
+! ============================================
+! FORTH I/O :
+! ============================================
+TERM_TX=\$10! ; P3.4 = TX
+TERM_RX=\$20! ; P3.5 = RX
+TERM_TXRX=\$30!
+
+TERM_REN=\$226!
+TERM_SEL=\$22C!
+TERM_IE=\$23A!
+TERM_IFG=\$23C!
+Deep_RST=\$10! ; = TX pin
+Deep_RST_IN=\$220! ; TERMINAL TX pin as FORTH Deep_RST
+
+RTS=2! ; P3.1
+CTS=1! ; P3.0
+HANDSHAKIN=\$220!
+HANDSHAKOUT=\$222!
+
+
+SD_CS=\$40! ; P2.6 as SD_CS
+SD_CD=\$80! ; P2.7 as SD_CD
+SD_CDIN=\$201!
+SD_CSOUT=\$203!
+SD_CSDIR=\$205!
+
+SD_SEL1=\$20C! ; word access, to configure UCB0
+SD_REN=\$206! ; word access, to configure pullup resistors
+SD_BUS=\$07! ; pins P2.2 as UCB0CLK, P2.0 as UCB0SIMO & P2.1 as UCB0SOMI
+
+
+! ============================================
+! APPLICATION I/O :
+! ============================================
+LED1_OUT=\$202!
+LED1=1! P1.0
+
+LED2_OUT=\$282!
+LED2=\$80! P9.7
+
+SW1_IN=\$200!
+SW1=2! P1.1
+
+SW2_IN=\$200!
+SW2=4! P1.2
+
+LCDVo_DIR=\$224!
+LCDVo_SEL=\$22C! SEL1
+LCDVo=\$40! P3.6
+
+LCD_CMD_IN=\$221!
+LCD_CMD_OUT=\$223!
+LCD_CMD_DIR=\$225!
+LCD_CMD_REN=\$227!
+LCD_RS=2! P4.1
+LCD_RW=4! P4.2
+LCD_EN=8! P4.3
+LCD_CMD=\$0E!
+
+LCD_DB_IN=\$280!
+LCD_DB_OUT=\$282!
+LCD_DB_DIR=\$284!
+LCD_DB_REN=\$286!
+LCD_DB=\$0F! P9.3-0
+
+
+IR_IN=\$221!
+IR_OUT=\$223!
+IR_DIR=\$225!
+IR_REN=\$227!
+IR_IES=\$239!
+IR_IE=\$23B!
+IR_IFG=\$23D!
+RC5_=RC5_!
+RC5=1! P4.0
+IR_Vec=\$FFCC! P4 int
+
+I2CSM_IN=\$200!
+I2CSM_OUT=\$202!
+I2CSM_DIR=\$204!
+I2CSM_REN=\$206!
+SMSDA=8! P1.3
+SMSCL=\$20! P1.5
+SM_BUS=\$28!
+
+I2CSMM_IN=\$200!
+I2CSMM_OUT=\$202!
+I2CSMM_DIR=\$204!
+I2CSMM_REN=\$206!
+SMMSDA=8! P1.3
+SMMSCL=\$20! P1.5
+SMM_BUS=\$28!
+
+I2CMM_IN=\$200!
+I2CMM_OUT=\$202!
+I2CMM_DIR=\$204!
+I2CMM_REN=\$206!
+I2CMM_SEL=\$20C! SEL1
+I2CMM_Vec=\$FFEC!
+MMSDA=\$40! P1.6
+MMSCL=\$80! P1.7
+MM_BUS=\$C0!
+
+I2CM_IN=\$200!
+I2CM_OUT=\$202!
+I2CM_DIR=\$204!
+I2CM_REN=\$206!
+I2CM_SEL=\$20C!
+I2CM_Vec=\$FFEC!
+MSDA=\$40! P1.6
+MSCL=\$80! P1.7
+M_BUS=\$C0!
+
+I2CS_IN=\$200!
+I2CS_OUT=\$202!
+I2CS_DIR=\$204!
+I2CS_REN=\$206!
+I2CS_SEL=\$20C!
+I2CS_Vec=\$FFEC!
+SSDA=\$40! P1.6
+SSCL=\$80! P1.7
+S_BUS=\$C0!
+
--- /dev/null
+\ PRIMES.4th
+
+PWR_STATE
+: PRIMES
+\ 2 SWAP 2 . 3 . 5
+ 2 SWAP 2 4 U.R 3 4 U.R 5
+ DO DUP DUP * I
+ < IF 1+ THEN
+ 1 OVER 1+ 3
+ DO J I MOD
+ 0= IF 1- LEAVE THEN
+ 2 +LOOP
+\ IF I . THEN
+ IF I 4 U.R THEN
+ 2 +LOOP
+ DROP ;
+
+\ 1000 PRIMES : display prime numbers up to 1000
+\ FAST FORTH for MSP430FR5969 @16MHz + TERATERM @921600Bds : 0.13 s
+
+: TEST \ 1.3s @ 16 MHz
+10 0 DO
+ CR
+ 1000 PRIMES
+LOOP ;
+
+TEST
\ No newline at end of file
--- /dev/null
+; -----------------------------------
+; prog100k.4th, to test speed of downloading
+; -----------------------------------
+ \
+WIPE
+NOECHO ; if an error occurs during download, comment this line then download again
+ \
+\ Copyright (C) <2016> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ ===========================================================================
+\ remember: for good downloading to target, all lines must be ended with CR+LF !
+\ ===========================================================================
+
+
+\ REGISTERS USAGE
+\ R4 to R7 must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, R7, R6, R5, R4
+\ example : PUSHM IP,Y
+\
+\ POPM order : R4, R5, R6, R7, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0<
+
+\ FORTH conditionnal : 0= 0< = < > U<
+
+\ display on a LCD 2x20 CHAR the code sent by an IR remote under philips RC5 protocol
+\ target : any TI MSP-EXP430FRxxxx launchpad (FRAM)
+\ LPM_MODE = LPM0 because use SMCLK for LCDVo
+
+\ DEMO : driver for IR remote compatible with the PHILIPS RC5 protocol
+\ plus : driver for 5V LCD 2x20 characters display with 4 bits data interface
+\ without usage of an auxiliary 5V to feed the LCD_Vo
+\ and without potentiometer to adjust the LCD contrast :
+\ to adjust LCD contrast, just press S1 (-) or S2 (+)
+\ LCDVo current consumption ~ 500 uA.
+
+\ ===================================================================================
+\ notice : adjust TA0EX0,TB0CTL,TB0EX0 and 20_us to the target frequency if <> 8MHz !
+\ ===================================================================================
+
+
+\ layout : I/O are defined in the launchpad.pat file (don't work with ChipStick_FR2433)
+
+\ GND <-------+---0V0----------> 1 LCD_Vss
+\ VCC >------ | --3V6-----+----> 2 LCD_Vdd
+\ | |
+\ ___ 470n ---
+\ ^ ---
+\ / \ 1N4148 |
+\ --- |
+\ 100n | 2k2 |
+\ TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (= 0V6 without modulation)
+\ -------------------------> 4 LCD_RW
+\ -------------------------> 5 LCD_RW
+\ -------------------------> 6 LCD_EN
+\ <------------------------> 11 LCD_DB4
+\ <------------------------> 12 LCD_DB5
+\ <------------------------> 13 LCD_DB5
+\ <------------------------> 14 LCD_DB7
+
+\ <----- LCD contrast + <--- Sw1 <--- (finger) :-)
+\ <----- LCD contrast - <--- Sw2 <--- (finger) :-)
+
+\ rc5 <--- OUT IR_Receiver (1 TSOP32236)
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+RST_STATE ;
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF1 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+ECHO
+ ; download is done
+RST_HERE ; this app is protected against <reset>,
+\ START
--- /dev/null
+; -----------------------------------
+; prog10k.4th
+; -----------------------------------
+ \
+PWR_STATE
+\ NOECHO ; if an error occurs during download, comment this line then download again
+ \
+\ Copyright (C) <2016> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ ===========================================================================
+\ remember: for good downloading to target, all lines must be ended with CR+LF !
+\ ===========================================================================
+
+
+\ REGISTERS USAGE
+\ R4 to R7 must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, R7, R6, R5, R4
+\ example : PUSHM IP,Y
+\
+\ POPM order : R4, R5, R6, R7, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0<
+
+\ FORTH conditionnal : 0= 0< = < > U<
+
+\ display on a LCD 2x20 CHAR the code sent by an IR remote under philips RC5 protocol
+\ target : any TI MSP-EXP430FRxxxx launchpad (FRAM)
+\ LPM_MODE = LPM0 because use SMCLK for LCDVo
+
+\ DEMO : driver for IR remote compatible with the PHILIPS RC5 protocol
+\ plus : driver for 5V LCD 2x20 characters display with 4 bits data interface
+\ without usage of an auxiliary 5V to feed the LCD_Vo
+\ and without potentiometer to adjust the LCD contrast :
+\ to adjust LCD contrast, just press S1 (-) or S2 (+)
+\ LCDVo current consumption ~ 500 uA.
+
+\ ===================================================================================
+\ notice : adjust TA0EX0,TB0CTL,TB0EX0 and 20_us to the target frequency if <> 8MHz !
+\ ===================================================================================
+
+
+\ layout : I/O are defined in the launchpad.pat file (don't work with ChipStick_FR2433)
+
+\ GND <-------+---0V0----------> 1 LCD_Vss
+\ VCC >------ | --3V6-----+----> 2 LCD_Vdd
+\ | |
+\ ___ 470n ---
+\ ^ ---
+\ / \ 1N4148 |
+\ --- |
+\ 100n | 2k2 |
+\ TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (= 0V6 without modulation)
+\ -------------------------> 4 LCD_RW
+\ -------------------------> 5 LCD_RW
+\ -------------------------> 6 LCD_EN
+\ <------------------------> 11 LCD_DB4
+\ <------------------------> 12 LCD_DB5
+\ <------------------------> 13 LCD_DB5
+\ <------------------------> 14 LCD_DB7
+
+\ <----- LCD contrast + <--- Sw1 <--- (finger) :-)
+\ <----- LCD contrast - <--- Sw2 <--- (finger) :-)
+
+\ rc5 <--- OUT IR_Receiver (1 TSOP32236)
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+PWR_STATE
+
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR to force fall down to LPM mode
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #38,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : BASE,TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+BIC #$F8,0(RSP) \ CPU is ON and GIE is OFF in retiSR to force fall down to LPM0_LOOP
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 1us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+BIC #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old UF9 = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF9,0(RSP) \ change Toggle bit memory, UserFlag1 = SR(9) = 1
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save variable BASE before use
+MOV TOS,0(PSP) \ save TOS before use
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #$4000,IP \ test /C6 bit in IP
+0= IF BIS #$40,TOS \ set C6 bit in S
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+
+\ ------------------------------\
+\ Display IR_RC5 code \
+\ ------------------------------\
+\ BIS.B #LED1,&LED1_OUT \ switch ON LED1, comment if no LED
+\ ------------------------------\
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ $10 BASE ! \ change BASE to hexadecimal
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+\ ------------------------------\
+\ BIC.B #LED1,&LED1_OUT \ switch OFF LED1, comment if no LED
+\ ------------------------------\
+MOV @PSP+,&BASE \ restore variable BASE
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+ MOV #$5A5E,&WDTCTL \ init WDT VLOCLK source ~10kHz /2^9 (50 ms), interval mode
+\ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init RC5_Int \
+\ ------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_INT,&WDT_Vec \ init WDT interval vector interrupt
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM) (very, very usefull after COLD or RESET !:-)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+
+ECHO
+ ; download is done
+PWR_HERE ; this app is protected against power ON/OFF,
+\ START
--- /dev/null
+; -----------------------------------
+; RC5toLCD.4th
+; -----------------------------------
+ \
+\ Copyright (C) <2016> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ ===========================================================================
+\ remember: for good downloading to target, all lines must be ended with CR+LF !
+\ ===========================================================================
+
+
+\ REGISTERS USAGE
+\ R4 to R7 must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+\ interrupts reset SR register !
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, R7, R6, R5, R4
+\ example : PUSHM IP,Y
+\
+\ POPM order : R4, R5, R6, R7, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0<
+
+\ FORTH conditionnal : 0= 0< = < > U<
+
+\ display on a LCD 2x20 CHAR the code sent by an IR remote under philips RC5 protocol
+\ target : any TI MSP-EXP430FRxxxx launchpad (FRAM)
+\ LPM_MODE = LPM0 because use SMCLK for LCDVo
+
+\ DEMO : driver for IR remote compatible with the PHILIPS RC5 protocol
+\ plus : driver for 5V LCD 2x20 characters display with 4 bits data interface
+\ without usage of an auxiliary 5V to feed the LCD_Vo
+\ and without potentiometer to adjust the LCD contrast :
+\ to adjust LCD contrast, just press S1 (-) or S2 (+)
+\ LCDVo current consumption ~ 500 uA.
+
+\ ===================================================================================
+\ notice : adjust TA0EX0,TB0CTL,TB0EX0 and 20_us to the target frequency if <> 8MHz !
+\ ===================================================================================
+
+
+\ layout : I/O are defined in the launchpad.pat file (don't work with ChipStick_FR2433)
+
+\ GND <-------+---0V0----------> 1 LCD_Vss
+\ VCC >------ | --3V6-----+----> 2 LCD_Vdd
+\ | |
+\ ___ 470n ---
+\ ^ ---
+\ / \ 1N4148 |
+\ --- |
+\ 100n | 2k2 |
+\ TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (= 0V6 without modulation)
+\ -------------------------> 4 LCD_RW
+\ -------------------------> 5 LCD_RW
+\ -------------------------> 6 LCD_EN
+\ <------------------------> 11 LCD_DB4
+\ <------------------------> 12 LCD_DB5
+\ <------------------------> 13 LCD_DB5
+\ <------------------------> 14 LCD_DB7
+
+\ <----- LCD contrast + <--- Sw1 <--- (finger) :-)
+\ <----- LCD contrast - <--- Sw2 <--- (finger) :-)
+
+\ rc5 <--- OUT IR_Receiver (1 TSOP32236)
+
+
+
+[UNDEFINED] {RC5TOLCD} [IF]
+ \
+MARKER {RC5TOLCD}
+ \
+[UNDEFINED] MAX [IF] \ MAX and MIN are defined in {ANS_COMP}
+ \
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+
+[THEN]
+ \
+
+[UNDEFINED] U.R [IF] \ defined in {UTILITY}
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+[THEN]
+ \
+
+\ CODE 20_US \ n -- n * 20 us
+\ BEGIN \ 3 cycles loop + 6~
+\ \ MOV #5,W \ 3 MCLK = 1 MHz
+\ \ MOV #23,W \ 3 MCLK = 4 MHz
+\ \ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ \ MOV #158,W \ 3 MCLK = 24 MHz
+\ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+\ SUB #1,W \ 1
+\ 0= UNTIL \ 2
+\ SUB #1,TOS \ 1
+\ 0= UNTIL \ 2
+\ MOV @PSP+,TOS \ 2
+\ MOV @IP+,PC \ 4
+\ ENDCODE
+\ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ here we presume that TB0IFG = 1...
+ BEGIN
+ BIT #1,&TB0CTL \ 3
+ 0<> UNTIL \ 2 loop until TB0IFG set
+ BIC #1,&TB0CTL \ 3 clear TB0IFG
+ SUB #1,TOS \ 1
+U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0=
+MOV @PSP+,TOS \ 2
+MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+: LCD_Entry_set $04 OR LCD_WrF ;
+ \
+: LCD_DSP_Ctrl $08 OR LCD_WrF ;
+ \
+: LCD_DSP_Shift $10 OR LCD_WrF ;
+ \
+: LCD_Fn_Set $20 OR LCD_WrF ;
+ \
+: LCD_CGRAM_Set $40 OR LCD_WrF ;
+ \
+: LCD_Goto $80 OR LCD_WrF ;
+ \
+CODE LCD_R \ -- byte read byte from LCD
+ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+COLON \ starts a FORTH word
+ TOP_LCD 2 20_us \ -- %0000HHHH
+ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+HI2LO \ switch from FORTH to assembler
+ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+ MOV @RSP+,IP \ restore IP saved by COLON
+ MOV @IP+,PC \
+ENDCODE
+ \
+
+CODE LCD_RdS \ -- status Read Status
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_R
+ENDCODE
+ \
+
+CODE LCD_RdC \ -- char Read Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_R
+ENDCODE
+ \
+
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+\ XOR.B #LED1,&LED1_OUT \ to visualise WDT
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #19,&TB0CCR2 \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 150 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #3,&TB0CCR2 \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -150 mV / decrement
+ THEN \
+ THEN \
+THEN \
+BW1 \ from quit on truncated RC5 message
+BW2 \ from repeated RC5 command
+BW3 \ from end of RC5_INT
+BIC #$78,0(RSP) \4 SCG1,SCG0,OSCOFF,CPUOFF and GIE are OFF in retiSR to force LPM0_LOOP despite pending interrupt
+RETI \5
+ENDASM
+ \
+
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : T,W,X,Y, TA1 timer, TA1R register
+\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ******************************\
+\ RC5_FirstStartBitHalfCycle: \
+\ ******************************\ division in TA1CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8)
+\ MOV #0,&TA1EX0 \ predivide by 1 in TA1EX0 register ( 125kHz| 1MHz | 2MHZ | 4MHZ | 8MHZ ), reset value
+ MOV #1,&TA1EX0 \ predivide by 2 in TA1EX0 register ( 250kHZ| 2MHz | 4MHZ | 8MHZ | 16MHZ )
+\ MOV #2,&TA1EX0 \ predivide by 3 in TA1EX0 register ( 375kHz| 3MHz | 6MHZ | 12MHZ | 24MHZ )
+\ MOV #3,&TA1EX0 \ predivide by 4 in TA1EX0 register ( 500kHZ| 4MHz | 8MHZ | 16MHZ )
+\ MOV #4,&TA1EX0 \ predivide by 6 in TA1EX0 register ( 625kHz| 5MHz | 10MHZ | 20MHZ )
+\ MOV #5,&TA1EX0 \ predivide by 6 in TA1EX0 register ( 750kHz| 6MHz | 12MHZ | 24MHZ )
+\ MOV #6,&TA1EX0 \ predivide by 7 in TA1EX0 register ( 875kHz| 7MHz | 14MHZ | 28MHZ )
+\ MOV #7,&TA1EX0 \ predivide by 8 in TA1EX0 register ( 1MHz | 8MHz | 16MHZ | 32MHZ )
+MOV #1778,X \ RC5_Period * 1us
+\ MOV #222,X \ RC5_Period * 8us (SMCLK/1 and first column above)
+MOV #14,W \ count of loop
+BEGIN \
+\ ******************************\
+\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period
+\ ******************************\ |
+\ MOV #%1000100100,&TA1CTL \ (re)start timer_A | SMCLK/1 time interval,free running,clear TA1_IFG and TA1R
+\ MOV #%1002100100,&TA1CTL \ (re)start timer_A | SMCLK/2 time interval,free running,clear TA1_IFG and TA1R
+\ MOV #%1010100100,&TA1CTL \ (re)start timer_A | SMCLK/4 time interval,free running,clear TA1_IFG and TA1R
+ MOV #%1011100100,&TA1CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear TA1_IFG and TA1R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4 cycle
+ BEGIN CMP Y,&TA1R \3 wait 1/2 + 3/4 cycle = n+1/4 cycles
+ U>= UNTIL \2
+\ ******************************\
+\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first
+\ ******************************\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag
+ MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+ ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present
+ BEGIN \ |
+ MOV &TA1R,X \3 | X grows from n+1/4 up to n+3/4 cycles
+ CMP Y,X \1 | cycle time out of bound ?
+ U>= IF \2 ^ | yes:
+ BIC #$30,&TA1CTL \ | | stop timer
+ GOTO BW1 \ | | quit on truncated RC5 message
+ THEN \ | |
+ BIT.B #RC5,&IR_IFG \3 | | n+1/2 cycles edge is always present
+ 0<> UNTIL \2 | |
+REPEAT \ ----> loop back --+ | with X = new RC5_period value
+\ ******************************\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ******************************\
+BIC #$30,&TA1CTL \ stop timer
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0
+MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0
+RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #BIT14,T \ test /C6 bit in T
+0= IF BIS #BIT6,X \ set C6 bit in X
+THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ -- BASE RC5_code
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+RRUM #3,T \ new toggle bit = T(13) ==> T(10)
+XOR @RSP,T \ (new XOR old) Toggle bits
+BIT #UF10,T \ repeated RC5_command ?
+0= ?GOTO BW2 \ yes, RETI without UF10 change and without action !
+XOR #UF10,0(RSP) \ 5 toggle bit memory
+\ ******************************\
+\ Display IR_RC5 code \ X = RC5 code
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save current base
+MOV #$0A,&BASE \ set hex base
+MOV TOS,0(PSP) \ save TOS
+MOV X,TOS \
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ CR ." $" 2 U.R \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+MOV @PSP+,&BASE \ restore current BASE
+\ ******************************\
+GOTO BW3
+\ ******************************\
+ENDASM
+ \
+
+\ ------------------------------\
+ASM BACKGROUND \
+\ ------------------------------\
+\ ... \ insert here your background task
+\ ... \
+\ ... \
+MOV #(SLEEP),PC \ Must be the last statement of BACKGROUND
+ENDASM \
+\ ------------------------------\
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ -------------------------------\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ -------------------------------\
+\ TB0CCRx \
+\ -------------------------------\
+\ TB0EX0 \
+\ ------------------------------\
+\ set TB0 to make 50kHz PWM \ for LCD_Vo, works without interrupt
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ)
+\ ------------------------------\
+\ MOV #%1001010100,&TB0CTL \ SMCLK/2, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (2 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+\ MOV #%1011010100,&TB0CTL \ SMCLK/8, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+ MOV #%1011010100,&TB0CTL \ SMCLK/8, up mode, clear timer, no int
+ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1011010100,&TB0CTL \ SMCLK/8, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #20,&TB0CCR0 \ 20*1us=20us
+\ ------------------------------\
+\ set TB0.2 to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+ MOV #10,&TB0CCR2 \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6)
+\ MOV #12,&TB0CCR2 \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ******************************\
+\ init RC5_Int \
+\ ******************************\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ******************************\
+\ init WatchDog TA0 \ eUSCI_A0 (FORTH terminal) has higher priority than TA0
+\ ******************************\
+\ %01 0001 0100 \ TAxCTL
+\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz
+\ -- \ ID divided by 1
+\ -- \ MC MODE = up to TAxCCRn
+\ - \ TACLR clear timer count
+\ - \ TAIE
+\ - \ TAIFG
+\ ------------------------------\
+ MOV #%0100010100,&TA0CTL \ start TA0, ACLK, up mode, disable int,
+\ ------------------------------\
+\ 000 \ TAxEX0
+\ --- \ TAIDEX pre divisor
+\ ------------------------------\
+\ %0000 0000 0000 0101 \ TAxCCR0
+ MOV ##1638,&TA0CCR0 \ init WDT for LFXT: 32768/20=1638 ==> 50ms
+\ MOV ##400,&TA0CCR0 \ init WDT for VLO: 8000/20=400 ==> 50ms
+\ ------------------------------\
+\ %0000 0000 0001 0000 \ TAxCCTL0
+\ - \ CAP capture/compare mode = compare
+\ - \ CCIEn
+\ - \ CCIFGn
+ MOV #%10000,&TA0CCTL0 \ enable compare interrupt, clear CCIFG0
+\ ------------------------------\
+ MOV #WDT_INT,&TA0_0_Vec \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+
+\ ------------------------------\
+\ redirects to background task \
+\ ------------------------------\
+ MOV #SLEEP,X \
+ MOV #BACKGROUND,2(X) \
+\ ------------------------------\
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ $03E8 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ $5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ $2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ $2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+\ NOECHO \ uncomment to run this app without terminal connexion
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM), must be the START last statement.
+;
+ \
+
+CODE STOP \ stops multitasking, must to be used before downloading app
+ MOV #SLEEP,X \
+ MOV #(SLEEP),2(X) \ restore the default background
+COLON
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+ECHO
+ ; downloading RC5toLCD.4th is done
+RST_HERE ; this app is protected against <reset>
+ \
+[THEN]
+ \
+START
\ No newline at end of file
; RTC_C.f
; --------------------
-\ Copyright (C) <2016> <J.M. THOORENS>
-\
-\ This program is free software: you can redistribute it and/or modify
-\ it under the terms of the GNU General Public License as published by
-\ the Free Software Foundation, either version 3 of the License, or
-\ (at your option) any later version.
-\
-\ This program is distributed in the hope that it will be useful,
-\ but WITHOUT ANY WARRANTY; without even the implied warranty of
-\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-\ GNU General Public License for more details.
-\
-\ You should have received a copy of the GNU General Public License
-\ along with this program. If not, see <http://www.gnu.org/licenses/>.
-
-
\ REGISTERS USAGE
\ R4 to R7 must be saved before use and restored after
\ scratch registers Y to S are free for use
\ allow to write on a SD_Card file with a valid date and a valid time
-\ ECHO ; if an error occurs during download, uncomment this line then download again
-
+[UNDEFINED] {RTC} [IF]
\
+[UNDEFINED] MAX [IF]
+ \
CODE MAX \ n1 n2 -- n3 signed maximum
- CMP @PSP,TOS \ n2-n1
- S< ?GOTO FW1 \ n2<n1
-BW1 ADD #2,PSP
- MOV @IP+,PC
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
ENDCODE
\
CODE MIN \ n1 n2 -- n3 signed minimum
- CMP @PSP,TOS \ n2-n1
- S< ?GOTO BW1 \ n2<n1
-FW1 MOV @PSP+,TOS
- MOV @IP+,PC
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
ENDCODE
+
+[THEN]
\
-: U.R \ u n -- display u unsigned in n width
+[UNDEFINED] U.R [IF]
+: U.R \ u n -- display u unsigned in n width (n >= 2)
>R <# 0 # #S #>
R> OVER - 0 MAX SPACES TYPE
;
+[THEN]
\
+
CODE DATE?
SUB #6,PSP
MOV TOS,4(PSP)
BEGIN
- BIT.B #$10,&RTCCTL2 \ test RTCRDY flag
+ BIT.B #RTCRDY,&RTCCTL1 \ test RTCRDY flag
0<> UNTIL \ wait until RTCRDY high
MOV &RTCYEARL,2(PSP) \ year
MOV.B &RTCMON,TOS
2 U.R $2F EMIT .
;
\
-CODE DATE!
- MOV.B #$A5,&RTCCTL1
+: DATE!
+DEPTH 2 > IF
+ HI2LO
MOV TOS,&RTCYEARL \ year
MOV.B @PSP,&RTCMON \ month \ @PSP+ don't work because byte format !
MOV.B 2(PSP),&RTCDAY \ day \ @PSP+ don't work because byte format !
ADD #4,PSP
MOV @PSP+,TOS \
-COLON
+ LO2HI
+THEN
." we are on " DATE?
;
\
CODE TIME?
SUB #6,PSP
- MOV TOS,4(PSP) \ save TOS
+ MOV TOS,4(PSP) \ save TOS
BEGIN
- BIT.B #$10,&RTCCTL2 \ test RTCRDY flag
- 0<> UNTIL \ wait until RTCRDY high
+ BIT.B #RTCRDY,&RTCCTL1 \
+ 0<> UNTIL \ wait until RTCRDY high
MOV.B &RTCSEC,TOS
- MOV TOS,2(PSP) \ seconds
+ MOV TOS,2(PSP) \ seconds
MOV.B &RTCMIN,TOS
- MOV TOS,0(PSP) \ minutes
- MOV.B &RTCHOUR,TOS \ hours
+ MOV TOS,0(PSP) \ minutes
+ MOV.B &RTCHOUR,TOS \ hours
COLON
2 U.R $3A EMIT
2 U.R $3A EMIT 2 U.R
;
\
: TIME!
+DEPTH 1 > IF
DEPTH 2 = IF 0 THEN \ to allow "hour min TIME!" scheme
HI2LO
- MOV.B #$A5,&RTCCTL1
MOV TOS,&RTCSEC \ seconds
MOV.B @PSP,&RTCMIN \ minutes \ @PSP+ don't work because byte format !
MOV.B 2(PSP),&RTCHOUR \ hours \ @PSP+ don't work because byte format !
ADD #4,PSP
MOV @PSP+,TOS \
LO2HI
+THEN
." it is " TIME?
;
\
ABUF ABUF 20 (ACCEPT) EVALUATE CR 3 SPACES DATE!
CR CR ." TIME (HMS or HM): "
ABUF ABUF 20 (ACCEPT) EVALUATE CR 3 SPACES TIME!
- CR
- PWR_STATE \ auto remove all this application !
+ CR NOECHO
HI2LO
MOV #PSTACK,PSP \ to avoid stack empty error if lack of typed values.
MOV @RSP+,IP
MOV @IP+,PC
ENDCODE
-
\
-GET_TIME \ all words created by RTC.f are removed
+PWR_HERE
+[THEN]
+ \
+GET_TIME
--- /dev/null
+
+\ how to test SD_CARD driver on your launchpad:
+
+
+\ remove the jumpers RX, TX of programming port (don't remove GND, TST, RST and VCC)
+\ wire PL2303TA/HXD: GND <-> GND, RX <-- TX, TX --> RX
+\ connect it to your PC on a free USB port
+\ connect the PL2303TA/HXD cable to your PC on another free USB port
+\ configure TERATERM as indicated in forthMSP430FR.asm
+
+
+\ if you have a MSP-EXP430FR5994 launchpad, program it with MSP_EXP430FR5994_3Mbds_SD_CARD.txt
+\ to do, drag and drop this file onto prog.bat
+\ nothing else to do!
+
+
+\ else edit forthMSP430FR.asm with scite editor
+\ uncomment your target, copy it
+\ paste it into (SHIFT+F8) param1
+\ set DTC .equ 1
+\ FREQUENCY .equ 16
+\ THREADS .equ 16
+\ TERMINALBAUDRATE .equ 3000000
+\
+\ uncomment: CONDCOMP
+\ MSP430ASSEMBLER
+\ SD_CARD_LOADER
+\ SD_CARD_READ_WRITE
+\
+\ compile for your target (CTRL+0)
+\
+\ program your target via TI interface (CTRL+1)
+\
+\ then wire your SD_Card module as described in your MSP430-FORTH\target.pat file
+
+
+
+
+\ format FAT16 or FAT32 a SD_CARD memory (max 64GB) with "FRxxxx" in the disk name
+\ drag and drop \CONDCOMP\MISC folder on the root of this SD_CARD memory (FastForth doesn't do yet)
+\ put it in your target SD slot
+\ if no reset, type COLD from the console input (teraterm) to reset FAST FORTH
+
+\ with MSP430FR5xxx or MSP430FR6xxx targets, you can first set RTC:
+\ by downloading RTC.f with SendSourceFileToTarget.bat
+\ then terminal input asks you to type (with spaces) (DMY), then (HMS) (or (HM)),
+\ So, subsequent copied files will be dated:
+
+\ with CopySourceFileToTarget_SD_Card.bat (or better, from scite editor, menu tools):
+
+\ copy TESTASM.4TH to \MISC\TESTASM.4TH (add path \MISC in the window opened by TERATERM)
+\ copy TSTWORDS.4TH to \TSTWORDS.4TH
+\ copy CORETEST_xMPY.4TH to \CORETEST.4TH (x=S for FR4133, else x=H; suppr _xMPY in the window opened by TERATERM)
+\ copy SD_TOOLS.f to \SD_TOOLS.4TH
+\ copy SD_TEST.f to \SD_TEST.4TH
+\ copy PROG10k.f to \PROG10k.4TH
+\ copy RTC.f to \RTC.4TH ( doesn't work with if FR2xxx or FR4xxx)
+
+
+[UNDEFINED] MAX [IF] \ MAX and MIN are defined in {ANS_COMP}
+ CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+ BW1 ADD #2,PSP
+ MOV @IP+,PC
+ ENDCODE
+ \
+
+ CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+ FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+[THEN]
+ \
+
+
+[UNDEFINED] U.R [IF] \ defined in {UTILITY}
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+>R <# 0 # #S #>
+R> OVER - 0 MAX SPACES TYPE
+;
+[THEN]
+ \
+
+[UNDEFINED] DUMP [IF] \ defined in {UTILITY}
+\ https://forth-standard.org/standard/tools/DUMP
+: DUMP \ adr n -- dump memory
+ BASE @ >R $10 BASE !
+ SWAP $FFF0 AND SWAP
+ OVER + SWAP
+ DO CR \ generate line
+ I 7 U.R SPACE \ generate address
+ I $10 + I \ display 16 bytes
+ DO I C@ 3 U.R LOOP
+ SPACE SPACE
+ I $10 + I \ display 16 chars
+ DO I C@ $7E MIN BL MAX EMIT LOOP
+ $10 +LOOP
+ R> BASE !
+;
+[THEN]
+ \
+
+: SD_TEST
+ ECHO CR
+ ." 1 Load {UTILITY} words" CR
+ ." 2 Load ANS core tests" CR
+ ." 3 Load a 10k program " CR
+ ." 4 Read only this source file" CR
+ ." 5 Write a dump of FORTH to yourfile.txt" CR
+ ." 6 append a dump of FORTH to yourfile.txt" CR
+ ." 7 Load truc (test error)" CR
+ ." 8 Set date and time" CR
+ ." your choice : "
+ KEY
+ 48 -
+ DUP 1 =
+ IF .
+ NOECHO LOAD" UTILITY.4TH" \ quiet downloading...
+ ELSE DUP 2 =
+ IF .
+ LOAD" CORETEST.4TH"
+ ELSE DUP 3 =
+ IF .
+ LOAD" PROG10K.4TH"
+ ELSE DUP 4 =
+ IF .
+ READ" PROG10K.4TH"
+ BEGIN
+ READ \ sequentially read 512 bytes
+ UNTIL \ prog10k.4TH is closed
+ ELSE DUP 5 =
+ IF .
+ DEL" YOURFILE.TXT"
+ WRITE" YOURFILE.TXT"
+ ['] SD_EMIT IS EMIT
+ PROGRAMSTART HERE OVER - DUMP
+ ['] (EMIT) IS EMIT
+ CLOSE
+ ELSE DUP 6 =
+ IF .
+ WRITE" YOURFILE.TXT"
+ ['] SD_EMIT IS EMIT
+ PROGRAMSTART HERE OVER - DUMP
+ ['] (EMIT) IS EMIT
+ CLOSE
+ ELSE DUP 7 =
+ IF .
+ LOAD" truc"
+ ELSE DUP 8 =
+ IF .
+ NOECHO LOAD" RTC.4TH" \ quiet downloading...
+ ELSE
+ DROP ." ?"
+ CR ." loading TSTWORDS.4TH..."
+ LOAD" TSTWORDS.4TH"
+ THEN
+ THEN
+ THEN
+ THEN
+ THEN
+ THEN
+ THEN
+ THEN
+;
+
+SD_TEST
--- /dev/null
+; ------------------------------------------------
+; BASIC TOOLS for SD Card : DIR FAT SECTOR CLUSTER
+; ------------------------------------------------
+
+\ Fast Forth For Texas Instrument MSP430FRxxxx FRAM devices
+\ Copyright (C) <2017> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY; without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+\ REGISTERS USAGE
+\ R4 to R7 must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, R7, R6, R5, R4
+\ example : PUSHM IP,Y
+\
+\ POPM order : R4, R5, R6, R7, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before GOTO ?GOTO : S< S>= U< U>= 0= 0<> <0
+
+\ FORTH conditionnal usage after IF UNTIL WHILE : 0= 0< = < > U<
+ \
+[DEFINED] {SD_LOAD} [UNDEFINED] {SD_TOOLS} AND [IF]
+ \
+MARKER {SD_TOOLS}
+ \
+[UNDEFINED] MAX [IF] \ MAX and MIN are defined in {ANS_COMP}
+ \
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+
+[THEN]
+ \
+
+[UNDEFINED] U.R [IF] \ defined in {UTILITY}
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+[THEN]
+ \
+
+[UNDEFINED] DUMP [IF] \ defined in {UTILITY}
+: DUMP \ adr n -- dump memory
+ BASE @ >R $10 BASE !
+ SWAP $FFF0 AND SWAP
+ OVER + SWAP
+ DO CR \ generate line
+ I 7 U.R SPACE \ generate address
+ I $10 + I \ display 16 bytes
+ DO I C@ 3 U.R LOOP
+ SPACE SPACE
+ I $10 + I \ display 16 chars
+ DO I C@ $7E MIN BL MAX EMIT LOOP
+ $10 +LOOP
+ R> BASE !
+;
+[THEN]
+ \
+
+
+\ display content of a sector
+\ ----------------------------------\
+CODE SECTOR \ sector. -- don't forget to add decimal point to your sector number
+\ ----------------------------------\
+ MOV TOS,X \ X = SectorH
+ MOV @PSP,W \ W = sectorL
+ CALL &ReadSectorWX \ W = SectorLO X = SectorHI
+COLON \
+ <# #S #> TYPE SPACE \ ud -- display the double number
+ BUFFER $200 DUMP CR ; \ then dump the sector
+\ ----------------------------------\
+ \
+
+\ ----------------------------------\
+CODE FAT \ Display CurFATsector
+\ ----------------------------------\
+ SUB #4,PSP \
+ MOV TOS,2(PSP) \
+ MOV &CurFATsector,0(PSP) \ FATsectorLO
+ ADD &OrgFAT1,0(PSP) \
+ MOV #0,TOS \ FATsectorHI = 0
+ JMP SECTOR \ jump to a defined word
+ENDCODE
+\ ----------------------------------\
+ \
+
+\ display first sector of a Cluster
+\ ----------------------------------\
+CODE CLUSTER \ cluster. -- don't forget to add decimal point to your cluster number
+\ ----------------------------------\
+ MOV.B &SecPerClus,W \ 3 SecPerClus(5-1) = multiplicator
+ MOV @PSP,X
+ RRA W \ 1
+ U< IF \ case of SecPerClus>1
+ BEGIN
+ ADD X,X \ 5 (RLA) shift one left MULTIPLICANDlo16
+ ADDC TOS,TOS \ 1 (RLC) shift one left MULTIPLICANDhi8
+ RRA W \ 1 shift one right multiplicator
+ U>= UNTIL \ carry set
+ THEN \
+ ADD &OrgClusters,X \ add OrgClusters = sector of virtual cluster 0 (word size)
+ MOV X,0(PSP)
+ ADDC #0,TOS \ don't forget carry
+ JMP SECTOR \ jump to a defined word
+ENDCODE
+\ ----------------------------------\
+ \
+
+\ ----------------------------------\
+CODE DIR \ Display CurrentDir first sector
+\ ----------------------------------\
+ SUB #4,PSP \
+ MOV TOS,2(PSP) \ save TOS
+ MOV &DIRclusterL,0(PSP) \
+ MOV &DIRclusterH,TOS \
+ JMP CLUSTER \
+ENDCODE
+\ ----------------------------------\
+ \
+ ; added : FAT to DUMP first sector of FAT1 and DIR for that of current DIRectory.
+ ; added : SECTOR to DUMP a sector and CLUSTER for first sector of a cluster
+ ; include a decimal point to force 32 bits number, example : .2 CLUSTER
+ \
+[THEN]
+ ; v--- use backspaces before hit "CR" to decrease application protection level
+PWR_HERE RST_HERE
\ No newline at end of file
--- /dev/null
+\ -----------------------------------------------------------------------
+\ File Name TestASM.4th
+\ -----------------------------------------------------------------------
+ECHO
+
+\ -----------------------------------------------------------------------
+\ test CPUx instructions PUSHM, POPM, RLAM, RRAM, RRCM, RRUM
+\ -----------------------------------------------------------------------
+CODE TESTPUSHM
+ MOV #22222,Y
+ MOV #3,X
+ MOV #2,W
+ MOV #1,T
+ MOV #0,S
+\ PUSHM Y,IP \ uncomment to test error (registers bad order)
+ PUSHM IP,W \ PUSHM order : PSP,TOS,IP,S,T,W,X,Y,rEXIT,rDOVAR,rDOCON,rDODOES
+ POPM W,IP \ POPM order : rDODOES,rDOCON,rDOVAR,rEXIT,Y,X,W,T,S,IP,TOS,PSP
+ SUB #10,PSP
+ MOV TOS,8(PSP) \ save old TOS
+ MOV S,6(PSP)
+ MOV T,4(PSP)
+ MOV W,2(PSP)
+ MOV X,0(PSP)
+ MOV Y,TOS
+\ RLAM #0,TOS \ uncomment to test error (bad shift value)
+ RRAM #1,TOS \ 0 < shift value < 5
+ RLAM #2,TOS
+ RRCM #1,TOS
+ RRUM #1,TOS
+ COLON \ high level part of the word starts here...
+ space . . . . .
+ ; \ and finishes here.
+ \
+TESTPUSHM ; you should see 11111 3 2 1 0 -->
+
+CODE TESTPOPM
+ MOV #22222,Y
+ MOV #3,X
+ MOV #2,W
+ MOV #1,T
+ MOV #0,S
+\ PUSHM W,IP \ uncomment to test error "out of bounds"
+ PUSHM IP,W \ PUSHM order : PSP,TOS,IP,S,T,W,X,Y,rEXIT,rDOVAR,rDOCON,rDODOES
+ POPM W,IP \ POPM order : rDODOES,rDOCON,rDOVAR,rEXIT,Y,X,W,T,S,IP,TOS,PSP
+ SUB #10,PSP
+ MOV TOS,8(PSP) \ save old TOS
+ MOV S,6(PSP)
+ MOV T,4(PSP)
+ MOV W,2(PSP)
+ MOV X,0(PSP)
+ MOV Y,TOS
+\ RLAM #0,TOS \ uncomment to test error "out of bounds"
+\ RLAM #5,TOS \ uncomment to test error "out of bounds"
+ RRAM #1,TOS \ 0 < shift value < 5
+ RLAM #2,TOS
+ RRCM #1,TOS
+ RRUM #1,TOS
+ COLON \ high level part of the word starts here...
+ space . . . . .
+ ; \ and finishes here.
+ \
+TESTPOPM ; you should see 11111 3 2 1 0 -->
+
+
+
+\ -----------------------------------------------------------------------
+\ test symbolic branch in assembler
+\ test a FORTH section encapsulated in an assembly word
+\ -----------------------------------------------------------------------
+CODE TEST1 \ the word "CODE" add ASSEMBLER as CONTEXT vocabulary...
+
+ MOV &BASE,&BASE \ to test &xxxx src operand
+ CMP #%10,&BASE
+0<> IF MOV #2,&BASE \ if base <> 2
+ELSE MOV #$0A,&BASE \ else base = 2
+THEN
+ COLON \ tips : no "ok" displayed in start of line <==> compilation mode
+ BASE @ U. \ always display 10 !
+ ;
+ \
+
+\ -----------------------------------------------------------------------
+\ test a word that starts as word FORTH and ends as assembly word
+\ -----------------------------------------------------------------------
+: TEST2 \ ":" starts compilation
+ BASE @ U. \ always display 10 !
+ HI2LO \ switch FORTH to ASM : compile one word (next address)
+ \ add vocabulary ASSEMBLER as CONTEXT vocabulary
+ \ switch in interpret mode
+ CMP #2, &BASE
+0<> IF MOV #2, &BASE \ if variable system BASE <> 2
+ELSE MOV #10,&BASE \ else (BASE = 2)
+THEN
+\ MOV #EXIT,PC \ to pair with ":" i.e. to restore IP saved by : then execute NEXT.
+\ but even compile two words, it's better to compile an inline EXIT :
+ MOV @RSP+,IP \ restore IP
+ MOV @IP+,PC \ = NEXT
+ENDCODE \ ends assembler : remove vocabulary ASSEMBLER from CONTEXT
+ \
+
+\ -----------------------------------------------------------------------
+\ test a word that starts as assembly word and ends as FORTH word
+\ -----------------------------------------------------------------------
+CODE TEST3 \ "CODE" starts assembler, i.e. add ASSEMBLER as CONTEXT vocabulary
+ CMP #2, &BASE
+0<> IF MOV #2, &BASE \ if variable system BASE <> 2
+ELSE MOV #10,&BASE \ else (BASE = 2)
+THEN COLON \
+ BASE @ U. \ always display 10 !
+; \
+ \
+
+
+\ -----------------------------------------------------------------------
+\ test an assembly jump spanning a section written in FORTH
+\ -----------------------------------------------------------------------
+: TEST5
+ SPACE
+ HI2LO
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV #%1010,TOS \ init count = 10
+BEGIN SUB #$0001,TOS
+ LO2HI
+ \ IP is already saved by word ":"
+ DUP U. \ display count
+ HI2LO
+ CMP #0,TOS
+0= UNTIL MOV @PSP+,TOS
+\ MOV #EXIT,PC \ to pair with ":" i.e. to restore IP saved by : then execute NEXT.
+ MOV @RSP+,IP \ restore IP
+ MOV @IP+,PC \ = NEXT
+ENDCODE
+ \
+TEST5 ; you should see : 9 8 7 6 5 4 3 2 1 0 -->
+ \
+
+\ -----------------------------------------------------------------------
+\ tests indexing address
+\ -----------------------------------------------------------------------
+
+: TABLE
+CREATE
+0 DO I C,
+LOOP
+DOES>
++
+;
+
+8 TABLE BYTES_TABLE
+ \
+2 BYTES_TABLE C@ . ; you should see 2 -->
+\
+
+
+VARIABLE BYTES_TABLE1
+
+$0201 BYTES_TABLE1 ! \ words written in memory are little endian !
+
+CODE IDX_TEST1 \ index -- value
+ MOV.B BYTES_TABLE1(TOS),TOS \ -- value
+COLON
+ U.
+;
+
+0 IDX_TEST1 ; you should see 1 -->
+
+CODE TEST6
+ MOV 0(PSP),0(PSP) \
+ MOV @IP+,PC
+ENDCODE
+
+
+1 TEST6 . ; you should see 1 -->
+
+
+\ -----------------------------------------------------------------------
+\ tests behaviour of assembly error
+\ -----------------------------------------------------------------------
+\ R16 causes an error, assembler context is aborted and the word TEST7 is "hidden".
+
+; CODE TEST7
+; MOV 0(PSP),0(R16) ; display an error "out of bounds" -->
+
+
+
+
+
+
--- /dev/null
+; -----------------------------------
+; RC5toLCD.4th
+; -----------------------------------
+ \
+RST_STATE ; remove all previous downloading
+ \
+\ Copyright (C) <2016> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ ===========================================================================
+\ remember: for good downloading to target, all lines must be ended with CR+LF !
+\ ===========================================================================
+
+
+\ REGISTERS USAGE
+\ R4 to R7 must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+\ interrupts reset SR register !
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, R7, R6, R5, R4
+\ example : PUSHM IP,Y
+\
+\ POPM order : R4, R5, R6, R7, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0<
+
+\ FORTH conditionnal : 0= 0< = < > U<
+
+\ display on a LCD 2x20 CHAR the code sent by an IR remote under philips RC5 protocol
+\ target : any TI MSP-EXP430FRxxxx launchpad (FRAM)
+\ LPM_MODE = LPM0 because use SMCLK for LCDVo
+
+\ DEMO : driver for IR remote compatible with the PHILIPS RC5 protocol
+\ plus : driver for 5V LCD 2x20 characters display with 4 bits data interface
+\ without usage of an auxiliary 5V to feed the LCD_Vo
+\ and without potentiometer to adjust the LCD contrast :
+\ to adjust LCD contrast, just press S1 (-) or S2 (+)
+\ LCDVo current consumption ~ 500 uA.
+
+\ ===================================================================================
+\ notice : adjust TA1EX0,TB0CTL,TB0EX0 and 20_us to the target frequency if <> 8MHz !
+\ ===================================================================================
+
+
+\ layout : I/O are defined in the launchpad.pat file (don't work with ChipStick_FR2433)
+
+\ GND <-------+---0V0----------> 1 LCD_Vss
+\ VCC >------ | --3V6-----+----> 2 LCD_Vdd
+\ | |
+\ ___ 470n ---
+\ ^ ---
+\ / \ 1N4148 |
+\ --- |
+\ 100n | 2k2 |
+\ TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (= 0V6 without modulation)
+\ -------------------------> 4 LCD_RW
+\ -------------------------> 5 LCD_RW
+\ -------------------------> 6 LCD_EN
+\ <------------------------> 11 LCD_DB4
+\ <------------------------> 12 LCD_DB5
+\ <------------------------> 13 LCD_DB5
+\ <------------------------> 14 LCD_DB7
+
+\ <----- LCD contrast + <--- Sw1 <--- (finger) :-)
+\ <----- LCD contrast - <--- Sw2 <--- (finger) :-)
+
+\ rc5 <--- OUT IR_Receiver (1 TSOP32236)
+
+
+
+CREATE CGRAM \ LCD_CGRAM
+$00 C, $02 C, $06 C, $0E C, $06 C, $02 C, $00 C, $00 C, \ char 0 = left arrow
+$00 C, $08 C, $0C C, $0E C, $0C C, $08 C, $00 C, $00 C, \ char 1 = right arrow
+$00 C, $00 C, $04 C, $0E C, $1F C, $00 C, $00 C, $00 C, \ char 2 = up arrow
+$00 C, $00 C, $1F C, $0E C, $04 C, $00 C, $00 C, $00 C, \ char 3 = down arrow
+
+ \
+[UNDEFINED] MAX [UNDEFINED] MIN OR [IF]
+ CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+ BW1 ADD #2,PSP
+ MOV @IP+,PC
+ ENDCODE
+ \
+ CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+ FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+[THEN]
+ \
+
+[UNDEFINED] U.R [IF]
+ : U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 #S #>
+ R> OVER - 0 MAX SPACES TYPE
+ ;
+[THEN]
+ \
+
+[UNDEFINED] S>D [IF]
+ CODE S>D \ n -- d
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIT #$8000,TOS
+ MOV #0,TOS
+ 0<> IF
+ SUB #1,TOS
+ THEN
+ NEXT
+ ENDCODE
+[THEN]
+ \
+
+CODE #DABS \ d1 -- |d1| absolute value, sign in SR(UF9)
+BIC #UF9,SR
+BIT #$8000,TOS
+0<> IF
+ XOR #-1,0(PSP)
+ XOR #-1,TOS
+ ADD #1,0(PSP)
+ ADDC #0,TOS
+ BIS #UF9,SR
+THEN
+NEXT
+ENDCODE
+ \
+
+CODE #SIGN \ tests SR(UF9) and displays sign + or sign -
+SUB #2,PSP
+MOV TOS,0(PSP)
+MOV.B #43,TOS \ "+"
+BIT #UF9,SR
+0<> IF
+ ADD.B #2,TOS \ "-"
+ BIC #UF9,SR
+THEN
+COLON
+HOLD ;
+ \
+
+: SS. \ n -- display signed n in 2 digits
+<# S>D #DABS # #S #SIGN #> TYPE
+;
+ \
+
+: UU. \ u -- display unsigned u in 2 digits
+ <# 0 # #S #> TYPE
+;
+ \
+
+: U.UUU \ u -- display unsigned u in 1.3 digits
+ <# 0 # # # #44 HOLD #S #> TYPE
+;
+ \
+
+\ CODE 20_US \ n -- n * 20 us
+\ BEGIN \ 3 cycles loop + 6~
+\ \ MOV #5,W \ 3 MCLK = 1 MHz
+\ \ MOV #23,W \ 3 MCLK = 4 MHz
+\ \ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ \ MOV #158,W \ 3 MCLK = 24 MHz
+\ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+\ SUB #1,W \ 1
+\ 0= UNTIL \ 2
+\ SUB #1,TOS \ 1
+\ 0= UNTIL \ 2
+\ MOV @PSP+,TOS \ 2
+\ MOV @IP+,PC \ 4
+\ ENDCODE
+\ \
+
+CODE 20_US \ n -- n * 20 us
+BEGIN \ as no TB0 interrupt, TB0IFG is always 1 here, so add a dummy loop with U< instead of 0= UNTIL
+ BEGIN
+ BIT #1,&TB0CTL \ 3 TBI0FG ?
+ 0<> UNTIL \ 2
+ BIC #1,&TB0CTL \ 3 clear TB0IFG
+ SUB #1,TOS \ 1
+U< UNTIL \ 2
+BW1
+MOV @PSP+,TOS \ 2
+MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+CODE TOP_LCD \ LCD Sample
+\ \ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ GOTO BW1
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+CODE LCD_W \ byte -- write byte to LCD
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+;
+ \
+
+CODE LCD_WrC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+
+CODE LCD_WrF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+
+: LCD_Clear
+ $01 LCD_WrF 100 20_us \ $01 LCD_WrF 80 20_us ==> bad init !
+;
+ \
+
+: LCD_Home
+ $02 LCD_WrF 100 20_us
+;
+ \
+
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+
+: LCD_Goto $80 OR LCD_WrF ;
+ \
+
+\ CODE LCD_R \ -- byte read byte from LCD
+\ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000HHHH
+\ TOP_LCD 2 20_us \ -- %0000HHHH %0000LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH0000 %0000LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHHLLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ CODE LCD_RdC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ JMP LCD_R
+\ ENDCODE
+\ \
+
+\ ******************************\
+ASM WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+\ XOR.B #LED1,&LED1_OUT \ to visualise WDT
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #17,&TB0CCR2 \ maxi Ton = 17/20 & VDD=3V6 ==> LCD_Vo = -1V4
+\ CMP #19,&TB0CCR2 \ maxi Ton = 19/20 & VDD=3V3 ==> LCD_Vo = -1V5
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 7/20 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+BW1
+BW2
+BW3
+\ BIC #$78,0(RSP) \4 SCG1,SCG0,OSCOFF,CPUOFF and GIE are OFF in retiSR to force LPM0_LOOP despite pending interrupt
+\ MOV @RSP+,SR \2
+\ RET \4~ for system OFF / 1 sec. ==> 1mA * 5us = 5nC + 6,5uA
+\ ADD #2,RSP \2
+\ RET \5~ for system OFF / 1 sec. ==> 1mA * 5us = 5nC + 6,5uA
+BIC #$78,0(RSP) \4 SCG1,SCG0,OSCOFF,CPUOFF and GIE are OFF in retiSR to force LPM0_LOOP despite pending interrupt
+RETI \5~ for system OFF / 1 sec. ==> 1mA * 5us = 5nC + 6,5uA
+ENDASM
+ \
+
+
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : T,W,X,Y, TA1 timer, TA1R register
+\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ******************************\
+\ RC5_FirstStartBitHalfCycle: \
+\ ******************************\ division in TA1CTL (SMCLK/1,SMCLK/1,SMCLK/2,SMCLK/4,SMCLK/8)
+\ MOV #0,&TA1EX0 \ predivide by 1 in TA1EX0 register ( 125kHz| 1MHz| 2MHZ| 4MHZ| 8MHZ), reset value
+ MOV #1,&TA1EX0 \ predivide by 2 in TA1EX0 register ( 250kHZ| 2MHz| 4MHZ| 8MHZ| 16MHZ)
+\ MOV #2,&TA1EX0 \ predivide by 3 in TA1EX0 register ( 375kHz| 3MHz| 6MHZ| 12MHZ| 24MHZ)
+\ MOV #3,&TA1EX0 \ predivide by 4 in TA1EX0 register ( 500kHZ| 4MHz| 8MHZ| 16MHZ)
+\ MOV #4,&TA1EX0 \ predivide by 6 in TA1EX0 register ( 625kHz| 5MHz| 10MHZ| 20MHZ)
+\ MOV #5,&TA1EX0 \ predivide by 6 in TA1EX0 register ( 750kHz| 6MHz| 12MHZ| 24MHZ)
+\ MOV #6,&TA1EX0 \ predivide by 7 in TA1EX0 register ( 875kHz| 7MHz| 14MHZ| 28MHZ)
+\ MOV #7,&TA1EX0 \ predivide by 8 in TA1EX0 register ( 1MHz| 8MHz| 16MHZ| 32MHZ)
+MOV #1778,X \ RC5_Period * 1us
+\ MOV #222,X \ RC5_Period * 8us (SMCLK/1 and first column above)
+MOV #14,W \ count of loop
+BEGIN \
+\ ******************************\
+\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period
+\ ******************************\ |
+\ MOV #%1000100100,&TA1CTL \ (re)start timer_A | SMCLK/1 time interval,free running,clear TA1_IFG and TA1R
+\ MOV #%1002100100,&TA1CTL \ (re)start timer_A | SMCLK/2 time interval,free running,clear TA1_IFG and TA1R
+\ MOV #%1010100100,&TA1CTL \ (re)start timer_A | SMCLK/4 time interval,free running,clear TA1_IFG and TA1R
+ MOV #%1011100100,&TA1CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear TA1_IFG and TA1R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4 cycle
+ BEGIN CMP Y,&TA1R \3 wait 1/2 + 3/4 cycle = n+1/4 cycles
+ U>= UNTIL \2
+\ ******************************\
+\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first
+\ ******************************\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag
+ MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+ ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present
+ BEGIN \ |
+ MOV &TA1R,X \3 | X grows from n+1/4 up to n+3/4 cycles
+ CMP Y,X \1 | cycle time out of bound ?
+ U>= IF \2 ^ | yes:
+ BIC #$30,&TA1CTL \ | | stop timer
+ GOTO BW1 \ | | quit on truncated RC5 message
+ THEN \ | |
+ BIT.B #RC5,&IR_IFG \3 | | n+1/2 cycles edge is always present
+ 0<> UNTIL \2 | |
+REPEAT \ ----> loop back --+ | with X = new RC5_period value
+\ ******************************\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ******************************\
+BIC #$30,&TA1CTL \ stop timer
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0
+MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0
+RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #BIT14,T \ test /C6 bit in T
+0= IF BIS #BIT6,X \ set C6 bit in X
+THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ -- BASE RC5_code
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+RRUM #3,T \ new toggle bit = T(13) ==> T(10)
+XOR @RSP,T \ (new XOR old) Toggle bits
+BIT #UF10,T \ repeated RC5_command ?
+0= ?GOTO BW2 \ yes, RETI without UF10 change and without action !
+XOR #UF10,0(RSP) \ 5 toggle bit memory
+\ ******************************\
+\ Display IR_RC5 code \ X = RC5 code
+\ ******************************\
+SUB #4,PSP \
+MOV &BASE,2(PSP) \ save current base
+MOV #$10,&BASE \ set hex base
+MOV TOS,0(PSP) \ save TOS
+MOV X,TOS \
+LO2HI \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ CR ." $" UU. \ print IR_RC5 code
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+HI2LO \ switch from FORTH to assembler
+MOV @PSP+,&BASE \ restore current BASE
+\ ******************************\
+GOTO BW3
+\ ******************************\
+ENDASM
+ \
+
+
+\ ------------------------------\
+ASM BACKGROUND \
+\ ------------------------------\
+\ ... \ insert here your background task
+\ ... \
+\ ... \
+\ ------------------------------\
+\ define LPM mode \
+\ ------------------------------\
+ BIS #LPM4,SR \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+ MOV #(SLEEP),PC \ Must be the last statement of BACKGROUND
+ENDASM \
+\ ------------------------------\
+ \
+
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to TB0CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ -------------------------------\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ -------------------------------\
+\ TB0CCRx \
+\ -------------------------------\
+\ TB0EX0 \
+\ ------------------------------\
+\ set TB0 to make 50kHz PWM \ for LCD_Vo, works without interrupt
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ)
+\ ------------------------------\
+\ MOV #%1001010100,&TB0CTL \ SMCLK/2, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (2 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+\ MOV #%1011010100,&TB0CTL \ SMCLK/8, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+ MOV #%1011010100,&TB0CTL \ SMCLK/8, up mode, clear timer, no int
+ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1011010100,&TB0CTL \ SMCLK/8, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #20,&TB0CCR0 \ 20*1us=20us
+\ ------------------------------\
+\ set TB0.2 to generate PWM for LCD_Vo
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+ MOV #12,&TB0CCR2 \ contrast adjust : 11/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6)
+\ MOV #14,&TB0CCR2 \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 TB0.2
+\ ------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ******************************\
+\ init RC5_Int \
+\ ******************************\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+ MOV #RC5_INT,&IR_Vec \ init interrupt vector
+\ ******************************\
+\ init WatchDog TA0 \ eUSCI_A0 (FORTH terminal) has higher priority than TA0
+\ ******************************\
+\ %01 0001 0100 \ TAxCTL
+\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz
+\ -- \ ID divided by 1
+\ -- \ MC MODE = up to TAxCCRn
+\ - \ TACLR clear timer count
+\ - \ TAIE
+\ - \ TAIFG
+\ ------------------------------\
+ MOV #%0100010100,&TA0CTL \ start TA0, ACLK, up mode, disable int,
+\ ------------------------------\
+\ 000 \ TAxEX0
+\ --- \ TAIDEX pre divisor
+\ ------------------------------\
+ MOV ##1638,&TA0CCR0 \ init WDT for LFXT: 32768/20=1638 ==> 50ms
+\ MOV ##400,&TA0CCR0 \ init WDT for VLO: 8000/20=400 ==> 50ms
+\ ------------------------------\
+\ %0000 0000 0001 0000 \ TAxCCTL0
+\ - \ CAP capture/compare mode = compare
+\ - \ CCIEn
+\ - \ CCIFGn
+ MOV #%10000,&TA0CCTL0 \ enable compare interrupt, clear CCIFG0
+\ ------------------------------\
+ MOV #WDT_INT,&TA0_0_Vec \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
+\ ------------------------------\
+\ redirects to background task \
+\ ------------------------------\
+ MOV #SLEEP,X \
+ MOV #BACKGROUND,2(X) \
+\ ------------------------------\
+
+LO2HI \ no need to push IP because (WARM) resets the Return Stack !
+
+\ ------------------------------\
+\ Init LCD 2x20 \
+\ ------------------------------\
+ #1000 20_US \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ #205 20_US \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ #5 20_US \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ #2 20_US \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ #2 20_US \ wait 40 us = LCD cycle
+ $28 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+
+ $40 LCD_WrF \ LCD_CGRAM_Adr_Set at 0
+ CGRAM 32 0 \ -- addr limit index @ of table CGRAM in FRAM
+ DO DUP I + C@ \ -- @ byte
+ LCD_WrC \ -- @ write byte
+ LOOP DROP
+
+ $0C LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+\ NOECHO \ uncomment to run this app without terminal connexion
+ CR
+ ." RC5toLCD is running. Type STOP to quit"
+ LIT RECURSE IS WARM \ insert this START routine between WARM and (WARM)...
+ (WARM) \ ...and continue with (WARM), must be the last statement.
+;
+ \
+
+
+CODE SRD
+SUB #1,TOS
+MOV SR,TOS
+SUB #2,PSP
+MOV &BASE,0(PSP)
+MOV #2,&BASE
+COLON \ switch from assembler to FORTH
+ ['] LCD_CLEAR IS CR \ redirects CR
+ ['] LCD_WrC IS EMIT \ redirects EMIT
+ CR
+ <# 0 # # # # # # # #
+ 32 HOLD
+ # # # # # # # # #> TYPE \ print SR register
+ ['] (CR) IS CR \ restore CR
+ ['] (EMIT) IS EMIT \ restore EMIT
+ R> BASE !
+;
+
+
+: A_L 0 EMIT ; \ LEFT ARROW
+: A_R 1 EMIT ; \ RIGHT ARROW
+: A_U 2 EMIT ; \ UP ARROW
+: A_D 3 EMIT ; \ DOWN ARROW
+: A_P 43 EMIT ; \ PLUS SIGN
+: A_M 45 EMIT ; \ MINUS SIGN
+ \
+
+\ display ARROWs, PLUS MINUS
+\ to hide ARROW : ' SPACE IS D_L, for example
+\ or MOV #D_L,X
+\ MOV #SPACE,2(X)
+
+DEFER D_L ' A_L IS D_L
+DEFER D_U ' A_U IS D_U
+DEFER D_D ' A_D IS D_D
+DEFER D_R ' A_R IS D_R
+DEFER D_P ' A_P IS D_P
+DEFER D_M ' A_M IS D_M
+
+ \
+
+: ONOFF
+IF ." ON "
+ELSE ." OFF "
+THEN
+;
+
+: D_VOLUME
+D_M ." Volume : " SS. ." dBV " D_P
+;
+
+
+\ ===============================================
+
+: MENUDEF \ CHANNEL --
+LCD_HOME D_L ." MENU " D_U D_D ." InLive " D_R ." PASSWORD: "
+$40 LCD_GOTO
+;
+ \
+
+: OUTPUT \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUDEF
+D_M ." Output : " SS. ." dBV " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: AUXCD1 \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUDEF
+D_M ." Chan 1 : " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: AUXCD2 \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUDEF
+D_M ." Chan 2 : " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+\ ===============================================
+
+: MENUCHAN \ CHANNEL --
+LCD_HOME D_L ." MENU " D_U D_D ." Chan" UU. SPACE D_R
+$40 LCD_GOTO
+;
+ \
+
+: GAIN \ GAIN CHANNEL --
+['] LCD_WRC IS EMIT
+MENUCHAN
+D_M ." Gain : " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: NGLVL \ NGLVL CHANNEL --
+['] LCD_WRC IS EMIT
+MENUCHAN
+D_M ." NGlevel: " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: NGDLY \ NGDLY CHANNEL --
+['] LCD_WRC IS EMIT
+MENUCHAN
+D_M ." NGdelay: " U.UUU ." s " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: HIPASS \ HIPASS CHANNEL --
+['] LCD_WRC IS EMIT
+MENUCHAN
+D_M ." HiPass : " 4 U.R ." Hz " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: AMPOUT \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUCHAN
+D_M ." Chan. output " ONOFF D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: PHANTOM \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUCHAN
+D_M ." MIC Phantom " ONOFF D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: PTT \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUCHAN
+D_M ." Push To Talk " ONOFF D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: AUTO \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUCHAN
+D_M ." Auto Filter " ONOFF D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+
+\ ===============================================
+
+: MENUAMP \ CHANNEL --
+LCD_HOME D_L ." MENU " D_U D_D ." COMMON " D_R
+$40 LCD_GOTO
+;
+ \
+
+: VOLUME \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUAMP
+D_VOLUME
+['] (EMIT) IS EMIT
+;
+ \
+
+: GRAVE \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUAMP
+D_M ." Graves : " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: AIGUS \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUAMP
+D_M ." Aigus : " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: VOLMAX \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUAMP
+D_M ." Vol Max : " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: AUX1MAX \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUAMP
+D_M ." Chn1 Max: " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: AUX2MAX \ PARAM(VALUE) CHANNEL --
+['] LCD_WRC IS EMIT
+MENUAMP
+D_M ." Chn2 Max: " SS. ." dB " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+: CONTRAST
+['] LCD_WRC IS EMIT
+MENUAMP
+D_M ." Contrast " UU. ." Incr " D_P
+['] (EMIT) IS EMIT
+;
+ \
+
+\ ===============================================
+
+
+CODE STOP \ stops multitasking, must to be used before downloading app
+ MOV #SLEEP,X \ restore the default background
+ MOV #(SLEEP),2(X) \
+COLON
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+
+
+ECHO
+ ; downloading RC5toLCD.4th is done
+RST_HERE ; this app is protected against <reset>
+\ START
--- /dev/null
+\ -----------------------------
+\ MSP-EXP430FR5969_TSTWORDS.4th
+\ -----------------------------
+
+PWR_HERE
+
+\ -----------------------------------------------------------------------
+\ test some assembler words and show how to mix FORTH/ASSEMBLER routines
+\ -----------------------------------------------------------------------
+LOAD" \misc\TestASM.4th"
+
+\ -------------------------------------
+\ here we returned in the TestWords.4th
+\ -------------------------------------
+
+\ ----------
+\ LOOP tests
+\ ----------
+: LOOP_TEST 8 0 DO I . LOOP
+;
+
+LOOP_TEST \ you should see 0 1 2 3 4 5 6 7 -->
+
+
+: LOOP_TEST1 \ n <LOOP_TEST1> ---
+
+ BEGIN DUP U. 1 -
+ ?DUP
+ 0= UNTIL
+;
+
+
+: LOOP_MAX \ FIND_NOTHING --
+ 0 0
+ DO
+ LOOP \ 14 cycles by loop
+ ABORT" 65536 LOOP "
+;
+
+
+
+ : FIND_TEST \ FIND_TEST <word> --
+ BL WORD \ -- c-addr
+ 50000 0
+ DO \ -- c-addr
+ DUP
+ FIND DROP DROP
+ LOOP
+ FIND
+ 0= IF ABORT" <-- not found !"
+ ELSE ABORT" <-- found !"
+ THEN
+ ;
+
+\ seeking $ word, FIND jumps all words on their first character so time of word loop is 20 cycles
+\ see FIND in the source file for more information
+
+\ FIND_TEST <lastword> result @ 8MHz, monothread : 1,2s
+
+\ FIND_TEST $ results @ 8MHz, monothread, 201 words in vocabulary FORTH :
+\ 27 seconds with only FORTH vocabulary in CONTEXT
+\ 540 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 2.6866 us / word, 21,49 cycles / word (for 20 cycles calculated (see FIND in source file)
+
+
+\ FIND_TEST $ results @ 8MHz, 2 threads, 201 words in vocabulary FORTH :
+\ 13 second with only FORTH vocabulary in CONTEXT
+\ 260 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 1,293 us / word, 10,34 cycles / word
+
+\ FIND_TEST $ results @ 8MHz, 4 threads, 201 words in vocabulary FORTH :
+\ 8 second with only FORTH vocabulary in CONTEXT
+\ 160 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 0,796 us / word, 6,37 cycles / word
+
+\ FIND_TEST $ results @ 8MHz, 8 threads, 201 words in vocabulary FORTH :
+\ 4.66 second with only FORTH vocabulary in CONTEXT
+\ 93 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 0,4463 us / word, 3,7 cycles / word
+
+\ FIND_TEST $ results @ 8MHz, 16 threads, 201 words in vocabulary FORTH :
+\ 2,8 second with only FORTH vocabulary in CONTEXT
+\ 56 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 0,278 us / word, 2,22 cycles / word
+
+
+\ --------
+\ KEY test
+\ --------
+: KEY_TEST
+ ECHO
+ ." type a key : "
+ KEY EMIT \ wait for a KEY, then emit it
+;
+\ KEY_TEST
--- /dev/null
+\ ------------------
+\ BOOT.f
+\ ------------------
+
+\ must be preprocessed with yourtarget.pat file
+
+\ REGISTERS USAGE
+\ R4 to R7 must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, R7, R6, R5, R4
+\ example : PUSHM IP,Y
+\
+\ POPM order : R4, R5, R6, R7, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before GOTO ?GOTO : S< S>= U< U>= 0= 0<> <0
+
+\ FORTH conditionnal usage before IF UNTIL WHILE : 0= 0< = < > U<
+
+\ NOECHO ; if an error occurs, comment this line before new download to find it.
+
+
+\ This source is loaded when FastForth detects a SD_Card memory
+
+\ =======================================================
+\ then, start what you want FastForth to do
+\ =======================================================
+
+\ ECHO ; if an error occurs during download, uncomment this line then download again
+
+\ PWR_HERE ; uncomment if you really want to preserve all previous and volatile applications
+
+
+
+: BOOT
+ ECHO CR
+ ." 1 set RTC" CR
+ ." 2 add SD_TOOLS" CR
+ ." 3 Test ANS94" CR
+ ." your choice : "
+
+ KEY
+ $30 -
+ DUP 1 =
+ IF .
+ LOAD" RTC.4TH" \ perform (reset to) PWR_STATE ==> remove BOOT
+ ELSE DUP 2 =
+ IF .
+ LOAD" SD_TOOLS.4th" \ performs PWR_HERE
+ ELSE DUP 3 =
+ IF .
+ LOAD" CORETEST.4TH"
+ ELSE
+ DROP 0 .
+ THEN
+ THEN
+ THEN
+ CR
+;
+
+BOOT
--- /dev/null
+\ UTILITY.f
+\ must be preprocessed with yourtarget.pat file because PSTACK,CONTEXT,INI_THREAD
+
+\ REGISTERS USAGE
+\ R4 to R7 must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, R7, R6, R5, R4
+\ example : PUSHM IP,Y
+\
+\ POPM order : R4, R5, R6, R7, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before GOTO ?GOTO : S< S>= U< U>= 0= 0<> <0
+
+\ FORTH conditionnal usage after IF UNTIL WHILE : 0= 0< = < > U<
+
+
+[UNDEFINED] {UTILITY} [IF]
+ \
+
+MARKER {UTILITY}
+ \
+
+[UNDEFINED] ? [IF] \
+\ https://forth-standard.org/standard/tools/q
+CODE ? \ adr -- display the content of adr
+ MOV @TOS,TOS
+ MOV #U.,PC \ goto U.
+ENDCODE
+[THEN]
+ \
+
+[UNDEFINED] .S [IF] \
+\ https://forth-standard.org/standard/tools/DotS
+CODE .S \ -- display <depth> of Param Stack and stack contents if not empty
+ MOV TOS,-2(PSP) \ -- TOS ( tos x x )
+ MOV PSP,TOS
+ SUB #2,TOS \ to take count that TOS is first cell
+ MOV TOS,-6(PSP) \ -- TOS ( tos x PSP )
+ MOV #PSTACK,TOS \ -- P0 ( tos x PSP )
+ SUB #2,TOS \ to take count that TOS is first cell
+BW1 MOV TOS,-4(PSP) \ -- S0 ( tos S0 SP )
+ SUB #6,PSP \ -- S0 SP S0
+ SUB @PSP,TOS \ -- S0 SP S0-SP
+ RRA TOS \ -- S0 SP #cells
+COLON
+ $3C EMIT \ char '<'
+ . \ display #cells
+ $08 EMIT \ backspace
+ $3E EMIT SPACE \ char '>' SPACE
+ OVER OVER > \
+ 0= IF
+ DROP DROP EXIT
+ THEN
+ DO
+ I @ U.
+ 2 +LOOP
+;
+[THEN]
+ \
+
+[UNDEFINED] .RS [IF] \
+CODE .RS \ -- display <depth> of Return Stack and stack contents if not empty
+ MOV TOS,-2(PSP) \ -- TOS ( tos x x )
+ MOV RSP,-6(PSP) \ -- TOS ( tos x RSP )
+ MOV #RSTACK,TOS \ -- R0 ( tos x RSP )
+ GOTO BW1
+ENDCODE
+[THEN]
+ \
+
+\ : WORDS \ -- list all words in all dicts in CONTEXT.
+\
+\ \ \ vvvvvvvv may be skipped vvvvvvvv
+\ \ BASE @ \ -- BASE
+\ \ #10 BASE !
+\ \ CR ." "
+\ \ INI_THREAD @ DUP
+\ \ 1 = IF DROP ." monothread"
+\ \ ELSE . ." threads"
+\ \ THEN ." vocabularies"
+\ \ BASE ! \ --
+\ \ \ ^^^^^^^^ may be skipped ^^^^^^^^
+\
+\ CONTEXT \ -- CONTEXT
+\ BEGIN \ search dictionnary
+\ DUP
+\ 2 + SWAP \ -- CONTEXT+2 CONTEXT
+\ @ ?DUP \ -- CONTEXT+2 (VOC_BODY VOC_BODY or 0)
+\ WHILE \ -- CONTEXT+2 VOC_BODY dictionnary found
+\ CR ." " \
+\ \ MOVE all threads of VOC_BODY in PAD
+\ DUP PAD INI_THREAD @ DUP + \ -- CONTEXT+2 VOC_BODY VOC_BODY PAD THREAD*2
+\ MOVE \ char MOVE
+\
+\ BEGIN \ -- CONTEXT+2 VOC_BODY
+\ 0 DUP \ -- CONTEXT+2 VOC_BODY ptr MAX
+\ \ select the MAX of NFA in threads
+\ INI_THREAD @ DUP + 0 DO \ ptr = threads*2
+\ DUP I PAD + @ \ -- CONTEXT+2 VOC_BODY ptr MAX MAX NFAx
+\ U< IF
+\ DROP DROP I DUP PAD + @ \ -- CONTEXT+2 VOC_BODY ptr MAX if MAX U< NFAx replace adr and MAX
+\ THEN \
+\ 2 +LOOP \ -- CONTEXT+2 VOC_BODY ptr MAX
+\ ?DUP \ -- CONTEXT+2 VOC_BODY ptr MAX max NFA = 0 ? end of vocabulary ?
+\ WHILE \ -- CONTEXT+2 VOC_BODY ptr MAX
+\ \ replace it by its LFA
+\ DUP \ -- CONTEXT+2 VOC_BODY ptr MAX MAX
+\ 2 - @ \ -- CONTEXT+2 VOC_BODY ptr MAX [LFA]
+\ ROT \ -- CONTEXT+2 VOC_BODY MAX [LFA] ptr
+\ PAD + \ -- CONTEXT+2 VOC_BODY MAX [LFA] thread
+\ ! \ -- CONTEXT+2 VOC_BODY MAX
+\ \ type it in 16 chars format
+\ DUP \ -- CONTEXT+2 VOC_BODY MAX MAX
+\ COUNT $7F AND TYPE \ -- CONTEXT+2 VOC_BODY MAX
+\ C@ $0F AND \ --
+\ $10 SWAP - SPACES \ -- CONTEXT+2 VOC_BODY
+\ \ search next MAX of NFA
+\ REPEAT
+\ \ -- CONTEXT+2 VOC_BODY 0
+\ DROP DROP \ -- CONTEXT+2
+\ CR
+\ \ repeat for each CONTEXT vocabulary
+\
+\ REPEAT \ -- 0
+\ DROP \ --
+\ ;
+ \
+
+
+[UNDEFINED] WORDS [IF] \
+\ https://forth-standard.org/standard/tools/WORDS
+: WORDS \ -- list all words in first vocabulary in CONTEXT.
+
+\ \ vvvvvvvv may be skipped vvvvvvvv
+\ BASE @ \ -- BASE
+\ #10 BASE !
+\ CR ." "
+\ INI_THREAD @ DUP
+\ 1 = IF DROP ." monothread"
+\ ELSE . ." threads"
+\ THEN ." vocabularies"
+\ BASE ! \ --
+\ \ ^^^^^^^^ may be skipped ^^^^^^^^
+
+CR ." " \
+CONTEXT @ \ -- VOC_BODY
+\ MOVE all threads of VOC_BODY in PAD
+ PAD INI_THREAD @ DUP + \ -- VOC_BODY PAD THREAD*2
+ MOVE \
+ BEGIN \ --
+ 0 DUP \ -- ptr MAX
+\ select the MAX of NFA in threads
+ INI_THREAD @ DUP + 0 DO \ ptr = threads*2
+ DUP I PAD + @ \ -- ptr MAX MAX NFAx
+ U< IF
+ DROP DROP I DUP PAD + @ \ -- ptr MAX if MAX U< NFAx replace adr and MAX
+ THEN \
+ 2 +LOOP \ -- ptr MAX
+ ?DUP \ -- ptr MAX MAX ( or -- ptr 0) max NFA = 0 ? end of vocabulary ?
+ WHILE \ -- ptr MAX
+\ replace it by its LFA
+ DUP \ -- ptr MAX MAX
+ 2 - @ \ -- ptr MAX [LFA]
+ ROT \ -- MAX [LFA] ptr
+ PAD + \ -- MAX [LFA] thread
+ ! \ -- MAX
+\ type it in 16 chars format
+ DUP \ -- MAX MAX
+ COUNT $7F AND \ -- MAX addr count
+ TYPE \ -- MAX
+ C@ $0F AND \ --
+ $10 SWAP - SPACES \ --
+\ search next MAX of NFA
+ REPEAT \ -- ptr
+ DROP \ --
+;
+[THEN]
+ \
+
+[UNDEFINED] MAX [IF] \ MAX and MIN are defined in {ANS_COMP}
+ CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+ BW1 ADD #2,PSP
+ MOV @IP+,PC
+ ENDCODE
+ \
+
+ CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+ FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+[THEN]
+ \
+
+
+[UNDEFINED] U.R [IF] \ MAX and MIN are defined in {ANS_COMP}
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+>R <# 0 # #S #>
+R> OVER - 0 MAX SPACES TYPE
+;
+[THEN]
+ \
+
+[UNDEFINED] DUMP [IF] \
+\ https://forth-standard.org/standard/tools/DUMP
+: DUMP \ adr n -- dump memory
+ BASE @ >R $10 BASE !
+ SWAP $FFF0 AND SWAP
+ OVER + SWAP
+ DO CR \ generate line
+ I 7 U.R SPACE \ generate address
+ I $10 + I \ display 16 bytes
+ DO I C@ 3 U.R LOOP
+ SPACE SPACE
+ I $10 + I \ display 16 chars
+ DO I C@ $7E MIN BL MAX EMIT LOOP
+ $10 +LOOP
+ R> BASE !
+;
+[THEN]
+ \
+
+[THEN]
+ECHO
+ ; added : ? .S .RS WORDS U.R MAX MIN DUMP
+ ; v--- use backspaces before hit "CR" to decrease application protection level
+PWR_HERE RST_HERE
\ No newline at end of file
--- /dev/null
+\ name : MSP430FR5xxx_I2CF_Soft_Master.asm
+
+WIPE
+\ NOECHO
+
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ version 2.0 2015-07-30
+\
+\
+\ -------------------------------------------------------------------------------------------------------------------\
+\ I2CF Soft MASTER, FAST MODE, 8MHz
+\ -------------------------------------------------------------------------------------------------------------------\
+
+\ ======================================================================================================
+\ ======================================================================================================
+
+\ ### ##### ##### ###### ##### # #
+\ # # # # # # # # #### ###### ##### ## ## ## #### ##### ###### #####
+\ # # # # # # # # # # # # # # # # # # # #
+\ # ##### # ##### ##### # # ##### # # # # # # #### # ##### # #
+\ # # # # # # # # # # # ###### # # # #####
+\ # # # # # # # # # # # # # # # # # # # # #
+\ ### ####### ##### # ##### #### # # # # # # #### # ###### # #
+
+\ ======================================================================================================
+\ ======================================================================================================
+
+\ use Px.0 to Px.3 pins as SCL and SDA pins to use immediate instruction in one byte (#1,#2,#4,#8)
+
+\ tested with P1.6 SDA, P1.7 SCL :
+\ Start + Adr + Write 3 bytes + Stop + Start + adr + read 2 bytes + stop = 300us ==> 210 kHz
+\ See MSP430FR5xxx_I2CF_Soft_Master.png
+
+VARIABLE I2CS_ADR \ low(I2CS_ADR) = slave I2C address with RW flag, high(I2CS_ADR) = RX buffer,data0
+2 ALLOT \ data1,data2
+VARIABLE I2CM_BUF \ low(I2CM_BUF) = RX or TX lentgh, high(I2CM_BUF) = TX buffer,data0
+2 ALLOT \ data1,data2
+ \
+
+\ ----------------------------------\
+AMS I2C_MTX \ MASTER TX \ shared code for address and TX data
+\ ----------------------------------\
+BEGIN \
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #MSDA,&I2CSM_DIR \ 4 l yes : SDA as input ==> SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #MSDA,&I2CSM_DIR \ 4 l no : SDA as output ==> SDA low
+ THEN \ l _
+ BIC.B #MSCL,&I2CSM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \ 14/16~l
+ BIT.B #MSCL,&I2CSM_IN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h _
+ BIS.B #MSCL,&I2CSM_DIR \ 4 h v_ SCL as output : force SCL low
+ SUB #1,W \ 1 l count of bits
+0= UNTIL \ 2 l
+BIC.B #MSDA,&I2CSM_DIR \ 5 l _ SDA as input : release SDA high to prepare read Ack/Nack
+MOV @RSP+,PC
+ENDASM \
+ \
+
+
+\ ==================================\
+ASM I2C_M \
+\ ==================================\
+\ \ in I2CS_ADR/I2CM_BUF as RX/TX buffer requested by I2CS_ADR(0(0))
+\ \ I2CS_ADR(0) = I2C_Slave_addr&R/w
+\ \ I2CM_BUF(0) = TX/RX count of datas
+\ \ I2CM_BUF(0) = 0 ==> send only I2C address
+\ \ used S BUF ptr
+\ \ T datas countdown
+\ \ W bits countdown
+\ \ X data
+\ \ out I2CSLA_ADR & (R/W) unCHNGd
+\ \ S = BUF PTR pointing on first data not exCHNGd
+\ \ T = count+1 of TX/RX datas exCHNGd
+\ \ I2CS_ADR(0) = unCHNGd
+\ \ I2CM_BUF(0) = count of data not exCHNGd (normally = 0)
+\ \ I2CM_BUF(0) = -1 <==> Nack on address
+\ ----------------------------------\
+\ I2C_Master_Start_Cond: \ here, SDA and SCL are in idle state
+\ ----------------------------------\
+BIS.B #MSDA,&I2CSM_DIR \ 4 l force SDA as output (low)
+MOV #I2CM_BUF,W \ 2 h W=buffer out
+MOV.B @W+,T \ 2 h T=datas countdown
+MOV #I2CS_ADR,S \ 2 h S=buffer in
+MOV.B @S+,X \ 2 h X=Slave address to TX
+BIT.B #1,X \ 1 h test I2C R/w flag
+0= IF \ 2 h if write
+ MOV W,S \ 2 h S= buffer out ptr
+THEN \ S= buffer ptr
+BIS.B #MSCL,&I2CSM_DIR \ 4 h force SCL as output (low)
+\ ----------------------------------\
+\ I2C_Master_Start_EndOf: \
+\ ----------------------------------\
+\ I2C_Master_Send_address \ may be SCL is held low by slave
+\ ----------------------------------\
+ADD #1,T \ 1 l to add address in count
+MOV #8,W \ 1 l prepare 8 bit Master writing
+CALL #I2C_MTX \ 21 l to send address
+\ ----------------------------------\
+\ I2C_Master_Loop_Data \
+\ ----------------------------------\
+BEGIN \ 4 l here ack/nack is received/transmitted
+\ --------------------------------\ l
+\ Master TX/RX ACK/NACK \
+\ --------------------------------\ l _
+ BIC.B #MSCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #MSCL,&I2CSM_IN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h
+ BIT.B #MSDA,&I2CSM_IN \ 3 h _ get SDA
+ BIS.B #MSCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+\ --------------------------------\ l
+\ I2C_Master_Loop_Data \
+\ --------------------------------\
+ 0<> IF BIS #Z,SR \ 5 l if Nack (TX), force Z=1 ==> StopCond
+ ELSE SUB.B #1,T \ 3 l else dec count
+ THEN \ l
+\ --------------------------------\
+\ I2C_Master_CheckCountDown \ count=0 (TX) or Nack received
+\ --------------------------------\
+ 0= IF \ 2 l send stop
+\ ----------------------------\
+\ Send Stop \
+\ ----------------------------\ _
+ BIS.B #MSDA,&I2CSM_DIR \ 4 l v_ SDA as output ==> SDA low
+ SUB.B T,&I2CM_BUF \ 4 l _ refresh buffer length and reach tSU:STO
+ BIC.B #MSCL,&I2CSM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #MSCL,&I2CSM_IN \ 3 h SCL released ?
+ 0<> UNTIL \ 2 h
+ BIC.B #MSDA,&I2CSM_DIR \ 4 h _^ SDA as input ==> SDA high with pull up resistor
+ MOV @RSP+,PC \ RET ====>
+ THEN \
+ MOV.B #8,W \ 1 l prepare 8 bits transaction
+ BIT.B #1,&I2CS_ADR \ 3 l I2C_Master Read/write bit test
+ 0= IF \ 2 l write flag test
+\ ============================\
+\ I2C_Master_TX \
+\ ============================\
+ MOV.B @S+,X \ 2 l next byte to transmit
+ CALL #I2C_MTX \ l to send data
+ ELSE \ l
+\ ============================\
+\ I2C_Master_RX: \ here, SDA is indetermined, SCL is strech low by master
+\ ============================\
+ BIC.B #MSDA,&I2CSM_DIR \ 5 l After ACK we must release SDA
+ BEGIN \
+\ ------------------------\ _
+\ send bit \ SCL _| |_
+\ ------------------------\ _
+ BIC.B #MSCL,&I2CSM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \ 14/16~l
+ BIT.B #MSCL,&I2CSM_IN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h
+ BIT.B #MSDA,&I2CSM_IN \ 4 h _ get SDA
+ BIS.B #MSCL,&I2CSM_DIR \ 4 h v_ SCL as output : force SCL low 13~
+ ADDC.B X,X \ 1 l C <-- X <--- C
+ SUB #1,W \ 1 l count of bits
+ 0= UNTIL \ 2 l
+ MOV.B X,0(S) \ 3 l store byte in buffer
+ ADD #1,S \ 1 l
+\ ----------------------------\
+\ Compute Ack Or Nack \ here, SDA is released by slave, SCL is strech low by master
+\ ----------------------------\
+ CMP.B #1,T \
+ 0<> IF \ 2 l
+ BIS.B #MSDA,&I2CSM_DIR \ 5 l yes : send Ack
+ THEN \
+ THEN \
+AGAIN \ 2 l
+ENDASM \
+ \
+
+
+
+\ ==================================\
+\ reduced version for TX only
+\ ==================================\
+VARIABLE I2CS_ADR \ low(I2CS_ADR) = slave I2C address with RW flag
+VARIABLE I2CM_BUF \ low(I2CM_BUF) = RX or TX lentgh, high(I2CM_BUF) = TX buffer,data0
+2 ALLOT \ data1,data2
+ \
+\ ==================================\
+ASM I2C_M_TX \
+\ ==================================\
+\ \ in I2CS_ADR/I2CM_BUF as RX/TX buffer requested by I2CS_ADR(0(0))
+\ \ I2CS_ADR(0) = I2C_Slave_addr&R/w
+\ \ I2CM_BUF(0) = TX/RX count of datas
+\ \ I2CM_BUF(0) = 0 ==> send only I2C address
+\ \ used S BUF ptr
+\ \ T datas countdown
+\ \ W bits countdown
+\ \ X data
+\ \ out I2CSLA_ADR & (R/W) unCHNGd
+\ \ S = BUF PTR pointing on first data not exCHNGd
+\ \ T = count+1 of TX/RX datas exCHNGd
+\ \ I2CS_ADR(0) = unCHNGd
+\ \ I2CM_BUF(0) = count of data not exCHNGd (normally = 0)
+\ \ I2CM_BUF(0) = -1 <==> Nack on address
+\ ----------------------------------\
+\ I2C_Master_Start_Cond: \ here, SDA and SCL are in idle state
+\ ----------------------------------\
+BIS.B #MSDA,&PI2CMDIR \ 4 l force SDA as output (low)
+MOV #I2CM_BUF,W \ 2 h W=buffer out
+MOV.B @W+,T \ 2 h T=datas countdown
+MOV.B &I2CS_ADR,X \ 3 h X=Slave address to TX
+BIS.B #MSCL,&PI2CMDIR \ 4 h force SCL as output (low)
+\ ----------------------------------\
+\ I2C_Master_Start_EndOf: \
+\ ----------------------------------\
+\ I2C_Master_Send_address \ may be SCL is held low by slave
+\ ----------------------------------\
+ADD #1,T \ 1 l to add address in count
+\ ----------------------------------\
+\ I2C_Master_Loop_Data \
+\ ----------------------------------\
+BEGIN \ 2 l
+\ --------------------------------\
+\ I2C_MTX \
+\ --------------------------------\
+ MOV #8,W \ 1 l prepare 8 bit Master writing
+ BEGIN \
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #MSDA,&PI2CMDIR \ 4 l yes : SDA as input ==> SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #MSDA,&PI2CMDIR \ 4 l no : SDA as output ==> SDA low
+ THEN \ l
+ BIC.B #MSCL,&PI2CMDIR \ 4 l _^ release SCL (high)
+ BEGIN \ 14/16~l
+ BIT.B #MSCL,&PI2CMIN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h _
+ BIS.B #MSCL,&PI2CMDIR \ 4 h v_ SCL as output : force SCL low
+ SUB #1,W \ 1 l count of bits
+ 0= UNTIL \ 2 l
+ BIC.B #MSDA,&PI2CMDIR \ 5 l _ SDA as input : release SDA high to prepare read Ack/Nack
+\ --------------------------------\ l
+\ Master TX/RX ACK/NACK \
+\ --------------------------------\ l _
+ BIC.B #MSCL,&PI2CMDIR \ 3 l _^ P1DIR.3 release SCL (high)
+ BEGIN \
+ BIT.B #MSCL,&PI2CMIN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h
+ BIT.B #MSDA,&PI2CMIN \ 3 h _ get SDA
+ BIS.B #MSCL,&PI2CMDIR \ 3 h v_ SCL as output : force SCL low
+\ --------------------------------\ l
+ 0<> IF BIS #Z,SR \ 5 l if Nack (TX), force Z=1 ==> StopCond
+ ELSE SUB.B #1,T \ 3 l else dec count
+ THEN \ l
+\ --------------------------------\
+\ I2C_Master_CheckCountDown \ count=0 (TX) or Nack received
+\ --------------------------------\
+ 0= IF \ 2 l send stop
+\ ----------------------------\
+\ Send Stop \
+\ ----------------------------\ _
+ BIS.B #MSDA,&PI2CMDIR \ 4 l v_ SDA as output ==> SDA low
+ SUB.B T,&I2CM_BUF \ 4 l _ refresh buffer length and reach tSU:STO
+ BIC.B #MSCL,&PI2CMDIR \ 4 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #MSCL,&PI2CMIN \ 3 h SCL released ?
+ 0<> UNTIL \ 2 h
+ BIC.B #MSDA,&PI2CMDIR \ 4 h _^ SDA as input ==> SDA high with pull up resistor
+ MOV @RSP+,PC \ RET ====>
+ THEN \
+ MOV.B @S+,X \ 2 l next byte to transmit
+AGAIN \ 2 l
+ENDASM \ 93 words
+ \
+
+
+
+\ ------------------------------\
+CODE START \
+\ ------------------------------\
+\ init PORTA (P2:P1) (complement) when reset occurs all I/O are set in input with resistors pullup
+BIC.B #M_BUS,&I2CSM_OUT \ preset SDA + SCL output low
+BIC.B #M_BUS,&I2CSM_REN \ SDA + SCL pullup/down disable
+\ ------------------------------\
+LO2HI
+." \ type stop to stop :-)"
+LIT recurse is WARM \ insert this starting routine between COLD and WARM...
+(WARM) \ ...and continue with (WARM)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+RST_HERE \ set here the reset dictionnary
+
+\ ---------------------------------------------------------------------------------------------------------------------\
+\ SCL clock generation, timing, and test of data(s) number are made by I2C_Master.
+\ slave can strech SCL low after Start Condition and after any bit.
+\
+\ address Ack/Nack is generated by the slave on SDA line (released by the master)
+\ Two groups of eight addresses (000xxxy and 1111xxxy) are not allowed (reserved)
+\ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
+\ data Ack/Nack are generated by the receiver (master or slave) on SDA line
+\ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
+\ Stop or restart conditions must be generated by master after a Nack bit.
+\ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions.
+\
+\
+\ first byte = address + R/W flag | byte data (one, for example)
+\ __ _____ _____ _..._ _____ __R__ _NAK_ _____ _____ _..._ _____ _____ _NAK_ _
+\ SDA \____/_MSB_X_____X_..._X_LSB_X__W__x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X___/
+\ _____ _ _ _ _ _ _ _ _ _ _ ___
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |SSL |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |stoP Condition
+\
+\ first byte = address + R/W flag | byte data (one, for example)
+\ __ _____ _____ _..._ _____ __R__ _NAK_ _____ _____ _..._ _____ _____ _NAK_ ___
+\ SDA \____/_MSB_X_____X_..._X_LSB_X__W__x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X \____...
+\ _____ _ _ _ _ _ _ _ _ _ _ ____
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |SSL |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |reStart Condition
+\
+\ SSL : Slave can strech SCL low
+\ tHIGH : SCL high time
+\ tLOW : SCL low time
+\ tBUF : SDA high time between Stop and Start conditions
+\ tHD:STA : Start_Condition SCL high time after SDA is low
+\ tSU:STO : Stop_Condition SCL high time before SDA rise
+\ tSU:STA : Start_Condition SCL high time before SDA fall
+\ tHD:DAT : SDA data change time after SCL is low
+\ the SDA line must be strobe just after SCL is high
+\ the SDA data must be change just after SCL is low
+\ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
+\ tLOW = tSU:STA = tBUF = 4,7µs
+\ tHD:DAT <= 3,45 µs
+\ -------------------------------------------------------------------------------------------------------------------\
--- /dev/null
+\ name : msp430FR5xxx_I2CF_Soft_MultiMaster.asm
+
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ I2C MASTER Standard Mode software driver without interrupt, with detection collision
+\ Target: MSP430FR5xxx, tested @ 8,16,24 MHz and adjusted @ 16,24 MHz
+\ SDA = P1.2, SCL = P1.3, with 3k3 pullup resistors
+
+\ version 1.0 2015-03-24
+
+WIPE
+\ ==============================================================================================================
+\ ==============================================================================================================
+
+\ ### ##### ##### ###### ##### # # # #
+\ # # # # # # # # #### ###### ##### ## ## ## ## ## #### ##### ###### #####
+\ # # # # # # # # # # # # # # # # # # # # # # # #
+\ # ##### # ##### ##### # # ##### # # # # # # # # # #### # ##### # #
+\ # # # # # # # # # # # # # ###### # # # #####
+\ # # # # # # # # # # # # # # # # # # # # # # #
+\ ### ####### ##### # ##### #### # # # # # # # # #### # ###### # #
+
+\ ==============================================================================================================
+\ ==============================================================================================================
+
+\ use Px.0 to Px.3 for good timing at 8 MHz
+
+\ tested with P1.6 SDA, P1.7 SCL :
+\ Start + Adr + Write 3 bytes + Stop + Start + adr + read 2 bytes + stop = 310us ==> 200 kHz
+\ See MSP430FR5xxx_I2CF_Soft_MultiMaster.png
+
+VARIABLE I2CS_ADR \ low(I2CS_ADR) = slave I2C address with RW flag, high(I2CS_ADR) = RX buffer,data0
+2 ALLOT \ data1,data2
+VARIABLE I2CM_BUF \ low(I2CM_BUF) = RX or TX lentgh, high(I2CM_BUF) = TX buffer,data0
+2 ALLOT \ data1,data2
+ \
+
+\ ==================================\
+ASM I2C_MM \ soft I2C_MultiMaster driver
+\ ==================================\
+\ \ in : I2CS_ADR pointer
+\ \ : I2CM_BUF pointer
+\ \ used: S BUF_PTR
+\ \ T count of I2C datas exchanged
+\ \ W count of bits
+\ \ X data
+\ \ Y BUF_ORG
+\ \ SR(10) collision flag
+\ \ out : I2CS_ADR(0) unchanged
+\ \ I2CM_BUF(0) = count of data not exchanged (normally = 0)
+\ \ I2CM_BUF(0) = -1 <==> Nack on address
+\ ----------------------------------\
+\ I2CMM_Stop_UCBxI2CSlave \ if SDA SCL of I2C_MultiMaster are hard wired onto SDA SCL of I2C_Slave under interrupt...
+\ ----------------------------------\
+\ BIS #1,&UCB0CTLW0 \ set eUSCI_B0 in reset state, reset StartCond int in UCB0IFG
+\ BIC.B #SMM_BUS,&PI2CMSEL1 \ disable I2C I/O
+\ ----------------------------------\
+\ I2C_MR_DC_listenBeforeStart: \ test if SCL & SDA lines are idle (high)
+\ ----------------------------------\
+BEGIN \
+ BIC.B #SMM_BUS,&I2CSMM_DIR \ SDA & SCL pins as input
+ BIC.B #SMM_BUS,&I2CSMM_OUT \ preset output LOW for SDA & SCL pins
+ MOV #2,T \ I2C_MR_DC_Wait_Start_Loop = 3 µs @ 8 MHz
+ BEGIN \ 15~loop
+ BEGIN \
+ BEGIN \
+ BIT.B #SMMSCL,&I2CSMM_IN \ 4 SCL high ?
+ 0<> UNTIL \ 2
+ BIT.B #SMMSDA,&I2CSMM_IN \ 4 SDA high ?
+ 0<> UNTIL \ 2
+ SUB #1,T \ 1
+ 0= UNTIL \ 2 here the I2C bus is idle
+\ --------------------------------\
+\ I2C_Master_Start_Cond: \ here, SDA and SCL are in idle state
+\ --------------------------------\
+ BIS.B #SMMSDA,&I2CSMM_DIR \ 4 h force SDA output (low)
+ MOV #I2CS_ADR,S \ 2 l
+ MOV.B @S+,X \ 3 l X = slave address, S = RX buffer
+ MOV #I2CM_BUF,W \ 2 l
+ MOV.B @W+,T \ 2 l T = count of datas, W = TX buffer
+ ADD.B #1,T \ 1 l to add address in count
+ BIT.B #1,X \ 1 l test I2C R/w flag
+ 0= IF \ 2 l write flag ?
+ MOV W,S \ 3 l TX buffer
+ THEN \
+ BIS.B #SMMSCL,&I2CSMM_DIR \ 4 h force SCL output (low)
+\ --------------------------------\ l
+\ I2C_Master_Start_EndOf: \ l
+\ --------------------------------\
+\ I2C_Master_Send_address \ l SCL
+\ --------------------------------\
+ BIC #UF2,SR \ 2 reset detection collision SR(10) flag
+ MOV #8,W \ 1 l 8 bits TX
+ BEGIN \
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #SMMSDA,&I2CSMM_DIR \ 4 l yes : releas SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #SMMSDA,&I2CSMM_DIR \ 4 l no : set as output ==> SDA low
+ THEN \ l _
+ BIC.B #SMMSCL,&I2CSMM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #SMMSCL,&I2CSMM_IN \ 4 h test if SCL is released
+ 0<> UNTIL \ 2 h
+ MOV.B &I2CSMM_IN,Y \ 3 h _ get SDA in Y
+ BIS.B #SMMSCL,&I2CSMM_DIR \ 4 h v_ force SCL low
+\ ----------------------------\
+\ collision detection \ l
+\ ----------------------------\
+ XOR.B &I2CSMM_DIR,Y \ 3 normal : IN(SMMSDA) XOR DIR(SMMSDA) = 1
+ BIT.B #SMMSDA,Y \ 2 collision : IN(SMMSDA=0) XOR DIR(SMMSDA=0) = 0
+ 0= IF BIS #$0402,SR \ 6 set collision detection flag SR(10) and set Z=1 to force end of loop
+ ELSE SUB #1,W \ 3 dec count of bits
+ THEN \
+ 0= UNTIL \ 2
+ BIT #UF2,SR \ 2 collision ?
+0= UNTIL \ 2 loop back if collision during send address
+BIC.B #SMMSDA,&I2CSMM_DIR \ 5 release SDA high before 9th bit
+\ ----------------------------------\
+\ I2C_Master_Loop \
+\ ----------------------------------\
+BEGIN \ 4 l
+\ --------------------------------\ l
+\ Master TX/RX ACK/NACK \
+\ --------------------------------\ l _
+ BIC.B #SMMSCL,&I2CSMM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #SMMSCL,&I2CSMM_IN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h
+ BIT.B #SMMSDA,&I2CSMM_IN \ 3 h _ get SDA
+ BIS.B #SMMSCL,&I2CSMM_DIR \ 3 h v_ force SCL low
+\ --------------------------------\ 4 l here ack/nack is received/transmitted
+\ I2C_Master_Loop_Data \
+\ --------------------------------\
+ 0<> IF BIS #Z,SR \ 5 if Nack (TX), force Z+1 ==> StopCond
+ ELSE SUB.B #1,T \ 3 else dec count
+ THEN \
+\ --------------------------------\
+\ I2C_Master_CheckCountDown \ count=0 or Nack received
+\ --------------------------------\
+ 0= IF \ count reached or Nack
+\ ----------------------------\
+\ I2C_Master_StopCond \
+\ ----------------------------\ _
+ BIS.B #SMMSDA,&I2CSMM_DIR \ 4 l v_ force SDA low
+ SUB.B T,&I2CM_BUF \ 4 l refresh buffer length and reach tSU:STO
+ BIC.B #SMMSCL,&I2CSMM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #SMMSCL,&I2CSMM_IN \ 3 h SCL released ?
+ 0<> UNTIL \ 2 h _
+ BIC.B #SMMSDA,&I2CSMM_DIR \ _| as input ==> SDA high with the hard wired pull up resistor
+\ ----------------------------\
+\ I2C_Master_Endof \
+\ ----------------------------\
+\ Restart I2C_Slave_Int \ if any
+\ ----------------------------\
+\ MOV #4,&UCB0IE \ enable StartCond interrupt in UCB0IE register
+\ BIC #1,&UCB0CTLW0 \ restart eUSCI_B
+\ BIS.B #SMM_BUS,&I2CSMM_SEL1 \ reenable I2C I/O
+\ ----------------------------\
+ MOV @RSP+,PC \ ====> out
+\ ----------------------------\
+ THEN \
+ MOV.B #8,W \ 1 l prepare 8 bits transaction
+ BIT #1,&I2CS_ADR \ 3 l I2C_Master Read/write bit test
+ 0= IF \ 2 l write flag test
+\ ----------------------------\
+\ I2C Master write \
+\ ----------------------------\
+ MOV.B @S+,X \ 2 l X = TX data
+ BEGIN \
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #SMMSDA,&I2CSMM_DIR \ 4 l yes : release SDA (high because pull up resistor)
+ ELSE \ 2 l
+ BIS.B #SMMSDA,&I2CSMM_DIR \ 4 l no : force SDA low
+ THEN \ l _
+ BIC.B #SMMSCL,&I2CSMM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #SMMSCL,&I2CSMM_IN \ 4 h test if SCL is released
+ 0<> UNTIL \ 2 h _
+ BIS.B #SMMSCL,&I2CSMM_DIR \ 4 h v_ force SCL low
+ SUB #1,W \ 1 l count of bits
+ 0= UNTIL \ 2 l
+ BIC.B #SMMSDA,&I2CSMM_DIR \ 4 l release SDA high
+ ELSE \ 2 l
+\ ============================\
+\ I2C_Master_RX: \ here, SDA is indetermined, SCL is strech low by master
+\ ============================\
+ BIC.B #SMMSDA,&I2CSMM_DIR \ 5 l _ After ACK we must release SDA
+ BEGIN \
+\ ------------------------\ _
+\ send bit \ SCL _| |_
+\ ------------------------\ _
+ BIC.B #SMMSCL,&I2CSMM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #SMMSCL,&I2CSMM_IN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h
+ BIT.B #SMMSDA,&I2CSMM_IN \ 3 h _ get SDA
+ BIS.B #SMMSCL,&I2CSMM_DIR \ 3 h v_ force SCL low
+ ADDC.B X,X \ 1 l C <-- X <--- C
+ SUB #1,W \ 1 l count of bits
+ 0= UNTIL \ 2 l
+ MOV.B X,0(S) \ 3 l store byte @ BUF_PTR
+ ADD #1,S \ 1 l
+\ ----------------------------\
+\ I2C_MSendAckOrNack \ here, SDA is released by slave, SCL is strech low by master
+\ ----------------------------\
+ CMP.B #1,T \ bytes count = 1 ?
+ 0<> IF \ 2
+ BIS.B #SMMSDA,&I2CSMM_DIR \ 4 l prepare send Ack if byte count <> 1
+ THEN \
+ THEN \
+AGAIN \ 2 l
+ENDASM \
+ \
+
+\ ------------------------------\
+CODE START \
+\ ------------------------------\
+\ init PORTA (P2:P1) (complement) when reset occurs all I/O are set in input with resistors pullup
+BIC.B #SMM_BUS,&I2CSMM_OUT \ preset SDA + SCL output low
+BIC.B #SMM_BUS,&I2CSMM_REN \ SDA + SCL pullup/down disable
+\ ------------------------------\
+LO2HI
+." Type STOP to stop :-)"
+LIT RECURSE IS WARM \ insert this routine between COLD and WARM...
+(WARM) ; \ ...and continue with WARM
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+RST_HERE
+
+
+\ ---------------------------------------------------------------------------------------------------------------------\
+\ SCL clock generation, timing, and test of data(s) number are made by I2C_Master.
+\ slave can strech SCL low after Start Condition and after any bit.
+
+\ address Ack/Nack is generated by the slave on SDA line (released by the master)
+\ Two groups of eight addresses (000xxxy and 1111xxxy) are not allowed (reserved)
+\ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
+\ data Ack/Nack are generated by the receiver (master or slave) on SDA line
+\ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
+\ Stop or restart conditions must be generated by master after a Nack bit.
+\ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK _
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X___/
+\ _____ _ _ _ _ _ _ _ _ _ _ ___
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |stoP Condition
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK ___
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X \____...
+\ _____ _ _ _ _ _ _ _ _ _ _ ____
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |reStart Condition
+\
+\ tHIGH : SCL high time
+\ tLOW : SCL low time
+\ tBUF : SDA high time between Stop and Start conditions
+\ tHD:STA : Start_Condition SCL high time after SDA is low
+\ tSU:STO : Stop_Condition SCL high time before SDA rise
+\ tSU:STA : Start_Condition SCL high time before SDA fall
+\ tHD:DAT : SDA data change time after SCL is low
+\ the SDA line must be strobe just after SCL is high
+\ the SDA data must be change just after SCL is low
+\ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
+\ tLOW = tSU:STA = tBUF = 4,7µs
+\ tHD:DAT <= 3,45 µs
+\ -------------------------------------------------------------------------------------------------------------------\
--- /dev/null
+\ name : msp430FR5xxx_I2C_Master.asm
+\
+\ Copyright (C) <2016> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY; without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+\
+\
+\ I2C MASTER Standard Mode software driver without interrupt
+\ Target: MSP-EXP430FR5969 @ 8,16MHz
+\ version 1.1 2016-03-18
+\
+\ ---------------------------------------------------------------------------------------------------------------------;
+\ SCL clock generation, timing, and test of data(s) number are made by I2C_Master.
+\ slave can strech SCL low after Start Condition and after any bit.
+\
+\ address Ack/Nack is generated by the slave on SDA line (released by the master)
+\ Two groups of eight addresses (000$xxy and 1111xxxy) are not allowed (reserved)
+\ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
+\ data Ack/Nack are generated by the receiver (master or slave) on SDA line
+\ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
+\ Stop or restart conditions must be generated by master after a Nack bit.
+\ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK _
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X___/
+\ _____ _ _ _ _ _ _ _ _ _ _ ___
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |stoP Condition
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK ___
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X \____...
+\ _____ _ _ _ _ _ _ _ _ _ _ ____
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |reStart Condition
+\
+\ tHIGH : SCL high time
+\ tLOW : SCL low time
+\ tBUF : SDA high time between Stop and Start conditions
+\ tHD:STA : Start_Condition SCL high time after SDA is low
+\ tSU:STO : Stop_Condition SCL high time before SDA rise
+\ tSU:STA : Start_Condition SCL high time before SDA fall
+\ tHD:DAT : SDA data change time after SCL is low
+\ the SDA line must be strobe just after SCL is high
+\ the SDA data must be change just after SCL is low
+\ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
+\ tLOW = tSU:STA = tBUF = 4,7µs
+\ tHD:DAT <= 3,45 µs
+\
+\ fast mode (up to 400 kHz) : tHIGH = tHD:STA = tSU:STO = 0,6µs
+\ tLOW = tSU:STA = tBUF = 1,3µs
+\ tHD:DAT <= 0,9 µs
+\ -------------------------------------------------------------------------------------------------------------------;
+
+\ =================================================================
+\ =================================================================
+
+\ ### ##### ##### # #
+\ # # # # # ## ## ## #### ##### ###### #####
+\ # # # # # # # # # # # # # #
+\ # ##### # # # # # # #### # ##### # #
+\ # # # # # ###### # # # #####
+\ # # # # # # # # # # # # # #
+\ ### ####### ##### # # # # #### # ###### # #
+
+\ =================================================================
+\ =================================================================
+
+\ tested with P1.6 SDA, P1.7 SCL :
+\ Start + Adr + Write 3 bytes + Stop + Start + adr + read 2 bytes + stop = 204us ==> 308 kHz (STOP=10us)
+\ See MSP430FR5xxx_I2C_Master.png
+
+
+
+VARIABLE I2CS_ADR \ low(I2CS_ADR) = slave I2C address with RW flag, high(I2CS_ADR) = RX buffer,data0
+2 ALLOT \ data1,data2
+VARIABLE I2CM_BUF \ low(I2CM_BUF) = RX or TX lentgh, high(I2CM_BUF) = TX buffer,data0
+2 ALLOT \ data1,data2
+ \
+
+
+
+\ ----------------------------------\
+ASM I2C_M \
+\ ----------------------------------\
+\ \ in I2CS_ADR/I2CM_BUF as RX/TX buffer requested by I2CS_ADR(0(0))
+\ \ I2CS_ADR(0) = I2C_Slave_addr&R/w
+\ \ I2CM_BUF(0) = TX/RX count of datas
+\ \ I2CM_BUF(0) = 0 ==> send only I2C address
+\ \ used S = BUF ptr
+\ \ T
+\ \ out I2CSLA_ADR & (R/W) unCHNGd
+\ \ S = BUF PTR pointing on first data not exCHNGd
+\ \ T = count of TX/RX datas exCHNGd
+\ \ T = -1 ==> NACK on address
+\ \ I2CS_ADR(0) = unCHNGd
+\ \ I2CM_BUF(0) = unCHNGd
+BIS #1,&UCB0CTLW0 \ SWRST
+MOV #$0FD3,&UCB0CTLW0 \ master mode + UCTR + START + SWRST, IFG=IE=0
+MOV #$00C8,&UCB0CTLW1 \ set automatic stop (count byte reached)
+MOV #$14,&UCB0BRW \ baudrate = SMCLK/20 = 400 kHz @8MHz ; 340 kHz measured
+MOV #I2CM_BUF,S \ count & TX buf
+MOV.B @S+,&UCB0TBCNT \
+CMP.B #0,&UCB0TBCNT \
+0= IF \ count = 0
+ BIS #4,&UCB0CTLW0 \ add Stop cmd to Start cmd ==> Master send only I2C address
+THEN
+MOV #I2CS_ADR,T \ I2Cadr & RX buf
+MOV.B @T+,&UCB0I2CSA \ UCB0I2CSA = slave_address & R/w bit
+RRA &UCB0I2CSA \ UCB0I2CSA = slave_address, C flag = R/w flag
+U>= IF \ C flag = 1
+ MOV T,S \ Master read : S = RX buffer
+ BIC #$10,&UCB0CTLW0 \ UCB0CTLW0 <-- UCTR=0
+THEN \
+\ ------------------------------ \
+\ Start \
+\ ------------------------------ \
+MOV.B #-1,T \ T=-1
+BIC #1,&UCB0CTLW0 \ UCB0CTLW0 : clear SWRST, start I2C MASTER
+BIT.B #1,&I2CS_ADR \ R/W test
+0= IF \
+\ ---------------------------- \
+\ MASTER TX \
+\ ---------------------------- \
+ BEGIN \
+ MOV.B &UCBCNT0,T \ store count of byte
+ BIT #8,&UCB0IFG \ test UCSTPIFG
+ 0<> IF \
+ MOV @RSP+,PC \ end of I2C_M TX driver
+ THEN \
+ BIT #$20,&UCB0IFG \ test UCNACKIFG
+ 0<> IF \
+ BIS #4,&UCB0CTLW0 \ generate stop bit
+ MOV @RSP+,PC \ end of I2C_M TX driver
+ THEN \
+ BIT #2,&UCB0IFG \ test UCTXIFG0
+ 0<> IF \
+ MOV.B @S+,&UCB0TXBUF \ load data into UCB0TXBUF
+ THEN \
+ AGAIN \
+THEN \
+\ ------------------------------ \
+\ MASTER RX \
+\ ------------------------------ \
+BEGIN \ of Master RX
+ MOV.B &UCBCNT0,T \ store count of byte
+ BIT #8,&UCB0IFG \ test UCSTPIFG
+ 0<> IF \
+ MOV @RSP+,PC \ end of I2C_M RX driver
+ THEN \
+ BIT #1,&UCB0IFG \ test UCRXIFG0
+ 0<> IF \
+ MOV.B &UCB0RXBUF,0(S) \ load data from UCB0RXBUF
+ ADD #1,S \
+ THEN \
+AGAIN \
+ENDASM \ 62 words + 9 init words
+ \
+
+\ ------------------------------\
+CODE START \ init
+\ ------------------------------\
+\ init I2C_Master \
+\ ------------------------------\
+\ %0000 1111 1101 0011 $640 = $0FD3
+\ - UCMM = 1 : multi master mode
+\ - UCMST = 1 : I2C_Master
+\ -- UCMODE = %11 = I2C
+\ _ USYNC=1 (always 1)
+\ -- UCSSEL=SMCLK=8MHz
+\ - UCTXACK=0 not auto ACK slave address
+\ - UCTR=1/0 : TX/RX modes
+\ - UCTXSTP
+\ - UCTXSTT send start
+\ - UCSWRST=1
+\ ------------------------------\
+\ %0000 0000 1100 1000 $642 = $00C8
+\ - UCETXINT=0 : UCTXIFG0 set address match UCxI2COAx and TX mode
+\ -- UCCLTO=%11 : SCL low time out = 34 ms
+\ - UCSWACK=1 : UCTXACK must be written to continue
+\ -- UCASTP0=%10 : automatic Stop when UCBxTBCNT is reached
+\ ------------------------------\
+\ PORTX (PORTx:y) default values\ DIR0,REN1,OUT1 (input with pullup resistors)
+\ ------------------------------\
+\ notice : UCB0 I2C driver seems to control only DIR register !!!
+BIC.B #M_BUS,&I2CM_REN \ REN0 : no_resistor
+BIC.B #M_BUS,&I2CM_OUT \ OUT0 : preset output low
+BIS.B #M_BUS,&I2CM_SEL1 \ SEL11 : enable I2C I/O
+COLON
+." type stop to stop :-)"
+LIT RECURSE IS WARM \ insert this starting routine between COLD and WARM...
+(WARM) \ ...and continue with (WARM)
+;
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
--- /dev/null
+\ name : msp430FR5xxx_I2C_MMultiMaster.f
+\
+\ Copyright (C) <2016> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY; without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+\
+\
+\ I2C MASTER Standard Mode software driver without interrupt
+\ Target: MSP-EXP430FR5969 @ 8,16MHz
+\ version 1.1 2016-03-18
+\
+\ ---------------------------------------------------------------------------------------------------------------------;
+\ SCL clock generation, timing, and test of data(s) number are made by I2C_MMaster.
+\ slave can strech SCL low after Start Condition and after any bit.
+\
+\ address Ack/Nack is generated by the slave on SDA line (released by the master)
+\ Two groups of eight addresses (000$xxy and 1111xxxy) are not allowed (reserved)
+\ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
+\ data Ack/Nack are generated by the receiver (master or slave) on SDA line
+\ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
+\ Stop or restart conditions must be generated by master after a Nack bit.
+\ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK _
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X___/
+\ _____ _ _ _ _ _ _ _ _ _ _ ___
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |stoP Condition
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK ___
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X \____...
+\ _____ _ _ _ _ _ _ _ _ _ _ ____
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |reStart Condition
+\
+\ tHIGH : SCL high time
+\ tLOW : SCL low time
+\ tBUF : SDA high time between Stop and Start conditions
+\ tHD:STA : Start_Condition SCL high time after SDA is low
+\ tSU:STO : Stop_Condition SCL high time before SDA rise
+\ tSU:STA : Start_Condition SCL high time before SDA fall
+\ tHD:DAT : SDA data change time after SCL is low
+\ the SDA line must be strobe just after SCL is high
+\ the SDA data must be change just after SCL is low
+\ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
+\ tLOW = tSU:STA = tBUF = 4,7µs
+\ tHD:DAT <= 3,45 µs
+\
+\ fast mode (up to 400 kHz) : tHIGH = tHD:STA = tSU:STO = 0,6µs
+\ tLOW = tSU:STA = tBUF = 1,3µs
+\ tHD:DAT <= 0,9 µs
+\ -------------------------------------------------------------------------------------------------------------------;
+
+\ =========================================================================
+\ =========================================================================
+
+\ ### ##### ##### # ## #
+\ # # # # # ## ## ## ## ## #### ##### ###### #####
+\ # # # # # # # # # # # # # # # # # #
+\ # ##### # # # # # # # # # #### # ##### # #
+\ # # # # # # # ###### # # # #####
+\ # # # # # # # # # # # # # # # #
+\ ### ####### ##### # # # # # # #### # ###### # #
+
+\ =========================================================================
+\ =========================================================================
+
+\ tested with P1.6 SDA, P1.7 SCL :
+\ Start + Adr + Write 3 bytes + Stop + Start + adr + read 2 bytes + stop = 206us ==> 305 kHz (STOP=14us)
+\ See MSP430FR5xxx_I2C_MultiMaster.png
+
+
+CREATE I2CMS_ADR \ low(I2CMS_ADR) = slave I2C address with RW flag, high(I2CMS_ADR) = RX buffer,data0
+4 ALLOT \ data1,data2
+CREATE I2CMM_BUF \ low(I2CMM_BUF) = RX or TX lentgh, high(I2CMM_BUF) = TX buffer,data0
+4 ALLOT \ data1,data2
+ \
+VARIABLE MY_OWN_ADR
+
+
+\ ----------------------------------\
+ASM I2C_MM \
+\ ----------------------------------\
+\ \ in I2CMS_ADR/I2CMM_BUF as RX/TX buffer requested by I2CMS_ADR(0(0))
+\ \ I2CMS_ADR(0) = I2C_Slave_addr&R/w
+\ \ I2CMM_BUF(0) = TX/RX count of datas
+\ \ I2CMM_BUF(0) = 0 ==> send only I2C address
+\ \ used S = BUF ptr
+\ \ T
+\ \ out S = BUF PTR pointing on first data not exCHNGd
+\ \ T = count of TX/RX datas exCHNGd
+\ \ T = -1 ==> NACK on address
+\ \ I2CMS_ADR(0) = -1 ==> arbitration lost, else unchanged
+\ \ I2CMM_BUF(0) = unchanged
+\ ------------------------------ \
+\ Swap Slave to Master mode \
+\ ------------------------------ \
+BIS #1,&UCB0CTLW0 \ SWRST
+MOV #$2FD3,&UCB0CTLW0 \ master mode + UCMM + UCTR + START + SWRST, IFG=IE=0
+MOV #$00C8,&UCB0CTLW1 \ set automatic stop (count byte reached)
+MOV #$14,&UCB0BRW \ baudrate = SMCLK/20 = 400 kHz @8MHz ; 340 kHz measured
+MOV &MY_OWN_ADR,&UCB0I2COA0 \ (required by multimaster mode)
+BIS #$0400,&UCB0I2COA0 \ UCOAEN=1 enable UCB0I2COA0 with address slave
+\ ------------------------------ \
+MOV #I2CMM_BUF,S \ count & TX buf
+MOV.B @S+,&UCB0TBCNT \
+CMP.B #0,&UCB0TBCNT \
+0= IF \ count = 0
+ BIS #4,&UCB0CTLW0 \ add Stop to Start cmd ==> Master send only I2C address
+THEN
+MOV #I2CMS_ADR,T \ I2Cadr & RX buf
+MOV.B @T+,&UCB0I2CSA \ UCB0I2CSA = slave_address & R/w bit
+RRA &UCB0I2CSA \ UCB0I2CSA = slave_address, C flag = R/w flag
+U>= IF \ C flag = 1
+ MOV T,S \ Master read : S = RX buffer
+ BIC #$10,&UCB0CTLW0 \ UCB0CTLW0 <-- UCTR=0
+THEN \
+\ ------------------------------ \
+\ Start \
+\ ------------------------------ \
+MOV.B #-1,T \ T=-1
+BIC #1,&UCB0CTLW0 \ UCB0CTLW0 : clear SWRST, start I2C MASTER
+BIT.B #1,&I2CMS_ADR \ R/W test
+0= IF \
+\ ---------------------------- \
+\ MASTER TX \
+\ ---------------------------- \
+ BEGIN \
+ MOV.B &UCBCNT0,T \ store count of byte
+ BIT #$10,&UCB0IFG \ test UCALIFG : arbitration lost interrupt
+ 0<> ?GOTO FW1 \ eUSCI is already in Slave mode
+ BIT #8,&UCB0IFG \ test UCSTPIFG
+ 0<> ?GOTO FW2 \
+ BIT #$20,&UCB0IFG \ test UCNACKIFG
+ 0<> IF \
+ BIS #4,&UCB0CTLW0 \ generate stop bit
+ THEN \
+ BIT #2,&UCB0IFG \ test UCTXIFG0
+ 0<> IF \
+ MOV.B @S+,&UCB0TXBUF \ load data into UCB0TXBUF
+ THEN \
+ AGAIN \
+THEN \
+\ ------------------------------ \
+\ MASTER RX \
+\ ------------------------------ \
+BEGIN \ of Master RX
+ MOV.B &UCBCNT0,T \ store count of byte
+ BIT #8,&UCB0IFG \ test UCSTPIFG
+ 0<> IF \
+ MOV @RSP+,PC \ end of I2C_MM RX driver
+ THEN \
+ BIT #1,&UCB0IFG \ test UCRXIFG0
+ 0<> IF \
+ MOV.B &UCB0RXBUF,0(S) \ load data from UCB0RXBUF
+ ADD #1,S \
+ THEN \
+AGAIN \
+\ ------------------------------ \
+\ Swap Master to Slave mode \
+\ ------------------------------ \
+FW2 MOV #1,&UCB0CTLW0 \ set eUSCI_B in reset state, clear UCB0IE & UCB0IFG all flags
+ BIS #$07A0,&UCB0CTLW0 \
+\ BIS #$10,&UCB0CTLW1 \ set software ack address (UCSWACK=1)
+\ MOV #0,&UCB0ADDMSK \ enable address mask for all addresses i.e. software address
+ BIC #1,&UCB0CTLW0 \ activate eUSCI_B
+ MOV #4,&UCB0IE \ enable StartCond interrupt
+FW1 MOV @RSP+,PC \
+\ ------------------------------ \
+ENDASM \ 62 words + 9 init words
+ \
+
+\ ------------------------------\
+CODE START \ init
+\ ------------------------------\
+\ init I2C_MMaster \
+\ ------------------------------\
+\ %0000 1111 1101 0011 $640 = $0FD3
+\ - UCMM = 1 : multi master mode
+\ - UCMST = 1 : I2C_MMaster
+\ -- UCMODE = %11 = I2C
+\ _ USYNC=1 (always 1)
+\ -- UCSSEL=SMCLK=8MHz
+\ - UCTXACK=0 not auto ACK slave address
+\ - UCTR=1/0 : TX/RX modes
+\ - UCTXSTP
+\ - UCTXSTT send start
+\ - UCSWRST=1
+\ ------------------------------\
+\ %0000 0000 1100 1000 $642 = $00C8
+\ - UCETXINT=0 : UCTXIFG0 set address match UCxI2COAx and TX mode
+\ -- UCCLTO=%11 : SCL low time out = 34 ms
+\ - UCSWACK=1 : UCTXACK must be written to continue
+\ -- UCASTP0=%10 : automatic Stop when UCBxTBCNT is reached
+\ ------------------------------\
+\ PORTX (PORTx:y) default values\ DIR0,REN1,OUT1 (input with pullup resistors)
+\ ------------------------------\
+\ notice : UCB0 I2C driver seems to control only DIR register !!!
+BIC.B #MM_BUS,&I2CMM_REN \ REN0 : no_resistor
+BIC.B #MM_BUS,&I2CMM_OUT \ OUT0 : preset output low
+BIS.B #MM_BUS,&I2CMM_SEL1 \ SEL11 : enable I2C I/O
+COLON
+." ; type stop to stop :-)"
+LIT recurse is WARM \ insert this starting routine between COLD and WARM...
+(WARM) \ ...and continue with (WARM)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
--- /dev/null
+\ name : MSP430FR5xxx_I2C_Slave.f
+RST_STATE
+\ NOECHO
+
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+\
+\ driver I2C SLAVE with START interrupt only, for any I2C_Slave addresses
+\ Target: MSP430FR5xxx @ 8,16,24 MHz
+\ version 1.0 2015-03-17
+
+\ ---------------------------------------------------------------------------------------------------------------------;
+\ SCL clock generation, timing, and test of data(s) number are made by I2C_Master.
+\ slave can strech SCL low after Start Condition and after any bit.
+\
+\ address Ack/Nack is generated by the slave on SDA line (released by the master)
+\ Two groups of eight addresses (000$xxy and 1111xxxy) are not allowed (reserved)
+\ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
+\ data Ack/Nack are generated by the receiver (master or slave) on SDA line
+\ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
+\ Stop or restart conditions must be generated by master after a Nack bit.
+\ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK _
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X___/
+\ _____ _ _ _ _ _ _ _ _ _ _ ___
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |stoP Condition
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK ___
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X \____...
+\ _____ _ _ _ _ _ _ _ _ _ _ ____
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |reStart Condition
+\
+\ tHIGH : SCL high time
+\ tLOW : SCL low time
+\ tBUF : SDA high time between Stop and Start conditions
+\ tHD:STA : Start_Condition SCL high time after SDA is low
+\ tSU:STO : Stop_Condition SCL high time before SDA rise
+\ tSU:STA : Start_Condition SCL high time before SDA fall
+\ tHD:DAT : SDA data change time after SCL is low
+\ the SDA line must be strobe just after SCL is high
+\ the SDA data must be change just after SCL is low
+\ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
+\ tLOW = tSU:STA = tBUF = 4,7µs
+\ tHD:DAT <= 3,45 µs
+\
+\ fast mode (up to 400 kHz) : tHIGH = tHD:STA = tSU:STO = 0,6µs
+\ tLOW = tSU:STA = tBUF = 1,3µs
+\ tHD:DAT <= 0,9 µs
+\ -------------------------------------------------------------------------------------------------------------------;
+
+
+
+VARIABLE I2CS_OWN \ slave I2C address without RW flag (low byte) + DATA0 input (HIGH byte)
+\ 2 ALLOT \ next the low byte of I2CS_OWN word, it is the input buffer
+VARIABLE I2CS_BUF \ buffer output, lentgh (low byte),DATA0 output (HIGH byte)
+\ 2 ALLOT \ this byte lentgh is shared by input and output buffers
+
+\ ******************************\
+ASM I2CS_TX \ TX part of I2C_Slave
+\ ******************************\
+\ \ T = TX buffer_org
+\ \ use W = TX buffer_ptr
+\ \ out : low(I2CS_BUF) = RX or TX lentgh
+\ ------------------------------\
+MOV T,W \ W = TX_buf_ptr -1
+BEGIN \
+ ADD #1,W \ first reserve one byte for length then inc
+ MOV.B @W,&UCB0TXBUF \ +[W] --> UCB0TXBUF
+\ ----------------------------\
+\ slave send byte \
+\ ----------------------------\
+ BEGIN \
+ BIT #$0C,&UCB0IFG \ UCB0IFG(STP,STT) = 1 ?
+ 0<> IF \
+\ --------------------\
+\ stop or restart received
+\ --------------------\
+ SUB T,W \
+ SUB.B #1,W \ sub #1, because char +[W] is not sent
+ MOV.B W,0(T) \ store length in first byte of buffer output
+ BIC #UCTR,&UCB0CTLW0 \ reset UCTR R/W bit for next START
+ MOV @RSP+,PC \ ===> ret
+\ --------------------\
+ THEN \
+ BIT #2,&UCB0IFG \ UCB0IFG(TX0) = 1 ?
+ 0<> UNTIL \
+AGAIN \
+ENDASM \
+ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+\ **************************************\
+ASM I2C_S \ <== eUSCIB0 interrupt vector : i2c_addres&R/w sent by master is received
+\ **************************************\
+BIC #$F8,0(RSP) \ SCG1,SCG0,OSCOFF,CPUOFF and GIE are OFF in retiSR to force LPM0_LOOP with pending interrupt
+MOV #$98,&LPM_MODE \ to reenter in LPM2 mode. LPM3-4 don't work with MSP430FR57xx.
+\ --------------------------------------\
+MOV #I2CS_BUF,T \ T = buffer output address -1
+MOV #I2CS_OWN,S \ S = buffer input address -1
+MOV #0,&UCB0IFG \ write UCB0IFG to clear all int flags (STTIFG,TXIFG,..)
+CMP.B &UCB0I2COA0,&UCB0ADDRX \ UCB0ADDRX = own address ?
+0= IF \
+\ --------------------------------------\
+\ It's my own address \
+\ --------------------------------------\
+ BIS #UCTXACK,&UCB0CTLW0 \ send software Ack address
+ BIT #UCTR,&UCB0CTLW0 \ test UCB0CTLW0(UCTR) R/W bit
+ 0= IF \ I2C_Master Write
+\ --------------------------------\
+\ slave receive datas \ yes
+\ --------------------------------\
+ MOV S,W \ W = input buffer address - 1
+ BEGIN \
+\ ----------------------------\
+\ slave receive one byte \
+\ ----------------------------\
+ BEGIN \
+ BIT #$8C,&UCB0IFG \ UCB0IFG(STP,STT,CLTO) = 1 ? (STOP, START, SCL low timeout)
+ 0<> IF \
+\ --------------------\
+\ TX stop or restart \ from master
+\ --------------------\
+ SUB S,W \ W = Adr_end - Adr_start = length
+ MOV.B W,0(T) \ store length in first byte of buffer output
+\ --------------------\
+\ insert here post RX code
+\ --------------------\
+ RETI \
+ THEN \ if not (stop, restart, CLTO)
+ BIT #1,&UCB0IFG \ UCB0IFG(RX0) = 1 ?
+ 0<> UNTIL \
+ ADD #1,W \ reserve one byte for length first, then preincrement
+ MOV.B &UCB0RXBUF,0(W) \ [UCB0RXBUF] = data --> +[W]
+ AGAIN \ loop for new received data if any
+ THEN \ end of I2C_Master read
+\ ------------------------------------\
+\ slave transmit datas variant 1 \ to loop back after bad_own_address code
+\ ------------------------------------\
+ CALL #I2CS_TX \
+ RETI \
+\ ------------------------------------\
+\ slave transmit datas variant 2 \
+\ ------------------------------------\
+\ MOV T,W \ W = output buffer address -1
+\ BEGIN \
+\ ADD #1,W \ first reserve one byte for length
+\ MOV.B @W,&UCB0TXBUF \ +[W] --> UCB0TXBUF
+\ \ ----------------------------\
+\ \ slave send byte \
+\ \ ----------------------------\
+\ BEGIN \
+\ BIT.B #$0C,&UCB0IFG \ UCB0IFG(STP,STT) = 1 ?
+\ 0<> IF \
+\ \ ------------------------\
+\ \ RX stop or restart \ from master
+\ \ ------------------------\
+\ SUB T,W \ W = Adr_end - Adr_start = length
+\ SUB.B #1,W \ sub #1, because char +[W] is not sent
+\ MOV.B W,0(T) \ store length in first byte of buffer output
+\ BIC.B #UCTR,&UCB0CTLW0 \ reset UCTR R/W bit for next START
+\ RETI \
+\ THEN \
+\ BIT.B #$02,&UCB0IFG \ UCB0IFG(TX0) = 1 ?
+\ 0<> UNTIL \
+\ AGAIN \
+\ ------------------------------------\
+\ End of slave transmit datas variants\
+\ ------------------------------------\
+THEN \ if bad I2C address
+\ --------------------------------------\
+\ BAD I2C ADDRESS CaseOf \
+\ --------------------------------------\
+\ insert here post BAD I2C address code \
+\ ...that can loop back to I2CS_TX... \
+\ --------------------------------------\
+BIC #UCTXACK,&UCB0CTLW0 \ send Nack address
+RETI \
+ENDASM
+ \
+
+\ --------------------------------------\
+CODE START \ init I2C_slave
+\ --------------------------------------\
+\ UCB0CTLW0 = %0000 0111 1100 0001 $640
+\ - UCMST = 0 : I2C_Slave
+\ -- UCMODE = %11 = I2C
+\ _ USYNC=1 (always 1)
+\ -- UCSSEL=SMCLK (don't care in slave mode)
+\ - UCTXACK=0 not auto ACK slave address
+\ - UCTR=0 : RX (for RX address)
+\ - UCSWRST=1
+\ UCB0CTLW1 = %0000 0000 1101 0000 $642
+\ - UCETXINT=0 : UCTXIFG0 set address match UCxI2COAx and TX mode
+\ -- UCCLTO=%11 : SCL low time out = 34 ms
+\ - UCSWACK=1 : UCTXACK must be written to continue
+\ UCB0RXBUF $64C
+\ UCB0TXBUF $64E
+\ UCB0I2COA0 $654 must be written ? enabled ?
+\ UCB0ADDRX $65C
+\ UCB0ADDMSK $65E
+\ UCB0IE = %0000 0000 0000 0100 $66A
+\ - UCSTTIE : StartCond Interrupt only
+\ UCB0IFG $66C
+\ UCB0IV $66E : write it to clear all IFG
+
+\ ------------------------------\
+\ init I2C_slave \
+MOV #1,&UCB0CTLW0 \ set eUSCI_B in reset state, clear UCB0IE & UCB0IFG all flags
+BIS #$07A0,&UCB0CTLW0 \
+BIS #$10,&UCB0CTLW1 \ set software ack address (UCSWACK=1)
+MOV #%1010,&UCB0I2COA0 \ set my own address
+BIS #$0400,&UCB0I2COA0 \ UCOAEN=1 enable UCB0I2COA0 with address slave
+\ MOV #0,&UCB0ADDMSK \ enable address mask for all addresses i.e. software address
+BIC #1,&UCB0CTLW0 \ activate eUSCI_B
+MOV #4,&UCB0IE \ enable StartCond interrupt
+\ ------------------------------\
+\ init interrupt vectors
+MOV #I2C_S,&$FFEE \ eUSCIB0 interrupt vector
+\ ------------------------------\
+\ init PORTA (P2:P1) (complement)
+\ notice : UCB0 I2C driver seems to control only DIR register !!!
+BIC.B #S_BUS,&I2CS_REN \ SDA + SCL pullup/down disable
+BIC.B #S_BUS,&I2CS_OUT \ OUT0 : preset output low
+BIS.B #S_BUS,&I2CS_SEL1 \ enable I2C I/O
+\ ------------------------------\
+COLON
+." I2C_Slave is running. Type STOP to quit"
+LIT recurse is WARM \ insert this routine between COLD and WARM...
+(WARM) ; \ ...and continue with WARM
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+ECHO
+PWR_HERE
+\ START
--- /dev/null
+\ name : I2C_Slave_to_LCD_2x20.f
+
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+\
+
+\ --------------------------------------\
+\ example of App running under interrupt
+\ --------------------------------------\
+
+\ for MSP_EXP430FR5739, MSP_EXP430FR5969, MSP_EXP430FR6989, ... launchpads @ 8MHz
+\
+\ prerequisites : your launchpad is wired as described in launchpad.pat file : UART0, SDA, SCL, LCD parts
+\ and FastForth runs @ 8MHz
+\ usage : create a logical network drive ( a: b: as you want) from your local copy of Gitlab FAST FORTH
+\ with scite.exe open this file MSP430-FORTH\I2C_Slave_to_LCD_2x20.f,
+\ select "tools" menu, "preprocess" item 2 (CTRL+1),
+\ a dialog box asks you for 4 parameters $(1) to $(4),
+\ in the 2th param. field, type your launchpad to select the launchpad.pat to be used : for example MSP_EXP430FR5969,
+\ in the 3th param. field, type the COMx port of your USBtoUART device.
+\ result : a file.4th in which all symbolic addresses are resolved according to the rules described in the selected launchpad.pat
+\ the word START starts the app that runs under LPMx.
+\ to recover the console input (i.e. to quit LPMx), type a space. Then you can enter a command, for example STOP.
+
+WIPE
+ \
+
+: U.R \ u n -- display u unsigned in n width
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+ \
+
+CODE ? \ adr -- display the content of adr
+ MOV @TOS,TOS
+ MOV #U.,PC
+ENDCODE
+ \
+
+
+\ ------------------------------\
+CODE 20_us \ n -- n * 20 us
+\ ------------------------------\
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+\ ------------------------------\
+CODE TOP_LCD \ LCD Sample
+\ ------------------------------\ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_W \ byte -- write byte
+\ ------------------------------\
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+ COLON
+ TOP_LCD 2 20_us \ write high nibble first
+ TOP_LCD 2 20_us ;
+ \
+\ ------------------------------\
+CODE LCD_R \ -- byte read byte
+\ ------------------------------\
+ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+ COLON
+ TOP_LCD 2 20_us \ read high nibble first
+ TOP_LCD 2 20_us
+ HI2LO \ -- %0000HHHH %0000LLLL
+ MOV @RSP+,IP
+ MOV @PSP+,W \ W = high nibble
+ RLAM #4,W \ -- %0000LLLL W = %HHHH0000
+ ADD.B W,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_WrF \ func -- Write Fonction
+\ ------------------------------\
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_RdS \ -- status Read Status
+\ ------------------------------\
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_R
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_WrC \ char -- Write Char
+\ ------------------------------\
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_RdC \ -- char Read Char
+\ ------------------------------\
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_R
+ENDCODE
+ \
+\ ------------------------------\
+\ : LCD_Clear $01 LCD_WrF 80 20_us \ bad init !
+: LCD_Clear $01 LCD_WrF 100 20_us ;
+ \
+\ ------------------------------\
+: LCD_Home $02 LCD_WrF 80 20_us ;
+ \
+\ ------------------------------\
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+\ ******************************\
+ASM WDT_Int \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+\ ------------------------------\
+\ define LPM mode for ACCEPT \ LPM0 is the default mode.
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0
+\ ------------------------------\
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #34,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+BIC #WDTIFG,&SFRIFG1 \ reset WDT_INT flag
+BIC #$78,0(RSP) \ set CPU ON and GIE OFF in retiSR
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+
+VARIABLE I2CS_OWN \ slave I2C address without RW flag (low byte) + DATA0 input (HIGH byte)
+\ 2 ALLOT \ next the low byte of I2CS_OWN word, it is the input buffer
+VARIABLE I2CS_BUF \ buffer output, lentgh (low byte),DATA0 output (HIGH byte)
+\ 2 ALLOT \ this byte lentgh is shared by input and output buffers
+
+\ ******************************\
+ASM I2CS_TX \ TX part of I2C_Slave
+\ ******************************\
+\ \ T = TX buffer_org
+\ \ use W = TX buffer_ptr
+\ \ out : low(I2CS_BUF) = RX or TX lentgh
+\ ------------------------------\
+MOV T,W \ W = TX_buf_ptr -1
+BEGIN \
+ ADD #1,W \ first reserve one byte for length then inc
+ MOV.B @W,&UCB0TXBUF \ +[W] --> UCB0TXBUF
+\ ----------------------------\
+\ slave send byte \
+\ ----------------------------\
+ BEGIN \
+ BIT #$0C,&UCB0IFG \ UCB0IFG(STP,STT) = 1 ?
+ 0<> IF \
+\ --------------------\
+\ stop or restart received
+\ --------------------\
+ SUB T,W \
+ SUB.B #1,W \ sub #1, because char +[W] is not sent
+ MOV.B W,0(T) \ store length in first byte of buffer output
+ BIC #UCTR,&UCB0CTLW0 \ reset UCTR R/W bit for next START
+ MOV @RSP+,PC \ ===> ret
+\ --------------------\
+ THEN \
+ BIT #2,&UCB0IFG \ UCB0IFG(TX0) = 1 ?
+ 0<> UNTIL \
+AGAIN \
+ENDASM \
+ \
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+\ **************************************\
+ASM I2C_S \ <== eUSCIB0 interrupt vector : i2c_addres&R/w sent by master is received
+\ **************************************\
+BIC #$78,0(RSP) \ SCG1,SCG0,OSCOFF,CPUOFF and GIE are OFF in retiSR to force LPM0_LOOP with pending interrupt
+\ --------------------------------------\
+\ define LPM mode for ACCEPT \ LPM0 is the default mode.
+\ --------------------------------------\
+\ MOV #LPM4,&LPM_MODE \ MSP430FR59xx family : LPM 0 to 4
+\ MOV #LPM2,&LPM_MODE \ MSP430FR57xx family : terminal input don't work for LPMx > 2
+\ \ MSP430FR2xxx family : terminal input don't work for LPMx > 0
+\ --------------------------------------\
+MOV #I2CS_BUF,T \ T = buffer output address -1
+MOV #I2CS_OWN,S \ S = buffer input address -1
+MOV #0,&UCB0IFG \ write UCB0IFG to clear all int flags (STTIFG,TXIFG,..)
+CMP.B &UCB0I2COA0,&UCB0ADDRX \ UCB0ADDRX = own address ?
+0= IF \
+ BIS #UCTXACK,&UCB0CTLW0 \ send software Ack address
+ BIT #UCTR,&UCB0CTLW0 \ test UCB0CTLW0(UCTR) R/W bit
+ 0= IF \ I2C_Master Write
+\ --------------------------------\
+\ slave receive datas \ yes
+\ --------------------------------\
+ MOV S,W \ W = input buffer address - 1
+ BEGIN \
+\ ----------------------------\
+\ slave receive one byte \
+\ ----------------------------\
+ BEGIN \
+ BIT #$8C,&UCB0IFG \ UCB0IFG(STP,STT,CLTO) = 1 ? (STOP, START, SCL low timeout)
+ 0<> IF \
+\ --------------------\
+\ TX stop or restart \ from master
+\ --------------------\
+ SUB S,W \ W = Adr_end - Adr_start = length
+ MOV.B W,0(T) \ store length in first byte of buffer output
+\ --------------------\
+\ insert here post RX code
+\ --------------------\
+\ BIS.B #LED1,&LED1_OUT \ OUT high ==> switch ON LED1 to test
+\ display IR_RC5 command
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \
+ MOV.B 1(X),TOS \ display RC6 command
+\ MOV.B 0(W),TOS \ display count
+ LO2HI \ IP is free
+ ['] LCD_Clear IS CR
+ ['] LCD_WrC IS EMIT
+ BASE @ HEX \ save BASE before change
+ CR ." $" 2 U.R SPACE \ display received byte
+ ." LPM = $" LPM_MODE ? \ display also LPM value
+ ['] (CR) IS CR
+ ['] (EMIT) IS EMIT
+ BASE ! \ restore BASE
+ HI2LO \ nice code, right ?
+\ ; endof display
+\ BIC.B #LED1,&LED1_OUT \ OUT low ==> switch OFF LED1 to test
+\ --------------------\
+ RETI \
+\ --------------------\
+ THEN \ if not (stop, restart, CLTO)
+ BIT #1,&UCB0IFG \ UCB0IFG(RX0) = 1 ?
+ 0<> UNTIL \
+ ADD #1,W \ reserve one byte for length first, then preincrement
+ MOV.B &UCB0RXBUF,0(W) \ [UCB0RXBUF] = data --> +[W]
+ AGAIN \ loop for new received data if any
+ THEN \ end of I2C_Master read
+\ ------------------------------------\
+\ slave transmit datas variant 1 \ to loop back after bad_own_address code
+\ ------------------------------------\
+ CALL #I2CS_TX \
+ RETI \
+\ ------------------------------------\
+\ slave transmit datas variant 2 \
+\ ------------------------------------\
+\ MOV T,W \ W = output buffer address -1
+\ BEGIN \
+\ ADD #1,W \ first reserve one byte for length
+\ MOV.B @W,&UCB0TXBUF \ +[W] --> UCB0TXBUF
+\ \ ----------------------------\
+\ \ slave send byte \
+\ \ ----------------------------\
+\ BEGIN \
+\ BIT.B #$0C,&UCB0IFG \ UCB0IFG(STP,STT) = 1 ?
+\ 0<> IF \
+\ \ ------------------------\
+\ \ RX stop or restart \ from master
+\ \ ------------------------\
+\ SUB T,W \ W = Adr_end - Adr_start = length
+\ SUB.B #1,W \ sub #1, because char +[W] is not sent
+\ MOV.B W,0(T) \ store length in first byte of buffer output
+\ BIC.B #UCTR,&UCB0CTLW0 \ reset UCTR R/W bit for next START
+\ RETI \
+\ THEN \
+\ BIT.B #$02,&UCB0IFG \ UCB0IFG(TX0) = 1 ?
+\ 0<> UNTIL \
+\ AGAIN \
+\ ------------------------------------\
+\ End of slave transmit datas variants\
+\ ------------------------------------\
+THEN \ if bad I2C address
+\ --------------------------------------\
+\ BAD I2C ADDRESS CaseOf \
+\ --------------------------------------\
+\ insert here post BAD I2C address code \
+\ ...that can loop back to I2CS_TX... \
+\ --------------------------------------\
+BIC #UCTXACK,&UCB0CTLW0 \ send Nack address
+RETI \
+ENDASM
+ \
+
+
+
+
+\ START performs a complementary initialisation of the FAST FORTH system to start your app.
+\ START is inserted COLD and ABORT via the fragment of code : LIT RECURSE IS WARM.
+\ --------------------------------------\
+CODE START \ init I2C_slave
+\ --------------------------------------\
+\ %0000 0111 1100 0001 UCB0CTLW0
+\ - UCMST = 0 : I2C_Slave
+\ -- UCMODE = %11 = I2C
+\ _ USYNC =1 (always 1)
+\ -- UCSSEL =SMCLK (don't care in slave mode)
+\ - UCTXACK =0 not auto ACK slave address
+\ - UCTR =0 : RX (for RX address)
+\ - UCSWRST =1
+\ --------------------------------------\
+\ %0000 0000 1101 0000 UCB0CTLW1
+\ - UCETXINT =0 : UCTXIFG0 set address match UCxI2COAx and TX mode
+\ -- UCCLTO =%11 : SCL low time out = 34 ms
+\ - UCSWACK =1 : UCTXACK must be written to continue
+\ --------------------------------------\
+\ UCB0RXBUF
+\ UCB0TXBUF
+\ UCB0I2COA0 must be written ? enabled ?
+\ UCB0ADDRX
+\ UCB0ADDMSK
+\ --------------------------------------\
+\ %0000 0000 0000 0100 UCB0IE
+\ - UCSTTIE : StartCond Interrupt only
+\ --------------------------------------\
+\ UCB0IFG
+\ UCB0IV : write it to clear all IFG
+
+\ ------------------------------\
+\ init I2C_slave \
+\ ------------------------------\
+MOV #1,&UCB0CTLW0 \ set eUSCI_B in reset state, clear UCB0IE & UCB0IFG all flags
+BIS #$07A0,&UCB0CTLW0 \
+BIS #$10,&UCB0CTLW1 \ set software ack address (UCSWACK=1)
+MOV #%1010,&UCB0I2COA0 \ set my own address
+BIS #$0400,&UCB0I2COA0 \ UCOAEN=1 enable UCB0I2COA0 with address slave
+\ MOV #0,&UCB0ADDMSK \ enable address mask for all addresses i.e. software address
+BIC #1,&UCB0CTLW0 \ activate eUSCI_B
+MOV #4,&UCB0IE \ enable StartCond interrupt
+MOV #%1010,&I2CS_OWN \ my slave address, without RW flag !
+\ ------------------------------\
+\ init PORT complement
+\ ------------------------------\
+\ notice : UCB0 I2C driver seems to control only DIR register !!!
+BIC.B #S_BUS,&I2CS_REN \ SDA + SCL pullup/down disable
+BIC.B #S_BUS,&I2CS_OUT \ OUT0 : preset output low
+BIS.B #S_BUS,&I2CS_SEL1 \ enable I2C I/O
+\ ------------------------------\
+BIS.B #LCDVo,&LCDVo_DIR \
+BIS.B #LCDVo,&LCDVo_SEL0 \ TB0.2
+\ ------------------------------\
+BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+BIS.B #LCD_DB,&LCD_DB_DIR \ lcd_db as output, wired to DB(4-7) LCD_Data
+BIC.B #LCD_DB,&LCD_DB_REN \ lcd_db pullup/down disable
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up mode
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate LCD_V0 via TB0.2 and P1.5/P2.2
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+\ MOV #$5A5E,&WDTCTL \ init WDT Vloclk source 10kHz /2^9 (50 ms), interval mode
+ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #I2C_S,&I2CS_Vec \ eUSCIB0 interrupt vector
+ MOV #WDT_Int,&WDT_Vec \ init WDT interval vector interrupt
+\ ------------------------------\
+\ define LPM mode for ACCEPT \ LPM0 is the default mode.
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0
+\ ------------------------------\
+\ Init LCD
+ COLON
+ $03E8 20_us \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_us \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ 5 20_us \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ 2 20_us \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ 2 20_us \ wait 40 us = LCD cycle
+ $28 LCD_WrF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WrF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WrF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WrF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+
+ ['] LCD_HOME IS CR \ CR redirected to LCD_HOME
+ ['] LCD_WrC IS EMIT \ EMIT redirected to LCD_WrC
+ CR ." I love you" \ display it on the LCD
+ ['] (EMIT) IS EMIT \ restore EMIT
+ ['] (CR) IS CR \ restore CR
+ ." I2C_Slave_to_LCD is running. Type STOP to quit" \ display on terminal
+\ NOECHO \ uncomment to run this app without terminal connexion
+ lit RECURSE IS WARM \ insert this starting routine between COLD and WARM...
+ (WARM) ; \ ...and continue with (WARM)
+ \
+
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+RST_HERE
+
+
+\ START runs your App.
+\ when downloading this file, all lines beyond the START command are ignored. Usefull to comment.
+
+\ driver for LCD 2x20 characters display with 4 bits data interface
+\ without usage of an auxiliary 5V to feed the Vo of LCD
+\ without potentiometer to adjust the LCD contrast
+\ LCD contrast software adjustable by 2 switches
+\ TB0.2 current consumption ~ 500 uA
+
+\ layout : see config.pat file for defining I/O
+
+\ GND <-------+---0V0----------> 1 LCD_Vss
+\ VCC >------ | --3V6-----+----> 2 LCD_Vdd
+\ | |
+\ |___ 470n ---
+\ ^ | ---
+\ / \ BAT54 |
+\ --- |
+\ 100n | 2k2 |
+\ TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+\ -------------------------> 4 LCD_RW
+\ -------------------------> 5 LCD_RW
+\ -------------------------> 6 LCD_EN
+\ <------------------------> 11 LCD_DB4
+\ <------------------------> 12 LCD_DB5
+\ <------------------------> 13 LCD_DB5
+\ <------------------------> 14 LCD_DB7
+
+\ Sw1 <--- LCD contrast + (finger :-)
+\ Sw2 <--- LCD contrast - (finger \-)
+
--- /dev/null
+\ name : msp430FR5xxx_I2C_Soft_Master.asm
+
+WIPE
+
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ version 2.0 2015-07-30
+\ ---------------------------------------------------------------------------------------------------------------------\
+\ SCL clock generation, timing, and test of data(s) number are made by I2C_Master.
+\ slave can strech SCL low after Start Condition and after any bit.
+\
+\ address Ack/Nack is generated by the slave on SDA line (released by the master)
+\ Two groups of eight addresses (000xxxy and 1111xxxy) are not allowed (reserved)
+\ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
+\ data Ack/Nack are generated by the receiver (master or slave) on SDA line
+\ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
+\ Stop or restart conditions must be generated by master after a Nack bit.
+\ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions.
+\
+\
+\ first byte = address + R/W flag | byte data (one, for example)
+\ __ _____ _____ _..._ _____ __R__ _NAK_ _____ _____ _..._ _____ _____ _NAK_ _
+\ SDA \____/_MSB_X_____X_..._X_LSB_X__W__x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X___/
+\ _____ _ _ _ _ _ _ _ _ _ _ ___
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |SSL |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |stoP Condition
+\
+\ first byte = address + R/W flag | byte data (one, for example)
+\ __ _____ _____ _..._ _____ __R__ _NAK_ _____ _____ _..._ _____ _____ _NAK_ ___
+\ SDA \____/_MSB_X_____X_..._X_LSB_X__W__x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X \____...
+\ _____ _ _ _ _ _ _ _ _ _ _ ____
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |SSL |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |reStart Condition
+\
+\ SSL : Slave can strech SCL low
+\ tHIGH : SCL high time
+\ tLOW : SCL low time
+\ tBUF : SDA high time between Stop and Start conditions
+\ tHD:STA : Start_Condition SCL high time after SDA is low
+\ tSU:STO : Stop_Condition SCL high time before SDA rise
+\ tSU:STA : Start_Condition SCL high time before SDA fall
+\ tHD:DAT : SDA data change time after SCL is low
+\ the SDA line must be strobe just after SCL is high
+\ the SDA data must be change just after SCL is low
+\ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
+\ tLOW = tSU:STA = tBUF = 4,7µs
+\ tHD:DAT <= 3,45 µs
+\ -------------------------------------------------------------------------------------------------------------------\
+\
+\
+\ -------------------------------------------------------------------------------------------------------------------\
+\ I2C Soft MASTER, Standard MODE, 8,16,24MHz
+\ -------------------------------------------------------------------------------------------------------------------\
+
+\ ===============================================================================================
+\ ===============================================================================================
+
+\ ### ##### ##### ##### # #
+\ # # # # # # # #### ###### ##### ## ## ## #### ##### ###### #####
+\ # # # # # # # # # # # # # # # # # # #
+\ # ##### # ##### # # ##### # # # # # # #### # ##### # #
+\ # # # # # # # # # # ###### # # # #####
+\ # # # # # # # # # # # # # # # # # # # #
+\ ### ####### ##### ##### #### # # # # # # #### # ###### # #
+
+\ ===============================================================================================
+\ ===============================================================================================
+
+\ use Px.0 to Px.3 pins as SCL and SDA pins to use immediate instruction in one byte (#1,#2,#4,#8)
+
+\ tested with P1.6 SDA, P1.7 SCL @8 MHZ :
+\ Start + Adr + Write 3 bytes + Stop + Start + adr + read 2 bytes + stop = 600us ==> 105 kHz
+\ See MSP430FR5xxx_I2C_Soft_Master.png
+
+VARIABLE I2CS_ADR \ low(I2CS_ADR) = slave I2C address with RW flag, high(I2CS_ADR) = RX buffer,data0
+2 ALLOT \ data1,data2
+VARIABLE I2CM_BUF \ low(I2CM_BUF) = RX or TX lentgh, high(I2CM_BUF) = TX buffer,data0
+2 ALLOT \ data1,data2
+ \
+
+\ ------------------------------\
+ASM T_I2C \ 4 init first once !!!
+\ ------------------------------\
+BEGIN \ 3~ loop
+ SUB #1,Y \ 1
+0= UNTIL \ 2
+ MOV #1,Y \ 2 set I2C tHIGH time @ 8MHz
+\ MOV #9,Y \ 2 set I2C tHIGH time @ 16MHz
+\ MOV #20,Y \ 2 set I2C tHIGH time @ 24MHz
+ MOV @RSP+,PC \ 4 ret
+ENDASM \
+ \
+
+\ ------------------------------\ _
+ASM I2C_PLS \ SCL _| |_ pulse
+\ ------------------------------\
+CALL #T_I2C \ _ wait tLOW
+BIC.B #SMSCL,&I2CSM_DIR \ _^ release SCL (high)
+BEGIN
+ BIT.B #SMSCL,&I2CSM_IN \ test if SCL is released
+0<> UNTIL
+CALL #T_I2C \ wait tHIGH
+BIT.B #SMSDA,&I2CSM_IN \ _ get SDA
+BIS.B #SMSCL,&I2CSM_DIR \ v_ force SCL low
+MOV @RSP+,PC \ ret
+ENDASM \
+ \
+
+\ ------------------------------\
+ASM I2C_MTX \ MASTER TX \ shared code for address and TX data
+\ ------------------------------\
+BEGIN \
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #SMSDA,&I2CSM_DIR \ 4 l yes : SDA as input ==> SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #SMSDA,&I2CSM_DIR \ 4 l no : SDA as output ==> SDA low
+ THEN \ l _
+ CALL I2C_PLS \ _| |_ SCL
+ SUB.B #1,W \ l count of bits
+0= UNTIL \ l
+BIC.B #SMSDA,&I2CSM_DIR \ 5 l _ SDA as input : release SDA high to prepare read Ack/Nack
+MOV @RSP+,PC \ ret
+ENDASM \
+ \
+
+\ ==================================\
+ASM I2C_M \
+\ ==================================\
+\ \ in I2CS_ADR/I2CM_BUF as RX/TX buffer requested by I2CS_ADR(0(0))
+\ \ I2CS_ADR(0) = I2C_Slave_addr&R/w
+\ \ I2CM_BUF(0) = TX/RX count of datas
+\ \ I2CM_BUF(0) = 0 ==> send only I2C address
+\ \ used S BUF ptr
+\ \ T datas countdown
+\ \ W bits countdown
+\ \ X dataI2CM_
+\ \ out I2CSLA_ADR & (R/W) unCHNGd
+\ \ S = BUF PTR pointing on first data not exCHNGd
+\ \ T = count+1 of TX/RX datas exCHNGd
+\ \ I2CS_ADR(0) = unCHNGd
+\ \ I2CM_BUF(0) = count of data not exCHNGd (normally = 0)
+\ \ I2CM_BUF(0) = -1 <==> Nack on address
+\ ----------------------------------\
+\ I2C_MR_DC_ListenBeforeStart: \ test if SCL & SDA lines are idle (high)
+\ ----------------------------------\
+ BIC.B #SM_BUS,&I2CSM_DIR \ SDA & SCL pins as input
+ BIC.B #SM_BUS,&I2CSM_OUT \ preset output LOW for SDA & SCL pins
+ MOV #2,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 8 MHz
+\ MOV #4,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 16 MHz
+\ MOV #6,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 24 MHz
+ BEGIN \
+ BEGIN \
+ BEGIN \
+ BIT.B #SMSCL,&I2CSM_IN \ 4 P1DIR.3 SCL high ?
+ 0<> UNTIL \ 2
+ BIT.B #SMSDA,&I2CSM_IN \ 4 P1IN.2 SDA high ?
+ 0<> UNTIL \ 2
+ SUB #1,T \ 1
+ 0= UNTIL \ 2 here the I2C bus is idle
+\ ------------------------------\
+\ I2C_Master_Start_Cond: \ here, SDA and SCL are in idle state
+\ ------------------------------\
+BIS.B #SMSDA,&I2CSM_DIR \ 4- P1DIR.2 force SDA output (low)
+MOV #5,Y \ 2 tHD\STA time 8 MHz
+\ MOV #15,Y \ 2 tHD\STA time 16MHz
+\ MOV #25,Y \ 2 tHD\STA time 24MHz
+CALL #T_I2C \ wait tHD\STA
+BIS.B #SMSCL,&I2CSM_DIR \ 4- P1DIR.3 force SCL output (low)
+\ ------------------------------\
+\ I2C_Master_Start_EndOf: \
+\ ------------------------------\
+MOV #I2CS_ADR,S \ 2 l
+MOV.B @S+,X \ 3 l X = slave address, S = RX buffer
+MOV #I2CM_BUF,W \ 2 l
+MOV.B @W+,T \ 2 l T = count of datas, W = TX buffer
+BIT.B #1,X \ 1 l test I2C R/w flag
+0= IF \ 2 l write flag
+ MOV W,S \ 3 l TX buffer
+THEN \
+\ ------------------------------\
+\ I2C_Master_Send_address \ SCL is held low by slave
+\ ------------------------------\
+ADD #1,T \ to add address in count
+MOV #8,W \ 1 l prepare 8 bit Master writing
+MOV #1,Y \ 2 tHD\STA time 8 MHz value
+\ MOV #5,Y \ 2 tHD\STA time 16MHz value
+\ MOV #15,Y \ 2 tHD\STA time 24MHz value
+CALL #I2C_MTX \ 4 to send address
+\ ------------------------------\
+\ I2C_Master_Loop_Data \
+\ ------------------------------\
+BEGIN \
+\ ----------------------------\
+\ Master TX/RX ACK/NACK \
+\ ----------------------------\
+ MOV #2,Y \ 2 tLOW time complement @ 8MHz
+\ MOV #15,Y \ 2 tLOW time complement @ 16MHz
+\ MOV #20,Y \ 2 tLOW time complement @ 24MHz
+ CALL #I2C_PLS \ _| |_ SCL with BIT SDA, then ret
+ 0<> IF BIS #2,SR \ l if Nack (TX), force Z=1 ==> StopCond
+ ELSE SUB.B #1,T \ else dec count
+ THEN \ l
+\ ----------------------------\
+\ I2C_Master_CheckCountDown \ count=0 or Nack received
+\ ----------------------------\
+ 0= IF \ count reached or Nack
+\ ----------------------------\
+\ I2C_Master_StopCond \
+\ ----------------------------\ before releasing SCL
+ BIS.B #SMSDA,&I2CSM_DIR \ l P1DIR.2 as output ==> SDA low
+ CALL #T_I2C \ l _ wait 4 us
+ BIC.B #SMSCL,&I2CSM_DIR \ _| P1DIR.2 release SCL (high)
+ MOV #5,Y \ 2 tSU:STO time 8 MHz value
+\ MOV #15,Y \ 2 tSU:STO time 16MHz value
+\ MOV #25,Y \ 2 tSU:STO time 24MHz value
+ CALL #T_I2C \ _ wait tSU:STO
+ BIC.B #SMSDA,&I2CSM_DIR \ _| P1DIR.2 as input ==> SDA high with pull up resistor
+ SUB.B T,&I2CM_BUF \ 4 l refresh buffer length and reach tSU:STO
+ MOV @RSP+,PC \ ====>
+\ ----------------------------\
+ THEN \
+\ ----------------------------\
+ MOV.B #8,W \ 1 l prepare 8 bits transaction
+ BIT.B #1,&I2CS_ADR \ 3 l I2C_Master Read/write bit test
+ 0= IF \ 2 l write flag test
+\ ------------------------\
+\ I2C write \
+\ ------------------------\
+ MOV.B @S+,X \ 2 l next byte to transmit
+ CALL #I2C_MTX \ 4 to send data + test ack
+ ELSE \ l
+\ ------------------------\
+\ I2C read \
+\ ========================\
+\ I2C_Master_RX: \ here, SDA is indetermined, SCL is strech low by master
+\ ========================\
+ BEGIN \
+ BIC.B #SMSDA,&I2CSM_DIR \ 4 l _ P1DIR.2 as input ==> release SDA high because pull up resistor
+ MOV #3,Y \ 2 tLOW time complement @ 8 MHz
+\ MOV #15,Y \ 2 tLOW time complement @ 16MHz
+\ MOV #24,Y \ 2 tLOW time complement @ 24MHz
+ CALL #I2C_PLS \ _| |_ SCL + BIT SDA input (SDA-->carry)
+ ADDC.B X,X \ 1 l C <-- X <--- C
+ SUB #1,W \ 1 l count of bits
+ 0= UNTIL \ 2 l
+ MOV.B X, 0(S) \ 3 l store byte in buffer
+ ADD #1,S \ 1 l
+\ ------------------------\
+\ Compute Ack Or Nack \ here, SDA is released by slave, SCL is strech low by master
+\ ------------------------\
+ CMP #1,T \ 1 l here, SDA is released by slave = Nack
+ 0<> IF \ 2
+ BIS.B #SMSDA,&I2CSM_DIR \ 4 l send Ack if byte count <> 1
+ THEN \ l
+ THEN \
+AGAIN \ l
+ENDASM \
+ \
+
+\ ------------------------------\
+CODE START \
+\ ------------------------------\
+\ init PORTA (P2:P1) (complement) when reset occurs all I/O are set in input with resistors pullup
+BIC.B #SM_BUS,&I2CSM_OUT \ P1OUT.32 preset SDA + SCL output low
+BIC.B #SM_BUS,&I2CSM_REN \ P1REN.32 SDA + SCL pullup/down disable
+\ ------------------------------\
+LO2HI
+." \ type stop to stop :-)"
+LIT recurse is WARM \ insert this starting routine between COLD and WARM...
+(WARM) \ ...and continue with (WARM)
+;
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
--- /dev/null
+\ name : msp430FR5xxx_I2C_Soft_MultiMaster.f
+
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ I2C MASTER Standard Mode software driver without interrupt, with detection collision
+\ Target: MSP430FR5xxx, tested @ 8,16,24 MHz and adjusted @ 16,24 MHz
+\ SDA = P1.2, SCL = P1.3, with 3k3 pullup resistors
+
+\ version 1.0 2016-04-10
+
+WIPE
+\ ========================================================================================================
+\ ========================================================================================================
+
+\ ### ##### ##### ##### # # # #
+\ # # # # # # # #### ###### ##### ## ## ## ## ## #### ##### ###### #####
+\ # # # # # # # # # # # # # # # # # # # # # # #
+\ # ##### # ##### # # ##### # # # # # # # # # #### # ##### # #
+\ # # # # # # # # # # # # ###### # # # #####
+\ # # # # # # # # # # # # # # # # # # # # # #
+\ ### ####### ##### ##### #### # # # # # # # # #### # ###### # #
+
+\ ========================================================================================================
+\ ========================================================================================================
+
+\ P1.2 = SDA, P1.3 = SCL
+\ use Px.0 to Px.3 for good timing at 8 MHz (immediate addressing is less of one cycle)
+
+\ tested with P1.6 SDA, P1.7 SCL @ 8MHz :
+\ Start + Adr + Write 3 bytes + Stop + Start + adr + read 2 bytes + stop = 628us ==> 100 kHz
+\ See MSP430FR5xxx_I2C_Soft_MultiMaster.png
+
+VARIABLE I2CS_ADR \ low(I2CS_ADR) = slave I2C address with RW flag, high(I2CS_ADR) = RX buffer,data0
+2 ALLOT \ data1,data2
+VARIABLE I2CM_BUF \ low(I2CM_BUF) = RX or TX lentgh, high(I2CM_BUF) = TX buffer,data0
+2 ALLOT \ data1,data2
+ \
+
+\ ------------------------------\
+ASM T_I2C \ 4 init first once !!!
+\ ------------------------------\
+BEGIN \ 3~ loop
+ SUB #1,Y \ 1
+0= UNTIL \ 2
+ MOV #1,Y \ 2 set I2C tHIGH time @ 8MHz
+\ MOV #9,Y \ 2 set I2C tHIGH time @ 16MHz
+\ MOV #20,Y \ 2 set I2C tHIGH time @ 24MHz
+ MOV @RSP+,PC \ 4 ret
+ENDASM \
+ \
+
+
+\ ------------------------------\
+ASM I2C_PLS \ SCL Pulse
+\ ------------------------------\
+ CALL #R11_I2C \ _ wait tLOW
+ BIC.B #SMMSCL,&I2CSMM_DIR \ _^ release SCL (high)
+ BEGIN
+ BIT.B #SMMSCL,&I2CSMM_IN \ test if SCL is released
+ 0<> UNTIL
+ CALL #R11_I2C \ wait tHIGH
+ MOV.B &I2CSMM_IN,Y \ 3
+ BIT.B #SMMSDA,Y \ _ get SDA
+ BIS.B #SMMSCL,&I2CSMM_DIR \ v_ force SCL low
+ MOV @RSP+,PC \ ret
+ENDASM \
+ \
+
+\ ------------------------------\
+ASM I2C_BTX \ MASTER TX \ one bit shared code for address and TX data
+\ ------------------------------\
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #SMMSDA,&I2CSMM_DIR \ 4 l yes : SDA as input ==> SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #SMMSDA,&I2CSMM_DIR \ 4 l no : SDA as output ==> SDA low
+ THEN \ l _
+ JMP I2C_PLS \ SCL _| |_ pulse
+ENDASM \
+ \
+
+\ ==================================\
+ASM I2C_MM \ soft I2C_MultiMaster driver
+\ ==================================\
+\ \ in : I2CS_ADR pointer
+\ \ : I2CM_BUF pointer
+\ \ used: S datas pointer
+\ \ T count of I2C datas exchanged
+\ \ W count of bits
+\ \ X data
+\ \ Y I2C_time
+\ \ SR(10) collision flag
+\ \ out : I2CS_ADR(0) unchanged
+\ \ I2CM_BUF(0) = count of data not exchanged (normally = 0)
+\ \ I2CM_BUF(0) = -1 <==> Nack on address
+\ ----------------------------------\
+\ I2CMM_Stop_UCBxI2CSlave \ if SDA SCL of I2C_MultiMaster are hard wired onto SDA SCL of I2C_Slave under interrupt...
+\ ----------------------------------\
+\ BIS #1,&UCB0CTLW0 \ set eUSCI_B0 in reset state, reset StartCond int in UCB0IFG
+\ BIC.B #I2CM_BUS,&I2CSMM_SEL1 \ disable I2C I/O
+\ ----------------------------------\
+\ I2C_MR_DC_ListenBeforeStart: \ test if SCL & SDA lines are idle (high)
+\ ----------------------------------\
+BEGIN \
+ BIC.B #SMM_BUS,&I2CSMM_DIR \ SDA & SCL pins as input
+ BIC.B #SMM_BUS,&I2CSMM_OUT \ preset output LOW for SDA & SCL pins
+ MOV #2,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 8 MHz
+\ MOV #4,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 16 MHz
+\ MOV #6,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 24 MHz
+ BEGIN \
+ BEGIN \
+ BEGIN \
+ BIT.B #SMMSCL,&I2CSMM_IN \ 4 P1DIR.3 SCL high ?
+ 0<> UNTIL \ 2
+ BIT.B #SMMSDA,&I2CSMM_IN \ 4 P1IN.2 SDA high ?
+ 0<> UNTIL \ 2
+ SUB #1,T \ 1
+ 0= UNTIL \ 2 here the I2C bus is idle
+\ --------------------------------\
+\ I2CMR_DC_Shutdown_Slave_Int \ if SDA SCL of I2C_MultiMaster are hard wired onto SDA SCL of I2C_Slave under interrupt...
+\ --------------------------------\
+\ BIS #1,&$640 \ ...set eUSCI_B0 in reset state, that allows I/O use for SDA & SCL...
+\ BIC.B #SMM_BUS,&PI2CSSEL1 \ disable I2C I/O
+\ --------------------------------\
+\ I2C_Master_Start_Cond: \ here, SDA and SCL are in idle state
+\ --------------------------------\
+ BIS.B #SMMSDA,&I2CSMM_DIR \ 4- force SDA output (low)
+ MOV #I2CS_ADR,S \ 2 l
+ MOV.B @S+,X \ 3 l X = slave address, S = RX buffer
+ MOV #I2CM_BUF,W \ 2 l
+ MOV.B @W+,T \ 2 l T = count of datas, W = TX buffer
+ ADD.B #1,T \ to include address in count
+ BIT.B #1,X \ 1 l test I2C R/w flag
+ 0= IF \ 2 l write flag
+ MOV W,S \ 3 l TX buffer
+ THEN \
+ MOV #5,Y \ 2 tHD\STA time 8 MHz complement
+\ MOV #14,Y \ 2 tHD\STA time 16MHz complement
+\ MOV #25,Y \ 2 tHD\STA time 24MHz complement
+ CALL #R11_I2C \ wait 4 us
+ BIS.B #SMMSCL,&I2CSMM_DIR \ 4- force SCL output (low)
+\ --------------------------------\
+\ I2C_Master_Start_EndOf: \
+\ --------------------------------\
+\ I2C_Master_Send_address \
+\ --------------------------------\
+ BIC #$0400,SR \ 2 reset detection collision SR(10) flag
+ MOV.B #8,W \ 1 l prepare 8 bit Master writing
+ BEGIN \
+ MOV #1,Y \ 2 tHD\STA time =8MHz complement
+\ MOV #2,Y \ 2 tHD\STA time =16MHz complement
+\ MOV #13,Y \ 2 tHD\STA time =24MHz complement
+ CALL #I2C_BTX \ l send one bit
+\ ----------------------------\
+\ collision detection \
+\ ----------------------------\
+ XOR.B &I2CSMM_DIR,Y \ 3 normal : IN(SMMSDA) XOR DIR(SMMSDA) = 1
+ BIT.B #SMMSDA,Y \ 2 collision : IN(SMMSDA=0) XOR DIR(SMMSDA=0) = 0
+ 0= IF BIS #$0402,SR \ 6 set collision detection flag SR(10) and set Z=1 to force end of loop
+ ELSE SUB #1,W \ 3 dec count of bits
+ THEN \
+ 0= UNTIL \ 2
+ BIT #$0400,SR \ 2 collision ?
+0= UNTIL \ 2 loop back if collision during send address
+BIC.B #SMMSDA,&I2CSMM_DIR \ 5 release SDA high before 9th bit
+\ ----------------------------------\
+\ I2C_Master_Loop \
+\ ----------------------------------\
+BEGIN
+\ --------------------------------\
+\ Master TX/RX ACK/NACK \
+\ --------------------------------\
+ MOV #1,Y \ 2 tLOW time complement @ 8MHz
+\ MOV #7,Y \ 2 tLOW time complement @ 16MHz
+\ MOV #18,Y \ 2 tLOW time complement @ 24MHz
+ CALL #I2C_PLS \ _| |_ SCL pulse with SDA bit test
+ 0<> IF BIS #2,SR \ l if Nack, force Z=1 ==> StopCond
+ ELSE SUB.B #1,T \ else dec count
+ THEN \ l
+\ --------------------------------\
+\ I2C_Master_CheckCountDown \ count=0 or Nack received
+\ --------------------------------\
+ 0= IF \ count reached or Nack
+\ --------------------------------\
+\ I2C_Master_StopCond \
+\ --------------------------------\ before releasing SCL
+ BIS.B #SMMSDA,&I2CSMM_DIR \ l force SDA low
+ MOV #1,Y \ 2 l tLOW time complement @ 8MHz
+\ MOV #7,Y \ 2 tLOW time complement @ 16MHz
+\ MOV #18,Y \ 2 tLOW time complement @ 24MHz
+ CALL #R11_I2C \ _ wait 4 us
+ BIC.B #SMMSCL,&I2CSMM_DIR \ _| release SCL (high with pull up resistor)
+ SUB.B T,&I2CM_BUF \ 4 refresh buffer length
+ MOV #5,Y \ 2 tSU:STO time 8 MHz complement
+\ MOV #15,Y \ 2 tSU:STO time 16MHz complement
+\ MOV #25,Y \ 2 tSU:STO time 24MHz complement
+ CALL #R11_I2C \ _ wait tSU:STO
+ BIC.B #SMMSDA,&I2CSMM_DIR \ _| release SDA (high with pull up resistor)
+\ ----------------------------\
+\ I2C_Master_Endof \
+\ ----------------------------\
+\ Restart I2C_Slave_Int \ if any
+\ ----------------------------\
+\ BIC #1,&UCB0CTLW0 \ restart eUSCI_B
+\ BIS.B #SMM_BUS,&I2CSMM_SEL1 \ reenable I2C I/O
+\ ----------------------------\
+ MOV @RSP+,PC \ ====>
+\ --------------------------------\
+ THEN \
+\ --------------------------------\
+ MOV.B #8,W \ 1 l prepare 8 bits transaction
+ BIT.B #1,&I2CS_ADR \ 3 l I2C_Master Read/write bit test
+ 0= IF \ 2 l write flag test
+\ ============================\
+\ I2C_Master_TX \
+\ ============================\
+ MOV.B @S+,X \ 2 l next byte to TX
+ BEGIN \
+ MOV #1,Y \ 2 tHD\STA time =8MHz complement
+\ MOV #2,Y \ 2 tHD\STA time =16MHz complement
+\ MOV #13,Y \ 2 tHD\STA time =24MHz complement
+ CALL #I2C_BTX \ l send one bit
+ SUB.B #1,W \ l count of bits
+ 0= UNTIL \ l
+ BIC.B #SMMSDA,&I2CSMM_DIR \ 5 l release SDA high before 9th bit
+ ELSE \ l
+\ ============================\
+\ I2C_Master_RX: \ here, SDA is indetermined, SCL is strech low by master
+\ ============================\
+ BIC.B #SMMSDA,&I2CSMM_DIR \ 5 l _ After ACK we must release SDA
+ BEGIN \
+ MOV #3,Y \ 2 tLOW time complement @ 8 MHz
+\ MOV #15,Y \ 2 tLOW time complement @ 16MHz
+\ MOV #24,Y \ 2 tLOW time complement @ 24MHz
+ CALL #I2C_PLS \ _| |_ SCL pulse with SDA bit test
+ ADDC.B X,X \ 1 l C <-- X <--- C ; C flag = SDA
+ SUB #1,W \ 1 l count of bits
+ 0= UNTIL \ 2 l
+ MOV.B X, 0(S) \ 3 l store RX byte in buffer
+ ADD #1,S \ 1 l
+\ ----------------------------\
+\ Compute RX Ack/Nack \
+\ ----------------------------\
+ CMP #1,T \ 1 l here, SDA is released by slave = Nack
+ 0<> IF \ 2
+ BIS.B #SMMSDA,&I2CSMM_DIR \ 4 l send Ack if byte count <> 1
+ THEN \ l
+ THEN \
+AGAIN \ l
+ENDASM \
+ \
+
+\ ------------------------------\
+CODE START \
+\ ------------------------------\
+\ init PORTA (P2:P1) (complement) when reset occurs all I/O are set in input with resistors pullup
+BIC.B #SMM_BUS,&I2CSMM_OUT \ preset SDA + SCL output low
+BIC.B #SMM_BUS,&I2CSMM_REN \ SDA + SCL pullup/down disable
+\ ------------------------------\
+ LO2HI
+ ." Type STOP to stop :-)"
+ LIT recurse is WARM \ insert this routine between COLD and WARM...
+ (WARM) ; \ ...and continue with WARM
+ \
+
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+RST_HERE
+
+\ ---------------------------------------------------------------------------------------------------------------------\
+\ SCL clock generation, timing, and test of data(s) number are made by I2C_Master.
+\ slave can strech SCL low after Start Condition and after any bit.
+
+\ address Ack/Nack is generated by the slave on SDA line (released by the master)
+\ Two groups of eight addresses (000xxxy and 1111xxxy) are not allowed (reserved)
+\ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
+\ data Ack/Nack are generated by the receiver (master or slave) on SDA line
+\ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
+\ Stop or restart conditions must be generated by master after a Nack bit.
+\ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK _
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/Wx_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X___/
+\ _____ _ _ _ _ _ _ _ _ _ _ ___
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |stoP Condition
+\
+\ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK ___
+\ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X \____...
+\ _____ _ _ _ _ _ _ _ _ _ _ ____
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |reStart Condition
+\
+\ tHIGH : SCL high time
+\ tLOW : SCL low time
+\ tBUF : SDA high time between Stop and Start conditions
+\ tHD:STA : Start_Condition SCL high time after SDA is low
+\ tSU:STO : Stop_Condition SCL high time before SDA rise
+\ tSU:STA : Start_Condition SCL high time before SDA fall
+\ tHD:DAT : SDA data change time after SCL is low
+\ the SDA line must be strobe just after SCL is high
+\ the SDA data must be change just after SCL is low
+\ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
+\ tLOW = tSU:STA = tBUF = 4,7µs
+\ tHD:DAT <= 3,45 µs
+\ -------------------------------------------------------------------------------------------------------------------\
--- /dev/null
+\ ---------------
+\ IR_RC5_P1.2.f
+\ ---------------
+RST_STATE \ to rub out this test with <reset> or RST_STATE or COLD
+
+\ Copyright (C) <2014> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ FORTH driver for IR remote compatible with the PHILIPS RC5 protocol, with select new/repeated command
+\ target : see IR_RC5.pat
+
+\ Send to terminal the RC5 new command.
+\ Press S1 to send also RC5 repeated command.
+
+
+\ HERE \ general minidump, part 1
+
+\ --------------------------------------------------------------------------------------------
+\ MSP-EXP430FR5969 driver for IR_RC5 receiver TSOP32236 wired on Px.y input \ 65 words, 24.5ms
+\ --------------------------------------------------------------------------------------------
+
+\ layout : see config.pat file for defining I/O
+
+\ ******************************\
+ASM RC5_INT \ wake up on Px.RC5 change interrupt
+\ ******************************\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : TOS,IP,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ******************************\
+\ RC5_FirstStartBitHalfCycle: \
+\ ******************************\ division in TA0CTL (SMCLK/1,SMCLK/1,SMCLK/2,SMCLK/4,SMCLK/8)
+\ MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 125kHz, 1MHz, 2MHZ, 4MHZ, 8MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register ( 250kHZ, 2MHz, 4MHZ, 8MHZ, 16MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register ( 375kHz, 3MHz, 6MHZ, 12MHZ, 24MHZ)
+\ MOV #3,&TA0EX0 \ predivide by 4 in TA0EX0 register ( 500kHZ, 4MHz, 8MHZ, 16MHZ)
+\ MOV #4,&TA0EX0 \ predivide by 6 in TA0EX0 register ( 625kHz, 5MHz, 10MHZ, 20MHZ)
+\ MOV #5,&TA0EX0 \ predivide by 6 in TA0EX0 register ( 750kHz, 6MHz, 12MHZ, 24MHZ)
+\ MOV #6,&TA0EX0 \ predivide by 7 in TA0EX0 register ( 875kHz, 7MHz, 14MHZ, 28MHZ)
+\ MOV #7,&TA0EX0 \ predivide by 8 in TA0EX0 register ( 1MHz, 8MHz, 16MHZ, 32MHZ)
+MOV #1778,X \ RC5_Period * 1us
+\ MOV #222,X \ RC5_Period * 8us (SMCLK/1 and first column above)
+MOV #14,W \ count of loop
+BEGIN \
+\ ******************************\
+\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period
+\ ******************************\ |
+\ MOV #%1000100100,&TA0CTL \ (re)start timer_A | SMCLK/1 time interval,free running,clear TA0_IFG and TA0R
+\ MOV #%1002100100,&TA0CTL \ (re)start timer_A | SMCLK/2 time interval,free running,clear TA0_IFG and TA0R
+\ MOV #%1010100100,&TA0CTL \ (re)start timer_A | SMCLK/4 time interval,free running,clear TA0_IFG and TA0R
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4 cycle
+ BEGIN CMP Y,&TA0R \3 wait 1/2 + 3/4 cycle = n+1/4 cycles
+ U>= UNTIL \2
+\ ******************************\
+\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first
+\ ******************************\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+ ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present
+ BEGIN \ |
+ MOV &TA0R,X \3 | X grows from n+1/4 up to n+3/4 cycles
+ CMP Y,X \1 | cycle time out of bound ?
+ U>= ?GOTO FW1 \2 ^ | yes: quit on truncated RC5 message
+ BIT.B #RC5,&IR_IFG \3 | | n+1/2 cycles edge is always present
+ 0<> UNTIL \2 | |
+REPEAT \ ----> loop back --+ | with X = new RC5_period value
+\ ******************************\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+SUB #2,PSP \
+MOV TOS,0(PSP) \ save TOS before use
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0
+MOV.B IP,TOS \ TOS = C5 C4 C3 C2 C1 C0 1 0
+RRUM #2,TOS \ TOS = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #BIT14,IP \ test /C6 bit in IP
+0= IF BIS #BIT6,TOS \ set C6 bit in TOS
+THEN \ TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ -- BASE RC5_code
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+RRUM #4,IP \5 new toggle bit = IP(13) ==> IP(9)
+XOR SR,IP \ (new XOR old) Toggle bits
+BIT #UF1,IP \ repeated RC5_command ?
+0= ?GOTO FW2 \ yes, RETI without UF1 change
+\ ******************************\
+XOR #UF1,0(RSP) \ 5 toggle bit memory
+FW2 \ endof repeated RC5_command : RETI without UF1 change
+FW1 \ endof truncated RC5 message
+BIC #$30,&TA0CTL \ stop timer_A0
+BIC #$F8,0(RSP) \ 4 SCG1,SCG0,OSCOFF,CPUOFF and GIE are OFF in retiSR to force LPM0_LOOP despite pending interrupt
+RETI \ 5 for system OFF / 1 sec. ==> 1mA * 5us = 5nC + 6,5uA
+ENDASM
+ \
+
+
+\ ------------------------------
+\ Start process RC5 part
+\ ------------------------------
+\ ------------------------------\
+CODE START \
+\ ------------------------------\
+\ init PORTX (P2:P1) (complement) default I/O are input with pullup resistors
+ BIC.B #RC5,&PIRIFG \ P1IFG.2 clear int flag for TSOP32236 (after IES select)
+ BIS.B #RC5,&PIRIE \ P1IE.2 enable interrupt for TSOP32236
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ init interrupt vectors \
+\ ------------------------------\
+ MOV #INT_RC5,&IR_Vec \ init Px vector interrupt
+\ ------------------------------\
+ LO2HI
+ ." RC5toLCD is running. Type STOP to quit"
+ LIT RECURSE IS WARM \ insert this starting routine between COLD and WARM...
+ (WARM) ; \ ...and continue with WARM (very, very usefull after COLD or RESET !:-)
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+\ HERE OVER - DUMP \ general minidump, part 2
+
+RST_HERE \
+
+
+
+\ --------------------------------------------------\
+\ PHILIPS IR REMOTE RC5/RC6 protocol \
+\ --------------------------------------------------\
+\ first half bit = no light, same as idle state
+\ second half bit : 32 IR-light pulses of 6,944us,light ON/off ratio = 1/3
+
+\ |<------32 IR light pulses = second half of first start bit ------->|
+\ |_ _ _ _ _ _ _ _ _ _ _ _|
+\ ...____| |___| |___| |___| |___| |___| |...| |___| |___| |___| |___| |___| |____________________________________...
+\ | |
+\
+
+
+\ at the output of IR receiver TSOPxxx during the first start bit :
+
+\ ...idle state ->|<----- first half bit ------>|<- second half bit (IR light) ->|
+\ ..._____________|_____________________________| |_________...
+\ | | |
+\ | | |
+\ | |________________________________|
+
+\ 32 cycles of 27,777us (36kHz) = 888,888 us
+\ one bit = 888,888 x 2 = 1778 us.
+
+
+
+\ 14 bits of active message = 24.889 ms
+\ + 50 bits of silent (idle) = 88.888 ms
+\ = RC5 message = 113.792 ms
+
+\
+\ RC5_message on IR LIGHT \ idle state = light off
+
+\ 89ms>|<--------------------------------------------------24.889 ms-------------------------------------------------->|<88,
+\ | |
+\ | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Tog | A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | C0 |
+\ | | | | | | | | | | | | | | |
+\ 1 1 1 1 0 0 1 1 1 1 1 1 1 1
+\ ___ ___ ___ _______ ___ ___ ___ ___ ___ ___ ___ ___ ___
+\ ^ | ^ | ^ | ^ | | | ^ | ^ | ^ | ^ | ^ | ^ | ^ | ^ |
+\ idle____| |___| |___| |___| v___| v_______| |___| |___| |___| |___| |___| |___| |___| |____
+\
+\
+\ notice that each cycle contains its bit value preceded by its complement
+
+
+
+
+\ the same RC5_message inverted at the output of IR receiver : idle state = 1
+\
+\ | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Tog | A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | C0 |
+\ | | | | | | | | | | | | | | |
+\ 1 1 1 1 0 0 1 1 1 1 1 1 1 1
+\ idle_____ ___ ___ ___ ___ _______ ___ ___ ___ ___ ___ ___ ___ __idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | | | |
+\ v___| v___| v___| v_______| |___| v___| v___| v___| v___| v___| v___| v___| v___|
+\ I R R R R R R R R R R R R R
+\
+\ notice that each cycle contains its bit value followed by its complement
+
+
+
+
+\ principe of the driver : 13 samples at 1/4 period and Resynchronise (R) on 1/2 period (two examples)
+
+\ 0,888 ms
+\ |<->|<--------------------------------routine time = 12 3/4 cycles = 22.644 ms--------------------------->|
+\ | | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Toggle| A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | |C0 |
+\ | | | | | | | | | | | | | | | |
+\ 1 1 1 1 0 0 1 1 1 1 1 1 1 | 1
+\ idle_____ _s_ _s_ _s_ ___ _____s_ _s_ _s_ _s_ _s_ _s_ _s_ _s_ __idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | | | |
+\ v___| v___| v___| v_____s_| |_s_| v___| v___| v___| v___| v___| v___| v___| v___|
+\ I R R R R R R R R R R R R ^ ^
+\ samples : 1 2 3 4 5 6 4 8 9 10 11 12 13 | |
+\ | |
+\ I I
+\ 0,888 ms
+\ |<->|<--------------------------------routine time = 12 3/4 cycles = 22.644 ms--------------------------->|
+\ | | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Toggle| A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | |C0 |
+\ | | | | | | | | | | | | | | | |
+\ 1 1 1 1 0 0 1 1 1 1 1 1 1 | 1
+\ idle_____ _s_ _s_ ___ _o_ _o___s_ _s_ _s_ _s_ _s_ _s_ _s_ ______idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | ^
+\ v___| v_o_| v_o_| v_o___s_| |_s_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o___s_|
+\ I R R R R R R R R R R R R ^
+\ samples : 1 2 3 4 5 6 7 8 9 10 11 12 13|
+\ |
+\ i !
+\ good ! but we have too many RC5_Int...
+
+
+
+
+\ So, to avoid these RC5_Int after end : 13+1=14 samples, then the result is shifted one to right (two examples)
+
+\ 0,888 ms
+\ |<->|<--------------------------------routine time = 13 3/4 cycles = 24.447 ms----------------------------------->|
+\ | | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Toggle| A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | C0 | |
+\ | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
+\ | | | | | | | | | | | | | | | |
+\ idle_____ _s_ _s_ _s_ _o_ _o___s_ _s_ _s_ _s_ _s_ _s_ _s_ _s_ _s_idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | | | |
+\ v___| v_o_| v_o_| v_o___s_| |_s_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_|
+\ I i R i R i R R i R R i R i R i R i R i R i R i R i
+\ samples : 1 2 3 4 5 6 7 8 9 10 11 12 13 14
+\
+\
+\ 0,888 ms
+\ |<->|<--------------------------------routine time = 13 3/4 cycles = 24.447 ms----------------------------------->|
+\ | | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Toggle| A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | C0 | |
+\ | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | |
+\ | | | | | | | | | | | | | | | |
+\ idle_____ _s_ _s_ _s_ _o_ _o___s_ _s_ _s_ _s_ _s_ _s_ _s_ _o___s_idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | ^
+\ v___| v_o_| v_o_| v_o___s_| |_s_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o___s_|
+\ I i R i R i R R i R R i R i R i R i R i R i R R
+\ samples : 1 2 3 4 5 6 7 8 9 10 11 12 13 14
+
+
+\ S = Wake up on RC5_Int at 1/2 cycle : clear and start timer
+\ I = first interruption
+\ i = useless RC5_Int (not periodic) at 4/4 cycle
+\ s = sample RC5_intput at (1/2+3/4) = 5/4 cycle = n+1/4 cycles and clear useless RC5_Int
+\ R = usefull (periodic) RC5_Int at 6/4 cycle = n+1/2 cycles : cycle value = timer value then clear it and restart it
+\ o = RC5_Int time out at 7/4 cycle = n+3/4 cycles, used to detect (samples<14) truncated RC5_message
+
+\ see also : http://www.sbprojects.com/knowledge/ir/rc5.php
+\ http://laurent.deschamps.free.fr/ir/rc5/rc5.htm
+\ Code RC5 : http://en.wikipedia.org/wiki/RC-5
+
--- /dev/null
+\ IR_RC5_to_I2CF_Soft_Master.f
+
+\ Copyright (C) <2016> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+\ --------------------------------------\
+\ example of App running under interrupt
+\ --------------------------------------\
+\ FORTH driver for IR remote compatible with the PHILIPS RC5 protocol, with select new/repeated command
+
+\ target : any MSP430FRxxxx @ 8Mhz
+
+\ prerequisites : your launchpad is wired as described in launchpad.pat file : UART0, Soft_Master(SDA,SCL), IR_RC5 parts.
+\ FastForth runs @ 8MHz
+\ add 3k3 pull up resistors on SDA and SCL lines.
+
+\ usage : create a logical network drive ( a: b: ...as you want) from your local copy of Gitlab FAST FORTH
+\ with scite.exe open this file MSP430-FORTH\IR_RC5_to_I2CF_Soft_Master.f,
+\ select "tools" menu, "preprocess" item 1 (CTRL+0),
+\ a dialog box asks you for 4 parameters $(1) to $(4),
+\ in the 2th param. field, type your launchpad to select the launchpad.pat to be used : for example MSP_EXP430FR5969,
+\ result : the word START starts the app that runs under LPMx.
+
+\ to recover the console input (i.e. to quit LPMx), type a space. Then you can enter a command, for example STOP.
+
+\ select one initial state :
+WIPE \ to suppress any previous app
+\ RST_STATE \ to conserve the previous app protected against <reset>
+\ PWR_STATE \ to conserve the previous app protected against POWER OFF
+NOECHO \ comment if an error occurs, to detect it with new download
+
+\ HERE \ uncomment for a dump, part 1
+ \
+
+
+
+\ -------------------------------------------------------------------------------------------------------------------\
+\ I2CF Soft MASTER driver, FAST MODE, 8MHz
+\ -------------------------------------------------------------------------------------------------------------------\
+
+VARIABLE I2CS_ADR \ low(I2CS_ADR) = slave I2C address with RW flag, high(I2CS_ADR) = RX buffer,data0
+2 ALLOT \ data1,data2
+VARIABLE I2CM_BUF \ low(I2CM_BUF) = RX or TX lentgh, high(I2CM_BUF) = TX buffer,data0
+2 ALLOT \ data1,data2
+ \
+
+\ ------------------------------\
+ASM I2C_MTX \ MASTER TX \ shared code for address and TX data
+\ ------------------------------\
+BEGIN \
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #MSDA,&I2CSM_DIR \ 4 l yes : SDA as input ==> SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #MSDA,&I2CSM_DIR \ 4 l no : SDA as output ==> SDA low
+ THEN \ l _
+ BIC.B #MSCL,&I2CSM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \ 14/16~l
+ BIT.B #MSCL,&I2CSM_IN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h _
+ BIS.B #MSCL,&I2CSM_DIR \ 4 h v_ SCL as output : force SCL low
+ SUB #1,W \ 1 l count of bits
+0= UNTIL \ 2 l
+BIC.B #MSDA,&I2CSM_DIR \ 5 l _ SDA as input : release SDA high to prepare read Ack/Nack
+RET
+ENDASM \
+ \
+
+\ ******************************\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ******************************\
+ASM INT_RC5 \ wake up on P1.2 change interrupt \ IP,TOS,W,X,Y are free for use
+\ ------------------------------\
+BIC #$F8,0(RSP) \ SCG1,SCG0,OSCOFF,CPUOFF and GIE are OFF in retiSR to force LPMx_LOOP with pending interrupt
+\ BIC #$B8,0(RSP) \ {SCG1,OSCOFF,CPUOFF,GIE}=OFF after RETI to force goto label "LPMx_LOOP" with any pending interrupt
+\ ------------------------------\
+\ define LPM mode for ACCEPT \ uncomment a line
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : IP,TOS,W,X,Y, TA0 timer, TA0R register
+\ \ out : TOS = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ------------------------------\
+\ RC5_FirstStartBitHalfCycle: \
+\ ------------------------------\
+MOV #0,&TA0EX0 \ predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
+\ MOV #1,&TA0EX0 \ predivide by 2 in TA0EX0 register (16 MHZ)
+\ MOV #2,&TA0EX0 \ predivide by 3 in TA0EX0 register (24 MHZ)
+MOV #1778,X \ RC5_Period in us
+MOV #14,W \ count of loop
+BEGIN \
+\ ------------------------------\
+\ RC5_TopSynchro: \ <--- loop back ---+ with readjusted RC5_Period
+\ ------------------------------\ | here, we are just after 1/2 RC5_cycle
+ MOV #%1011100100,&TA0CTL \ (re)start timer_A | SMCLK/8 : 2us time interval,free running,clear TA0_IFG and TA0R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ Y=1/2 ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4
+\ RC5_Wait_1_1/4 \ wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle+1
+ BEGIN CMP Y,&TA0R \ CMP &TA0R with 3/4 cycle value
+ 0= UNTIL \
+\ ------------------------------\
+\ RC5_Sample: \ at 5/4 cycle, we can sample RC5_input, ST2/C6 bit first
+\ ------------------------------\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC IP,IP \ C_flag <-- IP(15):IP(0) <-- C_flag
+ MOV &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> IP = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> IP = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+0<> WHILE \ ----> out of loop ----+
+\ RC5_compute_7/4_Time_out: \ |
+ ADD X,Y \ | out of bound = 7/4 period
+\ RC5_WaitHalfCycleP1.2_IFG: \ |
+ BEGIN \ |
+ CMP Y,&TA0R \ | TA0R = 5/4 cycle test
+ 0>= IF \ | if cycle time out of bound
+ BIC #$30,&TA0CTL \ | stop timer_A0
+ RETI \ | then quit to do nothing
+ THEN \ |
+\ ------------------------------\ |
+ BIT.B #RC5,&IR_IFG \ ^ | test P1.2_IFG
+ 0<> UNTIL \ | |
+ MOV &TA0R,X \ | | get new RC5_period value
+REPEAT \ ----> loop back --+ |
+\ ------------------------------\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ------------------------------\
+MOV #$30,&TA0CTL \ stop timer_A0
+RLAM #1,IP \ IP = x /C6 Tg A4 A3 A2|A1 A0 C5 C4 C3 C2 C1 C0 1 0
+\ ******************************\
+\ Only New_RC5_Command ADD_ON \ use SR(9) bit as toggle bit
+\ ******************************\
+MOV @RSP,X \ retiSR(9) = old RC5 toggle bit
+RLAM #4,X \ retiSR(11,10,9)= X(11,10,9) --> X(15,14,13)
+XOR IP,X \ (new XOR old) Toggle bit (13)
+BIT #BIT13,X \ X(13) = New_RC5_command
+0= IF
+ RETI \ case of repeated RC5_command : RETI without SR(9) change
+THEN \
+XOR #UF1,0(RSP) \ change Toggle bit memory, User Flag 1 = SR(9)
+\ ******************************\
+\ RC5_ComputeNewRC5word \
+\ ******************************\
+MOV.B IP,S \ S = C5 C4 C3 C2 C1 C0 0 0
+RRUM #2,S \ S = 0 0 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_ComputeC6bit \
+\ ******************************\
+BIT #BIT14,IP \ test /C6 bit in IP
+0= IF
+ BIS #BIT6,S \ set C6 bit in S
+THEN \ S = 0 C6 C5 C4 C3 C2 C1 C0
+\ ******************************\
+\ RC5_CommandByteIsDone \ RC5_code --
+\ ******************************\
+\ ------------------------------\
+\ Prepare I2C_MASTER \
+\ ------------------------------\
+SWPB S \ 1 high byte = data
+ADD #1,S \ 1 low byte = count
+MOV S,&I2CM_BUF \ 3
+MOV #%0010100,&I2CS_ADR \ MSP-EXP430FRxxx I2C slave address
+\ ------------------------------\
+\ echo code to terminal option \
+\ ------------------------------\
+\ SUB #2,PSP
+\ MOV TOS,0(PSP)
+\ MOV.B S,TOS
+\ LO2HI
+\ cr ." $" HEX 2 U.R
+\ HI2LO
+
+\ ==================================\
+\ CODE I2C_M \ fast I2C soft Master, only 8 MHz
+\ ==================================\
+\ \ in I2CS_ADR/I2CM_BUF as RX/TX buffer requested by I2CS_ADR(0(0))
+\ \ I2CS_ADR(0) = I2C_Slave_addr&R/w
+\ \ I2CM_BUF(0) = TX/RX count of datas
+\ \ I2CM_BUF(0) = 0 ==> send only I2C address
+\ \ used S BUF ptr
+\ \ T datas countdown
+\ \ W bits countdown
+\ \ X data
+\ \ out I2CSLA_ADR & (R/W) unCHNGd
+\ \ S = BUF PTR pointing on first data not exCHNGd
+\ \ T = count+1 of TX/RX datas exCHNGd
+\ \ I2CS_ADR(0) = unCHNGd
+\ \ I2CM_BUF(0) = count of data not exCHNGd (normally = 0)
+\ \ I2CM_BUF(0) = -1 <==> Nack on address
+\ ----------------------------------\
+\ I2C_MR_DC_ListenBeforeStart: \ test if SCL & SDA lines are idle (high)
+\ ----------------------------------\
+BIC.B #M_BUS,&I2CSM_DIR \ SDA & SCL pins as input
+BIC.B #M_BUS,&I2CSM_OUT \ preset output LOW for SDA & SCL pins
+MOV #2,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 8 MHz
+\ MOV #4,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 16 MHz
+\ MOV #6,T \ I2C_MR_DC_Wait_Start_Loop = 8 µs @ 24 MHz
+BEGIN \
+ BEGIN \
+ BEGIN \
+ BIT.B #MSCL,&I2CSM_IN \ 4 P1DIR.3 SCL high ?
+ 0<> UNTIL \ 2
+ BIT.B #MSDA,&I2CSM_IN \ 4 P1IN.2 SDA high ?
+ 0<> UNTIL \ 2
+ SUB #1,T \ 1
+0= UNTIL \ 2 here the I2C bus is idle
+\ ----------------------------------\
+\ I2C_Master_Start_Cond: \ here, SDA and SCL are in idle state
+\ ----------------------------------\
+BIS.B #MSDA,&I2CSM_DIR \ 4 l force SDA as output (low)
+MOV #I2CM_BUF,W \ 2 h W=buffer out
+MOV.B @W+,T \ 2 h T=datas countdown
+MOV #I2CS_ADR,S \ 2 h S=buffer in
+MOV.B @S+,X \ 2 h X=Slave address to TX
+BIT.B #1,X \ 1 h test I2C R/w flag
+0= IF \ 2 h if write
+ MOV W,S \ 2 h S= buffer out ptr
+THEN \ S= buffer ptr
+BIS.B #MSCL,&I2CSM_DIR \ 4 h force SCL as output (low)
+\ ----------------------------------\
+\ I2C_Master_Start_EndOf: \
+\ ----------------------------------\
+\ I2C_Master_Send_address \ may be SCL is held low by slave
+\ ----------------------------------\
+ADD #1,T \ 1 l to add address in count
+MOV #8,W \ 1 l prepare 8 bit Master writing
+CALL #I2C_MTX \ 21 l to send address
+\ ----------------------------------\
+\ I2C_Master_Loop_Data \
+\ ----------------------------------\
+BEGIN \ 4 l here ack/nack is received/transmitted
+\ --------------------------------\ l
+\ Master TX/RX ACK/NACK \
+\ --------------------------------\ l _
+ BIC.B #MSCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #MSCL,&I2CSM_IN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h
+ BIT.B #MSDA,&I2CSM_IN \ 3 h _ get SDA
+ BIS.B #MSCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+\ --------------------------------\ l
+\ I2C_Master_Loop_Data \
+\ --------------------------------\
+ 0<> IF BIS #Z,SR \ 5 l if Nack (TX), force Z=1 ==> StopCond
+ ELSE SUB.B #1,T \ 3 l else dec count
+ THEN \ l
+\ --------------------------------\
+\ I2C_Master_CheckCountDown \ count=0 (TX) or Nack received
+\ --------------------------------\
+ 0= IF \ 2 l send stop
+\ ----------------------------\
+\ Send Stop \
+\ ----------------------------\ _
+ BIS.B #MSDA,&I2CSM_DIR \ 4 l v_ SDA as output ==> SDA low
+ SUB.B T,&I2CM_BUF \ 4 l _ refresh buffer length and reach tSU:STO
+ BIC.B #MSCL,&I2CSM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \
+ BIT.B #MSCL,&I2CSM_IN \ 3 h SCL released ?
+ 0<> UNTIL \ 2 h
+ BIC.B #MSDA,&I2CSM_DIR \ 4 h _^ SDA as input ==> SDA high with pull up resistor
+\ MOV @RSP+,PC \ RET ====>
+ RETI \
+ THEN \
+ MOV.B #8,W \ 1 l prepare 8 bits transaction
+ BIT.B #1,&I2CS_ADR \ 3 l I2C_Master Read/write bit test
+ 0= IF \ 2 l write flag test
+\ ============================\
+\ I2C_Master_TX \
+\ ============================\
+ MOV.B @S+,X \ 2 l next byte to transmit
+ CALL #I2C_MTX \ l to send data
+ ELSE \ l
+\ ============================\
+\ I2C_Master_RX: \ here, SDA is indetermined, SCL is strech low by master
+\ ============================\
+ BIC.B #MSDA,&I2CSM_DIR \ 5 l _ After ACK we must release SDA
+ BEGIN \
+\ ------------------------\ _
+\ send bit \ SCL _| |_
+\ ------------------------\ _
+ BIC.B #MSCL,&I2CSM_DIR \ 4 l _^ release SCL (high)
+ BEGIN \ 14/16~l
+ BIT.B #MSCL,&I2CSM_IN \ 3 h test if SCL is released
+ 0<> UNTIL \ 2 h
+ BIT.B #MSDA,&I2CSM_IN \ 4 h _ get SDA
+ BIS.B #MSCL,&I2CSM_DIR \ 4 h v_ SCL as output : force SCL low 13~
+ ADDC.B X,X \ 1 l C <-- X <--- C
+ SUB #1,W \ 1 l count of bits
+ 0= UNTIL \ 2 l
+ MOV.B X,0(S) \ 3 l store byte in buffer
+ ADD #1,S \ 1 l
+\ ----------------------------\
+\ Compute Ack Or Nack \ here, SDA is released by slave, SCL is strech low by master
+\ ----------------------------\
+ CMP.B #1,T \
+ 0<> IF \ 2 l
+ BIS.B #MSDA,&I2CSM_DIR \ 5 l yes : send Ack
+ THEN \
+ THEN \
+AGAIN \ 2 l
+ENDASM \
+ \
+
+
+\ ------------------------------\
+CODE START \
+\ ------------------------------\
+\ init PORT M_BUS (complement) \ when reset occurs all I/O are set in input with resistors pullup
+BIC.B #M_BUS,&I2CSM_OUT \ preset SDA + SCL output low
+BIC.B #M_BUS,&I2CSM_REN \ SDA + SCL pullup/down disable
+\ ------------------------------\
+\ init PORT IR (complement) default I/O are input with pullup resistors
+BIS.B #RC5,&IR_IE \ enable interrupt for TSOP32236
+BIC.B #RC5,&IR_IFG \ clear int flag for TSOP32236
+\ ------------------------------\
+\ init interrupt vectors \
+\ ------------------------------\
+MOV #INT_RC5,&IR_Vec \ init IR vector interrupt
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+LO2HI
+." RC5toI2CF_Master is running. Type STOP to quit"
+\ NOECHO \ uncomment to run this app without terminal connexion
+LIT RECURSE IS WARM \ insert this starting routine between COLD and WARM...
+(WARM) ; \ ...and continue with WARM (very, very usefull after COLD or RESET !:-)
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+ECHO
+
+\ DUP HERE SWAP - DUMP \ uncomment for a dump, part 2
+ \
+
+\ select one end state :
+RST_HERE \ this app is protected against POWER OFF, <reset>, COLD, ...and STOP that executes COLD.
+\ PWR_HERE \ this app is protected only againt POWER OFF
+\ nothing \ this app is volatile !
+
+
+\ all lines beyond START command are ignored
+
+\ --------------------------------------------------\
+\ PHILIPS IR REMOTE RC5/RC6 protocol \
+\ --------------------------------------------------\
+\ first half bit = no light, same as idle state
+\ second half bit : 32 IR-light pulses of 6,944us,light ON/off ratio = 1/3
+
+\ |<------32 IR light pulses = second half of first start bit ------->|
+\ |_ _ _ _ _ _ _ _ _ _ _ _|
+\ ...____| |___| |___| |___| |___| |___| |...| |___| |___| |___| |___| |___| |____________________________________...
+\ | |
+\
+
+
+\ at the output of IR receiver TSOPxxx during the first start bit :
+
+\ ...idle state ->|<----- first half bit ------>|<- second half bit (IR light) ->|
+\ ..._____________|_____________________________| |_________...
+\ | | |
+\ | | |
+\ | |________________________________|
+
+\ 32 cycles of 27,777us (36kHz) = 888,888 us
+\ one bit = 888,888 x 2 = 1778 us.
+
+
+
+\ 14 bits of active message = 24.889 ms
+\ + 50 bits of silent (idle) = 88.888 ms
+\ = RC5 message = 113.792 ms
+
+\
+\ RC5_message on IR LIGHT \ idle state = light off
+
+\ 89ms>|<--------------------------------------------------24.889 ms-------------------------------------------------->|<88,
+\ | |
+\ | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Tog | A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | C0 |
+\ | | | | | | | | | | | | | | |
+\ 1 1 1 1 0 0 1 1 1 1 1 1 1 1
+\ ___ ___ ___ _______ ___ ___ ___ ___ ___ ___ ___ ___ ___
+\ ^ | ^ | ^ | ^ | | | ^ | ^ | ^ | ^ | ^ | ^ | ^ | ^ |
+\ idle____| |___| |___| |___| v___| v_______| |___| |___| |___| |___| |___| |___| |___| |____
+\
+\
+\ notice that each cycle contains its bit value preceded by its complement
+
+
+
+
+\ the same RC5_message inverted at the output of IR receiver : idle state = 1
+\
+\ | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Tog | A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | C0 |
+\ | | | | | | | | | | | | | | |
+\ 1 1 1 1 0 0 1 1 1 1 1 1 1 1
+\ idle_____ ___ ___ ___ ___ _______ ___ ___ ___ ___ ___ ___ ___ __idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | | | |
+\ v___| v___| v___| v_______| |___| v___| v___| v___| v___| v___| v___| v___| v___|
+\ I R R R R R R R R R R R R R
+\
+\ notice that each cycle contains its bit value followed by its complement
+
+
+
+
+\ principe of the driver : 13 samples at 1/4 period and Resynchronise (R) on 1/2 period (two examples)
+
+\ 0,888 ms
+\ |<->|<--------------------------------routine time = 12 3/4 cycles = 22.644 ms--------------------------->|
+\ | | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Toggle| A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | |C0 |
+\ | | | | | | | | | | | | | | | |
+\ 1 1 1 1 0 0 1 1 1 1 1 1 1 | 1
+\ idle_____ _s_ _s_ _s_ ___ _____s_ _s_ _s_ _s_ _s_ _s_ _s_ _s_ __idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | | | |
+\ v___| v___| v___| v_____s_| |_s_| v___| v___| v___| v___| v___| v___| v___| v___|
+\ S R R R R R R R R R R R R ^ ^
+\ samples : 1 2 3 4 5 6 4 8 9 10 11 12 13 | |
+\ | |
+\ I I
+\ 0,888 ms
+\ |<->|<--------------------------------routine time = 12 3/4 cycles = 22.644 ms--------------------------->|
+\ | | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Toggle| A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | |C0 |
+\ | | | | | | | | | | | | | | | |
+\ 1 1 1 1 0 0 1 1 1 1 1 1 1 | 1
+\ idle_____ _s_ _s_ ___ _o_ _o___s_ _s_ _s_ _s_ _s_ _s_ _s_ ______idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | ^
+\ v___| v_o_| v_o_| v_o___s_| |_s_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o___s_|
+\ S R R R R R R R R R R R R ^
+\ samples : 1 2 3 4 5 6 7 8 9 10 11 12 13|
+\ |
+\ I
+\ good ! but we have too many of RC5_Int...
+
+
+
+
+\ So, to avoid these RC5_Int after end : 13+1=14 samples, then the result is shifted one to right (two examples)
+
+\ 0,888 ms
+\ |<->|<--------------------------------routine time = 13 3/4 cycles = 24.447 ms----------------------------------->|
+\ | | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Toggle| A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | C0 | |
+\ | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
+\ | | | | | | | | | | | | | | | |
+\ idle_____ _s_ _s_ _s_ _o_ _o___s_ _s_ _s_ _s_ _s_ _s_ _s_ _s_ _s_idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | | | |
+\ v___| v_o_| v_o_| v_o___s_| |_s_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_|
+\ S i R i R i R R i R R i R i R i R i R i R i R i R i
+\ samples : 1 2 3 4 5 6 7 8 9 10 11 12 13 14
+\
+\
+\ 0,888 ms
+\ |<->|<--------------------------------routine time = 13 3/4 cycles = 24.447 ms----------------------------------->|
+\ | | | | | | | | | | | | | | | |
+\ | ST1 | ST2/C6| Toggle| A4 | A3 | A2 | A1 | A0 | C5 | C4 | C3 | C2 | C1 | C0 | |
+\ | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | |
+\ | | | | | | | | | | | | | | | |
+\ idle_____ _s_ _s_ ___ _o_ _o___s_ _s_ _s_ _s_ _s_ _s_ _s_ _o___s_idle
+\ | | | | | | | ^ | ^ | | | | | | | | | | | | | ^
+\ v___| v_o_| v_o_| v_o___s_| |_s_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o_| v_o___s_|
+\ S i R i R i R R i R R i R i R i R i R i R i R R
+\ samples : 1 2 3 4 5 6 7 8 9 10 11 12 13 14
+
+
+\ S = Wake up on RC5_Int at 1/2 cycle : clear and start timer
+\ i = useless RC5_Int (not periodic) at 4/4 cycle
+\ s = sample RC5_intput at (1/2+3/4) = 5/4 cycle = 1/4 cycle+1 and clear useless RC5_Int
+\ R = usefull (periodic) RC5_Int at 6/4 cycle = 1/2 cycle+1 : cycle value = timer value then clear it and restart it
+\ o = RC5_Int time out at 7/4 cycle = 3/4 cycle+1, used to detect (samples<14) truncated RC5_message
+
+\ see also : http://www.sbprojects.com/knowledge/ir/rc5.php
+\ http://laurent.deschamps.free.fr/ir/rc5/rc5.htm
+\ Code RC5 : http://en.wikipedia.org/wiki/RC-5
+
+
+\ ---------------------------------------------------------------------------------------------------------------------\
+\ SCL clock generation, timing, and test of data(s) number are made by I2C_Master.
+\ slave can strech SCL low after Start Condition and after any bit.
+\
+\ address Ack/Nack is generated by the slave on SDA line (released by the master)
+\ Two groups of eight addresses (000xxxy and 1111xxxy) are not allowed (reserved)
+\ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
+\ data Ack/Nack are generated by the receiver (master or slave) on SDA line
+\ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
+\ Stop or restart conditions must be generated by master after a Nack bit.
+\ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions.
+\
+\
+\ first byte = address + R/W flag | byte data (one, for example)
+\ __ _____ _____ _..._ _____ __R__ _NAK_ _____ _____ _..._ _____ _____ _NAK_ _
+\ SDA \____/_MSB_R9_____R9_..._R9_LSB_R9__R10__x_ACK_x_MSB_R9_____R9_..._R9_____R9_LSB_R9_ACK_R9___/
+\ _____ _ _ _ _ _ _ _ _ _ _ ___
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |SSL |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |stoP Condition
+\
+\ first byte = address + R/W flag | byte data (one, for example)
+\ __ _____ _____ _..._ _____ __R__ _NAK_ _____ _____ _..._ _____ _____ _NAK_ ___
+\ SDA \____/_MSB_R9_____R9_..._R9_LSB_R9__R10__x_ACK_x_MSB_R9_____R9_..._R9_____R9_LSB_R9_ACK_R9 \____...
+\ _____ _ _ _ _ _ _ _ _ _ _ ____
+\ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
+\ ^ ^ ^ ^ ^ ^ ^
+\ | |SSL |SSL |SSL |SSL |SSL |
+\ | |
+\ |Start Condition |reStart Condition
+\
+\ SSL : Slave can strech SCL low
+\ tHIGH : SCL high time
+\ tLOW : SCL low time
+\ tBUF : SDA high time between Stop and Start conditions
+\ tHD:STA : Start_Condition SCL high time after SDA is low
+\ tSU:STO : Stop_Condition SCL high time before SDA rise
+\ tSU:STA : Start_Condition SCL high time before SDA fall
+\ tHD:DAT : SDA data change time after SCL is low
+\ the SDA line must be strobe just after SCL is high
+\ the SDA data must be change just after SCL is low
+\ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
+\ tLOW = tSU:STA = tBUF = 4,7µs
+\ tHD:DAT <= 3,45 µs
+\ -------------------------------------------------------------------------------------------------------------------\
+
--- /dev/null
+\ ------------------------------
+\ MSP430FR5xxx_LCD_20.f
+\ ------------------------------
+RST_STATE
+\ NOECHO
+\ Copyright (C) <2014> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY\ without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+
+
+\ driver for LCD 2x20 characters display with 4 bits data interface
+\ without usage of an auxiliary 5V to feed the Vo of LCD
+\ without potentiometer to adjust the LCD contrast
+\ LCD contrast software adjustable by 2 switches
+\ TB0.2 current consumption ~ 500 uA
+
+\ layout : see config.pat file for defining I/O
+
+\ GND <-------+---0V0----------> 1 LCD_Vss
+\ VCC >------ | --3V6-----+----> 2 LCD_Vdd
+\ | |
+\ |___ 470n ---
+\ ^ | ---
+\ / \ BAT54 |
+\ --- |
+\ 100n | 2k2 |
+\ TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+\ -------------------------> 4 LCD_RW
+\ -------------------------> 5 LCD_RW
+\ -------------------------> 6 LCD_EN
+\ <------------------------> 11 LCD_DB4
+\ <------------------------> 12 LCD_DB5
+\ <------------------------> 13 LCD_DB5
+\ <------------------------> 14 LCD_DB7
+
+\ Sw1 <--- LCD contrast + (finger :-)
+\ Sw2 <--- LCD contrast - (finger \-)
+
+
+
+\ ------------------------------\
+CODE 20_us \ n -- n * 20 us
+\ ------------------------------\
+BEGIN \ 3 cycles loop + 6~
+\ MOV #5,W \ 3 MCLK = 1 MHz
+\ MOV #23,W \ 3 MCLK = 4 MHz
+ MOV #51,W \ 3 MCLK = 8 MHz
+\ MOV #104,W \ 3 MCLK = 16 MHz
+\ MOV #158,W \ 3 MCLK = 24 MHz
+ BEGIN \ 3 cycles loop ==> 3 * W / F us = 100 us - 1 @ 8 MHz
+ SUB #1,W \ 1
+ 0= UNTIL \ 2
+ SUB #1,TOS \ 1
+0= UNTIL \ 2
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ENDCODE
+ \
+
+\ ------------------------------\
+CODE TOP_LCD \ LCD Sample
+\ ------------------------------\ if write : %xxxxWWWW --
+\ \ if read : -- %0000RRRR
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+0= IF \ write LCD bits pattern
+ AND #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ENDCODE
+ \
+
+\ ------------------------------\
+CODE LCD_W \ byte -- write byte
+\ ------------------------------\
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %xxxxLLLL %HHHHLLLL
+ RRUM #4,TOS \ -- %xxxxLLLL %xxxxHHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+ COLON
+ TOP_LCD 2 20_us \ write high nibble first
+ TOP_LCD 2 20_us ;
+ \
+
+\ ------------------------------\
+CODE LCD_R \ -- byte read byte
+\ ------------------------------\
+ BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+ COLON
+ TOP_LCD 2 20_us \ read high nibble first
+ TOP_LCD 2 20_us
+ HI2LO \ -- %0000HHHH %0000LLLL
+ MOV @RSP+,IP
+ MOV @PSP+,W \ W = high nibble
+ RLAM #4,W \ -- %0000LLLL W = %HHHH0000
+ ADD.B W,TOS
+ MOV @IP+,PC
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_WrF \ func -- Write Fonction
+\ ------------------------------\
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_W
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_RdS \ -- status Read Status
+\ ------------------------------\
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ JMP LCD_R
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_WrC \ char -- Write Char
+\ ------------------------------\
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_W
+ENDCODE
+ \
+\ ------------------------------\
+CODE LCD_RdC \ -- char Read Char
+\ ------------------------------\
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+ JMP LCD_R
+ENDCODE
+ \
+\ ------------------------------\
+\ : LCD_Clear $01 LCD_WrF 80 20_us ; \ bad init !
+: LCD_Clear $01 LCD_WrF 100 20_us ;
+ \
+\ ------------------------------\
+: LCD_Home $02 LCD_WrF 80 20_us ;
+ \
+\ ------------------------------\
+\ : LCD_Entry_set $04 OR LCD_WrF ;
+\ : LCD_Display_Ctrl $08 OR LCD_WrF ;
+\ : LCD_Display_Shift $10 OR LCD_WrF ;
+\ : LCD_Fn_Set $20 OR LCD_WrF ;
+\ : LCD_CGRAM_Set $40 OR LCD_WrF ;
+\ : LCD_Goto $80 OR LCD_WrF ;
+
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+\ LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 180uA | default mode
+\ LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | | same mode as LPM0
+\ LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 60uA |
+\ LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 10uA | 32768Hz XTAL is running
+\ LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 6uA |
+\ -------------+------+------+------+------++---+---+---+---+---------+
+
+\ ******************************\
+ASM WDT_Int \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ******************************\
+BIC #$F8,0(RSP) \ set CPU ON and GIE OFF in retiSR
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+BIT.B #SW2,&SW2_IN \ test switch S2
+0= IF \ case of switch S2 pressed
+ CMP #34,&TB0CCR2 \ maxi Ton = 34/40 & VDD=3V6 ==> LCD_Vo = -2V2
+ U< IF
+ ADD #1,&TB0CCR2 \ action for switch S2 (P2.5) : 78 mV / increment
+ THEN
+ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #7,&TB0CCR2 \ mini Ton = 6/40 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&TB0CCR2 \ action for switch S1 (P2.6) : -78 mV / decrement
+ THEN \
+ THEN \
+THEN \
+RETI \ CPU is ON, GIE is OFF
+ENDASM \
+ \
+
+
+\ ------------------------------\
+CODE START \
+\ ------------------------------\
+\ TB0CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up mode
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ --------------------------------\\
+\ TB0CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ TB0CCRx \$3D{2,4,6,8,A,C,E}
+\ TB0EX0 \$3E0
+\ ------------------------------\
+\ set TimerB to make 50kHz PWM \
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (1 MHZ) (25 kHz PWM)
+\ ------------------------------\
+\ MOV #%1000010100,&TB0CTL \ SMCLK/1, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (4 MHZ)
+\ ------------------------------\
+ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+ MOV #0,&TB0EX0 \ predivide by 1 in TB0EX0 register (8 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #1,&TB0EX0 \ predivide by 2 in TB0EX0 register (16 MHZ)
+\ ------------------------------\
+\ MOV #%1010010100,&TB0CTL \ SMCLK/4, up mode, clear timer, no int
+\ MOV #2,&TB0EX0 \ predivide by 3 in TB0EX0 register (24 MHZ)
+\ ------------------------------\
+ MOV #40,&TB0CCR0 \ 40*0.5us=20us (40us @ 1MHz)
+\ ------------------------------\
+\ set TimerB to generate LCD_V0 via TB0.2 and P1.5/P2.2
+\ ------------------------------\
+ MOV #%1100000,&TB0CCTL2 \ output mode = set/reset \ clear CCIFG
+\ MOV #20,&TB0CCR2 \ contrast adjust : 20/40 ==> LCD_Vo = -1V1|+3V6 (Vcc=3V6)
+ MOV #25,&TB0CCR2 \ contrast adjust : 25/40 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ------------------------------\
+\ ------------------------------\
+\ WDT interval init part \
+\ ------------------------------\
+\ MOV #$5A5E,&WDTCTL \ init WDT Vloclk source 10kHz /2^9 (50 ms), interval mode
+ MOV #$5A3D,&WDTCTL \ init WDT ACLK source 32.768kHz /2^13 (250 ms), interval mode
+\ MOV #$5A5D,&WDTCTL \ init WDT Vloclk source 10kHz /2^13 (800 ms), interval mode
+ BIS #1,&SFRIE1 \ enable WDT interval mode interrupt in SFRIE
+\ ------------------------------\
+\ init interrupt vectors
+\ ------------------------------\
+ MOV #WDT_Int,&WDT_Vec \ init WDT interval vector interrupt
+\ ------------------------------\
+\ init PORTA (P2:P1) (complement)
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL0 \ SEL0.2 TB0.2
+\ ------------------------------\
+\ init PORTB (P4:P3) (complement)
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ------------------------------\
+\ init PORTJ (PJ) (complement)
+ BIS.B #LCD_DB,&LCD_DB_DIR \ PJDIR.(0-3) as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ PJREN.(0-3) LCD_Data pullup/down disable
+\ ------------------------------\
+\ define LPM mode for ACCEPT \
+\ ------------------------------\
+\ MOV #LPM4,&LPM_MODE \ with MSP430FR59xx
+\ MOV #LPM2,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2
+\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value
+\ ------------------------------\
+\ Init LCD
+ LO2HI
+ $3E8 20_us \ 1- wait 20 ms
+ $03 TOP_LCD \ 2- send DB5=DB4=1
+ $CD 20_us \ 3- wait 4,1 ms
+ $03 TOP_LCD \ 4- send again DB5=DB4=1
+ 5 20_us \ 5- wait 0,1 ms
+ $03 TOP_LCD \ 6- send again again DB5=DB4=1
+ 2 20_us \ wait 40 us = LCD cycle
+ $02 TOP_LCD \ 7- send DB5=1 DB4=0
+ 2 20_us \ wait 40 us = LCD cycle
+ $28 LCD_WrF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ $08 LCD_WrF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_Clear \ 10- "LCD_Clear"
+ $06 LCD_WrF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ $0C LCD_WrF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+ ['] LCD_WrC IS EMIT \ ' EMIT redirected to LCD_WrC
+ CR ." I love you"
+ ['] (CR) IS CR \ ' (CR) is CR
+ ['] (EMIT) IS EMIT \ ' (EMIT) is EMIT
+ ." xxxx_to_LCD is running. Type STOP to quit"
+ LIT recurse is WARM \ insert this starting routine between COLD and WARM...
+\ NOECHO \ uncomment to run this app without terminal connexion
+ (WARM) ; \ ...and continue with WARM
+ \
+
+: STOP \ stops multitasking, must to be used before downloading app
+ ['] (WARM) IS WARM \ remove START app from FORTH init process
+ ECHO COLD \ reset CPU, interrupt vectors, and start FORTH
+;
+ \
+
+PWR_HERE \ set here the power_on dictionnary
set howtoread=%1
set readfile=%2
-if c%1==c set howtoread=MAIN
-if c%2==c set readfile=DUMP
+if "%1" == "" set howtoread=MAIN
+if "%2" == "" set readfile=DUMP
-A:\prog\MSP430Flasher\msp430flasher -m SBW2 -r [%readfile%_%howtoread%.hex,%howtoread%] -z [VCC=3000]
-A:\prog\srecord\srec_cat %readfile%_%howtoread%.HEX -intel -output %readfile%_%howtoread%.bin -Binary
-A:\prog\HxD\HxD.exe" %readfile%_%howtoread%.bin
\ No newline at end of file
+A:\prog\MSP430Flasher\msp430flasher -m SBW2 -r [%readfile%_%howtoread%.txt,%howtoread%] -z [VCC=3000]
+::A:\prog\srecord\srec_cat %readfile%_%howtoread%.HEX -intel -output %readfile%_%howtoread%.bin -Binary
+::A:\prog\HxD\HxD.exe" %readfile%_%howtoread%.bin
+
+pause
MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh
; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz
; =====================================
- MOV #2,X
+; MOV #2,X
.ELSEIF FREQUENCY = 1
; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh
; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz
; =====================================
- MOV #4,X
+; MOV #4,X
.ELSEIF FREQUENCY = 2
; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh
; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz
; =====================================
- MOV #8,X
+; MOV #8,X
.ELSEIF FREQUENCY = 4
; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah
; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz
; =====================================
- MOV #16,X
+; MOV #16,X
.ELSEIF FREQUENCY = 8
; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz
; works with cp2102 and pl2303TA
; =====================================
- MOV #32,X
+; MOV #32,X
.ELSEIF FREQUENCY = 16
MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h
; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz
; =====================================
- MOV #64,X
+; MOV #64,X
.ELSEIF
.error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
.ENDIF
.IFDEF LF_XTAL
-; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value)
+; LFXIN : P4.1, LFXOUT : P4.2
+ MOV #0600h,&PBSEL0 ; SEL0 for only P4.1,P4.2
+; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value)
MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV
.ELSE
MOV #0010h,&CSCTL3 ; FLL select REFCLOCK, FLLREFDIV=0
BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV with preserving a pending request for DEEP_RST
- CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
- JZ ClockWaitX ; yes : wait 600ms to stabilize power source
- .word 0359h ; no : RRUM #1,X --> wait still 300 ms...
- ; ...because FLL lock time = 280 ms
-
-ClockWaitX MOV #50000,Y ;
-ClockWaitY SUB #1,Y ; 3 cycles loop
- JNZ ClockWaitY ; 50000x3 = 150000 cycles delay = 150ms @ 1MHz
- SUB #1,X ;
- JNZ ClockWaitX ;
+; CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
+; JZ ClockWaitX ; yes : wait 600ms to stabilize power source
+; .word 0359h ; no : RRUM #1,X --> wait still 300 ms...
+; ; ...because FLL lock time = 280 ms
+;
+; ClockWaitX MOV #50000,Y ;
+; ClockWaitY SUB #1,Y ; 3 cycles loop
+; JNZ ClockWaitY ; 50000x3 = 150000 cycles delay = 150ms @ 1MHz
+; SUB #1,X ;
+; JNZ ClockWaitX ;
+WAITFLL BIT #300,&CSCTL7 ; wait FLL lock
+ JNZ WAITFLL
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
-; ----------------------------------------------------------------------
-
- .IFDEF LF_XTAL
-; LFXIN : P4.1, LFXOUT : P4.2
- MOV #0600h,&PBSEL0 ; SEL0 for only P4.1,P4.2
- .ENDIF
+++ /dev/null
-@1800
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04 43 4F 4C 44 00 B2 40 04 A5 20 01 B2 40 88 5A
CC 01 B2 D0 00 08 04 02 B2 D3 06 02 B2 43 02 02
B2 40 00 01 24 02 B2 40 FF FE 22 02 B2 D0 FF FE
26 02 B2 43 42 02 B2 D3 46 02 B2 43 62 02 B2 D3
66 02 F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43
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08 C4 34 40 14 C4 B2 40 0A 00 DA 21 B2 43 AC 21
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18 53 82 48 08 18 B2 40 81 00 00 05 B2 40 11 00
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39 48 2A 48 09 5A 1A 52 C2 21 09 9A 03 24 7E 9A
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-03 58 4F 52 84 12 D8 D6 00 E0 00 D8 05 58 4F 52
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-D8 D6 00 F0 1A D8 05 41 4E 44 2E 42 84 12 D8 D6
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-C4 21 92 53 C2 21 3E 40 2C 00 B0 12 2A C4 EE C9
-1A CB C0 C5 08 CE 8A D6 5A D9 0A 4E 3E 4F 1A 83
-2A 92 CA 2F 8A 10 5A 06 6F 3F 92 D8 04 52 52 43
-4D 00 84 12 2E D9 50 00 6C D9 04 52 52 41 4D 00
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-2E D9 50 02 88 D9 04 52 52 55 4D 00 84 12 2E D9
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-02 55 3C 00 85 12 00 2C D0 D9 03 55 3E 3D 85 12
-00 28 C6 D9 03 30 3C 3E 85 12 00 24 E4 D9 02 30
-3D 00 85 12 00 20 84 C8 02 49 46 00 1A 42 C4 21
-8A 4E 00 00 A2 53 C4 21 0E 4A 30 4D DA D9 04 54
-48 45 4E 00 1A 42 C4 21 08 4E 3E 4F 09 48 29 53
-0A 89 0A 11 3A 90 00 02 68 2F 88 DA 00 00 30 4D
-A2 D7 04 45 4C 53 45 00 1A 42 C4 21 BA 40 00 3C
-00 00 A2 53 C4 21 2F 83 8F 4A 00 00 E3 3F 0E DA
-05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C4 21
-2A 83 0A 89 0A 11 3A 90 00 FE 47 3B 3A F0 FF 03
-08 DA 89 48 00 00 A2 53 C4 21 30 4D 26 D8 05 41
-47 41 49 4E 87 12 A2 D9 56 DA 2A C4 00 00 05 57
-48 49 4C 45 87 12 FC D9 6E C4 2A C4 B2 D9 06 52
-45 50 45 41 54 00 87 12 A2 D9 56 DA 14 DA 2A C4
-00 00 03 4A 4D 50 87 12 FA CD A2 D9 56 DA 2A C4
-3E B0 00 10 03 20 3E E0 00 04 30 4D 3E 90 00 34
-06 28 03 24 3E 40 00 34 30 4D 3E 40 00 38 30 4D
-00 00 04 3F 4A 4D 50 00 87 12 C0 DA FA CD 6E C4
-56 DA 2A C4 F6 DA 3D 41 08 4E 3E 4F 2A 48 0A 93
-04 20 98 42 C4 21 00 00 30 4D 88 43 00 00 A4 3F
-BC D8 03 42 57 31 84 12 F4 DA 00 00 12 DB 03 42
-57 32 84 12 F4 DA 00 00 1E DB 03 42 57 33 84 12
-F4 DA 00 00 36 DB 3D 41 1A 42 C4 21 28 4E 08 93
-08 20 BA 4F 00 00 A2 53 C4 21 8E 4A 00 00 3E 4F
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-34 DB 00 00 5A DB 03 46 57 32 84 12 34 DB 00 00
-66 DB 03 46 57 33 84 12 34 DB 00 00 72 DB 04 47
-4F 54 4F 00 87 12 A2 D9 FA CD EE CB 2A C4 E2 DA
-05 3F 47 4F 54 4F 87 12 C0 DA FA CD EE CB 2A C4
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+34 20 92 53 C2 21 B0 12 7E D6 0E 93 04 20 B2 40
+00 03 BC 21 27 3C 1E 93 04 20 B2 40 10 03 BC 21
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+3E 40 28 00 B0 12 7E D6 B0 12 B6 D6 D5 23 3D 40
+04 CE 30 4D A0 C8 04 52 45 54 49 00 87 12 34 C4
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+2E 42 84 12 36 D8 40 B0 1C D9 03 42 49 43 84 12
+36 D8 00 C0 2A D9 05 42 49 43 2E 42 84 12 36 D8
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+A2 53 C4 21 2F 83 8F 4A 00 00 E3 3F 6C DB 05 55
+4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C4 21 2A 83
+0A 89 0A 11 3A 90 00 FE 47 3B 3A F0 FF 03 08 DA
+89 48 00 00 A2 53 C4 21 30 4D 84 D9 05 41 47 41
+49 4E 87 12 00 DB B4 DB 2A C4 00 00 05 57 48 49
+4C 45 87 12 5A DB 78 C4 2A C4 10 DB 06 52 45 50
+45 41 54 00 87 12 00 DB B4 DB 72 DB 2A C4 00 00
+03 4A 4D 50 87 12 F6 CD 00 DB B4 DB 2A C4 3E B0
+00 10 03 20 3E E0 00 04 30 4D 3E 90 00 34 06 28
+03 24 3E 40 00 34 30 4D 3E 40 00 38 30 4D 00 00
+04 3F 4A 4D 50 00 87 12 1E DC F6 CD 78 C4 B4 DB
+2A C4 54 DC 3D 41 08 4E 3E 4F 2A 48 0A 93 04 20
+98 42 C4 21 00 00 30 4D 88 43 00 00 A4 3F 1A DA
+03 42 57 31 84 12 52 DC 00 00 70 DC 03 42 57 32
+84 12 52 DC 00 00 7C DC 03 42 57 33 84 12 52 DC
+00 00 94 DC 3D 41 1A 42 C4 21 28 4E 08 93 08 20
+BA 4F 00 00 A2 53 C4 21 8E 4A 00 00 3E 4F 30 4D
+8E 43 00 00 61 3F 00 00 03 46 57 31 84 12 92 DC
+00 00 B8 DC 03 46 57 32 84 12 92 DC 00 00 C4 DC
+03 46 57 33 84 12 92 DC 00 00 D0 DC 04 47 4F 54
+4F 00 87 12 00 DB F6 CD 16 CC 2A C4 40 DC 05 3F
+47 4F 54 4F 87 12 1E DC F6 CD 16 CC 2A C4
@FFE2
-1C D3 1C D3 1C D3 1C D3 1C D3 92 C8 1C D3 1C D3
-1C D3 1C D3 1C D3 1C D3 1C D3 1C D3 1C D3
+8C D4 8C D4 8C D4 8C D4 8C D4 BA C8 8C D4 8C D4
+8C D4 8C D4 8C D4 8C D4 8C D4 8C D4 8C D4
q
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr4133 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
@1800
-10 00 6A C6 C0 5D 80 04 FD FF 18 00 5C D9 12 D2
-2A C6 3C C6 00 00 00 00
+10 00 92 C6 C0 5D 80 04 05 00 18 00 CA DA 82 D3
+52 C6 64 C6 00 00 00 00
@1DAA
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
03 4C 49 54 2F 83 8F 4E 00 00 3E 4D 30 4D 24 C2
03 44 55 50 2F 83 8F 4E 00 00 30 4D 00 00 04 3F
44 55 50 00 0E 93 F6 23 30 4D 40 C2 04 44 52 4F
-50 00 3E 4F 30 4D 00 00 04 53 57 41 50 00 2A 4F
-8F 4E 00 00 0E 4A 30 4D 00 00 04 4F 56 45 52 00
-2F 83 8F 4E 00 00 1E 4F 02 00 30 4D 68 C2 03 52
-4F 54 2A 4F 8F 4E 00 00 1E 4F 02 00 8F 4A 02 00
-30 4D 4E C2 02 3E 52 00 0E 12 3E 4F 30 4D 8E C2
-02 52 3E 00 2F 83 8F 4E 00 00 3E 41 30 4D B0 C2
-02 52 40 00 2F 83 8F 4E 00 00 2E 41 30 4D 8F 4E
-FE FF 0E 4F 2F 83 30 4D 5C C2 05 44 45 50 54 48
-8F 4E FE FF 3E 40 80 1C 0E 8F 2F 83 0E 11 30 4D
-00 00 01 40 2E 4E 30 4D F2 C2 01 21 BE 4F 00 00
-3E 4F 30 4D 00 00 02 43 40 00 6E 4E 30 4D 06 C3
-02 43 21 00 3A 4F CE 4A 00 00 3E 4F 30 4D 00 00
-01 2B 3E 5F 30 4D 30 C2 01 2D 3A 4F 0A 8E 0E 4A
-30 4D FA C2 03 41 4E 44 3E FF 30 4D 7A C2 02 4F
-52 00 3E DF 30 4D 00 00 03 58 4F 52 3E EF 30 4D
-3E C3 06 4E 45 47 41 54 45 00 3E E3 1E 53 30 4D
-34 C3 03 41 42 53 0E 93 F8 33 30 4D 00 00 02 30
-3D 00 1E 83 0E 7E 30 4D 6E C3 02 30 3C 00 0E 5E
-0E 7E 3E E3 30 4D 00 00 01 3D 3E 8F 07 20 3E 43
-30 4D 88 C3 01 3C 3A 4F 0A 8E F9 3B 0E 43 30 4D
-A4 C2 01 3E 3E 8F F3 3B 0E 43 30 4D 00 00 02 55
+50 00 3E 4F 30 4D 00 00 03 4E 49 50 2F 53 30 4D
+00 00 04 53 57 41 50 00 2A 4F 8F 4E 00 00 0E 4A
+30 4D 68 C2 04 4F 56 45 52 00 8F 4E FE FF 2E 4F
+2F 83 30 4D 72 C2 03 52 4F 54 2A 4F 8F 4E 00 00
+1E 4F 02 00 8F 4A 02 00 30 4D 4E C2 02 3E 52 00
+0E 12 3E 4F 30 4D 96 C2 02 52 3E 00 2F 83 8F 4E
+00 00 3E 41 30 4D B8 C2 02 52 40 00 2F 83 8F 4E
+00 00 2E 41 30 4D 5C C2 05 44 45 50 54 48 8F 4E
+FE FF 3E 40 80 1C 0E 8F 2F 83 0E 11 30 4D 00 00
+01 40 2E 4E 30 4D F0 C2 01 21 BE 4F 00 00 3E 4F
+30 4D 00 00 02 43 40 00 6E 4E 30 4D 04 C3 02 43
+21 00 FE 4F 00 00 1F 53 3E 4F 30 4D 00 00 01 2B
+3E 5F 30 4D 30 C2 01 2D 3E 8F 3E E3 1E 53 30 4D
+F8 C2 03 41 4E 44 3E FF 30 4D 84 C2 02 4F 52 00
+3E DF 30 4D 00 00 03 58 4F 52 3E EF 30 4D 3C C3
+06 4E 45 47 41 54 45 00 E8 3F 32 C3 03 41 42 53
+0E 93 E3 33 30 4D D8 C2 04 44 41 42 53 00 3E F3
+06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 30 4D
+00 00 02 30 3D 00 1E 83 0E 7E 30 4D 82 C3 02 30
+3C 00 0E 5E 0E 7E 3E E3 30 4D 8E C3 02 30 3E 00
+1E 93 05 34 0B 3C 00 00 01 3D 3E 8F 07 20 3E 43
+30 4D A8 C3 01 3C 3A 4F 0A 8E F9 3B 0E 43 30 4D
+AC C2 01 3E 3E 8F F3 3B 0E 43 30 4D 00 00 02 55
3C 00 3A 4F 0A 8E EB 2B 0E 43 30 4D 2D 4D 30 4D
-0E 93 3E 4F FB 27 2D 53 30 4D 39 40 00 80 39 8F
-08 4E 3E 4F 08 59 19 15 30 4D 81 5E 00 00 3E 4F
-32 B0 00 01 EB 27 2D 53 21 52 30 4D 91 53 00 00
-F7 3F AE C3 06 55 4E 4C 4F 4F 50 00 F5 3F 00 00
-01 49 2F 83 8F 4E 00 00 2E 41 1E 81 02 00 30 4D
-20 C3 01 4A 2F 83 8F 4E 00 00 1E 41 04 00 1E 81
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+3C 00 85 12 00 30 00 00 02 55 3C 00 85 12 00 2C
+F8 D8 03 55 3E 3D 85 12 00 28 EE D8 03 30 3C 3E
+85 12 00 24 0C D9 02 30 3D 00 85 12 00 20 84 C6
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+0E 4A 30 4D 02 D9 04 54 48 45 4E 00 1A 42 C4 1D
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+68 2F 88 DA 00 00 30 4D CA D6 04 45 4C 53 45 00
+1A 42 C4 1D BA 40 00 3C 00 00 A2 53 C4 1D 2F 83
+8F 4A 00 00 E3 3F 36 D9 05 55 4E 54 49 4C 3A 4F
+08 4E 3E 4F 19 42 C4 1D 2A 83 0A 89 0A 11 3A 90
+00 FE 47 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53
+C4 1D 30 4D 4E D7 05 41 47 41 49 4E 87 12 CA D8
+7E D9 2A C2 00 00 05 57 48 49 4C 45 87 12 24 D9
+78 C2 2A C2 DA D8 06 52 45 50 45 41 54 00 87 12
+CA D8 7E D9 3C D9 2A C2 00 00 03 4A 4D 50 87 12
+A0 CB CA D8 7E D9 2A C2 3E B0 00 10 03 20 3E E0
+00 04 30 4D 3E 90 00 34 06 28 03 24 3E 40 00 34
+30 4D 3E 40 00 38 30 4D 00 00 04 3F 4A 4D 50 00
+87 12 E8 D9 A0 CB 78 C2 7E D9 2A C2 1E DA 3D 41
+08 4E 3E 4F 2A 48 0A 93 04 20 98 42 C4 1D 00 00
+30 4D 88 43 00 00 A4 3F E4 D7 03 42 57 31 84 12
+1C DA 00 00 3A DA 03 42 57 32 84 12 1C DA 00 00
+46 DA 03 42 57 33 84 12 1C DA 00 00 5E DA 3D 41
+1A 42 C4 1D 28 4E 08 93 08 20 BA 4F 00 00 A2 53
+C4 1D 8E 4A 00 00 3E 4F 30 4D 8E 43 00 00 61 3F
+00 00 03 46 57 31 84 12 5C DA 00 00 82 DA 03 46
+57 32 84 12 5C DA 00 00 8E DA 03 46 57 33 84 12
+5C DA 00 00 9A DA 04 47 4F 54 4F 00 87 12 CA D8
+A0 CB C0 C9 2A C2 0A DA 05 3F 47 4F 54 4F 87 12
+E8 D9 A0 CB C0 C9 2A C2
@FFCE
-C6 D0 C6 D0 C6 D0 C6 D0 C6 D0 C6 D0 C6 D0 C6 D0
-C6 D0 C6 D0 C6 D0 C6 D0 C6 D0 C6 D0 C6 D0 C6 D0
-C6 D0 6A C6 C6 D0 C6 D0 C6 D0 C6 D0 C6 D0 C6 D0
-C6 D0
+36 D2 36 D2 36 D2 36 D2 36 D2 36 D2 36 D2 36 D2
+36 D2 36 D2 36 D2 36 D2 36 D2 36 D2 36 D2 36 D2
+36 D2 92 C6 36 D2 36 D2 36 D2 36 D2 36 D2 36 D2
+36 D2
q
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr5739 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
; PORT3 usage
; PORT4 usage
-; switch S1
-SWITCHIN .set P4IN ; port
-S1 .set 020h ; P4.5
-
-; P4.6 as LED1 output low
+; P4.5 - switch S1
+; P4.6 - LED1 red
.IFDEF TERMINALCTSRTS
+++ /dev/null
-@1800
-10 00 C8 4B 40 1F 00 60 FD FF 18 00 9C 60 6A 57
-B2 4B BA 4B 00 00 00 00
-@1DAA
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00
-@4400
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-00 00 01 40 2E 4E 30 4D F2 44 01 21 BE 4F 00 00
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-02 43 21 00 3A 4F CE 4A 00 00 3E 4F 30 4D 00 00
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-3E 44 2F 83 8F 4E 00 00 7A 3F F4 45 03 55 4D 2A
-A2 4F C0 04 82 4E C8 04 9F 42 E4 04 00 00 1E 42
-E6 04 30 4D 28 45 02 4D 2A 00 A2 4F C2 04 82 4E
-C8 04 9F 42 E4 04 00 00 1E 42 E6 04 30 4D 8C 46
-06 55 4D 2F 4D 4F 44 00 3A 4F 2C 4F 08 43 39 40
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-0A 6A F7 2B 0A 8E 12 D3 F7 3F 8F 4A 00 00 0E 48
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-0E 93 02 34 3E E3 1E 53 8F 93 00 00 08 34 BF E3
-02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 1D 15
-3D 40 26 47 D1 3F 28 47 1C 17 0B 93 04 34 BF E3
-00 00 9F 53 00 00 0B EC 0B 93 02 34 3E E3 1E 53
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-A8 44 82 46 B4 44 4C 47 78 46 2A 44 A6 46 03 4D
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-05 43 45 4C 4C 53 0E 5E 30 4D F0 47 05 43 45 4C
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-30 4D FC 47 04 43 48 41 52 00 87 12 4C 46 24 4D
-D6 48 0A 45 2A 44 00 00 86 5B 43 48 41 52 5D 00
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-04 46 49 4C 4C 00 39 4F 3A 4F 09 93 05 24 CA 4E
-00 00 1A 53 19 83 FB 23 3E 4F 30 4D 8A 48 03 48
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-02 23 53 00 87 12 20 4A 5A 4A 2D 83 09 93 E0 23
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-76 4C 2A 44 9E 49 01 2E 3E B0 00 80 DD 27 2F 83
-3E 43 EC 3F 7E 4A 04 48 45 52 45 00 2F 83 8F 4E
-00 00 1E 42 C4 1D 30 4D 62 46 05 41 4C 4C 4F 54
-82 5E C4 1D 3E 4F 30 4D 6A 4A 02 43 2C 00 1A 42
-C4 1D CA 4E 00 00 92 53 C4 1D 3E 4F 30 4D 2F 83
-8F 4E 00 00 B0 12 B2 4B 92 B3 DC 05 FD 27 1E 42
-CC 05 B0 12 BA 4B 30 4D 30 40 3E 4B 06 4B 05 28
-4B 45 59 29 18 42 CC 05 EA 3F 16 49 03 4B 45 59
-30 40 64 4B 1A 4B 06 41 43 43 45 50 54 00 3C 40
-00 4C 3B 40 D0 4B 2D 15 0A 4E 2E 4F 0A 5E 3B 40
-0D 00 3C 40 20 00 3D 40 F4 4B 92 B3 DC 05 05 24
-18 42 CC 05 38 90 0A 00 04 20 21 53 39 40 C2 4B
-4D 15 B2 40 11 00 CE 05 30 41 B2 40 13 00 CE 05
-30 41 12 D2 0A 18 FD 3F 21 52 3A 17 58 42 CC 05
-48 9B F3 27 48 9C 06 2C 78 92 0E 20 2E 9F 0C 24
-1E 83 05 3C 0E 9A 03 24 CE 48 00 00 1E 53 82 48
-CE 05 30 4D F6 4B 2D 83 92 B3 DC 05 FD 27 E6 23
-B2 40 18 00 0A 18 3E 8F 3D 41 30 4D 5E 4B 06 28
-45 4D 49 54 29 00 08 4E 3E 4F A2 B3 DC 05 FD 27
-E6 3F D8 4A 04 45 4D 49 54 00 30 40 16 4C 24 4C
-04 45 43 48 4F 00 B2 40 82 48 EE 4B 30 4D F6 4A
-06 4E 4F 45 43 48 4F 00 B2 40 30 4D EE 4B 30 4D
-0E 4C 04 28 43 52 29 00 2F 83 8F 4E 00 00 3E 40
-0D 00 E3 3F 2A 4B 02 43 52 00 30 40 58 4C 8C 4A
-05 53 50 41 43 45 2F 83 8F 4E 00 00 3E 40 20 00
-D4 3F 70 4C 06 53 50 41 43 45 53 00 0E 93 09 24
-0D 12 3D 40 98 4C EF 3F 9A 4C 2D 83 1E 83 EB 23
-3D 41 3E 4F 30 4D B4 4A 04 54 59 50 45 00 0E 93
-95 24 2A 4F 8F 5E 00 00 0E 4A 87 12 CA 45 02 46
-0A 45 2A 4C EC 45 BE 4C 2A 44 2F 82 8F 4E 02 00
-7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 30 4D 84 4C
-82 53 22 00 87 12 34 44 CA 4C 2C 4F 34 44 22 00
-24 4D F4 4C 3D 41 6E 4E 1E 83 82 5E C4 1D 3E 4F
-92 B3 C4 1D A2 63 C4 1D 30 4D 40 4C 82 2E 22 00
-87 12 E4 4C 34 44 AE 4C 2C 4F 2A 44 00 00 04 57
-4F 52 44 00 3C 40 BE 1D 39 4C 3A 4C 09 5A 3A 5C
-28 4C 09 9A 19 24 7E 9A FC 27 1A 83 3B 40 60 00
-C8 4C 00 00 09 9A 0C 24 7C 4A 4E 9C 09 24 18 53
-4B 9C F6 2F 7C 90 7B 00 F3 2F 7C 80 20 00 F0 3F
-1A 82 C0 1D 82 4A C2 1D 1E 42 C4 1D 08 8E CE 48
-00 00 30 4D 50 49 04 46 49 4E 44 00 2F 83 0C 4E
-65 4C 74 40 80 00 3B 40 CA 1D 3E 4B 0E 93 1E 24
-58 4C 01 00 78 F0 1E 00 0E 58 2E 53 1E 4E FE FF
-0E 93 F3 27 09 4E 78 49 48 C4 48 95 F7 23 0A 4C
-1A 53 FA 99 00 00 F2 23 58 83 FA 23 19 B3 09 63
-0C 49 6A 4E 1E 43 4A 93 01 30 2E 83 8F 4C 00 00
-35 40 08 44 34 40 14 44 30 4D 2F 53 2F 53 3E 4F
-30 4D CE 49 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F
-29 4F 2F 82 1B 42 DA 1D 6A 4C 7A 80 30 00 7A 90
-0A 00 02 28 7A 80 07 00 0A 9B 13 2C 82 49 D0 04
-82 48 D2 04 82 4B C8 04 19 42 E4 04 18 42 E6 04
-09 5A 08 63 1C 53 1E 83 E7 23 8F 49 04 00 8F 48
-02 00 8F 4C 00 00 30 4D 03 12 0D 12 1B 42 DA 1D
-0B 12 32 C0 00 02 6D 4E 0D 5E 0C 4E 7A 40 2E 00
-0D 9C 0A 28 7A 9C FC 23 32 D0 00 02 FC 4C FE FF
-0D 9C FC 2F DE 83 00 00 09 43 08 43 3D 40 AE 4E
-3F 82 8F 4E 06 00 0C 4E 7E 4C 6A 4C 7A 90 2D 00
-10 2C 3B 40 10 00 7A 80 24 00 06 24 2B 43 5A 83
-03 24 3B 52 6A 53 B0 23 1C 53 1E 83 6A 4C 7A 90
-2D 00 AA 23 1C 53 1E 83 B1 43 04 00 A5 3F B0 4E
-2F 53 0E 93 2C 17 82 4C DA 1D 03 24 2F 52 0E F3
-30 4D 8F 93 00 00 15 20 32 B0 00 02 14 20 0E 93
-05 24 1A 4F 02 00 1A 83 0A 93 0B 38 2F 53 BF 4F
-00 00 3E E3 05 20 BF E3 00 00 9F 53 00 00 3E E3
-30 4D 32 D0 00 02 9F 4F 02 00 04 00 BF 4F 00 00
-3E E3 F6 23 BF E3 02 00 BF E3 00 00 9F 53 02 00
-8F 63 00 00 3E E3 30 4D 30 4C 07 45 58 45 43 55
-54 45 0A 4E 3E 4F 00 4A 08 49 01 2C 1A 42 C4 1D
-A2 53 C4 1D 8A 4E 00 00 3E 4F 30 4D 2A 4F 87 4C
-49 54 45 52 41 4C 82 93 B6 1D 16 24 32 B0 00 02
-09 24 1A 42 C4 1D A2 52 C4 1D BA 40 34 44 00 00
-BA 4F 02 00 1A 42 C4 1D A2 52 C4 1D BA 40 34 44
-00 00 8A 4E 02 00 3E 4F 30 4D 66 4C 05 43 4F 55
-4E 54 2F 83 1E 53 8F 4E 00 00 5E 4E FF FF 30 4D
-82 4E BE 1D B2 4F C0 1D 3E 4F 82 43 C2 1D 87 12
-4C 46 24 4D A6 4F 3D 40 B2 4F E8 22 3D 41 3E 4F
-30 4D B4 4F 0A 4E 3E 4F 3D 40 CA 4F 3D 27 3D 40
-A0 4F 1A E2 B6 1D B2 27 AC 23 CC 4F 3E 4F 3D 40
-A0 4F B9 23 DE 53 00 00 68 4E 08 5E F8 40 3F 00
-00 00 3D 40 92 51 CD 3F 1A 4F 08 45 56 41 4C 55
-41 54 45 00 39 40 BE 1D 39 12 39 12 39 12 0D 12
-B0 12 2A 44 90 4F 08 50 3D 41 B2 41 C2 1D B2 41
-C0 1D B2 41 BE 1D 30 4D DC 48 04 51 55 49 54 00
-31 40 E0 1C B2 40 00 1C AC 1D 82 43 B6 1D 82 43
-08 18 B0 12 2A 44 CA 4C 04 0D 6F 6B 20 00 AE 4C
-34 44 38 1D 44 44 34 44 50 00 7E 4B 76 4C 90 4F
-34 44 7E 1C CE 44 B2 45 CA 4C 0D 73 74 61 63 6B
-20 65 6D 70 74 79 20 21 A4 50 34 44 30 FF 0C 4B
-B2 45 CA 4C 0B 46 52 41 4D 20 66 75 6C 6C 20 21
-A4 50 42 46 F4 44 C0 45 36 50 CA 4C 04 0D 20 20
-20 00 BC 45 3E 50 76 4B 05 41 42 4F 52 54 3F 40
-80 1C BE 3F 8F 93 02 00 98 26 B2 40 82 48 EE 4B
-B0 12 8C 55 82 43 2E 5E 82 43 3A 5E 82 43 46 5E
-82 43 76 5E 82 43 82 5E 82 43 8E 5E A2 B3 DC 05
-FD 27 B2 40 11 00 CE 05 92 C3 DC 05 38 40 50 55
-39 42 19 83 FE 23 18 83 FB 23 92 B3 DC 05 F4 23
-87 12 CA 4C 04 1B 5B 37 6D 00 AE 4C AE 4C CA 4C
-04 1B 5B 30 6D 00 AE 4C D4 54 16 55 1C 55 9E 50
-98 50 86 41 42 4F 52 54 22 00 87 12 E4 4C 34 44
-A4 50 2C 4F 2A 44 76 4D 01 27 87 12 4C 46 24 4D
-7C 4D C0 45 38 51 2A 44 D4 4F DA 49 81 5C 92 42
-BE 1D C2 1D 30 4D 87 12 00 4D 4C 46 24 4D 50 51
-08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 C8 1D 6E 4E
-3E F0 1E 00 09 5E 82 48 AE 1D 82 49 B0 1D 82 4A
-B2 1D 2A 52 82 4A C4 1D 3E 4F 3D 41 30 41 87 12
-CA 4C 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63
-68 21 AA 50 82 9F B4 1D F2 23 18 42 AE 1D 19 42
-B0 1D A8 49 FE FF 89 48 00 00 30 4D 1E 4D 08 56
-41 52 49 41 42 4C 45 00 B0 12 46 51 BA 40 86 12
-FC FF EF 3F 7C 4F 08 43 4F 4E 53 54 41 4E 54 00
-B0 12 46 51 BA 40 85 12 FC FF 8A 4E FE FF 3E 4F
-E0 3F C6 51 06 43 52 45 41 54 45 00 B0 12 46 51
-BA 40 85 12 FC FF 8A 4A FE FF D3 3F EA 4F 05 44
-4F 45 53 3E 1A 42 B2 1D BA 40 84 12 00 00 8A 4D
-02 00 3D 41 30 4D FE 51 05 44 45 46 45 52 B0 12
-46 51 BA 40 30 40 FC FF BA 40 14 52 FE FF B9 3F
-38 49 81 5B 82 43 B6 1D 30 4D 3C 51 01 5D B2 43
-B6 1D 30 4D E0 4C 87 52 45 43 55 52 53 45 19 42
-C4 1D 99 42 B2 1D 00 00 A2 53 C4 1D 30 4D 32 52
-01 3A B0 12 46 51 BA 40 87 12 FC FF A2 83 C4 1D
-B2 43 B6 1D 82 4F B4 1D 30 4D 60 52 81 3B 82 93
-B6 1D 5D 27 87 12 34 44 2A 44 2C 4F 94 51 34 52
-2A 44 52 4C 09 49 4D 4D 45 44 49 41 54 45 1A 42
-AE 1D FA D0 80 00 00 00 30 4D BE 4F 02 00 3E 4F
-30 4D 94 52 82 49 53 00 87 12 42 46 F4 44 C0 45
-CC 52 D8 52 34 44 AA 52 2C 4F 2A 44 2A 51 AA 52
-2A 44 7C 52 83 5B 27 5D 87 12 2A 51 34 44 34 44
-2C 4F 2C 4F 2A 44 1A 50 88 50 4F 53 54 50 4F 4E
-45 00 87 12 4C 46 24 4D 7C 4D 54 44 C0 45 38 51
-7E 45 C0 45 12 53 34 44 34 44 2C 4F 2C 4F 34 44
-2C 4F 2C 4F 2A 44 18 53 3A 4E 82 4A C6 1D 2E 4E
-82 4E C4 1D 3D 40 10 00 09 4A 08 49 29 83 18 48
-FE FF 0E 98 FC 2B 89 48 00 00 1D 83 F6 23 2A 4A
-0A 93 F0 23 3E 4F 3D 41 30 4D B4 52 82 49 46 00
-2F 83 8F 4E 00 00 1E 42 C4 1D BE 40 C0 45 00 00
-A2 52 C4 1D 2E 53 30 4D 18 52 84 45 4C 53 45 00
-1A 42 C4 1D BA 40 BC 45 00 00 2A 52 82 4A C4 1D
-8E 4A 00 00 2A 83 0E 4A 30 4D A8 4C 84 54 48 45
-4E 00 9E 42 C4 1D 00 00 3E 4F 30 4D E4 51 85 42
-45 47 49 4E 30 40 0C 4B 8C 53 85 55 4E 54 49 4C
-39 40 C0 45 1A 42 C4 1D A2 52 C4 1D 8A 49 00 00
-8A 4E 02 00 3E 4F 30 4D 12 51 85 41 47 41 49 4E
-39 40 BC 45 EF 3F AE 51 85 57 48 49 4C 45 87 12
-50 53 6E 44 2A 44 46 52 86 52 45 50 45 41 54 00
-87 12 D0 53 92 53 2A 44 6A 53 82 44 4F 00 2F 83
-8F 4E 00 00 1E 42 C4 1D BE 40 CA 45 00 00 2E 53
-82 4E C4 1D A2 53 AC 1D 1A 42 AC 1D 8A 43 00 00
-30 4D 3E 4F 84 4C 4F 4F 50 00 39 40 EC 45 1A 42
-C4 1D A2 52 C4 1D 8A 49 00 00 8A 4E 02 00 1E 42
-AC 1D A2 83 AC 1D 2E 4E 0E 93 04 24 9E 42 C4 1D
-00 00 F5 3F 3E 4F 30 4D 6C 4B 85 2B 4C 4F 4F 50
-39 40 DA 45 E4 3F 24 54 85 4C 45 41 56 45 1A 42
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@FFCC
-C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52
-C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52
-C6 52 C6 52 6A 48 C6 52 C6 52 C6 52 C6 52 C6 52
-C6 52 C6 52
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+36 54 36 54 92 48 36 54 36 54 36 54 36 54 36 54
+36 54 36 54
q
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr5969 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
MOV #8, &REFCTL
; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
+; POWER ON RESET AND INITIALIZATION : RTC_C REGISTERS
; ----------------------------------------------------------------------
.IFDEF LF_XTAL
; LFXIN : PJ.4, LFXOUT : PJ.5
BIS.B #010h,&PJSEL0 ; SEL0 for only LFXIN
- BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B
+ MOV.B #0A5h,&RTCCTL0_H ; unlock RTC_C
+ BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_C
.ENDIF
; ----------------------------------------------------------------------
+++ /dev/null
-@1800
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-@2000
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+7A C0 E1 00 6A 92 DE 27 8C 10 1C 52 4C 06 D2 D3
+23 02 87 12 FC 45 0B 3C 20 53 44 20 45 72 72 6F
+72 21 C4 5D 2F 82 8F 4E 02 00 9F 42 DA 1D 00 00
+B2 40 10 00 DA 1D 0E 4C B0 12 2A 40 56 43 7A 42
+FA 40 98 49 9C 5A 09 7B 53 44 5F 4C 4F 41 44 7D
+30 4D 39 4F 18 42 C4 1D 4A 4E 0E 48 C8 4A 00 00
+18 53 30 40 9C 4D 92 4B 0E 00 22 20 92 4B 10 00
+24 20 5A 42 23 20 58 42 22 20 A2 93 02 20 08 20
+59 42 24 20 89 10 0A 59 88 10 08 58 0A 6A 88 10
+08 58 30 41 82 43 1C 20 92 42 0E 20 1A 20 C2 93
+24 20 03 20 92 93 22 20 14 24 92 42 22 20 D0 04
+92 42 24 20 D2 04 92 42 12 20 C8 04 92 42 E4 04
+1A 20 92 42 E6 04 1C 20 92 52 10 20 1A 20 82 63
+1C 20 30 41 92 4B 0E 00 22 20 92 4B 10 00 24 20
+B0 12 34 5E 5A 4B 03 00 82 5A 1A 20 82 63 1C 20
+30 41 09 93 07 24 F8 90 20 00 00 1E 03 20 18 53
+19 83 F9 23 30 41 1B 42 34 20 82 43 1E 20 B2 90
+00 02 20 20 96 20 BB 80 00 02 12 00 8B 73 14 00
+DB 53 03 00 DB 92 12 20 03 00 11 28 CB 43 03 00
+B0 12 06 5E B0 12 2C 5D 8B 43 10 00 9B 48 00 1E
+0E 00 92 93 02 20 03 24 9B 48 02 1E 10 00 B2 40
+00 02 20 20 8B 93 14 00 0B 20 92 9B 12 00 1E 20
+70 2C BB 90 00 02 12 00 03 2C 92 4B 12 00 20 20
+B0 12 74 5E 1A 42 1A 20 19 42 1C 20 0A 3F 3C 42
+3B 40 40 20 09 43 CB 93 02 00 10 24 9B 92 24 20
+0C 00 04 20 9B 92 22 20 0A 00 07 24 09 4B 3B 50
+18 00 3B 90 00 21 EF 23 0C 5C 30 41 0C 43 82 4B
+34 20 8B 49 00 00 4A 93 07 34 49 93 05 24 C9 93
+02 00 02 34 5A 59 02 00 CB 4A 02 00 CB 43 03 00
+9B 42 1A 20 04 00 9B 42 1C 20 06 00 18 42 30 20
+8B 48 08 00 9B 48 1A 1E 0A 00 9B 48 14 1E 0C 00
+9B 48 1A 1E 0E 00 9B 48 14 1E 10 00 9B 48 1C 1E
+12 00 9B 48 1E 1E 14 00 82 43 1E 20 6A 93 62 27
+CC 37 8B 43 16 00 7A 93 05 24 99 37 99 52 C2 1D
+16 00 95 3F 19 42 C2 1D 1A 42 BE 1D 0A 89 82 4A
+36 20 19 52 C0 1D 82 49 38 20 B2 40 04 44 78 44
+86 3F 1B 42 34 20 82 43 20 20 0B 93 AE 27 EB 93
+02 00 04 20 B0 12 50 64 B0 12 18 64 5A 4B 02 00
+CB 43 02 00 2B 4B 82 4B 34 20 5A 53 05 24 9D 37
+92 4B 16 00 1E 20 6B 3F 1E 42 36 20 9F 42 38 20
+02 00 B2 40 86 44 78 44 30 41 90 4E 85 52 45 41
+44 22 5A 43 19 3C 26 5B 86 57 52 49 54 45 22 00
+6A 43 12 3C 06 5C 84 44 45 4C 22 00 6A 42 0C 3C
+6E 53 05 43 4C 4F 53 45 B0 12 E2 5F 30 4D D0 5B
+85 4C 4F 41 44 22 7A 43 2F 83 8F 4E 00 00 0E 4A
+82 93 B6 1D 0D 24 87 12 34 40 34 40 32 48 32 48
+16 46 34 40 F2 5D 32 48 34 40 9C 60 32 48 2A 40
+87 12 34 40 22 00 56 46 9A 60 3D 41 78 4E 08 5E
+C8 43 00 00 1C 43 92 42 2C 20 22 20 92 42 2E 20
+24 20 CE 93 00 00 91 24 FE 90 3A 00 01 00 01 20
+2E 53 FE 90 5C 00 00 00 09 20 1E 53 92 42 02 20
+22 20 82 43 24 20 CE 93 00 00 73 24 82 4E 32 20
+B0 12 34 5E 34 40 20 00 A2 93 02 20 04 24 92 92
+22 20 02 20 02 24 14 42 12 20 B0 12 14 5F 2C 43
+0A 43 08 4A 58 0E 08 58 82 48 30 20 C8 93 00 1E
+64 24 39 42 F8 9E 00 1E 04 20 18 53 19 83 FA 23
+1E 53 FE 90 2E 00 FF FF 1A 24 39 50 03 00 B0 12
+92 5E 07 20 FE 90 5C 00 FF FF 2B 24 CE 93 FF FF
+28 24 1E 42 32 20 1A 53 3A 90 10 00 DA 23 92 53
+1A 20 82 63 1C 20 14 83 D0 23 2C 42 3E 3C FE 90
+2E 00 FE FF EE 27 B0 12 92 5E EB 23 39 40 03 00
+F8 9E 00 1E 04 20 18 53 19 83 FA 23 0A 3C CE 93
+FF FF DF 23 FE 90 5C 00 FF FF DB 23 B0 12 92 5E
+D8 23 18 42 30 20 92 48 1A 1E 22 20 92 48 14 1E
+24 20 F8 B0 10 00 0B 1E 15 24 82 93 24 20 06 20
+82 93 22 20 03 20 92 42 02 20 22 20 CE 93 FF FF
+8A 23 92 42 22 20 2C 20 92 42 24 20 2E 20 8F 43
+00 00 03 3C 2A 4F B0 12 1E 5F 3A 4F 34 40 14 40
+3E 4F 0A 93 06 24 7A 93 14 20 0C 93 03 20 3D 40
+98 48 30 4D 87 12 FC 45 0B 3C 20 4F 70 65 6E 45
+72 72 6F 72 68 45 A0 43 7A 48 E0 45 A8 45 DC 41
+C2 5D 1A 93 B5 20 0C 93 ED 23 30 4D 2C 60 04 52
+45 41 44 00 2F 83 8F 4E 00 00 1E 42 34 20 B0 12
+A6 5E 1E 82 34 20 30 4D 2C 43 12 12 2A 20 18 42
+02 20 08 58 2A 41 82 9A 0A 20 A0 24 B0 12 2C 5D
+09 43 28 93 03 24 89 93 02 1E 03 20 89 93 00 1E
+07 24 09 58 39 90 00 02 F4 23 91 53 00 00 EA 3F
+0C 43 6A 41 B9 43 00 1E 28 93 0F 24 B9 40 FF 0F
+02 1E 09 11 8A 10 09 5A 5A 41 01 00 0A 11 09 10
+82 4A 28 20 82 49 26 20 07 3C 09 11 C2 49 26 20
+C2 4A 27 20 82 43 28 20 3A 41 82 4A 2A 20 30 41
+0A 12 1A 52 08 20 B0 12 6E 5D 3A 41 1A 52 0C 20
+30 40 6E 5D F2 B0 40 00 A2 04 29 20 F2 B0 10 00
+A2 04 FC 27 5A 42 B0 04 4A 11 59 42 B4 04 F2 40
+20 00 C0 04 D2 42 B1 04 C8 04 1A 52 E4 04 D2 42
+B5 04 C8 04 19 52 E4 04 D2 42 B2 04 C0 04 B2 40
+00 08 C8 04 1A 52 E4 04 92 42 B6 04 C0 04 B2 80
+BC 07 C0 04 B2 40 00 02 C8 04 19 52 E4 04 30 41
+22 2A 2B 2C 2F 3A 3B 3C 3D 3E 3F 5B 5C 5D 7C 2E
+29 92 06 38 39 80 03 00 B0 12 6E 63 39 40 03 00
+7A 4B C8 4A 00 1E 0A 93 12 24 0D 12 3D 40 0F 00
+3C 40 20 63 7A 9C F4 27 1D 83 FC 23 3D 41 6A 9C
+E7 27 3A 80 21 00 EC 3B 18 53 19 83 E9 23 09 93
+06 24 F8 40 20 00 00 1E 18 53 19 83 FA 23 30 41
+2A 93 EB 20 2C 93 0D 24 0C 93 BA 24 87 12 FC 45
+0C 3C 20 57 72 69 74 65 45 72 72 6F 72 00 DC 41
+04 62 B0 12 38 62 92 42 26 20 22 20 92 42 28 20
+24 20 B0 12 B0 62 B0 12 14 5F 18 42 30 20 F8 40
+20 00 0B 1E B0 12 C4 62 88 43 0C 1E 88 4A 0E 1E
+88 49 10 1E 88 49 12 1E 98 42 24 20 14 1E 98 42
+22 20 1A 1E 88 43 1C 1E 88 43 1E 1E 1C 43 1B 42
+32 20 CB 93 00 00 CA 27 FB 90 2E 00 00 00 C6 27
+39 40 0B 00 B0 12 40 63 B0 12 5A 64 2A 43 B0 12
+1E 5F 0C 93 BB 23 30 4D 1A 4B 04 00 19 4B 06 00
+B0 12 32 5D B0 12 C4 62 18 4B 08 00 88 49 12 1E
+88 4A 16 1E 88 49 18 1E 98 4B 12 00 1C 1E 98 4B
+14 00 1E 1E 1A 4B 04 00 19 4B 06 00 30 40 70 5D
+9B 52 1E 20 12 00 8B 63 14 00 1A 42 1A 20 19 42
+1C 20 30 40 70 5D B2 40 00 02 1E 20 1B 42 34 20
+B0 12 50 64 82 43 1E 20 DB 53 03 00 DB 92 12 20
+03 00 22 20 CB 43 03 00 B0 12 06 5E 08 12 0A 12
+B0 12 38 62 2A 91 05 24 B0 12 B0 62 2A 41 B0 12
+2C 5D 3A 41 38 41 98 42 26 20 00 1E 92 93 02 20
+03 24 98 42 28 20 02 1E B0 12 B0 62 9B 42 26 20
+0E 00 9B 42 28 20 10 00 30 40 74 5E 38 60 05 57
+52 49 54 45 B0 12 66 64 30 4D 1E 62 07 53 44 5F
+45 4D 49 54 B2 90 00 02 1E 20 02 28 B0 12 66 64
+18 42 1E 20 C8 4E 00 1E 92 53 1E 20 3E 4F 30 4D
+58 4B 13 00 59 4B 14 00 89 10 09 58 58 4B 15 00
+5B 42 12 20 0A 43 3C 42 08 11 09 10 4A 10 1C 83
+0B 11 FA 2B 0A 11 1C 83 FD 37 1B 42 34 20 19 5B
+0A 00 18 6B 0C 00 8B 49 0E 00 8B 48 10 00 CB 4A
+03 00 1A 4B 12 00 BB C0 FF 01 12 00 3A F0 FF 01
+82 4A 1E 20 B0 12 10 5F 30 4D 0C 93 38 20 38 90
+E0 01 03 2C C8 93 20 1E 02 24 7C 40 E5 00 C8 4C
+00 1E B0 12 5A 64 B0 12 12 5E 82 4A 2A 20 0B 4A
+B0 12 2C 5D 1A 48 00 1E 88 43 00 1E 92 93 02 20
+09 24 19 48 02 1E 88 43 02 1E 39 F0 FF 0F 39 90
+FF 0F 02 20 3A 93 0E 24 82 4A 22 20 82 49 24 20
+B0 12 12 5E 0B 9A E6 27 0A 12 0A 4B B0 12 B0 62
+3A 41 DD 3F 0A 4B B0 12 B0 62 B0 12 E2 5F 30 4D
+DE 5B 08 54 45 52 4D 32 53 44 22 00 87 12 4C 60
+A0 43 E4 65 21 53 2F 83 AF 43 00 00 3D 40 F4 65
+30 40 9C 60 F6 65 92 C3 DC 05 08 43 B0 12 BA 44
+92 B3 DC 05 FD 27 59 42 CC 05 69 92 0D 24 C8 49
+00 1E 18 53 38 90 FF 01 F3 2B 03 24 B0 12 66 64
+EC 3F B0 12 CC 44 EC 3F B0 12 CC 44 82 48 1E 20
+B0 12 E2 5F 3D 41 30 4D
@FFB4
-58 4F 58 4F 58 4F 58 4F 58 4F 58 4F 58 4F 58 4F
-58 4F 58 4F 58 4F 58 4F 58 4F 58 4F 58 4F 58 4F
-58 4F 58 4F 58 4F 58 4F 58 4F 58 4F 58 4F 58 4F
-58 4F 58 4F 58 4F 58 4F 58 4F 58 4F E6 44 58 4F
-58 4F 58 4F 58 4F 58 4F 58 4F 58 4F
+B4 50 B4 50 B4 50 B4 50 B4 50 B4 50 B4 50 B4 50
+B4 50 B4 50 B4 50 B4 50 B4 50 B4 50 B4 50 B4 50
+B4 50 B4 50 B4 50 B4 50 B4 50 B4 50 B4 50 B4 50
+B4 50 B4 50 B4 50 B4 50 B4 50 B4 50 FA 44 B4 50
+B4 50 B4 50 B4 50 B4 50 B4 50 B4 50
q
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr5994 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
@1800
-10 00 6A 48 80 3E 80 04 FD FF 18 00 66 5B 1C 54
-2A 48 3C 48 00 00 00 00
+10 00 92 48 80 3E 80 04 05 00 18 00 D4 5C 8C 55
+52 48 64 48 00 00 00 00
@1DAA
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
03 4C 49 54 2F 83 8F 4E 00 00 3E 4D 30 4D 24 44
03 44 55 50 2F 83 8F 4E 00 00 30 4D 00 00 04 3F
44 55 50 00 0E 93 F6 23 30 4D 40 44 04 44 52 4F
-50 00 3E 4F 30 4D 00 00 04 53 57 41 50 00 2A 4F
-8F 4E 00 00 0E 4A 30 4D 00 00 04 4F 56 45 52 00
-2F 83 8F 4E 00 00 1E 4F 02 00 30 4D 68 44 03 52
-4F 54 2A 4F 8F 4E 00 00 1E 4F 02 00 8F 4A 02 00
-30 4D 4E 44 02 3E 52 00 0E 12 3E 4F 30 4D 8E 44
-02 52 3E 00 2F 83 8F 4E 00 00 3E 41 30 4D B0 44
-02 52 40 00 2F 83 8F 4E 00 00 2E 41 30 4D 8F 4E
-FE FF 0E 4F 2F 83 30 4D 5C 44 05 44 45 50 54 48
-8F 4E FE FF 3E 40 80 1C 0E 8F 2F 83 0E 11 30 4D
-00 00 01 40 2E 4E 30 4D F2 44 01 21 BE 4F 00 00
-3E 4F 30 4D 00 00 02 43 40 00 6E 4E 30 4D 06 45
-02 43 21 00 3A 4F CE 4A 00 00 3E 4F 30 4D 00 00
-01 2B 3E 5F 30 4D 30 44 01 2D 3A 4F 0A 8E 0E 4A
-30 4D FA 44 03 41 4E 44 3E FF 30 4D 7A 44 02 4F
-52 00 3E DF 30 4D 00 00 03 58 4F 52 3E EF 30 4D
-3E 45 06 4E 45 47 41 54 45 00 3E E3 1E 53 30 4D
-34 45 03 41 42 53 0E 93 F8 33 30 4D 00 00 02 30
-3D 00 1E 83 0E 7E 30 4D 6E 45 02 30 3C 00 0E 5E
-0E 7E 3E E3 30 4D 00 00 01 3D 3E 8F 07 20 3E 43
-30 4D 88 45 01 3C 3A 4F 0A 8E F9 3B 0E 43 30 4D
-A4 44 01 3E 3E 8F F3 3B 0E 43 30 4D 00 00 02 55
+50 00 3E 4F 30 4D 00 00 03 4E 49 50 2F 53 30 4D
+00 00 04 53 57 41 50 00 2A 4F 8F 4E 00 00 0E 4A
+30 4D 68 44 04 4F 56 45 52 00 8F 4E FE FF 2E 4F
+2F 83 30 4D 72 44 03 52 4F 54 2A 4F 8F 4E 00 00
+1E 4F 02 00 8F 4A 02 00 30 4D 4E 44 02 3E 52 00
+0E 12 3E 4F 30 4D 96 44 02 52 3E 00 2F 83 8F 4E
+00 00 3E 41 30 4D B8 44 02 52 40 00 2F 83 8F 4E
+00 00 2E 41 30 4D 5C 44 05 44 45 50 54 48 8F 4E
+FE FF 3E 40 80 1C 0E 8F 2F 83 0E 11 30 4D 00 00
+01 40 2E 4E 30 4D F0 44 01 21 BE 4F 00 00 3E 4F
+30 4D 00 00 02 43 40 00 6E 4E 30 4D 04 45 02 43
+21 00 FE 4F 00 00 1F 53 3E 4F 30 4D 00 00 01 2B
+3E 5F 30 4D 30 44 01 2D 3E 8F 3E E3 1E 53 30 4D
+F8 44 03 41 4E 44 3E FF 30 4D 84 44 02 4F 52 00
+3E DF 30 4D 00 00 03 58 4F 52 3E EF 30 4D 3C 45
+06 4E 45 47 41 54 45 00 E8 3F 32 45 03 41 42 53
+0E 93 E3 33 30 4D D8 44 04 44 41 42 53 00 3E F3
+06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 30 4D
+00 00 02 30 3D 00 1E 83 0E 7E 30 4D 82 45 02 30
+3C 00 0E 5E 0E 7E 3E E3 30 4D 8E 45 02 30 3E 00
+1E 93 05 34 0B 3C 00 00 01 3D 3E 8F 07 20 3E 43
+30 4D A8 45 01 3C 3A 4F 0A 8E F9 3B 0E 43 30 4D
+AC 44 01 3E 3E 8F F3 3B 0E 43 30 4D 00 00 02 55
3C 00 3A 4F 0A 8E EB 2B 0E 43 30 4D 2D 4D 30 4D
-0E 93 3E 4F FB 27 2D 53 30 4D 39 40 00 80 39 8F
-08 4E 3E 4F 08 59 19 15 30 4D 81 5E 00 00 3E 4F
-32 B0 00 01 EB 27 2D 53 21 52 30 4D 91 53 00 00
-F7 3F AE 45 06 55 4E 4C 4F 4F 50 00 F5 3F 00 00
-01 49 2F 83 8F 4E 00 00 2E 41 1E 81 02 00 30 4D
-20 45 01 4A 2F 83 8F 4E 00 00 1E 41 04 00 1E 81
-06 00 30 4D A2 45 03 3E 49 4E 85 12 C2 1D 10 45
-04 42 41 53 45 00 85 12 DA 1D C0 44 05 53 54 41
-54 45 85 12 B6 1D 30 46 02 42 4C 00 85 12 20 00
-94 45 02 3C 23 00 B2 40 AA 1D AA 1D 30 4D 1E 15
-0E 43 3D 40 20 00 0A 93 04 20 0D 11 0A 4C 0C 43
-09 43 0E 9B 01 28 0E 8B 09 69 08 68 1D 83 07 30
-0C 5C 0A 6A 0E 6E F5 2B 0E 8B 12 D3 F5 3F 0A 4E
-1D 17 30 41 48 46 01 23 1B 42 DA 1D 2C 4F 0A 4E
-B0 12 5E 46 8F 49 00 00 0E 48 7A 90 0A 00 02 28
-3A 50 07 00 3A 50 30 00 92 83 AA 1D 18 42 AA 1D
-C8 4A 00 00 30 4D 96 46 02 23 53 00 87 12 98 46
-D2 46 2D 83 09 93 E0 23 0E 93 DE 23 3D 41 30 4D
-C8 46 02 23 3E 00 9F 42 AA 1D 00 00 3E 40 AA 1D
-2E 8F 30 4D 00 46 04 48 4F 4C 44 00 0A 4E 3E 4F
-DB 3F 3C 46 04 53 49 47 4E 00 0E 93 3E 4F 3A 40
-2D 00 D2 33 30 4D F4 45 03 55 44 2E 87 12 56 46
-CC 46 E6 46 50 49 18 49 2A 44 18 47 02 55 2E 00
-2F 83 8F 4E 00 00 0E 43 F1 3F 3E B0 00 80 06 24
-BF E3 00 00 3E E3 9F 53 00 00 0E 63 30 4D DA 44
-02 44 2E 00 87 12 56 46 6E 44 80 44 3A 47 CC 46
-92 44 0A 47 E6 46 50 49 18 49 2A 44 52 45 01 2E
-3E B0 00 80 DD 27 2F 83 3E 43 EC 3F F6 46 04 48
-45 52 45 00 2F 83 8F 4E 00 00 1E 42 C4 1D 30 4D
-62 45 05 41 4C 4C 4F 54 82 5E C4 1D 3E 4F 30 4D
-E2 46 02 43 2C 00 1A 42 C4 1D CA 4E 00 00 92 53
-C4 1D 3E 4F 30 4D 2F 83 8F 4E 00 00 B0 12 2A 48
-92 B3 FC 05 FD 27 1E 42 EC 05 B0 12 3C 48 30 4D
-30 40 B6 47 7E 47 05 28 4B 45 59 29 18 42 EC 05
-EA 3F 12 46 03 4B 45 59 30 40 DC 47 92 47 06 41
-43 43 45 50 54 00 3C 40 A8 48 3B 40 72 48 2D 15
-0A 4E 2E 4F 0A 5E 3B 40 0D 00 3C 40 20 00 3D 40
-9C 48 92 B3 FC 05 05 24 18 42 EC 05 38 90 0A 00
-04 20 21 53 39 40 56 48 4D 15 B2 40 11 00 EE 05
-A2 B3 FC 05 FD 27 D2 C3 22 02 30 41 B2 40 13 00
-EE 05 A2 B3 FC 05 FD 27 D2 D3 22 02 30 41 00 00
-05 53 4C 45 45 50 30 40 64 48 00 00 07 28 53 4C
-45 45 50 29 12 D2 0A 18 F6 3F 21 52 3A 17 58 42
-EC 05 48 9B E3 27 48 9C 06 2C 78 92 11 20 2E 9F
-0F 24 1E 83 05 3C 0E 9A 03 24 CE 48 00 00 1E 53
-82 48 EE 05 A2 B3 FC 05 FD 27 30 4D 9E 48 2D 83
-92 B3 FC 05 FD 27 E3 23 B2 40 18 00 0A 18 3E 8F
-3D 41 30 4D D6 47 06 28 45 4D 49 54 29 00 08 4E
-3E 4F E6 3F 50 47 04 45 4D 49 54 00 30 40 BE 48
-C6 48 04 45 43 48 4F 00 B2 40 82 48 90 48 30 4D
-6E 47 06 4E 4F 45 43 48 4F 00 B2 40 30 4D 90 48
-30 4D B6 48 04 28 43 52 29 00 2F 83 8F 4E 00 00
-3E 40 0D 00 E3 3F A2 47 02 43 52 00 30 40 FA 48
-04 47 05 53 50 41 43 45 2F 83 8F 4E 00 00 3E 40
-20 00 D4 3F 12 49 06 53 50 41 43 45 53 00 0E 93
-09 24 0D 12 3D 40 3A 49 EF 3F 3C 49 2D 83 1E 83
-EB 23 3D 41 3E 4F 30 4D 2C 47 04 54 59 50 45 00
-0E 93 95 24 2A 4F 8F 5E 00 00 0E 4A 87 12 CA 45
-02 46 0A 45 CC 48 EC 45 60 49 2A 44 2F 82 8F 4E
-02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 30 4D
-26 49 82 53 22 00 87 12 34 44 6C 49 A2 4B 34 44
-22 00 C6 49 96 49 3D 41 6E 4E 1E 83 82 5E C4 1D
-3E 4F 92 B3 C4 1D A2 63 C4 1D 30 4D E2 48 82 2E
-22 00 87 12 86 49 34 44 50 49 A2 4B 2A 44 00 00
-04 57 4F 52 44 00 3C 40 BE 1D 39 4C 3A 4C 09 5A
-3A 5C 28 4C 09 9A 19 24 7E 9A FC 27 1A 83 3B 40
-60 00 C8 4C 00 00 09 9A 0C 24 7C 4A 4E 9C 09 24
-18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 7C 80 20 00
-F0 3F 1A 82 C0 1D 82 4A C2 1D 1E 42 C4 1D 08 8E
-CE 48 00 00 30 4D 00 00 04 46 49 4E 44 00 2F 83
-0C 4E 65 4C 74 40 80 00 3B 40 CA 1D 3E 4B 0E 93
-1E 24 58 4C 01 00 78 F0 1E 00 0E 58 2E 53 1E 4E
-FE FF 0E 93 F3 27 09 4E 78 49 48 C4 48 95 F7 23
-0A 4C 1A 53 FA 99 00 00 F2 23 58 83 FA 23 19 B3
-09 63 0C 49 6A 4E 1E 43 4A 93 01 30 2E 83 8F 4C
-00 00 35 40 08 44 34 40 14 44 30 4D 2F 53 2F 53
-3E 4F 30 4D 26 46 07 3E 4E 55 4D 42 45 52 3C 4F
-38 4F 29 4F 2F 82 1B 42 DA 1D 6A 4C 7A 80 30 00
-7A 90 0A 00 02 28 7A 80 07 00 0A 9B 13 2C 82 49
-D0 04 82 48 D2 04 82 4B C8 04 19 42 E4 04 18 42
-E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 49 04 00
-8F 48 02 00 8F 4C 00 00 30 4D 03 12 0D 12 1B 42
-DA 1D 0B 12 32 C0 00 02 6D 4E 0D 5E 0C 4E 7A 40
-2E 00 0D 9C 0A 28 7A 9C FC 23 32 D0 00 02 FC 4C
-FE FF 0D 9C FC 2F DE 83 00 00 09 43 08 43 3D 40
-50 4B 3F 82 8F 4E 06 00 0C 4E 7E 4C 6A 4C 7A 90
-2D 00 10 2C 3B 40 10 00 7A 80 24 00 06 24 2B 43
-5A 83 03 24 3B 52 6A 53 B0 23 1C 53 1E 83 6A 4C
-7A 90 2D 00 AA 23 1C 53 1E 83 B1 43 04 00 A5 3F
-52 4B 2F 53 0E 93 2C 17 82 4C DA 1D 03 24 2F 52
-0E F3 30 4D 9F 4F 02 00 04 00 BF 4F 00 00 3E E3
-09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00
-8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D D2 48
-07 45 58 45 43 55 54 45 0A 4E 3E 4F 00 4A 28 45
-01 2C 1A 42 C4 1D A2 53 C4 1D 8A 4E 00 00 3E 4F
-30 4D A0 4B 87 4C 49 54 45 52 41 4C 82 93 B6 1D
-16 24 32 B0 00 02 09 24 1A 42 C4 1D A2 52 C4 1D
-BA 40 34 44 00 00 BA 4F 02 00 1A 42 C4 1D A2 52
-C4 1D BA 40 34 44 00 00 8A 4E 02 00 3E 4F 30 4D
-08 49 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00
-5E 4E FF FF 30 4D 82 4E BE 1D B2 4F C0 1D 3E 4F
-82 43 C2 1D 87 12 4C 46 C6 49 1C 4C 3D 40 28 4C
-FE 22 3D 41 3E 4F 30 4D 2A 4C 0A 4E 3E 4F 3D 40
-40 4C 53 27 3D 40 16 4C 1A E2 B6 1D B2 27 AC 23
-42 4C 3E 4F 3D 40 16 4C B9 23 DE 53 00 00 68 4E
-08 5E F8 40 3F 00 00 00 3D 40 0C 4E CD 3F 90 4B
-08 45 56 41 4C 55 41 54 45 00 39 40 BE 1D 39 12
-39 12 39 12 0D 12 B0 12 2A 44 06 4C 7E 4C 3D 41
-B2 41 C2 1D B2 41 C0 1D B2 41 BE 1D 30 4D 7A 45
-04 51 55 49 54 00 31 40 E0 1C B2 40 00 1C 00 1C
-82 43 B6 1D 82 43 08 18 B0 12 2A 44 6C 49 04 0D
-6F 6B 20 00 50 49 34 44 38 1D 44 44 34 44 50 00
-F6 47 18 49 06 4C 34 44 7E 1C CE 44 B2 45 6C 49
-0D 73 74 61 63 6B 20 65 6D 70 74 79 20 21 1A 4D
-34 44 30 FF 84 47 B2 45 6C 49 0B 46 52 41 4D 20
-66 75 6C 6C 20 21 1A 4D 42 46 F4 44 C0 45 AC 4C
-6C 49 04 0D 20 20 20 00 BC 45 B4 4C EE 47 05 41
-42 4F 52 54 3F 40 80 1C BE 3F 8F 93 02 00 AE 26
-B2 40 82 48 90 48 B0 12 0C 52 82 43 E0 5A 82 43
-EC 5A 82 43 F8 5A 82 43 28 5B 82 43 34 5B 82 43
-40 5B A2 B3 FC 05 FD 27 B2 40 11 00 EE 05 D2 C3
-22 02 92 C3 FC 05 38 40 A0 AA 39 42 19 83 FE 23
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+02 00 30 41 39 90 84 12 01 20 2E 52 30 41 19 42
+C4 1D A2 53 C4 1D 89 4E 00 00 3E 40 29 00 12 12
+C2 1D 92 53 C2 1D B0 12 2A 44 EE 49 02 4B E0 45
+BE 56 B4 56 21 53 3E 90 10 00 BB 2D 30 41 C0 56
+B2 41 C2 1D 22 D3 30 41 87 12 90 46 34 56 D0 56
+82 43 BC 1D 92 42 C4 1D BA 1D A2 53 C4 1D 0A 4E
+3E 4F FA 90 23 00 00 00 34 20 92 53 C2 1D B0 12
+56 56 0E 93 04 20 B2 40 00 03 BC 1D 27 3C 1E 93
+04 20 B2 40 10 03 BC 1D 21 3C 2E 93 04 20 B2 40
+20 03 BC 1D 1B 3C 2E 92 04 20 B2 40 20 02 BC 1D
+15 3C 3E 92 04 20 B2 40 30 02 BC 1D 0F 3C 3E 93
+04 20 B2 40 30 03 BC 1D 09 3C B2 40 30 00 BC 1D
+19 42 C4 1D A2 53 C4 1D 89 4E 00 00 3E 4F 3D 41
+30 4D FA 90 26 00 00 00 08 20 B2 40 10 02 BC 1D
+92 53 C2 1D 30 12 40 57 76 3F FA 90 40 00 00 00
+1A 20 B2 40 20 00 BC 1D 92 53 C2 1D B0 12 9E 56
+0E 20 B2 50 10 00 BC 1D 3E 40 2B 00 B0 12 9E 56
+32 24 92 92 BE 1D C2 1D 02 24 92 53 C2 1D 8E 10
+82 5E BC 1D D3 3F B0 12 9E 56 F9 23 B2 50 10 00
+BC 1D 3E 40 28 00 B0 12 56 56 30 12 90 57 67 3F
+87 12 90 46 34 56 C8 57 FE 90 26 00 00 00 3E 40
+20 00 04 20 B2 50 82 00 BC 1D C2 3F B0 12 9E 56
+DF 23 B2 50 80 00 BC 1D 3E 40 28 00 B0 12 56 56
+B0 12 8E 56 D5 23 3D 40 AE 4D 30 4D 78 48 04 52
+45 54 49 00 87 12 34 44 00 13 CA 4B 2A 44 34 44
+2C 00 C8 56 C0 57 18 58 2E 4E 1E D2 BC 1D 19 42
+BA 1D 92 3F 18 56 03 4D 4F 56 84 12 0E 58 00 40
+26 58 05 4D 4F 56 2E 42 84 12 0E 58 40 40 00 00
+03 41 44 44 84 12 0E 58 00 50 40 58 05 41 44 44
+2E 42 84 12 0E 58 40 50 4C 58 04 41 44 44 43 00
+84 12 0E 58 00 60 5A 58 06 41 44 44 43 2E 42 00
+84 12 0E 58 40 60 FE 57 04 53 55 42 43 00 84 12
+0E 58 00 70 78 58 06 53 55 42 43 2E 42 00 84 12
+0E 58 40 70 86 58 03 53 55 42 84 12 0E 58 00 80
+96 58 05 53 55 42 2E 42 84 12 0E 58 40 80 FA 55
+03 43 4D 50 84 12 0E 58 00 90 B0 58 05 43 4D 50
+2E 42 84 12 0E 58 40 90 E8 55 04 44 41 44 44 00
+84 12 0E 58 00 A0 CA 58 06 44 41 44 44 2E 42 00
+84 12 0E 58 40 A0 BC 58 03 42 49 54 84 12 0E 58
+00 B0 E8 58 05 42 49 54 2E 42 84 12 0E 58 40 B0
+F4 58 03 42 49 43 84 12 0E 58 00 C0 02 59 05 42
+49 43 2E 42 84 12 0E 58 40 C0 0E 59 03 42 49 53
+84 12 0E 58 00 D0 1C 59 05 42 49 53 2E 42 84 12
+0E 58 40 D0 00 00 03 58 4F 52 84 12 0E 58 00 E0
+36 59 05 58 4F 52 2E 42 84 12 0E 58 40 E0 68 58
+03 41 4E 44 84 12 0E 58 00 F0 50 59 05 41 4E 44
+2E 42 84 12 0E 58 40 F0 90 46 C8 56 6E 59 1A 42
+BC 1D B2 F0 70 00 BC 1D 8A 10 3A F0 0F 00 82 DA
+BC 1D 4A 3F A2 58 03 52 52 43 84 12 68 59 00 10
+86 59 05 52 52 43 2E 42 84 12 68 59 40 10 92 59
+04 53 57 50 42 00 84 12 68 59 80 10 A0 59 03 52
+52 41 84 12 68 59 00 11 AE 59 05 52 52 41 2E 42
+84 12 68 59 40 11 BA 59 03 53 58 54 84 12 68 59
+80 11 00 00 04 50 55 53 48 00 84 12 68 59 00 12
+D4 59 06 50 55 53 48 2E 42 00 84 12 68 59 40 12
+28 59 04 43 41 4C 4C 00 84 12 68 59 80 12 34 44
+2C 00 C8 56 C0 57 08 5A 59 42 BC 1D 5A 42 BD 1D
+82 4A BC 1D BE 90 00 15 00 00 02 20 0A 89 02 3C
+09 8A 0A 49 3A 90 10 00 03 2C 5A 0E A8 3F 1A 53
+0E 4A 87 12 8A 47 94 49 0D 6F 75 74 20 6F 66 20
+62 6F 75 6E 64 73 30 4D E2 59 05 50 55 53 48 4D
+84 12 FE 59 00 15 4A 5A 04 50 4F 50 4D 00 84 12
+FE 59 00 17 90 46 34 56 6A 5A 82 43 BC 1D 92 42
+C4 1D BA 1D A2 53 C4 1D 92 53 C2 1D 3E 40 2C 00
+B0 12 2A 44 EE 49 02 4B E0 45 AE 4D C0 57 90 5A
+0A 4E 3E 4F 1A 83 2A 92 CA 2F 8A 10 5A 06 6F 3F
+C8 59 04 52 52 43 4D 00 84 12 64 5A 50 00 A2 5A
+04 52 52 41 4D 00 84 12 64 5A 50 01 B0 5A 04 52
+4C 41 4D 00 84 12 64 5A 50 02 BE 5A 04 52 52 55
+4D 00 84 12 64 5A 50 03 85 12 00 3C CC 5A 03 53
+3E 3D 85 12 00 38 DE 5A 02 53 3C 00 85 12 00 34
+58 5A 03 30 3E 3D 85 12 00 30 F2 5A 02 30 3C 00
+85 12 00 30 00 00 02 55 3C 00 85 12 00 2C 06 5B
+03 55 3E 3D 85 12 00 28 FC 5A 03 30 3C 3E 85 12
+00 24 1A 5B 02 30 3D 00 85 12 00 20 84 48 02 49
+46 00 1A 42 C4 1D 8A 4E 00 00 A2 53 C4 1D 0E 4A
+30 4D 10 5B 04 54 48 45 4E 00 1A 42 C4 1D 08 4E
+3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 68 2F
+88 DA 00 00 30 4D D8 58 04 45 4C 53 45 00 1A 42
+C4 1D BA 40 00 3C 00 00 A2 53 C4 1D 2F 83 8F 4A
+00 00 E3 3F 44 5B 05 55 4E 54 49 4C 3A 4F 08 4E
+3E 4F 19 42 C4 1D 2A 83 0A 89 0A 11 3A 90 00 FE
+47 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C4 1D
+30 4D 5C 59 05 41 47 41 49 4E 87 12 D8 5A 8C 5B
+2A 44 00 00 05 57 48 49 4C 45 87 12 32 5B 78 44
+2A 44 E8 5A 06 52 45 50 45 41 54 00 87 12 D8 5A
+8C 5B 4A 5B 2A 44 00 00 03 4A 4D 50 87 12 A0 4D
+D8 5A 8C 5B 2A 44 3E B0 00 10 03 20 3E E0 00 04
+30 4D 3E 90 00 34 06 28 03 24 3E 40 00 34 30 4D
+3E 40 00 38 30 4D 00 00 04 3F 4A 4D 50 00 87 12
+F6 5B A0 4D 78 44 8C 5B 2A 44 2C 5C 3D 41 08 4E
+3E 4F 2A 48 0A 93 04 20 98 42 C4 1D 00 00 30 4D
+88 43 00 00 A4 3F F2 59 03 42 57 31 84 12 2A 5C
+00 00 48 5C 03 42 57 32 84 12 2A 5C 00 00 54 5C
+03 42 57 33 84 12 2A 5C 00 00 6C 5C 3D 41 1A 42
+C4 1D 28 4E 08 93 08 20 BA 4F 00 00 A2 53 C4 1D
+8E 4A 00 00 3E 4F 30 4D 8E 43 00 00 61 3F 00 00
+03 46 57 31 84 12 6A 5C 00 00 90 5C 03 46 57 32
+84 12 6A 5C 00 00 9C 5C 03 46 57 33 84 12 6A 5C
+00 00 A8 5C 04 47 4F 54 4F 00 87 12 D8 5A A0 4D
+C0 4B 2A 44 18 5C 05 3F 47 4F 54 4F 87 12 F6 5B
+A0 4D C0 4B 2A 44
@FFC6
-C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52
-C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 6A 48
-C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52 C6 52
-C6 52 C6 52 C6 52 C6 52 C6 52
+36 54 36 54 36 54 36 54 36 54 36 54 36 54 36 54
+36 54 36 54 36 54 36 54 36 54 36 54 36 54 92 48
+36 54 36 54 36 54 36 54 36 54 36 54 36 54 36 54
+36 54 36 54 36 54 36 54 36 54
q
+++ /dev/null
-\prog\MSP430Flasher\msp430flasher -m SBW2 -n MSP430fr6989 -v -w %1 -z [VCC=3000]
-exit
-
-tip : how to calculate MAIN program lenght ?
-
-open the prog.txt file with your editor, select MAIN section
-in status bar, keep the number of selected chars
-if lines are ended with CR+LF, substract the number of lines selected
-then divide by 3.
+++ /dev/null
-; -*- coding: utf-8 -*-
-; MY_MSP430FR5738.asm
-; config file for MY_MSP430FR5738 board
-;
-; Copyright (C) <2014> <J.M. THOORENS>
-;
-; This program is free software: you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation, either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program. If not, see <http://www.gnu.org/licenses/>.
-
-
-; ======================================================================
-; MY_MSP430FR5738 board
-; ======================================================================
-
-; MSP430FR5738 XTAL 32768 Hz
-; 1 --- PJ.4 --- LFXIN
-; 2 --- PJ.5 --- LFXOUT
-
-; MSP430FR5738 PROG 6PINS UART 4PINS
-; --- VCC <-> 2 "3v3" <-> 1 "3v3"
-; 20 --- P2.1 <-- 6 "RXD" <-- 2 "RXD"
-; +--4k7-< DeepRST <-- GND
-; |
-; 19 --- P2.0 <+> 1 "TXD" --> 3 "TXD"
-; --- VSS <-> 5 "GND" <-> 4 "GND"
-; 17 --- TEST --- 3 "TST"
-; 18 --- RST --- 4 "RST"
-
-; SWITCH PROG/UART
-; oriented to UART 4PINS
-
-; I2C 4PINS
-; 1 "3v3" <-> DVCC,AVCC
-; 2 "SCL" <-> pin23 = P1.7 == UCB0RXD --> UCB0RXDBUF
-; 3 "SDA" <-> pin22 = P1.6 == UCB0TXD <-- UCB0TXDBUf
-; 4 "GND" <-> DVSS,AVSS
-
-; P1
-; 1 <-> pin5 P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
-; 2 <-> pin6 P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
-; 3 <-> pin7 P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
-; 4 <-> pin8 P1.3/TA1.2/UCB0STE/A3/CD3
-; 5 <-> pin9 P1.4/TB0.1/UCA0STE/A4/CD4
-; 6 <-> pin10 P1.5/TB0.2/UCA0CLK/A5/CD5
-; 7 <-> pin22 P1.6/UCB0SIMO/UCB0SDA/TA0.0
-; 8 <-> pin23 P1.7/UCB0SOMI/UCB0SCL/TA1.0
-
-; P2
-; 1 <-> pin19 P2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
-; 2 <-> pin20 P2.1/UCA0RXD/UCA0SOMI/TB0.0
-; 3 <-> pin21 P2.2/UCB0CLK
-; 4 <-> pin27 P2.3/TA0.0/A6/CD10
-; 5 <-> pin28 P2.4/TA1.0/A7/CD11
-; 6 <-> pin15 P2.5/TB0.0
-; 7 <-> pin16 P2.6
-; 8 <-> "NC "
-
-; PJ
-; 1 <-> "3V3 "
-; 2 <-> "3V3 "
-; 3 <-> pin11 PJ.0/TDO/TB0OUTH/SMCLK/CD6
-; 4 <-> pin12 PJ.1/TDI/TCLK/MCLK/CD7
-; 5 <-> pin13 PJ.2/TMS/ACLK/CD8
-; 6 <-> pin14 PJ.3/TCK/CD9
-; 7 <-> "GND "
-; 8 <-> "GND "
-
-; XTAL 32768 Hz
-; PJ.4 <->XIN LF XTAL
-; PJ.5 <->XOUT LF XTAL
-
-; Vcc <------------------------- Vcc \
-; RST <------------------------> RST \ TI_PROGRM
-; TST <------------------------> TST / INTERFACE
-; Vss <------------------------> Gnd /
-
-; Vcc <------------------------- Vcc \
-; P2.0 TX0 ---------------------> RX \ UARTtoUSB
-; P2.1 RX0 <--------------------- TX / CP2102
-; Vss <------------------------> Gnd /
-
-; GND <-------+---0V0----------> 1 LCD_Vss
-; VCC <------ | --3V6-----+----> 2 LCD_Vdd
-; | |
-; |___ 470n ---
-; ^ | ---
-; / \ BAT54 |
-; --- |
-; 100n | 2k2 |
-; P1.5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-; P1.4 >------------------------> 4 LCD_RS
-; P1.3 >------------------------> 5 LCD_R/W
-; P1.2 >------------------------> 6 LCD_EN
-
-; P1.1 >------------------------> 5 SCL I2C MASTER
-; P1.0 >------------------------> 6 SDA I2C MASTER | IR_RC5 receiver
-
-; PJ.0 <------------------------> 11 LCD_DB4
-; PJ.1 <------------------------> 12 LCD_DB5
-; PJ.2 <------------------------> 13 LCD_DB5
-; PJ.3 <------------------------> 14 LCD_DB7
-
-; P2.5 ---> S2 LCD contrast +
-; P2.6 ---> S1 LCD contrast - | HARD WIPE
-
-
-
-; VCC P1.1 ---> red SD_CardAdapter VCC
-; GND P1.2 <--> black SD_CardAdapter GND
-; P1.6/UCB0SIMO/UCB0SDA/TA0.0 P1.7 ---> grey SD_CardAdapter SDI (MOSI)
-; P1.7/UCB0SOMI/UCB0SCL/TA1.0 <--- purple SD_CardAdapter SDO (MISO)
-; P2.2/UCB0CLK ---> orange SD_CardAdapter CLK (SCK)
-; P2.3/TA0.0/A6/CD10 <--- violin SD_CardAdapter CD (Card Detect)
-; P2.4/TA1.0/A7/CD11 ---> brown SD_CardAdapter CS (Card Select)
-
-
-
-; Clocks:
-; 24 MHz DCO intern
-
-; ----------------------------------------------------------------------
-; INIT order : LOCK I/O, WDT, GPIOs, FRAM, Clock, UARTs
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : LOCK I/O as high impedance state
-; ----------------------------------------------------------------------
-
- BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
-; ----------------------------------------------------------------------
-
-; WDT code
- MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : I/O
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION PAIN=PORT2:PORT1
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORT1 usage
-
-; PORT2 usage
-
-Deep_RST_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
-Deep_RST .equ 1 ; P2.0 = TX
-TERM_TXRX .equ 003h ; P2.1 = RX
-TERM_SEL .equ P2SEL1
-TERM_REN .equ P2REN
-
- .IFDEF TERMINALCTSRTS
-;configure P2.2 as RTS output high
-RTS .equ 4
-HANDSHAKOUT .equ P2OUT
-HANDSHAKIN .equ P2IN
- BIS.B #RTS,&HANDSHAKOUT
- .ENDIF
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV #-1,&PAOUT ; all pins 1
- BIS #-1,&PAREN ; all pins 1 with pull resistors
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORTJ
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORTJ usage
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV.B #-1,&PJOUT ; pullup resistors
- BIS.B #-1,&PJREN ; enable pullup/pulldown resistors
-
-; ----------------------------------------------------------------------
-; FRAM config
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
-; ----------------------------------------------------------------------
-
-; DCOCLK: Internal digitally controlled oscillator (DCO).
-
- MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
-
- .IF FREQUENCY = 0.5
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_16 + DIVM_16,&CSCTL3
- MOV #4,X
-
- .ELSEIF FREQUENCY = 1
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_8 + DIVM_8,&CSCTL3
- MOV #8,X
-
- .ELSEIF FREQUENCY = 2
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_4 + DIVM_4,&CSCTL3
- MOV #16,X
-
- .ELSEIF FREQUENCY = 4
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
- MOV #32,X
-
- .ELSEIF FREQUENCY = 8
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #64,X
-
- .ELSEIF FREQUENCY = 16
- MOV #DCORSEL,&CSCTL1 ; Set 16MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #128,X
-
- .ELSEIF FREQUENCY = 24
- MOV #DCORSEL+DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 24 MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #192,X
-
- .ELSEIF
- .error "bad frequency setting, only 0.5,1,2,4,8,16,24 MHz"
- .ENDIF
-
- .IFDEF LF_XTAL
- MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ELSE
- MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ENDIF
- MOV.B #01h, &CSCTL0_H ; Lock CS Registers
-
- BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
- CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
- JZ ClockWaitX ; yes
- .word 0759h ; no RRUM #2,X --> wait only 125 ms
-ClockWaitX MOV #41666,Y ; wait 0.5s before starting after POWER ON
-ClockWaitY SUB #1,Y ;
- JNZ ClockWaitY ; 41666x3 = 125000 cycles delay = 125ms @ 1MHz
- SUB #1,X ; x 4 @ 1 MHZ
- JNZ ClockWaitX ; time to stabilize power source ( 1s )
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : REF
-; ----------------------------------------------------------------------
-
- MOV #8, &REFCTL
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
-; ----------------------------------------------------------------------
-
- .IFDEF LF_XTAL
-; LF Xtal XIN : PJ.4, LF Xtal XOUT : PJ.5
- BIS.B #010h,&PJSEL0 ; SEL0 for only XIN
- BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B
- .ENDIF
-
+++ /dev/null
-; -*- coding: utf-8 -*-
-; MY_MSP430FR5738_1.asm
-; config file for MY_MSP430FR5738 board
-;
-; Copyright (C) <2014> <J.M. THOORENS>
-;
-; This program is free software: you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation, either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program. If not, see <http://www.gnu.org/licenses/>.
-
-
-; ======================================================================
-; MY_MSP430FR5738_1 BOARD
-; ======================================================================
-;
-; MSP430FR5738 XTAL 32768 Hz
-; 1 --- PJ.4 --- LFXIN
-; 2 --- PJ.5 --- LFXOUT
-;
-; MSP430FR5738 PROG 6PINS ISOLATOR
-; --- VCC <-> 2 "3v3" >--------> Vdd1 1 [| SI |] 8 Vdd2 <---< 3v3 )
-; 20 --- P2.1 <-- 6 "RX0" <---4k7--< A1 2 [| 86 |] 7 B1 <---- TXD \ UART2USB
-; 19 --- P2.0 <-> 1 "TX0" <--+-----> A2 3 [| 22 |] 6 B2 >---> RXD / PL2303TA
-; --- VSS <-> 5 "GND" <- | ----> Gnd1 4 [| EC |] 5 Gnd2 <---> GND )
-; 17 --- TEST --- 3 "TST" |
-; 18 --- RST --- 4 "RST" |
-; +-4k7-< DeepRST <-- GND
-
-; DIP1 AVcc -- ferrite bead -- DVcc
-; DIP2 AVss -- ferrite bead -- DVss
-; DIP3 GND
-; DIP4 P2.4/TA1.0/A7/CD11
-; DIP5 P2.3/TA0.0/A6/CD10
-; DIP6 P1.7/UCB0SOMI/UCB0SCL/TA1.0
-; DIP7 P1.6/UCB0SIMO/UCB0SDA/TA0.0
-; DIP8 P2.2/UCB0CLK
-; DIP9 P2.6
-; DIP10 P2.5/TB0.0
-; DIP11 PJ.3/TCK/CD9
-; DIP12 PJ.2/TMS/ACLK/CD8
-; DIP13 PJ.1/TDI/TCLK/MCLK/CD7
-; DIP14 PJ.0/TDO/TB0OUTH/SMCLK/CD6
-; DIP15 P1.5/TB0.2/UCA0CLK/A5/CD5
-; DIP16 P1.4/TB0.1/UCA0STE/A4/CD4
-; DIP17 P1.3/TA1.2/UCB0STE/A3/CD3
-; DIP18 P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
-; DIP19 P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
-; DIP20 P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
-
-
-; CPU OUTPUT WORLD
-; --- ------------
-; GND <-------+---0V0----------> 1 LCD_Vss
-; VCC <------ | --3V6-----+----> 2 LCD_Vdd
-; | |
-; ___ 470n ---
-; ^ ---
-; / \ 1N4148 |
-; --- |
-; 100n | 2k2 |
-; P1.5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (0V6 without modulation)
-; P1.4 >------------------------> 4 LCD_RS
-; P1.3 >------------------------> 5 LCD_R/W
-; P1.2 >------------------------> 6 LCD_EN
-;
-; PJ.0 <------------------------> 11 LCD_DB4
-; PJ.1 <------------------------> 12 LCD_DB5
-; PJ.2 <------------------------> 13 LCD_DB5
-; PJ.3 <------------------------> 14 LCD_DB7
-;
-; P2.5 <------------------------< S2 LCD contrast +
-; P2.6 <------------------------< S1 LCD contrast -
-;
-; P1.1 >------------------------> SCL I2C MASTER
-; P1.0 >------------------------> SDA I2C MASTER | IR_RC5 receiver
-;
-;
-;
-; VCC DIP1 ---> red SD_CardAdapter VCC
-; GND DIP2 <--> black SD_CardAdapter GND
-; P1.6/UCB0SIMO/UCB0SDA/TA0.0 DIP7 ---> grey SD_CardAdapter SDI (MOSI)
-; P1.7/UCB0SOMI/UCB0SCL/TA1.0 DIP6 <--- purple SD_CardAdapter SDO (MISO)
-; P2.2/UCB0CLK DIP8 ---> orange SD_CardAdapter CLK (SCK)
-; P2.3/TA0.0/A6/CD10 DIP5 <--- violin SD_CardAdapter CD (Card Detect)
-; P2.4/TA1.0/A7/CD11 DIP4 ---> brown SD_CardAdapter CS (Card Select)
-
-; Clocks:
-; 24 MHz DCO intern
-
-; ----------------------------------------------------------------------
-; INIT order : LOCK I/O, WDT, GPIOs, FRAM, Clock, UARTs
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : LOCK I/O as high impedance state
-; ----------------------------------------------------------------------
-
- BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
-; ----------------------------------------------------------------------
-
-; WDT code
- MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : I/O
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION PAIN=PORT2:PORT1
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORT1 usage
-
-; PORT2 usage
-
-Deep_RST_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
-Deep_RST .equ 1 ; P2.0 = TX
-TERM_TXRX .equ 003h ; P2.1 = RX
-TERM_SEL .equ P2SEL1
-TERM_REN .equ P2REN
-
- .IFDEF TERMINALCTSRTS
-;configure P2.2 as RTS output high
-RTS .equ 4
-HANDSHAKOUT .equ P2OUT
-HANDSHAKIN .equ P2IN
- BIS.B #RTS,&HANDSHAKOUT
- .ENDIF
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV #-1,&PAOUT ; all pins 1
- BIS #-1,&PAREN ; all pins 1 with pull resistors
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORTJ
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORTJ usage
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV.B #-1,&PJOUT ; pullup resistors
- BIS.B #-1,&PJREN ; enable pullup/pulldown resistors
-
-; ----------------------------------------------------------------------
-; FRAM config
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
-; ----------------------------------------------------------------------
-
-; DCOCLK: Internal digitally controlled oscillator (DCO).
-
- MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
-
- .IF FREQUENCY = 0.5
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_16 + DIVM_16,&CSCTL3
- MOV #4,X
-
- .ELSEIF FREQUENCY = 1
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_8 + DIVM_8,&CSCTL3
- MOV #8,X
-
- .ELSEIF FREQUENCY = 2
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_4 + DIVM_4,&CSCTL3
- MOV #16,X
-
- .ELSEIF FREQUENCY = 4
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
- MOV #32,X
-
- .ELSEIF FREQUENCY = 8
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #64,X
-
- .ELSEIF FREQUENCY = 16
- MOV #DCORSEL,&CSCTL1 ; Set 16MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #128,X
-
- .ELSEIF FREQUENCY = 24
- MOV #DCORSEL+DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 24 MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #192,X
-
- .ELSEIF
- .error "bad frequency setting, only 0.5,1,2,4,8,16,24 MHz"
- .ENDIF
-
- .IFDEF LF_XTAL
- MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ELSE
- MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ENDIF
- MOV.B #01h, &CSCTL0_H ; Lock CS Registers
-
- BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
- CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
- JZ ClockWaitX ; yes
- .word 0759h ; no RRUM #2,X --> wait only 125 ms
-ClockWaitX MOV #41666,Y ; wait 0.5s before starting after POWER ON
-ClockWaitY SUB #1,Y ;
- JNZ ClockWaitY ; 41666x3 = 125000 cycles delay = 125ms @ 1MHz
- SUB #1,X ; x 4 @ 1 MHZ
- JNZ ClockWaitX ; time to stabilize power source ( 1s )
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : REF
-; ----------------------------------------------------------------------
-
- MOV #8, &REFCTL
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
-; ----------------------------------------------------------------------
-
- .IFDEF LF_XTAL
-; LF Xtal XIN : PJ.4, LF Xtal XOUT : PJ.5
- BIS.B #010h,&PJSEL0 ; SEL0 for only XIN
- BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B
- .ENDIF
-
+++ /dev/null
-; -*- coding: utf-8 -*-
-; MY_MSP430FR5738_2.asm
-; config file for MY_MSP430FR5738 board
-;
-; Copyright (C) <2014> <J.M. THOORENS>
-;
-; This program is free software: you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation, either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program. If not, see <http://www.gnu.org/licenses/>.
-
-
-; ======================================================================
-; MY_MSP430FR5738_2 BOARD
-; ======================================================================
-;
-; MSP430FR5738 XTAL 32768 Hz
-; 1 --- PJ.4 --- LFXIN
-; 2 --- PJ.5 --- LFXOUT
-;
-; MSP430FR5738 PROG 6PINS ISOLATOR
-; --- VCC <-> 2 "3v3" >--------> Vdd1 1 [| SI |] 8 Vdd2 <---< 3v3 )
-; 20 --- P2.1 <-- 6 "RX0" <---4k7--< A1 2 [| 86 |] 7 B1 <---- TXD \ UART2USB
-; 19 --- P2.0 <-> 1 "TX0" <--+-----> A2 3 [| 22 |] 6 B2 >---> RXD / PL2303TA
-; --- VSS <-> 5 "GND" <- | ----> Gnd1 4 [| EC |] 5 Gnd2 <---> GND )
-; 17 --- TEST --- 3 "TST" |
-; 18 --- RST --- 4 "RST" |
-; +-4k7-< DeepRST <-- GND
-
-; DIP1 AVcc -- ferrite bead -- DVcc
-; DIP2 AVss -- ferrite bead -- DVss
-; DIP3 P2.4/TA1.0/A7/CD11
-; DIP4 P2.3/TA0.0/A6/CD10
-; DIP5 P1.7/UCB0SOMI/UCB0SCL/TA1.0
-; DIP6 P1.6/UCB0SIMO/UCB0SDA/TA0.0
-; DIP7 P2.2/UCB0CLK
-; DIP8 P2.6
-; DIP9 P2.5/TB0.0
-; DIP10 GND
-; DIP11 PJ.3/TCK/CD9
-; DIP12 PJ.2/TMS/ACLK/CD8
-; DIP13 PJ.1/TDI/TCLK/MCLK/CD7
-; DIP14 PJ.0/TDO/TB0OUTH/SMCLK/CD6
-; DIP15 P1.5/TB0.2/UCA0CLK/A5/CD5
-; DIP16 P1.4/TB0.1/UCA0STE/A4/CD4
-; DIP17 P1.3/TA1.2/UCB0STE/A3/CD3
-; DIP18 P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
-; DIP19 P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
-; DIP20 P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
-
-
-; CPU OUTPUT WORLD
-; --- ------------
-; GND <-------+---0V0----------> 1 LCD_Vss
-; VCC <------ | --3V6-----+----> 2 LCD_Vdd
-; | |
-; ___ 470n ---
-; ^ ---
-; / \ 1N4148 |
-; --- |
-; 100n | 2k2 |
-; P1.5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (0V6 without modulation)
-; P1.4 >------------------------> 4 LCD_RS
-; P1.3 >------------------------> 5 LCD_R/W
-; P1.2 >------------------------> 6 LCD_EN
-;
-; PJ.0 <------------------------> 11 LCD_DB4
-; PJ.1 <------------------------> 12 LCD_DB5
-; PJ.2 <------------------------> 13 LCD_DB5
-; PJ.3 <------------------------> 14 LCD_DB7
-;
-; P2.5 <------------------------< S2 LCD contrast +
-; P2.6 <------------------------< S1 LCD contrast -
-;
-; P1.1 >------------------------> SCL I2C MASTER
-; P1.0 >------------------------> SDA I2C MASTER | IR_RC5 receiver
-;
-;
-;
-; VCC DIP1 ---> red SD_CardAdapter VCC
-; GND DIP2 <--> black SD_CardAdapter GND
-; P2.4/TA1.0/A7/CD11 DIP3 ---> brown SD_CardAdapter CS (Card Select)
-; P2.3/TA0.0/A6/CD10 DIP4 <--- violin SD_CardAdapter CD (Card Detect)
-; P1.7/UCB0SOMI/UCB0SCL/TA1.0 DIP5 <--- purple SD_CardAdapter SDO (MISO)
-; P1.6/UCB0SIMO/UCB0SDA/TA0.0 DIP6 ---> grey SD_CardAdapter SDI (MOSI)
-; P2.2/UCB0CLK DIP7 ---> orange SD_CardAdapter CLK (SCK)
-
-
-; Clocks:
-; 24 MHz DCO intern
-
-; ----------------------------------------------------------------------
-; INIT order : LOCK I/O, WDT, GPIOs, FRAM, Clock, UARTs
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : LOCK I/O as high impedance state
-; ----------------------------------------------------------------------
-
- BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
-; ----------------------------------------------------------------------
-
-; WDT code
- MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : I/O
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION PAIN=PORT2:PORT1
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORT1 usage
-
-; PORT2 usage
-
-Deep_RST_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
-Deep_RST .equ 1 ; P2.0 = TX
-TERM_TXRX .equ 003h ; P2.1 = RX
-TERM_SEL .equ P2SEL1
-TERM_REN .equ P2REN
-
- .IFDEF TERMINALCTSRTS
-;configure P2.2 as RTS output high
-RTS .equ 4
-HANDSHAKOUT .equ P2OUT
-HANDSHAKIN .equ P2IN
- BIS.B #RTS,&HANDSHAKOUT
- .ENDIF
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV #-1,&PAOUT ; all pins 1
- BIS #-1,&PAREN ; all pins 1 with pull resistors
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORTJ
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORTJ usage
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV.B #-1,&PJOUT ; pullup resistors
- BIS.B #-1,&PJREN ; enable pullup/pulldown resistors
-
-; ----------------------------------------------------------------------
-; FRAM config
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
-; ----------------------------------------------------------------------
-
-; DCOCLK: Internal digitally controlled oscillator (DCO).
-
- MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
-
- .IF FREQUENCY = 0.5
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_16 + DIVM_16,&CSCTL3
- MOV #4,X
-
- .ELSEIF FREQUENCY = 1
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_8 + DIVM_8,&CSCTL3
- MOV #8,X
-
- .ELSEIF FREQUENCY = 2
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_4 + DIVM_4,&CSCTL3
- MOV #16,X
-
- .ELSEIF FREQUENCY = 4
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
- MOV #32,X
-
- .ELSEIF FREQUENCY = 8
-; MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #64,X
-
- .ELSEIF FREQUENCY = 16
- MOV #DCORSEL,&CSCTL1 ; Set 16MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #128,X
-
- .ELSEIF FREQUENCY = 24
- MOV #DCORSEL+DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 24 MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #192,X
-
- .ELSEIF
- .error "bad frequency setting, only 0.5,1,2,4,8,16,24 MHz"
- .ENDIF
-
- .IFDEF LF_XTAL
- MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ELSE
- MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ENDIF
- MOV.B #01h, &CSCTL0_H ; Lock CS Registers
-
- BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
- CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
- JZ ClockWaitX ; yes
- .word 0759h ; no RRUM #2,X --> wait only 125 ms
-ClockWaitX MOV #41666,Y ; wait 0.5s before starting after POWER ON
-ClockWaitY SUB #1,Y ;
- JNZ ClockWaitY ; 41666x3 = 125000 cycles delay = 125ms @ 1MHz
- SUB #1,X ; x 4 @ 1 MHZ
- JNZ ClockWaitX ; time to stabilize power source ( 1s )
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : REF
-; ----------------------------------------------------------------------
-
- MOV #8, &REFCTL
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
-; ----------------------------------------------------------------------
-
- .IFDEF LF_XTAL
-; LF Xtal XIN : PJ.4, LF Xtal XOUT : PJ.5
- BIS.B #010h,&PJSEL0 ; SEL0 for only XIN
- BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B
- .ENDIF
-
+++ /dev/null
-; -*- coding: utf-8 -*-
-; MY_MSP430FR5948.asm
-
-; Fast Forth For Texas Instrument MSP430FR5739
-;
-; Copyright (C) <2014> <J.M. THOORENS>
-;
-; This program is free software: you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation, either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program. If not, see <http://www.gnu.org/licenses/>.
-
-; ======================================================================
-; MY_MSP430FR5948 : MSP430FR5948 TSSOP38 to DIP28 board MAP
-; may be remplaced by MSP430FR5939 TSSOP 38
-; with this first version, RX don't work via prog6pins when SI8622EC is present
-; ======================================================================
-
-; MSP430FR5948 XTAL 32768 Hz
-; 1 --- PJ.4 --- LFXIN
-; 2 --- PJ.5 --- LFXOUT
-
-; MSP430FR5948 PROG 6PINS ISOLATED UARTtoUSB bridge
-; --- VCC <-> 2 "3v3" --------> 1 Vdd1 <| SI |> Vdd2 8 <-- 3v3
-; 24 --- P2.1 <-- 6 "RX0" <----4k7- 2 A1 <| 86 |> B1 7 <-- TXD
-; 23 --- P2.0 <-> 1 "TX0" <--+----> 3 A2 <| 22 |> B2 6 --> RXD
-; --- VSS <-> 5 "GND" <- | ---> 4 Gnd1 <| EC |> Gnd2 5 <-- GND
-; 21 --- TEST --- 3 "TST" |
-; 22 --- RST --- 4 "RST" |
-; +-4k7- DeepRST <-- GND
-
-; MSP430FR5948 DIP28
-; 4,34 --- VCC --- 1 ; +
-; 3,33,38 --- VSS --- 2 ; -
-; 37 --- P2.4 --- 3 ; TA1.0/UCA1CLK/A7/C11
-; 36 --- P2.3 --- 4 ; TA0.0/UCA1STE/A6/C10
-; 5 ; GND
-; 31 --- P1.7 --- 6 ; TB0.4/UCB0SOMI/UCB0SCL/TA1.0
-; 30 --- P1.6 --- 7 ; TB0.3/UCB0SIMO/UCB0SDA/TA0.0
-; 29 --- P3.7 --- 8 ; TB0.6
-; 28 --- P3.6 --- 9 ; TB0.5
-; 27 --- P3.5 --- 10 ; TB0.4/COUT
-; 26 --- P3.4 --- 11 ; TB0.3/SMCLK
-; 20 --- P2.6 --- 12 ; TB0.1/UCA1RXD/UCA1SOMI
-; 25 --- P2.2 --- 13 ; TB0.2/UCB0CLK
-; 19 --- P2.5 --- 14 ; TB0.0/UCA1TXD/UCA1SIMO
-; 15 --- PJ.0 --- 15 ; TDO/TB0OUTH/SMCLK/SRSCG1/C6
-; 16 --- PJ.1 --- 16 ; TDI/TCLK/MCLK/SRSCG0/C7
-; 17 --- PJ.2 --- 17 ; TMS/ACLK/SROSCOFF/C8
-; 18 --- PJ.3 --- 18 ; TCK/SRCPUOFF/C9
-; 14 --- P1.5 --- 19 ; TB0.2/UCA0CLK/A5/C5
-; 13 --- P1.4 --- 20 ; TB0.1/UCA0STE/A4/C4
-; 12 --- P1.3 --- 21 ; TA1.2/UCB0STE/A3/C3
-; 10 --- P3.2 --- 22 ; A14/C14
-; 11 --- P3.3 --- 23 ; A15/C15
-; 9 --- P3.1 --- 24 ; A13/C13
-; 8 --- P3.0 --- 25 ; A12/C12
-; 5 --- P1.0 --- 26 ; TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
-; 6 --- P1.1 --- 27 ; TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
-; 7 --- P1.2 --- 28 ; TA1.1/TA0CLK/COUT/A2/C2
-
-
-; P1.0 - DIP.26
-; P1.1 - DIP.27
-; P1.2 - DIP.28 <------------------------> SDA I2C SOFTWARE MASTER
-; P1.3 - DIP.21 <------------------------> SCL I2C SOFTWARE MASTER
-; P1.4 - DIP.20
-; P1.5 - DIP.19
-; P1.6 - DIP.7 UCB0 SDA/SIMO <------------> SDA I2C MASTER/SLAVE
-; P1.7 - DIP.6 UCB0 SCL/SOMI <------------> SCL I2C MASTER/SLAVE
-;
-; SD_Card socket
-; VCC - -------------------------> VCC SD_CardAdapter
-; P2.2 - DIP.13 -------------------------> TB0.2 LCD_Vo
-; P2.3 - DIP.4 -------------------------> SD_CardAdapter CD (CardDetect)
-; P2.4 - DIP.3 UCA1/CLK ---------------> SD_CardAdapter SCK
-; P2.5 - DIP.14 UCA1/SIMO ---------------> SD_CardAdapter CMD/SDI (MOSI)
-; P2.6 - DIP.12 UCA1/SOMI <--------------- SD_CardAdapter DAT0/SDO (MISO)
-; P2.7 - -------------------------> SD_CardAdapter DAT3/CS (Card Select) (CD at power up)
-; VSS - <------------------------> GND SD_CardAdapter
-;
-;
-; P3.0 - DIP.25 -------------------------> 4 LCD_RS
-; P3.1 - DIP.24 -------------------------> 5 LCD_R/W
-; P3.2 - DIP.23 -------------------------> 6 LCD_EN
-; P3.3 - DIP.22 <------------------------- OUT IR_Receiver (1 TSOP32236)
-; P3.4 - DIP.11 -------------------------> sw1 (hard reset)
-; P3.5 - DIP.10 -------------------------> sw2
-; P3.6 - DIP.9
-; P3.7 - DIP.8
-;
-;
-; PJ.0 - DIP.15 <------------------------> 11 LCD_DB4
-; PJ.1 - DIP.16 <------------------------> 12 LCD_DB5
-; PJ.2 - DIP.17 <------------------------> 13 LCD_DB5
-; PJ.3 - DIP.18 <------------------------> 14 LCD_DB7
-;
-
-; Clocks:
-; 8 MHz DCO intern
-
-; ----------------------------------------------------------------------
-; INIT order : LOCK I/O, WDT, GPIOs, FRAM, Clock, UARTs
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
-; ----------------------------------------------------------------------
-
-; BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
-; ----------------------------------------------------------------------
-
- MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : I/O
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORT1/2
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORT1 usage
-
-; PORT2 usage
-
-Deep_RST_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
-Deep_RST .equ 1 ; P2.0
-TERM_TXRX .equ 003h
-TERM_SEL .equ P2SEL1
-TERM_REN .equ P2REN
-
- .IFDEF TERMINALCTSRTS
- .error "CTS/RTS Control Flow not implemented"
- .ENDIF
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV #-1,&PAOUT ; OUT1
- BIS #-1,&PAREN ; REN1 all pullup resistors
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORT3/4
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORT3 usage
-
-; PORT4 usage
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV #-1,&PBOUT ; pullup
- BIS #-1,&PBREN ; all pullup resistors
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORTJ
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PJ usage
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV.B #-1,&PJOUT ;
- BIS.B #-1,&PJREN ; pullup resistors on unused pins
-
-; ----------------------------------------------------------------------
-; FRAM config
-; ----------------------------------------------------------------------
-
- .IF FREQUENCY = 16
- MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
- MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
- MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
- .ENDIF
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
-; ----------------------------------------------------------------------
-
-; DCOCLK: Internal digitally controlled oscillator (DCO).
-; Startup clock system in max. DCO setting ~8MHz
-
-
-; CS code for MSP430FR5948
- MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
-
- .IF FREQUENCY = 0.5
- MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
- MOV #DIVA_2 + DIVS_2 + DIVM_2,&CSCTL3 ; set all dividers as 2
- MOV #4,X
-
- .ELSEIF FREQUENCY = 1
- MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #8,X
-
- .ELSEIF FREQUENCY = 2
- MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
- MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
- MOV #16,X
-
- .ELSEIF FREQUENCY = 4
- MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #32,X
-
- .ELSEIF FREQUENCY = 8
-; MOV #DCOFSEL2+DCOFSEL1,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #64,X
-
- .ELSEIF FREQUENCY = 16
- MOV #DCORSEL+DCOFSEL2,&CSCTL1 ; Set 16MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #128,X
-
- .ELSEIF
- .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
- .ENDIF
-
- .IFDEF LF_XTAL
- MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ELSE
- MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ENDIF
- MOV.B #01h, &CSCTL0_H ; Lock CS Registers
-
- BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
- CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
- JZ ClockWaitX ; yes
- .word 0759h ; no RRUM #2,X --> wait only 125 ms
-ClockWaitX MOV #41666,Y ; wait 0.5s before starting after POWER ON
-ClockWaitY SUB #1,Y ;
- JNZ ClockWaitY ; 41666x3 = 125000 cycles delay = 125ms @ 1MHz
- SUB #1,X ; x 4 @ 1 MHZ
- JNZ ClockWaitX ; time to stabilize power source ( 1s )
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : REF
-; ----------------------------------------------------------------------
-
- MOV #8, &REFCTL
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
-; ----------------------------------------------------------------------
-
- .IFDEF LF_XTAL
-; LF Xtal XIN : PJ.4, LF Xtal XOUT : PJ.5
- BIS.B #010h,&PJSEL0 ; SEL0 for only XIN
- BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B
- .ENDIF
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
-; ----------------------------------------------------------------------
-
-
-; SYS code
-; see COLD word
+++ /dev/null
-; -*- coding: utf-8 -*-
-; MY_MSP430FR5948.asm
-
-; Fast Forth For Texas Instrument MSP430FR5739
-;
-; Copyright (C) <2014> <J.M. THOORENS>
-;
-; This program is free software: you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation, either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program. If not, see <http://www.gnu.org/licenses/>.
-
-; ======================================================================
-; MY_MSP430FR5948_1 : MSP430FR5948 TSSOP38 to DIP28 board MAP
-; may be remplaced by MSP430FR5939 TSSOP 38
-; Version 1 : added a 4k7 resistor on RX signal between Si8622EC and PROG6PINS
-; SD_CS and SD_CD are inverted
-; ======================================================================
-;
-; MSP430FR5948 XTAL 32768 Hz
-; 1 --- PJ.4 --- LFXIN
-; 2 --- PJ.5 --- LFXOUT
-;
-; MSP430FR5948 PROG 6PINS ISOLATED UARTtoUSB bridge
-; 34 --- DVCC <-> 2 "3v3" --------> 1 Vdd1 <| SI |> Vdd2 8 <-- 3v3
-; 24 --- P2.1 <-- 6 "RX0" <----4k7- 2 A1 <| 86 |> B1 7 <-- TXD
-; 23 --- P2.0 <-> 1 "TX0" <--+----> 3 A2 <| 22 |> B2 6 --> RXD
-; 33 --- DVSS <-> 5 "GND" <- | ---> 4 Gnd1 <| EC |> Gnd2 5 <-- GND
-; 21 --- TEST --- 3 "TST" |
-; 22 --- RST --- 4 "RST" |
-; +-4k7- DeepRST <-- GND
-;
-;
-; DIP28 1 --- 4 AVCC --- ferrite bead --- DVCC 34
-; DIP28 2 --- 3 AVSS --- ferrite bead --- DVSS 33
-;
-; MSP430FR5948 DIP28
-; 4, --- AVCC --- 1 ; +
-; 3,38 --- AVSS --- 2 ; -
-; 3 ; GND
-; 37 --- P2.4 --- 4 ; TA1.0/UCA1CLK/A7/C11
-; 36 --- P2.3 --- 5 ; TA0.0/UCA1STE/A6/C10
-; 30 --- P1.6 --- 6 ; TB0.3/UCB0SIMO/UCB0SDA/TA0.0
-; 31 --- P1.7 --- 7 ; TB0.4/UCB0SOMI/UCB0SCL/TA1.0
-; 29 --- P3.7 --- 8 ; TB0.6
-; 28 --- P3.6 --- 9 ; TB0.5
-; 27 --- P3.5 --- 10 ; TB0.4/COUT
-; 26 --- P3.4 --- 11 ; TB0.3/SMCLK
-; 20 --- P2.6 --- 12 ; TB0.1/UCA1RXD/UCA1SOMI
-; 25 --- P2.2 --- 13 ; TB0.2/UCB0CLK
-; 19 --- P2.5 --- 14 ; TB0.0/UCA1TXD/UCA1SIMO
-; 15 --- PJ.0 --- 15 ; TDO/TB0OUTH/SMCLK/SRSCG1/C6
-; 16 --- PJ.1 --- 16 ; TDI/TCLK/MCLK/SRSCG0/C7
-; 17 --- PJ.2 --- 17 ; TMS/ACLK/SROSCOFF/C8
-; 18 --- PJ.3 --- 18 ; TCK/SRCPUOFF/C9
-; 14 --- P1.5 --- 19 ; TB0.2/UCA0CLK/A5/C5
-; 13 --- P1.4 --- 20 ; TB0.1/UCA0STE/A4/C4
-; 12 --- P1.3 --- 21 ; TA1.2/UCB0STE/A3/C3
-; 10 --- P3.2 --- 22 ; A14/C14
-; 11 --- P3.3 --- 23 ; A15/C15
-; 9 --- P3.1 --- 24 ; A13/C13
-; 8 --- P3.0 --- 25 ; A12/C12
-; 5 --- P1.0 --- 26 ; TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
-; 6 --- P1.1 --- 27 ; TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
-; 7 --- P1.2 --- 28 ; TA1.1/TA0CLK/COUT/A2/C2
-;
-;
-; P1.0 - DIP.26
-; P1.1 - DIP.27
-; P1.2 - DIP.28 <------------------------> SDA I2C SOFTWARE MASTER
-; P1.3 - DIP.21 <------------------------> SCL I2C SOFTWARE MASTER
-; P1.4 - DIP.20
-; P1.5 - DIP.19
-; P1.6 - DIP.6 UCB0 SDA/SIMO <------------> SDA I2C MASTER/SLAVE
-; P1.7 - DIP.7 UCB0 SCL/SOMI <------------> SCL I2C MASTER/SLAVE
-;
-; SD_Card socket
-; VCC - -------------------------> VCC SD_CardAdapter
-; P2.2 - DIP.13 -------------------------> TB0.2 LCD_Vo
-; P2.3 - DIP.5 -------------------------> SD_CardAdapter DAT3/CS (Card Select) (CD at power up)
-; P2.4 - DIP.4 UCA1/CLK ---------------> SD_CardAdapter SCK
-; P2.5 - DIP.14 UCA1/SIMO ---------------> SD_CardAdapter CMD/SDI (MOSI)
-; P2.6 - DIP.12 UCA1/SOMI <--------------- SD_CardAdapter DAT0/SDO (MISO)
-; P2.7 - -------------------------> SD_CardAdapter CD (CardDetect)
-; VSS - <------------------------> GND SD_CardAdapter
-;
-;
-; P3.0 - DIP.25 -------------------------> 4 LCD_RS
-; P3.1 - DIP.24 -------------------------> 5 LCD_R/W
-; P3.2 - DIP.23 -------------------------> 6 LCD_EN
-; P3.3 - DIP.22 <------------------------- OUT IR_Receiver (1 TSOP32236)
-; P3.4 - DIP.11 -------------------------> sw1 (hard reset)
-; P3.5 - DIP.10 -------------------------> sw2
-; P3.6 - DIP.9
-; P3.7 - DIP.8
-;
-;
-; PJ.0 - DIP.15 <------------------------> 11 LCD_DB4
-; PJ.1 - DIP.16 <------------------------> 12 LCD_DB5
-; PJ.2 - DIP.17 <------------------------> 13 LCD_DB5
-; PJ.3 - DIP.18 <------------------------> 14 LCD_DB7
-
-; Clocks:
-; 8 MHz DCO intern
-
-; ----------------------------------------------------------------------
-; INIT order : LOCK I/O, WDT, GPIOs, FRAM, Clock, UARTs
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5
-; ----------------------------------------------------------------------
-
-; BIS #LOCKLPM5,&PM5CTL0 ; unlocked by WARM
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
-; ----------------------------------------------------------------------
-
- MOV #WDTPW+WDTHOLD+WDTCNTCL,&WDTCTL ; stop WDT
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : I/O
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORT1/2
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORT1 usage
-
-; PORT2 usage
-
-Deep_RST_IN .equ P2IN ; TERMINAL TX pin as FORTH Deep_RST
-Deep_RST .equ 1 ; P2.0
-TERM_TXRX .equ 003h
-TERM_SEL .equ P2SEL1
-TERM_REN .equ P2REN
-
- .IFDEF TERMINALCTSRTS
- .error "CTS/RTS Control Flow not implemented"
- .ENDIF
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV #-1,&PAOUT ; OUT1
- BIS #-1,&PAREN ; REN1 all pullup resistors
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORT3/4
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PORT3 usage
-
-; PORT4 usage
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV #-1,&PBOUT ; pullup
- BIS #-1,&PBREN ; all pullup resistors
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : PORTJ
-; ----------------------------------------------------------------------
-
-; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ?
-
-; PJ usage
-
-; PORTx default wanted state : pins as input with pullup resistor
-
- MOV.B #-1,&PJOUT ;
- BIS.B #-1,&PJREN ; pullup resistors on unused pins
-
-; ----------------------------------------------------------------------
-; FRAM config
-; ----------------------------------------------------------------------
-
- .IF FREQUENCY = 16
- MOV.B #0A5h, &FRCTL0_H ; enable FRCTL0 access
- MOV.B #10h, &FRCTL0 ; 1 waitstate @ 16 MHz
- MOV.B #01h, &FRCTL0_H ; disable FRCTL0 access
- .ENDIF
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
-; ----------------------------------------------------------------------
-
-; DCOCLK: Internal digitally controlled oscillator (DCO).
-; Startup clock system in max. DCO setting ~8MHz
-
-
-; CS code for MSP430FR5948
- MOV.B #CSKEY,&CSCTL0_H ; Unlock CS registers
-
- .IF FREQUENCY = 0.5
- MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
- MOV #DIVA_2 + DIVS_2 + DIVM_2,&CSCTL3 ; set all dividers as 2
- MOV #4,X
-
- .ELSEIF FREQUENCY = 1
- MOV #0,&CSCTL1 ; Set 1MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #8,X
-
- .ELSEIF FREQUENCY = 2
- MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
- MOV #DIVA_0 + DIVS_2 + DIVM_2,&CSCTL3
- MOV #16,X
-
- .ELSEIF FREQUENCY = 4
- MOV #DCOFSEL1+DCOFSEL0,&CSCTL1 ; Set 4MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #32,X
-
- .ELSEIF FREQUENCY = 8
-; MOV #DCOFSEL2+DCOFSEL1,&CSCTL1 ; Set 8MHZ DCO setting (default value)
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #64,X
-
- .ELSEIF FREQUENCY = 16
- MOV #DCORSEL+DCOFSEL2,&CSCTL1 ; Set 16MHZ DCO setting
- MOV #DIVA_0 + DIVS_0 + DIVM_0,&CSCTL3 ; set all dividers as 0
- MOV #128,X
-
- .ELSEIF
- .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz"
- .ENDIF
-
- .IFDEF LF_XTAL
- MOV #SELA_LFXCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ELSE
- MOV #SELA_VLOCLK+SELS_DCOCLK+SELM_DCOCLK,&CSCTL2
- .ENDIF
- MOV.B #01h, &CSCTL0_H ; Lock CS Registers
-
- BIS &SYSRSTIV,&SAVE_SYSRSTIV; store volatile SYSRSTIV preserving a pending request for DEEP_RST
- CMP #2,&SAVE_SYSRSTIV ; POWER ON ?
- JZ ClockWaitX ; yes
- .word 0759h ; no RRUM #2,X --> wait only 125 ms
-ClockWaitX MOV #41666,Y ; wait 0.5s before starting after POWER ON
-ClockWaitY SUB #1,Y ;
- JNZ ClockWaitY ; 41666x3 = 125000 cycles delay = 125ms @ 1MHz
- SUB #1,X ; x 4 @ 1 MHZ
- JNZ ClockWaitX ; time to stabilize power source ( 1s )
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : REF
-; ----------------------------------------------------------------------
-
- MOV #8, &REFCTL
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
-; ----------------------------------------------------------------------
-
- .IFDEF LF_XTAL
-; LF Xtal XIN : PJ.4, LF Xtal XOUT : PJ.5
- BIS.B #010h,&PJSEL0 ; SEL0 for only XIN
- BIC.B #RTCHOLD,&RTCCTL1 ; Clear RTCHOLD = start RTC_B
- .ENDIF
-
-; ----------------------------------------------------------------------
-; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
-; ----------------------------------------------------------------------
-
-
-; SYS code
-; see COLD word
With a load, read,create, write, delete SD_CARD files driver, + source files direct copy from PC to SD_Card, its size is still < 9Kb.
It works with all SD CARD memories from 64MB to 64GB. Count 14/11 clock cycles to read/write a byte, with SPI_CLK = MCLK...
-This enables to make a fast data logger with a small footprint as a MSP430FR5738 QFN24.
+This enables to make a fast data logger with a small footprint as a MSP430FR5738 QFN24. To compare with a LPC800 ARM entry-level...
Tested on MSP-EXP430{FR5969,FR5994,FR6989,FR4133} launchpads and CHIPSTICKFR2433, at 0.5, 1, 2, 4, 8, 16 MHz,
and 24MHz on a MSP430FR5738 module.
which ensures its compatibility with the FORTH CORE ANS94 standard.
For MSP430FR4133 choose COMPSMPY.f, COMPHMPY.f for all others.
- Notice that FAST FORTH interprets only SPACE as delimiter (not TAB), BACKSPACE, and CR+LF as end of line.
+ Notice that FAST FORTH interprets lines up to 80 chars, only SPACE as delimiter, only CR+LF as EOL, and BACKSPACE.
And that memory access is limited to 64 kbytes. You can always create FORTH words to access data beyond this limit...
Finally, using the SCITE editor as IDE, you can do everything from its "tools" menu.
What is new ?
-------------
+ V162.
+
+ Added a set of words to enable conditional interpretation/compilation : MARKER [DEFINED] [UNDEFINED] [IF] [ELSE] [THEN]
+ A MARKER word ( defined as {word} to well see it) allows you to wipe some program even if loaded in memory below RST_STATE boundary.
+ see conditional compilation source files in the new subfolder MSP430_COND.
+
+ All interpretation / compilation errors now execute PWR_STATE, so any incorrect definition will be automatically erased,
+ as well as its source file, if any.
+
+ Added a bootloader option which loads BOOT.4TH from SD_Card memory when the cause of reset in SYSRSTIV register is <> 0 (<> WARM).
+ When you download FAST FORTH (SYSRSTIV = 15), and if a sd_card memory is present, BOOT.4TH will load SD_TOOLS.4TH.
+ You can of course modify BOOT.4TH according to your convenience!
+
V161.
SD_Card driver works also with software multiplier (with MSP430FR4133)
Content
-------
-With a size about 5.5 kb (enhanced version with vocabularies 16 threads), Fast Forth contains 116 words:
-
- ASM CODE HI2LO ASSEMBLER COLD WARM (WARM) WIPE
- RST_HERE RST_STATE PWR_HERE PWR_STATE MOVE LEAVE +LOOP LOOP
- DO REPEAT WHILE AGAIN UNTIL BEGIN THEN ELSE
- IF POSTPONE ['] IS IMMEDIATE ; : RECURSE
- ] [ DEFER DOES> CREATE CONSTANT VARIABLE \
- ' ABORT" ABORT QUIT EVALUATE COUNT LITERAL ,
- EXECUTE >NUMBER FIND WORD ." S" TYPE SPACES
- SPACE CR (CR) NOECHO ECHO EMIT (EMIT) (ACCEPT)
- ACCEPT KEY (KEY) C, ALLOT HERE . D.
- U. UD. SIGN HOLD #> #S # <#
- BL STATE BASE >IN J I UNLOOP U<
- > < = 0< 0= ABS NEGATE XOR
- OR AND - + C! C@ ! @
- DEPTH R@ R> >R ROT OVER SWAP DROP
- ?DUP DUP LIT EXIT
+With a size < 6 kb (enhanced version with 16 threads vocabularies), Fast Forth contains 119 words:
+
+ ASM CODE HI2LO COLD WARM (WARM) WIPE RST_HERE
+ RST_STATE PWR_HERE PWR_STATE MOVE LEAVE +LOOP LOOP DO
+ REPEAT WHILE AGAIN UNTIL BEGIN THEN ELSE IF
+ POSTPONE RECURSE IMMEDIATE ; : DEFER DOES> CREATE
+ CONSTANT VARIABLE IS ['] ] [ \ '
+ ABORT" ABORT QUIT EVALUATE COUNT LITERAL , EXECUTE
+ >NUMBER FIND WORD ." S" TYPE SPACES SPACE
+ CR (CR) NOECHO ECHO EMIT (EMIT) (ACCEPT) ACCEPT
+ KEY (KEY) C, ALLOT HERE . D. U.
+ SIGN HOLD #> #S # <# BL STATE
+ BASE >IN TIB PAD J I UNLOOP U<
+ > < = 0> 0< 0= DABS ABS
+ NEGATE XOR OR AND - + C! C@
+ ! @ DEPTH R@ R> >R ROT OVER
+ SWAP NIP DROP ?DUP DUP LIT EXIT
...size that includes its embedded assembler of 71 words:
[CHAR] CHAR CELL+ CELLS CHAR+ CHARS ALIGN ALIGNED
2OVER 2SWAP 2DROP 2DUP 2! 2@ */ */MOD
MOD / /MOD * FM/MOD SM/REM UM/MOD M*
- UM* S>D NIP 2/ 2* MIN MAX 1-
- 1+ RSHIFT LSHIFT INVERT
+ UM* S>D 2/ 2* MIN MAX 1- 1+
+ RSHIFT LSHIFT INVERT
external SD\_TOOLS ADD-ON in SD\_TOOLS.f adds:
assemble (CTRL+0). A window asks you for 4 parameters:
-set device as first param, i.e. MSP430FR5969,
-
-set your target as 2th param, i.e. MSP_EXP430fr5969,
+set device as first param, i.e. MSP_EXP430FR5969,
-then execute. the output is a target.txt file.
+then execute. the output is a target.txt file, i.e. MSP_EXP430FR5969.txt
Send a source file to the FAST FORH target
------------------
-Two .bat files are done in the folder \MSP430-FORTH that enable you to send any source file to any target.
+Three .bat files are done in folders \MSP430-FORTH and \CONDCOMP that enable you to do all you want.
+Double clic on them to see how to do.
-See how to in the file \MSP430-FORTH\send\_source\_file\_to\_target\_readme.txt. Or double click on .bat file
-
-you can also open any source file with scite, and do all via menu Tools.
+you can also open any source file with scite editor, and do all you want via its Tools menu.
SD_Card Load, Read, Write and Delete
HowTo change DIRectory
---------------
- READ" \misc". \misc becomes the current folder.
- READ" ..\" parent folder becomes the current folder.
- READ" \" Root becomes the current folder.
+ LOAD" \misc". \misc becomes the current folder.
+ LOAD" ..\" parent folder becomes the current folder.
+ LOAD" \" Root becomes the current folder.
Drive letters are always ignored.
Downloading source file to SD_Card
------------------------------------------
-to download a file.f/file.4th onto SD_CARD, use Send_file.f_to_SD_CARD_targe.bat/Send_file.4th_to_SD_CARD_targe.bat.
-any file.f will be preprocessed by gema before sending to SD_CARD as file.4th.
-
+to download a source file (.f or .4th) onto SD_CARD target, use CopySourceFileToTarget_SD_Card.bat.
+or use scite.
Double click on one of this bat files to see how to do.
=====
Management of vocabularies (not ANSI). VOCABULARY, DEFINITIONS, ONLY, ALSO, PREVIOUS, CONTEXT, CURRENT, FORTH, ASSEMBLER.
-In fact, it's the operation of the assembler that requires the vocabularies management.
+In fact, it's the the assembler that requires the vocabularies management.
Recognizing prefixed numbers %101011 (bin), $00FE (hex) and #220 (decimal).
case 1.1 : when you type PWR_STATE ==> the program beyond PWR_HERE is lost.
+ case 1.2 : If an error message (reverse video) occurs, PWR_STATE is automatically executed and the program beyond PWR_HERE is lost.
+ In this way, any compilation error is followed by the complete erasure of the uncompleted word,
+ or by that of the downloading source file causing this error.
+ So, it is recommended to finish a source file with at least PWR_HERE to protect it against any subsequent error.
+
case 2 : <reset> ==> performs reset and the program beyond RST_HERE is lost.
if ECHO is on, the WARM display is preceded by the SYSRSTIV value "4", else no display.
case 4.2 : writing -1 in SAVE_SYSRSTIV before COLD = software DEEP_RST ===> same effects
The WARM display is preceded by "-1".
+ case 5 : after FAST FORTH core compilation, the WARM displays SAVE_SYSRSTIV = 15. User may use this information before WARM occurs.
+
If SD\_CARD extention and SD\_CARD memory with \BOOT.4TH included, the cases 1 to 4 start it after displaying of WARM message.
statusbar.text.1=\
li=$(LineNumber) co=$(ColumnNumber) $(OverType) ($(EOLMode)) $(FileAttr)
statusbar.text.2=\
-$(BufferLength) chars in $(NbOfLines) lines. Sel: $(SelLength) chars.
+$(BufferLength) chars in $(NbOfLines) lines. Sel: $(SelHeight) lines, $(SelLength) chars.
statusbar.text.3=\
Now is: Date=$(CurrentDate) Time=$(CurrentTime)
statusbar.text.4=\
# to the types of files seen when opening.
# There is a limit (possibly 256 characters) to the length of a filter,
# so not all source extensions can be in this setting.
-#*.idl;*.odl;*.rc;*.rc2;*.dlg;*.def;make*;*.mak;\
-#*.frm;*.cls;*.ctl;;*.pl;;*.iface;*.e;#*.rb;*.cgi;*.lua;\
-#source.files=*.asm;*.c;*.cc;*.f;*.ff;*.far;*.cpp;*.cxx;*.cs;*.h;*.hh;*.hxx;*.hpp;\
-source.files=*.asm;*.avr;*.tiny;*.mega;*.vb;*.vbs;*.bas;*.bat;*.ini;*.py;*.js;*.properties;*.vhd;*.vhdl
+source.files=*.asm;*.inc;*.pat;*.f;*.4th;*.bat
# Each platform has a different idea of the most important filters
if PLAT_WIN
all.files=All Files (*.*)|*.*|
- top.filters=All Source|$(source.files)|$(all.files)
+ top.filters=$(all.files)All Source|$(source.files)|
if PLAT_GTK
all.files=All Files (*)|*|Hidden Files (.*)|.*|
top.filters=All Source|$(source.files)|$(all.files)
.ENDIF ; CHIPSTICK_FR2433
+ .IFDEF MY_MSP430FR5738
+ .warning "Code for MY_MSP430FR5738"
+DEVICE = "MSP430FR5738"
+;CHIP .equ 5738
+LF_XTAL
+UCA0_UART
+UCB0_SD
+ .include "MSP430FR57xx.inc"
+ .ENDIF ; MY_MSP430FR5738
+
+ .IFDEF MY_MSP430FR5734
+ .warning "Code for MY_MSP430FR5734"
+DEVICE = "MSP430FR5734"
+;CHIP .equ 5734
+UCA0_UART
+ .include "MSP430FR57xx.inc"
+ .ENDIF ; MY_MSP430FR5734_1
+
+ .IFDEF MY_MSP430FR5738_1
+ .warning "Code for MY_MSP430FR5738_1"
+DEVICE = "MSP430FR5738"
+;CHIP .equ 5738
+LF_XTAL
+UCA0_UART
+UCB0_SD
+ .include "MSP430FR57xx.inc"
+ .ENDIF ; MY_MSP430FR5738_1
+
+ .IFDEF MY_MSP430FR5948
+ .warning "Code for MY_MSP430FR5948"
+DEVICE = "MSP430FR5948"
+;CHIP .equ 5948
+UCA0_UART
+UCA1_SD
+ .include "MSP430FR5x6x.inc"
+ .ENDIF ; MY_MSP430FR5948
+
+ .IFDEF MY_MSP430FR5948_1
+ .warning "Code for MY_MSP430FR5948_1"
+DEVICE = "MSP430FR5948"
+;CHIP .equ 5948
+LF_XTAL
+UCA0_UART
+UCA1_SD
+ .include "MSP430FR5x6x.inc"
+ .ENDIF ; MY_MSP430FR5948_1
+
+ .IFDEF JMJ_BOX
+ .warning "Code for JMJ_BOX"
+DEVICE = "MSP430FR5738"
+;CHIP .equ 5738
+UCA0_UART
+ .include "MSP430FR57xx.inc"
+ .ENDIF ; JMJ_BOX
+
+ .IFDEF PA8_PA_MSP430
+ .warning "Code for PA8_PA_MSP430"
+DEVICE = "MSP430FR5738"
+;CHIP .equ 5738
+UCA0_UART
+ .include "MSP430FR57xx.inc"
+ .ENDIF ; PA8_PA_MSP430
+
+ .IFDEF PA_PA_MSP430
+ .warning "Code for PA_PA_MSP430"
+DEVICE = "MSP430FR5738"
+;CHIP .equ 5738
+UCA0_UART
+ .include "MSP430FR57xx.inc"
+ .ENDIF ; PA_PA_MSP430
+
+ .IFDEF PA_Core_MSP430
+ .warning "Code for PA_Core_MSP430"
+DEVICE = "MSP430FR5948"
+;CHIP .equ 5948
+LF_XTAL
+UCA0_UART
+ .include "MSP430FR5x6x.inc"
+ .ENDIF ; PA_Core_MSP430
+
.IF (charfromstr(DEVICE,8) = '5') & (charfromstr(DEVICE,9) = '7')
RAM_1K
.ENDIF
\ No newline at end of file
.IFDEF CHIPSTICK_FR2433
.include "CHIPSTICK_FR2433.asm"
.ENDIF
+ .IFDEF MY_MSP430FR5734
+ .include "MSP430FR5738.asm"
+ .ENDIF
+ .IFDEF MY_MSP430FR5738
+ .include "MSP430FR5738.asm"
+ .ENDIF
+ .IFDEF MY_MSP430FR5738_1
+ .include "MSP430FR5738.asm"
+ .ENDIF
+ .IFDEF MY_MSP430FR5738_2
+ .include "MSP430FR5738.asm"
+ .ENDIF
+ .IFDEF MY_MSP430FR5948
+ .include "MSP430FR5948.asm"
+ .ENDIF
+ .IFDEF MY_MSP430FR5948_1
+ .include "MSP430FR5948.asm"
+ .ENDIF
+ .IFDEF JMJ_BOX
+ .include "MSP430FR5738.asm"
+ .ENDIF
+ .IFDEF PA8_PA_MSP430
+ .include "MSP430FR5738.asm"
+ .ENDIF
+ .IFDEF PA_PA_MSP430
+ .include "MSP430FR5738.asm"
+ .ENDIF
+ .IFDEF PA_Core_MSP430
+ .include "MSP430FR5948.asm"
+ .ENDIF
--- /dev/null
+[BG]
+; Use Eterm look-feel Background extension (on/off)
+BGEnable=on
+
+; Use AlphaBlend API (on/off)
+BGUseAlphaBlendAPI=on
+
+; Susie plugin path
+BGSPIPath=plugin
+
+; Fast window sizing/moving
+BGFastSizeMove=on
+
+; Flickerless window moving
+BGFlickerlessMove=on
+
+; If HideTitle=on and BGNoFrame=on, use window without frame
+; you can resize window with Alt + Shift + LeftDrag
+BGNoFrame=on
+
+; wildcard => random select
+BGThemeFile=theme\*.INI
+
+
+[Tera Term]
+; Tera Term version number
+Version=2.3
+
+; Language (English/Japanese/Russian/Korean/UTF-8)
+Language=English
+
+; User interface language file that includes message strings.
+; Tera Term uses built-in English message when the file or message is not found.
+UILanguageFile=lang\French.lng
+
+; Connecting timeout value(per seconds). No action if the value is zero.
+; Connecting socket could be canceled after the value timeout if the value is greater than zero.
+; The default value is zero(depends on Windows TCP/IP stack implementation).
+ConnectingTimeout=0
+
+; pasting string by clicking mouse right button disabled
+DisablePasteMouseRButton=off
+
+; pasting string by clicking mouse middle button disabled
+DisablePasteMouseMButton=on
+
+; confirm pasting string by clicking mouse right button
+ConfirmPasteMouseRButton=off
+
+; confirm changing clipboard string by clicking mouse right button
+ConfirmChangePaste=on
+ConfirmChangePasteCR=on
+PasteDialogSize=330,220
+ConfirmChangePasteStringFile=
+
+; Scroll out the current buffer when the clear screen does.
+ScrollWindowClearScreen=on
+
+; Reset scrollback on display activity
+AutoScrollOnlyInBottomLine=on
+
+; Starting the selection only by a left button.
+SelectOnlyByLButton=on
+
+; New connection by Alt-N Accelerator key
+AcceleratorNewConnection=on
+
+; Duplicate session by Alt-D Accelerator key disabled
+DisableAcceleratorDuplicateSession=off
+
+; Cygwin connection by Alt-G Accelerator key
+AcceleratorCygwinConnection=on
+
+; Send break by Alt-B Accelerator key disabled
+DisableAcceleratorSendBreak=off
+
+; New connection Menu disabled
+DisableMenuNewConnection=off
+
+; Duplicate session Menu disabled
+DisableMenuDuplicateSession=off
+
+; Send break Menu disabled
+DisableMenuSendBreak=off
+
+; ANSI color definition (in the case FullColor=on)
+; * UseTextColor should be off, or the background and foreground color of
+; VTColor are assigned to color-number 0 and 7 respectively, even if
+; they are specified in ANSIColor.
+; * ANSIColor is a set of 4 values that are color-number(0--15),
+; red-value(0--255), green-value(0--255) and blue-value(0--255).
+ANSIColor=0,0,0,0, 1,255,0,0, 2,0,255,0, 3,255,255,0, 4,128,128,255, 5,255,0,255, 6,0,255,255, 7,255,255,255, 8,64,64,64, 9,192,0,0, 10,0,192,0, 11,192,192,0, 12,64,64,192, 13,192,0,192, 14,0,192,192, 15,192,192,192
+; xterm
+; ANSIColor=0,0,0,0, 1,255,0,0, 2,0,255,0, 3,255,255,0, 4,92,92,255, 5,255,0,255, 6,0,255,255, 7,255,255,255, 8,127,127,127, 9,205,0,0, 10,0,205,0, 11,205,205,0, 12,0,0,238, 13,205,0,205, 14,0,205,205, 15,229,229,229
+; PuTTY
+;ANSIColor=0,0,0,0, 1,255,85,85, 2,85,255,85, 3,255,255,85, 4,85,85,255, 5,255,85,255, 6,85,255,255, 7,255,255,255, 8,85,85,85, 9,187,0,0, 10,0,187,0, 11,187,187,0, 12,0,0,187, 13,187,0,187, 14,0,187,187, 15,187,187,187
+; Tera Term Pro 2.3
+;ANSIColor=0,0,0,0, 1,255,0,0, 2,0,255,0, 3,255,255,0, 4,0,0,255, 5,255,0,255, 6,0,255,255, 7,255,255,255, 8,128,128,128, 9,128,0,0, 10,0,128,0, 11,128,128,0, 12,0,0,128, 13,128,0,128, 14,0,128,128, 15,192,192,192
+; Solarized (http://ethanschoonover.com/solarized)
+;ANSIColor=0,7,54,66, 1,203,75,22, 2,88,110,117, 3,101,123,131, 4,131,148,150, 5,108,113,196, 6,147,161,161, 7,253,246,227, 8,0,43,54, 9,220,50,47, 10,133,153,0, 11,181,137,0, 12,38,139,210, 13,211,54,130, 14,42,161,152, 15,238,232,213
+
+; Enable continued-line copy
+EnableContinuedLineCopy=on
+
+; Mouse cursor type (arrow/ibeam/cross/hand)
+MouseCursor=IBEAM
+
+; Translucent window (0 - 255: transparency value)
+AlphaBlend=255
+
+; Cygwin install path
+CygwinDirectory=C:\cygwin64
+
+; Viewlog Editor path
+ViewlogEditor=C:\Windows\notepad.exe
+
+; Locale for Unicode
+;Locale=chs
+Locale=english
+
+; CodePage for Unicode
+CodePage=1252
+
+; Background color of text uses background color of screen (on/off)
+UseNormalBGColor=on
+
+; Port type (serial/tcpip/namedpipe)
+Port=serial
+
+; Window positions
+VTPos=-2147483648,-2147483648
+TEKPos=-2147483648,-2147483648
+
+; Terminal size
+TerminalSize=128,42
+; Terminal size=window size (on/off)
+TermIsWin=on
+; Auto window resizing option (on/off)
+AutoWinResize=off
+
+; Convert a received new-line (CR) char to CR/CRLF/LF/AUTO
+CRReceive=AUTO
+; New-line code to be transmitted (CR/CRLF/LF)
+CRSend=CRLF
+
+; Terminal ID
+TerminalID=VT100
+
+; Local echo (on/off)
+LocalEcho=off
+
+; Answerback
+Answerback=
+
+; Auto window switching (VT<->TEK; on/off)
+AutoWinSwitch=off
+
+; Kanji code to be received (SJIS/EUC/JIS)
+KanjiReceive=UTF-8
+; JIS Katakana code to be received (7/8)
+KatakanaReceive=8
+
+; Kanji code to be transmitted (SJIS/EUC/JIS)
+KanjiSend=UTF-8
+; JIS Katakana to be transmitted (7/8)
+KatakanaSend=8
+; Kanji-in sequence to be transmitted (@/B)
+KanjiIn=B
+; Kanji-out sequence to be transmitted (J/B)
+KanjiOut=B
+
+; Russian code set used in host
+RussHost=Windows
+; Russian code set used in PC
+RussClient=Windows
+
+; Window title
+Title=Tera Term
+
+; Cursor shape (block/vertical/horizontal)
+CursorShape=block
+
+; Hide title & menu bars and enable popup menu (on/off)
+HideTitle=off
+; Hide menu bar and enable popup menu (on/off)
+PopupMenu=off
+
+; Color mode (on/off)
+EnableANSIColor=on
+PcBoldColor=on
+Aixterm16Color=on
+Xterm256Color=on
+
+; Enable scroll buffer (on/off)
+EnableScrollBuff=on
+; Scroll buffer size
+ScrollBuffSize=12000
+
+; Text and background colors
+; for Normal characters
+VTColor=0,255,0,0,0,0
+; Solarized Dark
+;VTColor=131,148,150,0,43,54
+; Solarized Light
+;VTColor=101,123,131,253,246,227
+;
+; for Bold characters
+EnableBoldAttrColor=on
+VTBoldColor=255,255,0,0,0,0
+; Solarized Dark
+;VTBoldColor=147,161,161,7,54,66
+; Solarized Light
+;VTBoldColor=88,110,117,238,232,213
+;
+; for Blink characters
+EnableBlinkAttrColor=on
+VTBlinkColor=255,0,0,0,0,0
+; Solarized Dark
+;VTBlinkColor=133,153,0,0,43,54
+; Solarized Light
+;VTBlinkColor=133,153,0,253,246,227
+;
+; for Reverse characters
+EnableReverseAttrColor=on
+VTReverseColor=0,0,0,255,255,255
+; Solarized Dark
+;VTReverseColor=0,43,54,131,148,150
+;VTReverseColor=101,123,131,253,246,227
+; Solarized Light
+;VTReverseColor=253,246,227,101,123,131
+;VTReverseColor=131,148,150,0,43,54
+;
+; for URL(hyper link) text color
+EnableURLColor=on
+URLUnderline=on
+URLColor=0,255,255,0,0,0
+; Solarized Dark
+;URLColor=181,137,0,0,43,54
+; Solarized Light
+;URLColor=181,137,0,253,246,227
+;
+
+; Enable clickable URL
+EnableClickableUrl=off
+
+; Launched Browser
+; Firefox example
+; ClickableUrlBrowser=firefox
+; ClickableUrlBrowserArg=-new-tab
+; Opera example
+; ClickableUrlBrowser=opera
+; ClickableUrlBrowserArg=-newpage
+; IE example
+; ClickableUrlBrowser=iexplore
+; ClickableUrlBrowserArg=
+; Chrome example
+; ClickableUrlBrowser=chrome
+; ClickableUrlBrowserArg=
+ClickableUrlBrowser=
+ClickableUrlBrowserArg=
+
+
+; for TEK window
+TEKColor=0,0,0,255,255,255
+
+; TEK color emulation (on/off)
+TEKColorEmulation=off
+
+; Font
+VTFont=Lucida Console,0,-13,0
+; Bold style font (on/off)
+EnableBold=on
+; Font for TEK window
+TEKFont=Terminal,0,-8,255
+; Font quality(default/non-antialiased/antialiased/cleartype)
+FontQuality=default
+
+; Russian code set of the font
+RussFont=Windows
+
+; Backspace key (BS/DEL)
+BSKey=BS
+; transmit DEL by Delete key (on/off)
+DeleteKey=on
+
+; Russian code set used in the keyboard driver
+RussKeyb=Windows
+
+; Meta key (on/off/left/right)
+MetaKey=off
+
+; Meta key sets MSB (off/raw/text)
+Meta8Bit=off
+
+; Application keypad mode disabled.
+DisableAppKeypad=on
+
+; Application cursor mode disabled.
+DisableAppCursor=on
+
+; Serial port parameters
+; Port number
+ComPort=3
+; Baud rate
+BaudRate=921600
+; Parity (even/odd/none/mark/space)
+Parity=none
+; Data (7/8)
+DataBit=8
+; Stop (1/1.5/2)
+StopBit=1
+; Flow control (x/hard/none)
+FlowCtrl=x
+; Transmit delay per character (in msec)
+DelayPerChar=0
+; Transmit delay per line (in msec)
+DelayPerLine=0
+
+; TCP/IP parameters
+; TCP port#
+TCPPort=80
+; Telnet flag (on/off)
+Telnet=off
+; Telnet terminal type
+;TermType=vt100
+TermType=xterm
+
+; Auto window closing option (on/off)
+AutoWinClose=on
+; History list of hosts
+HistoryList=on
+
+; Binary flag for Send File (on/off)
+TransBin=off
+
+; without transfer dialog flag for Send File (on/off)
+FTHideDialog=off
+
+; Binary flag for Log (on/off)
+LogBinary=off
+; Log append (on/off)
+LogAppend=on
+; plain text flag for Log (on/off)
+LogTypePlainText=on
+; timestamp flag for Log (on/off)
+LogTimestamp=off
+; without transfer dialog flag for Log (on/off)
+LogHideDialog=off
+; Current all buffer included in first (on/off)
+LogIncludeScreenBuffer=off
+
+; Default Log file name. You can specify strftime format to here.
+LogDefaultName=teraterm.log
+; Default path to save the log file.
+LogDefaultPath=
+; Auto start logging with default log file name.
+LogAutoStart=off
+
+; === Log Rotate ===
+; Mode: 0(none), 1(size)
+LogRotate=0
+; Size
+LogRotateSize=0
+; Size type: 0(byte), 1(KB), 2(MB)
+LogRotateSizeType=0
+; Step: 0(none), >=1(count times)
+LogRotateStep=0
+
+; Deferred Log Write Mode (on/off)
+DeferredLogWriteMode=on
+
+
+; XMODEM option (checksum/crc/1k)
+XmodemOpt=checksum
+; Binary flag for XMODEM Receive and ZMODEM Send (on/off)
+XmodemBin=on
+
+; XMODEM receive command
+XmodemRcvCommand=
+
+; Default directory for file transfers
+FileDir=A:\projets\msp430\MSP430-FORTH
+
+; Filter for send file
+FileSendFilter=
+
+; SCP sending directory
+ScpSendDir=
+
+; Save Broadcast Command History
+BroadcastCommandHistory=on
+
+; Broadcast command enabling flag on the dialog window (on/off)
+AcceptBroadcast=on
+
+; Number of broadcast command history
+MaxBroadcatHistory=99
+
+;------ special options (see Tera Term help)
+
+; C1 (8-bit) control characters
+Accept8BitCtrl=on
+Send8BitCtrl=off
+
+; Accept remote-controlled window title changing (off/overwrite/ahead/last)
+AcceptTitleChangeRequest=overwrite
+
+; Wrong kanji-out ^[(H (Japanese only)
+AllowWrongSequence=off
+
+; Alternate screen buffer support
+AlternateScreenBuffer=on
+
+; Automatic serial reconnection when serial cable is inserted and extracted(Windows XP or later).
+AutoComPortReconnect=on
+
+; When serial port is specified with with /C= option and the port does not exist,
+; Tera Term will wait for port connection.
+WaitCom=off
+
+; Auto file renaming for downloading
+AutoFileRename=on
+
+; Auto text copying
+AutoTextCopy=on
+
+; Back wrap
+BackWrap=off
+
+; Beep by BEL (on/off/visual)
+Beep=on
+
+; Beep over-used
+BeepOverUsedTime=2
+BeepOverUsedCount=5
+BeepSuppressTime=5
+
+; Beep on connection & disconnection
+BeepOnConnect=off
+
+; B-Plus auto receive
+BPAuto=off
+
+; Escape all control characters in B-Plus
+BPEscCtl=off
+
+; B-Plus log
+BPLog=off
+
+; Clear serial port buffer when port opening
+ClearComBuffOnOpen=on
+
+; Clear screen when window is resized
+ClearOnResize=on
+
+; Clear screen after the connection is closed
+ClearScreenOnCloseConnection=off
+
+; Clipboard access from remote (on/off/read/write)
+ClipboardAccessFromRemote=off
+
+; "Disconnect?" warning
+ConfirmDisconnect=on
+
+; Control characters in kanji (Japanese only)
+CtrlInKanji=on
+
+; Confirm send a file when drag and drop
+ConfirmFileDragAndDrop=on
+
+; allow the sequences related to cursor control
+CursorCtrlSequence=off
+
+; Display all characters (debug mode)
+Debug=off
+; Debug mode type which can be selected by user.
+; on|all = All types
+; off|none = Disabled debug mode
+; normal = usual teraterm debug mode
+; hex = hex output
+; noout = disable output completely
+DebugModes=all
+
+; Delimters for word selection
+; (compatible with earlier versions of Tera Term)
+; DelimList=$20
+; DelimDBCS=off
+DelimList=$20!"#$24%&'()*+,:;<=>?@[\]^`{|}
+DelimDBCS=on
+
+; Disable mouse event tracking when Control-Key is pressed.
+DisableMouseTrackingByCtrl=on
+
+; Disable wheel to cursor translation when Control-Key is pressed.
+DisableWheelToCursorByCtrl=on
+
+; Line at a time mode
+EnableLineMode=on
+
+; Popup menu
+EnablePopupMenu=on
+
+; "Show menu bar" command
+EnableShowMenu=on
+
+; Enable the status line
+EnableStatusLine=on
+
+; High speed file transfer on serial connection.
+FileSendHighSpeedMode=on
+
+; Display "New Connection" dialog on startup
+HostDialogOnStartup=on
+
+; Enable IME / inline input (Japanese only)
+IME=on
+IMEInline=on
+
+IMERelatedCursor=off
+
+; Windows 7 jump list support
+JumpList=on
+
+; Join Split URL
+JoinSplitURL=off
+JoinSplitURLIgnoreEOLChar=\
+
+; Kermit log
+KmtLog=off
+; Kermit CAPAS: Ability to transmit and receive extended-length packets
+KmtLongPacket=off
+; Kermit CAPAS: Ability to accept "A" packets (file attributes)
+KmtFileAttr=off
+
+; Language selection
+LanguageSelection=on
+
+; Lock Terminal Unique ID
+LockTUID=on
+
+; Exclusive lock for log file
+LogLockExclusive=on
+
+; Max scroll buffer size
+MaxBuffSize=500000
+
+; Max serial port number
+MaxComPort=256
+
+; Max buffer size of OSC string
+MaxOSCBufferSize=4096
+
+; Mouse event tracking
+MouseEventTracking=on
+
+; Maximized window bug tweak
+MaximizedBugTweak=2
+
+; Nonblinking cursor
+NonblinkingCursor=off
+
+; Polygon cursor for KILLFOCUS
+KillFocusCursor=on
+
+; Delay for pass-thru printing (in secs)
+PassThruDelay=3
+
+; Direct pass-thru printing
+PassThruPort=
+
+; Delay for paste per each lines (in msec)
+PasteDelayPerLine=10
+
+; Allow the sequences related to printer control
+PrinterCtrlSequence=on
+
+; Printer font
+PrnFont=
+
+; Page margins for printing
+; (left, right, top and bottom in 1/100 inches)
+PrnMargin=50,50,50,50
+
+; Quick-VAN log
+QVLog=off
+
+; Quick-VAN window size
+QVWinSize=8
+
+; Russian code set of printer font
+RussPrint=Windows
+
+; Save VT Window position
+SaveVTWinPos=off
+
+; Max lines per one jump scroll
+ScrollThreshold=12
+
+; Scroll line count with mouse wheel button
+MouseWheelScrollLine=3
+
+; Text selection on window activation
+SelectOnActivate=on
+
+; Break signal length (in msec)
+SendBreakTime=1000
+
+; Startup macro
+StartupMacro=
+
+; Strict Key Mapping
+StrictKeyMapping=off
+
+; Tab Stop Modify Sequence (on/off/combination of HTS,HTS7,HTS8,TBC,TBC0,TBC3)
+TabStopModifySequence=on
+
+; TEK mouse code
+TEKGINMouseCode=32
+
+; Telnet Auto Detection
+TelAutoDetect=on
+
+; Telnet binary option
+TelBin=off
+
+; Telnet auto echo
+TelEcho=off
+
+; Telnet log
+TelLog=off
+
+; Standard telnet port
+TelPort=23
+
+; Keep-Alive packet sending interval on telnet connection (per second, 0=disabled)
+TelKeepAliveInterval=300
+
+; Auto setup for non-telnet
+TCPLocalEcho=off
+TCPCRSend=
+
+; Terminal Unique ID
+TerminalUID=FFFFFFFF
+
+; Title format
+; format ID: 5(000101) <title> - <host/port> VT/TEK
+; format ID: 13(001101) <host/port> - <title> VT/TEK
+; format ID: 29(011101) <host:tcpport/port> - <title> VT/TEK
+; format ID: 45(101101) <host/port:baud> - <title> VT/TEK
+; format ID: 61(111101) <host:tcpport/port:baud> - <title> VT/TEK
+TitleFormat=45
+
+; Allow the sequences related to title report (accept/ignore/empty)
+TitleReportSequence=empty
+
+; Translate mouse wheel to cursor key when application cursor mode
+TranslateWheelToCursor=on
+
+; Trim trailing new line character when pasting
+TrimTrailingNLonPaste=off
+
+; Unknown Unicode character handling
+UnknownUnicodeCharacterAsWide=off
+
+; Mapping of Unicode to DEC special character
+; The sum of following values:
+; 1 : Box drawings (U+2500-U+257F)
+; 2 : Bullet (U+2022)
+; Hyphenation point (U+2027)
+; Light shade (25%) (U+2591)
+; Medium shade (50%) (U+2592)
+; Dark shade (75%) (U+2593)
+; Black small square (U+25AA)
+; Black vertical rectangle (U+25AE)
+; Black verty small square (U+2B1D)
+; 4 : Middle dot (U+00B7)
+; One dot leader (U+2024)
+; Bullet operator (U+2219)
+UnicodeToDecSpMapping=3
+
+; White & black color conversion
+UseTextColor=off
+
+; VT Compatible Tab
+VTCompatTab=off
+
+; Space between characters (lines)
+VTFontSpace=0,0,0,0
+
+; Window Icon
+VTIcon=Default
+TEKIcon=Default
+
+; Scaling factors for printing (in pixels per inch)
+VTPPI=0,0
+TEKPPI=0,0
+
+; `wait4all' macro command
+Wait4allMacroCommand=off
+
+; allow the sequences related to window control
+WindowCtrlSequence=on
+
+; allow the sequences related to window report
+WindowReportSequence=on
+
+; [Window] menu
+WindowMenu=on
+
+; XMODEM log
+XmodemLog=off
+
+; XMODEM Timeout value(v1,v2,v3,v4,v5) by seconds
+; v1=NAK mode: Timeout value for first packet
+; v2=CRC mode: Timeout value for first packet
+; v3=Timeout short time
+; v4=Timeout long time
+; v5=Timeout very long time
+XmodemTimeouts=10,3,10,20,60
+
+; YMODEM log
+YmodemLog=off
+
+; YMODEM receive command
+YmodemRcvCommand=
+
+; YMODEM Timeout value(v1,v2,v3,v4,v5) by seconds
+; v1=NAK mode: Timeout value for first packet
+; v2=CRC mode: Timeout value for first packet
+; v3=Timeout short time
+; v4=Timeout long time
+; v5=Timeout very long time
+YmodemTimeouts=10,3,10,20,60
+
+; ZMODEM auto receive
+ZmodemAuto=off
+
+; ZMODEM parameters for sending
+ZmodemDataLen=1024
+ZmodemWinSize=32767
+
+; Escape all control characters in ZMODEM
+ZmodemEscCtl=off
+
+; ZMODEM log
+ZmodemLog=off
+
+; ZMODEM receive command
+ZmodemRcvCommand=rz
+
+; ZMODEM Timeout value(v1,v2,v3,v4) by seconds
+; v1=Timeout value for serial port
+; v2=Timeout value for TCP/IP port
+; v3=Timeout value for initial packet
+; v4=Timeout value for final packet
+ZmodemTimeouts=10,0,10,3
+NormalizeLineBreakOnPaste=off
+NotifyClipboardAccess=on
+
+;------ end of special options
+
+[TTSSH]
+; SSH enabled flag (1=enabled 0=disabled)
+Enabled=1
+
+; default login username (setup to authentication dialog)
+DefaultUserName=
+DefaultForwarding=
+
+; Cipher algorithm order
+; 2...DES(SSH1), 3...3DES(SSH1), 6...Blowfish(SSH1), 7...3DES-CBC,
+; 8...AES128-CBC, 9...AES192-CBC, :...AES256-CBC, ;...Blowfish-CBC,
+; <...AES128-CTR, =...AES192-CTR, >...AES256-CTR, ?...Arcfour,
+; @...Arcfour128, A...Arcfour256, B...CAST128-CBC, C...3DES-CTR,
+; D...Blowfish-CTR, E...CAST128-CTR, F...Camellia128-CBC,
+; G...Camellia192-CBC, H...Camellia256-CBC, I...Camellia128-CTR,
+; J...Camellia192-CTR, K...Camellia256-CTR
+; 0...Ciphers below this line are disabled.
+CipherOrder=K>H:J=G9I<F8C7D;EB30A@?62
+
+; KEX algorithm order(SSH2)
+; 1...diffie-hellman-group1-sha1
+; 2...diffie-hellman-group14-sha1
+; 3...diffie-hellman-group-exchange-sha1
+; 4...diffie-hellman-group-exchange-sha256
+; 5...ecdh-sha2-nistp256
+; 6...ecdh-sha2-nistp384
+; 7...ecdh-sha2-nistp521
+; 8...diffie-hellman-group14-sha256
+; 9...diffie-hellman-group16-sha512
+; :...diffie-hellman-group18-sha512
+; 0...KEXs below this line are disabled.
+KexOrder=567:9843210
+
+; minimal size in bits of an acceptable group in SSH_MSG_KEY_DH_GEX_REQUEST packet
+GexMinimalGroupSize=0
+
+; Host Key algorithm order(SSH2)
+; 2...ssh-rsa
+; 3...ssh-dss
+; 4...ecdh-sha2-nistp256
+; 5...ecdh-sha2-nistp384
+; 6...ecdh-sha2-nistp521
+; 7...ssh-ed25519
+; 0...below this line are disabled.
+HostKeyOrder=4567230
+
+; MAC algorithm order(SSH2)
+; 1...hmac-sha1
+; 2...hmac-md5
+; 3...hmac-sha1-96
+; 4...hmac-md5-96
+; 5...hmac-ripemd160@openssh.com
+; 6...hmac-sha2-256
+; 8...hmac-sha2-512
+; 0...below this line are disabled.
+MacOrder=86152034
+
+; Compression algorithm order(SSH2)
+; 1...none
+; 2...zlib
+; 3...zlib@openssh.com(Delayed Compression)
+; 0...below this line are disabled.
+CompOrder=3210
+; packet compression level (0=none)
+Compression=0
+
+
+KnownHostsFiles=ssh_known_hosts
+DefaultRhostsLocalUserName=
+DefaultRhostsHostPrivateKeyFile=
+DefaultRSAPrivateKeyFile=
+DefaultAuthMethod=3
+; Debug message logging level of `TTSSH.LOG'.
+; The default value is disabled(0).
+; LOG_LEVEL_FATAL 5
+; LOG_LEVEL_ERROR 10
+; LOG_LEVEL_URGENT 20
+; LOG_LEVEL_WARNING 30
+; LOG_LEVEL_NOTIFY 50
+; LOG_LEVEL_INFO 80
+; LOG_LEVEL_VERBOSE 100
+; LOG_LEVEL_SSHDUMP 200
+LogLevel=0
+WriteBufferSize=2097152
+
+; SSH protocol version (1 or 2)
+ProtocolVersion=2
+
+; SSH heartbeat(keepalive): per second (0=disabled)
+HeartBeat=60
+
+; Remember password in memory (1=enabled 0=disabled)
+RememberPassword=1
+
+; Check supported auth methods with "none" method (1=enabled 0=disabled)
+CheckAuthListFirst=0
+
+; Enable connection to the server that has RSA key length less than 768 bit (1=enabled 0=disabled)
+EnableRsaShortKeyServer=0
+
+; SSH agent forwarding (pageant) (1=enabled 0=disabled)
+ForwardAgent=0
+
+; Confirm SSH agent forwarding (1=enabled 0=disabled)
+ForwardAgentConfirm=1
+
+; Verify host key by DNS (1=enabled 0=disabled)
+VerifyHostKeyDNS=0
+
+; SSH Icon
+SSHIcon=Default
+
+; Disable error popup-message box
+; 0 ... Default(not disabling)
+; 1 ... Sending forwarded data to a local port
+DisablePopupMessage=0
+
+; X11 Forwarding
+X11Display=
+
+; Host key rotation support (derived from OpenSSH 6.8)
+; 0 ... Disabled
+; 1 ... Enabled
+; 2 ... Enabled with User's confirmation
+UpdateHostkeys=0
+ForwardAgentNotify=1
+
+
+[TTProxy]
+ConnectionTimeout="10"
+SocksResolve="auto"
+TelnetHostnamePrompt=">> Host name: "
+TelnetUsernamePrompt="Username:"
+TelnetPasswordPrompt="Password:"
+TelnetConnectedMessage="-- Connected to "
+TelnetErrorMessage="!!!!!!!!"
+
+[TTXKanjiMenu]
+UseOneSetting=on
+
+[TTXttyrec]
+RecordStartSize=on
+
+[TTXRecurringCommand]
+Enable=off
+Command=
+Interval=300
+AddNewLine=off
+
+[Resize Menu]
+; 80x62
+;ResizeMenu1= 80, 24
+;
+; 120x52
+;ResizeMenu2=120, 52
+;
+; Width: no-change, Height: 52
+;ResizeMenu3= 0, 52
+;
+; Width: 80, Height: no-change
+;ResizeMenu4= 80, 0
+
+;------ Telnet host list
+; Max number of hosts is 200.
+; You can edit this list in the [Setup] TCP/IP dialog box.
+;[Hosts]
+; Host name
+;Host1=myhost.example.com
+; IPv4 address
+;Host2=192.0.2.1
+; IPv6 address
+;Host3=[2001:db8:1:2:8401:02ff:fe03:0405]
+; IPv6 address with interface number
+;Host4=[fe80::8401:02ff:fe03:0405%3]
+; Host name with option
+;Host5=myhost.example.com /F=myhost.ini
+; Host name with user, port and option
+;Host6=user@myhost.example.com:10022 /ssh
+; URL
+;Host7=ssh://user@myhost.example.com
+; COM1 port
+;Host8=/C=1
+; Replay a file
+;Host9=/R=readme.txt
+
+[Hosts]
+Host1=192.168.4.2
+Host2=192.168.0.8
+Host3=192.168.1.8
+Host4=192.168.1.8/
+Host5=myhost.example.com
+Host6=192.0.2.1
+Host7=[2001:db8:1:2:8401:2ff:fe03:405]
+Host8=[fe80::8401:2ff:fe03:405%3]
+Host9=myhost.example.com /F=myhost.ini
+Host10=user@myhost.example.com:10022 /ssh
+Host11=ssh://user@myhost.example.com
+Host12=/C=1 ;serial port
+Host13=\\.\pipe\vmware-serial-port ;Named pipe
+Host14=/R=readme.txt ;replay a file
!MSP430FR2xxx.pat
-LPM4,=\$F8,! SR(LPM4+GIE)
-LPM3,=\$D8,! SR(LPM3+GIE)
-LPM2,=\$98,! SR(LPM2+GIE)
-LPM1,=\$58,! SR(LPM1+GIE)
-LPM0,=\$18,! SR(LPM0+GIE)
+LPM4=\$F8! SR(LPM4+GIE)
+LPM3=\$D8! SR(LPM3+GIE)
+LPM2=\$98! SR(LPM2+GIE)
+LPM1=\$58! SR(LPM1+GIE)
+LPM0=\$18! SR(LPM0+GIE)
SFRIE1=\$100! \ SFR enable register
P2SEL0=\$20B!
P2SEL1=\$20D!
P2SELC=\$217!
-P2IES=\$218!
+P2IES=\$219!
P2IE=\$21B!
P2IFG=\$21D!
!MSP430FR2x4x_FastForth.pat
+
! ===========================================================
! MSP430FR2xxx and FR4xxx DEVICES HAVE SPECIFIC RAM ADDRESSES
! ===========================================================
SCG0=\$40! = SR(6) SCG0
SCG1=\$80! = SR(7) SCG1
V=\$100! = SR(8) oVerflow flag
-UF1=\$200! = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
-UF2=\$400! = SR(10) User Flag 2
-UF3=\$800! = SR(11) User Flag 3
+UF9=\$200! = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
+UF10=\$400! = SR(10) User Flag 2
+UF11=\$800! = SR(11) User Flag 3
C\@=C\@
C\!=C\!
! ============================================
! symbolic codes :
! ============================================
+POP=MOV \@R1+,! \ MOV @RSP+,
+POP\.B=MOV\.B \@R1+,! \ MOV.B @RSP+,
RET=MOV \@R1+,R0! \ MOV @RSP+,PC
NOP=MOV 0,R3! \ one word one cycle
NOP2=\$3C00 ,! \ compile JMP 0 one word two cycles
NEXT=MOV \@R13+,R0! \ MOV @IP+,PC
+! ============================================
+! FORTH DOxxx registers :
+! ============================================
+rDOCOL=R7!
+rDOVAR=R6!
+rDOCON=R5!
+rDODOES=R4!
! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
! those addresses are usable with the symbolic assembler
INIDP=\$180C! define RST_STATE, init by wipe
INIVOC=\$180E! define RST_STATE, init by wipe
-XON=\$1810!
-XOFF=\$1812!
+RXON=\$1810!
+RXOFF=\$1812!
ReadSectorWX=\$1814! call with W = SectorLO X = SectorHI
WriteSectorWX=\$1816! call with W = SectorLO X = SectorHI
! ============================================
+! FORTH RAM areas :
+! ============================================
+LSTACK_SIZE=\#16! words
+PSTACK_SIZE=\#48! words
+RSTACK_SIZE=\#48! words
+PAD_LEN=\#84! bytes
+TIB_LEN=\#80! bytes
+HOLD_SIZE=\#34! bytes
+
+! ============================================
! FastForth RAM memory map (>= 1k):
! ============================================
-LSATCK=\$2000! \ leave stack, grow up
LEAVEPTR=\$2000! \ Leave-stack pointer, init by QUIT
+LSATCK=\$2000! \ leave stack, grow up
PSTACK=\$2080! \ parameter stack, grow down
RSTACK=\$20E0! \ Return stack, grow down
-PAD=\$20E2! \ user scratch pad buffer, grow up
-TIB=\$2138! \ Terminal input buffer, grow up
+PAD_ORG=\$20E2! \ user scratch pad buffer, grow up
+TIB_ORG=\$2138! \ Terminal input buffer, grow up
BASE_HOLD=\$21AA! \ BASE HOLD area, grow down
! ----------------------
HandleOutOfBound=\$2500!
SDIB=\$2500!
-
+SDIB_LEN=\#84!
SD_END_DATA=\$2554!
\ No newline at end of file
!MSP430fr57xx.pat
-LPM4,=\$F8,! SR(LPM4+GIE)
-LPM3,=\$D8,! SR(LPM3+GIE)
-LPM2,=\$98,! SR(LPM2+GIE)
-LPM1,=\$58,! SR(LPM1+GIE)
-LPM0,=\$18,! SR(LPM0+GIE)
+LPM4=\$F8! SR(LPM4+GIE)
+LPM3=\$D8! SR(LPM3+GIE)
+LPM2=\$98! SR(LPM2+GIE)
+LPM1=\$58! SR(LPM1+GIE)
+LPM0=\$18! SR(LPM0+GIE)
P2SEL0=\$20B!
P2SEL1=\$20D!
P2SELC=\$217!
-P2IES=\$218!
+P2IES=\$219!
P2IE=\$21B!
P2IFG=\$21D!
P4SEL0=\$22B!
P4SEL1=\$22D!
P4SELC=\$237!
-P4IES=\$238!
+P4IES=\$239!
P4IE=\$23B!
P4IFG=\$23D!
TACLR=4!
TAIFG=1!
-TBCLR=2!
+TBCLR=4!
TBIFG=1!
CCIFG=1!
TB2EX0=\$460! \ TB2 expansion register 0
TB2IV=\$46E! \ TB2 interrupt vector
+! RTC_B
RTCCTL0=\$4A0! \ RTC control 0
RTCCTL1=\$4A1! \ RTC control 1
RTCCTL2=\$4A2! \ RTC control 2
BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
BCD2BIN=\$4BE! \ BCD-to-binary conversion register
RTCHOLD=\$40!
+RTCRDY=\$10!
MPY=\$4C0! \ 16-bit operand 1 \96 multiply
MPYS=\$4C2! \ 16-bit operand 1 \96 signed multiply
SCG0=\$40! = SR(6) SCG0
SCG1=\$80! = SR(7) SCG1
V=\$100! = SR(8) oVerflow flag
-UF1=\$200! = SR(9) User Flag 1, set by ?NUMBER, used and reset to 0 by following LITERAL (double number process) else free for use.
-UF2=\$400! = SR(10) User Flag 2
-UF3=\$800! = SR(11) User Flag 3
+UF9=\$200! = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
+UF10=\$400! = SR(10) User Flag 2
+UF11=\$800! = SR(11) User Flag 3
C\@=C\@
C\!=C\!
! symbolic codes :
! ============================================
RET=MOV \@R1+,R0! \ MOV @RSP+,PC
-NOP=MOV 0,R3! \ one word one cycle
+NOP=MOV \#0,R3! \ one word one cycle
NOP2=\$3C00 ,! \ compile JMP 0 one word two cycles
NOP3=MOV R0,R0! \ MOV PC,PC one word three cycles
NEXT=MOV \@R13+,R0! \ MOV @IP+,PC
+SEMI=MOV \@R1+,R13 \n MOV \@R13+,R0!
+! ============================================
+! FORTH DOxxx registers :
+! ============================================
+rDOCOL=R7!
+rDOVAR=R6!
+rDOCON=R5!
+rDODOES=R4!
! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
! those addresses are usable with the symbolic assembler
INIDP=\$180C! define RST_STATE, init by wipe
INIVOC=\$180E! define RST_STATE, init by wipe
-XON=\$1810!
-XOFF=\$1812!
+RXON=\$1810!
+RXOFF=\$1812!
ReadSectorWX=\$1814! call with W = SectorLO X = SectorHI
WriteSectorWX=\$1816! call with W = SectorLO X = SectorHI
! ============================================
+! FORTH RAM areas :
+! ============================================
+LSTACK_SIZE=\#16! words
+PSTACK_SIZE=\#48! words
+RSTACK_SIZE=\#48! words
+PAD_LEN=\#84! bytes
+TIB_LEN=\#80! bytes
+HOLD_SIZE=\#34! bytes
+
+! ============================================
! FastForth RAM memory map (= 1k):
! ============================================
-LSATCK=\$1C00! \ leave stack, grow up
LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT
+LSATCK=\$1C00! \ leave stack, grow up
PSTACK=\$1C80! \ parameter stack, grow down
RSTACK=\$1CE0! \ Return stack, grow down
-PAD=\$1CE2! \ user scratch pad buffer, grow up
-TIB=\$1D38! \ Terminal input buffer, grow up
+PAD_ORG=\$1CE2! \ user scratch pad buffer, grow up
+TIB_ORG=\$1D38! \ Terminal input buffer, grow up
BASE_HOLD=\$1DAA! \ BASE HOLD area, grow down
! ----------------------
@define{@read{/config/gema/MSP430FR5x6x.pat}}
+! \ RTC_B
+RTCCTL0=\$4A0! \ RTC control 0
+RTCCTL1=\$4A1! \ RTC control 1
+RTCCTL2=\$4A2! \ RTC control 2
+RTCCTL3=\$4A3! \ RTC control 3
+RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
+RTCPS0=\$4AC! \ RTC prescaler 0
+RTCPS1=\$4AD! \ RTC prescaler 1
+RTCIV=\$4AE! \ RTC interrupt vector word
+RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCDAY=\$4B4! \ RTC days
+RTCMON=\$4B5! \ RTC month
+RTCYEAR=\$4B6!
+RTCYEARL=\$4B6! \ RTC year low
+RTCYEARH=\$4B7! \ RTC year high
+RTCAMIN=\$4B8! \ RTC alarm minutes
+RTCAHOUR=\$4B9! \ RTC alarm hours
+RTCADOW=\$4BA! \ RTC alarm day of week
+RTCADAY=\$4BB! \ RTC alarm days
+BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE! \ BCD-to-binary conversion register
+RTCHOLD=\$40!
+RTCRDY=\$10!
+
! ----------------------------------------------
! MSP430fr5948 MEMORY MAP
! ----------------------------------------------
eUSCI_A1_Vec=\$FFE6!
TA0_x_Vec=\$FFE8!
TA0_0_Vec=\$FFEA!
-ADC10_B_Vec=\$FFEC!
+ADC12_B_Vec=\$FFEC!
eUSCI_B0_Vec=\$FFEE!
eUSCI_A0_Vec=\$FFF0!
WDT_Vec=\$FFF2!
@define{@read{/config/gema/MSP430FR5x6x.pat}}
+! \ RTC_B
+RTCCTL0=\$4A0! \ RTC control 0
+RTCCTL1=\$4A1! \ RTC control 1
+RTCCTL2=\$4A2! \ RTC control 2
+RTCCTL3=\$4A3! \ RTC control 3
+RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
+RTCPS0=\$4AC! \ RTC prescaler 0
+RTCPS1=\$4AD! \ RTC prescaler 1
+RTCIV=\$4AE! \ RTC interrupt vector word
+RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCDAY=\$4B4! \ RTC days
+RTCMON=\$4B5! \ RTC month
+RTCYEAR=\$4B6!
+RTCYEARL=\$4B6! \ RTC year low
+RTCYEARH=\$4B7! \ RTC year high
+RTCAMIN=\$4B8! \ RTC alarm minutes
+RTCAHOUR=\$4B9! \ RTC alarm hours
+RTCADOW=\$4BA! \ RTC alarm day of week
+RTCADAY=\$4BB! \ RTC alarm days
+BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE! \ BCD-to-binary conversion register
+RTCHOLD=\$40!
+RTCRDY=\$10!
+
! ----------------------------------------------
! MSP430FR5969 MEMORY MAP
! ----------------------------------------------
@define{@read{/config/gema/MSP430FR5x6x.pat}}
+! \ RTC_C
+RTCCTL0_L=\$4A0! \ RTCCTL0_L
+RTCCTL0_H=\$4A1! \ RTCCTL0_H
+RTCCTL1=\$4A2! \ RTCCTL1
+RTCCTL3=\$4A3! \ RTCCTL3
+RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
+RTCPS0=\$4AC! \ RTC prescaler 0
+RTCPS1=\$4AD! \ RTC prescaler 1
+RTCIV=\$4AE! \ RTC interrupt vector word
+RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCDAY=\$4B4! \ RTC days
+RTCMON=\$4B5! \ RTC month
+RTCYEAR=\$4B6!
+RTCYEARL=\$4B6! \ RTC year low
+RTCYEARH=\$4B7! \ RTC year high
+RTCAMIN=\$4B8! \ RTC alarm minutes
+RTCAHOUR=\$4B9! \ RTC alarm hours
+RTCADOW=\$4BA! \ RTC alarm day of week
+RTCADAY=\$4BB! \ RTC alarm days
+BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE! \ BCD-to-binary conversion register
+RTCHOLD=\$40!
+RTCRDY=\$10!
+
! ----------------------------------------------
! MSP430FR5994 MEMORY MAP
! ----------------------------------------------
!MSP430fr5x6x.pat
-LPM4,=\$F8,! SR(LPM4+GIE)
-LPM3,=\$D8,! SR(LPM3+GIE)
-LPM2,=\$98,! SR(LPM2+GIE)
-LPM1,=\$58,! SR(LPM1+GIE)
-LPM0,=\$18,! SR(LPM0+GIE)
+LPM4=\$F8! SR(LPM4+GIE)
+LPM3=\$D8! SR(LPM3+GIE)
+LPM2=\$98! SR(LPM2+GIE)
+LPM1=\$58! SR(LPM1+GIE)
+LPM0=\$18! SR(LPM0+GIE)
CAPTIO1CTL=\$47E! \ Capacitive Touch IO 1 control
-! \ RTC_B / RTC_C
-RTCCTL0=\$4A0! \ RTC control 0 / RTCCTL0_L
-RTCCTL1=\$4A1! \ RTC control 1 / RTCCTL0_H
-RTCCTL2=\$4A2! \ RTC control 2 / RTCCTL1
-RTCCTL3=\$4A3! \ RTC control 3 / RTCCTL3
-RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
-RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
-RTCPS0=\$4AC! \ RTC prescaler 0
-RTCPS1=\$4AD! \ RTC prescaler 1
-RTCIV=\$4AE! \ RTC interrupt vector word
-RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
-RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
-RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
-RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
-RTCDAY=\$4B4! \ RTC days
-RTCMON=\$4B5! \ RTC month
-RTCYEAR=\$4B6!
-RTCYEARL=\$4B6! \ RTC year low
-RTCYEARH=\$4B7! \ RTC year high
-RTCAMIN=\$4B8! \ RTC alarm minutes
-RTCAHOUR=\$4B9! \ RTC alarm hours
-RTCADOW=\$4BA! \ RTC alarm day of week
-RTCADAY=\$4BB! \ RTC alarm days
-BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
-BCD2BIN=\$4BE! \ BCD-to-binary conversion register
-RTCHOLD=\$40!
-
MPY=\$4C0! \ 16-bit operand 1 \96 multiply
MPYS=\$4C2! \ 16-bit operand 1 \96 signed multiply
MAC=\$4C4! \ 16-bit operand 1 \96 multiply accumulate
ADC12MEM30=\$89C! \ ADC12_B Memory 30
ADC12MEM31=\$89E! \ ADC12_B Memory 31
+ADCON=\$10!
+ADCSTART=\$03!
CDIFG=1!
CDIIFG=2!
SCG0=\$40! = SR(6) SCG0
SCG1=\$80! = SR(7) SCG1
V=\$100! = SR(8) oVerflow flag
-UF1=\$200! = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
-UF2=\$400! = SR(10) User Flag 2
-UF3=\$800! = SR(11) User Flag 3
+UF9=\$200! = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
+UF10=\$400! = SR(10) User Flag 2
+UF11=\$800! = SR(11) User Flag 3
C\@=C\@
C\!=C\!
! ============================================
! symbolic codes :
! ============================================
+POP=MOV \@R1+,! \ MOV @RSP+,
+POP\.B=MOV\.B \@R1+,! \ MOV.B @RSP+,
RET=MOV \@R1+,R0! \ MOV @RSP+,PC
NOP=MOV 0,R3! \ one word one cycle
NOP2=\$3C00 ,! \ compile JMP 0 one word two cycles
NEXT=MOV \@R13+,R0! \ MOV @IP+,PC
+! ============================================
+! FORTH DOxxx registers :
+! ============================================
+rDOCOL=R7!
+rDOVAR=R6!
+rDOCON=R5!
+rDODOES=R4!
+
! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
! those addresses are usable with the symbolic assembler
INIDP=\$180C! define RST_STATE, init by wipe
INIVOC=\$180E! define RST_STATE, init by wipe
-XON=\$1810!
-XOFF=\$1812!
+RXON=\$1810!
+RXOFF=\$1812!
ReadSectorWX=\$1814! call with W = SectorLO X = SectorHI
WriteSectorWX=\$1816! call with W = SectorLO X = SectorHI
+GPFLAGS=\$1818!
+! ============================================
+! FORTH RAM areas :
+! ============================================
+LSTACK_SIZE=\#16! words
+PSTACK_SIZE=\#48! words
+RSTACK_SIZE=\#48! words
+PAD_LEN=\#84! bytes
+TIB_LEN=\#80! bytes
+HOLD_SIZE=\#34! bytes
! ============================================
! FastForth RAM memory map (>= 2k):
! ============================================
-LSATCK=\$1C00! \ leave stack, grow up
LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT
+LSATCK=\$1C00! \ leave stack, grow up
PSTACK=\$1C80! \ parameter stack, grow down
RSTACK=\$1CE0! \ Return stack, grow down
-PAD=\$1CE2! \ user scratch pad buffer, grow up
-TIB=\$1D38! \ Terminal input buffer, grow up
+PAD_ORG=\$1CE2! \ user scratch pad buffer, grow up
+TIB_ORG=\$1D38! \ Terminal input buffer, grow up
BASE_HOLD=\$1DAA! \ BASE HOLD area, grow down
! ----------------------
HandleOutOfBound=\$2100!
SDIB=\$2100!
-
+SDIB_LEN=\#84!
SD_END_DATA=\$2154!
\ No newline at end of file
@define{@read{/config/gema/MSP430FR5x6x.pat}}
+! \ RTC_C
+RTCCTL0_L=\$4A0! \ RTCCTL0_L
+RTCCTL0_H=\$4A1! \ RTCCTL0_H
+RTCCTL1=\$4A2! \ RTCCTL1
+RTCCTL3=\$4A3! \ RTCCTL3
+RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
+RTCPS0=\$4AC! \ RTC prescaler 0
+RTCPS1=\$4AD! \ RTC prescaler 1
+RTCIV=\$4AE! \ RTC interrupt vector word
+RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCDAY=\$4B4! \ RTC days
+RTCMON=\$4B5! \ RTC month
+RTCYEAR=\$4B6!
+RTCYEARL=\$4B6! \ RTC year low
+RTCYEARH=\$4B7! \ RTC year high
+RTCAMIN=\$4B8! \ RTC alarm minutes
+RTCAHOUR=\$4B9! \ RTC alarm hours
+RTCADOW=\$4BA! \ RTC alarm day of week
+RTCADAY=\$4BB! \ RTC alarm days
+BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE! \ BCD-to-binary conversion register
+RTCHOLD=\$40!
+RTCRDY=\$10!
+
! ----------------------------------------------
! MSP430FR6989 MEMORY MAP
! ----------------------------------------------
--- /dev/null
+@ECHO OFF
+
+:: ==============================================================================================
+:: your git copy of fast forth must be the root of a virtual drive
+:: ==============================================================================================
+
+IF "%1" == "" GOTO CopyError
+
+:: ==============================================================================================
+:: source file.f part
+:: %~dpn1.f is the symbolic source file.f described as drive\path\name.f
+:: %~dpn2.pat is the pattern file.pat for preprocessor gema.exe described as drive\path\name.pat
+:: %~dpn1.4th is the source file.4th to be sent to the target
+:: %~d1 is the drive of arg %1
+:: %~nx0 is name.ext of this bat file
+
+IF NOT EXIST %~dpn1.f GOTO 4th
+IF NOT EXIST %~dpn2.pat GOTO errorF
+
+IF /I "%3" == "" GOTO preprocessF
+
+:errorF
+@start %~d1\config\scite\AS_MSP430\Error.bat CopyErrorF %~nx0
+exit
+
+:preprocessF
+@%~d1\prog\gema\gema.exe -nobackup -line -t -f %~dpn2.pat %~dpn1.f %~dpn1.4th
+
+:DownloadF
+@taskkill /F /IM ttermpro.exe 1> NULL 2>&1
+
+:win32f
+@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendToSD.ttl %~dpn1.4th /C 1> NULL 2>&1
+@IF NOT ERRORLEVEL 1 GOTO EndF
+
+:win64f
+del null
+@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendToSD.ttl %~dpn1.4th /C
+
+:EndF
+@del %~dpn1.4th
+exit
+
+:: ==============================================================================================
+:: source file.4th part
+:: %~dpn1.4th is the file to be sent described as drive\path\name.4th
+:: %~d1 is the drive of param %1
+:: %~nx0 is name.ext of this bat file
+:: %2 must not exist
+
+:4th
+
+IF NOT EXIST %~dpn1.4th GOTO CopyError
+
+if /I "%2"=="" GOTO Download4th
+
+:Error4th
+@start %~d1\config\scite\AS_MSP430\Error.bat CopyError4th %~nx0
+exit
+
+:Download4th
+@taskkill /F /IM ttermpro.exe 1> NULL 2>&1
+
+:win324th
+@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d0\config\scite\AS_MSP430\SendtoSD.ttl %~dpn1.4th /C 1> NULL 2>&1
+@IF NOT ERRORLEVEL 1 GOTO End4th
+
+:win644th
+del null
+@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d0\config\scite\AS_MSP430\SendtoSD.ttl %~dpn1.4th /C
+
+:End4th
+exit
+
+
+:CopyError
+@start %~d1\config\scite\AS_MSP430\Error.bat CopyError %~nx0
+exit
--- /dev/null
+
+@GOTO %1
+
+:DownloadErrorF
+@call :before0
+@call :before
+@echo how to download a generic file.f to your target
+@echo -----------------------------------------------
+@echo 1- clic on your file.f,
+@echo 2- ctrl+clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- then drag and drop your file.f onto %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo which is itself downloaded onto target
+@echo.
+@pause
+exit
+
+:DownloadError4th
+@call :before0
+@call :before
+@echo how to download a file.4th to your target
+@echo -----------------------------------------
+@echo drag and drop your file.4th onto %2
+@echo.
+@pause
+exit
+
+:CopyErrorF
+@call :before0
+@call :before
+@echo how to copy a generic file.f to your SD_CARD target
+@echo ---------------------------------------------------
+@echo and a formatted FAT16/32 SD_CARD is in it's slot...
+@echo 1- clic on your file.f,
+@echo 2- ctrl+clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- release ctrl+clic
+@echo 4- then drag and drop your file.f onto %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo which is itself copied onto SD_CARD target
+@echo.
+@pause
+exit
+
+:CopyError4th
+@call :before0
+@call :before
+@echo how to copy a file.4th to the SD_CARD target
+@echo --------------------------------------------
+@echo and a formatted FAT16/32 SD_CARD is in it's slot...
+@echo drag and drop your file.4th onto %2
+@echo.
+@pause
+exit
+
+:ConvertError
+@call :before0
+@echo how to convert a generic file.f to a target specific file.4th
+@echo -------------------------------------------------------------
+@echo 1- clic on a file.f,
+@echo 2- ctrl+clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- release ctrl+clic
+@echo 4- then drag and drop your file.f onto %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo.
+@pause
+exit
+
+:DownloadError
+@call :before0
+@call :before
+@echo how to download a generic file.f to your target
+@echo -----------------------------------------------
+@echo 1- clic on your file.f,
+@echo 2- ctrl+clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- release ctrl+clic
+@echo 4- then drag and drop your file.f onto %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo which is itself downloaded onto target
+@echo.
+@echo how to download a file.4th to your target
+@echo -----------------------------------------
+@echo drag and drop your file.4th onto %2
+@echo.
+@pause
+exit
+
+
+:COPYError
+@call :before0
+@call :before
+@echo how to copy a generic file.f to your SD_CARD target
+@echo ---------------------------------------------------
+@echo and a formatted FAT16/32 SD_CARD is in it's slot...
+@echo 1- clic on your file.f,
+@echo 2- ctrl+clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- release ctrl+clic
+@echo 4- then drag and drop your file.f onto %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo which is itself copied onto SD_CARD target
+@echo.
+@echo how to download a file.4th to your target
+@echo -----------------------------------------
+@echo drag and drop your file.4th onto %2
+@echo.
+@pause
+exit
+
+
+:before0
+@echo you have downloaded your copy of gitlab fast forth onto a folder shared and connected as virtual drive (A: or B: ...)
+@echo so config files.pat for the preprocessor gema.exe are in the folder \config\gema\
+@echo and batch file are in the folder \config\scite\msp430_as\
+@echo you have installed the last version of teraterm,
+@echo you have installed the last version of gema.exe in the folder \prog\gema\.
+@echo.
+@echo edit properties of these three links SendSourceFileToTarget.bat, CopySourceFileToTarget_SD_Card.bat and
+@echo PreprocessSourceFile.f.bat to change the drive letter B: as yours.
+@echo.
+@exit /B
+
+:before
+@echo before sending a file
+@echo ---------------------
+@echo teraterm must be well configured, and its config must be saved,
+@echo so you must see the FAST FORTH prompt "ok" when you type "return" on the teraterm terminal.
+@echo.
+@exit /B
\ No newline at end of file
@ECHO OFF
-if not exist %~dpn1.hex goto eof
-if exist %2 goto eof
+if not exist %~dpn1.hex exit
+if exist %2 exit
a:\prog\srecord\srec_cat %~dpn1.hex -intel -output %~dpn1.txt -ti-txt
-:eof
exit
rem %1 is the target device, example: MSP430FR5969
\ No newline at end of file
--- /dev/null
+@ECHO OFF
+IF NOT EXIST %~dpn1.f GOTO error
+IF NOT EXIST %~dpn2.pat GOTO error
+
+IF "%3" == "" GOTO preprocess
+
+:error
+@start %~d1\config\scite\AS_MSP430\Error.bat ConvertError %~nx0
+exit
+
+:preprocess
+@%~d1\prog\gema\gema.exe -nobackup -line -t -f %~dpn2.pat %~dpn1.f %~dpn1.4th
+exit
+
+:: %~dpn1.f is the symbolic source file described as drive\path\name.f of first arg (%1)
+:: %~dpn2.pat is the pattern file for preprocessor gema.exe described as drive\path\name.pat of 2th arg (%2)
+:: %~dpn1.4th is the source file ready to send to the target
+:: %~d1 is the drive of arg %1
+:: %~nx0 is name.ext of this bat file
+
+rem your git copy must be the root of a virtual drive
+
statusbar.text.1=\
li=$(LineNumber) co=$(ColumnNumber) $(OverType) ($(EOLMode)) $(FileAttr)
statusbar.text.2=\
-$(BufferLength) chars in $(NbOfLines) lines. Sel: $(SelLength) chars.
+$(BufferLength) chars in $(NbOfLines) lines. Sel: $(SelHeight) lines, $(SelLength) chars.
statusbar.text.3=\
Now is: Date=$(CurrentDate) Time=$(CurrentTime)
statusbar.text.4=\
# to the types of files seen when opening.
# There is a limit (possibly 256 characters) to the length of a filter,
# so not all source extensions can be in this setting.
-#*.idl;*.odl;*.rc;*.rc2;*.dlg;*.def;make*;*.mak;\
-#*.frm;*.cls;*.ctl;;*.pl;;*.iface;*.e;#*.rb;*.cgi;*.lua;\
-#source.files=*.asm;*.c;*.cc;*.f;*.ff;*.far;*.cpp;*.cxx;*.cs;*.h;*.hh;*.hxx;*.hpp;\
-source.files=*.asm;*.avr;*.tiny;*.mega;*.vb;*.vbs;*.bas;*.bat;*.ini;*.py;*.js;*.properties;*.vhd;*.vhdl
+source.files=*.asm;*.inc;*.pat;*.f;*.4th;*.bat
# Each platform has a different idea of the most important filters
if PLAT_WIN
all.files=All Files (*.*)|*.*|
- top.filters=All Source|$(source.files)|$(all.files)
+ top.filters=$(all.files)All Source|$(source.files)|
if PLAT_GTK
all.files=All Files (*)|*|Hidden Files (.*)|.*|
top.filters=All Source|$(source.files)|$(all.files)
--- /dev/null
+
+@GOTO %1
+
+:DownloadErrorF
+@call :before
+@echo how to download a generic file.f to your target
+@echo -----------------------------------------------
+@echo 1- clic on your file.f,
+@echo 2- ctrl clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- then drag and drop your file.f onto %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo which is itself downloaded onto target
+@echo.
+@pause
+exit
+
+:DownloadError4th
+@call :before
+@echo how to download a file.4th to your target
+@echo -----------------------------------------
+@echo drag and drop your file.4th onto %2
+@echo.
+@pause
+exit
+
+:CopyErrorF
+@call :before
+@echo how to copy a generic file.f to your SD_CARD target
+@echo ---------------------------------------------------
+@echo and a formatted FAT16/32 SD_CARD is in it's slot...
+@echo 1- clic on your file.f,
+@echo 2- ctrl clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- then drag and drop your file.f onto %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo which is itself copied onto SD_CARD target
+@echo.
+@pause
+exit
+
+:CopyError4th
+@call :before
+@echo how to copy a file.4th to the SD_CARD target
+@echo --------------------------------------------
+@echo and a formatted FAT16/32 SD_CARD is in it's slot...
+@echo drag and drop your file.4th onto %2
+@echo.
+@pause
+exit
+
+:ConvertError
+@echo you have downloaded your copy of gitlab fast forth onto a folder shared and connected as virtual drive (A: or B: ...)
+@echo so config files.pat for the preprocessor gema.exe are in the folder \config\gema\
+@echo and batch file are in the folder \config\scite\msp430_as\
+@echo you have installed the last version of gema.exe in the folder \prog\gema\.
+@echo.
+@echo how to convert a generic file.f to a file.4th specific to a target
+@echo ------------------------------------------------------------------
+@echo 1- clic on a file.f,
+@echo 2- ctrl clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- clic selected file.f then drag and drop it on to %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo.
+@pause
+exit
+
+:DownloadError
+@echo you have downloaded your copy of gitlab fast forth onto a folder shared and connected as virtual drive (A: or B: ...)
+@echo so config files.pat for the preprocessor gema.exe are in the folder \config\gema\
+@echo and batch file are in the folder \config\scite\msp430_as\
+@echo you have installed the last version of teraterm,
+@echo you have installed the last version of gema.exe in the folder \prog\gema\.
+@echo.
+@echo edit properties of these three links SendSourceFileToTarget.bat, CopySourceFileToTarget_SD_Card.bat and
+@echo PreprocessSourceFile.f.bat to change the drive letter B: as yours.
+@echo.
+@call :before
+@echo how to download a generic file.f to your target
+@echo -----------------------------------------------
+@echo 1- clic on your file.f,
+@echo 2- ctrl clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
+@echo 3- then drag and drop your file.f onto %2
+@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
+@echo which is itself downloaded onto target
+@echo.
+@echo how to download a file.4th to your target
+@echo -----------------------------------------
+@echo drag and drop your file.4th onto %2
+@echo.
+@pause
+exit
+
+
+:before
+@echo before sending a file
+@echo ---------------------
+@echo teraterm must be well configured, and its config must be saved,
+@echo so you must see the FAST FORTH prompt "ok" when you type "return" on the teraterm terminal.
+@echo.
connect param3
-sendln ' $0A BASE ! STOP' ; blanks are to pass LPMx wake up time...
+sendln ' $0A BASE ! ECHO STOP' ; blanks are to pass LPMx wake up time...
inputbox 'Send a File' 'Select File : ' param2
sendfile inputstr 0
showtt 1
+
end
; param1 = this macro
; param2 = file to send
; param3 = "/C"
+; param4 = ECHO or NOECHO
\ No newline at end of file
--- /dev/null
+@ECHO OFF
+
+:: ==============================================================================================
+:: your git copy of fast forth must be the root of a virtual drive
+:: ==============================================================================================
+
+IF "%1" == "" GOTO DownloadError
+
+:: ==============================================================================================
+:: source file.f part
+:: %~dpn1.f is the symbolic source file.f described as drive\path\name.f
+:: %~dpn2.pat is the pattern file.pat for preprocessor gema.exe described as drive\path\name.pat
+:: %~dpn1.4th is the source file.4th to be sent to the target
+:: %~d1 is the drive of arg %1
+:: %~nx0 is name.ext of this bat file
+
+IF NOT EXIST %~dpn1.f GOTO 4th
+IF NOT EXIST %~dpn2.pat GOTO errorF
+
+IF /I "%3" == "" GOTO preprocessF
+IF /I "%3" == "ECHO" GOTO preprocessF
+IF /I "%3" == "NOECHO" GOTO preprocessF
+
+:errorF
+@start %~d1\config\scite\AS_MSP430\Error.bat DownloadErrorF %~nx0
+exit
+
+:preprocessF
+@%~d1\prog\gema\gema.exe -nobackup -line -t -f %~dpn2.pat %~dpn1.f %~dpn1.4th
+
+:DownloadF
+@taskkill /F /IM ttermpro.exe 1> NULL 2>&1
+
+:Win32F
+@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendFile.ttl %~dpn1.4th /C %3 1> NULL 2>&1
+@IF NOT ERRORLEVEL 1 GOTO EndF
+
+:Win64F
+del null
+@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendFile.ttl %~dpn1.4th /C %3
+
+:EndF
+@del %~dpn1.4th
+exit
+
+
+:: ==============================================================================================
+:: source file.4th part
+:: %~dpn1.4th is the file to be sent described as drive\path\name.4th
+:: %~d1 is the drive of param %1
+:: %~nx0 is name.ext of this bat file
+
+:4th
+
+IF NOT EXIST %~dpn1.4th GOTO DownloadError
+
+if /I "%2"=="" GOTO Download4th
+if /I "%2"=="ECHO" GOTO Download4th
+if /I "%2"=="NOECHO" GOTO Download4th
+
+:Error4th
+@start %~d1\config\scite\AS_MSP430\Error.bat DownloadError4th %~nx0
+exit
+
+:Download4th
+@taskkill /F /IM ttermpro.exe 1> NULL 2>&1
+
+:Win324th
+@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendFile.ttl %~dpn1.4th /C %2 1> NULL 2>&1
+@IF NOT ERRORLEVEL 1 GOTO End4th
+
+:Win644th
+del null
+@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendFile.ttl %~dpn1.4th /C %2
+
+:End4th
+exit
+
+
+:DownloadError
+@start %~d1\config\scite\AS_MSP430\Error.bat DownloadError %~nx0
+exit
sendln ' $0A BASE ! ECHO STOP' ; blanks are added to pass LPMx wake up time...
-inputbox 'here you can add a path to the file: ' 'Send a File to SD_CARD target' fname
+inputbox 'here you can modify destination: ' 'Send a File to SD_CARD target' fname
sendln 'TERM2SD" ' inputstr '"' ; send to FastForth the command TERM2SD" \file.ext" ...with optionnal path added in inputbox
+++ /dev/null
-
-; param1 = this macro filename
-; param2 = pathname of the bat file
-; param3 = /C = default COM saved in TERATERM.INI with all its parameters.
-
-timeout=0 ; 0 s
-mtimeout=100 ; + 100 ms = 100 ms
-noname = '\'
-connect param3
-
-; blanks are added to pass LPMx wake up time...
-sendln ' $0A BASE ! ECHO STOP'
-
-
-; first input box to define file to be read
-inputbox 'select SD_CARD file to be read:' 'SD_CARD file' '\'
-
-strcompare inputstr noname
-if result=0 then
-goto end
-endif
-
-fileorg = inputstr
-namedst = inputstr
-
-strremove namedst 1 1
-dirdst = param2 ; disdst = path of bat file
-makepath filedst dirdst namedst ; filedst = pathname of file selected in windows 2
-
-
-; 2th input box to define destination file with param1 path
-inputbox 'select destination file:' 'destination file' filedst
-
-filecreate filehandle inputstr
-
-;setsync 1 ; enter synchronous mode
-
-; send to FastForth the command TERM2SD" \file.ext"...
-; ...with optionnal path added in first inputbox
-sendln 'SD2TERM" ' fileorg '"'
-
-recvln ; keep sendln 'SD2TERM" ' fileorg '"'
-recvln ; keep FastForth response
-
-:start
-
-recvln ; receive one line
-
-if result=0 then ; case of timeout
- fileclose filehandle
- goto end
-endif
-
-filewriteln filehandle inputstr ; write it to output file
-
-send #17 ; send XON
-
-goto start
-
-:end
-
-;setsync 0 ; enter asynchronous mode
-
-showtt 1
-
-closett
-end
\ No newline at end of file
+++ /dev/null
-@ECHO OFF
-if not exist %~dpn1%.4th goto error
-if exist %2 goto error
-taskkill /F /IM ttermpro.exe 1> NULL 2>&1
-@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d0\config\scite\AS_MSP430\SendtoSD.ttl %~dpn1%.4th /C 1> NULL 2>&1
-if ERRORLEVEL 1 goto nextcmd
-exit
-
-:nextcmd
-del null
-@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d0\config\scite\AS_MSP430\SendtoSD.ttl %~dpn1%.4th /C
-exit
-
-:error
-
-@start %~d0\config\scite\AS_MSP430\error4thtoSDCARD.bat
-exit
-
-rem %~d0% is the drive of bat file
-rem %~dpn1%.4th is the file to send described as drive\path\name.4th of param %1
-rem %~d1 is the drive of param %1
+++ /dev/null
-@ECHO OFF
-if not exist %~dpn1.4th goto error
-
-if "%2"=="" GOTO testend
-if /I "%2"=="ECHO" GOTO testend
-if /I "%2"=="NOECHO" GOTO testend
-
-:error
-start %~d1\config\scite\AS_MSP430\error4th.bat
-exit
-
-
-
-
-
-:testend
-taskkill /F /IM ttermpro.exe 1> NULL 2>&1
-@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendFile.ttl %~dpn1.4th /C %2 1> NULL 2>&1
-if ERRORLEVEL 1 goto nextcmd
-exit
-
-:nextcmd
-del null
-@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendFile.ttl %~dpn1.4th /C %2
-:eof
-exit
-
-
-
-rem %~dpn1.4th is the file to send described as drive\path\name.4th of param %1
-rem %~d1 is the drive of param %1
-
-
-
-
# asm styles
#MSP430_instructions
-keywords.$(file.patterns.asm)=adc adc.b adc.w add add.b add.w addc addc.b addc.w and and.b and.w \
- bic bic.b bic.w bis bis.b bis.w bit bit.b bit.w br branch call clrc clrn clrz dint eint \
- clr clr.b clr.w cmp cmp.b cmp.w dadc dadc.b dadc.w dadd dadd.b dadd.w dec dec.b dec.w decd decd.b decd.w \
- inc inc.b inc.w incd incd.b incd.w inv inv.b inv.w mov mov.b mov.w pop pop.b pop.w push push.b push.w \
- jc jhs je jeq jz jge jl jmp jn jnc jlo jne jnz nop nop2 nop3 nop4 nop5 nop6 nop7 ret reti setc setn setz swpb sxt \
- rla rla.b rla.w rlc rlc.b rlc.w rra rra.b rra.w rrc rrc.b rrc.w sbc sbc.b sbc.w sub sub.b sub.w \
- subc subc.b subc.w sbb sbb.b sbb.w tst tst.b tst.w xor xor.b xor.w \
+keywords.$(file.patterns.asm)=add add.b add.w addc addc.b addc.w and and.b and.w \
+ bic bic.b bic.w bis bis.b bis.w bit bit.b bit.w br branch call \
+ cmp cmp.b cmp.w dadd dadd.b dadd.w \
+ mov mov.b mov.w push push.b push.w \
+ jc jhs je jeq jz jge jl jmp jn jnc jlo jne jnz \
+ nop nop2 nop3 ret reti swpb sxt \
+ rra rra.b rra.w rrc rrc.b rrc.w sub sub.b sub.w \
+ subc subc.b subc.w xor xor.b xor.w \
pushm popm rlam rram rrcm rrum
##preprocessor
# the star at the start of this command line is to display the parameters box
-# write the name of the device in the first parameter; example : MSP430fr5969
-# write the name of the target in the 2th parameter; example : MSP_EXP430fr5969
+# copy the name of the target in the first parameter; example : MSP_EXP430FR5969
-command.name.0.*.asm=Assembler 1:[device] 2:[target]
-command.0.*.asm=*\config\scite\AS_MSP430\build.bat $(FileNameExt) $(2)$(3)
+command.name.0.*.asm=Assemble for 1:[target]
+command.0.*.asm=*\config\scite\AS_MSP430\build.bat $(FileNameExt) $(1)$(2)
-command.name.1.*.asm=FET Prog 1:[device] 2:[target]
-command.1.*.asm=*\config\scite\AS_MSP430\prog.bat $(1) $(2)$(3).txt
+command.name.1.*.asm=FET Prog 1:[target]
+command.1.*.asm=*\config\scite\AS_MSP430\prog.bat $(1)$(2)
+
+
+command.name.2.*.asm=Assemble for target CurrentSelection
+command.2.*.asm=\config\scite\AS_MSP430\build.bat $(FileNameExt) $(CurrentSelection)
+
+command.name.3.*.asm=FET Prog target CurrentSelection
+command.3.*.asm=\config\scite\AS_MSP430\prog.bat $(CurrentSelection)
@ECHO OFF
-\prog\MacroAssemblerAS\bin\asw -L -i \projets\msp430 %1 -o %2.p
-\prog\MacroAssemblerAS\bin\p2hex %2.p -r 0x0000-0xffff
-\prog\srecord\srec_cat %2.hex -intel -output %2.txt -ti-txt
+%~d1\prog\MacroAssemblerAS\bin\asw -L -i \projets\msp430 %1 -o %2.p
+%~d1\prog\MacroAssemblerAS\bin\p2hex %2.p -r 0x0000-0xffff
+%~d1\prog\srecord\srec_cat %2.hex -intel -output %2.txt -ti-txt
del %2.p
del %2.hex
exit
-rem %1 is the target device, example: MSP430FR5969
-rem %2 is the target, example: MSP_EXP430FR5969
\ No newline at end of file
+rem your git copy must be the root of a virtual drive
+
+rem %1 is the input file.asm
+rem %2 is the target name, plus optional infos
+++ /dev/null
-@ECHO OFF
-if not exist %~dpn1.f goto error
-if not exist %~dpn2.pat goto error
-if exist %3 goto error
-@%~d1\prog\gema\gema.exe -nobackup -line -t -f %~dpn2.pat %~dpn1.f %~dpn1.4th
-exit
-
-:error
-
-@start %~d1\config\scite\AS_MSP430\errorfto4th.bat
-exit
-
-
-
-exit
-%~dpn1.f is the symbolic source file described as drive\path\name.f of first arg (%1)
-%~dpn2.pat is the pattern file for preprocessor gema.exe described as drive\path\name.pat of 2th arg (%2)
-%~dpn1.4th is the source file ready to send to the target
-%~d1 is the drive of arg %1
+++ /dev/null
-
-@echo how to download a file.4th to your target
-@echo -----------------------------------------
-@echo I presume you are connected to your fastforth target via input terminal TERATERM.EXE
-@echo drag and drop your file.4th onto Send_file.4th_to_target.bat
-
-@pause
-exit
-
+++ /dev/null
-
-@echo how to copy a file.4th to the SD_CARD target
-@echo --------------------------------------------
-@echo I presume you are connected via TERATERM.EXE to your fastforth target with its SD_CARD extensions,
-@echo and a formatted FAT 16 SD_CARD is in it's slot...
-@echo drag and drop your file.4th onto Send_File.4th_to_SD_CARD_target.bat
-
-@pause
-exit
-
+++ /dev/null
-
-@echo how to download a generic file.f to your target
-@echo -----------------------------------------------
-@echo I presume you are connected to your fastforth target via input terminal TERATERM.EXE
-@echo 1- clic on your file.f,
-@echo 2- ctrl clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
-@echo 3- then drag and drop your file.f onto Send_File.f_to_SD_CARD_target.bat
-@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
-@echo which is itself loaded by FastForth onto target
-
-@pause
-exit
+++ /dev/null
-
-@echo how to convert a generic file.f to a file.4th specific to a target
-@echo ------------------------------------------------------------------
-@echo I presume you are connected to your fastforth target via input terminal TERATERM.EXE
-@echo 1- clic on a file.f,
-@echo 2- ctrl clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
-@echo 3- clic selected file.f then drag and drop it on to Convert_file.f_to_file.4th.bat
-@echo the generic file.f is sent so to the preprocessor gema.exe which products specific the file.4th
-@pause
-exit
+++ /dev/null
-
-
-@echo how to copy a generic file.f to your SD_CARD target
-@echo ---------------------------------------------------
-@echo I presume you are connected via TERATERM.EXE to your fastforth target with its SD_CARD extensions,
-@echo and a formatted FAT 16 SD_CARD is in it's slot...
-@echo 1- clic on your file.f,
-@echo 2- ctrl clic on your selected target.pat file, for example MSP_EXP430FR5994.pat
-@echo 3- then drag and drop your file.f onto Send_File.f_to_SD_CARD_target.bat
-@echo the generic file.f is sent so to the preprocessor gema.exe which products a specific file.4th
-@echo which is itself copied onto SD_CARD target
-
-@pause
-exit
-
+++ /dev/null
-
-
-@echo how to receive a file from target SD_CARD
-@echo -----------------------------------------
-@echo I presume you are connected via TERATERM.EXE to your fastforth target with its SD_CARD extensions,
-@echo and a formatted FAT 16 SD_CARD is in it's slot...
-@echo 1- drag and drop any file.f/.4th of your destination folder onto Receive_file_from_SD_CARD_target.bat
-@echo this defines path for 2th window below
-@echo 2- in the first window opened by TERATERM select the SD_CARD file you want upload
-@echo 3- in the 2th window, change if necessary filename to be written on your PC.
-@echo 4- wait for TERATERM window blinking (at 15kb/s, this may do a long time): it's done.
-
-@pause
-exit
-
# control keywords Forth
keywords.$(file.patterns.forth)=\
again begin case do else endcase endof if loop +loop leave unloop of repeat then until while ?do \
-< > >= = <> 0<> 0= 0< <0 0>= u< u>= S< S>= jmp goto bw1 bw2 bw3 fw1 fw2 fw3
+< > >= = <> 0<> 0= 0< <0 0>= u< u>= s< s>= jmp goto ?goto bw1 bw2 bw3 fw1 fw2 fw3
# Keywords
keywords2.$(file.patterns.forth)=\
keywords3.$(file.patterns.forth)=\
code endcode : ; \
lo2hi hi2lo colon asm endasm \
+\[if] \[else] \[then] \[undefined] \[defined]
# MSP430 assembly words & MSP430_instructions
keywords4.$(file.patterns.forth)=\
style.forth.3=fore:#FFFFFF
# control (keyword_FORTH_CONTROL)
-style.forth.4=fore:#007f7F
+style.forth.4=fore:#00bfbF
# Keywords (keyword2_SCE_FORTH_KEYWORD)
style.forth.5=fore:#FF0FF,$(font.base)
style.forth.8=fore:#FFFF00,$(font.base)
# number (SCE_FORTH_NUMBER)
-style.forth.9=fore:#007F7F,$(font.base)
+style.forth.9=fore:#00BFBF,$(font.base)
# Double quoted string (SCE_FORTH_STRING)
style.forth.10=fore:#00FFFF,$(font.base)
# locale
-style.forth.11=fore:#0000CC,$(font.base)
+style.forth.11=fore:#0077FF,$(font.base)
#command.compile.*.f=spf.cmd $(FileNameExt)
-command.name.0.*.f=preprocess file.f with 2:[target].pat then send file.4th to [target] with ECHO
-command.0.*.f=*\config\scite\AS_MSP430\send_file.f_to_target.bat $(FileDir)\$(FileName).f $(2) ECHO
+command.name.0.*.f=preprocess file.f with 1:[target].pat then send file.4th to [target] with ECHO
+command.0.*.f=*\config\scite\AS_MSP430\SendSourceFileToTarget.bat $(FileDir)\$(FileName).f $(1) ECHO
-command.name.1.*.f=preprocess file.f with 2:[target].pat then send file.4th to [target] without ECHO
-command.1.*.f=*\config\scite\AS_MSP430\send_file.f_to_target.bat $(FileDir)\$(FileName).f $(2) NOECHO
+command.name.1.*.f=preprocess file.f with 1:[target].pat then send file.4th to [target] without ECHO
+command.1.*.f=*\config\scite\AS_MSP430\SendSourceFileToTarget.bat $(FileDir)\$(FileName).f $(1) NOECHO
-command.name.2.*.f=preprocess file.f with 2:[target].pat then send file.4th to [target] SD_CARD
-command.2.*.f=*\config\scite\AS_MSP430\send_file.f_to_SD_CARD_target.bat $(FileDir)\$(FileName).f $(2)
+command.name.2.*.f=preprocess file.f with 1:[target].pat then send file.4th to [target] SD_CARD
+command.2.*.f=*\config\scite\AS_MSP430\CopySourceFileToTarget_SD_Card.bat $(FileDir)\$(FileName).f $(1)
-command.name.3.*.f=preprocess file.f with 2:[target].pat to file.4th (for debug)
-command.3.*.f=*\config\scite\AS_MSP430\convert_file.f_to_file.4th.bat $(FileDir)\$(FileName).f $(2)
+command.name.3.*.f=preprocess file.f with 1:[target].pat to file.4th (for debug)
+command.3.*.f=*\config\scite\AS_MSP430\PreprocessSourceFile.f.bat $(FileDir)\$(FileName).f $(1)
command.name.4.*.f=convert FORTH registers to TI's ones
command.4.*.f=\prog\gema\gema -line -t -f \config\gema\FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt)
command.name.0.*.4th=send file.4th to [target] with ECHO
-command.0.*.4th=*\config\scite\AS_MSP430\send_file.4th_to_target.bat $(FileDir)\$(FileName).4th ECHO
+command.0.*.4th=*\config\scite\AS_MSP430\SendSourceFileToTarget.bat $(FileDir)\$(FileName).4th ECHO
command.name.1.*.4th=send file.4th to [target] without ECHO
-command.1.*.4th=*\config\scite\AS_MSP430\send_file.4th_to_target.bat $(FileDir)\$(FileName).4th NOECHO
+command.1.*.4th=*\config\scite\AS_MSP430\SendSourceFileToTarget.bat $(FileDir)\$(FileName).4th NOECHO
command.name.2.*.4th=send file.4th to [target] SD_CARD
-command.2.*.4th=*\config\scite\AS_MSP430\send_file.4th_to_SD_CARD_target.bat $(FileDir)\$(FileName).4th
+command.2.*.4th=*\config\scite\AS_MSP430\CopySourceFileToTarget_SD_Card.bat $(FileDir)\$(FileName).4th
command.name.3.*.4th=convert TI registers to FORTH's ones
-command.3.*.4th=*\prog\gema\gema -line -t -f \config\gema\TiREGtoFastForth.pat $(FileNameExt) $(FileNameExt)
+command.3.*.4th=\prog\gema\gema -line -t -f \config\gema\TiREGtoFastForth.pat $(FileNameExt) $(FileNameExt)
command.name.4.*.4th=convert FORTH registers to TI's ones
-command.4.*.4th=*\prog\gema\gema -line -t -f \config\gema\FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt)
+command.4.*.4th=\prog\gema\gema -line -t -f \config\gema\FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt)
-\prog\MSP430Flasher\msp430flasher -s -m SBW2 -n %1 -v -w %2 -z [RESET,VCC]
-exit
-
-rem -s : force update
-rem -m : select SBW2 mode
-rem -n %1 : device
-rem -v : verify device
-rem -w %2 : file to be flashed
-rem -z [] : end of flasher behaviour
\ No newline at end of file
+::@echo off
+
+@set device=%~n1
+@if %device:~0,16% == MSP_EXP430FR5739 set device=MSP430FR5739
+@if %device:~0,16% == MSP_EXP430FR5969 set device=MSP430FR5969
+@if %device:~0,16% == MSP_EXP430FR5994 set device=MSP430FR5994
+@if %device:~0,16% == MSP_EXP430FR6989 set device=MSP430FR6989
+@if %device:~0,16% == MSP_EXP430FR4133 set device=MSP430FR4133
+@if %device:~0,16% == CHIPSTICK_FR2433 set device=MSP430FR2433
+
+@if %device:~0,15% == MY_MSP430FR5738 set device=MSP430FR5738
+@if %device:~0,15% == MY_MSP430FR5948 set device=MSP430FR5948
+@if %device:~0,17% == MY_MSP430FR5738_1 set device=MSP430FR5738
+@if %device:~0,17% == MY_MSP430FR5738_2 set device=MSP430FR5738
+@if %device:~0,17% == MY_MSP430FR5948_1 set device=MSP430FR5948
+@if %device:~0,7% == JMJ_BOX set device=MSP430FR5738
+@if %device:~0,13% == PA8_PA_MSP430 set device=MSP430FR5738
+@if %device:~0,12% == PA_PA_MSP430 set device=MSP430FR5738
+@if %device:~0,14% == PA_Core_MSP430 set device=MSP430FR5948
+
+ %~d1\prog\MSP430Flasher\msp430flasher -s -m SBW2 -n %device% -v -w %~n1.txt -z [RESET,VCC]
+
+@exit
+
+:: your git copy must be the root of a virtual drive
+
+:: %n1 = file filename (= target) to flash
+:: -s : force update
+:: -m : select SBW2 mode
+:: -n %device% : device set from %n1
+:: -v : verify device
+:: -w %~dpn1.txt : file to be flashed
+:: -z [] : end of flasher behaviour
+++ /dev/null
-@ECHO OFF
-if not exist %~dpn1.f goto error
-if not exist %~dpn2.pat goto error
-if exist %3 goto error
-@%~d1\prog\gema\gema.exe -nobackup -line -t -f %~dpn2.pat %~dpn1.f %~dpn1.4th
-@taskkill /F /IM ttermpro.exe 1> NULL 2>&1
-@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendToSD.ttl %~dpn1.4th /C 1> NULL 2>&1
-if ERRORLEVEL 1 goto nextcmd
-exit
-
-:nextcmd
-del null
-@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendToSD.ttl %~dpn1.4th /C
-@del %~dpn1.4th
-:eof
-exit
-
-:error
-
-@start %~d1\config\scite\AS_MSP430\errorftoSDCARD.bat
-exit
-
-rem %~dpn1.f is the symbolic source file described as drive\path\name.f of first arg (%1)
-rem %~dpn2.pat is the pattern file for preprocessor gema.exe described as drive\path\name.pat of 2th arg (%2)
-rem %~dpn1.4th is the source file send to the target
-rem %~d1 is the drive of arg %1
-
+++ /dev/null
-@ECHO OFF
-IF NOT EXIST %~dpn1.f GOTO error
-IF NOT EXIST %~dpn2.pat GOTO error
-
-if "%3"=="" goto testend
-if /I "%3"=="ECHO" GOTO testend
-if /I "%3"=="NOECHO" GOTO testend
-
-:error
-@start %~d1\config\scite\AS_MSP430\errorf.bat
-exit
-
-
-:testend
-@%~d1\prog\gema\gema.exe -nobackup -line -t -f %~dpn2.pat %~dpn1.f %~dpn1.4th
-
-@taskkill /F /IM ttermpro.exe 1> NULL 2>&1
-@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendFile.ttl %~dpn1.4th /C %3 1> NULL 2>&1
-if ERRORLEVEL 1 goto nextcmd
-exit
-
-:nextcmd
-del null
-@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\scite\AS_MSP430\SendFile.ttl %~dpn1.4th /C %3
-@del %~dpn1.4th
-:eof
-exit
-
-
-rem %~dpn1.f is the symbolic source file described as drive\path\name.f of first arg (%1)
-rem %~dpn2.pat is the pattern file for preprocessor gema.exe described as drive\path\name.pat of 2th arg (%2)
-rem %~dpn1.4th is the source file send to the target
-rem %~d1 is the drive of arg %1
-
--- /dev/null
+;
+; tera term mecrisp-stellaris forth upload helper
+; Copyright (C) 2015 Jean Jonethal
+;
+; This program is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+; small upload macro for uploading forth source via tera term tested with version 4.88
+; Tera Term website http://ttssh2.osdn.jp/index.html.en
+; tera term supports call stack up to 10 levels on my laptop so using iterative approach here
+
+; upload source file to target line by line and waits for "ok." after transmission of line.
+; supports nesting include with pathname
+; line containing include directive is not sent to target
+; max source line length is 511
+; include path\filename.ext
+
+; example project.txt :
+; include dump.txt
+; include ..\common\disassembler-m3.txt
+; include demo2.fth
+
+; TODO:
+; "require" - support for single inclusion
+; error handling for MAXLEVEL
+; path handling relative to root file
+; test path handling
+
+; global definitions
+MAXLEVEL = 20 ; max nesting level up to 65536 levels might be supported by tera term
+MAX_LINE_LENGTH = 511 ; max string/line length supported by tera term
+INCLUDE_PATTERN = "include\s+([\.\w/:\\-]+)" ; this pattern marks our include file
+SOURCE_PATTERN = "^([^\\]+)" ; skip line comments
+timeout = 5 ; you might tune this for longer response times
+mtimeout = 500 ; wait 500 ms for "ok." response
+infilehandle = -1 ; current file handle
+fname = "" ; current filename
+newfileHandle = -1 ; store the new file handle
+; parameter stack ; stack rised upwards
+level = 1 ; current include level
+intdim FileHandleStack MAXLEVEL ; file handle stack
+intdim clp MAXLEVEL ; line position stack - unused at the moment
+strdim LineStack MAXLEVEL ; line stack - unused at the moment
+strdim FileNameStack MAXLEVEL ; filename stack
+
+
+; check for macro parameter
+if paramcnt = 2 then ; if there is a macro parameter use it as input file name
+ fname = param2
+endif
+strlen fname
+if result = 0 then ; if there is no valid parameter open file dialog for selection
+ filenamebox "select file" 0
+ fname = inputstr
+ messagebox fname "opened"
+endif
+
+dirname prjdir fname ; dirname <strvar> <path> setup current directory to fname
+setdir prjdir ; setdir <dir> set macrodir to directory containing file fname
+
+call uploading
+goto ende
+
+:uploading
+ fileopen infilehandle fname 0 1 ; fileopen <file handle> <filename> <append flag> [<readonly flag>]
+ if infilehandle <> -1 then ; if file open successful
+ level = 1 ; we start at level 1
+ FileNameStack[level] = fname ;
+ FileHandleStack[level] = infilehandle
+ while 1 ; infinite loop !
+ infilehandle = FileHandleStack[level] ; update current file handle
+ filereadln infilehandle line ; filereadln <file handle> <strvar> get next line from this file
+ if result = 0 then
+ call processLine
+ else ; end of file (it is the last line of file)
+ call levelback ; close file , back one nesting level
+ if level < 1 then ; upper most file ended
+ messagebox fname "Finished" ; notify user
+ break
+ endif
+ endif
+ endwhile
+ endif
+return
+
+:levelback
+; close file and switch to previous level
+
+ fileclose infilehandle
+ level = level - 1
+ if level > 0 then ; back to previous level
+ infilehandle = FileHandleStack[level]
+ fname = FileNameStack[level]
+ else
+ infilehandle = -1
+ FileHandleStack[level] = -1
+ endif
+return
+
+:processLine
+; scan every line for include filename or send to target and wait for "ok."
+; line contains current line to be scanned
+
+ strmatch line INCLUDE_PATTERN ; scan the line for include pattern
+ if result > 0 then
+ fname = groupmatchstr1 ; found new include line
+ call openNewFile
+ else
+ call skipComment
+ send line #10 ; send line + LF
+ wait "ok."
+ endif
+return
+
+:openNewFile
+; start a new include level when open successfull
+; fname contains new include filename
+; notify user if failed to open included file
+
+ fileopen newfileHandle fname 0 1
+ if newfileHandle <> -1 then ; new include file opened
+ level = level + 1
+ infilehandle = newfileHandle
+ FileNameStack[level] = fname
+ FileHandleStack[level] = infilehandle
+ else
+ messagebox fname "open failed" ; notify user about failed file
+ endif
+return
+
+:skipComment
+; dont transfer comments
+ strmatch line SOURCE_PATTERN ; skip comments
+ if result > 0 then
+ line = groupmatchstr1
+ else
+ line = ""
+ endif
+return
+
+
+:ende
\ No newline at end of file
+++ /dev/null
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-S&QL|sql||\
-#Specman|e||\
-&TCL|tcl||\
-TeX|tex||\
-#&txt2tags|t2t||\
-&VB|vb||\
-VBScr&ipt|vbs||\
-#Verilog|v||\
-#VHDL|vhd||\
-&XML|xml|$(keyXML)|\
-YAML|yaml||
-
-# User defined key commands
-user.shortcuts=\
-Ctrl+Shift+V|IDM_PASTEANDDOWN|\
-Ctrl+PageUp|IDM_PREVFILE|\
-Ctrl+PageDown|IDM_NEXTFILE|
-
-#KeypadPlus|IDM_EXPAND|\
-#KeypadMinus|IDM_BLOCK_COMMENT|
-
-#user.context.menu=\
-#||\
-#Next File|IDM_NEXTFILE|\
-#Prev File|IDM_PREVFILE|
-
-# Import all the language specific properties files
-#import abaqus
-#import ada
-#import asn1
-#import au3
-#import ave
-#import baan
-#import freebasic
-#import blitzbasic
-#import bullant
-#import caml
-import conf
-#import cobol
-import cpp
-#import cmake
-#import csound
-import css
-#import d
-#import eiffel
-#import erlang
-#import escript
-#import flagship
-import \config\scite\fortran
-#import gap
-#import haskell
-import html
-#import inno
-#import kix
-import lisp
-#import lot
-#import lout
-import lua
-#import matlab
-#import metapost
-#import mmixal
-#import modula3
-#import nimrod
-#import nncrontab
-#import nsis
-#import opal
-import \config\scite\others
-#import pascal
-#import perl
-#import pov
-#import powerpro
-#import powershell
-import ps
-#import purebasic
-import python
-#import r
-#import rebol
-import ruby
-#import scriptol
-#import smalltalk
-#import spice
-#import sql
-#import specman
-#import tacl
-#import tal
-import tcl
-#import txt2tags
-import tex
-#import vb
-#import yaml
-#import verilog
-#import vhdl
-import \config\scite\AS_MSP430\asm
-import \config\scite\AS_MSP430\gema
-import \config\scite\AS_MSP430\forth
-import \config\scite\hex
-
-
-# Error list styles
-
-style.errorlist.32=fore:#B0B000,$(font.small)
-# Default
-style.errorlist.0=fore:#FFFFFF
-# Microsoft Error
-style.errorlist.3=fore:#0080FF
-# command or return status
-style.errorlist.4=fore:#FF00FF
-
-# Text matched with find in files and message part of GCC errors
-style.errorlist.21=fore:#FF0000
-
-
-
-
word.characters.$(file.patterns.text)=$(chars.alpha)$(chars.numeric)$(chars.accented)-'
-colour.other.operator=fore:#B06000
+colour.other.operator=fore:#FFFF00
# Properties styles
del dir do dpath echo else endlocal erase errorlevel exist \
exit for ftype goto if in lpt1 lpt2 lpt3 lpt4 md mkdir move \
not nul path pause popd prompt prn pushd rd rem ren \
-rename rmdir set setlocal shift start time title type ver \
+rename rmdir set setlocal shift start taskkill time title type ver \
verify vol
keywords.$(file.patterns.batch)=$(keywordclass.batch)
#keywords2.$(file.patterns.batch)=append attrib chkdsk comp diskcomp
# Default
-style.batch.0=fore:#000000
+style.batch.0=fore:#FFFFFF
# Comment (rem or ::)
-style.batch.1=fore:#007F00,$(font.comment)
+style.batch.1=fore:#00FF00,$(font.comment)
# Keywords
-style.batch.2=$(colour.keyword),bold
+style.batch.2=$(colour.keyword)
# Label (line beginning with ':')
-style.batch.3=$(colour.string),back:#606060,fore:#FFFF00,eolfilled
+style.batch.3=$(colour.string),fore:#FFFF00,eolfilled
# Hide command character ('@')
style.batch.4=$(colour.preproc)
# External commands
-style.batch.5=fore:#007090,$(font.monospace),bold
+style.batch.5=fore:#00FFFF,$(font.monospace)
# Variable: %%x (x is almost whatever, except space and %), %n (n in [0-9]), %EnvironmentVar%
-style.batch.6=fore:#800080
+style.batch.6=fore:#FF00FF
# Operator: * ? < > |
-style.batch.7=fore:#000000
+style.batch.7=fore:#FFFFFF
comment.block.batch=REM ~
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; assembled with MACROASSEMBLER AS (http://john.ccac.rwth-aachen.de:8000/as/)
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
.cpu MSP430
.include "mspregister.mac" ;
; macexp off ; unrem to hide macro results
-;----------------------------------------------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; Vingt fois sur le métier remettez votre ouvrage,
; Polissez-le sans cesse, et le repolissez,
; Ajoutez quelquefois, et souvent effacez.
-; Boileau, L'Art poétique
-;----------------------------------------------------------------------------------------------------------
-
-;===============================================================================================
-;===============================================================================================
-; before assembling or programming you must set DEVICE in param1 and TARGET in param2 (SHIFT+F8)
-; according to the TARGET "switched" below
-; example : your TARGET = MSP_EXP430FR5969 (notice the underscore) ==> DEVICE = MSP430FR5969
-;===============================================================================================
-;===============================================================================================
-
-;-----------------------------------------------------------------------------------------------
-; TARGET configuration SWITCHES ; bytes values are for DTC=1, 8MHz 2457600bds XON/XOFF + RTS
-;-----------------------------------------------------------------------------------------------
-; TOTAL - SUM of (INFO+RAM +VECTORS) = MAIN PROG
-;MSP_EXP430FR5739 ; compile for MSP-EXP430FR5739 launchpad ; 4136 - 160 ( 24 + 86 + 50 ) = 3976 bytes
-;MSP_EXP430FR5969 ; compile for MSP-EXP430FR5969 launchpad ; 4102 - 162 ( 24 + 86 + 52 ) = 3940 bytes
-;MSP_EXP430FR5994 ; compile for MSP-EXP430FR5994 launchpad ; 4144 - 186 ( 24 + 86 + 76 ) = 3956 bytes
-;MSP_EXP430FR6989 ; compile for MSP-EXP430FR6989 launchpad ; 4140 - 168 ( 24 + 86 + 58 ) = 3972 bytes
-;MSP_EXP430FR4133 ; compile for MSP-EXP430FR4133 launchpad ; 4174 - 140 ( 24 + 86 + 30 ) = 4034 bytes
-CHIPSTICK_FR2433 ; compile for the "CHIPSTICK" of M. Ken BOAK ; 4070 - 148 ( 24 + 86 + 38 ) = 3928 bytes
+; Boileau, L'Art poétique
+;-------------------------------------------------------------------------------
+
+;===============================================================================
+;===============================================================================
+;before assembling or programming you must copy your TARGET in param1 (SHIFT+F8)
+;===============================================================================
+;===============================================================================
+
+;-------------------------------------------------------------------------------
+; TARGET configuration SWITCHES ; bytes values are for DTC=1, 8MHz 2457600 bds XON/XOFF
+;-------------------------------------------------------------------------------
+; TOTAL - SUM of (INFO+RAM +VECTORS) = MAIN PROG
+;MSP_EXP430FR5739 ;; MSP-EXP430FR5739 launchpad ; 4154 - 160 ( 24 + 86 + 50 ) = 3994 bytes
+;MSP_EXP430FR5969 ; MSP-EXP430FR5969 launchpad ; 4136 - 162 ( 24 + 86 + 52 ) = 3974 bytes
+MSP_EXP430FR5994 ; MSP-EXP430FR5994 launchpad ; 4172 - 186 ( 24 + 86 + 76 ) = 3986 bytes
+;MSP_EXP430FR6989 ; MSP-EXP430FR6989 launchpad ; 4170 - 168 ( 24 + 86 + 58 ) = 4002 bytes
+;MSP_EXP430FR4133 ; MSP-EXP430FR4133 launchpad ; 4180 - 140 ( 24 + 86 + 30 ) = 4040 bytes
+;CHIPSTICK_FR2433 ; "CHIPSTICK" of M. Ken BOAK ; 4096 - 148 ( 24 + 86 + 38 ) = 3948 bytes
+;MY_MSP430FR5738 ; my MSP430FR5738 miniboards ; 4100 - 160 ( 24 + 86 + 50 ) = 3940 bytes
+;MY_MSP430FR5738_1 ; MYMSP430FR5738_1 miniboard ; 4100 - 160 ( 24 + 86 + 50 ) = 3940 bytes
+;MY_MSP430FR5948 ; my MSP430FR5948 miniboard ; 4110 - 162 ( 24 + 86 + 52 ) = 3948 bytes
+;MY_MSP430FR5948_1 ; my MSP430FR5948_1 miniboard ; 4122 - 162 ( 24 + 86 + 52 ) = 3960 bytes
+;JMJ_BOX ; JMJ_BOX MSP430FR5738 ; 4088 - 160 ( 24 + 86 + 50 ) = 3928 bytes
+;PA8_PA_MSP430 ; PA8_PA_MSP430 MSP430FR5738 ; 4088 - 160 ( 24 + 86 + 50 ) = 3928 bytes
; choose DTC (Direct Threaded Code) model, if you don't know, choose 1
-DTC .equ 1 ; DTC model 1 : DOCOL = CALL rDOCOL 14 cycles 1 word shortest DTC model
- ; DTC model 2 : DOCOL = PUSH IP, CALL rEXIT 13 cycles 2 words good compromize for mix FORTH/ASM code
- ; DTC model 3 : inlined DOCOL 9 cycles 4 words fastest
+DTC .equ 2 ; DTC model 1 : DOCOL = CALL rDOCOL 14 cycles 1 word shortest DTC model
+ ; DTC model 2 : DOCOL = PUSH IP, CALL rEXIT 13 cycles 2 words good compromize for mix FORTH/ASM code
+ ; DTC model 3 : inlined DOCOL 9 cycles 4 words fastest
FREQUENCY .equ 16 ; fully tested at 0.25,0.5,1,2,4,8,16 (and 24 for MSP430FR57xx) MHz
THREADS .equ 16 ; 1, 4, 8, 16, 32 search entries in dictionnary. 16 is the good compromise between speed and size.
; +40, +66, +90, +154 bytes
-TERMINALBAUDRATE .equ 3000000 ; choose value considering the frequency and the UART2USB bridge, see explanations below.
-TERMINALXONXOFF ; to enable XON/XOFF flow control (PL2303TA/HXD, CP2102)
-TERMINALCTSRTS ; to enable hardware flow control with RTS (PL2303TA/HXD, FT232RL)
+TERMINALBAUDRATE .equ 921600 ; choose value considering the frequency and the UART2USB bridge, see choices below.
- .include "Target.inc" ; to define target config: I/O, memory, SFR, vectors, TERMINAL eUSCI, SD_Card eUSCI, LF_XTAL,
+ ; select a minima one item below, input terminal don't work if no flow control.
+TERMINALXONXOFF ; set 3 wires (GND,RX,TX) XON/XOFF software flow control; unselect if you plan to use binary flows
+TERMINALCTSRTS ; +12 bytes to set 4 wires (GND,RX,TX,RTS) hardware input flow control
-;-----------------------------------------------------------------------
-; KERNEL ADD-ON SWITCHES ;
-;-----------------------------------------------------------------------
-MSP430ASSEMBLER ;; + 1896 bytes : add embedded assembler with TI syntax; without, you can do all but all much more slowly...
-;SD_CARD_LOADER ; + 1754 bytes : to LOAD source files from SD_card
-;SD_CARD_READ_WRITE ; + 1162 bytes : to read, create, write and del files + source files direct copy from PC to SD_Card
+ .include "Target.inc" ; to define target config: I/O, memory, SFR, vectors, TERMINAL eUSCI, SD_Card eUSCI, LF_XTAL,
+ ; but only for FAST FORTH core use, not for your FAST FORTH application.
+
+;-------------------------------------------------------------------------------
+; KERNEL ADD-ON SWITCHES
+;-------------------------------------------------------------------------------
+CONDCOMP ;; + 354 bytes : add conditionnal compilation : [UNDEFINED] [DEFINED] [IF] [ELSE] [THEN], strongly recommended.
+MSP430ASSEMBLER ;; + 1894 bytes : add embedded assembler with TI syntax; without, you can do all but all much more slowly...
+SD_CARD_LOADER ;; + 1834 bytes : to LOAD source files from SD_card
+SD_CARD_READ_WRITE ;; + 1176 bytes : to read, create, write and del files + source files direct copy from PC to SD_Card
+BOOTLOADER ; + 50 bytes : add a bootstrap to SD_CARD\BOOT.4TH.
;VOCABULARY_SET ; + 108 bytes : add VOCABULARY FORTH ASSEMBLER ALSO PREVIOUS ONLY DEFINITIONS (FORTH83, not ANSI)
-;LOWERCASE ; + 30 bytes : enable to EMIT strings in lowercase.
+;LOWERCASE ; + 30 bytes : enable to write strings in lowercase.
;BACKSPACE_ERASE ; + 24 bytes : replace BS by ERASE, for visual comfort
-;-------------------------------------------------------------------------------------------------
-; OPTIONAL KERNELL ADD-ON SWITCHES, because their source file can be downloaded later >----------------+
-;------------------------------------------------------------------------------------------------- |
-; v
-;UTILITY ; + 404 bytes : add .S WORDS U.R DUMP ? UTILITY.f
-;SD_TOOLS ; + 126 bytes for trivial DIR, FAT, CLUSTER and SECTOR view, adds UTILITY SD_TOOLS.f
-;ANS_CORE_COMPLIANT ; + 876 bytes : required to pass coretest.4th ; (includes items below) COMPxMPY.f (x = H or S)
+;-------------------------------------------------------------------------------
+; OPTIONAL KERNELL ADD-ON SWITCHES (can be downloaded later) >------------------+
+; Tip: when switched ON below, ADD-ONs become protected against WIPE and Deep Reset... |
+;------------------------------------------------------------------------------- v
+;UTILITY ; + 412/494 bytes : add .S .RS WORDS U.R DUMP ? UTILITY.f
+;SD_TOOLS ; + 126 bytes for trivial DIR, FAT, CLUSTER and SECTOR view, adds UTILITY SD_TOOLS.f
+;ANS_CORE_COMPLIANT ; + 876 bytes : required to pass coretest.4th ; (includes items below) COMPxMPY.f (x = H or S)
;ARITHMETIC ; + 358 bytes : add S>D M* SM/REM FM/MOD * /MOD / MOD */MOD /MOD */
;DOUBLE ; + 130 bytes : add 2@ 2! 2DUP 2SWAP 2OVER
;ALIGNMENT ; + 24 bytes : add ALIGN ALIGNED
;PORTABILITY ; + 46 bytes : add CHARS CHAR+ CELLS CELL+
-
-;=================================================================
+;===============================================================================
; XON/XOFF control flow configuration ; up to 322kBd/MHz with ECHO
-;=================================================================
+;===============================================================================
-; Only two usb2uart bridges correctly handle XON / XOFF: cp2102 and pl2303.
+; Only two usb2uart bridges correctly handle XON/XOFF: cp2102 and pl2303.
; the best and cheapest: UARTtoUSB cable with Prolific PL2303TA (supply current = 8 mA) or PL2303HXD
; ...but pl2303HXD cable have not the 3.3V pin...
; don't forget : save new TERATERM configuration !
-;======================================================================
+;===============================================================================
; Hardware control flow configuration: RTS is wired on UART2USB CTS pin
-;======================================================================
+;===============================================================================
; Launchpad <-> UARTtoUSB
; RX <-- TX
; UARTtoUSB module with FTDI FT232RL (FT230X don't work correctly)
-; --------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; WARNING ! buy a FT232RL module with a switch 5V/3V3 and select 3V3 !
-; --------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; 9600,19200,38400,57600,115200 (500kHz)
; + 230400 (1MHz)
; + 460800 (2MHz)
; don't forget : save new TERATERM configuration !
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; DTCforthMSP430FR5xxx Init vocabulary pointers:
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
.IF THREADS = 1
.include "ForthThreads.mac"
.ENDIF
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; DTCforthMSP430FR5xxx RAM memory map:
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; name words ; comment
;PAD ; ----- RAMSTART + $E2
; |
-PAD_SIZE .equ 84 ; | grows up (ans spec. : PAD >= 84 chars)
+PAD_LEN .equ 84 ; | grows up (ans spec. : PAD >= 84 chars)
; |
; v
; ----- RAMSTART + $136
;TIB ; ----- RAMSTART + $138
; |
-TIB_SIZE .equ 80 ; | grows up (ans spec. : TIB >= 80 chars)
+TIB_LEN .equ 80 ; | grows up (ans spec. : TIB >= 80 chars)
; |
; v
; ^
LEAVEPTR .equ LSTACK ; Leave-stack pointer
PSTACK .equ LSTACK+(LSTACK_SIZE*2)+(PSTACK_SIZE*2)
RSTACK .equ PSTACK+(RSTACK_SIZE*2)
-PAD .equ RSTACK+2
-TIB .equ PAD+PAD_SIZE+2
-BASE_HOLD .equ TIB+TIB_SIZE+HOLD_SIZE
+PAD_ORG .equ RSTACK+2
+TIB_ORG .equ PAD_ORG+PAD_LEN+2
+BASE_HOLD .equ TIB_ORG+TIB_LEN+HOLD_SIZE
; ----------------------------------
HP .word 0 ; HOLD ptr
CAPS .word 0
-LAST_NFA .word 0 ; NFA, VOC_PFA, LFA, CFA, CSP of last created word
-LAST_THREAD .word 0
+LAST_NFA .word 0 ; NFA, VOC_PFA, LFA, CFA, PSP of last created word
+LAST_THREAD .word 0 ; used by QREVEAL
LAST_CFA .word 0
-LAST_CSP .word 0
+LAST_PSP .word 0
STATE .word 0 ; Interpreter state
ASM_CURRENT .word 0 ; preserve CURRENT during create assembler words
OPCODE .word 0 ; OPCODE adr
BUFEND .equ BUFFER + 200h ; 512bytes
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; INFO(DCBA) >= 256 bytes memory map:
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
.org INFOSTART
.ENDIF
HECTOBAUDS .word TERMINALBAUDRATE/100 ; user use
-SAVE_SYSRSTIV .word -3 ; to perform DEEP_RST after FastForth compiling
+SAVE_SYSRSTIV .word 05 ; value to identify FAST FORTH first start after core recompiling
LPM_MODE .word CPUOFF+GIE ; LPM0 is the default mode
INIDP .word ROMDICT ; define RST_STATE
INIVOC .word lastvoclink ; define RST_STATE
; ------------------------------
; VARIABLES that could be in RAM
; ------------------------------
- .IFNDEF RAM_1K ; if RAM = 1K the variables below stay in FRAM
+ .IFNDEF RAM_1K ; if RAM = 1K (FR57xx) the variables below stay in FRAM
.org BUFEND ; else in RAM beyond BUFFER
.ENDIF
; ---------------------------------------
SAVEtsLEN .word 0 ; of previous ACCEPT
SAVEtsPTR .word 0 ; of previous ACCEPT
-MemSectorL .word 0 ;
-MemSectorH .word 0 ;
+ .word 0 ;
+ .word 0 ;
.word 0
; ---------------------------------------
HDLW_BUFofst .equ 22 ; BUFFER offset ; used by LOAD"
- .IFDEF RAM_1K ; RAM_Size = 1k
+ .IFDEF RAM_1K ; RAM_Size = 1k, no SDIB due to the lack of RAM
FirstHandle
HandleMax .equ 7
HandleLenght .equ 24
.org HandleEnd
SDIB
-SDIB_SIZE .equ 84
+SDIB_LEN .equ 84
- .org SDIB+SDIB_SIZE
+ .org SDIB+SDIB_LEN
.ENDIF ; RAM_Size
.ENDIF ; SD_CARD_LOADER
-SD_END_DATA ; used to init SD_ram area
-; ----------------------------------------------------------------------
-; DTCforthMSP430FR5xxx REGISTER USAGE
-; ----------------------------------------------------------------------
-
- .SWITCH DTC
- .CASE 1 ; DOCOL = CALL rDOCOL
-
-RSP .reg SP ; RSP = Return Stack Pointer (return stack)
-
-; DOxxx registers ; must be saved before use and restored after use
-rDODOES .reg r4
-rDOCON .reg r5
-rDOVAR .reg r6
-rDOCOL .reg R7
-
-; Scratch registers
-Y .reg R8
-X .reg R9
-W .reg R10
-T .reg R11
-S .reg R12
-
-; Forth virtual machine
-IP .reg R13 ; interpretative pointer
-TOS .reg R14 ; first PSP cell
-PSP .reg R15 ; PSP = Parameters Stack Pointer (stack data)
-
- .CASE 2 ; DOCOL = PUSH IP + CALL rEXIT
-
-RSP .reg SP ; RSP = Return Stack Pointer (return stack)
+SD_END_DATA ; used by SD_INIT to init SD_ram area
-; DOxxx registers ; must be saved before use and restored after use
-rDODOES .reg r4
-rDOCON .reg r5
-rDOVAR .reg r6
-rEXIT .reg R7
+;-------------------------------------------------------------------------------
+; DTCforthMSP430FR5xxx program (FRAM) memory
+;-------------------------------------------------------------------------------
-; Scratch registers
-Y .reg R8
-X .reg R9
-W .reg R10
-T .reg R11
-S .reg R12
+ .org PROGRAMSTART
-; Forth virtual machine
-IP .reg R13 ; interpretative pointer
-TOS .reg R14 ; first PSP cell
-PSP .reg R15 ; PSP = Parameters Stack Pointer (stack data)
+;-------------------------------------------------------------------------------
+; DEFINING EXECUTIVE WORDS - DTC model
+;-------------------------------------------------------------------------------
- .CASE 3 ; INLINED DOCOL
+;-------------------------------------------------------------------------------
+; very nice FAST FORTH added feature:
+;-------------------------------------------------------------------------------
+; as IP is computed from the PC value, we can place low level to high level
+; switches "COLON" or "LO2HI" anywhere in a word, i.e. not only at its beginning.
+;-------------------------------------------------------------------------------
-RSP .reg SP ; RSP = Return Stack Pointer (return stack)
+RSP .reg R1 ; RSP = Return Stack Pointer (return stack)
; DOxxx registers ; must be saved before use and restored after use
rDODOES .reg r4
rDOVAR .reg r6
; Scratch registers
-R .reg R7
Y .reg R8
X .reg R9
W .reg R10
TOS .reg R14 ; first PSP cell
PSP .reg R15 ; PSP = Parameters Stack Pointer (stack data)
- .ENDCASE ; DTC
-
-; ----------------------------------------------------------------------
-; DTCforthMSP430FR5xxx program (FRAM) memory
-; ----------------------------------------------------------------------
-
- .org PROGRAMSTART
-
-; ----------------------------------------------------------------------
-; DEFINING EXECUTIVE WORDS - DTC model
-; ----------------------------------------------------------------------
-
-; ----------------------------------------------------------------------
-; very nice FAST FORTH added feature:
-; ----------------------------------------------------------------------
-; as IP is calculated from the PC value we can place the low to high level
-; switches "COLON" or "LO2HI" anywhere in a word, i.e. not only at its beginning.
-; ----------------------------------------------------------------------
-
-
- .SWITCH DTC
- .CASE 1 ; DOCOL = CALL rDOCOL
-
mNEXT .MACRO ; return for low level words (written in assembler)
MOV @IP+,PC ; 4 fetch code address into PC, IP=PFA
.ENDM ; 4 cycles,1word = ITC -2cycles -1 word
.word $+2 ; 0 cycle
.ENDM ; 0 cycle, 1 word
-ASMtoFORTH .MACRO ; compiled by LO2HI
- CALL #EXIT ;
- .ENDM ; 2 words, 10~
-DOCOL1 .equ 1287h ; 4 CALL R7 ; [R7] is set as xdocol by COLD
-mDOCOL .MACRO ; compiled by : and by colon
- CALL R7 ;
- .ENDM ; 14~ 1 word
+ .SWITCH DTC
+;-------------------------------------------------------------------------------
+ .CASE 1 ; DOCOL = CALL rDOCOL
+;-------------------------------------------------------------------------------
+
+rDOCOL .reg R7 ; COLD defines xdocol as R7 content
-xdocol ; 4 for CALL rDOCOL
- MOV @RSP+,W ; 2
+xdocol MOV @RSP+,W ; 2
PUSH IP ; 3 save old IP on return stack
MOV W,IP ; 1 set new IP to PFA
MOV @IP+,PC ; 4 = NEXT
- ; 14 = ITC +4
+ ; 10 cycles
- .CASE 2 ; DOCOL = PUSH IP + CALL rEXIT
+ASMtoFORTH .MACRO ; compiled by LO2HI
+ CALL #EXIT ; 2 words, 10 cycles
+ .ENDM ;
-mNEXT .MACRO
- MOV @IP+,PC ; 4 fetch code address into PC, IP=PFA
- .ENDM ; 4cycles,1word = ITC -2cycles -1 word
+mDOCOL .MACRO ; compiled by : and by colon
+ CALL R7 ; 1 word, 14 cycles (CALL included) = ITC+4
+ .ENDM ;
-NEXT .equ 4D30h ; 4 MOV @IP+,PC
+DOCOL1 .equ 1287h ; 4 CALL R7
-FORTHtoASM .MACRO ; compiled by HI2LO
- .word $+2 ; 0 cycle
- .ENDM ; 0 cycle, 1 word
+;-------------------------------------------------------------------------------
+ .CASE 2 ; DOCOL = PUSH IP + CALL rEXIT
+;-------------------------------------------------------------------------------
+
+rEXIT .reg R7 ; COLD defines EXIT as R7 content
ASMtoFORTH .MACRO ; compiled by LO2HI
- CALL rEXIT ; CALL EXIT
- .ENDM ; 10 cycles, 1 word
+ CALL rEXIT ; 1 word, 10 cycles
+ .ENDM ;
mDOCOL .MACRO ; compiled by : and by COLON
PUSH IP ; 3
- CALL rEXIT ; 10 CALL EXIT
- .ENDM ; 13 cycles (ITC+3), two words
+ CALL rEXIT ; 10
+ .ENDM ; 2 words, 13 cycles = ITC+3
DOCOL1 .equ 120Dh ; 3 PUSH IP
-DOCOL2 .equ 1287h ; 4 CALL rEXIT ; [rEXIT] is set as EXIT by COLD
+DOCOL2 .equ 1287h ; 4 CALL rEXIT
+;-------------------------------------------------------------------------------
.CASE 3 ; inlined DOCOL
+;-------------------------------------------------------------------------------
-mNEXT .MACRO ; return for low level words (written in assembler)
- MOV @IP+,PC ; 4 fetch code address into PC, IP=PFA
- .ENDM ; 4 cycles,1word = ITC -2cycles -1 word
-
-NEXT .equ 4D30h ; 4 MOV @IP+,PC
-
-FORTHtoASM .MACRO ; compiled by HI2LO
- .word $+2 ; 0 cycle
- .ENDM ; 0 cycle, 1 word
+R .reg R7 ; Scratch register
ASMtoFORTH .MACRO ; compiled by LO2HI
MOV PC,IP ; 1
MOV PC,IP ; 1
ADD #4,IP ; 1
MOV @IP+,PC ; 4 NEXT
- .ENDM ; 9 cycles (ITC -1), 4 words
+ .ENDM ; 4 words, 9 cycles (ITC-1)
DOCOL1 .equ 120Dh ; 3 PUSH IP
DOCOL2 .equ 400Dh ; 1 MOV PC,IP
.ENDCASE ; DTC
+;-------------------------------------------------------------------------------
; mDOVAR leave on parameter stack the PFA of a VARIABLE definition
+;-------------------------------------------------------------------------------
mDOVAR .MACRO ; compiled by VARIABLE
- CALL rDOVAR ; CALL RFROM
- .ENDM ; 14 cycles (ITC+4), 1 word
+ CALL rDOVAR ; 1 word, 14 cycles (ITC+4)
+ .ENDM ;
-DOVAR .equ 1286h ; 4 CALL rDOVAR ; [rDOVAR] is set as RFROM by COLD
+DOVAR .equ 1286h ; CALL rDOVAR ; [rDOVAR] is defined as RFROM by COLD
+;-------------------------------------------------------------------------------
; mDOCON leave on parameter stack the [PFA] of a CONSTANT definition
+;-------------------------------------------------------------------------------
mDOCON .MACRO ; compiled by CONSTANT
- CALL rDOCON ; CALL xdocon
- .ENDM ; 16 cycles (ITC+4), 1 word
+ CALL rDOCON ; 1 word, 16 cycles (ITC+4)
+ .ENDM ;
-DOCON .equ 1285h ; 4 CALL rDOCON ; [rDOCON] is set as xdocon by COLD
+DOCON .equ 1285h ; 4 CALL rDOCON ; [rDOCON] is defined as xdocon by COLD
xdocon ; -- constant ; 4 for CALL rDOCON
- SUB #2,PSP ; 1 make room on stack
- MOV TOS,0(PSP) ; 3 push first PSP cell
- MOV @RSP+,TOS ; 2 TOS=CONSTANT address
- MOV @TOS,TOS ; 2 TOS=CONSTANT
+ SUB #2,PSP ; 1
+ MOV TOS,0(PSP) ; 3 save TOS on parameters stack
+ MOV @RSP+,TOS ; 2 TOS = CFA address of master word CONSTANT
+ MOV @TOS,TOS ; 2 TOS = CONSTANT value
MOV @IP+,PC ; 4 execute next word
; 16 = ITC (+4)
-; mDODOES leave on parameter stack the PFA of a CREATE definition
+;-------------------------------------------------------------------------------
+; mDODOES leave on parameter stack the PFA of a CREATE definition and execute Master word
+;-------------------------------------------------------------------------------
mDODOES .MACRO ; compiled by DOES>
CALL rDODOES ; CALL xdodoes
- .ENDM ; 19 cycles (ITC-2), 1 word
+ .ENDM ; 1 word, 19 cycles (ITC-2)
-DODOES .equ 1284h ; 4 CALL rDODOES ; [rDODOES] is set as xdodoes by COLD
+DODOES .equ 1284h ; 4 CALL rDODOES ; [rDODOES] is defind as xdodoes by COLD
xdodoes ; -- a-addr ; 4 for CALL rDODOES
SUB #2,PSP ; 1
MOV TOS,0(PSP) ; 3 save TOS on parameters stack
MOV @RSP+,TOS ; 2 TOS = CFA address of master word, i.e. address of its first cell after DOES>
PUSH IP ; 3 save IP on return stack
- MOV @TOS+,IP ; 2 IP = CFA of Master word, TOS = BODY of created word
+ MOV @TOS+,IP ; 2 IP = CFA of Master word, TOS = BODY address of created word
MOV @IP+,PC ; 4 Execute Master word
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; INTERPRETER LOGIC
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
;https://forth-standard.org/standard/core/EXIT
-;C EXIT -- exit a colon definition; CALL #EXIT performs ASMtoFORTH
+;C EXIT -- exit a colon definition; CALL #EXIT performs ASMtoFORTH (10 cycles)
FORTHWORD "EXIT"
EXIT: MOV @RSP+,IP ; 2 pop previous IP (or next PC) from return stack
MOV @IP+,PC ; 4 = NEXT
MOV @IP+,PC ; 4 NEXT
; 11 = ITC - 2
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; STACK OPERATIONS
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
;https://forth-standard.org/standard/core/DUP
;C DUP x -- x x duplicate top of stack
DROP: MOV @PSP+,TOS ; 2
mNEXT ; 4
+;https://forth-standard.org/standard/core/NIP
+;C NIP x1 x2 -- x2 Drop the first item below the top of stack
+ FORTHWORD "NIP"
+NIP: ADD #2,PSP ; 1
+ mNEXT ; 4
+
;https://forth-standard.org/standard/core/SWAP
;C SWAP x1 x2 -- x2 x1 swap top two items
FORTHWORD "SWAP"
;https://forth-standard.org/standard/core/OVER
;C OVER x1 x2 -- x1 x2 x1
FORTHWORD "OVER"
-OVER: SUB #2,PSP ; 2 -- x1 x x2
- MOV TOS,0(PSP) ; 3 -- x1 x2 x2
- MOV 2(PSP),TOS ; 2 -- x1 x2 x1
+OVER: MOV TOS,-2(PSP) ; 3 -- x1 (x2) x2
+ MOV @PSP,TOS ; 2 -- x1 (x2) x1
+ SUB #2,PSP ; 2 -- x1 x2 x1
mNEXT ; 4
;https://forth-standard.org/standard/core/ROT
MOV @RSP,TOS
mNEXT
-;;Z SP@ -- a-addr get data stack pointer, must leave PSTACK value if stack empty
-; FORTHWORD "SP@"
-SPFETCH: MOV TOS,-2(PSP) ;3
- MOV PSP,TOS ;1
- SUB #2,PSP ;1 post decrement stack...
- mNEXT
-
;https://forth-standard.org/standard/core/DEPTH
;C DEPTH -- +n number of items on stack, must leave 0 if stack empty
FORTHWORD "DEPTH"
RRA TOS ; TOS/2 --> TOS
mNEXT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; MEMORY OPERATIONS
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
;https://forth-standard.org/standard/core/Fetch
;C @ a-addr -- x fetch cell from memory
FETCH: MOV @TOS,TOS
mNEXT
-
;https://forth-standard.org/standard/core/Store
;C ! x a-addr -- store cell in memory
FORTHWORD "!"
;https://forth-standard.org/standard/core/CFetch
;C C@ c-addr -- char fetch char from memory
FORTHWORD "C@"
-CFETCH: MOV.B @TOS,TOS
- mNEXT
-
+CFETCH: MOV.B @TOS,TOS ;2
+ mNEXT ;4
;https://forth-standard.org/standard/core/CStore
;C C! char c-addr -- store char in memory
FORTHWORD "C!"
-CSTORE: MOV @PSP+,W ;2
- MOV.B W,0(TOS) ;3
+CSTORE: MOV.B @PSP+,0(TOS);4
+ ADD #1,PSP ;1
MOV @PSP+,TOS ;2
mNEXT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; ARITHMETIC OPERATIONS
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
;https://forth-standard.org/standard/core/Plus
;C + n1/u1 n2/u2 -- n3/u3 add n1+n2
mNEXT
;https://forth-standard.org/standard/core/Minus
-;C - n1/u1 n2/u2 -- n3/u3 subtract n1-n2
+;C - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
FORTHWORD "-"
-MINUS: MOV @PSP+,W ; 2
- SUB TOS,W ; 1
- MOV W,TOS ; 1
+MINUS: SUB @PSP+,TOS ;2 -- n2-n1
+NEGATE: XOR #-1,TOS ;1
+ONEPLUS: ADD #1,TOS ;1 -- n3 = -(n2-n1)
mNEXT
;https://forth-standard.org/standard/core/AND
;https://forth-standard.org/standard/core/NEGATE
;C NEGATE x1 -- x2 two's complement
FORTHWORD "NEGATE"
-NEGATE: XOR #-1,TOS
- ADD #1,TOS
- mNEXT
+ JMP NEGATE
;https://forth-standard.org/standard/core/ABS
;C ABS n1 -- +n2 absolute value
JN NEGATE
mNEXT
-; ----------------------------------------------------------------------
+;https://forth-standard.org/standard/double/DABS
+;C DABS d1 -- |d1| absolute value
+ FORTHWORD "DABS"
+DABBS: AND #-1,TOS ; clear V, set N
+ JGE DABBSEND ; JMP if positive
+DNEGATE: XOR #-1,0(PSP)
+ XOR #-1,TOS
+ ADD #1,0(PSP)
+ ADDC #0,TOS
+DABBSEND mNEXT
+
+;-------------------------------------------------------------------------------
; COMPARAISON OPERATIONS
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
;https://forth-standard.org/standard/core/ZeroEqual
;C 0= n/u -- flag return true if TOS=0
;https://forth-standard.org/standard/core/Zeroless
;C 0< n -- flag true if TOS negative
FORTHWORD "0<"
-ZEROLESS: ADD TOS,TOS ; set carry if TOS negative
- SUBC TOS,TOS ; TOS=-1 if carry was clear
- XOR #-1,TOS ; TOS=-1 if carry was set
+ZEROLESS: ADD TOS,TOS ;1 set carry if TOS negative
+ SUBC TOS,TOS ;1 TOS=-1 if carry was clear
+ XOR #-1,TOS ;1 TOS=-1 if carry was set
mNEXT
+;https://forth-standard.org/standard/core/Zeromore
+;C 0> n -- flag true if TOS positive
+ FORTHWORD "0>"
+ZEROMORE: CMP #1,TOS
+ JGE TOSTRUE
+ JMP TOSFALSE
+
;https://forth-standard.org/standard/core/Equal
;C = x1 x2 -- flag test x1=x2
FORTHWORD "="
-EQUAL: SUB @PSP+,TOS ; 2
- JNZ TOSFALSE ; 2 --> +4
-TOSTRUE MOV #-1,TOS ; 2 (MOV @R3+,TOS)
- mNEXT ; 4
+EQUAL: SUB @PSP+,TOS ;2
+ JNZ TOSFALSE ;2 --> +4
+TOSTRUE MOV #-1,TOS ;1
+ mNEXT ;4
;https://forth-standard.org/standard/core/less
;C < n1 n2 -- flag test n1<n2, signed
FORTHWORD "<"
-LESS: MOV @PSP+,W ; 2 W=n1
- SUB TOS,W ; 1 W=n1-n2 flags set
- JL TOSTRUE ; 2
-TOSFALSE MOV #0,TOS ; 1
- mNEXT ; 4
+LESS: MOV @PSP+,W ;2 W=n1
+ SUB TOS,W ;1 W=n1-n2 flags set
+ JL TOSTRUE ;2
+TOSFALSE MOV #0,TOS ;1
+ mNEXT ;4
;https://forth-standard.org/standard/core/more
;C > n1 n2 -- flag test n1>n2, signed
FORTHWORD ">"
-GREATER: SUB @PSP+,TOS ; 2 TOS=n2-n1
- JL TOSTRUE ; 2
- MOV #0,TOS ; 1
- mNEXT ; 4
+GREATER: SUB @PSP+,TOS ;2 TOS=n2-n1
+ JL TOSTRUE ;2
+ MOV #0,TOS ;1
+ mNEXT ;4
;https://forth-standard.org/standard/core/Uless
;C U< u1 u2 -- flag test u1<u2, unsigned
FORTHWORD "U<"
-ULESS: MOV @PSP+,W ; 2
- SUB TOS,W ; 1 u1-u2 in W, cy clear if borrow
- JNC TOSTRUE ; 2
- MOV #0,TOS ; 1
- mNEXT ; 4
+ULESS: MOV @PSP+,W ;2
+ SUB TOS,W ;1 u1-u2 in W, carry clear if borrow
+ JNC TOSTRUE ;2
+ MOV #0,TOS ;1
+ mNEXT ;4
-; ----------------------------------------------------------------------
-; BRANCH and LOOP OPERATIONS
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+; BRANCH and LOOP OPERATORS
+;-------------------------------------------------------------------------------
;Z branch -- branch always
-; FORTHWORD "BRANCH"
BRAN: MOV @IP,IP ; 2
mNEXT ; 4
;Z ?branch x -- branch if TOS = zero
-; FORTHWORD "?BRANCH"
QBRAN: CMP #0,TOS ; 1 test TOS value
- MOV @PSP+,TOS ; 2 pop new TOS value (doesn't change flags)
+QBRAN1 MOV @PSP+,TOS ; 2 pop new TOS value (doesn't change flags)
JZ bran ; 2 if TOS was zero, take the branch = 11 cycles
ADD #2,IP ; 1 else skip the branch destination
mNEXT ; 4 ==> branch not taken = 10 cycles
+;Z 0?branch x -- branch if TOS <> zero
+QZBRAN: SUB #1,TOS ; 1 borrow (clear cy) if TOS was 0
+ SUBC TOS,TOS ; 1 TOS=-1 if borrow was set
+ JMP QBRAN1 ; 2
+
+
;Z (do) n1|u1 n2|u2 -- R: -- sys1 sys2 run-time code for DO
; n1|u1=limit, n2|u2=index
-; FORTHWORD "(DO)"
-
xdo: MOV #8000h,X ;2 compute 8000h-limit "fudge factor"
SUB @PSP+,X ;2
MOV TOS,Y ;1 loop ctr = index+fudge
; run-time code for +LOOP
; Add n to the loop index. If loop terminates, clean up the
; return stack and skip the branch. Else take the inline branch.
-; FORTHWORD "(+LOOP)"
-
xploop: ADD TOS,0(RSP) ;4 increment INDEX by TOS value
MOV @PSP+,TOS ;2 get new TOS, doesn't change flags
xloopnext BIT #100h,SR ;2 is overflow bit set?
; Add 1 to the loop index. If loop terminates, clean up the
; return stack and skip the branch. Else take the inline branch.
; Note that LOOP terminates when index=8000h.
-; FORTHWORD "(LOOP)"
-
xloop: ADD #1,0(RSP) ;4 increment INDEX
JMP xloopnext ;2
+;https://forth-standard.org/standard/core/UNLOOP
;C UNLOOP -- R: sys1 sys2 -- drop loop parms
FORTHWORD "UNLOOP"
UNLOOP: JMP UNXLOOP
+;https://forth-standard.org/standard/core/I
;C I -- n R: sys1 sys2 -- sys1 sys2
;C get the innermost loop index
FORTHWORD "I"
-II: SUB #2,PSP ; make room in TOS
- MOV TOS,0(PSP)
- MOV @RSP,TOS ; index = loopctr - fudge
- SUB 2(RSP),TOS
- mNEXT
+II: SUB #2,PSP ;1 make room in TOS
+ MOV TOS,0(PSP) ;3
+ MOV @RSP,TOS ;2 index = loopctr - fudge
+ SUB 2(RSP),TOS ;3
+ mNEXT ;4 13~
+;https://forth-standard.org/standard/core/J
;C J -- n R: 4*sys -- 4*sys
;C get the second loop index
FORTHWORD "J"
SUB 6(RSP),TOS
mNEXT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; SYSTEM VARIABLES & CONSTANTS
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+
+;https://forth-standard.org/standard/core/PAD
+; PAD -- pad address
+ FORTHWORD "PAD"
+PAD mDOCON
+ .WORD PAD_ORG
+
+; TIB -- terminal input buffer address
+ FORTHWORD "TIB"
+TIB mDOCON
+ .WORD TIB_ORG ; constant, may be modified by IS
+
+; CPL -- terminal input buffer lenght (CPL = Chars Per Line)
+ FORTHWORD "CPL"
+CPL mDOCON
+ .WORD TIB_LEN ; constant, may be modified by IS
;https://forth-standard.org/standard/core/toIN
;C >IN -- a-addr holds offset in input stream
FBLANK: mDOCON
.word 32
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; MULTIPLY
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
.IFNDEF MPY ; if no hardware MPY
;https://forth-standard.org/standard/core/UMTimes
;C UM* u1 u2 -- ud unsigned 16x16->32 mult.
FORTHWORD "UM*"
-UMSTAR: MOV @PSP,S ; U1 = MULTIPLICANDlo
- MOV #0,W ; 0 -> created MULTIPLICANDhi
- MOV #0,Y ; 0 -> created RESULTlo
- MOV #0,T ; 0 -> created RESULThi
- MOV #1,X ; BIT TEST REGISTER
+UMSTAR: MOV @PSP,S ;2 U1 = MULTIPLICANDlo
+ MOV #0,W ;1 0 -> created MULTIPLICANDhi
+ MOV #0,Y ;1 0 -> created RESULTlo
+ MOV #0,T ;1 0 -> created RESULThi
+ MOV #1,X ;1 BIT TEST REGISTER
UMSTARLOOP BIT X,TOS ;1 TEST ACTUAL BIT MULTIPLIER
JZ UMSTARNEXT ;2 IF 0: DO NOTHING
ADD S,Y ;1 IF 1: ADD MULTIPLICAND TO RESULT
ADDC W,W ;1 (RLC MSBs)
ADD X,X ;1 (RLA) NEXT BIT TO TEST
JNC UMSTARLOOP ;2 IF BIT IN CARRY: FINISHED 10~ loop
- MOV Y,0(PSP) ; low result on stack
- MOV T,TOS ; high result in TOS
+ MOV Y,0(PSP) ;3 low result on stack
+ MOV T,TOS ;1 high result in TOS
mNEXT
- .ENDIF ; hardware MPY
+ .ENDIF ; no hardware MPY
-; ----------------------------------------------------------------------------------------
-; ANS complement OPTION that include ALIGNMENT, PORTABILITY, ARITHMETIC and DOUBLE options
-; ----------------------------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+; ANS complement OPTION
+;-------------------------------------------------------------------------------
.IFDEF ANS_CORE_COMPLIANT
.include "ADDON\ANS_COMPLEMENT.asm"
-; ----------------------------------------------------------------------------------------
-
.ELSEIF
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; ALIGNMENT OPERATORS OPTION
-; ----------------------------------------------------------------------
- .IFDEF ALIGNMENT ; included in ANS_COMPLEMENT
- .include "ADDON\ALIGNMENT.asm"
- .ENDIF ; ALIGNMENT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+ .IFDEF ALIGNMENT ; included in ANS_COMPLEMENT
+ .include "ADDON\ALIGNMENT.asm"
+ .ENDIF ; ALIGNMENT
+
+;-------------------------------------------------------------------------------
; PORTABILITY OPERATORS OPTION
-; ----------------------------------------------------------------------
- .IFDEF PORTABILITY
- .include "ADDON\PORTABILITY.asm"
- .ENDIF ; PORTABILITY
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+ .IFDEF PORTABILITY
+ .include "ADDON\PORTABILITY.asm"
+ .ENDIF ; PORTABILITY
+
+;-------------------------------------------------------------------------------
; ARITHMETIC OPERATORS OPTION
-; ----------------------------------------------------------------------
- .IFDEF ARITHMETIC ; included in ANS_COMPLEMENT
- .include "ADDON\ARITHMETIC.asm"
- .ENDIF ; ARITHMETIC
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+ .IFDEF ARITHMETIC ; included in ANS_COMPLEMENT
+ .include "ADDON\ARITHMETIC.asm"
+ .ENDIF ; ARITHMETIC
+
+;-------------------------------------------------------------------------------
; DOUBLE OPERATORS OPTION
-; ----------------------------------------------------------------------
- .IFDEF DOUBLE ; included in ANS_COMPLEMENT
- .include "ADDON\DOUBLE.asm"
- .ENDIF ; DOUBLE
+;-------------------------------------------------------------------------------
+ .IFDEF DOUBLE ; included in ANS_COMPLEMENT
+ .include "ADDON\DOUBLE.asm"
+ .ENDIF ; DOUBLE
-; ----------------------------------------------------------------------------------------
.ENDIF ; ANS_COMPLEMENT
-; ----------------------------------------------------------------------------------------
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; NUMERIC OUTPUT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; Numeric conversion is done last digit first, so
; the output buffer is built backwards in memory.
;https://forth-standard.org/standard/core/num-start
-;C <# -- begin numeric conversion (initialize Hold Pointer in PAD area)
+;C <# -- begin numeric conversion (initialize Hold Pointer)
FORTHWORD "<#"
LESSNUM: MOV #BASE_HOLD,&HP
mNEXT
; unsigned 32-BIT DIVIDEND : 16-BIT DIVISOR --> 32-BIT QUOTIENT, 16-BIT REMAINDER
-; DVDhi|DVDlo : DVR --> QUOThi|QUOTlo, REMAINDER
-; about 2 times faster if ud1 < 65536 (it's the general case)
-
-; input registers :
-; T = DIVISOR
-; S = DVDlo
-; W = DVDhi
-; output registers :
-; W = remainder
-; X = QUOTlo
-; Y = QUOThi
-; saved registers :
-; IP = count
-; TOS = DVD48
-
-UDIVQ32: ; use S,T,W,X,Y
- .word 151Eh ;4 PUSHM TOS,IP (1+1 push,TOS=Eh): save all no scratch registers before use
- MOV #0,TOS ;1 TOS = DVD48 = 0
- MOV #32,IP ;3 init loop count
- CMP #0,W ;1 DVDhi <> 0 ?
+; DVDhi|DVDlo : DIVlo --> QUOThi|QUOTlo REMlo
+; then REMlo is converted in ASCII char
+; 2 times faster if DVDhi = 0 (it's the general case)
+
+; Input: division NUM
+; -----------------------------
+; S = DVDlo (15-0) = ud1lo
+; TOS = DVDhi (31-16) = ud1hi
+; W = REMAINDER(15-0)
+; T = DIVlo = BASE
+; rDODOES = count
+
+; Output: division NUM
+; -----------------------------
+; X = QUOTlo = ud2lo
+; Y = QUOThi = ud2hi
+; W = REMlo = digit --> char --> -[HP]
+
+;https://forth-standard.org/standard/core/num
+;C # ud1lo ud1hi -- ud2lo ud2hi convert 1 digit of output
+ FORTHWORD "#"
+NUM MOV @PSP,S ;2 TOS = DVDhi, S = DVDlo
+ MOV.B &BASE,T ;3 T = DIVlo
+ MOV #0,W ;1 W = REMlo = 0
+ MOV #32,rDODOES ;2 init loop count
+ CMP #0,TOS ;1 DVDhi <> 0 ?
JNZ MDIV1 ;2 yes
- RRA IP ;1 no: loop count / 2
- MOV S,W ;1 DVD = DVD<<16
- MOV #0,S ;1
- MOV #0,X ;1 QUOTlo = 0
-MDIV1 CMP T,TOS ;1 DVD48 > divisor ?
- JNC MDIV2 ;2 U<
- SUB T,TOS ;1 DVD48 - DVR
-MDIV2 ADDC X,X ;1 RLC quotLO
- ADDC Y,Y ;1 RLC quotHI
- SUB #1,IP ;1 Decrement loop counter
- JN ENDMDIVIDE ;2 If 0< --> end
+ RRA rDODOES ;1 no: loop count / 2
+ MOV S,TOS ;1 DVDhi <-- DVDlo
+ MOV #0,S ;1 DVDlo <-- 0
+ MOV #0,X ;1 QUOTlo <-- 0 (to do QUOThi = 0 at the end of division)
+MDIV1: CMP T,W ;1 REMlo U>= DIVlo ?
+ JNC MDIV2 ;2 no
+ SUB T,W ;1 REMlo - DIVlo
+MDIV2: ADDC X,X ;1 RLC QUOTlo
+ ADDC Y,Y ;1 RLC QUOThi
+ SUB #1,rDODOES ;1 Decrement loop counter
+ JN ENDMDIV ;2 If 0< --> end
ADD S,S ;1 RLA DVDlo
- ADDC W,W ;1 RLC DVDhi
- ADDC TOS,TOS ;1 RLC DVD48
+ ADDC TOS,TOS ;1 RLC DVDhi
+ ADDC W,W ;1 RLC REMlo
JNC MDIV1 ;2 14~ loop
- SUB T,TOS ;1 DVD48 - DVR
+ SUB T,W ;1 REMlo - DIVlo
BIS #1,SR ;1 SETC
JMP MDIV2 ;2 14~ loop
-ENDMDIVIDE MOV TOS,W ;1 DVD48 ==> W = remainder
- .word 171Dh ;4 POPM IP, TOS
- RET ;4 27 words
-
-
-;https://forth-standard.org/standard/core/num
-;C # ud1lo:ud1hi -- ud2lo:ud2hi convert 1 digit of output
- FORTHWORD "#"
-NUM: MOV &BASE,T ;3 T = Divisor
- MOV @PSP,S ;2 S = DVDlo
- MOV TOS,W ;1 TOS ==> W = DVDhi
- CALL #UDIVQ32 ;4 use S,T,W,X,Y
+ENDMDIV MOV #xdodoes,rDODOES;2 restore rDODOES
MOV X,0(PSP) ;3 QUOTlo in 0(PSP)
MOV Y,TOS ;1 QUOThi in TOS
-TODIGIT CMP.B #10,W ;2 W = REMAINDER
+TODIGIT CMP.B #10,W ;2 W = REMlo
JLO TODIGIT1 ;2 U<
ADD #7,W ;2
TODIGIT1 ADD #30h,W ;2
HOLDW SUB #1,&HP ;3 store W=char --> -[HP]
MOV &HP,Y ;3
MOV.B W,0(Y) ;3
- mNEXT ;4 23 words, about 290/490 cycles/char
+ mNEXT ;4 45 words, about 270/492 cycles/char
;https://forth-standard.org/standard/core/numS
;C #S udlo:udhi -- udlo:udhi=0 convert remaining digits
FORTHWORD "#S"
NUMS: mDOCOL
.word NUM ;
-NUMS1 FORTHtoASM ;
- SUB #2,IP ;1 define NUM return
- CMP #0,X ;1 test udlo first
+ FORTHtoASM ;
+ SUB #2,IP ;1 restore NUM return
+ CMP #0,X ;1 test ud2lo first (generally true)
JNZ NUM ;2
- CMP #0,TOS ;1 then udhi
+ CMP #0,TOS ;1 then test ud2hi (generally false)
JNZ NUM ;2
-NUMSEND MOV @RSP+,IP ;2
- mNEXT ;4
+ MOV @RSP+,IP ;2
+ mNEXT ;4 about 280/505 cycles/char
;https://forth-standard.org/standard/core/num-end
;C #> udlo:udhi=0 -- c-addr u end conversion, get string
MOV @PSP+,TOS ;2
JMP HOLDW ;15
-;;https://forth-standard.org/standard/core/HOLDS
-;;Adds the string represented by addr u to the pictured numeric output string
-;;compilation use: <# S" string" HOLDS #>
-;;free HOLDS chars space in the 34 bytes HOLD area (requested by ANS) = 24 chars if hexa, 22 chars if decimal, 0 if binary.
-;;C HOLDS addr u --
-; FORTHWORD "HOLDS"
-;HOLDS MOV @PSP+,X ;2
-; ADD TOS,X ;1 src
-; MOV &HP,Y ;3 dst
-;HOLDSLOOP SUB #1,Y ;1 dst-1
-; SUB #1,X ;1 src-1
-; SUB #1,TOS ;1 cnt-1
-; JLO HOLDSNEXT ;2 u<
-; MOV.B @X,0(Y) ;4
-; JMP HOLDSLOOP ;2
-;HOLDSNEXT MOV Y,&HP ;3
-; MOV @PSP+,TOS ;2
-; mNEXT ;4 15 words
-
;https://forth-standard.org/standard/core/SIGN
;C SIGN n -- add minus sign if n<0
FORTHWORD "SIGN"
JN HOLDW ; 0<
mNEXT
-;X UD. udlo udhi -- display ud (unsigned)
- FORTHWORD "UD."
-UDDOT: mDOCOL
- .word LESSNUM,NUMS,NUMGREATER,TYPE
- .word SPACE,EXIT
-
;https://forth-standard.org/standard/core/Ud
;C U. u -- display u (unsigned)
FORTHWORD "U."
-UDOT: SUB #2,PSP
- MOV TOS,0(PSP)
- MOV #0,TOS
- JMP UDDOT
-
-;https://forth-standard.org/standard/double/DABS
-;C DABS d1 -- |d1| absolute value
-; FORTHWORD "DABS"
-DABBS: BIT #8000h,TOS ; 1
- JZ DABBSEND
- XOR #-1,0(PSP)
- XOR #-1,TOS
- ADD #1,0(PSP)
- ADDC #0,TOS
-DABBSEND mNEXT
+UDOT: mDOCOL
+ .word LESSNUM,lit,0,NUMS,NUMGREATER,TYPE,SPACE,EXIT
;https://forth-standard.org/standard/double/Dd
;C D. dlo dhi -- display d (signed)
;https://forth-standard.org/standard/core/d
;C . n -- display n (signed)
FORTHWORD "."
-DOT: BIT #8000h,TOS
- JZ UDOT
+DOT: CMP #0,TOS
+ JGE UDOT
SUB #2,PSP
- MOV #-1,TOS
+ MOV TOS,0(PSP)
+ MOV #-1,TOS ; extend sign
JMP DDOT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; DICTIONARY MANAGEMENT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
;https://forth-standard.org/standard/core/HERE
;C HERE -- addr returns dictionary ptr
CALL #RXOFF ;
mNEXT
-;https://forth-standard.org/standard/facility/KEYq
;F KEY? -- c get character from input device ; deferred word
; FORTHWORD "KEY?"
-KEYTST: MOV #PARENKEYTST,PC
+;KEYTST: MOV #PARENKEYTST,PC
;Z (KEY) -- c get character from the terminal
FORTHWORD "KEY"
KEY: MOV #PARENKEY,PC
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; INTERPRETER INPUT, the kernel of kernel !
-; ----------------------------------------------------------------------
-
- .IFDEF SD_CARD_LOADER ; ACCEPT becomes a DEFERred word
+;-------------------------------------------------------------------------------
- .include "forthMSP430FR_SD_ACCEPT.asm" ; that creates SD_ACCEPT and (SD_ACCEPT)
+ .IFDEF SD_CARD_LOADER
+ .include "forthMSP430FR_SD_ACCEPT.asm" ; that creates SD_ACCEPT
+ .ENDIF ; SD_CARD_LOADER
- .ELSE ; ACCEPT is not a DEFERred word
;https://forth-standard.org/standard/core/ACCEPT
-;C ACCEPT addr len -- len' get line at addr to interpret len' chars
+;C ACCEPT addr addr len -- addr' len' get line at addr to interpret len' chars
FORTHWORD "ACCEPT"
-ACCEPT:
+ACCEPT MOV #PARENACCEPT,PC
- .ENDIF
+;C (ACCEPT) addr addr len -- addr len' get len' (up to len) chars from terminal (TERATERM.EXE) via USBtoUART bridge
+ FORTHWORD "(ACCEPT)"
+PARENACCEPT
; con speed of TERMINAL link, there are three bottlenecks :
; 1- time to send XOFF/RTS_high on CR (CR+LF=EOL), first emergency.
; --------------------------------------;
MOV #ENDACCEPT,S ;2 S = ACCEPT XOFF return
MOV #AKEYREAD1,T ;2 T = default XON return
- .word 152Dh ;5 PUSHM IP,S,T, as IP ret, ACCEPT XOFF ret, XON ret
+; .word 1537h ;6 in advance, we can also save R7 to R4
+ .word 152Dh ;5 PUSHM IP,S,T, as IP ret, XOFF ret, XON ret
MOV TOS,W ;1 -- addr len
MOV @PSP,TOS ;2 -- org ptr )
ADD TOS,W ;1 -- org ptr W=Bound )
MOV #20h,S ;2 S = 'BL' to speed up char loop in part II ) for TERMINAL_INT use
MOV #AYEMIT_RET,IP ;2 IP = return for YEMIT )
BIT #UCRXIFG,&TERMIFG ;3 RX_Int ?
- JZ ACCEPTNEXT ;2 no : case of FORTH init or input terminal quiet
+ JZ ACCEPTNEXT ;2 no : case of quiet input terminal
MOV &TERMRXBUF,Y ;3 yes: clear RX_Int
CMP #0Ah,Y ;2 received char = LF ? (end of downloading ?)
- JNZ RXON ;2 no : RXON return ==> AKEYREAD1, to process first char of new line.
-ACCEPTNEXT ADD #2,RSP ;1 yes: remove previous XON return address,
- MOV #SLEEP,X ;2 set XON return ==> SLEEP
-; MOV #PARENSLEEP,X ;2 set XON return ==> SLEEP
- .word 154Dh ;7 PUSHM IP,S,T,W,X
+ JNZ RXON ;2 no : RXON return = AKEYREAD1, to process first char of new line.
+ACCEPTNEXT ADD #2,RSP ;1 yes: remove AKEYREAD1 as XON return,
+ MOV #SLEEP,X ;2 and set XON return = SLEEP
+ .word 154Dh ;7 PUSHM IP,S,T,W,X before SLEEP (and so WAKE on any interrupts)
; --------------------------------------;
; ======================================;
; ======================================;
.IFDEF TERMINALXONXOFF ;
MOV #17,&TERMTXBUF ;4 move char XON into TX_buf
+ .ENDIF ;
+ .IFDEF TERMINALCTSRTS ;
+ BIC.B #RTS,&HANDSHAKOUT ;4 set RTS low
+ .ENDIF ;
+ .IFDEF TERMINALXONXOFF ;
.IF TERMINALBAUDRATE/FREQUENCY <230400
RXON_LOOP BIT #UCTXIFG,&TERMIFG ;3 wait the sending end of XON, useless at high baudrates
JZ RXON_LOOP ;2
- .ENDIF
.ENDIF ;
- .IFDEF TERMINALCTSRTS ;
- BIC.B #RTS,&HANDSHAKOUT ;4 set RTS low
.ENDIF ;
; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;
; starts first and 3th stopwatches ;
; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^;
- RET ;4 to BACKGND or AKEYREAD1
-; --------------------------------------;
+ RET ;4 to BACKGND (End of file download or quiet input) or AKEYREAD1 (get next line of file downloading)
+; --------------------------------------; ...or user defined
+; ASMWORD "RXON"
+; JMP RXON
+
+; ASMWORD "RXOFF"
; ======================================;
RXOFF: ; NOP11
; ======================================;
.IFDEF TERMINALXONXOFF ;
MOV #19,&TERMTXBUF ;4 move XOFF char into TX_buf
+ .ENDIF ;
+ .IFDEF TERMINALCTSRTS ;
+ BIS.B #RTS,&HANDSHAKOUT ;4 set RTS high
+ .ENDIF ;
+ .IFDEF TERMINALXONXOFF ;
.IF TERMINALBAUDRATE/FREQUENCY <230400
RXOFF_LOOP BIT #UCTXIFG,&TERMIFG ;3 wait the sending end of XOFF, useless at high baudrates
JZ RXOFF_LOOP ;2
- .ENDIF
.ENDIF ;
- .IFDEF TERMINALCTSRTS ;
- BIS.B #RTS,&HANDSHAKOUT ;4 set RTS high
.ENDIF ;
RET ;4 to ENDACCEPT, ...or user defined
; --------------------------------------;
-; redirection of word SLEEP to word BACKGROUND is easy: MOV #SLEEP,X
-; MOV #BACKGROUND,2(X)
-;
-; ...but this word BACKGROUND must be ended by: MOV #(SLEEP),PC
-;
-; removing redirection made by : MOV #SLEEP,X
-; MOV #(SLEEP),2(X)
-;
+
; --------------------------------------;
- ASMWORD "SLEEP" ;
+ ASMWORD "SLEEP" ; may be redirected
SLEEP: ;
MOV #PARENSLEEP,PC ;3
; --------------------------------------;
; --------------------------------------;
- ASMWORD "(SLEEP)"
+ ASMWORD "(SLEEP)" ;
PARENSLEEP: ;
BIS &LPM_MODE,SR ;3 enter in LPMx sleep mode with GIE=1
-; --------------------------------------; default mode : LPM0.
+; --------------------------------------; default FAST FORTH mode (for its input terminal use) : LPM0.
+;###############################################################################################################
+;###############################################################################################################
; ### # # ####### ####### ###### ###### # # ###### ####### ##### # # ####### ###### #######
; # ## # # # # # # # # # # # # # # # # # # # #
; # # ## # # # # # # # # # # # # # # # # # #
; ### # # # ####### # # # # ##### # # ##### # # ####### # # #######
+;###############################################################################################################
+;###############################################################################################################
+
; here, Fast FORTH sleeps, waiting any interrupt.
; IP,S,T,W,X,Y registers (R13 to R8) are free for any interrupt routine...
; ...and so PSP and RSP stacks with their rules of use.
-; remember : in any interrupt routine you must include : BIC #0xF8,0(RSP) before RETI
+; remember: in any interrupt routine you must include : BIC #0x78,0(RSP) before RETI
; to force return to SLEEP.
-; or simply (previous SR flags are lost): ADD #2 RSP, then RET instead of RETI
+; or (bad idea ? previous SR flags are lost) simply : ADD #2 RSP, then RET instead of RETI
; ======================================;
- JMP SLEEP ;2 and here is the return for any interrupts, else TERMINAL_INT :-)
-; JMP PARENSLEEP ;2 and here is the return for any interrupts, else TERMINAL_INT :-)
+ JMP SLEEP ;2 here is the return for any interrupts, else TERMINAL_INT :-)
; ======================================;
; **************************************;
-TERMINAL_INT: ; <--- UCA0 RX interrupt vector, delayed by the LPMx wake up time
+TERMINAL_INT: ; <--- TEMR RX interrupt vector, delayed by the LPMx wake up time
; **************************************; if wake up time increases, max bauds rate decreases...
; (ACCEPT) part II under interrupt ; Org Ptr -- len'
; --------------------------------------;
- ADD #4,RSP ;1 remove SR and PC from stack
- .word 173Ah ;6 POPM W=bound,T=0Dh,S=20h,IP=AYEMIT_RET
+ ADD #4,RSP ;1 remove SR and PC from stack, SR flags are lost (unused by FORTH interpreter)
+ .word 173Ah ;6 POPM W=buffer_bound,T=0Dh,S=20h,IP=AYEMIT_RET
; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;
; starts the 2th stopwatch ;
; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^;
AKEYREAD1 ; <--- XON RET address 2 ; first emergency: anticipate XOFF on CR as soon as possible
CMP.B T,Y ;1 char = CR ?
JZ RXOFF ;2 then RET to ENDACCEPT
-; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;+ 4
-; stops the first stopwatch ; first bottleneck, best case result: 24~ + LPMx wake_up time..
+; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;+ 4 to send RXOFF
+; stops the first stopwatch ;= first bottleneck, best case result: 24~ + LPMx wake_up time..
; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; ...or 11~ in case of empty line
CMP.B S,Y ;1 printable char ?
JHS ASTORETEST ;2 yes
CMP.B #8,Y ; char = BS ?
- JNE WAITaKEY ;
+ JNE WAITaKEY ; case of other control chars
; --------------------------------------;
-; start of backspace ;
+; start of backspace ; made only by an human
; --------------------------------------;
-BACKSPACE CMP @PSP,TOS ; Ptr = Org ?
+ CMP @PSP,TOS ; Ptr = Org ?
JZ WAITaKEY ; yes: do nothing
SUB #1,TOS ; no : dec Ptr
; --------------------------------------;
; --------------------------------------;
; end of backspace ;
; --------------------------------------;
-ASTORETEST CMP W,TOS ; 1 Bound is reached ? (protect against big lines without CR, UNIX like)
- JZ YEMIT ; 2 yes, send echo without store, then loopback
-ASTORE MOV.B Y,0(TOS) ; 3 no, store char @ Ptr before send echo, then loopback
+ASTORETEST CMP W,TOS ; 1 Bound is reached ?
+ JZ YEMIT ; 2 yes: send echo then loopback
+ MOV.B Y,0(TOS) ; 3 no: store char @ Ptr, send echo then loopback
ADD #1,TOS ; 1 increment Ptr
YEMIT: .word 4882h ; hi7/4~ lo:12/4~ send/send_not echo to terminal
.word TERMTXBUF ; 3 MOV Y,&TERMTXBUF
; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^;
; --------------------------------------;
-ENDACCEPT ; <--- XOFF RET address
+ENDACCEPT ; <--- XOFF return address
; --------------------------------------;
- MOV #LPM0+GIE,&LPM_MODE ; reset LPM_MODE to default mode LPM0
-DROPEXIT SUB @PSP+,TOS ; Org Ptr -- len'
+ MOV #LPM0+GIE,&LPM_MODE ; reset LPM_MODE to default mode LPM0 for next line of input stream
+DROPEXIT
+; .word 1734h ;6 we can also restore R7 to R4
+ SUB @PSP+,TOS ; Org Ptr -- len'
MOV @RSP+,IP ; 2 and continue with INTERPRET with GIE=0.
; So FORTH machine is protected against any interrupt...
mNEXT ; ...until next falling down to LPMx mode of (ACCEPT) part1,
YEMIT2 BIT #UCTXIFG,&TERMIFG ; 3 wait the sending end of previous char (usefull for low baudrates)
JZ YEMIT2 ; 2
.ENDIF
- JMP YEMIT
+ JMP YEMIT ;9 12~
;https://forth-standard.org/standard/core/EMIT
;C EMIT c -- output character to the output device ; deferred word
FORTHWORD "EMIT"
-EMIT: MOV #PARENEMIT,PC ; 3
+EMIT: MOV #PARENEMIT,PC ;3 15~
;Z ECHO -- connect console output (default)
;https://forth-standard.org/standard/core/SPACE
;C SPACE -- output a space
FORTHWORD "SPACE"
-SPACE: SUB #2,PSP
- MOV TOS,0(PSP)
- MOV #20h,TOS
- JMP EMIT
+SPACE: SUB #2,PSP ;1
+ MOV TOS,0(PSP) ;3
+ MOV #20h,TOS ;2
+ JMP EMIT ;17~ 23~
;https://forth-standard.org/standard/core/SPACES
;C SPACES n -- output n spaces
JZ SPACESEND
PUSH IP
MOV #SPACESNEXT,IP
- JMP SPACE
+ JMP SPACE ;25~
SPACESNEXT FORTHtoASM
- SUB #2,IP
- SUB #1,TOS
- JNZ SPACE
+ SUB #2,IP ;1
+ SUB #1,TOS ;1
+ JNZ SPACE ;25~ ==> 27~ by space ==> 2.963 MBds @ 8 MHz
MOV @RSP+,IP
SPACESEND MOV @PSP+,TOS
mNEXT
MOV W,TOS
mDOCOL
.word xdo
-TYPELOOP .word II,CFETCH,EMIT,xloop,TYPELOOP
+TYPELOOP .word II,CFETCH,EMIT,xloop,TYPELOOP ; 13+6+15+16= 50~ char loop ==> 1.6MBds @ 8MHz
.word EXIT
ADDC #0,IP ; 1 -- addr u IP=addr+u aligned
mNEXT ; 4 16~
+ .IFDEF LOWERCASE
+
+ FORTHWORD "CAPS_ON"
+CAPS_ON: MOV #-1,&CAPS ; state by default
+ mNEXT
+
+ FORTHWORD "CAPS_OFF"
+CAPS_OFF: MOV #0,&CAPS
+ mNEXT
+
;https://forth-standard.org/standard/core/Sq
;C S" -- compile in-line string
FORTHWORDIMM "S\34" ; immediate
SQUOTE: mDOCOL
.word lit,XSQUOTE,COMMA
-SQUOTE1 .word lit,'"',WORDD ; -- c-addr (= HERE)
+SQUOTE1 .word CAPS_OFF
+ .word lit,'"',WORDD ; -- c-addr (= HERE)
+ .word CAPS_ON
FORTHtoASM
MOV @RSP+,IP
MOV.B @TOS,TOS ; -- u
ADDC #2,&DDP ;4 +2 bytes
mNEXT
- .IFDEF LOWERCASE
+ .ELSE
- FORTHWORD "CAPS_ON"
-CAPS_ON: MOV #-1,&CAPS ; state by default
+;https://forth-standard.org/standard/core/Sq
+;C S" -- compile in-line string
+ FORTHWORDIMM "S\34" ; immediate
+SQUOTE: mDOCOL
+ .word lit,XSQUOTE,COMMA
+SQUOTE1 .word lit,'"',WORDD ; -- c-addr (= HERE)
+ FORTHtoASM
+ MOV @RSP+,IP
+ MOV.B @TOS,TOS ; -- u
+ SUB #1,TOS ; -1 byte
+ ADD TOS,&DDP
+ MOV @PSP+,TOS
+CELLPLUSALIGN
+ BIT #1,&DDP ;3 carry set if 1
+ ADDC #2,&DDP ;4 +2 bytes
mNEXT
- FORTHWORD "CAPS_OFF"
-CAPS_OFF: MOV #0,&CAPS
- mNEXT
+ .ENDIF ; LOWERCASE
;https://forth-standard.org/standard/core/Dotq
;C ." -- compile string to print
FORTHWORDIMM ".\34" ; immediate
DOTQUOTE: mDOCOL
- .word CAPS_OFF
.word SQUOTE
- .word CAPS_ON
.word lit,TYPE,COMMA,EXIT
- .ELSE
-
-;https://forth-standard.org/standard/core/Dotq
-;C ." -- compile string to print
- FORTHWORDIMM ".\34" ; immediate
-DOTQUOTE: mDOCOL
- .word SQUOTE
- .word lit,TYPE,COMMA,EXIT
-
- .ENDIF ; LOWERCASE
-
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; INTERPRETER
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
;https://forth-standard.org/standard/core/WORD
;C WORD char -- addr Z=1 if len=0
-; parse a word delimited by char ( and begining usually at [TIB])
+; parse a word delimited by char separator
; "word" is capitalized
; TOIN is the relative displacement into buffer
-; empty line = 25 cycles + 7 cycles by char
+; spaces (as separator) filled line = 25 cycles + 7 cycles by char
FORTHWORD "WORD"
WORDD: MOV #SOURCE_LEN,S ;2 -- separator
MOV @S+,X ;2 X = buf_len
CMP.B @W+,TOS ;2 does char = separator ?
JZ SKIPCHARLOO ;2 -- separator if yes
SCANWORD SUB #1,W ;1
- MOV #96,T ;2 T = 96 = ascii(a)-1 (test value in register before SCANWORD loop)
+ MOV #96,T ;2 T = 96 = ascii(a)-1 (test value set in a register before SCANWORD loop)
SCANWORDLOO ; -- separator 15/23 cycles loop for upper/lower case char... write words in upper case !
MOV.B S,0(Y) ;3 first time puts anything in dst word length, then put char @ dst.
CMP W,X ;1 buf_ptr = buf_end ?
ADD #1,Y ;1 increment dst just before test loop
CMP.B S,T ;1 char U< 'a' ? ('a'-1 U>= char) this condition is tested at each loop
JC SCANWORDLOO ;2 15~ upper case char loop
- .IFDEF LOWERCASE ; enable lowercase strings
+ .IFDEF LOWERCASE ;
QCAPS CMP #0,&CAPS ;3 CAPS is OFF ? (case available only for ABORT" ." .( )
JZ SCANWORDLOO ;2 yes
.ENDIF ; LOWERCASE ; here CAPS is ON (other cases)
CMP.B #123,S ;2 char U>= 'z'+1 ?
JC SCANWORDLOO ;2 if yes
SUB.B #32,S ;2 convert lowercase char to uppercase
- JMP SCANWORDLOO ;2 28~ lower case char loop
+ JMP SCANWORDLOO ;2
SCANWORDEND SUB &SOURCE_ADR,W ;3 -- separator W=buf_ptr - buf_org = new >IN (first char separator next)
MOV W,&TOIN ;3 update >IN
mNEXT ;4 42/47 words
-
THREEDROP ADD #2,PSP
TWODROP ADD #2,PSP
MOV @PSP+,TOS
; ----------------------------------;
; decimal point process add-on ;
; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;
- BIC #UF1,SR ;2 reset flag UF1 used here as Decimal Point flag
+ BIC #UF9,SR ;2 reset flag UF9 used here as Decimal Point flag
MOV.B @TOS,IP ;2 IP = count of chars
ADD TOS,IP ;1 IP = end address
MOV TOS,S ;1 S = ptr
JLO SearchDPEND ;2
CMP.B @S+,W ;2 DP found ?
JNE SearchDP ;2 7~ loop by char
-DPfound BIS #UF1,SR ;2 DP found: set flag UF1
+DPfound BIS #UF9,SR ;2 DP found: set flag UF9
DPrubLoop MOV.B @S+,-2(S) ;4 rub out decimal point
CMP S,IP ;1 and move left one all susbsequent chars
JHS DPrubLoop ;2 7~ loop by char
SUB.B #'$',W ;2 = 0 ==> "$" : hex number ?
JZ PREFIXED ;2
QBINARY MOV #2,T ;1 BASE = 2
- SUB.B #1,W ;1 "%" - "$" - 1 = 0 ==> '%' : hex number ?
+ SUB.B #1,W ;1 "%" - "$" - 1 = 0 ==> '%' : bin number ?
JZ PREFIXED ;2
QDECIMAL ADD #8,T ;1 BASE = 10
ADD.B #2,W ;1 "#" - "%" + 2 = 0 ==> '#' : decimal number ?
XOR #-1,0(PSP) ;3 -- dlo-1 udhi tf
ADD #1,2(PSP) ;3 -- dlo dhi-1 tf
ADDC #0,0(PSP) ;3 -- dlo dhi tf
-QDOUBLE BIT #UF1,SR ;2 decimal point added ?
+QDOUBLE BIT #UF9,SR ;2 decimal point added ?
JNZ QNUMEND ;2 leave double
ADD #2,PSP ;1 leave number
QNUMEND mNEXT ;4 90 words TOS=-1 and Z=0 ==> conversion ok
; ----------------------------------;
; decimal point process add-on ;
; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;
- BIC #UF1,SR ;2 reset flag UF1 used here as decimal point flag
+ BIC #UF9,SR ;2 reset flag UF9 used here as decimal point flag
MOV.B @TOS,IP ;2 IP = count of chars
ADD TOS,IP ;1 IP = end address
MOV TOS,S ;1 S = ptr
JLO SearchDPEND ;2
CMP.B @S+,W ;2 DP found ?
JNE SearchDP ;2 7~ loop by char
-DPfound BIS #UF1,SR ;2 DP found: set flag UF1
+DPfound BIS #UF9,SR ;2 DP found: set flag UF9
DPrubLoop MOV.B @S+,-2(S) ;4 rub out decimal point
CMP S,IP ;1 and move left one all susbsequent chars
JHS DPrubLoop ;2 7~ loop by char
XOR #-1,0(PSP) ;3 -- dlo-1 udhi tf
ADD #1,2(PSP) ;3 -- dlo dhi-1 tf
ADDC #0,0(PSP) ;3 -- dlo dhi tf
-QDOUBLE BIT #UF1,SR ;2 decimal point added ?
+QDOUBLE BIT #UF9,SR ;2 decimal point added ?
JNZ QNUMEND ;2 process double numbers
ADD #2,PSP ;
QNUMEND mNEXT ;4 100 words TOS=-1 and Z=0 ==> conversion ok
.ENDIF ; MPY
-
;https://forth-standard.org/standard/core/EXECUTE
;C EXECUTE i*x xt -- j*x execute Forth word at 'xt'
FORTHWORD "EXECUTE"
;https://forth-standard.org/standard/core/LITERAL
;C LITERAL (n|d) -- append single numeric literal if compiling state
-; (n|d) -- append double numeric literal if compiling state and if UF1=1 (not ANS)
+; (n|d) -- append double numeric literal if compiling state and if UF9=1 (not ANS)
FORTHWORDIMM "LITERAL" ; immediate
LITERAL: CMP #0,&STATE ;3
JZ LITERALEND ;2
- BIT #UF1,SR ;2
- JZ LITERAL1 ;2
-LITERAL2 MOV &DDP,W ;3
- ADD #4,&DDP ;3
- MOV #lit,0(W) ;4
- MOV @PSP+,2(W) ;3
LITERAL1 MOV &DDP,W ;3
ADD #4,&DDP ;3
MOV #lit,0(W) ;4
MOV TOS,2(W) ;3
MOV @PSP+,TOS ;2
-LITERALEND mNEXT ;4 24~
+ BIT #UF9,SR ;2
+ BIC #UF9,SR ;2
+ JNZ LITERAL1 ;2
+LITERALEND mNEXT ;4 30~
;https://forth-standard.org/standard/core/COUNT
;C COUNT c-addr1 -- adr len counted->adr/len
;C INTERPRET i*x addr u -- j*x interpret given buffer
; This is the common factor of EVALUATE and QUIT.
; Absent from forth 2012
-
+; set addr, u as input buffer then parse it word by word
; FORTHWORD "INTERPRET"
INTERPRET: MOV TOS,&SOURCE_LEN ; -- addr u buffer lentgh ==> ticksource variable
MOV @PSP+,&SOURCE_ADR ; -- u buffer address ==> ticksource+2 variable
JZ COMMA ;2 c-addr -- if W xor STATE = 0 compile xt then loop back to INTLOOP
JNZ EXECUTE ;2 c-addr -- if W xor STATE <> 0 execute then loop back to INTLOOP
-INTQNUMNEXT FORTHtoASM ; -- n|c-addr fl Z = not a number
+INTQNUMNEXT FORTHtoASM ; -- n|c-addr fl Z = not a number, UF9 = double number request
MOV @PSP+,TOS ;2
MOV #INTLOOP,IP ;2 -- n|c-addr define LITERAL return
JNZ LITERAL ;2 n -- execute LITERAL then loop back to INTLOOP
ADD TOS,Y ;1
MOV.B #'?',0(Y) ;5 add '?' to end of word
MOV #FQABORTYES,IP ;2 define COUNT return
- JMP COUNT ;2 c-addr -- 44 words
+ JMP COUNT ;2 -- addr len 44 words
;https://forth-standard.org/standard/core/EVALUATE
; EVALUATE \ i*x c-addr u -- j*x interpret string
FORTHWORD "EVALUATE"
-EVALUATE: MOV #SOURCE_LEN,X
- PUSH @X+ ;4 push SOURCE_LEN
- PUSH @X+ ;4 push SOURCE_ADR
- PUSH @X+ ;4 push TOIN
- PUSH IP
+EVALUATE: MOV #SOURCE_LEN,X ;2
+ MOV @X+,S ;2 S = SOURCE_LEN
+ MOV @X+,T ;2 T = SOURCE_ADR
+ MOV @X+,W ;2 W = TOIN
+ .word 153Dh ;6 PUSHM IP,S,T,W
ASMtoFORTH
.word INTERPRET
FORTHtoASM
- MOV @RSP+,IP ;2
MOV @RSP+,&TOIN ;4
MOV @RSP+,&SOURCE_ADR ;4
MOV @RSP+,&SOURCE_LEN ;4
+ MOV @RSP+,IP ;2
mNEXT
;https://forth-standard.org/standard/core/QUIT
MOV #LSTACK,&LEAVEPTR
MOV #0,&STATE
- MOV #0,&SAVE_SYSRSTIV ;
+ .IFDEF SD_CARD_LOADER
+ .IFDEF CONDCOMP
+ .IFDEF BOOTLOADER
+; ----------------------------------;
+; BOOTSTRAP TEST ;
+; ----------------------------------;
+ CMP #0,&SAVE_SYSRSTIV ; if WARM
+ JZ QUIT0 ; no boostrap
+ BIT.B #SD_CD,&SD_CDIN ; SD_memory in SD_Card module ?
+ JNZ QUIT0 ; no
+; ----------------------------------;
+; BOOTSTRAP ; on SYSRSTIV <> 0
+; ----------------------------------;
+ SUB #2,PSP ;
+ MOV TOS,0(PSP) ;
+ MOV &SAVE_SYSRSTIV,TOS ;
+ MOV #0,&SAVE_SYSRSTIV ;
+ ASMtoFORTH ;
+ .word NOECHO ; warning ! your BOOT.4TH must to be finish with ECHO command!
+ .word XSQUOTE ; -- addr u
+ .byte 15,"LOAD\34 BOOT.4TH\34" ; issues error 2 if no such file...
+ .word BRAN,QUIT4 ;
+; ----------------------------------;
+ .ENDIF
+ .ENDIF
+ .ENDIF
-QUIT0 ASMtoFORTH
+QUIT0 MOV #0,&SAVE_SYSRSTIV ;
+ ASMtoFORTH
QUIT1 .word XSQUOTE
- .byte 4,13,"ok " ; CR + system prompt
-QUIT2 .word TYPE
-QUIT3 .word lit,TIB,DUP,lit,TIB_SIZE ; -- StringOrg StringOrg len
- .word ACCEPT ; -- StringOrg len'
+ .byte 3,13,"ok" ; CR + system prompt
+QUIT2 .word TYPE,SPACE
+QUIT3 .word TIB,DUP,CPL ; -- StringOrg StringOrg maxlenght
+ .word ACCEPT ; -- StringOrg len' (len' <= maxlenght)
.word SPACE
QUIT4 .word INTERPRET
- .word lit,PSTACK-2,SPFETCH,ULESS
+ .word DEPTH,ZEROLESS
.word XSQUOTE
- .byte 13,"stack empty !"
+ .byte 13,"stack empty! "
.word QABORT
.word lit,FRAM_FULL,HERE,ULESS
.word XSQUOTE
- .byte 11,"FRAM full !"
+ .byte 11,"FRAM full! "
.word QABORT
.word FSTATE,FETCH
.word QBRAN,QUIT1 ; case of interpretion state
.word XSQUOTE ; case of compilation state
- .byte 4,13," " ; CR + 3 spaces
+ .byte 3,13,32,32 ; CR + 2 blanks
.word BRAN,QUIT2
;https://forth-standard.org/standard/core/ABORT
QABORT: CMP #0,2(PSP) ; -- f c-addr u flag test
QABORTNO JZ THREEDROP
-QABORTYES MOV #4882h,&YEMIT ; restore default YEMIT = set ECHO
+QABORTYES MOV #4882h,&YEMIT ; -- c-addr u restore default YEMIT = set ECHO
+
.IFDEF SD_CARD_LOADER ; close all handles
- MOV &CurrentHdl,T
-QABORTCLOSE
- CMP #0,T
- JZ QABORTYESNOECHO
- MOV.B #0,HDLB_Token(T)
- MOV @T,T
- JMP QABORTCLOSE
+ MOV &CurrentHdl,T
+QABORTCLOSE CMP #0,T
+ JZ QABORTYESNOECHO
+ MOV.B #0,HDLB_Token(T)
+ MOV @T,T
+ JMP QABORTCLOSE
.ENDIF
- ; -- c-addr u
; ----------------------------------;
QABORTYESNOECHO ; <== WARM jumps here, thus, if NOECHO, TERMINAL can be disconnected without freezing the app
; ----------------------------------;
- CALL #QAB_DEFER ; restore default deferred words ....else WARM.
- .IFDEF MSP430ASSEMBLER ; reset all branch labels
- MOV #0,&CLRBW1
- MOV #0,&CLRBW2
- MOV #0,&CLRBW3
- MOV #0,&CLRFW1
- MOV #0,&CLRFW2
- MOV #0,&CLRFW3
- .ENDIF
-
-
+ CALL #QAB_DEFER ; restore default deferred words ....else WARM and SLEEP.
; ----------------------------------;
QABORTTERM ; wait the end of source file downloading
; ----------------------------------;
MOV #17,&TERMTXBUF ; yes move XON char into TX_buf
.ENDIF ;
.IFDEF TERMINALCTSRTS ;
- BIC.B #RTS,&HANDSHAKOUT ; set /RTS low (connected to /CTS pin of UARTtoUSB bridge)
+ BIC.B #RTS,&HANDSHAKOUT ; set /RTS low (connected to /CTS pin of UARTtoUSB bridge)
.ENDIF ;
QABORTLOOP BIC #UCRXIFG,&TERMIFG ; reset TERMIFG(UCRXIFG)
- MOV #RefillUSBtime,Y ; 2730*28 = 75 ms
-QABUSBLOOPJ ; 28~ loop : PL2303TA seems the slower USB device to refill its buffer.
- MOV #8,X ; 1~
-QABUSBLOOPI ; 3~ loop
- SUB #1,X ; 1~
- JNZ QABUSBLOOPI ; 2~
- SUB #1,Y ; 1~
- JNZ QABUSBLOOPJ ; 2~
- BIT #UCRXIFG,&TERMIFG ; 4 new char in TERMXBUF ?
+ MOV #RefillUSBtime,Y ; 2730*36 = 98 ms : PL2303TA seems to be the slower USB device to refill its TX buffer.
+QABUSBLOOPJ MOV #8,X ; 1~ <-------+
+QABUSBLOOPI NOP ; 1~ <---+ |
+ SUB #1,X ; 1~ | |
+ JNZ QABUSBLOOPI ; 2~ > 4~ loop -+ |
+ SUB #1,Y ; 1~ |
+ JNZ QABUSBLOOPJ ; 2~ --> 36~ loop --+
+ BIT #UCRXIFG,&TERMIFG ; 4 new char in TERMXBUF after refill time out ?
JNZ QABORTLOOP ; 2 yes, the input stream (download source file) is still active
-
; ----------------------------------;
; Display WARM/ABORT message ;
; ----------------------------------;
mDOCOL ; no, the input stream is quiet (end of download source file)
.word XSQUOTE ; -- c-addr u c-addr1 u1
- .byte 4,1Bh,"[7m" ;
+ .byte 4,27,"[7m" ;
.word TYPE ; -- c-addr u set reverse video
.word TYPE ; -- type abort message
.word XSQUOTE ; -- c-addr2 u2
- .byte 4,1Bh,"[0m" ;
+ .byte 4,27,"[0m" ;
.word TYPE ; -- set normal video
.word FORTH,ONLY ; to quit assembler and so to abort any ASSEMBLER definitions
.word DEFINITIONS ; reset CURRENT directory
+ .word PWR_STATE ; wipe, if exist, not well finished definition and its previous MARKER
.IFDEF LOWERCASE
.word CAPS_ON ;
.ENDIF
FORTHWORDIMM "ABORT\34" ; immediate
ABORTQUOTE: mDOCOL
-
- .IFDEF LOWERCASE
- .word CAPS_OFF,SQUOTE,CAPS_ON
- .word lit,QABORT,COMMA
- .word EXIT
- .ELSE
.word SQUOTE
.word lit,QABORT,COMMA
.word EXIT
- .ENDIF ; LOWERCASE
-
;https://forth-standard.org/standard/core/Tick
-;C ' -- xt find word in dictionary
+;C ' -- xt find word in dictionary and leave on stack its execution address
FORTHWORD "'"
TICK: mDOCOL ; separator -- xt
.word FBLANK,WORDD,FIND ; Z=1 if not found
BACKSLASH: MOV &SOURCE_LEN,&TOIN ;
mNEXT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; COMPILER
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+
+;https://forth-standard.org/standard/core/Bracket
+;C [ -- enter interpretative state
+ FORTHWORDIMM "[" ; immediate
+LEFTBRACKET: MOV #0,&STATE
+ mNEXT
+
+;https://forth-standard.org/standard/core/right-bracket
+;C ] -- enter compiling state
+ FORTHWORD "]"
+RIGHTBRACKET: MOV #-1,&STATE
+ mNEXT
+
+;https://forth-standard.org/standard/core/BracketTick
+;C ['] <name> -- find word & compile it as literal
+ FORTHWORDIMM "[']" ; immediate word, i.e. word executed also during compilation
+BRACTICK: mDOCOL
+ .word TICK ; get xt of <name>
+ .word lit,lit,COMMA ; append LIT action
+ .word COMMA,EXIT ; append xt literal
+
+;https://forth-standard.org/standard/core/DEFERStore
+;C DEFER! xt CFA_DEFER -- ; store xt to the address after DODEFER
+; FORTHWORD "DEFER!"
+DEFERSTORE: MOV @PSP+,2(TOS) ; -- CFA_DEFER xt --> [CFA_DEFER+2]
+ MOV @PSP+,TOS ; --
+ mNEXT
+
+;https://forth-standard.org/standard/core/IS
+;C IS <name> xt --
+; used as is :
+; DEFER DISPLAY create a "do nothing" definition (2 CELLS)
+; inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY
+; or in a definition : ... ['] U. IS DISPLAY ...
+; KEY, EMIT, CR, ACCEPT and WARM are DEFERred words
+
+; as IS replaces the PFA value of a "PFA word", it may be also used with VARIABLE and CONSTANT words...
+
+ FORTHWORDIMM "IS" ; immediate
+IS: mDOCOL
+ .word FSTATE,FETCH
+ .word QBRAN,IS_EXEC
+IS_COMPILE .word BRACTICK ; find the word, compile its CFA as literal
+ .word lit,DEFERSTORE,COMMA ; compile DEFERSTORE
+ .word EXIT
+IS_EXEC .word TICK,DEFERSTORE ; find the word, leave its CFA on the stack and execute DEFERSTORE
+ .word EXIT
+
+;https://forth-standard.org/standard/core/IMMEDIATE
+;C IMMEDIATE -- make last definition immediate
+ FORTHWORD "IMMEDIATE"
+IMMEDIATE: MOV &LAST_NFA,W
+ BIS.B #80h,0(W)
+ mNEXT
+
+;https://forth-standard.org/standard/core/RECURSE
+;C RECURSE -- recurse to current definition (compile current definition)
+ FORTHWORDIMM "RECURSE" ; immediate
+RECURSE: MOV &DDP,X ;
+ MOV &LAST_CFA,0(X) ;
+ ADD #2,&DDP ;
+ mNEXT
+
+
+;https://forth-standard.org/standard/core/POSTPONE
+ FORTHWORDIMM "POSTPONE" ; immediate
+POSTPONE: mDOCOL
+ .word FBLANK,WORDD,FIND,QDUP
+ .word QBRAN,NotFound
+ .word ZEROLESS ; immediate ?
+ .word QBRAN,POST1 ; yes
+ .word lit,lit,COMMA,COMMA
+ .word lit,COMMA
+POST1: .word COMMA,EXIT
+
+
+;;Z ?REVEAL -- if no stack mismatch, link this created word in the CURRENT vocabulary
+; FORTHWORD "REVEAL"
+QREVEAL: CMP PSP,&LAST_PSP ; Check SP with its saved value by :
+ JZ GOOD_CSP ; if no stack mismatch. See MARKER below
+BAD_CSP mDOCOL
+ .word XSQUOTE
+ .byte 15,"stack mismatch!"
+FQABORTYES .word QABORTYES
; HEADER create an header for a new word. Max count of chars = 126
-; common code for VARIABLE, CONSTANT, CREATE, DEFER, :, CODE, ASM.
+; common code for VARIABLE, CONSTANT, CREATE, DEFER, :, MARKER, CODE, ASM.
; don't link created word in vocabulary.
-
HEADER: mDOCOL
.word CELLPLUSALIGN ; ALIGN then make room for LFA
.word FBLANK,WORDD ;
; X is LAST_THREAD > used by VARIABLE, CONSTANT, CREATE, DEFER and :
; Y is NFA )
-BAD_CSP mDOCOL
- .word XSQUOTE
- .byte 15,"stack mismatch!"
-FQABORTYES .word QABORTYES
-
-;;Z ?REVEAL -- link last created word in vocabulary if no stack mismatch
-; FORTHWORD "REVEAL"
-QREVEAL: CMP PSP,&LAST_CSP ; check actual SP with saved value by :
- JNZ BAD_CSP ; if stack mismatch
- MOV &LAST_NFA,Y ;
- MOV &LAST_THREAD,X ;
-REVEAL MOV @X,-2(Y) ; [LAST_THREAD] --> LFA
- MOV Y,0(X) ; LAST_NFA --> [LAST_THREAD]
- mNEXT
-
-
;https://forth-standard.org/standard/core/VARIABLE
;C VARIABLE <name> -- define a Forth VARIABLE
FORTHWORD "VARIABLE"
-VARIABLE: CALL #HEADER ; -- W = DDP = CFA + 2 words
- MOV #DOVAR,-4(W)
- JMP REVEAL
+VARIABLE: CALL #HEADER ; W = DDP = CFA + 2 words
+ MOV #DOVAR,-4(W) ; CFA = DOVAR
+ JMP REVEAL ; PFA = undefined
;https://forth-standard.org/standard/core/CONSTANT
-;C CONSTANT <name> n -- define a Forth CONSTANT
+;C CONSTANT <name> n -- define a Forth CONSTANT (it's also an alias of VALUE)
FORTHWORD "CONSTANT"
-CONSTANT: CALL #HEADER ; -- W = DDP
- MOV #DOCON,-4(W) ; compile exec
- MOV TOS,-2(W) ; compile TOS as constant
+CONSTANT: CALL #HEADER ; W = DDP = CFA + 2 words
+ MOV #DOCON,-4(W) ; CFA = DOCON
+ MOV TOS,-2(W) ; PFA = n
MOV @PSP+,TOS
JMP REVEAL
+;;https://forth-standard.org/standard/core/VALUE
+;;( x "<spaces>name" -- ) define a Forth VALUE
+;;Skip leading space delimiters. Parse name delimited by a space.
+;;Create a definition for name with the execution semantics defined below,
+;;with an initial value equal to x.
+;
+;;name Execution: ( -- x )
+;;Place x on the stack. The value of x is that given when name was created,
+;;until the phrase x TO name is executed, causing a new value of x to be assigned to name.
+;
+;;TO name Run-time: ( x -- )
+;;Assign the value x to name.
+;
+; FORTHWORD "VALUE"
+; JMP CONSTANT
+;
+; FORTHWORDIMM "TO"
+; JMP IS
+
+
;https://forth-standard.org/standard/core/CREATE
-;C CREATE <name> -- define a CONSTANT with its next address
+;C CREATE <name> -- define a CONSTANT with its next address
; Execution: ( -- a-addr ) ; a-addr is the address of name's data field
; ; the execution semantics of name may be extended by using DOES>
FORTHWORD "CREATE"
CREATE: CALL #HEADER ; -- W = DDP
- MOV #DOCON,-4(W) ;4 first CELL = DOCON
- MOV W,-2(W) ;3 second CELL = HERE
+ MOV #DOCON,-4(W) ;4 CFA = DOCON
+ MOV W,-2(W) ;3 PFA = next address
JMP REVEAL
;https://forth-standard.org/standard/core/DOES
;C DOES> -- set action for the latest CREATEd definition
FORTHWORD "DOES>"
DOES: MOV &LAST_CFA,W ; W = CFA of latest CREATEd word that becomes a master word
- MOV #DODOES,0(W) ; remplace code of CFA (DOCON) by DODOES
- MOV IP,2(W) ; remplace parameter of PFA (HERE) by the address after DOES> as execution address
+ MOV #DODOES,0(W) ; replace old CFA (DOCON) by new CFA (DODOES)
+ MOV IP,2(W) ; replace old PFA by the address after DOES> as execution address
MOV @RSP+,IP ; exit of the new created word
NEXTADR mNEXT
;https://forth-standard.org/standard/core/DEFER
-;X DEFER <name> -- ; create a word to be deferred
+;C DEFER "<spaces>name" --
+;Skip leading space delimiters. Parse name delimited by a space.
+;Create a definition for name with the execution semantics defined below.
+
+;name Execution: --
+;Execute the xt that name is set to execute, i.e. NEXT (nothing),
+;until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name.
+
FORTHWORD "DEFER"
DEFER: CALL #HEADER
- MOV #4030h,-4(W) ;4 first CELL = MOV @PC+,PC = BR...
- MOV #NEXTADR,-2(W) ;4 second CELL = address of mNEXT below : created word does nothing by default
+ MOV #4030h,-4(W) ;4 CFA = MOV @PC+,PC = BR...
+ MOV #NEXTADR,-2(W) ;4 PFA = address of NEXT: created word does nothing by default
JMP REVEAL
-;https://forth-standard.org/standard/core/Bracket
-;C [ -- enter interpretative state
- FORTHWORDIMM "[" ; immediate
-LEFTBRACKET: MOV #0,&STATE
- mNEXT
-
-;https://forth-standard.org/standard/core/right-bracket
-;C ] -- enter compiling state
- FORTHWORD "]"
-RIGHTBRACKET: MOV #-1,&STATE
- mNEXT
-
-;https://forth-standard.org/standard/core/RECURSE
-;C RECURSE -- recurse to current definition (compile current definition)
- FORTHWORDIMM "RECURSE" ; immediate
-RECURSE: MOV &DDP,X ;
- MOV &LAST_CFA,0(X) ;
- ADD #2,&DDP ;
- mNEXT
;https://forth-standard.org/standard/core/Colon
;C : <name> -- begin a colon definition
.CASE 1
MOV #DOCOL1,-4(W) ; compile CALL rDOCOL
SUB #2,&DDP
-
.CASE 2
MOV #DOCOL1,-4(W) ; compile PUSH IP 3~
MOV #DOCOL2,-2(W) ; compile CALL rEXIT
-
.CASE 3 ; inlined DOCOL
MOV #DOCOL1,-4(W) ; compile PUSH IP 3~
MOV #DOCOL2,-2(W) ; compile MOV PC,IP 1~
MOV #DOCOL3,0(W) ; compile ADD #4,IP 1~
MOV #NEXT,+2(W) ; compile MOV @IP+,PC 4~
ADD #4,&DDP
-
- .ENDCASE ; DTC
+ .ENDCASE ; of DTC
MOV #-1,&STATE ; enter compiling state
-SAVE_PSP MOV PSP,&LAST_CSP ; save PSP for check compiling, used by QREVEAL
+SAVE_PSP MOV PSP,&LAST_PSP ; save PSP for check compiling, used by QREVEAL
mNEXT
;https://forth-standard.org/standard/core/Semi
;C ; -- end a colon definition
FORTHWORDIMM ";" ; immediate
SEMICOLON: CMP #0,&STATE ; interpret mode : semicolon becomes a comment separator
- JZ BACKSLASH ; tip: ; it's transparent to the preprocessor, so semicolon comments are kept in file.4th
+ JZ BACKSLASH ; tip: ";" is transparent to the preprocessor, so semicolon comments are kept in file.4th
mDOCOL ; compile mode
.word lit,EXIT,COMMA
.word QREVEAL,LEFTBRACKET,EXIT
-;https://forth-standard.org/standard/core/IMMEDIATE
-;C IMMEDIATE -- make last definition immediate
- FORTHWORD "IMMEDIATE"
-IMMEDIATE: MOV &LAST_NFA,W
- BIS.B #80h,0(W)
- mNEXT
-
-;https://forth-standard.org/standard/core/DEFERStore
-;CE DEFER! xt CFA_DEFER -- ; store xt to the address after DODEFER
-; FORTHWORD "DEFER!"
-DEFERSTORE: MOV @PSP+,2(TOS) ; -- CFA_DEFER xt --> [CFA_DEFER+2]
- MOV @PSP+,TOS ; --
- mNEXT
-
-;https://forth-standard.org/standard/core/IS
-;C IS <name> xt --
-; used as is :
-; DEFER DISPLAY create a "do nothing" definition (2 CELLS)
-; inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY
-; or in a definition : ... ['] U. IS DISPLAY ...
-; KEY, EMIT, CR, ACCEPT and WARM are DEFERred words
-
- FORTHWORDIMM "IS" ; immediate
-IS: mDOCOL
- .word FSTATE,FETCH
- .word QBRAN,IS_EXEC
-IS_COMPILE .word BRACTICK ; find the word, compile its CFA as literal
- .word lit,DEFERSTORE,COMMA ; compile DEFERSTORE
- .word EXIT
-IS_EXEC .word TICK,DEFERSTORE ; find the word, leave its CFA on the stack and execute DEFERSTORE
- .word EXIT
-
-;https://forth-standard.org/standard/core/BracketTick
-;C ['] <name> -- find word & compile it as literal
- FORTHWORDIMM "[']" ; immediate word, i.e. word executed also during compilation
-BRACTICK: mDOCOL
- .word TICK ; get xt of <name>
- .word lit,lit,COMMA ; append LIT action
- .word COMMA,EXIT ; append xt literal
-
-;https://forth-standard.org/standard/core/POSTPONE
- FORTHWORDIMM "POSTPONE" ; immediate
-POSTPONE: mDOCOL
- .word FBLANK,WORDD,FIND,QDUP
- .word QBRAN,NotFound
- .word ZEROLESS ; immediate ?
- .word QBRAN,POST1 ; yes
- .word lit,lit,COMMA,COMMA
- .word lit,COMMA
-POST1: .word COMMA,EXIT
-
+ .IFDEF CONDCOMP
;; CORE EXT MARKER
;;( "<spaces>name" -- )
;;Skip leading space delimiters. Parse name delimited by a space. Create a definition for name
;;of any structures still existing that could refer to deleted definitions or deallocated data space is
;;not necessarily provided. No other contextual information such as numeric base is affected
-; FORTHWORD "MARKER"
-; CALL #HEADER ;4
-; MOV #DODOES,-4(W) ;4 CFA = DODOES
-; MOV #MARKER_DOES,-2(W) ;4 PFA = MARKER_DOES
-; ADD #4,&DDP ;3
-; MOV &LASTVOC,0(W) ;5 [BODY] = VOCLINK to be restored
-; MOV Y,2(W) ;3 [BODY+2] = NFA
-; SUB #2,2(W) ;4 [BODY+2] = LFA = DP to be restored
-; JMP REVEAL ;2
-
-MARKER_DOES
- .IFDEF VOCABULARY_SET
- .word FORTH,ONLY,DEFINITIONS
- .ENDIF
- FORTHtoASM ; -- BODY IP is free
- MOV @TOS+,W ; -- BODY+2 W= old VOCLINK =VLK
- MOV W,&LASTVOC ; -- BODY+2 restore LASTVOC
- MOV @TOS,TOS ; -- OLD_DP
- MOV TOS,&DDP ; -- OLD_DP restore DP
-
- .SWITCH THREADS
-
- .CASE 1
-MARKALLVOC MOV W,Y ; -- OLD_DP W=VLK Y=VLK
-MRKWORDLOOP MOV -2(Y),Y ; -- OLD_DP W=VLK Y=NFA
- CMP Y,TOS ; -- OLD_DP CMP = TOS-Y : OLD_DP-NFA
- JNC MRKWORDLOOP ; loop back if TOS<Y : OLD_DP<NFA
- MOV Y,-2(W) ; W=VLK X=THD Y=NFA refresh thread with good NFA
- MOV @W,W ; -- OLD_DP W=[VLK] = next voclink
- CMP #0,W ; -- OLD_DP W=[VLK] = next voclink end of vocs ?
- JNZ MARKALLVOC ; -- OLD_DP W=VLK no : loopback
-
- .ELSECASE ; multi threads
-
-MARKALLVOC MOV #THREADS,IP ; -- OLD_DP W=VLK
- MOV W,X ; -- OLD_DP W=VLK X=VLK
-MRKTHRDLOOP MOV X,Y ; -- OLD_DP W=VLK X=VLK Y=VLK
- SUB #2,X ; -- OLD_DP W=VLK X=THD (thread ((case-2)to0))
-MRKWORDLOOP MOV -2(Y),Y ; -- OLD_DP W=VLK Y=NFA
- CMP Y,TOS ; -- OLD_DP CMP = TOS-Y : OLD_DP-NFA
- JNC MRKWORDLOOP ; loop back if TOS<Y : OLD_DP<NFA
-MARKTHREAD MOV Y,0(X) ; W=VLK X=THD Y=NFA refresh thread with good NFA
- SUB #1,IP ; -- OLD_DP W=VLK X=THD Y=NFA IP=CFT-1
- JNZ MRKTHRDLOOP ; loopback to compare NFA in next thread (thread-1)
- MOV @W,W ; -- OLD_DP W=[VLK] = next voclink
- CMP #0,W ; -- OLD_DP W=[VLK] = next voclink end of vocs ?
- JNZ MARKALLVOC ; -- OLD_DP W=VLK no : loopback
+MARKER_DOES FORTHtoASM ; execution part
+ MOV @RSP+,IP ; -- PFA
+ MOV @TOS+,&INIVOC ; set VOC_LINK value for RST_STATE
+ MOV @TOS,&INIDP ; set DP value for RST_STATE
+ MOV @PSP+,TOS ; --
+ JMP RST_STATE ; execute RST_STATE, PWR_STATE then STATE_DOES
+
+ FORTHWORD "MARKER" ; definition part
+ CALL #HEADER ;4 W = DP+4
+ MOV #DODOES,-4(W) ;4 CFA = DODOES
+ MOV #MARKER_DOES,-2(W) ;4 PFA = MARKER_DOES
+ MOV &LASTVOC,0(W) ;5 [BODY] = VOCLINK to be restored
+ SUB #2,Y ;1 Y = LFA
+ MOV Y,2(W) ;3 [BODY+2] = LFA = DP to be restored
+ ADD #4,&DDP ;3
+
+ .ENDIF ; CONDCOMP
+
+GOOD_CSP MOV &LAST_NFA,Y ;
+ MOV &LAST_THREAD,X ;
+REVEAL MOV @X,-2(Y) ; [LAST_THREAD] --> LFA
+ MOV Y,0(X) ; LAST_NFA --> [LAST_THREAD]
+ mNEXT
- .ENDCASE ; THREADS ; -- HERE
-
- MOV @PSP+,TOS ;
- MOV @RSP+,IP ;
- mNEXT ;
-; ----------------------------------;
; ----------------------------------------------------------------------
; CONTROL STRUCTURES
IFF: SUB #2,PSP ;
MOV TOS,0(PSP) ;
MOV &DDP,TOS ; -- HERE
- MOV #QBRAN,0(TOS) ; -- HERE
- ADD #4,&DDP ; compile two words
+ ADD #4,&DDP ; compile one word, reserve one word
+ MOV #QBRAN,0(TOS) ; -- HERE compile QBRAN
CELLPLUS ADD #2,TOS ; -- HERE+2=IFadr
mNEXT
+
;https://forth-standard.org/standard/core/ELSE
;C ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
FORTHWORDIMM "ELSE" ; immediate
-ELSS: MOV &DDP,W
- MOV #bran,0(W)
- ADD #4,W ; W=HERE+4
- MOV W,&DDP ; compile two words
+ELSS: ADD #4,&DDP ; make room to compile two words
+ MOV &DDP,W ; W=HERE+4
+ MOV #bran,-4(W)
MOV W,0(TOS) ; HERE+4 ==> [IFadr]
SUB #2,W ; HERE+2
MOV W,TOS ; -- ELSEadr
;C UNTIL BEGINadr -- resolve conditional backward branch
FORTHWORDIMM "UNTIL" ; immediate
UNTIL: MOV #qbran,X
-UNTIL1 MOV &DDP,W ; W = HERE
- ADD #4,&DDP ; compile two words
- MOV X,0(W) ; compile Bran or qbran at HERE
- MOV TOS,2(W) ; compile bakcward adr at HERE+2
+UNTIL1 ADD #4,&DDP ; compile two words
+ MOV &DDP,W ; W = HERE
+ MOV X,-4(W) ; compile Bran or qbran at HERE
+ MOV TOS,-2(W) ; compile bakcward adr at HERE+2
MOV @PSP+,TOS
mNEXT
FORTHWORDIMM "DO" ; immediate
DO: SUB #2,PSP ;
MOV TOS,0(PSP) ;
- MOV &DDP,TOS ; -- HERE
- MOV #xdo,0(TOS)
- ADD #2,TOS ; -- HERE+2
- MOV TOS,&DDP ; compile one word
+ ADD #2,&DDP ; make room to compile xdo
+ MOV &DDP,TOS ; -- HERE+2
+ MOV #xdo,-2(TOS) ; compile xdo
ADD #2,&LEAVEPTR ; -- HERE+2 LEAVEPTR+2
MOV &LEAVEPTR,W ;
MOV #0,0(W) ; -- HERE+2 L-- 0
mNEXT
;https://forth-standard.org/standard/core/LOOP
-;C LOOP DOadr -- L-- 0 a1 a2 .. aN
+;C LOOP DOadr -- L-- an an-1 .. a1 0
FORTHWORDIMM "LOOP" ; immediate
LOO: MOV #xloop,X
-ENDLOOP MOV &DDP,W
- ADD #4,&DDP ; compile two words
- MOV X,0(W) ; xloop --> HERE
- MOV TOS,2(W) ; DOadr --> HERE+2
+ENDLOOP ADD #4,&DDP ; make room to compile two words
+ MOV &DDP,W
+ MOV X,-4(W) ; xloop --> HERE
+ MOV TOS,-2(W) ; DOadr --> HERE+2
; resolve all "leave" adr
LEAVELOOP MOV &LEAVEPTR,TOS ; -- Adr of top LeaveStack cell
SUB #2,&LEAVEPTR ; --
MOV @TOS,TOS ; -- first LeaveStack value
CMP #0,TOS ; -- = value left by DO ?
JZ ENDLOOPEND
- MOV &DDP,0(TOS) ; move adr after loop as UNLOOP adr
+ MOV W,0(TOS) ; move adr after loop as UNLOOP adr
JMP LEAVELOOP
ENDLOOPEND MOV @PSP+,TOS
mNEXT
;https://forth-standard.org/standard/core/PlusLOOP
-;C +LOOP adrs -- L: 0 a1 a2 .. aN --
+;C +LOOP adrs -- L-- an an-1 .. a1 0
FORTHWORDIMM "+LOOP" ; immediate
PLUSLOOP: MOV #xploop,X
JMP ENDLOOP
MOVE_X mNEXT
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; WORDS SET for VOCABULARY, not ANS compliant
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
;X VOCABULARY -- create a vocabulary
.IFDEF VOCABULARY_SET
FORTHWORD "ALSO"
.ENDIF ; VOCABULARY_SET
-ALSO: MOV #12,W ; -- move up 6 words
+ALSO: MOV #14,W ; -- move up 7 words
MOV #CONTEXT,X ; X=src
MOV #CONTEXT+2,Y ; Y=dst
JMP MOVEUP ; src < dst
DEFINITIONS: MOV &CONTEXT,&CURRENT
mNEXT
-; ----------------------------------------------------------------------
-; IMPROVED POWER ON RESET AND INITIALIZATION
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
+; IMPROVED ON/OFF AND RESET
+;-------------------------------------------------------------------------------
+
+STATE_DOES
+ .IFDEF VOCABULARY_SET
+ .word FORTH,ONLY,DEFINITIONS ; doesn't restore search order pointers
+ .ENDIF
+ FORTHtoASM ; -- BODY IP is free
+ MOV @TOS+,W ; -- BODY+2 W = old VOCLINK = VLK
+ MOV W,&LASTVOC ; -- BODY+2 restore LASTVOC
+ MOV @TOS,TOS ; -- OLD_DP
+ MOV TOS,&DDP ; -- OLD_DP restore DP
+
+ .SWITCH THREADS
+ .CASE 1 ; mono thread vocabularies
+MARKALLVOC MOV W,Y ; -- OLD_DP W=VLK Y=VLK
+MRKWORDLOOP MOV -2(Y),Y ; -- OLD_DP W=VLK Y=NFA
+ CMP Y,TOS ; -- OLD_DP CMP = TOS-Y : OLD_DP-NFA
+ JNC MRKWORDLOOP ; loop back if TOS<Y : OLD_DP<NFA
+ MOV Y,-2(W) ; W=VLK X=THD Y=NFA refresh thread with good NFA
+ MOV @W,W ; -- OLD_DP W=[VLK] = next voclink
+ CMP #0,W ; -- OLD_DP W=[VLK] = next voclink end of vocs ?
+ JNZ MARKALLVOC ; -- OLD_DP W=VLK no : loopback
- FORTHWORD "PWR_STATE" ; set dictionary in same state as OFF/ON
+ .ELSECASE ; multi threads vocabularies
+MARKALLVOC MOV #THREADS,IP ; -- OLD_DP W=VLK
+ MOV W,X ; -- OLD_DP W=VLK X=VLK
+MRKTHRDLOOP MOV X,Y ; -- OLD_DP W=VLK X=VLK Y=VLK
+ SUB #2,X ; -- OLD_DP W=VLK X=THD (thread ((case-2)to0))
+MRKWORDLOOP MOV -2(Y),Y ; -- OLD_DP W=VLK Y=NFA
+ CMP Y,TOS ; -- OLD_DP CMP = TOS-Y : OLD_DP-NFA
+ JNC MRKWORDLOOP ; loop back if TOS<Y : OLD_DP<NFA
+MARKTHREAD MOV Y,0(X) ; W=VLK X=THD Y=NFA refresh thread with good NFA
+ SUB #1,IP ; -- OLD_DP W=VLK X=THD Y=NFA IP=CFT-1
+ JNZ MRKTHRDLOOP ; loopback to compare NFA in next thread (thread-1)
+ MOV @W,W ; -- OLD_DP W=[VLK] = next voclink
+ CMP #0,W ; -- OLD_DP W=[VLK] = next voclink end of vocs ?
+ JNZ MARKALLVOC ; -- OLD_DP W=VLK no : loopback
+
+ .ENDCASE ; of THREADS ; -- DDP
+ MOV @PSP+,TOS ;
+ MOV @RSP+,IP ;
+ mNEXT ;
+
+ FORTHWORD "PWR_STATE" ; reinitialize dictionary in same state as after OFF/ON
PWR_STATE: mDODOES ; DOES part of MARKER : resets pointers DP, voclink and latest
- .word MARKER_DOES ; execution vector of MARKER DOES
-MARKVOC .word lastvoclink ; as voclink value
-MARKDP .word ROMDICT ; as DP value
+ .word STATE_DOES ; execution vector of PWR_STATE
+MARKVOC .word lastvoclink ; initialised by forthMSP430FR.asm as voclink value
+MARKDP .word ROMDICT ; initialised by forthMSP430FR.asm as DP value
+
+ FORTHWORD "RST_STATE" ; reinitialize dictionary in same state as after <reset>
+RST_STATE: MOV &INIVOC,&MARKVOC ; INI value saved in FRAM
+ MOV &INIDP,&MARKDP ; INI value saved in FRAM
+ JMP PWR_STATE
- FORTHWORD "PWR_HERE" ; define dictionary bound for PWR_STATE
-PWR_HERE: MOV &DDP,&MARKDP
- MOV &LASTVOC,&MARKVOC
- JMP PWR_STATE
- FORTHWORD "RST_STATE" ; set dictionary in same state as <reset>
-RST_STATE: MOV &INIDP,&MARKDP
- MOV &INIVOC,&MARKVOC
- JMP PWR_STATE
+ FORTHWORD "PWR_HERE" ; define dictionary bound for power OFF/ON
+PWR_HERE: MOV &LASTVOC,&MARKVOC
+ MOV &DDP,&MARKDP
+ mNEXT
- FORTHWORD "RST_HERE" ; define dictionary bound for RST_STATE
-RST_HERE: MOV &DDP,&INIDP
- MOV &LASTVOC,&INIVOC
- JMP PWR_HERE ; and reset PWR_STATE same as RST_STATE
+ FORTHWORD "RST_HERE" ; define dictionary bound for <reset>
+RST_HERE: MOV &LASTVOC,&INIVOC
+ MOV &DDP,&INIDP
+ JMP PWR_HERE ; and init PWR_STATE same as RST_STATE
WIPE_DEFER MOV #PARENWARM,&WARM+2
.IFDEF SD_CARD_LOADER
MOV #PARENACCEPT,&ACCEPT+2 ; always restore default console input
.ENDIF
+ .IFDEF MSP430ASSEMBLER ; reset all branch labels
+ MOV #0,&CLRBW1
+ MOV #0,&CLRBW2
+ MOV #0,&CLRBW3
+ MOV #0,&CLRFW1
+ MOV #0,&CLRFW2
+ MOV #0,&CLRFW3
+ .ENDIF
+
RET
- FORTHWORD "WIPE" ; restore the program as it was in FastForth.hex file
+ FORTHWORD "WIPE" ; restore the program as it was in forthMSP430FR.txt file
WIPE:
; reset JTAG and BSL signatures ; unlock JTAG, SBW and BSL
MOV #SIGNATURES,X
; reset all FACTORY defered words to allow execution from SD_Card
CALL #WIPE_DEFER
; reinit this factory values :
- MOV #ROMDICT,&DDP
- MOV #lastvoclink,&LASTVOC
+ MOV #ROMDICT,&INIDP
+ MOV #lastvoclink,&INIVOC
; then reinit RST_STATE and PWR_STATE
- JMP RST_HERE
+ JMP RST_STATE
+
+
+
+; ------------------------------------------------------------------------------------------
+; forthMSP430FR : CONDITIONNAL COMPILATION
+; ------------------------------------------------------------------------------------------
+ .IFDEF CONDCOMP ; 2- conditionnal compilation part
+ .IFNDEF LOWERCASE
+ .WARNING "uncomment LOWERCASE ADD-ON to pass coretest COMPARE !"
+ .ENDIF ; LOWERCASE
+;COMPARE ( c-addr1 u1 c-addr2 u2 -- n )
+;https://forth-standard.org/standard/string/COMPARE
+;Compare the string specified by c-addr1 u1 to the string specified by c-addr2 u2.
+;The strings are compared, beginning at the given addresses, character by character,
+;up to the length of the shorter string or until a difference is found.
+;If the two strings are identical, n is zero.
+;If the two strings are identical up to the length of the shorter string,
+; n is minus-one (-1) if u1 is less than u2 and one (1) otherwise.
+;If the two strings are not identical up to the length of the shorter string,
+; n is minus-one (-1) if the first non-matching character in the string specified by c-addr1 u1
+; has a lesser numeric value than the corresponding character in the string specified by c-addr2 u2 and one (1) otherwise.
+ FORTHWORD "COMPARE"
+COMPARE
+ MOV TOS,S ;1 u2 = S
+ MOV @PSP+,Y ;2 addr2 = Y
+ MOV @PSP+,T ;2 u1 = T
+ MOV @PSP+,X ;2 addr1 = X
+COMPAR1 MOV T,TOS ;1
+ ADD S,TOS ;1
+ JZ COMPEQUAL ;2 end of all successfull comparisons
+ SUB #1,T ;1
+ JN COMPLESS ;2 u1<u2
+ SUB #1,S ;1
+ JN COMPGREATER ;2 u2<u1
+ ADD #1,X ;1
+ CMP.B @Y+,-1(X) ;4 char1-char2
+ JZ COMPAR1 ;2 char1=char2 17~ loop
+ JHS COMPGREATER ;2 char1>char2
+COMPLESS ; char1<char2
+ MOV #-1,TOS ;1
+ MOV @IP+,PC ;4
+COMPGREATER
+ MOV #1,TOS ;1
+COMPEQUAL
+ MOV @IP+,PC ;4 20 words
+
+;[THEN]
+;https://forth-standard.org/standard/tools/BracketTHEN
+ FORTHWORDIMM "[THEN]" ; do nothing
+ mNEXT
+
+ONEMIN
+ SUB #1,TOS
+ mNEXT
+
+;[ELSE]
+;Compilation:
+;Perform the execution semantics given below.
+;Execution:
+;( "<spaces>name ..." -- )
+;Skipping leading spaces, parse and discard space-delimited words from the parse area,
+;including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN],
+;until the word [THEN] has been parsed and discarded.
+;If the parse area becomes exhausted, it is refilled as with REFILL.
+ FORTHWORDIMM "[ELSE]"
+BRACKETELSE
+ mDOCOL
+ .word lit,1 ; 1
+BRACKETELSE1 ; BEGIN
+BRACKETELSE2 ; BEGIN
+ .word FBLANK,WORDD,COUNT ; BL WORD COUNT
+ .word DUP,QBRAN,BRACKETELSE10 ; DUP WHILE
+ .word OVER,OVER ; 2DUP
+ .word XSQUOTE ; S" [IF]"
+ .byte 4,"[IF]" ;
+ .word COMPARE ; COMPARE
+ .word QZBRAN,BRACKETELSE3 ; 0= IF
+ .word TWODROP,ONEPLUS ; 2DROP 1+
+ .word BRAN,BRACKETELSE8 ; (ENDIF)
+BRACKETELSE3 ; ELSE
+ .word OVER,OVER ; OVER OVER
+ .word XSQUOTE ; S" [ELSE]"
+ .byte 6,"[ELSE]" ;
+ .word COMPARE ; COMPARE
+ .word QZBRAN,BRACKETELSE5 ; 0= IF
+ .word TWODROP,ONEMIN ; 2DROP 1-
+ .word DUP,QBRAN,BRACKETELSE4 ; DUP IF
+ .word ONEPLUS ; 1+
+BRACKETELSE4 ; THEN
+ .word BRAN,BRACKETELSE7 ; (ENDIF)
+BRACKETELSE5 ; ELSE
+ .word XSQUOTE ; S" [THEN]"
+ .byte 6,"[THEN]" ;
+ .word COMPARE ; COMPARE
+ .word QZBRAN,BRACKETELSE6 ; 0= IF
+ .word ONEMIN ; 1-
+BRACKETELSE6 ; THEN
+BRACKETELSE7 ; THEN
+BRACKETELSE8 ; THEN
+ .word QDUP ; ?DUP
+ .word QZBRAN,BRACKETELSE9 ; 0= IF
+ .word EXIT ; EXIT
+BRACKETELSE9 ; THEN
+ .word BRAN,BRACKETELSE2 ; REPEAT
+BRACKETELSE10 ;
+ .word TWODROP ; 2DROP
+ .word XSQUOTE ;
+ .byte 3,13,107,111 ;
+ .word TYPE,SPACE ; CR ." ko " to show false branch of conditionnal compilation
+ .word TIB,DUP,CPL ; REFILL
+ .word ACCEPT ; -- StringOrg len' (len' <= TIB_LEN)
+ FORTHtoASM ;
+ MOV #0,&TOIN ;
+ MOV TOS,&SOURCE_LEN ; -- StringOrg len'
+ MOV @PSP+,&SOURCE_ADR ; -- len'
+ MOV @PSP+,TOS ; --
+ MOV #BRACKETELSE1,IP ; AGAIN
+ mNEXT ; 78 words
+
+
+;[IF]
+;https://forth-standard.org/standard/tools/BracketIF
+;Compilation:
+;Perform the execution semantics given below.
+;Execution: ;( flag | flag "<spaces>name ..." -- )
+;If flag is true, do nothing. Otherwise, skipping leading spaces,
+; parse and discard space-delimited words from the parse area,
+; including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN],
+; until either the word [ELSE] or the word [THEN] has been parsed and discarded.
+;If the parse area becomes exhausted, it is refilled as with REFILL. [IF] is an immediate word.
+;An ambiguous condition exists if [IF] is POSTPONEd,
+; or if the end of the input buffer is reached and cannot be refilled before the terminating [ELSE] or [THEN] is parsed.
+ FORTHWORDIMM "[IF]" ; flag --
+ CMP #0,TOS
+ MOV @PSP+,TOS
+ JZ BRACKETELSE
+ mNEXT
+
+;[UNDEFINED]
+;https://forth-standard.org/standard/tools/BracketUNDEFINED
+;Compilation:
+;Perform the execution semantics given below.
+;Execution: ( "<spaces>name ..." -- flag )
+;Skip leading space delimiters. Parse name delimited by a space.
+;Return a false flag if name is the name of a word that can be found,
+;otherwise return a true flag.
+ FORTHWORDIMM "[UNDEFINED]"
+ mDOCOL
+ .word FBLANK,WORDD,FIND,NIP,ZEROEQUAL,EXIT
+
+;[DEFINED]
+;https://forth-standard.org/standard/tools/BracketDEFINED
+;Compilation:
+;Perform the execution semantics given below.
+;Execution:
+;( "<spaces>name ..." -- flag )
+;Skip leading space delimiters. Parse name delimited by a space.
+;Return a true flag if name is the name of a word that can be found,
+;otherwise return a false flag. [DEFINED] is an immediate word.
+
+ FORTHWORDIMM "[DEFINED]"
+ mDOCOL
+ .word FBLANK,WORDD,FIND,NIP,EXIT
+
+ .ENDIF ; CONDCOMP
+
+; ------------------------------------------------------------------------------
+; forthMSP430FR : WARM
+; ------------------------------------------------------------------------------
; define FREQ used in WARM message (6)
.IF FREQUENCY = 0.25
; .word DOT ; display SYSSNIV
; .word DOT ; display SYSUNIV
.word XSQUOTE
- .byte 39," FastForth V160",FREQ," (C) J.M.Thoorens "
+ .byte 39," FastForth V162",FREQ," (C) J.M.Thoorens "
.word TYPE
.word LIT,FRAM_FULL,HERE,MINUS,UDOT
.word XSQUOTE ;
.byte 11,"bytes free ";
- .word QABORTYESNOECHO ; NOECHO enables any app to execute COLD without terminal connexion !
+ .word QABORTYESNOECHO ; NOECHO state enables any app to execute COLD or WARM without terminal connexion
;Z WARM -- ; deferred word used to init your application
FORTHWORD "WARM"
WARM: MOV #PARENWARM,PC
+; ------------------------------------------------------------------------------
+; forthMSP430FR : COLD
+; ------------------------------------------------------------------------------
+
;Z COLD -- performs a software reset
FORTHWORD "COLD"
-COLD: MOV #0A500h+PMMSWBOR,&PMMCTL0
+COLD MOV #0A500h+PMMSWBOR,&PMMCTL0
-; -------------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; in addition to <reset>, DEEP_RST restores the program as it was in the forthMSP430FR.txt file and the electronic fuse so.
-; -------------------------------------------------------------------------
+;-------------------------------------------------------------------------------
RESET
-; -------------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; case 1 : Power ON ==> RESET + the volatile program beyond PWR_HERE (not protected by PWR_STATE against POWER OFF) is lost
; SYSRSTIV = 2
; case 3 : TERM_TX wired to GND via 4k7 + <reset> ===> DEEP_RST, works even if the electronic fuse is "blown" !
; case 3.1 : (SYSRSTIV = 0Ah | SYSRSTIV >= 16h) ===> DEEP_RST on failure,
; case 3.2 : writing -1 in SAVE_SYSRSTIV then COLD ===> software DEEP_RST (WARM displays "-1")
-; -------------------------------------------------------------------------
+;-------------------------------------------------------------------------------
-; ------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; RESET : Target Init, limited to FORTH usage : I/O, FRAM, RTC
; all others I/O are set as input with pullup resistor
-; ------------------------------------------------------------------
+;-------------------------------------------------------------------------------
.include "TargetInit.asm" ; include for each target the init code
MOV &INI_TERM,&TERMVEC
MOV #CPUOFF+GIE,&LPM_MODE
-; -----------------------------------------------------------
+;-------------------------------------------------------------------------------
; RESET : INIT FORTH machine
-; -----------------------------------------------------------
+;-------------------------------------------------------------------------------
MOV #RSTACK,SP ; init return stack
MOV #PSTACK,PSP ; init parameter stack
.SWITCH DTC
MOV #10,&BASE
MOV #-1,&CAPS
-; -----------------------------------------------------------
+;-------------------------------------------------------------------------------
; RESET : test TERM_TXD/Deep_RST before init TERM_UART I/O
-; -----------------------------------------------------------
+;-------------------------------------------------------------------------------
BIC #LOCKLPM5,&PM5CTL0 ; activate all previous I/O settings before DEEP_RST test
MOV &SAVE_SYSRSTIV,Y ;
BIT.B #DEEP_RST,&Deep_RST_IN ; TERM TXD wired to GND via 4k7 resistor ?
ADD #1,Y ; to display SAVE_SYSRSTIV as negative value
MOV Y,&SAVE_SYSRSTIV
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; RESET : INIT TERM_UART
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
TERM_INIT
-
MOV #0081h,&TERMCTLW0 ; Configure TERM_UART UCLK = SMCLK
.include "TERMINALBAUDRATE.asm" ; include code to configure baudrate
BIC #UCSWRST,&TERMCTLW0 ; release from reset...
BIS #UCRXIE,&TERMIE ; ... then enable RX interrupt for wake up on terminal input
-; -----------------------------------------------------------
+;-------------------------------------------------------------------------------
; RESET : Select POWER_ON|<reset>|DEEP_RST
-; -----------------------------------------------------------
+;-------------------------------------------------------------------------------
SelectReset MOV #COLD_END,IP ; define return of WIPE,RST_STATE,PWR_STATE
MOV &SAVE_SYSRSTIV,Y;
JNZ RST_STATE ; else execute RST_STATE
JZ PWR_STATE ; yes execute PWR_STATE
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; RESET : INIT SD_Card optionally
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
COLD_END
.IFNDEF SD_CARD_LOADER ;
.word WARM ; the next step
JMP WARM
.ENDIF
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; ASSEMBLER OPTION
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
.IFDEF MSP430ASSEMBLER
.include "forthMSP430FR_ASM.asm"
.ENDIF
-; ----------------------------------------------------------------------
-; SD CARD FAT OPTIONS
-; ----------------------------------------------------------------------
- .IFDEF SD_CARD_LOADER
- .include "forthMSP430FR_SD_LowLvl.asm" ; SD primitives
- .include "forthMSP430FR_SD_LOAD.asm" ; SD LOAD fonctions
- .IFDEF SD_CARD_READ_WRITE
- .include "forthMSP430FR_SD_RW.asm" ; SD Read/Write fonctions
- .ENDIF
- .ENDIF ; SD_CARD_LOADER
-
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
; UTILITY WORDS OPTION
-; ----------------------------------------------------------------------
+;-------------------------------------------------------------------------------
.IFDEF UTILITY
.include "ADDON\UTILITY.asm"
.ENDIF ; UTILITY
-;-----------------------------------------------------------------------
-; SD TOOLS
-;-----------------------------------------------------------------------
- .IFDEF SD_TOOLS
-
- .IFNDEF UTILITY
- .include "ADDON\UTILITY.asm"
+ .IFDEF SD_CARD_LOADER
+;-------------------------------------------------------------------------------
+; SD CARD FAT OPTIONS
+;-------------------------------------------------------------------------------
+ .include "forthMSP430FR_SD_LowLvl.asm" ; SD primitives
+ .include "forthMSP430FR_SD_LOAD.asm" ; SD LOAD driver
+ .IFDEF SD_CARD_READ_WRITE
+ .include "forthMSP430FR_SD_RW.asm" ; SD Read/Write driver
.ENDIF
+;-------------------------------------------------------------------------------
+; SD TOOLS
+;-------------------------------------------------------------------------------
+ .IFDEF SD_TOOLS
.include "ADDON\SD_TOOLS.asm"
.ENDIF ; SD_READ_WRITE_TOOLS
+;-------------------------------------------------------------------------------
+ .ENDIF ; SD_CARD_LOADER
-; -----------------------------------------------------------
+;-------------------------------------------------------------------------------
; IT'S FINISH : RESOLVE ASSEMBLY PTR
-; -----------------------------------------------------------
-ROMDICT ; init DDP
+;-------------------------------------------------------------------------------
+ROMDICT ; init DDP with this current address
lastvoclink .equ voclink
lastforthword .equ forthlink
lastasmword .equ asmlink
.word voclink
voclink .set $-2
- FORTHWORDIMM "HI2LO" ; immediate, switch to low level, add ASSEMBLER context, set interpretation state
+ FORTHWORDIMM "HI2LO" ; immediate, switch to low level, add ASSEMBLER context, set interpretation state
mDOCOL
- .word HERE,CELLPLUS,COMMA
+HI2LO .word HERE,CELLPLUS,COMMA
.word LEFTBRACKET
HI2LONEXT .word ALSO,ASSEMBLER
.word EXIT
- FORTHWORD "CODE" ;
-ASMCODE CALL #HEADER ; same as ":" ...
- SUB #4,&DDP ; ...but compile nothing
+; FORTHWORDIMM "SEMIC" ; same as HI2LO, plus restore IP; counterpart of COLON
+; mDOCOL
+; .word HI2LO
+; .word LIT,413Dh,COMMA ; compile MOV @RSP+,IP
+; .word EXIT
+
+ FORTHWORD "CODE" ; a CODE word must be finished with ENDCODE
+ASMCODE CALL #HEADER ;
+ SUB #4,&DDP ;
mDOCOL
.word SAVE_PSP
.word BRAN,HI2LONEXT
FORTHWORD "ASM" ; used to define an assembler word which is not executable by FORTH interpreter
; i.e. typically an assembler word called by CALL and ended by RET
- ; ASM words are only v in ASSEMBLER CONTEXT
+ ; ASM words are only usable in another ASSEMBLER words
+ ; an ASM word must be finished with ENDASM
MOV &CURRENT,&ASM_CURRENT
MOV #ASSEMBLER_BODY,&CURRENT
JMP ASMCODE
- asmword "ENDASM" ; end of ASM word
+ asmword "ENDASM" ; end of an ASM word
MOV &ASM_CURRENT,&CURRENT
JMP ENDCODE
; Search ARG of <sep>"xxxx(REG)" ; <== PARAM210
SearchARG ASMtoFORTH ; -- separator search word first
.word WORDD,FIND ; -- c-addr
- .word ZEROEQUAL
- .word QBRAN,SearchARGW ; -- c-addr if found
+; .word ZEROEQUAL
+; .word QBRAN,SearchARGW ; -- c-addr if found
+ .word QZBRAN,SearchARGW ; -- c-addr if found
.word QNUMBER ;
.word QBRAN,NotFound ; -- c-addr
.word AsmSrchEnd ; -- value end if number found
MOV @RSP+,PC ; ret
QDOCON CMP #DOCON,X
JNZ QDODOES
- MOV 2(TOS),TOS ; remplace CFA by [PFA] for CONSTANT and CREATE words
+ MOV 2(TOS),TOS ; remplace CFA by [PFA] for CONSTANT (and CREATEd) words
MOV @RSP+,PC ; ret
QDODOES CMP #DODOES,X
JNZ AsmSrchEnd
-
-
-
-; ------------------------------------------------------------------------------------------
-; forthMSP430FR ASSEMBLER : .IF .ELSEIF .ENDIF structure
-; ------------------------------------------------------------------------------------------
-; it's borrows leave stack
-; [IF] interpret next word, if false scans line and refill it until [ELSE] or [IF] or [THEN] found, else do nothing
-; [ELSE] tests address, tests flag, remove them and leave [THEN] address, if false scans line and refill it until [THEN] found
-; [THEN] remove one parameter from leave stack
-
-; ASMWORD ".ELSEIF" ; fall here if [IF] was true
-;brELSE PSUH IP
-; MOV &LEAVEPTR,IP
-; CMP #brIF,-2(IP) ; case of [IF] state was true
-; JZ BrElseNext ; to skip [ELSE] state
-; CMP #BrElse,-2(IP) ; case of [ELSE] state was true
-; JZ BrThenNext ; to terminate with [THEN] state
-; ASMtoFORTH ; else abort
-; .word XSQUOTE
-; .byte 13,"[IF] missing!"
-; .word QABORTYES
-;
-;BrElseNext
-
-
-
-
-; ASMWORD ".ENDIF" ; fall here if [IF] without [ELSE] was true, or if [ELSE] was true
-;brTHEN JMP brELSE ;
-;BrThenNext SUB #2,&LEAVEPTR
-; MOV @RSP+,IP
-; mNEXT
-;
-;
-; ASMWORD ".IF"
-;BrIF mDOCOL
-;BrIf1 .word FBLANK,WORDD ; Z = EOL
-; FORTHtoASM
-; JZ SrchCndEol
-; ASMtoFORTH
-; .word FIND
-; .word ZEROEQUAL
-; .word QBRAN,SrchCOND1 ; -- c-addr if found
-; .word QNUMBER ;
-;SrchCOND1 FORTHtoASM ; -- xt|value|0
-; MOV @TOS,IP
-;cDOVAR CMP #DOVAR,IP
-; JNZ cDOCON
-; MOV 2(IP),TOS
-; MOV @TOS,TOS ; remplace CFA by value of VARIABLE
-; JMP SrchCOND2
-;cDOCON CMP #DOCON,IP
-; JNZ SrchBrIF
-; MOV 2(TOS),TOS ; remplace CFA by value for CONSTANT and CREATEd words
-;SrchBrIF CMP #BrIF,IP ; [IF] found ?
-; JNZ SrchBrELSE
-; ADD #2,&LEAVEPTR ; -- flag LEAVEPTR+2
-; MOV &LEAVEPTR,IP ;
-; CMP #0,TOS
-; JZ SrchBrIF1 ; to scan
-; MOV #BrIf,-2(IP) ; case of [IF] is true
-; MOV @RSP+,IP
-; mNEXT
-;SrchBrIF1 MOV #BrElse,-2(IP) ; case of [IF] is false
-; MOV #BrIf1,IP
-; mNEXT
-
-;SrchBrELSE CMP #BrELSE,IP ; [ELSE] found ?
-; JZ BrELSECond
-;SrchBrTHEN CMP #BrTHEN,IP ; [THEN] found ?
-; JZ BrTHENCond
-;SrchCOND2
-;
-;SrchCndEol FORTHtoASM
-; MOV @PSP+,TOS
-; MOV
-
-;SrchCOND3 JZ BrIF
-;
-; CMP #0,TOS
-; JZ SrchCOND3
-; .word QBRAN,SrchCOND4
-; .word BRAN,SrchCOND3
-;SrchCOND4 .word FTOIN,FETCH
; used variables : BufferPtr, BufferLen
; ----------------------------------;
-; FORTHWORD "SD_ACCEPT" ; TIB TIB len -- PAD|SDIB len'
+; FORTHWORD "SD_ACCEPT" ; TIB TIB TIB_LEN -- PAD|SDIB len'
; ----------------------------------;
SD_ACCEPT ; sequentially move from BUFFER to SDIB (or PAD) a line of chars delimited by CRLF
-; ----------------------------------;
+; ----------------------------------; up to TIB_LEN = 80 chars
PUSH IP ;
MOV #SDA_YEMIT_RET,IP ; set YEMIT return
; ----------------------------------;
StartNewLine ;
; ----------------------------------;
- MOV &CurrentHdl,T ; prepare link for any next LOAD"ed file...
+ MOV &CurrentHdl,T ; prepare a link for the next LOADed file...
MOV &BufferPtr,HDLW_BUFofst(T) ; ...see usage : HandleComplements
; ----------------------------------; -- TIB TIB len
.IFDEF RAM_1K ; use PAD as SD Input Buffer because the lack of RAM
MOV #PAD,W ; W=dst
- MOV #PAD_SIZE-4,0(PSP) ; -- TIB max_count len
.ELSEIF ; use SDIB as SD Input Buffer
MOV #SDIB,W ; W=dst
- MOV #SDIB_SIZE-4,0(PSP) ; -- TIB max_count len
.ENDIF
- MOV W,2(PSP) ; -- StringOrg' max_count len
- MOV #0,TOS ; -- StringOrg' max_count Count
+ MOV W,2(PSP) ; -- StringOrg' TIB TIB_LEN
+ MOV TOS,0(PSP) ; -- StringOrg' TIB_LEN TIB_LEN
+ MOV #0,TOS ; -- StringOrg' TIB_LEN Count
; ----------------------------------;
SDA_InitSrcAddr ; <== SDA_GetFileNextSector
; ----------------------------------;
CMP #0,&BufferLen ; test if input buffer is empty (EOF)
- JZ SDA_GoToInterpret ; yes
+ JZ SDA_GoToInterpret ; yes, to interpret an empty line (to do nothing)
MOV &BufferPtr,X ; X=src
JMP SDA_ComputeChar ;
; ----------------------------------;
ADD #1,X ; 1 increment input BufferPtr
CMP.B #32,Y ; 2 ascii printable char ?
JHS SDA_MoveChar ; 2 yes
- CMP.B #10,Y ; control char = 'LF' ?
- JNZ SDA_ComputeChar ; no
+ CMP.B #10,Y ; 2 control char = 'LF' ?
+ JNZ SDA_ComputeChar ; 2 no
; ----------------------------------;
SDA_EndOfLine ;
; ----------------------------------;
MOV X,&BufferPtr ; yes save BufferPtr for next line
; ----------------------------------;
-SDA_GoToInterpret ; -- StringOrg' max_count len'
+SDA_GoToInterpret ; -- StringOrg' TIB_LEN len'
; ----------------------------------;
ADD #2,PSP ; -- StringOrg' len'
MOV @RSP+,IP ;
; ----------------------------------;
SDA_MoveChar ;
; ----------------------------------;
- CMP TOS,0(PSP) ; 3 count = max_chars_count ?
+ CMP @PSP,TOS ; 2 count = TIB_LEN ?
JZ YEMIT ; 2 yes, don't move char to dst
MOV.B Y,0(W) ; 3 move char to dst
ADD #1,W ; 1 increment dst addr
ADD #1,TOS ; 1 increment count of moved chars
JMP YEMIT ; 9/6~ send echo to terminal if ECHO, do nothing if NOECHO
-; ----------------------------------; 33/30~ char loop, add 14~ for readsectorW ==> 47/44~ ==> 21/23 kbytes/s / MHz
-SDA_GetFileNextSector ;
+; ----------------------------------; 32/29~ char loop, add 14~ for readsectorW ==> 46/43~ ==> 174/186 kbytes/s @ 8MHz
+SDA_GetFileNextSector ; StringOrg' TIB_LEN Count --
; ----------------------------------;
PUSH W ; save dst
CALL #Read_File ; that resets BufferPtr
; ----------------------------------;
-;C ACCEPT addr addr len -- addr' len' get line at addr to interpret len' chars
- FORTHWORD "ACCEPT"
-ACCEPT MOV #PARENACCEPT,PC
-
-;C (ACCEPT) addr addr len -- addr len' get len' (up to len) chars from terminal (TERATERM.EXE) via USBtoUART bridge
- FORTHWORD "(ACCEPT)"
-PARENACCEPT
-
BIC.B #00Eh,&P1REN ; disable pullup resistors for SIMO/SOMI/SCK pins
.ENDIF
+ .IFDEF MY_MSP430FR5738
+
+; COLD default state : Px{DIR,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; PX{OUT,REN} = 1 ; Px{IN,IES} = ?
+
+; P2.3 as SD_CD
+SD_CD .equ 08h
+SD_CDIN .equ P2IN
+; P2.4 as SD_CS
+SD_CS .equ 10h
+SD_CSOUT .equ P2OUT
+ BIS.B #SD_CS,&P2DIR ; SD_CS output high
+
+; P2.2/UCB0CLK ---> SD_CardAdapter CLK (SCK) default value
+; P1.6/UCB0SIMO/UCB0SDA/TA0.0 ---> SD_CardAdapter SDI (MOSI) default value
+; P1.7/UCB0SOMI/UCB0SCL/TA1.0 <--- SD_CardAdapter SDO (MISO) default value
+ BIS #04C0h,&PASEL1 ; Configure UCB0 pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0SOMI
+ ; P2DIR.x is controlled by eUSCI_B0 module
+ BIC #04C0h,&PAREN ; disable pullup resistors for SIMO/SOMI/CLK pins
+
+ .ENDIF
+ .IFDEF MY_MSP430FR5738_1
+
+; COLD default state : Px{DIR,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; PX{OUT,REN} = 1 ; Px{IN,IES} = ?
+
+; P2.3 as SD_CD
+SD_CD .equ 08h
+SD_CDIN .equ P2IN
+; P2.4 as SD_CS
+SD_CS .equ 10h
+SD_CSOUT .equ P2OUT
+ BIS.B #SD_CS,&P2DIR ; SD_CS output high
+
+; P2.2/UCB0CLK ---> SD_CardAdapter CLK (SCK) default value
+; P1.6/UCB0SIMO/UCB0SDA/TA0.0 ---> SD_CardAdapter SDI (MOSI) default value
+; P1.7/UCB0SOMI/UCB0SCL/TA1.0 <--- SD_CardAdapter SDO (MISO) default value
+ BIS #04C0h,&PASEL1 ; Configure UCB0 pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0SOMI
+ ; P2DIR.x is controlled by eUSCI_B0 module
+ BIC #04C0h,&PAREN ; disable pullup resistors for SIMO/SOMI/CLK pins
+
+ .ENDIF
+ .IFDEF MY_MSP430FR5948
+
+; COLD default state : Px{DIR,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; PX{OUT,REN} = 1 ; Px{IN,IES} = ?
+
+; P2.3 <--- SD_CD (Card Detect)
+SD_CD .equ 08h
+SD_CDIN .equ P2IN
+; P2.7 ---> SD_CS (Card Select)
+SD_CS .equ 80h
+SD_CSOUT .equ P2OUT
+ BIS.B #SD_CS,&P2DIR ; SD_CS output high
+
+; P2.4 UCA1 CLK ---> SD_CLK
+; P2.5 UCA1 TX/SIMO ---> SD_SDI
+; P2.6 UCA1 RX/SOMI <--- SD_SDO
+ BIS.B #070h,&P2SEL1 ; Configure UCA1 pins P2.4 as UCA1CLK, P2.5 as UCA1SIMO & P2.6 as UCA1SOMI
+ ; P2DIR.x is controlled by eUSCI_A0 module
+ BIC.B #070h,&P2REN ; disable pullup resistors for SIMO/SOMI/SCK pins
+
+ .ENDIF
+ .IFDEF MY_MSP430FR5948_1 ; = new version of MY_MSP430FR5948
+
+; COLD default state : Px{DIR,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; PX{OUT,REN} = 1 ; Px{IN,IES} = ?
+
+; P2.7 ---> SD_CD (Card Detect)
+SD_CD .equ 80h
+SD_CDIN .equ P2IN
+; P2.3 <--- SD_CS (Card Select)
+SD_CS .equ 08h
+SD_CSOUT .equ P2OUT
+ BIS.B #SD_CS,&P2DIR ; SD_CS output high
+
+; P2.4 UCA1 CLK ---> SD_CLK
+; P2.5 UCA1 TX/SIMO ---> SD_SDI
+; P2.6 UCA1 RX/SOMI <--- SD_SDO
+ BIS.B #070h,&P2SEL1 ; Configure UCA1 pins P2.4 as UCA1CLK, P2.5 as UCA1SIMO & P2.6 as UCA1SOMI
+ ; P2DIR.x is controlled by eUSCI_A0 module
+ BIC.B #070h,&P2REN ; disable pullup resistors for SIMO/SOMI/SCK pins
+
+ .ENDIF
BIC #1,&SD_CTLW0 ; release eUSCI from reset
; along with this program. If not, see <http://www.gnu.org/licenses/>.
+ FORTHWORD "{SD_LOAD}" ; SD_LOAD words mark
+ mNEXT
+
;-----------------------------------------------------------------------
; SD card OPEN, LOAD subroutines
;-----------------------------------------------------------------------
MOV #MOVEDOWN,PC ;
-
; rules for registers use
; S = error
; T = CurrentHdl, pathname
MOV.B &ClusterL+1,W ;3 W = ClusterLoHI
MOV.B &ClusterL,Y ;3 Y = ClusterLoLo
CMP #2,&FATtype ;3 FAT32?
- JZ ClusterToFAT32sector ;2 yes
- ADD Y,Y ;1 Y = ClusterLoLo << 1
- RET
-
+ JNZ CTF1S_end ;2 no
+; JZ ClusterToFAT32sector ;2 yes
+; ADD Y,Y ;1 Y = ClusterLoLo << 1
+; RET
; input : Cluster n, max = 7FFFFF ==> SDcard up to 256 GB
; ClusterLoLo*4 = displacement in 512 bytes sector ==> FAToffset
ADD X,W ; W = ClusterHiLo:ClusterLoHi
; ----------------------------------;
SWPB Y ; Y = ClusterLoLo:0
- ADD Y,Y ;1 Y = ClusterLoLo:0 * 2 + carry for FATsector
- ADDC W,W ; W = ClusterHiLo:ClusterLoHi * 2 = ClusterHiLo:ClusterL / 128
+ ADD Y,Y ;1 Y = ClusterLoLo:0 << 1 + carry for FATsector
+ ADDC W,W ; W = ClusterHiLo:ClusterLoHi << 1 = ClusterHiLo:ClusterL / 128
SWPB Y
- ADD Y,Y ; Y = 0:ClusterLoLo * 4
+CTF1S_end
+ ADD Y,Y ; Y = 0:ClusterLoLo << 1
RET ;4
; ----------------------------------;
; ----------------------------------;
FirstLoadFileHandle ;
; ----------------------------------;
- MOV &SOURCE_LEN,&SAVEtsLEN ;
- SUB &TOIN,&SAVEtsLEN ; save remaining lenght
- MOV &SOURCE_ADR,&SAVEtsPTR ;
- ADD &TOIN,&SAVEtsPTR ; save new input org address
+ MOV &TOIN,X ;3
+ MOV &SOURCE_LEN,W ;3
+ SUB X,W ;1
+ MOV W,&SAVEtsLEN ;3 save remaining lenght
+ ADD &SOURCE_ADR,X ;3
+ MOV X,&SAVEtsPTR ;3 save new input org address
MOV #SD_ACCEPT,&ACCEPT+2 ; redirect ACCEPT to SD_ACCEPT
- MOV &SOURCE_LEN,&TOIN ; to quit interpret (same as BACKSLASH)
JMP SetBufLenAndLoadCurSector ;
-;; ----------------------------------;
-;FirstLoadFileHandle ;
-;; ----------------------------------;
-; SUB &TOIN,&SOURCE_LEN ;
-; ADD &TOIN,&SOURCE_ADR ;
-; MOV #SD_ACCEPT,&ACCEPT+2 ; redirect ACCEPT to SD_ACCEPT
-; MOV &SOURCE_LEN,&TOIN ; to quit interpret (same as BACKSLASH)
-; JMP SetBufLenAndLoadCurSector ;
; ----------------------------------;
-
; If closed token = -1, restore DefaultInputStream
; if closed token < -1, restore previous context
; ==================================;
CheckCaseOfClosedLoadedFile ;
; ----------------------------------;
ADD.B #1,W ;
- JZ LastFileLoadClosed ; W=0, this closed LOADed file had not a paren
+ JZ CloseFirstLoadedFile ; W=0, this closed LOADed file had not a paren
JGE InitHandleRET ; W>0, for READ, WRITE, DEL files
; ----------------------------------;
RestorePreviousLoadedFileContext ; W<0, this closed LOADed file had a paren
MOV HDLW_BUFofst(T),&BufferPtr ; restore BufferPtr saved by SD_ACCEPT before interpreting LOAD cmd line
JMP SetBufLenAndLoadCurSector ;
; ----------------------------------;
-LastFileLoadClosed ;
+CloseFirstLoadedFile ;
; ----------------------------------;
-RestoreDefaultInputStream ; it was the first LOADed filre
MOV &SAVEtsLEN,TOS ; restore lenght
MOV &SAVEtsPTR,2(PSP) ; restore pointer for interpret
MOV #PARENACCEPT,&ACCEPT+2 ; restore (ACCEPT)
- JMP InitHandleRET ; RET
-; ----------------------------------;
-;RestoreDefaultInputStream ; it was the first LOADed filre
-; MOV &SOURCE_LEN,TOS ; restore lenght
-; MOV &SOURCE_ADR,2(PSP) ; restore pointer for interpret
-; MOV #0,&TOIN ; reset interpret ptr
-; MOV #PARENACCEPT,&ACCEPT+2 ; restore (ACCEPT)
-; JMP InitHandleRET ; RET
+ RET ; RET
; ----------------------------------;
OPEN_COMP ;
mDOCOL ; if compile state
.word lit,lit,COMMA,COMMA ; compile open_type as literal
+ .IFDEF LOWERCASE
+ .word CAPS_ON
+ .ENDIF
.word SQUOTE ; compile string_exec + string
.word lit,SQUOTE2HERE,COMMA ; compile move in-line string to a counted string at HERE
.word lit,ParenOpen,COMMA ; compile (OPEN)
; ----------------------------------;
ParenOpen ; open_type HERE --
; ----------------------------------;
- SUB #2,PSP ; make room for DIRsector
+; SUB #2,PSP ; make room for DIRsector
; ----------------------------------;
OPN_CountedToStringZ ;
; ----------------------------------;
; ----------------------------------;
MOV TOS,&Pathname ; save name addr
CALL #ComputeClusFrstSect ; output: SectorHL
- MOV #32,0(PSP) ; preset countdown for FAT16 RootDIR sectors
+; MOV #32,0(PSP) ; preset countdown for FAT16 RootDIR sectors
+ MOV #32,rDODOES ; preset countdown for FAT16 RootDIR sectors
CMP #2,&FATtype ; FAT32?
JZ OPN_SetDirSectors ; yes
CMP &ClusterL,&FATtype ; FAT16 AND RootDIR ?
JZ OPN_LoadSectorDir ; yes
OPN_SetDirSectors ;
- MOV &SecPerClus,0(PSP) ;
+; MOV &SecPerClus,0(PSP) ;
+ MOV &SecPerClus,rDODOES ;
; ----------------------------------;
OPN_LoadSectorDir ; <=== Dir Sector loopback
; ----------------------------------;
; ----------------------------------;
ADD #1,&SectorL ;
ADDC #0,&SectorH ;
- SUB #1,0(PSP) ; dec count of Dir sectors
+; SUB #1,0(PSP) ; dec count of Dir sectors
+ SUB #1,rDODOES ; dec count of Dir sectors
JNZ OPN_LoadSectorDir ; ===> loopback for next DIR sector
; ----------------------------------;
MOV #4,S ;
; ----------------------------------;
MOV &ClusterL,&DIRClusterL ;
MOV &ClusterH,&DIRclusterH ;
- ADD #4,PSP ; -- ptr
- MOV @PSP+,TOS ; --
- MOV @RSP+,IP ;
- mNEXT ; happy end
+; MOV #THREEDROP,PC ; 3drop
+ MOV #0,0(PSP)
+ JMP OPN_Dir
; ----------------------------------;
OPN_FileFound ; -- open_type DIRsector ptr
; ----------------------------------;
- MOV 2(PSP),W
+; MOV 2(PSP),W ;
+ MOV @PSP,W ;
CALL #GetFreeHandle ;STWXY init handle(HDLL_DIRsect,HDLW_DIRofst,HDLL_FirstClus = HDLL_CurClust,HDLL_CurSize)
; ----------------------------------; output : T = CurrentHdl*, S = ReturnError, Y = DIRentry offset
OPN_NomoreHandle ; S = error 16
OPN_EndOfDIR ; S = error 4
OPN_NoSuchFile ; S = error 2
OPN_NoPathName ; S = error 1
- ADD #2,PSP ; -- open_type ptr
+OPN_Dir
+; ADD #2,PSP ; -- open_type ptr
MOV @PSP+,W ; -- ptr W = open_type
+ MOV #xdodoes,rDODOES ; -- open_type ptr
MOV @PSP+,TOS ; --
; ----------------------------------; then go to selected OpenType subroutine (OpenType = W register)
; ======================================================================
; ----------------------------------;
+OPEN_QDIR ;
+; ----------------------------------;
+ CMP #0,W ;
+ JZ OPEN_LOAD_END ; nothing to do
+; ----------------------------------;
+OPEN_QLOAD ;
+; ----------------------------------;
.IFDEF SD_CARD_READ_WRITE ;
CMP.B #-1,W ; open_type = LOAD"
JNZ OPEN_QREAD ; next step
; ----------------------------------;
CMP #0,S ; open file happy end ?
JNZ OPEN_Error ; no
+ MOV #INTLOOP,IP ; return to sender (QUIT) to get new line.
+OPEN_LOAD_END
mNEXT ;
; ----------------------------------;
-
-
; ----------------------------------;
OPEN_Error ; S= error
; ----------------------------------;
; Formatage FA16 d'une SDSC Card 2GB
; First sector of physical drive (sector 0) content :
; ---------------------------------------------------
-; dec@| HEX@ = HEX decimal
-; 446 |0x1BE : partition table first record ==> logical drive 0
-; 446 |0x1CE : partition table 2th record ==> logical drive 1
-; 446 |0x1DE : partition table 3th record ==> logical drive 2
-; 446 |0x1EE : partition table 4th record ==> logical drive 3
+; dec@| HEX@
+; 446 |0x1BE : partition table first record ==> logical drive 0
+; 446 |0x1CE : partition table 2th record ==> logical drive 1
+; 446 |0x1DE : partition table 3th record ==> logical drive 2
+; 446 |0x1EE : partition table 4th record ==> logical drive 3
; partition record content :
; ---------------------------------------------------
-; dec@|HEX@ = HEX decimal
+; dec@|HEX@ = HEX decimal
; 0 |0x00 = 0x00 : not bootable
; 1 |0x01 = 02 0C 00 : Org Cylinder/Head/Sector offset (CHS-addressing) = not used
; 4 |0x04 = 0x0E : type FAT16 using LBA addressing = 14 ==> FAT16
; 5 |0x05 = ED 3F EE : End Cylinder/Head/Sector offset (CHS-addressing) = not used
-; 8 |0x08 = 00 20 00 00 : sector offset of logical drive = 8192
-; 12 |0x0C = 00 40 74 00 : sector size of logical drive = 7618560 sectors
+; 8 |0x08 = 00 20 00 00 : sectors offset of logical drive = 8192
+; 12 |0x0C = 00 40 74 00 : sectors size of logical drive = 7618560 sectors
; 450 |0x04 = 0x0E : type FAT16 using LBA addressing = 14 ==> set FATtype = FAT16 with byte CMD addressing
; 454 |0x1C6 = 89 00 : FirstSector (of logical drive 0) BS_FirstSector = 137
; FirstSector of logical drive (sector 0) content :
; -------------------------------------------------
-; dec@| HEX@ = HEX decimal
+; dec@| HEX@ = HEX decimal
; 11 | 0x0B = 00 02 : 512 bytes/sector BPB_BytsPerSec = 512
; 13 | 0x0D = 40 : 64 sectors/cluster BPB_SecPerClus = 64
; 14 | 0x0E = 01 00 : 2 reserved sectors BPB_RsvdSecCnt = 1
; Formatage FA32 d'une SDSC Card 8GB
; First sector of physical drive (sector 0) content :
; ---------------------------------------------------
-; dec@| HEX@ = HEX decimal
-; 446 |0x1BE : partition table first record ==> logical block 0
-; 446 |0x1CE : partition table 2th record ==> logical block 1
-; 446 |0x1DE : partition table 3th record ==> logical block 2
-; 446 |0x1EE : partition table 4th record ==> logical block 3
+; dec@| HEX@
+; 446 |0x1BE : partition table first record ==> logical block 0
+; 446 |0x1CE : partition table 2th record ==> logical block 1
+; 446 |0x1DE : partition table 3th record ==> logical block 2
+; 446 |0x1EE : partition table 4th record ==> logical block 3
; partition record content :
; ---------------------------------------------------
; 1 |0x01 = 82 03 00 : Org CHS offset (Cylinder/Head/Sector) = not used
; 4 |0x04 = 0x0C : type FAT32 using LBA addressing = 12 ==> set FATtype = FAT32 with sector CMD addressing
; 5 |0x05 = 82 03 00 : End offset (Cylinder/Head/Sector offset) = not used
-; 8 |0x08 = 00 20 00 00 : sector offset of logical block = 8192
-; 12 |0x0C = 00 40 74 00 : sector size of logical block = 7618560
+; 8 |0x08 = 00 20 00 00 : sectors offset of logical block = 8192
+; 12 |0x0C = 00 40 74 00 : sectors size of logical block = 7618560
; 454 |0x1C6 = 00 20 00 00 : FirstSector (of logical drive 0) = BS_FirstSector = 8192
;
; FirstSector of logical block (sector 0) content :
; -------------------------------------------------
-; dec@| HEX@ = HEX decimal
+; dec@| HEX@ = HEX decimal
; 11 | 0x0B = 00 02 : 512 bytes/sector BPB_BytsPerSec = 512
; 13 | 0x0D = 08 : 8 sectors/cluster BPB_SecPerClus = 8
; 14 | 0x0E = 20 00 : 32 reserved sectors BPB_RsvdSecCnt = 32
; ==================================;
RW_Sector_CMD ;WX <=== CMD17 or CMD24 (read or write Sector CMD)
; ==================================;
- BIC.B #SD_CS,&SD_CSOUT ; SD_CS low
- BIT.B #SD_CD,&SD_CDIN ; memory card present ?
+ BIC.B #SD_CS,&SD_CSOUT ; set SD_CS low
+ BIT.B #SD_CD,&SD_CDIN ; test CD: memory card present ?
JZ ComputePhysicalSector ; yes
MOV #COLD,PC ; no: force COLD
; ----------------------------------;
-ComputePhysicalSector ; input = logical sector, output = physical sector
-; ----------------------------------;
+ComputePhysicalSector ;
+; ----------------------------------; input = logical sector...
ADD &BS_FirstSectorL,W ;3
ADDC &BS_FirstSectorH,X ;3
+; ----------------------------------; ...output = physical sector
+;Compute CMD ;
; ----------------------------------;
- MOV #1,&SD_CMD_FRM ;3 $(01 00 xx xx xx CMD) (set stop bit)
+ MOV #1,&SD_CMD_FRM ;3 $(01 00 xx xx xx CMD) set stop bit in CMD frame
CMP #2,&FATtype ;3 FAT32 ?
JZ FAT32_CMD ;2 yes
FAT16_CMD ; FAT16 : CMD17/24 byte address = Sector * BPB_BytsPerSec
SWPB X ;1
MOV.B X,&SD_CMD_FRM+4 ;3 $(01 ll LL hh HH CMD)
; ==================================;
-WaitIdleBeforeSendCMD ; <=== CMD41, CMD1, CMD16 (R1 expected response = 0 = ready)
+WaitIdleBeforeSendCMD ; <=== CMD41, CMD1, CMD16 (forthMSP430FR_SD_INIT.asm)
; ==================================;
CALL #SPI_GET ;
- CMP.B #-1,W ; FFh expected value <==> MISO = 1 = not busy = idle state
+ CMP.B #-1,W ; FFh = expected value <==> MISO = 1 = not busy = idle state
JNE WaitIdleBeforeSendCMD ; loop back until idle state
- MOV #0,W ; W = expected R1 response = ready = 0 for CMD41,CMD16, CMD17, CMD24
+ MOV #0,W ; W = expected R1 response = ready, for CMD41,CMD16, CMD17, CMD24
; ==================================;
-sendCommand ;X <=== CMD0, CMD8, CMD55 (W = R1 expected response = 1 = idle)
+sendCommand ;X <=== CMD0, CMD8, CMD55: W = R1 expected response = idle (forthMSP430FR_SD_INIT.asm)
; ==================================;
; input : SD_CMD_FRM : {CRC,byte_l,byte_L,byte_h,byte_H,CMD}
; W = expected return value
; output W is unchanged, flag Z is positionned
; reverts CMD bytes before send : $(CMD hh LL ll 00 CRC)
- MOV #5,X ; X = SD_CMD_FRM index AND countdown
+ MOV #5,X ; X = SD_CMD_FRM ptr AND countdown
; ----------------------------------;
Send_CMD_PUT ; performs little endian --> big endian conversion
; ----------------------------------;
MOV.B SD_CMD_FRM(X),&SD_TXBUF ;5
CMP #0,&SD_BRW ;3 full speed ?
JZ FullSpeedSend ;2 yes
-Send_CMD_Loop ; no: case of low speed during memCardInit
- BIT #UCRXIFG,&SD_IFG ;3
+Send_CMD_Loop ;
+ BIT #UCRXIFG,&SD_IFG ;3 no: case of low speed during memCardInit
JZ Send_CMD_Loop ;2
CMP.B #0,&SD_RXBUF ;3 to clear UCRXIFG
FullSpeedSend ;
; MOV #32,X ; to pass Panasonic SD_Card init
; MOV #64,X ; to pass SanDisk SD_Card init
; ----------------------------------;
-Wait_Command_Response ; expect W = return value during X = 255 time
+Wait_Command_Response ; expect W = return value during X = 255 times
; ----------------------------------;
SUB #1,X ;1
- JN SPI_WAIT_RET ;2 error on time out with SR(Z) = 0
+ JN SPI_WAIT_RET ;2 error on time out with flag Z = 0
MOV.B #-1,&SD_TXBUF ;3 PUT FFh
CMP #0,&SD_BRW ;3 full speed ?
JZ FullSpeedGET ;2 yes
BIT #UCRXIFG,&SD_IFG ;3
JZ cardResp_Getloop ;2
FullSpeedGET ;
-; NOP2 ; NOPx adjusted to avoid SD_error
+; NOP ; NOPx adjusted to avoid SD_error
CMP.B &SD_RXBUF,W ;3 return value = ExpectedValue ?
- JNZ Wait_Command_Response ;2 18~ full speed loop
-SPI_WAIT_RET ; SR(Z) = 1 <==> Return value = expected value
+ JNZ Wait_Command_Response ;2 16~ full speed loop
+SPI_WAIT_RET ; flag Z = 1 <==> Returned value = expected value
RET ; W = expected value, unchanged
; ----------------------------------;
; ==================================; output : W = received byte, X = 0 always
MOV #1,X ;1
; ==================================;
-SPI_X_GET ; PUT(FFh) X time
+SPI_X_GET ; PUT(FFh) X times
; ==================================; output : W = last received byte, X = 0
MOV #-1,W ;1
; ==================================;
SPI_PUT ; PUT(W) X time
; ==================================; output : W = last received byte, X = 0
SWPB W ;1
- MOV.B W,&SD_TXBUF ;3 put W high byte then W low byte and so forth that performs little to big endian conversion
+ MOV.B W,&SD_TXBUF ;3 put W high byte then W low byte and so forth, that performs little to big endian conversion
CMP #0,&SD_BRW ;3 full speed ?
JZ FullSpeedPut ;2
SPI_PUTWAIT BIT #UCRXIFG,&SD_IFG ;3
FullSpeedPut
; NOP ; NOPx adjusted to avoid SD error
SUB #1,X ;1
- JNZ SPI_PUT ;2
+ JNZ SPI_PUT ;2 12~ loop
SPI_PUT_END MOV.B &SD_RXBUF,W ;3
RET ;4
; ----------------------------------;
; ==================================;
BIS #1,S ; preset sd_read error
MOV.B #51h,&SD_CMD_FRM+5 ; CMD17 = READ_SINGLE_BLOCK
- CALL #RW_Sector_CMD ; which performs logical sector to physical sector then little endian to big endian conversions
+ CALL #RW_Sector_CMD ; which performs logical sector to physical sector then little endian to big endian conversion
JNE SD_CARD_ERROR ; time out error if R1 <> 0
; ----------------------------------;
WaitFEhResponse ; wait SD_Card response FEh
; ----------------------------------;
; 2.1- Compute Sectors count ; Sectors = HDLL_CurSize/512
; ----------------------------------;
- MOV.B HDLL_CurSize+1(T),Y ; Y = 0:CurSizeLoHi
- MOV.B HDLH_CurSize(T),S ; S = 0:CurSizeHiLo
- SWPB S ; S = CurSizeHiLo:0
- ADD Y,S ; S = CurSizeHiLo:CurSizeLoHi
- MOV.B HDLH_CurSize+1(T),W ; W:S = CurSize / 256
- RRA W ; W = Sectors number_High
- RRC S ; S = Sectors number_Low
-; ----------------------------------;
-; 2.2- Compute Buffer offset ; tested with 4100 bytes and SecPerClus=8
-; ----------------------------------;
- MOV HDLL_CurSize(T),Y ; Y = 1004
- BIC #01FFh,HDLL_CurSize(T) ; substract 4 from HDLL_CurSize
- AND #01FFh,Y ; Y = 4
- MOV Y,&BufferPtr ; init Buffer Pointer with 4
-; ----------------------------------;
-ComputeClustersCount ; with W:S / T ==> quotient = Y:X, remainder = W
-; ----------------------------------;
- MOV.B &SecPerClus,T ;3 T = DIVISOR = SecPerClus
- CALL #UDIVQ32 ; unsigned division 32/16 ==> Q32,R16 i.e. W:S/T ==> Y:X,W use S,T,W,X,Y
- MOV &CurrentHDL,T ;
-; ----------------------------------;
-; 2.3- Compute Cluster offset ;
-; ----------------------------------;
- MOV.B W,HDLB_ClustOfst(T) ;3 update handle with W = R16 (remainder) = sectors offset in cluster
-; ----------------------------------;
-; 2.4- Compute last Cluster ; X = Q32lo = Clusters numberLO, Y = Q32hi = Clusters numberHI
+ MOV.B HDLL_CurSize+1(T),Y ;Y = 0:CurSizeLOHi
+ MOV.B HDLH_CurSize(T),X ;X = 0:CurSizeHILo
+ SWPB X ;X = CurSizeHIlo:0
+ ADD Y,X ;X = CurSizeHIlo:CurSizeLOhi
+ MOV.B HDLH_CurSize+1(T),Y ;Y:X = CurSize / 256
+; RRA Y ;Y = Sectors number_High
+; RRC X ;X = Sectors number_Low
+; ----------------------------------;
+; 2.2 Compute Clusters Count ;
+; ----------------------------------;
+ MOV.B &SecPerClus,T ;3 T = DIVISOR = SecPerClus = 0:SPClo
+DIVSECPERSPC ;
+ MOV #0,W ;1 W = 0:REMlo = 0
+ MOV #8,S ;1 S = CNT
+; RRA T ;1 0>0:SPClo>C preshift one right DIVISOR
+DIVSECPERSPC1 ;
+ RRA Y ;1 0>0:SEC_HI>C
+ RRC X ;1 C>SEC_LO>C
+ RRC.B W ;1 C>REMlo>C
+ SUB #1,S ;1 CNT-1
+ RRA T ;1 0>SPChi:SPClo>C
+ JNC DIVSECPERSPC1 ;2 7~ loopback if carry clear
+DIVSECPERSPC2 ;
+ RRA W ;1 0>0:REMlo>C
+ SUB #1,S ;1 CNT-1
+; JNZ DIVSECPERSPC2 ;2 4~ loopback Wlo = OFFSET, X = CLU_LO, Y = CLU_HI
+ JGE DIVSECPERSPC2 ;2 4~ loopback Wlo = OFFSET, X = CLU_LO, Y = CLU_HI
+; ----------------------------------;
+ MOV &CurrentHDL,T ;3 reload Handle ptr
+; ----------------------------------;
+; 2.3- Compute last Cluster ; X = Clusters numberLO, Y = Clusters numberHI
; ----------------------------------;
ADD HDLL_FirstClus(T),X ;
ADDC HDLH_FirstClus(T),Y ;
MOV X,HDLL_CurClust(T) ; update handle
MOV Y,HDLH_CurClust(T) ;
; ----------------------------------;
+; 2.4- Compute Sectors offset ;
+; ----------------------------------;
+ MOV.B W,HDLB_ClustOfst(T) ;3 update handle with W = REMlo = sectors offset in last cluster
+; ----------------------------------;
; 3- load last sector in BUFFER ;
; ----------------------------------;
+ MOV HDLL_CurSize(T),W ; example : W = 1013
+ BIC #01FFh,HDLL_CurSize(T) ; substract 13 from HDLL_CurSize, because loaded in buffer
+ AND #01FFh,W ; W = 13
+ MOV W,&BufferPtr ; init Buffer Pointer with 13
CALL #LoadHDLcurrentSector ;SWX
- mNEXT ; --
-; ----------------------------------; BufferPtr leaves first free byte offset
+ mNEXT ; BufferPtr = first free byte offset
+; ----------------------------------;
; ======================================================================
MOV.B X,BUFFER(Y) ;3
ADD #1,Y ;1
CMP #BytsPerSec-1,Y ;2
- JZ T2S_XOFF ;2 Y=511 send XOFF after RX 511th char
JLO T2S_FillBufferLoop ;2 Y<511 21 cycles char loop
+ JZ T2S_XOFF ;2 Y=511 send XOFF after RX 511th char
; ----------------------------------;
T2S_WriteFile ;2 Y>511
; ----------------------------------;
FAST FORTH have one pass assembler, not able to make forward jump.
-In my (well written) apps I have never used forward jumps.
-
-But I have added possibility of several "non canonical" jumps, up to 3 backward and up to 3 forward imbricated jumps to label :
+I have added possibility of several "non canonical" jumps, up to 3 backward and up to 3 forward imbricated jumps to label :
\ C UM/MOD udlo|udhi u1 -- ur uq
CODE UM/MOD
example : RRUM #3,R9 \ R9 register is Unsigned Right shifted by n=3
error occurs if 1 > n > 4
+
+
+conditionnal jumps use with symbolic assembler
+
+ 0= { IF UNTIL WHILE ?JMP ?GOTO }
+ 0<> { IF UNTIL WHILE ?JMP ?GOTO }
+ U>= { IF UNTIL WHILE ?JMP ?GOTO }
+ U< { IF UNTIL WHILE ?JMP ?GOTO }
+ S< { IF UNTIL WHILE ?JMP ?GOTO }
+ S>= { IF UNTIL WHILE ?JMP ?GOTO }
+ 0>= { IF UNTIL WHILE }
+ 0< { ?JMP ?GOTO }
+
OSCOFF equ 0020h
SCG0 equ 0040h
SCG1 equ 0080h
-UF1 equ 0200h ; = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
-UF2 equ 0400h ; = SR(10) User Flag 2
-UF3 equ 0800h ; = SR(11) User Flag 3
+UF9 equ 0200h ; = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
+UF10 equ 0400h ; = SR(10) User Flag 2
+UF11 equ 0800h ; = SR(11) User Flag 3
;----------------------------------------------------------------------------
; Low-Power-Mode Bitmuster
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