FORTHWORD "{CORE_ANS}"
MOV @IP+,PC
+ FORTHWORD "ABORT"
+ MOV #ABORT,PC
+
+ FORTHWORD "QUIT"
+ MOV #QUIT,PC
+
;-------------------------------------------------------------------------------
; COMPARAISON OPERATIONS
;-------------------------------------------------------------------------------
FORTHWORD "0<"
; https://forth-standard.org/standard/core/Zeroless
; 0< n -- flag true if TOS negative
- ADD TOS,TOS ;1 set carry if TOS negative
+ZLESS ADD TOS,TOS ;1 set carry if TOS negative
SUBC TOS,TOS ;1 TOS=-1 if carry was clear
EQUALTRUE XOR #-1,TOS ;1 TOS=-1 if carry was set
MOV @IP+,PC ;
JL TOSFALSE ;2 signed jump
TOSTRUE MOV #-1,TOS ;1 flag Z = 0
LESSEND MOV @IP+,PC ;4
- .ENDIF
FORTHWORD ">"
;https://forth-standard.org/standard/core/more
TOSFALSE AND #0,TOS ;1 flag Z = 1
MOV @IP+,PC ;4
+ .ENDIF
.IFNDEF ULESS
; https://forth-standard.org/standard/core/Uless
; U< u1 u2 -- flag test u1<u2, unsigned
JNC UTOSTRUE ; 2 flag = true, Z = 0
UTOSFALSE AND #0,TOS ;1 flag Z = 1
MOV @IP+,PC ;4
- .ENDIF
+ .ENDIF
;-------------------------------------------------------------------------------
; STACK OPERATIONS
;-------------------------------------------------------------------------------
; ?DUP x -- 0 | x x DUP if nonzero
FORTHWORD "?DUP"
QDUP CMP #0,TOS
- JZ QDUPEND
JNZ QDUPNEXT
- .ENDIF
+ JZ QDUPEND
+ .ENDIF
; https://forth-standard.org/standard/core/SWAP
; SWAP x1 x2 -- x2 x1 swap top two items
FORTHWORD "SWAP"
FORTHWORD "DROP"
; https://forth-standard.org/standard/core/DROP
; DROP x -- drop top of stack
- MOV @PSP+,TOS ; 2
+DROP1 MOV @PSP+,TOS ; 2
MOV @IP+,PC ; 4
.IFNDEF OVER
MOV @PSP,TOS ; 2 -- x1 (x2) x1
SUB #2,PSP ; 1 -- x1 x2 x1
MOV @IP+,PC ; 4
- .ENDIF
+ .ENDIF
FORTHWORD "NIP"
; https://forth-standard.org/standard/core/NIP
; NIP x1 x2 -- x2 Drop the first item below the top of stack
- ADD #2,PSP ; 1
+NIP1 ADD #2,PSP ; 1
MOV @IP+,PC ; 4
FORTHWORD "ROT"
;https://forth-standard.org/standard/core/ROT
;C ROT x1 x2 x3 -- x2 x3 x1
- MOV @PSP,W ; 2 fetch x2
+ROT MOV @PSP,W ; 2 fetch x2
MOV TOS,0(PSP) ; 3 store x3
MOV 2(PSP),TOS ; 3 fetch x1
MOV W,2(PSP) ; 3 store x2
; https://forth-standard.org/standard/core/Rfrom
; R> -- x R: x -- pop from return stack
FORTHWORD "R>"
- SUB #2,PSP ; 1
+RFROM1 SUB #2,PSP ; 1
MOV TOS,0(PSP) ; 3
MOV @RSP+,TOS ; 2
MOV @IP+,PC ; 4
TOR PUSH TOS
MOV @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
; https://forth-standard.org/standard/core/TUCK
; TUCK ( x1 x2 -- x2 x1 x2 )
FORTHWORD "TUCK"
; https://forth-standard.org/standard/core/DEPTH
; DEPTH -- +n number of items on stack, must leave 0 if stack empty
FORTHWORD "DEPTH"
- MOV #DEPTH,PC
+ MOV TOS,-2(PSP)
+ MOV #PSTACK,TOS
+ SUB PSP,TOS ; PSP-S0--> TOS
+ RRA TOS ; TOS/2 --> TOS
+ SUB #2,PSP ; post decrement stack...
+ MOV @IP+,PC
;-------------------------------------------------------------------------------
; RETURN from high level word
MOV @RSP+,IP ;
SPACESNEXT2 MOV @PSP+,TOS ; -- drop n
MOV @IP+,PC ;
- .ENDIF
+ .ENDIF
.IFNDEF CR
FORTHWORD "CR"
; https://forth-standard.org/standard/core/CR
.word LIT,0Dh,EMIT
.word LIT,0Ah,EMIT
.word EXIT
- .ENDIF
+ .ENDIF
;-------------------------------------------------------------------------------
; ARITHMETIC OPERATIONS
;-------------------------------------------------------------------------------
+
.IFNDEF ANDD
;https://forth-standard.org/standard/core/AND
;C AND x1 x2 -- x3 logical AND
FORTHWORD "AND"
ANDD AND @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
;https://forth-standard.org/standard/core/OR
;C OR x1 x2 -- x3 logical OR
FORTHWORD "OR"
JL SELn2 ; n2<n1
SELn1 MOV @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
FORTHWORD "1+"
; https://forth-standard.org/standard/core/OnePlus
; 1+ n1/u1 -- n2/u2 add 1 to TOS
FORTHWORD "1-"
; https://forth-standard.org/standard/core/OneMinus
; 1- n1/u1 -- n2/u2 subtract 1 from TOS
- SUB #1,TOS
+ONEMINUS1 SUB #1,TOS
MOV @IP+,PC
FORTHWORD "+"
MOV @IP+,PC
.IFDEF MPY
-
;https://forth-standard.org/standard/core/UMTimes
;C UM* u1 u2 -- ud unsigned 16x16->32 mult.
FORTHWORD "UM*"
MOV @IP+,PC
.ELSE
-
;https://forth-standard.org/standard/core/MTimes
;C M* n1 n2 -- dlo dhi signed 16*16->32 multiply
FORTHWORD "M*"
;-------------------------------------------------------------------------------
; MEMORY OPERATIONS
;-------------------------------------------------------------------------------
- .IFNDEF FETCH
-;https://forth-standard.org/standard/core/Fetch
-; C@ c-addr -- word fetch word from memory
- FORTHWORD "@"
-FETCH MOV @TOS,TOS ;2
- MOV @IP+,PC ;4
- .ENDIF
-
- .IFNDEF STORE
-;https://forth-standard.org/standard/core/Store
-; C! word c-addr -- store word in memory
- FORTHWORD "!"
-STORE MOV @PSP+,0(TOS) ;4
- MOV @PSP+,TOS ;2
- MOV @IP+,PC
- .ENDIF
-
.IFNDEF CFETCH
;https://forth-standard.org/standard/core/CFetch
; C@ c-addr -- char fetch char from memory
FORTHWORD "C@"
CFETCH MOV.B @TOS,TOS ;2
MOV @IP+,PC ;4
- .ENDIF
+ .ENDIF
.IFNDEF CSTORE
;https://forth-standard.org/standard/core/CStore
; C! char c-addr -- store char in memory
ADD #1,PSP ;1
MOV @PSP+,TOS ;2
MOV @IP+,PC
- .ENDIF
+ .ENDIF
.IFNDEF CCOMMA
;https://forth-standard.org/standard/core/CComma
; C, char -- append char
ADD #1,&DP
MOV @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
;https://forth-standard.org/standard/core/PlusStore
;C +! n/u a-addr -- add to memory
FORTHWORD "+!"
FORTHWORDIMM "BEGIN" ; immediate
; https://forth-standard.org/standard/core/BEGIN
; BEGIN -- BEGINadr initialize backward branch
- MOV #HEREXEC,PC ; -- HERE
+ MOV #HERE,PC ; -- HERE
FORTHWORDIMM "UNTIL" ; immediate
; https://forth-standard.org/standard/core/UNTIL
REPEAT mDOCOL
.word AGAIN,THEN,EXIT
- FORTHWORDIMM "DO" ; immediate
; Primitive XDO; compiled by DO
;Z (do) n1|u1 n2|u2 -- R: -- sys1 sys2 run-time code for DO
; n1|u1=limit, n2|u2=index
MOV @PSP+,TOS ;2
MOV @IP+,PC ;4
+ FORTHWORDIMM "DO" ; immediate
; https://forth-standard.org/standard/core/DO
; DO -- DOadr L: -- 0
DO SUB #2,PSP ;
MOV @RSP,TOS ;2 index = loopctr - fudge
SUB 2(RSP),TOS ;3
MOV @IP+,PC ;4 13~
- .ENDIF
+ .ENDIF
; Primitive XLOOP; compiled by LOOP
;Z (loop) R: sys1 sys2 -- | sys1 sys2
; run-time code for LOOP
; https://forth-standard.org/standard/core/HERE
; HERE -- addr returns memory ptr
-HERE FORTHWORD "HERE"
- MOV #HEREXEC,PC
+ FORTHWORD "HERE"
+ MOV #HERE,PC
;https://forth-standard.org/standard/core/p
;C ( \ -- paren ; skip input until )
FORTHWORD ">BODY"
TOBODY ADD #4,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
; https://forth-standard.org/standard/core/EXECUTE
; EXECUTE i*x xt -- j*x execute Forth word at 'xt'
FORTHWORD "EXECUTE"
FORTHWORD "PAD"
PAD CALL rDOCON
.WORD PAD_ORG
- .ENDIF
+ .ENDIF
; https://forth-standard.org/standard/core/VARIABLE
; VARIABLE <name> -- define a Forth VARIABLE
FORTHWORD "VARIABLE"
.word CREATE
mNEXTADR
MOV #4030h,-4(W) ;4 first CELL = MOV @PC+,PC = BR #addr
- MOV #NEXTADR,-2(W) ;3 second CELL = ...mNEXT : do nothing by default
+ MOV #NEXT_ADR,-2(W) ;3 second CELL = ...mNEXT : do nothing by default
MOV @RSP+,IP
MOV @IP+,PC
MOV @PSP+,0(TOS) ; 4 execute Store
MOV @PSP+,TOS ; 2
MOV @IP+,PC ; 4
-
--- /dev/null
+; -*- coding: utf-8 -*-
+;
+; to see kernel options, download FastForthSpecs.f
+; FastForth kernel options: MSP430ASSEMBLER, CONDCOMP, DOUBLE_INPUT
+;
+; TARGET SELECTION ( = the name of ;INC;target.pat file without the extension)
+; MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
+; MSP_EXP430FR4133 MSP_EXP430FR2433 CHIPSTICK_FR2433 MSP_EXP430FR2355
+; LP_MSP430FR2476
+;
+; from scite editor : copy your target selection in (shift+F8) parameter 1:
+;
+; OR
+;
+; drag and drop this file onto SendSourceFileToTarget.bat
+; then select your TARGET when asked.
+;
+;
+; REGISTERS USAGE
+; rDODOES to rEXIT must be saved before use and restored after
+; scratch registers Y to S are free for use
+; under interrupt, IP is free for use
+;
+; FORTH conditionnals: unary{ 0= 0< 0> }, binary{ = < > U< }
+;
+; ASSEMBLER conditionnal usage with IF UNTIL WHILE S< S>= U< U>= 0= 0<> 0>=
+;
+; ASSEMBLER conditionnal usage with ?GOTO S< S>= U< U>= 0= 0<> 0<
+;
+
+; -----------------------------------------------------
+; DOUBLE.asm
+; -----------------------------------------------------
+
+ FORTHWORD "{DOUBLE}"
+ MOV @IP+,PC
+
+ .IFNDEF TOR
+; https://forth-standard.org/standard/core/toR
+; >R x -- R: -- x push to return stack
+ FORTHWORD ">R"
+TOR PUSH TOS
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF RFROM1
+; https://forth-standard.org/standard/core/Rfrom
+; R> -- x R: x -- pop from return stack
+ FORTHWORD "R>"
+RFROM1 SUB #2,PSP ; 1
+ MOV TOS,0(PSP) ; 3
+ MOV @RSP+,TOS ; 2
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF ZEROLESS
+ FORTHWORD "0<"
+; https://forth-standard.org/standard/core/Zeroless
+; 0< n -- flag true if TOS negative
+ZEROLESS ADD TOS,TOS ;1 set carry if TOS negative
+ SUBC TOS,TOS ;1 TOS=-1 if carry was clear
+EQUALTRUE XOR #-1,TOS ;1 TOS=-1 if carry was set
+ MOV @IP+,PC ;
+
+ .ENDIF
+ .IFNDEF STOD
+; https://forth-standard.org/standard/core/StoD
+; S>D n -- d single -> double prec.
+ FORTHWORD "S>D"
+STOD SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV #ZEROLESS,PC
+
+ .ENDIF
+ .IFNDEF DROP1
+; https://forth-standard.org/standard/core/DROP
+; DROP x -- drop top of stack
+ FORTHWORD "DROP"
+DROP1 MOV @PSP+,TOS ; 2
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF QDUP
+; https://forth-standard.org/standard/core/DUP
+; DUP x -- x x duplicate top of stack
+ FORTHWORD "DUP"
+QDUPNEXT SUB #2,PSP ; 2 push old TOS..
+ MOV TOS,0(PSP) ; 3 ..onto stack
+QDUPEND MOV @IP+,PC ; 4
+
+; https://forth-standard.org/standard/core/qDUP
+; ?DUP x -- 0 | x x DUP if nonzero
+ FORTHWORD "?DUP"
+QDUP CMP #0,TOS
+ JNZ QDUPNEXT
+ JZ QDUPEND
+
+ .ENDIF
+ .IFNDEF SWAP
+; https://forth-standard.org/standard/core/SWAP
+; SWAP x1 x2 -- x2 x1 swap top two items
+ FORTHWORD "SWAP"
+SWAP MOV @PSP,W ; 2
+ MOV TOS,0(PSP) ; 3
+ MOV W,TOS ; 1
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF OVER
+;https://forth-standard.org/standard/core/OVER
+;C OVER x1 x2 -- x1 x2 x1
+ FORTHWORD "OVER"
+OVER MOV TOS,-2(PSP) ; 3 -- x1 (x2) x2
+ MOV @PSP,TOS ; 2 -- x1 (x2) x1
+ SUB #2,PSP ; 1 -- x1 x2 x1
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF NIP1
+ FORTHWORD "NIP"
+; https://forth-standard.org/standard/core/NIP
+; NIP x1 x2 -- x2 Drop the first item below the top of stack
+NIP1 ADD #2,PSP ; 1
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF ROT
+;https://forth-standard.org/standard/core/ROT
+;C ROT x1 x2 x3 -- x2 x3 x1
+ FORTHWORD "ROT"
+ROT MOV @PSP,W ; 2 fetch x2
+ MOV TOS,0(PSP) ; 3 store x3
+ MOV 2(PSP),TOS ; 3 fetch x1
+ MOV W,2(PSP) ; 3 store x2
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF UMSLASHMOD
+;https://forth-standard.org/standard/core/UMDivMOD
+; UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16
+ FORTHWORD "UM/MOD"
+UMSLASHMOD PUSH #DROP ;3 as return address for MU/MOD
+ MOV #MUSMOD,PC
+
+ .ENDIF
+ .IFNDEF FLOORED_DIVISION
+ .IFNDEF SMSLASHREM
+;https://forth-standard.org/standard/core/SMDivREM
+;C SM/REM d1lo d1hi n2 -- n3 n4 symmetric signed div
+ FORTHWORD "SM/REM"
+SMSLASHREM MOV TOS,S ;1 S=divisor
+ MOV @PSP,T ;2 T=rem_sign
+ CMP #0,TOS ;1 n2 >= 0 ?
+ JGE d1u2SMSLASHREM ;2 yes
+ XOR #-1,TOS ;1
+ ADD #1,TOS ;1
+d1u2SMSLASHREM ; -- d1 u2
+ CMP #0,0(PSP) ;3 d1hi >= 0 ?
+ JGE ud1u2SMSLASHREM ;2 yes
+ XOR #-1,2(PSP) ;4 d1lo
+ XOR #-1,0(PSP) ;4 d1hi
+ ADD #1,2(PSP) ;4 d1lo+1
+ ADDC #0,0(PSP) ;4 d1hi+C
+ud1u2SMSLASHREM ; -- ud1 u2
+ PUSHM #2,S ;4 PUSHM S,T
+ CALL #MUSMOD
+ MOV @PSP+,TOS
+ POPM #2,S ;4 POPM T,S
+ CMP #0,T ;1 -- ur uq T=rem_sign>=0?
+ JGE SMSLASHREMnruq ;2 yes
+ XOR #-1,0(PSP) ;3
+ ADD #1,0(PSP) ;3
+SMSLASHREMnruq
+ XOR S,T ;1 S=divisor T=quot_sign
+ CMP #0,T ;1 -- nr uq T=quot_sign>=0?
+ JGE SMSLASHREMnrnq ;2 yes
+NEGAT XOR #-1,TOS ;1
+ ADD #1,TOS ;1
+SMSLASHREMnrnq ; -- nr nq S=divisor
+ MOV @IP+,PC ;4 34 words
+
+ .ENDIF
+ .ELSE ; FLOORED_DIVISION
+ .IFNDEF FMSLASHMOD
+;https://forth-standard.org/standard/core/FMDivMOD
+;C FM/MOD d1 n1 -- r q floored signed div'n
+ FORTHWORD "FM/MOD"
+FMSLASHMOD MOV TOS,S ;1 S=divisor
+ MOV @PSP,T ;2 T=rem_sign
+ CMP #0,TOS ;1 n2 >= 0 ?
+ JGE d1u2FMSLASHMOD ;2 yes
+ XOR #-1,TOS ;1
+ ADD #1,TOS ;1
+d1u2FMSLASHMOD ; -- d1 u2
+ CMP #0,0(PSP) ;3 d1hi >= 0 ?
+ JGE ud1u2FMSLASHMOD ;2 yes
+ XOR #-1,2(PSP) ;4 d1lo
+ XOR #-1,0(PSP) ;4 d1hi
+ ADD #1,2(PSP) ;4 d1lo+1
+ ADDC #0,0(PSP) ;4 d1hi+C
+ud1u2FMSLASHMOD ; -- ud1 u2
+ PUSHM #2,S ;4 PUSHM S,T
+ CALL #MUSMOD
+ MOV @PSP+,TOS
+ POPM #2,S ;4 POPM T,S
+ CMP #0,T ;1 -- ur uq T=rem_sign>=0?
+ JGE FMSLASHMODnruq ;2 yes
+ XOR #-1,0(PSP) ;3
+ ADD #1,0(PSP) ;3
+FMSLASHMODnruq
+ XOR S,T ;1 S=divisor T=quot_sign
+ CMP #0,T ;1 -- nr uq T=quot_sign>=0?
+ JGE FMSLASHMODnrnq ;2 yes
+NEGAT XOR #-1,TOS ;1
+ ADD #1,TOS ;1
+FMSLASHMODnrnq ; -- nr nq S=divisor
+
+ CMP #0,0(PSP) ;
+ JZ FMSLASHMODEND
+ CMP #1,TOS ; quotient < 1 ?
+ JGE FMSLASHMODEND ;
+QUOTLESSONE ADD S,0(PSP) ; add divisor to remainder
+ SUB #1,TOS ; decrement quotient
+FMSLASHMODEND
+ MOV @RSP+,IP
+ MOV @IP+,PC ;
+
+ .ENDIF
+ .ENDIF
+ .IFNDEF SLASH
+;https://forth-standard.org/standard/core/Div
+;C / n1 n2 -- n3 signed divide
+ FORTHWORD "/"
+SLASH mDOCOL
+ .word TOR,STOD,RFROM
+ .IFNDEF FLOORED_DIVISION
+ .word SMSLASHREM
+ .ELSE
+ .word FMSLASHMOD
+ .ENDIF
+ .word NIP,EXIT
+
+ .ENDIF
+ .IFNDEF CFETCH
+;https://forth-standard.org/standard/core/CFetch
+; C@ c-addr -- char fetch char from memory
+ FORTHWORD "C@"
+CFETCH MOV.B @TOS,TOS ;2
+ MOV @IP+,PC ;4
+
+ .ENDIF
+ .IFNDEF LESS
+; https://forth-standard.org/standard/core/OneMinus
+; 1- n1/u1 -- n2/u2 subtract 1 from TOS
+ FORTHWORD "1-"
+ONEMINUS1 SUB #1,TOS
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF LESS
+;https://forth-standard.org/standard/core/less
+;C < n1 n2 -- flag test n1<n2, signed
+ FORTHWORD "<"
+LESS SUB @PSP+,TOS ;1 TOS=n2-n1
+ JZ LESSEND ;2 flag Z = 1
+ JL TOSFALSE ;2 signed jump
+TOSTRUE MOV #-1,TOS ;1 flag Z = 0
+LESSEND MOV @IP+,PC ;4
+
+;https://forth-standard.org/standard/core/more
+;C > n1 n2 -- flag test n1>n2, signed
+ FORTHWORD ">"
+MORE SUB @PSP+,TOS ;2 TOS=n2-n1
+ JL TOSTRUE ;2 --> +5
+TOSFALSE AND #0,TOS ;1 flag Z = 1
+ MOV @IP+,PC ;4
+
+ .ENDIF
+
+; .IFNDEF IFF
+;; https://forth-standard.org/standard/core/IF
+;; IF -- IFadr initialize conditional forward branch
+; FORTHWORDIMM "IF" ; immediate
+;IFF SUB #2,PSP ;
+; MOV TOS,0(PSP) ;
+; MOV &DP,TOS ; -- HERE
+; ADD #4,&DP ; compile one word, reserve one word
+; MOV #QFBRAN,0(TOS) ; -- HERE compile QFBRAN
+; ADD #2,TOS ; -- HERE+2=IFadr
+; MOV @IP+,PC
+;
+; FORTHWORDIMM "ELSE" ; immediate
+;; https://forth-standard.org/standard/core/ELSE
+;; ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
+;ELSS ADD #4,&DP ; make room to compile two words
+; MOV &DP,W ; W=HERE+4
+; MOV #BRAN,-4(W)
+; MOV W,0(TOS) ; HERE+4 ==> [IFadr]
+; SUB #2,W ; HERE+2
+; MOV W,TOS ; -- ELSEadr
+; MOV @IP+,PC
+;
+; FORTHWORDIMM "THEN" ; immediate
+;; https://forth-standard.org/standard/core/THEN
+;; THEN IFadr -- resolve forward branch
+;THEN MOV &DP,0(TOS) ; -- IFadr
+; MOV @PSP+,TOS ; --
+; MOV @IP+,PC
+; .ENDIF
+
+ .IFNDEF TO
+; https://forth-standard.org/standard/core/TO
+ FORTHWORD "TO"
+TO BIS #UF9,SR
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF SPACE
+;https://forth-standard.org/standard/core/SPACE
+;C SPACE -- output a space
+ FORTHWORD "SPACE"
+SPACE SUB #2,PSP ;1
+ MOV TOS,0(PSP) ;3
+ MOV #20h,TOS ;2
+ MOV #EMIT,PC ;17~ 23~
+
+ .ENDIF
+ .IFNDEF SPACES
+;https://forth-standard.org/standard/core/SPACES
+;C SPACES n -- output n spaces
+ FORTHWORD "SPACES"
+SPACES CMP #0,TOS
+ JZ SPACESNEXT2
+ PUSH IP
+ MOV #SPACESNEXT,IP
+ JMP SPACE ;25~
+SPACESNEXT mNEXTADR
+ SUB #2,IP ;1
+ SUB #1,TOS ;1
+ JNZ SPACE ;25~ ==> 27~ by space ==> 2.963 MBds @ 8 MHz
+ MOV @RSP+,IP ;
+SPACESNEXT2 MOV @PSP+,TOS ; -- drop n
+ MOV @IP+,PC ;
+
+ .ENDIF
+ .IFNDEF TWOFETCH
+; https://forth-standard.org/standard/core/TwoFetch
+; 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack
+ FORTHWORD "2@"
+TWOFETCH SUB #2, PSP
+ MOV 2(TOS),0(PSP)
+ MOV @TOS,TOS
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF TWOSTORE
+; https://forth-standard.org/standard/core/TwoStore
+; 2! x1 x2 a-addr -- store 2 cells ; the top of stack is stored at the lower adr
+ FORTHWORD "2!"
+TWOSTORE MOV @PSP+,0(TOS)
+ MOV @PSP+,2(TOS)
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF TWODUP
+; https://forth-standard.org/standard/core/TwoDUP
+; 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells
+ FORTHWORD "2DUP"
+TWODUP MOV TOS,-2(PSP) ; 3
+ MOV @PSP,-4(PSP) ; 4
+ SUB #4,PSP ; 1
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF TWODROP
+; https://forth-standard.org/standard/core/TwoDROP
+; 2DROP x1 x2 -- drop 2 cells
+ FORTHWORD "2DROP"
+TWODROP ADD #2,PSP
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF TWOSWAP
+; https://forth-standard.org/standard/core/TwoSWAP
+; 2SWAP x1 x2 x3 x4 -- x3 x4 x1 x2
+ FORTHWORD "2SWAP"
+TWOSWAP MOV @PSP,W ; -- x1 x2 x3 x4 W=x3
+ MOV 4(PSP),0(PSP) ; -- x1 x2 x1 x4
+ MOV W,4(PSP) ; -- x3 x2 x1 x4
+ MOV TOS,W ; -- x3 x2 x1 x4 W=x4
+ MOV 2(PSP),TOS ; -- x3 x2 x1 x2 W=x4
+ MOV W,2(PSP) ; -- x3 x4 x1 x2
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF TwoOVER
+; https://forth-standard.org/standard/core/TwoOVER
+; 2OVER x1 x2 x3 x4 -- x1 x2 x3 x4 x1 x2
+ FORTHWORD "2OVER"
+TwoOVER SUB #4,PSP ; -- x1 x2 x3 x x x4
+ MOV TOS,2(PSP) ; -- x1 x2 x3 x4 x x4
+ MOV 8(PSP),0(PSP) ; -- x1 x2 x3 x4 x1 x4
+ MOV 6(PSP),TOS ; -- x1 x2 x3 x4 x1 x2
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF TWOTOR
+; https://forth-standard.org/standard/core/TwotoR
+; ( x1 x2 -- ) ( R: -- x1 x2 ) Transfer cell pair x1 x2 to the return stack.
+ FORTHWORD "2>R"
+TWOTOR PUSH @PSP+
+ PUSH TOS
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF TWORFETCH
+; https://forth-standard.org/standard/core/TwoRFetch
+; ( -- x1 x2 ) ( R: x1 x2 -- x1 x2 ) Copy cell pair x1 x2 from the return stack.
+ FORTHWORD "2R@"
+TWORFETCH SUB #4,PSP
+ MOV TOS,2(PSP)
+ MOV @RSP,TOS
+ MOV 2(RSP),0(PSP)
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF TwoRfrom
+; https://forth-standard.org/standard/core/TwoRfrom
+; ( -- x1 x2 ) ( R: x1 x2 -- ) Transfer cell pair x1 x2 from the return stack
+ FORTHWORD "2R>"
+TWORFROM SUB #4,PSP
+ MOV TOS,2(PSP)
+ MOV @RSP+,TOS
+ MOV @RSP+,0(PSP)
+ MOV @IP+,PC
+ .ENDIF
+
+; ===============================================
+; DOUBLE word set
+; ===============================================
+ .IFNDEF DDOT
+; https://forth-standard.org/standard/double/Dd
+; D. dlo dhi -- display d (signed)
+ FORTHWORD "D."
+ MOV TOS,S ; S will be pushed as sign
+ MOV #UDOT+10,PC ; U. + 10 = D.
+
+ .ENDIF
+ .IFNDEF TwoROT
+; https://forth-standard.org/standard/double/TwoROT
+; Rotate the top three cell pairs on the stack bringing cell pair x1 x2 to the top of the stack.
+ FORTHWORD "2ROT"
+TWOROT MOV 8(PSP),X ; 3
+ MOV 6(PSP),Y ; 3
+ MOV 4(PSP),8(PSP) ; 5
+ MOV 2(PSP),6(PSP) ; 5
+ MOV @PSP,4(PSP) ; 4
+ MOV TOS,2(PSP) ; 3
+ MOV X,0(PSP) ; 3
+ MOV Y,TOS ; 1
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF DtoS
+; https://forth-standard.org/standard/double/DtoS
+; D>S d -- n double prec -> single.
+ FORTHWORD "D>S"
+DTOS MOV @PSP+,TOS
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF DZEQU
+; https://forth-standard.org/standard/double/DZeroEqual
+ FORTHWORD "D0="
+DZEROEQUAL ADD #2,PSP
+ CMP #0,TOS
+ MOV #0,TOS
+ JNZ DSETFLAG
+ CMP #0,-2(PSP)
+ JNZ DSETFLAG
+DTRUE MOV #-1,TOS
+DSETFLAG AND #-1,TOS ; to set N, Z flags
+ MOV @IP+,PC
+
+; https://forth-standard.org/standard/double/DZeroless
+ FORTHWORD "D0<"
+DZEROLESS ADD #2,PSP
+ CMP #0,TOS
+ MOV #0,TOS
+ JGE DSETFLAG
+ JL DTRUE
+
+; https://forth-standard.org/standard/double/DEqual
+ FORTHWORD "D="
+DEQUAL ADD #6,PSP ; 2
+ CMP TOS,-4(PSP) ; 3 ud1H - ud2H
+ MOV #0,TOS ; 1
+ JNZ DSETFLAG ; 2
+ CMP -6(PSP),-2(PSP) ; 4 ud1L - ud2L
+ JZ DTRUE ; 2
+ JMP DSETFLAG
+
+; https://forth-standard.org/standard/double/Dless
+; flag is true if and only if d1 is less than d2
+ FORTHWORD "D<"
+DLESS ADD #6,PSP ; 2
+ CMP TOS,-4(PSP) ; 3 d1H - d2H
+ MOV #0,TOS ; 1
+ JGE DLESS2 ; 2
+DLESS1 MOV #-1,TOS ;
+DLESS2 JNZ DSETFLAG ; 2
+ CMP -6(PSP),-2(PSP) ; 4 d1L - d2L
+ JNC DTRUE ; 2
+ JMP DSETFLAG ; 2
+
+; https://forth-standard.org/standard/double/DUless
+; flag is true if and only if ud1 is less than ud2
+ FORTHWORD "DU<"
+DULESS ADD #6,PSP ; 2
+ CMP TOS,-4(PSP) ; 3 ud1H - ud2H
+ MOV #0,TOS ; 1
+ JC DLESS2 ; 2
+ JNC DLESS1
+
+ .ENDIF ; DZEQU
+ .IFNDEF DPlus
+; https://forth-standard.org/standard/double/DPlus
+ FORTHWORD "D+"
+DPLUS ADD @PSP+,2(PSP)
+ ADDC @PSP+,TOS
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF MPLUS
+; https://forth-standard.org/standard/double/MPlus
+ FORTHWORD "M+"
+MPLUS SUB #2,PSP
+ CMP #0,TOS
+ MOV TOS,0(PSP)
+ MOV #-1,TOS
+ JL DPLUS
+ MOV #0,TOS
+ JMP DPLUS
+
+ .ENDIF
+ .IFNDEF DMinus
+; https://forth-standard.org/standard/double/DMinus
+ FORTHWORD "D-"
+DMINUS SUB @PSP+,2(PSP)
+ SUBC TOS,0(PSP)
+ MOV @PSP+,TOS
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF DNEGATE
+; https://forth-standard.org/standard/double/DNEGATE
+ FORTHWORD "DNEGATE"
+DNEGATE XOR #-1,0(PSP)
+ XOR #-1,TOS
+ ADD #1,0(PSP)
+ ADDC #0,TOS
+ MOV @IP+,PC ; 4
+
+; https://forth-standard.org/standard/double/DABS
+; DABS d1 -- |d1| absolute value
+ FORTHWORD "DABS"
+DABS CMP #0,TOS ; 1
+ JL DNEGATE
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF DTwoDiv
+; https://forth-standard.org/standard/double/DTwoDiv
+ FORTHWORD "D2/"
+DTWODIV RRA TOS
+ RRC 0(PSP)
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF DTwoTimes
+; https://forth-standard.org/standard/double/DTwoTimes
+DTWOTIMES FORTHWORD "D2*"
+ ADD @PSP,0(PSP)
+ ADDC TOS,TOS
+ MOV @IP+,PC ; 4
+
+ .ENDIF
+ .IFNDEF DMAX
+; https://forth-standard.org/standard/double/DMAX
+ FORTHWORD "DMAX" ; -- d1 d2
+DMAX mDOCOL
+ .word TWOOVER,TWOOVER ; -- d1 d2 d1 d2
+ .word DLESS,QFBRAN,DMAX1 ; -- d1 d2
+ .word TWOTOR,TWODROP,TWORFROM ; -- d2
+ .word BRAN,DMAX2 ; -- d1 d2
+DMAX1 .word TWODROP ; -- d1
+DMAX2 .word EXIT
+
+ .ENDIF
+ .IFNDEF DMIN
+; https://forth-standard.org/standard/double/DMIN
+ FORTHWORD "DMIN" ; -- d1 d2
+DMIN mDOCOL
+ .word TWOOVER,TWOOVER ; -- d1 d2 d1 d2
+ .word DLESS,QFBRAN,DMIN1 ; -- d1 d2
+ .word TWODROP ; -- d1
+ .word BRAN,DMIN2 ; -- d1 d2
+DMIN1 .word TWOTOR,TWODROP,TWORFROM ; -- d2
+DMIN2 .word EXIT
+
+ .ENDIF
+ .IFNDEF MTIMESDIV
+; https://forth-standard.org/standard/double/MTimesDiv
+ FORTHWORD "M*/" ; d1 * n1 / +n2 -- d2
+MTIMESDIV
+ .IFDEF HMPY
+ MOV 4(PSP),&MPYS32L ; 5 Load 1st operand d1lo
+ MOV 2(PSP),&MPYS32H ; 5 d1hi
+ MOV @PSP+,&OP2 ; 4 -- d1 n2 load 2nd operand n1
+ MOV TOS,T ; T = DIV
+ NOP3
+ MOV &RES0,S ; 3 S = RESlo
+ MOV &RES1,TOS ; 3 TOS = RESmi
+ MOV &RES2,W ; 3 W = REShi
+ MOV #0,rDOCON ; clear sign flag
+ CMP #0,W ; negative product ?
+ JGE MTIMESDIV1 ; no
+ XOR #-1,S ; compute ABS value if yes
+ XOR #-1,TOS
+ XOR #-1,W
+ ADD #1,S
+ ADDC #0,TOS
+ ADDC #0,W
+ MOV #-1,rDOCON ; set sign flag
+MTIMESDIV1
+ .ELSE
+ MOV #0,rDOCON ; rDOCON = sign
+ CMP #0,2(PSP) ; d1 < 0 ?
+ JGE MTIMESDIV2 ; no
+ XOR #-1,4(PSP) ; compute ABS value if yes
+ XOR #-1,2(PSP)
+ ADD #1,4(PSP)
+ ADDC #0,2(PSP)
+ MOV #-1,rDOCON
+MTIMESDIV2 ; ud1
+ CMP #0,0(PSP) ; n1 < 0 ?
+ JGE MTIMESDIV3 ; no
+ XOR #-1,0(PSP)
+ ADD #1,0(PSP) ; u1
+ XOR #-1,rDOCON
+; let's process UM* -- ud1lo ud1hi u1 +n2
+MTIMESDIV3 MOV 4(PSP),Y ; 3 uMDlo
+ MOV 2(PSP),T ; 3 uMDhi
+ MOV @PSP+,S ; 2 uMRlo -- ud1lo ud1hi +n2
+ MOV #0,rDODOES ; 1 uMDlo=0
+ MOV #0,2(PSP) ; 3 uRESlo=0
+ MOV #0,0(PSP) ; 3 uRESmi=0 -- uRESlo uRESmi +n2
+ MOV #0,W ; 1 uREShi=0
+ MOV #1,X ; 1 BIT TEST REGlo
+MTIMESDIV4 BIT X,S ; 1 test actual bit in uMRlo
+ JZ MTIMESDIV5
+ ADD Y,2(PSP) ; 3 IF 1: ADD uMDlo TO uRESlo
+ ADDC T,0(PSP) ; 3 ADDC uMDmi TO uRESmi
+ ADDC rDODOES,W ; 1 ADDC uMRlo TO uREShi
+MTIMESDIV5 ADD Y,Y ; 1 (RLA LSBs) uMDlo *2
+ ADDC T,T ; 1 (RLC MSBs) uMDhi *2
+ ADDC rDODOES,rDODOES ; 1 (RLA LSBs) uMDlo *2
+ ADD X,X ; 1 (RLA) NEXT BIT TO TEST
+ JNC MTIMESDIV4 ; 1 IF BIT IN CARRY: FINISHED W=uREShi
+; TOS +n2
+; W REShi
+; 0(PSP) RESmi
+; 2(PSP) RESlo
+ MOV TOS,T
+ MOV @PSP,TOS
+ MOV 2(PSP),S
+ .ENDIF ; endcase of software/hardware_MPY
+; process division
+; reg input output
+; ------------------------------
+; S = DVD(15-0)
+; TOS = DVD(31-16)
+; W = DVD(47-32) REM
+; T = DIV(15-0)
+; X = Don't care QUOTlo
+; Y = Don't care QUOThi
+; rDODOES = count
+; rDOCON = sign
+; 2(PSP) REM
+; 0(PSP) QUOTlo
+; TOS QUOThi
+ MOV #32,rDODOES ; 2 init loop count
+ CMP #0,W ; DVDhi = 0 ?
+ JNZ MTIMESDIV6 ; if no
+ MOV TOS,W ; DVDmi --> DVDhi
+ CALL #MDIV1DIV2 ; with loop count / 2
+ JMP MTIMESDIV7
+MTIMESDIV6 CALL #MDIV1 ; -- urem ud2lo ud2hi
+MTIMESDIV7 MOV @PSP+,0(PSP) ; -- d2lo d2hi
+ CMP #0,rDOCON ; RES sign is set ?
+ JZ MTIMESDIV8 ; no
+ XOR #-1,0(PSP) ; DNEGATE quot
+ XOR #-1,TOS
+ ADD #1,0(PSP)
+ ADDC #0,TOS
+ CMP #0,&FORTHADDON ; floored/symetric division flag test
+ JGE MTIMESDIV8 ; if not(floored division and quot<0)
+ CMP #0,W ; remainder <> 0 ?
+ JZ MTIMESDIV8 ; if not(floored division, quot<0 and remainder <>0)
+ SUB #1,0(PSP) ; decrement quotient
+ SUBC #0,TOS
+MTIMESDIV8 MOV #XDODOES,rDODOES
+ MOV #XDOCON,rDOCON
+ MOV @IP+,PC ; 52 words
+
+ .ENDIF ;
+ .IFNDEF TwoVARIABLE
+; https://forth-standard.org/standard/double/TwoVARIABLE
+ FORTHWORD "2VARIABLE" ; --
+TwoVARIABLE mDOCOL
+ .word CREATE
+ mNEXTADR
+ ADD #4,&DP
+ MOV @RSP+,IP
+ MOV @IP+,PC
+
+ .ENDIF
+ .IFNDEF TwoCONSTANT
+; https://forth-standard.org/standard/double/TwoCONSTANT
+ FORTHWORD "2CONSTANT" ; udlo/dlo/Flo udhi/dhi/Shi -- to create double or s15q16 CONSTANT
+TwoCONSTANT mDOCOL
+ .word CREATE
+ .word COMMA,COMMA ; compile Shi then Flo
+ .word DOES
+ .word TWOFETCH ; execution part
+ .word EXIT
+
+ .ENDIF
+ .IFNDEF TwoVALUE
+; https://forth-standard.org/standard/double/TwoVALUE
+ FORTHWORD "2VALUE" ; x1 x2 "<spaces>name" --
+TwoVALUE mDOCOL
+ .word CREATE ; compile Shi then Flo
+ .word COMMA,COMMA ; compile Shi then Flo
+ .word DOES
+ mNEXTADR
+ MOV @RSP+,IP
+ BIT #UF9,SR ; flag set by TO
+ JNZ TwoVALUESTO
+ MOV #TwoFetch,PC ; execute TwoFetch
+TwoVALUESTO BIC #UF9,SR ; clear flag
+ MOV #TwoStore,PC ; execute TwoStore
+
+ .ENDIF
+ .IFNDEF TwoLITERAL
+; https://forth-standard.org/standard/double/TwoLITERAL
+ FORTHWORDIMM "2LITERAL"
+TwoLITERAL BIS #UF9,SR ; see LITERAL
+ MOV #LITERAL,PC
+
+ .ENDIF
+ .IFNDEF DDotR
+; https://forth-standard.org/standard/double/DDotR
+; D.R d n --
+ FORTHWORD "D.R"
+ mDOCOL
+ .word TOR,SWAP,OVER,DABS,LESSNUM,NUMS,ROT,SIGN,NUMGREATER
+ .word RFROM,OVER,MINUS,SPACES,TYPE
+ .word EXIT
+ .ENDIF
FORTHWORD "{FIXPOINT}"
MOV @IP+,PC
- .IFNDEF DABS
-DABS AND #-1,TOS ; clear V, set N
- JGE DABSEND ; if positive (N=0)
- XOR #-1,0(PSP) ;4
- XOR #-1,TOS ;1
- ADD #1,0(PSP) ;4
- ADDC #0,TOS ;1
-DABSEND MOV @IP+,PC
- .ENDIF
+ .IFNDEF DNEGATE
+; https://forth-standard.org/standard/double/DNEGATE
+ FORTHWORD "DNEGATE"
+DNEGATE XOR #-1,0(PSP)
+ XOR #-1,TOS
+ ADD #1,0(PSP)
+ ADDC #0,TOS
+ MOV @IP+,PC ; 4
+; https://forth-standard.org/standard/double/DABS
+; DABS d1 -- |d1| absolute value
+ FORTHWORD "DABS"
+DABS CMP #0,TOS ; 1
+ JL DNEGATE
+ MOV @IP+,PC
+
+ .ENDIF
; https://forth-standard.org/standard/core/HOLDS
; Adds the string represented by addr u to the pictured numeric output string
; compilation use: <# S" string" HOLDS #>
MOV @RSP+,IP ; 2
MOV @IP+,PC
-
FORTHWORD "F*" ; s15.16 * s15.16 --> s15.16 result
MOV 2(PSP),S ;
XOR TOS,S ; MDhi XOR MRhi --> S keep sign of result
ADDC #0,TOS
FSTAREND MOV @IP+,PC
-
FORTHWORD "F/" ; s15.16 / s15.16 --> s15.16 result
FDIV PUSHM #4,rDOVAR ; 6 save rDOVAR to rDOCOL regs to use M to R alias
MOV @PSP+,M ; DIVlo
; -*- coding: utf-8 -*-
- .IFNDEF ANDD
-;https://forth-standard.org/standard/core/AND
-;C AND x1 x2 -- x3 logical AND
- FORTHWORD "AND"
-ANDD AND @PSP+,TOS
- MOV @IP+,PC
- .ENDIF
+ FORTHWORD "{SD_TOOLS}"
+ MOV @IP+,PC
.IFNDEF MAX
MOV @IP+,PC
.ENDIF
-
.IFNDEF SPACE
;https://forth-standard.org/standard/core/SPACE
;C SPACE -- output a space
MOV @IP+,PC ;
.ENDIF
+ .IFNDEF XDO
+; Primitive XDO; compiled by DO
+;Z (do) n1|u1 n2|u2 -- R: -- sys1 sys2 run-time code for DO
+; n1|u1=limit, n2|u2=index
+XDO MOV #8000h,X ;2 compute 8000h-limit = "fudge factor"
+ SUB @PSP+,X ;2
+ MOV TOS,Y ;1 loop ctr = index+fudge
+ ADD X,Y ;1 Y = INDEX
+ PUSHM #2,X ;4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX
+ MOV @PSP+,TOS ;2
+ MOV @IP+,PC ;4
+
+ FORTHWORDIMM "DO" ; immediate
+; https://forth-standard.org/standard/core/DO
+; DO -- DOadr L: -- 0
+DO SUB #2,PSP ;
+ MOV TOS,0(PSP) ;
+ ADD #2,&DP ; make room to compile xdo
+ MOV &DP,TOS ; -- HERE+2
+ MOV #XDO,-2(TOS) ; compile xdo
+ ADD #2,&LEAVEPTR ; -- HERE+2 LEAVEPTR+2
+ MOV &LEAVEPTR,W ;
+ MOV #0,0(W) ; -- HERE+2 L-- 0
+ MOV @IP+,PC
+
+; Primitive XLOOP; compiled by LOOP
+;Z (loop) R: sys1 sys2 -- | sys1 sys2
+; run-time code for LOOP
+; Add 1 to the loop index. If loop terminates, clean up the
+; return stack and skip the branch. Else take the inline branch.
+; Note that LOOP terminates when index=8000h.
+XLOOP ADD #1,0(RSP) ;4 increment INDEX
+XLOOPNEXT BIT #100h,SR ;2 is overflow bit set?
+ JZ XLOOPDO ;2 no overflow = loop
+ ADD #4,RSP ;1 empties RSP
+ ADD #2,IP ;1 overflow = loop done, skip branch ofs
+ MOV @IP+,PC ;4 14~ taken or not taken xloop/loop
+XLOOPDO MOV @IP,IP
+ MOV @IP+,PC ;4 14~ taken or not taken xloop/loop
+ FORTHWORDIMM "LOOP" ; immediate
+; https://forth-standard.org/standard/core/LOOP
+; LOOP DOadr -- L-- an an-1 .. a1 0
+LOO MOV #XLOOP,X
+LOOPNEXT ADD #4,&DP ; make room to compile two words
+ MOV &DP,W
+ MOV X,-4(W) ; xloop --> HERE
+ MOV TOS,-2(W) ; DOadr --> HERE+2
+; resolve all "leave" adr
+LEAVELOOP MOV &LEAVEPTR,TOS ; -- Adr of top LeaveStack cell
+ SUB #2,&LEAVEPTR ; --
+ MOV @TOS,TOS ; -- first LeaveStack value
+ CMP #0,TOS ; -- = value left by DO ?
+ JZ LOOPEND
+ MOV W,0(TOS) ; move adr after loop as UNLOOP adr
+ JMP LEAVELOOP
+LOOPEND MOV @PSP+,TOS
+ MOV @IP+,PC
+
+; Primitive XPLOOP; compiled by +LOOP
+;Z (+loop) n -- R: sys1 sys2 -- | sys1 sys2
+; run-time code for +LOOP
+; Add n to the loop index. If loop terminates, clean up the
+; return stack and skip the branch. Else take the inline branch.
+XPLOO ADD TOS,0(RSP) ;4 increment INDEX by TOS value
+ MOV @PSP+,TOS ;2 get new TOS, doesn't change flags
+ JMP XLOOPNEXT ;2
+
+ FORTHWORDIMM "+LOOP" ; immediate
+; https://forth-standard.org/standard/core/PlusLOOP
+; +LOOP adrs -- L-- an an-1 .. a1 0
+PLUSLOOP MOV #XPLOO,X
+ JMP LOOPNEXT
+
+ .ENDIF
.IFNDEF II
; https://forth-standard.org/standard/core/I
; I -- n R: sys1 sys2 -- sys1 sys2
MOV @RSP,TOS ;2 index = loopctr - fudge
SUB 2(RSP),TOS ;3
MOV @IP+,PC ;4 13~
+
.ENDIF
+ .IFNDEF CR
+ FORTHWORD "CR"
+; https://forth-standard.org/standard/core/CR
+; CR -- send CR to the output device
+CR MOV @PC+,PC
+ .word BODYCR
+BODYCR mDOCOL ; send CR+LF to the default output device
+ .word XSQUOTE
+ .byte 2,0Dh,0Ah
+ .word TYPE,EXIT
+ .ENDIF
.IFNDEF OVER
;https://forth-standard.org/standard/core/OVER
;C OVER x1 x2 -- x1 x2 x1
MOV @PSP,TOS ; 2 -- x1 (x2) x1
SUB #2,PSP ; 1 -- x1 x2 x1
MOV @IP+,PC ; 4
- .ENDIF
+ .ENDIF
.IFNDEF TOR
; https://forth-standard.org/standard/core/toR
; >R x -- R: -- x push to return stack
TOR PUSH TOS
MOV @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
.IFNDEF UDOTR
;https://forth-standard.org/standard/core/UDotR
;X U.R u n -- display u unsigned in n width
.word TOR,LESSNUM,lit,0,NUM,NUMS,NUMGREATER
.word RFROM,OVER,MINUS,lit,0,MAX,SPACES,TYPE
.word EXIT
- .ENDIF
+ .ENDIF
.IFNDEF CFETCH
;https://forth-standard.org/standard/core/CFetch
;C C@ c-addr -- char fetch char from memory
FORTHWORD "C@"
CFETCH MOV.B @TOS,TOS ;2
MOV @IP+,PC ;4
- .ENDIF
+ .ENDIF
.IFNDEF PLUS
;https://forth-standard.org/standard/core/Plus
;C + n1/u1 n2/u2 -- n3/u3 add n1+n2
FORTHWORD "+"
PLUS ADD @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
.IFNDEF DUMP
;https://forth-standard.org/standard/tools/DUMP
FORTHWORD "DUMP"
DUMP PUSH IP
- PUSH &BASE ; save current base
- MOV #10h,&BASE ; HEX base
+ PUSH &BASEADR ; save current base
+ MOV #10h,&BASEADR ; HEX base
ADD @PSP,TOS ; -- ORG END
- ASMtoFORTH
+ mASM2FORTH
.word SWAP ; -- END ORG
- .word LIT,FFF0h,AND ; -- END ORG_modulo_16
+ .word CR,LIT,4,SPACES ; display line of byte order
+ .word LIT,10h,LIT,0,xdo
+DUMP1 .word II,LIT,3,UDOTR
+ .word xloop,DUMP1 ; -- END ORG
.word xdo ; --
-DUMP1 .word CR
+DUMP2 .word CR ; display a dump line
.word II,lit,4,UDOTR,SPACE ; generate address
-
- .word II,lit,8,PLUS,II,xdo ; display first 8 bytes
-DUMP2 .word II,CFETCH,lit,3,UDOTR
- .word xloop,DUMP2 ; bytes display loop
- .word SPACE
- .word II,lit,10h,PLUS,II,lit,8,PLUS,xdo ; display last 8 bytes
+ .word II,lit,10h,PLUS,II,xdo ; display 16 bytes
DUMP3 .word II,CFETCH,lit,3,UDOTR
.word xloop,DUMP3 ; bytes display loop
- .word SPACE,SPACE
+ .word SPACE,SPACE ; display 2 spaces
.word II,lit,10h,PLUS,II,xdo ; display 16 chars
DUMP4 .word II,CFETCH
- .word lit,7Eh,MIN,FBLANK,MAX,EMIT
+ .word lit,7Eh,MIN,BL,MAX,EMIT
.word xloop,DUMP4 ; chars display loop
- .word lit,10h,xploop,DUMP1 ; line loop
- .word RFROM,lit,BASE,STORE ; restore current base
+ .word lit,10h,xploo,DUMP2 ; line loop
+ .word RFROM,lit,BASEADR,STORE ; restore current base
.word EXIT
-
.ENDIF
- FORTHWORD "{SD_TOOLS}"
- MOV @IP+,PC
-
; read logical sector and dump it
; ----------------------------------;
FORTHWORD "SECTOR." ; sector. -- don't forget to add decimal point to your sector number (if < 65536)
JMP SECTOR ;
; ----------------------------------;
-
; dump current DIR first sector
; ----------------------------------;
FORTHWORD "DIR" ;
MOV &DIRclusterH,TOS ;
JMP CLUSTER
; ----------------------------------;
-
TOR PUSH TOS
MOV @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
.IFNDEF ANDD
;https://forth-standard.org/standard/core/AND
;C AND x1 x2 -- x3 logical AND
FORTHWORD "AND"
ANDD AND @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
.IFNDEF CFETCH
;https://forth-standard.org/standard/core/CFetch
;C C@ c-addr -- char fetch char from memory
FORTHWORD "C@"
CFETCH MOV.B @TOS,TOS ;2
MOV @IP+,PC ;4
- .ENDIF
+ .ENDIF
.IFNDEF ULESS
; https://forth-standard.org/standard/core/Uless
; U< u1 u2 -- flag test u1<u2, unsigned
JNC UTOSTRUE ; 2 flag = true, Z = 0
UTOSFALSE AND #0,TOS ;1 flag Z = 1
MOV @IP+,PC ;4
+
.ENDIF
-
.IFNDEF SPACE
;https://forth-standard.org/standard/core/SPACE
;C SPACE -- output a space
MOV @IP+,PC ;
.ENDIF
-
.IFNDEF TWODUP
; https://forth-standard.org/standard/core/TwoDUP
; 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells
MOV @PSP,-4(PSP) ; 4
SUB #4,PSP ; 1
MOV @IP+,PC ; 4
- .ENDIF
+ .ENDIF
.IFNDEF XDO
; Primitive XDO; compiled by DO
;Z (do) n1|u1 n2|u2 -- R: -- sys1 sys2 run-time code for DO
; +LOOP adrs -- L-- an an-1 .. a1 0
PLUSLOOP MOV #XPLOO,X
JMP LOOPNEXT
- .ENDIF
+ .ENDIF
.IFNDEF II
; https://forth-standard.org/standard/core/I
; I -- n R: sys1 sys2 -- sys1 sys2
MOV @RSP,TOS ;2 index = loopctr - fudge
SUB 2(RSP),TOS ;3
MOV @IP+,PC ;4 13~
- .ENDIF
+ .ENDIF
;https://forth-standard.org/standard/tools/DotS
FORTHWORD ".S" ; -- print <depth> of Param Stack and stack contents if not empty
DOTS MOV TOS,-2(PSP) ; -- TOS ( tos x x )
.word lit,2,xploo,STKDISPL2
.word EXIT
-
FORTHWORD ".RS" ; -- print <depth> of Return Stack and stack contents if not empty
DOTRS MOV TOS,-2(PSP) ; -- TOS ( tos x x )
MOV RSP,-6(PSP) ; -- TOS ( tos x RSP )
QDUP CMP #0,TOS
JZ QDUPEND
JNZ QDUPNEXT
- .ENDIF
+ .ENDIF
.IFNDEF CR
FORTHWORD "CR"
; https://forth-standard.org/standard/core/CR
.word XSQUOTE
.byte 2,0Dh,0Ah
.word TYPE,EXIT
- .ENDIF
+ .ENDIF
.IFNDEF TWODIV
;https://forth-standard.org/standard/core/TwoDiv
;C 2/ x1 -- x2 arithmetic right shift
FORTHWORD "2/"
TWODIV RRA TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
.SWITCH THREADS
.CASE 1
WORDS2 .word EXIT ; --
.ELSECASE
-
.IFNDEF PAD
;https://forth-standard.org/standard/core/PAD
; PAD -- pad address
FORTHWORD "PAD"
PAD CALL rDOCON
.WORD PAD_ORG
- .ENDIF
+ .ENDIF
.IFNDEF ROT
;https://forth-standard.org/standard/core/ROT
;C ROT x1 x2 x3 -- x2 x3 x1
MOV 2(PSP),TOS ; 3 fetch x1
MOV W,2(PSP) ; 3 store x2
MOV @IP+,PC ; 4
- .ENDIF
+ .ENDIF
.IFNDEF MOVE
; https://forth-standard.org/standard/core/MOVE
; MOVE addr1 addr2 u -- smart move
.word EXIT
.ENDCASE
-
-
.IFNDEF MAX
;https://forth-standard.org/standard/core/MAX
MOV @IP+,PC
.ENDIF
-
.IFNDEF PLUS
;https://forth-standard.org/standard/core/Plus
;C + n1/u1 n2/u2 -- n3/u3 add n1+n2
FORTHWORD "+"
PLUS ADD @PSP+,TOS
MOV @IP+,PC
- .ENDIF
+ .ENDIF
.IFNDEF OVER
;https://forth-standard.org/standard/core/OVER
;C OVER x1 x2 -- x1 x2 x1
MOV @PSP,TOS ; 2 -- x1 (x2) x1
SUB #2,PSP ; 1 -- x1 x2 x1
MOV @IP+,PC ; 4
- .ENDIF
+ .ENDIF
.IFNDEF UDOTR
;https://forth-standard.org/standard/core/UDotR
;X U.R u n -- display u unsigned in n width
.word TOR,LESSNUM,lit,0,NUM,NUMS,NUMGREATER
.word RFROM,OVER,MINUS,lit,0,MAX,SPACES,TYPE
.word EXIT
- .ENDIF
+ .ENDIF
.IFNDEF HERE
; https://forth-standard.org/standard/core/HERE
; HERE -- addr returns memory ptr
HERE FORTHWORD "HERE"
MOV #HEREXEC,PC
- .ENDIF
+ .ENDIF
+ .IFNDEF DUMP
;https://forth-standard.org/standard/tools/DUMP
FORTHWORD "DUMP"
DUMP PUSH IP
.word lit,10h,xploo,DUMP1 ; line loop
.word RFROM,lit,BASEADR,STORE ; restore current base
.word EXIT
-
+ .ENDIF
\ #44 $2C MPUSEG2IFG segment 2 memory violation (PUC)
\ #46 $2E MPUSEG3IFG segment 3 memory violation (PUC)
\
-\ emulated SYSRSTIV values added by FastForth SYS
-\ -----------------------------------------------
-\ n SYS ( n<0) : user WIPE = Deep Reset: restores FastForth as it was "flashed"
-\ -3 : reset after FastForth "flashing".
-\ SYS : WARM
-\ n SYS (n even ) : user COLD (don't reuse hardware SYSRSTIV!)
-\ n SYS (n odd ) : user WARM.
+\ emulated SYSRSTIV values added by FastForth
+\ -------------------------------------------
+\ -n SYS : BOR + Deep Reset --> WARM display #-1
+\ <SW1+RESET> : BOR + Deep Reset --> WARM display #-1
+\ SYS : NO PUC --> --> --> WARM display #0
+\ n SYS (n odd ) : NO PUC --> --> --> WARM display #n (odd)
+\ n SYS (n even ) : BOR --> --> --> WARM display #n (even)
+\ <RESET> : BOR --> --> --> WARM display #4
\
\ note
\ ------------------------------------------------------------------------------
\
\ it's an example:
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] DUP [IF]
\ https://forth-standard.org/standard/core/DUP
\ DUP x -- x x duplicate top of stack
- [UNDEFINED] DUP
- [IF]
CODE DUP
BW1 SUB #2,PSP \ 2 push old TOS..
MOV TOS,0(PSP) \ 3 ..onto stack
ENDCODE
[THEN]
+ [UNDEFINED] DROP [IF]
\ https://forth-standard.org/standard/core/DROP
\ DROP x -- drop top of stack
- [UNDEFINED] DROP
- [IF]
CODE DROP
MOV @PSP+,TOS \ 2
MOV @IP+,PC \ 4
ENDCODE
[THEN]
- [UNDEFINED] =
- [IF]
+ [UNDEFINED] = [IF]
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
CODE =
ENDCODE
[THEN]
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
\ https://forth-standard.org/standard/core/Plus
\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
CODE +
ENDCODE
[THEN]
- [UNDEFINED] EXECUTE
- [IF]
+ [UNDEFINED] EXECUTE [IF]
\ https://forth-standard.org/standard/core/EXECUTE
\ EXECUTE i*x xt -- j*x execute Forth word at 'xt'
CODE EXECUTE
ENDCODE
[THEN]
-\ ------------------------------------------------------------------------------
-\ WARNING !
-\ ------------------------------------------------------------------------------
-\ it is not recommended here to compile then execute a definition
-\ because the risk of crushing thereafter.
-\ Interpreting mode as below is required:
-\ ------------------------------------------------------------------------------
- DUP 4 = \ TOS = SYS value
- [IF] \ if PUC event is <SW1+RESET> or -1 SYS
- DROP
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+; ------------------------------------------------------------------------------
+; WARNING !
+; ------------------------------------------------------------------------------
+; it is not recommended here to compile then execute a definition
+; because the risk of crushing thereafter.
+; Interpreting mode as below is required:
+; ------------------------------------------------------------------------------
+
+ DUP 6 = \ TOS = SYS value
+ [IF] \ if <RESET> | 6 SYS
+ DROP \
RST_RET \ remove definitions above
LOAD" SD_TEST.4TH" \ load a file to test the SD_Card driver
[ELSE] \ else
- ' SYS $0A + EXECUTE \ return to n SYS to remove definitions above
+ ' SYS $0E + EXECUTE \ TOS2WARM address, does same as n SYS (n odd)
[THEN] \ then
\
\ COLD \ uncomment for this TEST which must not disrupt the downloading process
+; ------------
+; CHNGBAUD.f
+; ------------
+
+\ first, we do some tests allowing the download
CODE I2CTERM_ABORT
SUB #4,PSP
MOV TOS,2(PSP)
0<> IF MOV #0,TOS THEN \ if TOS <> 0 (UART TERMINAL), set TOS = 0
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
$0D EMIT \ return to column 1 without CR
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" <-- Ouch! unexpected I2C_FastForth target!"
RST_RET \ remove ABORT_UARTI2CS definition before resuming
;
I2CTERM_ABORT
-; ------------
-; CHNGBAUD.f
-; ------------
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
+ [UNDEFINED] DUP [IF] \ define DUP and DUP?
\ https://forth-standard.org/standard/core/DUP
\ DUP x -- x x duplicate top of stack
- [UNDEFINED] DUP [IF] \ define DUP and DUP?
CODE DUP
BW1 SUB #2,PSP \ 2 push old TOS..
MOV TOS,0(PSP) \ 3 ..onto stack
ENDCODE
[THEN]
+ [UNDEFINED] DROP [IF]
\ https://forth-standard.org/standard/core/DROP
\ DROP x -- drop top of stack
- [UNDEFINED] DROP [IF]
CODE DROP
MOV @PSP+,TOS \ 2
MOV @IP+,PC \ 4
ENDCODE
[THEN]
+ [UNDEFINED] OVER [IF]
\ https://forth-standard.org/standard/core/OVER
\ OVER x1 x2 -- x1 x2 x1
- [UNDEFINED] OVER [IF]
CODE OVER
MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
MOV @PSP,TOS \ 2 -- x1 (x2) x1
ENDCODE
[THEN]
+ [UNDEFINED] CR [IF]
\ https://forth-standard.org/standard/core/CR
\ CR -- send CR+LF to the output device
- [UNDEFINED] CR [IF]
- DEFER CR \ DEFERed definition, by default executes that of :NONAME
+
+\ DEFER CR \ DEFERed definition, by default executes that of :NONAME
+ CODE CR
+ MOV #NEXT_ADR,PC \ compile same as DEFER
+ ENDCODE
:NONAME
'CR' EMIT 'LF' EMIT
; IS CR
[THEN]
+ [UNDEFINED] 1+ [IF]
\ https://forth-standard.org/standard/core/OnePlus
\ 1+ n1/u1 -- n2/u2 add 1 to TOS
- [UNDEFINED] 1+ [IF]
CODE 1+
ADD #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
-\ U/ u1 u2 -- q unsigned 16/16->q16
[UNDEFINED] U/ [IF]
+\ U/ u1 u2 -- q unsigned 16/16->q16
CODE U/
SUB #2,PSP
MOV #0,0(PSP) \ -- u1lo u1hi u2
ENDCODE
[THEN]
+ [UNDEFINED] >R [IF]
\ https://forth-standard.org/standard/core/toR
\ >R x -- R: -- x push to return stack
- [UNDEFINED] >R [IF]
CODE >R
PUSH TOS
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] R> [IF]
\ https://forth-standard.org/standard/core/Rfrom
\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
- [UNDEFINED] R> [IF]
CODE R>
SUB #2,PSP \ 1
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] = [IF]
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
- [UNDEFINED] = [IF]
CODE =
SUB @PSP+,TOS \ 2
0<> IF \ 2
ENDCODE
[THEN]
+ [UNDEFINED] < [IF] \ define < and >
\ https://forth-standard.org/standard/core/less
\ < n1 n2 -- flag test n1<n2, signed
- [UNDEFINED] < [IF] \ define < and >
CODE <
SUB @PSP+,TOS \ 1 TOS=n2-n1
S< ?GOTO FW1 \ 2 signed
ENDCODE
[THEN]
+ [UNDEFINED] IF [IF] \ define IF THEN
\ https://forth-standard.org/standard/core/IF
\ IF -- IFadr initialize conditional forward branch
- [UNDEFINED] IF [IF]
CODE IF
SUB #2,PSP \
MOV TOS,0(PSP) \
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] ELSE [IF]
\ https://forth-standard.org/standard/core/ELSE
\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
- [UNDEFINED] ELSE [IF]
CODE ELSE
ADD #4,&DP \ make room to compile two words
MOV &DP,W \ W=HERE+4
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] DO [IF] \ define DO LOOP +LOOP
\ https://forth-standard.org/standard/core/DO
\ DO -- DOadr L: -- 0
- [UNDEFINED] DO
- [IF] \ define DO LOOP +LOOP
HDNCODE XDO \ DO run time
MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor"
SUB @PSP+,X \ 2
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] CASE [IF] \ define CASE OF ENDOF ENDCASE
\ https://forth-standard.org/standard/core/CASE
- [UNDEFINED] CASE [IF]
: CASE 0 ; IMMEDIATE \ -- #of-1
- \ https://forth-standard.org/standard/core/OF
+\ https://forth-standard.org/standard/core/OF
: OF \ #of-1 -- orgOF #of
1+ \ count OFs
>R \ move off the stack in case the control-flow stack is the data stack.
; IMMEDIATE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
[UNDEFINED] S_ [IF]
- CODE S_ \ Squote alias with blank separator instead quote
- MOV #0,&CAPS \ turn CAPS OFF
- COLON
- XSQUOTE , \ compile run-time code
- $20 WORD \ -- c-addr (= HERE)
- HI2LO
- MOV.B @TOS,TOS \ -- len compile string
- ADD #1,TOS \ -- len+1
- BIT #1,TOS \ C = ~Z
- ADDC TOS,&DP \ store aligned DP
- MOV @PSP+,TOS \ --
- MOV @RSP+,IP \ pop paired with push COLON
- MOV #$20,&CAPS \ turn CAPS ON (default state)
- MOV @IP+,PC \ NEXT
+ CODE S_ \ Squote alias with blank instead quote separator
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV #'SP',TOS
+ MOV #S"+10,PC \ addr S" + 10 --> PC
ENDCODE IMMEDIATE
[THEN]
TERMBRW_RST ! \ set UCAxBRW value in FRAM
CR ESC [7m \ escape sequence to set reverse video
." Change baudrate in Teraterm, save its setup, then reset target."
+ ESC [0m
;
CHNGBAUD
\ ASSEMBLER conditionnal usage with IF UNTIL WHILE S< S>= U< U>= 0= 0<> 0>=
\ ASSEMBLER conditionnal usage with ?JMP ?GOTO S< S>= U< U>= 0= 0<> 0<
+; ----------
+; CORDIC.f
+; ----------
+
CODE ABORT_CORDIC
SUB #4,PSP
MOV TOS,2(PSP)
0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT_INPUT), set TOS = 0
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
$0D EMIT \ return to column 1 without CR
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" build FastForth with FIXPOINT_INPUT addon"
RST_RET \ if no abort remove this word
;
ABORT_CORDIC
-; ----------
-; CORDIC.f
-; ----------
-
MARKER {CORDIC}
\ CORDIC USES
39797 ,
39797 ,
+ [UNDEFINED] DABS [IF]
\ https://forth-standard.org/standard/double/DABS
\ DABS d1 -- |d1| absolute value
- [UNDEFINED] DABS
- [IF]
CODE DABS
AND #-1,TOS \ clear V, set N
S< IF \
ENDCODE
[THEN]
+ [UNDEFINED] R> [IF]
\ https://forth-standard.org/standard/core/Rfrom
\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
- [UNDEFINED] R>
- [IF]
CODE R>
SUB #2,PSP \ 1
MOV TOS,0(PSP) \ 3
[IF] ; MSP430FRxxxx with hardware_MPY
+ [UNDEFINED] HOLDS [IF]
\ https://forth-standard.org/standard/core/HOLDS
\ Adds the string represented by addr u to the pictured numeric output string
\ compilation use: <# S" string" HOLDS #>
\ free chars area in the 32+2 bytes HOLD buffer = {26,23,2} chars with a 32 bits sized {hexa,decimal,binary} number.
\ (2 supplementary bytes are room for sign - and decimal point)
\ C HOLDS addr u --
- [UNDEFINED] HOLDS
- [IF]
- CODE HOLDS
- MOV @PSP+,X \ 2 X=src
-BW3 ADD TOS,X \ 1 X=src_end
- MOV &HP,Y \ 3 Y=dst
- BEGIN
- SUB #1,X \ 1 src-1
- SUB #1,TOS \ 1 cnt-1
- U>= WHILE
- SUB #1,Y \ 1 dst-1
- MOV.B @X,0(Y) \ 4
- REPEAT
- MOV Y,&HP \ 3
- MOV @PSP+,TOS \ 2
- MOV @IP+,PC \ 4 15 words
- ENDCODE
+ CODE HOLDS
+ MOV @PSP+,X \ 2 X=src
+BW3 ADD TOS,X \ 1 X=src_end
+ MOV &HP,Y \ 3 Y=dst
+ BEGIN
+ SUB #1,X \ 1 src-1
+ SUB #1,TOS \ 1 cnt-1
+ U>= WHILE
+ SUB #1,Y \ 1 dst-1
+ MOV.B @X,0(Y) \ 4
+ REPEAT
+ MOV Y,&HP \ 3
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4 15 words
+ ENDCODE
[THEN]
+ [UNDEFINED] F#S [IF]
\ F#S Qlo Qhi u -- Qhi 0 convert fractionnal part of Q15.16 fixed point number
\ with u digits
- [UNDEFINED] F#S
- [IF]
- CODE F#S
- MOV 2(PSP),X \ -- Qlo Qhi u X = Qlo
- MOV @PSP,2(PSP) \ -- Qhi Qhi u
- MOV X,0(PSP) \ -- Qhi Qlo u
- MOV TOS,T \ T = len
- MOV #0,S \ S = count
- BEGIN MOV @PSP,&MPY \ Load 1st operand
- MOV &BASEADR,&OP2 \ Load 2nd operand
- MOV &RES0,0(PSP) \ -- Qhi RESlo x low result on stack
- MOV &RES1,TOS \ -- Qhi RESlo REShi high result in TOS
- CMP #10,TOS \ digit to char
- U>= IF ADD #7,TOS
- THEN ADD #$30,TOS
- MOV.B TOS,HOLDS_ORG(S) \ -- Qhi RESlo char char to string
- ADD #1,S \ count+1
- CMP T,S \ count=len ?
- 0= UNTIL MOV T,TOS \ -- len RESlo len
- MOV #0,0(PSP) \ -- Qhi 0 len
- MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG
- GOTO BW3 \ 35~ JMP HOLDS+2
- ENDCODE
+ CODE F#S
+ MOV 2(PSP),X \ -- Qlo Qhi u X = Qlo
+ MOV @PSP,2(PSP) \ -- Qhi Qhi u
+ MOV X,0(PSP) \ -- Qhi Qlo u
+ MOV TOS,T \ T = len
+ MOV #0,S \ S = count
+ BEGIN
+ MOV @PSP,&MPY \ Load 1st operand
+ MOV &BASEADR,&OP2 \ Load 2nd operand
+ MOV &RES0,0(PSP) \ -- Qhi RESlo x low result on stack
+ MOV &RES1,TOS \ -- Qhi RESlo REShi high result in TOS
+ CMP #10,TOS \ digit to char
+ U>= IF
+ ADD #7,TOS
+ THEN
+ ADD #$30,TOS
+ MOV.B TOS,HOLDS_ORG(S) \ -- Qhi RESlo char char to string
+ ADD #1,S \ count+1
+ CMP T,S \ count=len ?
+ 0= UNTIL
+ MOV T,TOS \ -- len RESlo len
+ MOV #0,0(PSP) \ -- Qhi 0 len
+ MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG
+ GOTO BW3 \ 35~ JMP HOLDS+2
+ ENDCODE
[THEN]
- HDNCODE XSCALE \ X = X*Cordic_Gain
- MOV T_SCALE(W),&MPYS32L \ 3 CORDIC Gain * 65536
- MOV #0,&MPYS32H
- MOV X,&OP2 \ 3 Load 1st operand
- MOV &RES1,X \ 3 hi result
- MOV @RSP+,PC \ RET
- ENDCODE
+ HDNCODE XSCALE \ X = X*Cordic_Gain
+ MOV T_SCALE(W),&MPYS32L \ 3 CORDIC Gain * 65536
+ MOV #0,&MPYS32H
+ MOV X,&OP2 \ 3 Load 1st operand
+ MOV &RES1,X \ 3 hi result
+ MOV @RSP+,PC \ RET
+ ENDCODE
[ELSE] ; no hardware multiplier
\ C HOLDS addr u --
[UNDEFINED] HOLDS
[IF]
- CODE HOLDS
- MOV @PSP+,X \ 2 X=src
-BW3 ADD TOS,X \ 1 X=src_end
- MOV &HP,Y \ 3 Y=dst
- BEGIN
- SUB #1,X \ 1 src-1
- SUB #1,TOS \ 1 cnt-1
- U>= WHILE
- SUB #1,Y \ 1 dst-1
- MOV.B @X,0(Y) \ 4
- REPEAT
- MOV Y,&HP \ 3
- MOV @PSP+,TOS \ 2
- MOV @IP+,PC \ 4 15 words
- ENDCODE
+ CODE HOLDS
+ MOV @PSP+,X \ 2 X=src
+BW3 ADD TOS,X \ 1 X=src_end
+ MOV &HP,Y \ 3 Y=dst
+ BEGIN
+ SUB #1,X \ 1 src-1
+ SUB #1,TOS \ 1 cnt-1
+ U>= WHILE
+ SUB #1,Y \ 1 dst-1
+ MOV.B @X,0(Y) \ 4
+ REPEAT
+ MOV Y,&HP \ 3
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4 15 words
+ ENDCODE
[THEN]
\ F#S Qlo Qhi len -- Qhi 0 convert fractional part Qlo of Q15.16 fixed point number
\ with len digits
[UNDEFINED] F#S
[IF]
- CODE F#S
- MOV @PSP,S \ -- Qlo Qhi len S = Qhi
- MOV #0,T \ T = count
- PUSHM #3,IP \ R-- IP Qhi count
- MOV 2(PSP),0(PSP) \ -- Qlo Qlo len
- MOV TOS,2(PSP) \ -- len Qlo len
- BEGIN MOV &BASEADR,TOS \ -- len Qlo base
- LO2HI
- UM* \ u1 u2 -- RESlo REShi
- HI2LO \ -- len RESlo digit
- CMP #10,TOS \ digit to char
- U>= IF ADD #7,TOS
- THEN ADD #$30,TOS \ -- len RESlo char
- MOV @RSP,T \ T=count
- MOV.B TOS,HOLDS_ORG(T) \ char to string_org(T)
- ADD #1,T \ count+1
- MOV T,0(RSP) \
- CMP 2(PSP),T \ -- len RESlo char count=len ?
- U>= UNTIL POPM #3,IP \ S=Qhi, T=len
- MOV T,TOS \ -- len RESlo len
- MOV S,2(PSP) \ -- Qhi RESlo len
- MOV #0,0(PSP) \ -- Qhi 0 len
- MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG
- GOTO BW3 \ 36~ JMP HOLDS
- ENDCODE
+ CODE F#S
+ MOV @PSP,S \ -- Qlo Qhi len S = Qhi
+ MOV #0,T \ T = count
+ PUSHM #3,IP \ R-- IP Qhi count
+ MOV 2(PSP),0(PSP) \ -- Qlo Qlo len
+ MOV TOS,2(PSP) \ -- len Qlo len
+ BEGIN
+ MOV &BASEADR,TOS \ -- len Qlo base
+ LO2HI
+ UM* \ u1 u2 -- RESlo REShi
+ HI2LO \ -- len RESlo digit
+ CMP #10,TOS \ digit to char
+ U>= IF
+ ADD #7,TOS
+ THEN
+ ADD #$30,TOS \ -- len RESlo char
+ MOV @RSP,T \ T=count
+ MOV.B TOS,HOLDS_ORG(T) \ char to string_org(T)
+ ADD #1,T \ count+1
+ MOV T,0(RSP) \
+ CMP 2(PSP),T \ -- len RESlo char count=len ?
+ U>= UNTIL
+ POPM #3,IP \ S=Qhi, T=len
+ MOV T,TOS \ -- len RESlo len
+ MOV S,2(PSP) \ -- Qhi RESlo len
+ MOV #0,0(PSP) \ -- Qhi 0 len
+ MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG
+ GOTO BW3 \ 36~ JMP HOLDS
+ ENDCODE
[THEN]
\ T.I. UNSIGNED MULTIPLY SUBROUTINE: U1 x U2 -> Ud
\ https://forth-standard.org/standard/core/UMTimes
\ UM* u1 u2 -- ud unsigned 16x16->32 mult.
- HDNCODE XSCALE \ X --> X*Cordic_Gain
- MOV T_SCALE(W),rDOCON \ rDOCON=MR, X=MDlo
- UMSTAR1 MOV #0,Y \ 1 MDhi=0
- MOV #0,S \ 1 RES0=0
- MOV #0,T \ 1 RES1=0
- MOV #1,W \ 1 BIT TEST REGISTER
- BEGIN BIT W,rDOCON \ 1 TEST ACTUAL BIT MRlo
- 0<> IF ADD X,S \ 1 IF 1: ADD MDlo TO RES0
- ADDC Y,T \ 1 ADDC MDhi TO RES1
- THEN ADD X,X \ 1 (RLA LSBs) MDlo x 2
- ADDC Y,Y \ 1 (RLC MSBs) MDhi x 2
- ADD W,W \ 1 (RLA) NEXT BIT TO TEST
- U>= UNTIL \ S = RESlo, T=REShi
- MOV T,X \ 2 IF BIT IN CARRY: FINISHED 10~ loop
- MOV #XDOCON,rDOCON \ restore rDOCON
- MOV @RSP+,PC \ RET
- ENDCODE
+ HDNCODE XSCALE \ X --> X*Cordic_Gain
+ MOV T_SCALE(W),rDOCON \ rDOCON=MR, X=MDlo
+ MOV #0,Y \ 1 MDhi=0
+ MOV #0,S \ 1 RES0=0
+ MOV #0,T \ 1 RES1=0
+ MOV #1,W \ 1 BIT TEST REGISTER
+ BEGIN
+ BIT W,rDOCON \ 1 TEST ACTUAL BIT MRlo
+ 0<> IF
+ ADD X,S \ 1 IF 1: ADD MDlo TO RES0
+ ADDC Y,T \ 1 ADDC MDhi TO RES1
+ THEN
+ ADD X,X \ 1 (RLA LSBs) MDlo x 2
+ ADDC Y,Y \ 1 (RLC MSBs) MDhi x 2
+ ADD W,W \ 1 (RLA) NEXT BIT TO TEST
+ U>= UNTIL \ S = RESlo, T=REShi
+ MOV T,X \ 2 IF BIT IN CARRY: FINISHED 10~ loop
+ MOV #XDOCON,rDOCON \ restore rDOCON
+ MOV @RSP+,PC \ RET
+ ENDCODE
[THEN] ; endcase of hardware multiplier
ENDCODE
- [UNDEFINED] F.
- [IF]
+ [UNDEFINED] F. [IF]
CODE F. \ display a Q15.16 number with 4/5/16 digits after comma
MOV TOS,S \ S = sign
MOV #4,T \ T = 4 preset 4 digits for base 16 and by default
\ https://forth-standard.org/standard/core/SWAP
\ SWAP x1 x2 -- x2 x1 swap top two items
- [UNDEFINED] SWAP
- [IF]
+ [UNDEFINED] SWAP [IF]
CODE SWAP
MOV @PSP,W \ 2
MOV TOS,0(PSP) \ 3
\ https://forth-standard.org/standard/core/ROT
\ ROT x1 x2 x3 -- x2 x3 x1
- [UNDEFINED] ROT
- [IF] \
+ [UNDEFINED] ROT [IF] \
CODE ROT
MOV @PSP,W \ 2 fetch x2
MOV TOS,0(PSP) \ 3 store x3
\ ; CORETEST.4TH for any FastForth target
\ ; -------------------------------------
-MARKER {CORETEST}
+ MARKER {CORETEST}
-: ABORT_TEST \ flag --
-$0D EMIT \ return to column 1
-POSTPONE {CORETEST} \ remove all test words
-ABORT" {CORE_ANS} word set not found !"
-;
+ : ABORT_TEST \ flag --
+ $0D EMIT \ return to column 1, no 'LF'
+ POSTPONE {CORETEST} \ remove all test words
+ ABORT" {CORE_ANS} word set not found !"
+ ;
-[UNDEFINED] {CORE_ANS} ABORT_TEST
+ [UNDEFINED] {CORE_ANS} ABORT_TEST
-: CORETESTSUCCESS
-$0D EMIT \ -- $0D return to column 1
-$0A BASE ! \ set decimal
-{CORETEST} \ remove all test words
-." CORETEST + COREPLUSTEST success!" \ true --
-;
+ : CORETESTSUCCESS
+ $0D DUP EMIT \ return to column 1, set true flag for ABORT"
+ $0A BASE ! \ set decimal
+ {CORETEST} \ remove all test words
+ ABORT" CORETEST + COREPLUSTEST success!" \ true_flag --
+ ;
-[UNDEFINED] SM/REM [IF]
-CODE SM/REM
-MOV R14,R12
-MOV @R15,R11
-CMP #0,R14
-S< IF
- XOR #-1,R14
- ADD #1,R14
-THEN
-CMP #0,0(R15)
-S< IF
- XOR #-1,2(R15)
- XOR #-1,0(R15)
- ADD #1,2(R15)
- ADDC #0,0(R15)
-THEN
-PUSHM #3,R13
-LO2HI
- UM/MOD
-HI2LO
-POPM #3,R13
-CMP #0,R11
-S< IF
- XOR #-1,0(R15)
- ADD #1,0(R15)
-THEN
-XOR R12,R11
-CMP #0,R11
-S< IF
- XOR #-1,R14
- ADD #1,R14
-THEN
-MOV @R13+,R0
-ENDCODE
-[THEN]
-
-[UNDEFINED] FM/MOD [IF]
+ [UNDEFINED] SM/REM [IF]
+\ https://forth-standard.org/standard/core/SMDivREM
+\ SM/REM d1 n1 -- r q symmetric signed div'n
+ CODE SM/REM
+ MOV R14,R12
+ MOV @R15,R11
+ CMP #0,R14
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ CMP #0,0(R15)
+ S< IF
+ XOR #-1,2(R15)
+ XOR #-1,0(R15)
+ ADD #1,2(R15)
+ ADDC #0,0(R15)
+ THEN
+ PUSHM #3,R13
+ LO2HI
+ UM/MOD
+ HI2LO
+ POPM #3,R13
+ CMP #0,R11
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ THEN
+ XOR R12,R11
+ CMP #0,R11
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] FM/MOD [IF]
\ https://forth-standard.org/standard/core/FMDivMOD
\ FM/MOD d1 n1 -- r q floored signed div'n
-: FM/MOD
-SM/REM
-HI2LO \ -- remainder quotient S=divisor
-CMP #0,0(R15) \ remainder <> 0 ?
-0<> IF
- CMP #1,R14 \ quotient < 1 ?
- S< IF
- ADD R12,0(R15) \ add divisor to remainder
- SUB #1,R14 \ decrement quotient
+ : FM/MOD
+ SM/REM
+ HI2LO \ -- remainder quotient S=divisor
+ CMP #0,0(R15) \ remainder <> 0 ?
+ 0<> IF
+ CMP #1,R14 \ quotient < 1 ?
+ S< IF
+ ADD R12,0(R15) \ add divisor to remainder
+ SUB #1,R14 \ decrement quotient
+ THEN
THEN
-THEN
-MOV @R1+,R13
-MOV @R13+,R0
-ENDCODE
-[THEN]
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
\ From: John Hayes S1I
\ Subject: tester.fr
FALSE VERBOSE !
\ TRUE VERBOSE !
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ \ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
+: EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
+ DEPTH ?DUP
+ IF DUP 0< IF NEGATE 0
+ DO 0 LOOP
+ ELSE 0 DO DROP LOOP THEN
+ THEN ;
+
+: ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
+ \ THE LINE THAT HAD THE ERROR.
+ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
+ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
+ QUIT \ *** Uncomment this line to QUIT on an error
+;
VARIABLE ACTUAL-DEPTH \ STACK RECORD
CREATE ACTUAL-RESULTS 20 CELLS ALLOT
0 DO \ FOR EACH STACK ITEM
ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF TRUE ABORT" INCORRECT RESULT" THEN \ jmt : abort with colorised message
+ = 0= ABORT" INCORRECT RESULT" \ jmt : abort with colorised message
LOOP
THEN
ELSE \ DEPTH MISMATCH
: TESTING \ ( -- ) TALKING COMMENT.
SOURCE VERBOSE @
IF DUP >R TYPE CR R> >IN !
-\ ELSE >IN ! DROP [CHAR] * EMIT
- ELSE >IN ! DROP \ [CHAR] * EMIT
+ ELSE >IN ! DROP [CHAR] * EMIT
THEN ;
-ECHO HEX
+HEX
\ From: John Hayes S1I
\ Subject: core.fr
( TEST IF ANY BITS ARE SET; ANSWER IN BASE 1 )
T{ : BITSSET? IF 0 0 ELSE 0 THEN ; -> }T
T{ 0 BITSSET? -> 0 }T ( ZERO IS ALL BITS CLEAR )
-T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
+T{ 1 BITSSET? -> 0 0 }T ( OTHER NUMBER HAVE AT LEAST ONE BIT )
T{ -1 BITSSET? -> 0 0 }T
\ ------------------------------------------------------------------------
T{ 0S 2/ -> 0S }T
T{ 1 2/ -> 0 }T
T{ 4000 2/ -> 2000 }T
-T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
+T{ 1S 2/ -> 1S }T \ MSB PROPOGATED
T{ 1S 1 XOR 2/ -> 1S }T
T{ MSB 2/ MSB AND -> MSB }T
T{ 3 GI6 -> 0 1 2 3 }T
T{ 4 GI6 -> 0 1 2 3 4 }T
-\ ------------------------------------------------------------------------
+\ ----------------------------------------------------------------------------
TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
T{ : GD1 DO I LOOP ; -> }T
: ACCEPT-TEST
CR ." PLEASE TYPE UP TO 80 CHARACTERS: "
-ABUF 80 \ ACCEPT \ JMT
- ['] ACCEPT >BODY \ JMT: find default part of deferred ACCEPT
- EXECUTE \ JMT: execute ACCEPT
+ ABUF 80 ACCEPT
CR ." RECEIVED: " [CHAR] " EMIT
ABUF SWAP TYPE [CHAR] " EMIT CR
;
T{ ACCEPT-TEST -> }T
\ ZYXWVUTSRQPONMLKJIHGFEDCBAzyxwvutsrqponmlkjihgfedcba
-\ ------------------------------------------------------------------------
+ \ ------------------------------------------------------------------------
TESTING DICTIONARY SEARCH RULES
T{ : GDX 123 ; : GDX GDX 234 ; -> }T
T{ MA0 -> }T
T{ MA? MA0 MA? MA1 MA? MA2 -> FALSE FALSE FALSE }T
+ECHO
CORETESTSUCCESS
\ (used by preprocessor GEMA to load the pattern: \inc\TARGET.pat)
\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
\ MSP_EXP430FR4133 CHIPSTICK_FR2433 MSP_EXP430FR2433 MSP_EXP430FR2355
+\ LP_MSP430FR2476
+\ MY_MSP430FR5738_2
\
\ from scite editor : copy your target selection in (shift+F8) parameter 1:
\
SUB #2,PSP
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
- $0D EMIT \ return to column 1 without CR
- ABORT" FastForth V3.9 please!"
+ 'CR' EMIT \ return to column 1, no 'LF'
+ ABORT" FastForth V4.0 please!"
;
ABORT_CORE_ANS
+ [UNDEFINED] BC! [IF]
\ BC! pattern @ -- Bits Clear in @
- [UNDEFINED] BC!
- [IF]
CODE BC!
BIC @PSP+,0(TOS)
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] BS! [IF]
\ BS! pattern @ -- Bits Set in @
- [UNDEFINED] BS!
- [IF]
CODE BS!
BIS @PSP+,0(TOS)
MOV @PSP+,TOS
[THEN]
\ =============================================================================
-\ $8000 KERNEL_ADDON BS! \ uncomment to select FLOORED division
$8000 KERNEL_ADDON BC! \ uncomment to select SYMMETRIC division
+\ $8000 KERNEL_ADDON BS! \ uncomment to select FLOORED division
\ =============================================================================
RST_RET \ remove all above before CORE_ANS downloading
\
\ words complement to pass CORETEST.4TH
- MARKER {CORE_ANS} \ if already defined removes it before.
+ [DEFINED] {CORE_ANS}
+ [IF] {CORE_ANS} [THEN] \ if already defined removes it before.
- [UNDEFINED] HERE
- [IF]
+ [UNDEFINED] {CORE_ANS} [IF]
+
+ MARKER {CORE_ANS}
+
+ [UNDEFINED] ABORT [IF]
+\ https://forth-standard.org/standard/core/ABORT
+\ Empty the data stack and perform the function of QUIT
+ CODE ABORT
+ MOV #ABORT,PC \ addr defined in MSP430FRxxxx.pat
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] QUIT [IF]
+\ https://forth-standard.org/standard/core/QUIT
+\ Empty the return stack, store zero in SOURCE-ID if it is present,
+\ make the user input device the input source, and enter interpretation state.
+\ Do not display a message. Repeat the following:
+\ Accept a line from the input source into the input buffer, set >IN to zero, and interpret.
+\ Display the implementation-defined system prompt if in interpretation state,
+\ all processing has been completed,
+\ and no ambiguous condition exists.
+ CODE QUIT
+ MOV #QUIT,PC \ addr defined in MSP430FRxxxx.pat
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] HERE [IF]
+\ https://forth-standard.org/standard/core/HERE
+\ HERE -- addr addr is the data-space pointer.
CODE HERE
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC \ execute ASM BEGIN
ENDCODE
[THEN]
+ [UNDEFINED] + [IF]
\ https://forth-standard.org/standard/core/Plus
\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
- [UNDEFINED] +
- [IF]
CODE +
ADD @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] - [IF]
\ https://forth-standard.org/standard/core/Minus
\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
- [UNDEFINED] -
- [IF]
CODE -
SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3)
XOR #-1,TOS \ 1
ENDCODE
[THEN]
+ [UNDEFINED] DUP [IF] \ define DUP and ?DUP
+
\ https://forth-standard.org/standard/core/DUP
\ DUP x -- x x duplicate top of stack
- [UNDEFINED] DUP
- [IF]
CODE DUP
BW1 SUB #2,PSP \ 2 push old TOS..
MOV TOS,0(PSP) \ 3 ..onto stack
ENDCODE
[THEN]
+ [UNDEFINED] EXIT [IF]
\ https://forth-standard.org/standard/core/EXIT
\ EXIT -- exit a colon definition
- [UNDEFINED] EXIT
- [IF]
CODE EXIT
MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack
MOV @IP+,PC \ 4 = NEXT
ENDCODE
[THEN]
+ [UNDEFINED] DEPTH [IF]
\ https://forth-standard.org/standard/core/DEPTH
\ DEPTH -- +n number of items on stack, must leave 0 if stack empty
- [UNDEFINED] DEPTH
- [IF]
CODE DEPTH
MOV TOS,-2(PSP)
MOV #PSTACK,TOS
ENDCODE
[THEN]
+ [UNDEFINED] SWAP [IF]
\ https://forth-standard.org/standard/core/SWAP
\ SWAP x1 x2 -- x2 x1 swap top two items
- [UNDEFINED] SWAP
- [IF]
CODE SWAP
PUSH TOS \ 3
MOV @PSP,TOS \ 2
ENDCODE
[THEN]
+ [UNDEFINED] DROP [IF]
\ https://forth-standard.org/standard/core/DROP
\ DROP x -- drop top of stack
- [UNDEFINED] DROP
- [IF]
CODE DROP
MOV @PSP+,TOS \ 2
MOV @IP+,PC \ 4
ENDCODE
[THEN]
+ [UNDEFINED] OVER [IF]
\ https://forth-standard.org/standard/core/OVER
\ OVER x1 x2 -- x1 x2 x1
- [UNDEFINED] OVER
- [IF]
CODE OVER
MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
MOV @PSP,TOS \ 2 -- x1 (x2) x1
ENDCODE
[THEN]
+ [UNDEFINED] NIP [IF]
\ https://forth-standard.org/standard/core/NIP
\ NIP x1 x2 -- x2 Drop the first item below the top of stack
- [UNDEFINED] NIP
- [IF]
CODE NIP
ADD #2,PSP
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] >R [IF]
\ https://forth-standard.org/standard/core/toR
\ >R x -- R: -- x push to return stack
- [UNDEFINED] >R
- [IF]
CODE >R
PUSH TOS
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] R> [IF]
\ https://forth-standard.org/standard/core/Rfrom
\ R> -- x R: x -- pop from return stack
- [UNDEFINED] R>
- [IF]
CODE R>
SUB #2,PSP \ 1
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/Fetch
-\ @ c-addr -- word fetch word from memory
- [UNDEFINED] @
- [IF]
- CODE @
- MOV @TOS,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
-
-\ https://forth-standard.org/standard/core/Store
-\ ! word c-addr -- store word in memory
- [UNDEFINED] !
- [IF]
- CODE !
- MOV @PSP+,0(TOS) \ 4
- MOV @PSP+,TOS \ 2
- MOV @IP+,PC
- ENDCODE
- [THEN]
-
+ [UNDEFINED] C@ [IF]
\ https://forth-standard.org/standard/core/Fetch
\ C@ c-addr -- char fetch char from memory
- [UNDEFINED] C@
- [IF]
CODE C@
MOV.B @TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] C! [IF]
\ https://forth-standard.org/standard/core/CStore
\ C! char c-addr -- store char in memory
- [UNDEFINED] C!
- [IF]
CODE C!
MOV.B @PSP+,0(TOS) \ 4
ADD #1,PSP \ 1
ENDCODE
[THEN]
+ [UNDEFINED] C, [IF]
\ https://forth-standard.org/standard/core/CComma
\ C, char -- append char
- [UNDEFINED] C,
- [IF]
CODE C,
MOV &DP,W
MOV.B TOS,0(W)
ENDCODE
[THEN]
+ [UNDEFINED] 0= [IF]
\ https://forth-standard.org/standard/core/ZeroEqual
\ 0= n/u -- flag return true if TOS=0
- [UNDEFINED] 0=
- [IF]
CODE 0=
SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0
SUBC TOS,TOS \ 1 TOS=-1 if borrow was set
ENDCODE
[THEN]
+ [UNDEFINED] 0<> [IF]
\ https://forth-standard.org/standard/core/Zerone
\ 0<> n/u -- flag return true if TOS<>0
- [UNDEFINED] 0<>
- [IF]
CODE 0<>
SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0
SUBC TOS,TOS \ 1 TOS=-1 if borrow was set
ENDCODE
[THEN]
+ [UNDEFINED] 0< [IF]
\ https://forth-standard.org/standard/core/Zeroless
\ 0< n -- flag true if TOS negative
- [UNDEFINED] 0<
- [IF]
CODE 0<
-BW1 ADD TOS,TOS \ 1 set carry if TOS negative
+ ADD TOS,TOS \ 1 set carry if TOS negative
SUBC TOS,TOS \ 1 TOS=-1 if carry was clear
XOR #-1,TOS \ 1 TOS=-1 if carry was set
MOV @IP+,PC \
ENDCODE
[THEN]
-\ HERE
-
+ [UNDEFINED] S>D [IF]
\ https://forth-standard.org/standard/core/StoD
\ S>D n -- d single -> double prec.
- [UNDEFINED] S>D
- [IF]
: S>D
DUP 0<
;
[THEN]
+ [UNDEFINED] = [IF]
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
- [UNDEFINED] =
- [IF]
CODE =
SUB @PSP+,TOS \ 2
SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/Uless
-\ U< u1 u2 -- flag test u1<u2, unsigned
- [UNDEFINED] U<
- [IF]
-
- CODE U<
- SUB @PSP+,TOS \ 2 u2-u1
- U< ?GOTO FW1
- 0<> IF
-BW1 MOV #-1,TOS \ 1
- THEN
- MOV @IP+,PC \ 4
- ENDCODE
+ [UNDEFINED] U< [IF] \ define U< and U>
\ https://forth-standard.org/standard/core/Umore
\ U> n1 n2 -- flag
CODE U>
SUB @PSP+,TOS \ 2
- U< ?GOTO BW1 \ 2 flag = true, Z = 0
-FW1 AND #0,TOS \ 1 Z = 1
+ U< ?GOTO FW1 \ 2 flag = true, Z = 0
+BW1 AND #0,TOS \ 1 Z = 1
MOV @IP+,PC \ 4
ENDCODE
- [THEN]
-\ https://forth-standard.org/standard/core/less
-\ < n1 n2 -- flag test n1<n2, signed
- [UNDEFINED] <
- [IF] \ define < and >
-
- CODE <
- SUB @PSP+,TOS \ 1 TOS=n2-n1
- S< ?GOTO FW1 \ 2 signed
- 0<> IF \ 2
-BW1 MOV #-1,TOS \ 1 flag Z = 0
- THEN
- MOV @IP+,PC
+\ https://forth-standard.org/standard/core/Uless
+\ U< u1 u2 -- flag test u1<u2, unsigned
+ CODE U<
+ SUB @PSP+,TOS \ 2 u2-u1
+ 0= ?GOTO BW1
+ U< ?GOTO BW1
+FW1 MOV #-1,TOS \ 1
+ MOV @IP+,PC \ 4
ENDCODE
+ [THEN]
+
+ [UNDEFINED] < [IF] \ define < and >
\ https://forth-standard.org/standard/core/more
\ > n1 n2 -- flag test n1>n2, signed
CODE >
SUB @PSP+,TOS \ 2 TOS=n2-n1
- S< ?GOTO BW1 \ 2 --> +5
-FW1 AND #0,TOS \ 1 flag Z = 1
+ S< ?GOTO FW1 \ 2 --> +5
+BW1 AND #0,TOS \ 1 flag Z = 1
+ MOV @IP+,PC
+ ENDCODE
+
+\ https://forth-standard.org/standard/core/less
+\ < n1 n2 -- flag test n1<n2, signed
+ CODE <
+ SUB @PSP+,TOS \ 1 TOS=n2-n1
+ 0= ?GOTO BW1
+ S< ?GOTO BW1 \ 2 signed
+FW1 MOV #-1,TOS \ 1 flag Z = 0
MOV @IP+,PC
ENDCODE
[THEN]
\ IF, ELSE, AGAIN, UNTIL, WHILE, REPEAT, LOOP & +LOOP compile two words
\ LEAVE compile three words
\
+ [UNDEFINED] IF [IF] \ define IF THEN
+
\ https://forth-standard.org/standard/core/IF
\ IF -- IFadr initialize conditional forward branch
- [UNDEFINED] IF
- [IF] \ define IF THEN
-
CODE IF
SUB #2,PSP \
MOV TOS,0(PSP) \
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] ELSE [IF]
\ https://forth-standard.org/standard/core/ELSE
\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
- [UNDEFINED] ELSE
- [IF]
CODE ELSE
ADD #4,&DP \ make room to compile two words
MOV &DP,W \ W=HERE+4
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
+
\ https://forth-standard.org/standard/core/BEGIN
\ BEGIN -- BEGINadr initialize backward branch
- [UNDEFINED] BEGIN
- [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
-
CODE BEGIN
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC \ execute ASM BEGIN !
ENDCODE IMMEDIATE
\ https://forth-standard.org/standard/core/UNTIL
; IMMEDIATE
[THEN]
- [UNDEFINED] DO
- [IF] \ define DO LOOP +LOOP
+ [UNDEFINED] DO [IF] \ define DO LOOP +LOOP
-\ https://forth-standard.org/standard/core/DO
-\ DO -- DOadr L: -- 0
HDNCODE XDO \ DO run time
MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor"
SUB @PSP+,X \ 2
MOV @IP+,PC \ 4
ENDCODE
+\ https://forth-standard.org/standard/core/DO
+\ DO -- DOadr L: -- 0
CODE DO
SUB #2,PSP \
MOV TOS,0(PSP) \
MOV @IP+,PC
ENDCODE IMMEDIATE
-\ https://forth-standard.org/standard/core/LOOP
-\ LOOP DOadr -- L-- an an-1 .. a1 0
HDNCODE XLOOP \ LOOP run time
ADD #1,0(RSP) \ 4 increment INDEX
BW1 BIT #$100,SR \ 2 is overflow bit set?
MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop
ENDCODE \
+\ https://forth-standard.org/standard/core/LOOP
+\ LOOP DOadr -- L-- an an-1 .. a1 0
CODE LOOP
MOV #XLOOP,X
BW2 ADD #4,&DP \ make room to compile two words
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] I [IF]
\ https://forth-standard.org/standard/core/I
\ I -- n R: sys1 sys2 -- sys1 sys2
\ get the innermost loop index
- [UNDEFINED] I
- [IF]
CODE I
SUB #2,PSP \ 1 make room in TOS
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] J [IF]
\ https://forth-standard.org/standard/core/J
\ J -- n R: 4*sys -- 4*sys
\ C get the second loop index
- [UNDEFINED] J
- [IF]
CODE J
SUB #2,PSP
MOV TOS,0(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] UNLOOP [IF]
\ https://forth-standard.org/standard/core/UNLOOP
\ UNLOOP -- R: sys1 sys2 -- drop loop parms
- [UNDEFINED] UNLOOP
- [IF]
CODE UNLOOP
ADD #4,RSP
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] LEAVE [IF]
\ https://forth-standard.org/standard/core/LEAVE
\ LEAVE -- L: -- adrs
- [UNDEFINED] LEAVE
- [IF]
CODE LEAVE
MOV &DP,W \ compile three words
MOV #UNLOOP,0(W) \ [HERE] = UNLOOP
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] AND [IF]
\ https://forth-standard.org/standard/core/AND
\ C AND x1 x2 -- x3 logical AND
- [UNDEFINED] AND
- [IF]
CODE AND
AND @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] OR [IF]
\ https://forth-standard.org/standard/core/OR
\ C OR x1 x2 -- x3 logical OR (BIS, BIts Set)
- [UNDEFINED] OR
- [IF]
CODE OR
BIS @PSP+,TOS
AND #-1,TOS \ to set flags
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/XOR
-\ C XOR x1 x2 -- x3 logical XOR
[UNDEFINED] XOR
[IF]
+\ https://forth-standard.org/standard/core/XOR
+\ C XOR x1 x2 -- x3 logical XOR
CODE XOR
XOR @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] 1+ [IF]
\ https://forth-standard.org/standard/core/OnePlus
\ 1+ n1/u1 -- n2/u2 add 1 to TOS
- [UNDEFINED] 1+
- [IF]
CODE 1+
ADD #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] 1- [IF]
\ https://forth-standard.org/standard/core/OneMinus
\ 1- n1/u1 -- n2/u2 subtract 1 from TOS
- [UNDEFINED] 1-
- [IF]
CODE 1-
SUB #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] INVERT [IF]
\ https://forth-standard.org/standard/core/INVERT
\ INVERT x1 -- x2 bitwise inversion
- [UNDEFINED] INVERT
- [IF]
CODE INVERT
XOR #-1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] NEGATE [IF]
\ https://forth-standard.org/standard/core/NEGATE
\ C NEGATE x1 -- x2 two's complement
- [UNDEFINED] NEGATE
- [IF]
CODE NEGATE
XOR #-1,TOS
ADD #1,TOS
ENDCODE
[THEN]
+ [UNDEFINED] ABS [IF]
\ https://forth-standard.org/standard/core/ABS
\ C ABS n1 -- +n2 absolute value
- [UNDEFINED] ABS
- [IF]
CODE ABS
CMP #0,TOS \ 1
0>= IF
ENDCODE
[THEN]
+ [UNDEFINED] LSHIFT [IF]
\ https://forth-standard.org/standard/core/LSHIFT
\ LSHIFT x1 u -- x2 logical L shift u places
- [UNDEFINED] LSHIFT
- [IF]
CODE LSHIFT
MOV @PSP+,W
AND #$1F,TOS \ no need to shift more than 16
ENDCODE
[THEN]
+ [UNDEFINED] RSHIFT [IF]
\ https://forth-standard.org/standard/core/RSHIFT
\ RSHIFT x1 u -- x2 logical R7 shift u places
- [UNDEFINED] RSHIFT
- [IF]
CODE RSHIFT
MOV @PSP+,W
AND #$1F,TOS \ no need to shift more than 16
ENDCODE
[THEN]
+ [UNDEFINED] MAX [IF] \ define MIN MAX
\ https://forth-standard.org/standard/core/MAX
\ MAX n1 n2 -- n3 signed maximum
- [UNDEFINED] MAX
- [IF]
-
CODE MAX
CMP @PSP,TOS \ n2-n1
S< ?GOTO FW1 \ n2<n1
ENDCODE
[THEN]
+ [UNDEFINED] 2* [IF]
\ https://forth-standard.org/standard/core/TwoTimes
\ 2* x1 -- x2 arithmetic left shift
- [UNDEFINED] 2*
- [IF]
CODE 2*
ADD TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] 2/ [IF]
\ https://forth-standard.org/standard/core/TwoDiv
\ 2/ x1 -- x2 arithmetic right shift
- [UNDEFINED] 2/
- [IF]
CODE 2/
RRA TOS
MOV @IP+,PC
\ $81EF DEVICEID @ U<
\ DEVICEID @ $81F3 U<
\ = [IF] ; MSP430FR413x subfamily without hardware_MPY
- KERNEL_ADDON HMPY TSTBIT \ KERNEL_ADDON(BIT0) = hardware MPY flag
+ KERNEL_ADDON HMPY TSTBIT \ KERNEL_ADDON(BIT0) = hardware MPY flag
+
RST_RET
- [IF]
+ [IF] ; MSP430FRxxxx subfamily with hardware_MPY
+
+ [UNDEFINED] UM* [IF]
\ https://forth-standard.org/standard/core/MTimes
\ M* n1 n2 -- dlo dhi signed 16*16->32 multiply
- CODE UM*
- MOV @PSP,&MPY \ Load 1st operand for unsigned multiplication
-BW1 MOV TOS,&OP2 \ Load 2nd operand
- MOV &RES0,0(PSP) \ low result on stack
- MOV &RES1,TOS \ high result in TOS
- MOV @IP+,PC
- ENDCODE
+ CODE UM*
+ MOV @PSP,&MPY \ Load 1st operand for unsigned multiplication
+BW1 MOV TOS,&OP2 \ Load 2nd operand
+ MOV &RES0,0(PSP) \ low result on stack
+ MOV &RES1,TOS \ high result in TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+ [UNDEFINED] M* [IF]
\ https://forth-standard.org/standard/core/MTimes
\ M* n1 n2 -- dlo dhi signed 16*16->32 multiply
- CODE M*
- MOV @PSP,&MPYS \ Load 1st operand for signed multiplication
- GOTO BW1
- ENDCODE
+ CODE M*
+ MOV @PSP,&MPYS \ Load 1st operand for signed multiplication
+ GOTO BW1
+ ENDCODE
+ [THEN]
+
+ [ELSE] ; MSP430FR413x without hardware_MPY
- [ELSE] ; MSP430FRxxxx with hardware_MPY
+ [UNDEFINED] M* [IF]
\ https://forth-standard.org/standard/core/UMTimes
\ UM* u1 u2 -- udlo udhi unsigned 16x16->32 mult.
- [UNDEFINED] M* [IF]
- CODE M*
- MOV @PSP,S \ S= n1
- CMP #0,S \ n1 > -1 ?
- S< IF
- XOR #-1,0(PSP) \ n1 --> u1
- ADD #1,0(PSP) \
- THEN
- XOR TOS,S \ S contains sign of result
- CMP #0,TOS \ n2 > -1 ?
- S< IF
- XOR #-1,TOS \ n2 --> u2
- ADD #1,TOS \
- THEN
- PUSHM #2,IP \ UMSTAR use S,T,W,X,Y
- LO2HI \ -- ud1 u2
- UM*
- HI2LO
- POPM #2,IP \ pop S,IP
- CMP #0,S \ sign of result > -1 ?
- S< IF
- XOR #-1,0(PSP) \ ud --> d
- XOR #-1,TOS
- ADD #1,0(PSP)
- ADDC #0,TOS
- THEN
- MOV @IP+,PC
- ENDCODE
+ CODE M*
+ MOV @PSP,S \ S= n1
+ CMP #0,S \ n1 > -1 ?
+ S< IF
+ XOR #-1,0(PSP) \ n1 --> u1
+ ADD #1,0(PSP) \
+ THEN
+ XOR TOS,S \ S contains sign of result
+ CMP #0,TOS \ n2 > -1 ?
+ S< IF
+ XOR #-1,TOS \ n2 --> u2
+ ADD #1,TOS \
+ THEN
+ PUSHM #2,IP \ UMSTAR use S,T,W,X,Y
+ LO2HI \ -- ud1 u2
+ UM*
+ HI2LO
+ POPM #2,IP \ pop S,IP
+ CMP #0,S \ sign of result > -1 ?
+ S< IF
+ XOR #-1,0(PSP) \ ud --> d
+ XOR #-1,TOS
+ ADD #1,0(PSP)
+ ADDC #0,TOS
+ THEN
+ MOV @IP+,PC
+ ENDCODE
[THEN]
[THEN] ; endof hardware_MPY
-\ HERE
-
-\ https://forth-standard.org/standard/core/UMDivMOD
-\ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16
[UNDEFINED] UM/MOD
[IF]
+\ https://forth-standard.org/standard/core/UMDivMOD
+\ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16
CODE UM/MOD
PUSH #DROP \
MOV #MUSMOD,PC \ execute MUSMOD then return to DROP
ENDCODE
[THEN]
-\ HERE OVER - DUMP
-
-
- KERNEL_ADDON @ 0< ; test the switch: FLOORED / SYMETRIC DIVISION
+ KERNEL_ADDON @ 0< ; test the switch: FLOORED/SYMETRIC DIVISION
[IF]
+ [UNDEFINED] FM/MOD [IF]
\ https://forth-standard.org/standard/core/FMDivMOD
\ FM/MOD d1 n1 -- r q floored signed div'n
- [UNDEFINED] FM/MOD
- [IF]
CODE FM/MOD
MOV TOS,S \ S=DIV
MOV @PSP,T \ T=DVDhi
ENDCODE
[THEN]
[ELSE]
+ [UNDEFINED] SM/REM [IF]
\ https://forth-standard.org/standard/core/SMDivREM
\ SM/REM DVDlo DVDhi DIV -- r3 q4 symmetric signed div
- [UNDEFINED] SM/REM
- [IF]
CODE SM/REM
MOV TOS,S \ S=DIV
MOV @PSP,T \ T=DVDhi
[THEN]
[THEN]
+ [UNDEFINED] * [IF]
\ https://forth-standard.org/standard/core/Times
\ * n1 n2 -- n3 signed multiply
- [UNDEFINED] *
- [IF]
: *
M* DROP
;
[THEN]
+ [UNDEFINED] /MOD [IF]
\ https://forth-standard.org/standard/core/DivMOD
\ /MOD n1 n2 -- r3 q4 signed division
- [UNDEFINED] /MOD
- [IF]
: /MOD
>R DUP 0< R>
- [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
;
[THEN]
+ [UNDEFINED] / [IF]
\ https://forth-standard.org/standard/core/Div
\ / n1 n2 -- n3 signed quotient
- [UNDEFINED] /
- [IF]
: /
>R DUP 0< R>
- [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
NIP
;
[THEN]
+ [UNDEFINED] MOD [IF]
\ https://forth-standard.org/standard/core/MOD
\ MOD n1 n2 -- n3 signed remainder
- [UNDEFINED] MOD
- [IF]
: MOD
>R DUP 0< R>
- [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
DROP
;
[THEN]
+ [UNDEFINED] */MOD [IF]
\ https://forth-standard.org/standard/core/TimesDivMOD
\ */MOD n1 n2 n3 -- r4 q5 signed mult/div
- [UNDEFINED] */MOD
- [IF]
: */MOD
>R M* R>
- [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
;
[THEN]
+ [UNDEFINED] */ [IF]
\ https://forth-standard.org/standard/core/TimesDiv
\ */ n1 n2 n3 -- n4 n1*n2/q3
- [UNDEFINED] */
- [IF]
: */
>R M* R>
- [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
NIP
;
[THEN]
\ -------------------------------------------------------------------------------
\ STACK OPERATIONS
\ -------------------------------------------------------------------------------
+ [UNDEFINED] ROT [IF]
\ https://forth-standard.org/standard/core/ROT
\ ROT x1 x2 x3 -- x2 x3 x1
- [UNDEFINED] ROT
- [IF]
CODE ROT
MOV @PSP,W \ 2 fetch x2
MOV TOS,0(PSP) \ 3 store x3
ENDCODE
[THEN]
+ [UNDEFINED] R@ [IF]
\ https://forth-standard.org/standard/core/RFetch
\ R@ -- x R: x -- x fetch from return stack
- [UNDEFINED] R@
- [IF]
CODE R@
SUB #2,PSP
MOV TOS,0(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] TUCK [IF]
\ https://forth-standard.org/standard/core/TUCK
\ TUCK ( x1 x2 -- x2 x1 x2 )
- [UNDEFINED] TUCK
- [IF]
: TUCK SWAP OVER ;
[THEN]
\ ----------------------------------------------------------------------
\ DOUBLE OPERATORS
\ ----------------------------------------------------------------------
+ [UNDEFINED] 2@ [IF]
\ https://forth-standard.org/standard/core/TwoFetch
\ 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack
- [UNDEFINED] 2@
- [IF]
CODE 2@
SUB #2,PSP
MOV 2(TOS),0(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] 2! [IF]
\ https://forth-standard.org/standard/core/TwoStore
\ 2! x1 x2 a-addr -- store 2 cells ; the top of stack is stored at the lower adr
- [UNDEFINED] 2!
- [IF]
CODE 2!
MOV @PSP+,0(TOS)
MOV @PSP+,2(TOS)
ENDCODE
[THEN]
+ [UNDEFINED] 2DUP [IF]
\ https://forth-standard.org/standard/core/TwoDUP
\ 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells
- [UNDEFINED] 2DUP
- [IF]
CODE 2DUP
- MOV TOS,-2(PSP) \ 3
MOV @PSP,-4(PSP) \ 4
+ MOV TOS,-2(PSP) \ 3
SUB #4,PSP \ 1
MOV @IP+,PC \ 4
ENDCODE
[THEN]
+ [UNDEFINED] 2DROP [IF]
\ https://forth-standard.org/standard/core/TwoDROP
\ 2DROP x1 x2 -- drop 2 cells
- [UNDEFINED] 2DROP
- [IF]
CODE 2DROP
ADD #2,PSP
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] 2SWAP [IF]
\ https://forth-standard.org/standard/core/TwoSWAP
\ 2SWAP x1 x2 x3 x4 -- x3 x4 x1 x2
- [UNDEFINED] 2SWAP
- [IF]
CODE 2SWAP
MOV @PSP,W \ -- x1 x2 x3 x4 W=x3
MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x4
ENDCODE
[THEN]
+ [UNDEFINED] 2OVER [IF]
\ https://forth-standard.org/standard/core/TwoOVER
\ 2OVER x1 x2 x3 x4 -- x1 x2 x3 x4 x1 x2
- [UNDEFINED] 2OVER
- [IF]
CODE 2OVER
SUB #4,PSP \ -- x1 x2 x3 x x x4
MOV TOS,2(PSP) \ -- x1 x2 x3 x4 x x4
\ ----------------------------------------------------------------------
\ ALIGNMENT OPERATORS
\ ----------------------------------------------------------------------
+ [UNDEFINED] ALIGNED [IF]
\ https://forth-standard.org/standard/core/ALIGNED
\ ALIGNED addr -- a-addr align given addr
- [UNDEFINED] ALIGNED
- [IF]
CODE ALIGNED
BIT #1,TOS
ADDC #0,TOS
ENDCODE
[THEN]
+ [UNDEFINED] ALIGN [IF]
\ https://forth-standard.org/standard/core/ALIGN
\ ALIGN -- align HERE
- [UNDEFINED] ALIGN
- [IF]
CODE ALIGN
BIT #1,&DP \ 3
ADDC #0,&DP \ 4
\ ---------------------
\ PORTABILITY OPERATORS
\ ---------------------
+ [UNDEFINED] CHARS [IF]
\ https://forth-standard.org/standard/core/CHARS
\ CHARS n1 -- n2 chars->adrs units
- [UNDEFINED] CHARS
- [IF]
CODE CHARS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] CHAR+ [IF]
\ https://forth-standard.org/standard/core/CHARPlus
\ CHAR+ c-addr1 -- c-addr2 add char size
- [UNDEFINED] CHAR+
- [IF]
CODE CHAR+
ADD #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] CELLS [IF]
\ https://forth-standard.org/standard/core/CELLS
\ CELLS n1 -- n2 cells->adrs units
- [UNDEFINED] CELLS
- [IF]
CODE CELLS
ADD TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] CELL+ [IF]
\ https://forth-standard.org/standard/core/CELLPlus
\ CELL+ a-addr1 -- a-addr2 add cell size
- [UNDEFINED] CELL+
- [IF]
CODE CELL+
ADD #2,TOS
MOV @IP+,PC
\ ---------------------------
\ BLOCK AND STRING COMPLEMENT
\ ---------------------------
+ [UNDEFINED] CHAR [IF]
\ https://forth-standard.org/standard/core/CHAR
\ CHAR -- char parse ASCII character
- [UNDEFINED] CHAR
- [IF]
: CHAR
$20 WORD 1+ C@
;
[THEN]
+ [UNDEFINED] [CHAR] [IF]
\ https://forth-standard.org/standard/core/BracketCHAR
\ [CHAR] -- compile character literal
- [UNDEFINED] [CHAR]
- [IF]
: [CHAR]
CHAR POSTPONE LITERAL
; IMMEDIATE
[THEN]
+ [UNDEFINED] +! [IF]
\ https://forth-standard.org/standard/core/PlusStore
\ +! n/u a-addr -- add n/u to memory
- [UNDEFINED] +!
- [IF]
CODE +!
ADD @PSP+,0(TOS)
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] MOVE [IF]
\ https://forth-standard.org/standard/core/MOVE
\ MOVE addr1 addr2 u -- smart move
\ VERSION FOR 1 ADDRESS UNIT = 1 CHAR
- [UNDEFINED] MOVE
- [IF]
CODE MOVE
MOV TOS,W \ W = cnt
MOV @PSP+,Y \ Y = addr2 = dst
ENDCODE
[THEN]
+ [UNDEFINED] FILL [IF]
\ https://forth-standard.org/standard/core/FILL
\ FILL c-addr u char -- fill memory with char
- [UNDEFINED] FILL
- [IF]
CODE FILL
MOV @PSP+,X \ count
MOV @PSP+,W \ address
\ --------------------
\ INTERPRET COMPLEMENT
\ --------------------
+ [UNDEFINED] HEX [IF]
\ https://forth-standard.org/standard/core/HEX
- [UNDEFINED] HEX
- [IF]
CODE HEX
MOV #$10,&BASEADR
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] DECIMAL [IF]
\ https://forth-standard.org/standard/core/DECIMAL
- [UNDEFINED] DECIMAL
- [IF]
CODE DECIMAL
MOV #$0A,&BASEADR
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] ( [IF]
\ https://forth-standard.org/standard/core/p
\ ( -- skip input until char ) or EOL
- [UNDEFINED] ( ; )
- [IF]
: (
')' WORD DROP
; IMMEDIATE
[THEN]
+ [UNDEFINED] .( [IF] ; "
\ https://forth-standard.org/standard/core/Dotp
\ .( -- type comment immediatly.
- [UNDEFINED] .( ; "
- [IF]
CODE .( ; "
+ PUSH IP
MOV #0,&CAPS \ CAPS OFF
- COLON
+ LO2HI
')' WORD
COUNT TYPE
HI2LO
- MOV #$20,&CAPS \ CAPS ON
+ MOV #$20,&CAPS \ CAPS ON
MOV @RSP+,IP
MOV @IP+,PC
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] >BODY [IF]
\ https://forth-standard.org/standard/core/toBODY
\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word
- [UNDEFINED] >BODY
- [IF]
CODE >BODY
ADD #4,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] EXECUTE [IF]
\ https://forth-standard.org/standard/core/EXECUTE
\ EXECUTE i*x xt -- j*x execute Forth word at 'xt'
- [UNDEFINED] EXECUTE
- [IF]
CODE EXECUTE
PUSH TOS \ 3 push xt
MOV @PSP+,TOS \ 2
ENDCODE
[THEN]
+ [UNDEFINED] EVALUATE [IF]
+\ EVALUATE upside down...
+ CODENNM \ as the end of EVALUATE
+ MOV @RSP+,&TOIN \ 4
+ MOV @RSP+,&SOURCE_ORG \ 4
+ MOV @RSP+,&SOURCE_LEN \ 4
+ MOV @RSP+,IP
+ MOV @IP+,PC
+ ENDCODE \ -- end_of_EVALUATE_addr
+
\ https://forth-standard.org/standard/core/EVALUATE
\ EVALUATE \ i*x c-addr u -- j*x interpret string
- [UNDEFINED] EVALUATE
- [IF]
CODE EVALUATE
MOV #SOURCE_LEN,X \ 2
MOV @X+,S \ 2 S = SOURCE_LEN
MOV @X+,T \ 2 T = SOURCE_ORG
MOV @X+,W \ 2 W = TOIN
PUSHM #4,IP \ 6 PUSHM IP,S,T,W
- LO2HI
- [ ' \ 8 + , ] \ compile INTERPRET
- HI2LO
- MOV @RSP+,&TOIN \ 4
- MOV @RSP+,&SOURCE_ORG \ 4
- MOV @RSP+,&SOURCE_LEN \ 4
- MOV @RSP+,IP
- MOV @IP+,PC
- ENDCODE
+ MOV PC,IP \ 1
+ ADD #8,IP \ 1 IP = address compiled after ENDCODE
+ MOV #INTERPRET,PC \ 3 addr defined in MSP430FRxxxx.pat
+ NOP \ 1 stuffing instruction
+ ENDCODE \
+ , \ end_of_EVALUATE_addr -- compile the end_of_EVALUATE_addr
+
[THEN]
+ [UNDEFINED] RECURSE [IF]
\ https://forth-standard.org/standard/core/RECURSE
\ C RECURSE -- recurse to current definition
- [UNDEFINED] RECURSE
- [IF]
CODE RECURSE
MOV &DP,X
MOV &LAST_CFA,0(X)
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] SOURCE [IF]
\ https://forth-standard.org/standard/core/SOURCE
\ SOURCE -- adr u of current input buffer
- [UNDEFINED] SOURCE
- [IF]
CODE SOURCE
SUB #4,PSP
MOV TOS,2(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] VARIABLE [IF]
\ https://forth-standard.org/standard/core/VARIABLE
\ VARIABLE <name> -- define a Forth VARIABLE
- [UNDEFINED] VARIABLE
- [IF]
: VARIABLE
CREATE
HI2LO
ENDCODE
[THEN]
+ [UNDEFINED] CONSTANT [IF]
\ https://forth-standard.org/standard/core/CONSTANT
\ CONSTANT <name> n -- define a Forth CONSTANT
- [UNDEFINED] CONSTANT
- [IF]
: CONSTANT
CREATE
HI2LO
ENDCODE
[THEN]
+ [UNDEFINED] STATE [IF]
\ https://forth-standard.org/standard/core/STATE
\ STATE -- a-addr holds compiler state
- [UNDEFINED] STATE
- [IF]
STATEADR CONSTANT STATE
[THEN]
+ [UNDEFINED] BASE [IF]
\ https://forth-standard.org/standard/core/BASE
\ BASE -- a-addr holds conversion radix
- [UNDEFINED] BASE
- [IF]
BASEADR CONSTANT BASE
[THEN]
+ [UNDEFINED] >IN [IF]
\ https://forth-standard.org/standard/core/toIN
\ C >IN -- a-addr holds offset in input stream
- [UNDEFINED] >IN
- [IF]
TOIN CONSTANT >IN
[THEN]
+ [UNDEFINED] PAD [IF]
\ https://forth-standard.org/standard/core/PAD
\ PAD -- addr
- [UNDEFINED] PAD
- [IF]
PAD_ORG CONSTANT PAD
[THEN]
+ [UNDEFINED] BL [IF]
\ https://forth-standard.org/standard/core/BL
\ BL -- char an ASCII space
- [UNDEFINED] BL
- [IF]
'SP' CONSTANT BL
[THEN]
+ [UNDEFINED] SPACE [IF]
\ https://forth-standard.org/standard/core/SPACE
\ SPACE -- output a space
- [UNDEFINED] SPACE
- [IF]
: SPACE
'SP' EMIT ;
[THEN]
+ [UNDEFINED] SPACES [IF]
\ https://forth-standard.org/standard/core/SPACES
\ SPACES n -- output n spaces
- [UNDEFINED] SPACES
- [IF]
: SPACES
BEGIN
?DUP
;
[THEN]
- [UNDEFINED] DEFER
- [IF]
+ [UNDEFINED] DEFER [IF]
\ https://forth-standard.org/standard/core/DEFER
\ Skip leading space delimiters. Parse name delimited by a space.
\ Create a definition for name with the execution semantics defined below.
\ name Execution: --
\ Execute the xt that name is set to execute, i.e. NEXT (nothing),
\ until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name.
- : DEFER
+ : DEFER \ useless definition for FAST FORTH...
CREATE
HI2LO
MOV #$4030,-4(W) \4 first CELL = MOV @PC+,PC = BR #addr
ENDCODE
[THEN]
+ [UNDEFINED] CR [IF]
\ https://forth-standard.org/standard/core/CR
\ CR -- send CR+LF to the output device
- [UNDEFINED] CR
- [IF]
-\ DEFER CR \ DEFERed definition, by default executes :NONAME part
- CODE CR \ replaced by this CODE definition
- MOV #NEXT_ADR,PC
+\ DEFER CR
+\
+\ :NONAME
+\ 'CR' EMIT 'LF' EMIT
+\ ; IS CR
+\
+ CODE CR
+ MOV #NEXT_ADR,PC \ compile same as DEFER
ENDCODE
:NONAME
; IS CR
[THEN]
+ [UNDEFINED] TO [IF]
\ https://forth-standard.org/standard/core/TO
\ TO name Run-time: ( x -- )
\ Assign the value x to named VALUE.
- [UNDEFINED] TO
- [IF]
CODE TO
BIS #UF9,SR
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] VALUE [IF]
\ https://forth-standard.org/standard/core/VALUE
\ ( x "<spaces>name" -- ) define a Forth VALUE
\ Skip leading space delimiters. Parse name delimited by a space.
\ name Execution: ( -- x )
\ Place x on the stack. The value of x is that given when name was created,
\ until the phrase x TO name is executed, causing a new value of x to be assigned to name.
- [UNDEFINED] VALUE
- [IF]
- : VALUE \ x "<spaces>name" --
+ : VALUE \ x "<spaces>name" --
CREATE ,
DOES>
HI2LO
MOV @RSP+,IP
BIT #UF9,SR \ 2 see TO
0= IF \ 2 if UF9 is not set
- MOV @TOS,TOS \ 2 execute FETCH
- MOV @IP+,PC \ 4
+ MOV #@,PC \ execute FETCH
THEN \ else
BIC #UF9,SR \ 2 clear UF9 flag
- MOV #!,PC \ 4 execute STORE
+ MOV #!,PC \ execute STORE
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/CASE
- [UNDEFINED] CASE
- [IF]
+ [UNDEFINED] CASE [IF] \ define CASE OF ENDOF ENDCASE
- : CASE 0
+\ https://forth-standard.org/standard/core/CASE
+ : CASE
+ 0
; IMMEDIATE \ -- #of-1
\ https://forth-standard.org/standard/core/OF
RST_SET
+ [THEN]
+
ECHO
-; CORE_ANS.f is loaded
+; CORE_ANS.f is loaded
\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
\ MSP_EXP430FR4133 MSP_EXP430FR2433 CHIPSTICK_FR2433 MSP_EXP430FR2355
\ LP_MSP430FR2476
+\ MY_MSP430FR5738_2
\
\ from scite editor : copy your target selection in (shift+F8) parameter 1:
\
0<> IF MOV #0,TOS THEN \ if TOS <> 0 (DOUBLE input), set TOS = 0
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
- $0D EMIT \ return to column 1 without CR
- ABORT" FastForth V3.9 please!"
- ABORT" build FastForth with DOUBLE_INPUT addon !"
- RST_RET \ if no abort remove this word
+ $0D EMIT \ return to column 1 without CR
+ ABORT" FastForth V4.0 please!"
+ ABORT" build FastForth with DOUBLE_INPUT addon!"
+ RST_RET \ if no abort remove this word
;
ABORT_DOUBLE
; -----------------------------------------------------
; DOUBLE.f
; -----------------------------------------------------
+ [DEFINED] {DOUBLE}
+ [IF] {DOUBLE} [THEN]
+ [UNDEFINED] {DOUBLE} [IF]
MARKER {DOUBLE}
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] >R [IF]
\ https://forth-standard.org/standard/core/toR
\ >R x -- R: -- x push to return stack
- [UNDEFINED] >R
- [IF]
CODE >R
PUSH TOS
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] R> [IF]
\ https://forth-standard.org/standard/core/Rfrom
\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
- [UNDEFINED] R>
- [IF]
CODE R>
SUB #2,PSP \ 1
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] 0< [IF]
\ https://forth-standard.org/standard/core/Zeroless
\ 0< n -- flag true if TOS negative
- [UNDEFINED] 0<
- [IF]
CODE 0<
ADD TOS,TOS \ 1 set carry if TOS negative
SUBC TOS,TOS \ 1 TOS=-1 if carry was clear
ENDCODE
[THEN]
+ [UNDEFINED] DROP [IF]
\ https://forth-standard.org/standard/core/DROP
\ DROP x -- drop top of stack
- [UNDEFINED] DROP
- [IF]
CODE DROP
MOV @PSP+,TOS \ 2
MOV @IP+,PC \ 4
ENDCODE
[THEN]
+ [UNDEFINED] DUP [IF]
\ https://forth-standard.org/standard/core/DUP
\ DUP x -- x x duplicate top of stack
- [UNDEFINED] DUP
- [IF]
CODE DUP
BW1 SUB #2,PSP \ 2 push old TOS..
MOV TOS,0(PSP) \ 3 ..onto stack
MOV @IP+,PC \ 4
ENDCODE
+ CODE ?DUP
\ https://forth-standard.org/standard/core/qDUP
\ ?DUP x -- 0 | x x DUP if nonzero
- CODE ?DUP
CMP #0,TOS \ 2 test for TOS nonzero
0<> ?GOTO BW1 \ 2
MOV @IP+,PC \ 4
ENDCODE
[THEN]
+ [UNDEFINED] NIP [IF]
\ https://forth-standard.org/standard/core/NIP
\ NIP x1 x2 -- x2 Drop the first item below the top of stack
- [UNDEFINED] NIP
- [IF]
CODE NIP
ADD #2,PSP
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] UM/MOD [IF]
\ https://forth-standard.org/standard/core/UMDivMOD
\ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16
- [UNDEFINED] UM/MOD
- [IF]
CODE UM/MOD
PUSH #DROP \
MOV #MUSMOD,PC \ execute MUSMOD then return to DROP
ENDCODE
[THEN]
- KERNEL_ADDON @ 0< ; test the switch: FLOORED / SYMETRIC DIVISION
- [IF] ; FLOORED DIVISION
+ KERNEL_ADDON @ 0< ; test the switch: FLOORED/SYMETRIC DIVISION
+ [IF]
+ [UNDEFINED] FM/MOD [IF]
\ https://forth-standard.org/standard/core/FMDivMOD
\ FM/MOD d1 n1 -- r q floored signed div'n
- [UNDEFINED] FM/MOD
- [IF]
- CODE FM/MOD
- MOV TOS,S \ S=DIV
- MOV @PSP,T \ T=DVDhi
- CMP #0,TOS \ n2 >= 0 ?
- S< IF \
- XOR #-1,TOS
- ADD #1,TOS \ -- d1 u2
- THEN
- CMP #0,0(PSP) \ d1hi >= 0 ?
- S< IF \
- XOR #-1,2(PSP) \ d1lo
- XOR #-1,0(PSP) \ d1hi
- ADD #1,2(PSP) \ d1lo+1
- ADDC #0,0(PSP) \ d1hi+C
- THEN \ -- uDVDlo uDVDhi uDIVlo
- PUSHM #3,IP \ save IP,S,T
- LO2HI
- UM/MOD \ -- uREMlo uQUOTlo
- HI2LO
- POPM #3,IP \ restore T,S,IP
- CMP #0,T \ T=DVDhi --> REM_sign
- S< IF
- XOR #-1,0(PSP)
- ADD #1,0(PSP)
- THEN
- XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign
- CMP #0,T \ -- n3 u4 T=quot_sign
- S< IF
- XOR #-1,TOS
- ADD #1,TOS
- THEN \ -- n3 n4 S=divisor
-
- CMP #0,0(PSP) \ remainder <> 0 ?
- 0<> IF
- CMP #1,TOS \ quotient < 1 ?
+ CODE FM/MOD
+ MOV TOS,S \ S=DIV
+ MOV @PSP,T \ T=DVDhi
+ CMP #0,TOS \ n2 >= 0 ?
+ S< IF \
+ XOR #-1,TOS
+ ADD #1,TOS \ -- d1 u2
+ THEN
+ CMP #0,0(PSP) \ d1hi >= 0 ?
+ S< IF \
+ XOR #-1,2(PSP) \ d1lo
+ XOR #-1,0(PSP) \ d1hi
+ ADD #1,2(PSP) \ d1lo+1
+ ADDC #0,0(PSP) \ d1hi+C
+ THEN \ -- uDVDlo uDVDhi uDIVlo
+ PUSHM #3,IP \ save IP,S,T
+ LO2HI
+ UM/MOD \ -- uREMlo uQUOTlo
+ HI2LO
+ POPM #3,IP \ restore T,S,IP
+ CMP #0,T \ T=DVDhi --> REM_sign
S< IF
- ADD S,0(PSP) \ add divisor to remainder
- SUB #1,TOS \ decrement quotient
+ XOR #-1,0(PSP)
+ ADD #1,0(PSP)
THEN
- THEN
- MOV @IP+,PC
- ENDCODE
- [THEN]
+ XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign
+ CMP #0,T \ -- n3 u4 T=quot_sign
+ S< IF
+ XOR #-1,TOS
+ ADD #1,TOS
+ THEN \ -- n3 n4 S=divisor
+
+ CMP #0,0(PSP) \ remainder <> 0 ?
+ 0<> IF
+ CMP #1,TOS \ quotient < 1 ?
+ S< IF
+ ADD S,0(PSP) \ add divisor to remainder
+ SUB #1,TOS \ decrement quotient
+ THEN
+ THEN
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
- [ELSE] ; SYMETRIC DIVISION
+ [ELSE]
+ [UNDEFINED] SM/REM [IF]
\ https://forth-standard.org/standard/core/SMDivREM
\ SM/REM DVDlo DVDhi DIV -- r3 q4 symmetric signed div
- [UNDEFINED] SM/REM
- [IF]
- CODE SM/REM
- MOV TOS,S \ S=DIV
- MOV @PSP,T \ T=DVDhi
- CMP #0,TOS \ n2 >= 0 ?
- S< IF \
- XOR #-1,TOS
- ADD #1,TOS \ -- d1 u2
- THEN
- CMP #0,0(PSP) \ d1hi >= 0 ?
- S< IF \
- XOR #-1,2(PSP) \ d1lo
- XOR #-1,0(PSP) \ d1hi
- ADD #1,2(PSP) \ d1lo+1
- ADDC #0,0(PSP) \ d1hi+C
- THEN \ -- uDVDlo uDVDhi uDIVlo
- PUSHM #3,IP \ save IP,S,T
- LO2HI
- UM/MOD \ -- uREMlo uQUOTlo
- HI2LO
- POPM #3,IP \ restore T,S,IP
- CMP #0,T \ T=DVDhi --> REM_sign
- S< IF
- XOR #-1,0(PSP)
- ADD #1,0(PSP)
- THEN
- XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign
- CMP #0,T \ -- n3 u4 T=quot_sign
- S< IF
- XOR #-1,TOS
- ADD #1,TOS
- THEN \ -- n3 n4 S=divisor
- MOV @IP+,PC
- ENDCODE
- [THEN]
+ CODE SM/REM
+ MOV TOS,S \ S=DIV
+ MOV @PSP,T \ T=DVDhi
+ CMP #0,TOS \ n2 >= 0 ?
+ S< IF \
+ XOR #-1,TOS
+ ADD #1,TOS \ -- d1 u2
+ THEN
+ CMP #0,0(PSP) \ d1hi >= 0 ?
+ S< IF \
+ XOR #-1,2(PSP) \ d1lo
+ XOR #-1,0(PSP) \ d1hi
+ ADD #1,2(PSP) \ d1lo+1
+ ADDC #0,0(PSP) \ d1hi+C
+ THEN \ -- uDVDlo uDVDhi uDIVlo
+ PUSHM #3,IP \ save IP,S,T
+ LO2HI
+ UM/MOD \ -- uREMlo uQUOTlo
+ HI2LO
+ POPM #3,IP \ restore T,S,IP
+ CMP #0,T \ T=DVDhi --> REM_sign
+ S< IF
+ XOR #-1,0(PSP)
+ ADD #1,0(PSP)
+ THEN
+ XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign
+ CMP #0,T \ -- n3 u4 T=quot_sign
+ S< IF
+ XOR #-1,TOS
+ ADD #1,TOS
+ THEN \ -- n3 n4 S=divisor
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
[THEN]
+ [UNDEFINED] / [IF]
\ https://forth-standard.org/standard/core/Div
\ / n1 n2 -- n3 signed quotient
- [UNDEFINED] /
- [IF]
: /
>R DUP 0< R>
- [ KERNEL_ADDON @ 0< ] [IF]
- FM/MOD
- [ELSE]
- SM/REM
+ [ KERNEL_ADDON @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
[THEN]
NIP
;
[THEN]
-\ https://forth-standard.org/standard/core/Fetch
-\ @ c-addr -- char fetch char from memory
- [UNDEFINED] @
- [IF]
- CODE @
- MOV @TOS,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
-
-\ https://forth-standard.org/standard/core/Store
-\ ! x a-addr -- store cell in memory
- [UNDEFINED] !
- [IF]
- CODE !
- MOV @PSP+,0(TOS) \ 4
- MOV @PSP+,TOS \ 2
- MOV @IP+,PC \ 4
- ENDCODE
- [THEN]
-
+ [UNDEFINED] C@ [IF]
\ https://forth-standard.org/standard/core/CFetch
\ C@ c-addr -- char fetch char from memory
- [UNDEFINED] C@
- [IF]
CODE C@
MOV.B @TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] SWAP [IF]
\ https://forth-standard.org/standard/core/SWAP
\ SWAP x1 x2 -- x2 x1 swap top two items
- [UNDEFINED] SWAP
- [IF]
CODE SWAP
MOV @PSP,W \ 2
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] OVER [IF]
\ https://forth-standard.org/standard/core/OVER
\ OVER x1 x2 -- x1 x2 x1
- [UNDEFINED] OVER
- [IF]
CODE OVER
MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
MOV @PSP,TOS \ 2 -- x1 (x2) x1
ENDCODE
[THEN]
+ [UNDEFINED] ROT [IF]
\ https://forth-standard.org/standard/core/ROT
\ ROT x1 x2 x3 -- x2 x3 x1
- [UNDEFINED] ROT
- [IF]
CODE ROT
MOV @PSP,W \ 2 fetch x2
MOV TOS,0(PSP) \ 3 store x3
ENDCODE
[THEN]
+ [UNDEFINED] - [IF]
\ https://forth-standard.org/standard/core/Minus
\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
- [UNDEFINED] -
- [IF]
CODE -
SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3)
XOR #-1,TOS \ 1
ENDCODE
[THEN]
+ [UNDEFINED] < [IF] \ define < and >
\ https://forth-standard.org/standard/core/less
\ < n1 n2 -- flag test n1<n2, signed
- [UNDEFINED] <
- [IF] \ define < and >
CODE <
SUB @PSP+,TOS \ 1 TOS=n2-n1
S< ?GOTO FW1 \ 2 signed
ENDCODE
[THEN]
+ [UNDEFINED] IF [IF] \ define IF THEN
\ https://forth-standard.org/standard/core/IF
\ IF -- IFadr initialize conditional forward branch
- [UNDEFINED] IF
- [IF] \ define IF THEN
- CODE IF \ immediate
- SUB #2,PSP \
- MOV TOS,0(PSP) \
- MOV &DP,TOS \ -- HERE
- ADD #4,&DP \ compile one word, reserve one word
- MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN
- ADD #2,TOS \ -- HERE+2=IFadr
+ CODE IF \ immediate
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \
+ MOV &DP,TOS \ -- HERE
+ ADD #4,&DP \ compile one word, reserve one word
+ MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN
+ ADD #2,TOS \ -- HERE+2=IFadr
MOV @IP+,PC
ENDCODE IMMEDIATE
\ https://forth-standard.org/standard/core/THEN
\ THEN IFadr -- resolve forward branch
- CODE THEN \ immediate
- MOV &DP,0(TOS) \ -- IFadr
- MOV @PSP+,TOS \ --
+ CODE THEN \ immediate
+ MOV &DP,0(TOS) \ -- IFadr
+ MOV @PSP+,TOS \ --
MOV @IP+,PC
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] ELSE [IF]
\ https://forth-standard.org/standard/core/ELSE
\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
- [UNDEFINED] ELSE
- [IF]
- CODE ELSE \ immediate
- ADD #4,&DP \ make room to compile two words
- MOV &DP,W \ W=HERE+4
- MOV #BRAN,-4(W)
- MOV W,0(TOS) \ HERE+4 ==> [IFadr]
- SUB #2,W \ HERE+2
- MOV W,TOS \ -- ELSEadr
+ CODE ELSE \ immediate
+ ADD #4,&DP \ make room to compile two words
+ MOV &DP,W \ W=HERE+4
+ MOV #BRAN,-4(W)
+ MOV W,0(TOS) \ HERE+4 ==> [IFadr]
+ SUB #2,W \ HERE+2
+ MOV W,TOS \ -- ELSEadr
MOV @IP+,PC
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] TO [IF]
\ https://forth-standard.org/standard/core/TO
- [UNDEFINED] TO
- [IF]
CODE TO
BIS #UF9,SR
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] DOES> [IF]
\ https://forth-standard.org/standard/core/DOES
\ DOES> -- set action for the latest CREATEd definition
- [UNDEFINED] DOES>
- [IF]
CODE DOES>
- MOV &LAST_CFA,W \ W = CFA of CREATEd word
- MOV #DODOES,0(W) \ replace CFA (CALL rDOCON) by new CFA (CALL rDODOES)
- MOV IP,2(W) \ replace PFA by the address after DOES> as execution address
+ MOV &LAST_CFA,W \ W = CFA of CREATEd word
+ MOV #DODOES,0(W) \ replace CFA (CALL rDOCON) by new CFA (CALL rDODOES)
+ MOV IP,2(W) \ replace PFA by the address after DOES> as execution address
MOV @RSP+,IP
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] SPACES [IF]
\ https://forth-standard.org/standard/core/SPACES
\ SPACES n -- output n spaces
- [UNDEFINED] SPACES
- [IF]
CODE SPACES
CMP #0,TOS
0<> IF
ENDCODE
[THEN]
+ [UNDEFINED] 2@ [IF]
\ https://forth-standard.org/standard/core/TwoFetch
\ 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack
- [UNDEFINED] 2@
- [IF]
CODE 2@
SUB #2,PSP
MOV 2(TOS),0(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] 2! [IF]
\ https://forth-standard.org/standard/core/TwoStore
\ 2! x1 x2 a-addr -- store 2 cells ; the top of stack is stored at the lower adr
- [UNDEFINED] 2!
- [IF]
CODE 2!
MOV @PSP+,0(TOS)
MOV @PSP+,2(TOS)
ENDCODE
[THEN]
+ [UNDEFINED] 2DUP [IF]
\ https://forth-standard.org/standard/core/TwoDUP
\ 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells
- [UNDEFINED] 2DUP
- [IF]
CODE 2DUP
SUB #4,PSP \ -- x1 x x x2
MOV TOS,2(PSP) \ -- x1 x2 x x2
ENDCODE
[THEN]
+ [UNDEFINED] 2DROP [IF]
\ https://forth-standard.org/standard/core/TwoDROP
\ 2DROP x1 x2 -- drop 2 cells
- [UNDEFINED] 2DROP
- [IF]
CODE 2DROP
ADD #2,PSP
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] 2SWAP [IF]
\ https://forth-standard.org/standard/core/TwoSWAP
\ 2SWAP x1 x2 x3 x4 -- x3 x4 x1 x2
- [UNDEFINED] 2SWAP
- [IF]
CODE 2SWAP
MOV @PSP,W \ -- x1 x2 x3 x4 W=x3
MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x4
ENDCODE
[THEN]
+ [UNDEFINED] 2OVER [IF]
\ https://forth-standard.org/standard/core/TwoOVER
\ 2OVER x1 x2 x3 x4 -- x1 x2 x3 x4 x1 x2
- [UNDEFINED] 2OVER
- [IF]
CODE 2OVER
SUB #4,PSP \ -- x1 x2 x3 x x x4
MOV TOS,2(PSP) \ -- x1 x2 x3 x4 x x4
ENDCODE
[THEN]
+ [UNDEFINED] 2>R [IF]
\ https://forth-standard.org/standard/core/TwotoR
\ ( x1 x2 -- ) ( R: -- x1 x2 ) Transfer cell pair x1 x2 to the return stack.
- [UNDEFINED] 2>R
- [IF]
CODE 2>R
PUSH @PSP+
PUSH TOS
ENDCODE
[THEN]
+ [UNDEFINED] 2R@ [IF]
\ https://forth-standard.org/standard/core/TwoRFetch
\ ( -- x1 x2 ) ( R: x1 x2 -- x1 x2 ) Copy cell pair x1 x2 from the return stack.
- [UNDEFINED] 2R@
- [IF]
CODE 2R@
SUB #4,PSP
MOV TOS,2(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] 2R> [IF]
\ https://forth-standard.org/standard/core/TwoRfrom
\ ( -- x1 x2 ) ( R: x1 x2 -- ) Transfer cell pair x1 x2 from the return stack
- [UNDEFINED] 2R>
- [IF]
CODE 2R>
SUB #4,PSP
MOV TOS,2(PSP)
ENDCODE
[THEN]
-\ ===============================================
-\ DOUBLE word set
-\ ===============================================
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+; ===============================================
+; DOUBLE word set
+; ===============================================
+ [UNDEFINED] D. [IF]
\ https://forth-standard.org/standard/double/Dd
\ D. dlo dhi -- display d (signed)
- [UNDEFINED] D.
- [IF]
CODE D.
- MOV TOS,S \ S will be pushed as sign
- MOV #U.+10,PC \ U. + 10 = D.
+ MOV TOS,S \ S will be pushed as sign by DDOT
+ MOV #D.,PC \ U. + 10 = DDOT
ENDCODE
[THEN]
+ [UNDEFINED] 2ROT [IF]
\ https://forth-standard.org/standard/double/TwoROT
\ Rotate the top three cell pairs on the stack bringing cell pair x1 x2 to the top of the stack.
- [UNDEFINED] 2ROT
- [IF]
CODE 2ROT
MOV 8(PSP),X \ 3
MOV 6(PSP),Y \ 3
ENDCODE
[THEN]
+ [UNDEFINED] D>S [IF]
\ https://forth-standard.org/standard/double/DtoS
\ D>S d -- n double prec -> single.
- [UNDEFINED] D>S
- [IF]
CODE D>S
MOV @PSP+,TOS
NEXT
ENDCODE
[THEN]
+ [UNDEFINED] D0= [IF] \ define: D0= D0< D= D< DU<
+
\ https://forth-standard.org/standard/double/DZeroEqual
- [UNDEFINED] D0=
- [IF]
CODE D0=
+ ADD #2,PSP
CMP #0,TOS
MOV #0,TOS
0= IF
- CMP #0,0(PSP)
+ CMP #0,-2(PSP)
0= IF
- MOV #-1,TOS
+BW1 MOV #-1,TOS
THEN
THEN
- ADD #2,PSP
+BW2 AND #-1,TOS \ to set N, Z flags
NEXT
ENDCODE
- [THEN]
\ https://forth-standard.org/standard/double/DZeroless
- [UNDEFINED] D0<
- [IF]
CODE D0<
+ ADD #2,PSP
CMP #0,TOS
MOV #0,TOS
- S< IF
- MOV #-1,TOS
- THEN
- ADD #2,PSP
- AND #-1,TOS \ to set N, Z flags
- NEXT
+ S< ?GOTO BW1
+ GOTO BW2
ENDCODE
- [THEN]
\ https://forth-standard.org/standard/double/DEqual
- [UNDEFINED] D=
- [IF]
CODE D=
- CMP TOS,2(PSP) \ 3 ud1H - ud2H
- MOV #0,TOS \ 1
- 0= IF \ 2
- CMP @PSP,4(PSP) \ 4 ud1L - ud2L
- 0= IF \ 2
- MOV #-1,TOS \ 1
- THEN
- THEN
- ADD #6,PSP \ 2
- MOV @IP+,PC \ 4
+ ADD #6,PSP \ 2
+ CMP TOS,-4(PSP) \ 3 ud1H - ud2H
+ MOV #0,TOS \ 1
+ 0<> ?GOTO BW2 \ 2
+ CMP -6(PSP),-2(PSP) \ 4 ud1L - ud2L
+ 0= ?GOTO BW1 \ 2
+ GOTO BW2
ENDCODE
- [THEN]
\ https://forth-standard.org/standard/double/Dless
\ flag is true if and only if d1 is less than d2
- [UNDEFINED] D<
- [IF]
CODE D<
- CMP TOS,2(PSP) \ 3 d1H - d2H
- MOV #0,TOS \ 1
- S< IF \ 2
- MOV #-1,TOS \ 1
- THEN
- 0= IF \ 2
- CMP @PSP,4(PSP) \ 4 d1L - d2L
- U< IF \ 2
- MOV #-1,TOS \ 1
- THEN
+ ADD #6,PSP \ 2
+ CMP TOS,-4(PSP) \ 3 d1H - d2H
+ MOV #0,TOS \ 1
+ S< IF
+BW1 MOV #-1,TOS
THEN
- ADD #6,PSP \ 2
- MOV @IP+,PC \ 4
+BW3 0<> ?GOTO BW2 \ 2
+ CMP -6(PSP),-2(PSP) \ 4 d1L - d2L
+ U>= ?GOTO BW2 \ to set N, Z flags
+ U< ?GOTO BW1 \ 2
ENDCODE
- [THEN]
\ https://forth-standard.org/standard/double/DUless
\ flag is true if and only if ud1 is less than ud2
- [UNDEFINED] DU<
- [IF]
CODE DU<
- CMP TOS,2(PSP) \ 3 ud1H - ud2H
- MOV #0,TOS \ 1
- U< IF \ 2
- MOV #-1,TOS \ 1
- THEN
- 0= IF \ 2
- CMP @PSP,4(PSP) \ 4 ud1L - ud2L
- U< IF \ 2
- MOV #-1,TOS \ 1
- THEN
- THEN
- ADD #6,PSP \ 2
- MOV @IP+,PC \ 4
+ ADD #6,PSP \ 2
+ CMP TOS,-4(PSP) \ 3 ud1H - ud2H
+ MOV #0,TOS \ 1
+ U>= ?GOTO BW3
+ U< ?GOTO BW1 \ 4
ENDCODE
[THEN]
+ [UNDEFINED] D+ [IF] \ define: D+ M+
\ https://forth-standard.org/standard/double/DPlus
- [UNDEFINED] D+
- [IF]
CODE D+
BW1 ADD @PSP+,2(PSP)
ADDC @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] D- [IF]
\ https://forth-standard.org/standard/double/DMinus
- [UNDEFINED] D-
- [IF]
CODE D-
SUB @PSP+,2(PSP)
SUBC TOS,0(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] DNEGATE [IF] \ define DNEGATE DABS
\ https://forth-standard.org/standard/double/DNEGATE
- [UNDEFINED] DNEGATE
- [IF]
CODE DNEGATE
- XOR #-1,0(PSP)
+BW1 XOR #-1,0(PSP)
XOR #-1,TOS
ADD #1,0(PSP)
ADDC #0,TOS
MOV @IP+,PC \ 4
ENDCODE
- [THEN]
\ https://forth-standard.org/standard/double/DABS
\ DABS d1 -- |d1| absolute value
- [UNDEFINED] DABS
- [IF]
CODE DABS
CMP #0,TOS \ 1
- 0>= IF
- MOV @IP+,PC
- THEN
- MOV #DNEGATE,PC
+ 0< ?GOTO BW1
+ MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] D2/ [IF]
\ https://forth-standard.org/standard/double/DTwoDiv
- [UNDEFINED] D2/
- [IF]
CODE D2/
RRA TOS
RRC 0(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] D2* [IF]
\ https://forth-standard.org/standard/double/DTwoTimes
- [UNDEFINED] D2*
- [IF]
CODE D2*
ADD @PSP,0(PSP)
ADDC TOS,TOS
ENDCODE
[THEN]
+ [UNDEFINED] DMAX [IF]
\ https://forth-standard.org/standard/double/DMAX
- [UNDEFINED] DMAX
- [IF]
: DMAX \ -- d1 d2
2OVER 2OVER \ -- d1 d2 d1 d2
D< IF \ -- d1 d2
;
[THEN]
+ [UNDEFINED] DMIN [IF]
\ https://forth-standard.org/standard/double/DMIN
- [UNDEFINED] DMIN
- [IF]
: DMIN \ -- d1 d2
2OVER 2OVER \ -- d1 d2 d1 d2
D< IF \ -- d1 d2
;
[THEN]
- RST_SET
-\ \ https://forth-standard.org/standard/core/Equal
-\ \ = x1 x2 -- flag test x1=x2
-\ [UNDEFINED] =
-\ [IF]
-\ CODE =
-\ SUB @PSP+,TOS \ 2
-\ 0<> IF \ 2
-\ AND #0,TOS \ 1
-\ MOV @IP+,PC \ 4
-\ THEN
-\ XOR #-1,TOS \ 1 flag Z = 1
-\ MOV @IP+,PC \ 4
-\ ENDCODE
-\ [THEN]
-\
-\ \ https://forth-standard.org/standard/core/Uless
-\ \ U< u1 u2 -- flag test u1<u2, unsigned
-\ [UNDEFINED] U<
-\ [IF]
-\ CODE U<
-\ SUB @PSP+,TOS \ 2 u2-u1
-\ 0<> IF
-\ MOV #-1,TOS \ 1
-\ U< IF \ 2 flag
-\ AND #0,TOS \ 1 flag Z = 1
-\ THEN
-\ THEN
-\ MOV @IP+,PC \ 4
-\ ENDCODE
-\ [THEN]
-\
-\ $81EF DEVICEID @ U<
-\ DEVICEID @ $81F3 U<
-\ =
+ [UNDEFINED] M*/ [IF]
+\ https://forth-standard.org/standard/double/MTimesDiv
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
+ RST_SET
- KERNEL_ADDON HMPY TSTBIT \ hardware MPY ?
-
- RST_RET
-
- [IF] ; MSP430FRxxxx with hardware_MPY
-
-\ https://forth-standard.org/standard/double/MTimesDiv
- [UNDEFINED] M*/
- [IF]
- CODE M*/ \ d1 * n1 / +n2 -- d2
- MOV 4(PSP),&MPYS32L \ 5 Load 1st operand d1lo
- MOV 2(PSP),&MPYS32H \ 5 d1hi
- MOV @PSP+,&OP2 \ 4 -- d1 n2 load 2nd operand n1
- MOV TOS,T \ T = DIV
- NOP3
- MOV &RES0,S \ 3 S = RESlo
- MOV &RES1,TOS \ 3 TOS = RESmi
- MOV &RES2,W \ 3 W = REShi
- MOV #0,rDOCON \ clear sign flag
- CMP #0,W \ negative product ?
- S< IF \ compute ABS value if yes
- XOR #-1,S
- XOR #-1,TOS
- XOR #-1,W
- ADD #1,S
- ADDC #0,TOS
- ADDC #0,W
- MOV #-1,rDOCON \ set sign flag
- THEN
+ CODE TSTBIT \ addr bit_mask -- true/flase flag
+ MOV @PSP+,X
+ AND @X,TOS
+ MOV @IP+,PC
+ ENDCODE
+
+ KERNEL_ADDON HMPY TSTBIT \ hardware MPY ?
+
+ RST_RET \ remove TSTBIT definition
+
+ [IF] ; MSP430FRxxxx with hardware_MPY
+
+ CODE M*/ \ d1 * n1 / +n2 -- d2
+ MOV 4(PSP),&MPYS32L \ 5 Load 1st operand d1lo
+ MOV 2(PSP),&MPYS32H \ 5 d1hi
+ MOV @PSP+,&OP2 \ 4 -- d1 n2 load 2nd operand n1
+ MOV TOS,T \ T = DIV
+ NOP3
+ MOV &RES0,S \ 3 S = RESlo
+ MOV &RES1,TOS \ 3 TOS = RESmi
+ MOV &RES2,W \ 3 W = REShi
+ MOV #0,rDOCON \ clear sign flag
+ CMP #0,W \ negative product ?
+ S< IF \ compute ABS value if yes
+ XOR #-1,S
+ XOR #-1,TOS
+ XOR #-1,W
+ ADD #1,S
+ ADDC #0,TOS
+ ADDC #0,W
+ MOV #-1,rDOCON \ set sign flag
+ THEN
- [ELSE] ; no hardware multiplier
-\ https://forth-standard.org/standard/double/MTimesDiv
- [UNDEFINED] M*/
- [IF]
- CODE M*/ \ d1lo d1hi n1 +n2 -- d2lo d2hi
- MOV #0,rDOCON \ rDOCON = sign
- CMP #0,2(PSP) \ d1 < 0 ?
- S< IF
- XOR #-1,4(PSP)
- XOR #-1,2(PSP)
- ADD #1,4(PSP)
- ADDC #0,2(PSP)
- MOV #-1,rDOCON
- THEN \ ud1
- CMP #0,0(PSP) \ n1 < 0 ?
- S< IF
- XOR #-1,0(PSP)
- ADD #1,0(PSP) \ u1
- XOR #-1,rDOCON
- THEN \ let's process UM* -- ud1lo ud1hi u1 +n2
- MOV 4(PSP),Y \ 3 uMDlo
- MOV 2(PSP),T \ 3 uMDhi
- MOV @PSP+,S \ 2 uMRlo -- ud1lo ud1hi +n2
- MOV #0,rDODOES \ 1 uMDlo=0
- MOV #0,2(PSP) \ 3 uRESlo=0
- MOV #0,0(PSP) \ 3 uRESmi=0 -- uRESlo uRESmi +n2
- MOV #0,W \ 1 uREShi=0
- MOV #1,X \ 1 BIT TEST REGlo
- BEGIN BIT X,S \ 1 test actual bit in uMRlo
- 0<> IF ADD Y,2(PSP) \ 3 IF 1: ADD uMDlo TO uRESlo
- ADDC T,0(PSP) \ 3 ADDC uMDmi TO uRESmi
- ADDC rDODOES,W \ 1 ADDC uMRlo TO uREShi
- THEN ADD Y,Y \ 1 (RLA LSBs) uMDlo *2
- ADDC T,T \ 1 (RLC MSBs) uMDhi *2
- ADDC rDODOES,rDODOES \ 1 (RLA LSBs) uMDlo *2
- ADD X,X \ 1 (RLA) NEXT BIT TO TEST
- U>= UNTIL \ 1 IF BIT IN CARRY: FINISHED W=uREShi
-\ TOS +n2
-\ W REShi
-\ 0(PSP) RESmi
-\ 2(PSP) RESlo
- MOV TOS,T
- MOV @PSP,TOS
- MOV 2(PSP),S
- [THEN]
+ [ELSE] ; no hardware multiplier
+
+ CODE M*/ \ d1lo d1hi n1 +n2 -- d2lo d2hi
+ MOV #0,rDOCON \ rDOCON = sign
+ CMP #0,2(PSP) \ d1 < 0 ?
+ S< IF
+ XOR #-1,4(PSP)
+ XOR #-1,2(PSP)
+ ADD #1,4(PSP)
+ ADDC #0,2(PSP)
+ MOV #-1,rDOCON
+ THEN \ ud1
+ CMP #0,0(PSP) \ n1 < 0 ?
+ S< IF
+ XOR #-1,0(PSP)
+ ADD #1,0(PSP) \ u1
+ XOR #-1,rDOCON
+ THEN \ let's process UM* -- ud1lo ud1hi u1 +n2
+ MOV 4(PSP),Y \ 3 uMDlo
+ MOV 2(PSP),T \ 3 uMDhi
+ MOV @PSP+,S \ 2 uMRlo -- ud1lo ud1hi +n2
+ MOV #0,rDODOES \ 1 uMDlo=0
+ MOV #0,2(PSP) \ 3 uRESlo=0
+ MOV #0,0(PSP) \ 3 uRESmi=0 -- uRESlo uRESmi +n2
+ MOV #0,W \ 1 uREShi=0
+ MOV #1,X \ 1 BIT TEST REGlo
+ BEGIN BIT X,S \ 1 test actual bit in uMRlo
+ 0<> IF ADD Y,2(PSP) \ 3 IF 1: ADD uMDlo TO uRESlo
+ ADDC T,0(PSP) \ 3 ADDC uMDmi TO uRESmi
+ ADDC rDODOES,W \ 1 ADDC uMRlo TO uREShi
+ THEN ADD Y,Y \ 1 (RLA LSBs) uMDlo *2
+ ADDC T,T \ 1 (RLC MSBs) uMDhi *2
+ ADDC rDODOES,rDODOES \ 1 (RLA LSBs) uMDlo *2
+ ADD X,X \ 1 (RLA) NEXT BIT TO TEST
+ U>= UNTIL \ 1 IF BIT IN CARRY: FINISHED W=uREShi
+\ TOS +n2
+\ W REShi
+\ 0(PSP) RESmi
+\ 2(PSP) RESlo
+ MOV TOS,T
+ MOV @PSP,TOS
+ MOV 2(PSP),S
[THEN] ; endcase of software/hardware_MPY
ENDCODE
[THEN]
+ [UNDEFINED] 2VARIABLE [IF]
\ https://forth-standard.org/standard/double/TwoVARIABLE
- [UNDEFINED] 2VARIABLE
- [IF]
: 2VARIABLE \ --
CREATE
HI2LO
ADD #4,&DP
MOV @RSP+,IP
- NEXT
+ MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] 2CONSTANT [IF]
\ https://forth-standard.org/standard/double/TwoCONSTANT
- [UNDEFINED] 2CONSTANT
- [IF]
: 2CONSTANT \ udlo/dlo/Flo udhi/dhi/Shi -- to create double or s15q16 CONSTANT
CREATE
- , , \ compile Shi then Flo
+ , , \ compile hi then lo
DOES>
2@ \ execution part
;
[THEN]
+ [UNDEFINED] 2VALUE [IF]
\ https://forth-standard.org/standard/double/TwoVALUE
- [UNDEFINED] 2VALUE
- [IF]
: 2VALUE \ x1 x2 "<spaces>name" --
CREATE , , \ compile Shi then Flo
DOES>
[THEN]
+ [UNDEFINED] 2LITERAL [IF]
\ https://forth-standard.org/standard/double/TwoLITERAL
- [UNDEFINED] 2LITERAL
- [IF]
- CODE 2LITERAL
- BIS #UF9,SR \ see LITERAL
- MOV #LITERAL,PC
- ENDCODE IMMEDIATE
+ CODE 2LITERAL
+ BIS #UF9,SR \ see LITERAL
+ MOV #LITERAL,PC
+ ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] D.R [IF]
\ https://forth-standard.org/standard/double/DDotR
\ D.R d n --
- [UNDEFINED] D.R
- [IF]
: D.R
>R SWAP OVER DABS <# #S ROT SIGN #>
R> OVER - SPACES TYPE
RST_SET
-\ ==============================================================================
+ [THEN] \ endof [UNDEFINED] {DOUBLE}
+
+; -------------------------------
; Complement to pass DOUBLE TESTS
-\ ==============================================================================
+; -------------------------------
+
+ [UNDEFINED] SWAP [IF]
+\ https://forth-standard.org/standard/core/SWAP
+\ SWAP x1 x2 -- x2 x1 swap top two items
+ CODE SWAP
+ MOV @PSP,W \ 2
+ MOV TOS,0(PSP) \ 3
+ MOV W,TOS \ 1
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+ [UNDEFINED] VARIABLE [IF]
\ https://forth-standard.org/standard/core/VARIABLE
-\ VARIABLE <name> -- define a Forth VARIABLE
- [UNDEFINED] VARIABLE
- [IF]
+\ VARIABLE <name> -- define a Forth VARIABLE
: VARIABLE
CREATE
HI2LO
- MOV #DOVAR,-4(W) \ CFA = CALL rDOVAR
+ MOV #DOVAR,-4(W) \ CFA = CALL rDOVAR
MOV @RSP+,IP
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] CONSTANT [IF]
\ https://forth-standard.org/standard/core/CONSTANT
-\ CONSTANT <name> n -- define a Forth CONSTANT
- [UNDEFINED] CONSTANT
- [IF]
+\ CONSTANT <name> n -- define a Forth CONSTANT
: CONSTANT
CREATE
HI2LO
- MOV TOS,-2(W) \ PFA = n
+ MOV TOS,-2(W) \ PFA = n
MOV @PSP+,TOS
MOV @RSP+,IP
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] CELLS [IF]
\ https://forth-standard.org/standard/core/CELLS
\ CELLS n1 -- n2 cells->adrs units
- [UNDEFINED] CELLS
- [IF]
CODE CELLS
ADD TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] DEPTH [IF]
\ https://forth-standard.org/standard/core/DEPTH
\ DEPTH -- +n number of items on stack, must leave 0 if stack empty
- [UNDEFINED] DEPTH
- [IF]
CODE DEPTH
MOV TOS,-2(PSP)
MOV #PSTACK,TOS
ENDCODE
[THEN]
- [UNDEFINED] DO
- [IF] \ define DO LOOP +LOOP
+ [UNDEFINED] IF [IF] \ define IF THEN
+\ https://forth-standard.org/standard/core/IF
+\ IF -- IFadr initialize conditional forward branch
+ CODE IF \ immediate
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \
+ MOV &DP,TOS \ -- HERE
+ ADD #4,&DP \ compile one word, reserve one word
+ MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN
+ ADD #2,TOS \ -- HERE+2=IFadr
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/THEN
+\ THEN IFadr -- resolve forward branch
+ CODE THEN \ immediate
+ MOV &DP,0(TOS) \ -- IFadr
+ MOV @PSP+,TOS \ --
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] ELSE [IF]
+\ https://forth-standard.org/standard/core/ELSE
+\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
+ CODE ELSE \ immediate
+ ADD #4,&DP \ make room to compile two words
+ MOV &DP,W \ W=HERE+4
+ MOV #BRAN,-4(W)
+ MOV W,0(TOS) \ HERE+4 ==> [IFadr]
+ SUB #2,W \ HERE+2
+ MOV W,TOS \ -- ELSEadr
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] DO [IF] \ define DO LOOP +LOOP
\ https://forth-standard.org/standard/core/DO
\ DO -- DOadr L: -- 0
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] I [IF]
\ https://forth-standard.org/standard/core/I
\ I -- n R: sys1 sys2 -- sys1 sys2
\ get the innermost loop index
- [UNDEFINED] I
- [IF]
CODE I
SUB #2,PSP \ 1 make room in TOS
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] + [IF]
\ https://forth-standard.org/standard/core/Plus
\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
- [UNDEFINED] +
- [IF]
CODE +
ADD @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] = [IF]
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
- [UNDEFINED] =
- [IF]
CODE =
SUB @PSP+,TOS \ 2
0<> IF \ 2
ENDCODE
[THEN]
+ [UNDEFINED] 0= [IF]
\ https://forth-standard.org/standard/core/ZeroEqual
\ 0= n/u -- flag return true if TOS=0
- [UNDEFINED] 0=
- [IF]
CODE 0=
SUB #1,TOS \ borrow (clear cy) if TOS was 0
SUBC TOS,TOS \ TOS=-1 if borrow was set
ENDCODE
[THEN]
+ [UNDEFINED] SOURCE [IF]
\ https://forth-standard.org/standard/core/SOURCE
\ SOURCE -- adr u of current input buffer
- [UNDEFINED] SOURCE
- [IF]
CODE SOURCE
SUB #4,PSP
MOV TOS,2(PSP)
ENDCODE
[THEN]
+ [UNDEFINED] >IN [IF]
\ https://forth-standard.org/standard/core/toIN
\ C >IN -- a-addr holds offset in input stream
- [UNDEFINED] >IN
- [IF]
TOIN CONSTANT >IN
[THEN]
+ [UNDEFINED] 1+ [IF]
\ https://forth-standard.org/standard/core/OnePlus
\ 1+ n1/u1 -- n2/u2 add 1 to TOS
- [UNDEFINED] 1+
- [IF]
CODE 1+
ADD #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] CHAR [IF]
\ https://forth-standard.org/standard/core/CHAR
\ CHAR -- char parse ASCII character
- [UNDEFINED] CHAR
- [IF]
: CHAR
$20 WORD 1+ C@
;
[THEN]
+ [UNDEFINED] [CHAR] [IF]
\ https://forth-standard.org/standard/core/BracketCHAR
\ [CHAR] -- compile character literal
- [UNDEFINED] [CHAR]
- [IF]
: [CHAR]
CHAR POSTPONE LITERAL
; IMMEDIATE
[THEN]
+ [UNDEFINED] 2/ [IF]
\ https://forth-standard.org/standard/core/TwoDiv
\ 2/ x1 -- x2 arithmetic right shift
- [UNDEFINED] 2/
- [IF]
CODE 2/
RRA TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] INVERT [IF]
\ https://forth-standard.org/standard/core/INVERT
\ INVERT x1 -- x2 bitwise inversion
- [UNDEFINED] INVERT
- [IF]
CODE INVERT
XOR #-1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] RSHIFT [IF]
\ https://forth-standard.org/standard/core/RSHIFT
\ RSHIFT x1 u -- x2 logical R7 shift u places
- [UNDEFINED] RSHIFT
- [IF]
CODE RSHIFT
MOV @PSP+,W
AND #$1F,TOS \ no need to shift more than 16
ENDCODE
[THEN]
+ [UNDEFINED] S>D [IF]
\ https://forth-standard.org/standard/core/StoD
\ S>D n -- d single -> double prec.
- [UNDEFINED] S>D
- [IF]
: S>D
DUP 0<
;
[THEN]
+ [UNDEFINED] 1- [IF]
\ https://forth-standard.org/standard/core/OneMinus
\ 1- n1/u1 -- n2/u2 subtract 1 from TOS
- [UNDEFINED] 1-
- [IF]
CODE 1-
SUB #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] NEGATE [IF]
\ https://forth-standard.org/standard/core/NEGATE
\ C NEGATE x1 -- x2 two's complement
- [UNDEFINED] NEGATE
- [IF]
CODE NEGATE
XOR #-1,TOS
ADD #1,TOS
ENDCODE
[THEN]
- [UNDEFINED] HERE
- [IF]
+ [UNDEFINED] HERE [IF]
CODE HERE
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE
[THEN]
+ [UNDEFINED] CHARS [IF]
\ https://forth-standard.org/standard/core/CHARS
\ CHARS n1 -- n2 chars->adrs units
- [UNDEFINED] CHARS
- [IF]
CODE CHARS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] MOVE [IF]
\ https://forth-standard.org/standard/core/MOVE
\ MOVE addr1 addr2 u -- smart move
\ VERSION FOR 1 ADDRESS UNIT = 1 CHAR
- [UNDEFINED] MOVE
- [IF]
CODE MOVE
MOV TOS,W \ W = cnt
MOV @PSP+,Y \ Y = addr2 = dst
ENDCODE
[THEN]
+ [UNDEFINED] DECIMAL [IF]
\ https://forth-standard.org/standard/core/DECIMAL
- [UNDEFINED] DECIMAL
- [IF]
CODE DECIMAL
MOV #$0A,&BASEADR
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] BASE [IF]
\ https://forth-standard.org/standard/core/BASE
\ BASE -- a-addr holds conversion radix
- [UNDEFINED] BASE
- [IF]
BASEADR CONSTANT BASE
[THEN]
+ [UNDEFINED] ( [IF]
\ https://forth-standard.org/standard/core/p
\ ( -- skip input until char ) or EOL
- [UNDEFINED] ( ; )
- [IF]
: (
')' WORD DROP
; IMMEDIATE
[THEN]
+ [UNDEFINED] .( [IF] ; "
\ https://forth-standard.org/standard/core/Dotp
\ .( -- type comment immediatly.
- [UNDEFINED] .( ; "
- [IF]
CODE .( ; "
MOV #0,&CAPS \ CAPS OFF
COLON
')' WORD
COUNT TYPE
- $20 CAPS ! \ CAPS ON
+ $20 CAPS ! \ CAPS ON
; IMMEDIATE
[THEN]
+ [UNDEFINED] CR [IF]
\ https://forth-standard.org/standard/core/CR
\ CR -- send CR+LF to the output device
- [UNDEFINED] CR
- [IF]
- DEFER CR \ DEFERed definition, by default executes that of :NONAME
+\ DEFER CR \ DEFERed definition, by default executes :NONAME part
+ CODE CR \ replaced by this CODE definition
+ MOV #NEXT_ADR,PC
+ ENDCODE
:NONAME
'CR' EMIT 'LF' EMIT
\ - tester.fr (or ttester.fs), errorreport.fth and utilities.fth have been
\ included prior to this file
\ - the Core word set is available and tested
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING interpreter and compiler reading double numbers, with/without prefixes
T{ 1. -> 1 0 }T
T{ $-12AbCdEf. -> -313249263. }T
T{ %10010110. -> 150. }T
T{ %-10010110. -> -150. }T
-\ Check BASE is unchanged
+; Check BASE is unchanged
T{ BASE @ OLD-DBASE @ = -> TRUE }T
-\ Repeat in Hex mode
+; Repeat in Hex mode
16 OLD-DBASE ! 16 BASE !
T{ #12346789. -> BC65A5. }T
T{ #-12346789. -> -BC65A5. }T
T{ $-12AbCdEf. -> -12ABCDef. }T
T{ %10010110. -> 96. }T
T{ %-10010110. -> -96. }T
-\ Check BASE is unchanged
+; Check BASE is unchanged
T{ BASE @ OLD-DBASE @ = -> TRUE }T \ 2
DECIMAL
-\ Check number prefixes in compile mode
+; Check number prefixes in compile mode
T{ : dnmp #8327. $-2cbe. %011010111. ; dnmp -> 8327. -11454. 215. }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING 2CONSTANT
T{ 1 2 2CONSTANT 2C1 -> }T
T{ 4 5 2CONSTANT 2C3 IMMEDIATE 2C3 -> 4 5 }T
T{ : CD6 2C3 2LITERAL ; CD6 -> 4 5 }T
-\ ------------------------------------------------------------------------------
-\ Some 2CONSTANTs for the following tests
+; ----------------------------------------------------------------------------
+; Some 2CONSTANTs for the following tests
1SD MAX-INTD 2CONSTANT MAX-2INT \ 01...1
0 MIN-INTD 2CONSTANT MIN-2INT \ 10...0
MAX-2INT 2/ 2CONSTANT HI-2INT \ 001...1
MIN-2INT 2/ 2CONSTANT LO-2INT \ 110...0
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING DNEGATE
T{ 0. DNEGATE -> 0. }T
T{ MAX-2INT DNEGATE -> MIN-2INT SWAP 1+ SWAP }T
T{ MIN-2INT SWAP 1+ SWAP DNEGATE -> MAX-2INT }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING D+ with small integers
T{ 0. 5. D+ -> 5. }T
T{ HI-2INT MIN-2INT D+ 1. D+ -> LO-2INT }T
T{ LO-2INT 2DUP D+ -> MIN-2INT }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING D- with small integers
T{ 0. 5. D- -> -5. }T
T{ MIN-2INT MIN-2INT D- -> 0. }T
T{ MIN-2INT LO-2INT D- -> LO-2INT }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING D0< D0=
T{ 0. D0< -> FALSE }T
T{ -1. D0= -> FALSE }T
T{ 0 MIN-INTD D0= -> FALSE }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING D2* D2/
T{ 0. D2* -> 0. D2* }T
T{ -1. D2/ -> -1. }T
T{ MIN-2INT D2/ -> LO-2INT }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING D< D=
T{ 0. 1. D< -> TRUE }T
T{ MIN-2INT LO-2INT D= -> FALSE }T
T{ MIN-2INT MAX-2INT D= -> FALSE }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING 2LITERAL 2VARIABLE
T{ : CD3 [ MAX-2INT ] 2LITERAL ; -> }T
T{ : CD7 2V3 [ 2@ ] 2LITERAL ; CD7 -> 5 6 }T
T{ : CD8 [ 6 7 ] 2V3 [ 2! ] ; 2V3 2@ -> 6 7 }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING DMAX DMIN
T{ 1. 2. DMAX -> 2. }T
T{ MIN-2INT 1. DMIN -> MIN-2INT }T
T{ MIN-2INT -1. DMIN -> MIN-2INT }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING D>S DABS
T{ 1234 0 D>S -> 1234 }T
T{ MAX-2INT DABS -> MAX-2INT }T
T{ MIN-2INT 1. D+ DABS -> MAX-2INT }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING M+ M*/
T{ HI-2INT 1 M+ -> HI-2INT 1. D+ }T
T{ MIN-2INT 1 M+ -> MIN-2INT 1. D+ }T
T{ LO-2INT -1 M+ -> LO-2INT -1. D+ }T
-\ To correct the result if the division is floored, only used when
-\ necessary i.e. negative quotient and remainder <> 0
+; To correct the result if the division is floored, only used when
+; necessary i.e. negative quotient and remainder <> 0
: ?FLOORED [ -3 2 / -2 = ] LITERAL IF 1. D- THEN ;
T{ MAX-2INT LO-2INT NIP DUP NEGATE M*/ -> MAX-2INT DNEGATE }T
T{ MIN-2INT MAX-INTD DUP M*/ -> MIN-2INT }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING D. D.R
-\ Create some large double numbers
+; Create some large double numbers
MAX-2INT 71 73 M*/ 2CONSTANT DBL1
MIN-2INT 73 79 M*/ 2CONSTANT DBL2
;
T{ DOUBLEOUTPUT -> }T
-
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING 2ROT DU< (Double Number extension words)
T{ 1. 2. 3. 2ROT -> 2. 3. 1. }T
T{ MIN-2INT MAX-2INT DU< -> FALSE }T
T{ MIN-2INT LO-2INT DU< -> TRUE }T
-\ ------------------------------------------------------------------------------
+; ----------------------------------------------------------------------------
TESTING 2VALUE
T{ 1111 2222 2VALUE 2VAL -> }T
T{ : TO-2VAL TO 2VAL ; 5555 6666 TO-2VAL -> }T
T{ 2VAL -> 5555 6666 }T
-\ ------------------------------------------------------------------------------
-
CR .( End of Double-Number word tests) CR
\ MSP_EXP430FR4133 CHIPSTICK_FR2433 MSP_EXP430FR2433 MSP_EXP430FR2355
\ LP_MSP430FR2476
\ MY_MSP430FR5738_2
+\ JMJ_BOX_2018_10_29
\
\ from scite editor : copy your TARGET selection in (shift+F8) parameter 1:
\ copy COMPLEMENT if used in (shift+F8) parameter 2:
SUB #2,PSP
MOV TOS,0(PSP)
MOV &VERSION,TOS \ ARG
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
- 'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
+ 'CR' EMIT \ return to column 1, no 'LF'
+ ABORT" FastForth V4.0 please!"
RST_RET \ remove ABORT_FF_SPECS definition before resuming
;
- ABORT_FF_SPECS
+ ABORT_FF_SPECS \ run tests
+; ------------------------------------------------------------------
+; first we download the set of definitions we need, from CORE_ANS
+; ------------------------------------------------------------------
+
+ [UNDEFINED] DUP [IF] \ define DUP and DUP?
\ https://forth-standard.org/standard/core/DUP
\ DUP x -- x x duplicate top of stack
- [UNDEFINED] DUP
- [IF] \ define DUP and DUP?
CODE DUP
BW1 SUB #2,PSP \ 2 push old TOS..
MOV TOS,0(PSP) \ 3 ..onto stack
ENDCODE
[THEN]
+ [UNDEFINED] OVER [IF]
\ https://forth-standard.org/standard/core/OVER
\ OVER x1 x2 -- x1 x2 x1
- [UNDEFINED] OVER
- [IF]
CODE OVER
MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
MOV @PSP,TOS \ 2 -- x1 (x2) x1
ENDCODE
[THEN]
+ [UNDEFINED] DROP [IF]
\ https://forth-standard.org/standard/core/DROP
\ DROP x -- drop top of stack
- [UNDEFINED] DROP
- [IF]
CODE DROP
MOV @PSP+,TOS \ 2
MOV @IP+,PC \ 4
ENDCODE
[THEN]
+ [UNDEFINED] SWAP [IF]
\ https://forth-standard.org/standard/core/SWAP
\ SWAP x1 x2 -- x2 x1 swap top two items
- [UNDEFINED] SWAP
- [IF]
CODE SWAP
MOV @PSP,W \ 2
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] ROT [IF]
\ https://forth-standard.org/standard/core/ROT
\ ROT x1 x2 x3 -- x2 x3 x1
- [UNDEFINED] ROT
- [IF]
CODE ROT
MOV @PSP,W \ 2 fetch x2
MOV TOS,0(PSP) \ 3 store x3
ENDCODE
[THEN]
+ [UNDEFINED] >R [IF]
\ https://forth-standard.org/standard/core/toR
\ >R x -- R: -- x push to return stack
- [UNDEFINED] >R
- [IF]
CODE >R
PUSH TOS
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] R> [IF]
\ https://forth-standard.org/standard/core/Rfrom
\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
- [UNDEFINED] R>
- [IF]
CODE R>
SUB #2,PSP \ 1
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] 0< [IF]
\ https://forth-standard.org/standard/core/Zeroless
\ 0< n -- flag true if TOS negative
- [UNDEFINED] 0<
- [IF]
CODE 0<
ADD TOS,TOS \ 1 set carry if TOS negative
SUBC TOS,TOS \ 1 TOS=-1 if carry was clear
ENDCODE
[THEN]
+ [UNDEFINED] = [IF]
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
- [UNDEFINED] =
- [IF]
CODE =
SUB @PSP+,TOS \ 2
0<> IF \ 2
ENDCODE
[THEN]
+ [UNDEFINED] U< [IF] \ define U> and U>
\ https://forth-standard.org/standard/core/Uless
\ U< u1 u2 -- flag test u1<u2, unsigned
- [UNDEFINED] U<
- [IF]
CODE U<
SUB @PSP+,TOS \ 2 u2-u1
U< ?GOTO FW1
ENDCODE
[THEN]
+ [UNDEFINED] IF [IF] \ define IF and THEN
\ https://forth-standard.org/standard/core/IF
\ IF -- IFadr initialize conditional forward branch
- [UNDEFINED] IF
- [IF] \ define IF and THEN
CODE IF
SUB #2,PSP \
MOV TOS,0(PSP) \
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] ELSE [IF]
\ https://forth-standard.org/standard/core/ELSE
\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
- [UNDEFINED] ELSE
- [IF]
CODE ELSE
ADD #4,&DP \ make room to compile two words
MOV &DP,W \ W=HERE+4
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
+
\ https://forth-standard.org/standard/core/BEGIN
\ BEGIN -- BEGINadr initialize backward branch
- [UNDEFINED] BEGIN
- [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
CODE BEGIN
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE IMMEDIATE
\ https://forth-standard.org/standard/core/UNTIL
MOV #BRAN,X
GOTO BW1
ENDCODE IMMEDIATE
- [THEN]
- [UNDEFINED] WHILE
- [IF] \
\ https://forth-standard.org/standard/core/WHILE
\ WHILE BEGINadr -- WHILEadr BEGINadr
: WHILE
POSTPONE IF SWAP
; IMMEDIATE
- [THEN]
- [UNDEFINED] REPEAT
- [IF]
\ https://forth-standard.org/standard/core/REPEAT
\ REPEAT WHILEadr BEGINadr -- resolve WHILE loop
: REPEAT
; IMMEDIATE
[THEN]
-\ https://forth-standard.org/standard/core/DO
-\ DO -- DOadr L: -- 0
- [UNDEFINED] DO
- [IF] \ define DO LOOP +LOOP
+ [UNDEFINED] DO [IF] \ define DO LOOP +LOOP
+
HDNCODE XDO \ DO run time
MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor"
SUB @PSP+,X \ 2
MOV TOS,Y \ 1 loop ctr = index+fudge
ADD X,Y \ 1 Y = INDEX
- PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX
+ PUSHM #Z,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX
MOV @PSP+,TOS \ 2
MOV @IP+,PC \ 4
ENDCODE
+\ https://forth-standard.org/standard/core/DO
+\ DO -- DOadr L: -- 0
CODE DO
SUB #2,PSP \
MOV TOS,0(PSP) \
MOV @IP+,PC
ENDCODE IMMEDIATE
-\ https://forth-standard.org/standard/core/LOOP
-\ LOOP DOadr -- L-- an an-1 .. a1 0
HDNCODE XLOOP \ LOOP run time
ADD #1,0(RSP) \ 4 increment INDEX
BW1 BIT #$100,SR \ 2 is overflow bit set?
MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop
ENDCODE \
+\ https://forth-standard.org/standard/core/LOOP
+\ LOOP DOadr -- L-- an an-1 .. a1 0
CODE LOOP
MOV #XLOOP,X
BW2 ADD #4,&DP \ make room to compile two words
MOV @IP+,PC
ENDCODE IMMEDIATE
-\ https://forth-standard.org/standard/core/PlusLOOP
-\ +LOOP adrs -- L-- an an-1 .. a1 0
HDNCODE XPLOO \ +LOOP run time
ADD TOS,0(RSP) \ 4 increment INDEX by TOS value
MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags
GOTO BW1 \ 2
ENDCODE \
+\ https://forth-standard.org/standard/core/PlusLOOP
+\ +LOOP adrs -- L-- an an-1 .. a1 0
CODE +LOOP
MOV #XPLOO,X
GOTO BW2
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] I [IF]
\ https://forth-standard.org/standard/core/I
\ I -- n R: sys1 sys2 -- sys1 sys2
\ get the innermost loop index
- [UNDEFINED] I
- [IF]
CODE I
SUB #2,PSP \ 1 make room in TOS
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
- [UNDEFINED] HERE
- [IF]
+ [UNDEFINED] HERE [IF]
CODE HERE
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE
[THEN]
+ [UNDEFINED] C@ [IF]
\ https://forth-standard.org/standard/core/CFetch
\ C@ c-addr -- char fetch char from memory
- [UNDEFINED] C@
- [IF]
CODE C@
MOV.B @TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] SPACES [IF]
\ https://forth-standard.org/standard/core/SPACES
\ SPACES n -- output n spaces
- [UNDEFINED] SPACES
- [IF]
CODE SPACES
CMP #0,TOS
0<> IF
ENDCODE
[THEN]
+ [UNDEFINED] 1+ [IF]
\ https://forth-standard.org/standard/core/OnePlus
\ 1+ n1/u1 -- n2/u2 add 1 to TOS
- [UNDEFINED] 1+
- [IF]
CODE 1+
ADD #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] + [IF]
\ https://forth-standard.org/standard/core/Plus
\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
- [UNDEFINED] +
- [IF]
CODE +
ADD @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] - [IF]
\ https://forth-standard.org/standard/core/Minus
\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
- [UNDEFINED] -
- [IF]
CODE -
SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3)
XOR #-1,TOS \ 1
ENDCODE
[THEN]
+ [UNDEFINED] 2* [IF]
\ https://forth-standard.org/standard/core/TwoTimes
\ 2* x1 -- x2 arithmetic left shift
- [UNDEFINED] 2*
- [IF]
CODE 2*
ADD TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] 2/ [IF]
\ https://forth-standard.org/standard/core/TwoDiv
\ 2/ x1 -- x2 arithmetic right shift
- [UNDEFINED] 2/
- [IF]
CODE 2/
RRA TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] UM/MOD [IF]
\ https://forth-standard.org/standard/core/UMDivMOD
\ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16
- [UNDEFINED] UM/MOD
- [IF]
CODE UM/MOD
PUSH #DROP \
MOV #MUSMOD,PC \ execute MUSMOD then return to DROP
ENDCODE
[THEN]
+ [UNDEFINED] MOVE [IF]
\ https://forth-standard.org/standard/core/MOVE
\ MOVE addr1 addr2 u -- smart move
\ VERSION FOR 1 ADDRESS UNIT = 1 CHAR
- [UNDEFINED] MOVE
- [IF]
CODE MOVE
MOV TOS,W \ W = cnt
MOV @PSP+,Y \ Y = addr2 = dst
ENDCODE
[THEN]
+ [UNDEFINED] CR [IF]
\ https://forth-standard.org/standard/core/CR
\ CR -- send CR+LF to the output device
- [UNDEFINED] CR
- [IF]
\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition
CODE CR \ part I : DEFERed definition of CR
[THEN]
-\ customised WORD
- : WORDS \ VOC_BODY --
- PAD_ORG \ -- VOC_BODY PAD MOVE all threads of VOC_BODY in PAD_ORG
- THREADS @ 2* \ -- VOC_BODY PAD THREADS*2
- MOVE \ -- vocabulary entries are copied in PAD_ORG
- BEGIN \ --
- 0 DUP \ -- ptr=0 MAX=0
- THREADS @ 2* 0 \ -- ptr=0 MAX=0 THREADS*2 0
- DO \ -- ptr MAX I = PAD_ptr = thread*2
- DUP I PAD_ORG + @ \ -- ptr MAX MAX NFAx
- U< IF \ -- ptr MAX if MAX U< NFAx
- DROP DROP \ -- drop ptr and MAX
- I DUP PAD_ORG + @ \ -- new_ptr new_MAX
- THEN \
- 2 +LOOP \ -- ptr MAX
- ?DUP \ -- ptr MAX MAX | -- ptr 0 (all threads in PAD = 0)
- WHILE \ -- ptr MAX replace it by its LFA
- DUP \ -- ptr MAX MAX
- 2 - @ \ -- ptr MAX [LFA]
- ROT \ -- MAX [LFA] ptr
- PAD_ORG + \ -- MAX [LFA] thread
- ! \ -- MAX MAX=highest_NFA [LFA]=new_NFA updates PAD_ORG+ptr
- COUNT 2/ \ -- addr name_count 2/ to hide Immediate flag
- DUP >R TYPE \ -- R-- count
- $10 R> - SPACES \ -- R-- complete with spaces modulo 16 chars
- REPEAT \ --
- DROP \ ptr --
- ; \ all threads in PAD are filled with 0
+ [UNDEFINED] CASE [IF] \ define CASE OF ENDOF ENDCASE
\ https://forth-standard.org/standard/core/CASE
- [UNDEFINED] CASE
- [IF]
: CASE
0
; IMMEDIATE \ -- #of-1
; IMMEDIATE
[THEN]
- [UNDEFINED] S_
- [IF]
- CODE S_ \ Squote alias with blank instead quote separator
- MOV #0,&CAPS \ turn CAPS OFF
- COLON
- XSQUOTE , \ compile run-time code
- 'SP' WORD \ -- c-addr (= HERE)
- HI2LO
- MOV.B @TOS,TOS \ -- len compile string
- ADD #1,TOS \ -- len+1
- BIT #1,TOS \ C = ~Z
- ADDC TOS,&DP \ store aligned DP
- MOV @PSP+,TOS \ --
- MOV @RSP+,IP \ pop paired with push COLON
- MOV #$20,&CAPS \ turn CAPS ON (default state)
- MOV @IP+,PC \ NEXT
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ [UNDEFINED] S? [IF] \
+ CODE S? \ to compile: sep S? <string>sep
+ MOV #S"+10,PC \ (S" + 10) --> PC
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] ESC
- [IF]
+ [UNDEFINED] ESC [IF]
CODE ESC
CMP #0,&STATEADR
0= IF MOV @IP+,PC \ interpret time usage disallowed
'ESC' \ -- char escape
POSTPONE LITERAL \ compile-time code : lit 'ESC'
POSTPONE EMIT \ compile-time code : EMIT
- POSTPONE S_ \ compile-time code : S_ <escape_sequence>
+ 'SP' \ char SPACE as separator for next string
+ POSTPONE S? \ compile-time code : S?
POSTPONE TYPE \ compile-time code : TYPE
; IMMEDIATE
[THEN]
- [DEFINED] FORTH \ word-set addon ?
- [IF]
+ [DEFINED] FORTH [IF] \ word-set addon ?
CODE BODY>SQNFA \ BODY -- ADR cnt BODY > SQuoteNFA
SUB #2,PSP
SUB #4,TOS
0<> WHILE \ out of loop if yes
MOV @PSP,X \ loop back to test with X - one_word
REPEAT
- MOV X,0(PSP) \ -- string_addr string_cnt
+ MOV X,0(PSP) \ -- string_addr string_cnt of NFA
MOV @IP+,PC
ENDCODE
[THEN]
-\ -------------------------------------------------------
: SPECS \ to see all FastForth specifications
-\ -------------------------------------------------------
- RST_RET \ before computing free bytes, remove all FF_SPECS definitions
+\
+ RST_RET \ before computing free bytes, remove all FF_SPECS previous definitions
ECHO
ESC [8;42;80t \ set 42L * 80C terminal display
-
+\
\ title in reverse video
ESC [7m \ Turn reverse video on
CR ." FastForth V"
HERE \ HERE - MAIN_ORG = bytes code
DEVICEID @ \ value kept in TLV area
CASE
-
+\
\ device_ID OF ." xxxx," $MAIN_ORG ENDOF \ <-- add here your device
$8102 OF ." 5738," $C200 ENDOF
$8103 OF ." 5739," $C200 ENDOF
$8240 OF ." 2433," $C400 ENDOF
$825D OF ." 5972," $4400 ENDOF
$82A1 OF ." 5994," $4000 ENDOF
- $82A6 OF ." 5962," $4000 ENDOF
$830C OF ." 2355," $8000 ENDOF
$830D OF ." 2353," $C000 ENDOF
$831E OF ." 2155," $8000 ENDOF
$833D OF ." 2533," $C400 ENDOF
ABORT" xxxx <-- unrecognized device!"
ENDCASE \ -- HERE MAIN_ORG
+ ." DTC"
['] ['] DUP @ $1284 = \ DOCOL = CALL rDOCOL opcode
- IF ." DTC=1," DROP \ [CFA] = CALL rDOCOL
+ IF ." =1," DROP \ [CFA] = CALL rDOCOL
ELSE 2 + @ $1284 = \
- IF ." DTC=2," \ [CFA] = PUSH IP, [CFA+2] = CALL rDOCOL
- ELSE ." DTC=3," \ [CFA] = PUSH IP, [CFA+2] = MOV PC,IP
+ IF ." =2," \ [CFA] = PUSH IP, [CFA+2] = CALL rDOCOL
+ ELSE ." =3," \ [CFA] = PUSH IP, [CFA+2] = MOV PC,IP
THEN
THEN
'SP' EMIT
THEN ." MHz, " \ MCLK
- U. ." bytes" \ HERE - MAIN_ORG = number of bytes code,
ESC [0m \ Turn off character attributes
-
+\
\ general
CR
." /COUNTED-STRING = 255" CR
." /HOLD = 34" CR
." /PAD = 84" CR
." ADDRESS-UNIT-BITS = 16" CR
+ [DEFINED] {CORE_ANS}
+ [IF]
." FLOORED DIVISION = "
KERNEL_ADDON @ \ negative value if FLOORED DIVISION
0< IF ." true"
ELSE ." false"
THEN CR
+ [THEN]
." MAX-CHAR = 255" CR
." MAX-N = 32767" CR
." MAX-U = 65535" CR
." MAX-UD = 4294967295" CR
." STACK-CELLS = 48" CR
." RETURN-STACK-CELLS= 48" CR
- ." Definitions are forced to UPPERCASE." CR
-
+ ." Definitions are always UPPERCASE." CR
+\
\ kernel specs
CR ESC [7m ." Kernel add-ons" ESC [0m CR \ subtitle in reverse video
KERNEL_ADDON @
THEN
." with TI's syntax" CR
THEN DROP \ BIT2 to BIT0 are free
- [DEFINED] FORTH [IF] ." word-set management" CR
+ [DEFINED] FORTH [IF] ." word-set management" CR
[THEN]
[DEFINED] LOAD" [IF] ." SD_CARD Load" CR
[THEN]
[THEN]
[DEFINED] READ" [IF] ." SD_CARD Read/Write" CR
[THEN]
-
-\ word-set
+\
+\ display word-sets
LASTVOC \ -- VOCLINK addr.
BEGIN
@ ?DUP \ -- VOCLINK word-set here ?
WHILE \ -- VLK
+\ --------------------------------\
+ CR ESC [7m \ word-set TITLE in reverse video
DUP THREADS @ 2* - \ -- VLK WORDSET_BODY
- CR ESC [7m
[DEFINED] FORTH \ word-set addon ?
[IF] DUP BODY>SQNFA \ -- VLK WRDST_BODY addr cnt
[ELSE] OVER @ \ -- VLK WRDST_BODY NEXT_VLINK
ELSE S" FORTH" \ if next_vlink = 0
THEN \ -- VLK WRDST_BODY addr cnt
[THEN]
- TYPE ." word-set" \ -- VLK WRDST_BODY subtitle in reverse video
+ TYPE ." word-set" \ -- VLK WRDST_BODY
ESC [0m CR
- WORDS CR \ -- VLINK definitions display
+\ --------------------------------\ block of DEFINITIONS
+\ : WORDS \ VOC_BODY -- customized WORD definition
+ PAD_ORG \ -- VOC_BODY PAD MOVE all threads from VOC_BODY to PAD_ORG
+ THREADS @ 2* \ -- VOC_BODY PAD THREADS*2
+ MOVE \ -- vocabulary entries are copied in PAD_ORG
+ BEGIN \ --
+ 0 DUP \ -- ptr=0 MAX=0
+ THREADS @ 2* 0 \ -- ptr=0 MAX=0 THREADS*2 0
+ DO \ -- ptr MAX I = PAD_ptr = thread*2
+ DUP I PAD_ORG + @ \ -- ptr MAX MAX NFAx
+ U< IF \ -- ptr MAX if MAX U< NFAx
+ DROP DROP \ -- drop ptr and MAX
+ I DUP PAD_ORG + @ \ -- new_ptr new_MAX
+ THEN \
+ 2 +LOOP \ -- ptr MAX
+ ?DUP \ -- ptr MAX MAX | -- ptr 0 (all threads in PAD = 0)
+ WHILE \ -- ptr MAX replace it by its LFA
+ DUP \ -- ptr MAX MAX
+ 2 - @ \ -- ptr MAX [LFA]
+ ROT \ -- MAX [LFA] ptr
+ PAD_ORG + \ -- MAX [LFA] thread
+ ! \ -- MAX MAX=highest_NFA [LFA]=new_NFA updates PAD_ORG+ptr
+ COUNT 2/ \ -- addr name_count 2/ to hide Immediate flag
+ DUP >R TYPE \ -- R-- count
+ $10 R> - SPACES \ -- R-- complete with spaces modulo 16 chars
+ REPEAT \ --
+ DROP \ ptr --
+\ ; \ all threads in PAD are filled with 0
+\ --------------------------------\
+ CR \ -- VLINK definitions display
REPEAT
-
+ DROP
+\
\ extensions
CR ESC [7m ." EXTENSIONS" ESC [0m \ subtitle in reverse video
- [DEFINED] {CORE_ANS} [IF] CR ." core ANS94"
+ [DEFINED] {CORE_ANS} [IF] CR ." CORE ANS94"
[THEN]
- [DEFINED] {DOUBLE} [IF] CR ." DOUBLE word set"
+ [DEFINED] {DOUBLE} [IF] CR ." DOUBLE numbers set"
[THEN]
[DEFINED] {UTILITY} [IF] CR ." UTILITY"
[THEN]
[DEFINED] {UARTI2CS} [IF] CR ." UART to I2C_FastForth bridge"
[THEN]
CR
- 0 SYS \ WARM
+ SYS \ WARM
;
SPECS \ performs RST_RET and displays FastForth specs
\ ASSEMBLER conditionnal usage with ?JMP ?GOTO S< S>= U< U>= 0= 0<> 0<
\
+; -----------------------------------------------------
+; FIXPOINT.f
+; -----------------------------------------------------
+
CODE ABORT_FIXPOINT
SUB #4,PSP
MOV TOS,2(PSP)
0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT input), set TOS = 0
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
- $0D EMIT \ return to column 1 without CR
- ABORT" FastForth V3.9 please!"
+ $0D EMIT \ return to column 1 without CR
+ ABORT" FastForth V4.0 please!"
ABORT" build FastForth with Q15.16_INPUT addon !"
- RST_RET \ if no abort remove this word
- $1B EMIT $63 EMIT \ send 'ESC c' (clear screen)
+ RST_RET \ if no abort remove this word
+ $1B EMIT $63 EMIT \ send 'ESC c' (clear screen)
;
ABORT_FIXPOINT
-; -----------------------------------------------------
-; FIXPOINT.f
-; -----------------------------------------------------
-
+ [DEFINED] {FIXPOINT}
+ [IF] {FIXPOINT}
+ [THEN]
+ [UNDEFINED] {FIXPOINT}
+ [IF]
MARKER {FIXPOINT}
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] + [IF]
\ https://forth-standard.org/standard/core/Plus
\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
- [UNDEFINED] +
- [IF]
CODE +
ADD @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] R> [IF]
\ https://forth-standard.org/standard/core/Rfrom
\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
- [UNDEFINED] R>
- [IF]
CODE R>
SUB #2,PSP \ 1
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] = [IF]
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
- [UNDEFINED] =
- [IF]
CODE =
SUB @PSP+,TOS \ 2
0<> IF \ 2
ENDCODE
[THEN]
+ [UNDEFINED] U< [IF]
\ https://forth-standard.org/standard/core/Uless
\ U< u1 u2 -- flag test u1<u2, unsigned
- [UNDEFINED] U<
- [IF]
CODE U<
SUB @PSP+,TOS \ 2 u2-u1
0<> IF
ENDCODE
[THEN]
+ [UNDEFINED] DABS [IF]
\ https://forth-standard.org/standard/double/DABS
\ DABS d1 -- |d1| absolute value
- [UNDEFINED] DABS
- [IF]
CODE DABS
AND #-1,TOS \ clear V, set N
S< IF \
ENDCODE
[THEN]
+ [UNDEFINED] HOLDS [IF]
\ https://forth-standard.org/standard/core/HOLDS
\ Adds the string represented by addr u to the pictured numeric output string
\ compilation use: <# S" string" HOLDS #>
\ free chars area in the 32+2 bytes HOLD buffer = {26,23,2} chars with a 32 bits sized {hexa,decimal,binary} number.
\ (2 supplementary bytes are room for sign - and decimal point)
\ C HOLDS addr u --
- [UNDEFINED] HOLDS
- [IF]
CODE HOLDS
MOV @PSP+,X \ 2 X=src
BW3 ADD TOS,X \ 1 X=src_end
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ [UNDEFINED] F+ [IF]
CODE F+ \ add Q15.16|double numbers
ADD @PSP+,2(PSP) \ -- sumlo d1hi d2hi
ADDC @PSP+,TOS \ -- sumlo sumhi
MOV @IP+,PC
ENDCODE
+ [THEN]
+ [UNDEFINED] F- [IF]
CODE F- \ substract Q15.16|double numbers
SUB @PSP+,2(PSP) \ -- diflo d1hi d2hi
SUBC TOS,0(PSP) \ -- diflo difhi d2hi
MOV @PSP+,TOS
MOV @IP+,PC
ENDCODE
+ [THEN]
TLV_ORG 4 + @ $81F3 U<
$81EF TLV_ORG 4 + @ U<
= [IF] ; MSP430FR413x subfamily without hardware_MPY
+ [UNDEFINED] UDM* [IF]
\ unsigned multiply 32*32 = 64
\ don't use S reg (keep sign)
CODE UDM*
MOV @RSP+,IP \ 2
MOV @IP+,PC
ENDCODE
+ [THEN]
+ [UNDEFINED] F* [IF]
CODE F* \ s15.16 * s15.16 --> s15.16 result
MOV 2(PSP),S \
XOR TOS,S \ 1s15 XOR 2s15 --> S keep sign of result
THEN
MOV @IP+,PC
ENDCODE
+ [THEN]
+ [UNDEFINED] F#S [IF]
+ CODE F#S
\ F#S Qlo Qhi len -- Qhi 0 convert fractional part Qlo of Q15.16 fixed point number
\ with len digits
- CODE F#S
MOV @PSP,S \ -- Qlo Qhi len S = Qhi
MOV #0,T \ T = count
PUSHM #3,IP \ R-- IP Qhi count
MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG
GOTO BW3 \ 36~ JMP HOLDS
ENDCODE
+ [THEN]
[ELSE] ; hardware multiplier
+ [UNDEFINED] F* [IF]
CODE F* \ signed s15.16 multiplication --> s15.16 result
MOV 4(PSP),&MPYS32L \ 5 Load 1st operand
MOV 2(PSP),&MPYS32H \ 5
MOV &RES2,TOS \ 5
MOV @IP+,PC
ENDCODE
+ [THEN]
-
+ [UNDEFINED] F#S [IF]
\ F#S Qlo Qhi len -- Qhi 0 convert fractionnal part of Q15.16 fixed point number
\ with len digits
CODE F#S
MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG
GOTO BW3 \ 35~ JMP HOLDS+2
ENDCODE
+ [THEN]
[THEN] ; end of hardware/software multiplier
+ [UNDEFINED] F/ [IF]
CODE F/ \ Q15.16 / Q15.16 --> Q15.16 result
MOV TOS,Y \ 1 Y=DVRhi
MOV @PSP+,W \ 2 W=DVRlo
MOV S,0(PSP) \ 3 QUOTlo
MOV @IP+,PC \ 4
ENDCODE
+ [THEN]
+ [UNDEFINED] F. [IF]
CODE F. \ display a Q15.16 number with 4/5/16 digits after comma
MOV TOS,S \ S = sign
MOV #4,T \ T = 4 preset 4 digits for base 16 and by default
R> SIGN #> \ -- addr len R-- IP
TYPE $20 EMIT \ --
;
+ [THEN]
+ [UNDEFINED] S>F [IF]
CODE S>F \ convert a signed number to a Q15.16 (signed) number
SUB #2,PSP
MOV #0,0(PSP)
MOV @IP+,PC
ENDCODE
+ [THEN]
RST_SET
+ [THEN] \ endof [UNDEFINED] {FIXPOINT}
+
; -----------------------
; complement (volatile) for tests below
; -----------------------
-\ https://forth-standard.org/standard/core/Store
-\ ! x a-addr -- store cell in memory
- [UNDEFINED] !
- [IF]
- CODE !
- MOV @PSP+,0(TOS) \ 4
- MOV @PSP+,TOS \ 2
- MOV @IP+,PC \ 4
- ENDCODE
- [THEN]
-
-\ https://forth-standard.org/standard/core/DOES
-\ DOES> -- set action for the latest CREATEd definition
- [UNDEFINED] DOES>
- [IF]
- CODE DOES>
- MOV &LAST_CFA,W \ W = CFA of CREATEd word
- MOV #DODOES,0(W) \ replace CFA (DOCON) by new CFA (DODOES)
- MOV IP,2(W) \ replace PFA by the address after DOES> as execution address
- MOV @RSP+,IP
- MOV @IP+,PC
- ENDCODE
- [THEN]
-
\ https://forth-standard.org/standard/core/CONSTANT
\ CONSTANT <name> n -- define a Forth CONSTANT
- [UNDEFINED] CONSTANT
- [IF]
+ [UNDEFINED] CONSTANT [IF]
: CONSTANT
CREATE
HI2LO
[THEN]
\ https://forth-standard.org/standard/double/TwoCONSTANT
- [UNDEFINED] 2CONSTANT
- [IF]
+ [UNDEFINED] 2CONSTANT [IF]
: 2CONSTANT \ udlo/dlo/Qlo udhi/dhi/Qhi -- to create double or Q15.16 CONSTANT
CREATE , , \ compile Qhi then Qlo
DOES> \ execution part addr -- Qhi Qlo
\ https://forth-standard.org/standard/double/Dd
\ D. dlo dhi -- display d (signed)
- [UNDEFINED] D.
- [IF]
+ [UNDEFINED] D. [IF]
CODE D.
- MOV #U.,W \ U. + 10 = D.
- ADD #10,W
- MOV W,PC
+ MOV #U.+10,PC \ U. + 10 = D.
ENDCODE
[THEN]
\ https://forth-standard.org/standard/core/BASE
\ BASE -- a-addr holds conversion radix
- [UNDEFINED] BASE
- [IF]
+ [UNDEFINED] BASE [IF]
BASEADR CONSTANT BASE
[THEN]
ECHO
-; -----------------------
-; (volatile) tests for FIXPOINT.asm|FIXPOINT.f
-; -----------------------
+; ------------------------------------------------
+; (volatile) tests for FIXPOINT.asm | FIXPOINT.4th
+; ------------------------------------------------
3,14159 2CONSTANT PI
PI -1,0 F* 2CONSTANT -PI
--- /dev/null
+
+; ---------------------------------
+; FF_SPECS.4th for MSP_EXP430FR5994
+; ---------------------------------
+
+ CODE ABORT_FF_SPECS
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV &$180A,R14
+ SUB #400,R14
+ COLON
+ $0D EMIT
+ ABORT" FastForth V4.0 please!"
+ RST_RET
+ ;
+
+ ABORT_FF_SPECS
+
+; ------------------------------------------------------------------
+; first we download the set of definitions we need, from CORE_ANS
+; ------------------------------------------------------------------
+
+ [UNDEFINED] DUP [IF]
+ CODE DUP
+BW1 SUB #2,R15
+ MOV R14,0(R15)
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE ?DUP
+ CMP #0,R14
+ 0<> ?GOTO BW1
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] OVER [IF]
+ CODE OVER
+ MOV R14,-2(R15)
+ MOV @R15,R14
+ SUB #2,R15
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DROP [IF]
+ CODE DROP
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] SWAP [IF]
+ CODE SWAP
+ MOV @R15,R10
+ MOV R14,0(R15)
+ MOV R10,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] ROT [IF]
+ CODE ROT
+ MOV @R15,R10
+ MOV R14,0(R15)
+ MOV 2(R15),R14
+ MOV R10,2(R15)
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] >R [IF]
+ CODE >R
+ PUSH R14
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] R> [IF]
+ CODE R>
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV @R1+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 0< [IF]
+ CODE 0<
+ ADD R14,R14
+ SUBC R14,R14
+ XOR #-1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] = [IF]
+ CODE =
+ SUB @R15+,R14
+ 0<> IF
+ AND #0,R14
+ MOV @R13+,R0
+ THEN
+ XOR #-1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] U< [IF]
+ CODE U<
+ SUB @R15+,R14
+ U< ?GOTO FW1
+ 0<> IF
+BW1 MOV #-1,R14
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE U>
+ SUB @R15+,R14
+ U< ?GOTO BW1
+FW1 AND #0,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] IF [IF]
+ CODE IF
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
+ ADD #2,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ CODE THEN
+ MOV &$1DC0,0(R14)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] ELSE [IF]
+ CODE ELSE
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
+ MOV R10,0(R14)
+ SUB #2,R10
+ MOV R10,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] BEGIN [IF]
+
+ CODE BEGIN
+ MOV #BEGIN,R0
+ ENDCODE IMMEDIATE
+
+ CODE UNTIL
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV R9,-4(R10)
+ MOV R14,-2(R10)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ CODE AGAIN
+ MOV #$409C,R9
+ GOTO BW1
+ ENDCODE IMMEDIATE
+
+ : WHILE
+ POSTPONE IF SWAP
+ ; IMMEDIATE
+
+ : REPEAT
+ POSTPONE AGAIN POSTPONE THEN
+ ; IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] DO [IF]
+
+ HDNCODE XDO
+ MOV #$8000,R9
+ SUB @R15+,R9
+ MOV R14,R8
+ ADD R9,R8
+ PUSHM #2,R9
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE DO
+ SUB #2,R15
+ MOV R14,0(R15)
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
+ MOV #XDO,-2(R14)
+ ADD #2,&$1C00
+ MOV &$1C00,R10
+ MOV #0,0(R10)
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ HDNCODE XLOOP
+ ADD #1,0(R1)
+BW1 BIT #$100,R2
+ 0= IF
+ MOV @R13,R13
+ MOV @R13+,R0
+ THEN
+ ADD #4,R1
+ ADD #2,R13
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE LOOP
+ MOV #XLOOP,R9
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV R9,-4(R10)
+ MOV R14,-2(R10)
+ BEGIN
+ MOV &$1C00,R14
+ SUB #2,&$1C00
+ MOV @R14,R14
+ CMP #0,R14
+ 0<> WHILE
+ MOV R10,0(R14)
+ REPEAT
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ HDNCODE XPLOO
+ ADD R14,0(R1)
+ MOV @R15+,R14
+ GOTO BW1
+ ENDCODE
+
+ CODE +LOOP
+ MOV #XPLOO,R9
+ GOTO BW2
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] I [IF]
+ CODE I
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV @R1,R14
+ SUB 2(R1),R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] HERE [IF]
+ CODE HERE
+ MOV #BEGIN,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C@ [IF]
+ CODE C@
+ MOV.B @R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] SPACES [IF]
+ CODE SPACES
+ CMP #0,R14
+ 0<> IF
+ PUSH R13
+ BEGIN
+ LO2HI
+ $20 EMIT
+ HI2LO
+ SUB #1,R14
+ 0= UNTIL
+ MOV @R1+,R13
+ THEN
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 1+ [IF]
+ CODE 1+
+ ADD #1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] + [IF]
+ CODE +
+ ADD @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] - [IF]
+ CODE -
+ SUB @R15+,R14
+ XOR #-1,R14
+ ADD #1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2* [IF]
+ CODE 2*
+ ADD R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2/ [IF]
+ CODE 2/
+ RRA R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] UM/MOD [IF]
+ CODE UM/MOD
+ PUSH #DROP
+ MOV #$4028,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] MOVE [IF]
+ CODE MOVE
+ MOV R14,R10
+ MOV @R15+,R8
+ MOV @R15+,R9
+ MOV @R15+,R14
+ CMP #0,R10
+ 0<> IF
+ CMP R9,R8
+ 0<> IF
+ U< IF
+ BEGIN
+ MOV.B @R9+,0(R8)
+ ADD #1,R8
+ SUB #1,R10
+ 0= UNTIL
+ MOV @R13+,R0
+ THEN
+ ADD R10,R8
+ ADD R10,R9
+ BEGIN
+ SUB #1,R9
+ SUB #1,R8
+ MOV.B @R9,0(R8)
+ SUB #1,R10
+ 0= UNTIL
+ THEN
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CR [IF]
+
+ CODE CR
+ MOV #$409E,R0
+ ENDCODE
+
+ :NONAME
+ $0D EMIT $0A EMIT
+ ; IS CR
+
+ [THEN]
+
+ [UNDEFINED] CASE [IF]
+
+ : CASE
+ 0
+ ; IMMEDIATE
+
+ : OF
+ 1+
+ >R
+ POSTPONE OVER
+ POSTPONE =
+ POSTPONE IF
+ POSTPONE DROP
+ R>
+ ; IMMEDIATE
+
+ : ENDOF
+ >R
+ POSTPONE ELSE
+ R>
+ ; IMMEDIATE
+
+ : ENDCASE
+ POSTPONE DROP
+ 0 DO
+ POSTPONE THEN
+ LOOP
+ ; IMMEDIATE
+ [THEN]
+
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ [UNDEFINED] S? [IF]
+ CODE S?
+ MOV #S"+10,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] ESC [IF]
+ CODE ESC
+ CMP #0,&$1DB4
+ 0= IF MOV @R13+,R0
+ THEN
+ COLON
+ $1B
+ POSTPONE LITERAL
+ POSTPONE EMIT
+ $20
+ POSTPONE S?
+ POSTPONE TYPE
+ ; IMMEDIATE
+ [THEN]
+
+ [DEFINED] FORTH [IF]
+ CODE BODY>SQNFA
+ SUB #2,R15
+ SUB #4,R14
+ MOV R14,R8
+ MOV R8,R9
+ BEGIN
+ SUB #2,R9
+ MOV R9,0(R15)
+ MOV.B @R9+,R14
+ RRA R14
+ MOV R14,R10
+ BIT #1,R10
+ 0= IF
+ ADD #1,R10
+ THEN
+ ADD R9,R10
+ CMP R10,R8
+ 0<> WHILE
+ MOV @R15,R9
+ REPEAT
+ MOV R9,0(R15)
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ : SPECS
+ RST_RET
+ ECHO
+ ESC [8;42;80t
+ ESC [7m
+ CR ." FastForth V"
+ $180A @
+ 0 <# # $08 HOLD # '.' HOLD #S #> TYPE
+ ." for MSP430FR"
+ HERE
+ $1A04 @
+ CASE
+ $8102 OF ." 5738," $C200 ENDOF
+ $8103 OF ." 5739," $C200 ENDOF
+ $810D OF ." 5986," $4400 ENDOF
+ $8160 OF ." 5948," $4400 ENDOF
+ $8169 OF ." 5969," $4400 ENDOF
+ $81A8 OF ." 6989," $4400 ENDOF
+ $81F0 OF ." 4133," $C400 ENDOF
+ $8240 OF ." 2433," $C400 ENDOF
+ $825D OF ." 5972," $4400 ENDOF
+ $82A1 OF ." 5994," $4000 ENDOF
+ $830C OF ." 2355," $8000 ENDOF
+ $830D OF ." 2353," $C000 ENDOF
+ $831E OF ." 2155," $8000 ENDOF
+ $831D OF ." 2153," $C000 ENDOF
+ $832A OF ." 2476," $8000 ENDOF
+ $832B OF ." 2475," $8000 ENDOF
+ $833C OF ." 2633," $C400 ENDOF
+ $833D OF ." 2533," $C400 ENDOF
+ ABORT" xxxx <-- unrecognized device!"
+ ENDCASE
+ ." DTC"
+ ['] ['] DUP @ $1284 =
+ IF ." =1," DROP
+ ELSE 2 + @ $1284 =
+ IF ." =2,"
+ ELSE ." =3,"
+ THEN
+ THEN
+ $20 EMIT
+ $180C @ U. $08 EMIT
+ ." -Entry word set, "
+ $1800 @ 0 1000 UM/MOD U.
+ ?DUP IF $08 EMIT ',' EMIT U.
+ THEN ." MHz, "
+ - U. ." bytes"
+ ESC [0m
+ CR
+ ." /COUNTED-STRING = 255" CR
+ ." /HOLD = 34" CR
+ ." /PAD = 84" CR
+ ." ADDRESS-UNIT-BITS = 16" CR
+ [DEFINED] {CORE_ANS}
+ [IF]
+ ." FLOORED DIVISION = "
+ $180E @
+ 0< IF ." true"
+ ELSE ." false"
+ THEN CR
+ [THEN]
+ ." MAX-CHAR = 255" CR
+ ." MAX-N = 32767" CR
+ ." MAX-U = 65535" CR
+ ." MAX-D = 2147483647" CR
+ ." MAX-UD = 4294967295" CR
+ ." STACK-CELLS = 48" CR
+ ." RETURN-STACK-CELLS= 48" CR
+ ." Definitions are always UPPERCASE." CR
+ CR ESC [7m ." Kernel add-ons" ESC [0m CR
+ $180E @
+ 2* DUP 0< IF ." 32.768kHz LF XTAL" CR THEN
+ 2* DUP 0< IF ." /RTS /CTS " 2*
+ ELSE 2* DUP
+ 0< IF ." /RTS " THEN
+ THEN
+ 2* DUP 0< IF ." XON/XOFF " THEN
+ 2* DUP 0< IF ." Half-Duplex " THEN
+ 2* DUP 0< IF ." I2C_Master TERMINAL"
+ ELSE ." UART TERMINAL" THEN CR
+ 2* DUP 0< IF 2* DUP 0< IF ." DOUBLE and "
+ THEN ." Q15.16 numbers handling" CR
+ ELSE 2* DUP 0< IF ." DOUBLE numbers handling" CR
+ THEN
+ THEN
+ 2* DUP 0< IF ." MSP430_X assembler with TI's syntax"
+ CR 2* 2*
+ ELSE
+ 2* DUP
+ 0< IF ." MSP430 Assembler"
+ 2* DUP
+ 0< IF ." , 20bits extended addresses,"
+ THEN
+ ELSE 2*
+ THEN
+ ." with TI's syntax" CR
+ THEN DROP
+ [DEFINED] FORTH [IF] ." word-set management" CR
+ [THEN]
+ [DEFINED] LOAD" [IF] ." SD_CARD Load" CR
+ [THEN]
+ [DEFINED] BOOT [IF] ." SD_CARD Bootloader" CR
+ [THEN]
+ [DEFINED] READ" [IF] ." SD_CARD Read/Write" CR
+ [THEN]
+ $1DC2
+ BEGIN
+ @ ?DUP
+ WHILE
+ CR ESC [7m
+ DUP $180C @ 2* -
+ [DEFINED] FORTH
+ [IF] DUP BODY>SQNFA
+ [ELSE] OVER @
+ IF S" hidden"
+ ELSE S" FORTH"
+ THEN
+ [THEN]
+ TYPE ." word-set"
+ ESC [0m CR
+ $1CE4
+ $180C @ 2*
+ MOVE
+ BEGIN
+ 0 DUP
+ $180C @ 2* 0
+ DO
+ DUP I $1CE4 + @
+ U< IF
+ DROP DROP
+ I DUP $1CE4 + @
+ THEN
+ 2 +LOOP
+ ?DUP
+ WHILE
+ DUP
+ 2 - @
+ ROT
+ $1CE4 +
+ !
+ COUNT 2/
+ DUP >R TYPE
+ $10 R> - SPACES
+ REPEAT
+ DROP
+ CR
+ REPEAT
+ DROP
+ CR ESC [7m ." EXTENSIONS" ESC [0m
+ [DEFINED] {CORE_ANS} [IF] CR ." CORE ANS94"
+ [THEN]
+ [DEFINED] {DOUBLE} [IF] CR ." DOUBLE numbers set"
+ [THEN]
+ [DEFINED] {UTILITY} [IF] CR ." UTILITY"
+ [THEN]
+ [DEFINED] {FIXPOINT} [IF] CR ." Q15.16 ADD SUB MUL DIV"
+ [THEN]
+ [DEFINED] {CORDIC} [IF] CR ." CORDIC engine"
+ [THEN]
+ [DEFINED] {SD_TOOLS} [IF] CR ." SD_TOOLS"
+ [THEN]
+ [DEFINED] {RTC} [IF] CR ." RTC utility"
+ [THEN]
+ [DEFINED] {UARTI2CS} [IF] CR ." UART to I2C_FastForth bridge"
+ [THEN]
+ CR
+ SYS
+ ;
+
+SPECS
SUB #2,PSP
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET \ remove ABORT_UARTI2CS definition before resuming
;
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
-\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
-\ {RC5TOLCD}+4 make room to save previous IR_VEC
-\ {RC5TOLCD}+6 make room for 20 us count loop.
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
+ \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
+ \ {RC5TOLCD}+4 make room to save previous IR_VEC
+ \ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
+
+\ https://forth-standard.org/standard/core/Equal
+\ = x1 x2 -- flag test x1=x2
+ [UNDEFINED] =
[IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
+ CODE =
+ SUB @PSP+,TOS \ 2
+ 0<> IF \ 2
+ AND #0,TOS \ 1
+ MOV @IP+,PC \ 4
+ THEN
+ XOR #-1,TOS \ 1 flag Z = 1
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] IF
+ [IF] \ define IF and THEN
+\ https://forth-standard.org/standard/core/IF
+\ IF -- IFadr initialize conditional forward branch
+ CODE IF \ immediate
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \
+ MOV &DP,TOS \ -- HERE
+ ADD #4,&DP \ compile one word, reserve one word
+ MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN
+ ADD #2,TOS \ -- HERE+2=IFadr
MOV @IP+,PC
+ ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/THEN
+\ THEN IFadr -- resolve forward branch
+ CODE THEN \ immediate
+ MOV &DP,0(TOS) \ -- IFadr
+ MOV @PSP+,TOS \ --
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+\ https://forth-standard.org/standard/core/ELSE
+\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
+ [UNDEFINED] ELSE
+ [IF]
+ CODE ELSE \ immediate
+ ADD #4,&DP \ make room to compile two words
+ MOV &DP,W \ W=HERE+4
+ MOV #BRAN,-4(W)
+ MOV W,0(TOS) \ HERE+4 ==> [IFadr]
+ SUB #2,W \ HERE+2
+ MOV W,TOS \ -- ELSEadr
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+\ \ https://forth-standard.org/standard/core/DEFERStore
+\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER.
+\ [UNDEFINED] IS
+\ [IF] \ define DEFER! and IS
+\ CODE DEFER! \ xt2 xt1 --
+\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2]
+\ MOV @PSP+,TOS \ --
+\ MOV @IP+,PC
+\ ENDCODE
+\
+\ \ https://forth-standard.org/standard/core/IS
+\ \ IS <name> xt --
+\ \ used as is :
+\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS)
+\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY
+\ \ or in a definition : ... ['] U. IS DISPLAY ...
+\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words
+\ \
+\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words...
+\
+\ : IS
+\ STATEADR @
+\ IF POSTPONE ['] POSTPONE DEFER!
+\ ELSE ' DEFER!
+\ THEN
+\ ; IMMEDIATE
+\ [THEN]
+
+\ https://forth-standard.org/standard/core/CR
+\ CR -- send CR+LF to the output device
+ [UNDEFINED] CR
+ [IF]
+\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition
+ CODE CR \ part I : DEFERed definition of CR
+ MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR
+ ENDCODE
+
+ :NONAME
+ 'CR' EMIT 'LF' EMIT
+ ; IS CR
+ [THEN]
+
+\ https://forth-standard.org/standard/core/toBODY
+\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word
+ [UNDEFINED] >BODY
+ [IF]
+ CODE >BODY
+ ADD #4,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ CODE 20_US \ n --
+ BEGIN \ J_loop 8000 16000 24000 kHz
+ MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
+ SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles
+ BEGIN \ I_loop
+ NOP \ 1
+ SUB #1,X \ +1
+ 0= UNTIL \ +2
+ NOP \ +1
+ SUB #1,TOS \ +1
+ 0= UNTIL \ +2
+ MOV @PSP+,TOS \
+ MOV @RSP+,IP \
+ ENDCODE
+
+\ \ if write : %xxxx_WWWW --
+\ \ if read : -- %0000_RRRR
+ CODE TOP_LCD \ LCD Sample
+ BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1
+ BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test
+ 0= IF \ write LCD bits pattern
+ AND.B #LCD_DB,TOS \
+ MOV.B TOS,&LCD_DB_OUT \ send LCD_Data
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV @PSP+,TOS \
+ MOV @IP+,PC
+ THEN \ read LCD bits pattern
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data
+ MOV.B &LCD_DB_IN,TOS \ get LCD_Data
+ AND.B #LCD_DB,TOS \
+ MOV @IP+,PC
+ ENDCODE
+
+ CODE LCD_WRC \ char -- Write Char
+ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+BW1 SUB #2,PSP \
+ MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL
+ RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH
+ BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0
+ BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output
+ COLON \ high level word starts here
+ TOP_LCD 2 20_US \ write high nibble first
+ TOP_LCD 2 20_US
+ ;
+
+ CODE LCD_WRF \ func -- Write Fonction
+ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+ GOTO BW1
+ ENDCODE
+
+ : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init !
+ : LCD_HOME $02 LCD_WRF 100 20_us ;
+
+\ CODE LCD_ENTRY_SET
+\ BIS #$04,TOS
+\ BW1 COLON
+\ LCD_WrF
+\ ;
+\
+\ CODE LCD_DSP_CTRL
+\ BIS#$08,TOS
+\ GOTO BW1
+\ ENDCODE
+\
+\ CODE LCD_DSP_SHIFT
+\ BIS#$10,TOS
+\ GOTO BW1
+\ ENDCODE
+\
+\ CODE LCD_FN_SET
+\ BIS#$20,TOS
+\ GOTO BW1
+\ ENDCODE
+\
+\ CODE LCD_CGRAM_SET
+\ BIS #$40,TOS
+\ GOTO BW1
+\ ENDCODE
+\
+\ CODE LCD_GOTO
+\ BIS #$80,TOS
+\ GOTO BW1
+\ ENDCODE
+\
+\ CODE LCD_RDS \ -- status Read Status
+\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0
+\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput
+\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1
+\ COLON \ starts a FORTH word
+\ TOP_LCD 2 20_us \ -- %0000_HHHH
+\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL
+\ HI2LO \ switch from FORTH to assembler
+\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL
+\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL
+\ MOV @RSP+,IP \ restore IP saved by COLON
+\ MOV @IP+,PC \
+\ ENDCODE
+\
+\ CODE LCD_RDC \ -- char Read Char
+\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1
+\ GOTO BW1
+\ ENDCODE
+\
+\
+\ ********************************\
+ HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable !
+\ ********************************\
+\ XOR.B #LED1,&LED1_OUT \ to visualise WDT
+ BIT.B #SW2,&SW2_IN \ test switch S2
+ 0= IF \ case of switch S2 pressed
+ CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4
+ U< IF
+ ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment
+ THEN
+ ELSE
+ BIT.B #SW1,&SW1_IN \ test switch S1 input
+ 0= IF \ case of Switch S1 pressed
+ CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V
+ U>= IF \
+ SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement
+ THEN \
+ THEN \
+ THEN \
+ RETI \ 5
+ ENDCODE \
+\ ********************************\
+
+\ ********************************\
+ HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt
+\ ********************************\
+\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use
+\ ********************************\
+\ \ in : SR(9)=old Toggle bit memory (ADD on)
+\ \ SMclock = 8|16|24 MHz
+\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register
+\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0
+\ \ SR(9)=new Toggle bit memory (ADD on)
+\ ********************************\
+\ RC5_FirstStartBitHalfCycle: \
+\ ********************************\
+ MOV #1778,X \ RC5_Period in us
+ MOV #14,W \ count of loop
+ BEGIN \
+\ ****************************\
+\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period
+\ ****************************\ |
+ MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R
+\ RC5_Compute_3/4_Period: \ |
+ RRUM #1,X \ X=1/2 cycle |
+ MOV X,Y \ ^
+ RRUM #1,Y \ Y=1/4
+ ADD X,Y \ Y=3/4 cycle
+ BEGIN \
+ CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles
+ U>= UNTIL \ 2
+\ ****************************\
+\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first
+\ ****************************\
+ BIT.B #RC5,&IR_IN \ C_flag = IR bit
+ ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag
+ MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG
+ BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change
+ SUB #1,W \ decrement count loop
+\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6
+\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
+ 0<> WHILE \ ----> out of loop ----+
+ ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present
+ BEGIN \ |
+ MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles
+ CMP Y,X \ 1 ^ | cycle time out of bound ?
+ U>= ?GOTO FW1 \ | | quit on truncated RC5 message
+ BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present
+ 0<> UNTIL \ 2 | |
+ REPEAT \ ----> loop back --+ | with X = new RC5_period value
+\ ********************************\ |
+\ RC5_SampleEndOf: \ <---------------------+
+\ ********************************\
+ BIC #$30,&RC5_TIM_CTL \ stop timer
+\ ********************************\
+\ RC5_ComputeNewRC5word \
+\ ********************************\
+ RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0
+ MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0
+ RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0
+\ ********************************\
+\ RC5_ComputeC6bit \
+\ ********************************\
+ BIT #BIT14,T \ test /C6 bit in T
+ 0= IF BIS #BIT6,X \ set C6 bit in X
+ THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0
+\ ********************************\
+\ RC5_CommandByteIsDone \
+\ ********************************\
+\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit
+\ ********************************\
+ RRUM #3,T \ new toggle bit = T(13) ==> T(10)
+ XOR @RSP,T \ (new XOR old) Toggle bits
+ BIT #UF10,T \ repeated RC5_command ?
+ 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action !
+ XOR #UF10,0(RSP) \ 5 toggle bit memory
+\ ********************************\
+\ Display IR_RC5 code \
+\ ********************************\
+ SUB #6,PSP \ -- x x x TOS
+ MOV TOS,4(PSP) \ -- TOS x x TOS
+ MOV &BASEADR,2(PSP) \ -- TOS Base x TOS
+ MOV #$10,&BASEADR \ set hexadecimal base
+ MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte
+ MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii
+ LO2HI \ switch from assembler to FORTH
+ LCD_CLEAR \ set LCD cursor at home
+ <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx"
+ ['] LCD_WRC IS EMIT \ redirect EMIT to LCD
+ TYPE \ -- TOS Base display "$xx" on LCD
+ ['] EMIT >BODY IS EMIT \ restore EMIT
+ HI2LO \ switch from FORTH to assembler
+ MOV @PSP+,&BASEADR \ -- TOS restore current BASE
+ MOV @PSP+,TOS \ --
+FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message)
+FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR
+ RETI \
+ ENDCODE \
+\ ********************************\
+
+\ define our STOP_APP
+\ ----------------------------------\
+ HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD}
+\ ----------------------------------\
+ CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START
+ 0= IF \ only if START is done
+ BIC.B #RC5,&IR_IE \ clear I/O RC5_Int
+ BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag
+ MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG
+ MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER
+ MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
+ MOV #{RC5TOLCD},W \
+ MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
+ MOV @W+,&HARD_APP \ restore previous ini_APP
+ MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
+ MOV @W+,&IR_VEC \ restore Vector previous value
+ THEN
+ MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD}
ENDCODE
+\ ----------------------------------\
+
+\ ----------------------------------\
+ CODE STOP \ also called by INIT_R2L for some events
+\ ----------------------------------\
+BW1 CALL #STOP_R2L
+ COLON \
+ ECHO \
+ ." type START to start RC5toLCD"
+ ;
+\ ----------------------------------\
+
+\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app.
+\ ----------------------------------\
+ HDNCODE INIT_R2L \ called by START|SYS
+\ ----------------------------------\
+\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0
+\ - - \CNTL Counter lentgh \ 00 = 16 bits
+\ -- \TBSSEL TimerB clock select \ 10 = SMCLK
+\ -- \ID input divider \ 10 = /4
+\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0
+\ - \TBCLR TimerB Clear
+\ - \TBIE
+\ -\TBIFG
+\ ----------------------------------\
+\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E}
+\ -- \CM Capture Mode
+\ -- \CCIS
+\ - \SCS
+\ -- \CLLD
+\ - \CAP
+\ --- \OUTMOD \ 011 = set/reset
+\ - \CCIE
+\ - \CCI
+\ - \OUT
+\ - \COV
+\ -\CCIFG
+\ ----------------------------------\
+\ LCD_TIM_CCRx \
+\ ----------------------------------\
+\ LCD_TIM_EX0 \
+\ ----------------------------------\
+\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt
+\ ----------------------------------\
+ MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG
+\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value
+\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ)
+ FREQ_KHZ @ 16000 =
+ [IF] \ if 16 MHz
+ MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register
+ MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ)
[THEN]
+ FREQ_KHZ @ 24000 =
+ [IF] \ if 24 MHz
+ MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register
+ MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ)
+ [THEN]
+ MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us
+\ ----------------------------------\
+\ set LCD_TIM_.2 to generate PWM for LCD_Vo
+\ ----------------------------------\
+ MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG
+ MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6)
+\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3)
+\ ----------------------------------\
+ BIS.B #LCDVo,&LCDVo_DIR \
+ BIS.B #LCDVo,&LCDVo_SEL \ SEL.2
+\ ----------------------------------\
+ BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs
+ BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable
+\ ----------------------------------\
+ BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data
+ BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable
+\ ----------------------------------\
+\ init RC5_Int \
+\ ----------------------------------\
+ BIS.B #RC5,&IR_IE \ enable RC5_Int
+ BIC.B #RC5,&IR_IFG \ reset RC5_Int flag
+\ ----------------------------------\
+\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_
+\ ----------------------------------\
+\ %01 0001 0100 \ TAxCTL
+\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz
+\ -- \ ID divided by 1
+\ -- \ MC MODE = up to TAxCCRn
+\ - \ TACLR clear timer count
+\ - \ TAIE
+\ - \ TAIFG
+\ ----------------------------------\
+ MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int,
+\ ----------------------------------\
+\ 000 \ TAxEX0
+\ --- \ TAIDEX pre divisor
+\ ----------------------------------\
+\ %0000 0000 0000 0101 \ TAxCCR0
+ MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms
+\ ----------------------------------\
+\ %0000 0000 0001 0000 \ TAxCCTL0
+\ - \ CAP capture/compare mode = compare
+\ - \ CCIEn
+\ - \ CCIFGn
+ MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0
+\ ----------------------------------\
+\ activate I/O \
+\ ----------------------------------\
+ CALL &{RC5TOLCD} \ run previous INIT_HARD_APP
+\ ----------------------------------\
+\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing
+\ ----------------------------------\
+ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ?
+ 0<> IF \ if not
+ CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ?
+ U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM
+ THEN \
+\ CMP #2,TOS \ Power_ON event
+\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case...
+ CMP #4,TOS \ SYSRSTIV|USERSYS RST ?
+ 0= ?GOTO BW1 \ if yes run STOP.
+\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ?
+\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP
+\ ----------------------------------\
+ LO2HI \
+\ ----------------------------------\
+\ Init LCD 2x20 \
+\ ----------------------------------\
+ #1000 20_US \ 1- wait 20 ms
+ %011 TOP_LCD \ 2- send DB5=DB4=1
+ #205 20_US \ 3- wait 4,1 ms
+ %011 TOP_LCD \ 4- send again DB5=DB4=1
+ #5 20_US \ 5- wait 0,1 ms
+ %011 TOP_LCD \ 6- send again again DB5=DB4=1
+ #2 20_US \ wait 40 us = LCD cycle
+ %010 TOP_LCD \ 7- send DB5=1 DB4=0
+ #2 20_US \ wait 40 us = LCD cycle
+ %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal
+ %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off.
+ LCD_CLEAR \ 10- "LCD_Clear"
+ %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM
+ %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off.
+ LCD_CLEAR \ 10- "LCD_Clear"
+ HI2LO \
+ MOV @RSP+,PC \ RET to WARM|START
+ ENDCODE
+\ ----------------------------------\
+
+\ ----------------------------------\
+ CODE START \ this routine replaces INT_HARD_APP default values by these of this application.
+\ ----------------------------------\
+ CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START
+ 0= IF \
+ MOV @IP+,PC \ does nothing if already initialised
+ THEN
+ MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
+ MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
+ MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
+ MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
+ MOV #RC5_INT,&IR_VEC \ init interrupt vector
+\ ----------------------------------\
+\ init 20 us count loop \ see 20_US
+\ ----------------------------------\ -- TOS
+ SUB #6,PSP \ -- x x x TOS
+ MOV TOS,4(PSP) \ -- TOS x x TOS
+ MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS
+ MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS
+ MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo
+ CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi
+ MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US
+ ADD #4,PSP \ -- TOS QUOThi
+ MOV @PSP+,TOS \ -- TOS
+\ ----------------------------------\
+ CALL #INIT_R2L \ run new INIT_HARD_APP
+ LO2HI
+\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME
+\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC
+\ CR ." I love you" \ display message on LCD
+\ ['] CR >BODY IS CR \ CR executes its default value
+\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value
+ ." RC5toLCD is running," \
+ ." Type STOP to quit." \ display message on FastForth Terminal
+ HI2LO
+ MOV #ABORT,PC \ goto FORTH interpreter without WARM message.
+ ENDCODE \
+\ ----------------------------------\
+
+RST_SET
+
+ MARKER {RC5TOLCD} \ restore the state before MARKER definition
+\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
+ \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
+ \ {RC5TOLCD}+4 make room to save previous IR_VEC
+ \ {RC5TOLCD}+6 make room for 20 us count loop.
+
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_SET
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
\ {RC5TOLCD}+4 make room to save previous IR_VEC
\ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_SET
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
\ {RC5TOLCD}+4 make room to save previous IR_VEC
\ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_SET
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
\ {RC5TOLCD}+4 make room to save previous IR_VEC
\ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_SET
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
\ {RC5TOLCD}+4 make room to save previous IR_VEC
\ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_SET
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
\ {RC5TOLCD}+4 make room to save previous IR_VEC
\ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_SET
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
\ {RC5TOLCD}+4 make room to save previous IR_VEC
\ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_SET
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
\ {RC5TOLCD}+4 make room to save previous IR_VEC
\ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_RET
+
\ START
\ rc5 <--- OUT IR_Receiver (1 TSOP32236)
-\ first, we test for downloading driver only if UART TERMINAL target
+\ first, we do some tests allowing the download
CODE ABORT_RC5TOLCD
SUB #2,PSP
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
- 'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
- RST_RET \ remove ABORT_UARTI2CS definition before resuming
+ 'CR' EMIT \ return to column 1 without 'LF'
+ ABORT" FastForth V4.0 please!"
+ RST_RET \ remove ABORT_UARTI2CS definition before resuming
;
ABORT_RC5TOLCD
MARKER {RC5TOLCD} \ restore the state before MARKER definition
\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR
- 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address
+ 8 ALLOT \ {UARTI2CS} make room to save previous HARD_APP address
\ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC
\ {RC5TOLCD}+4 make room to save previous IR_VEC
\ {RC5TOLCD}+6 make room for 20 us count loop.
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT \ addr bit_mask -- true/flase flag
- MOV @PSP+,X
- AND @X,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US \ n --
BEGIN \ J_loop 8000 16000 24000 kHz
MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120}
MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0
MOV #{RC5TOLCD},W \
MOV #RET_ADR,-2(W) \ clear MARKER_DOES call
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV @W+,&UART_WARM+2 \ restore previous ini_APP
- [ELSE]
- MOV @W+,&I2C_WARM+2 \ restore previous ini_APP
- [THEN]
+ MOV @W+,&HARD_APP \ restore previous ini_APP
MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value
MOV @W+,&IR_VEC \ restore Vector previous value
THEN
MOV @IP+,PC \ does nothing if already initialised
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L.
- KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test)
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP
- [ELSE]
- MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine
- MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP
- [THEN]
+ MOV &HARD_APP,&{RC5TOLCD} \ save previous HARD_APP subroutine
+ MOV #INIT_R2L,&HARD_APP \ replace it by RC5toLCD INIT_R2L
MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value
MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0
MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value
ENDCODE \
\ ----------------------------------\
-RST_SET
+RST_SET
+
ECHO
\ START
\
\
+; --------------------
+; RTC.f
+; --------------------
+\ use :
+\ to set date, type : d m y DATE!
+\ to view date, type DATE?
+\ to set time, type : h m [s] TIME!
+\ to view time, type TIME?
+\
+
+\ first, we do some tests allowing the download
CODE ABORT_RTC
SUB #4,PSP
MOV TOS,2(PSP)
0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT input), set TOS = 0
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
$0D EMIT \ return to column 1 without CR
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" target without LF_XTAL !"
RST_RET \ if no abort remove this word
;
ABORT_RTC
-; --------------------
-; RTC.f
-; --------------------
-
-\ use :
-\ to set date, type : d m y DATE!
-\ to view date, type DATE?
-\ to set time, type : h m [s] TIME!
-\ to view time, type TIME?
-\
-
MARKER {RTC}
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] OR [IF]
\ https://forth-standard.org/standard/core/OR
\ C OR x1 x2 -- x3 logical OR
- [UNDEFINED] OR
- [IF]
CODE OR
BIS @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] C@ [IF]
\ https://forth-standard.org/standard/core/CFetch
\ C@ c-addr -- char fetch char from memory
- [UNDEFINED] C@
- [IF]
CODE C@
MOV.B @TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] C! [IF]
\ https://forth-standard.org/standard/core/CStore
\ C! char c-addr -- store char in memory
- [UNDEFINED] C!
- [IF]
CODE C!
MOV.B @PSP+,0(TOS) \ 4
ADD #1,PSP \ 1
ENDCODE
[THEN]
+ [UNDEFINED] SWAP [IF]
\ https://forth-standard.org/standard/core/SWAP
\ SWAP x1 x2 -- x2 x1 swap top two items
- [UNDEFINED] SWAP
- [IF]
CODE SWAP
MOV @PSP,W \ 2
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] OVER [IF]
\ https://forth-standard.org/standard/core/OVER
\ OVER x1 x2 -- x1 x2 x1
- [UNDEFINED] OVER
- [IF]
CODE OVER
MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
MOV @PSP,TOS \ 2 -- x1 (x2) x1
ENDCODE
[THEN]
+ [UNDEFINED] DUP [IF] \ define DUP and DUP?
\ https://forth-standard.org/standard/core/DUP
\ DUP x -- x x duplicate top of stack
- [UNDEFINED] DUP
- [IF] \define DUP and DUP?
CODE DUP
BW1 SUB #2,PSP \ 2 push old TOS..
MOV TOS,0(PSP) \ 3 ..onto stack
ENDCODE
[THEN]
+ [UNDEFINED] DROP [IF]
\ https://forth-standard.org/standard/core/DROP
\ DROP x -- drop top of stack
- [UNDEFINED] DROP
- [IF]
CODE DROP
MOV @PSP+,TOS \ 2
MOV @IP+,PC \ 4
ENDCODE
[THEN]
+ [UNDEFINED] DEPTH [IF]
\ https://forth-standard.org/standard/core/DEPTH
\ DEPTH -- +n number of items on stack, must leave 0 if stack empty
- [UNDEFINED] DEPTH
- [IF]
CODE DEPTH
MOV TOS,-2(PSP)
MOV #PSTACK,TOS
ENDCODE
[THEN]
+ [UNDEFINED] >R [IF]
\ https://forth-standard.org/standard/core/toR
\ >R x -- R: -- x push to return stack
- [UNDEFINED] >R
- [IF]
CODE >R
PUSH TOS \ 3
MOV @PSP+,TOS \ 2
ENDCODE
[THEN]
+ [UNDEFINED] R> [IF]
\ https://forth-standard.org/standard/core/Rfrom
\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
- [UNDEFINED] R>
- [IF]
CODE R>
SUB #2,PSP \ 1
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] 1+ [IF]
\ https://forth-standard.org/standard/core/OnePlus
\ 1+ n1/u1 -- n2/u2 add 1 to TOS
- [UNDEFINED] 1+
- [IF]
CODE 1+
ADD #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] 1- [IF]
\ https://forth-standard.org/standard/core/OneMinus
\ 1- n1/u1 -- n2/u2 subtract 1 from TOS
- [UNDEFINED] 1-
- [IF]
CODE 1-
SUB #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] = [IF]
\ https://forth-standard.org/standard/core/Equal
\ = x1 x2 -- flag test x1=x2
- [UNDEFINED] =
- [IF]
CODE =
SUB @PSP+,TOS \ 2
0<> IF \ 2
ENDCODE
[THEN]
+ [UNDEFINED] IF [IF] \ define IF THEN
+
\ https://forth-standard.org/standard/core/IF
\ IF -- IFadr initialize conditional forward branch
- [UNDEFINED] IF
- [IF] \ define IF THEN
CODE IF \ immediate
SUB #2,PSP \
MOV TOS,0(PSP) \
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] ELSE [IF]
\ https://forth-standard.org/standard/core/ELSE
\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
- [UNDEFINED] ELSE
- [IF]
CODE ELSE \ immediate
ADD #4,&DP \ make room to compile two words
MOV &DP,W \ W=HERE+4
MOV W,TOS \ -- ELSEadr
MOV @IP+,PC
ENDCODE IMMEDIATE
+
[THEN]
+ [UNDEFINED] DO [IF] \ define DO LOOP +LOOP
+
\ https://forth-standard.org/standard/core/DO
\ DO -- DOadr L: -- 0
- [UNDEFINED] DO
- [IF] \ define DO LOOP +LOOP
HDNCODE XDO \ DO run time
MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor"
SUB @PSP+,X \ 2
MOV #XPLOO,X
GOTO BW2 \ goto BW1 LOOP
ENDCODE IMMEDIATE
+
[THEN]
+ [UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
+
\ https://forth-standard.org/standard/core/BEGIN
\ BEGIN -- BEGINadr initialize backward branch
- [UNDEFINED] BEGIN
- [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
-
CODE BEGIN
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE IMMEDIATE
\ https://forth-standard.org/standard/core/UNTIL
: REPEAT
POSTPONE AGAIN POSTPONE THEN
; IMMEDIATE
+
[THEN]
\ https://forth-standard.org/standard/core/CASE
- [UNDEFINED] CASE
- [IF]
+ [UNDEFINED] CASE [IF] \ define CASE OF ENDOF ENDCASE
: CASE
0
; IMMEDIATE \ -- #of-1
; IMMEDIATE
[THEN]
+ [UNDEFINED] + [IF]
\ https://forth-standard.org/standard/core/Plus
\ + n1/u1 n2/u2 -- n3/u3
- [UNDEFINED] +
- [IF]
CODE +
ADD @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] - [IF]
\ https://forth-standard.org/standard/core/Minus
\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
- [UNDEFINED] -
- [IF]
CODE -
SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3)
XOR #-1,TOS \ 1
ENDCODE
[THEN]
- [UNDEFINED] MAX
- [IF] \define MAX and MIN
+ [UNDEFINED] MAX [IF] \define MAX and MIN
CODE MAX \ n1 n2 -- n3 signed maximum
CMP @PSP,TOS \ n2-n1
S< ?GOTO FW1 \ n2<n1
[THEN] \ MAX
+ [UNDEFINED] 2* [IF]
\ https://forth-standard.org/standard/core/TwoTimes
\ 2* x1 -- x2 arithmetic left shift
- [UNDEFINED] 2*
- [IF]
CODE 2*
ADD TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] UM* [IF] \ case of hardware_MPY
\ https://forth-standard.org/standard/core/UMTimes
\ UM* u1 u2 -- udlo udhi unsigned 16x16->32 mult.
- [UNDEFINED] UM*
- [IF] \ case of hardware_MPY
CODE UM*
MOV @PSP,&MPY \ Load 1st operand for unsigned multiplication
BW1 MOV TOS,&OP2 \ Load 2nd operand
ENDCODE
[THEN]
+ [UNDEFINED] UM/MOD [IF]
\ https://forth-standard.org/standard/core/UMDivMOD
\ UM/MOD udlo|udhi u1 -- ur uq unsigned 32/16->r16 q16
- [UNDEFINED] UM/MOD
- [IF]
CODE UM/MOD
PUSH #DROP \
MOV #MUSMOD,PC \ execute MUSMOD then return to DROP
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
\ U*/ u1 u2 u3 -- uq u1*u2/u3
: U*/
>R UM* R> UM/MOD SWAP DROP
U/MOD SWAP DROP
;
+ [UNDEFINED] SPACES [IF]
\ https://forth-standard.org/standard/core/SPACES
\ SPACES n -- output n spaces
- [UNDEFINED] SPACES
- [IF]
: SPACES
BEGIN
?DUP
." we are on " DATE?
;
- RST_SET
-
- [UNDEFINED] S_
- [IF]
- CODE S_ \ Squote alias with blank instead quote separator
- MOV #0,&CAPS \ turn CAPS OFF
- COLON
- XSQUOTE , \ compile run-time code
- $20 WORD \ -- c-addr (= HERE)
- HI2LO
- MOV.B @TOS,TOS \ -- len compile string
- ADD #1,TOS \ -- len+1
- BIT #1,TOS \ C = ~Z
- ADDC TOS,&DP \ store aligned DP
- MOV @PSP+,TOS \ --
- MOV @RSP+,IP \ pop paired with push COLON
- MOV #$20,&CAPS \ turn CAPS ON (default state)
- MOV @IP+,PC \ NEXT
+ [UNDEFINED] S_ [IF]
+ CODE S_ \ Squote alias with blank instead of double quote separator
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV #'SP',TOS
+ MOV #S"+10,PC \ addr S" + 10 --> PC
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] ESC
- [IF]
+ [UNDEFINED] ESC [IF]
CODE ESC
CMP #0,&STATEADR
0= IF MOV @IP+,PC \ interpret time usage disallowed
; IMMEDIATE
[THEN]
+ [UNDEFINED] >BODY [IF]
\ https://forth-standard.org/standard/core/toBODY
\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word
- [UNDEFINED] >BODY
- [IF]
CODE >BODY
ADD #4,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] EXECUTE [IF]
\ https://forth-standard.org/standard/core/EXECUTE
\ EXECUTE i*x xt -- j*x execute Forth word at 'xt'
- [UNDEFINED] EXECUTE
- [IF] \ "
CODE EXECUTE
PUSH TOS \ 3 push xt
MOV @PSP+,TOS \ 2
ENDCODE
[THEN]
+ [UNDEFINED] EVALUATE [IF]
+
+\ EVALUATE upside down...
+ CODENNM \ as the end of EVALUATE
+ MOV @RSP+,&TOIN \ 4
+ MOV @RSP+,&SOURCE_ORG \ 4
+ MOV @RSP+,&SOURCE_LEN \ 4
+ MOV @RSP+,IP
+ MOV @IP+,PC
+ ENDCODE \ -- end_of_EVALUATE_addr
+
\ https://forth-standard.org/standard/core/EVALUATE
\ EVALUATE \ i*x c-addr u -- j*x interpret string
- [UNDEFINED] EVALUATE
- [IF]
CODE EVALUATE
MOV #SOURCE_LEN,X \ 2
MOV @X+,S \ 2 S = SOURCE_LEN
MOV @X+,T \ 2 T = SOURCE_ORG
MOV @X+,W \ 2 W = TOIN
PUSHM #4,IP \ 6 PUSHM IP,S,T,W
- LO2HI
- [ ' \ 8 + , ] \ compile INTERPRET = BACKSLASH + 8
- HI2LO
- MOV @RSP+,&TOIN \ 4
- MOV @RSP+,&SOURCE_ORG \ 4
- MOV @RSP+,&SOURCE_LEN \ 4
- MOV @RSP+,IP
- MOV @IP+,PC
- ENDCODE
+ MOV PC,IP \ 1
+ ADD #8,IP \ 1 IP = address compiled after ENDCODE
+ MOV #INTERPRET,PC \ 3 addr defined in MSP430FRxxxx.pat
+ NOP \ 1 stuffing instruction
+ ENDCODE \
+ , \ end_of_EVALUATE_addr -- compile the end_of_EVALUATE_addr
+
[THEN]
+ [UNDEFINED] CR [IF]
\ https://forth-standard.org/standard/core/CR
\ CR -- send CR+LF to the output device
- [UNDEFINED] CR
- [IF]
\ DEFER CR \ DEFERed definition, by default executes that of :NONAME
CODE CR \ create a DEFER definition of CR
[THEN]
: SET_TIME
- ESC [8;40;80t \ set terminal display 42L * 80C
+ ESC [8;42;80t \ set terminal display 42L * 80C
39 0 DO CR LOOP \ to avoid erasing any line of source, create 42 empty lines
ESC [H \ then set cursor home
CR ." DATE (DMY): "
EXECUTE \ wait human input for H M S
EVALUATE \ interpret this input
CR TIME! \ set time
- RST_RET \ remove code beyond RST_HERE
;
-ECHO
-SET_TIME
+ RST_SET
+
+ ECHO
+ SET_TIME
; BOOT.4th for MSP_EXP430FR5994
; --------
- [UNDEFINED] DUP
- [IF]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] DUP [IF]
CODE DUP
BW1 SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] DROP
- [IF]
+ [UNDEFINED] DROP [IF]
CODE DROP
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] =
- [IF]
+ [UNDEFINED] = [IF]
CODE =
SUB @R15+,R14
SUB #1,R14
ENDCODE
[THEN]
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
CODE +
ADD @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] EXECUTE
- [IF]
+ [UNDEFINED] EXECUTE [IF]
CODE EXECUTE
PUSH R14
MOV @R15+,R14
ENDCODE
[THEN]
- DUP 4 =
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+; ------------------------------------------------------------------------------
+; WARNING !
+; ------------------------------------------------------------------------------
+; it is not recommended here to compile then execute a definition
+; because the risk of crushing thereafter.
+; Interpreting mode as below is required:
+; ------------------------------------------------------------------------------
+
+ DUP 6 =
[IF]
DROP
RST_RET
LOAD" SD_TEST.4TH"
[ELSE]
- ' SYS $0A + EXECUTE
+ ' SYS $0E + EXECUTE
[THEN]
+; ------------
+; CHNGBAUD.4th for MSP_EXP430FR5994
+; ------------
+
CODE I2CTERM_ABORT
SUB #4,R15
MOV R14,2(R15)
0<> IF MOV #0,R14 THEN
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" <-- Ouch! unexpected I2C_FastForth target!"
RST_RET
;
I2CTERM_ABORT
-; ------------
-; CHNGBAUD.4th for MSP_EXP430FR5994
-; ------------
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] DUP [IF]
CODE DUP
[THEN]
[UNDEFINED] CR [IF]
- DEFER CR
+
+ CODE CR
+ MOV #$409E,R0
+ ENDCODE
:NONAME
$0D EMIT $0A EMIT
CODE U/
SUB #2,R15
MOV #0,0(R15)
- CALL #$403E
+ CALL #$4028
MOV @R15,R14
ADD #4,R15
MOV @R13+,R0
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE [IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] DO
- [IF]
+ [UNDEFINED] DO [IF]
HDNCODE XDO
MOV #$8000,R9
SUB @R15+,R9
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
[UNDEFINED] CASE [IF]
: CASE 0 ; IMMEDIATE
-
: OF
- 1+
- >R
+ 1+
+ >R
POSTPONE OVER POSTPONE =
- POSTPONE IF
- POSTPONE DROP
- R>
+ POSTPONE IF
+ POSTPONE DROP
+ R>
; IMMEDIATE
: ENDOF
- >R
+ >R
POSTPONE ELSE
- R>
+ R>
; IMMEDIATE
: ENDCASE
; IMMEDIATE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
[UNDEFINED] S_ [IF]
CODE S_
- MOV #0,&$1DC0
- COLON
- $401E ,
- $20 WORD
- HI2LO
- MOV.B @R14,R14
- ADD #1,R14
- BIT #1,R14
- ADDC R14,&$1DC8
- MOV @R15+,R14
- MOV @R1+,R13
- MOV #$20,&$1DC0
- MOV @R13+,R0
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV #$20,R14
+ MOV #S"+10,R0
ENDCODE IMMEDIATE
[THEN]
[UNDEFINED] ESC [IF]
CODE ESC
- CMP #0,&$1DBC
+ CMP #0,&$1DB4
0= IF MOV @R13+,R0
THEN
COLON
$1802 !
CR ESC [7m
." Change baudrate in Teraterm, save its setup, then reset target."
+ ESC [0m
;
CHNGBAUD
+; ----------
+; CORDIC.4th for MSP_EXP430FR5994
+; ----------
+
CODE ABORT_CORDIC
SUB #4,R15
MOV R14,2(R15)
0<> IF MOV #0,R14 THEN
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" build FastForth with FIXPOINT_INPUT addon"
RST_RET
;
ABORT_CORDIC
-; ----------
-; CORDIC.4th for MSP_EXP430FR5994
-; ----------
-
MARKER {CORDIC}
CREATE T_ARCTAN
39797 ,
39797 ,
- [UNDEFINED] DABS
- [IF]
+ [UNDEFINED] DABS [IF]
CODE DABS
AND #-1,R14
S< IF
ENDCODE
[THEN]
- [UNDEFINED] R>
- [IF]
+ [UNDEFINED] R> [IF]
CODE R>
SUB #2,R15
MOV R14,0(R15)
MOV @R13+,R0
ENDCODE
- $180E 1 TSTBIT
+ $180E 8 TSTBIT
RST_RET
[IF] ; MSP430FRxxxx with hardware_MPY
- [UNDEFINED] HOLDS
- [IF]
- CODE HOLDS
- MOV @R15+,R9
-BW3 ADD R14,R9
- MOV &$1DB2,R8
- BEGIN
- SUB #1,R9
- SUB #1,R14
- U>= WHILE
- SUB #1,R8
- MOV.B @R9,0(R8)
- REPEAT
- MOV R8,&$1DB2
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
+ [UNDEFINED] HOLDS [IF]
+ CODE HOLDS
+ MOV @R15+,R9
+BW3 ADD R14,R9
+ MOV &$1DB2,R8
+ BEGIN
+ SUB #1,R9
+ SUB #1,R14
+ U>= WHILE
+ SUB #1,R8
+ MOV.B @R9,0(R8)
+ REPEAT
+ MOV R8,&$1DB2
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
[THEN]
- [UNDEFINED] F#S
- [IF]
- CODE F#S
- MOV 2(R15),R9
- MOV @R15,2(R15)
- MOV R9,0(R15)
- MOV R14,R11
- MOV #0,R12
- BEGIN MOV @R15,&$4C0
- MOV &$1DBE,&$4C8
- MOV &$4E4,0(R15)
- MOV &$4E6,R14
- CMP #10,R14
- U>= IF ADD #7,R14
- THEN ADD #$30,R14
- MOV.B R14,$1D90(R12)
- ADD #1,R12
- CMP R11,R12
- 0= UNTIL MOV R11,R14
- MOV #0,0(R15)
- MOV #$1D90,R9
- GOTO BW3
- ENDCODE
+ [UNDEFINED] F#S [IF]
+ CODE F#S
+ MOV 2(R15),R9
+ MOV @R15,2(R15)
+ MOV R9,0(R15)
+ MOV R14,R11
+ MOV #0,R12
+ BEGIN
+ MOV @R15,&$4C0
+ MOV &$1DB6,&$4C8
+ MOV &$4E4,0(R15)
+ MOV &$4E6,R14
+ CMP #10,R14
+ U>= IF
+ ADD #7,R14
+ THEN
+ ADD #$30,R14
+ MOV.B R14,$1D90(R12)
+ ADD #1,R12
+ CMP R11,R12
+ 0= UNTIL
+ MOV R11,R14
+ MOV #0,0(R15)
+ MOV #$1D90,R9
+ GOTO BW3
+ ENDCODE
[THEN]
- HDNCODE XSCALE
- MOV T_SCALE(R10),&$4D4
- MOV #0,&$4D6
- MOV R9,&$4C8
- MOV &$4E6,R9
- MOV @R1+,R0
- ENDCODE
+ HDNCODE XSCALE
+ MOV T_SCALE(R10),&$4D4
+ MOV #0,&$4D6
+ MOV R9,&$4C8
+ MOV &$4E6,R9
+ MOV @R1+,R0
+ ENDCODE
[ELSE] ; no hardware multiplier
[UNDEFINED] HOLDS
[IF]
- CODE HOLDS
- MOV @R15+,R9
-BW3 ADD R14,R9
- MOV &$1DB2,R8
- BEGIN
- SUB #1,R9
- SUB #1,R14
- U>= WHILE
- SUB #1,R8
- MOV.B @R9,0(R8)
- REPEAT
- MOV R8,&$1DB2
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
+ CODE HOLDS
+ MOV @R15+,R9
+BW3 ADD R14,R9
+ MOV &$1DB2,R8
+ BEGIN
+ SUB #1,R9
+ SUB #1,R14
+ U>= WHILE
+ SUB #1,R8
+ MOV.B @R9,0(R8)
+ REPEAT
+ MOV R8,&$1DB2
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
[THEN]
[UNDEFINED] F#S
[IF]
- CODE F#S
- MOV @R15,R12
- MOV #0,R11
- PUSHM #3,R13
- MOV 2(R15),0(R15)
- MOV R14,2(R15)
- BEGIN MOV &$1DBE,R14
- LO2HI
- UM*
- HI2LO
- CMP #10,R14
- U>= IF ADD #7,R14
- THEN ADD #$30,R14
- MOV @R1,R11
- MOV.B R14,$1D90(R11)
- ADD #1,R11
- MOV R11,0(R1)
- CMP 2(R15),R11
- U>= UNTIL POPM #3,R13
- MOV R11,R14
- MOV R12,2(R15)
- MOV #0,0(R15)
- MOV #$1D90,R9
- GOTO BW3
- ENDCODE
+ CODE F#S
+ MOV @R15,R12
+ MOV #0,R11
+ PUSHM #3,R13
+ MOV 2(R15),0(R15)
+ MOV R14,2(R15)
+ BEGIN
+ MOV &$1DB6,R14
+ LO2HI
+ UM*
+ HI2LO
+ CMP #10,R14
+ U>= IF
+ ADD #7,R14
+ THEN
+ ADD #$30,R14
+ MOV @R1,R11
+ MOV.B R14,$1D90(R11)
+ ADD #1,R11
+ MOV R11,0(R1)
+ CMP 2(R15),R11
+ U>= UNTIL
+ POPM #3,R13
+ MOV R11,R14
+ MOV R12,2(R15)
+ MOV #0,0(R15)
+ MOV #$1D90,R9
+ GOTO BW3
+ ENDCODE
[THEN]
- HDNCODE XSCALE
- MOV T_SCALE(R10),R6
- UMSTAR1 MOV #0,R8
- MOV #0,R12
- MOV #0,R11
- MOV #1,R10
- BEGIN BIT R10,R6
- 0<> IF ADD R9,R12
+ HDNCODE XSCALE
+ MOV T_SCALE(R10),R6
+ MOV #0,R8
+ MOV #0,R12
+ MOV #0,R11
+ MOV #1,R10
+ BEGIN
+ BIT R10,R6
+ 0<> IF
+ ADD R9,R12
ADDC R8,R11
- THEN ADD R9,R9
- ADDC R8,R8
- ADD R10,R10
- U>= UNTIL
- MOV R11,R9
- MOV #$40C4,R6
- MOV @R1+,R0
- ENDCODE
+ THEN
+ ADD R9,R9
+ ADDC R8,R8
+ ADD R10,R10
+ U>= UNTIL
+ MOV R11,R9
+ MOV #$40AE,R6
+ MOV @R1+,R0
+ ENDCODE
[THEN] ; endcase of hardware multiplier
MOV #0,2(R15)
MOV R14,0(R15)
MOV #286,R14
- CALL #$403E
+ CALL #$4028
MOV @R15+,0(R15)
CMP #0,R6
S< IF
ADD #1,0(R15)
ADDC #0,R14
THEN
- MOV #$40C4,R6
+ MOV #$40AE,R6
MOV @R13+,R0
ENDCODE
- [UNDEFINED] F.
- [IF]
+ [UNDEFINED] F. [IF]
CODE F.
MOV R14,R12
MOV #4,R11
- MOV &$1DBE,R10
+ MOV &$1DB6,R10
CMP ##10,R10
0= IF
ADD #1,R11
RST_SET
- [UNDEFINED] SWAP
- [IF]
+ [UNDEFINED] SWAP [IF]
CODE SWAP
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] ROT
- [IF]
+ [UNDEFINED] ROT [IF]
CODE ROT
MOV @R15,R10
MOV R14,0(R15)
ECHO
-10000 89,0 POL2REC . . ; sin, cos -->
-10000 75,0 POL2REC . . ; sin, cos -->
-10000 60,0 POL2REC . . ; sin, cos -->
-10000 45,0 POL2REC . . ; sin, cos -->
-10000 30,0 POL2REC . . ; sin, cos -->
-10000 15,0 POL2REC . . ; sin, cos -->
-10000 1,0 POL2REC . . ; sin, cos -->
-16384 30,0 POL2REC SWAP . . ; x, y -->
-16384 45,0 POL2REC SWAP . . ; x, y -->
-16384 60,0 POL2REC SWAP . . ; x, y -->
-
-10000 -89,0 POL2REC . . ; sin, cos -->
-10000 -75,0 POL2REC . . ; sin, cos -->
-10000 -60,0 POL2REC . . ; sin, cos -->
-10000 -45,0 POL2REC . . ; sin, cos -->
-10000 -30,0 POL2REC . . ; sin, cos -->
-10000 -15,0 POL2REC . . ; sin, cos -->
-10000 -1,0 POL2REC . . ; sin, cos -->
-16384 -30,0 POL2REC SWAP . . ; x, y -->
-16384 -45,0 POL2REC SWAP . . ; x, y -->
-16384 -60,0 POL2REC SWAP . . ; x, y -->
-
--10000 89,0 POL2REC . . ; sin, cos -->
--10000 75,0 POL2REC . . ; sin, cos -->
--10000 60,0 POL2REC . . ; sin, cos -->
--10000 45,0 POL2REC . . ; sin, cos -->
--10000 30,0 POL2REC . . ; sin, cos -->
--10000 15,0 POL2REC . . ; sin, cos -->
--10000 1,0 POL2REC . . ; sin, cos -->
--16384 30,0 POL2REC SWAP . . ; x, y -->
--16384 45,0 POL2REC SWAP . . ; x, y -->
--16384 60,0 POL2REC SWAP . . ; x, y -->
-
--10000 -89,0 POL2REC . . ; sin, cos -->
--10000 -75,0 POL2REC . . ; sin, cos -->
--10000 -60,0 POL2REC . . ; sin, cos -->
--10000 -45,0 POL2REC . . ; sin, cos -->
--10000 -30,0 POL2REC . . ; sin, cos -->
--10000 -15,0 POL2REC . . ; sin, cos -->
--10000 -1,0 POL2REC . . ; sin, cos -->
--16384 -30,0 POL2REC SWAP . . ; x, y -->
--16384 -45,0 POL2REC SWAP . . ; x, y -->
--16384 -60,0 POL2REC SWAP . . ; x, y -->
-
-
-2 1 REC2POL F. . ; phase module -->
-2 -1 REC2POL F. . ; phase module -->
-20 10 REC2POL F. . ; phase module -->
-20 -10 REC2POL F. . ; phase module -->
-200 100 REC2POL F. . ; phase module -->
-100 -100 REC2POL F. . ; phase module -->
-2000 1000 REC2POL F. . ; phase module -->
-1000 -1000 REC2POL F. . ; phase module -->
-16000 8000 REC2POL F. . ; phase module -->
-16000 -8000 REC2POL F. . ; phase module -->
-16000 0 REC2POL F. . ; phase module -->
-0 16000 REC2POL F. . ; phase module -->
-
--2 1 REC2POL F. . ; phase module -->
--2 -1 REC2POL F. . ; phase module -->
--20 10 REC2POL F. . ; phase module -->
--20 -10 REC2POL F. . ; phase module -->
--200 100 REC2POL F. . ; phase module -->
--100 -100 REC2POL F. . ; phase module -->
--2000 1000 REC2POL F. . ; phase module -->
--1000 -1000 REC2POL F. . ; phase module -->
--16000 8000 REC2POL F. . ; phase module -->
--16000 -8000 REC2POL F. . ; phase module -->
-16000 0 REC2POL F. . ; phase module -->
-0 16000 REC2POL F. . ; phase module -->
-
-10000 89,0 POL2REC REC2POL ROT . F.
-10000 75,0 POL2REC REC2POL ROT . F.
-10000 60,0 POL2REC REC2POL ROT . F.
-10000 45,0 POL2REC REC2POL ROT . F.
-10000 30,0 POL2REC REC2POL ROT . F.
-10000 26,565 POL2REC REC2POL ROT . F.
-10000 15,0 POL2REC REC2POL ROT . F.
-10000 14,036 POL2REC REC2POL ROT . F.
-10000 7,125 POL2REC REC2POL ROT . F.
-10000 1,0 POL2REC REC2POL ROT . F.
+10000 89,0 POL2REC . . ; sin, cos -->
+10000 75,0 POL2REC . . ; sin, cos -->
+10000 60,0 POL2REC . . ; sin, cos -->
+10000 45,0 POL2REC . . ; sin, cos -->
+10000 30,0 POL2REC . . ; sin, cos -->
+10000 15,0 POL2REC . . ; sin, cos -->
+10000 1,0 POL2REC . . ; sin, cos -->
+16384 30,0 POL2REC SWAP . . ; x, y -->
+16384 45,0 POL2REC SWAP . . ; x, y -->
+16384 60,0 POL2REC SWAP . . ; x, y -->
+
+10000 -89,0 POL2REC . . ; sin, cos -->
+10000 -75,0 POL2REC . . ; sin, cos -->
+10000 -60,0 POL2REC . . ; sin, cos -->
+10000 -45,0 POL2REC . . ; sin, cos -->
+10000 -30,0 POL2REC . . ; sin, cos -->
+10000 -15,0 POL2REC . . ; sin, cos -->
+10000 -1,0 POL2REC . . ; sin, cos -->
+16384 -30,0 POL2REC SWAP . . ; x, y -->
+16384 -45,0 POL2REC SWAP . . ; x, y -->
+16384 -60,0 POL2REC SWAP . . ; x, y -->
+
+-10000 89,0 POL2REC . . ; sin, cos -->
+-10000 75,0 POL2REC . . ; sin, cos -->
+-10000 60,0 POL2REC . . ; sin, cos -->
+-10000 45,0 POL2REC . . ; sin, cos -->
+-10000 30,0 POL2REC . . ; sin, cos -->
+-10000 15,0 POL2REC . . ; sin, cos -->
+-10000 1,0 POL2REC . . ; sin, cos -->
+-16384 30,0 POL2REC SWAP . . ; x, y -->
+-16384 45,0 POL2REC SWAP . . ; x, y -->
+-16384 60,0 POL2REC SWAP . . ; x, y -->
+
+-10000 -89,0 POL2REC . . ; sin, cos -->
+-10000 -75,0 POL2REC . . ; sin, cos -->
+-10000 -60,0 POL2REC . . ; sin, cos -->
+-10000 -45,0 POL2REC . . ; sin, cos -->
+-10000 -30,0 POL2REC . . ; sin, cos -->
+-10000 -15,0 POL2REC . . ; sin, cos -->
+-10000 -1,0 POL2REC . . ; sin, cos -->
+-16384 -30,0 POL2REC SWAP . . ; x, y -->
+-16384 -45,0 POL2REC SWAP . . ; x, y -->
+-16384 -60,0 POL2REC SWAP . . ; x, y -->
+
+
+2 1 REC2POL F. . ; phase module -->
+2 -1 REC2POL F. . ; phase module -->
+20 10 REC2POL F. . ; phase module -->
+20 -10 REC2POL F. . ; phase module -->
+200 100 REC2POL F. . ; phase module -->
+100 -100 REC2POL F. . ; phase module -->
+2000 1000 REC2POL F. . ; phase module -->
+1000 -1000 REC2POL F. . ; phase module -->
+16000 8000 REC2POL F. . ; phase module -->
+16000 -8000 REC2POL F. . ; phase module -->
+16000 0 REC2POL F. . ; phase module -->
+0 16000 REC2POL F. . ; phase module -->
+
+-2 1 REC2POL F. . ; phase module -->
+-2 -1 REC2POL F. . ; phase module -->
+-20 10 REC2POL F. . ; phase module -->
+-20 -10 REC2POL F. . ; phase module -->
+-200 100 REC2POL F. . ; phase module -->
+-100 -100 REC2POL F. . ; phase module -->
+-2000 1000 REC2POL F. . ; phase module -->
+-1000 -1000 REC2POL F. . ; phase module -->
+-16000 8000 REC2POL F. . ; phase module -->
+-16000 -8000 REC2POL F. . ; phase module -->
+16000 0 REC2POL F. . ; phase module -->
+0 16000 REC2POL F. . ; phase module -->
+
+10000 89,0 POL2REC REC2POL ROT . F.
+10000 75,0 POL2REC REC2POL ROT . F.
+10000 60,0 POL2REC REC2POL ROT . F.
+10000 45,0 POL2REC REC2POL ROT . F.
+10000 30,0 POL2REC REC2POL ROT . F.
+10000 26,565 POL2REC REC2POL ROT . F.
+10000 15,0 POL2REC REC2POL ROT . F.
+10000 14,036 POL2REC REC2POL ROT . F.
+10000 7,125 POL2REC REC2POL ROT . F.
+10000 1,0 POL2REC REC2POL ROT . F.
\ ; CORETEST.4TH for any FastForth target
\ ; -------------------------------------
-MARKER {CORETEST}
+ MARKER {CORETEST}
-: ABORT_TEST \ flag --
-$0D EMIT \ return to column 1
-POSTPONE {CORETEST} \ remove all test words
-ABORT" {CORE_ANS} word set not found !"
-;
+ : ABORT_TEST \ flag --
+ $0D EMIT \ return to column 1
+ POSTPONE {CORETEST} \ remove all test words
+ ABORT" {CORE_ANS} word set not found !"
+ ;
-[UNDEFINED] {CORE_ANS} ABORT_TEST
+ [UNDEFINED] {CORE_ANS} ABORT_TEST
-: CORETESTSUCCESS
-$0D EMIT \ -- $0D return to column 1
-$0A BASE ! \ set decimal
-{CORETEST} \ remove all test words
-." CORETEST + COREPLUSTEST success!" \ true --
-;
+ : CORETESTSUCCESS
+ $0D EMIT \ -- $0D return to column 1
+ $0A BASE ! \ set decimal
+ {CORETEST} \ remove all test words
+ ." CORETEST + COREPLUSTEST success!" \ true --
+ ;
-[UNDEFINED] SM/REM [IF]
-CODE SM/REM
-MOV R14,R12
-MOV @R15,R11
-CMP #0,R14
-S< IF
- XOR #-1,R14
- ADD #1,R14
-THEN
-CMP #0,0(R15)
-S< IF
- XOR #-1,2(R15)
- XOR #-1,0(R15)
- ADD #1,2(R15)
- ADDC #0,0(R15)
-THEN
-PUSHM #3,R13
-LO2HI
- UM/MOD
-HI2LO
-POPM #3,R13
-CMP #0,R11
-S< IF
- XOR #-1,0(R15)
- ADD #1,0(R15)
-THEN
-XOR R12,R11
-CMP #0,R11
-S< IF
- XOR #-1,R14
- ADD #1,R14
-THEN
-MOV @R13+,R0
-ENDCODE
-[THEN]
-
-[UNDEFINED] FM/MOD [IF]
+ [UNDEFINED] SM/REM
+ [IF]
+\ https://forth-standard.org/standard/core/SMDivREM
+\ SM/REM d1 n1 -- r q symmetric signed div'n
+ CODE SM/REM
+ MOV R14,R12
+ MOV @R15,R11
+ CMP #0,R14
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ CMP #0,0(R15)
+ S< IF
+ XOR #-1,2(R15)
+ XOR #-1,0(R15)
+ ADD #1,2(R15)
+ ADDC #0,0(R15)
+ THEN
+ PUSHM #3,R13
+ LO2HI
+ UM/MOD
+ HI2LO
+ POPM #3,R13
+ CMP #0,R11
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ THEN
+ XOR R12,R11
+ CMP #0,R11
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] FM/MOD
+ [IF]
\ https://forth-standard.org/standard/core/FMDivMOD
\ FM/MOD d1 n1 -- r q floored signed div'n
-: FM/MOD
-SM/REM
-HI2LO \ -- remainder quotient S=divisor
-CMP #0,0(R15) \ remainder <> 0 ?
-0<> IF
- CMP #1,R14 \ quotient < 1 ?
- S< IF
- ADD R12,0(R15) \ add divisor to remainder
- SUB #1,R14 \ decrement quotient
+ : FM/MOD
+ SM/REM
+ HI2LO \ -- remainder quotient S=divisor
+ CMP #0,0(R15) \ remainder <> 0 ?
+ 0<> IF
+ CMP #1,R14 \ quotient < 1 ?
+ S< IF
+ ADD R12,0(R15) \ add divisor to remainder
+ SUB #1,R14 \ decrement quotient
+ THEN
THEN
-THEN
-MOV @R1+,R13
-MOV @R13+,R0
-ENDCODE
-[THEN]
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
\ From: John Hayes S1I
\ Subject: tester.fr
FALSE VERBOSE !
\ TRUE VERBOSE !
-\ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
-\ DEPTH ?DUP
-\ IF DUP 0< IF NEGATE 0
-\ DO 0 LOOP
-\ ELSE 0 DO DROP LOOP THEN
-\ THEN ;
-\
-\ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
-\ \ THE LINE THAT HAD THE ERROR.
-\ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
-\ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
-\ \ QUIT \ *** Uncomment this line to QUIT on an error
-\ ;
+: EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO.
+ DEPTH ?DUP
+ IF DUP 0< IF NEGATE 0
+ DO 0 LOOP
+ ELSE 0 DO DROP LOOP THEN
+ THEN ;
+
+: ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY
+ \ THE LINE THAT HAD THE ERROR.
+ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR
+ EMPTY-STACK \ THROW AWAY EVERY THING ELSE
+ QUIT \ *** Uncomment this line to QUIT on an error
+;
VARIABLE ACTUAL-DEPTH \ STACK RECORD
CREATE ACTUAL-RESULTS 20 CELLS ALLOT
0 DO \ FOR EACH STACK ITEM
ACTUAL-RESULTS I CELLS + @ \ COMPARE ACTUAL WITH EXPECTED
\ = 0= IF S" INCORRECT RESULT: " ERROR LEAVE THEN \ jmt
- = 0= IF TRUE ABORT" INCORRECT RESULT" THEN \ jmt : abort with colorised message
+ = 0= ABORT" INCORRECT RESULT" \ jmt : abort with colorised message
LOOP
THEN
ELSE \ DEPTH MISMATCH
: TESTING \ ( -- ) TALKING COMMENT.
SOURCE VERBOSE @
IF DUP >R TYPE CR R> >IN !
-\ ELSE >IN ! DROP [CHAR] * EMIT
- ELSE >IN ! DROP \ [CHAR] * EMIT
+ ELSE >IN ! DROP [CHAR] * EMIT
THEN ;
-ECHO HEX
+HEX
\ From: John Hayes S1I
\ Subject: core.fr
T{ 3 GI6 -> 0 1 2 3 }T
T{ 4 GI6 -> 0 1 2 3 4 }T
-\ ------------------------------------------------------------------------
+\ ----------------------------------------------------------------------------
TESTING DO LOOP +LOOP I J UNLOOP LEAVE EXIT
T{ : GD1 DO I LOOP ; -> }T
CREATE ABUF 80 CHARS ALLOT
-: ACCEPT-TEST
- CR ." PLEASE TYPE UP TO 80 CHARACTERS: "
-ABUF 80 \ ACCEPT \ JMT
- ['] ACCEPT >BODY \ JMT: find default part of deferred ACCEPT
- EXECUTE \ JMT: execute ACCEPT
- CR ." RECEIVED: " [CHAR] " EMIT
- ABUF SWAP TYPE [CHAR] " EMIT CR
-;
+\ ' ACCEPT DUP >BODY SWAP 2 + @ = \ JMT:
+\ [IF] \ JMT: ACCEPT is not redirected
+ : ACCEPT-TEST
+ CR ." PLEASE TYPE UP TO 80 CHARACTERS: "
+ ABUF 80 ACCEPT
+ CR ." RECEIVED: " [CHAR] " EMIT
+ ABUF SWAP TYPE [CHAR] " EMIT CR
+ ;
+\ [ELSE] \ JMT: ACCEPT is redirected
+\ : ACCEPT-TEST
+\ ['] NOECHO >BODY DUP @ @ \ JMT: -- NOECHO_BODY YEMIT_exec
+\ SWAP 2 - @ \ JMT: -- YEMIT_exec NOECHO_exec
+\ = DUP \ JMT: -- NOECHO_flag NOECHO_flag
+\ IF ECHO THEN \ JMT: -- NOECHO_flag
+\ CR ." PLEASE TYPE UP TO 80 CHARACTERS: "
+\ ['] ACCEPT >BODY \ JMT: find default exec part of ACCEPT
+\ EXECUTE \ JMT: execute it
+\ CR ." RECEIVED: " [CHAR] " EMIT
+\ ABUF SWAP TYPE [CHAR] " EMIT CR
+\ IF NOECHO THEN \ JMT: --
+\ ;
+\ [THEN]
T{ ACCEPT-TEST -> }T
\ ZYXWVUTSRQPONMLKJIHGFEDCBAzyxwvutsrqponmlkjihgfedcba
-\ ------------------------------------------------------------------------
+ \ ------------------------------------------------------------------------
TESTING DICTIONARY SEARCH RULES
T{ : GDX 123 ; : GDX GDX 234 ; -> }T
T{ MA0 -> }T
T{ MA? MA0 MA? MA1 MA? MA2 -> FALSE FALSE FALSE }T
+ECHO
CORETESTSUCCESS
SUB #2,R15
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
;
ABORT_CORE_ANS
- [UNDEFINED] BC!
- [IF]
+ [UNDEFINED] BC! [IF]
CODE BC!
BIC @R15+,0(R14)
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] BS!
- [IF]
+ [UNDEFINED] BS! [IF]
CODE BS!
BIS @R15+,0(R14)
MOV @R15+,R14
; CORE_ANS.4th for MSP_EXP430FR5994
; ----------------------------------
+ [DEFINED] {CORE_ANS}
+ [IF] {CORE_ANS} [THEN]
+
+ [UNDEFINED] {CORE_ANS} [IF]
+
MARKER {CORE_ANS}
- [UNDEFINED] HERE
- [IF]
+ [UNDEFINED] ABORT [IF]
+ CODE ABORT
+ MOV #ALLOT+$08,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] QUIT [IF]
+ CODE QUIT
+ MOV #ALLOT+$0E,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] HERE [IF]
CODE HERE
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE
[THEN]
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
CODE +
ADD @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] -
- [IF]
+ [UNDEFINED] - [IF]
CODE -
SUB @R15+,R14
XOR #-1,R14
ENDCODE
[THEN]
- [UNDEFINED] DUP
- [IF]
+ [UNDEFINED] DUP [IF]
+
CODE DUP
BW1 SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] EXIT
- [IF]
+ [UNDEFINED] EXIT [IF]
CODE EXIT
MOV @R1+,R13
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] DEPTH
- [IF]
+ [UNDEFINED] DEPTH [IF]
CODE DEPTH
MOV R14,-2(R15)
MOV #$1C80,R14
ENDCODE
[THEN]
- [UNDEFINED] SWAP
- [IF]
+ [UNDEFINED] SWAP [IF]
CODE SWAP
PUSH R14
MOV @R15,R14
ENDCODE
[THEN]
- [UNDEFINED] DROP
- [IF]
+ [UNDEFINED] DROP [IF]
CODE DROP
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] OVER
- [IF]
+ [UNDEFINED] OVER [IF]
CODE OVER
MOV R14,-2(R15)
MOV @R15,R14
ENDCODE
[THEN]
- [UNDEFINED] NIP
- [IF]
+ [UNDEFINED] NIP [IF]
CODE NIP
ADD #2,R15
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] >R
- [IF]
+ [UNDEFINED] >R [IF]
CODE >R
PUSH R14
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] R>
- [IF]
+ [UNDEFINED] R> [IF]
CODE R>
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] @
- [IF]
- CODE @
- MOV @R14,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] !
- [IF]
- CODE !
- MOV @R15+,0(R14)
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] C@
- [IF]
+ [UNDEFINED] C@ [IF]
CODE C@
MOV.B @R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] C!
- [IF]
+ [UNDEFINED] C! [IF]
CODE C!
MOV.B @R15+,0(R14)
ADD #1,R15
ENDCODE
[THEN]
- [UNDEFINED] C,
- [IF]
+ [UNDEFINED] C, [IF]
CODE C,
- MOV &$1DC8,R10
+ MOV &$1DC0,R10
MOV.B R14,0(R10)
- ADD #1,&$1DC8
+ ADD #1,&$1DC0
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] 0=
- [IF]
+ [UNDEFINED] 0= [IF]
CODE 0=
SUB #1,R14
SUBC R14,R14
ENDCODE
[THEN]
- [UNDEFINED] 0<>
- [IF]
+ [UNDEFINED] 0<> [IF]
CODE 0<>
SUB #1,R14
SUBC R14,R14
ENDCODE
[THEN]
- [UNDEFINED] 0<
- [IF]
+ [UNDEFINED] 0< [IF]
CODE 0<
-BW1 ADD R14,R14
+ ADD R14,R14
SUBC R14,R14
XOR #-1,R14
MOV @R13+,R0
ENDCODE
[THEN]
-
- [UNDEFINED] S>D
- [IF]
+ [UNDEFINED] S>D [IF]
: S>D
DUP 0<
;
[THEN]
- [UNDEFINED] =
- [IF]
+ [UNDEFINED] = [IF]
CODE =
SUB @R15+,R14
SUB #1,R14
ENDCODE
[THEN]
- [UNDEFINED] U<
- [IF]
+ [UNDEFINED] U< [IF]
- CODE U<
+ CODE U>
SUB @R15+,R14
U< ?GOTO FW1
- 0<> IF
-BW1 MOV #-1,R14
- THEN
+BW1 AND #0,R14
MOV @R13+,R0
ENDCODE
- CODE U>
+ CODE U<
SUB @R15+,R14
+ 0= ?GOTO BW1
U< ?GOTO BW1
-FW1 AND #0,R14
+FW1 MOV #-1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] <
- [IF]
+ [UNDEFINED] < [IF]
- CODE <
+ CODE >
SUB @R15+,R14
S< ?GOTO FW1
- 0<> IF
-BW1 MOV #-1,R14
- THEN
+BW1 AND #0,R14
MOV @R13+,R0
ENDCODE
- CODE >
+ CODE <
SUB @R15+,R14
+ 0= ?GOTO BW1
S< ?GOTO BW1
-FW1 AND #0,R14
+FW1 MOV #-1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] IF
- [IF]
+ [UNDEFINED] IF [IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] ELSE
- [IF]
+ [UNDEFINED] ELSE [IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] BEGIN
- [IF]
+ [UNDEFINED] BEGIN [IF]
CODE BEGIN
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE IMMEDIATE
CODE UNTIL
- MOV #$40AC,R9
-BW1 ADD #4,&$1DC8
- MOV &$1DC8,R10
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
MOV @R15+,R14
ENDCODE IMMEDIATE
CODE AGAIN
- MOV #$40B2,R9
+ MOV #$409C,R9
GOTO BW1
ENDCODE IMMEDIATE
; IMMEDIATE
[THEN]
- [UNDEFINED] DO
- [IF]
+ [UNDEFINED] DO [IF]
HDNCODE XDO
MOV #$8000,R9
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] I
- [IF]
+ [UNDEFINED] I [IF]
CODE I
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] J
- [IF]
+ [UNDEFINED] J [IF]
CODE J
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] UNLOOP
- [IF]
+ [UNDEFINED] UNLOOP [IF]
CODE UNLOOP
ADD #4,R1
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] LEAVE
- [IF]
+ [UNDEFINED] LEAVE [IF]
CODE LEAVE
- MOV &$1DC8,R10
+ MOV &$1DC0,R10
MOV #UNLOOP,0(R10)
- MOV #$40B2,2(R10)
- ADD #6,&$1DC8
+ MOV #$409C,2(R10)
+ ADD #6,&$1DC0
ADD #2,&$1C00
ADD #4,R10
MOV &$1C00,R9
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] AND
- [IF]
+ [UNDEFINED] AND [IF]
CODE AND
AND @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] OR
- [IF]
+ [UNDEFINED] OR [IF]
CODE OR
BIS @R15+,R14
AND #-1,R14
ENDCODE
[THEN]
- [UNDEFINED] 1+
- [IF]
+ [UNDEFINED] 1+ [IF]
CODE 1+
ADD #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] 1-
- [IF]
+ [UNDEFINED] 1- [IF]
CODE 1-
SUB #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] INVERT
- [IF]
+ [UNDEFINED] INVERT [IF]
CODE INVERT
XOR #-1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] NEGATE
- [IF]
+ [UNDEFINED] NEGATE [IF]
CODE NEGATE
XOR #-1,R14
ADD #1,R14
ENDCODE
[THEN]
- [UNDEFINED] ABS
- [IF]
+ [UNDEFINED] ABS [IF]
CODE ABS
CMP #0,R14
0>= IF
ENDCODE
[THEN]
- [UNDEFINED] LSHIFT
- [IF]
+ [UNDEFINED] LSHIFT [IF]
CODE LSHIFT
MOV @R15+,R10
AND #$1F,R14
ENDCODE
[THEN]
- [UNDEFINED] RSHIFT
- [IF]
+ [UNDEFINED] RSHIFT [IF]
CODE RSHIFT
MOV @R15+,R10
AND #$1F,R14
ENDCODE
[THEN]
- [UNDEFINED] MAX
- [IF]
-
+ [UNDEFINED] MAX [IF]
CODE MAX
CMP @R15,R14
S< ?GOTO FW1
ENDCODE
[THEN]
- [UNDEFINED] 2*
- [IF]
+ [UNDEFINED] 2* [IF]
CODE 2*
ADD R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] 2/
- [IF]
+ [UNDEFINED] 2/ [IF]
CODE 2/
RRA R14
MOV @R13+,R0
MOV @R13+,R0
ENDCODE
- $180E 1 TSTBIT
+ $180E 8 TSTBIT
+
RST_RET
- [IF]
- CODE UM*
- MOV @R15,&$4C0
-BW1 MOV R14,&$4C8
- MOV &$4E4,0(R15)
- MOV &$4E6,R14
- MOV @R13+,R0
- ENDCODE
+ [IF] ; MSP430FRxxxx subfamily with hardware_MPY
- CODE M*
- MOV @R15,&$4C2
- GOTO BW1
- ENDCODE
+ [UNDEFINED] UM* [IF]
+ CODE UM*
+ MOV @R15,&$4C0
+BW1 MOV R14,&$4C8
+ MOV &$4E4,0(R15)
+ MOV &$4E6,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
- [ELSE] ; MSP430FRxxxx with hardware_MPY
[UNDEFINED] M* [IF]
- CODE M*
- MOV @R15,R12
- CMP #0,R12
- S< IF
- XOR #-1,0(R15)
- ADD #1,0(R15)
- THEN
- XOR R14,R12
- CMP #0,R14
- S< IF
- XOR #-1,R14
- ADD #1,R14
- THEN
- PUSHM #2,R13
- LO2HI
- UM*
- HI2LO
- POPM #2,R13
- CMP #0,R12
- S< IF
- XOR #-1,0(R15)
- XOR #-1,R14
- ADD #1,0(R15)
- ADDC #0,R14
- THEN
- MOV @R13+,R0
- ENDCODE
+ CODE M*
+ MOV @R15,&$4C2
+ GOTO BW1
+ ENDCODE
[THEN]
- [THEN] ; endof hardware_MPY
+ [ELSE] ; MSP430FR413x without hardware_MPY
+
+ [UNDEFINED] M* [IF]
+ CODE M*
+ MOV @R15,R12
+ CMP #0,R12
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ THEN
+ XOR R14,R12
+ CMP #0,R14
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ PUSHM #2,R13
+ LO2HI
+ UM*
+ HI2LO
+ POPM #2,R13
+ CMP #0,R12
+ S< IF
+ XOR #-1,0(R15)
+ XOR #-1,R14
+ ADD #1,0(R15)
+ ADDC #0,R14
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+ [THEN] ; endof hardware_MPY
[UNDEFINED] UM/MOD
[IF]
CODE UM/MOD
PUSH #DROP
- MOV #$403E,R0
+ MOV #$4028,R0
ENDCODE
[THEN]
-
-
- $180E @ 0< ; test the switch: $8000 / SYMETRIC DIVISION
+ $180E @ 0< ; test the switch: FLOORED/SYMETRIC DIVISION
[IF]
- [UNDEFINED] FM/MOD
- [IF]
+ [UNDEFINED] FM/MOD [IF]
CODE FM/MOD
MOV R14,R12
MOV @R15,R11
ADDC #0,0(R15)
THEN
PUSHM #2,R12
- CALL #$403E
+ CALL #$4028
MOV @R15+,R14
POPM #2,R12
CMP #0,R11
ENDCODE
[THEN]
[ELSE]
- [UNDEFINED] SM/REM
- [IF]
+ [UNDEFINED] SM/REM [IF]
CODE SM/REM
MOV R14,R12
MOV @R15,R11
ADDC #0,0(R15)
THEN
PUSHM #2,R12
- CALL #$403E
+ CALL #$4028
MOV @R15+,R14
POPM #2,R12
CMP #0,R11
[THEN]
[THEN]
- [UNDEFINED] *
- [IF]
+ [UNDEFINED] * [IF]
: *
M* DROP
;
[THEN]
- [UNDEFINED] /MOD
- [IF]
+ [UNDEFINED] /MOD [IF]
: /MOD
>R DUP 0< R>
- [ $180E @ 0< ]
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
;
[THEN]
- [UNDEFINED] /
- [IF]
+ [UNDEFINED] / [IF]
: /
>R DUP 0< R>
- [ $180E @ 0< ]
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
NIP
;
[THEN]
- [UNDEFINED] MOD
- [IF]
+ [UNDEFINED] MOD [IF]
: MOD
>R DUP 0< R>
- [ $180E @ 0< ]
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
DROP
;
[THEN]
- [UNDEFINED] */MOD
- [IF]
+ [UNDEFINED] */MOD [IF]
: */MOD
>R M* R>
- [ $180E @ 0< ]
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
;
[THEN]
- [UNDEFINED] */
- [IF]
+ [UNDEFINED] */ [IF]
: */
>R M* R>
- [ $180E @ 0< ]
- [IF] FM/MOD
- [ELSE] SM/REM
- [THEN]
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
NIP
;
[THEN]
- [UNDEFINED] ROT
- [IF]
+ [UNDEFINED] ROT [IF]
CODE ROT
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] R@
- [IF]
+ [UNDEFINED] R@ [IF]
CODE R@
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] TUCK
- [IF]
+ [UNDEFINED] TUCK [IF]
: TUCK SWAP OVER ;
[THEN]
- [UNDEFINED] 2@
- [IF]
+ [UNDEFINED] 2@ [IF]
CODE 2@
SUB #2,R15
MOV 2(R14),0(R15)
ENDCODE
[THEN]
- [UNDEFINED] 2!
- [IF]
+ [UNDEFINED] 2! [IF]
CODE 2!
MOV @R15+,0(R14)
MOV @R15+,2(R14)
ENDCODE
[THEN]
- [UNDEFINED] 2DUP
- [IF]
+ [UNDEFINED] 2DUP [IF]
CODE 2DUP
- MOV R14,-2(R15)
MOV @R15,-4(R15)
+ MOV R14,-2(R15)
SUB #4,R15
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] 2DROP
- [IF]
+ [UNDEFINED] 2DROP [IF]
CODE 2DROP
ADD #2,R15
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] 2SWAP
- [IF]
+ [UNDEFINED] 2SWAP [IF]
CODE 2SWAP
MOV @R15,R10
MOV 4(R15),0(R15)
ENDCODE
[THEN]
- [UNDEFINED] 2OVER
- [IF]
+ [UNDEFINED] 2OVER [IF]
CODE 2OVER
SUB #4,R15
MOV R14,2(R15)
ENDCODE
[THEN]
- [UNDEFINED] ALIGNED
- [IF]
+ [UNDEFINED] ALIGNED [IF]
CODE ALIGNED
BIT #1,R14
ADDC #0,R14
ENDCODE
[THEN]
- [UNDEFINED] ALIGN
- [IF]
+ [UNDEFINED] ALIGN [IF]
CODE ALIGN
- BIT #1,&$1DC8
- ADDC #0,&$1DC8
+ BIT #1,&$1DC0
+ ADDC #0,&$1DC0
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] CHARS
- [IF]
+ [UNDEFINED] CHARS [IF]
CODE CHARS
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] CHAR+
- [IF]
+ [UNDEFINED] CHAR+ [IF]
CODE CHAR+
ADD #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] CELLS
- [IF]
+ [UNDEFINED] CELLS [IF]
CODE CELLS
ADD R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] CELL+
- [IF]
+ [UNDEFINED] CELL+ [IF]
CODE CELL+
ADD #2,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] CHAR
- [IF]
+ [UNDEFINED] CHAR [IF]
: CHAR
$20 WORD 1+ C@
;
[THEN]
- [UNDEFINED] [CHAR]
- [IF]
+ [UNDEFINED] [CHAR] [IF]
: [CHAR]
CHAR POSTPONE LITERAL
; IMMEDIATE
[THEN]
- [UNDEFINED] +!
- [IF]
+ [UNDEFINED] +! [IF]
CODE +!
ADD @R15+,0(R14)
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] MOVE
- [IF]
+ [UNDEFINED] MOVE [IF]
CODE MOVE
MOV R14,R10
MOV @R15+,R8
ENDCODE
[THEN]
- [UNDEFINED] FILL
- [IF]
+ [UNDEFINED] FILL [IF]
CODE FILL
MOV @R15+,R9
MOV @R15+,R10
ENDCODE
[THEN]
- [UNDEFINED] HEX
- [IF]
+ [UNDEFINED] HEX [IF]
CODE HEX
- MOV #$10,&$1DBE
+ MOV #$10,&$1DB6
MOV @R13+,R0
ENDCODE
[THEN]
+ [UNDEFINED] DECIMAL [IF]
- [UNDEFINED] DECIMAL
- [IF]
CODE DECIMAL
- MOV #$0A,&$1DBE
+ MOV #$0A,&$1DB6
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] ( ; )
- [IF]
+ [UNDEFINED] ( [IF]
: (
')' WORD DROP
; IMMEDIATE
[THEN]
- [UNDEFINED] .( ; "
- [IF]
+ [UNDEFINED] .( [IF] ; "
CODE .( ; "
- MOV #0,&$1DC0
- COLON
+ PUSH R13
+ MOV #0,&$1DB8
+ LO2HI
')' WORD
COUNT TYPE
HI2LO
- MOV #$20,&$1DC0
+ MOV #$20,&$1DB8
MOV @R1+,R13
MOV @R13+,R0
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] >BODY
- [IF]
+ [UNDEFINED] >BODY [IF]
CODE >BODY
ADD #4,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] EXECUTE
- [IF]
+ [UNDEFINED] EXECUTE [IF]
CODE EXECUTE
PUSH R14
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] EVALUATE
- [IF]
+ [UNDEFINED] EVALUATE [IF]
+ CODENNM
+ MOV @R1+,&$1DBE
+ MOV @R1+,&$1DBC
+ MOV @R1+,&$1DBA
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+
CODE EVALUATE
- MOV #$1DC2,R9
+ MOV #$1DBA,R9
MOV @R9+,R12
MOV @R9+,R11
MOV @R9+,R10
PUSHM #4,R13
- LO2HI
- [ ' \ 8 + , ]
- HI2LO
- MOV @R1+,&$1DC6
- MOV @R1+,&$1DC4
- MOV @R1+,&$1DC2
- MOV @R1+,R13
- MOV @R13+,R0
+ MOV R0,R13
+ ADD #8,R13
+ MOV #\+$08,R0
+ MOV #0,R3
ENDCODE
+ ,
+
[THEN]
- [UNDEFINED] RECURSE
- [IF]
+ [UNDEFINED] RECURSE [IF]
CODE RECURSE
- MOV &$1DC8,R9
- MOV &$1DB8,0(R9)
- ADD #2,&$1DC8
+ MOV &$1DC0,R9
+ MOV &$1DDC,0(R9)
+ ADD #2,&$1DC0
MOV @R13+,R0
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] SOURCE
- [IF]
+ [UNDEFINED] SOURCE [IF]
CODE SOURCE
SUB #4,R15
MOV R14,2(R15)
- MOV &$1DC2,R14
- MOV &$1DC4,0(R15)
+ MOV &$1DBA,R14
+ MOV &$1DBC,0(R15)
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] VARIABLE
- [IF]
+ [UNDEFINED] VARIABLE [IF]
: VARIABLE
CREATE
HI2LO
ENDCODE
[THEN]
- [UNDEFINED] CONSTANT
- [IF]
+ [UNDEFINED] CONSTANT [IF]
: CONSTANT
CREATE
HI2LO
ENDCODE
[THEN]
- [UNDEFINED] STATE
- [IF]
- $1DBC CONSTANT STATE
+ [UNDEFINED] STATE [IF]
+ $1DB4 CONSTANT STATE
[THEN]
- [UNDEFINED] BASE
- [IF]
- $1DBE CONSTANT BASE
+ [UNDEFINED] BASE [IF]
+ $1DB6 CONSTANT BASE
[THEN]
- [UNDEFINED] >IN
- [IF]
- $1DC6 CONSTANT >IN
+ [UNDEFINED] >IN [IF]
+ $1DBE CONSTANT >IN
[THEN]
- [UNDEFINED] PAD
- [IF]
+ [UNDEFINED] PAD [IF]
$1CE4 CONSTANT PAD
[THEN]
- [UNDEFINED] BL
- [IF]
+ [UNDEFINED] BL [IF]
$20 CONSTANT BL
[THEN]
- [UNDEFINED] SPACE
- [IF]
+ [UNDEFINED] SPACE [IF]
: SPACE
$20 EMIT ;
[THEN]
- [UNDEFINED] SPACES
- [IF]
+ [UNDEFINED] SPACES [IF]
: SPACES
BEGIN
?DUP
;
[THEN]
- [UNDEFINED] DEFER
- [IF]
+ [UNDEFINED] DEFER [IF]
: DEFER
CREATE
HI2LO
MOV #$4030,-4(R10)
- MOV #$40B4,-2(R10)
+ MOV #$409E,-2(R10)
MOV @R1+,R13
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] CR
- [IF]
-
+ [UNDEFINED] CR [IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
; IS CR
[THEN]
- [UNDEFINED] TO
- [IF]
+ [UNDEFINED] TO [IF]
CODE TO
BIS #$200,R2
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] VALUE
- [IF]
+ [UNDEFINED] VALUE [IF]
: VALUE
CREATE ,
DOES>
MOV @R1+,R13
BIT #$200,R2
0= IF
- MOV @R14,R14
- MOV @R13+,R0
+ MOV #@,R0
THEN
BIC #$200,R2
MOV #!,R0
ENDCODE
[THEN]
- [UNDEFINED] CASE
- [IF]
+ [UNDEFINED] CASE [IF]
- : CASE 0
+ : CASE
+ 0
; IMMEDIATE
: OF
- 1+
- >R
+ 1+
+ >R
POSTPONE OVER POSTPONE =
- POSTPONE IF
- POSTPONE DROP
- R>
+ POSTPONE IF
+ POSTPONE DROP
+ R>
; IMMEDIATE
: ENDOF
- >R
+ >R
POSTPONE ELSE
- R>
+ R>
; IMMEDIATE
: ENDCASE
RST_SET
+ [THEN]
+
ECHO
-; CORE_ANS.4th for MSP_EXP430FR5994 is loaded
+; CORE_ANS.4th for MSP_EXP430FR5994 is loaded
0<> IF MOV #0,R14 THEN
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
- ABORT" build FastForth with DOUBLE_INPUT addon !"
+ ABORT" FastForth V4.0 please!"
+ ABORT" build FastForth with DOUBLE_INPUT addon!"
RST_RET
;
; -----------------------------------------------------
; DOUBLE.4th for MSP_EXP430FR5994
; -----------------------------------------------------
+ [DEFINED] {DOUBLE}
+ [IF] {DOUBLE} [THEN]
+ [UNDEFINED] {DOUBLE} [IF]
MARKER {DOUBLE}
- [UNDEFINED] >R
- [IF]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] >R [IF]
CODE >R
PUSH R14
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] R>
- [IF]
+ [UNDEFINED] R> [IF]
CODE R>
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] 0<
- [IF]
+ [UNDEFINED] 0< [IF]
CODE 0<
ADD R14,R14
SUBC R14,R14
ENDCODE
[THEN]
- [UNDEFINED] DROP
- [IF]
+ [UNDEFINED] DROP [IF]
CODE DROP
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] DUP
- [IF]
+ [UNDEFINED] DUP [IF]
CODE DUP
BW1 SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] NIP
- [IF]
+ [UNDEFINED] NIP [IF]
CODE NIP
ADD #2,R15
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] UM/MOD
- [IF]
+ [UNDEFINED] UM/MOD [IF]
CODE UM/MOD
PUSH #DROP
- MOV #$403E,R0
+ MOV #$4028,R0
ENDCODE
[THEN]
- $180E @ 0< ; test the switch: $8000 / SYMETRIC DIVISION
- [IF] ; $8000 DIVISION
- [UNDEFINED] FM/MOD
+ $180E @ 0< ; test the switch: FLOORED/SYMETRIC DIVISION
[IF]
- CODE FM/MOD
- MOV R14,R12
- MOV @R15,R11
- CMP #0,R14
- S< IF
- XOR #-1,R14
- ADD #1,R14
- THEN
- CMP #0,0(R15)
- S< IF
- XOR #-1,2(R15)
- XOR #-1,0(R15)
- ADD #1,2(R15)
- ADDC #0,0(R15)
- THEN
- PUSHM #3,R13
- LO2HI
- UM/MOD
- HI2LO
- POPM #3,R13
- CMP #0,R11
- S< IF
- XOR #-1,0(R15)
- ADD #1,0(R15)
- THEN
- XOR R12,R11
- CMP #0,R11
- S< IF
- XOR #-1,R14
- ADD #1,R14
- THEN
-
- CMP #0,0(R15)
- 0<> IF
- CMP #1,R14
+ [UNDEFINED] FM/MOD [IF]
+ CODE FM/MOD
+ MOV R14,R12
+ MOV @R15,R11
+ CMP #0,R14
S< IF
- ADD R12,0(R15)
- SUB #1,R14
+ XOR #-1,R14
+ ADD #1,R14
THEN
- THEN
- MOV @R13+,R0
- ENDCODE
- [THEN]
+ CMP #0,0(R15)
+ S< IF
+ XOR #-1,2(R15)
+ XOR #-1,0(R15)
+ ADD #1,2(R15)
+ ADDC #0,0(R15)
+ THEN
+ PUSHM #3,R13
+ LO2HI
+ UM/MOD
+ HI2LO
+ POPM #3,R13
+ CMP #0,R11
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ THEN
+ XOR R12,R11
+ CMP #0,R11
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+
+ CMP #0,0(R15)
+ 0<> IF
+ CMP #1,R14
+ S< IF
+ ADD R12,0(R15)
+ SUB #1,R14
+ THEN
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
- [ELSE] ; SYMETRIC DIVISION
- [UNDEFINED] SM/REM
- [IF]
- CODE SM/REM
- MOV R14,R12
- MOV @R15,R11
- CMP #0,R14
- S< IF
- XOR #-1,R14
- ADD #1,R14
- THEN
- CMP #0,0(R15)
- S< IF
- XOR #-1,2(R15)
- XOR #-1,0(R15)
- ADD #1,2(R15)
- ADDC #0,0(R15)
- THEN
- PUSHM #3,R13
- LO2HI
- UM/MOD
- HI2LO
- POPM #3,R13
- CMP #0,R11
- S< IF
- XOR #-1,0(R15)
- ADD #1,0(R15)
- THEN
- XOR R12,R11
- CMP #0,R11
- S< IF
- XOR #-1,R14
- ADD #1,R14
- THEN
- MOV @R13+,R0
- ENDCODE
- [THEN]
+ [ELSE]
+ [UNDEFINED] SM/REM [IF]
+ CODE SM/REM
+ MOV R14,R12
+ MOV @R15,R11
+ CMP #0,R14
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ CMP #0,0(R15)
+ S< IF
+ XOR #-1,2(R15)
+ XOR #-1,0(R15)
+ ADD #1,2(R15)
+ ADDC #0,0(R15)
+ THEN
+ PUSHM #3,R13
+ LO2HI
+ UM/MOD
+ HI2LO
+ POPM #3,R13
+ CMP #0,R11
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ THEN
+ XOR R12,R11
+ CMP #0,R11
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
[THEN]
- [UNDEFINED] /
- [IF]
+ [UNDEFINED] / [IF]
: /
>R DUP 0< R>
- [ $180E @ 0< ] [IF]
- FM/MOD
- [ELSE]
- SM/REM
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
[THEN]
NIP
;
[THEN]
- [UNDEFINED] @
- [IF]
- CODE @
- MOV @R14,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] !
- [IF]
- CODE !
- MOV @R15+,0(R14)
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] C@
- [IF]
+ [UNDEFINED] C@ [IF]
CODE C@
MOV.B @R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] SWAP
- [IF]
+ [UNDEFINED] SWAP [IF]
CODE SWAP
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] OVER
- [IF]
+ [UNDEFINED] OVER [IF]
CODE OVER
MOV R14,-2(R15)
MOV @R15,R14
ENDCODE
[THEN]
- [UNDEFINED] ROT
- [IF]
+ [UNDEFINED] ROT [IF]
CODE ROT
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] -
- [IF]
+ [UNDEFINED] - [IF]
CODE -
SUB @R15+,R14
XOR #-1,R14
ENDCODE
[THEN]
- [UNDEFINED] <
- [IF]
+ [UNDEFINED] < [IF]
CODE <
SUB @R15+,R14
S< ?GOTO FW1
ENDCODE
[THEN]
- [UNDEFINED] IF
- [IF]
+ [UNDEFINED] IF [IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] ELSE
- [IF]
+ [UNDEFINED] ELSE [IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] TO
- [IF]
+ [UNDEFINED] TO [IF]
CODE TO
BIS #$200,R2
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] DOES>
- [IF]
+ [UNDEFINED] DOES> [IF]
CODE DOES>
- MOV &$1DB8,R10
+ MOV &$1DDC,R10
MOV #$1285,0(R10)
MOV R13,2(R10)
MOV @R1+,R13
ENDCODE
[THEN]
- [UNDEFINED] SPACES
- [IF]
+ [UNDEFINED] SPACES [IF]
CODE SPACES
CMP #0,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] 2@
- [IF]
+ [UNDEFINED] 2@ [IF]
CODE 2@
SUB #2,R15
MOV 2(R14),0(R15)
ENDCODE
[THEN]
- [UNDEFINED] 2!
- [IF]
+ [UNDEFINED] 2! [IF]
CODE 2!
MOV @R15+,0(R14)
MOV @R15+,2(R14)
ENDCODE
[THEN]
- [UNDEFINED] 2DUP
- [IF]
+ [UNDEFINED] 2DUP [IF]
CODE 2DUP
SUB #4,R15
MOV R14,2(R15)
ENDCODE
[THEN]
- [UNDEFINED] 2DROP
- [IF]
+ [UNDEFINED] 2DROP [IF]
CODE 2DROP
ADD #2,R15
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] 2SWAP
- [IF]
+ [UNDEFINED] 2SWAP [IF]
CODE 2SWAP
MOV @R15,R10
MOV 4(R15),0(R15)
ENDCODE
[THEN]
- [UNDEFINED] 2OVER
- [IF]
+ [UNDEFINED] 2OVER [IF]
CODE 2OVER
SUB #4,R15
MOV R14,2(R15)
ENDCODE
[THEN]
- [UNDEFINED] 2>R
- [IF]
+ [UNDEFINED] 2>R [IF]
CODE 2>R
PUSH @R15+
PUSH R14
ENDCODE
[THEN]
- [UNDEFINED] 2R@
- [IF]
+ [UNDEFINED] 2R@ [IF]
CODE 2R@
SUB #4,R15
MOV R14,2(R15)
ENDCODE
[THEN]
- [UNDEFINED] 2R>
- [IF]
+ [UNDEFINED] 2R> [IF]
CODE 2R>
SUB #4,R15
MOV R14,2(R15)
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
- [UNDEFINED] D.
- [IF]
+; ===============================================
+; DOUBLE word set
+; ===============================================
+
+ [UNDEFINED] D. [IF]
CODE D.
MOV R14,R12
- MOV #U.+10,R0
+ MOV #U.+$0A,R0
ENDCODE
[THEN]
- [UNDEFINED] 2ROT
- [IF]
+ [UNDEFINED] 2ROT [IF]
CODE 2ROT
MOV 8(R15),R9
MOV 6(R15),R8
ENDCODE
[THEN]
- [UNDEFINED] D>S
- [IF]
+ [UNDEFINED] D>S [IF]
CODE D>S
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] D0=
- [IF]
+ [UNDEFINED] D0= [IF]
+
CODE D0=
+ ADD #2,R15
CMP #0,R14
MOV #0,R14
0= IF
- CMP #0,0(R15)
+ CMP #0,-2(R15)
0= IF
- MOV #-1,R14
+BW1 MOV #-1,R14
THEN
THEN
- ADD #2,R15
+BW2 AND #-1,R14
MOV @R13+,R0
ENDCODE
- [THEN]
- [UNDEFINED] D0<
- [IF]
CODE D0<
+ ADD #2,R15
CMP #0,R14
MOV #0,R14
- S< IF
- MOV #-1,R14
- THEN
- ADD #2,R15
- AND #-1,R14
- MOV @R13+,R0
+ S< ?GOTO BW1
+ GOTO BW2
ENDCODE
- [THEN]
- [UNDEFINED] D=
- [IF]
CODE D=
- CMP R14,2(R15)
- MOV #0,R14
- 0= IF
- CMP @R15,4(R15)
- 0= IF
- MOV #-1,R14
- THEN
- THEN
ADD #6,R15
- MOV @R13+,R0
+ CMP R14,-4(R15)
+ MOV #0,R14
+ 0<> ?GOTO BW2
+ CMP -6(R15),-2(R15)
+ 0= ?GOTO BW1
+ GOTO BW2
ENDCODE
- [THEN]
- [UNDEFINED] D<
- [IF]
CODE D<
- CMP R14,2(R15)
+ ADD #6,R15
+ CMP R14,-4(R15)
MOV #0,R14
S< IF
- MOV #-1,R14
+BW1 MOV #-1,R14
THEN
- 0= IF
- CMP @R15,4(R15)
- U< IF
- MOV #-1,R14
- THEN
- THEN
- ADD #6,R15
- MOV @R13+,R0
+BW3 0<> ?GOTO BW2
+ CMP -6(R15),-2(R15)
+ U>= ?GOTO BW2
+ U< ?GOTO BW1
ENDCODE
- [THEN]
- [UNDEFINED] DU<
- [IF]
CODE DU<
- CMP R14,2(R15)
- MOV #0,R14
- U< IF
- MOV #-1,R14
- THEN
- 0= IF
- CMP @R15,4(R15)
- U< IF
- MOV #-1,R14
- THEN
- THEN
ADD #6,R15
- MOV @R13+,R0
+ CMP R14,-4(R15)
+ MOV #0,R14
+ U>= ?GOTO BW3
+ U< ?GOTO BW1
ENDCODE
[THEN]
- [UNDEFINED] D+
- [IF]
+ [UNDEFINED] D+ [IF]
CODE D+
BW1 ADD @R15+,2(R15)
ADDC @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] D-
- [IF]
+ [UNDEFINED] D- [IF]
CODE D-
SUB @R15+,2(R15)
SUBC R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] DNEGATE
- [IF]
+ [UNDEFINED] DNEGATE [IF]
CODE DNEGATE
- XOR #-1,0(R15)
+BW1 XOR #-1,0(R15)
XOR #-1,R14
ADD #1,0(R15)
ADDC #0,R14
MOV @R13+,R0
ENDCODE
- [THEN]
- [UNDEFINED] DABS
- [IF]
CODE DABS
CMP #0,R14
- 0>= IF
- MOV @R13+,R0
- THEN
- MOV #DNEGATE,R0
+ 0< ?GOTO BW1
+ MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] D2/
- [IF]
+ [UNDEFINED] D2/ [IF]
CODE D2/
RRA R14
RRC 0(R15)
ENDCODE
[THEN]
- [UNDEFINED] D2*
- [IF]
+ [UNDEFINED] D2* [IF]
CODE D2*
ADD @R15,0(R15)
ADDC R14,R14
ENDCODE
[THEN]
- [UNDEFINED] DMAX
- [IF]
+ [UNDEFINED] DMAX [IF]
: DMAX
2OVER 2OVER
D< IF
;
[THEN]
- [UNDEFINED] DMIN
- [IF]
+ [UNDEFINED] DMIN [IF]
: DMIN
2OVER 2OVER
D< IF
;
[THEN]
- RST_SET
+ [UNDEFINED] M*/ [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
+ RST_SET
- $180E 1 TSTBIT
+ CODE TSTBIT
+ MOV @R15+,R9
+ AND @R9,R14
+ MOV @R13+,R0
+ ENDCODE
- RST_RET
+ $180E 8 TSTBIT
- [IF] ; MSP430FRxxxx with hardware_MPY
-
- [UNDEFINED] M*/
- [IF]
- CODE M*/
- MOV 4(R15),&$4D4
- MOV 2(R15),&$4D6
- MOV @R15+,&$4C8
- MOV R14,R11
- MOV R0,R0
- MOV &$4E4,R12
- MOV &$4E6,R14
- MOV &$4E8,R10
- MOV #0,R6
- CMP #0,R10
- S< IF
- XOR #-1,R12
- XOR #-1,R14
- XOR #-1,R10
- ADD #1,R12
- ADDC #0,R14
- ADDC #0,R10
- MOV #-1,R6
- THEN
+ RST_RET
- [ELSE] ; no hardware multiplier
- [UNDEFINED] M*/
- [IF]
- CODE M*/
- MOV #0,R6
- CMP #0,2(R15)
- S< IF
- XOR #-1,4(R15)
- XOR #-1,2(R15)
- ADD #1,4(R15)
- ADDC #0,2(R15)
- MOV #-1,R6
- THEN
- CMP #0,0(R15)
- S< IF
- XOR #-1,0(R15)
- ADD #1,0(R15)
- XOR #-1,R6
- THEN
- MOV 4(R15),R8
- MOV 2(R15),R11
- MOV @R15+,R12
- MOV #0,R5
- MOV #0,2(R15)
- MOV #0,0(R15)
- MOV #0,R10
- MOV #1,R9
- BEGIN BIT R9,R12
- 0<> IF ADD R8,2(R15)
- ADDC R11,0(R15)
- ADDC R5,R10
- THEN ADD R8,R8
- ADDC R11,R11
- ADDC R5,R5
- ADD R9,R9
- U>= UNTIL
- MOV R14,R11
- MOV @R15,R14
- MOV 2(R15),R12
- [THEN]
+ [IF] ; MSP430FRxxxx with hardware_MPY
+
+ CODE M*/
+ MOV 4(R15),&$4D4
+ MOV 2(R15),&$4D6
+ MOV @R15+,&$4C8
+ MOV R14,R11
+ MOV R0,R0
+ MOV &$4E4,R12
+ MOV &$4E6,R14
+ MOV &$4E8,R10
+ MOV #0,R6
+ CMP #0,R10
+ S< IF
+ XOR #-1,R12
+ XOR #-1,R14
+ XOR #-1,R10
+ ADD #1,R12
+ ADDC #0,R14
+ ADDC #0,R10
+ MOV #-1,R6
+ THEN
+
+ [ELSE] ; no hardware multiplier
+
+ CODE M*/
+ MOV #0,R6
+ CMP #0,2(R15)
+ S< IF
+ XOR #-1,4(R15)
+ XOR #-1,2(R15)
+ ADD #1,4(R15)
+ ADDC #0,2(R15)
+ MOV #-1,R6
+ THEN
+ CMP #0,0(R15)
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ XOR #-1,R6
+ THEN
+ MOV 4(R15),R8
+ MOV 2(R15),R11
+ MOV @R15+,R12
+ MOV #0,R5
+ MOV #0,2(R15)
+ MOV #0,0(R15)
+ MOV #0,R10
+ MOV #1,R9
+ BEGIN BIT R9,R12
+ 0<> IF ADD R8,2(R15)
+ ADDC R11,0(R15)
+ ADDC R5,R10
+ THEN ADD R8,R8
+ ADDC R11,R11
+ ADDC R5,R5
+ ADD R9,R9
+ U>= UNTIL
+ MOV R14,R11
+ MOV @R15,R14
+ MOV 2(R15),R12
[THEN] ; endcase of software/hardware_MPY
CMP #0,R10
0= IF
MOV R14,R10
- CALL #$4050
+ CALL #$403A
ELSE
- CALL #$4058
+ CALL #$4042
THEN
MOV @R15+,0(R15)
CMP #0,R6
THEN
THEN
THEN
- MOV #$40B6,R5
- MOV #$40C4,R6
+ MOV #$40A0,R5
+ MOV #$40AE,R6
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] 2VARIABLE
- [IF]
+ [UNDEFINED] 2VARIABLE [IF]
: 2VARIABLE
CREATE
HI2LO
- ADD #4,&$1DC8
+ ADD #4,&$1DC0
MOV @R1+,R13
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] 2CONSTANT
- [IF]
+ [UNDEFINED] 2CONSTANT [IF]
: 2CONSTANT
CREATE
, ,
;
[THEN]
- [UNDEFINED] 2VALUE
- [IF]
+ [UNDEFINED] 2VALUE [IF]
: 2VALUE
CREATE , ,
DOES>
[THEN]
- [UNDEFINED] 2LITERAL
- [IF]
- CODE 2LITERAL
- BIS #$200,R2
- MOV #LITERAL,R0
- ENDCODE IMMEDIATE
+ [UNDEFINED] 2LITERAL [IF]
+ CODE 2LITERAL
+ BIS #$200,R2
+ MOV #LITERAL,R0
+ ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] D.R
- [IF]
+ [UNDEFINED] D.R [IF]
: D.R
>R SWAP OVER DABS <# #S ROT SIGN #>
R> OVER - SPACES TYPE
RST_SET
+ [THEN]
+
+; -------------------------------
; Complement to pass DOUBLE TESTS
+; -------------------------------
- [UNDEFINED] VARIABLE
- [IF]
+ [UNDEFINED] SWAP [IF]
+ CODE SWAP
+ MOV @R15,R10
+ MOV R14,0(R15)
+ MOV R10,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] VARIABLE [IF]
: VARIABLE
CREATE
HI2LO
ENDCODE
[THEN]
- [UNDEFINED] CONSTANT
- [IF]
+ [UNDEFINED] CONSTANT [IF]
: CONSTANT
CREATE
HI2LO
ENDCODE
[THEN]
- [UNDEFINED] CELLS
- [IF]
+ [UNDEFINED] CELLS [IF]
CODE CELLS
ADD R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] DEPTH
- [IF]
+ [UNDEFINED] DEPTH [IF]
CODE DEPTH
MOV R14,-2(R15)
MOV #$1C80,R14
ENDCODE
[THEN]
- [UNDEFINED] DO
- [IF]
+ [UNDEFINED] IF [IF]
+ CODE IF
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
+ ADD #2,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ CODE THEN
+ MOV &$1DC0,0(R14)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] ELSE [IF]
+ CODE ELSE
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
+ MOV R10,0(R14)
+ SUB #2,R10
+ MOV R10,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] DO [IF]
HDNCODE XDO
MOV #$8000,R9
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] I
- [IF]
+ [UNDEFINED] I [IF]
CODE I
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
CODE +
ADD @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] =
- [IF]
+ [UNDEFINED] = [IF]
CODE =
SUB @R15+,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] 0=
- [IF]
+ [UNDEFINED] 0= [IF]
CODE 0=
SUB #1,R14
SUBC R14,R14
ENDCODE
[THEN]
- [UNDEFINED] SOURCE
- [IF]
+ [UNDEFINED] SOURCE [IF]
CODE SOURCE
SUB #4,R15
MOV R14,2(R15)
- MOV &$1DC2,R14
- MOV &$1DC4,0(R15)
+ MOV &$1DBA,R14
+ MOV &$1DBC,0(R15)
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] >IN
- [IF]
- $1DC6 CONSTANT >IN
+ [UNDEFINED] >IN [IF]
+ $1DBE CONSTANT >IN
[THEN]
- [UNDEFINED] 1+
- [IF]
+ [UNDEFINED] 1+ [IF]
CODE 1+
ADD #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] CHAR
- [IF]
+ [UNDEFINED] CHAR [IF]
: CHAR
$20 WORD 1+ C@
;
[THEN]
- [UNDEFINED] [CHAR]
- [IF]
+ [UNDEFINED] [CHAR] [IF]
: [CHAR]
CHAR POSTPONE LITERAL
; IMMEDIATE
[THEN]
- [UNDEFINED] 2/
- [IF]
+ [UNDEFINED] 2/ [IF]
CODE 2/
RRA R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] INVERT
- [IF]
+ [UNDEFINED] INVERT [IF]
CODE INVERT
XOR #-1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] RSHIFT
- [IF]
+ [UNDEFINED] RSHIFT [IF]
CODE RSHIFT
MOV @R15+,R10
AND #$1F,R14
ENDCODE
[THEN]
- [UNDEFINED] S>D
- [IF]
+ [UNDEFINED] S>D [IF]
: S>D
DUP 0<
;
[THEN]
- [UNDEFINED] 1-
- [IF]
+ [UNDEFINED] 1- [IF]
CODE 1-
SUB #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] NEGATE
- [IF]
+ [UNDEFINED] NEGATE [IF]
CODE NEGATE
XOR #-1,R14
ADD #1,R14
ENDCODE
[THEN]
- [UNDEFINED] HERE
- [IF]
+ [UNDEFINED] HERE [IF]
CODE HERE
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE
[THEN]
- [UNDEFINED] CHARS
- [IF]
+ [UNDEFINED] CHARS [IF]
CODE CHARS
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] MOVE
- [IF]
+ [UNDEFINED] MOVE [IF]
CODE MOVE
MOV R14,R10
MOV @R15+,R8
ENDCODE
[THEN]
- [UNDEFINED] DECIMAL
- [IF]
+ [UNDEFINED] DECIMAL [IF]
CODE DECIMAL
- MOV #$0A,&$1DBE
+ MOV #$0A,&$1DB6
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] BASE
- [IF]
- $1DBE CONSTANT BASE
+ [UNDEFINED] BASE [IF]
+ $1DB6 CONSTANT BASE
[THEN]
- [UNDEFINED] ( ; )
- [IF]
+ [UNDEFINED] ( [IF]
: (
')' WORD DROP
; IMMEDIATE
[THEN]
- [UNDEFINED] .( ; "
- [IF]
+ [UNDEFINED] .( [IF] ; "
CODE .( ; "
- MOV #0,&$1DC0
+ MOV #0,&$1DB8
COLON
')' WORD
COUNT TYPE
- $20 $1DC0 !
+ $20 $1DB8 !
; IMMEDIATE
[THEN]
- [UNDEFINED] CR
- [IF]
- DEFER CR
+ [UNDEFINED] CR [IF]
+ CODE CR
+ MOV #$409E,R0
+ ENDCODE
:NONAME
$0D EMIT $0A EMIT
ECHO
+; ----------------------------------------------------------------------------
TESTING interpreter and compiler reading double numbers, with/without prefixes
T{ 1. -> 1 0 }T
T{ $-12AbCdEf. -> -313249263. }T
T{ %10010110. -> 150. }T
T{ %-10010110. -> -150. }T
+; Check BASE is unchanged
T{ BASE @ OLD-DBASE @ = -> TRUE }T
+; Repeat in Hex mode
16 OLD-DBASE ! 16 BASE !
T{ #12346789. -> BC65A5. }T
T{ #-12346789. -> -BC65A5. }T
T{ $-12AbCdEf. -> -12ABCDef. }T
T{ %10010110. -> 96. }T
T{ %-10010110. -> -96. }T
+; Check BASE is unchanged
T{ BASE @ OLD-DBASE @ = -> TRUE }T
DECIMAL
+; Check number prefixes in compile mode
T{ : dnmp #8327. $-2cbe. %011010111. ; dnmp -> 8327. -11454. 215. }T
+; ----------------------------------------------------------------------------
TESTING 2CONSTANT
T{ 1 2 2CONSTANT 2C1 -> }T
T{ 4 5 2CONSTANT 2C3 IMMEDIATE 2C3 -> 4 5 }T
T{ : CD6 2C3 2LITERAL ; CD6 -> 4 5 }T
+; ----------------------------------------------------------------------------
+; Some 2CONSTANTs for the following tests
1SD MAX-INTD 2CONSTANT MAX-2INT
0 MIN-INTD 2CONSTANT MIN-2INT
MAX-2INT 2/ 2CONSTANT HI-2INT
MIN-2INT 2/ 2CONSTANT LO-2INT
+; ----------------------------------------------------------------------------
TESTING DNEGATE
T{ 0. DNEGATE -> 0. }T
T{ MAX-2INT DNEGATE -> MIN-2INT SWAP 1+ SWAP }T
T{ MIN-2INT SWAP 1+ SWAP DNEGATE -> MAX-2INT }T
+; ----------------------------------------------------------------------------
TESTING D+ with small integers
T{ 0. 5. D+ -> 5. }T
T{ HI-2INT MIN-2INT D+ 1. D+ -> LO-2INT }T
T{ LO-2INT 2DUP D+ -> MIN-2INT }T
+; ----------------------------------------------------------------------------
TESTING D- with small integers
T{ 0. 5. D- -> -5. }T
T{ MIN-2INT MIN-2INT D- -> 0. }T
T{ MIN-2INT LO-2INT D- -> LO-2INT }T
+; ----------------------------------------------------------------------------
TESTING D0< D0=
T{ 0. D0< -> FALSE }T
T{ -1. D0= -> FALSE }T
T{ 0 MIN-INTD D0= -> FALSE }T
+; ----------------------------------------------------------------------------
TESTING D2* D2/
T{ 0. D2* -> 0. D2* }T
T{ -1. D2/ -> -1. }T
T{ MIN-2INT D2/ -> LO-2INT }T
+; ----------------------------------------------------------------------------
TESTING D< D=
T{ 0. 1. D< -> TRUE }T
T{ MIN-2INT LO-2INT D= -> FALSE }T
T{ MIN-2INT MAX-2INT D= -> FALSE }T
+; ----------------------------------------------------------------------------
TESTING 2LITERAL 2VARIABLE
T{ : CD3 [ MAX-2INT ] 2LITERAL ; -> }T
T{ : CD7 2V3 [ 2@ ] 2LITERAL ; CD7 -> 5 6 }T
T{ : CD8 [ 6 7 ] 2V3 [ 2! ] ; 2V3 2@ -> 6 7 }T
+; ----------------------------------------------------------------------------
TESTING DMAX DMIN
T{ 1. 2. DMAX -> 2. }T
T{ MIN-2INT 1. DMIN -> MIN-2INT }T
T{ MIN-2INT -1. DMIN -> MIN-2INT }T
+; ----------------------------------------------------------------------------
TESTING D>S DABS
T{ 1234 0 D>S -> 1234 }T
T{ MAX-2INT DABS -> MAX-2INT }T
T{ MIN-2INT 1. D+ DABS -> MAX-2INT }T
+; ----------------------------------------------------------------------------
TESTING M+ M*/
T{ HI-2INT 1 M+ -> HI-2INT 1. D+ }T
T{ MIN-2INT 1 M+ -> MIN-2INT 1. D+ }T
T{ LO-2INT -1 M+ -> LO-2INT -1. D+ }T
+; To correct the result if the division is floored, only used when
+; necessary i.e. negative quotient and remainder <> 0
: ?$8000 [ -3 2 / -2 = ] LITERAL IF 1. D- THEN ;
T{ MAX-2INT LO-2INT NIP DUP NEGATE M*/ -> MAX-2INT DNEGATE }T
T{ MIN-2INT MAX-INTD DUP M*/ -> MIN-2INT }T
+; ----------------------------------------------------------------------------
TESTING D. D.R
+; Create some large double numbers
MAX-2INT 71 73 M*/ 2CONSTANT DBL1
MIN-2INT 73 79 M*/ 2CONSTANT DBL2
;
T{ DOUBLEOUTPUT -> }T
-
+; ----------------------------------------------------------------------------
TESTING 2ROT DU< (Double Number extension words)
T{ 1. 2. 3. 2ROT -> 2. 3. 1. }T
T{ MIN-2INT MAX-2INT DU< -> FALSE }T
T{ MIN-2INT LO-2INT DU< -> TRUE }T
+; ----------------------------------------------------------------------------
TESTING 2VALUE
T{ 1111 2222 2VALUE 2VAL -> }T
T{ : TO-2VAL TO 2VAL ; 5555 6666 TO-2VAL -> }T
T{ 2VAL -> 5555 6666 }T
-
CR .( End of Double-Number word tests) CR
SUB #2,R15
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET
;
ABORT_FF_SPECS
- [UNDEFINED] DUP
- [IF]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need, from CORE_ANS
+; ------------------------------------------------------------------
+
+ [UNDEFINED] DUP [IF]
CODE DUP
BW1 SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] OVER
- [IF]
+ [UNDEFINED] OVER [IF]
CODE OVER
MOV R14,-2(R15)
MOV @R15,R14
ENDCODE
[THEN]
- [UNDEFINED] DROP
- [IF]
+ [UNDEFINED] DROP [IF]
CODE DROP
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] SWAP
- [IF]
+ [UNDEFINED] SWAP [IF]
CODE SWAP
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] ROT
- [IF]
+ [UNDEFINED] ROT [IF]
CODE ROT
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] >R
- [IF]
+ [UNDEFINED] >R [IF]
CODE >R
PUSH R14
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] R>
- [IF]
+ [UNDEFINED] R> [IF]
CODE R>
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] 0<
- [IF]
+ [UNDEFINED] 0< [IF]
CODE 0<
ADD R14,R14
SUBC R14,R14
ENDCODE
[THEN]
- [UNDEFINED] =
- [IF]
+ [UNDEFINED] = [IF]
CODE =
SUB @R15+,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] U<
- [IF]
+ [UNDEFINED] U< [IF]
CODE U<
SUB @R15+,R14
U< ?GOTO FW1
ENDCODE
[THEN]
- [UNDEFINED] IF
- [IF]
+ [UNDEFINED] IF [IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] ELSE
- [IF]
+ [UNDEFINED] ELSE [IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] BEGIN
- [IF]
+ [UNDEFINED] BEGIN [IF]
+
CODE BEGIN
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE IMMEDIATE
CODE UNTIL
- MOV #$40AC,R9
-BW1 ADD #4,&$1DC8
- MOV &$1DC8,R10
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
MOV @R15+,R14
ENDCODE IMMEDIATE
CODE AGAIN
- MOV #$40B2,R9
+ MOV #$409C,R9
GOTO BW1
ENDCODE IMMEDIATE
- [THEN]
- [UNDEFINED] WHILE
- [IF]
: WHILE
POSTPONE IF SWAP
; IMMEDIATE
- [THEN]
- [UNDEFINED] REPEAT
- [IF]
: REPEAT
POSTPONE AGAIN POSTPONE THEN
; IMMEDIATE
[THEN]
- [UNDEFINED] DO
- [IF]
+ [UNDEFINED] DO [IF]
+
HDNCODE XDO
MOV #$8000,R9
SUB @R15+,R9
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] I
- [IF]
+ [UNDEFINED] I [IF]
CODE I
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] HERE
- [IF]
+ [UNDEFINED] HERE [IF]
CODE HERE
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE
[THEN]
- [UNDEFINED] C@
- [IF]
+ [UNDEFINED] C@ [IF]
CODE C@
MOV.B @R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] SPACES
- [IF]
+ [UNDEFINED] SPACES [IF]
CODE SPACES
CMP #0,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] 1+
- [IF]
+ [UNDEFINED] 1+ [IF]
CODE 1+
ADD #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
CODE +
ADD @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] -
- [IF]
+ [UNDEFINED] - [IF]
CODE -
SUB @R15+,R14
XOR #-1,R14
ENDCODE
[THEN]
- [UNDEFINED] 2*
- [IF]
+ [UNDEFINED] 2* [IF]
CODE 2*
ADD R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] 2/
- [IF]
+ [UNDEFINED] 2/ [IF]
CODE 2/
RRA R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] UM/MOD
- [IF]
+ [UNDEFINED] UM/MOD [IF]
CODE UM/MOD
PUSH #DROP
- MOV #$403E,R0
+ MOV #$4028,R0
ENDCODE
[THEN]
- [UNDEFINED] MOVE
- [IF]
+ [UNDEFINED] MOVE [IF]
CODE MOVE
MOV R14,R10
MOV @R15+,R8
ENDCODE
[THEN]
- [UNDEFINED] CR
- [IF]
+ [UNDEFINED] CR [IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
[THEN]
- : WORDS
- $1CE4
- $180C @ 2*
- MOVE
- BEGIN
- 0 DUP
- $180C @ 2* 0
- DO
- DUP I $1CE4 + @
- U< IF
- DROP DROP
- I DUP $1CE4 + @
- THEN
- 2 +LOOP
- ?DUP
- WHILE
- DUP
- 2 - @
- ROT
- $1CE4 +
- !
- COUNT 2/
- DUP >R TYPE
- $10 R> - SPACES
- REPEAT
- DROP
- ;
+ [UNDEFINED] CASE [IF]
- [UNDEFINED] CASE
- [IF]
: CASE
0
; IMMEDIATE
: OF
- 1+
- >R
+ 1+
+ >R
POSTPONE OVER
POSTPONE =
- POSTPONE IF
- POSTPONE DROP
- R>
+ POSTPONE IF
+ POSTPONE DROP
+ R>
; IMMEDIATE
: ENDOF
- >R
+ >R
POSTPONE ELSE
- R>
+ R>
; IMMEDIATE
: ENDCASE
; IMMEDIATE
[THEN]
- [UNDEFINED] S_
- [IF]
- CODE S_
- MOV #0,&$1DC0
- COLON
- $401E ,
- $20 WORD
- HI2LO
- MOV.B @R14,R14
- ADD #1,R14
- BIT #1,R14
- ADDC R14,&$1DC8
- MOV @R15+,R14
- MOV @R1+,R13
- MOV #$20,&$1DC0
- MOV @R13+,R0
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ [UNDEFINED] S? [IF]
+ CODE S?
+ MOV #S"+10,R0
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] ESC
- [IF]
+ [UNDEFINED] ESC [IF]
CODE ESC
- CMP #0,&$1DBC
+ CMP #0,&$1DB4
0= IF MOV @R13+,R0
THEN
COLON
$1B
POSTPONE LITERAL
POSTPONE EMIT
- POSTPONE S_
+ $20
+ POSTPONE S?
POSTPONE TYPE
; IMMEDIATE
[THEN]
- [DEFINED] FORTH
- [IF]
+ [DEFINED] FORTH [IF]
CODE BODY>SQNFA
SUB #2,R15
SUB #4,R14
RST_RET
ECHO
ESC [8;42;80t
-
ESC [7m
CR ." FastForth V"
$180A @
HERE
$1A04 @
CASE
-
$8102 OF ." 5738," $C200 ENDOF
$8103 OF ." 5739," $C200 ENDOF
$810D OF ." 5986," $4400 ENDOF
$8240 OF ." 2433," $C400 ENDOF
$825D OF ." 5972," $4400 ENDOF
$82A1 OF ." 5994," $4000 ENDOF
- $82A6 OF ." 5962," $4000 ENDOF
$830C OF ." 2355," $8000 ENDOF
$830D OF ." 2353," $C000 ENDOF
$831E OF ." 2155," $8000 ENDOF
$833D OF ." 2533," $C400 ENDOF
ABORT" xxxx <-- unrecognized device!"
ENDCASE
+ ." DTC"
['] ['] DUP @ $1284 =
- IF ." DTC=1," DROP
+ IF ." =1," DROP
ELSE 2 + @ $1284 =
- IF ." DTC=2,"
- ELSE ." DTC=3,"
+ IF ." =2,"
+ ELSE ." =3,"
THEN
THEN
$20 EMIT
THEN ." MHz, "
- U. ." bytes"
ESC [0m
-
CR
." /COUNTED-STRING = 255" CR
." /HOLD = 34" CR
." /PAD = 84" CR
." ADDRESS-UNIT-BITS = 16" CR
+ [DEFINED] {CORE_ANS}
+ [IF]
." FLOORED DIVISION = "
$180E @
0< IF ." true"
ELSE ." false"
THEN CR
+ [THEN]
." MAX-CHAR = 255" CR
." MAX-N = 32767" CR
." MAX-U = 65535" CR
." MAX-UD = 4294967295" CR
." STACK-CELLS = 48" CR
." RETURN-STACK-CELLS= 48" CR
- ." Definitions are forced to UPPERCASE." CR
-
+ ." Definitions are always UPPERCASE." CR
CR ESC [7m ." Kernel add-ons" ESC [0m CR
$180E @
2* DUP 0< IF ." 32.768kHz LF XTAL" CR THEN
THEN
." with TI's syntax" CR
THEN DROP
- [DEFINED] FORTH [IF] ." word-set management" CR
+ [DEFINED] FORTH [IF] ." word-set management" CR
[THEN]
[DEFINED] LOAD" [IF] ." SD_CARD Load" CR
[THEN]
[THEN]
[DEFINED] READ" [IF] ." SD_CARD Read/Write" CR
[THEN]
-
- $1DCA
+ $1DC2
BEGIN
@ ?DUP
WHILE
- DUP $180C @ 2* -
CR ESC [7m
+ DUP $180C @ 2* -
[DEFINED] FORTH
[IF] DUP BODY>SQNFA
[ELSE] OVER @
[THEN]
TYPE ." word-set"
ESC [0m CR
- WORDS CR
+ $1CE4
+ $180C @ 2*
+ MOVE
+ BEGIN
+ 0 DUP
+ $180C @ 2* 0
+ DO
+ DUP I $1CE4 + @
+ U< IF
+ DROP DROP
+ I DUP $1CE4 + @
+ THEN
+ 2 +LOOP
+ ?DUP
+ WHILE
+ DUP
+ 2 - @
+ ROT
+ $1CE4 +
+ !
+ COUNT 2/
+ DUP >R TYPE
+ $10 R> - SPACES
+ REPEAT
+ DROP
+ CR
REPEAT
-
+ DROP
CR ESC [7m ." EXTENSIONS" ESC [0m
- [DEFINED] {CORE_ANS} [IF] CR ." core ANS94"
+ [DEFINED] {CORE_ANS} [IF] CR ." CORE ANS94"
[THEN]
- [DEFINED] {DOUBLE} [IF] CR ." DOUBLE word set"
+ [DEFINED] {DOUBLE} [IF] CR ." DOUBLE numbers set"
[THEN]
[DEFINED] {UTILITY} [IF] CR ." UTILITY"
[THEN]
[DEFINED] {UARTI2CS} [IF] CR ." UART to I2C_FastForth bridge"
[THEN]
CR
- 0 SYS
+ SYS
;
SPECS
+; -----------------------------------------------------
+; FIXPOINT.4th for MSP_EXP430FR5994
+; -----------------------------------------------------
+
CODE ABORT_FIXPOINT
SUB #4,R15
MOV R14,2(R15)
0<> IF MOV #0,R14 THEN
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" build FastForth with Q15.16_INPUT addon !"
RST_RET
$1B EMIT $63 EMIT
ABORT_FIXPOINT
-; -----------------------------------------------------
-; FIXPOINT.4th for MSP_EXP430FR5994
-; -----------------------------------------------------
-
+ [DEFINED] {FIXPOINT}
+ [IF] {FIXPOINT}
+ [THEN]
+ [UNDEFINED] {FIXPOINT}
+ [IF]
MARKER {FIXPOINT}
- [UNDEFINED] +
- [IF]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] + [IF]
CODE +
ADD @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] R>
- [IF]
+ [UNDEFINED] R> [IF]
CODE R>
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] =
- [IF]
+ [UNDEFINED] = [IF]
CODE =
SUB @R15+,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] U<
- [IF]
+ [UNDEFINED] U< [IF]
CODE U<
SUB @R15+,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] DABS
- [IF]
+ [UNDEFINED] DABS [IF]
CODE DABS
AND #-1,R14
S< IF
ENDCODE
[THEN]
- [UNDEFINED] HOLDS
- [IF]
+ [UNDEFINED] HOLDS [IF]
CODE HOLDS
MOV @R15+,R9
BW3 ADD R14,R9
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ [UNDEFINED] F+ [IF]
CODE F+
ADD @R15+,2(R15)
ADDC @R15+,R14
MOV @R13+,R0
ENDCODE
+ [THEN]
+ [UNDEFINED] F- [IF]
CODE F-
SUB @R15+,2(R15)
SUBC R14,0(R15)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
+ [THEN]
$1A00 4 + @ $81F3 U<
- $81EF $1A00 4 + @ U<
+ $81EF $1A00 4 + @ U<
= [IF] ; MSP430FR413x subfamily without hardware_MPY
+ [UNDEFINED] UDM* [IF]
CODE UDM*
PUSH R13
PUSHM #4,R7
MOV #1,R9
MOV #0,R8
BEGIN
- CMP #0,R9
+ CMP #0,R9
0<> IF
BIT R9,R10
ELSE
MOV @R1+,R13
MOV @R13+,R0
ENDCODE
+ [THEN]
+ [UNDEFINED] F* [IF]
CODE F*
MOV 2(R15),R12
XOR R14,R12
THEN
MOV @R13+,R0
ENDCODE
+ [THEN]
+ [UNDEFINED] F#S [IF]
CODE F#S
MOV @R15,R12
MOV #0,R11
MOV 2(R15),0(R15)
MOV R14,2(R15)
BEGIN
- MOV &$1DBE,R14
+ MOV &$1DB6,R14
LO2HI
UM*
HI2LO
MOV #$1D90,R9
GOTO BW3
ENDCODE
+ [THEN]
[ELSE] ; hardware multiplier
+ [UNDEFINED] F* [IF]
CODE F*
MOV 4(R15),&$4D4
MOV 2(R15),&$4D6
MOV &$4E8,R14
MOV @R13+,R0
ENDCODE
+ [THEN]
-
+ [UNDEFINED] F#S [IF]
CODE F#S
MOV 2(R15),R9
MOV @R15,2(R15)
MOV #0,R12
BEGIN
MOV @R15,&$4C0
- MOV &$1DBE,&$4C8
+ MOV &$1DB6,&$4C8
MOV &$4E4,0(R15)
MOV &$4E6,R14
CMP #10,R14
MOV #$1D90,R9
GOTO BW3
ENDCODE
+ [THEN]
[THEN] ; end of hardware/software multiplier
+ [UNDEFINED] F/ [IF]
CODE F/
MOV R14,R8
MOV @R15+,R10
XOR #-1,R8
ADD #1,R10
ADDC #0,R8
- THEN
+ THEN
AND #-1,R9
S< IF
XOR #-1,R11
XOR #-1,R9
ADD #1,R11
ADDC #0,R9
- THEN
+ THEN
MOV R9,R7
MOV R11,R9
MOV #0,R11
MOV R12,0(R15)
MOV @R13+,R0
ENDCODE
+ [THEN]
+ [UNDEFINED] F. [IF]
CODE F.
MOV R14,R12
MOV #4,R11
- MOV &$1DBE,R10
+ MOV &$1DB6,R10
CMP #$0A,R10
0= IF
ADD #1,R11
R> SIGN #>
TYPE $20 EMIT
;
+ [THEN]
+ [UNDEFINED] S>F [IF]
CODE S>F
SUB #2,R15
MOV #0,0(R15)
MOV @R13+,R0
ENDCODE
+ [THEN]
RST_SET
+ [THEN]
+
; -----------------------
; complement (volatile) for tests below
; -----------------------
- [UNDEFINED] !
- [IF]
- CODE !
- MOV @R15+,0(R14)
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] DOES>
- [IF]
- CODE DOES>
- MOV &$1DB8,R10
- MOV #$1285,0(R10)
- MOV R13,2(R10)
- MOV @R1+,R13
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] CONSTANT
- [IF]
- : CONSTANT
+ [UNDEFINED] CONSTANT [IF]
+ : CONSTANT
CREATE
HI2LO
MOV R14,-2(R10)
ENDCODE
[THEN]
- [UNDEFINED] 2CONSTANT
- [IF]
+ [UNDEFINED] 2CONSTANT [IF]
: 2CONSTANT
CREATE , ,
DOES>
ENDCODE
[THEN]
- [UNDEFINED] D.
- [IF]
+ [UNDEFINED] D. [IF]
CODE D.
- MOV #U.,R10
- ADD #10,R10
- MOV R10,R0
+ MOV #U.+10,R0
ENDCODE
[THEN]
- [UNDEFINED] BASE
- [IF]
- $1DBE CONSTANT BASE
+ [UNDEFINED] BASE [IF]
+ $1DB6 CONSTANT BASE
[THEN]
ECHO
-; -----------------------
-; (volatile) tests for FIXPOINT.asm|FIXPOINT.4th for MSP_EXP430FR5994
-; -----------------------
+; ------------------------------------------------
+; (volatile) tests for FIXPOINT.asm | FIXPOINT.4th
+; ------------------------------------------------
3,14159 2CONSTANT PI
PI -1,0 F* 2CONSTANT -PI
-PI D. ; D. is not appropriate -->
+PI D. ; D. is not appropriate -->
-PI D. ; D. is not appropriate -->
-PI F. ; F. is a good choice! --->
+PI F. ; F. is a good choice! --->
-PI F. ; F. is a good choice! --->
-$10 BASE ! PI F.
+$10 BASE ! PI F.
-PI F.
-%10 BASE ! PI F.
+%10 BASE ! PI F.
-PI F.
-#10 BASE ! PI F.
+#10 BASE ! PI F.
-PI F.
- PI 2,0 F* F.
- PI -2,0 F* F.
--PI 2,0 F* F.
--PI -2,0 F* F.
+ PI 2,0 F* F.
+ PI -2,0 F* F.
+-PI 2,0 F* F.
+-PI -2,0 F* F.
- PI 2,0 F/ F.
- PI -2,0 F/ F.
--PI 2,0 F/ F.
--PI -2,0 F/ F.
+ PI 2,0 F/ F.
+ PI -2,0 F/ F.
+-PI 2,0 F/ F.
+-PI -2,0 F/ F.
32768,0 1,0 F* F. ; overflow! -->
32768,0 1,0 F/ F. ; overflow! -->
-32768,0 -1,0 F* F. ; overflow! -->
-32768,0 -1,0 F/ F. ; overflow! -->
-32767,99999 1,0 F* F.
-32767,99999 1,0 F/ F.
-32767,99999 2,0 F/ F.
-32767,99999 4,0 F/ F.
-32767,99999 8,0 F/ F.
-32767,99999 16,0 F/ F.
-
--32768,0 -2,0 F/ F.
--32768,0 -4,0 F/ F.
--32768,0 -8,0 F/ F.
--32768,0 -16,0 F/ F.
--32768,0 -32,0 F/ F.
--32768,0 -64,0 F/ F.
-
--3276,80 -1,0 F/ F.
--327,680 -1,0 F/ F.
--32,7680 -1,0 F/ F.
--3,27680 -1,0 F/ F.
--0,32768 -1,0 F/ F.
+32767,99999 1,0 F* F.
+32767,99999 1,0 F/ F.
+32767,99999 2,0 F/ F.
+32767,99999 4,0 F/ F.
+32767,99999 8,0 F/ F.
+32767,99999 16,0 F/ F.
+
+-32768,0 -2,0 F/ F.
+-32768,0 -4,0 F/ F.
+-32768,0 -8,0 F/ F.
+-32768,0 -16,0 F/ F.
+-32768,0 -32,0 F/ F.
+-32768,0 -64,0 F/ F.
+
+-3276,80 -1,0 F/ F.
+-327,680 -1,0 F/ F.
+-32,7680 -1,0 F/ F.
+-3,27680 -1,0 F/ F.
+-0,32768 -1,0 F/ F.
; SQRT(32768)^2 = 32768
- 181,01933598375 181,01933598375 F* F.
+ 181,01933598375 181,01933598375 F* F.
181,01933598375 -181,01933598375 F* F.
-181,01933598375 181,01933598375 F* F.
--181,01933598375 -181,01933598375 F* F.
-
+-181,01933598375 -181,01933598375 F* F.
+
RST_RET
+++ /dev/null
-
-; -----------
-; SD_TEST.4th for MSP_EXP430FR5994
-; -----------
-
- CODE ABORT_SD_TEST
- SUB #2,R15
- MOV R14,0(R15)
- MOV &$180A,R14
- SUB #309,R14
- COLON
- $0D EMIT
- ABORT" FastForth V3.9 please!"
- [UNDEFINED] WRITE
- [IF]
- 1 ABORT" no SD_CARD_READ_WRITE addon!"
- [THEN]
- RST_RET
- ;
-
- ABORT_SD_TEST
-
- MARKER {SD_TEST}
-
- [UNDEFINED] EXIT
- [IF]
- CODE EXIT
- MOV @R1+,R13
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] SWAP
- [IF]
- CODE SWAP
- MOV @R15,R10
- MOV R14,0(R15)
- MOV R10,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] >BODY
- [IF]
- CODE >BODY
- ADD #4,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] 0=
- [IF]
- CODE 0=
- SUB #1,R14
- SUBC R14,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] IF
- [IF]
- CODE IF
- SUB #2,R15
- MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
- ADD #2,R14
- MOV @R13+,R0
- ENDCODE IMMEDIATE
-
- CODE THEN
- MOV &$1DC8,0(R14)
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE IMMEDIATE
- [THEN]
-
- [UNDEFINED] ELSE
- [IF]
- CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
- MOV R10,0(R14)
- SUB #2,R10
- MOV R10,R14
- MOV @R13+,R0
- ENDCODE IMMEDIATE
- [THEN]
-
- [UNDEFINED] BEGIN
- [IF]
- CODE BEGIN
- MOV #$4032,R0
- ENDCODE IMMEDIATE
-
- CODE UNTIL
- MOV #$40AC,R9
-BW1 ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV R9,-4(R10)
- MOV R14,-2(R10)
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE IMMEDIATE
-
- CODE AGAIN
- MOV #$40B2,R9
- GOTO BW1
- ENDCODE IMMEDIATE
-
- : WHILE
- POSTPONE IF SWAP
- ; IMMEDIATE
-
- : REPEAT
- POSTPONE AGAIN POSTPONE THEN
- ; IMMEDIATE
- [THEN]
-
- [UNDEFINED] DO
- [IF]
- HDNCODE XDO
- MOV #$8000,R9
- SUB @R15+,R9
- MOV R14,R8
- ADD R9,R8
- PUSHM #2,R9
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
-
- CODE DO
- SUB #2,R15
- MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
- MOV #XDO,-2(R14)
- ADD #2,&$1C00
- MOV &$1C00,R10
- MOV #0,0(R10)
- MOV @R13+,R0
- ENDCODE IMMEDIATE
-
- HDNCODE XLOOP
- ADD #1,0(R1)
-BW1 BIT #$100,R2
- 0= IF
- MOV @R13,R13
- MOV @R13+,R0
- THEN
- ADD #4,R1
- ADD #2,R13
- MOV @R13+,R0
- ENDCODE
-
- CODE LOOP
- MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV R9,-4(R10)
- MOV R14,-2(R10)
- BEGIN
- MOV &$1C00,R14
- SUB #2,&$1C00
- MOV @R14,R14
- CMP #0,R14
- 0<> WHILE
- MOV R10,0(R14)
- REPEAT
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE IMMEDIATE
-
- HDNCODE XPLOO
- ADD R14,0(R1)
- MOV @R15+,R14
- GOTO BW1
- ENDCODE
-
- CODE +LOOP
- MOV #XPLOO,R9
- GOTO BW2
- ENDCODE IMMEDIATE
- [THEN]
-
- [UNDEFINED] I
- [IF]
- CODE I
- SUB #2,R15
- MOV R14,0(R15)
- MOV @R1,R14
- SUB 2(R1),R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] +
- [IF]
- CODE +
- ADD @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] -
- [IF]
- CODE -
- SUB @R15+,R14
- XOR #-1,R14
- ADD #1,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] MAX
- [IF]
- CODE MAX
- CMP @R15,R14
- S< ?GOTO FW1
-BW1 ADD #2,R15
- MOV @R13+,R0
- ENDCODE
-
- CODE MIN
- CMP @R15,R14
- S< ?GOTO BW1
-FW1 MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] C@
- [IF]
- CODE C@
- MOV.B @R14,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] SPACE
- [IF]
- : SPACE
- $20 EMIT ;
- [THEN]
-
- [UNDEFINED] SPACES
- [IF]
- CODE SPACES
- CMP #0,R14
- 0<> IF
- PUSH R13
- BEGIN
- LO2HI
- $20 EMIT
- HI2LO
- SUB #2,R13
- SUB #1,R14
- 0= UNTIL
- MOV @R1+,R13
- THEN
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] DUP
- [IF]
- CODE DUP
-BW1 SUB #2,R15
- MOV R14,0(R15)
- MOV @R13+,R0
- ENDCODE
-
- CODE ?DUP
- CMP #0,R14
- 0<> ?GOTO BW1
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] OVER
- [IF]
- CODE OVER
- MOV R14,-2(R15)
- MOV @R15,R14
- SUB #2,R15
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] >R
- [IF]
- CODE >R
- PUSH R14
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] R>
- [IF]
- CODE R>
- SUB #2,R15
- MOV R14,0(R15)
- MOV @R1+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] CONSTANT
- [IF]
- : CONSTANT
- CREATE
- HI2LO
- MOV R14,-2(R10)
- MOV @R15+,R14
- MOV @R1+,R13
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] STATE
- [IF]
- $1DBC CONSTANT STATE
- [THEN]
-
- [UNDEFINED] CR
- [IF]
-
- CODE CR
- MOV #$40B4,R0
- ENDCODE
-
- :NONAME
- $0D EMIT $0A EMIT
- ; IS CR
- [THEN]
-
- [UNDEFINED] U.R
- [IF]
- : U.R
- >R <# 0 # #S #>
- R> OVER - 0 MAX SPACES TYPE
- ;
- [THEN]
-
- [UNDEFINED] BASE
- [IF]
- $1DBE CONSTANT BASE
- [THEN]
-
- [UNDEFINED] DUMP
- [IF]
- CODE DUMP
- PUSH R13
- PUSH &BASE
- MOV #$10,&BASE
- ADD @R15,R14
- LO2HI
- SWAP
- DO
- I 4 U.R SPACE
- I 8 + I
- DO I C@ 3 U.R LOOP
- SPACE
- I $10 + I 8 +
- DO I C@ 3 U.R LOOP
- SPACE SPACE
- I $10 + I
- DO I C@ $7E MIN $20 MAX EMIT LOOP
- CR
- $10 +LOOP
- R> BASE !
- ;
- [THEN]
-
- [UNDEFINED] HERE
- [IF]
- CODE HERE
- MOV #BEGIN,R0
- ENDCODE
- [THEN]
-
-
- [UNDEFINED] DROP
- [IF]
- CODE DROP
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] 1+
- [IF]
- CODE 1+
- ADD #1,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] =
- [IF]
- CODE =
- SUB @R15+,R14
- 0<> IF
- AND #0,R14
- MOV @R13+,R0
- THEN
- XOR #-1,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] CASE
- [IF]
- : CASE
- 0
- ; IMMEDIATE
-
- : OF
- 1+
- >R
- POSTPONE OVER
- POSTPONE =
- POSTPONE IF
- POSTPONE DROP
- R>
- ; IMMEDIATE
-
- : ENDOF
- >R
- POSTPONE ELSE
- R>
- ; IMMEDIATE
-
- : ENDCASE
- POSTPONE DROP
- 0 DO
- POSTPONE THEN
- LOOP
- ; IMMEDIATE
- [THEN]
-
- CODE SD_EMIT
- CMP #$200,&$201E
- U>= IF
- CALL &WRITE+2
- THEN
- MOV &$201E,R8
- MOV.B R14,$1E00(R8)
- ADD #1,&$201E
- MOV @R15+,R14
- MOV @R13+,R0
- ENDCODE
-
- : DOESWRITE
- ['] SD_EMIT IS EMIT
- $4000 HERE OVER - DUMP
- ['] EMIT >BODY IS EMIT
- CLOSE
- ;
-
- : SD_TEST
- ECHO
- $0D EMIT CR
- ." ----------" CR
- ." Bootloader" CR
- ." ----------" CR
- ." ? Fast Forth Specifs" CR
- ." 0 Set date and time" CR
- ." 1 Load {UTILITY} words" CR
- ." 2 Load {SD_TOOLS} words" CR
- ." 3 Load {CORE_COMP} words" CR
- ." 4 Load ANS core tests" CR
- ." 5 Load a source file to make 10k program" CR
- ." 6 Read it only (47k)" CR
- ." 7 write FORTH dump in YOURFILE.TXT" CR
- ." 8 append FORTH dump to YOURFILE.TXT" CR
- ." 9 delete YOURFILE.TXT" CR
- ." your choice: "
- KEY DUP EMIT
- {SD_TEST}
- CASE
- '?' OF LOAD" FF_SPECS.4TH" ENDOF
- '0' OF LOAD" RTC.4TH" ENDOF
- '1' OF LOAD" UTILITY.4TH" ENDOF
- '2' OF LOAD" SD_TOOLS.4TH" ENDOF
- '3' OF LOAD" CORE_ANS.4TH" ENDOF
- '4' OF LOAD" CORETEST.4TH" ENDOF
- '5' OF LOAD" PROG10K.4TH" ENDOF
- '6' OF READ" PROG10K.4TH"
- BEGIN READ
- UNTIL ENDOF
- '7' OF WRITE" YOURFILE.TXT"
- DOESWRITE ENDOF
- '8' OF APPEND" YOURFILE.TXT"
- DOESWRITE ENDOF
- '9' OF DEL" YOURFILE.TXT" ENDOF
- ENDCASE
- CR
- ;
-
-SD_TEST
SUB #2,R15
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
- RST_RET
+ ABORT" FastForth V4.0 please!"
;
ABORT_TEST_ASM
- MARKER {TEST_ASM}
+ECHO
+
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] >R
[IF]
ENDCODE
[THEN]
- [UNDEFINED] DEFER
- [IF]
-
- : DEFER
- CREATE
- HI2LO
- MOV #$4030,-4(R10)
- MOV #$40B4,-2(R10)
- MOV @R1+,R13
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
[UNDEFINED] >BODY
[IF]
CODE >BODY
ENDCODE
[THEN]
+ [UNDEFINED] DROP
+ [IF]
+ CODE DROP
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
[UNDEFINED] OVER
[IF]
CODE OVER
ENDCODE
[THEN]
- [UNDEFINED] U.R
- [IF]
- : U.R
- >R <# 0 # #S #>
- R> OVER - 0 MAX SPACES TYPE
- ;
- [THEN]
-
[UNDEFINED] IF
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[IF]
CODE BEGIN
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE IMMEDIATE
CODE UNTIL
- MOV #$40AC,R9
-BW1 ADD #4,&$1DC8
- MOV &$1DC8,R10
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
MOV @R15+,R14
ENDCODE IMMEDIATE
CODE AGAIN
- MOV #$40B2,R9
+ MOV #$409C,R9
GOTO BW1
ENDCODE IMMEDIATE
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
[UNDEFINED] BASE
[IF]
- $1DBE CONSTANT BASE
+ $1DB6 CONSTANT BASE
[THEN]
[UNDEFINED] CR
[IF]
- DEFER CR
+ CODE CR
+ MOV #$409E,R0
+ ENDCODE
:NONAME
$0D EMIT $0A EMIT
; IS CR
[THEN]
+ [UNDEFINED] C,
+ [IF]
+ CODE C,
+ MOV &$1DC0,R10
+ MOV.B R14,0(R10)
+ ADD #1,&$1DC0
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C@
+ [IF]
+ CODE C@
+ MOV.B @R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+; ------------------------------------------------------------------
+; then we download the set of definitions we need (from UTILITY.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] U.R
+ [IF]
+ : U.R
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+ ;
+ [THEN]
+
[UNDEFINED] DUMP
[IF]
CODE DUMP
PUSH R13
PUSH &BASE
- MOV #$10,&$1DBE
+ MOV #$10,&$1DB6
ADD @R15,R14
LO2HI
SWAP
;
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ECHO
CODE TESTPUSHM
BW1
MOV #22222,R8
TESTPOPM ; you should see 11111 3 2 1 0 -->
-
CODE TEST1
MOV &BASE,&BASE
TEST5 ; you should see : 9 8 7 6 5 4 3 2 1 0 -->
-
-[UNDEFINED] C, [IF]
-CODE C,
-MOV &$1DC8,R10
-MOV.B R14,0(R10)
-ADD #1,&$1DC8
-MOV @R15+,R14
-MOV @R13+,R0
-ENDCODE
-[THEN]
-
-[UNDEFINED] C@ [IF]
-CODE C@
-MOV.B @R14,R14
-MOV @R13+,R0
-ENDCODE
-[THEN]
-
: BYTES_TABLE_IDX
CREATE
0 DO I C,
; create a primary DEFERred assembly word
; -----------------------------------------------------------------------
+ CODE TRUC
+ MOV #$409E,R0
+ ENDCODE
-DEFER TRUC ; here, TRUC is a secondary DEFERred word (i.e. without BODY)
-
-
-CODENNM ; does DUP
+ CODENNM
SUB #2,R15
MOV R14,0(R15)
MOV @R13+,R0
-ENDCODE ; leaves its execution address (CFA) on stack
+ ENDCODE ; leaves its execution address (CFA) on stack
-DUP .
+DUP . ; see it -->
-IS TRUC ; TRUC becomes a primary DEFERred word
- ; with its default action (DUP) located at its BODY addresse.
+IS TRUC ; TRUC becomes a primary DEFERred word
+ ; with its default action (DUP) located at its BODY addresse.
-TRUC . ; display R14 value -->
+TRUC . ; display R14 value -->
+' DROP IS TRUC ; TRUC is redirected to DROP
+; TRUC ; The generated error displays stack empty! in reverse video, removes the TRUC definition and restarts the interpretation after the end of the file. And as you see, FastForth is able to display long lines, interesting, doesn't it? -->
' TRUC >BODY IS TRUC ; TRUC is reinitialized with its default action
-
-TRUC . ; display R14 value -->
-
-
-
-
+TRUC . ; display R14 value -->
SUB #2,R15
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET
;
MARKER {RC5TOLCD}
8 ALLOT
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
+
+
+
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] =
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&$4186+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &$4186+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4186+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_SET
MARKER {RC5TOLCD}
8 ALLOT
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] =
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&$4186+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &$4186+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4186+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_SET
MARKER {RC5TOLCD}
8 ALLOT
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] =
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&$4186+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &$4186+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4186+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_SET
MARKER {RC5TOLCD}
8 ALLOT
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] =
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&$4186+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &$4186+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4186+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_SET
MARKER {RC5TOLCD}
8 ALLOT
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] =
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&$4186+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &$4186+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4186+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_SET
MARKER {RC5TOLCD}
8 ALLOT
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] =
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&$4186+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &$4186+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4186+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_SET
MARKER {RC5TOLCD}
8 ALLOT
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] =
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&$4186+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &$4186+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4186+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_SET
MARKER {RC5TOLCD}
8 ALLOT
- [UNDEFINED] TSTBIT
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] =
[IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
+ CODE =
+ SUB @R15+,R14
+ 0<> IF
+ AND #0,R14
+ MOV @R13+,R0
+ THEN
+ XOR #-1,R14
MOV @R13+,R0
ENDCODE
[THEN]
+ [UNDEFINED] IF
+ [IF]
+ CODE IF
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
+ ADD #2,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ CODE THEN
+ MOV &$1DC0,0(R14)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] ELSE
+ [IF]
+ CODE ELSE
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
+ MOV R10,0(R14)
+ SUB #2,R10
+ MOV R10,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+
+ [UNDEFINED] CR
+ [IF]
+ CODE CR
+ MOV #$409E,R0
+ ENDCODE
+
+ :NONAME
+ $0D EMIT $0A EMIT
+ ; IS CR
+ [THEN]
+
+ [UNDEFINED] >BODY
+ [IF]
+ CODE >BODY
+ ADD #4,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ CODE 20_US
+ BEGIN
+ MOV &{RC5TOLCD}+6,R9
+ SUB #2,R9
+ BEGIN
+ MOV #0,R3
+ SUB #1,R9
+ 0= UNTIL
+ MOV #0,R3
+ SUB #1,R14
+ 0= UNTIL
+ MOV @R15+,R14
+ MOV @R1+,R13
+ ENDCODE
+
+ CODE TOP_LCD
+ BIS.B #4,&$243
+ BIT.B #1,&$241
+ 0= IF
+ AND.B #$0F,R14
+ MOV.B R14,&$222
+ BIC.B #4,&$243
+ MOV @R15+,R14
+ MOV @R13+,R0
+ THEN
+ SUB #2,R15
+ MOV R14,0(R15)
+ BIC.B #4,&$243
+ MOV.B &$220,R14
+ AND.B #$0F,R14
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE LCD_WRC
+ BIS.B #2,&$243
+BW1 SUB #2,R15
+ MOV R14,0(R15)
+ RRUM #4,R14
+ BIC.B #1,&$243
+ BIS.B #$0F,&$224
+ COLON
+ TOP_LCD 2 20_US
+ TOP_LCD 2 20_US
+ ;
+
+ CODE LCD_WRF
+ BIC.B #2,&$243
+ GOTO BW1
+ ENDCODE
+
+ : LCD_CLEAR $01 LCD_WRF 100 20_us ;
+ : LCD_HOME $02 LCD_WRF 100 20_us ;
+
+ HDNCODE WDT_INT
+ BIT.B #$20,&$240
+ 0= IF
+ CMP #19,&$3D6
+ U< IF
+ ADD #1,&$3D6
+ THEN
+ ELSE
+ BIT.B #$40,&$240
+ 0= IF
+ CMP #3,&$3D6
+ U>= IF
+ SUB #1,&$3D6
+ THEN
+ THEN
+ THEN
+ RETI
+ ENDCODE
+
+ HDNCODE RC5_INT
+ MOV #1778,R9
+ MOV #14,R10
+ BEGIN
+ MOV #%1011100100,&$380
+ RRUM #1,R9
+ MOV R9,R8
+ RRUM #1,R8
+ ADD R9,R8
+ BEGIN
+ CMP R8,&$390
+ U>= UNTIL
+ BIT.B #4,&$200
+ ADDC R11,R11
+ MOV.B &$200,&$208
+ BIC.B #4,&$20C
+ SUB #1,R10
+ 0<> WHILE
+ ADD R9,R8
+ BEGIN
+ MOV &$390,R9
+ CMP R8,R9
+ U>= ?GOTO FW1
+ BIT.B #4,&$20C
+ 0<> UNTIL
+ REPEAT
+ BIC #$30,&$380
+ RLAM #1,R11
+ MOV.B R11,R9
+ RRUM #2,R9
+ BIT #$4000,R11
+ 0= IF BIS #$40,R9
+ THEN
+ RRUM #3,R11
+ XOR @R1,R11
+ BIT #$400,R11
+ 0= ?GOTO FW2
+ XOR #$400,0(R1)
+ SUB #6,R15
+ MOV R14,4(R15)
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
+ MOV R9,0(R15)
+ MOV #0,R14
+ LO2HI
+ LCD_CLEAR
+ <# # #S #36 HOLD #>
+ ['] LCD_WRC IS EMIT
+ TYPE
+ ['] EMIT >BODY IS EMIT
+ HI2LO
+ MOV @R15+,&$1DB6
+ MOV @R15+,R14
+FW1 BIC #$30,&$380
+FW2 BIC #%1111_1000,0(R1)
+ RETI
+ ENDCODE
+
+ HDNCODE STOP_R2L
+ CMP #WDT_INT,&$FFEA
+ 0= IF
+ BIC.B #4,&$20A
+ BIC.B #4,&$20C
+ MOV #0,&$3C0
+ MOV #0,&$340
+ MOV #0,&$342
+ MOV #{RC5TOLCD},R10
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
+ MOV @R10+,&$FFEA
+ MOV @R10+,&$FFDE
+ THEN
+ MOV @R1+,R0
+ ENDCODE
+
+ CODE STOP
+BW1 CALL #STOP_R2L
+ COLON
+ ECHO
+ ." type START to start RC5toLCD"
+ ;
+
+ HDNCODE INIT_R2L
+ MOV #%10_1101_0100,&$3C0
+ $1800 @ 16000 =
+ [IF]
+ MOV #1,&$3A0
+ MOV #1,&$3E0
+ [THEN]
+ $1800 @ 24000 =
+ [IF]
+ MOV #2,&$3A0
+ MOV #2,&$3E0
+ [THEN]
+ MOV #19,&$3D2
+ MOV #%0110_0000,&$3C6
+ MOV #10,&$3D6
+ BIS.B #$20,&$204
+ BIS.B #$20,&$20A
+ BIS.B #7,&$245
+ BIC.B #7,&$247
+ BIS.B #$0F,&$224
+ BIC.B #$0F,&$226
+ BIS.B #4,&$20A
+ BIC.B #4,&$20C
+ MOV #%01_0001_0100,&$340
+ MOV ##3276,&$352
+ MOV #%10000,&$342
+ CALL &{RC5TOLCD}
+ CMP #$0E,R14
+ 0<> IF
+ CMP #$0A,R14
+ U>= ?GOTO BW1
+ THEN
+ CMP #4,R14
+ 0= ?GOTO BW1
+ LO2HI
+ #1000 20_US
+ %011 TOP_LCD
+ #205 20_US
+ %011 TOP_LCD
+ #5 20_US
+ %011 TOP_LCD
+ #2 20_US
+ %010 TOP_LCD
+ #2 20_US
+ %00101000 LCD_WRF
+ %1000 LCD_WRF
+ LCD_CLEAR
+ %0110 LCD_WRF
+ %1100 LCD_WRF
+ LCD_CLEAR
+ HI2LO
+ MOV @R1+,R0
+ ENDCODE
+
+ CODE START
+ CMP #WDT_INT,&$FFEA
+ 0= IF
+ MOV @R13+,R0
+ THEN
+ MOV #STOP_R2L,&{RC5TOLCD}-2
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
+ MOV &$FFEA,&{RC5TOLCD}+2
+ MOV #WDT_INT,&$FFEA
+ MOV &$FFDE,&{RC5TOLCD}+4
+ MOV #RC5_INT,&$FFDE
+ SUB #6,R15
+ MOV R14,4(R15)
+ MOV &$1800,2(R15)
+ MOV #0,0(R15)
+ MOV #200,R14
+ CALL #$4028
+ MOV @R15,&{RC5TOLCD}+6
+ ADD #4,R15
+ MOV @R15+,R14
+ CALL #INIT_R2L
+ LO2HI
+ ." RC5toLCD is running,"
+ ." Type STOP to quit."
+ HI2LO
+ MOV #ALLOT+$08,R0
+ ENDCODE
+
+RST_SET
+
+ MARKER {RC5TOLCD}
+ 8 ALLOT
+
+
+
+
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
[UNDEFINED] =
[IF]
CODE =
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&$4186+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &$4186+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4186+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_RET
+
SUB #2,R15
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET
;
- [UNDEFINED] TSTBIT
- [IF]
- CODE TSTBIT
- MOV @R15+,R9
- AND @R9,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] =
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE 20_US
BEGIN
MOV &{RC5TOLCD}+6,R9
XOR #$400,0(R1)
SUB #6,R15
MOV R14,4(R15)
- MOV &$1DBE,2(R15)
- MOV #$10,&$1DBE
+ MOV &$1DB6,2(R15)
+ MOV #$10,&$1DB6
MOV R9,0(R15)
MOV #0,R14
LO2HI
TYPE
['] EMIT >BODY IS EMIT
HI2LO
- MOV @R15+,&$1DBE
+ MOV @R15+,&$1DB6
MOV @R15+,R14
FW1 BIC #$30,&$380
FW2 BIC #%1111_1000,0(R1)
MOV #0,&$340
MOV #0,&$342
MOV #{RC5TOLCD},R10
- MOV #$4082,-2(R10)
- $180E $3C00 TSTBIT
- [IF]
- MOV @R10+,&UART_WARM+2
- [ELSE]
- MOV @R10+,&$4180+2
- [THEN]
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183E
MOV @R10+,&$FFEA
MOV @R10+,&$FFDE
THEN
MOV @R13+,R0
THEN
MOV #STOP_R2L,&{RC5TOLCD}-2
- $180E $3C00 TSTBIT
- [IF]
- MOV &UART_WARM+2,&{RC5TOLCD}
- MOV #INIT_R2L,&UART_WARM+2
- [ELSE]
- MOV &$4180+2,&{RC5TOLCD}
- MOV #INIT_R2L,&$4180+2
- [THEN]
+ MOV &$183E,&{RC5TOLCD}
+ MOV #INIT_R2L,&$183E
MOV &$FFEA,&{RC5TOLCD}+2
MOV #WDT_INT,&$FFEA
MOV &$FFDE,&{RC5TOLCD}+4
MOV &$1800,2(R15)
MOV #0,0(R15)
MOV #200,R14
- CALL #$403E
+ CALL #$4028
MOV @R15,&{RC5TOLCD}+6
ADD #4,R15
MOV @R15+,R14
." RC5toLCD is running,"
." Type STOP to quit."
HI2LO
- MOV #ALLOT+$8,R0
+ MOV #ALLOT+$08,R0
ENDCODE
-RST_SET
+RST_SET
+
ECHO
+; --------------------
+; RTC.4th for MSP_EXP430FR5994
+; --------------------
+
CODE ABORT_RTC
SUB #4,R15
MOV R14,2(R15)
0<> IF MOV #0,R14 THEN
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" target without LF_XTAL !"
RST_RET
;
ABORT_RTC
-; --------------------
-; RTC.4th for MSP_EXP430FR5994
-; --------------------
-
-
MARKER {RTC}
- [UNDEFINED] OR
- [IF]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] OR [IF]
CODE OR
BIS @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] C@
- [IF]
+ [UNDEFINED] C@ [IF]
CODE C@
MOV.B @R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] C!
- [IF]
+ [UNDEFINED] C! [IF]
CODE C!
MOV.B @R15+,0(R14)
ADD #1,R15
ENDCODE
[THEN]
- [UNDEFINED] SWAP
- [IF]
+ [UNDEFINED] SWAP [IF]
CODE SWAP
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] OVER
- [IF]
+ [UNDEFINED] OVER [IF]
CODE OVER
MOV R14,-2(R15)
MOV @R15,R14
ENDCODE
[THEN]
- [UNDEFINED] DUP
- [IF]
+ [UNDEFINED] DUP [IF]
CODE DUP
BW1 SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] DROP
- [IF]
+ [UNDEFINED] DROP [IF]
CODE DROP
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] DEPTH
- [IF]
+ [UNDEFINED] DEPTH [IF]
CODE DEPTH
MOV R14,-2(R15)
MOV #$1C80,R14
ENDCODE
[THEN]
- [UNDEFINED] >R
- [IF]
+ [UNDEFINED] >R [IF]
CODE >R
PUSH R14
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] R>
- [IF]
+ [UNDEFINED] R> [IF]
CODE R>
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] 1+
- [IF]
+ [UNDEFINED] 1+ [IF]
CODE 1+
ADD #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] 1-
- [IF]
+ [UNDEFINED] 1- [IF]
CODE 1-
SUB #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] =
- [IF]
+ [UNDEFINED] = [IF]
CODE =
SUB @R15+,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] IF
- [IF]
+ [UNDEFINED] IF [IF]
+
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] ELSE
- [IF]
+ [UNDEFINED] ELSE [IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
+
[THEN]
- [UNDEFINED] DO
- [IF]
+ [UNDEFINED] DO [IF]
+
HDNCODE XDO
MOV #$8000,R9
SUB @R15+,R9
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
MOV #XPLOO,R9
GOTO BW2
ENDCODE IMMEDIATE
+
[THEN]
- [UNDEFINED] BEGIN
- [IF]
+ [UNDEFINED] BEGIN [IF]
CODE BEGIN
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE IMMEDIATE
CODE UNTIL
- MOV #$40AC,R9
-BW1 ADD #4,&$1DC8
- MOV &$1DC8,R10
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
MOV @R15+,R14
ENDCODE IMMEDIATE
CODE AGAIN
- MOV #$40B2,R9
+ MOV #$409C,R9
GOTO BW1
ENDCODE IMMEDIATE
: REPEAT
POSTPONE AGAIN POSTPONE THEN
; IMMEDIATE
+
[THEN]
- [UNDEFINED] CASE
- [IF]
+ [UNDEFINED] CASE [IF]
: CASE
0
; IMMEDIATE
: OF
- 1+
- >R
+ 1+
+ >R
POSTPONE OVER POSTPONE =
- POSTPONE IF
- POSTPONE DROP
- R>
+ POSTPONE IF
+ POSTPONE DROP
+ R>
; IMMEDIATE
: ENDOF
- >R
+ >R
POSTPONE ELSE
- R>
+ R>
; IMMEDIATE
: ENDCASE
; IMMEDIATE
[THEN]
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
CODE +
ADD @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] -
- [IF]
+ [UNDEFINED] - [IF]
CODE -
SUB @R15+,R14
XOR #-1,R14
ENDCODE
[THEN]
- [UNDEFINED] MAX
- [IF]
+ [UNDEFINED] MAX [IF]
CODE MAX
CMP @R15,R14
S< ?GOTO FW1
[THEN]
- [UNDEFINED] 2*
- [IF]
+ [UNDEFINED] 2* [IF]
CODE 2*
ADD R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] UM*
- [IF]
+ [UNDEFINED] UM* [IF]
CODE UM*
MOV @R15,&$4C0
BW1 MOV R14,&$4C8
ENDCODE
[THEN]
- [UNDEFINED] UM/MOD
- [IF]
+ [UNDEFINED] UM/MOD [IF]
CODE UM/MOD
PUSH #DROP
- MOV #$403E,R0
+ MOV #$4028,R0
ENDCODE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
: U*/
>R UM* R> UM/MOD SWAP DROP
;
U/MOD SWAP DROP
;
- [UNDEFINED] SPACES
- [IF]
+ [UNDEFINED] SPACES [IF]
: SPACES
BEGIN
?DUP
." we are on " DATE?
;
- RST_SET
-
- [UNDEFINED] S_
- [IF]
+ [UNDEFINED] S_ [IF]
CODE S_
- MOV #0,&$1DC0
- COLON
- $401E ,
- $20 WORD
- HI2LO
- MOV.B @R14,R14
- ADD #1,R14
- BIT #1,R14
- ADDC R14,&$1DC8
- MOV @R15+,R14
- MOV @R1+,R13
- MOV #$20,&$1DC0
- MOV @R13+,R0
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV #$20,R14
+ MOV #S"+10,R0
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] ESC
- [IF]
+ [UNDEFINED] ESC [IF]
CODE ESC
- CMP #0,&$1DBC
+ CMP #0,&$1DB4
0= IF MOV @R13+,R0
THEN
COLON
; IMMEDIATE
[THEN]
- [UNDEFINED] >BODY
- [IF]
+ [UNDEFINED] >BODY [IF]
CODE >BODY
ADD #4,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] EXECUTE
- [IF]
+ [UNDEFINED] EXECUTE [IF]
CODE EXECUTE
PUSH R14
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] EVALUATE
- [IF]
+ [UNDEFINED] EVALUATE [IF]
+
+ CODENNM
+ MOV @R1+,&$1DBE
+ MOV @R1+,&$1DBC
+ MOV @R1+,&$1DBA
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+
CODE EVALUATE
- MOV #$1DC2,R9
+ MOV #$1DBA,R9
MOV @R9+,R12
MOV @R9+,R11
MOV @R9+,R10
PUSHM #4,R13
- LO2HI
- [ ' \ 8 + , ]
- HI2LO
- MOV @R1+,&$1DC6
- MOV @R1+,&$1DC4
- MOV @R1+,&$1DC2
- MOV @R1+,R13
- MOV @R13+,R0
+ MOV R0,R13
+ ADD #8,R13
+ MOV #\+$08,R0
+ MOV #0,R3
ENDCODE
+ ,
+
[THEN]
- [UNDEFINED] CR
- [IF]
+ [UNDEFINED] CR [IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
[THEN]
: SET_TIME
- ESC [8;40;80t
+ ESC [8;42;80t
39 0 DO CR LOOP
ESC [H
CR ." DATE (DMY): "
EXECUTE
EVALUATE
CR TIME!
- RST_RET
;
-ECHO
-SET_TIME
+ RST_SET
+
+ ECHO
+ SET_TIME
-; -----------
+; --------------------------------
; SD_TEST.4th for MSP_EXP430FR5994
-; -----------
+; --------------------------------
CODE ABORT_SD_TEST
- SUB #2,R15
- MOV R14,0(R15)
+ SUB #4,R15
+ MOV R14,2(R15)
+ [UNDEFINED] WRITE
+ [IF]
+ MOV #-1,0(R15)
+ [ELSE]
+ MOV #0,0(R15)
+ [THEN]
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
- [UNDEFINED] WRITE
- [IF]
- 1 ABORT" no SD_CARD_READ_WRITE addon!"
- [THEN]
+ ABORT" FastForth V4.0 please!"
+ ABORT" build FastForth with SD_CARD_READ_WRITE addon!"
RST_RET
;
ABORT_SD_TEST
- MARKER {SD_TEST}
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] EXIT
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[UNDEFINED] BEGIN
[IF]
CODE BEGIN
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE IMMEDIATE
CODE UNTIL
- MOV #$40AC,R9
-BW1 ADD #4,&$1DC8
- MOV &$1DC8,R10
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
MOV @R15+,R14
ENDCODE IMMEDIATE
CODE AGAIN
- MOV #$40B2,R9
+ MOV #$409C,R9
GOTO BW1
ENDCODE IMMEDIATE
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
[UNDEFINED] STATE
[IF]
- $1DBC CONSTANT STATE
+ $1DB4 CONSTANT STATE
[THEN]
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
; IS CR
[THEN]
- [UNDEFINED] U.R
- [IF]
- : U.R
- >R <# 0 # #S #>
- R> OVER - 0 MAX SPACES TYPE
- ;
- [THEN]
-
[UNDEFINED] BASE
[IF]
- $1DBE CONSTANT BASE
- [THEN]
-
- [UNDEFINED] DUMP
- [IF]
- CODE DUMP
- PUSH R13
- PUSH &BASE
- MOV #$10,&BASE
- ADD @R15,R14
- LO2HI
- SWAP
- DO
- I 4 U.R SPACE
- I 8 + I
- DO I C@ 3 U.R LOOP
- SPACE
- I $10 + I 8 +
- DO I C@ 3 U.R LOOP
- SPACE SPACE
- I $10 + I
- DO I C@ $7E MIN $20 MAX EMIT LOOP
- CR
- $10 +LOOP
- R> BASE !
- ;
+ $1DB6 CONSTANT BASE
[THEN]
[UNDEFINED] HERE
ENDCODE
[THEN]
-
[UNDEFINED] DROP
[IF]
CODE DROP
; IMMEDIATE
[THEN]
+; ------------------------------------------------------------------
+; then we download the set of definitions we need (from UTILITY.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] U.R
+ [IF]
+ : U.R
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+ ;
+ [THEN]
+
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ CODE DUMP
+ PUSH R13
+ PUSH &BASE
+ MOV #$10,&BASE
+ ADD @R15,R14
+ LO2HI
+ SWAP
+ DO
+ I 4 U.R SPACE
+ I 8 + I
+ DO I C@ 3 U.R LOOP
+ SPACE
+ I $10 + I 8 +
+ DO I C@ 3 U.R LOOP
+ SPACE SPACE
+ I $10 + I
+ DO I C@ $7E MIN $20 MAX EMIT LOOP
+ CR
+ $10 +LOOP
+ R> BASE !
+ ;
+
+
CODE SD_EMIT
- CMP #$200,&$201E
- U>= IF
- CALL &WRITE+2
- THEN
MOV &$201E,R8
MOV.B R14,$1E00(R8)
- ADD #1,&$201E
MOV @R15+,R14
+ ADD #1,R8
+ MOV R8,&$201E
+ CMP #$200,R8
+ U>= IF
+ CALL #WRITE+4
+ THEN
MOV @R13+,R0
ENDCODE
- : DOESWRITE
+ : WRITEDUMP
['] SD_EMIT IS EMIT
$4000 HERE OVER - DUMP
['] EMIT >BODY IS EMIT
." 0 Set date and time" CR
." 1 Load {UTILITY} words" CR
." 2 Load {SD_TOOLS} words" CR
- ." 3 Load {CORE_COMP} words" CR
+ ." 3 Load {CORE_ANS} words" CR
." 4 Load ANS core tests" CR
." 5 Load a source file to make 10k program" CR
." 6 Read it only (47k)" CR
." 8 append FORTH dump to YOURFILE.TXT" CR
." 9 delete YOURFILE.TXT" CR
." your choice: "
- KEY DUP EMIT CR
+ KEY DUP $0D =
+ IF KEY DROP ." 'CR'"
+ ELSE DUP EMIT
+ THEN CR
NOECHO
- {SD_TEST}
+ RST_RET
CASE
'?' OF LOAD" FF_SPECS.4TH" ENDOF
'0' OF LOAD" RTC.4TH" ENDOF
'4' OF LOAD" CORETEST.4TH" ENDOF
'5' OF LOAD" PROG10K.4TH" ENDOF
'6' OF READ" PROG10K.4TH"
- BEGIN READ
- UNTIL ENDOF
+ BEGIN READ UNTIL ENDOF
'7' OF WRITE" YOURFILE.TXT"
- DOESWRITE ENDOF
+ WRITEDUMP ENDOF
'8' OF APPEND" YOURFILE.TXT"
- DOESWRITE ENDOF
+ WRITEDUMP ENDOF
'9' OF DEL" YOURFILE.TXT" ENDOF
ENDCASE
- CR
;
SD_TEST
; ---------------------------------------------------------------
; SD_TOOLS.4th for MSP_EXP430FR5994
-; BASIC TOOLS for SD Card : DIR FAT SECTOR CLUSTER
+; BASIC TOOLS for SD Card : DIR FAT SECTOR. CLUSTER.
; ---------------------------------------------------------------
CODE ABORT_SD_TOOLS
SUB #4,R15
MOV R14,2(R15)
- [UNDEFINED] LOAD" \ "
+ [UNDEFINED] LOAD" \ "
[IF]
- MOV #-1,0(R15)
+ MOV #-1,0(R15)
[ELSE]
- MOV #0,0(R15)
+ MOV #0,0(R15)
[THEN]
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
- ABORT" Builds FastForth with SD_CARD_LOADER addon.."
+ ABORT" FastForth V4.0 please!"
+ ABORT" Build FastForth with SD_CARD_LOADER addon!"
RST_RET
;
ABORT_SD_TOOLS
+ [DEFINED] {SD_TOOLS}
+ [IF] {SD_TOOLS}
+ [THEN]
+ [UNDEFINED] {SD_TOOLS}
+ [IF]
MARKER {SD_TOOLS}
- [UNDEFINED] HERE
- [IF]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] HERE [IF]
CODE HERE
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE
[THEN]
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
CODE +
ADD @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] U.R
- [IF]
- : U.R
- >R <# 0 # #S #>
- R> OVER - 0 MAX SPACES TYPE
- ;
- [THEN]
-
[UNDEFINED] DO
[IF]
HDNCODE XDO
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
ENDCODE IMMEDIATE
[THEN]
-
[UNDEFINED] I
[IF]
CODE I
[UNDEFINED] CR
[IF]
CODE CR
- MOV #$40B4,R0
+ MOV #$409E,R0
ENDCODE
:NONAME
; IS CR
[THEN]
+; ------------------------------------------------------------------
+; then we download the set of definitions we need (from UTILITY.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] U.R
+ [IF]
+ : U.R
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+ ;
+ [THEN]
+
[UNDEFINED] DUMP
[IF]
CODE DUMP
PUSH R13
- PUSH &$1DBE
- MOV #$10,&$1DBE
+ PUSH &$1DB6
+ MOV #$10,&$1DB6
ADD @R15,R14
LO2HI
SWAP
+ CR
+ 4 SPACES $10 0
+ DO I 3 U.R LOOP
DO CR
- I 4 U.R SPACE
- I 8 + I
- DO I C@ 3 U.R LOOP
- SPACE
- I $10 + I 8 +
+ I 4 U.R
+ I $10 + I
DO I C@ 3 U.R LOOP
SPACE SPACE
I $10 + I
DO I C@ $7E MIN $20 MAX EMIT LOOP
$10 +LOOP
- R> $1DBE !
+ R> $1DB6 !
;
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
CODE SECTOR.
BW1 MOV R14,R9
MOV @R15,R10
- CALL #R_SECT_WX
+ CALL #RD_SECT
COLON
SPACE <# #S #> TYPE
$1E00 $200 DUMP CR ;
CODE CLUSTER.
BW2 BIT.B #4,&$260
0<> IF
- MOV #SYS+$16,R0
+ MOV #COLD,R0
THEN
MOV.B &$2012,R10
MOV @R15,R9
MOV R14,2(R15)
MOV &$202C,0(R15)
MOV &$202E,R14
- GOTO BW2
+ CMP #0,R14
+ 0<> ?GOTO BW2
+ CMP #1,0(R15)
+ 0<> ?GOTO BW2
+ MOV &$200E,0(R15)
+ GOTO BW1
ENDCODE
- RST_SET ECHO
+ RST_SET
+
+ [THEN]
+
+ ECHO
--- /dev/null
+
+ CODE ABORT_CORE_ANS
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV &$180A,R14
+ SUB #400,R14
+ COLON
+ $0D EMIT
+ ABORT" FastForth V4.0 please!"
+ ;
+
+ ABORT_CORE_ANS
+
+ [UNDEFINED] BC!
+ [IF]
+ CODE BC!
+ BIC @R15+,0(R14)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] BS!
+ [IF]
+ CODE BS!
+ BIS @R15+,0(R14)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ $8000 $180E BC!
+
+ RST_RET
+
+; ----------------------------------
+; CORE_ANS.4th for MSP_EXP430FR5994
+; ----------------------------------
+
+ [DEFINED] {TEST}
+ [IF] {TEST} [THEN]
+
+ [UNDEFINED] {TEST}
+ [IF]
+
+ MARKER {TEST}
+
+ [UNDEFINED] ABORT
+ [IF]
+ CODE ABORT
+ MOV #ALLOT+$08,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] QUIT
+ [IF]
+ CODE QUIT
+ MOV #ALLOT+$0E,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] HERE
+ [IF]
+ CODE HERE
+ MOV #BEGIN,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] +
+ [IF]
+ CODE +
+ ADD @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] -
+ [IF]
+ CODE -
+ SUB @R15+,R14
+ XOR #-1,R14
+ ADD #1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DUP
+ [IF]
+
+ CODE DUP
+BW1 SUB #2,R15
+ MOV R14,0(R15)
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE ?DUP
+ CMP #0,R14
+ 0<> ?GOTO BW1
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] EXIT
+ [IF]
+ CODE EXIT
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DEPTH
+ [IF]
+ CODE DEPTH
+ MOV R14,-2(R15)
+ MOV #$1C80,R14
+ SUB R15,R14
+ RRA R14
+ SUB #2,R15
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] SWAP
+ [IF]
+ CODE SWAP
+ PUSH R14
+ MOV @R15,R14
+ MOV @R1+,0(R15)
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DROP
+ [IF]
+ CODE DROP
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] OVER
+ [IF]
+ CODE OVER
+ MOV R14,-2(R15)
+ MOV @R15,R14
+ SUB #2,R15
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] NIP
+ [IF]
+ CODE NIP
+ ADD #2,R15
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] >R
+ [IF]
+ CODE >R
+ PUSH R14
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] R>
+ [IF]
+ CODE R>
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV @R1+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C@
+ [IF]
+ CODE C@
+ MOV.B @R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C!
+ [IF]
+ CODE C!
+ MOV.B @R15+,0(R14)
+ ADD #1,R15
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C,
+ [IF]
+ CODE C,
+ MOV &$1DC0,R10
+ MOV.B R14,0(R10)
+ ADD #1,&$1DC0
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 0=
+ [IF]
+ CODE 0=
+ SUB #1,R14
+ SUBC R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 0<>
+ [IF]
+ CODE 0<>
+ SUB #1,R14
+ SUBC R14,R14
+ XOR #-1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 0<
+ [IF]
+ CODE 0<
+ ADD R14,R14
+ SUBC R14,R14
+ XOR #-1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] S>D
+ [IF]
+ : S>D
+ DUP 0<
+ ;
+ [THEN]
+
+ [UNDEFINED] =
+ [IF]
+ CODE =
+ SUB @R15+,R14
+ SUB #1,R14
+ SUBC R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] U<
+ [IF]
+
+ CODE U>
+ SUB @R15+,R14
+ U< ?GOTO FW1
+BW1 AND #0,R14
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE U<
+ SUB @R15+,R14
+ 0= ?GOTO BW1
+ U< ?GOTO BW1
+FW1 MOV #-1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] <
+ [IF]
+
+ CODE >
+ SUB @R15+,R14
+ S< ?GOTO FW1
+BW1 AND #0,R14
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE <
+ SUB @R15+,R14
+ 0= ?GOTO BW1
+ S< ?GOTO BW1
+FW1 MOV #-1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] IF
+ [IF]
+
+ CODE IF
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
+ ADD #2,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ CODE THEN
+ MOV &$1DC0,0(R14)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] ELSE
+ [IF]
+ CODE ELSE
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
+ MOV R10,0(R14)
+ SUB #2,R10
+ MOV R10,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] BEGIN
+ [IF]
+
+ CODE BEGIN
+ MOV #BEGIN,R0
+ ENDCODE IMMEDIATE
+
+ CODE UNTIL
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV R9,-4(R10)
+ MOV R14,-2(R10)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ CODE AGAIN
+ MOV #$409C,R9
+ GOTO BW1
+ ENDCODE IMMEDIATE
+
+ : WHILE
+ POSTPONE IF SWAP
+ ; IMMEDIATE
+
+ : REPEAT
+ POSTPONE AGAIN POSTPONE THEN
+ ; IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] DO
+ [IF]
+
+ HDNCODE XDO
+ MOV #$8000,R9
+ SUB @R15+,R9
+ MOV R14,R8
+ ADD R9,R8
+ PUSHM #2,R9
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE DO
+ SUB #2,R15
+ MOV R14,0(R15)
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
+ MOV #XDO,-2(R14)
+ ADD #2,&$1C00
+ MOV &$1C00,R10
+ MOV #0,0(R10)
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ HDNCODE XLOOP
+ ADD #1,0(R1)
+BW1 BIT #$100,R2
+ 0= IF
+ MOV @R13,R13
+ MOV @R13+,R0
+ THEN
+ ADD #4,R1
+ ADD #2,R13
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE LOOP
+ MOV #XLOOP,R9
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV R9,-4(R10)
+ MOV R14,-2(R10)
+ BEGIN
+ MOV &$1C00,R14
+ SUB #2,&$1C00
+ MOV @R14,R14
+ CMP #0,R14
+ 0<> WHILE
+ MOV R10,0(R14)
+ REPEAT
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+
+ HDNCODE XPLOO
+ ADD R14,0(R1)
+ MOV @R15+,R14
+ GOTO BW1
+ ENDCODE
+
+ CODE +LOOP
+ MOV #XPLOO,R9
+ GOTO BW2
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] I
+ [IF]
+ CODE I
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV @R1,R14
+ SUB 2(R1),R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] J
+ [IF]
+ CODE J
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV 4(R1),R14
+ SUB 6(R1),R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] UNLOOP
+ [IF]
+ CODE UNLOOP
+ ADD #4,R1
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] LEAVE
+ [IF]
+ CODE LEAVE
+ MOV &$1DC0,R10
+ MOV #UNLOOP,0(R10)
+ MOV #$409C,2(R10)
+ ADD #6,&$1DC0
+ ADD #2,&$1C00
+ ADD #4,R10
+ MOV &$1C00,R9
+ MOV R10,0(R9)
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] AND
+ [IF]
+ CODE AND
+ AND @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] OR
+ [IF]
+ CODE OR
+ BIS @R15+,R14
+ AND #-1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] XOR
+ [IF]
+ CODE XOR
+ XOR @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 1+
+ [IF]
+ CODE 1+
+ ADD #1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 1-
+ [IF]
+ CODE 1-
+ SUB #1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] INVERT
+ [IF]
+ CODE INVERT
+ XOR #-1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] NEGATE
+ [IF]
+ CODE NEGATE
+ XOR #-1,R14
+ ADD #1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] ABS
+ [IF]
+ CODE ABS
+ CMP #0,R14
+ 0>= IF
+ MOV @R13+,R0
+ THEN
+ MOV #NEGATE,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] LSHIFT
+ [IF]
+ CODE LSHIFT
+ MOV @R15+,R10
+ AND #$1F,R14
+ 0<> IF
+ BEGIN
+ ADD R10,R10
+ SUB #1,R14
+ 0= UNTIL
+ THEN
+ MOV R10,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] RSHIFT
+ [IF]
+ CODE RSHIFT
+ MOV @R15+,R10
+ AND #$1F,R14
+ 0<> IF
+ BEGIN
+ BIC #1,R2
+ RRC R10
+ SUB #1,R14
+ 0= UNTIL
+ THEN
+ MOV R10,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] MAX
+ [IF]
+ CODE MAX
+ CMP @R15,R14
+ S< ?GOTO FW1
+BW1 ADD #2,R15
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE MIN
+ CMP @R15,R14
+ S< ?GOTO BW1
+FW1 MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2*
+ [IF]
+ CODE 2*
+ ADD R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2/
+ [IF]
+ CODE 2/
+ RRA R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ RST_SET
+
+ CODE TSTBIT
+ MOV @R15+,R9
+ AND @R9,R14
+ MOV @R13+,R0
+ ENDCODE
+
+ $180E 8 TSTBIT
+
+ RST_RET
+
+ [IF] ; MSP430FR413x subfamily with hardware_MPY
+
+ [UNDEFINED] UM*
+ [IF]
+ CODE UM*
+ MOV @R15,&$4C0
+BW1 MOV R14,&$4C8
+ MOV &$4E4,0(R15)
+ MOV &$4E6,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] M*
+ [IF]
+ CODE M*
+ MOV @R15,&$4C2
+ GOTO BW1
+ ENDCODE
+ [THEN]
+
+ [ELSE] ; MSP430FRxxxx without hardware_MPY
+
+ [UNDEFINED] M*
+ [IF]
+ CODE M*
+ MOV @R15,R12
+ CMP #0,R12
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ THEN
+ XOR R14,R12
+ CMP #0,R14
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ PUSHM #2,R13
+ LO2HI
+ UM*
+ HI2LO
+ POPM #2,R13
+ CMP #0,R12
+ S< IF
+ XOR #-1,0(R15)
+ XOR #-1,R14
+ ADD #1,0(R15)
+ ADDC #0,R14
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+ [THEN] ; endof hardware_MPY
+
+ [UNDEFINED] UM/MOD
+ [IF]
+ CODE UM/MOD
+ PUSH #DROP
+ MOV #$4028,R0
+ ENDCODE
+ [THEN]
+
+ $180E @ 0< ; test the switch: FLOORED/SYMETRIC DIVISION
+ [IF]
+ [UNDEFINED] FM/MOD
+ [IF]
+ CODE FM/MOD
+ MOV R14,R12
+ MOV @R15,R11
+ CMP #0,R14
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ CMP #0,0(R15)
+ S< IF
+ XOR #-1,2(R15)
+ XOR #-1,0(R15)
+ ADD #1,2(R15)
+ ADDC #0,0(R15)
+ THEN
+ PUSHM #2,R12
+ CALL #$4028
+ MOV @R15+,R14
+ POPM #2,R12
+ CMP #0,R11
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ THEN
+ XOR R12,R11
+ CMP #0,R11
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+
+ CMP #0,0(R15)
+ 0<> IF
+ CMP #1,R14
+ S< IF
+ ADD R12,0(R15)
+ SUB #1,R14
+ THEN
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+ [ELSE]
+ [UNDEFINED] SM/REM
+ [IF]
+ CODE SM/REM
+ MOV R14,R12
+ MOV @R15,R11
+ CMP #0,R14
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ CMP #0,0(R15)
+ S< IF
+ XOR #-1,2(R15)
+ XOR #-1,0(R15)
+ ADD #1,2(R15)
+ ADDC #0,0(R15)
+ THEN
+ PUSHM #2,R12
+ CALL #$4028
+ MOV @R15+,R14
+ POPM #2,R12
+ CMP #0,R11
+ S< IF
+ XOR #-1,0(R15)
+ ADD #1,0(R15)
+ THEN
+ XOR R12,R11
+ CMP #0,R11
+ S< IF
+ XOR #-1,R14
+ ADD #1,R14
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+ [THEN]
+
+ [UNDEFINED] *
+ [IF]
+ : *
+ M* DROP
+ ;
+ [THEN]
+
+ [UNDEFINED] /MOD
+ [IF]
+ : /MOD
+ >R DUP 0< R>
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ ;
+ [THEN]
+
+ [UNDEFINED] /
+ [IF]
+ : /
+ >R DUP 0< R>
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ NIP
+ ;
+ [THEN]
+
+ [UNDEFINED] MOD
+ [IF]
+ : MOD
+ >R DUP 0< R>
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ DROP
+ ;
+ [THEN]
+
+ [UNDEFINED] */MOD
+ [IF]
+ : */MOD
+ >R M* R>
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ ;
+ [THEN]
+
+ [UNDEFINED] */
+ [IF]
+ : */
+ >R M* R>
+ [ $180E @ 0< ]
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ NIP
+ ;
+ [THEN]
+
+ [UNDEFINED] ROT
+ [IF]
+ CODE ROT
+ MOV @R15,R10
+ MOV R14,0(R15)
+ MOV 2(R15),R14
+ MOV R10,2(R15)
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] R@
+ [IF]
+ CODE R@
+ SUB #2,R15
+ MOV R14,0(R15)
+ MOV @R1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] TUCK
+ [IF]
+ : TUCK SWAP OVER ;
+ [THEN]
+
+ [UNDEFINED] 2@
+ [IF]
+ CODE 2@
+ SUB #2,R15
+ MOV 2(R14),0(R15)
+ MOV @R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2!
+ [IF]
+ CODE 2!
+ MOV @R15+,0(R14)
+ MOV @R15+,2(R14)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2DUP
+ [IF]
+ CODE 2DUP
+ MOV R14,-2(R15)
+ MOV @R15,-4(R15)
+ SUB #4,R15
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2DROP
+ [IF]
+ CODE 2DROP
+ ADD #2,R15
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2SWAP
+ [IF]
+ CODE 2SWAP
+ MOV @R15,R10
+ MOV 4(R15),0(R15)
+ MOV R10,4(R15)
+ MOV R14,R10
+ MOV 2(R15),R14
+ MOV R10,2(R15)
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2OVER
+ [IF]
+ CODE 2OVER
+ SUB #4,R15
+ MOV R14,2(R15)
+ MOV 8(R15),0(R15)
+ MOV 6(R15),R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] ALIGNED
+ [IF]
+ CODE ALIGNED
+ BIT #1,R14
+ ADDC #0,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] ALIGN
+ [IF]
+ CODE ALIGN
+ BIT #1,&$1DC0
+ ADDC #0,&$1DC0
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CHARS
+ [IF]
+ CODE CHARS
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CHAR+
+ [IF]
+ CODE CHAR+
+ ADD #1,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CELLS
+ [IF]
+ CODE CELLS
+ ADD R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CELL+
+ [IF]
+ CODE CELL+
+ ADD #2,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CHAR
+ [IF]
+ : CHAR
+ $20 WORD 1+ C@
+ ;
+ [THEN]
+
+ [UNDEFINED] [CHAR]
+ [IF]
+ : [CHAR]
+ CHAR POSTPONE LITERAL
+ ; IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] +!
+ [IF]
+ CODE +!
+ ADD @R15+,0(R14)
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] MOVE
+ [IF]
+ CODE MOVE
+ MOV R14,R10
+ MOV @R15+,R8
+ MOV @R15+,R9
+ MOV @R15+,R14
+ CMP #0,R10
+ 0<> IF
+ CMP R9,R8
+ 0<> IF
+ U< IF
+ BEGIN
+ MOV.B @R9+,0(R8)
+ ADD #1,R8
+ SUB #1,R10
+ 0= UNTIL
+ MOV @R13+,R0
+ THEN
+ ADD R10,R8
+ ADD R10,R9
+ BEGIN
+ SUB #1,R9
+ SUB #1,R8
+ MOV.B @R9,0(R8)
+ SUB #1,R10
+ 0= UNTIL
+ THEN
+ THEN
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] FILL
+ [IF]
+ CODE FILL
+ MOV @R15+,R9
+ MOV @R15+,R10
+ CMP #0,R9
+ 0<> IF
+ BEGIN
+ MOV.B R14,0(R10)
+ ADD #1,R10
+ SUB #1,R9
+ 0= UNTIL
+ THEN
+ MOV @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] HEX
+ [IF]
+ CODE HEX
+ MOV #$10,&$1DB6
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DECIMAL
+ [IF]
+
+ CODE DECIMAL
+ MOV #$0A,&$1DB6
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] ( ; )
+ [IF]
+ : (
+ ')' WORD DROP
+ ; IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] .( ; "
+ [IF]
+ CODE .( ; "
+ PUSH R13
+ MOV #0,&$1DB8
+ LO2HI
+ ')' WORD
+ COUNT TYPE
+ HI2LO
+ MOV #$20,&$1DB8
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] >BODY
+ [IF]
+ CODE >BODY
+ ADD #4,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] EXECUTE
+ [IF]
+ CODE EXECUTE
+ PUSH R14
+ MOV @R15+,R14
+ MOV @R1+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] EVALUATE
+ [IF]
+
+ CODENNM
+ MOV @R1+,&$1DBE
+ MOV @R1+,&$1DBC
+ MOV @R1+,&$1DBA
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+
+ CODE EVALUATE
+ MOV #$1DBA,R9
+ MOV @R9+,R12
+ MOV @R9+,R11
+ MOV @R9+,R10
+ PUSHM #4,R13
+ MOV R0,R13
+ ADD #8,R13
+ MOV #\+$08,R0
+ MOV #0,R3
+ ENDCODE
+ ,
+
+ [THEN]
+
+ [UNDEFINED] RECURSE
+ [IF]
+ CODE RECURSE
+ MOV &$1DC0,R9
+ MOV &$1DDC,0(R9)
+ ADD #2,&$1DC0
+ MOV @R13+,R0
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] SOURCE
+ [IF]
+ CODE SOURCE
+ SUB #4,R15
+ MOV R14,2(R15)
+ MOV &$1DBA,R14
+ MOV &$1DBC,0(R15)
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] VARIABLE
+ [IF]
+ : VARIABLE
+ CREATE
+ HI2LO
+ MOV #$1287,-4(R10)
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CONSTANT
+ [IF]
+ : CONSTANT
+ CREATE
+ HI2LO
+ MOV R14,-2(R10)
+ MOV @R15+,R14
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] STATE
+ [IF]
+ $1DB4 CONSTANT STATE
+ [THEN]
+
+ [UNDEFINED] BASE
+ [IF]
+ $1DB6 CONSTANT BASE
+ [THEN]
+
+ [UNDEFINED] >IN
+ [IF]
+ $1DBE CONSTANT >IN
+ [THEN]
+
+ [UNDEFINED] PAD
+ [IF]
+ $1CE4 CONSTANT PAD
+ [THEN]
+
+ [UNDEFINED] BL
+ [IF]
+ $20 CONSTANT BL
+ [THEN]
+
+ [UNDEFINED] SPACE
+ [IF]
+ : SPACE
+ $20 EMIT ;
+ [THEN]
+
+ [UNDEFINED] SPACES
+ [IF]
+ : SPACES
+ BEGIN
+ ?DUP
+ WHILE
+ $20 EMIT
+ 1-
+ REPEAT
+ ;
+ [THEN]
+
+ [UNDEFINED] DEFER
+ [IF]
+ : DEFER
+ CREATE
+ HI2LO
+ MOV #$4030,-4(R10)
+ MOV #$409E,-2(R10)
+ MOV @R1+,R13
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CR
+ [IF]
+ CODE CR
+ MOV #$409E,R0
+ ENDCODE
+
+ :NONAME
+ $0D EMIT $0A EMIT
+ ; IS CR
+ [THEN]
+
+ [UNDEFINED] TO
+ [IF]
+ CODE TO
+ BIS #$200,R2
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] VALUE
+ [IF]
+ : VALUE
+ CREATE ,
+ DOES>
+ HI2LO
+ MOV @R1+,R13
+ BIT #$200,R2
+ 0= IF
+ MOV @R14,R14
+ MOV @R13+,R0
+ THEN
+ BIC #$200,R2
+ MOV #!,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CASE
+ [IF]
+
+ : CASE 0
+ ; IMMEDIATE
+
+ : OF
+ 1+
+ >R
+ POSTPONE OVER POSTPONE =
+ POSTPONE IF
+ POSTPONE DROP
+ R>
+ ; IMMEDIATE
+
+ : ENDOF
+ >R
+ POSTPONE ELSE
+ R>
+ ; IMMEDIATE
+
+ : ENDCASE
+ POSTPONE DROP
+ 0 DO POSTPONE THEN
+ LOOP
+ ; IMMEDIATE
+ [THEN]
+
+ RST_SET
+
+ [THEN]
+
+ ECHO
+
+; CORE_ANS.4th for MSP_EXP430FR5994 is loaded
SUB #2,R15
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET
;
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
[UNDEFINED] CR
[IF]
- DEFER CR
+ CODE CR
+ MOV #$409E,R0
+ ENDCODE
:NONAME
$0D EMIT $0A EMIT
[UNDEFINED] BASE
[IF]
- $1DBE CONSTANT BASE
+ $1DB6 CONSTANT BASE
[THEN]
[UNDEFINED] DUMP
[UNDEFINED] HERE
[IF]
CODE HERE
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE
[THEN]
HERE
CODE TT
-MOVA #$0.1,R12
+MOVA #$.1,R12
ENDCODE
HERE OVER - DUMP
; you should see: 8C 00 01 00
SUB #2,R15
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET
;
ABORT_TSTWORDS
- [DEFINED] {TSTWORDS} [IF] {TSTWORDS} [THEN]
-
- MARKER {TSTWORDS}
-
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
[UNDEFINED] 0=
[IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] ELSE
[IF]
CODE ELSE
- ADD #4,&$1DC8
- MOV &$1DC8,R10
- MOV #$40B2,-4(R10)
+ ADD #4,&$1DC0
+ MOV &$1DC0,R10
+ MOV #$409C,-4(R10)
MOV R10,0(R14)
SUB #2,R10
MOV R10,R14
[IF]
CODE BEGIN
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE IMMEDIATE
CODE UNTIL
- MOV #$40AC,R9
-BW1 ADD #4,&$1DC8
- MOV &$1DC8,R10
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
MOV @R15+,R14
ENDCODE IMMEDIATE
CODE AGAIN
- MOV #$40B2,R9
+ MOV #$409C,R9
GOTO BW1
ENDCODE IMMEDIATE
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
ENDCODE IMMEDIATE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ECHO
+
+; -----------------------------------------------------------------------
+; test some assembler words and show how to mix FORTH/ASSEMBLER routines
+; -----------------------------------------------------------------------
- RST_SET
LOAD" \misc\TestASM.4th"
ECHO
+; -------------------------------------
+; here we returned in the TestWords.4th
+; -------------------------------------
: LOOP_TEST 8 0 DO I . LOOP
;
ELSE ABORT" <-- found !"
THEN
;
-\
\ No newline at end of file
+
-; ---------------------------------------------------------
; UARTI2CS.4th for MSP_EXP430FR5994
-; ---------------------------------------------------------
CODE ABORT_UARTI2CS
SUB #4,R15
0<> IF MOV #0,R14 THEN
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" <-- Ouch! unexpected I2C_FastForth target!"
RST_RET
;
ABORT_UARTI2CS
+
MARKER {UARTI2CS}
- 10 ALLOT
+ 16 ALLOT
+
+
+ CODE LEDS MOV @R13+,R0 ENDCODE
+
+ [UNDEFINED] = [IF]
+ CODE =
+ SUB @R15+,R14
+ SUB #1,R14
+ SUBC R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
- [UNDEFINED] TSTBIT
- [IF]
+ [UNDEFINED] + [IF]
+ CODE +
+ ADD @R15+,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] TSTBIT [IF]
CODE TSTBIT
MOV @R15+,R9
AND @R9,R14
MOV @R1+,R0
ENDCODE
- CODE REMOVE_U2I
+ HDNCODE REMOVE_U2I
BW1
+ [DEFINED] LEDS [IF]
BIC.B #1,&$202
BIC.B #1,&$204
BIC.B #2,&$202
BIC.B #2,&$204
+ [THEN]
CALL #I2CM_STOP
- MOV #6,R10
- BIC.B R10,&$265
- BIS.B R10,&$263
- BIS.B R10,&$267
+ BIS.B #6,&$263
+ BIS.B #6,&$267
MOV #0,&$3C0
- BIC.B #$80,&$20C
- BIC.B #$80,&$204
- BIC.B #$40,&$21A
- CMP #$4082,&{UARTI2CS}-2
+ BIC.B #$20,&$20C
+ BIC.B #$20,&$204
+ BIC.B #$10,&$21A
+ CMP #$406C,&{UARTI2CS}-2
0<> IF
MOV #{UARTI2CS},R10
- MOV #$4082,-2(R10)
+ MOV #$406C,-2(R10)
+ MOV @R10+,&$183A
MOV @R10+,&$183E
MOV @R10+,&$1840
MOV @R10+,&$FFF0
MOV @R10+,&$FFDE
THEN
- MOV #1,R14
- MOV #$4186+4,R0
+ MOV @R1+,R0
+ ENDCODE
+
+ HDNCODE STOP_U2I
+ CALL #I2CM_STOP
+ MOV &{UARTI2CS},R0
+ ENDCODE
+
+ HDNCODE BACKGRND_U2I
+ BIT #8,&$5CA
+ 0<> IF
+ MOV #WARM_IP_ADR,0(R1)
+ PUSH #$40BA
+BW2 MOV #1,R14
+ GOTO BW1
+ THEN
+ BIC.B #$10,&$21C
+ MOV #$0D,R12
+ MOV #0,R11
+ MOV.B &{UARTI2CS}+15,R8
+ MOV &{UARTI2CS}+4,R0
+ ENDCODE
+
+ HDNCODE HARD_U2I
+BW3 MOV &{UARTI2CS}+12,&$3C0
+ MOV #4096,&$3D2
+ MOV #$60,&$3C6
+ MOV #4096,&$3D6
+ BIS.B #$20,&$204
+ BIS.B #$20,&$20C
+ BIS.B #$10,&$21A
+ BIC.B #6,&$267
+ BIC.B #6,&$263
+ BIC.B #6,&I2CSM_IES
+ [DEFINED] LEDS [IF]
+ BIS.B #1,&$204
+ BIS.B #2,&$204
+ [THEN]
+ CALL &{UARTI2CS}+2
+ CMP #6,R14
+ 0= ?GOTO BW2
+ CMP #$0E,R14
+ 0<> IF
+ CMP #$0A,R14
+ U>= ?GOTO BW1
+ THEN
+ MOV #ALLOT+$08,0(R1)
+ MOV @R1+,R0
ENDCODE
HDNCODE I2CM_START
BIS.B #4,&$265
- BIS.B &{UARTI2CS}+8,R9
- MOV R0,R0
+ BIS &{UARTI2CS}+10,R9
BIS.B #2,&$265
MOV.B #8,R10
BEGIN
ADD.B R9,R9
- U>= IF
- BIC.B #4,&$265
- ELSE
+ U< IF
BIS.B #4,&$265
- THEN
- BIC.B #2,&$265
- BIT.B #4,&$261
- BIS.B #2,&$265
- 0= IF
- BIT.B #4,&$265
+ BIC.B #2,&$265
+ MOV R0,R0
+ ELSE
+ BIC.B #4,&$265
+ BIC.B #2,&$265
+ BIT.B #4,&$261
0= IF
- BIS.B #6,&$265
- BIC.B #6,&I2CSM_IES
BEGIN
- BIT.B #6,&I2CSM_IFG
- BIC.B #6,&I2CSM_IFG
- 0<> IF
- MOV #9,R10
- ELSE
- $3C00 ,
- $3C00 ,
- THEN
- SUB #1,R10
+ BIT #2,&$5DC
+ 0<> UNTIL
+ MOV.B #'c',&$5CE
+ BEGIN
+ BIT.B #4,&$261
+ 0<> UNTIL
+ BEGIN
+ BIC.B #6,&I2CSM_IFG
+ MOV R0,R0
+ MOV.B &{UARTI2CS}+14,R10
+ BEGIN
+ MOV #0,R3
+ SUB #1,R10
+ 0= UNTIL
+ BIT.B #6,&I2CSM_IFG
0= UNTIL
ADD #2,R1
- MOV @R1+,R0
+ MOV @R1,R0
THEN
THEN
+ BIS.B #2,&$265
SUB #1,R10
0= UNTIL
BIC.B #4,&$265
MOV @R1+,R0
ENDCODE
-
HDNCODE U2I_TERM_INT
ADD #4,R1
BEGIN
- MOV.B &$5CC,R8
- MOV.B R8,$1CE4(R11)
+ MOV.B &$5CC,R10
ADD #1,R11
- CMP.B R8,R12
+ CMP.B R12,R10
0<> WHILE
- CMP #4,R10
+ CMP ##84+1,R11
+ U< IF
+ MOV.B R10,$1CE4-3(R11)
+ THEN
+ CMP.B #4,R8
0<> IF
BEGIN
BIT #2,&$5DC
0<> UNTIL
- MOV.B R8,&$5CE
+ MOV.B R10,&$5CE
THEN
BEGIN
BIT #1,&$5DC
0<> UNTIL
REPEAT
- CALL #ACCEPT+$2A
+ CALL #ACCEPT+$26
+ MOV.B R10,$1CE4-3(R11)
BEGIN
BIT #1,&$5DC
0<> UNTIL
BW2
MOV.B &$5CC,R12
- MOV.B R12,$1CE4(R11)
+ MOV.B R12,$1CE4-2(R11)
PUSH R0
MOV #0,R9
CALL #I2CM_START
0<> ?GOTO FW2
+ [DEFINED] LEDS [IF]
BIS.B #1,&$202
- MOV #$1CE4,R8
+ [THEN]
+ MOV #$1CE4-2,R11
BEGIN
- MOV.B @R8,R9
- MOV.B #8,R10
+ MOV.B @R11,R9
+ MOV.B #7,R10
BEGIN
ADD.B R9,R9
U>= IF
BIC.B #4,&$265
ELSE
BIS.B #4,&$265
+ $3C00 ,
THEN
BIC.B #2,&$265
- BEGIN
- BIT.B #2,&$261
- 0<> UNTIL
+ MOV R0,R0
BIS.B #2,&$265
SUB #1,R10
0= UNTIL
- BIC.B #4,&$265
+ ADD.B R9,R9
+ U>= IF
+ BIC.B #4,&$265
+ ELSE
+ BIS.B #4,&$265
+ $3C00 ,
+ THEN
BIC.B #2,&$265
BEGIN
BIT.B #2,&$261
0<> UNTIL
+ BIS.B #2,&$265
+ BIC.B #4,&$265
+ BIC.B #2,&$265
+ MOV R0,R0
BIT.B #4,&$261
BIS.B #2,&$265
0= WHILE
- CMP.B @R8+,R12
+ CMP.B @R11+,R12
0= UNTIL
THEN
+ [DEFINED] LEDS [IF]
BIC.B #1,&$202
+ [THEN]
GOTO FW1
ENDCODE
FW2
PUSH R0
BEGIN
- BIT #8,&$5CA
- 0<> ?GOTO BW1
- BIT.B #$20,&$240
- 0= ?GOTO BW1
BIC.B #2,&$265
MOV #1,R9
- CALL #I2CM_START
+ CALL #I2CM_START
0<> IF
CALL #I2CM_STOP
- MOV #'.',&$5CE
- MOV #$4000,R0
+ MOV.B #'.',&$5CE
+ MOV.B #-1,&{UARTI2CS}+15
+ MOV #ACCEPT+$1C,R0
+ THEN
+ CMP.B #-1,R8
+ 0= IF
+ MOV.B #0,R8
+ MOV.B #$0D,&$5CE
+ BEGIN
+ BIT #2,&$5DC
+ 0<> UNTIL
+ MOV.B #$0A,&$5CE
THEN
+ [DEFINED] LEDS [IF]
BIS.B #2,&$202
+ [THEN]
BEGIN
BEGIN
BIC.B #4,&$265
MOV.B #8,R10
BEGIN
- BIC.B #2,&$265
- BIT.B #4,&$261
- BIS.B #2,&$265
- ADDC.B R9,R9
- SUB #1,R10
+ BIC.B #2,&$265
+ BIT.B #4,&$261
+ BIS.B #2,&$265
+ ADDC.B R9,R9
+ SUB #1,R10
0= UNTIL
CMP.B #-1,R9
- 0= IF
- MOV #2,R9
- THEN
+ 0<> WHILE
CMP.B #8,R9
U>= WHILE
BIS.B #4,&$265
BIT.B #2,&$261
0<> UNTIL
BIS.B #2,&$265
- CMP.B #4,&{UARTI2CS}+9
+ CMP.B #4,R8
0<> IF
BEGIN
BIT #2,&$5DC
MOV.B R9,&$5CE
THEN
REPEAT
- CMP.B #4,R9
- U>= IF
- MOV.B R9,&{UARTI2CS}+9
- BIS.B #4,&$265
+ CMP.B #4,R9
+ U>= IF
+ MOV.B R9,R8
+ BIS.B #4,&$265
+ THEN
THEN
BIC.B #2,&$265
BEGIN
0<> UNTIL
CMP.B #2,R9
U>= WHILE
- 0= IF
- MOV.B #0,&{UARTI2CS}+9
- CALL #KEY+$8
- BEGIN
- BIC #1,&$5DC
- MOV &$1800,R9
- BEGIN MOV #65,R10
- BEGIN SUB #1,R10
- 0= UNTIL
- SUB #1,R9
+ MOV.B #0,R8
+ CALL #KEY+8
+ BEGIN
+ BIC #1,&$5DC
+ MOV &$1800,R9
+ BEGIN MOV #65,R10
+ BEGIN SUB #1,R10
0= UNTIL
- BIT #1,&$5DC
- 0= UNTIL
- THEN
+ SUB #1,R9
+ 0= UNTIL
+ BIT #1,&$5DC
+ 0= UNTIL
REPEAT
CALL #I2CM_STOP
+ [DEFINED] LEDS [IF]
BIC.B #2,&$202
+ [THEN]
CMP.B #0,R9
0= IF
- MOV #$4000,R0
+ MOV.B R8,&{UARTI2CS}+15
+ MOV #ACCEPT+$1C,R0
THEN
- CALL #KEY+$8
+ CALL #KEY+8
BEGIN
BIT #1,&$5DC
0<> UNTIL
- CALL #ACCEPT+$2A
+ CALL #ACCEPT+$26
MOV #0,R11
GOTO BW2
ENDCODE
- HDNCODE SLEEP_U2I
- $180E $4000 TSTBIT
- [IF] MOV #%1_1001_0100,&$3C0 ; if ACLK=LFXTAL
- [ELSE] MOV #%1_0001_0100,&$3C0 ; if ACLK=VLO
- [THEN]
- MOV.B &{UARTI2CS}+9,R10
- MOV #$0D,R12
- MOV #0,R11
- BIC #$40,&$21C
- MOV &{UARTI2CS}+2,R0
- ENDCODE
-
- HDNCODE INIT_U2I
- MOV #4096,&$3D2
- MOV #$60,&$3C6
- MOV #4095,&$3D6
- BIS.B #$80,&$204
- BIS.B #$80,&$20C
- BIS.B #$40,&$21A
- BIC.B #6,&$267
- BIC.B #6,&$263
- BIS.B #1,&$204
- BIS.B #2,&$204
- CALL &{UARTI2CS}
- CMP #$0E,R14
- 0<> IF
- CMP #$0A,R14
- U>= ?GOTO BW1
- THEN
- BIS.B #$40,&$21C
- MOV #ALLOT+$8,R0
- ENDCODE
-
- : UARTI2CS
+ CODE START_U2I
+ SUB #2,R15
+ MOV R14,0(R15)
+ COLON
$0D EMIT $0A EMIT
+ ." Connect to I2C_SLAVE at @"
+ . $08 EMIT
+ ." , TERATERM(Alt-B) "
+ ." or I2C_MASTER(S2) to quit..."
HI2LO
MOV @R1+,R13
BEGIN
BIT #1,&$5CA
0= UNTIL
- CMP #$4082,&{UARTI2CS}-2
+ CMP #$406C,&{UARTI2CS}-2
0= IF
MOV #REMOVE_U2I,&{UARTI2CS}-2
- MOV &$183E,&{UARTI2CS}
- MOV &$1840,&{UARTI2CS}+2
- MOV &$FFF0,&{UARTI2CS}+4
- MOV &$FFDE,&{UARTI2CS}+6
- MOV R14,&{UARTI2CS}+8
+ MOV &$183A,&{UARTI2CS}
+ MOV &$183E,&{UARTI2CS}+2
+ MOV &$1840,&{UARTI2CS}+4
+ MOV &$FFF0,&{UARTI2CS}+6
+ MOV &$FFDE,&{UARTI2CS}+8
+ MOV #STOP_U2I,&$183A
+ MOV #HARD_U2I,&$183E
+ MOV #BACKGRND_U2I,&$1840
+ MOV #U2I_TERM_INT,&$FFF0
+ MOV #500MS_INT,&$FFDE
+ MOV R14,&{UARTI2CS}+10
+ $180E $4000 TSTBIT
+ [IF] MOV #$0194,&{UARTI2CS}+12
+ [ELSE] MOV #$0114,&{UARTI2CS}+12
+ [THEN]
+ $1800 @ 24000 =
+ [IF] MOV #116,&{UARTI2CS}+14
+ [ELSE] $1800 @ 16000 =
+ [IF] MOV #76,&{UARTI2CS}+14
+ [ELSE] MOV #36,&{UARTI2CS}+14
+ [THEN]
+ [THEN]
THEN
MOV #0,R14
- MOV #INIT_U2I,&$183E
- MOV #SLEEP_U2I,&$1840
- MOV #U2I_TERM_INT,&$FFF0
- MOV #500MS_INT,&$FFDE
- MOV #INIT_U2I,R0
+ GOTO BW3
ENDCODE
- RST_SET ECHO
+RST_SET ECHO
- $12 UARTI2CS ; TERATERM(Alt-B) or USB_to_I2C_bridge(SW2) to quit
+#18 START_U2I
-
; --------------------------------
; UTILITY.4th for MSP_EXP430FR5994
; --------------------------------
SUB #2,R15
MOV R14,0(R15)
MOV &$180A,R14
- SUB #309,R14
+ SUB #400,R14
COLON
$0D EMIT
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET
;
ABORT_UTILITY
+ [DEFINED] {UTILITY}
+ [IF] {UTILITY}
+ [THEN]
+ [UNDEFINED] {UTILITY}
+ [IF]
MARKER {UTILITY}
- [UNDEFINED] EXIT
- [IF]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.4th for MSP_EXP430FR5994)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] EXIT [IF]
CODE EXIT
MOV @R1+,R13
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] SWAP
- [IF]
+ [UNDEFINED] SWAP [IF]
CODE SWAP
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] U<
- [IF]
+ [UNDEFINED] U< [IF]
CODE U<
SUB @R15+,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] IF
- [IF]
+ [UNDEFINED] IF [IF]
CODE IF
SUB #2,R15
MOV R14,0(R15)
- MOV &$1DC8,R14
- ADD #4,&$1DC8
- MOV #$40AC,0(R14)
+ MOV &$1DC0,R14
+ ADD #4,&$1DC0
+ MOV #$4096,0(R14)
ADD #2,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
CODE THEN
- MOV &$1DC8,0(R14)
+ MOV &$1DC0,0(R14)
MOV @R15+,R14
MOV @R13+,R0
ENDCODE IMMEDIATE
[UNDEFINED] BEGIN [IF]
CODE BEGIN
- MOV #$4032,R0
+ MOV #BEGIN,R0
ENDCODE IMMEDIATE
CODE UNTIL
- MOV #$40AC,R9
-BW1 ADD #4,&$1DC8
- MOV &$1DC8,R10
+ MOV #$4096,R9
+BW1 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
MOV @R15+,R14
ENDCODE IMMEDIATE
CODE AGAIN
- MOV #$40B2,R9
+ MOV #$409C,R9
GOTO BW1
ENDCODE IMMEDIATE
; IMMEDIATE
[THEN]
- [UNDEFINED] DO
- [IF]
+ [UNDEFINED] DO [IF]
+
HDNCODE XDO
MOV #$8000,R9
SUB @R15+,R9
CODE DO
SUB #2,R15
MOV R14,0(R15)
- ADD #2,&$1DC8
- MOV &$1DC8,R14
+ ADD #2,&$1DC0
+ MOV &$1DC0,R14
MOV #XDO,-2(R14)
ADD #2,&$1C00
MOV &$1C00,R10
CODE LOOP
MOV #XLOOP,R9
-BW2 ADD #4,&$1DC8
- MOV &$1DC8,R10
+BW2 ADD #4,&$1DC0
+ MOV &$1DC0,R10
MOV R9,-4(R10)
MOV R14,-2(R10)
BEGIN
ENDCODE IMMEDIATE
[THEN]
- [UNDEFINED] I
- [IF]
+ [UNDEFINED] I [IF]
CODE I
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] DUP
- [IF]
+ [UNDEFINED] DUP [IF]
CODE DUP
BW1 SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] DROP
- [IF]
+ [UNDEFINED] DROP [IF]
CODE DROP
MOV @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] >R
- [IF]
+ [UNDEFINED] >R [IF]
CODE >R
PUSH R14
MOV @R15+,R14
ENDCODE
[THEN]
- [UNDEFINED] R>
- [IF]
+ [UNDEFINED] R> [IF]
CODE R>
SUB #2,R15
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] SPACE
- [IF]
+ [UNDEFINED] SPACE [IF]
: SPACE
$20 EMIT ;
[THEN]
- [UNDEFINED] SPACES
- [IF]
+ [UNDEFINED] SPACES [IF]
CODE SPACES
CMP #0,R14
0<> IF
ENDCODE
[THEN]
- [UNDEFINED] 2DUP
- [IF]
+ [UNDEFINED] 2DUP [IF]
CODE 2DUP
MOV R14,-2(R15)
MOV @R15,-4(R15)
ENDCODE
[THEN]
- [UNDEFINED] 1+
- [IF]
+ [UNDEFINED] 1+ [IF]
CODE 1+
ADD #1,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
CODE +
ADD @R15+,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] -
- [IF]
+ [UNDEFINED] - [IF]
CODE -
SUB @R15+,R14
XOR #-1,R14
ENDCODE
[THEN]
- [UNDEFINED] C@
- [IF]
+ [UNDEFINED] C@ [IF]
CODE C@
MOV.B @R14,R14
MOV @R13+,R0
ENDCODE
[THEN]
- [UNDEFINED] AND
- [IF]
- CODE AND
- AND @R15+,R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] ROT
- [IF]
+ [UNDEFINED] ROT [IF]
CODE ROT
MOV @R15,R10
MOV R14,0(R15)
ENDCODE
[THEN]
- [UNDEFINED] MAX
- [IF]
+ [UNDEFINED] MAX [IF]
CODE MAX
CMP @R15,R14
S< ?GOTO FW1
ENDCODE
[THEN]
- [UNDEFINED] OVER
- [IF]
+ [UNDEFINED] OVER [IF]
CODE OVER
MOV R14,-2(R15)
MOV @R15,R14
ENDCODE
[THEN]
- [UNDEFINED] MOVE
- [IF]
+ [UNDEFINED] MOVE [IF]
CODE MOVE
MOV R14,R10
MOV @R15+,R8
ENDCODE
[THEN]
- [UNDEFINED] CONSTANT
- [IF]
+ [UNDEFINED] CR [IF]
+ CODE CR
+ MOV #$409E,R0
+ ENDCODE
+
+ :NONAME
+ $0D EMIT $0A EMIT
+ ; IS CR
+ [THEN]
+
+ [UNDEFINED] 2* [IF]
+ CODE 2*
+ ADD R14,R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2/ [IF]
+ CODE 2/
+ RRA R14
+ MOV @R13+,R0
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CONSTANT [IF]
: CONSTANT
CREATE
HI2LO
ENDCODE
[THEN]
- [UNDEFINED] BASE
- [IF]
- $1DBE CONSTANT BASE
+ [UNDEFINED] BASE [IF]
+ $1DB6 CONSTANT BASE
[THEN]
- [UNDEFINED] .S
- [IF]
+ [UNDEFINED] HERE [IF]
+ CODE HERE
+ MOV #BEGIN,R0
+ ENDCODE
+ [THEN]
+
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ [UNDEFINED] .S [IF]
CODE .S
MOV R14,-2(R15)
MOV R15,R14
;
[THEN]
- [UNDEFINED] .RS
- [IF]
+ [UNDEFINED] .RS [IF]
CODE .RS
MOV R14,-2(R15)
MOV R1,-6(R15)
ENDCODE
[THEN]
- [UNDEFINED] ?
- [IF]
+ [UNDEFINED] ? [IF]
CODE ?
MOV @R14,R14
MOV #U.,R0
ENDCODE
[THEN]
- [UNDEFINED] CR
- [IF]
-
- CODE CR
- MOV #$40B4,R0
- ENDCODE
-
- :NONAME
- $0D EMIT $0A EMIT
- ; IS CR
- [THEN]
-
- [UNDEFINED] 2/
- [IF]
- CODE 2/
- RRA R14
- MOV @R13+,R0
- ENDCODE
- [THEN]
-
- [UNDEFINED] WORDS
- [IF]
+ [UNDEFINED] WORDS [IF]
: WORDS
CR
- $1DCE @ $1CE4
- $180C @ DUP +
+ $1DC6 @ $1CE4
+ $180C @ 2*
MOVE
BEGIN
0 DUP
- $180C @ DUP + 0
+ $180C @ 2* 0
DO
DUP I $1CE4 + @
U< IF
;
[THEN]
- [UNDEFINED] DUMP
- [IF]
+ [UNDEFINED] DUMP [IF]
CODE DUMP
PUSH R13
- PUSH &$1DBE
- MOV #$10,&$1DBE
+ PUSH &$1DB6
+ MOV #$10,&$1DB6
ADD @R15,R14
LO2HI
SWAP
- $FFF0 AND
+ CR
+ 4 SPACES $10 0 DO I 3 U.R LOOP
DO CR
- I 4 U.R SPACE
- I 8 + I
- DO I C@ 3 U.R LOOP
- SPACE
- I $10 + I 8 +
+ I 4 U.R
+ I $10 + I
DO I C@ 3 U.R LOOP
SPACE SPACE
I $10 + I
RST_SET
- [THEN] ECHO ; endof [UNDEFINED] {TOOLS}
+ [THEN]
+
+ ECHO
\ -*- coding: utf-8 -*-
-
-; -----------
-; SD_TEST.f
-; -----------
\
\ to see kernel options, download FastForthSpecs.f
\ FastForth kernel options: MSP430ASSEMBLER, CONDCOMP, SD_CARD_READ_WRITE
\ copy PROG100k.f to \PROG100k.4TH
\ copy RTC.f to \RTC.4TH ( doesn't work with if FR2xxx or FR4xxx)
-\ first, we test for downloading driver only if UART TERMINAL target
+; --------------------------------
+; SD_TEST.f
+; --------------------------------
+
+\ first, we do some tests allowing the download
CODE ABORT_SD_TEST
- SUB #2,PSP
- MOV TOS,0(PSP)
- MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
- COLON
- 'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
- [UNDEFINED] WRITE
+ SUB #4,PSP
+ MOV TOS,2(PSP)
+ [UNDEFINED] WRITE
[IF]
- 1 ABORT" no SD_CARD_READ_WRITE addon!"
+ MOV #-1,0(PSP)
+ [ELSE]
+ MOV #0,0(PSP)
[THEN]
- RST_RET \ remove ABORT_SD_TEST definition before resuming
+ MOV &VERSION,TOS
+ SUB #400,TOS \ FastForth V4.0
+ COLON
+ 'CR' EMIT \ return to column 1 without 'LF'
+ ABORT" FastForth V4.0 please!"
+ ABORT" build FastForth with SD_CARD_READ_WRITE addon!"
+ RST_RET \ remove ABORT_SD_TEST definition before resuming
;
ABORT_SD_TEST
- MARKER {SD_TEST}
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
\ https://forth-standard.org/standard/core/EXIT
\ EXIT -- exit a colon definition; CALL #EXIT performs ASMtoFORTH (10 cycles)
[UNDEFINED] BEGIN
[IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
CODE BEGIN
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE IMMEDIATE
\ https://forth-standard.org/standard/core/UNTIL
; IS CR
[THEN]
- [UNDEFINED] U.R
- [IF] \ defined in {UTILITY}
- : U.R \ u n -- display u unsigned in n width (n >= 2)
- >R <# 0 # #S #>
- R> OVER - 0 MAX SPACES TYPE
- ;
- [THEN]
-
\ https://forth-standard.org/standard/core/BASE
\ BASE -- a-addr holds conversion radix
[UNDEFINED] BASE
BASEADR CONSTANT BASE
[THEN]
-\ https://forth-standard.org/standard/tools/DUMP
- [UNDEFINED] DUMP
- [IF] \ defined in {UTILITY}
- CODE DUMP \ adr n -- dump memory
- PUSH IP
- PUSH &BASE \ save current base
- MOV #$10,&BASE \ HEX base
- ADD @PSP,TOS \ -- ORG END
- LO2HI
- SWAP \ -- END ORG
- DO \ generate line
- I 4 U.R SPACE \ generate address
- I 8 + I
- DO I C@ 3 U.R LOOP
- SPACE
- I $10 + I 8 +
- DO I C@ 3 U.R LOOP
- SPACE SPACE
- I $10 + I \ display 16 chars
- DO I C@ $7E MIN $20 MAX EMIT LOOP
- CR
- $10 +LOOP
- R> BASE ! \ restore current base
- ;
- [THEN]
-
[UNDEFINED] HERE
[IF]
CODE HERE
ENDCODE
[THEN]
-
\ https://forth-standard.org/standard/core/DROP
\ DROP x -- drop top of stack
[UNDEFINED] DROP
; IMMEDIATE
[THEN]
-\ SD_EMIT c -- output char c to a SD_CARD file opened as write
+; ------------------------------------------------------------------
+; then we download the set of definitions we need (from UTILITY.f)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] U.R
+ [IF] \ defined in {UTILITY}
+ : U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+ ;
+ [THEN]
+
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+\ https://forth-standard.org/standard/tools/DUMP
+ CODE DUMP \ adr n -- dump memory
+ PUSH IP
+ PUSH &BASE \ save current base
+ MOV #$10,&BASE \ HEX base
+ ADD @PSP,TOS \ -- ORG END
+ LO2HI
+ SWAP \ -- END ORG
+ DO \ generate line
+ I 4 U.R SPACE \ generate address
+ I 8 + I
+ DO I C@ 3 U.R LOOP
+ SPACE
+ I $10 + I 8 +
+ DO I C@ 3 U.R LOOP
+ SPACE SPACE
+ I $10 + I \ display 16 chars
+ DO I C@ $7E MIN $20 MAX EMIT LOOP
+ CR
+ $10 +LOOP
+ R> BASE ! \ restore current base
+ ;
+
+ \ SD_EMIT c -- output char c to a SD_CARD file opened as write
CODE SD_EMIT
- CMP #$200,&BufferPtr \ 512 bytes by sector
- U>= IF \ if file buffer is full
- CALL &WRITE+2 \ CALL #Write_File ; BufferPtr = 0
- THEN
MOV &BufferPtr,Y \ 3
MOV.B TOS,SD_BUF(Y) \ 3
- ADD #1,&BufferPtr \ 4
MOV @PSP+,TOS \ 2
- MOV @IP+,PC
- ENDCODE
-
- : DOESWRITE
- ['] SD_EMIT IS EMIT
- MAIN_ORG HERE OVER - DUMP
- ['] EMIT >BODY IS EMIT
- CLOSE
+ ADD #1,Y \ 1
+ MOV Y,&BufferPtr \ 3
+ CMP #$200,Y \ 2 512 bytes by sector
+ U>= IF \ 2 if buffer is full
+ CALL #Write_File \ write it; BufferPtr = 0
+ THEN
+ MOV @IP+,PC \ 4
+ ENDCODE \ 20~
+
+ : WRITEDUMP
+ ['] SD_EMIT IS EMIT \ redirect output to SD_EMIT
+ MAIN_ORG HERE OVER - DUMP \ dump MAIN memory up to HERE address
+ ['] EMIT >BODY IS EMIT \ redirect output to default EMIT
+ CLOSE \ close YOURFILE.TXT
;
: SD_TEST
." 0 Set date and time" CR
." 1 Load {UTILITY} words" CR
." 2 Load {SD_TOOLS} words" CR
- ." 3 Load {CORE_COMP} words" CR
+ ." 3 Load {CORE_ANS} words" CR
." 4 Load ANS core tests" CR
." 5 Load a source file to make 10k program" CR
." 6 Read it only (47k)" CR
." 8 append FORTH dump to YOURFILE.TXT" CR
." 9 delete YOURFILE.TXT" CR
." your choice: "
- KEY DUP EMIT CR
+ KEY DUP 'CR' =
+ IF KEY DROP ." 'CR'"
+ ELSE DUP EMIT
+ THEN CR
NOECHO
- {SD_TEST} \ remove {SD_TEST} application
+ RST_RET \ remove all definitions
CASE
'?' OF LOAD" FF_SPECS.4TH" ENDOF \
'0' OF LOAD" RTC.4TH" ENDOF
'2' OF LOAD" SD_TOOLS.4TH" ENDOF
'3' OF LOAD" CORE_ANS.4TH" ENDOF
'4' OF LOAD" CORETEST.4TH" ENDOF
- '5' OF LOAD" PROG10K.4TH" ENDOF \ download one ko, so no erasure here
- '6' OF READ" PROG10K.4TH"
- BEGIN READ \ sequentially read 512 bytes
- UNTIL ENDOF \ prog10k.4TH is closed
- '7' OF WRITE" YOURFILE.TXT"
- DOESWRITE ENDOF
- '8' OF APPEND" YOURFILE.TXT"
- DOESWRITE ENDOF
+ '5' OF LOAD" PROG10K.4TH" ENDOF
+ '6' OF READ" PROG10K.4TH" \ open file as read
+ BEGIN READ UNTIL ENDOF \ sequentially read 512 bytes, then file is closed
+ '7' OF WRITE" YOURFILE.TXT" \ overwrite existing file or create new file
+ WRITEDUMP ENDOF
+ '8' OF APPEND" YOURFILE.TXT" \ append to existing file or create new file
+ WRITEDUMP ENDOF
'9' OF DEL" YOURFILE.TXT" ENDOF
ENDCASE
- CR
;
SD_TEST
; ---------------------------------------------------------------
; SD_TOOLS.f
-; BASIC TOOLS for SD Card : DIR FAT SECTOR CLUSTER
+; BASIC TOOLS for SD Card : DIR FAT SECTOR. CLUSTER.
; ---------------------------------------------------------------
-\ first, we test for downloading driver only if UART TERMINAL target
+\ first, we do some tests allowing the download
CODE ABORT_SD_TOOLS
SUB #4,PSP
MOV TOS,2(PSP)
- [UNDEFINED] LOAD" \ "
+ [UNDEFINED] LOAD" \ "
[IF]
- MOV #-1,0(PSP)
+ MOV #-1,0(PSP)
[ELSE]
- MOV #0,0(PSP)
+ MOV #0,0(PSP)
[THEN]
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
- 'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
- ABORT" Builds FastForth with SD_CARD_LOADER addon.."
- RST_RET \ remove ABORT_UARTI2CS definition before resuming
+ 'CR' EMIT \ return to column 1 without 'LF'
+ ABORT" FastForth V4.0 please!"
+ ABORT" Build FastForth with SD_CARD_LOADER addon!"
+ RST_RET \ remove ABORT_UARTI2CS definition before resuming
;
ABORT_SD_TOOLS
+ [DEFINED] {SD_TOOLS}
+ [IF] {SD_TOOLS}
+ [THEN]
+ [UNDEFINED] {SD_TOOLS}
+ [IF]
MARKER {SD_TOOLS}
- [UNDEFINED] HERE
- [IF]
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] HERE [IF]
CODE HERE
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE
[THEN]
\ https://forth-standard.org/standard/core/Plus
\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
- [UNDEFINED] +
- [IF]
+ [UNDEFINED] + [IF]
CODE +
ADD @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
- [UNDEFINED] U.R
- [IF] \ defined in {UTILITY}
- : U.R \ u n -- display u unsigned in n width (n >= 2)
- >R <# 0 # #S #>
- R> OVER - 0 MAX SPACES TYPE
- ;
- [THEN]
-
\ https://forth-standard.org/standard/core/DO
\ DO -- DOadr L: -- 0
[UNDEFINED] DO
ENDCODE IMMEDIATE
[THEN]
-
\ https://forth-standard.org/standard/core/I
\ I -- n R: sys1 sys2 -- sys1 sys2
\ get the innermost loop index
; IS CR
[THEN]
+; ------------------------------------------------------------------
+; then we download the set of definitions we need (from UTILITY.f)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] U.R
+ [IF] \ defined in {UTILITY}
+ : U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+ ;
+ [THEN]
+
\ https://forth-standard.org/standard/tools/DUMP
[UNDEFINED] DUMP
[IF] \ defined in {UTILITY}
ADD @PSP,TOS \ -- ORG END
LO2HI
SWAP \ -- END ORG
-\ $FFF0 AND \ -- END ORG_modulo_16
+ CR
+ 4 SPACES $10 0
+ DO I 3 U.R LOOP \ -- END ORG
DO CR \ generate line
- I 4 U.R SPACE \ generate address
- I 8 + I
- DO I C@ 3 U.R LOOP
- SPACE
- I $10 + I 8 +
+ I 4 U.R \ generate address
+ I $10 + I
DO I C@ 3 U.R LOOP
SPACE SPACE
I $10 + I \ display 16 chars
;
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
\ display content of a sector
+\ to Display MBR_FirstSector, type : 0. SECTOR.
\ --------------------------------\
CODE SECTOR. \ sector. -- don't forget to add decimal point to your sector number
\ --------------------------------\
BW1 MOV TOS,X \ X = SectorH
MOV @PSP,W \ W = sectorL
- CALL #R_SECT_WX \ W = SectorLO X = SectorHI
+ CALL #RD_SECT \ W = SectorLO X = SectorHI
COLON \
SPACE <# #S #> TYPE \ ud -- display the double number
SD_BUF $200 DUMP CR ; \ then dump the sector
MOV TOS,2(PSP) \ save TOS
MOV &DIRclusterL,0(PSP) \
MOV &DIRclusterH,TOS \
- GOTO BW2 \ jump to SECTOR
+ CMP #0,TOS
+ 0<> ?GOTO BW2 \ jump to CLUSTER
+ CMP #1,0(PSP) \ cluster 1 ?
+ 0<> ?GOTO BW2 \ jump to CLUSTER
+ MOV &OrgRootDir,0(PSP) \ if yes, special case of FAT16 OrgRootDir
+ GOTO BW1 \ jump to SECTOR
ENDCODE
\ --------------------------------\
- RST_SET ECHO
+ RST_SET
+
+ [THEN] \ endof [UNDEFINED] {SD_TOOLS}
+
+ ECHO
--- /dev/null
+\ -*- coding: utf-8 -*-
+\
+\ TARGET SELECTION ( = the name of \INC\target.pat file without the extension)
+\ (used by preprocessor GEMA to load the pattern: \inc\TARGET.pat)
+\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
+\ MSP_EXP430FR4133 CHIPSTICK_FR2433 MSP_EXP430FR2433 MSP_EXP430FR2355
+\ LP_MSP430FR2476
+\ MY_MSP430FR5738_2
+\
+\ from scite editor : copy your target selection in (shift+F8) parameter 1:
+\
+\ OR
+\
+\ drag and drop this file onto SendSourceFileToTarget.bat
+\ then select your TARGET when asked.
+\
+\
+\ REGISTERS USAGE
+\ rDODOES to rEXIT must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+\
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT, rDOVAR, rDOCON, rDODOES
+\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack
+\
+\ POPM order : rDODOES, rDOCON, rDOVAR, rEXIT, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM #6,IP pulls Y,X,W,T,S,IP registers from return stack
+\
+\ FORTH conditionnals: unary{ 0= 0< 0> }, binary{ = < > U< }
+\
+\ ASSEMBLER conditionnal usage with IF UNTIL WHILE S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage with ?GOTO S< S>= U< U>= 0= 0<> 0<
+
+ CODE ABORT_CORE_ANS
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV &VERSION,TOS
+ SUB #400,TOS \ FastForth V4.0
+ COLON
+ 'CR' EMIT \ return to column 1, no 'LF'
+ ABORT" FastForth V4.0 please!"
+ ;
+
+ ABORT_CORE_ANS
+
+ [UNDEFINED] BC!
+ [IF]
+\ BC! pattern @ -- Bits Clear in @
+ CODE BC!
+ BIC @PSP+,0(TOS)
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] BS!
+ [IF]
+\ BS! pattern @ -- Bits Set in @
+ CODE BS!
+ BIS @PSP+,0(TOS)
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+\ =============================================================================
+ $8000 KERNEL_ADDON BC! \ uncomment to select SYMMETRIC division
+\ $8000 KERNEL_ADDON BS! \ uncomment to select FLOORED division
+\ =============================================================================
+
+ RST_RET \ remove all above before CORE_ANS downloading
+
+; ----------------------------------
+; CORE_ANS.f
+; ----------------------------------
+\
+\ words complement to pass CORETEST.4TH
+
+ [DEFINED] {TEST}
+ [IF] {TEST} [THEN] \ if already defined removes it before.
+
+ [UNDEFINED] {TEST}
+ [IF]
+
+ MARKER {TEST}
+
+ [UNDEFINED] ABORT
+ [IF]
+\ https://forth-standard.org/standard/core/ABORT
+\ Empty the data stack and perform the function of QUIT
+ CODE ABORT
+ MOV #ABORT,PC \ addr defined in MSP430FRxxxx.pat
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] QUIT
+ [IF]
+\ https://forth-standard.org/standard/core/QUIT
+\ Empty the return stack, store zero in SOURCE-ID if it is present,
+\ make the user input device the input source, and enter interpretation state.
+\ Do not display a message. Repeat the following:
+\ Accept a line from the input source into the input buffer, set >IN to zero, and interpret.
+\ Display the implementation-defined system prompt if in interpretation state,
+\ all processing has been completed,
+\ and no ambiguous condition exists.
+ CODE QUIT
+ MOV #QUIT,PC \ addr defined in MSP430FRxxxx.pat
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] HERE
+ [IF]
+\ https://forth-standard.org/standard/core/HERE
+\ HERE -- addr addr is the data-space pointer.
+ CODE HERE
+ MOV #BEGIN,PC \ execute ASM BEGIN
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] +
+ [IF]
+\ https://forth-standard.org/standard/core/Plus
+\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
+ CODE +
+ ADD @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] -
+ [IF]
+\ https://forth-standard.org/standard/core/Minus
+\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
+ CODE -
+ SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3)
+ XOR #-1,TOS \ 1
+ ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DUP
+ [IF] \ define DUP and ?DUP
+
+\ https://forth-standard.org/standard/core/DUP
+\ DUP x -- x x duplicate top of stack
+ CODE DUP
+BW1 SUB #2,PSP \ 2 push old TOS..
+ MOV TOS,0(PSP) \ 3 ..onto stack
+ MOV @IP+,PC \ 4
+ ENDCODE
+
+\ https://forth-standard.org/standard/core/qDUP
+\ ?DUP x -- 0 | x x DUP if nonzero
+ CODE ?DUP
+ CMP #0,TOS \ 2 test for TOS nonzero
+ 0<> ?GOTO BW1 \ 2
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] EXIT
+ [IF]
+\ https://forth-standard.org/standard/core/EXIT
+\ EXIT -- exit a colon definition
+ CODE EXIT
+ MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack
+ MOV @IP+,PC \ 4 = NEXT
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DEPTH
+ [IF]
+\ https://forth-standard.org/standard/core/DEPTH
+\ DEPTH -- +n number of items on stack, must leave 0 if stack empty
+ CODE DEPTH
+ MOV TOS,-2(PSP)
+ MOV #PSTACK,TOS
+ SUB PSP,TOS \ PSP-S0--> TOS
+ RRA TOS \ TOS/2 --> TOS
+ SUB #2,PSP \ post decrement stack...
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] SWAP
+ [IF]
+\ https://forth-standard.org/standard/core/SWAP
+\ SWAP x1 x2 -- x2 x1 swap top two items
+ CODE SWAP
+ PUSH TOS \ 3
+ MOV @PSP,TOS \ 2
+ MOV @RSP+,0(PSP) \ 4
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DROP
+ [IF]
+\ https://forth-standard.org/standard/core/DROP
+\ DROP x -- drop top of stack
+ CODE DROP
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] OVER
+ [IF]
+\ https://forth-standard.org/standard/core/OVER
+\ OVER x1 x2 -- x1 x2 x1
+ CODE OVER
+ MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
+ MOV @PSP,TOS \ 2 -- x1 (x2) x1
+ SUB #2,PSP \ 1 -- x1 x2 x1
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] NIP
+ [IF]
+\ https://forth-standard.org/standard/core/NIP
+\ NIP x1 x2 -- x2 Drop the first item below the top of stack
+ CODE NIP
+ ADD #2,PSP
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] >R
+ [IF]
+\ https://forth-standard.org/standard/core/toR
+\ >R x -- R: -- x push to return stack
+ CODE >R
+ PUSH TOS
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] R>
+ [IF]
+\ https://forth-standard.org/standard/core/Rfrom
+\ R> -- x R: x -- pop from return stack
+ CODE R>
+ SUB #2,PSP \ 1
+ MOV TOS,0(PSP) \ 3
+ MOV @RSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C@
+ [IF]
+\ https://forth-standard.org/standard/core/Fetch
+\ C@ c-addr -- char fetch char from memory
+ CODE C@
+ MOV.B @TOS,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C!
+ [IF]
+\ https://forth-standard.org/standard/core/CStore
+\ C! char c-addr -- store char in memory
+ CODE C!
+ MOV.B @PSP+,0(TOS) \ 4
+ ADD #1,PSP \ 1
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C,
+ [IF]
+\ https://forth-standard.org/standard/core/CComma
+\ C, char -- append char
+ CODE C,
+ MOV &DP,W
+ MOV.B TOS,0(W)
+ ADD #1,&DP
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 0=
+ [IF]
+\ https://forth-standard.org/standard/core/ZeroEqual
+\ 0= n/u -- flag return true if TOS=0
+ CODE 0=
+ SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0
+ SUBC TOS,TOS \ 1 TOS=-1 if borrow was set
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 0<>
+ [IF]
+\ https://forth-standard.org/standard/core/Zerone
+\ 0<> n/u -- flag return true if TOS<>0
+ CODE 0<>
+ SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0
+ SUBC TOS,TOS \ 1 TOS=-1 if borrow was set
+ XOR #-1,TOS \ 1
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 0<
+ [IF]
+\ https://forth-standard.org/standard/core/Zeroless
+\ 0< n -- flag true if TOS negative
+ CODE 0<
+ ADD TOS,TOS \ 1 set carry if TOS negative
+ SUBC TOS,TOS \ 1 TOS=-1 if carry was clear
+ XOR #-1,TOS \ 1 TOS=-1 if carry was set
+ MOV @IP+,PC \
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] S>D
+ [IF]
+\ https://forth-standard.org/standard/core/StoD
+\ S>D n -- d single -> double prec.
+ : S>D
+ DUP 0<
+ ;
+ [THEN]
+
+ [UNDEFINED] =
+ [IF]
+\ https://forth-standard.org/standard/core/Equal
+\ = x1 x2 -- flag test x1=x2
+ CODE =
+ SUB @PSP+,TOS \ 2
+ SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0
+ SUBC TOS,TOS \ 1 TOS=-1 if borrow was set
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] U<
+ [IF]
+
+\ https://forth-standard.org/standard/core/Umore
+\ U> n1 n2 -- flag
+ CODE U>
+ SUB @PSP+,TOS \ 2
+ U< ?GOTO FW1 \ 2 flag = true, Z = 0
+BW1 AND #0,TOS \ 1 Z = 1
+ MOV @IP+,PC \ 4
+ ENDCODE
+
+\ https://forth-standard.org/standard/core/Uless
+\ U< u1 u2 -- flag test u1<u2, unsigned
+ CODE U<
+ SUB @PSP+,TOS \ 2 u2-u1
+ 0= ?GOTO BW1
+ U< ?GOTO BW1
+FW1 MOV #-1,TOS \ 1
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] <
+ [IF] \ define < and >
+
+\ https://forth-standard.org/standard/core/more
+\ > n1 n2 -- flag test n1>n2, signed
+ CODE >
+ SUB @PSP+,TOS \ 2 TOS=n2-n1
+ S< ?GOTO FW1 \ 2 --> +5
+BW1 AND #0,TOS \ 1 flag Z = 1
+ MOV @IP+,PC
+ ENDCODE
+
+\ https://forth-standard.org/standard/core/less
+\ < n1 n2 -- flag test n1<n2, signed
+ CODE <
+ SUB @PSP+,TOS \ 1 TOS=n2-n1
+ 0= ?GOTO BW1
+ S< ?GOTO BW1 \ 2 signed
+FW1 MOV #-1,TOS \ 1 flag Z = 0
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+\ ------------------------------------------------------------------------------
+\ CONTROL STRUCTURES
+\ ------------------------------------------------------------------------------
+\ THEN and BEGIN compile nothing
+\ DO compile one word
+\ IF, ELSE, AGAIN, UNTIL, WHILE, REPEAT, LOOP & +LOOP compile two words
+\ LEAVE compile three words
+\
+ [UNDEFINED] IF
+ [IF] \ define IF THEN
+
+\ https://forth-standard.org/standard/core/IF
+\ IF -- IFadr initialize conditional forward branch
+ CODE IF
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \
+ MOV &DP,TOS \ -- HERE
+ ADD #4,&DP \ compile one word, reserve one word
+ MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN
+ ADD #2,TOS \ -- HERE+2=IFadr
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/THEN
+\ THEN IFadr -- resolve forward branch
+ CODE THEN
+ MOV &DP,0(TOS) \ -- IFadr
+ MOV @PSP+,TOS \ --
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] ELSE
+ [IF]
+\ https://forth-standard.org/standard/core/ELSE
+\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
+ CODE ELSE
+ ADD #4,&DP \ make room to compile two words
+ MOV &DP,W \ W=HERE+4
+ MOV #BRAN,-4(W)
+ MOV W,0(TOS) \ HERE+4 ==> [IFadr]
+ SUB #2,W \ HERE+2
+ MOV W,TOS \ -- ELSEadr
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] BEGIN
+ [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
+
+\ https://forth-standard.org/standard/core/BEGIN
+\ BEGIN -- BEGINadr initialize backward branch
+ CODE BEGIN
+ MOV #BEGIN,PC \ execute ASM BEGIN !
+ ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/UNTIL
+\ UNTIL BEGINadr -- resolve conditional backward branch
+ CODE UNTIL
+ MOV #QFBRAN,X
+BW1 ADD #4,&DP \ compile two words
+ MOV &DP,W \ W = HERE
+ MOV X,-4(W) \ compile Bran or QFBRAN at HERE
+ MOV TOS,-2(W) \ compile bakcward adr at HERE+2
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/AGAIN
+\ AGAIN BEGINadr -- resolve uncondionnal backward branch
+ CODE AGAIN
+ MOV #BRAN,X
+ GOTO BW1
+ ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/WHILE
+\ WHILE BEGINadr -- WHILEadr BEGINadr
+ : WHILE
+ POSTPONE IF SWAP
+ ; IMMEDIATE
+
+\ https://forth-standard.org/standard/core/REPEAT
+\ REPEAT WHILEadr BEGINadr -- resolve WHILE loop
+ : REPEAT
+ POSTPONE AGAIN POSTPONE THEN
+ ; IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] DO
+ [IF] \ define DO LOOP +LOOP
+
+ HDNCODE XDO \ DO run time
+ MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor"
+ SUB @PSP+,X \ 2
+ MOV TOS,Y \ 1 loop ctr = index+fudge
+ ADD X,Y \ 1 Y = INDEX
+ PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ ENDCODE
+
+\ https://forth-standard.org/standard/core/DO
+\ DO -- DOadr L: -- 0
+ CODE DO
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \
+ ADD #2,&DP \ make room to compile xdo
+ MOV &DP,TOS \ -- HERE+2
+ MOV #XDO,-2(TOS) \ compile xdo
+ ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2
+ MOV &LEAVEPTR,W \
+ MOV #0,0(W) \ -- HERE+2 L-- 0, init
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+
+ HDNCODE XLOOP \ LOOP run time
+ ADD #1,0(RSP) \ 4 increment INDEX
+BW1 BIT #$100,SR \ 2 is overflow bit set?
+ 0= IF \ branch if no overflow
+ MOV @IP,IP
+ MOV @IP+,PC
+ THEN
+ ADD #4,RSP \ 1 empties RSP
+ ADD #2,IP \ 1 overflow = loop done, skip branch ofs
+ MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop
+ ENDCODE \
+
+\ https://forth-standard.org/standard/core/LOOP
+\ LOOP DOadr -- L-- an an-1 .. a1 0
+ CODE LOOP
+ MOV #XLOOP,X
+BW2 ADD #4,&DP \ make room to compile two words
+ MOV &DP,W
+ MOV X,-4(W) \ xloop --> HERE
+ MOV TOS,-2(W) \ DOadr --> HERE+2
+ BEGIN \ resolve all "leave" adr
+ MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell
+ SUB #2,&LEAVEPTR \ --
+ MOV @TOS,TOS \ -- first LeaveStack value
+ CMP #0,TOS \ -- = value left by DO ?
+ 0<> WHILE
+ MOV W,0(TOS) \ move adr after loop as UNLOOP adr
+ REPEAT
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/PlusLOOP
+\ +LOOP adrs -- L-- an an-1 .. a1 0
+ HDNCODE XPLOO \ +LOOP run time
+ ADD TOS,0(RSP) \ 4 increment INDEX by TOS value
+ MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags
+ GOTO BW1 \ 2
+ ENDCODE \
+
+ CODE +LOOP
+ MOV #XPLOO,X
+ GOTO BW2
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] I
+ [IF]
+\ https://forth-standard.org/standard/core/I
+\ I -- n R: sys1 sys2 -- sys1 sys2
+\ get the innermost loop index
+ CODE I
+ SUB #2,PSP \ 1 make room in TOS
+ MOV TOS,0(PSP) \ 3
+ MOV @RSP,TOS \ 2 index = loopctr - fudge
+ SUB 2(RSP),TOS \ 3
+ MOV @IP+,PC \ 4 13~
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] J
+ [IF]
+\ https://forth-standard.org/standard/core/J
+\ J -- n R: 4*sys -- 4*sys
+\ C get the second loop index
+ CODE J
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV 4(RSP),TOS
+ SUB 6(RSP),TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] UNLOOP
+ [IF]
+\ https://forth-standard.org/standard/core/UNLOOP
+\ UNLOOP -- R: sys1 sys2 -- drop loop parms
+ CODE UNLOOP
+ ADD #4,RSP
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] LEAVE
+ [IF]
+\ https://forth-standard.org/standard/core/LEAVE
+\ LEAVE -- L: -- adrs
+ CODE LEAVE
+ MOV &DP,W \ compile three words
+ MOV #UNLOOP,0(W) \ [HERE] = UNLOOP
+ MOV #BRAN,2(W) \ [HERE+2] = BRAN
+ ADD #6,&DP \ [HERE+4] = at adr After LOOP
+ ADD #2,&LEAVEPTR
+ ADD #4,W
+ MOV &LEAVEPTR,X
+ MOV W,0(X) \ leave HERE+4 on LEAVEPTR stack
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] AND
+ [IF]
+\ https://forth-standard.org/standard/core/AND
+\ C AND x1 x2 -- x3 logical AND
+ CODE AND
+ AND @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] OR
+ [IF]
+\ https://forth-standard.org/standard/core/OR
+\ C OR x1 x2 -- x3 logical OR (BIS, BIts Set)
+ CODE OR
+ BIS @PSP+,TOS
+ AND #-1,TOS \ to set flags
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] XOR
+ [IF]
+\ https://forth-standard.org/standard/core/XOR
+\ C XOR x1 x2 -- x3 logical XOR
+ CODE XOR
+ XOR @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 1+
+ [IF]
+\ https://forth-standard.org/standard/core/OnePlus
+\ 1+ n1/u1 -- n2/u2 add 1 to TOS
+ CODE 1+
+ ADD #1,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 1-
+ [IF]
+\ https://forth-standard.org/standard/core/OneMinus
+\ 1- n1/u1 -- n2/u2 subtract 1 from TOS
+ CODE 1-
+ SUB #1,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] INVERT
+ [IF]
+\ https://forth-standard.org/standard/core/INVERT
+\ INVERT x1 -- x2 bitwise inversion
+ CODE INVERT
+ XOR #-1,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] NEGATE
+ [IF]
+\ https://forth-standard.org/standard/core/NEGATE
+\ C NEGATE x1 -- x2 two's complement
+ CODE NEGATE
+ XOR #-1,TOS
+ ADD #1,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] ABS
+ [IF]
+\ https://forth-standard.org/standard/core/ABS
+\ C ABS n1 -- +n2 absolute value
+ CODE ABS
+ CMP #0,TOS \ 1
+ 0>= IF
+ MOV @IP+,PC
+ THEN
+ MOV #NEGATE,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] LSHIFT
+ [IF]
+\ https://forth-standard.org/standard/core/LSHIFT
+\ LSHIFT x1 u -- x2 logical L shift u places
+ CODE LSHIFT
+ MOV @PSP+,W
+ AND #$1F,TOS \ no need to shift more than 16
+ 0<> IF
+ BEGIN
+ ADD W,W
+ SUB #1,TOS
+ 0= UNTIL
+ THEN
+ MOV W,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] RSHIFT
+ [IF]
+\ https://forth-standard.org/standard/core/RSHIFT
+\ RSHIFT x1 u -- x2 logical R7 shift u places
+ CODE RSHIFT
+ MOV @PSP+,W
+ AND #$1F,TOS \ no need to shift more than 16
+ 0<> IF
+ BEGIN
+ BIC #C,SR \ Clr Carry
+ RRC W
+ SUB #1,TOS
+ 0= UNTIL
+ THEN
+ MOV W,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] MAX
+ [IF]
+\ https://forth-standard.org/standard/core/MAX
+\ MAX n1 n2 -- n3 signed maximum
+ CODE MAX
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ ENDCODE
+
+\ https://forth-standard.org/standard/core/MIN
+\ MIN n1 n2 -- n3 signed minimum
+ CODE MIN
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2*
+ [IF]
+\ https://forth-standard.org/standard/core/TwoTimes
+\ 2* x1 -- x2 arithmetic left shift
+ CODE 2*
+ ADD TOS,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2/
+ [IF]
+\ https://forth-standard.org/standard/core/TwoDiv
+\ 2/ x1 -- x2 arithmetic right shift
+ CODE 2/
+ RRA TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+\ --------------------
+\ ARITHMETIC OPERATORS
+\ --------------------
+ RST_SET
+
+ CODE TSTBIT \ addr bit_mask -- true/flase flag
+ MOV @PSP+,X
+ AND @X,TOS
+ MOV @IP+,PC
+ ENDCODE
+
+\ $81EF DEVICEID @ U<
+\ DEVICEID @ $81F3 U<
+\ = [IF] ; MSP430FR413x subfamily without hardware_MPY
+ KERNEL_ADDON HMPY TSTBIT \ KERNEL_ADDON(BIT0) = hardware MPY flag
+
+ RST_RET
+
+ [IF] ; MSP430FR413x subfamily with hardware_MPY
+
+ [UNDEFINED] UM*
+ [IF]
+\ https://forth-standard.org/standard/core/MTimes
+\ M* n1 n2 -- dlo dhi signed 16*16->32 multiply
+ CODE UM*
+ MOV @PSP,&MPY \ Load 1st operand for unsigned multiplication
+BW1 MOV TOS,&OP2 \ Load 2nd operand
+ MOV &RES0,0(PSP) \ low result on stack
+ MOV &RES1,TOS \ high result in TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] M*
+ [IF]
+\ https://forth-standard.org/standard/core/MTimes
+\ M* n1 n2 -- dlo dhi signed 16*16->32 multiply
+ CODE M*
+ MOV @PSP,&MPYS \ Load 1st operand for signed multiplication
+ GOTO BW1
+ ENDCODE
+ [THEN]
+
+ [ELSE] ; MSP430FRxxxx without hardware_MPY
+
+ [UNDEFINED] M*
+ [IF]
+\ https://forth-standard.org/standard/core/UMTimes
+\ UM* u1 u2 -- udlo udhi unsigned 16x16->32 mult.
+ CODE M*
+ MOV @PSP,S \ S= n1
+ CMP #0,S \ n1 > -1 ?
+ S< IF
+ XOR #-1,0(PSP) \ n1 --> u1
+ ADD #1,0(PSP) \
+ THEN
+ XOR TOS,S \ S contains sign of result
+ CMP #0,TOS \ n2 > -1 ?
+ S< IF
+ XOR #-1,TOS \ n2 --> u2
+ ADD #1,TOS \
+ THEN
+ PUSHM #2,IP \ UMSTAR use S,T,W,X,Y
+ LO2HI \ -- ud1 u2
+ UM*
+ HI2LO
+ POPM #2,IP \ pop S,IP
+ CMP #0,S \ sign of result > -1 ?
+ S< IF
+ XOR #-1,0(PSP) \ ud --> d
+ XOR #-1,TOS
+ ADD #1,0(PSP)
+ ADDC #0,TOS
+ THEN
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+ [THEN] ; endof hardware_MPY
+
+ [UNDEFINED] UM/MOD
+ [IF]
+\ https://forth-standard.org/standard/core/UMDivMOD
+\ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16
+ CODE UM/MOD
+ PUSH #DROP \
+ MOV #MUSMOD,PC \ execute MUSMOD then return to DROP
+ ENDCODE
+ [THEN]
+
+ KERNEL_ADDON @ 0< ; test the switch: FLOORED / SYMETRIC DIVISION
+ [IF]
+ [UNDEFINED] FM/MOD
+ [IF]
+\ https://forth-standard.org/standard/core/FMDivMOD
+\ FM/MOD d1 n1 -- r q floored signed div'n
+ CODE FM/MOD
+ MOV TOS,S \ S=DIV
+ MOV @PSP,T \ T=DVDhi
+ CMP #0,TOS \ n2 >= 0 ?
+ S< IF \
+ XOR #-1,TOS
+ ADD #1,TOS \ -- d1 u2
+ THEN
+ CMP #0,0(PSP) \ d1hi >= 0 ?
+ S< IF \
+ XOR #-1,2(PSP) \ d1lo
+ XOR #-1,0(PSP) \ d1hi
+ ADD #1,2(PSP) \ d1lo+1
+ ADDC #0,0(PSP) \ d1hi+C
+ THEN \ -- uDVDlo uDVDhi uDIVlo
+ PUSHM #2,S \ 4 PUSHM S,T
+ CALL #MUSMOD
+ MOV @PSP+,TOS
+ POPM #2,S \ 4 POPM T,S
+ CMP #0,T \ T=DVDhi --> REM_sign
+ S< IF
+ XOR #-1,0(PSP)
+ ADD #1,0(PSP)
+ THEN
+ XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign
+ CMP #0,T \ -- n3 u4 T=quot_sign
+ S< IF
+ XOR #-1,TOS
+ ADD #1,TOS
+ THEN \ -- n3 n4 S=divisor
+
+ CMP #0,0(PSP) \ remainder <> 0 ?
+ 0<> IF
+ CMP #1,TOS \ quotient < 1 ?
+ S< IF
+ ADD S,0(PSP) \ add divisor to remainder
+ SUB #1,TOS \ decrement quotient
+ THEN
+ THEN
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+ [ELSE]
+ [UNDEFINED] SM/REM
+ [IF]
+\ https://forth-standard.org/standard/core/SMDivREM
+\ SM/REM DVDlo DVDhi DIV -- r3 q4 symmetric signed div
+ CODE SM/REM
+ MOV TOS,S \ S=DIV
+ MOV @PSP,T \ T=DVDhi
+ CMP #0,TOS \ n2 >= 0 ?
+ S< IF \
+ XOR #-1,TOS
+ ADD #1,TOS \ -- d1 u2
+ THEN
+ CMP #0,0(PSP) \ d1hi >= 0 ?
+ S< IF \
+ XOR #-1,2(PSP) \ d1lo
+ XOR #-1,0(PSP) \ d1hi
+ ADD #1,2(PSP) \ d1lo+1
+ ADDC #0,0(PSP) \ d1hi+C
+ THEN \ -- uDVDlo uDVDhi uDIVlo
+ PUSHM #2,S \ 4 PUSHM S,T
+ CALL #MUSMOD
+ MOV @PSP+,TOS
+ POPM #2,S \ 4 POPM T,S
+ CMP #0,T \ T=DVDhi --> REM_sign
+ S< IF
+ XOR #-1,0(PSP)
+ ADD #1,0(PSP)
+ THEN
+ XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign
+ CMP #0,T \ -- n3 u4 T=quot_sign
+ S< IF
+ XOR #-1,TOS
+ ADD #1,TOS
+ THEN \ -- n3 n4 S=divisor
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+ [THEN]
+
+ [UNDEFINED] *
+ [IF]
+\ https://forth-standard.org/standard/core/Times
+\ * n1 n2 -- n3 signed multiply
+ : *
+ M* DROP
+ ;
+ [THEN]
+
+ [UNDEFINED] /MOD
+ [IF]
+\ https://forth-standard.org/standard/core/DivMOD
+\ /MOD n1 n2 -- r3 q4 signed division
+ : /MOD
+ >R DUP 0< R>
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ ;
+ [THEN]
+
+ [UNDEFINED] /
+ [IF]
+\ https://forth-standard.org/standard/core/Div
+\ / n1 n2 -- n3 signed quotient
+ : /
+ >R DUP 0< R>
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ NIP
+ ;
+ [THEN]
+
+ [UNDEFINED] MOD
+ [IF]
+\ https://forth-standard.org/standard/core/MOD
+\ MOD n1 n2 -- n3 signed remainder
+ : MOD
+ >R DUP 0< R>
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ DROP
+ ;
+ [THEN]
+
+ [UNDEFINED] */MOD
+ [IF]
+\ https://forth-standard.org/standard/core/TimesDivMOD
+\ */MOD n1 n2 n3 -- r4 q5 signed mult/div
+ : */MOD
+ >R M* R>
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ ;
+ [THEN]
+
+ [UNDEFINED] */
+ [IF]
+\ https://forth-standard.org/standard/core/TimesDiv
+\ */ n1 n2 n3 -- n4 n1*n2/q3
+ : */
+ >R M* R>
+ [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION
+ [IF] FM/MOD
+ [ELSE] SM/REM
+ [THEN]
+ NIP
+ ;
+ [THEN]
+
+\ -------------------------------------------------------------------------------
+\ STACK OPERATIONS
+\ -------------------------------------------------------------------------------
+ [UNDEFINED] ROT
+ [IF]
+\ https://forth-standard.org/standard/core/ROT
+\ ROT x1 x2 x3 -- x2 x3 x1
+ CODE ROT
+ MOV @PSP,W \ 2 fetch x2
+ MOV TOS,0(PSP) \ 3 store x3
+ MOV 2(PSP),TOS \ 3 fetch x1
+ MOV W,2(PSP) \ 3 store x2
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] R@
+ [IF]
+\ https://forth-standard.org/standard/core/RFetch
+\ R@ -- x R: x -- x fetch from return stack
+ CODE R@
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV @RSP,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] TUCK
+ [IF]
+\ https://forth-standard.org/standard/core/TUCK
+\ TUCK ( x1 x2 -- x2 x1 x2 )
+ : TUCK SWAP OVER ;
+ [THEN]
+
+\ ----------------------------------------------------------------------
+\ DOUBLE OPERATORS
+\ ----------------------------------------------------------------------
+ [UNDEFINED] 2@
+ [IF]
+\ https://forth-standard.org/standard/core/TwoFetch
+\ 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack
+ CODE 2@
+ SUB #2,PSP
+ MOV 2(TOS),0(PSP)
+ MOV @TOS,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2!
+ [IF]
+\ https://forth-standard.org/standard/core/TwoStore
+\ 2! x1 x2 a-addr -- store 2 cells ; the top of stack is stored at the lower adr
+ CODE 2!
+ MOV @PSP+,0(TOS)
+ MOV @PSP+,2(TOS)
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2DUP
+ [IF]
+\ https://forth-standard.org/standard/core/TwoDUP
+\ 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells
+ CODE 2DUP
+ MOV TOS,-2(PSP) \ 3
+ MOV @PSP,-4(PSP) \ 4
+ SUB #4,PSP \ 1
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2DROP
+ [IF]
+\ https://forth-standard.org/standard/core/TwoDROP
+\ 2DROP x1 x2 -- drop 2 cells
+ CODE 2DROP
+ ADD #2,PSP
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2SWAP
+ [IF]
+\ https://forth-standard.org/standard/core/TwoSWAP
+\ 2SWAP x1 x2 x3 x4 -- x3 x4 x1 x2
+ CODE 2SWAP
+ MOV @PSP,W \ -- x1 x2 x3 x4 W=x3
+ MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x4
+ MOV W,4(PSP) \ -- x3 x2 x1 x4
+ MOV TOS,W \ -- x3 x2 x1 x4 W=x4
+ MOV 2(PSP),TOS \ -- x3 x2 x1 x2 W=x4
+ MOV W,2(PSP) \ -- x3 x4 x1 x2
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2OVER
+ [IF]
+\ https://forth-standard.org/standard/core/TwoOVER
+\ 2OVER x1 x2 x3 x4 -- x1 x2 x3 x4 x1 x2
+ CODE 2OVER
+ SUB #4,PSP \ -- x1 x2 x3 x x x4
+ MOV TOS,2(PSP) \ -- x1 x2 x3 x4 x x4
+ MOV 8(PSP),0(PSP) \ -- x1 x2 x3 x4 x1 x4
+ MOV 6(PSP),TOS \ -- x1 x2 x3 x4 x1 x2
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+\ ----------------------------------------------------------------------
+\ ALIGNMENT OPERATORS
+\ ----------------------------------------------------------------------
+ [UNDEFINED] ALIGNED
+ [IF]
+\ https://forth-standard.org/standard/core/ALIGNED
+\ ALIGNED addr -- a-addr align given addr
+ CODE ALIGNED
+ BIT #1,TOS
+ ADDC #0,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] ALIGN
+ [IF]
+\ https://forth-standard.org/standard/core/ALIGN
+\ ALIGN -- align HERE
+ CODE ALIGN
+ BIT #1,&DP \ 3
+ ADDC #0,&DP \ 4
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+\ ---------------------
+\ PORTABILITY OPERATORS
+\ ---------------------
+ [UNDEFINED] CHARS
+ [IF]
+\ https://forth-standard.org/standard/core/CHARS
+\ CHARS n1 -- n2 chars->adrs units
+ CODE CHARS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CHAR+
+ [IF]
+\ https://forth-standard.org/standard/core/CHARPlus
+\ CHAR+ c-addr1 -- c-addr2 add char size
+ CODE CHAR+
+ ADD #1,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CELLS
+ [IF]
+\ https://forth-standard.org/standard/core/CELLS
+\ CELLS n1 -- n2 cells->adrs units
+ CODE CELLS
+ ADD TOS,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CELL+
+ [IF]
+\ https://forth-standard.org/standard/core/CELLPlus
+\ CELL+ a-addr1 -- a-addr2 add cell size
+ CODE CELL+
+ ADD #2,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+\ ---------------------------
+\ BLOCK AND STRING COMPLEMENT
+\ ---------------------------
+ [UNDEFINED] CHAR
+ [IF]
+\ https://forth-standard.org/standard/core/CHAR
+\ CHAR -- char parse ASCII character
+ : CHAR
+ $20 WORD 1+ C@
+ ;
+ [THEN]
+
+ [UNDEFINED] [CHAR]
+ [IF]
+\ https://forth-standard.org/standard/core/BracketCHAR
+\ [CHAR] -- compile character literal
+ : [CHAR]
+ CHAR POSTPONE LITERAL
+ ; IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] +!
+ [IF]
+\ https://forth-standard.org/standard/core/PlusStore
+\ +! n/u a-addr -- add n/u to memory
+ CODE +!
+ ADD @PSP+,0(TOS)
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] MOVE
+ [IF]
+\ https://forth-standard.org/standard/core/MOVE
+\ MOVE addr1 addr2 u -- smart move
+\ VERSION FOR 1 ADDRESS UNIT = 1 CHAR
+ CODE MOVE
+ MOV TOS,W \ W = cnt
+ MOV @PSP+,Y \ Y = addr2 = dst
+ MOV @PSP+,X \ X = addr1 = src
+ MOV @PSP+,TOS \ pop new TOS
+ CMP #0,W \ count = 0 ?
+ 0<> IF \ if 0, already done !
+ CMP X,Y \ dst = src ?
+ 0<> IF \ if 0, already done !
+ U< IF \ U< if src > dst
+ BEGIN \ copy W bytes
+ MOV.B @X+,0(Y)
+ ADD #1,Y
+ SUB #1,W
+ 0= UNTIL
+ MOV @IP+,PC \ out 1 of MOVE ====>
+ THEN \ U>= if dst > src
+ ADD W,Y \ copy W bytes beginning with the end
+ ADD W,X
+ BEGIN
+ SUB #1,X
+ SUB #1,Y
+ MOV.B @X,0(Y)
+ SUB #1,W
+ 0= UNTIL
+ THEN
+ THEN
+ MOV @IP+,PC \ out 2 of MOVE ====>
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] FILL
+ [IF]
+\ https://forth-standard.org/standard/core/FILL
+\ FILL c-addr u char -- fill memory with char
+ CODE FILL
+ MOV @PSP+,X \ count
+ MOV @PSP+,W \ address
+ CMP #0,X
+ 0<> IF
+ BEGIN
+ MOV.B TOS,0(W) \ store char in memory
+ ADD #1,W
+ SUB #1,X
+ 0= UNTIL
+ THEN
+ MOV @PSP+,TOS \ empties stack
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+\ --------------------
+\ INTERPRET COMPLEMENT
+\ --------------------
+ [UNDEFINED] HEX
+ [IF]
+\ https://forth-standard.org/standard/core/HEX
+ CODE HEX
+ MOV #$10,&BASEADR
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] DECIMAL
+ [IF]
+ \ https://forth-standard.org/standard/core/DECIMAL
+ CODE DECIMAL
+ MOV #$0A,&BASEADR
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] ( ; )
+ [IF]
+\ https://forth-standard.org/standard/core/p
+\ ( -- skip input until char ) or EOL
+ : (
+ ')' WORD DROP
+ ; IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] .( ; "
+ [IF]
+\ https://forth-standard.org/standard/core/Dotp
+\ .( -- type comment immediatly.
+ CODE .( ; "
+ PUSH IP
+ MOV #0,&CAPS \ CAPS OFF
+ LO2HI
+ ')' WORD
+ COUNT TYPE
+ HI2LO
+ MOV #$20,&CAPS \ CAPS ON
+ MOV @RSP+,IP
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] >BODY
+ [IF]
+\ https://forth-standard.org/standard/core/toBODY
+\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word
+ CODE >BODY
+ ADD #4,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] EXECUTE
+ [IF]
+\ https://forth-standard.org/standard/core/EXECUTE
+\ EXECUTE i*x xt -- j*x execute Forth word at 'xt'
+ CODE EXECUTE
+ PUSH TOS \ 3 push xt
+ MOV @PSP+,TOS \ 2
+ MOV @RSP+,PC \ 4 xt --> PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] EVALUATE
+ [IF]
+
+\ EVALUATE upside down...
+ CODENNM \ as the end of EVALUATE
+ MOV @RSP+,&TOIN \ 4
+ MOV @RSP+,&SOURCE_ORG \ 4
+ MOV @RSP+,&SOURCE_LEN \ 4
+ MOV @RSP+,IP
+ MOV @IP+,PC
+ ENDCODE \ -- end_of_EVALUATE_addr
+
+\ https://forth-standard.org/standard/core/EVALUATE
+\ EVALUATE \ i*x c-addr u -- j*x interpret string
+ CODE EVALUATE
+ MOV #SOURCE_LEN,X \ 2
+ MOV @X+,S \ 2 S = SOURCE_LEN
+ MOV @X+,T \ 2 T = SOURCE_ORG
+ MOV @X+,W \ 2 W = TOIN
+ PUSHM #4,IP \ 6 PUSHM IP,S,T,W
+ MOV PC,IP \ 1
+ ADD #8,IP \ 1 IP = address compiled after ENDCODE
+ MOV #INTERPRET,PC \ 3 addr defined in MSP430FRxxxx.pat
+ NOP \ 1 stuffing instruction
+ ENDCODE \
+ , \ end_of_EVALUATE_addr -- compile the end_of_EVALUATE_addr
+
+ [THEN]
+
+ [UNDEFINED] RECURSE
+ [IF]
+\ https://forth-standard.org/standard/core/RECURSE
+\ C RECURSE -- recurse to current definition
+ CODE RECURSE
+ MOV &DP,X
+ MOV &LAST_CFA,0(X)
+ ADD #2,&DP
+ MOV @IP+,PC
+ ENDCODE IMMEDIATE
+ [THEN]
+
+ [UNDEFINED] SOURCE
+ [IF]
+\ https://forth-standard.org/standard/core/SOURCE
+\ SOURCE -- adr u of current input buffer
+ CODE SOURCE
+ SUB #4,PSP
+ MOV TOS,2(PSP)
+ MOV &SOURCE_LEN,TOS
+ MOV &SOURCE_ORG,0(PSP)
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] VARIABLE
+ [IF]
+\ https://forth-standard.org/standard/core/VARIABLE
+\ VARIABLE <name> -- define a Forth VARIABLE
+ : VARIABLE
+ CREATE
+ HI2LO
+ MOV #DOVAR,-4(W) \ CFA = CALL rDOVAR
+ MOV @RSP+,IP
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CONSTANT
+ [IF]
+\ https://forth-standard.org/standard/core/CONSTANT
+\ CONSTANT <name> n -- define a Forth CONSTANT
+ : CONSTANT
+ CREATE
+ HI2LO
+ MOV TOS,-2(W) \ PFA = n
+ MOV @PSP+,TOS
+ MOV @RSP+,IP
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] STATE
+ [IF]
+\ https://forth-standard.org/standard/core/STATE
+\ STATE -- a-addr holds compiler state
+ STATEADR CONSTANT STATE
+ [THEN]
+
+ [UNDEFINED] BASE
+ [IF]
+\ https://forth-standard.org/standard/core/BASE
+\ BASE -- a-addr holds conversion radix
+ BASEADR CONSTANT BASE
+ [THEN]
+
+ [UNDEFINED] >IN
+ [IF]
+\ https://forth-standard.org/standard/core/toIN
+\ C >IN -- a-addr holds offset in input stream
+ TOIN CONSTANT >IN
+ [THEN]
+
+ [UNDEFINED] PAD
+ [IF]
+\ https://forth-standard.org/standard/core/PAD
+\ PAD -- addr
+ PAD_ORG CONSTANT PAD
+ [THEN]
+
+ [UNDEFINED] BL
+ [IF]
+\ https://forth-standard.org/standard/core/BL
+\ BL -- char an ASCII space
+ 'SP' CONSTANT BL
+ [THEN]
+
+ [UNDEFINED] SPACE
+ [IF]
+\ https://forth-standard.org/standard/core/SPACE
+\ SPACE -- output a space
+ : SPACE
+ 'SP' EMIT ;
+ [THEN]
+
+ [UNDEFINED] SPACES
+ [IF]
+\ https://forth-standard.org/standard/core/SPACES
+\ SPACES n -- output n spaces
+ : SPACES
+ BEGIN
+ ?DUP
+ WHILE
+ 'SP' EMIT
+ 1-
+ REPEAT
+ ;
+ [THEN]
+
+ [UNDEFINED] DEFER
+ [IF]
+\ https://forth-standard.org/standard/core/DEFER
+\ Skip leading space delimiters. Parse name delimited by a space.
+\ Create a definition for name with the execution semantics defined below.
+\
+\ name Execution: --
+\ Execute the xt that name is set to execute, i.e. NEXT (nothing),
+\ until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name.
+ : DEFER
+ CREATE
+ HI2LO
+ MOV #$4030,-4(W) \4 first CELL = MOV @PC+,PC = BR #addr
+ MOV #NEXT_ADR,-2(W) \3 second CELL = ...mNEXT : do nothing by default
+ MOV @RSP+,IP
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CR
+ [IF]
+\ https://forth-standard.org/standard/core/CR
+\ CR -- send CR+LF to the output device
+\ DEFER CR \ DEFERed definition, by default executes :NONAME part
+ CODE CR \ DEFERed definition replaced by this CODE definition
+ MOV #NEXT_ADR,PC
+ ENDCODE
+
+ :NONAME
+ 'CR' EMIT 'LF' EMIT
+ ; IS CR
+ [THEN]
+
+ [UNDEFINED] TO
+ [IF]
+\ https://forth-standard.org/standard/core/TO
+\ TO name Run-time: ( x -- )
+\ Assign the value x to named VALUE.
+ CODE TO
+ BIS #UF9,SR
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] VALUE
+ [IF]
+\ https://forth-standard.org/standard/core/VALUE
+\ ( x "<spaces>name" -- ) define a Forth VALUE
+\ Skip leading space delimiters. Parse name delimited by a space.
+\ Create a definition for name with the execution semantics defined below,
+\ with an initial value equal to x.
+\
+\ name Execution: ( -- x )
+\ Place x on the stack. The value of x is that given when name was created,
+\ until the phrase x TO name is executed, causing a new value of x to be assigned to name.
+ : VALUE \ x "<spaces>name" --
+ CREATE ,
+ DOES>
+ HI2LO
+ MOV @RSP+,IP
+ BIT #UF9,SR \ 2 see TO
+ 0= IF \ 2 if UF9 is not set
+ MOV @TOS,TOS \ 2 execute FETCH
+ MOV @IP+,PC \ 4
+ THEN \ else
+ BIC #UF9,SR \ 2 clear UF9 flag
+ MOV #!,PC \ 4 execute STORE
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CASE
+ [IF] \ define CASE OF ENDOF ENDCASE
+
+\ https://forth-standard.org/standard/core/CASE
+ : CASE 0
+ ; IMMEDIATE \ -- #of-1
+
+\ https://forth-standard.org/standard/core/OF
+ : OF \ #of-1 -- orgOF #of
+ 1+ \ count OFs
+ >R \ move off the stack in case the control-flow stack is the data stack.
+ POSTPONE OVER POSTPONE = \ copy and test case value
+ POSTPONE IF \ add orig to control flow stack
+ POSTPONE DROP \ discards case value if =
+ R> \ we can bring count back now
+ ; IMMEDIATE
+
+\ https://forth-standard.org/standard/core/ENDOF
+ : ENDOF \ orgOF #of -- orgENDOF #of
+ >R \ move off the stack in case the control-flow stack is the data stack.
+ POSTPONE ELSE
+ R> \ we can bring count back now
+ ; IMMEDIATE
+
+\ https://forth-standard.org/standard/core/ENDCASE
+ : ENDCASE \ orgENDOF1..orgENDOFn #of --
+ POSTPONE DROP
+ 0 DO POSTPONE THEN
+ LOOP
+ ; IMMEDIATE
+ [THEN]
+
+ RST_SET
+
+ [THEN]
+
+ ECHO
+
+; CORE_ANS.f is loaded
\
\ FORTH conditionnal : 0= 0< = < > U<
-\ first, we test for downloading driver only if UART TERMINAL target
+\ first, we do some tests allowing the download
CODE ABORT_TEST_ASM
SUB #2,PSP
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
- RST_RET \ remove ABORT_TEST_ASM definition before resuming
+ ABORT" FastForth V4.0 please!"
+\ RST_RET \ remove ABORT_TEST_ASM definition before resuming
;
ABORT_TEST_ASM \ abort test
- MARKER {TEST_ASM}
+ECHO
+
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
[UNDEFINED] >R
[IF]
ENDCODE
[THEN]
- [UNDEFINED] DEFER
- [IF]
-\ https://forth-standard.org/standard/core/DEFER
-\ DEFER "<spaces>name" --
-\Skip leading space delimiters. Parse name delimited by a space.
-\Create a definition for name with the execution semantics defined below.
-
-\name Execution: --
-\Execute the xt that name is set to execute, i.e. NEXT (nothing),
-\until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name.
- : DEFER
- CREATE
- HI2LO
- MOV #$4030,-4(W) \ CFA = MOV @PC+,PC = BR MOV @IP+,PC
- MOV #NEXT_ADR,-2(W) \ PFA = address of MOV @IP+,PC to do nothing.
- MOV @RSP+,IP
- MOV @IP+,PC
- ENDCODE
- [THEN]
-
[UNDEFINED] >BODY
[IF]
\ https://forth-standard.org/standard/core/toBODY
ENDCODE
[THEN]
+ [UNDEFINED] DROP
+ [IF]
+\ https://forth-standard.org/standard/core/DROP
+\ DROP x -- drop top of stack
+ CODE DROP
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
[UNDEFINED] OVER
[IF]
\ https://forth-standard.org/standard/core/OVER
ENDCODE
[THEN]
- [UNDEFINED] U.R
- [IF] \ defined in {UTILITY}
- : U.R \ u n -- display u unsigned in n width (n >= 2)
- >R <# 0 # #S #>
- R> OVER - 0 MAX SPACES TYPE
- ;
- [THEN]
-
\ https://forth-standard.org/standard/core/IF
\ IF -- IFadr initialize conditional forward branch
[UNDEFINED] IF
[IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
CODE BEGIN
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE IMMEDIATE
\ https://forth-standard.org/standard/core/UNTIL
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/BASE
-\ BASE -- a-addr holds conversion radix
[UNDEFINED] BASE
[IF]
+\ https://forth-standard.org/standard/core/BASE
+\ BASE -- a-addr holds conversion radix
BASEADR CONSTANT BASE
[THEN]
\ CR -- send CR+LF to the output device
[UNDEFINED] CR
[IF]
- DEFER CR \ DEFERed definition, by default executes that of :NONAME
+\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition
+ CODE CR \ part I : DEFERed definition of CR
+ MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR
+ ENDCODE
- :NONAME
+ :NONAME \ part II : :NONAME part as default runtime of CR
'CR' EMIT 'LF' EMIT
- ; IS CR
+ ; IS CR \ set [PFA] of CR = >BODY addr of CR = CFA of :NONAME part
+ [THEN]
+
+ [UNDEFINED] C,
+ [IF]
+\ https://forth-standard.org/standard/core/CComma
+\ C, char -- append char
+ CODE C,
+ MOV &DP,W
+ MOV.B TOS,0(W)
+ ADD #1,&DP
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] C@
+ [IF]
+\ https://forth-standard.org/standard/core/CFetch
+\ C@ c-addr -- char fetch char from memory
+ CODE C@
+ MOV.B @TOS,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+; ------------------------------------------------------------------
+; then we download the set of definitions we need (from UTILITY.f)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] U.R
+ [IF] \ defined in {UTILITY}
+ : U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+ ;
[THEN]
[UNDEFINED] DUMP
;
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ECHO
\ -----------------------------------------------------------------------
\ test CPUx instructions PUSHM, POPM, RLAM, RRAM, RRCM, RRUM
\ -----------------------------------------------------------------------
TESTPOPM ; you should see 11111 3 2 1 0 -->
-
\ -----------------------------------------------------------------------
\ test symbolic branch in assembler
\ test a FORTH section encapsulated in an assembly word
\ -----------------------------------------------------------------------
\ tests indexing address
\ -----------------------------------------------------------------------
-
-[UNDEFINED] C, [IF]
-\ https://forth-standard.org/standard/core/CComma
-\ C, char -- append char
-CODE C,
-MOV &DP,W
-MOV.B TOS,0(W)
-ADD #1,&DP
-MOV @PSP+,TOS
-MOV @IP+,PC
-ENDCODE
-[THEN]
-
-[UNDEFINED] C@ [IF]
-\ https://forth-standard.org/standard/core/CFetch
-\ C@ c-addr -- char fetch char from memory
-CODE C@
-MOV.B @TOS,TOS
-MOV @IP+,PC
-ENDCODE
-[THEN]
-
: BYTES_TABLE_IDX
CREATE
0 DO I C,
; create a primary DEFERred assembly word
; -----------------------------------------------------------------------
+\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition
+ CODE TRUC \ part I : DEFERed definition of TRUC
+ MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR
+ ENDCODE
-DEFER TRUC ; here, TRUC is a secondary DEFERred word (i.e. without BODY)
-
-
-CODENNM ; does DUP
+ CODENNM \ part II : :NONAME part as default runtime of TRUC
SUB #2,PSP
MOV TOS,0(PSP)
MOV @IP+,PC
-ENDCODE ; leaves its execution address (CFA) on stack
+ ENDCODE ; leaves its execution address (CFA) on stack
-DUP .
+DUP . ; see it -->
-IS TRUC ; TRUC becomes a primary DEFERred word
- ; with its default action (DUP) located at its BODY addresse.
+IS TRUC ; TRUC becomes a primary DEFERred word
+ ; with its default action (DUP) located at its BODY addresse.
-TRUC . ; display TOS value -->
+TRUC . ; display TOS value -->
+' DROP IS TRUC ; TRUC is redirected to DROP
-\ ' DROP IS TRUC ; TRUC is redirected to DROP
-\
-\ TRUC ; The generated error displays stack empty! in reverse video, removes the TRUC definition and restarts the interpretation after the end of the file. And as you see, FastForth is able to display long lines, interesting, doesn't it? -->
-\
+; TRUC ; The generated error displays stack empty! in reverse video, removes the TRUC definition and restarts the interpretation after the end of the file. And as you see, FastForth is able to display long lines, interesting, doesn't it? -->
' TRUC >BODY IS TRUC ; TRUC is reinitialized with its default action
-
-TRUC . ; display TOS value -->
+TRUC . ; display TOS value -->
\ bla
\ bla
\
\ bla
\ ...
-
-
-
-
SUB #2,PSP
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET \ remove ABORT_TEST_ASM definition before resuming
;
\ CR -- send CR+LF to the output device
[UNDEFINED] CR
[IF]
- DEFER CR \ DEFERed definition, by default executes that of :NONAME
+\ DEFER CR \ DEFERed definition, by default executes that of :NONAME
+\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition
+ CODE CR \ part I : DEFERed definition of CR
+ MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR
+ ENDCODE
:NONAME
'CR' EMIT 'LF' EMIT
[UNDEFINED] HERE
[IF]
CODE HERE
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE
[THEN]
HERE
CODE TT
-MOVA #$0.1,S
+MOVA #$.1,S
ENDCODE
HERE OVER - DUMP
; you should see: 8C 00 01 00
\ MSP-EXP430FR5969_TSTWORDS.f
\ -----------------------------
-\ first, we test for downloading driver only if UART TERMINAL target
+\ first, we do some tests allowing the download
CODE ABORT_TSTWORDS
SUB #2,PSP
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET \ remove ABORT_TEST_ASM definition before resuming
;
ABORT_TSTWORDS \ abort test
- [DEFINED] {TSTWORDS} [IF] {TSTWORDS} [THEN] \ remove it
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
- MARKER {TSTWORDS}
-
-
-\ https://forth-standard.org/standard/core/ZeroEqual
-\ 0= n/u -- flag return true if TOS=0
[UNDEFINED] 0=
[IF]
+\ https://forth-standard.org/standard/core/ZeroEqual
+\ 0= n/u -- flag return true if TOS=0
CODE 0=
SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0
SUBC TOS,TOS \ 1 TOS=-1 if borrow was set
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/IF
-\ IF -- IFadr initialize conditional forward branch
[UNDEFINED] IF
[IF] \ define IF THEN
+\ https://forth-standard.org/standard/core/IF
+\ IF -- IFadr initialize conditional forward branch
CODE IF
SUB #2,PSP \
MOV TOS,0(PSP) \
ENDCODE IMMEDIATE
[THEN]
-\ https://forth-standard.org/standard/core/ELSE
-\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
[UNDEFINED] ELSE
[IF]
+\ https://forth-standard.org/standard/core/ELSE
+\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
CODE ELSE
ADD #4,&DP \ make room to compile two words
MOV &DP,W \ W=HERE+4
ENDCODE IMMEDIATE
[THEN]
-\ https://forth-standard.org/standard/core/SWAP
-\ SWAP x1 x2 -- x2 x1 swap top two items
[UNDEFINED] SWAP
[IF]
+\ https://forth-standard.org/standard/core/SWAP
+\ SWAP x1 x2 -- x2 x1 swap top two items
CODE SWAP
PUSH TOS \ 3
MOV @PSP,TOS \ 2
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/BEGIN
-\ BEGIN -- BEGINadr initialize backward branch
[UNDEFINED] BEGIN
[IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
+\ https://forth-standard.org/standard/core/BEGIN
+\ BEGIN -- BEGINadr initialize backward branch
CODE BEGIN
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE IMMEDIATE
\ https://forth-standard.org/standard/core/UNTIL
MOV @IP+,PC
ENDCODE IMMEDIATE
-\ https://forth-standard.org/standard/core/LOOP
-\ LOOP DOadr -- L-- an an-1 .. a1 0
HDNCODE XLOOP \ LOOP run time
ADD #1,0(RSP) \ 4 increment INDEX
BW1 BIT #$100,SR \ 2 is overflow bit set?
MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop
ENDCODE \
+\ https://forth-standard.org/standard/core/LOOP
+\ LOOP DOadr -- L-- an an-1 .. a1 0
CODE LOOP
MOV #XLOOP,X
BW2 ADD #4,&DP \ make room to compile two words
MOV @IP+,PC
ENDCODE IMMEDIATE
-\ https://forth-standard.org/standard/core/PlusLOOP
-\ +LOOP adrs -- L-- an an-1 .. a1 0
HDNCODE XPLOO \ +LOOP run time
ADD TOS,0(RSP) \ 4 increment INDEX by TOS value
MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags
GOTO BW1 \ 2
ENDCODE \
+\ https://forth-standard.org/standard/core/PlusLOOP
+\ +LOOP adrs -- L-- an an-1 .. a1 0
CODE +LOOP
MOV #XPLOO,X
GOTO BW2
ENDCODE IMMEDIATE
[THEN]
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ECHO
+
+; -----------------------------------------------------------------------
+; test some assembler words and show how to mix FORTH/ASSEMBLER routines
+; -----------------------------------------------------------------------
- RST_SET
-\ -----------------------------------------------------------------------
-\ test some assembler words and show how to mix FORTH/ASSEMBLER routines
-\ -----------------------------------------------------------------------
LOAD" \misc\TestASM.4th"
ECHO
-\ -------------------------------------
-\ here we returned in the TestWords.4th
-\ -------------------------------------
+; -------------------------------------
+; here we returned in the TestWords.4th
+; -------------------------------------
\ ----------
\ LOOP tests
\ KEY EMIT \ wait for a KEY, then emit it
\ ;
\ \ KEY_TEST
-\
\ No newline at end of file
+
\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
\ MSP_EXP430FR4133 (can't use LED1 because wired on UART TX)
\ MSP_EXP430FR2433 CHIPSTICK_FR2433 MSP_EXP430FR2355
-\ LP_MSP430FR2476 MY_MSP430FR5738_1
+\ LP_MSP430FR2476 MY_MSP430FR5738_2
\
\ from scite editor : copy your target selection in (shift+F8) parameter 1:
\
\
\
\ FastForth kernel compilation minimal options:
-\ TERMINAL3WIRES, TERMINAL4WIRES
+\ TERMINAL3WIRES | TERMINAL4WIRES
+\
+\ see symbolic values in \inc\launchpad.pat or/and in \inc\device.pat
\
\ ================================================================================
-\ REGISTERS USAGE for embedded MSP430 ASSEMBLER
+\ coupled to a PL2303HXD/GC/TA cable, this driver enables a FastForth target to act as USB to I2C_Slave bridge,
+\ thus, from TERATERM.exe you can take the entire control of up to 112 I2C_FastForth targets.
+\ In addition, it simulates a full duplex communication while the I2C bus is only half duplex.
\ ================================================================================
-\ don't use R2, R3,
-\ R4, R5, R6, R7 must be PUSHed/POPed before/after use
-\ scratch registers S,T,W,X and Y are free,
-\ in interrupt routines, IP is free,
-\ Apply FORTH rules for TOS, PSP, RSP registers.
+
+\ -------------------------------------------------
+; UARTI2CS.f \I2C to UART bridge for I2C_FastForth\ -------------------------->+
+\ -------------------------------------------------- |
+\ ------------------------------ |
+\ see forthMSP430FR_TERM_I2C.asm |
+\ ------------------------------ |
+\ | |
+\ | |
+\ | GND------------------------------GND |
+\ | 3V3-------------o---o------------3V3 |
+\ | | | |
+\ | 1 1 |
+\ | k k Txy.z output |
+\ v 0 0 to v GND-------------------------------------GND
+\ I2C_FastForth | | Px.y int UARTI2CS +-------------------------------------->+
+\ (hardware +<-------------|---o------------>+ jumper (Software | +<----------------------------+ |
+\ I2C Slave) ^ +<------o----------+ ^ +--->+ I2C Master) | | +------(option)---->+ | |
+\ v v ^ v ^ | ^ v ^ v ^ v
+\ I2C_FastForth(s) SDA SCL connected to: SCL SDA | v I2C_to_UART_bridge TXD RXD RTS connected to : CTS TXD RXD UARTtoUSB <--> COMx <--> TERMINAL
+\ ------------------ ---- ---- ---- ---- ---------------- --- --- --- --- --- --- --------- ---- --------
+\ MSP_EXP430FR2355 P1.2 P1.3 P3.3 P3.2 P1.7 P1.6 MSP_EXP430FR2355 (24MHz) P4.3 P4.2 P2.0 PL2303GC |
+\ MSP_EXP430FR5739 P1.6 P1.7 P4.1 P4.0 P1.1 P1.0 MSP_EXP430FR5739 (24MHz) P2.0 P2.1 P2.2 PL2303HXD v
+\ MSP_EXP430FR5969 P1.6 P1.7 P1.3 P1.2 P2.2 P3.4 MSP_EXP430FR5969 (16MHz) P2.0 P2.1 P4.1 PL2303TA TERATERM.EXE
+\ MSP_EXP430FR5994 P7.0 P7.1 P8.1 P8.2 P1.5 P1.4 MSP_EXP430FR5994 (16MHz) P2.0 P2.1 P4.2 CP2102 ^
+\ MSP_EXP430FR6989 P1.6 P1.7 P1.5 P1.3 P3.6 P3.7 MSP_EXP430FR6989 (16MHz) P3.4 P3.5 P3.0 |
+\ MSP_EXP430FR4133 P5.2 P5.3 P8.3 P8.2 P1.6 P1.7 MSP_EXP430FR4133 (16MHz) P1.0 P1.1 P2.3 |
+\ MSP_EXP430FR2433 P1.2 P1.3 P3.1 P3.2 P1.2 P1.3 MSP_EXP430FR2433 (16MHz) P1.4 P1.5 P1.0 |
+\ LP_MSP430FR2476 P4.4 P4.3 P3.3 P3.2 P1.2 P1.1 LP_MSP430FR2476 (16MHz) P1.4 P1.5 P6.1 |
+\ MY_MSP430FR5738_2 P1.6 P1.7 P1.3 P1.2 P1.1 P1.0 MY_MSP430FR5738_2 (24MHz) P2.0 P2.1 P2.2 PL2303HXD |
+\ ^ |
+\ | |
+\ RST ALT+B
+\ ^ ^
+\ | |
+\ QUIT UARTI2CS QUIT UARTI2CS
+\
+\ =============================================================================================
+\ don't forget to link 3V3 and GND on each side and to add 1k0 pullup resistors on SDA and SCL.
+\ =============================================================================================
+\ don't forget to set the jumper Txy.z <--> Px.y
+\ =============================================================================================
+\ don't forget to remove the jumpers SBWTCK & SBWTDIO from the USB unpowered launchpad if any
+\ =============================================================================================
+\
+\ empiric value of I2C pullup resistors: R (k) = 8 Vcc / MCLK (MHz). ex. VCC = 3.3, MCLK = 24 MHz ==> R = 1k1
+\
+\ if you want to see what is happening on the I2C bus with an oscilloscope, pay attention to the capacitance of the probes,
+\ switch them from x1 to x10.
\
-\ PUSHM order : PSP,TOS, IP, S , T , W , X , Y ,rDOVAR,rDOCON,rDODOES,rDOCOL, R3, SR,RSP, PC
-\ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
+\ ------------
+\ how it works
+\ ------------
\
-\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack, with IP first pushed
+\ 1- the I2C bus is Master to Slave oriented, the Slave does not decide anything.
+\ The I2C Master device is placed on the TERMINAL side and the FastForth target on the I2C Slave side.
+\ Once the Master to Slave link is made, we have to find a trick to reverse the roles,
+\ so that the Slave can take control of the data exchange.
\
-\ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP
-\ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
+\ 2- The I2C bus is a half duplex exchange.
+\ Another trick will be to simulate an I2C_Master TERMINAL in Full Duplex mode.
\
-\ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack, with IP last poped
+\ 3- ..without forgetting a visual effect to show the lack of I2C connection.
\
-\ ASSEMBLER conditionnal usage before IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
-\ ASSEMBLER conditionnal usage before ?GOTO : S< S>= U< U>= 0= 0<> 0<
+\ Solution: The slave "slavishly" sends control characters to the master,
+\ and since this one obeys a bigger than itself, the programmer,
+\ he makes it his "masterly" duty to obey the slave.
\
-\ ================================================================================
-\ coupled to a PL2303HXD/TA cable, this driver enables a FastForth target to act as USB to I2C_Slave bridge,
-\ thus, from TERATERM.exe you can take the entire control of up to 112 I2C_FastForth targets.
-\ In addition, it simulates a full duplex communication while the I2C bus is only half duplex.
-\ Don't forget to wire 3k3 pull up resistors on wires SDA SCL!
-\ ================================================================================
-\
-\ driver test : MCLK=24MHz, PL2303HXD with shortened cable (20cm), WIFI off, all windows apps closed else Scite and TERATERM.
+\ To take control of the master, the slave emits one of 5 CTRL-Chars:
+\ CTRL-Char $00 sent by ACCEPT (before falling asleep with BACKGRND),
+\ CTRL-Char $01 sent by KEY: request to send a single character from TERMINAL,
+\ CTRL-Char $04 sent by NOECHO to switch the UART to half-duplex mode,
+\ CTRL-Char $05 sent by ECHO to switch the UART to full duplex mode,
+\ CTRL-Char $FF sent by ABORT": request to abort the file being downloaded if any,
+\ followed by a START RX to display the ABORT" message.
+\ More, if the master receives a $FF as data (it's the case for any SYS event on I2C_Slave side),
+\ it considers the link broken and performs ABORT, which forces a START RX into a 500 ms loop with an appropriate visual effect.
+\ All this guarantees a perfect hot swap of any I2C_slave.
+\
+\ Once the slave sends the CTRL_Char $00, he falls asleep,
+\ On its receipt, the master sends an UART RXON then falls down to sleep awaiting a UART RX interruption from TERMINAL.
+\ As long as the TERMINAL is silent, the master and the slave remain in their SLEEP mode,
+\ (a part a Tx0_INT interrupt (2*12us @24MHz --> Ires < 0,1uA ) every 1/2s on Master side).
+\ SLEEP mode is LPM0 for the master (else UART does not work), LPM4 for the slave.
+\
+\ interruptions
+\ -------------
+\ Since the slave can't wake up the master with a dedicated pin interrupt, the master must generate one
+\ cyclically to listen to the slave.
+\ 500MS_INT is used to generate a 1/2 second interrupt, obviously taken into account only when the master goes to sleep.
+\ It performs a (re)START I2C RX that enables the I2C link to be re-established following a RESET performed on I2C_Slave side.
+\
+\ This interruption also allows to exit the UARTI2CS program when user sends a software BREAK (Teraterm(Alt-B)).
+\
+\ To avoid locking, we have to ensure U2I_TERM_INT priority greater than 500MS_INT. As MSP430FR2xxx don't have timer with lower priority than eUSCI,
+\ we link the timer output pin with a contiguous pin with lower interrupt than TERM_INT to do this.
+\
+\
+\ driver test : MCLK=24MHz, PL2303CG with shortened cable (20cm), WIFI off, all windows apps closed else Scite and TERATERM.
\ ----------- .
\ . ┌────────────────────────────────┐
-\ notebook USB to I2C bridge +-- I2C -->| up to 112 I2C_Slave targets |
+\ notebook USB to I2C bridge +-- I2C -->| up to 112 I2C_FASTFORTH targets|
\ ┌───────────────┐ ╔════════════════════════════════════════════════════════════╗ / ┌───────────────────────────────┐ |
-\ | | ║ PL2303HXD device running UARTI2CS @ 24MHz ║ +-- I2C -->| MSP430FR4133 @ 1 MHz | |
+\ | WINDOWS 10 | ║ PL2303GC/HXD/TA launchpad running UARTI2CS ║ +-- I2C -->| MSP430FR4133 @ 1 MHz | |
\ | | ║───────────────┐ ┌────────────────────────────────║ / ┌───────────────────────────────┐ |──┘
\ | | ║ | 3 wires | MSP430FR2355 @ 24MHz ║/ | MSP430FR5738 @ 24 MHz | |
-\ | TERATERM -o--> USB --o--> USB2UART --o--> UART --o--> FAST FORTH ---> UARTI2CS --o--> I2C --o--> FAST FORTH with |──┘
-\ | terminal | ║ | 6 MBds | (I2C MASTER) ║ | I2C TERMINAL |
+\ | TERATERM -o--> USB --o--> USB2UART --o--> UART --o--> FASTFORTH + UARTI2CS --o--> I2C --o--> I2C_FASTFORTH |──┘
+\ | terminal | ║ | 6 MBds | (software I2C MASTER) ║ | (hardware I2C SLAVE) |
\ | | ║───────────────┘ └────────────────────────────────║ └───────────────────────────────┘
-\ | | ║ |<- l=20cm->| ║
+\ | | ║ |<- l=20cm->| ║<-l=20cm->|
\ └───────────────┘ ╚════════════════════════════════════════════════════════════╝
-\
-\ test results :
+\ |_|
+\ test results : RST
\ ------------
\
-\ downloading (+ interpret + compile + execute) CORETEST.4TH to I2C Master target = 1016ms.
-\ downloading (+ interpret + compile + execute) CORETEST.4TH to I2C Slave target = 1422ms.
-\ the difference (406 ms) is the time of the I2C Half duplex exchange.
-\ [(45906 chars * 9 bits) + (1533 * 31)] / 0,406 = 1,135 MHz (9 bits / char + (2*START + 2*STOP + 2*addr + CTRL_Char) / line)
-\ ==> 113 % of I2C Fast-mode Plus (Fm+)!
+\ Full duplex downloading (+ interpret + compile + execute) CORETEST.4TH to I2C Master target = 625ms/732kBds.
+\ Full duplex downloading (+ interpret + compile + execute) CORETEST.4TH to I2C Slave target = 1047ms/431kBds.
+\ the difference (422 ms) is the effective time of the I2C Half duplex exchange.
+\ [(9 bits / char) + ( 2*START + 2*addr + 1 CTRL_Char + 1 STOP / line )] = [(45763 chars * 9 bits) + (1538 lines * 30 bits)] / 0,422 = 1,085 MHz
+\ ==> I2C effective rate = 109 % of I2C Fast-mode Plus (Fm+).
\
-\ also connected to and tested with another I2C_FastForth target with MCLK = 1MHz (I2C CLK = MCLK ! ).
+\ also connected to and tested with another I2C_FastForth target with MCLK = 1MHz (I2C CLK > MCLK !).
\
-\ The I2C_Slave address is defined as 'MYSLAVEADR' in forthMSP430FR.asm source file of I2C_Slave target.
+\ The I2C_Slave address is defined as 'MYSLAVEADR' in forthMSP430FR.asm source file for the I2C_Slave target.
\ You can use any pin for SDA and SCL, preferably in the interval Px0...Px3.
-\ don't forget to add 3.3k pullup resitors on wires SDA and SCL.
-\
+\ don't forget to add 3.3k (maxi) pullup resitors on wires SDA and SCL.
\
\ the LEDs TX and RX work fine, comment/uncomment as you want.
\
\ Multi Master Mode works but is not tested in the real word.
\
-\ how it works
-\ ------------
-\
-\ 1- the I2C bus is Master to Slave oriented, the Slave does not decide anything.
-\ This order of things allows in any case to establish the connection.
-\ The I2C Master device is therefore placed on the TERMINAL side and the FastForth target on the I2C Slave side.
-\ But once the link is established, we have to find a trick to reverse the roles,
-\ so that the slave can take control of the data exchange.
-\
-\ 2- The I2C bus operates on half duplex.
-\ Another trick will be to simulate an I2C_Master TERMINAL in Full Duplex mode.
-\
-\ 3- Without forgetting a visual effect to show the lack of I2C connection...
-\
-\ Solution: The slave "slavishly" sends control characters to the master,
-\ and since this one obeys a bigger man than himself: the programmer..,
-\ he makes it his "masterly" duty to obey the slave.
\
-\ To take control of the master, the slave emits one of 5+1 CTRL-Char:
-\ CTRL-Char $00 sent by ACCEPT (before falling asleep with SLEEP),
-\ CTRL-Char $01 sent by KEY: request to send a single character entered on TERMINAL,
-\ CTRL-Char $02 sent by ABORT": request to abort the file being downloaded if any,
-\ followed by a START RX for ABORT" message,
-\ CTRL-Char $04 sent by NOECHO, to switch the UART to half-duplex mode,
-\ CTRL-Char $05 sent by ECHO, to switch the UART to full duplex mode.
-\
-\ Finally, if the master receives a $FF as data, he considers the link broken,
-\ it performs ABORT which forces a START RX into a 500 ms loop with an appropriate visual effect...
-\
-\ Once the slave sends the CTRL_Char $00, he falls asleep,
-\ On its receipt, the master also falls asleep, awaiting a UART RX interruption.
-\ As long as the TERMINAL is silent, the master and the slave remain in SLEEP mode,
-\ (a part the Tx0_INT interrupt every 1/2 s).
-\ SLEEP mode is LPM0 for the master (UART does not work if LPMx > LPM0), LPM4 for the slave.
+\ ================================================================================
+\ REGISTERS USAGE for embedded MSP430 ASSEMBLER
+\ ================================================================================
+\ don't use R2, R3,
+\ R4, R5, R6, R7 must be PUSHed/POPed before/after use
+\ scratch registers S,T,W,X and Y are free,
+\ in interrupt routines, IP is free,
+\ Apply FORTH rules for TOS, PSP, RSP registers.
\
-\ interruptions
-\ -------------
-\ Since the slave can't wake up the master with a dedicated interrupt, the master must generate one
-\ cyclically to listen to the slave.
-\ 500MS_INT is used to generate a 1/2 second interrupt, obviously taken into account only when the master goes to sleep.
-\ It performs a (re)START RX that enables the I2C link to be re-established following a RESET performed on I2C_Slave side.
+\ PUSHM order : PSP,TOS, IP, S , T , W , X , Y ,rDOVAR,rDOCON,rDODOES,rDOCOL, R3, SR,RSP, PC
+\ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
\
-\ This interruption also allows to exit the UARTI2CS program when user sends a software BREAK (Teraterm(Alt-B)), or presses SW2.
+\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack, with IP first pushed
\
-\ the other interruption U2I_TERM_INT is used to link the TERMINAL with UARTI2CS instead of FORTH interpreter.
+\ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP
+\ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
\
-\ don't forget to link 3V3 and GND on each side and to add 3k3 pullup resistors on SDA and SCL.
+\ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack, with IP last poped
\
-\ because Txi_int > UCxi_int > Pi.j_int and to ensure U2I_TERM_INT priority greater than 500MS_INT
-\ we choose P1.7 = TB0.2 output linked to P1.6 to use P1.6_int instead of Txi_int for 500MS_INT.
-
-; --------------------------------------------------------- \
-; UARTI2CS.f \ UART to I2C bridge for I2C_FastForth TERMINAL----------+
-; --------------------------------------------------------- \ |
-\ |
-\ |
-\ GND------------------------------GND |
-\ Vcc-------------o---o------------Vcc |
-\ | | |
-\ 3 3 |
-\ k k |
-\ 3 3 v
-\ I2C_FastForth | | UARTI2CS +---------------------------------------+
-\ hardware +--------------|---o-------------+ Software | +-----------------------------+ |
-\ I2C Slave | +-------o----------+ | I2C Master | | +------(option)-----+ | |
-\ | | | | | | | | | |
-\ I2C_FastForth(s) SCL SDA connected to: SDA SCL of I2C to UART bridge TXD RXD RTS connected to : CTS TXD RXD UARTtoUSB <--> COMx <--> TERMINAL
-\ ------------------ ---- ---- ---- ---- ------------------ --- --- --- --- --- --- --------- ---- ------------
-\ MSP_EXP430FR5739 P1.7 P1.6 P4.0 P4.1 MSP_EXP430FR5739 P2.0 P2.1 P2.2 PL2303TA TERATERM.EXE
-\ MSP_EXP430FR5969 P1.7 P1.6 P1.2 P1.3 MSP_EXP430FR5969 P2.0 P2.1 P4.1 PL2303HXD
-\ MSP_EXP430FR5994 P7.1 P7.0 P8.2 P8.1 MSP_EXP430FR5994 P2.0 P2.1 P4.2 CP2102
-\ MSP_EXP430FR6989 P1.7 P1.6 P1.3 P1.5 MSP_EXP430FR6989 P3.4 P3.5 P3.0
-\ MSP_EXP430FR4133 P5.3 P5.2 P8.2 P8.3 MSP_EXP430FR4133 P1.0 P1.1 P2.3
-\ CHIPSTICK_FR2433 P1.3 P1.2 P2.0 P2.2 CHIPSTICK_FR2433 P1.4 P1.5 P3.2
-\ MSP_EXP430FR2433 P1.3 P1.2 P3.2 P3.1 MSP_EXP430FR2433 P1.4 P1.5 P1.0
-\ MSP_EXP430FR2355 P1.3 P1.2 P3.2 P3.3 MSP_EXP430FR2355 P4.3 P4.2 P2.0
-\ LP_MSP430FR2476 P4.3 P4.4 P3.2 P3.3 LP_MSP430FR2476 P1.4 P1.5 P6.1
+\ ASSEMBLER conditionnal usage before IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before ?GOTO : S< S>= U< U>= 0= 0<> 0<
\ first, we do some tests allowing the download
-\ ------------------------\
CODE ABORT_UARTI2CS \
-\ ------------------------\
SUB #4,PSP
MOV TOS,2(PSP)
MOV &KERNEL_ADDON,TOS
0<> IF MOV #0,TOS THEN \ if TOS <> 0 (UART TERMINAL), set TOS = 0
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
- COLON
+ SUB #400,TOS \ FastForth V4.0
+ COLON \ ASSEMBLER switch to FORTH with IP backup
$0D EMIT \ return to column 1 without CR
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
ABORT" <-- Ouch! unexpected I2C_FastForth target!"
RST_RET \ remove the ABORT_UARTI2CS definition before continuing the download.
;
ABORT_UARTI2CS \ run tests
- MARKER {UARTI2CS} \ USER_PARAM-2 addr = {UARTI2CS}-2 <-- REMOVE_APP (RET_ADR by default)
- 10 ALLOT \ USER_PARAM addr = {UARTI2CS} <-- previous HARD_APP
-\ USER_PARAM+2 addr = {UARTI2CS}+2 <-- previous SLEEP_APP
-\ USER_PARAM+4 addr = {UARTI2CS}+4 <-- previous TERM_VEC
-\ USER_PARAM+6 addr = {UARTI2CS}+6 <-- previous P1_VEC
-\ USER_PARAM+8 addr = {UARTI2CS}+8 <-- I2C_Slave_Addr << 1
-\ USER_PARAM+9 addr = {UARTI2CS}+9 <-- Half_Duplex flag : 4 --> NOECHO, <> 4 --> ECHO
+\ here is a MARKER definition, used to free the program memory including it, and restoring previous hardware context if any.
+
+ MARKER {UARTI2CS} \ the command : ' <MARKER_definition>, leaves USER_PARAM address on the stack.
+\ &{UARTI2CS}-2 = USER_DOES <-- #REMOVE_U2I addr, the subroutine used to restore the low level environment below:
+ 16 ALLOT \ &{UARTI2CS} = USER_PARAM <-- previous &STOP_APP addr
+ \ &{UARTI2CS}+2 = USER_PARAM+2 <-- previous &HARD_APP addr
+\ &{UARTI2CS}+4 = USER_PARAM+4 <-- previous &BACKGRND_APP addr
+\ &{UARTI2CS}+6 = USER_PARAM+6 <-- previous &TERM_VEC addr
+\ &{UARTI2CS}+8 = USER_PARAM+8 <-- previous &Px_VEC addr
+\ local variables : UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+\ TIMER_CONF=\{UARTI2CS\}\+12 <-- TIM_CTL configuration
+\ COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+\ DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+\ USER_PARAMS[-2...+16[ are initialised by START_U2I and USER_PARAMS[-2...+10[ are restored by REMOVE_U2I.
+
+\ =========================================================================
+ CODE LEDS MOV @IP+,PC ENDCODE \ comment this line to remove LEDS option
+\ =========================================================================
+
+\ -----------------------------------------------------------------------
+\ first we download the set of definitions we need (copied from CORE_ANS)
+\ -----------------------------------------------------------------------
+\
+ [UNDEFINED] = [IF]
+\ https://forth-standard.org/standard/core/Equal
+\ = x1 x2 -- flag test x1=x2
+ CODE =
+ SUB @PSP+,TOS \ 2
+ SUB #1,TOS \ 1 borrow if TOS was 0
+ SUBC TOS,TOS \ 1 TOS=-1 if borrow was set
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] + [IF] \ for [ABORT, (GEMA pattern)
+\ https://forth-standard.org/standard/core/Plus
+\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
+ CODE +
+ ADD @PSP+,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
- [UNDEFINED] TSTBIT
- [IF]
+\ -----------------------------
+\ end of definitions we need...
+\ -----------------------------
+\
+ [UNDEFINED] TSTBIT [IF]
CODE TSTBIT \ addr bit_mask -- true/flase flag
MOV @PSP+,X
AND @X,TOS
ENDCODE
[THEN]
-\ note: HDNCODE definitions are HiDdeN and cannot be executed from TERMINAL
-\ ----------------------------\
- HDNCODE I2CM_STOP \ sends a STOP on I2C_BUS
-\ ----------------------------\ _
- BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low)
- NOP3 \ 3 l _
- BIS.B #SM_SDA,&I2CSM_DIR \ 3 l v_ SDA as output ==> SDA low
- NOP3 \ 3 l _
- BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
- NOP3 \ 3 h _
- BIC.B #SM_SDA,&I2CSM_DIR \ 3 h _^ relase SDA (high) when SCL is high = STOP
- MOV @RSP+,PC \
- ENDCODE \
-\ ----------------------------\
+\ see symbolic values in ..\inc\launchpad.pat or/and in ..\inc\device.pat
+\ note: HDNCODE definitions are HiDdeN and cannot be called from TERMINAL
+\ ------------------------------------\
+ HDNCODE I2CM_STOP \ sends a STOP on I2C_BUS
+\ ------------------------------------\ _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low)
+ NOP3 \ 3 l _
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l v_ SDA as output ==> SDA low
+ NOP3 \ 3 l _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ NOP3 \ 3 h _
+ BIC.B #SM_SDA,&I2CSM_DIR \ 3 h _^ relase SDA (high) when SCL is high = STOP
+ MOV @RSP+,PC \ 4
+ ENDCODE \
+\ ------------------------------------\
+
+\ ------------------------------------\
+ HDNCODE REMOVE_U2I \ REMOVE_APP subroutine
+\ ------------------------------------\
+BW1 \ <-- WARM <-- INIT_FORTH <-- SYS_failures|RESET
+\ ------------------------------------\
+ [DEFINED] LEDS [IF]
+ BIC.B #LED1,&LED1_OUT \ set TX red led OFF
+ BIC.B #LED1,&LED1_DIR \ set TX red led pin as input
+ BIC.B #LED2,&LED2_OUT \ set RX green led OFF
+ BIC.B #LED2,&LED2_DIR \ set RX green led pin as input
+ [THEN]
+ CALL #I2CM_STOP \ stop properly I2C_BUS
+ BIS.B #SM_BUS,&I2CSM_OUT \ restore I2C_BUS I/O
+ BIS.B #SM_BUS,&I2CSM_REN \ with pull up resistors
+\ ------------------------------------\
+ MOV #0,&TIM_CTL \ stop timer
+ BIC.B #T_OUT2,&T_OUT2_SEL \ clear T_OUT2 SEL
+ BIC.B #T_OUT2,&T_OUT2_DIR \ set T_OUT2 as input
+ BIC.B #INT_IN,&INT_IN_IE \ clear INT_IN IE
+\ ------------------------------------\
+ CMP #RET_ADR,&{UARTI2CS}-2 \
+ 0<> IF \ restore USER_PARAMS[-2...+10[
+ MOV #{UARTI2CS},W \ W = addr of first user parameter following MARKER
+ MOV #RET_ADR,-2(W) \ don't forget: restore default USER_DOES call address !
+ MOV @W+,&STOP_APP \ restore previous (default) STOP_APP value
+ MOV @W+,&HARD_APP \ restore previous (default) HARD_APP value
+ MOV @W+,&BACKGRND_APP \ restore previous (default) BACKGRND_APP value
+ MOV @W+,&TERM_VEC \ restore previous (default) TERM_VEC value
+ MOV @W+,&INT_IN_VEC \ restore previous (default) INT_IN_VEC value
+ THEN \
+\ ------------------------------------\
+ MOV @RSP+,PC \ --> WARM --> previous_HARD_APP --> display I2C_address + WARM message --> FORTH interpreter
+ ENDCODE \
+\ ------------------------------------\
-\ ----------------------------\
- CODE REMOVE_U2I \
-\ ----------------------------\
-BW1 \ <-- TERATERM(ALT+B)|USBtoI2C_bridge(SW2)|SYS_failures
-\ vvvvvvvvvvvv OPTION vvvvvvvv\
- BIC.B #LED1,&LED1_OUT \ set TX red led OFF
- BIC.B #LED1,&LED1_DIR \ set TX red led pin as input
- BIC.B #LED2,&LED2_OUT \ set RX green led OFF
- BIC.B #LED2,&LED2_DIR \ set RX green led pin as input
-\ ^^^^^^^^^^^^ OPTION ^^^^^^^^\
- CALL #I2CM_STOP \ stop properly I2C_BUS
- MOV #SM_BUS,W \
- BIC.B W,&I2CSM_DIR \ restore I2C_BUS I/O as input
- BIS.B W,&I2CSM_OUT \ with pull up resistors
- BIS.B W,&I2CSM_REN \
-\ ----------------------------\
- MOV #0,&TB0CTL \ stop TBO
- BIC.B #BIT7,&P1SEL1 \ clear P1.7 SEL1
- BIC.B #BIT7,&P1DIR \ P1.7 as input
- BIC.B #BIT6,&P1IE \ stop P1.6 int
-\ ----------------------------\
- CMP #RET_ADR,&{UARTI2CS}-2 \
+\ ------------------------------------\
+ HDNCODE STOP_U2I \ new STOP_APP subroutine, defined for the example, not used.
+\ ------------------------------------\
+ CALL #I2CM_STOP \ send I2C STOP
+ MOV &{UARTI2CS},PC \ run previous STOP_APP then RET
+ ENDCODE \
+\ ------------------------------------\
+
+\ ------------------------------------\
+ HDNCODE BACKGRND_U2I \ new BACKGRND_APP subroutine, RET to LPM0 shut down.
+\ ------------------------------------\
+\ user request test \
+\ ------------------------------------\
+ BIT #8,&TERM_STATW \ 3 break sent by TERATERM (Alt+B) ?
0<> IF
- MOV #{UARTI2CS},W \ W = addr of first user parameter following MARKER
- MOV #RET_ADR,-2(W) \ don't forget: restore default MARKER_DOES call address !
- MOV @W+,&HARD_APP \ restore previous (default) HARD_APP value
- MOV @W+,&SLEEP_APP \ restore previous (default) SLEEP_APP value
- MOV @W+,&TERM_VEC \ restore previous (default) TERM_VEC value
- MOV @W+,&P1_VEC \ restore previous (default) P1_VEC value
+ MOV #WARM_IP_ADR,0(RSP) \ replace BACKGRND_U2I return by INIT_FORTH followed by WARM
+ PUSH #INIT_FORTH \
+\ ------------------------------------\
+BW2 MOV #1,TOS \ to identify manual request to REMOVE_U2I
+ GOTO BW1 \ 2
THEN
-\ ----------------------------\
- MOV #1,TOS \ TOS = USERSYS value we want for TERATERM(ALT+B)|USBtoI2C_bridge(SW2)|SYS_failures events
- MOV #UART_WARM+4,PC \ display WARM message then RET to FORTH interpreter
- ENDCODE \ REMOVE_U2I is redirected to this CODENNM definition
-\ ----------------------------\
+\ ------------------------------------\
+ BIC.B #INT_IN,&INT_IN_IFG \ 4 clear INT_IN IFG
+ MOV #'CR',S \ 2 S = 'CR' = penultimate char of line to be RXed by UART
+ MOV #0,T \ 2 T = init buffer pointer for UART_TERMINAL input
+ MOV.B &DUPLEX_MODE,Y \ 3 Y = 4 ==> NOECHO else ECHO, for U2I_TERM_INT and 500MS_INT use
+ MOV &{UARTI2CS}+4,PC \ 3 previous BACKGRND_APP executes RXON, enabling TERMINAL TX, then RET to LPM0 shut down.
+ ENDCODE \
+\ ------------------------------------\
+
+\ ------------------------------------\
+ HDNCODE HARD_U2I \ new HARD_APP subroutine, RETurn redirected to ABORT --> ACCEPT --> BACKGRND
+\ ------------------------------------\
+\ init 500MS_INT \ used to scan I2C_Slave hard RESET and to slow down (re)START RX loop
+\ ------------------------------------\
+BW3 MOV &TIMER_CONF,&TIM_CTL \ start RX_timer, up mode
+ MOV #4096,&TIM_CCR0 \ time 0.5s
+\ ------------------------------------\
+\ set TB0.2 to generate 500ms int \
+\ ------------------------------------\
+ MOV #$60,&TIM_CCTL2 \ output mode = set/reset )
+ MOV #4096,&TIM_CCR2 \ one cycle pulse to set P1.6IFG )
+ BIS.B #T_OUT2,&T_OUT2_DIR \ P1.7 as output > (MSP-EXP430FR2355 values, to custom for your launchpad)
+ BIS.B #T_OUT2,&T_OUT2_SEL \ P1.7 as TB0.2 output )
+ BIS.B #INT_IN,&INT_IN_IE \ P1.6IE )
+\ ------------------------------------\
+\ init I2C_MASTER I/O \
+\ ------------------------------------\
+ BIC.B #SM_BUS,&I2CSM_REN \ remove internal pull up resistors because the next instruction which change them to pull down resistors
+ BIC.B #SM_BUS,&I2CSM_OUT \ preset SDA + SCL output LOW
+ BIC.B #SM_BUS,&I2CSM_IES \ set IES for SDA_IFG and SCL_IFG on low_to_high transition, for detection collision.
+ [DEFINED] LEDS [IF]
+ BIS.B #LED1,&LED1_DIR \ set red led (I2C TX) pin as output
+ BIS.B #LED2,&LED2_DIR \ set green led (I2C RX) pin as output
+ [THEN]
+\ ------------------------------------\
+\ run previous HARD_APP \
+\ ------------------------------------\
+ CALL &{UARTI2CS}+2 \ execute previous HARD_APP to init TERM_UC, activates I/O.
+\ ------------------------------------\ TOS = USERSYS=$00|SYSRSTIV=$02|$04|$0E|$xx as UARTI2CS|POWER_ON|RST|SVSH_threshold|SYS_failures
+\ define new SYSRSTIV select \
+\ ------------------------------------\
+ CMP #6,TOS \ SYSRSTIV = RESET ?
+ 0= ?GOTO BW2 \ if yes goto REMOVE_U2I with TOS = 1, return to WARM
+ CMP #$0E,TOS \ SVSHIFG SVSH event = #14 ? (POWER_ON)
+ 0<> IF \ if not
+ CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas ?
+ U>= ?GOTO BW1 \ if yes goto REMOVE_U2I, return to WARM
+ THEN \
+\ ------------------------------------\
+ MOV #ABORT,0(RSP) \ replace WARM return by ABORT return
+ MOV @RSP+,PC \ --> ABORT --> ACCCEPT --> BACKGRND --> LPM4
+ ENDCODE \
+\ ------------------------------------\
\ ----------------------------------------\
- HDNCODE I2CM_START \ WX use I2C_Master TX ADdRess with collision detection and resolution
+ HDNCODE I2CM_START \ I2C_Master START and TX Address, version with collision detection and resolution
\ ----------------------------------------\ _
BIS.B #SM_SDA,&I2CSM_DIR \ 3 v_ force SDA as output (low)
- BIS.B &{UARTI2CS}+8,X \ 3 X = Slave_Address&flag
- NOP3 \ 3
+ BIS &UARTI2CS_ADR,X \ 3 _ X = (Slave_Address<<1 | R/w bit)
BIS.B #SM_SCL,&I2CSM_DIR \ 3 v_ force SCL as output (low)
\ ----------------------------------------\
-\ I2C_Master_Send_I2C_Addr \
+\ I2C_Master Send I2C Addr \
\ ----------------------------------------\
MOV.B #8,W \ 1 l count for 7 bits address + R/w bit
BEGIN \
ADD.B X,X \ 1 l shift one left
- U>= IF \ 2 l carry set ?
- BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor
- ELSE \ 2 l
- BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no : SDA as output ==> SDA low
- THEN \ l _
- BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
-\ BEGIN \
-\ BIT.B #SM_SCL,&I2CSM_IN \ 3 h The I2C_Slave hardware takes the I2C address without delay even if the CPU is in the LPM4 state (wired logic).
-\ 0<> UNTIL \ 2 h
- BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA
- BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
-\ vvvvvvvvv Multi-Master-Mode vvvvvvvv\
- 0= IF \ 2 l if SDA input low
- BIT.B #SM_SDA,&I2CSM_DIR \ 3 l + SDA command high
- 0= IF \ 2 l = collision detected
- BIS.B #SM_BUS,&I2CSM_DIR \ 4 l release SDA,SCL
- BIC.B #SM_BUS,&I2CSM_IES \ 4 l set IES for SDA_IFG and SCL_IFG on low_to_high transition
- BEGIN \ SDA_IFG=1, SCL_IFG=1
- BIT.B #SM_BUS,&I2CSM_IFG \ 4 SM_BUS IFG ?
- BIC.B #SM_BUS,&I2CSM_IFG \ 4 clear SM_BUS IFG
- 0<> IF \ 2 if yes
-\ MOV #3,W \ 2 SCL is still active: load for 8*15/MHz = 5.6 µs delay @ 8 MHz
-\ MOV #6,W \ 2 SCL is still active: load for 8*15/MHz = 5.6 µs delay @ 16 MHz
- MOV #9,W \ 2 SCL is still active: load for 8*15/MHz = 5.6 µs delay @ 24 MHz
- ELSE \ 2 if no
- NOP2 \ 2 does the same
- NOP2 \ 2 time as if yes
- THEN
- SUB #1,W \ 1
- 0= UNTIL \ 2 end of collision process
- ADD #2,RSP \ remove RET to Nack/Ack processing and select..
- MOV @RSP+,PC \ 2 l RET to ReStart after a collision detection
+ U< IF \ 2 l carry set ?
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l _ no SDA as output ==> SDA low
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ NOP3 \ 3 h for symmetry.
+ ELSE \ 2 l yes we can detect collision only when SDA is driven high
+ BIC.B #SM_SDA,&I2CSM_DIR \ 3 l _ SDA as input ==> SDA high because pull up resistor
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h get SDA input
+ 0= IF \ 2 h
+\ ----------------------------\
+\ collision detected \ if SDA input low, collision detected
+\ ----------------------------\
+ BEGIN \
+ BIT #TX,&TERM_IFG \ 3
+ 0<> UNTIL \ 2
+ MOV.B #'c',&TERM_TXBUF \ 3 send 'c' to TERMINAL to show collision
+\ ----------------------------\
+\ collision resolution \
+\ ----------------------------\
+ BEGIN \ wait until SDA high
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h
+ 0<> UNTIL \ 2
+\ ----------------------------\
+ BEGIN \ wait for 20us bus idle time
+ BIC.B #SM_BUS,&I2CSM_IFG \ 4 clear SM_BUS IFG
+ NOP3 \ 3
+ MOV.B &COLLISION_DLY,W \ 3 load delay value
+ BEGIN \
+ NOP \ 1
+ SUB #1,W \ 1
+ 0= UNTIL \ 2 4~ x (delay value)
+ BIT.B #SM_BUS,&I2CSM_IFG \ 4
+ 0= UNTIL \ 2 + 16~ dead time for the remainder of idle time
+\ ----------------------------\
+ ADD #2,RSP \ 1 remove the RET for Nack/Ack processing and select..
+ MOV @RSP,PC \ 4 h ...RET to ReStart after a collision detection with preserving this RET address on RSP
+\ ----------------------------\
THEN \
- THEN \
-\ ^^^^^^^^^ Multi-Master-Mode ^^^^^^^^\
+ THEN \ _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
SUB #1,W \ 1 l bits count-1
- 0= UNTIL \ 2 l
+ 0= UNTIL \ 2 l 20 * 8 cycles
\ ----------------------------------------\
-\ I2C_Master_TX get Slave Ack/Nack \
+\ I2C_Master get Slave Ack/Nack on address\
\ ----------------------------------------\ _
BIC.B #SM_SDA,&I2CSM_DIR \ 3 l _^_ after TX address we must release SDA to read Ack/Nack from Slave
BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
BEGIN \ we must wait I2C_Slave software
BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released
- 0<> UNTIL \ 2 h because Slave can strech SCL low (wake up from interrupt)
- BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA state
+ 0<> UNTIL \ 2 h because Slave can strech SCL low (may be occupied)
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA state: flag Z = 0 if Nack
BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
-\ ^^^^^^^^^^^ Multi-Master-Mode ^^^^^^^^^^\
- MOV @RSP+,0(RSP) \ remove RET to ReStart after a collision detection
-\ vvvvvvvvvvv Multi-Master-Mode vvvvvvvvvv\
- MOV @RSP+,PC \ RET to Nack/Ack select
- ENDCODE
\ ----------------------------------------\
-
+ MOV @RSP+,0(RSP) \ 4 remove RET to (ReStart after a collision detection)
+ MOV @RSP+,PC \ 4 RET to RX|RX datas
+ ENDCODE \ 195 cycles
+\ ----------------------------------------\
\ ****************************************\
HDNCODE U2I_TERM_INT \ UART RX interrupt starts on first char of each line sent by TERMINAL
\ ****************************************\
- ADD #4,RSP \ 1 remove unused PC_RET and SR_RET
+ ADD #4,RSP \ 1 remove unused SR_RET, and remove PC_RET because we want include BACKGRND_U2I as end of U2I_TERM_INT routine
\ ----------------------------------------\
-\ get one line from UART TERMINAL to PAD \ S = 'CR', T = 0
+\ get one line from UART TERMINAL to PAD \ S = 'CR', T = 0, W = char, Y = ECHO/NOECHO flag (see U2I_BACKGRND)
\ ----------------------------------------\
- BEGIN \
- MOV.B &TERM_RXBUF,Y \ 3 move char from TERM_RXBUF...
- MOV.B Y,PAD_ORG(T) \ 3 ... to input buffer
+ BEGIN \ input buffer begins at PAD-2, able to receive CIB_LEN = 84 chars, plus CR+LF !!!
+ MOV.B &TERM_RXBUF,W \ 3
ADD #1,T \ 1
- CMP.B Y,S \ 1 char = CR ? (if yes goto next REPEAT)
- 0<> WHILE \ 2 if <>
- CMP #4,W \ 1 HALF_DUPLEX = 4 ?
- 0<> IF \ 2 no, echo is ON
+ CMP.B S,W \ 1 char = CR ? (if yes goto next REPEAT)
+ 0<> WHILE \ 2 while <> CR
+ CMP #CIB_LEN+1,T \ 2
+ U< IF \ 2 discard chars out of PAD-2 + CIB_LEN bound
+ MOV.B W,PAD_ORG-3(T) \ 3 write char to input buffer, PAD-2 first
+ THEN
+ CMP.B #4,Y \ 1 echo OFF ?
+ 0<> IF \ 2 if echo is ON
BEGIN \ )
- BIT #2,&TERM_IFG \ 3 > Test TX_Buf empty, mandatory for low baudrates
+ BIT #TX,&TERM_IFG \ 3 > Test TX_Buf empty, mandatory for low baudrates
0<> UNTIL \ 2 )
- MOV.B Y,&TERM_TXBUF \ 3 return all characters to UART_TERMINAL except CR+LF which will be later by I2C_SLAVE
+ MOV.B W,&TERM_TXBUF \ 3 return all characters to UART_TERMINAL except CR+LF which will be sent later by I2C_SLAVE
THEN \
BEGIN \
- BIT #1,&TERM_IFG \ 3 wait for next char received
+ BIT #RX,&TERM_IFG \ 3 wait for next char received
0<> UNTIL \ 2
- REPEAT \ 2 2 cycles loop ==> up to UART 2.58 Mbds @ 8MHz
+ REPEAT \ 2 32 cycles loop ==> up to UART 2.5 Mbds @ 8MHz
CALL #UART_RXOFF \ stops UART RX still char CR is received, the LF char is being transmitted.
+ MOV.B W,PAD_ORG-3(T) \ move CR in buffer
BEGIN \
- BIT #1,&TERM_IFG \ 3 char LF received ?
+ BIT #RX,&TERM_IFG \ 3 char LF received ?
0<> UNTIL \ 2
\ ----------------------------------------\
-BW2 \ <=== KEY input from TERMINAL, via I2C_MASTER
+BW2 \ here, BW2 is redefined \ <=== KEY input from TERMINAL, via I2C_MASTER
\ ----------------------------------------\
- MOV.B &TERM_RXBUF,S \ 3 S = last char RXed by UART (LF|KEY_input), used by I2C_MASTER_TX as last byte to be TXed.
- MOV.B S,PAD_ORG(T) \ 3 store it into buffer
+ MOV.B &TERM_RXBUF,S \ S = last char RXed by UART (LF|KEY_input), used by I2C_MASTER_TX as last byte to be TXed.
+ MOV.B S,PAD_ORG-2(T) \ 3
\ ========================================\ here I2C_Slave is sleeping in its ACCEPT routine
-\ I2C MASTER TX \ now we transmit UART RX buffer (PAD) to I2C_Slave, S = LF|KEY = last char to transmit
+\ I2C_MASTER TX \ now we transmit UART RX buffer (PAD) to I2C_Slave, S = LF|KEY = last char to transmit
\ ========================================\
+ PUSH PC \ PUSH next address as RET for reSTART after collision detection
\ ----------------------------------------\
-\ I2C_Master_TX_Start \ S = last char UART RXed
+\ I2C Master TX Start \ S = last char UART RXed
\ ----------------------------------------\
-\ ^^^^^^^^^^^ Multi-Master-Mode ^^^^^^^^^^\
- PUSH PC \ PUSH next address as RET for START with collision detection
-\ vvvvvvvvvvv Multi-Master-Mode vvvvvvvvvv\
- MOV #0,X \ to Start I2C_Master_TX
- CALL #I2CM_START \WX use return to I2C_Master_TX_Start if collision detection on I2C address
- 0<> ?GOTO FW2 \ if Nack on address
-\ vvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvv\
- BIS.B #LED1,&LED1_OUT \ red led ON = I2C TX
-\ ^^^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^^^^\
- MOV #PAD_ORG,Y \ 2 Y = buffer pointer for I2C_Master TX datas
- BEGIN \
- MOV.B @Y,X \ 2 l get first char to be TX
+ MOV #0,X \ 1 to Start I2C TX
+ CALL #I2CM_START \ 4 flag Z = 0 if Nack_On_Address
+ 0<> ?GOTO FW2 \ if Nack on address ───────────────┐
+\ ========================================\ |
+\ I2C MASTER TX datas \ |
+\ ========================================\ |
+ [DEFINED] LEDS [IF] \ |
+ BIS.B #LED1,&LED1_OUT \ red led ON = I2C TX |
+ [THEN] \ |
+\ ----------------------------------------\ |
+ MOV #PAD_ORG-2,T \ 2 Y = buffer pointer, PAD-2 first |
+ BEGIN \ |
+ MOV.B @T,X \ 2 l get first char to be TX |
+\ ------------------------------------\ v
+\ I2C_Master TX 7 bits of Data \
\ ------------------------------------\
-\ I2C_Master_TX Data from PAD \
-\ ------------------------------------\
- MOV.B #8,W \ 1 l count for 8 bits data
+ MOV.B #7,W \ 2 l count for 7 data bits
BEGIN \
ADD.B X,X \ 1 l shift one left
U>= IF \ 2 l carry set ?
BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor
ELSE \ 2 l
- BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no : SDA as output ==> SDA low
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no: SDA as output ==> SDA low
+ NOP2 \ 2 l for symmetry
THEN \ l _
BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
\ --------------------------------\
- BEGIN \
- BIT.B #SM_SCL,&I2CSM_IN \ 3 h TERM2SD" doesn't work if you replace this test by NOP3 !
- 0<> UNTIL \ 2 h
+ NOP3 \ 3 h
\ --------------------------------\ _
BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
SUB #1,W \ 1 l bits count-1
0= UNTIL \ 2 l
\ ------------------------------------\
- BIC.B #SM_SDA,&I2CSM_DIR \ 3 l after TX byte we must release SDA to read Ack/Nack from Slave
+\ I2C_Master TX 8th bit of Data \
\ ------------------------------------\
-\ I2C_Master_TX get Slave Ack/Nack \
-\ ------------------------------------\ _
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no: SDA as output ==> SDA low
+ NOP2 \ 2 l for symmetry
+ THEN \ l _
BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
- BEGIN \
- BIT.B #SM_SCL,&I2CSM_IN \ 3 h
+\ ------------------------------------\
+ BEGIN \ here, (last bit of TX data), I2C_Slave streches SCL low until its RX_BUF is read,
+ BIT.B #SM_SCL,&I2CSM_IN \ 3 h that is not documented in any MSP430FRxxx family user's guide...
0<> UNTIL \ 2 h
+\ ------------------------------------\ _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+\ ------------------------------------\
+\ I2C_Master_TX get Slave Ack/Nack \
+\ ------------------------------------\
+ BIC.B #SM_SDA,&I2CSM_DIR \ 3 l _ after TX byte we must release SDA to read Ack/Nack from Slave
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ NOP3 \ here, I2C_Slave doesn't strech SCL low, as suggested in TI's documentation...
BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA state
- BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low, to keep I2C_BUS until next I2C_MASTER START (RX|TX)
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low, to keep I2C_BUS until next START (RX|TX)
\ ----------------------------------------\
- 0= WHILE \ 1- Slave Ack received \ 2 l out of loop if Nack on data
+ 0= WHILE \ 1- Slave Ack received \ 2 l out of loop if Nack on data (goto next THEN)
\ ----------------------------------------\
-\ I2C_Master_TX_Data_Loop \
+\ I2C_Master TX Data Loop \
\ ----------------------------------------\
- CMP.B @Y+,S \ 2 last char I2C TXed = last char UART RXed (LF|KEY) ?
+ CMP.B @T+,S \ 2 l last char I2C TXed = last char UART RXed (LF|KEY) ?
\ ----------------------------------------\
- 0= UNTIL \ TXed char = last char \ 2
+ 0= UNTIL \ TXed char = last char \ 2 l loop back if <> 0
\ ----------------------------------------\
- THEN \ <-- WHILE1 case of I2C_Slave Nack on Master_TX
-\ vvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvv\
+ THEN \ <-- WHILE1 case of I2C_Slave Nack on Master_TX data
+\ ========================================\
+\ END OF I2C MASTER TX datas \
+\ ========================================\
+ [DEFINED] LEDS [IF]
BIC.B #LED1,&LED1_OUT \ red led OFF = endof I2C TX
-\ ^^^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^^^^\
- GOTO FW1 \ SCL is kept low ──────────┐
-\ ========================================\ |
-\ END OF I2C MASTER TX \ |
-\ ========================================\ |
- ENDCODE \ |
-\ ****************************************\ v
+ [THEN]
+\ ----------------------------------------\
+ GOTO FW1 \ SCL is kept low ──────┐
+ ENDCODE \ |
+\ ****************************************\ v
\ wakes up every 1/2s by P1.6 int to listen I2C Slave or
\ break from TERMINAL/USB_to_I2C_bridge.
-\ ********************************************\ |
- HDNCODE 500MS_INT \ |
-\ ********************************************\ |
- ADD #4,RSP \ 1 remove PC_RET, SR_RET |
-\ --------------------------------------------\ |
-FW1 \ <────── does START <──────┘
-FW2 \ <────── if Nack on Address Master TX
-\ ^^^^^^^^^^^ Multi-Master-Mode ^^^^^^^^^^^^^^\
- PUSH PC \ PUSH next address as RET for START with collision detection
-\ vvvvvvvvvvv Multi-Master-Mode vvvvvvvvvvvvvv\
-\ ============================================\
-\ I2C_MASTER RX \ le driver I2C_Master envoie START RX en boucle continue (X < 4) ou discontinue (X >= 4).
-\ ============================================\ le test d'un break en provenance de l'UART est intégré dans cette boucle.
- BEGIN \
-\ ----------------------------------------\
-\ QUIT on user request tests \
-\ ----------------------------------------\
- BIT #8,&TERM_STATW \ 3 break sent by TERATERM (Alt+B) ?
- 0<> ?GOTO BW1 \ 2 goto REMOVE_U2I, RET to WARM+4 with TOS=1.
- BIT.B #SW2,&SW2_IN \ 3 USB_to_I2C_bridge(SW2) pressed ?
- 0= ?GOTO BW1 \ 2 goto REMOVE_U2I, RET to WARM+4 with TOS=1.
-\ ----------------------------------------\
-\ I2C MASTER START RX \
-\ ----------------------------------------\ _
- BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL to enable START RX
- MOV #1,X \ to Start I2C_Master as RX
- CALL #I2CM_START \ Start MASTER RX
- 0<> IF \ if Nack_On_Address
- CALL #I2CM_STOP \ I2C_Master Send STOP
- MOV #'.',&TERM_TXBUF \ to view the absence of I2C_target at the I2C_Addr provided.
- MOV #SLEEP,PC \ which executes SLEEP_U2I then RXON before LPM0 shut down.
- THEN \
-\ ----------------------------------------\
-\ I2C_Master_RX_data \ End of RX_Data only on Ctrl_Char {$00|$01|$02|$FF}
-\ ----------------------------------------\
-\ vvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvvvv\
- BIS.B #LED2,&LED2_OUT \ green led ON = I2C RX
-\ ^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^^^^^^\
- BEGIN \
- BEGIN \
- BIC.B #SM_SDA,&I2CSM_DIR \ 4 l after Ack and before RX next byte, we must release SDA
- MOV.B #8,W \ 1 l prepare 8 bits transaction
- BEGIN \
-\ ----------------------------\ _
- BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
-\ ----------------------------\
- BIT.B #SM_SDA,&I2CSM_IN \ 3 h get SDA
-\ ----------------------------\ _
- BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low 13~
- ADDC.B X,X \ 1 l C <--- X(7) ... X(0) <--- SDA
- SUB #1,W \ 1 l count down of bits
- 0= UNTIL \ 2 l here, slave has set SDA for next bit
-\ --------------------------------\
-\ case of RX data $FF \ case of -1 SYS for example
-\ --------------------------------\
- CMP.B #-1,X \ 1
- 0= IF \ 2 received char $FF: let's consider that the slave is lost...
- MOV #2,X \ to do ABORT action after Nack sent
- THEN \
-\ --------------------------------\
- CMP.B #8,X \ 1 l $08 = char BS
- U>= WHILE \ 2 l ASCII char received, from char 'BS' up to char $7F.
-\ --------------------------------\
-\ I2C_Master_RX Send Ack \ on ASCII char >= $08
-\ --------------------------------\
- BIS.B #SM_SDA,&I2CSM_DIR \ 3 l _ set SDA as Ack
- BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
- BEGIN \ we must wait I2C_Slave software (data processing)
- BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released,
- 0<> UNTIL \ 2 h _ because Slave can strech SCL low
- BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
-\ --------------------------------\
-\ I2C_Master echoes to TERMINAL \
-\ --------------------------------\
- CMP.B #4,&{UARTI2CS}+9 \ 3 W = HALF_DUPLEX = $04 if NOECHO, $05 if ECHO
- 0<> IF
- BEGIN \
- BIT #2,&TERM_IFG \ 3 l UART TX buffer empty ?
- 0<> UNTIL \ 2 l loop if no
- MOV.B X,&TERM_TXBUF \ 3 h send RXed ASCII char to UART TERMINAL
- THEN
- REPEAT \ 2 l loop back to I2C_Master_RX_data for chars >= 8
-\ ------------------------------------\
-\ case of RX CTRL_Chars < $08 \ here Master holds SCL low, Slave can test it: CMP #8,&TERM_STATW
-\ ------------------------------------\ see forthMSP430FR_TERM_I2C.asm
- CMP.B #4,X \ 1
- U>= IF \ 2
- MOV.B X,&{UARTI2CS}+9 \ set NOECHO = $04, ECHO = $05
- BIS.B #SM_SDA,&I2CSM_DIR \ 3 l prepare Ack for Ctrl_Chars $04 $05
- THEN \
-\ ------------------------------------\
-\ Master_RX send Ack/Nack on data \ Ack for $04, $05, Nack for $00, $01, $02
-\ ------------------------------------\ _
- BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
- BEGIN \ we must wait I2C_Slave software (data processing)
- BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released
- 0<> UNTIL \ 2 h (because Slave can strech SCL low)
- BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA as TX Ack/Nack state
- BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
-\ ------------------------------------\ l
- 0<> UNTIL \ if Ack, loop back to Master_RX data for CTRL_Char $04,$05
-\ ----------------------------------------\
-\ Nack is sent by Master \ l case of CTRL-Char {$00|$01|$02}
-\ ----------------------------------------\
- CMP.B #2,X \ $02 = ctrl_char for ABORT request
- U>= WHILE \
-\ ----------------------------------------\
-\ CTRL_Char $02|$03 \ l if ABORT request, SDA is high, SCL is low
-\ ----------------------------------------\
- 0= IF \ if ABORT request $02 :
- MOV.B #0,&{UARTI2CS}+9 \ set echo ON I2C_Master side
- CALL #UART_RXON \ resume UART downloading source file
- BEGIN \
- BIC #UCRXIFG,&TERM_IFG \ clear UCRXIFG
- MOV &FREQ_KHZ,X \ 1000, 2000, 4000, 8000, 16000, 240000
-\ BEGIN MOV #32,W \ 2~ <-------+ windows 10 seems very slow...
-\ BEGIN SUB #1,W \ 1~ <---+ | ==> ((32*3)+5)*FREQ_KHZ/1000 = 101ms delay
-\ 0= UNTIL \ 2~ 3~ loop ---+ | to refill its USB buffer
-\ SUB #1,X \ 1~ |
-\ 0= UNTIL \ 2~ 101~ loop -----+
- BEGIN MOV #65,W \ 2~ <-------+ linux with minicom seems very very slow...
- BEGIN SUB #1,W \ 1~ <---+ | ==> ((65*3)+5)*FREQ_KHZ/1000 = 200ms delay
- 0= UNTIL \ 2~ 3~ loop ---+ | to refill its USB buffer
- SUB #1,X \ 1~ |
- 0= UNTIL \ 2~ 200~ loop -----+
- BIT #UCRXIFG,&TERM_IFG \ 4 new char in TERMRXBUF during this delay ?
- 0= UNTIL \ 2 yes, the input stream may be still active: loop back
- THEN
- REPEAT \ loop back to reSTART RX
-\ --------------------------------------------\
-\ I2C_Master_RX Send STOP \ remainder: CTRL_Chars $00,$01
-\ --------------------------------------------\
- CALL #I2CM_STOP \
-\ vvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvvvvvv\
- BIC.B #LED2,&LED2_OUT \ green led OFF = endof I2C RX
-\ ^^^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^^^^^^^^\
-\ ============================================\
-\ END OF I2C MASTER RX \ here I2C_bus is freed, Nack on Ctrl_char $00|$01 remains to be processed.
-\ ============================================\
- CMP.B #0,X \
-\ --------------------------------------------\
-\ I2C_Slave ACCEPT ctrl_char $00 \ I2C_Slave requests I2C_Master to stop RX
-\ --------------------------------------------\
-\ en début de sa routine ACCEPT, I2C_Slave envoie sur le bus I2C le caractère de contrôle $00
-\ avant de s'endormir avec SLEEP.
-\ Quand I2C_Slave est sorti de son sommeil par un START RX, il renvoie aussi un $00.
-\ I2C_Master envoie alors ce NACK + STOP pour signifier la fin de la transaction.
-\ --------------------------------------------\
-\ I2C_Master se réveillera au premier caractère saisi sur le TERMINAL ==> TERM_INT,
-\ ou en fin du temps TxIFG ==> 500MS_INT \
- 0= IF \ prepare U2I_TERM_INT environment
- MOV #SLEEP,PC \ which executes SLEEP_U2I then RXON, enabling TERMINAL TX, before LPM0 shut down.
- THEN \
-\ --------------------------------------------\
-\ I2C_Slave KEY ctl_char $01 \ I2C_Slave request for KEY input
-\ --------------------------------------------\
-\ Quand I2C_Master reçoit ce caractère de contrôle,
-\ il attend un caractère en provenance de TERMINAL UART
-\ et une fois ce caractère reçu ReStart TX pour l'envoyer à I2C_Slave
- CALL #UART_RXON \ enables TERMINAL to TX; use no registers
- BEGIN \ wait for a char
- BIT #UCRXIFG,&TERM_IFG \ received char ?
- 0<> UNTIL \
- CALL #UART_RXOFF \ stops UART RX; use no registers
- MOV #0,T \ ready to store KEY char as last char to be received
- GOTO BW2 \ goto end of UART RX line input
- ENDCODE \
-\ ********************************************\
-
-\ --------------------------------------------\
- HDNCODE SLEEP_U2I \ new SLEEP_APP subroutine called by SLEEP before shutdown
-\ --------------------------------------------\
- KERNEL_ADDON LF_XTAL TSTBIT \
- [IF] MOV #%1_1001_0100,&TB0CTL ; if ACLK=LFXTAL \ 3 (re)starts RX_timer,ACLK=LFXTAL=32768/4=8192Hz,up mode,clear timer
- [ELSE] MOV #%1_0001_0100,&TB0CTL ; if ACLK=VLO \ 3 (re)starts RX_timer,ACLK=VLO=8kHz, up mode,clear timer
- [THEN] \
- MOV.B &{UARTI2CS}+9,W \ 3 W = HALF_DUPLEX = $04 if NOECHO, $05 if ECHO
- MOV #'CR',S \ 2 S = 'CR' = penultimate char of line to be RXed by UART
- MOV #0,T \ 2 T = init buffer pointer for UART_TERMINAL input
- BIC #BIT6,&P1IFG \ 3 clear P1.6 IFG
- MOV &{UARTI2CS}+2,PC \ which executes RXON, enabling TERMINAL TX, before LPM0 shut down.
- ENDCODE \
-\ --------------------------------------------\
-
-\ ----------------------------\
- HDNCODE INIT_U2I \ adds the INIT_HARD_APP to HARD_APP called by PUC|WARM
-\ ----------------------------\
-\ init 500MS_INT \ used to scan I2C_Slave hard RESET and to slow down (re)START RX loop
-\ ----------------------------\
-\ MOV #%10_1101_0100,&TB0_CTL \ ACLK/4=8192Hz, up mode, clear timer
- MOV #4096,&TB0CCR0 \ time 0.5s
-\ ------------------------------\
-\ set TB0.2 to generate pulse \
-\ ------------------------------\
- MOV #$60,&TB0CCTL2 \ output mode = set/reset
- MOV #4095,&TB0CCR2 \ 0.12 ms pulse
- BIS.B #BIT7,&P1DIR \ P1.7 as output
- BIS.B #BIT7,&P1SEL1 \ P1.7 as TB0.2 output
- BIS.B #BIT6,&P1IE
-\ ----------------------------\
-\ init I2C_MASTER I/O \ see \inc\your_target.pat to find I2C MASTER SDA & SCL pins (as SM_BUS)
-\ ----------------------------\
- BIC.B #SM_BUS,&I2CSM_REN \ remove internal pull up resistors because the next instruction which change them to pull down resistors
- BIC.B #SM_BUS,&I2CSM_OUT \ preset SDA + SCL output LOW
-\ ----------------------------\
-\ vvvvvvvvv OPTION vvvvvvvvvvv\
- BIS.B #LED1,&LED1_DIR \ set red led (I2C TX) pin as output
- BIS.B #LED2,&LED2_DIR \ set green led (I2C RX) pin as output
-\ ^^^^^^^^^ OPTION ^^^^^^^^^^^\
-\ ----------------------------\
-\ run previous INIT_HARD_APP \
-\ ----------------------------\
- CALL &{UARTI2CS} \ execute previous INIT_HARD_APP to init TERM_UC, activates I/O.
-\ ----------------------------\ TOS = SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures
-\ define new SYSRSTIV select \
-\ ----------------------------\
- CMP #$0E,TOS \ SVSHIFG SVSH event ?
- 0<> IF \ if not
- CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas ?
- U>= ?GOTO BW1 \ if yes goto REMOVE_U2I, RET to WARM+4.
- THEN \ else TOS = SYSRSTIV = {$02,$06,$0E} as: {PWR_ON,RST,SVSH_Threshold}
- BIS.B #BIT6,&P1IFG \ to force wake up from SLEEP to execute 500MS_INT.
-\ ----------------------------\
- MOV #ABORT,PC \ skip WARM message, goto ABORT --> ACCEPT --> SLEEP.
- ENDCODE \
-\ ----------------------------\
+\ ****************************************\ | |
+ HDNCODE 500MS_INT \ | |
+\ ****************************************\ | |
+ ADD #4,RSP \ 1 remove PC_RET, SR_RET | |
+\ ----------------------------------------\ | |
+FW1 \ single use forward label \ <──────── does START <────┘ |
+FW2 \ single use forward label \ <──────── if Nack on Address Master TX <────┘
+\ ========================================\
+\ I2C_MASTER RX \
+\ ========================================\
+ PUSH PC \ 3 l PUSH next address as RET for reSTART after collision detection
+\ ----------------------------------------\
+ BEGIN \ Start MASTER RX
+\ ------------------------------------\
+\ I2C MASTER (re)START RX \
+\ ------------------------------------\ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL to enable START RX
+ MOV #1,X \ 1 h to Start MASTER RX
+ CALL #I2CM_START \ 199~ flag Z = 0 if Nack_On_Address
+\ ------------------------------------\
+ 0<> IF \ 2 l if Nack on address
+ CALL #I2CM_STOP \ 28~ generate STOP
+ MOV.B #'.',&TERM_TXBUF \ 4 to view the lack of I2C_target at the I2C_Addr provided.
+ MOV.B #-1,&DUPLEX_MODE \ 3 set 'no_I2C_Slave' flag
+ MOV #BACKGRND,PC \ 29~ which calls BACKGRND_U2I then RXON before LPM0 shut down.
+ THEN \ (275 cycles for 500MS_INT)
+ CMP.B #-1,Y \ 1 l return of I2C_Slave on bus ?
+ 0= IF \ 2 l if yes
+ MOV.B #0,Y \ clear 'no_I2C_Slave' flag, ECHO is ON
+ MOV.B #'CR',&TERM_TXBUF \ send CR+LF to terminal
+ BEGIN \
+ BIT #TX,&TERM_IFG \
+ 0<> UNTIL \
+ MOV.B #'LF',&TERM_TXBUF \
+ THEN \
+\ ====================================\
+\ I2C Master RX data \
+\ ====================================\
+ [DEFINED] LEDS [IF]
+ BIS.B #LED2,&LED2_OUT \ 3 l green led ON = I2C RX
+ [THEN]
+\ ------------------------------------\
+ BEGIN \ l
+ BEGIN \ l
+ BIC.B #SM_SDA,&I2CSM_DIR \ 4 l after Ack and before RX next byte, we must release SDA
+ MOV.B #8,W \ 2 l count for 8 data bits
+ BEGIN \ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low 13~
+ ADDC.B X,X \ 1 l C <--- X(7) ... X(0) <--- SDA
+ SUB #1,W \ 1 l count down of bits
+ 0= UNTIL \ 2 l
+\ ----------------------------\
+\ case of RX data $FF \ case of -1 SYS for example
+\ ----------------------------\
+ CMP.B #-1,X \ 1 l received char $FF ? let's consider that the slave is lost...
+ 0<> WHILE \ 2 l
+\ ----------------------------\
+ CMP.B #8,X \ 1 l $08 = char BS
+ U>= WHILE \ 2 l ASCII char received, from char 'BS' up to char $FE.
+\ ----------------------------\
+\ I2C_Master_RX Send Ack \ on char {$08...$FE}
+\ ----------------------------\
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l _ set SDA low to do Ack
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \ we must wait I2C_Slave software (data processing)
+ BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released,
+ 0<> UNTIL \ 2 h _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+\ ----------------------------\
+\ I2C_Master echo to TERMINAL \
+\ ----------------------------\
+ CMP.B #4,Y \ 1 $04 = NOECHO request
+ 0<> IF \ 2
+ BEGIN \
+ BIT #TX,&TERM_IFG \ 3 l UART TX buffer empty ?
+ 0<> UNTIL \ 2 l loop if no
+ MOV.B X,&TERM_TXBUF \ 3 l send RXed char to UART TERMINAL
+ THEN \
+ REPEAT \ 2 l loop back to RX data
+\ --------------------------------\
+\ case of RX CTRL_Char {$00...$07}\ here Master holds SCL low, Slave can test it: CMP #8,&TERM_STATW
+\ --------------------------------\ see forthMSP430FR_TERM_I2C.asm
+ CMP.B #4,X \ 1
+ U>= IF \ 2
+ MOV.B X,Y \ NOECHO = $04, ECHO = {$05...$07}
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l prepare SDA low = Ack for Ctrl_Chars {$04...$07}
+ THEN \
+\ --------------------------------\
+ THEN \ false branch of CMP.B #-1,X 0<> WHILE
+\ --------------------------------\
+\ Master_RX send Ack/Nack on data \ Ack for {$04...$07,$08...$FE}, Nack for {$FF...$03}
+\ --------------------------------\ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \ we must wait I2C_Slave software (data processing)
+ BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released
+ 0<> UNTIL \ 2 h (because Slave may strech SCL low)
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA as TX Ack/Nack state
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+\ --------------------------------\
+ 0<> UNTIL \ 2 l if Ack, loop back to Master_RX data after CTRL_Chars {$04...$07,$08...$FE}
+\ ------------------------------------\
+\ Nack is sent by Master \ case of CTRL-Chars {$FF...$03}, SDA is high, SCL is low
+\ ------------------------------------\
+ CMP.B #2,X \
+ U>= WHILE \ l out of loop for CTRL_chars {$00,$01}
+\ ------------------------------------\
+\ CTRL_Char {$02,$03,$FF} \ only CTRL_Char $FF is used
+\ ------------------------------------\
+ MOV.B #0,Y \ set echo ON
+ CALL #UART_RXON \ resume UART downloading source file
+ BEGIN \
+ BIC #RX,&TERM_IFG \ clear UCRXIFG
+ MOV &FREQ_KHZ,X \ 1000, 2000, 4000, 8000, 16000, 240000
+ BEGIN MOV #65,W \ 2~ <-------+ wait time for TERMINAL to refill its USB buffer
+ BEGIN SUB #1,W \ 1~ <---+ | ==> ((65*3)+5)*FREQ_KHZ/1000 = 200ms delay
+ 0= UNTIL \ 2~ 3~ loop ---+ |
+ SUB #1,X \ 1~ |
+ 0= UNTIL \ 2~ 200~ loop -----+
+ BIT #RX,&TERM_IFG \ 4 new char in TERMRXBUF during this delay ?
+ 0= UNTIL \ 2 yes, the input stream is still active: loop back
+ REPEAT \ l loop back to reSTART RX on WARM|ABORT messages.
+\ ----------------------------------------\
+\ I2C_Master_RX Send STOP \ remainder: CTRL_Chars {$00,$01}
+\ ----------------------------------------\
+ CALL #I2CM_STOP \
+\ ========================================\
+\ END OF I2C MASTER RX datas \ here I2C_bus is freed, CTRL_chars $00|$01 remain to be processed.
+\ ========================================\
+ [DEFINED] LEDS [IF]
+ BIC.B #LED2,&LED2_OUT \ green led OFF = endof I2C RX
+ [THEN]
+\ ========================================\
+ CMP.B #0,X \
+\ ----------------------------------------\
+\ I2C_Slave ACCEPT ctrl_char $00 \ case of request by I2C_Slave ACCEPT
+\ ----------------------------------------\
+ 0= IF \
+ MOV.B Y,&DUPLEX_MODE \ save updated NOECHO flag before RET
+ MOV #BACKGRND,PC \ which calls BACKGRND_U2I, RXON enabling TERMINAL TX, then LPM0 shut down.
+ THEN \
+\ ----------------------------------------\
+\ I2C_Slave KEY ctl_char $01 \ I2C_Slave request for KEY input
+\ ----------------------------------------\
+ CALL #UART_RXON \ enables TERMINAL to TX; use no registers
+ BEGIN \ wait for a char
+ BIT #RX,&TERM_IFG \ received char ?
+ 0<> UNTIL \
+ CALL #UART_RXOFF \ stops UART RX; use no registers
+ MOV #0,T \ ready to store KEY char as last char to be received
+ GOTO BW2 \ goto the end of UART RX line input
+ ENDCODE \
+\ ****************************************\
\
\
\ ==============================================================================
\ Driver UART to I2C to do a bridge USB to I2C_FastForth devices
\ ==============================================================================
\
-\ I2C address mini = 10h, maxi = 0EEh (I2C-bus specification and user manual V6)
-\ type on TERMINAL "$12 UARTI2CS" to link teraterm TERMINAL with FastForth I2C_Slave target at address $12
-
-\ UARTI2CS starts the USB to I2C bridge, to quit: TERATERM(Alt-B) or USB_to_I2C_bridge(SW2)
-\ --------------------------------\
- : UARTI2CS \ I2C_Addr&b0 --
-\ --------------------------------\ init UARTI2CS environment.
- 'CR' EMIT 'LF' EMIT \
- HI2LO
- MOV @RSP+,IP \
- BEGIN
- BIT #1,&TERM_STATW \ uart busy ?
- 0= UNTIL \ wait end of 'LF' TX
- CMP #RET_ADR,&{UARTI2CS}-2 \
- 0= IF
- MOV #REMOVE_U2I,&{UARTI2CS}-2 \ MARKER_DOES of {UARTI2CS} will CALL &{UARTI2CS}-2 = CALL #REMOVE_U2I
- MOV &HARD_APP,&{UARTI2CS} \ save previous HARD_APP to {UARTI2CS}
- MOV &SLEEP_APP,&{UARTI2CS}+2 \ save previous SLEEP_APP to {UARTI2CS}+2
- MOV &TERM_VEC,&{UARTI2CS}+4 \ save previous TERM_VEC value to {UARTI2CS}+4, see target.pat
- MOV &P1_VEC,&{UARTI2CS}+6 \ save previous P1_VEC value to {UARTI2CS}+6
- MOV TOS,&{UARTI2CS}+8 \ -- I2C_Addr&0 save I2C address, set ECHO
-\ MOV.B #0,&{UARTI2CS}+9 \ set ECHO ON
- THEN
- MOV #0,TOS \ -- 0 to enter in INIT_U2I with 0 SYS
- MOV #INIT_U2I,&HARD_APP \ replace HARD_APP by new INIT_U2I
- MOV #SLEEP_U2I,&SLEEP_APP \ replace HARD_APP by new INIT_U2I
- MOV #U2I_TERM_INT,&TERM_VEC \ set TERM_VEC with U2I_TERM_INT
- MOV #500MS_INT,&P1_VEC \ set P1_VEC as 500MS_INT
- MOV #INIT_U2I,PC \ load INIT_U2I
- ENDCODE \
-\ --------------------------------\
+\ I2C_address<<1 mini = $10, maxi = $EE (I2C-bus specification and user manual V6)
+\ type on TERMINAL "$12 START_U2I" to link teraterm TERMINAL with FastForth I2C_Slave target at address $12
- RST_SET ECHO
+\ ------------------------------------\
+ CODE START_U2I \ I2C_Addr<<1 --
+\ ------------------------------------\
+ SUB #2,PSP \ DUP
+ MOV TOS,0(PSP) \
+ COLON \ ASSEMBLER switch to FORTH with IP backup
+ 'CR' EMIT 'LF' EMIT \
+ ." Connect to I2C_SLAVE at @" \
+ . 'BS' EMIT \ display number without space after
+ ." , TERATERM(Alt-B) " \
+ ." or I2C_MASTER(S2) to quit..." \
+ HI2LO \ FORTH switch to ASSEMBLER
+ MOV @RSP+,IP \ restore IP
+ BEGIN \
+ BIT #1,&TERM_STATW \ uart busy ?
+ 0= UNTIL \ wait end of TX last char
+ CMP #RET_ADR,&{UARTI2CS}-2 \ USER_DOES default value ?
+ 0= IF \ if yes
+ MOV #REMOVE_U2I,&{UARTI2CS}-2 \ USER_DOES of {UARTI2CS} will CALL &{UARTI2CS}-2 = CALL #REMOVE_U2I
+ MOV &STOP_APP,&{UARTI2CS} \ save STOP_APP value to {UARTI2CS}
+ MOV &HARD_APP,&{UARTI2CS}+2 \ save HARD_APP value to {UARTI2CS}+2
+ MOV &BACKGRND_APP,&{UARTI2CS}+4 \ save BACKGRND_APP value to {UARTI2CS}+4
+ MOV &TERM_VEC,&{UARTI2CS}+6 \ save TERM_VEC value to {UARTI2CS}+6
+ MOV &INT_IN_VEC,&{UARTI2CS}+8 \ save INT_IN_VEC value to {UARTI2CS}+8
+ MOV #STOP_U2I,&STOP_APP \ set STOP_APP with STOP_U2I addr
+ MOV #HARD_U2I,&HARD_APP \ set HARD_APP with HARD_U2I addr
+ MOV #BACKGRND_U2I,&BACKGRND_APP \ set BACKGRND_APP with BACKGRND_U2I addr
+ MOV #U2I_TERM_INT,&TERM_VEC \ set TERM_VEC with U2I_TERM_INT addr
+ MOV #500MS_INT,&INT_IN_VEC \ set INT_IN_VEC with 500MS_INT addr
+\ --------------------------------\
+ MOV TOS,&UARTI2CS_ADR \ save I2C_address<<1 at {UARTI2CS}+10
+ KERNEL_ADDON LF_XTAL TSTBIT \ test ACLK source before compilation
+ [IF] MOV #$0194,&TIMER_CONF \ start RX_timer,ACLK=LFXTAL=32768/4=8192Hz,up mode
+ [ELSE] MOV #$0114,&TIMER_CONF \ start RX_timer,ACLK=VLO=8kHz, up mode
+ [THEN] \
+ FREQ_KHZ @ 24000 = \ in assembly mode the FORTH interpreter is always active, let's enjoy it...
+ [IF] MOV #116,&COLLISION_DLY \ )
+ [ELSE] FREQ_KHZ @ 16000 = \ )
+ [IF] MOV #76,&COLLISION_DLY \ > set 20us delay = (delay*MHz/4 -4, and set ECHO (<>4)
+ [ELSE] MOV #36,&COLLISION_DLY \ )
+ [THEN] \ )
+ [THEN] \
+ THEN \
+ MOV #0,TOS \ -- 0 to enter in HARD_U2I with 0 SYS
+ GOTO BW3 \ goto HARD_U2I as new HARD_APP, direct return to ABORT
+ ENDCODE \
+\ ------------------------------------\
- $12 UARTI2CS ; TERATERM(Alt-B) or USB_to_I2C_bridge(SW2) to quit
+RST_SET ECHO \ RST_SET defines the new bound of program memory protected against any (positive) SYS event,
+ \ and so protects the MARKER structure before its use by START_U2I:
+\
+#18 START_U2I \ $12 is the wanted I2C_Slave_Address<<1 to link
\ -*- coding: utf-8 -*-
-
\
\ to see kernel options, download FastForthSpecs.f
\ FastForth kernel options: MSP430ASSEMBLER, CONDCOMP
; UTILITY.f
; --------------------------------
-\ first, we test for downloading driver only if UART TERMINAL target
+\ first, we do some tests allowing the download
CODE ABORT_UTILITY
SUB #2,PSP
MOV TOS,0(PSP)
MOV &VERSION,TOS
- SUB #309,TOS \ FastForth V3.9
+ SUB #400,TOS \ FastForth V4.0
COLON
'CR' EMIT \ return to column 1 without 'LF'
- ABORT" FastForth V3.9 please!"
+ ABORT" FastForth V4.0 please!"
RST_RET \ remove ABORT_UTILITY definition before resuming
;
ABORT_UTILITY
+ [DEFINED] {UTILITY}
+ [IF] {UTILITY}
+ [THEN]
+ [UNDEFINED] {UTILITY}
+ [IF]
MARKER {UTILITY}
+; ------------------------------------------------------------------
+; first we download the set of definitions we need (from CORE_ANS.f)
+; ------------------------------------------------------------------
+
+ [UNDEFINED] EXIT [IF]
\ https://forth-standard.org/standard/core/EXIT
\ EXIT -- exit a colon definition; CALL #EXIT performs ASMtoFORTH (10 cycles)
\ JMP #EXIT performs EXIT
- [UNDEFINED] EXIT
- [IF]
CODE EXIT
MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack
MOV @IP+,PC \ 4 = NEXT
ENDCODE
[THEN]
+ [UNDEFINED] SWAP [IF]
\ https://forth-standard.org/standard/core/SWAP
\ SWAP x1 x2 -- x2 x1 swap top two items
- [UNDEFINED] SWAP
- [IF]
CODE SWAP
MOV @PSP,W \ 2
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] U< [IF]
\ https://forth-standard.org/standard/core/Uless
\ U< u1 u2 -- flag test u1<u2, unsigned
- [UNDEFINED] U<
- [IF]
CODE U<
SUB @PSP+,TOS \ 2 u2-u1
0<> IF
ENDCODE
[THEN]
+ [UNDEFINED] IF [IF] \ define IF and THEN
\ https://forth-standard.org/standard/core/IF
\ IF -- IFadr initialize conditional forward branch
- [UNDEFINED] IF
- [IF] \ define IF and THEN
CODE IF \ immediate
SUB #2,PSP \
MOV TOS,0(PSP) \
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
\ https://forth-standard.org/standard/core/BEGIN
\ BEGIN -- BEGINadr initialize backward branch
- [UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT
CODE BEGIN
- MOV #HEREXEC,PC
+ MOV #BEGIN,PC
ENDCODE IMMEDIATE
\ https://forth-standard.org/standard/core/UNTIL
; IMMEDIATE
[THEN]
-\ https://forth-standard.org/standard/core/DO
-\ DO -- DOadr L: -- 0
- [UNDEFINED] DO
- [IF] \ define DO LOOP +LOOP
+ [UNDEFINED] DO [IF] \ define DO LOOP +LOOP
+
HDNCODE XDO \ DO run time
MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor"
SUB @PSP+,X \ 2
MOV @IP+,PC \ 4
ENDCODE
+\ https://forth-standard.org/standard/core/DO
+\ DO -- DOadr L: -- 0
CODE DO \ immediate
SUB #2,PSP \
MOV TOS,0(PSP) \
MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop
ENDCODE \
+\ https://forth-standard.org/standard/core/LOOP
+\ LOOP DOadr -- L-- an an-1 .. a1 0
CODE LOOP
MOV #XLOOP,X
BW2 ADD #4,&DP \ make room to compile two words
MOV @IP+,PC
ENDCODE IMMEDIATE
-\ https://forth-standard.org/standard/core/PlusLOOP
-\ +LOOP adrs -- L-- an an-1 .. a1 0
HDNCODE XPLOO \ +LOOP run time
ADD TOS,0(RSP) \ 4 increment INDEX by TOS value
MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags
GOTO BW1 \ 2
ENDCODE \
+\ https://forth-standard.org/standard/core/PlusLOOP
+\ +LOOP adrs -- L-- an an-1 .. a1 0
CODE +LOOP
MOV #XPLOO,X
GOTO BW2
ENDCODE IMMEDIATE
[THEN]
+ [UNDEFINED] I [IF]
\ https://forth-standard.org/standard/core/I
\ I -- n R: sys1 sys2 -- sys1 sys2
\ get the innermost loop index
- [UNDEFINED] I
- [IF]
CODE I
SUB #2,PSP \ 1 make room in TOS
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] DUP [IF] \ define DUP and ?DUP
\ https://forth-standard.org/standard/core/DUP
\ DUP x -- x x duplicate top of stack
- [UNDEFINED] DUP
- [IF] \ define DUP and ?DUP
CODE DUP
BW1 SUB #2,PSP \ 2 push old TOS..
MOV TOS,0(PSP) \ 3 ..onto stack
ENDCODE
[THEN]
+ [UNDEFINED] DROP [IF]
\ https://forth-standard.org/standard/core/DROP
\ DROP x -- drop top of stack
- [UNDEFINED] DROP
- [IF]
CODE DROP
MOV @PSP+,TOS \ 2
MOV @IP+,PC \ 4
ENDCODE
[THEN]
+ [UNDEFINED] >R [IF]
\ https://forth-standard.org/standard/core/toR
\ >R x -- R: -- x push to return stack
- [UNDEFINED] >R
- [IF]
CODE >R
PUSH TOS
MOV @PSP+,TOS
ENDCODE
[THEN]
+ [UNDEFINED] R> [IF]
\ https://forth-standard.org/standard/core/Rfrom
\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
- [UNDEFINED] R>
- [IF]
CODE R>
SUB #2,PSP \ 1
MOV TOS,0(PSP) \ 3
ENDCODE
[THEN]
+ [UNDEFINED] SPACE [IF]
\ https://forth-standard.org/standard/core/SPACE
\ SPACE -- output a space
- [UNDEFINED] SPACE
- [IF]
: SPACE
$20 EMIT ;
[THEN]
+ [UNDEFINED] SPACES [IF]
\ https://forth-standard.org/standard/core/SPACES
\ SPACES n -- output n spaces
- [UNDEFINED] SPACES
- [IF]
CODE SPACES
CMP #0,TOS
0<> IF
ENDCODE
[THEN]
+ [UNDEFINED] 2DUP [IF]
\ https://forth-standard.org/standard/core/TwoDUP
\ 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells
- [UNDEFINED] 2DUP
- [IF] \
CODE 2DUP
MOV TOS,-2(PSP) \ 3
MOV @PSP,-4(PSP) \ 4
ENDCODE
[THEN]
+ [UNDEFINED] 1+ [IF]
\ https://forth-standard.org/standard/core/OnePlus
\ 1+ n1/u1 -- n2/u2 add 1 to TOS
- [UNDEFINED] 1+
- [IF]
CODE 1+
ADD #1,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] + [IF]
\ https://forth-standard.org/standard/core/Plus
\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
- [UNDEFINED] +
- [IF]
CODE +
ADD @PSP+,TOS
MOV @IP+,PC
ENDCODE
[THEN]
+ [UNDEFINED] - [IF]
\ https://forth-standard.org/standard/core/Minus
\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
- [UNDEFINED] -
- [IF]
CODE -
SUB @PSP+,TOS \ 2 -- n2-n1
XOR #-1,TOS \ 1
ENDCODE
[THEN]
+ [UNDEFINED] C@ [IF]
\ https://forth-standard.org/standard/core/CFetch
\ C@ c-addr -- char fetch char from memory
- [UNDEFINED] C@
- [IF]
CODE C@
MOV.B @TOS,TOS
MOV @IP+,PC
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/AND
-\ C AND x1 x2 -- x3 logical AND
- [UNDEFINED] AND
- [IF]
- CODE AND
- AND @PSP+,TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
-
+ [UNDEFINED] ROT [IF]
\ https://forth-standard.org/standard/core/ROT
\ ROT x1 x2 x3 -- x2 x3 x1
- [UNDEFINED] ROT
- [IF]
CODE ROT
MOV @PSP,W \ 2 fetch x2
MOV TOS,0(PSP) \ 3 store x3
ENDCODE
[THEN]
- [UNDEFINED] MAX
- [IF] \ define MAX and MIN
+ [UNDEFINED] MAX [IF] \ define MAX and MIN
CODE MAX \ n1 n2 -- n3 signed maximum
CMP @PSP,TOS \ n2-n1
S< ?GOTO FW1 \ n2<n1
ENDCODE
[THEN]
+ [UNDEFINED] OVER [IF]
\ https://forth-standard.org/standard/core/OVER
\ OVER x1 x2 -- x1 x2 x1
- [UNDEFINED] OVER
- [IF]
CODE OVER
MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
MOV @PSP,TOS \ 2 -- x1 (x2) x1
ENDCODE
[THEN]
+ [UNDEFINED] MOVE [IF]
\ https://forth-standard.org/standard/core/MOVE
\ MOVE addr1 addr2 u -- smart move
\ VERSION FOR 1 ADDRESS UNIT = 1 CHAR
- [UNDEFINED] MOVE
- [IF]
CODE MOVE
MOV TOS,W \ W = cnt
MOV @PSP+,Y \ Y = addr2 = dst
ENDCODE
[THEN]
+ [UNDEFINED] CR [IF]
+\ https://forth-standard.org/standard/core/CR
+\ CR -- send CR+LF to the output device
+ CODE CR \ create a DEFER definition of CR
+ MOV #NEXT_ADR,PC
+ ENDCODE
+
+ :NONAME
+ 'CR' EMIT 'LF' EMIT
+ ; IS CR
+ [THEN]
+
+ [UNDEFINED] 2* [IF]
+\ https://forth-standard.org/standard/core/TwoTimes
+\ 2* x1 -- x2 arithmetic left shift
+ CODE 2*
+ ADD TOS,TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] 2/ [IF]
+\ https://forth-standard.org/standard/core/TwoDiv
+\ 2/ x1 -- x2 arithmetic right shift
+ CODE 2/
+ RRA TOS
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+ [UNDEFINED] CONSTANT [IF]
\ https://forth-standard.org/standard/core/CONSTANT
\ CONSTANT <name> n -- define a Forth CONSTANT
- [UNDEFINED] CONSTANT
- [IF]
: CONSTANT
CREATE
HI2LO
ENDCODE
[THEN]
+ [UNDEFINED] BASE [IF]
\ https://forth-standard.org/standard/core/BASE
\ BASE -- a-addr holds conversion radix
- [UNDEFINED] BASE
- [IF]
BASEADR CONSTANT BASE
[THEN]
+ [UNDEFINED] HERE [IF]
+\ https://forth-standard.org/standard/core/HERE
+\ HERE -- addr addr is the data-space pointer.
+ CODE HERE
+ MOV #BEGIN,PC \ execute ASM BEGIN
+ ENDCODE
+ [THEN]
+
+; --------------------------
+; end of definitions we need
+; --------------------------
+
+ [UNDEFINED] .S [IF]
\ https://forth-standard.org/standard/tools/DotS
\ .S TOS -- TOS display <depth> of param Stack and stack contents in hexadecimal if not empty
- [UNDEFINED] .S
- [IF] \
CODE .S
MOV TOS,-2(PSP) \ -- TOS ( TOS x x )
MOV PSP,TOS \ -- PSP ( TOS x x )
;
[THEN]
+ [UNDEFINED] .RS [IF]
\ .RS TOS -- TOS display <depth> of Return Stack and stack contents if not empty
- [UNDEFINED] .RS
- [IF] \
CODE .RS
MOV TOS,-2(PSP) \ -- TOS ( TOS x x )
MOV RSP,-6(PSP) \ -- TOS ( TOS x RSP )
ENDCODE
[THEN]
+ [UNDEFINED] ? [IF]
\ https://forth-standard.org/standard/tools/q
\ ? adr -- display the content of adr
- [UNDEFINED] ?
- [IF] \
CODE ?
MOV @TOS,TOS
MOV #U.,PC \ goto U.
ENDCODE
[THEN]
-\ https://forth-standard.org/standard/core/CR
-\ CR -- send CR+LF to the output device
- [UNDEFINED] CR
- [IF]
-
-\ DEFER CR \ DEFERed definition, by default executes that of :NONAME
- CODE CR \ create a DEFER definition of CR
- MOV #NEXT_ADR,PC
- ENDCODE
-
- :NONAME
- 'CR' EMIT 'LF' EMIT
- ; IS CR
- [THEN]
-
-\ https://forth-standard.org/standard/core/TwoDiv
-\ 2/ x1 -- x2 arithmetic right shift
- [UNDEFINED] 2/
- [IF]
- CODE 2/
- RRA TOS
- MOV @IP+,PC
- ENDCODE
- [THEN]
-
+ [UNDEFINED] WORDS [IF]
\ https://forth-standard.org/standard/tools/WORDS
\ list all words of vocabulary first in CONTEXT.
- [UNDEFINED] WORDS
- [IF]
: WORDS \ --
CR
CONTEXT @ PAD_ORG \ -- VOC_BODY PAD_ORG MOVE all threads of VOC_BODY in PAD_ORG
- THREADS @ DUP + \ -- VOC_BODY PAD_ORG THREAD*2
+ THREADS @ 2* \ -- VOC_BODY PAD_ORG THREAD*2
MOVE \ -- vocabumary entries are copied in PAD_ORG
BEGIN \ --
0 DUP \ -- ptr=0 MAX=0
- THREADS @ DUP + 0 \ -- ptr=0 MAX=0 THREADS*2 0
+ THREADS @ 2* 0 \ -- ptr=0 MAX=0 THREADS*2 0
DO \ -- ptr MAX I = PAD_ptr = thread*2
- DUP I PAD_ORG + @ \ -- ptr MAX MAX NFAx
+ DUP I PAD_ORG + @ \ -- ptr MAX MAX NFAx
U< IF \ -- ptr MAX if MAX U< NFAx
DROP DROP \ -- drop ptr and MAX
I DUP
;
[THEN]
+ [UNDEFINED] DUMP [IF]
\ https://forth-standard.org/standard/tools/DUMP
- [UNDEFINED] DUMP
- [IF]
CODE DUMP \ adr n -- dump memory
PUSH IP
PUSH &BASEADR \ save current base
ADD @PSP,TOS \ -- ORG END
LO2HI
SWAP \ -- END ORG
- $FFF0 AND \ -- END ORG_modulo_16
+ CR
+ 4 SPACES $10 0 DO I 3 U.R LOOP
DO CR \ generate line
- I 4 U.R SPACE \ generate address
- I 8 + I \ display first 8 bytes
- DO I C@ 3 U.R LOOP
- SPACE
- I $10 + I 8 + \ display last 8 bytes
+ I 4 U.R \ generate address
+ I $10 + I
DO I C@ 3 U.R LOOP
SPACE SPACE
- I $10 + I \ display 16 chars
+ I $10 + I \ display 16 chars
DO I C@ $7E MIN $20 MAX EMIT LOOP
$10 +LOOP
R> BASE ! \ restore current base
RST_SET
- [THEN] ECHO ; endof [UNDEFINED] {TOOLS}
+ [THEN] \ endof [UNDEFINED] {UTILITY}
+
+ ECHO
--- /dev/null
+\ -*- coding: utf-8 -*-
+\ http://patorjk.com/software/taag/#p=display&f=Banner&t=Fast Forth
+
+\ Fast Forth For Texas Instrument MSP430FRxxxx FRAM devices
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY; without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+\ REGISTERS USAGE
+\ rDODOES to rEXIT must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT, rDOVAR, rDOCON, rDODOES
+\ example : PUSHM IP,Y
+\
+\ POPM order : rDODOES, rDOCON, rDOVAR, rEXIT, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ FORTH conditionnals: unary{ 0= 0< 0> }, binary{ = < > U< }
+
+\ ASSEMBLER conditionnal usage with IF UNTIL WHILE S< S>= U< U>= 0= 0<> 0>=
+
+\ ASSEMBLER conditionnal usage with ?JMP ?GOTO S< S>= U< U>= 0= 0<> <0
+
+
+
+\ https://forth-standard.org/standard/string/COMPARE
+\ COMPARE ( c-addr1 u1 c-addr2 u2 -- flag )
+\Compare the string specified by c-addr1 u1 to the string specified by c-addr2 u2.
+\The strings are compared, beginning at the given addresses, character by character,
+\up to the length of the shorter string or until a difference is found.
+\If the two strings are identical, n is zero.
+\If the two strings are identical up to the length of the shorter string,
+\ n is minus-one (-1) if u1 is less than u2 and one (1) otherwise.
+\If the two strings are not identical up to the length of the shorter string,
+\ n is minus-one (-1) if the first non-matching character in the string specified by c-addr1 u1
+\ has a lesser numeric value than the corresponding character in the string specified by c-addr2 u2 and one (1) otherwise.
+CODE COMPARE
+ MOV TOS,S \ 1 S = u2
+ MOV @PSP+,Y \ 2 Y = addr2
+ MOV @PSP+,T \ 2 T = u1
+ MOV @PSP+,X \ 2 X = addr1
+BEGIN MOV T,TOS \ 1
+ ADD S,TOS \ 1 TOS = u1+u2
+ 0= ?GOTO FW3 \ 2 u1=u2=0, Z=1, end of all successfull comparisons
+ SUB #1,T \ 1
+ 0< ?GOTO FW1 \ 2 u1<u2 if u1 < 0
+ SUB #1,S \ 1
+ 0< ?GOTO FW2 \ 2 u1>u2 if u2 < 0
+ ADD #1,X \ 1
+ CMP.B @Y+,-1(X) \ 4 char1-char2
+0<> UNTIL \ 2 char1=char2 17~ loop
+U< IF \ 2
+FW1 MOV #-1,TOS \ 1 -- -1 Z=0
+ MOV @IP+,PC \ 4
+THEN
+FW2 MOV #1,TOS \ 1 -- 1 Z=0
+FW3 MOV @IP+,PC \ 4 20 + 6 def'n words
+
+
+
+CODE F>S \ convert a s15q16 (signed) number to a signed number (rounded)
+CMP #0,0(PSP) \
+ADD #2,PSP
+S< IF
+ ADD #1,TOS
+THEN
+NEXT \ 4
+ENDCODE
+ \
+
+\ input: file size double word Sector_per_cluster {1,2,4,8,16,32,64}
+\ output cluster double word and cluster offset
+CODE SD_DIV \ SIZ_LO SIZ_HI SECPERCLU -- CLU_LO CLU_HI OFFSET
+MOV.B 3(PSP),Y \ Y = 0:CurSizeLOHi
+MOV.B @PSP,X \ X = 0:CurSizeHILo
+SWPB X \ X = CurSizeHIlo:0
+ADD Y,X \ X = CurSizeHIlo:CurSizeLOhi
+MOV.B 1(PSP),Y \ Y:X = CurSize / 256
+\ RRA Y \ Y = Sectors number_High
+\ RRC X \ X = Sectors number_Low
+
+MOV.B TOS,T \ T = divisor = SECPERCLU
+
+MOV #0,W \ 1 W = 0:REMlo = 0
+MOV #8,S \ 1 CNT
+\ RRA T \ 1 0>0:SPClo>C preshift one right DIVISOR
+BEGIN
+ RRA Y \ 1 0>SEC_HI>C
+ RRC X \ 1 C>SEC_LO>C
+ RRC.B W \ 1 C>REMlo>C
+ SUB #1,S \ CNT-1
+ RRA T \ 1 0>SPChi:SPClo>C
+U>= UNTIL
+BEGIN
+ RRA W \ 1 0>0:REMlo>C
+ SUB #1,S \ 1 CNT-1
+\ 0= UNTIL \ Y = OFFSET, S = CLU_LO, W = CLU_HI
+S< UNTIL \ Y = OFFSET, S = CLU_LO, W = CLU_HI
+MOV.B W,TOS \ -- xx xx REMlo
+MOV X,2(PSP) \ -- CLU_LO xx OFFSET
+MOV Y,0(PSP) \ -- CLU_LO CLU_HI OFFSET
+MOV @IP+,PC
+ENDCODE
+
+
+\ tests tools
+\ -----------
+ \
+
+VARIABLE >PAD \ declaration to do in start of source file
+PAD IS >PAD \ init >PAD, idem
+ \
+
+\ sample anything during an interrupt for example
+\ usage in ASSEMBLER WORD : ... LO2HI SAMPLE HI2LO ... if IP is already saved
+\ usage in ASSEMBLER WORD : ... PUSH IP LO2HI SAMPLE HI2LO MOV @RSP+,IP ... if IP is not already saved
+\ usage in FORTH WORD : ... SAMPLE ...
+
+CODE SAMPLE2PAD
+CMP #TIB,&>PAD \ 4 do nothing if [>PAD] = TIB
+0<> IF \ 2
+ MOV &>PAD,rDOVAR \ 3 rDOVAR = rDOVAR
+ MOV &TA0R,0(rDOVAR) \ 5 we want sample TB0R
+ MOV W,2(rDOVAR)
+ ADD #4,&>PAD \ 3
+ MOV #R>,rDOVAR \ 2 RFROM ==> rDOVAR
+THEN \
+MOV @IP+,PC \ 4
+ENDCODE \ add LO2HI = 10 + 23 = 33 cycles ==> 4us @ 8MHz
+ \
+
+\ display samples, up to 42 samples
+CODE DISPLAY_S \ --
+CMP #PAD,&>PAD
+0= IF
+ NEXT
+THEN
+COLON
+CR
+>PAD @ PAD DO \ limit first --
+ I @ U.
+2 +LOOP
+PAD IS >PAD \ reset >PAD
+;
+ \
+
+
+
+
+DEFER TEST
+ \
+CODE NOOP \ compile MOV #NEXT,PC
+NEXT
+ENDCODE
+ \
+
+CODE SAMPLE. \ display what you want ( much slower than SAMPLE2PAD )
+ SUB #4,PSP
+ MOV TOS,2(PSP)
+ MOV &BASE,0(PSP)
+ MOV &GPFLAGS,TOS \ we want sample GPFLAGS
+ MOV #$10,&BASE
+ PUSHM S,Y
+ COLON
+ ." $" U.
+ BASE !
+ HI2LO
+ MOV @RSP+,IP
+ POPM Y,S
+ NEXT
+ENDCODE
+ \
+
--- /dev/null
+\ fibonacci.4th
+
+
+: (
+$29 WORD DROP
+; IMMEDIATE
+ \
+
+
+CODE 1-
+SUB #1,R14
+MOV @R13+,R0
+ENDCODE
+ \
+
+CODE 2-
+SUB #2,R14
+MOV @R13+,R0
+ENDCODE
+ \
+
+
+: BENCHME ( xt n -- )
+ DUP >R
+ 0 DO DUP EXECUTE LOOP DROP
+ 7 EMIT \ BEEP
+ CR R> . ." Iterations." CR ;
+
+
+
+: fib1 ( n1 -- n2 )
+ dup 2 < if drop 1 exit then
+ dup 1- recurse
+ swap 2- recurse + ;
+ \
+
+: fib1-bench 20 0 do i fib1 drop loop ;
+ \
+
+: fib2 ( n1 -- n2 )
+ 0 1 rot 0 do
+ over + swap loop
+ drop ;
+ \
+
+: fib2-bench 1000 0 do i fib2 drop loop ;
+ \
+
+
+( 2017-09-15)
+( DTC=1, MSP430FR4133 8MHz --> 50s )
+' FIB1-BENCH 100 BENCHME
\ No newline at end of file
--- /dev/null
+\ ForthNesting.4th
+
+PWR_STATE
+
+: bottom ;
+: 1st bottom bottom ; : 2nd 1st 1st ; : 3rd 2nd 2nd ;
+: 4th 3rd 3rd ; : 5th 4th 4th ; : 6th 5th 5th ;
+: 7th 6th 6th ; : 8th 7th 7th ; : 9th 8th 8th ;
+: 10th 9th 9th ; : 11th 10th 10th ; : 12th 11th 11th ;
+: 13th 12th 12th ; : 14th 13th 13th ; : 15th 14th 14th ;
+: 16th 15th 15th ; : 17th 16th 16th ; : 18th 17th 17th ;
+: 19th 18th 18th ; : 20th 19th 19th ; : 21th 20th 20th ;
+: 22th 21th 21th ; : 23th 22th 22th ; : 24th 23th 23th ;
+: 25th 24th 24th ;
+ \
+: 32million CR ." 32 million nest/unnest operations" 25th ;
+: 1million CR ." 1 million nest/unnest operations" 20th ;
+ \
+: (
+$29 WORD DROP
+; IMMEDIATE
+ \
+
+( 2017-09-15)
+( 32million, DTC=1, 8 MHz --> 208s )
+( 32million, DTC=2, 8 MHz --> 186s )
+( 32million, DTC=3, 8 MHz --> 150s )
+( 32million, DTC=1, 16 MHz --> 104s )
+( 32million, DTC=2, 16 MHz --> 94s )
+( 32million, DTC=3, 16 MHz --> 80s )
+ \
+
+32million 7 EMIT \ BEEP at end
\ No newline at end of file
--- /dev/null
+\ https://theforth.net/package/i2c/current-view/i2c-detect.frt
+
+\ I2C
+\ ===
+\
+\ Matthias Trute <mtrute@web.de>
+\ Version 1.0.3 - 2017-04-30
+\
+\ This package provides some more or less
+\ generic I2C related words. They are generic
+\ in a sense that they depend on a low level
+\ hardware driver, that provides some very
+\ basic routines to access the I2C interface.
+\ They are based on the amforth recipe
+\ http://amforth.sourceforge.net/TG/recipes/I2C-Generic.html
+\
+\ They are tested with amforth on an Atmega with
+\ it's hardware I2C module called TWI.
+\
+\ The driver uses the following hardware low level words, that
+\ the user has to provide.
+\
+\ i2c.wait ( -- )
+\ wait for the bus
+\
+\ i2c.start ( -- )
+\ send start condition
+\
+\ i2c.stop ( -- )
+\ send stop condition
+\
+\ i2c.restart ( -- )
+\ send the restart condition
+\
+\ i2c.tx ( c -- )
+\ send 1 byte
+\
+\ i2c.rx ( -- c )
+\ receive 1 byte, send ACK
+\
+\ i2c.rxn ( -- c )
+\ receive 1 byte, send NACK
+\
+\ The following two words are not essential but
+\ are useful for tools and checks.
+\
+\ i2c.status ( -- n )
+\ get i2c status in a system specific way
+\
+\ i2c.ping? ( addr -- f )
+\ detect the presence of a device on the bus, f is true if a device
+\ at addr responds
+
+
+\ detect presence of all possible devices on I2C bus
+\ only the 7 bit address schema is supported
+
+\ not all bitpatterns are valid 7bit i2c addresses
+: i2c.7bitaddr? ( a -- f) $7 $78 within ;
+
+: i2c.detect ( -- )
+ base @ hex
+ \ header line
+ 4 spaces $10 0 do i 3 .r loop
+ $80 0 do
+ i $0f and 0= if
+ cr i 2 .r [char] : emit space
+ then
+ i i2c.7bitaddr? if
+ i i2c.ping? if \ does device respond?
+ i 3 .r
+ else
+ ." --"
+ then
+ else
+ ." "
+ then
+ loop
+ cr base !
+;
+
+\ output looks like
+\ (ATmega1280)> i2c.detect
+\ 0 1 2 3 4 5 6 7 8 9 A B C D E F
+\ 0: -- -- -- -- -- -- -- -- --
+\ 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+\ 20: -- -- -- -- -- -- -- 27 -- -- -- -- -- -- -- --
+\ 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+\ 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+\ 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+\ 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+\ 70: -- -- -- -- -- -- -- --
+\ ok
+\
\ No newline at end of file
--- /dev/null
+\ fibonacci.4th
+
+
+: (
+$29 WORD DROP
+; IMMEDIATE
+ \
+
+
+CODE 1-
+SUB #1,R14
+MOV @R13+,R0
+ENDCODE
+ \
+
+CODE 2-
+SUB #2,R14
+MOV @R13+,R0
+ENDCODE
+ \
+
+
+: BENCHME ( xt n -- )
+ DUP >R
+ 0 DO DUP EXECUTE LOOP DROP
+ 7 EMIT \ BEEP
+ CR R> . ." Iterations." CR ;
+
+
+
+: fib1 ( n1 -- n2 )
+ dup 2 < if drop 1 exit then
+ dup 1- recurse
+ swap 2- recurse + ;
+ \
+
+: fib1-bench 20 0 do i fib1 drop loop ;
+ \
+
+: fib2 ( n1 -- n2 )
+ 0 1 rot 0 do
+ over + swap loop
+ drop ;
+ \
+
+: fib2-bench 1000 0 do i fib2 drop loop ;
+ \
+
+
+( 2017-09-15)
+( DTC=1, MSP430FR4133 8MHz --> 50s )
+' FIB1-BENCH 100 BENCHME
\ No newline at end of file
--- /dev/null
+\ -*- coding: utf-8 -*-
+\
+\ TARGET SELECTION ( = the name of \INC\target.pat file without extension)
+\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
+\ MSP_EXP430FR4133 (can't use LED1 because wired on UART TX)
+\ MSP_EXP430FR2433 CHIPSTICK_FR2433 MSP_EXP430FR2355
+\ LP_MSP430FR2476 MY_MSP430FR5738_1
+\
+\ from scite editor : copy your target selection in (shift+F8) parameter 1:
+\
+\ OR
+\
+\ drag and drop this file onto SendSourceFileToTarget.bat
+\ then select your TARGET when asked.
+\
+\
+\ FastForth kernel compilation minimal options:
+\ TERMINAL3WIRES, TERMINAL4WIRES
+\ MSP430ASSEMBLER, CONDCOMP
+\
+\ ================================================================================
+\ REGISTERS USAGE for embedded MSP430 ASSEMBLER
+\ ================================================================================
+\ don't use R2, R3,
+\ R4, R5, R6, R7 must be PUSHed/POPed before/after use
+\ scratch registers S to Y are free,
+\ under interrupt, IP is free,
+\ Apply FORTH rules for TOS, PSP, RSP registers use.
+\
+\ PUSHM order : PSP,TOS, IP, S , T , W , X , Y ,rDOVAR,rDOCON,rDODOES,rDOCOL, R3, SR,RSP, PC
+\ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
+\
+\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack
+\
+\ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP
+\ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
+\
+\ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack
+\
+\ ASSEMBLER conditionnal usage before IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before ?GOTO : S< S>= U< U>= 0= 0<> 0<
+\
+\ ================================================================================
+\ driver to load a binary file as core program
+\ ================================================================================
+\
+\
+\ how it works
+\ ------------
+\
+\ 1- compile this file.4TH as FORTH program,
+\ 2- copy it in RAM @ SD_BUF then executes it:
+\ 3- wait UART RX the TI formated file.txt.
+\ 4- load bytes in INFO|MAIN memory, at addresse next '@'flag
+\ 5- performs a software BOR after RX 'q' flag.
+
+\ no interruptions, no subroutines
+\ --------------------------------
+
+
+; ----------------------------------------------------------------------
+; LOADBIN.f (UART to I2C_Slave bridge)
+; ----------------------------------------------------------------------
+
+\ first, we do some tests to allow downloading application
+ CODE ABORT_LOADBIN
+ SUB #4,PSP
+ MOV TOS,2(PSP)
+ MOV &KERNEL_ADDON,TOS
+ BIT #$3C00,TOS \ BIT13|BIT12|BIT11|BIT10 test
+ 0<> IF MOV #0,TOS THEN \ if TOS <> 0 (UART TERMINAL), set TOS = 0
+ MOV TOS,0(PSP)
+ MOV &VERSION,TOS
+ SUB #309,TOS \ FastForth V3.9
+ COLON
+ $0D EMIT \ return to column 1 without CR
+ ABORT" FastForth V3.9 please!"
+ ABORT" <-- Ouch! unexpected I2C_FastForth target!"
+ PWR_RET \ remove the ABORT_UARTI2CS definition before continuing the download.
+ ;
+
+ ABORT_LOADBIN \ abort test
+
+
+\ https://forth-standard.org/standard/core/CR
+\ CR -- send CR+LF to the output device
+ [UNDEFINED] CR
+ [IF]
+ DEFER CR \ DEFERed definition, by default executes that of :NONAME
+
+ :NONAME
+ 'CR' EMIT 'LF' EMIT
+ ; IS CR
+ [THEN]
+
+
+; ******************************************
+ HDNCODE U2I_TERM_INT \ UART RX interrupt starts on first char of each line sent by TERMINAL
+; ******************************************
+ ADD #4,RSP \ 1 remove unused PC_RET and SR_RET
+\ ------------------------------------------\
+ MOV &{UARTI2CS}+16,W \ 3 W = HALF_DUPLEX = 0 if ECHO, -1 if NOECHO
+ MOV #SD_BUF,T \ 2 T = buffer pointer for UART_TERMINAL input
+ MOV #$0D,S \ 2 S = 'CR' = penultimate char of line to be RXed by UART
+ BEGIN \
+ MOV.B &TERM_RXBUF,Y \ 3 move char from TERM_RXBUF...
+ ADD #1,T \ 1
+ MOV.B Y,-1(T) \ 3 ... to input buffer
+ CMP.B Y,S \ 1 char = CR ? (if yes goto next REPEAT)
+ 0<> WHILE \ 2 if <>
+ CMP #4,W \ 1 HALF_DUPLEX ?
+ 0<> IF \ 2 no, echo is ON
+ BEGIN \ )
+ BIT #2,&TERM_IFG \ 3 > Test TX_Buf empty, mandatory for low baudrates
+ 0<> UNTIL \ 2 )
+ MOV.B Y,&TERM_TXBUF \ 3 echo char to UART_TERMINAL
+ THEN \
+ BEGIN \
+ BIT #1,&TERM_IFG \ 3 wait for next char received
+ 0<> UNTIL \ 2
+ REPEAT \ 2 31 cycles loop ==> up to UART 2.58 Mbds @ 8MHz
+ CALL #UART_RXOFF \ stops UART RX still char CR is received, the LF char is being transmitted.
+ BEGIN \
+ BIT #1,&TERM_IFG \ 3 char LF received ?
+ 0<> UNTIL \ 2
+\ ------------------------------------------\
+BW2 \ <=== Ctrl_char $01 (KEY input)
+\ ------------------------------------------\
+ MOV.B &TERM_RXBUF,S \ 3 S = last char RXed by UART (LF|KEY)
+ MOV.B S,0(T) \ 4 store it into buffer
+\ ==========================================\
+\ ==========================================\ here I2C_Slave is sleeping in its ACCEPT routine
+\ PARSE LINE \
+\ ==========================================\
+\ ==========================================\
+ MOV #SD_BUF+1,S \
+ CMP.B #'q',-1(S)
+ 0= IF \ end of file.txt
+ ELSE
+ CMP.B #'@'-1(S) \ case of address
+ 0= IF
+ MOV.B @S+,X
+ SUB #$30,X
+ MOV X,Y
+ RLAM #4,Y
+ MOV @S+,X
+ SUB #$30,X
+ BIS X,Y
+
+
+ M
+ ELSE
+ MOV
+\ vvvvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvv\
+ BIS.B #LED1,&LED1_OUT \ red led ON = I2C TX
+\ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\
+\ ------------------------------------------\
+\ I2C_Master_TX_Start \ here, SDA and SCL must be in idle state
+\ ------------------------------------------\
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l v_ force SDA low when SCL is high = START
+ MOV.B &I2CS_ADR,X \ 3 h X = Slave_Address
+ MOV #SD_BUF,Y \ 2 h Y = buffer pointer for I2C_Master TX
+ NOP3 \ 3 h _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low)
+\ ----------------------------------------\
+ BEGIN
+\ ----------------------------------------\
+\ I2C_Master_TX address/Data \
+\ ----------------------------------------\
+ MOV.B #8,W \ 1 l prepare 8 bits address
+ BEGIN \
+ ADD.B X,X \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no : SDA as output ==> SDA low
+ THEN \ l _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \ we must wait I2C_Slave software
+ BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released
+ 0<> UNTIL \ 2 h (because Slave can strech SCL low)
+\ \ vvvvvvvvMulti-Master-Modevvvvvvv\
+\ BIT.B #SM_SDA,&I2CSM_IN \ 3 h test SDA
+\ \ ^^^^^^^^Multi-Master-Mode^^^^^^^\ _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+\ \ vvvvvvvvvvvvMulti-Master-Modevvvvvvvvvvv\
+\ 0= IF \ 2 l SDA input low
+\ BIT.B #SM_SDA,&I2CSM_DIR \ 3 l + SDA command high
+\ 0= IF \ 2 l = collision detected
+\ BIS.B #SM_SCL,&I2CSM_DIR \ 4 l release SCL first
+\ CALL #DO_IDLE \ wait stable idle state
+\ GOTO BW3 \ 2 l goto START TX
+\ THEN \
+\ THEN \
+\ \ ^^^^^^^^^^^^Multi-Master-Mode^^^^^^^^^^^\
+ SUB #1,W \ 1 l bits count-1
+ 0= UNTIL \ 2 l
+\ ------------------------------------------\
+ BIC.B #SM_SDA,&I2CSM_DIR \ 3 l after TX byte we must release SDA to read Ack/Nack from Slave
+\ ------------------------------------------\
+\ I2C_Master_TX get Slave Ack/Nack \
+\ ----------------------------------------\ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+\ BEGIN \
+\ BIT.B #SM_SCL,&I2CSM_IN \ 3 h testing SCL released is useless
+\ 0<> UNTIL \ 2 h because no risk of Slave streching SCL low
+ NOP3 \ 3 h replaced by NOP3.
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA state
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low, to keep I2C_BUS until next I2C_MASTER START (RX|TX)
+\ ------------------------------------------\
+ 0= WHILE \ 1- Slave Ack received \ 2 l out of loop if Nack (goto THEN next REPEAT)
+\ ------------------------------------------\
+\ I2C_Master_TX_data_loop \
+\ ------------------------------------------\
+ CMP S,T \ 1 last char TXed = last char RXed ? (when address is sent, T = 16bits <> S = 8bits)
+\ ------------------------------------------\
+ 0<> WHILE \ 2- TXed char <> last char \ 2 out of loop if TXed char T = last char S to be TXed (goto below REPEAT)
+\ ------------------------------------------\
+ MOV.B @Y+,X \ 2 l get next RXed char
+ MOV X,T \ 1 T = last TX char for comparaison above, on next loop.
+ REPEAT \ <-- WHILE2 search "Extended control-flow patterns" in https://forth-standard.org/standard/rationale..
+ THEN \ <-- WHILE1 case of I2C_Slave Nack on Master_TX
+\ vvvvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvv\
+ BIC.B #LED1,&LED1_OUT \ red led OFF = endof I2C TX
+\ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\
+ GOTO FW1 \ X > 4 ==> reSTART RX repeated every 1/2s
+\ ==========================================\
+\ END OF I2C MASTER TX \ SCL is kept low until START RX --┐
+\ ==========================================\ |
+ ENDCODE \ |
+\ ******************************************\ v
+\
+\
+\
+
+; ******************************************
+ HDNCODE 500MS_INT \ wakes up every 1/2s to listen I2C Slave or break from TERMINAL.
+; ******************************************
+ ADD #4,RSP \ 1 remove PC_RET and SR_RET |
+\ ------------------------------------------\ |
+FW1 \ <-- the next of TERM_INT above <--┘
+BW3 \ <=== multi master RX
+\ \ <-- the next of INI_U2I below <--┐
+\ ------------------------------------------\ |
+ BIT #BIT14,&KERNEL_ADDON \ 3 KERNEL_ADDON(BIT14) = LF XTAL flag
+ 0= IF \ if no LF XTAL
+\ MOV #%0001_0101_0110,&TA0CTL \ 3 (re)starts RX_timer,ACLK=VLO=8kHz,/2=4096Hz,up mode,clear timer,enable TA0 int, clear IFG
+ MOV #%0001_0101_0110,&TB0CTL \ 3 (re)starts RX_timer,ACLK=VLO=8kHz,/2=4096Hz,up mode,clear timer,enable TB0 int, clear IFG
+ ELSE \ if LF XTAL
+\ MOV #%0001_1101_0110,&TA0CTL \ 3 (re)starts RX_timer,ACLK=LFXTAL=32768,/8=4096Hz,up mode,clear timer,enable TA0 int, clear IFG
+ MOV #%0001_1101_0110,&TB0CTL \ 3 (re)starts RX_timer,ACLK=LFXTAL=32738,/8=4096Hz,up mode,clear timer,enable TB0 int, clear IFG
+ THEN \
+\ ========================================\
+\ I2C_MASTER RX \ le driver I2C_Master envoie START RX en boucle continue (X < 4) ou discontinue (X >= 4).
+\ ========================================\ le test d'un break en provenance de l'UART est intégré dans cette boucle.
+ BEGIN \ I2C MASTER START RX \ ABORT|WARM loop back
+\ ------------------------------------\ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL to enable ReSTART RX
+ BIT #8,&TERM_STATW \ 3 break (Alt+B) sent by TERATERM ?
+ 0<> IF \ 2 goto REMOVE_U2I, exit to WARM+4.
+ MOV #REMOVE_U2I,PC
+ THEN
+ BIT.B #SW2,&SW2_IN \ 3 SW2 pressed ?
+ 0= IF \ 2 goto REMOVE_U2I then RET to BODY of WARM
+ MOV #REMOVE_U2I,PC
+ THEN
+\ ------------------------------------\
+\ I2C_Master_RX_Start_Cond \ here, SDA and SCL must be in idle state
+\ ------------------------------------\ _
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l v_ force SDA as output (low)
+ MOV.B &I2CS_ADR,Y \ 3 h X = Slave_Address
+ BIS.B #1,Y \ 1 h set Master RX
+ NOP2 \ 2 _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low)
+\ ------------------------------------\
+\ I2C_Master_RX_Send_address \ may be SCL is held low by slave
+\ ------------------------------------\
+ MOV.B #8,W \ 1 l prepare 8 bits address
+ BEGIN \
+ ADD.B Y,Y \ 1 l shift one left
+ U>= IF \ 2 l carry set ?
+ BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor
+ ELSE \ 2 l
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no : SDA as output ==> SDA low
+ THEN \ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+\ BEGIN \
+\ BIT.B #SM_SCL,&I2CSM_IN \ 3 h testing SCL released is useless
+\ 0<> UNTIL \ 2 h because no risk of Slave streching SCL low
+ NOP3 \ 3 replaced by NOP3
+\ \ vvvvvvMulti-Master-Modevvvvvvvvv\
+\ BIT.B #SM_SDA,&I2CSM_IN \ 3 h test SDA
+\ \ ^^^^^^Multi-Master-Mode^^^^^^^^^\ _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low)
+\ \ vvvvvvvvvvvvMulti-Master-Modevvvvvvvvvvv\
+\ 0= IF \ 2 l SDA input low
+\ BIT.B #SM_SDA,&I2CSM_DIR \ 3 l + SDA command high
+\ 0= IF \ 2 l = collision detected
+\ BIS.B #SM_SCL,&I2CSM_DIR \ 4 l release SCL first
+\ CALL #DO_IDLE \ wait stable idle state
+\ GOTO BW3 \ 2 l goto START RX
+\ THEN \
+\ THEN \
+\ \ ^^^^^^^^^^^^Multi-Master-Mode^^^^^^^^^^^\
+ SUB #1,W \ 1 l bits count - 1
+ 0= UNTIL \ 2 l
+\ ------------------------------------\
+\ Wait Ack/Nack on address \
+\ ------------------------------------\ _
+ BIC.B #SM_SDA,&I2CSM_DIR \ 3 l _^_ after TX address we must release SDA to read Ack/Nack from Slave
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \ we must wait I2C_Slave software
+ BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released
+ 0<> UNTIL \ 2 h (because Slave can strech SCL low)
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+\ ------------------------------------\
+ 0<> IF \ Nack_On_Address \ 2 l
+\ --------------------------------\
+\ I2C_Master Send STOP \
+\ --------------------------------\
+ CALL #I2CSTOP \
+ MOV #'.',&TERM_TXBUF \ to see when no I2C_target is linked
+ MOV #SLEEP,PC \ 4 goto dodo for 1/2 s .. wake up by 500MS_INT
+ THEN \ 2
+\ ------------------------------------\
+\ I2C_Master_RX_data \
+\ ------------------------------------\
+\ vvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvv\
+ BIS.B #LED2,&LED2_OUT \ green led ON = I2C RX
+\ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\
+ BEGIN \
+ BEGIN \
+ BIC.B #SM_SDA,&I2CSM_DIR \ 4 l after Ack and before RX next byte, we must release SDA
+ MOV.B #8,W \ 1 l prepare 8 bits transaction
+\ ----------------------------\
+ BEGIN \
+\ ----------------------------\ _
+\ do SCL pulse \ SCL _| |_
+\ ----------------------------\ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+\ BEGIN \
+\ BIT.B #SM_SCL,&I2CSM_IN \ 3 h testing SCL released is useless
+\ 0<> UNTIL \ 2 h because no risk of Slave streching SCL low
+ NOP3 \ 3 replaced by NOP3
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low 13~
+ ADDC.B X,X \ 1 l C <--- X(7) ... X(0) <--- SDA
+ SUB #1,W \ 1 l count down of bits
+ 0= UNTIL \ 2 l here, slave releases SDA
+\ ----------------------------\
+\ case of RX data $FF \
+\ ----------------------------\
+ CMP.B #-1,X \ 1
+ 0= IF \ 2 received char $FF: let's consider that the slave is lost...
+ MOV #2,X \ to do ABORT action
+ THEN \
+\ ----------------------------\
+ CMP.B #8,X \ 1 l $08 = char BS
+ U>= WHILE \ 2 l ASCII char received, from char 'BS' up to char $7F.
+\ ----------------------------\
+ BEGIN \
+ BIT #2,&TERM_IFG \ 3 l UART TX buffer empty ?
+ 0<> UNTIL \ 2 l loop if no
+\ ----------------------------\
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l prepare Ack
+\ ----------------------------\
+\ I2C_Master_RX Send Ack \ on ASCII char >= $08
+\ ----------------------------\ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \ we must wait I2C_Slave software
+ BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released
+ 0<> UNTIL \ 2 h (because Slave can strech SCL low)
+\ ----------------------------\
+ MOV.B X,&TERM_TXBUF \ 3 h send RXed ASCII char to UART TERMINAL
+\ ----------------------------\ _
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+ REPEAT \ 2 l loop back to I2C_Master_RX_data for chars >= 8
+\ --------------------------------\
+\ case of RX CTRL_Chars < $08 \ here Master holds SCL low, Slave can test it: CMP #8,&TERM_STATW
+\ --------------------------------\ see forthMSP430FR_TERM_I2C.asm
+ CMP.B #4,X \ 1
+ U>= IF \ 2
+ MOV X,&{UARTI2CS}+16 \ set NOECHO = $04, ECHO = $05
+ BIS.B #SM_SDA,&I2CSM_DIR \ 3 l prepare Ack for Ctrl_Chars $04 $05
+ THEN \
+\ --------------------------------\
+\ Master_RX send Ack/Nack on data \ Ack for $04, $05, Nack for $00, $01, $02
+\ --------------------------------\ _
+ BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high)
+ BEGIN \ we must wait I2C_Slave software
+ BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released
+ 0<> UNTIL \ 2 h (because Slave can strech SCL low)
+ BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA as TX Ack/Nack state
+ BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low
+\ --------------------------------\ l
+ 0<> UNTIL \ if Ack, loop back to Master_RX data for CTRL_Char $04,$05
+\ ------------------------------------\
+\ Nack is sent by Master \ l case of CTRL-Char {$00|$01|$02|$03}
+\ ------------------------------------\
+ CMP.B #2,X \ $02 = ctrl_char for ABORT request
+ 0= WHILE \
+\ ------------------------------------\
+\ CTRL_Char $02 \ l if ABORT request, SDA is high, SCL is low
+\ ------------------------------------\
+ MOV #0,&{UARTI2CS}+16 \ set echo ON I2C_Master side
+ CALL #UART_RXON \ resume UART downloading source file
+ BEGIN \
+ BIC #UCRXIFG,&TERM_IFG \ clear UCRXIFG
+ MOV &FREQ_KHZ,Y \ 1000, 2000, 4000, 8000, 16000, 240000
+ BEGIN MOV #32,W \ 2~ <-------+ windows 10 seems very slow...
+ BEGIN SUB #1,W \ 1~ <---+ | ==> ((32*3)+5)*1000 = 101ms delay
+ 0= UNTIL \ 2~ 3~ loop ---+ | to refill its USB buffer
+ SUB #1,Y \ 1~ |
+ 0= UNTIL \ 2~ 101~ loop -----+
+\ BEGIN MOV #65,W \ <-------+ linux with minicom seems very very slow...
+\ BEGIN SUB #1,W \ <---+ | ==> ((65*3)+5)*1000 = 200ms delay
+\ 0= UNTIL \ 3~ loop ---+ | to refill its USB buffer
+\ SUB #1,Y \ |
+\ 0= UNTIL \ 200~ loop -----+
+ BIT #UCRXIFG,&TERM_IFG \ 4 new char in TERMRXBUF during this delay ?
+ 0= UNTIL \ 2 yes, the input stream may be still active: loop back
+ REPEAT \ l loop back to reSTART RX
+\ ----------------------------------------\
+\ I2C_Master_RX Send STOP \ l remainder: CTRL_Chars $00,$01
+\ ----------------------------------------\
+ CALL #I2CSTOP \
+\ vvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvv\
+ BIC.B #LED2,&LED2_OUT \ green led OFF = endof I2C RX
+\ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\
+\ ========================================\
+\ END OF I2C MASTER RX \ here I2C_bus is freed, Nack on Ctrl_char $FF|$00|$01 remains to be processed.
+\ ========================================\
+\ I2C_Slave KEY ctl_char $01 \ I2C_Slave request for KEY input
+\ ----------------------------------------\
+ CMP.B #1,X \
+\ Quand I2C_Master reçoit ce caractère de contrôle,
+\ il attend un caractère en provenance de TERMINAL UART
+\ et une fois ce caractère reçu reSTART TX pour l'envoyer à I2C_Slave
+ 0= IF \
+ MOV #SD_BUF,T \ ready to store KEY char: MOV.B S,0(T)
+ CALL #UART_RXON \ enables TERMINAL to TX; use no registers
+ BEGIN \ wait for a char
+ BIT #UCRXIFG,&TERM_IFG \ received char ?
+ 0<> UNTIL \
+ CALL #UART_RXOFF \ stops UART RX then
+ GOTO BW2 \ goto end of UART RX line input, for receiving last char
+ THEN \
+\ ----------------------------------------\
+\ I2C_Slave ACCEPT ctrl_char $00 \ I2C_Slave requests I2C_Master to stop RX and start TX
+\ ----------------------------------------\
+\ en début de sa routine ACCEPT, I2C_Slave envoie sur le bus I2C le caractère de contrôle $00
+\ avant de s'endormir avec SLEEP
+\ I2C_Master envoie NACK + STOP pour signifier la fin de la transaction.
+\ ----------------------------------------\
+\ et si I2C_Slave est sorti de son sommeil par un START RX, idem.
+\ ----------------------------------------\
+ MOV #SLEEP,PC \ executes RXON (that enables TERMINAL to TX) before LPM0 shut down.
+\ ----------------------------------------\
+\ I2C_Master se réveillera au premier caractère saisi sur le TERMINAL ==> TERM_INT,
+\ ou en fin du temps TxIFG ==> 500MS_INT\
+ ENDCODE \
+\ ***************************************\
+
+\ ----------------------------\
+ HDNCODE INI_U2I \ define INI_HARD_APP subroutine called by PUC|WARM
+\ ----------------------------\
+\ init 500MS_INT \ used to scan I2C_Slave hard RESET and to slow (re)START RX loop
+\ ----------------------------\
+ MOV #$800,&TB0CCR0 \ time = (2047+1)/4096 = 0.5s
+\ MOV #$800,&TA0CCR0 \ time = (2047+1)/4096 = 0.5s
+\ ----------------------------\
+\ init I2C_MASTER I/O \ see \inc\your_target.pat to find I2C MASTER SDA & SCL pins (as SM_BUS)
+\ ----------------------------\
+ BIC.B #SM_BUS,&I2CSM_REN \ remove internal pull up resistors because external 3k3 pullup resistors
+ BIC.B #SM_BUS,&I2CSM_OUT \ preset SDA + SCL output LOW
+\ ----------------------------\
+\ vvvvvvvvv OPTION vvvvvvvvvvv\
+ BIS.B #LED1,&LED1_DIR \ set red led (I2C TX) pin as output
+ BIS.B #LED2,&LED2_DIR \ set green led (I2C RX) pin as output
+\ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^\
+\ ----------------------------\
+ CALL &{UARTI2CS}+10 \ previous INI_APP executing init TERM_UC, activates I/O and sets TOS = RSTIV_MEM.
+\ ----------------------------\ TOS = SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures
+ CMP #$0E,TOS \ SVSHIFG SVSH event ?
+ 0<> IF \ if not
+ CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ?
+ U>= IF \ goto REMOVE_U2I then RET to BODY of WARM
+ MOV #REMOVE_U2I,PC
+ THEN
+ THEN \ RSTIV_MEM = {$00,$02,$04,$6,$0E} as: {WARM,PWR_ON,RST,COLD,SVSH_Threshold}
+ BIT.B #SW2,&SW2_IN \ SW2 pressed (RST+SW2) ?
+ 0= IF \ goto REMOVE_U2I then RET to BODY of WARM
+ MOV #REMOVE_U2I,PC
+ THEN
+ MOV #0,&RSTIV_MEM \ clear RSTIV_MEM before next RST event!
+ MOV #500MS_INT+2,PC \ goto I2C_Master START RX loop+2, with no other return than ALT+B|SW2+RST
+\ ----------------------------\
+ ENDCODE \
+\ ----------------------------\
+\
+\ ==============================================================
+\ Driver UART to I2CM which does the bridge USB to I2C_FastForth
+\ ==============================================================
+
+\ I2C address mini = 10h, maxi = 0EEh (I2C-bus specification and user manual V6)
+\ type on TERMINAL "16 UARTI2CS" to link teraterm TERMINAL with FastForth I2C_Slave at address $10
+\ you can also link with last known I2C_Slave address : "I2CS_ADR @ UARTI2CS"
+\
+ : UARTI2CS \ I2C_Slave_Address_%0 --
+ CR I2CS_ADR ! \ --
+ HI2LO
+ CMP #RET_ADR,&{UARTI2CS}+8 \
+ 0= IF \ save parameters only if MARKER_DOES is not initialized
+ MOV #REMOVE_U2I,&{UARTI2CS}+8 \ MARKER_DOES of {UARTI2CS} will do CALL &{UARTI2CS}+8 = CALL #REMOVE_U2I
+ MOV &WARM+2,&{UARTI2CS}+10 \ save previous INI_APP from WARM PFA to {UARTI2CS}+10
+ MOV #INI_U2I,&WARM+2 \ replace INI_APP by new INI_U2I
+ MOV &TERM_VEC,&{UARTI2CS}+12 \ save previous TERM_VEC value to {UARTI2CS}+12, see target.pat
+ MOV #U2I_TERM_INT,&TERM_VEC \ set TERM_VEC with U2I_TERM_INT
+\ MOV &TA0_X_VEC,&{UARTI2CS}+14 \ save previous TA0_X_VEC value to {UARTI2CS}+14
+\ MOV #500MS_INT,&TA0_X_VEC \ set TA0_X_VEC with 500MS_INT
+ MOV &TB0_X_VEC,&{UARTI2CS}+14 \ save previous TB0_X_VEC value to {UARTI2CS}+14
+ MOV #500MS_INT,&TB0_X_VEC \ set TB0_X_VEC with 500MS_INT
+ MOV #0,&{UARTI2CS}+16 \ reset Half_Duplex variable (set ECHO ON)
+ THEN
+ MOV #WARM,PC \ execute INI_U2I then goto BW3; abort with Alt-B or SW2+RST.
+ ENDCODE \ when there is no i2C slave at the provided address, UARTI2CS sends to TERMINAL a LF char each 1/2s.
+
+ RST_SET
+ ECHO 18 UARTI2CS ; TERATERM(Alt-B) or I2C_Master(SW2) to quit
--- /dev/null
+\ PID controller written in Forth
+\ Based on the code presented here:
+\ http://brettbeauregard.com/blog/2011/04/improving-the-beginners-pid-introduction/
+
+\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
+\ MSP_EXP430FR4133 MSP_EXP430FR2433 MSP_EXP430FR2355 CHIPSTICK_FR2433
+
+MARKER {PID}
+
+[UNDEFINED] VARIABLE [IF]
+\ https://forth-standard.org/standard/core/VARIABLE
+\ VARIABLE <name> -- define a Forth VARIABLE
+: VARIABLE
+CREATE
+HI2LO
+MOV @RSP+,IP
+MOV #DOVAR,-4(W) \ CFA = DOVAR
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] CONSTANT [IF]
+\ https://forth-standard.org/standard/core/CONSTANT
+\ CONSTANT <name> n -- define a Forth CONSTANT
+: CONSTANT
+CREATE
+HI2LO
+MOV TOS,-2(W) \ PFA = n
+MOV @PSP+,TOS
+MOV @RSP+,IP
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] STATE [IF]
+\ https://forth-standard.org/standard/core/STATE
+\ STATE -- a-addr holds compiler state
+STATEADR CONSTANT STATE
+[THEN]
+
+[UNDEFINED] ROT [IF]
+\ https://forth-standard.org/standard/core/ROT
+\ ROT x1 x2 x3 -- x2 x3 x1
+CODE ROT
+MOV @PSP,W \ 2 fetch x2
+MOV TOS,0(PSP) \ 3 store x3
+MOV 2(PSP),TOS \ 3 fetch x1
+MOV W,2(PSP) \ 3 store x2
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] SWAP [IF]
+\ https://forth-standard.org/standard/core/SWAP
+\ SWAP x1 x2 -- x2 x1 swap top two items
+CODE SWAP
+MOV @PSP,W \ 2
+MOV TOS,0(PSP) \ 3
+MOV W,TOS \ 1
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+[UNDEFINED] DUP [IF]
+\ https://forth-standard.org/standard/core/DUP
+\ DUP x -- x x duplicate top of stack
+CODE DUP
+BW1 SUB #2,PSP \ 2 push old TOS..
+ MOV TOS,0(PSP) \ 3 ..onto stack
+ MOV @IP+,PC \ 4
+ENDCODE
+
+\ https://forth-standard.org/standard/core/qDUP
+\ ?DUP x -- 0 | x x DUP if nonzero
+CODE ?DUP
+CMP #0,TOS \ 2 test for TOS nonzero
+0<> ?GOTO BW1 \ 2
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+[UNDEFINED] AND [IF]
+\ https://forth-standard.org/standard/core/AND
+\ C AND x1 x2 -- x3 logical AND
+CODE AND
+AND @PSP+,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] SPACE [IF]
+\ https://forth-standard.org/standard/core/SPACE
+\ SPACE -- output a space
+: SPACE
+$20 EMIT ;
+[THEN]
+
+[UNDEFINED] R> [IF]
+\ https://forth-standard.org/standard/core/Rfrom
+\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
+CODE R>
+MOV rDOVAR,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] @ [IF]
+\ https://forth-standard.org/standard/core/Fetch
+\ @ c-addr -- char fetch char from memory
+CODE @
+MOV @TOS,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] ! [IF]
+\ https://forth-standard.org/standard/core/Store
+\ ! x a-addr -- store cell in memory
+CODE !
+MOV @PSP+,0(TOS) \ 4
+MOV @PSP+,TOS \ 2
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+[UNDEFINED] C@ [IF]
+\ https://forth-standard.org/standard/core/CFetch
+\ C@ c-addr -- char fetch char from memory
+CODE C@
+MOV.B @TOS,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] 1+ [IF]
+\ https://forth-standard.org/standard/core/OnePlus
+\ 1+ n1/u1 -- n2/u2 add 1 to TOS
+CODE 1+
+ADD #1,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] + [IF]
+\ https://forth-standard.org/standard/core/Plus
+\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
+CODE +
+ADD @PSP+,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] - [IF]
+\ https://forth-standard.org/standard/core/Minus
+\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
+CODE -
+SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3)
+XOR #-1,TOS \ 1
+ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] MAX [IF]
+\ https://forth-standard.org/standard/core/MAX
+\ MAX n1 n2 -- n3 signed maximum
+CODE MAX
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+
+\ https://forth-standard.org/standard/core/MIN
+\ MIN n1 n2 -- n3 signed minimum
+CODE MIN
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+[THEN]
+
+
+[UNDEFINED] 2NIP [IF]
+\ 2NIP d1 d2 -- d2
+CODE 2NIP
+MOV @PSP,X
+ADD #4,PSP
+MOV X,0(PSP)
+NEXT
+ENDCODE
+[THEN]
+
+[UNDEFINED] 2DUP [IF]
+\ https://forth-standard.org/standard/core/TwoDUP
+\ 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells
+CODE 2DUP
+SUB #4,PSP \ -- x1 x x x2
+MOV TOS,2(PSP) \ -- x1 x2 x x2
+MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x2
+NEXT
+ENDCODE
+[THEN]
+
+[UNDEFINED] 2SWAP [IF]
+\ https://forth-standard.org/standard/core/TwoSWAP
+\ 2SWAP x1 x2 x3 x4 -- x3 x4 x1 x2
+CODE 2SWAP
+MOV @PSP,W \ -- x1 x2 x3 x4 W=x3
+MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x4
+MOV W,4(PSP) \ -- x3 x2 x1 x4
+MOV TOS,W \ -- x3 x2 x1 x4 W=x4
+MOV 2(PSP),TOS \ -- x3 x2 x1 x2 W=x4
+MOV W,2(PSP) \ -- x3 x4 x1 x2
+NEXT
+ENDCODE
+[THEN]
+
+[UNDEFINED] 2ROT [IF]
+\ https://forth-standard.org/standard/double/TwoROT
+\ Rotate the top three cell pairs on the stack bringing cell pair x1 x2 to the top of the stack.
+CODE 2ROT
+MOV 8(PSP),X \ 3
+MOV 6(PSP),Y \ 3
+MOV 4(PSP),8(PSP) \ 5
+MOV 2(PSP),6(PSP) \ 5
+MOV @PSP,4(PSP) \ 4
+MOV TOS,2(PSP) \ 3
+MOV X,0(PSP) \ 3
+MOV Y,TOS \ 1
+NEXT
+ENDCODE
+[THEN]
+
+[UNDEFINED] 2DROP [IF]
+\ https://forth-standard.org/standard/core/TwoDROP
+\ 2DROP x1 x2 -- drop 2 cells
+CODE 2DROP
+ADD #2,PSP
+MOV @PSP+,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] 2OVER [IF]
+\ https://forth-standard.org/standard/core/TwoOVER
+\ 2OVER x1 x2 x3 x4 -- x1 x2 x3 x4 x1 x2
+CODE 2OVER
+SUB #4,PSP \ -- x1 x2 x3 x x x4
+MOV TOS,2(PSP) \ -- x1 x2 x3 x4 x x4
+MOV 8(PSP),0(PSP) \ -- x1 x2 x3 x4 x1 x4
+MOV 6(PSP),TOS \ -- x1 x2 x3 x4 x1 x2
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] DABS [IF]
+\ https://forth-standard.org/standard/double/DABS
+\ DABS d1 -- |d1| absolute value
+CODE DABS
+AND #-1,TOS \ clear V, set N
+U< IF \ if positive (N=0)
+ XOR #-1,0(PSP) \ 4
+ XOR #-1,TOS \ 1
+ ADD #1,0(PSP) \ 4
+ ADDC #0,TOS \ 1
+THEN
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] 2@ [IF]
+ \ https://forth-standard.org/standard/core/TwoFetch
+ \ 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack
+ CODE 2@
+ SUB #2,PSP
+ MOV 2(TOS),0(PSP)
+ MOV @TOS,TOS
+ NEXT
+ ENDCODE
+[THEN]
+
+[UNDEFINED] 2! [IF]
+ \ https://forth-standard.org/standard/core/TwoStore
+ \ x1 x2 addr -- Store the cell pair x1 x2 at a-addr, with x2 at a-addr and x1 at the next consecutive cell.
+ CODE 2!
+ MOV @PSP+,0(TOS)
+ MOV @PSP+,2(TOS)
+ MOV @PSP+,TOS
+ NEXT
+ ENDCODE
+[THEN]
+
+\ https://forth-standard.org/standard/core/TwotoR
+\ ( x1 x2 -- ) ( R: -- x1 x2 ) Transfer cell pair x1 x2 to the return stack.
+CODE 2>R
+PUSH @PSP+
+PUSH TOS
+MOV @PSP+,TOS
+NEXT
+ENDCODE
+
+\ https://forth-standard.org/standard/core/TwoRFetch
+\ ( -- x1 x2 ) ( R: x1 x2 -- x1 x2 ) Copy cell pair x1 x2 from the return stack.
+CODE 2R@
+SUB #4,PSP
+MOV TOS,2(PSP)
+MOV @RSP,TOS
+MOV 2(RSP),0(PSP)
+NEXT
+ENDCODE
+
+\ https://forth-standard.org/standard/core/TwoRfrom
+\ ( -- x1 x2 ) ( R: x1 x2 -- ) Transfer cell pair x1 x2 from the return stack
+CODE 2R>
+SUB #4,PSP
+MOV TOS,2(PSP)
+MOV @RSP+,TOS
+MOV @RSP+,0(PSP)
+NEXT
+ENDCODE
+
+[UNDEFINED] 2VARIABLE [IF]
+\ https://forth-standard.org/standard/double/TwoVARIABLE
+: 2VARIABLE \ --
+CREATE 4 ALLOT
+;
+[THEN]
+
+[UNDEFINED] 2CONSTANT [IF] \ defined if MEM_EXT
+ \ https://forth-standard.org/standard/double/TwoCONSTANT
+ : 2CONSTANT \ udlo/dlo/Qlo udhi/dhi/Qhi -- to create double or Q15.16 CONSTANT
+ CREATE , , \ compile Qhi then Qlo
+ DOES> 2@ \ execution part addr -- Qhi Qlo
+ ;
+[THEN]
+
+[UNDEFINED] <> [IF]
+\ https://forth-standard.org/standard/core/ne
+\ = ( x1 x2 -- flag ) flag is true if and only if x1 is not bit-for-bit the same as x2
+CODE <>
+SUB @PSP+,TOS \ 2
+0<> IF
+ MOV #-1,TOS
+THEN
+NEXT \ 4
+ENDCODE
+[THEN]
+
+[UNDEFINED] = [IF]
+\ https://forth-standard.org/standard/core/Equal
+\ = x1 x2 -- flag test x1=x2
+CODE =
+SUB @PSP+,TOS \ 2
+0<> IF \ 2
+ AND #0,TOS \ 1
+ MOV @IP+,PC \ 4
+THEN
+XOR #-1,TOS \ 1 flag Z = 1
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+\ https://forth-standard.org/standard/core/Uless
+\ U< u1 u2 -- flag test u1<u2, unsigned
+[UNDEFINED] U< [IF]
+CODE U<
+SUB @PSP+,TOS \ 2 u2-u1
+0<> IF
+ MOV #-1,TOS \ 1
+ U< IF \ 2 flag
+ AND #0,TOS \ 1 flag Z = 1
+ THEN
+THEN
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+\ ------------------------------------------------------------------------------
+\ CONTROL STRUCTURES
+\ ------------------------------------------------------------------------------
+\ THEN and BEGIN compile nothing
+\ DO compile one word
+\ IF, ELSE, AGAIN, UNTIL, WHILE, REPEAT, LOOP & +LOOP compile two words
+\ LEAVE compile three words
+\
+[UNDEFINED] IF [IF]
+\ https://forth-standard.org/standard/core/IF
+\ IF -- IFadr initialize conditional forward branch
+CODE IF \ immediate
+SUB #2,PSP \
+MOV TOS,0(PSP) \
+MOV &DP,TOS \ -- HERE
+ADD #4,&DP \ compile one word, reserve one word
+MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN
+ADD #2,TOS \ -- HERE+2=IFadr
+MOV @IP+,PC
+ENDCODE IMMEDIATE
+[THEN]
+
+[UNDEFINED] THEN [IF]
+\ https://forth-standard.org/standard/core/THEN
+\ THEN IFadr -- resolve forward branch
+CODE THEN \ immediate
+MOV &DP,0(TOS) \ -- IFadr
+MOV @PSP+,TOS \ --
+MOV @IP+,PC
+ENDCODE IMMEDIATE
+[THEN]
+
+[UNDEFINED] ELSE [IF]
+\ https://forth-standard.org/standard/core/ELSE
+\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
+CODE ELSE \ immediate
+ADD #4,&DP \ make room to compile two words
+MOV &DP,W \ W=HERE+4
+MOV #BRAN,-4(W)
+MOV W,0(TOS) \ HERE+4 ==> [IFadr]
+SUB #2,W \ HERE+2
+MOV W,TOS \ -- ELSEadr
+MOV @IP+,PC
+ENDCODE IMMEDIATE
+[THEN]
+
+[UNDEFINED] DEFER! [IF]
+\ https://forth-standard.org/standard/core/DEFERStore
+\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER.
+CODE DEFER! \ xt2 xt1 --
+MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2]
+MOV @PSP+,TOS \ --
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] IS [IF]
+\ https://forth-standard.org/standard/core/IS
+\ IS <name> xt --
+\ used as is :
+\ DEFER DISPLAY create a "do nothing" definition (2 CELLS)
+\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY
+\ or in a definition : ... ['] U. IS DISPLAY ...
+\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words
+\
+\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words...
+: IS
+STATE @
+IF POSTPONE ['] POSTPONE DEFER!
+ELSE ' DEFER!
+THEN
+; IMMEDIATE
+[THEN]
+
+[UNDEFINED] >BODY [IF]
+\ https://forth-standard.org/standard/core/toBODY
+\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word
+CODE >BODY
+ADD #4,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+\ =============================================================================
+\ fixpoint words
+CODE F+
+BW1 ADD @PSP+,2(PSP)
+ ADDC @PSP+,TOS
+ NEXT \ 4
+ENDCODE
+
+CODE F-
+BW1 SUB @PSP+,2(PSP)
+ SUBC TOS,0(PSP)
+ MOV @PSP+,TOS
+ NEXT \ 4
+ENDCODE
+
+\ https://forth-standard.org/standard/core/HOLDS
+\ Adds the string represented by addr u to the pictured numeric output string
+\ compilation use: <# S" string" HOLDS #>
+\ free chars area in the 32+2 bytes HOLD buffer = {26,23,2} chars with a 32 bits sized {hexa,decimal,binary} number.
+\ (2 supplementary bytes are room for sign - and decimal point)
+\ C HOLDS addr u --
+CODE HOLDS
+BW3 MOV @PSP+,X \ 2
+ ADD TOS,X \ 1 src
+ MOV &HP,Y \ 3 dst
+BEGIN SUB #1,X \ 1 src-1
+ SUB #1,TOS \ 1 cnt-1
+U>= WHILE SUB #1,Y \ 1 dst-1
+ MOV.B @X,0(Y) \ 4
+REPEAT MOV Y,&HP \ 3
+ MOV @PSP+,TOS \ 2
+ MOV @IP+,PC \ 4 15 words
+ENDCODE
+
+TLV_ORG 4 + @ $81F3 U<
+$81EF TLV_ORG 4 + @ U<
+= [IF] ; MSP430FR2xxx|MSP430FR4xxx subfamilies without hardware_MPY
+
+
+CODE F/ \ Q15.16 / Q15.16 --> Q15.16 result
+ PUSHM #4,R7
+ MOV @PSP+,R6 \ DVRlo
+ MOV @PSP+,X \ DVDhi --> REMlo
+ MOV #0,W \ REMhi = 0
+ MOV @PSP,Y \ DVDlo --> DVDhi
+ MOV #0,T \ DVDlo = 0
+ MOV X,S \
+ XOR TOS,S \ DVDhi XOR DVRhi --> S keep sign of result
+ AND #-1,X \ DVD < 0 ?
+S< IF XOR #-1,Y \ INV(DVDlo)
+ XOR #-1,X \ INV(DVDhi)
+ ADD #1,Y \ INV(DVDlo)+1
+ ADDC #0,X \ INV(DVDhi)+C
+THEN AND #-1,TOS \ DVR < 0 ?
+S< IF XOR #-1,R6 \ INV(DVRlo)
+ XOR #-1,TOS \ INV(DVRhi)
+ ADD #1,R6 \ INV(DVRlo)+1
+ ADDC #0,TOS \ INV(DVRhi)+C
+THEN
+\ don't uncomment lines below !
+\ ------------------------------------------------------------------------
+\ UD/MOD DVDlo DVDhi DVRlo DVRhi -- REMlo REMhi QUOTlo QUOThi
+\ ------------------------------------------------------------------------
+\ MOV 4(PSP),T \ DVDlo
+\ MOV 2(PSP),Y \ DVDhi
+\ MOV #0,X \ REMlo = 0
+\ MOV #0,W \ REMhi = 0
+ MOV #32,R5 \ init loop count
+BW1 CMP TOS,W \ 1 REMhi = DVRhi ?
+ 0= IF CMP R6,X \ 1 REMlo U< DVRlo ?
+ THEN
+ U>= IF SUB R6,X \ 1 no: REMlo - DVRlo (carry is set)
+ SUBC TOS,W \ 1 REMhi - DVRhi
+ THEN
+BW2 ADDC R7,R7 \ 1 RLC quotLO
+ ADDC R4,R4 \ 1 RLC quotHI
+ SUB #1,R5 \ 1 Decrement loop counter
+ 0< ?GOTO FW1 \ 2 out of loop if count<0
+ ADD T,T \ 1 RLA DVDlo
+ ADDC Y,Y \ 1 RLC DVDhi
+ ADDC X,X \ 1 RLC REMlo
+ ADDC W,W \ 1 RLC REMhi
+ U< ?GOTO BW1 \ 2 15~ loop
+ SUB R6,X \ 1 REMlo - DVRlo
+ SUBC TOS,W \ 1 REMhi - DVRhi
+ BIS #1,SR \ 1
+ GOTO BW2 \ 2 16~ loop
+FW1
+\ MOV X,4(PSP) \ REMlo
+\ MOV W,2(PSP) \ REMhi
+\ ADD #4,PSP \ skip REMlo REMhi
+ MOV R7,0(PSP) \ QUOTlo
+ MOV R4,TOS \ QUOThi
+ POPM #4,R7 \ restore R4 to R7
+\ MOV @IP+,PC \ end of UD/MOD
+\ ------------------------------------------------------------------------
+BW1 AND #-1,S \ clear V, set N; QUOT < 0 ?
+S< IF XOR #-1,0(PSP) \ INV(QUOTlo)
+ XOR #-1,TOS \ INV(QUOThi)
+ ADD #1,0(PSP) \ INV(QUOTlo)+1
+ ADDC #0,TOS \ INV(QUOThi)+C
+THEN MOV @IP+,PC
+ENDCODE
+
+\ F#S Qlo Qhi u -- Qhi 0 convert fractional part Qlo of Q15.16 fixed point number
+\ with u digits
+CODE F#S
+ MOV 2(PSP),X \ -- Qlo Qhi u X = Qlo
+ MOV @PSP,2(PSP) \ -- Qhi Qhi u
+ MOV X,0(PSP) \ -- Qhi Qlo u
+ PUSHM #2,TOS \ save TOS,IP
+ MOV #0,S \ -- Qhi Qlo x
+BEGIN PUSH S \ R-- limit IP count
+ MOV &BASEADR,TOS \ -- Qhi Qlo base
+ LO2HI
+ UM* \ u1 u2 -- RESlo REShi
+ HI2LO \ -- Qhi RESlo digit
+ SUB #2,IP
+ CMP #10,TOS \ digit to char
+ U>= IF ADD #7,TOS
+ THEN ADD #$30,TOS
+ MOV @RSP+,S \ R-- limit IP
+ MOV.B TOS,HOLDS_ORG(S) \ -- Qhi RESlo char char to string
+ ADD #1,S \ count+1
+ CMP 2(RSP),S \ count=limit ?
+U>= UNTIL
+ POPM #2,TOS \ restore IP,TOS
+ MOV #0,0(PSP) \ -- Qhi 0 len
+ SUB #2,PSP \ -- Qhi 0 x len
+ MOV #HOLDS_ORG,0(PSP) \ -- Qhi 0 addr len
+ GOTO BW3 \ jump HOLDS
+ENDCODE
+
+\ unsigned multiply 32*32 = 64
+\ don't use S reg (keep sign)
+CODE UDM*
+ PUSH IP \ 3
+ PUSHM #4,R7 \ 6 save R7 ~ R4 regs
+ MOV 4(PSP),IP \ 3 MDlo
+ MOV 2(PSP),T \ 3 MDhi
+ MOV @PSP,W \ 2 MRlo
+ MOV #0,R4 \ 1 MDLO=0
+ MOV #0,R5 \ 1 MDHI=0
+ MOV #0,4(PSP) \ 3 RESlo=0
+ MOV #0,2(PSP) \ 3 REShi=0
+ MOV #0,R6 \ 1 RESLO=0
+ MOV #0,R7 \ 1 RESHI=0
+ MOV #1,X \ 1 BIT TEST REGlo
+ MOV #0,Y \ 1 BIT TEST2 REGhi
+BEGIN CMP #0,X
+ 0<> IF BIT X,W \ 2+1 TEST ACTUAL BIT MRlo
+ ELSE BIT Y,TOS \ 2+1 TEST ACTUAL BIT MRhi
+ THEN
+ 0<> IF ADD IP,4(PSP) \ 2+3 IF 1: ADD MDlo TO RESlo
+ ADDC T,2(PSP) \ 3 ADDC MDhi TO REShi
+ ADDC R4,R6 \ 1 ADDC MDLO TO RESLO
+ ADDC R5,R7 \ 1 ADDC MDHI TO RESHI
+ THEN ADD IP,IP \ 1 (RLA LSBs) MDlo *2
+ ADDC T,T \ 1 (RLC MSBs) MDhi *2
+ ADDC R4,R4 \ 1 (RLA LSBs) MDLO *2
+ ADDC R5,R5 \ 1 (RLC MSBs) MDHI *2
+ ADD X,X \ 1 (RLA) NEXT BIT TO TEST
+ ADDC Y,Y \ 1 (RLA) NEXT BIT TO TEST
+U>= UNTIL MOV R6,0(PSP) \ 2+2 IF BIT IN CARRY: FINISHED 32 * 16~ (average loop)
+ MOV R7,TOS \ 1 high result in TOS
+ POPM #4,R7 \ 6 restore R4 to R7
+ MOV @RSP+,IP \ 2
+ MOV @IP+,PC
+ENDCODE
+
+CODE F* \ s15.16 * s15.16 --> s15.16 result
+ MOV 2(PSP),S \
+ XOR TOS,S \ 1s15 XOR 2s15 --> S keep sign of result
+ BIT #$8000,2(PSP) \ MD < 0 ?
+0<> IF XOR #-1,2(PSP)
+ XOR #-1,4(PSP)
+ ADD #1,4(PSP)
+ ADDC #0,2(PSP)
+THEN
+ COLON
+ DABS UDM* \ -- RES0 RES1 RES2 RES3
+ HI2LO
+ MOV @RSP+,IP
+ MOV @PSP+,TOS \ -- RES0 RES1 RES2
+ MOV @PSP+,0(PSP) \ -- RES1 RES2
+ GOTO BW1 \ goto end of F/ to process sign of result
+ENDCODE
+
+[ELSE] \ hardware multiplier
+
+CODE F/ \ Q15.16 / Q15.16 --> Q15.16 result
+\ TOS = DVRhi
+\ 0(PSP) = DVRlo
+\ 2(PSP) = DVDhi
+\ 4(PSP) = DVDlo
+ PUSHM #4,R7 \ 6 PUSHM R7 to R4
+ MOV @PSP+,R6 \ 2 DVRlo
+ MOV @PSP+,X \ 2 DVDhi --> REMlo
+ MOV #0,W \ 1 REMhi = 0
+ MOV @PSP,Y \ 2 DVDlo --> DVDhi
+ MOV #0,T \ 1 DVDlo = 0
+ MOV X,S \ 1
+ XOR TOS,S \ 1 DVDhi XOR DVRhi --> S keep sign of result
+ AND #-1,X \ 1 DVD < 0 ?
+S< IF XOR #-1,Y \ 1 INV(DVDlo)
+ XOR #-1,X \ 1 INV(DVDhi)
+ ADD #1,Y \ 1 INV(DVDlo)+1
+ ADDC #0,X \ 1 INV(DVDhi)+C
+THEN AND #-1,TOS \ 1 DVR < 0 ?
+S< IF XOR #-1,R6 \ 1 INV(DVRlo)
+ XOR #-1,TOS \ 1 INV(DVRhi)
+ ADD #1,R6 \ 1 INV(DVRlo)+1
+ ADDC #0,TOS \ 1 INV(DVRhi)+C
+THEN MOV #32,R5 \ 2 init loop count
+BW1 CMP TOS,W \ 1 REMhi = DVRhi ?
+ 0= IF \ 2
+ CMP R6,X \ 1 REMlo U< DVRlo ?
+ THEN
+ U>= IF \ 2
+ SUB R6,X \ 1 no: REMlo - DVRlo (carry is set)
+ SUBC TOS,W \ 1 REMhi - DVRhi
+ THEN
+BW2 ADDC R7,R7 \ 1 RLC quotLO
+ ADDC R4,R4 \ 1 RLC quotHI
+ SUB #1,R5 \ 1 Decrement loop counter
+ 0< ?GOTO FW1 \ 2 out of loop if count<0
+ ADD T,T \ 1 RLA DVDlo
+ ADDC Y,Y \ 1 RLC DVDhi
+ ADDC X,X \ 1 RLC REMlo
+ ADDC W,W \ 1 RLC REMhi
+ U< ?GOTO BW1 \ 2 19~ loop
+ SUB R6,X \ 1 REMlo - DVRlo
+ SUBC TOS,W \ 1 REMhi - DVRhi
+ BIS #1,SR \ 1
+ GOTO BW2 \ 2 16~ loop
+FW1 AND #-1,S \ 1 clear V, set N; QUOT < 0 ?
+S< IF XOR #-1,R7 \ 1 INV(QUOTlo)
+ XOR #-1,R4 \ 1 INV(QUOThi)
+ ADD #1,R7 \ 1 INV(QUOTlo)+1
+ ADDC #0,R4 \ 1 INV(QUOThi)+C
+THEN MOV R7,0(PSP) \ 3 QUOTlo
+ MOV R4,TOS \ 1 QUOThi
+ POPM #4,R7 \ 6 restore R4 to R7
+ MOV @IP+,PC \ 4
+ENDCODE
+
+\ F#S Qlo Qhi u -- Qhi 0 convert fractionnal part of Q15.16 fixed point number
+\ with u digits
+CODE F#S
+ MOV 2(PSP),X \ -- Qlo Qhi u X = Qlo
+ MOV @PSP,2(PSP) \ -- Qhi Qhi u
+ MOV X,0(PSP) \ -- Qhi Qlo u
+ MOV TOS,T \ T = limit
+ MOV #0,S \ S = count
+BEGIN MOV @PSP,&MPY \ Load 1st operand
+ MOV &BASEADR,&OP2 \ Load 2nd operand
+ MOV &RES0,0(PSP) \ -- Qhi RESlo x low result on stack
+ MOV &RES1,TOS \ -- Qhi RESlo REShi high result in TOS
+ CMP #10,TOS \ digit to char
+ U>= IF ADD #7,TOS
+ THEN ADD #$30,TOS
+ MOV.B TOS,HOLDS_ORG(S) \ -- Qhi RESlo char char to string
+ ADD #1,S \ count+1
+ CMP T,S \ count=limit ?
+0= UNTIL MOV #0,0(PSP) \ -- Qhi 0 REShi
+ MOV T,TOS \ -- Qhi 0 limit
+ SUB #2,PSP \ -- Qhi 0 x len
+ MOV #HOLDS_ORG,0(PSP) \ -- Qhi 0 addr len
+ GOTO BW3 \ jump HOLDS
+ENDCODE
+
+CODE F* \ signed s15.16 multiplication --> s15.16 result
+ MOV 4(PSP),&MPYS32L \ 5 Load 1st operand
+ MOV 2(PSP),&MPYS32H \ 5
+ MOV @PSP,&OP2L \ 4 load 2nd operand
+ MOV TOS,&OP2H \ 3
+ ADD #4,PSP \ 1 remove 2 cells
+\ NOP2 \ 2
+\ NOP2 \ 2 wait 8 cycles after write OP2L before reading RES1
+ MOV &RES1,0(PSP) \ 5
+ MOV &RES2,TOS \ 5
+ MOV @IP+,PC
+ENDCODE
+
+[THEN] \ hardware multiplier
+
+CODE F.N \ ( f n -- ) display a Q15.16 number with n digits after comma
+MOV TOS,T \ T = #digits
+MOV @PSP+,TOS
+MOV TOS,S \ S = sign
+PUSHM #3,IP \ R-- IP sign #digit
+LO2HI
+ <# DABS \ -- uQlo uQhi R-- IP sign #digit
+ R> F#S \ -- uQhi 0 R-- IP sign
+ $2C HOLD \ $2C = char ','
+ #S \ -- 0 0
+ R> SIGN #> \ -- addr len R-- IP
+ TYPE SPACE \ --
+;
+
+
+\ https://forth-standard.org/standard/double/Dless
+\ flag is true if and only if d1 is less than d2
+CODE D<
+ MOV @PSP+,S \ S=d2L
+ MOV @PSP+,T \ T=d1H
+ MOV @PSP+,W \ W=d1L
+BW1 CMP TOS,T \ 1 d1H - d2H
+ MOV #0,TOS \ 1 -- false_flag by default
+S< IF MOV #-1,TOS \ 2 -- true_flag if d1H < d2H
+THEN
+0= IF CMP S,W \ 1 -- false_flag d1L - d2L
+ S< IF MOV #-1,TOS \ 1 -- true_flag if (d1H = d2H) & (d1L < d2L)
+ THEN
+THEN
+NEXT \ 4
+ENDCODE
+
+\ : D> 2SWAP D< ;
+CODE D>
+MOV TOS,T \ T=d2H
+MOV @PSP+,W \ W=d2L
+MOV @PSP+,TOS \ TOS=d1H
+MOV @PSP+,S \ S=d1L
+GOTO BW1
+ENDCODE
+
+CODE S2F \ ( s -- f ) Signed number to fixed point
+ SUB #2,PSP
+ MOV #0,0(PSP)
+ MOV @IP+,PC
+ENDCODE
+
+: F2S \ ( f -- s ) Fixed point to signed number (rounded)
+ SWAP $8000 AND IF 1 + THEN ;
+
+: DMIN \ ( d1 d2 -- d_min ) Minimum of double number (also for fixed-point)
+ 2OVER 2OVER
+ D< IF 2DROP ELSE 2NIP THEN
+;
+
+: DMAX \ ( d1 d2 -- d_max ) Maximum of double number (also for fixed-point)
+ 2OVER 2OVER
+ D> IF 2DROP ELSE 2NIP THEN
+;
+
+: DRANGE \ ( d_val d_min d_max -- d_val ) Make sure a double number is in range
+ 2ROT DMIN DMAX
+;
+
+: RANGE \ ( s_val s_min s_max -- s_val ) Make sure a number is in range
+ ROT MIN MAX
+;
+
+: F.000 3 F.N ; \ Output fixed point value
+
+\ Setup variables for pid control
+2VARIABLE KP \ Proportionnal coeff, scaled to input range.
+2VARIABLE KI \ integral coeff, in second
+2VARIABLE KD \ derivative coeff, in second
+VARIABLE SETPOINT \ setpoint, same scale as input
+
+VARIABLE SAMPLE_TIME \ sampling interval in ms
+VARIABLE OUT_MAX \ output max limit (--> 20 mA)
+VARIABLE OUT_MIN \ output min limit (--> 4 mA)
+VARIABLE OUT-OVERRIDE \ output override (auto mode if -1)
+
+\ Working variables while pid is running
+VARIABLE SET-VAL \ current setpoint
+VARIABLE INPUT_PREV \ last seen input
+2VARIABLE I_SUM \ cummulative i error
+
+VARIABLE DEBUG \ PID compute state
+0 DEBUG !
+
+: ?DEBUG DEBUG @ ;
+
+
+\ =============================================================================
+\ Main PID - internal definitions (do not call manually)
+\ inputs and outputs are 16 bits numbers
+\ PID parameters and PID compute are Q15.16 numbers.
+
+: CALC-P \ ( f_error -- f_correction ) Calculate proportionnal output
+KP 2@ F* \ fetch k-value and scale error
+?DEBUG IF ." Pval:" 2DUP F2S .
+THEN
+;
+
+
+: CALC-I \ ( f_error -- f_correction ) Calculate integral output
+KI 2@ F* \ apply ki factor
+I_SUM 2@ F+ \ sum up with running integral error
+OUT_MIN @ S2F
+OUT_MAX @ S2F
+DRANGE \ cap inside output range
+2DUP I_SUM 2! \ update running integral error
+?DEBUG IF ." Ival:" 2DUP F2S .
+THEN
+;
+
+: CALC-D \ ( s_is -- f_correction ) Calculate differential output
+ \ actually use "derivative on input", not on error
+ INPUT_PREV @ - \ substract last input from current input
+ S2F KD 2@ F* \ make fixed point, fetch kd factor and multiply
+?DEBUG IF ." Dval:" 2DUP F2S .
+THEN
+;
+
+: PID_COMPUTE \ ( s_is -- s_corr ) Do a PID calculation, return duty-cycle
+\ CR ." SET:" SET-VAL @ . ." IS:" DUP . \ DEBUG
+\ feed error in p and i, current setpoint in d, sum up results
+DUP DUP SET-VAL @ SWAP - S2F \ ( s_is s_is f_error )
+2DUP CALC-P \ ( s_is s_is f_error f_p )
+2SWAP CALC-I F+ \ ( s_is s_is f_p+i )
+ROT CALC-D F- \ ( s_is f_p+i+d ) \ substract! derivate on input - not error
+
+F2S \ ( s_is s_corr )
+?DEBUG IF ." OUT:" DUP .
+THEN
+SWAP INPUT_PREV ! \ Update INPUT_PREV for next run
+OUT_MIN @ OUT_MAX @ RANGE \ Make sure we return something inside PWM range
+?DEBUG IF ." PWM:" DUP .
+THEN
+;
+
+\ =============================================================================
+\ Main PID - external interface
+
+: SET \ ( s -- ) Change setpoint on a running pid
+ SET-VAL ! ;
+
+: TUNING \ ( f_kp f_ki f_kd -- ) Change tuning-parameters on a running pid
+ \ depends on sampletime, so fetch it, move to fixed-point and change unit to seconds
+ \ store on return stack for now
+ SAMPLE_TIME @ S2F 1000,0 F/ 2>R \
+
+ 2R@ F/ KD 2! \ translate from 1/s to the sampletime
+ 2R> F* KI 2! \ translate from 1/s to the sampletime
+ KP 2! ;
+
+\ Init PID
+\ To use in a *reverse acting system* (bigger output value **reduced**
+\ input value make sure `kp`, `ki` and `kd` are **all** negative.
+\ Starts pid in manual mode (no setpoint set!). Set setpoint and call auto
+\ to start the control loop.
+: PID-INIT \ ( f_kp f_ki f_kd s_sampletime s_outmin s_outmax -- )
+ OUT_MAX !
+ OUT_MIN !
+ SAMPLE_TIME !
+ TUNING
+ 0 OUT-OVERRIDE ! \ Make sure we're in manual mode
+ CR ." PID initialized - kp:" KP 2@ F.000 ." ki:" KI 2@ F.000 ." kd:" KD 2@ F.000
+;
+
+\ Returns calculated PID value or override value if in manual mode
+: PID \ ( s_is -- s_corr )
+ OUT-OVERRIDE @ -1 = IF \ we're in auto-mode - do PID calculation
+ PID_COMPUTE
+ ELSE \ manual-mode! store input, return override value
+ CR ." SET:" SET-VAL @ . ." IS:" DUP .
+ INPUT_PREV !
+ OUT-OVERRIDE @
+ ." PWM:" DUP .
+ THEN ;
+
+: MANUAL \ ( s -- ) Override output - switches PID into *manual mode*
+ OUT-OVERRIDE ! ;
+
+
+: AUTO \ ( -- ) Switch back to auto-mode after manual mode
+ OUT-OVERRIDE @ -1 <> IF \ only do something if we'r in override mode
+ \ store current output value as i to let it run smoothly
+ OUT-OVERRIDE @
+ OUT_MIN @ OUT_MAX @ RANGE \ Make sure we return something inside PWM range
+ S2F I_SUM 2! \ init I_SUM
+ -1 OUT-OVERRIDE !
+ THEN ;
+
+: AUTOHOLD \ ( -- ) Bring PID back to auto-mode after a manual override
+ INPUT_PREV @ SET-VAL ! \ Use last input as setpoint (no bumps!)
+ AUTO ;
+
+
+
+\ \ ******************************\
+\ ASM BACKGROUND \
+\ \ ******************************\
+\ BEGIN
+\ \ ... \ insert here your background task
+\ \ ... \
+\ \ ... \
+\ CALL &RXON \ comment this line to disable TERMINAL_INPUT
+\ BIS &LPM_MODE,SR \
+\ \ ******************************\
+\ \ here start all interrupts \
+\ \ ******************************\
+\ \ here return all interrupts \
+\ \ ******************************\
+\ AGAIN \
+\ ENDASM \
+\ \ ******************************\
+
+\ ------------------------------\
+CODE STOP \ stops multitasking, must to be used before downloading app
+\ ------------------------------\
+ MOV @IP+,PC
+ENDCODE
+
+\ ------------------------------\
+CODE APP_INIT \ this routine completes the init of system, i.e. FORTH + this app.
+\ ------------------------------\
+ MOV @IP+,PC
+ENDCODE \
+
+\ ------------------------------\
+CODE START \ this routine replaces WARM and SLEEP default values by these of this application.
+\ ------------------------------\
+\ MOV #SLEEP,X \ replace default background process SLEEP
+\ MOV #BACKGROUND,2(X) \ by RC5toLCD BACKGROUND
+\ MOV #WARM,X \ replace default WARM
+\ MOV #APP_INIT,2(X) \ by RC5toLCD APP_INIT
+\ MOV X,PC \ then execute it
+ MOV @IP+,PC
+ENDCODE
+
+
+ECHO
--- /dev/null
+\ -*- coding: utf-8 -*-
+
+SD_LOAD.f
+\ ===========================================================
+\ ABOUT INIT SD_CARD AND HOW TO SELECT FAT16/FAT32 FORMAT
+\ ===========================================================
+\ FAT16/FAT32 selection is made via the ID of partition in EBP
+\ because SD must be always FAT16 and SDHC must be always FAT32
+\ this is automatically done when we format the SD_Card !
+
+
+\ =====================================================================
+\ goal : accept 64 MB up to 64 GB SD_CARD
+\ =====================================================================
+\ thus FAT and RootClus logical sectors are word addressable.
+
+\ FAT is a little endian structure.
+\ CMD frame is sent as big endian.
+
+\ we assume that SDSC Card (up to 2GB) is FAT16 with a byte addressing
+\ and that SDHC Card (4GB up to 64GB) is FAT32 with a sector addressing (sector = 512 bytes)
+\ for SDHC Card = 64 GB, cluster = 64 sectors ==> max clusters = 20 0000h ==> FAT size = 16384 sectors
+\ ==> FAT1 and FAT2 can be addressed with a single word.
+
+\ ref. https://en.wikipedia.org/wiki/Extended_boot_record
+\ ref. https://en.wikipedia.org/wiki/Partition_type
+
+\ Formatage FA16 d'une SDSC Card 2GB
+\ First sector of physical drive (sector 0) content :
+\ ---------------------------------------------------
+\ dec@| HEX@
+\ 446 |0x1BE : partition table first record ==> logical drive 0
+\ 462 |0x1CE : partition table 2th record ==> logical drive 1
+\ 478 |0x1DE : partition table 3th record ==> logical drive 2
+\ 494 |0x1EE : partition table 4th record ==> logical drive 3
+
+\ partition of first record content :
+\ ---------------------------------------------------
+\ 450 |0x1C2 = 0x0E : type FAT16 using LBA addressing
+\ 454 |0x1C6 = 89 00 00 00 : FirstSector (of logical drive 0) BS_FirstSector = 137
+
+
+\ Partition type Description
+\ 0 empty / unused
+\ 1 FAT12
+\ 4 FAT16 for partitions <= 32 MiB
+\ 5 extended partition
+\ 6 FAT16 for partitions > 32 MiB
+\ 11 FAT32 for partitions <= 2 GiB
+\ 12 Same as type 11 (FAT32), but using LBA addressing, which removes size constraints
+\ 14 Same as type 6 (FAT16), but using LBA addressing
+\ 15 Same as type 5, but using LBA addressing
+\ ref. https://www.compuphase.com/mbr_fat.htm#BOOTSECTOR
+
+\ FirstSector of logical drive (sector 0) content :
+\ -------------------------------------------------
+\ dec@| HEX@ = HEX decimal
+\ 11 | 0x0B = 00 02 : 512 bytes/sector BPB_BytsPerSec = 512
+\ 13 | 0x0D = 40 : 64 sectors/cluster BPB_SecPerClus = 64
+\ 14 | 0x0E = 01 00 : 2 reserved sectors BPB_RsvdSecCnt = 1
+\ 16 | 0x10 = 02 : 2 FATs BPB_NumFATs = 2 (always 2)
+\ 17 | 0x11 = 00 02 : 512 entries/directory BPB_RootEntCnt = 512
+\ 19 | 0x13 = 00 00 : BPB_TotSec16 (if < 65535) BPB_TotSec16 = 0
+\ 22 | 0x16 = EB 00 : 235 sectors/FAT (FAT16) BPB_FATSize = 235
+\ 32 | 0x20 = 77 9F 3A 00 : 3841911 total sectors BPB_TotSec32 = 3841911
+\ 54 | 0x36 = "FAT16" BS_FilSysType (not used)
+
+\ all values below are evaluated in logical sectors
+\ FAT1 = BPB_RsvdSecCnt = 1
+\ FAT2 = BPB_RsvdSecCnt + BPB_FATSz32 = 1 + 235 = 236
+\ OrgRootDirL = BPB_RsvdSecCnt + (BPB_FATSize * BPB_NumFATs) = 471
+\ RootDirSize = BPB_RootEntCnt * 32 / BPB_BytsPerSec = 32 sectors
+\ OrgDatas = OrgRootDir + RootDirSize = 503
+\ OrgCluster = OrgRootDir - 2*BPB_SecPerClus = 375 (virtual value)
+\ FirstSectorOfCluster(n) = OrgCluster + n*BPB_SecPerClus ==> cluster(3) = 705
+
+\ ====================================================================================
+
+\ Formatage FA32 d'une SDSC Card 8GB
+\ First sector of physical drive (sector 0) content :
+\ ---------------------------------------------------
+\ dec@| HEX@
+\ 446 |0x1BE : partition table first record ==> logical drive 0
+\ 462 |0x1CE : partition table 2th record ==> logical drive 1
+\ 478 |0x1DE : partition table 3th record ==> logical drive 2
+\ 494 |0x1EE : partition table 4th record ==> logical drive 3
+
+\ partition record content :
+\ ---------------------------------------------------
+\ 450 |0x1C2 = 0x0C : type FAT32 using LBA addressing
+\ 454 |0x1C6 = 00 20 00 00 : FirstSector (of logical drive 0) = BS_FirstSector = 8192
+
+\
+\ FirstSector of logical block (sector 0) content :
+\ -------------------------------------------------
+\ dec@| HEX@ = HEX decimal
+\ 11 | 0x0B = 00 02 : 512 bytes/sector BPB_BytsPerSec = 512
+\ 13 | 0x0D = 08 : 8 sectors/cluster BPB_SecPerClus = 8
+\ 14 | 0x0E = 20 00 : 32 reserved sectors BPB_RsvdSecCnt = 32
+\ 16 | 0x10 = 02 : 2 FATs BPB_NumFATs = 2 (always 2)
+\ 17 | 0x11 = 00 00 : 0 BPB_RootEntCnt = 0 (always 0 for FAT32)
+
+\ 32 | 0x20 = 00 C0 EC 00 : BPB_TotSec32 BPB_TotSec32 = 15515648
+\ 36 | 0x24 = 30 3B 00 00 : BPB_FATSz32 BPB_FATSz32 = 15152
+\ 40 | 0x28 = 00 00 : BPB_ExtFlags BPB_ExtFlags
+\ 44 | 0x2C = 02 00 00 00 : BPB_RootClus BPB_RootClus = 2
+\ 48 | 0x30 = 01 00 : BPB_FSInfo BPB_FSInfo = 1
+\ 50 | 0x33 = 06 00 : BPB_BkBootSec BPB_BkBootSec = 6
+\ 82 | 0x52 = "FAT32" : BS_FilSysType BS_FilSysType (not used)
+
+\
+\ all values below are evaluated in logical sectors
+\ FAT1 = BPB_RsvdSecCnt = 32
+\ FAT2 = BPB_RsvdSecCnt + BPB_FATSz32 = 32 + 15152 = 15184
+\ OrgRootDirL = BPB_RsvdSecCnt + BPB_FATSz32 * BPB_NumFATs = 32 + 15152*2 = 30336
+\ OrgCluster = OrgRootDir - 2*BPB_SecPerClus = 30320
+\ RootDirSize = BPB_RootEntCnt * 32 / BPB_BytsPerSec = 0
+\ OrgDatas = OrgRootDir + RootDirSize = 30336
+\ FirstSectorOfCluster(n) = OrgCluster + n*BPB_SecPerClus ==> cluster(6) = 30368
+
+\ SPI_GET and SPI_PUT are adjusted for SD_CLK = MCLK
+\ PUT value must be a word or byte:byte because little endian to big endian conversion
+
+
+ MARKER {SD_APP}
+\ CFA = DODOES
+\ PFA = MARKER_DOES
+\ BODY = DP value before MARKER definition
+\ BODY+2 = VOClink value before MARKER definition
+\ BODY+4 = RET_ADR: by default MARKER_DOES does a call to RET_ADR (does nothing)
+ 10 ALLOT \ make room for:
+\ {SD_APP}+10 = content of previous ....
+\ {SD_APP}+12 = content of previous ....
+\ {SD_APP}+14 = content of previous ....
+\ {SD_APP}+16 = content of previous ....
+\ {SD_APP}+18 = content of previous ....
+
+
+
+\ ====================================\
+ HDNCODE SPI_GET \ PUT(FFh) one time, output : W = received byte, X = 0
+\ ====================================\
+ MOV #1,X \
+\ ====================================\
+\ SPI_X_GET \ PUT(FFh) X times, output : W = last received byte, X = 0
+\ ====================================\
+ MOV #-1,W \
+\ ====================================\
+\ SPI_PUT \ PUT(W) X times, output : W = last received byte, X = 0
+\ ====================================\
+ BEGIN
+ SWPB W \ 1
+ MOV.B W,&SD_TXBUF \ 3 put W high byte then W low byte and so forth, that performs little to big endian conversion
+ CMP #0,&SD_BRW \ 3 full speed ?
+ 0<> IF \ no
+ BEGIN
+ BIT #RX_SD,&SD_IFG \ 3
+ 0<> UNTIL
+ CMP.B #0,&SD_RXBUF \ 3 clear RX_BUF flag
+ THEN
+\ NOP \ NOPx adjusted to avoid SD error
+ SUB #1,X \ 1
+ 0= UNTIL \ 2 12~ loop
+ MOV.B &SD_RXBUF,W \ 3
+ MOV @RSP+,PC \ 4 X=0
+ ENDCODE
+\ ------------------------------------\
+
+\ in SPI mode CRC is not required, but CMD frame must be ended with a stop bit
+\ ====================================\
+ HDNCODE REWR_CMD \ WX <=== CMD17 or CMD24 (read or write Sector CMD)
+\ ====================================\
+ BIC.B #CS_SD,&SD_CSOUT \ set Chip Select low
+ BIT.B #CD_SD,&SD_CDIN \ test Card Detect: memory card present ?
+ 0<> IF \
+ MOV #COLD,PC \ no: force COLD
+ THEN \ yes
+\ ------------------------------------\ input = logical sector...
+ ADD &BS_FirstSectorL,W \ 3
+ ADDC &BS_FirstSectorH,X \ 3
+\ ------------------------------------\ ...output = physical sector
+\ Compute CMD \
+\ ------------------------------------\
+ MOV #1,&SD_CMD_FRM \ 3 $(01 00 xx xx xx CMD) set stop bit in CMD frame
+ CMP #1,&FATtype \ 3 FAT16 ?
+ 0= IF \ 2 yes : CMD17/24 byte address = Sector * BPB_BytsPerSec
+ ADD W,W \ 1 shift left one Sector
+ ADDC.B X,X \ 1
+ MOV W,&SD_CMD_FRM+2 \ 3 $(01 00 ll LL xx CMD)
+ MOV.B X,&SD_CMD_FRM+4 \ 3 $(01 00 ll LL hh CMD)
+ ELSE \ FAT32 : CMD17/24 sector address
+ MOV.B W,&SD_CMD_FRM+1 \ 3 $(01 ll xx xx xx CMD)
+ SWPB W \ 1
+ MOV.B W,&SD_CMD_FRM+2 \ 3 $(01 ll LL xx xx CMD)
+ MOV.B X,&SD_CMD_FRM+3 \ 3 $(01 ll LL hh xx CMD)
+ SWPB X \ 1
+ MOV.B X,&SD_CMD_FRM+4 \ 3 $(01 ll LL hh HH CMD)
+ THEN
+\ ====================================\
+BW1 \ WaitIdleBeforeSendCMD \ <=== CMD41, CMD1, CMD16 (forthMSP430FR_SD_INIT.asm)
+\ ====================================\
+ BEGIN \
+ CALL #SPI_GET \
+ ADD.B #1,W \ expected value = FFh <==> MISO = 1 = SPI idle state
+ 0= UNTIL \ loop back if <> FFh
+\ ====================================\ W = 0 = expected R1 response = ready, for CMD41,CMD16, CMD17, CMD24
+BW2 \ sendCommand \ sendCommand = WaitIdleBeforeSendCMD+8
+\ ====================================\
+ \ input : SD_CMD_FRM : {CRC,byte_l,byte_L,byte_h,byte_H,CMD}
+ \ W = expected return value
+ \ output W is unchanged, flag Z is positionned
+ \ reverts CMD bytes before send : $(CMD hh LL ll 00 CRC)
+ MOV #5,X \ X = SD_CMD_FRM ptr AND countdown
+\ ------------------------------------\
+\ Send_CMD_PUT \ performs little endian --> big endian conversion
+\ ------------------------------------\
+ BEGIN
+ MOV.B SD_CMD_FRM(X),&SD_TXBUF \ 5
+ CMP #0,&SD_BRW \ 3 full speed ?
+ 0<> IF \ no
+ BEGIN \ case of low speed during memCardInit
+ BIT #RX_SD,&SD_IFG \ 3
+ JZ Send_CMD_Loop \ 2
+ 0<> UNTIL
+ CMP.B #0,&SD_RXBUF \ 3 to clear UCRXIFG
+ THEN
+\ NOP \ 0 NOPx adjusted to avoid SD error
+ SUB.B #1,X \ 1
+ U< UNTIL \ 2 don't skip SD_CMD_FRM(0) !
+ \ host must provide height clock cycles to complete operation
+ \ here X=255, so wait for CMD return expected value with PUT FFh 256 times
+\ MOV #4,X \ to pass made in PRC SD_Card init
+\ MOV #16,X \ to pass Transcend SD_Card init
+\ MOV #32,X \ to pass Panasonic SD_Card init
+\ MOV #64,X \ to pass SanDisk SD_Card init
+\ ------------------------------------\ expect W = return value during X = 255 times
+ BEGIN
+ SUB #1,X \ 1
+ 0>= WHILE \ 2 if out of loop, error on time out with flag Z = 0
+ MOV.B #-1,&SD_TXBUF \ 3 PUT FFh
+ CMP #0,&SD_BRW \ 3 full speed ?
+ 0<> IF \
+ BEGIN \ case of low speed during memCardInit (CMD0,CMD8,ACMD41,CMD16)
+ BIT #RX_SD,&SD_IFG \ 3
+ 0<> UNTIL \ 2
+ THEN
+\ NOP \ NOPx adjusted to avoid SD_error
+ CMP.B &SD_RXBUF,W \ 3 return value = ExpectedValue ?
+ 0= UNTIL \ 2 16~ full speed loop
+ THEN \ WHILE resolution
+ MOV @RSP+,PC \ W = expected value, unchanged
+\ ------------------------------------\ flag Z = 1 <==> Returned value = expected value
+
+\ ------------------------------------\
+ HDNCODE CMD_IDLE \ <=== CMD0, CMD8, CMD55: W = 1 = R1 expected response = idle (forthMSP430FR_SD_INIT.asm)
+\ ------------------------------------\
+ MOV #1,W \ expected R1 response (first byte of SPI R7) = 01h : idle state
+ GOTO BW2 \
+\ ------------------------------------\
+
+
+\ SD Error n°
+\ High byte
+\ 1 = CMD17 read error
+\ 2 = CMD24 write error
+\ 4 = CMD0 time out (GO_IDLE_STATE)
+\ 8 = ACMD41 time out (APP_SEND_OP_COND)
+\ $10 = CMD16 time out (SET_BLOCKLEN)
+\ $20 = not FAT16/FAT32 media, low byte = partition ID
+
+\ low byte, if CMD R1 response : %0xxx_xxxx
+\ 1th bit = In Idle state
+\ 2th bit = Erase reset
+\ 3th bit = Illegal command
+\ 4th bit = Command CRC error
+\ 5th bit = erase sequence error
+\ 6th bit = address error
+\ 7th bit = parameter error
+
+\ Data Response Token
+\ Every data block written to the card will be acknowledged by a data response token.
+\ It is one byte long and has the following format:
+\ %xxxx_sss0 with bits(3-1) = Status
+\The meaning of the status bits is defined as follows:
+\'010' - Data accepted.
+\'101' - Data rejected due to a CRC error.
+\'110' - Data Rejected due to a Write Error
+
+\ ----------------------------------\
+CODE ABORT_SD \ <=== OPEN file errors from forthMSP430FR_SD_LOAD.asm
+\ ----------------------------------\
+ SUB #2,PSP \
+ MOV TOS,0(PSP) \
+ MOV #10h,&BASE \ select hex
+ MOV S,TOS \
+\ MOV #TIB_ORG,&CIB_ADR \ restore TIB as Current Input Buffer
+\ MOV #BODYACCEPT,&PFAACCEPT \ restore default ACCEPT
+ LO2HI \
+ U.
+ HI2LO
+ MOV #ABORT_TERM,PC \ no return...
+ENDCODE
+\ ----------------------------------\
+
+\ ----------------------------------\
+CODE SD_ERROR \ <=== SD_INIT errors 4,8,$10
+\ ----------------------------------\
+ SWPB S \ High Level error in High byte
+ ADD &SD_RXBUF,S \ add SPI(GET) return value as low byte error
+BW3 \ SD_CARD_ID_ERROR \ <=== SD_INIT error $20 from forthMSP430FR_SD_LowLvl.asm
+ BIS.B #CS_SD,&SD_CSOUT \ Chip Select high
+ COLON \
+ S" < SD Error!" \ don't use S register
+ ABORT_SD
+ ;
+
+\ ==================================\
+ CODE READ_SWX \ Read Sector
+\ ==================================\
+ BIS #1,S \ preset sd_read error
+ MOV.B #51h,&SD_CMD_FRM+5 \ CMD17 = READ_SINGLE_BLOCK
+ CALL #REWR_CMD \ which performs logical sector to physical sector then little endian to big endian conversion
+ 0<> ?GOTO BW3 \ SD_ERROR \ time out error if R1 <> 0
+\ ------------------------------------\
+ BEGIN \ wait SD_Card response FEh
+\ ------------------------------------\
+ CALL #SPI_GET \
+ ADD.B #2,W \ 1 FEh expected value
+ 0= UNTIL
+\ ------------------------------------\
+ BEGIN \ get 512+1 bytes, write 512 bytes in SD_BUF
+\ ------------------------------------\
+ MOV.B #-1,&SD_TXBUF \ 3 put FF
+ NOP \ 1 NOPx adjusted to avoid read SD_error
+ ADD #1,X \ 1
+ CMP #BytsPerSec+1,X \ 2
+ 0<> WHILE
+ MOV.B &SD_RXBUF,SD_BUF-1(X) \ 5
+ REPEAT
+\ ------------------------------------\
+ MOV.B #-1,&SD_TXBUF \ 3 put only one FF because first CRC byte is already received...
+\ ------------------------------------\
+\ ReadWriteHappyEnd \ <==== WriteSector
+\ ------------------------------------\
+BW2 BIC #3,S \ reset read and write errors
+ BIS.B #CS_SD,&SD_CSOUT \ Chip Select high
+ MOV @RSP+,PC \
+ ENDCODE
+\ ------------------------------------\
+
+\ .IFDEF SD_CARD_READ_WRITE
+
+\ ====================================\
+ CODE WRITE_SWX \ Write Sector
+\ ====================================\
+ BIS #2,S \ preset sd_write error
+ MOV.B #058h,SD_CMD_FRM+5 \ CMD24 = WRITE_SINGLE_BLOCK
+ CALL #CMD_RW \ which performs logical sector to physical sector then little endian to big endian conversions
+ 0<> ?GOTO BW3 \ ReturnError = 2
+ MOV #2,X \ to put 16 bits value
+ CALL #SPI_PUT \ which performs little endian to big endian conversion
+ BEGIN \ 11 cycles loop write, starts with X = 0
+ MOV.B SD_BUF(X),&SD_TXBUF \ 5
+ NOP \ 1 NOPx adjusted to avoid write SD_error
+ ADD #1,X \ 1
+ CMP #BytsPerSec,X \ 2
+ 0= UNTIL
+\ ------------------------------------\ CRC16 not used in SPI mode
+ MOV #3,X \ PUT 2 bytes to skip CRC16
+ CALL #SPI_X_GET \ + 1 byte to get data token in W
+\ ------------------------------------\ CheckWriteState
+ BIC.B #0E1h,W \ apply mask for Data response
+ CMP.B #4,W \ data accepted
+ 0= ?GOTO BW2 \ goto ReadWriteHappyEnd
+ GOTO BW3 \ goto SD_ERROR
+ ENDCODE
+\ ----------------------------------\
+
+\ .ENDIF \ SD_CARD_READ_WRITE
+
+\ ===========================================================
+\ Init SD_Card
+\ ===========================================================
+\ ----------------------------------\
+ CODE INIT_SD
+\ ----------------------------------\
+ CALL #INIT_TERM \ which activates all previous I/O settings and set TOS = RSTIV_MEM.
+\ ----------------------------------\
+ CMP #0,TOS \ RSTIV_MEM = WARM ?
+ 0<> IF \ init if RSTIV_MEM <> WARM
+\ ----------------------------------\
+ BIT.B #CD_SD,&SD_CDIN \ SD_memory in SD_Card module ?
+\ JNZ INI_SD_END \ no
+ 0= IF \ yes
+\ ----------------------------------\
+ MOV #$0A981,&SD_CTLW0 \ UCxxCTL1 = CKPH, MSB, MST, SPI_3, SMCLK + UCSWRST
+ MOV #FREQUENCY*3,&SD_BRW \ UCxxBRW init SPI CLK = 333 kHz ( < 400 kHz) for SD_Card initialisation
+ BIS.B #CS_SD,&SD_CSDIR \ SD Chip Select as output high
+ BIS #BUS_SD,&SD_SEL \ Configure pins as SIMO, SOMI & SCK (PxDIR.y are controlled by eUSCI module)
+ BIC #1,&SD_CTLW0 \ release eUSCI from reset
+\ ----------------------------------\
+ MOV #SD_LEN,X \
+ BEGIN \ case of MSP430FR57xx : SD datas are in FRAM not initialized by RESET.
+ SUB #2,X \ 1
+ MOV #0,SD_ORG(X) \ 3
+ 0= UNTIL \ 2
+\ ----------------------------------\
+\ SD_POWER_ON
+\ ----------------------------------\
+ MOV #8,X \ send 64 clk on SD_clk
+ CALL #SPI_X_GET \
+ BIC.B #CS_SD,&SD_CSOUT \ preset Chip Select output low to switch in SPI mode
+\ ----------------------------------\
+\ INIT_CMD0 \ all SD area is 0 filled
+\ ----------------------------------\
+ MOV #4,S \ preset error 4R1 for CMD0
+ MOV #$95,&SD_CMD_FRM \ $(95 00 00 00 00 00)
+ MOV #$4000,&SD_CMD_FRM+4 \ $(95 00 00 00 00 40)\ send CMD0
+\ ----------------------------------\
+\ SEND_CMD0 \ CMD0 : GO_IDLE_STATE expected SPI_R1 response = 1 = idle state
+\ ----------------------------------\
+ CALL #sendCommandIdleRet \ X
+ 0<> IF \ INIT_CMD8 \ if no idle state
+ MOV #SD_ERROR,PC \ ReturnError = $04R1, case of defectuous card (or insufficient SD_POWER_ON clk)
+ THEN
+\ ----------------------------------\ see forthMSP430FR_SD_lowLvl.asm
+\ INIT_CMD8 \ mandatory if SD_Card >= V2.x [11:8]supply voltage(VHS)
+\ ----------------------------------\
+ BEGIN
+ CALL #SPI_GET \ (needed to pass SanDisk ultra 8GB "HC I")
+ CMP.B #-1,W \ FFh expected value <==> MISO = high level
+\ JNE INIT_CMD8 \ loop back while yet busy
+ 0= UNTIL
+ MOV #$0AA87,&SD_CMD_FRM \ $(87 AA ...) (CRC:CHECK PATTERN)
+ MOV #1,&SD_CMD_FRM+2 \ $(87 AA 01 00 ...) (CRC:CHECK PATTERN:VHS set as 2.7to3.6V:0)
+ MOV #$4800,&SD_CMD_FRM+4 \ $(87 AA 01 00 00 48)
+\ ----------------------------------\
+\ SEND_CMD8 \ CMD8 = SEND_IF_COND\ expected R1 response (first byte of SPI R7) = 01h : idle state
+\ ----------------------------------\
+ CALL #sendCommandIdleRet \X time out occurs with SD_Card V1.x (and all MMC_card)
+\ ----------------------------------\
+ MOV #4,X \ skip end of SD_Card V2.x type R7 response (4 bytes), because useless
+ CALL #SPI_X_GET \WX
+\ ----------------------------------\
+INIT_ACMD41 \ no more CRC needed from here
+\ ----------------------------------\
+ MOV #1,&SD_CMD_FRM \ $(01 00 ... set stop bit
+ MOV #0,&SD_CMD_FRM+2 \ $(01 00 00 00 ...
+\ MOV.B #16,Y \ init 16 * ACMD41 repeats (power on fails with SanDisk ultra 8GB "HC I" and Transcend 2GB)
+\ MOV.B #32,Y \ init 32 * ACMD41 repeats ==> ~400ms time out
+ MOV.B #-1,Y \ init 255 * ACMD41 repeats ==> ~3 s time out
+ MOV #8,S \ preset error 8R1 for ACMD41
+\ ----------------------------------\
+\ SEND_ACMD41 \ send CMD55+CMD41
+\ ----------------------------------\
+ BEGIN
+\ INIT_CMD55 \
+ MOV #$7700,&SD_CMD_FRM+4 \ $(01 00 00 00 00 77)
+\ SEND_CMD55 \ CMD55 = APP_CMD\ expected SPI_R1 response = 1 : idle
+ CALL #sendCommandIdleRet \X
+\ SEND_CMD41 \ CMD41 = APP OPERATING CONDITION
+ MOV #$6940,&SD_CMD_FRM+4 \ $(01 00 00 00 40 69) (30th bit = HCS = High Capacity Support request)
+ CALL #WaitIdleBeforeSendCMD \ wait until idle (needed to pass SanDisk ultra 8GB "HC I") then send Command CMD41
+\ JZ SetBLockLength \ if SD_Card ready (R1=0)
+ 0<> WHILE \ if SD_Card not ready (R1<>0)
+ SUB.B #1,Y \ else decr time out delay
+\ JNZ INIT_CMD55 \ then loop back while count of repeat not reached
+ 0= IF
+ MOV #SD_ERROR,PC \ ReturnError on time out : unusable card (or insufficient Vdd SD)
+ THEN
+ REPEAT \
+\ ----------------------------------\
+\ setBLockLength \ set block = 512 bytes (buffer size), usefull only for FAT16 SD Cards
+\ ----------------------------------\
+ ADD S,S \ preset error $10 for CMD16
+\ SEND_CMD16 \ CMD16 = SET_BLOCKLEN
+ MOV #$02,&SD_CMD_FRM+2 \ $(01 00 02 00 ...)
+ MOV #$5000,&SD_CMD_FRM+4 \ $(01 00 02 00 00 50)
+ CALL #WaitIdleBeforeSendCMD \ wait until idle then send CMD16
+ 0<> IF
+ MOV #SD_ERROR,PC \ if W = R1 <> 0, ReturnError = $20R1 \ send command ko
+ THEN \
+\ ----------------------------------\ W = R1 = 0
+\ SwitchSPIhighSpeed \ end of SD init ==> SD_CLK = SMCLK
+\ ----------------------------------\
+ BIS #1,&SD_CTLW0 \ Software reset
+ MOV #0,&SD_BRW \ UCxxBRW = 0 ==> SPI_CLK = MCLK
+ BIC #1,&SD_CTLW0 \ release from reset
+\ ----------------------------------\
+\ Read_EBP_FirstSector \ W=0, BS_FirstSectorHL=0
+\ ----------------------------------\
+ MOV #0,X
+ CALL #readSectorWX \ read physical first sector
+ MOV #SD_BUF,Y \
+ MOV 454(Y),&BS_FirstSectorL \ so, sectors become logical
+ MOV 456(Y),&BS_FirstSectorH \
+ MOV.B 450(Y),W \ W = partition ID
+\ ----------------------------------\
+\ TestPartitionID \
+\ ----------------------------------\
+ MOV #1,&FATtype \ preset FAT16
+\ FAT16_CHS_LBA_Test \
+ SUB.B #6,W \ ID=06h Partition FAT16 > 32MB using CHS & LBA ?
+ 0<> IF \ no
+\ FAT16_LBA_Test \
+ SUB.B #8,W \ ID=0Eh Partition FAT16 using LBA ?
+ 0<> IF \ no
+\ ----------------------------------\
+ MOV #2,&FATtype \ set FAT32
+\ FAT32_LBA_Test \
+ ADD.B #2,W \ ID=0Ch Partition FAT32 using LBA ?
+ 0<> IF \ no
+\ FAT32_CHS_LBA_Test \
+ ADD.B #1,W \ ID=0Bh Partition FAT32 using CHS & LBA ?
+ 0<> IF \ no
+ ADD.B #4,W \ ID=07h assigned to FAT 32 by MiniTools Partition Wizard....
+ 0<> IF \ no
+ ADD #0$200B,W \
+ MOV W,S \
+ MOV #SD_CARD_ID_ERROR,PC \ S = ReturnError = $20xx with xx = partition ID
+ THEN
+ THEN
+ THEN
+ THEN
+ THEN
+\ ----------------------------------\ see: https://en.wikipedia.org/wiki/Partition_type
+\ Read_MBR_FirstSector \ read first logical sector
+\ ----------------------------------\ W = 0
+ MOV #0,X
+ CALL #READ_SWX \ ...with the good CMD17 bytes/sectors frame ! (good switch FAT16/FAT32)
+\ ----------------------------------\
+\ FATxx_SetFileSystem \
+\ ----------------------------------\
+ MOV.B 13(Y),&SecPerClus \
+ MOV 14(Y),X \ 3 X = BPB_RsvdSecCnt
+ MOV X,&OrgFAT1 \ 3 set OrgFAT1
+ MOV 22(Y),W \ W = BPB_FATsize
+ CMP #0,W \ BPB_FATsize = 0 ?
+ 0= IF
+ MOV 36(Y),W \ W = BPB_FATSz32
+ THEN
+\ Set_FATsize \
+ MOV W,&FATSize \ limited to 16384 sectors....
+ ADD W,X \
+ MOV X,&OrgFAT2 \ X = OrgFAT1 + FATsize = OrgFAT2
+ ADD W,X \ X = OrgFAT2 + FATsize = FAT16 OrgRootDir | FAT32 OrgDatas
+ CMP #2,&FATtype \ FAT32?
+ 0<> IF
+\ FAT16_SetRootCluster \
+ MOV X,&OrgRootDIR \ only FAT16 use, is a sector used by CLS_SCT
+ ADD #32,X \ OrgRootDir + RootDirSize = OrgDatas
+ THEN
+ SUB &SecPerClus,X \ OrgDatas - SecPerClus*2 = OrgClusters
+ SUB &SecPerClus,X \ no borrow expected
+ MOV X,&OrgClusters \ X = virtual cluster 0 address (clusters 0 and 1 don't exist)
+ MOV &FATtype,&DIRClusterL \ init DIRcluster as RootDIR
+ THEN \
+ THEN \
+ MOV @RSP+,PC \ RET
+ ENDCODE
+\ ----------------------------------\
+
+\ ----------------------------------\
+ HDNCODE RST_ABORT_SD \ common part of ?ABORT|RST
+\ ----------------------------------\
+ CALL #RET_ADR \ which does nothing
+\ ----------------------------------\
+ MOV &CurrentHdl,T \
+ GOTO FW1
+ BEGIN
+ MOV.B #0,HDLB_Token(T) \
+ MOV @T,T \
+FW1 CMP #0,T \
+ 0= UNTIL
+ MOV #TIB_ORG,&CIB_ADR \ restore TIB as Current Input Buffer for next line (next QUIT)
+ MOV #ACCEPT+4,&ACCEPT+2 \ restore default ACCEPT for next line (next QUIT)
+ MOV @RSP+,PC \ RET
+ ENDCODE
+\ ----------------------------------\
+
+\-----------------------------------------------------------------------
+\ SD card OPEN, LOAD subroutines
+\-----------------------------------------------------------------------
+
+\ used variables : BufferPtr, BufferLen
+
+\ rules for registers use
+\ S = error
+\ T = CurrentHdl, pathname
+\ W = SectorL, (RTC) TIME
+\ X = SectorH, (RTC) DATE
+\ Y = BufferPtr, (DIR) EntryOfst, FAToffset
+
+
+ HDNCODE CLS_FAT
+\ ----------------------------------\
+\ HDLCurClusToFAT1sectWofstY \WXY Input: T=currentHandle, Output: W=FATsector, Y=FAToffset, Cluster=HDL_CurCluster
+\ ----------------------------------\
+ MOV HDLL_CurClust(T),&ClusterL \
+ MOV HDLH_CurClust(T),&ClusterH \
+\ ----------------------------------\
+\ ClusterToFAT1sectWofstY \WXY Input : Cluster \ Output: W = FATsector, Y = FAToffset
+\ ----------------------------------\
+ MOV.B &ClusterL+1,W \ 3 W = ClusterLoHI
+ MOV.B &ClusterL,Y \ 3 Y = ClusterLoLo
+ CMP #2,&FATtype \ 3 FAT32?
+ 0= IF \ yes
+\ JZ CTF1S_end \ 2 yes
+
+\ input : Cluster n, max = 7FFFFF (SDcard up to 256 GB)
+\ ClusterLoLo*4 = displacement in 512 bytes sector ==> FAToffset
+\ ClusterHiLo&ClusterLoHi +C << 1 = relative FATsector + orgFAT1 ==> FATsector
+\ ----------------------------------\
+ MOV.B &ClusterH,X \ X = 0:ClusterHiLo
+ SWPB X \ X = ClusterHiLo:0
+ ADD X,W \ W = ClusterHiLo:ClusterLoHi
+\ ----------------------------------\
+ SWPB Y \ Y = ClusterLoLo:0
+ ADD Y,Y \ 1 Y = ClusterLoLo:0 << 1 + carry for FATsector
+ ADDC W,W \ W = ClusterHiLo:ClusterLoHi << 1 = ClusterHiLo:ClusterL / 128
+ SWPB Y
+\ CTF1S_end
+ THEN
+ ADD Y,Y \ Y = 0:ClusterLoLo << 1
+ MOV @RSP+,PC \ 4
+ ENDCODE
+\ ----------------------------------\
+
+
+\ use no registers
+ HDNCODE CLS_SCT
+\ ----------------------------------\ Input : Cluster, output: Sector = Cluster_first_sector
+\ ComputeClusFrstSect \ If Cluster = 1 ==> RootDirectory ==> SectorL = OrgRootDir
+\ ----------------------------------\ Output: SectorL of Cluster
+ MOV #0,&SectorH \
+ MOV &OrgRootDir,&SectorL \
+ CMP.B #0,&ClusterH \ clusterH <> 0 ?
+ 0= IF
+ CMP #1,&ClusterL \ clusterHL = 1 ? (FAT16 specificity)
+ 0= IF \ yes, sectorL for FAT16 OrgRootDIR is done
+ MOV @RSP+,PC
+ THEN
+ THEN
+
+ TLV_ORG 4 + @ $81F3 U<
+ $81EF TLV_ORG 4 + @ U< = \ MSP430FR413x subfamily without hardware_MPY
+ [IF] \ Cluster24<<SecPerClus --> ClusFrstSect\ SecPerClus = {1,2,4,8,16,32,64}
+ PUSHM #3,W \ 5 PUSHM W,X,Y
+ MOV.B &SecPerClus,W \ 3 SecPerClus(5-1) = multiplicator
+ MOV &ClusterL,X \ 3 Cluster(16-1) --> MULTIPLICANDlo
+ MOV.B &ClusterH,Y \ 3 Cluster(24-17) --> MULTIPLICANDhi
+ GOTO FW1 \
+ BEGIN \
+ ADD X,X \ 1 (RLA) shift one left MULTIPLICANDlo16
+ ADDC Y,Y \ 1 (RLC) shift one left MULTIPLICANDhi8
+FW1 RRA W \ 1 shift one right multiplicator
+ U>= UNTIL \ 2 C = 0 loop back
+ ADD &OrgClusters,X \ 3 OrgClusters = sector of virtual_cluster_0, word size
+ ADDC #0,Y \ 1
+ MOV X,&SectorL \ 3 low result
+ MOV Y,&SectorH \ 3 high result
+ POPM #3,W \ 5 POPM Y,X,W
+\ ----------------------------------\
+ [ELSE] ; hardware MPY, the general case
+\ ----------------------------------\
+ MOV &ClusterL,&MPY32L \ 3
+ MOV &ClusterH,&MPY32H \ 3
+ MOV &SecPerClus,&OP2 \ 5+3
+ MOV &RES0,&SectorL \ 5
+ MOV &RES1,&SectorH \ 5
+ ADD &OrgClusters,&SectorL \ 5 OrgClusters = sector of virtual cluster 0, word size
+ ADDC #0,&SectorH \ 3 32~
+\ ----------------------------------\
+ [THEN]
+\ ----------------------------------\32~ + 5~ by 2* shift
+ MOV @RSP+,PC \
+\ ----------------------------------\
+ ENDCODE
+
+
+ HDNCODE CUR_SCT
+\ ----------------------------------\
+\ ComputeHDLcurrentSector \ input: currentHandle, output: Cluster, Sector
+\ ----------------------------------\
+ MOV HDLL_CurClust(T),&ClusterL \
+ MOV HDLH_CurClust(T),&ClusterH \
+ CALL #CLS_SCT \ Cluster --> its first sector
+ MOV.B HDLB_ClustOfst(T),W \
+ ADD W,&SectorL \
+ ADDC #0,&SectorH \
+ MOV @RSP+,PC \
+\ ----------------------------------\
+ ENDCODE
+
+ HDNCODE LOAD_SCT
+\ ==================================\
+\ SetBufLenAndLoadCurSector \WXY <== previous handle reLOAD with BufferPtr<>0
+\ ==================================\
+ MOV #bytsPerSec,&BufferLen \ preset BufferLen
+ CMP #0,HDLH_CurSize(T) \ CurSize > 65535 ?
+ JNZ LoadHDLcurrentSector \ yes
+\ CMP HDLL_CurSize(T),&BufferPtr \ BufferPtr >= CurSize ? (BufferPtr = 0 or see RestorePreviousLoadedBuffer)
+\ JC CLOSE_HDL \ yes
+ CMP #bytsPerSec,HDLL_CurSize(T) \ CurSize >= 512 ?
+ JC LoadHDLcurrentSector \ yes
+ MOV HDLL_CurSize(T),&BufferLen \ no: adjust BufferLen
+\ ==================================\
+\ LoadHDLcurrentSector \ <=== OPEN_WRITE_APPEND
+\ ==================================\
+ CALL #CUR_SCT \ use no registers
+ MOV #READ_SECT,PC \ SWX then RET
+\ ----------------------------------\
+ ENDCODE
+
+ HDNCODE CLOSE_HDL
+\ ==================================\
+\ CloseHandleT \ <== CLOSE, Read_File, TERM2SD", OPEN_DEL
+\ ==================================\
+MOV &CurrentHdl,T \
+CMP #0,T \ no handle?
+0<> IF \
+ CMP.B #2,HDLB_Token(T) \ opened as write (updated) file ?
+ 0= IF
+ CALL #WriteBuffer \SWXY
+ CALL #OPWW_UpdateDirectory \SWXY
+ ELSE
+ CMP.B #-1,HDLB_Token(T) \ token type = LOAD?
+ 0= IF
+\ ----------------------------------\
+\ RestoreSD_ACCEPTContext \
+\ ----------------------------------\
+ MOV HDLW_PrevLEN(T),TOS \
+ MOV HDLW_PrevORG(T),0(PSP) \ -- org len
+\ ----------------------------------\
+\ RestoreReturnOfSD_ACCEPT \
+\ ----------------------------------\
+ ADD #6,RSP \ R-- QUIT3 empties return stack
+ MOV @RSP+,IP \ skip return to SD_ACCEPT
+ CMP #0,HDLW_PrevHDL(T) \
+ 0= IF \ no more token
+ PUSH #ECHO
+ MOV #TIB_ORG,&CIB_ADR \ restore TIB as Current Input Buffer for next line (next QUIT)
+ MOV #ACCEPT+4,&ACCEPT+2 \ restore default ACCEPT for next line (next QUIT)
+ ELSE
+ PUSH #NOECHO
+ THEN
+ THEN
+ THEN
+ MOV.B #0,HDLB_Token(T) \ release the handle
+ MOV @T,T \ T = previous handle
+ MOV T,&CurrentHdl \ becomes current handle
+ CMP #0,T \
+ 0<> IF \ if more handles
+\ ----------------------------------\
+\ RestorePreviousLoadedBuffer \
+\ ----------------------------------\
+ MOV HDLW_BUFofst(T),&BufferPtr \ restore previous BufferPtr
+ CALL #LOAD_SCT \ then reload previous buffer
+ BIC #Z,SR \
+ THEN
+THEN
+ MOV @RSP+,PC \ Z = 1 if no more handle
+\ ----------------------------------\
+ ENDCODE
+
+\ sequentially load in SD_BUF bytsPerSec bytes of a file opened as read or as load
+\ if new bufferLen have a size <= BufferPtr, closes the file then RET.
+\ if previous bufferLen had a size < bytsPerSec, closes the file and reloads previous LOADed file if exist.
+\ HDLL_CurSize leaves the not yet read size
+\ All used registers must be initialized.
+
+ HDNCODE READ_FILE
+\ ==================================\
+\ Read_File \ <== SD_ACCEPT, READ
+\ ==================================\
+ MOV &CurrentHdl,T \
+ MOV #0,&BufferPtr \ reset BufferPtr (the buffer is already read)
+\ ----------------------------------\
+ CMP #bytsPerSec,&BufferLen \
+ JNZ CLOSE_HDL \ because this last and incomplete sector is already read
+ SUB #bytsPerSec,HDLL_CurSize(T) \ HDLL_CurSize is decremented of one sector lenght
+ SUBC #0,HDLH_CurSize(T) \
+ ADD.B #1,HDLB_ClustOfst(T) \ current cluster offset is incremented
+ CMP.B &SecPerClus,HDLB_ClustOfst(T) \ Cluster Bound reached ?
+ JNC LOAD_SCT \ no
+\ ----------------------------------\
+\SearchNextCluster \ yes
+\ ----------------------------------\
+ MOV.B #0,HDLB_ClustOfst(T) \ reset Current_Cluster sectors offset
+ CALL #CLS_FAT\WXY Output: W=FATsector, Y=FAToffset, Cluster=HDL_CurCluster
+ ADD &OrgFAT1,W \
+ MOV #0,X
+ CALL #ReadSectorWX \SWX (< 65536)
+ MOV #0,HDLH_CurClust(T) \
+ MOV SD_BUF(Y),HDLL_CurClust(T) \
+ CMP #1,&FATtype \ FAT16?
+ JZ LOAD_SCT \
+ MOV SD_BUF+2(Y),HDLH_CurClust(T) \
+ MOV LOAD_SCT,PC
+ ENDCODE
+
+
+
+\ if first open_load token, save DefaultInputStream
+\ if other open_load token, decrement token, save previous context
+
+\ OPEN subroutine
+\ Input : EntryOfst, Cluster = EntryOfst(HDLL_FirstClus())
+\ init handle(HDLL_DIRsect,HDLW_DIRofst,HDLL_FirstClus,HDLL_CurClust,HDLL_CurSize)
+\ Output: Cluster = first Cluster of file, X = CurrentHdl
+
+ HDNCODE NEW_HDL
+\ ----------------------------------\ input : Cluster, EntryOfst
+\ GetFreeHandle \STWXY init handle(HDLL_DIRsect,HDLW_DIRofst,HDLL_FirstClus = HDLL_CurClust,HDLL_CurSize)
+\ ----------------------------------\ output : T = new CurrentHdl
+MOV #8,S \ prepare file already open error
+MOV #FirstHandle,T \
+MOV #0,X \ X = init previous handle as 0
+\ ----------------------------------\
+\ SearchHandleLoop \
+\ ----------------------------------\
+BEGIN
+ CMP.B #0,HDLB_Token(T) \ free handle ?
+0<> WHILE \ no
+\ AlreadyOpenTest \
+ CMP &ClusterH,HDLH_FirstClus(T) \
+ 0= IF
+ CMP &ClusterL,HDLL_FirstClus(T) \
+ 0= IF
+ MOV @RSP+,PC \ error 8: file already Open abort ===>
+ THEN
+ THEN
+\ SearchNextHandle \
+ MOV T,X \ handle is occupied, keep it in X as previous handle
+ ADD #HandleLenght,T \
+ CMP #HandleEnd,T \
+ 0= IF
+ ADD S,S \ 16 = no more handle error
+ MOV @RSP+,PC \ abort ===>
+ THEN
+REPEAT
+\ ----------------------------------\
+\FreeHandleFound \ T = new handle, X = previous handle
+\ ----------------------------------\
+MOV #0,S \ prepare Happy End (no error)
+MOV T,&CurrentHdl \
+MOV X,HDLW_PrevHDL(T) \ link to previous handle
+\ ----------------------------------\
+\ CheckCaseOfPreviousToken \
+\ ----------------------------------\
+CMP #0,X \ existing previous handle?
+0<> IF \ yes
+ ADD &TOIN,HDLW_BUFofst(X) \ in previous handle, add interpret offset to Buffer offset
+\ ----------------------------------\
+\ CheckCaseOfLoadFileToken \
+\ ----------------------------------\
+ CMP.B #0,W \ open_type is LOAD (-1) ?
+ S< IF \ yes
+ CMP.B #0,HDLB_Token(X) \ previous token is negative? (open_load type)
+ S< IF \ yes
+ ADD.B HDLB_Token(X),W \ LOAD token = previous LOAD token -1
+ THEN
+ THEN
+THEN
+\ ----------------------------------\
+\ InitHandle \
+\ ----------------------------------\
+MOV.B W,HDLB_Token(T) \ marks handle as open type: <0=LOAD, 1=READ, 2=WRITE, 4=DEL
+MOV.B #0,HDLB_ClustOfst(T) \ clear ClustOfst
+MOV &SectorL,HDLL_DIRsect(T) \ init handle DIRsectorL
+MOV &SectorH,HDLH_DIRsect(T) \
+MOV &EntryOfst,Y \
+MOV Y,HDLW_DIRofst(T) \ init handle SD_BUF offset of DIR entry
+MOV SD_BUF+26(Y),HDLL_FirstClus(T) \ init handle firstcluster of file (to identify file)
+MOV SD_BUF+20(Y),HDLH_FirstClus(T)
+MOV SD_BUF+26(Y),HDLL_CurClust(T) \ init handle CurrentCluster
+MOV SD_BUF+20(Y),HDLH_CurClust(T)
+MOV SD_BUF+28(Y),HDLL_CurSize(T) \ init handle LOW currentSizeL
+MOV SD_BUF+30(Y),HDLH_CurSize(T) \
+MOV #0,&BufferPtr \ reset BufferPtr all type of files
+CMP.B #2,W \ is a WRITE file handle?
+0= IF
+ MOV CUR_SCT,PC \ = 2, is a WRITE file
+THEN
+S>= IF \ > 2, is a file to be deleted
+ MOV @RSP+,PC \ RET
+THEN
+MOV #0,HDLW_BUFofst(T) \ < 2, is a READ or a LOAD file
+CMP.B #-1,W \
+0= IF \ case of first loaded file: ReplaceInputBuffer
+ MOV #SDIB_ORG,&CIB_ADR \ set SD Input Buffer as Current Input Buffer before return to QUIT
+ MOV #SD_ACCEPT,&ACCEPT+2 \ redirect ACCEPT to SD_ACCEPT before return to QUIT
+THEN
+S>= IF
+MOV LOAD_SCT,PC \ case of READ file
+THEN
+\ ----------------------------------\
+\ SaveBufferContext \ (see CLOSE_HDL)
+\ ----------------------------------\
+MOV &SOURCE_LEN,HDLW_PrevLEN(T) \ = CPL
+SUB &TOIN,HDLW_PrevLEN(T) \ PREVLEN = CPL - >IN
+MOV &SOURCE_ORG,HDLW_PrevORG(T) \ = CIB
+ADD &TOIN,HDLW_PrevORG(T) \ PrevORG = CIB + >IN
+\ ----------------------------------\
+MOV LOAD_SCT,PC \ then RET
+ ENDCODE
+
+ HDNCODE NAME_BL
+\ ----------------------------------\ input : X = countdown_of_spaces, Y = name pointer in buffer
+\ ParseEntryNameSpaces \XY
+\ ----------------------------------\ output: Z flag, Y is set after the last space char
+CMP #0,X \
+0<> IF
+ BEGIN
+ CMP.B #32,SD_BUF(Y) \ SPACE ?
+ 0<> WHILE
+ ADD #1,Y \ inc pointer
+ SUB #1,X \ dec countdown_of_spaces
+ 0= UNTIL
+ THEN
+THEN
+MOV @RSP+,PC \
+\ ----------------------------------\
+ ENDCODE
+
+
+CODE OPEN_ERROR
+BW1
+\ S = Error 1 : PathNameNotFound \
+\ S = Error 2 : NoSuchFile \
+\ S = Error 4 : DIRisFull \
+\ S = Error 8 : alreadyOpen \
+\ S = Error 16 : NomoreHandle \
+\ ----------------------------------\
+COLON \ set ECHO, type Pathname, type #error, type "< OpenError"\ no return
+S" < OpenError" \
+ABORT_SD \ to insert S error as flag, no return
+;
+
+
+\ ======================================================================
+\ OPEN FILE primitive
+\ ======================================================================
+\ Open_File --
+\ primitive for LOAD" READ" CREATE" WRITE" DEL"
+\ store OpenType on TOS,
+\ compile state : compile OpenType, compile SQUOTE and the string of provided pathname
+\ exec state : open a file from SD card via its pathname
+\ convert counted string found at HERE in a String then parse it
+\ media identifiers "A:", "B:" ... are ignored (only one SD_Card),
+\ char "\" as first one initializes rootDir as SearchDir.
+\ if file found, if not already open and if free handle...
+\ ...open the file as read and return the handle in CurrentHdl.
+\ if the pathname is a directory, change current directory, no handle is set.
+\ if an error is encountered, no handle is set, an error message is displayed.
+
+ HDNCODE OPEN_FILE
+\ ----------------------------------\
+\ Open_File \ -- open_type HERE HERE as pathname ptr
+\ ----------------------------------\
+MOV @PSP+,rDOCON \ rDOCON = addr = pathname PTR
+ADD rDOCON,TOS \ TOS = EOS (End Of String) = pathname end
+MOV TOS,&EndOfPath \ for WRITE CREATE part
+\ ----------------------------------\
+\ OPN_PathName \
+\ ----------------------------------\
+MOV #1,S \ error 1
+MOV &DIRClusterL,&ClusterL \
+MOV &DIRclusterH,&ClusterH \
+CMP rDOCON,TOS \ PTR = end of pathname ?
+\ JZ OPN_NoPathName ;
+0= ?GOTO BW1 \ yes: error 1 ===>
+ CMP.B #':',1(rDOCON) \ A: B: C: ... in pathname ?
+ 0= IF
+ ADD #2,rDOCON \ yes : skip drive because not used, only one SD_card
+ THEN
+ CMP.B #'\',0(rDOCON) \ "\" as first char ?
+ 0<> ?GOTO FW1
+\ JNZ OPN_SearchDirSector \ no
+ ADD #1,rDOCON \ yes : skip '\' char
+ MOV &FATtype,&ClusterL \ FATtype = 1 as FAT16 RootDIR, FATtype = 2 = FAT32RootDIR
+ MOV #0,&ClusterH \
+\ OPN_EndOfStringTest \ <=== dir found in path
+BW2 CMP rDOCON,TOS \ PTR = EOS ? (end of pathname ?)
+ 0= ?GOTO FW3
+\ JZ OPN_SetCurrentDIR \ yes
+\ OPN_SearchDirSector \
+FW1 MOV rDOCON,&Pathname \ save Pathname ptr
+ CALL #CLS_SCT \ output: SectorHL
+ MOV #32,rDODOES \ preset countdown for FAT16 RootDIR sectors
+ CMP #2,&FATtype \ FAT32?
+ JZ OPN_SetDirSectors \ yes
+ 0<> IF
+ CMP &ClusterL,&FATtype \ FAT16 AND RootDIR ?
+\ JZ OPN_LoadDIRsector \ yes
+ 0= ?GOTO FW1
+\ OPN_SetDirSectors \
+ THEN
+ MOV &SecPerClus,rDODOES \
+\ OPN_LoadDIRsector \ <=== Dir Sector loopback
+BW2
+FW1 CALL #READ_SECT \SWX
+ MOV #2,S \ prepare no such file error
+ MOV #0,W \ init entries count
+\ OPN_SearchDIRentry \ <=== DIR Entry loopback
+BW3 MOV W,Y \ 1
+ RLAM #4,Y \ --> * 16
+ ADD Y,Y \ 1 --> * 2
+ MOV Y,&EntryOfst \ EntryOfst points to first free entry
+ CMP.B #0,SD_BUF(Y) \ free entry ? (end of entries in DIR)
+\ JZ OPN_NoSuchFile
+ 0= ?GOTO BW1 \ error 2 NoSuchFile, used by create ===>
+ MOV #8,X \ count of chars in entry name
+\ OPN_CompareName8chars
+ BEGIN \
+ CMP.B @rDOCON+,SD_BUF(Y) \ compare Pathname(char) with DirEntry(char)
+ 0= WHILE
+\ JNZ OPN_FirstCharMismatch \
+ ADD #1,Y \
+ SUB #1,X \
+\ JNZ OPN_CompareName8chars \ loopback if chars 1 to 7 of string and DirEntry are equal
+ 0= UNTIL
+ ADD #1,rDOCON \ 9th char of Pathname is always a dot
+ THEN
+\ OPN_FirstCharMismatch \
+ CMP.B #'.',-1(rDOCON) \ FirstNotEqualChar of Pathname = dot ?
+ 0<> IF \ OPN_DotNotFound
+ ADD #3,X \ for next cases not equal chars of entry until 11 must be spaces
+ CALL #NAME_BL \ for X + 3 chars
+ JNZ OPN_DIRentryMismatch \ if a char entry <> space
+ CMP.B #'\',-1(rDOCON) \ FirstNotEqualChar of Pathname = "\" ?
+\ JZ OPN_EntryFound \
+ 0= ?GOTO FW1
+ CMP rDOCON,TOS \ EOS exceeded ?
+\ JNC OPN_EntryFound \ yes
+ U< ?GOTO FW2
+\ OPN_DIRentryMismatch \
+ MOV &pathname,rDOCON \ reload Pathname
+ ADD #1,W \ inc entry
+ CMP #16,W \ 16 entry in a sector
+ JNZ OPN_SearchDIRentry \ ===> loopback for search next DIR entry
+ 0<> ?GOTO BW3
+ ADD #1,&SectorL \
+ ADDC #0,&SectorH \
+ SUB #1,rDODOES \ dec count of Dir sectors
+ JNZ OPN_LoadDIRsector \ ===> loopback for search next DIR sector
+ MOV #4,S \
+ GOTO BW1 \ error 4 ===>
+ THEN
+\ OPN_DotFound \ not equal chars of entry name until 8 must be spaces
+ CMP.B #'.',-2(rDOCON) \ LastCharEqual = dot ?
+ JZ OPN_DIRentryMismatch \ case of first DIR entry = "." and Pathname = "..\"
+ CALL #NAME_BL \ parse X spaces, X{0,...,7}
+ JNZ OPN_DIRentryMismatch \ if a char entry <> space
+ MOV #3,X \
+\ OPN_CompareExt3chars \
+ CMP.B @rDOCON+,SD_BUF(Y) \ compare string(char) with DirEntry(char)
+ JNZ OPN_ExtNotEqualChar \
+ ADD #1,Y \
+ SUB #1,X \
+ JNZ OPN_CompareExt3chars \ nothing to do if chars equal
+ JMP OPN_EntryFound \
+\ OPN_ExtNotEqualChar \
+ CMP rDOCON,TOS \ EOS exceeded ?
+ JC OPN_DIRentryMismatch \ no, loop back
+ CMP.B #'\',-1(rDOCON) \ FirstNotEqualChar = "\" ?
+ JNZ OPN_DIRentryMismatch \
+ CALL #NAME_BL \ parse X spaces, X{0,...,3}
+ JNZ OPN_DIRentryMismatch \ if a char entry <> space, loop back
+\ OPN_EntryFound \ Y points on the file attribute (11th byte of entry)
+FW1
+FW2 MOV &EntryOfst,Y \ reload DIRentry
+ MOV SD_BUF+26(Y),&ClusterL \ first clusterL of file
+ MOV SD_BUF+20(Y),&ClusterH \ first clusterT of file, always 0 if FAT16
+\ OPN_EntryFoundNext
+ BIT.B #10h,SD_BUF+11(Y) \ test if Directory or File
+ JZ OPN_FileFound \
+\ OPN_DIRfound \ entry is a DIRECTORY
+ CMP #0,&ClusterH \ case of ".." entry, when parent directory is root
+ JNZ OPN_DIRfoundNext \
+ CMP #0,&ClusterL \ case of ".." entry, when parent directory is root
+ JNZ OPN_DIRfoundNext \
+ MOV &FATtype,&ClusterL \ set cluster as RootDIR cluster
+\ OPN_DIRfoundNext \
+ CMP rDOCON,TOS \ EOS exceeded ?
+ JC OPN_EndOfStringTest \ no: (we presume that FirstNotEqualChar = "\") ==> loop back
+\ OPN_SetCurrentDIR \ -- open_type ptr
+FW3 MOV &ClusterL,&DIRClusterL \
+ MOV &ClusterH,&DIRclusterH \
+ MOV #0,0(PSP) \ -- open_type ptr open_type = 0
+ JMP OPN_Dir
+\ OPN_FileFound \ -- open_type ptr
+ MOV @PSP,W \
+ CALL #NEW_HDL \STWXY init handle(HDLL_DIRsect,HDLW_DIRofst,HDLL_FirstClus = HDLL_CurClust,HDLL_CurSize)
+\ --------------------------------\ output : T = CurrentHdl*, S = ReturnError, Y = DIRentry offset
+ \ OPN_NomoreHandle \ S = error 16
+ \ OPN_alreadyOpen \ S = error 8
+ \ OPN_EndOfDIR \ S = error 4
+ \ OPN_NoSuchFile \ S = error 2
+ \ OPN_NoPathName, S = error 1
+OPN_Dir
+ MOV #xdodoes,rDODOES \ restore rDODOES
+ MOV #xdocon,rDOCON \ restore rDODOES
+ MOV @PSP+,W \ -- ptr W = open_type
+ MOV @PSP+,TOS \ --
+\ ----------------------------------\ then go to selected OpenType subroutine (OpenType = W register)
+\OPEN_QDIR \
+\ ----------------------------------\
+ CMP #0,W \
+ JZ OPEN_LOAD_END \ nothing to do
+\ ----------------------------------\
+\OPEN_QLOAD \
+\ ----------------------------------\
+ .IFDEF SD_CARD_READ_WRITE \
+ CMP.B #-1,W \ open_type = LOAD"
+ JNZ OPEN_QREAD \ next step
+ .ENDIF \
+\ ----------------------------------\ here W is free
+\OPEN_LOAD \
+\ ----------------------------------\
+MOV @IP+,PC \
+ ENDCODE
+
+\-----------------------------------------------------------------------
+\ SD_CARD_LOADER FORTH word
+\-----------------------------------------------------------------------
+
+\Z LOAD" pathame" -- immediate
+\ compile state : compile LOAD" pathname"
+\ exec state : open a file from SD card via its pathname
+\ see Open_File primitive for pathname conventions
+\ the opened file becomes the new input stream for INTERPRET
+\ this command is recursive, limited only by the count of free handles (up to 8)
+\ LOAD" acts also as dos command "CD" :
+\ - LOAD" \misc\" set a:\misc as current directory
+\ - LOAD" \" reset current directory to root
+\ - LOAD" ..\" change to parent directory
+
+\ ======================================================================
+\ LOAD" primitive as part of Open_File
+\ input from open: S = OpenError, W = open_type, SectorHL = DIRsectorHL,
+\ Buffer = [DIRsector], ClusterHL = FirstClusterHL
+\ from open(GetFreeHandle): Y = DIRentry, T = CurrentHdl
+\ output: nothing else abort on error
+\ ======================================================================
+
+ [UNDEFINED] S_
+ [IF]
+ CODE S_ \ Squote alias with blank instead quote separator
+ MOV #0,&CAPS \ turn CAPS OFF
+ COLON
+ XSQUOTE , \ compile run-time code
+ $20 WORD \ -- c-addr (= HERE)
+ HI2LO
+ MOV.B @TOS,TOS \ -- len compile string
+ ADD #1,TOS \ -- len+1
+ BIT #1,TOS \ C = ~Z
+ ADDC TOS,&DP \ store aligned DP
+ MOV @PSP+,TOS \ --
+ MOV @RSP+,IP \ pop paired with push COLON
+ MOV #$20,&CAPS \ turn CAPS ON (default state)
+ MOV @IP+,PC \ NEXT
+ ENDCODE IMMEDIATE
+ [THEN]
+
+\ ----------------------------------\
+ CODE LOAD \ immediate
+\ ----------------------------------\
+ MOV.B #-1,W \ W = OpenType
+\ ----------------------------------\
+BW1 SUB #4,PSP \
+ MOV TOS,2(PSP) \
+ MOV W,0(PSP) \ -- Open_type (0=LOAD", 1=READ", 2=WRITE", 4=DEL")
+ MOV &STATE,TOS \
+ COLON \ if exec state
+ IF
+ 20 WORD COUNT \ -- open_type addr u
+ ELSE \ compile OPEN_FILE
+ LITERAL
+ S_ [ 20 WORD DROP ]
+ THEN
+ OPEN_FILE
+ ; IMMEDIATE
+
+\ .IFDEF SD_CARD_READ_WRITE
+
+\-----------------------------------------------------------------------
+\ SD_READ_WRITE FORTH words
+\-----------------------------------------------------------------------
+
+\Z READ --
+\ parse string until " is encountered, convert counted string in String
+\ then parse string until char '0'.
+\ media identifiers "A:", "B:" ... are ignored (only one SD_Card),
+\ char "\" as first one initializes rootDir as SearchDir.
+\ if file found, if not already open and if free handle...
+\ ...open the file as read and return the handle in CurrentHdl.
+\ then load first sector in buffer, bufferLen and bufferPtr are ready for read
+\ currentHdl keep handle that is flagged as "read".
+
+\ to read sequentially next sectors use READ word. A flag is returned : true if file is closed.
+\ the last sector so is in buffer.
+
+\ if pathname is a directory, change current directory.
+\ if an error is encountered, no handle is set, error message is displayed.
+
+\ READ" acts also as CD dos command :
+\ - READ" a:\misc\" set a:\misc as current directory
+\ - READ" a:\" reset current directory to root
+\ - READ" ..\" change to parent directory
+
+\ to close all files type : WARM (or COLD, RESET)
+
+\ ----------------------------------\
+ CODE READ \ "
+ MOV.B #1,W \ W = OpenType
+ GOTO BW1 \
+ ENDCODE IMMEDIATE
+
+\Z WRITE" pathame" -- immediate
+\ open or create the file designed by pathname.
+\ an error occurs if the file is already opened.
+\ the last sector of the file is loaded in buffer, and bufferPtr leave the address of the first free byte.
+\ compile state : compile WRITE" pathname"
+\ exec state : open or create entry selected by pathname
+\ ----------------------------------\
+ CODE WRITE \ "
+ MOV.B #2,W \ W = OpenType
+ GOTO BW1 \
+ ENDCODE IMMEDIATE
+
+
+\Z DEL" pathame" -- immediate
+\ compile state : compile DEL" pathname"
+\ exec state : DELETE entry selected by pathname
+
+\ ----------------------------------\
+ CODE DEL \ "
+\ ----------------------------------\
+ MOV.B #4,W \ W = OpenType
+ GOTO BW1 \
+ ENDCODE IMMEDIATE
+
+
+\Z CLOSE --
+\ close current handle
+\ ----------------------------------\
+ CODE CLOSE \
+\ ----------------------------------\
+ CALL #CLOSE_HDL \
+ MOV @IP+,PC \
+ ENDCODE
+
+\ .ENDIF \ SD_CARD_READ_WRITE
+
+
+
+
+\ .IFDEF BOOTLOADER
+\ https://forth-standard.org/standard/core/Equal
+\ = x1 x2 -- flag test x1=x2
+ [UNDEFINED] =
+ [IF]
+ CODE =
+ SUB @PSP+,TOS \ 2
+ 0<> IF \ 2
+ AND #0,TOS \ 1
+ MOV @IP+,PC \ 4
+ THEN
+ XOR #-1,TOS \ 1 flag Z = 1
+ MOV @IP+,PC \ 4
+ ENDCODE
+ [THEN]
+
+\ https://forth-standard.org/standard/core/DUP
+\ DUP x -- x x duplicate top of stack
+ [UNDEFINED] DUP
+ [IF]
+ CODE DUP
+ BW1 SUB #2,PSP \ 2 push old TOS..
+ MOV TOS,0(PSP) \ 3 ..onto stack
+ MOV @IP+,PC \ 4
+ ENDCODE
+
+\ https://forth-standard.org/standard/core/qDUP
+\ ?DUP x -- 0 | x x DUP if nonzero
+ CODE ?DUP
+ CMP #0,TOS \ 2 test for TOS nonzero
+ 0<> ?GOTO BW1 \ 2
+ MOV @IP+,PC \ 4
+ ENDCODE
+[THEN]
+
+\ https://forth-standard.org/standard/core/EVALUATE
+\ EVALUATE \ i*x c-addr u -- j*x interpret string
+ [UNDEFINED] EVALUATE
+ [IF]
+ CODE EVALUATE
+ MOV #SOURCE_LEN,X \ 2
+ MOV @X+,S \ 2 S = SOURCE_LEN
+ MOV @X+,T \ 2 T = SOURCE_ORG
+ MOV @X+,W \ 2 W = TOIN
+ PUSHM #4,IP \ 6 PUSHM IP,S,T,W
+ LO2HI
+ INTERPRET
+ HI2LO
+ MOV @RSP+,&TOIN \ 4
+ MOV @RSP+,&SOURCE_ORG \ 4
+ MOV @RSP+,&SOURCE_LEN \ 4
+ MOV @RSP+,IP
+ MOV @IP+,PC
+ ENDCODE
+ [THEN]
+
+\ BOOT RSTIV_MEM -- \ bootstrap on SD_CARD\BOOT.4th file
+\ \ called by WARM
+\ to enable bootstrap type: ' BOOT IS WARM
+\ to disable bootstrap type: ' BOOT [PFA] IS WARM
+ CODE BOOT
+ MOV #INIT_SD,X \ X = INIT_SD
+ BIC #LOCKLPM5,&PM5CTL0 \ activate all previous I/O settings, mandatory for QSD_MEM.
+ CMP #2,TOS \ RSTIV_MEM <> WARM ?
+ U< IF \ yes
+ MOV @RSP+,PC \ if RSTIV_MEM U< 2, return to BODYWARM
+ THEN
+ BIT.B #CD_SD,&SD_CDIN \ SD_memory in SD_Card socket ?
+ 0<> IF \
+ MOV 2(X),PC \ if no, goto previous INIT: INIT TERMINAL only then ret to PFAWARM
+ THEN
+\---------------------------------------------------------------------------------
+\ RESET 6: if RSTIV_MEM <> WARM, init TERM, init SD
+\---------------------------------------------------------------------------------
+ CALL X \ init TERM UC first then init SD card, TOS = RSTIV_MEM
+\---------------------------------------------------------------------------------
+\ END OF RESET
+\---------------------------------------------------------------------------------
+ MOV #PSTACK-2,PSP \ to avoid error "Stack empty!"
+ MOV #0,&STATE \ )
+ MOV #LSTACK,&LEAVEPTR \ > same as QUIT
+ MOV #RSTACK,RSP \ )
+ LO2HI \
+ S_ LOAD" BOOT.4TH" \ LOAD BOOT.4TH issues error 2 if no such file...
+ EVALUATE \ to interpret this string
+ ;
--- /dev/null
+\ -*- coding: utf-8 -*-
+
+; -----------------------------------------------------------------------
+; TEST_ASM.f
+; -----------------------------------------------------------------------
+\
+\ TARGET SELECTION
+\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
+\ MSP_EXP430FR4133 MSP_EXP430FR2433 MSP_EXP430FR2355 CHIPSTICK_FR2433
+\
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC
+\ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
+\
+\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack
+\
+\ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP
+\ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
+\
+\ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack
+\
+\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>=
+\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0<
+\
+\ FORTH conditionnal : 0= 0< = < > U<
+
+PWR_STATE
+
+[UNDEFINED] >R [IF]
+\ https://forth-standard.org/standard/core/toR
+\ >R x -- R: -- x push to return stack
+CODE >R
+PUSH TOS
+MOV @PSP+,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] R> [IF]
+\ https://forth-standard.org/standard/core/Rfrom
+\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR
+CODE R>
+SUB #2,PSP \ 1
+MOV TOS,0(PSP) \ 3
+MOV @RSP+,TOS \ 2
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+[UNDEFINED] + [IF]
+\ https://forth-standard.org/standard/core/Plus
+\ + n1/u1 n2/u2 -- n3/u3 add n1+n2
+CODE +
+ADD @PSP+,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] - [IF]
+\ https://forth-standard.org/standard/core/Minus
+\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2
+CODE -
+SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3)
+XOR #-1,TOS \ 1
+ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] SWAP [IF]
+\ https://forth-standard.org/standard/core/SWAP
+\ SWAP x1 x2 -- x2 x1 swap top two items
+CODE SWAP
+MOV @PSP,W \ 2
+MOV TOS,0(PSP) \ 3
+MOV W,TOS \ 1
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+[UNDEFINED] MAX [IF] \ define MAX and MIN
+
+CODE MAX \ n1 n2 -- n3 signed maximum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO FW1 \ n2<n1
+BW1 ADD #2,PSP
+ MOV @IP+,PC
+ENDCODE
+
+CODE MIN \ n1 n2 -- n3 signed minimum
+ CMP @PSP,TOS \ n2-n1
+ S< ?GOTO BW1 \ n2<n1
+FW1 MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE
+
+[THEN]
+
+[UNDEFINED] @ [IF]
+\ https://forth-standard.org/standard/core/Fetch
+\ @ c-addr -- char fetch char from memory
+CODE @
+MOV @TOS,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] ! [IF]
+\ https://forth-standard.org/standard/core/Store
+\ ! x a-addr -- store cell in memory
+CODE !
+MOV @PSP+,0(TOS) \ 4
+MOV @PSP+,TOS \ 2
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+[UNDEFINED] C@ [IF]
+\ https://forth-standard.org/standard/core/CFetch
+\ C@ c-addr -- char fetch char from memory
+CODE C@
+MOV.B @TOS,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] VARIABLE [IF]
+\ https://forth-standard.org/standard/core/VARIABLE
+\ VARIABLE <name> -- define a Forth VARIABLE
+: VARIABLE
+CREATE
+HI2LO
+MOV #DOVAR,-4(W) \ CFA = DOVAR
+MOV @RSP+,IP
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] CONSTANT [IF]
+\ https://forth-standard.org/standard/core/CONSTANT
+\ CONSTANT <name> n -- define a Forth CONSTANT
+: CONSTANT
+CREATE
+HI2LO
+MOV TOS,-2(W) \ PFA = n
+MOV @PSP+,TOS
+MOV @RSP+,IP
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] DEFER [IF]
+\ https://forth-standard.org/standard/core/DEFER
+\ DEFER "<spaces>name" --
+\ Skip leading space delimiters. Parse name delimited by a space.
+\ Create a definition for name with the execution semantics defined below.
+
+\ name Execution: --
+\ Execute the xt that name is set to execute, i.e. NEXT (nothing),
+\ until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name.
+: DEFER
+CREATE
+HI2LO
+MOV #$4030,-4(W) \ CFA = MOV @PC+,PC = BR MOV @IP+,PC
+MOV #NEXT_ADR,-2(W) \ PFA = address of MOV @IP+,PC to do nothing.
+MOV @RSP+,IP
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] IF [IF] \ define IF THEN
+\ https://forth-standard.org/standard/core/IF
+\ IF -- IFadr initialize conditional forward branch
+CODE IF \ immediate
+SUB #2,PSP \
+MOV TOS,0(PSP) \
+MOV &DP,TOS \ -- HERE
+ADD #4,&DP \ compile one word, reserve one word
+MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN
+ADD #2,TOS \ -- HERE+2=IFadr
+MOV @IP+,PC
+ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/THEN
+\ THEN IFadr -- resolve forward branch
+CODE THEN \ immediate
+MOV &DP,0(TOS) \ -- IFadr
+MOV @PSP+,TOS \ --
+MOV @IP+,PC
+ENDCODE IMMEDIATE
+[THEN]
+
+[UNDEFINED] ELSE [IF]
+\ https://forth-standard.org/standard/core/ELSE
+\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack
+CODE ELSE \ immediate
+ADD #4,&DP \ make room to compile two words
+MOV &DP,W \ W=HERE+4
+MOV #BRAN,-4(W)
+MOV W,0(TOS) \ HERE+4 ==> [IFadr]
+SUB #2,W \ HERE+2
+MOV W,TOS \ -- ELSEadr
+MOV @IP+,PC
+ENDCODE IMMEDIATE
+[THEN]
+
+[UNDEFINED] IS [IF] \ define DEFER! IS
+
+\ https://forth-standard.org/standard/core/DEFERStore
+\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER.
+CODE DEFER! \ xt2 xt1 --
+MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2]
+MOV @PSP+,TOS \ --
+MOV @IP+,PC
+ENDCODE
+
+\ https://forth-standard.org/standard/core/IS
+\ IS <name> xt --
+\ used as is :
+\ DEFER DISPLAY create a "do nothing" definition (2 CELLS)
+\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY
+\ or in a definition : ... ['] U. IS DISPLAY ...
+\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words
+\
+\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words...
+: IS
+STATEADR @
+IF POSTPONE ['] POSTPONE DEFER!
+ELSE ' DEFER!
+THEN
+; IMMEDIATE
+[THEN]
+
+[UNDEFINED] >BODY [IF]
+\ https://forth-standard.org/standard/core/toBODY
+\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word
+CODE >BODY
+ADD #4,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] SPACE [IF]
+\ https://forth-standard.org/standard/core/SPACE
+\ SPACE -- output a space
+: SPACE
+$20 EMIT ;
+[THEN]
+
+[UNDEFINED] SPACES [IF]
+\ https://forth-standard.org/standard/core/SPACES
+\ SPACES n -- output n spaces
+CODE SPACES
+CMP #0,TOS
+0<> IF
+ PUSH IP
+ BEGIN
+ LO2HI
+ $20 EMIT
+ HI2LO
+ SUB #2,IP
+ SUB #1,TOS
+ 0= UNTIL
+ MOV @RSP+,IP
+THEN
+MOV @PSP+,TOS \ -- drop n
+NEXT
+ENDCODE
+[THEN]
+
+[UNDEFINED] DUP [IF] \ define DUP and DUP?
+\ https://forth-standard.org/standard/core/DUP
+\ DUP x -- x x duplicate top of stack
+CODE DUP
+BW1 SUB #2,PSP \ 2 push old TOS..
+ MOV TOS,0(PSP) \ 3 ..onto stack
+ MOV @IP+,PC \ 4
+ENDCODE
+
+\ https://forth-standard.org/standard/core/qDUP
+\ ?DUP x -- 0 | x x DUP if nonzero
+CODE ?DUP
+CMP #0,TOS \ 2 test for TOS nonzero
+0<> ?GOTO BW1 \ 2
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+[UNDEFINED] OVER [IF]
+\ https://forth-standard.org/standard/core/OVER
+\ OVER x1 x2 -- x1 x2 x1
+CODE OVER
+MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2
+MOV @PSP,TOS \ 2 -- x1 (x2) x1
+SUB #2,PSP \ 1 -- x1 x2 x1
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] U.R [IF] \ defined in {UTILITY}
+: U.R \ u n -- display u unsigned in n width (n >= 2)
+ >R <# 0 # #S #>
+ R> OVER - 0 MAX SPACES TYPE
+;
+[THEN]
+
+[UNDEFINED] DO [IF] \ define DO LOOP +LOOP
+\ https://forth-standard.org/standard/core/DO
+\ DO -- DOadr L: -- 0
+CODE DO
+SUB #2,PSP \
+MOV TOS,0(PSP) \
+ADD #2,&DP \ make room to compile xdo
+MOV &DP,TOS \ -- HERE+2
+MOV #XDO,-2(TOS) \ compile xdo
+ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2
+MOV &LEAVEPTR,W \
+MOV #0,0(W) \ -- HERE+2 L-- 0
+MOV @IP+,PC
+ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/LOOP
+\ LOOP DOadr -- L-- an an-1 .. a1 0
+CODE LOOP
+ MOV #XLOOP,X
+BW1 ADD #4,&DP \ make room to compile two words
+ MOV &DP,W
+ MOV X,-4(W) \ xloop --> HERE
+ MOV TOS,-2(W) \ DOadr --> HERE+2
+BEGIN \ resolve all "leave" adr
+ MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell
+ SUB #2,&LEAVEPTR \ --
+ MOV @TOS,TOS \ -- first LeaveStack value
+ CMP #0,TOS \ -- = value left by DO ?
+0<> WHILE
+ MOV W,0(TOS) \ move adr after loop as UNLOOP adr
+REPEAT
+ MOV @PSP+,TOS
+ MOV @IP+,PC
+ENDCODE IMMEDIATE
+
+\ https://forth-standard.org/standard/core/PlusLOOP
+\ +LOOP adrs -- L-- an an-1 .. a1 0
+CODE +LOOP
+MOV #XPLOOP,X
+GOTO BW1 \ goto BW1 LOOP
+ENDCODE IMMEDIATE
+[THEN]
+
+[UNDEFINED] I [IF]
+\ https://forth-standard.org/standard/core/I
+\ I -- n R: sys1 sys2 -- sys1 sys2
+\ get the innermost loop index
+CODE I
+SUB #2,PSP \ 1 make room in TOS
+MOV TOS,0(PSP) \ 3
+MOV @RSP,TOS \ 2 index = loopctr - fudge
+SUB 2(RSP),TOS \ 3
+MOV @IP+,PC \ 4 13~
+ENDCODE
+[THEN]
+
+[UNDEFINED] DUMP [IF] \ defined in {UTILITY}
+\ https://forth-standard.org/standard/tools/DUMP
+CODE DUMP \ adr n -- dump memory
+PUSH IP
+PUSH &BASEADR \ save current base
+MOV #$10,&BASEADR \ HEX base
+ADD @PSP,TOS \ -- ORG END
+LO2HI
+ SWAP \ -- END ORG
+ DO CR \ generate line
+ I 4 U.R SPACE \ generate address
+ I 8 + I
+ DO I C@ 3 U.R LOOP
+ SPACE
+ I $10 + I 8 +
+ DO I C@ 3 U.R LOOP
+ SPACE SPACE
+ I $10 + I \ display 16 chars
+ DO I C@ $7E MIN $20 MAX EMIT LOOP
+ $10 +LOOP
+ R> BASEADR ! \ restore current base
+;
+[THEN]
+
+\ -----------------------------------------------------------------------
+\ test CPUx instructions PUSHM, POPM, RLAM, RRAM, RRCM, RRUM
+\ -----------------------------------------------------------------------
+CODE TESTPUSHM
+BW1
+\ PUSHM #16,R14 \ uncomment to test error "out of bounds"
+\ PUSHM #2,R0 \ uncomment to test error "out of bounds"
+\ PUSHM #0,IP \ uncomment to test error "out of bounds"
+\ POPM #17,R15 \ uncomment to test error "out of bounds"
+\ POPM #2,R0 \ uncomment to test error "out of bounds"
+\ POPM #0,IP \ uncomment to test error "out of bounds"
+ MOV #22222,Y
+ MOV #3,X
+ MOV #2,W
+ MOV #1,T
+ MOV #0,S
+
+ PUSHM #4,IP \ PUSHM IP,S,T,W
+ POPM #4,IP \ POPM W,T,S,IP
+ SUB #10,PSP
+ MOV TOS,8(PSP) \ save old TOS
+ MOV S,6(PSP)
+ MOV T,4(PSP)
+ MOV W,2(PSP)
+ MOV X,0(PSP)
+ MOV Y,TOS
+\ RLAM #0,TOS \ uncomment to test error "out of bounds"
+\ RLAM #5,TOS \ uncomment to test error "out of bounds"
+ RRAM #1,TOS \ 0 < shift value < 5
+ RLAM #2,TOS
+ RRCM #1,TOS
+ RRUM #1,TOS
+ COLON \ high level part of the word starts here...
+ space . . . . .
+ ; \ and finishes here.
+ \
+TESTPUSHM ; you should see 11111 3 2 1 0 -->
+
+CODE TESTPOPM
+ GOTO BW1 \ JMP TESTPUSHM
+ENDCODE
+
+ \
+TESTPOPM ; you should see 11111 3 2 1 0 -->
+
+
+
+\ -----------------------------------------------------------------------
+\ test symbolic branch in assembler
+\ test a FORTH section encapsulated in an assembly word
+\ -----------------------------------------------------------------------
+CODE TEST1 \ the word "CODE" add ASSEMBLER as CONTEXT vocabulary...
+
+ MOV &BASEADR,&BASEADR \ to test &xxxx src operand
+ CMP #%10,&BASEADR
+0<> IF MOV #2,&BASEADR \ if base <> 2
+ELSE MOV #$0A,&BASEADR \ else base = 2
+THEN
+ COLON \ tips : no "ok" displayed in start of line <==> compilation mode
+ BASEADR @ U. \ always display 10 !
+ ;
+ \
+
+\ -----------------------------------------------------------------------
+\ test a word that starts as word FORTH and ends as assembly word
+\ -----------------------------------------------------------------------
+: TEST2 \ ":" starts compilation
+ BASEADR @ U. \ always display 10 !
+ HI2LO \ switch FORTH to ASM : compile one word (next address)
+ \ add vocabulary ASSEMBLER as CONTEXT vocabulary
+ \ switch in interpret mode
+ CMP #2, &BASEADR
+0<> IF MOV #2, &BASEADR \ if variable system BASE <> 2
+ELSE MOV #10,&BASEADR \ else (BASE = 2)
+THEN
+\ MOV #EXIT,PC \ to pair with ":" i.e. to restore IP saved by : then execute NEXT.
+\ but even compile two words, it's better to compile an inline EXIT :
+ MOV @RSP+,IP \ restore IP
+ MOV @IP+,PC \ = NEXT
+ENDCODE \ ends assembler : remove vocabulary ASSEMBLER from CONTEXT
+ \
+
+\ -----------------------------------------------------------------------
+\ test a word that starts as assembly word and ends as FORTH word
+\ -----------------------------------------------------------------------
+CODE TEST3 \ "CODE" starts assembler, i.e. add ASSEMBLER as CONTEXT vocabulary
+ CMP #2, &BASEADR
+0<> IF MOV #2, &BASEADR \ if variable system BASE <> 2
+ELSE MOV #10,&BASEADR \ else (BASE = 2)
+THEN COLON \
+ BASEADR @ U. \ always display 10 !
+; \
+ \
+
+
+\ -----------------------------------------------------------------------
+\ test an assembly jump spanning a section written in FORTH
+\ -----------------------------------------------------------------------
+: TEST5
+ SPACE
+ HI2LO
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV #%1010,TOS \ init count = 10
+BEGIN SUB #$0001,TOS
+ LO2HI
+ \ IP is already saved by word ":"
+ DUP U. \ display count
+ HI2LO
+ CMP #0,TOS
+0= UNTIL MOV @PSP+,TOS
+\ MOV #EXIT,PC \ to pair with ":" i.e. to restore IP saved by : then execute NEXT.
+ MOV @RSP+,IP \ restore IP
+ MOV @IP+,PC \ = NEXT
+ENDCODE
+ \
+TEST5 ; you should see : 9 8 7 6 5 4 3 2 1 0 -->
+ \
+
+\ -----------------------------------------------------------------------
+\ tests indexing address
+\ -----------------------------------------------------------------------
+
+[UNDEFINED] C, [IF]
+\ https://forth-standard.org/standard/core/CComma
+\ C, char -- append char
+CODE C,
+MOV &DP,W
+MOV.B TOS,0(W)
+ADD #1,&DP
+MOV @PSP+,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] C@ [IF]
+\ https://forth-standard.org/standard/core/CFetch
+\ C@ c-addr -- char fetch char from memory
+CODE C@
+MOV.B @TOS,TOS
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+[UNDEFINED] DOES> [IF]
+\ https://forth-standard.org/standard/core/DOES
+\ DOES> -- set action for the latest CREATEd definition
+CODE DOES>
+MOV &LAST_CFA,W \ W = CFA of CREATEd word
+MOV #DODOES,0(W) \ replace CFA (DOCON) by new CFA (DODOES)
+MOV IP,2(W) \ replace PFA by the address after DOES> as execution address
+MOV @RSP+,IP
+MOV @IP+,PC
+ENDCODE
+[THEN]
+
+: BYTES_TABLE_IDX
+CREATE
+0 DO I C,
+LOOP
+DOES>
++
+;
+
+8 BYTES_TABLE_IDX BYTES_TABLE \ create table "BYTES_TABLE" with bytes content = 0,1,2,3,4,5,6,7
+ \
+2 BYTES_TABLE C@ . ; you should see 2 -->
+\
+
+
+VARIABLE BYTES_TABLE1
+
+$0201 BYTES_TABLE1 ! \ words written in memory are little endian !
+
+CODE IDX_TEST1 \ index -- value
+ MOV.B BYTES_TABLE1(TOS),TOS \ -- value
+COLON
+ U.
+;
+
+0 IDX_TEST1 ; you should see 1 -->
+
+CODE TEST6
+ MOV 0(PSP),0(PSP) \
+ MOV @IP+,PC
+ENDCODE
+
+
+1 TEST6 . ; you should see 1 -->
+
+
+\ -----------------------------------------------------------------------
+\ tests access to a CREATED word with assembler
+\ -----------------------------------------------------------------------
+
+
+ \
+CREATE TABLE0
+0 C,
+1 C,
+2 C,
+3 C,
+ \
+
+CREATE TABLE10
+$10 C,
+$11 C,
+$12 C,
+$13 C,
+
+ \
+
+CREATE TABLE20
+$20 C,
+$21 C,
+$22 C,
+$23 C,
+ \
+
+CREATE TABLE
+
+
+TABLE 2 - CONSTANT PFA_TABLE \ PFA_TABLE leave the PFA of TABLE
+
+
+CODE REDIRECT ; <table> -- redirects TABLE to argument <table>
+MOV TOS,&PFA_TABLE
+MOV @PSP+,TOS
+MOV @IP+,PC
+ENDCODE
+ \
+
+CODE REDIRECT0 ; -- redirects TABLE to TABLE0
+MOV #TABLE0,&PFA_TABLE
+MOV @IP+,PC
+ENDCODE
+ \
+
+CODE REDIRECT10 ; -- redirects TABLE to TABLE10
+MOV #TABLE10,&PFA_TABLE
+MOV @IP+,PC
+ENDCODE
+ \
+
+CODE REDIRECT20 ; -- redirects TABLE to TABLE20
+MOV #TABLE20,&PFA_TABLE
+MOV @IP+,PC
+ENDCODE
+ \
+
+' TABLE0 10 DUMP
+ \
+' TABLE10 10 DUMP
+ \
+' TABLE20 10 DUMP
+ \
+ \
+TABLE0 REDIRECT TABLE 10 DUMP
+ \
+TABLE10 REDIRECT TABLE 10 DUMP
+ \
+TABLE20 REDIRECT TABLE 10 DUMP
+ \
+ \
+REDIRECT0 TABLE 10 DUMP
+ \
+REDIRECT10 TABLE 10 DUMP
+ \
+REDIRECT20 TABLE 10 DUMP
+ \
+
+TABLE0 PFA_TABLE ! TABLE 10 DUMP
+ \
+TABLE10 PFA_TABLE ! TABLE 10 DUMP
+ \
+TABLE20 PFA_TABLE ! TABLE 10 DUMP
+ \
+
+\ -----------------------------------------------------------------------
+\ tests behaviour of assembly error
+\ -----------------------------------------------------------------------
+\ R16 causes an error, assembler context is aborted and the word TEST7 is "hidden".
+
+\CODE TEST7
+\ MOV 0(truc),0(R16) ; display an error "out of bounds" -->
+
+; -----------------------------------------------------------------------
+; create a primary DEFERred assembly word
+; -----------------------------------------------------------------------
+
+
+DEFER TRUC ; here, TRUC is a secondary DEFERred word (i.e. without BODY)
+ \
+
+
+CODENNM ; leaves its execution address (CFA) on stack
+ SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV @IP+,PC
+ENDCODE
+
+DUP .
+
+IS TRUC ; TRUC becomes a primary DEFERred word
+ ; with its default action (DUP) located at its BODY addresse.
+
+TRUC . ; display TOS value -->
+
+
+' TRUC >BODY IS TRUC ; TRUC is reinitialzed with its default action
+
+
+TRUC . ; display TOS value -->
+
+\ ' DROP IS TRUC ; TRUC is redirected to DROP
+\
+\ TRUC ; The generated error displays stack empty! in reverse video, removes the TRUC definition and restarts the interpretation after the end of the file. And as you see, FastForth is able to display long lines, interesting, doesn't it? -->
+\
+\ bla
+\ bla
+\ bla
+\
+\
+\
+\
+\
+\
+\
+\ bla
+\ ...
+
+
+
+
--- /dev/null
+\ -----------------------------
+\ MSP-EXP430FR5969_TSTWORDS.4th
+\ -----------------------------
+
+PWR_STATE
+
+\ -----------------------------------------------------------------------
+\ test some assembler words and show how to mix FORTH/ASSEMBLER routines
+\ -----------------------------------------------------------------------
+LOAD" \misc\TestASM.4th"
+
+\ -------------------------------------
+\ here we returned in the TestWords.4th
+\ -------------------------------------
+ECHO
+\ ----------
+\ LOOP tests
+\ ----------
+: LOOP_TEST 8 0 DO I . LOOP
+;
+
+LOOP_TEST \ you should see 0 1 2 3 4 5 6 7 -->
+
+
+: LOOP_TEST1 \ n <LOOP_TEST1> ---
+
+ BEGIN DUP U. 1 -
+ ?DUP
+ 0= UNTIL
+;
+
+: LOOP_MAX \ FIND_NOTHING --
+ 0 0
+ DO
+ LOOP \ 14 cycles by loop
+ ABORT" 65536 LOOP "
+;
+
+ : FIND_TEST \ FIND_TEST <word> --
+ $20 WORD \ -- c-addr
+ 50000 0
+ DO \ -- c-addr
+ DUP
+ FIND DROP DROP
+ LOOP
+ FIND
+ 0= IF ABORT" <-- not found !"
+ ELSE ABORT" <-- found !"
+ THEN
+ ;
+
+\ seeking $ word, FIND jumps all words on their first character so time of word loop is 20 cycles
+\ see FIND in the source file for more information
+\
+\ FIND_TEST <lastword> result @ 8MHz, monothread : 1,2s
+\
+\ FIND_TEST $ results @ 8MHz, monothread, 201 words in vocabulary FORTH :
+\ 27 seconds with only FORTH vocabulary in CONTEXT
+\ 540 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 2.6866 us / word, 21,49 cycles / word (for 20 cycles calculated (see FIND in source file)
+\
+\
+\ FIND_TEST $ results @ 8MHz, 2 threads, 201 words in vocabulary FORTH :
+\ 13 second with only FORTH vocabulary in CONTEXT
+\ 260 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 1,293 us / word, 10,34 cycles / word
+\
+\ FIND_TEST $ results @ 8MHz, 4 threads, 201 words in vocabulary FORTH :
+\ 8 second with only FORTH vocabulary in CONTEXT
+\ 160 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 0,796 us / word, 6,37 cycles / word
+\
+\ FIND_TEST $ results @ 8MHz, 8 threads, 201 words in vocabulary FORTH :
+\ 4.66 second with only FORTH vocabulary in CONTEXT
+\ 93 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 0,4463 us / word, 3,7 cycles / word
+\
+\ FIND_TEST $ results @ 8MHz, 16 threads, 201 words in vocabulary FORTH :
+\ 2,8 second with only FORTH vocabulary in CONTEXT
+\ 56 us for one search ( which gives the delay for QNUMBER in INTERPRET routine)
+\ 0,278 us / word, 2,22 cycles / word
+\
+\ --------
+\ KEY test
+\ --------
+: KEY_TEST
+ ." type a key : "
+ KEY EMIT \ wait for a KEY, then emit it
+;
+\ KEY_TEST
--- /dev/null
+\ -*- coding: utf-8 -*-
+\ http://patorjk.com/software/taag/#p=display&f=Banner&t=Fast Forth
+
+\ TARGET SELECTION
+\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989
+\ MSP_EXP430FR4133 MSP_EXP430FR2433 MSP_EXP430FR2355 CHIPSTICK_FR2433
+\ MY_MSP430FR5738_1 MY_MSP430FR5738 MY_MSP430FR5948 MY_MSP430FR5948_1
+\ JMJ_BOX
+
+\ Fast Forth For Texas Instrument MSP430FRxxxx FRAM devices
+\ Copyright (C) <2015> <J.M. THOORENS>
+\
+\ This program is free software: you can redistribute it and/or modify
+\ it under the terms of the GNU General Public License as published by
+\ the Free Software Foundation, either version 3 of the License, or
+\ (at your option) any later version.
+\
+\ This program is distributed in the hope that it will be useful,
+\ but WITHOUT ANY WARRANTY; without even the implied warranty of
+\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+\ GNU General Public License for more details.
+\
+\ You should have received a copy of the GNU General Public License
+\ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+\ REGISTERS USAGE
+\ rDODOES to rEXIT must be saved before use and restored after
+\ scratch registers Y to S are free for use
+\ under interrupt, IP is free for use
+
+\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT, rDOVAR, rDOCON, rDODOES
+\ example : PUSHM IP,Y
+\
+\ POPM order : rDODOES, rDOCON, rDOVAR, rEXIT, Y, X, W, T, S, IP,TOS,PSP
+\ example : POPM Y,IP
+
+\ FORTH conditionnals: unary{ 0= 0< 0> }, binary{ = < > U< }
+
+\ ASSEMBLER conditionnal usage with IF UNTIL WHILE S< S>= U< U>= 0= 0<> 0>=
+
+\ ASSEMBLER conditionnal usage with ?JMP ?GOTO S< S>= U< U>= 0= 0<> 0<
+
+
+PWR_STATE
+
+CODE DSM/REM \ D1 / D2 --> DREM DQUOT
+ MOV TOS,Y \ 1 Y=DVRhi
+ MOV @PSP+,W \ 2 W=DVRlo
+ MOV @PSP+,X \ 2 X=DVDhi
+ MOV @PSP,T \ 2 T=DVDlo
+ PUSHM #5,X \ 7 PUSHM DVDhi,DVRhi, M, P, Q
+ AND #-1,Y \ 1 Y=DVRhi < 0 ?
+S< IF XOR #-1,W \ 1 W=INV(DVRlo)
+ XOR #-1,Y \ 1 Y=INV(DVRhi)
+ ADD #1,W \ 1 W=INV(DVRlo)+1
+ ADDC #0,Y \ 1 Y=INV(DVRhi)+C
+THEN
+ AND #-1,X \ 1 X=DVDhi < 0 ?
+S< IF XOR #-1,T \ 1 T=INV(DVDlo)
+ XOR #-1,X \ 1 X=INV(DVDhi)
+ ADD #1,T \ 1 T=INV(DVDlo)+1
+ ADDC #0,X \ 1 X=INV(DVDhi)+C
+THEN
+\ ------------------------------------------------------------------------
+\ don't uncomment lines below, don't rub out, please !
+\ ------------------------------------------------------------------------
+\ UD/MOD DVDlo DVDhi DVRlo DVRhi -- REMlo REMhi QUOTlo QUOThi
+\ ------------------------------------------------------------------------
+\ MOV TOS,Y \ 1 Y=DVRhi
+\ MOV @PSP+,W \ 2 W=DVRlo
+\ MOV @PSP+,X \ 2 X=DVDhi
+\ MOV @PSP,T \ 2 T=DVDlo
+\ PUSHM #5,X \ 7 PUSHM DVDhi,DVRhi, M, P, Q
+ MOV #0,M \ 1 M=REMlo = 0
+ MOV #0,P \ 1 P=REMhi = 0
+ MOV #32,Q \ 2 Q=count
+BW1 CMP Y,P \ 1 REMhi = DVRhi ?
+ 0= IF CMP W,M \ 1 REMlo U< DVRlo ?
+ THEN
+ U>= IF SUB W,M \ 1 no: REMlo - DVRlo (carry is set)
+ SUBC Y,P \ 1 REMhi - DVRhi
+ THEN
+ BEGIN ADDC S,S \ 1 RLC quotLO
+ ADDC TOS,TOS \ 1 RLC quotHI
+ SUB #1,Q \ 1 Decrement loop counter
+ U>= WHILE \ 2 out of loop if count<0
+ ADD T,T \ 1 RLA DVDlo
+ ADDC X,X \ 1 RLC DVDhi
+ ADDC M,M \ 1 RLC REMlo
+ ADDC P,P \ 1 RLC REMhi
+ U< ?GOTO BW1 \ 2 19~ loop
+ SUB W,M \ 1 REMlo - DVRlo
+ SUBC Y,P \ 1 REMhi - DVRhi
+ BIS #1,SR \ 1
+ REPEAT \ 2 16~ loop
+ MOV M,T \ 1 T=REMlo
+ MOV P,W \ 1 W=REMhi
+ POPM #5,X \ 7 X=DVDhi, Y=DVRhi, restore M, P, Q, as system regs
+ CMP #0,X \ 1 sign of Rem ?
+ S< IF XOR #-1,T \ 1 INV(REMlo)
+ XOR #-1,W \ 1 INV(REMhi)
+ ADD #1,T \ 1 INV(REMlo)+1
+ ADDC #0,W \ 1 INV(REMhi)+C
+ THEN
+ SUB #4,PSP \
+ MOV T,4(PSP) \ REMlo
+ MOV W,2(PSP) \ REMhi
+ XOR X,Y
+ CMP #0,Y \ sign of Quot ?
+S< IF XOR #-1,S \ 1 INV(QUOTlo)
+ XOR #-1,TOS \ 1 INV(QUOThi)
+ ADD #1,S \ 1 INV(QUOTlo)+1
+ ADDC #0,TOS \ 1 INV(QUOThi)+C
+THEN
+ MOV S,0(PSP) \ 3 QUOTlo
+ MOV @IP+,PC \ 4
+ENDCODE
+
+PWR_HERE
+
+[UNDEFINED] DROP [IF]
+\ https://forth-standard.org/standard/core/DROP
+\ DROP x -- drop top of stack
+CODE DROP
+MOV @PSP+,TOS \ 2
+MOV @IP+,PC \ 4
+ENDCODE
+[THEN]
+
+: UD. \ u -- display ud (unsigned)
+<# #S #> TYPE $20 EMIT
+;
+
+\ https://forth-standard.org/standard/double/Dd
+\ D. dlo dhi -- display d (signed)
+CODE D.
+MOV #U.,W \ U. + 10 = D.
+ADD #10,W
+MOV W,PC
+ENDCODE
+
+
+
+; dvd div ; Quot Rem
+ .0 .0 UD/MOD D. D. ; inf 0 -->
+ .0 .1 UD/MOD D. D. ; 0 0 -->
+ .1 .0 UD/MOD D. D. ; inf dvd -->
+ .1 .1 UD/MOD D. D. ; 1 0 -->
+ .1 .2 UD/MOD D. D. ; 0 1 -->
+ .0 .2 UD/MOD D. D. ; 0 0 -->
+ .2 .0 UD/MOD D. D. ; inf dvd -->
+ .2 .1 UD/MOD D. D. ; 2 0 -->
+ .2 .2 UD/MOD D. D. ; 1 0 -->
+ .2 .3 UD/MOD D. D. ; 0 2 -->
+ .0 .3 UD/MOD D. D. ; 0 0 -->
+ .3 .0 UD/MOD D. D. ; inf dvd -->
+ .3 .1 UD/MOD D. D. ; 3 0 -->
+ .3 .2 UD/MOD D. D. ; 1 1 -->
+ .3 .3 UD/MOD D. D. ; 1 0 -->
+ .3 .4 UD/MOD D. D. ; 0 3 -->
+ .4 .1 UD/MOD D. D. ; 4 0 -->
+
+; dvd div ; Quot Rem
+ .0 -.1 UD/MOD D. D. ; 0 0 -->
+ -.1 .0 UD/MOD D. D. ; inf dvd -->
+ -.1 .1 UD/MOD D. D. ; dvd 0 -->
+ -.1 -.1 UD/MOD D. D. ; 1 0 -->
+ -.1 -.2 UD/MOD D. D. ; 1 1 -->
+ -.1 -.3 UD/MOD D. D. ; 1 2 -->
+ -.2 .0 UD/MOD D. D. ; inf dvd -->
+ -.2 -.1 UD/MOD D. D. ; 0 dvd -->
+ -.2 -.2 UD/MOD D. D. ; 1 0 -->
+ -.2 -.3 UD/MOD D. D. ; 1 1 -->
+ -.2 -.4 UD/MOD D. D. ; 1 2 -->
## FastForth for MSP430FRxxxx TI's CPUs, light, fast, reliable.
-Tested on TI MSP-EXP430FR 5739,
-[5969](https://duckduckgo.com/?q=MSP-EXP430FR5969),
-[5994](https://duckduckgo.com/?q=MSP-EXP430FR5994),
-6989,
-4133,
-[2476](https://duckduckgo.com/?q=Lp-MSP430FR2476),
-[2355](https://duckduckgo.com/?q=MSP-EXP430FR2355),
-2433) launchpads, at 1, 2, 4, 8, 12, 16 MHz plus 20 & 24 MHz with MSP430FR(23xx,57xx) devices.
-FastForth is a "load interpret compile execute" operating system for the CPU's MSP430 Texas Instruments with FRAM:
+Tested on TI MSP-EXP430FR
+[5739](https://duckduckgo.com/?q=MSP-EXP430FR5739&iax=images&ia=images),
+[**5969**](https://duckduckgo.com/?q=MSP-EXP430FR5969&iax=images&ia=images),
+[**5994**](https://duckduckgo.com/?q=MSP-EXP430FR5994&iax=images&ia=images),
+[6989](https://duckduckgo.com/?q=MSP-EXP430FR6989&iax=images&ia=images),
+[4133](https://duckduckgo.com/?q=MSP-EXP430FR4133&iax=images&ia=images),
+[2476](https://duckduckgo.com/?q=LP-MSP430FR2476&iax=images&ia=images),
+[**2355**](https://duckduckgo.com/?q=MSP-EXP430FR2355&iax=images&ia=images),
+[2433](https://duckduckgo.com/?q=MSP-EXP430FR2433&iax=images&ia=images) launchpads, at 1, 2, 4, 8, 12, 16 MHz plus 20 & 24 MHz with MSP430FR(23xx,57xx) devices.
-* LOAD: choice of the TERMINAL (TERATERM.exe) interface:
- * UART TERMINAL up to 6MBds @ MCLK=24MHz, with software (XON/XOFF) and/or hardware (RTS) control flow, **transmit delay: 0 ms/char, 0 ms/line**
+note: if you want to write a program to make a LED flash, i suggest you to go [here](https://www.raspberrypi.com),
+ but if you want to deepen your programming basics, you've come to the right place.
- * a very well designed **I2C TERMINAL up to 1MHz**, with a behaviour full duplex, ready to communicate with all modules **I2C_FastForth** wired onto bus,
+FastForth is a "Just In First" Load-Interpret-Compile Operating System for all the 16/20 bits CPU MSP430FRxxxx (MSP430 with FRAM) :
+
+* LOAD: choice of the TERMINAL interface:
+
+ * UART TERMINAL up to 6MBds @ MCLK=24MHz, with software (XON/XOFF) or hardware (RTS) control flow, **transmit delay: 0 ms/char, 0 ms/line**
+
+ * a very well designed **I2C TERMINAL**, with a full duplex behaviour, ready to communicate with all the targets **I2C_FastForth** wired on its I2C bus,
* INTERPRET: with a 16-entry word-set that speeds up the FORTH interpreter by 4,
-* COMPILE: in addition to the FORTH engine, the **MSP430 assembler (label free) with syntax TI's**,
+* COMPILE: in addition to the FORTH engine, the **MSP430 assembler, label free, with the TI's syntax** (not the FORTH one!),
-and as result **"load interpret compile" a source file is faster and easier than loading its binary equivalent** via the TI's eZFET interface:
-For example, with MCLK=24MHz, THREADS=16, UART=6MBds 8n1, a [PL2303GC](https://duckduckgo.com/?q=DSD+TECH+SH-U06A+PL2303GC) and Teraterm.exe as TERMINAL, the download/interpret/execute process of the file CORETEST is done at an effective rate close to 43KB/s (430kBds).
-with a bridge UARTtoI2C and an I2C_Slave target MCLK=24MHz, THREADS=16, the effective rate is the same ( I don't understand but it's like this...)
+and as result "Load Interpret Compile" a source file is faster and easier than **just** loading its equivalent TI.txt binary file via the TI's eZFET interface.
+For example, with a target running at 24MHz, UART=6MBds 8n1, an USBtoUART bridge [PL2303GC](https://duckduckgo.com/?q=DSD+TECH+SH-U06A)
+and [Teraterm.exe](https://osdn.net/projects/ttssh2/releases/) as TERMINAL,
+the "JIF" process of the /MSP430-FORTH/CORETEST.4TH file is done at an **effective rate** up to 800 kBds, up to 500 kBds with an I2C_Slave target running at 24MHz, and beyond 1Mbit/s from a SD_CARD.
+This is, by far, unparalleled on the planet FORTH, and on others too.
-Despite its **size of 5 kb** FastForth includes:
+Despite its **size of 4.75 kb** FastForth includes:
* FORTH kernel with interpreting decimal, hex, binary (#,$,% prefixed) numbers, digits separator '_', 'char', double numbers and Q15.16 numbers,
-* the MSP430 16 bits assembler (1,5 kb),
+* the assembler for MSP430 (with TI's syntax),
-* a good error management which interrupts the downloading at the slightest error,
+* a good error handling which discards the "JIF" process of source files and thus avoids system crash,
-* a memory management which can be modulated according to these 3 levels: MARKER, RESET, DEEP_RESET,
+* a memory management which can be modulated according to these 3 levels (software|hardware): `-1 SYS`|`<SW1+RST>`, `MARKER`|, `6 SYS`|`<RST>`.
-* everything you need to write a real time application made of a mix of FORTH/assembler:
+* everything you need to write a real time application:
- * the complete set of the FORTH building words,
+ * the complete set of the FORTH building definitions,
* conditional compilation,
* thanks to [GEMA preprocessor](http://gema.sourceforge.net/new/index.shtml), the compilation of all symbolic addresses without having to declare them in FORTH,
- * easy roundtrip between FORTH and assembler with only two switches 'one word' `HI2LO` and `LO2HI`,
+ * easy roundtrip between FORTH and ASSEMBLER levels with only two 'one word' switches: `HI2LO`, `LO2HI`,
- * automatic releasing memory with MARKER tags,
+ * automatic releasing memory with `MARKER` and `RST_SET`/`RST_RET` tags,
- * Fully configurable sequences: reset, initialisation and background,
+ * Fully configurable sequences reset, init and background,
* CPU in sleep mode LPM0|LPM4 in awaiting a command from UART|I2C TERMINAL, and ready to process any interrupts.
-For only 3 kbytes in addition, we have the primitives to access the SD_CARD FAT16 and FAT32: read, write, del, download source files and also to copy them from PC to the SD_Card.
-It works with all SD\_CARD memories from 64MB to 64GB with FAT32 format.
-The cycle to read/write a **byte** is below 1us @ 16 MHz.
+If you want to quickly get an idea of what Fast Forth can do, see the /MSP430-FORTH/UARTI2CS.f application file.
+You will see that the FORTH language is used here as packaging of the program written in assembler.
+See /MSP430-FORTH/FF_SPECS.f for another point of view.
+
+For only 3 kbytes in addition, we have the primitives to access the SD_CARD FAT32: read, write, del, download source files and also to copy them from PC to the SD_Card.
+It works with all SD\_CARD memories from 4GB to 64GB with FAT32 format.
With all the kernel addons, including the 20 bits MSP430\_X assembler and the SD\_Card driver, FastForth size is **10 kB**.
-After downloading CORE_ANS.f file (+2 kb), FastForth passes successfully the CORE ANS94 + COREPLUSTEST tests.
+Once downloading /MSP430-FORTH/CORE_ANS.f file (2.25 kb), FastForth passes the tests: /MSP430-FORTH/CORETEST.4TH ( CORE ANS94 + COREPLUSTEST ), thus proving its compliance with the ANS94 standard.
However, if all works well with Windows 10, it works less well with Linux due to the lack of a good alternative to TERATERM...
## how to connect TERMINAL
The files \binaries\launchpad_xMHz.txt are the executables ready to use with a serial terminal
- (TERATERM.exe), 115200Bds, with XON/XOFF or RTS_hardware flow controls and a PL2303TA/CP2102 cable.
+ (TERATERM.exe), with XON/XOFF or RTS_hardware flow controls and a PL2303TA/CP2102 cable.
------------------------------------------------------------------------------------------
WARNING! doesn't use it to supply your launchpad: red wire is 5V ==> MSP430FRxxxx destroyed!
------------------------------------------------------------------------------------------
J101 connector
|
v
- TI Launchpad <--> FET interface <-------------> USB <-------------> MSP430Flasher.exe/UniFlash
+ TI Launchpad <--> FET interface <-------------> USB <-------->COMx<----> MSP430Flasher.exe/UniFlash
Vcc <--- 3V3
- TST/SBWTCK <--> SBWTCK
- GND <--> GND
- RST/SBWTDIO <--> SBWTDIO
+ TST/SBWTCK <--> SBWTCK )
+ GND <--> GND > used to program MAIN
+ RST/SBWTDIO <--> SBWTDIO )
- TI Launchpad <--> CP2102/PL2302TA cable <------> USB <-------------> TERATERM.exe
+ TI Launchpad <--> CP2102/PL2303 cable <--------> USB <-------->COMy<----> TERATERM.exe
RX <--- TX )
- GND <--> GND > used by FastForth TERMINAL
+ GND <--> GND > FastForth TERMINAL
TX ---> RX )
- RTS ---> CTS (optionnal) RTS pin Px.y is described in your \inc\launchpad.asm)
+ Pin Px.y RTS ---> CTS (optionnal) RTS pin Px.y is described in your \inc\launchpad.asm)
-### programming with BSL_Scripter.exe (don't work with MSP-EXP430FR2355 launchpad)
-
- J101 connector
- |
- v
- MSP430FRxxxx <--> CP2102/PL2303TA cable <------> USB <-------->+<--> TERATERM.exe
- RX <--- TX ) |
- GND <--> GND > used by FastForth TERMINAL +<--> BSL_Scripter.exe
- TX ---> RX )
- Vcc <--- 3V3 )
- TST/SBWTCK <--- RTS )
- GND <--> GND > used by BSL_Scripter
- RST/SBWTDIO <--> DTR )
-
- Before programming device, close teraterm TERMINAL and connect the wire RST/SBWTDIO <--> DTR
- Once device is programmed, open teraterm TERMINAL then disconnect the wire RST/SBWTDIO <--> DTR.
-
## Out of the box
Once FastForth is loaded in the target FRAM memory, you add assembly code or FORTH code, or both,
XON/XOFF flow control allows 3.75kV galvanic isolation of terminal input with SOIC8 Si8622EC|ISO7021.
-If you choose I2C_FastForth for your project, you will need of one more launchpad to make the USBtoI2C bridge.
-See driver for I2C_FastForth: \MSP430-FORTH\UARTI2CS.f.
-
-After downloading of complementary words in \MSP430-FORTH\ANS_COMP.f, FastForth executes CORETEST.4th
-in one second, and without errors which ensures its compatibility with the FORTH CORE ANS94 standard.
+If you choose I2C_FastForth for your project, you will need of one more launchpad to make the UARTtoI2C bridge.
+See driver for it : \MSP430-FORTH\UARTI2CS.f.
Notice that FAST FORTH interprets lines up to 84 chars, only SPACE as delimiter, only CR+LF as
-End Of Line, and BACKSPACE.
-And that the high limit of a FORTH program memory is $FF80.
+End Of Line, and BACKSPACE; all other control chars are discarded.
+And that the high limit of a FORTH program memory is $FF40.
Finally, using the SCITE editor as IDE, all is ready to do everything from its "tools" menu.
What is new ?
-------------
-### V309
+### V4.0, the last.
+
+* = V3.9 - 26 bytes.
+
+* `HNDCODE` and `TICK` fixed
+
+* `KEY` and `EMIT` rewritten, also `ECHO` and `NOECHO`
+
+* the assembler handles correctly argument+/-offset
+
+* the SD_Card driver is re-rewritten
+
+ * it only supports FAT32 format and SD Cards from 4 GB to 64 GB
+
+ * FAT32 Directories can be enlarged
+
+ * fixed errors handling
+
+* the driver UART to I2C is enhanced and more reliable
+
+* added DOUBLE.asm in /ADDONS (DOUBLE word set)
-* = V308 - 344 bytes.
+
+### V3.9
+
+* = V3.8 - 350 bytes.
* removed `INTERPRET`, `CR` and the useless error line displaying.
* Removed `PWR_HERE` and `PWR_STATE`, replaced `RST_HERE` by `RST_SET` and `RST_STATE` by `RST_RET`.
-* Replaced `WIPE` by `-1 SYS`, `COLD` by `6 SYS` and `WARM` by `0 SYS` or simply `SYS`.
+* Replaced `WIPE` by `-1 SYS`, `COLD` by `4 SYS` and `WARM` by `0 SYS` or simply `SYS`.
-* replaced `VOCABULARY` with `WORDSET`. `ALSO` is also :-) removed because the executing of a definition created by `WORDSET` adds it into the CONTEXT stack. For example, typing `FORTH` adds it into CONTEXT. Note that as result the use of ONLY is modified: `FORTH ONLY` instead of `ONLY FORTH`.
+* replaced `VOCABULARY` with `WORDSET`. `ALSO` is removed because the executing of a definition created by `WORDSET` adds it into the CONTEXT stack. For example, typing `FORTH` adds it into CONTEXT. Note that as result the use of ONLY is modified: `FORTH ONLY` instead of ~~`ONLY FORTH`~~.
* modified QNUMBER QABORT `ABORT` `QUIT` `HI2LO` `PREVIOUS` `WORD` `FIND` `>NUMBER` `TYPE` `#>` `COUNT` `SWAP` `TICK` `POSTPONE` `COLON` `[ELSE]` plus the assembler.
* the word-set `ASSEMBLER` is renamed `hidden` because it stores not only the ASM instructions definitions but also HDNCODE definitions.
-* when you executes a `MARKER` definition, it starts by removing its previous definition if exists.
+* when you execute a `MARKER` definition, it starts by removing from its previous definition if exists.
* Some bugs corrected:
* QNUMBER FORWDOES `TYPE` `WORD`,
* `M*/` in \MSP430-FORTH\DOUBLE.f file,
- * the assembler handles correctly argument+/-offset.
+ * ~~the assembler handles correctly argument+/-offset.~~
* User can choose floored or symmetric division. See \MSP430-FORTH\ANS_CORE.f
* FF_SPECS.f displays all word-sets, including the `hidden` one.
* the SD_Card driver is rewritten. Only FAT32 format is supported. I suggest 4kb sized clusters.
- The old WRITE" command is duplicated :
- ** `WRITE"` to create a new file (or to overwrite it if exists),
- ** `APPEND"` to append to a file (or to create it if not exists)
+ The old `WRITE"` command is duplicated :
+ * `WRITE"` to create a new file (to overwrite if found),
+ * `APPEND"` to append to a file (to create it if not found)
-### V308
+### V3.8
-* = V307 - 16 bytes.
+* = V3.7 - 16 bytes.
* Source file copy from TERMINAL to the SD\_Card of any I2C\_FastForth target works fine.
* Double number word `D<` corrected in \MSP430-FORTH\DOUBLE.f
-### V307
+### V3.7
* 54 bytes added to (Kernel + Conditional_Compilation + Assembler).
When use in source.f files, all ASCII special chars are available. See \inc\FastForthREGtoTI.pat.
* Assembler allows "argument+offset" into FORTH area (0 to $FFFF). Examples:
- `MOV #RXON,&SLEEP+2` to store RXON addr at SLEEP+2 addr.
- `MOV.B BUFFER+-1(X),TOS` to load the byte at BUFFER-1(X) addr in the register TOS.
+ `MOV #RXON,&BACKGRND+2` to store RXON addr at BACKGRND+2 addr.
+ `MOV.B BUFFER-1(X),TOS` to load the byte at BUFFER-1(X) addr in the register TOS.
-* ~~`COLD` does same than hardware RST~~.
- `6 SYS` does same than hardware RST.
- ~~`WIPE` does same than hardware SW1+RST (DEEP_RESET)~~.
+* `6 SYS` does same than hardware RST.
`-1 SYS` does same than hardware SW1+RST (DEEP_RESET).
* More complicated:
-In the FastForth init process, COLD WARM SLEEP are modified and INIT_FORTH is added.
-They start each with a call to a paired assembly subroutine:
+ In the FastForth init process, COLD WARM BACKGRND are modified and INIT_FORTH is added.
+ They start each with a call to a paired assembly subroutine:
- RST_SYS failures --------->+ +<- ABORT_TERM <--------(error)<------------+<--COMPILE/EXECUTE<-INTERPRET<-+
- | | | ^
- RST ------------>+ | v v |
- v | +-> INIT_FORTH -> ABORT" ->+-> ABORT->QUIT->+->ACCEPT->+ +->ACCEPT->+
- SW1+RST -------->+ | ========== ^ | ^
- v v | v |
- -n SYS --------->+->COLD-->+->PUC->+-> INIT_FORTH --> WARM" ->+ +->SLEEP->+
- ^ ==== ^ ========== ==== =====
- | |
- +n SYS (even) -->+ (NOPUC)
- |
- +n SYS (odd) --------------------->+
- ^
- [0] SYS -------------------------->+
-
- CALL... &COLD_APP &SOFT_APP &HARD_APP &SLEEP_APP
- ========= ========= ========= ==========
- Default subroutine... COLD_TERM RET_ADR INIT_TERM RXON
- Default action... wait TERM idle do nothing init TERM UC, unlock I/O enable TERMINAL to TX
-
- note: -n SYS|SW1+RST reset the default subroutine of these four calls.
-
-On the other hand, MARKER is modified in such a way that MARKER\_DOES executes a CALL to
-the content of USER_BODY-2, by default RET_ADR:
+ RST_SYS failures ------------>+ +<- ABORT_TERM <--- ABORT" <--- (error) <---+<-- COMPILE/EXECUTE<-INTERPRET <--+
+ | | | ^
+ RST ----------->+ | v v |
+ v | +-> INIT_FORTH ----------->+-> ABORT->QUIT->+->ACCEPT->+ +->ACCEPT->+
+ SW1+RST ------->+ | ========== ^ | ^
+ v v | v |
+ -n SYS -------->+---> COLD -->+->PUC->+-> INIT_FORTH --> WARM -->+ +->BACKGRND->o
+ ^ ==== ^ ========== ==== ======== ^
+ | | \
+ +n SYS (even) ->+ | /
+ | \
+ +n SYS (odd) -->+--> (NOPUC) -------->+ UART_RX_INT/I2C_START_INT
+ ^ ====
+ [0] SYS ------->+
+
+ CALL... &STOP_APP &SOFT_APP &HARD_APP &BACKGRND_APP
+ ========= ========= ========= =============
+
+ Default subroutine INIT_STOP INIT_SOFT INIT_TERM INIT_BACKGRND
+ Default action UART: wait idle do nothing init TERM UC.. UART: send RXON
+ I2C: do nothing ..unlock I/O I2C: send Ctrl_Char $00
+
+ note: -n SYS|SW1+RST reset the default subroutine of these four calls.
+ don't use TOS in these subroutines.
+
+ On the other hand, MARKER is modified in such a way that MARKER\_DOES executes a CALL to
+ the content of USER_BODY-2, by default RET_ADR:
- MARKER [CFA] = DODOES
- [PFA] = MARKER_DOES
- [BODY] = previous DP (Dictionnary Pointer)
- ...
- [USER_PARAM-2] = RET_ADR as REMOVE_APP by default
+ MARKER [CFA] = DODOES
+ [PFA] = MARKER_DOES
+ [BODY] = previous DP (Dictionnary Pointer)
+ ...
+ [USER_PARAM-2] = RET_ADR as REMOVE_APP by default
By replacing [USER_PARAM-2] with the address of a new defined subroutine (named for example: REMOVE_XXX),
MARKER_DOES will execute it to restore n critical pointers (room made by 2n ALLOT) at USER_PARAM, USER_PARAM+2, ...
-Thus, with MARKER and the definition of subroutines STOP_XXX, INIT_SOFT_XXX, INIT_HARD_XXX, BACKGND_XXX,
+Thus, with MARKER and the definition of subroutines STOP_XXX, SOFT_XXX, HARD_XXX, BACKGRND_XXX,
the programmer has full control of his "XXX" real time application using interrupts,
-with everything he needs to start, stop and remove it properly, thanks to a 'soft' MARKER definition,
-avoiding the (SW1+RST) of the last chance.
+with everything he needs to start, stop and remove it properly, thanks to this 'soft' MARKER definition,
+avoiding the hardware (SW1+RST) of the last chance.
See example in /MSP430-FORTH/UARTI2CS.f.
-### V306
+### V3.6
* 8 bytes added to (Kernel + Conditional_Compilation + Assembler).
* Added the word set DOUBLE in the \MSP430-FORTH\DOUBLE.f file.
-### V305
+### V3.5
- 48 bytes removed.
+* 48 bytes removed.
- from Scite menu, we can program MSP430FRxxxx also with BSL_Scripter.
+* from Scite menu, we can program MSP430FRxxxx also with BSL_Scripter.
To do, save file \prog\BSL_Scripter.exe from:
https://github.com/drcrane/bslscripter-vs2017/releases/download/v3.4.2/BSL-Scripter-v3.4.2.zip,
So, we download both binaries and source files with only one CP2102|PL2303TA module,
the XON/XOFF TERMINAL and BSL_Scripter. Bye bye T.I. FET!
- ABORT messages display first the I2C address, if applicable.
- QNUMBER some issues solved.
- UART version of ACCEPT and KEY are shortened.
- EVALUATE is moved to CORE_ANS.
+* ABORT messages display first the I2C address, if applicable.
+
+* QNUMBER some issues solved.
+* UART version of ACCEPT and KEY are shortened.
+* EVALUATE is moved to CORE_ANS.
-### V304
+### V3.4
- 36 bytes removed.
+* 36 bytes removed.
- Fixed: word F. issue in FIXPOINT.asm
+* Fixed: word F. issue in FIXPOINT.asm
- the new kernel DEFERRED option adds :NONAME CODENNM DEFER IS.
+* the new kernel DEFERRED option adds :NONAME CODENNM DEFER IS.
- pin RESET is software replaced by pin NMI and so, RESET executes COLD, allowing code insert before BOR.
- however SYSRSTIV numbering remains unchanged: = 4 for RESET, = 6 for COLD.
+* pin RESET is software replaced by pin NMI and so, RESET executes COLD, allowing code insert before BOR.
+ however SYSRSTIV numbering remains unchanged: = 4 for RESET, = 6 for COLD.
- Hardware Deep RESET (S1+RST) reinitializes vectors interrupts and SIGNATURES area, as WIPE.
+* Hardware Deep RESET (S1+RST) reinitializes vectors interrupts and SIGNATURES area, as WIPE.
- A newcomer: FastForth for I2C TERMINAL. With the driver UART2I2CS running on another FastForth target,
- we have the USB to I2C_Slave bridge we need: one TERMINAL for up to 112 I2C_FastForth targets.
-
- +-------------------------+
- notebook USB to I2C_Slave bridge +-I2C-| others I2C_slave target |
- +-----------+ +-------------------------------------------------+ / +-------------------------+ |
- | | ¦ PL2303HXD target running UARTI2CS @24MHz¦ +-I2C-| MSP430FR4133 @ 1 MHz | |
- | | ¦------------+ +----------------------------¦ / +--------------------------+ |-+
- | | ¦ | 3wires| MSP430FR2355 @ 24MHz ¦/ | MSP430FR5738 @ 24 MHz | |
- | TERATERM -o->USB-o->USB2UART->o->UART-o-> FAST FORTH -> UARTI2CS -o-I2C-o-> FAST FORTH with option |-+
- | terminal | ¦ | 6MBds | (I2C MASTER) ¦ | TERMINAL_I2C (I2C SLAVE)|
- | | ¦------------+ +----------------------------¦ +--------------------------+
- | | ¦ |< 20cm>| ¦ up to 112 I2C_Slave targets
- +-----------+ +-------------------------------------------------+
-
- With the indicated MCLK and UART speed, Coretest.4th is downloaded to (and executed by) I2C_Slave in 800ms.
- The driver UARTI2CS works without error from 1MHz to 24MHz MCLK and from 115200Bds up to 6MBds UART.
- With I2C_Master running at 24 MHz, the I2C bus frequency is about 1MHz, and it works fine
- even if I2C_slave is running at 1 MHz.
- Don't forget to add two 3k3 pullup resistors on SCL and SDA...
-
- the Multi Master Mode works but is not tested in multi master environment.
+* A newcomer: FastForth for I2C TERMINAL. With the driver UART2I2CS running on another FastForth target,
+we have the USB to I2C_Slave bridge we need: one TERMINAL for up to 112 I2C_FastForth targets.
+
+ +-------------------------+
+ notebook USB to I2C_Slave bridge +-I2C-| others I2C_slave target |
+ +-----------+ +-------------------------------------------------+ / +-------------------------+ |
+ | | ¦ PL2303HXD target running UARTI2CS @24MHz¦ +-I2C-| MSP430FR4133 @ 1 MHz | |
+ | | ¦------------+ +----------------------------¦ / +--------------------------+ |-+
+ | | ¦ | 3wires| MSP430FR2355 @ 24MHz ¦/ | MSP430FR5738 @ 24 MHz | |
+ | TERATERM -o->USB-o->USB2UART->o->UART-o-> FAST FORTH -> UARTI2CS -o-I2C-o-> FAST FORTH with option |-+
+ | terminal | ¦ | 6MBds | (I2C MASTER) ¦ | TERMINAL_I2C (I2C SLAVE)|
+ | | ¦------------+ +----------------------------¦ +--------------------------+
+ | | ¦ |< 20cm>| ¦ up to 112 I2C_Slave targets
+ +-----------+ +-------------------------------------------------+
+
+With the indicated MCLK and UART speed, Coretest.4th (45896 bytes) is downloaded to (and executed by) I2C_Slave in 1220ms.
+The driver UARTI2CS works without error from 1MHz to 24MHz MCLK and from 115200Bds up to 6MBds UART.
+With I2C_Master running at 24 MHz, the I2C bus frequency is about 1MHz, and it works fine
+even if I2C_slave is running at 1 MHz.
+Don't forget to add two 3k3 pullup resistors on SCL and SDA...
+
+the Multi Master Mode works but is not tested in multi master environment.
- "cerise sur le gâteau": when they wait for a TERMINAL input (idle state),
- both I2C_Master and I2C_Slave(s) are sleeping in LPMx mode and the bus I2C is freed.
- The I2C_slave driver handles LPM4 mode.
+"Cerise sur le gâteau": when they wait for a TERMINAL input (idle state),
+both I2C_Master and I2C_Slave(s) are sleeping in LPMx mode and the bus I2C is freed.
+The I2C_slave driver handles LPM4 mode.
- The UART2I2CS does not use TI's horrible UCBx_I2C_Master driver, but a much faster software driver,
- with the UCBx still available for an I2C_Slave or SPI driver.
+The UART2I2CS does not use TI's horrible UCBx_I2C_Master driver, but a much faster software driver,
+with one more UCBx still available for an I2C_Slave or SPI driver.
##### HOW TO DO ?
At the end of UART2I2CS.f file set the <slave address you want>, i.e. $10.
then download it, it's done: TERMINAL is linked to I2C_Slave.
- Type `Alt+B` on teraterm (send UART break) to unlink I2C_Slave.
-
-### V302
-
- 646 bytes removed
- Kernel + FIXPOINT input + DOUBLE input + Conditional Compilation + Assembler under 5 kB.
-
- the FORTH kernel is drastically reduced to 55 words.
- All others are moved in the \ADDON\ANS_COMPLEMENT.asm file,
- the conditionnal compilation with the assembler allowing to reuse them on request.
-
- Fixed: QNUMBER,
- ACCEPT (XON/XOFF TERMINAL with MSP430FR2xxx).
- Modified: [ELSE].
-
- FF_SPECS.f displays FastForth environment.
-
-### V301
-
- 584 bytes removed, Kernel + Conditional Compilation + Assembler under 5.5 kb.
-
- the FORTH kernel is drastically reduced to 82 words, just what the operating system needs.
- All others are moved in the \ADDON\ANS_COMPLEMENT.asm file, the conditionnal compilation
- allowing you to use them on request.
-
- Taking into account the new TI launchpad LP_MSP430FR2476.
-
- Fixed: :NONAME (now aligned), LOAD" (no more crash on error).
- Modified: ACCEPT, WORD, HEADER, CODE, ENDCODE, ASM, GOTO, ?GOTO, RPT.
- Removed JMP <word> and ?JMP <word> from assembler (replaced by GOTO BWx and ?GOTO BWx).
-
- ACCEPT is modified to include the RXON call in the word SLEEP.
- By rewriting the defered word SLEEP, we can easily disable the TERMINAL_INPUT interrupt.
- See BACKGROUND, START and STOP in \MSP430-FORTH\RC5toLCD.f.
-
-### V300
-
- 4 bytes removed.
- The prompt "ok" becomes a compilation option.
-
- Taking into account the digit separator '_' in ?NUMBER, to better see when typing binary numbers.
- example: %1010100011000111 can be typed as well: %1010_1000_1100_0111
-
- Corrected >NUMBER
-
- Modified GetFreeHandle CloseHandle
-
- Tested with BLE 5.0 terminal (a couple of BGX13P EVK) at 16MHz, 921600 bds + terminal 5 wires:
- download throughput = 5 kbytes/s (and with errors when ECHO is ON), disappointing...
- (Bluetooth 2.1 terminal with one RN42 works well).
-
- RePeaTed instructions RRUX,RRCX,RLAX,ADDX,SUBX work fine! See TESTASMX.4TH
-
+ Type `Alt+B` on teraterm (send a BREAK) or press S2 on UARTtoI2C module to unlink I2C_Slave.
### PREVIOUS versions
Unlocking I/O's is transfered from RESET to WARM.
-Thus, by redirecting WARM, you can add I/O's configuration of your application before unlocking.
+Thus, by redefining HARD_APP, you can add I/O's configuration for your application before a global unlocking.
+
+The structure of primary DEFERred words as KEY,EMIT,CR,ACCEPT... is modified,
+the address of their default execute part, without name, can be found with: `' <name> >BODY`
-The structure of primary DEFERred words as KEY,EMIT,CR,WARM... is modified,
-the address of their default execute part, without name, can be found with:
- `' <name> >BODY`
+example, after this entry: `' DROP IS KEY` KEY runs DROP i.e. runs the redirection made by IS,
-example, after this entry: `' DROP IS KEY` KEY runs DROP i.e. runs the redirection
-made by IS,
but `' KEY >BODY EXECUTE` runs KEY, the default action at the BODY address.
-and: `' KEY >BODY IS KEY`
-restore the default action of this **primary** DEFERred word.
+and `' KEY >BODY IS KEY` restores the default action of this **primary** DEFERred word.
-WARNING! you cannot do that with words created by DEFER which creates only **secondary** DEFERred words, without BODY !
+to build a **primary** DEFERred definition, you must create a CODE definition followed by a :NONAME definition:
-to build a **primary** DEFERred FORTH word, you must create a DEFERred word followed by a
-:NONAME definition:
+ CODE SPACES \ create a CODE definition named 'SPACES' which does a jump to the NEXT_ADR instruction to do nothing
+ MOV #NEXT_ADR,PC \ CFA = code of the instruction, PFA = parameter I of the instruction = NEXT_ADR
+ ENDCODE \ this definition 'SPACES' does nothing, for the moment...
- DEFER truc
- :NONAME \ does nothing (for the example)
- DUP
- DROP
- ; IS truc \
+ :NONAME \ starts a FORTH definition without name
+ BEGIN
+ ?DUP
+ WHILE
+ 'SP' EMIT
+ 1-
+ REPEAT
+ ;
+ IS SPACES \ this :NONAME execution_address is stored at PFA of SPACES, replacing NEXT_ADR
-The advantage of creating primary DEFERred words is to set their
-default state, enabling to reinitialize them easily.
-
-CODENNM is the low level equivalent of :NONAME
+The advantage of creating primary DEFERred definitionss is to set their
+default execution subroutine at their BODY address, enabling to reinitialize them easily:
+' truc >BODY IS truc
-to build the primary DEFERred low level definition "machin" :
- -------
+Same with CODENNM definition, as low level equivalent of :NONAME
- DEFER machin
+ CODE TSTBIT \ create a CODE definition named 'TSTBIT' which does a jump to the NEXT_ADR instruction to do nothing
+ MOV #NEXT_ADR,PC \ CFA = instruction, PFA = NEXT_ADR
+ ENDCODE \ this definition 'TSTBIT' does nothing, for the moment...
- CODENNM
- NOP2 \ assembly instruction
- NOP3 \ assembly instruction
- MOV @IP+,PC \ mandatory before ENDCODE
- ENDCODE IS machin
+ CODENNM \ starts an assembly definition without name
+ MOV @PSP+,X
+ AND @X,TOS
+ MOV @IP+,PC
+ ENDCODE \ -- execution_address_of_CODENNM
+ IS TSTBIT \ this CODENNM execution_address is stored at PFA of TSTBIT, replacing NEXT_ADR
you can obviously mix LOW/HIGH levels in CODENNM and :NONAME
-All interpretation/compilation errors now execute ~~`PWR_RET`~~~ `RST_RET`, so any incorrect definition
+All interpretation/compilation errors now execute ~~`PWR_RET`~~ `RST_RET`, so any incorrect definition
and all its source file will be automatically erased.
-Accept SD_Card from 64 MB (FAT16) up to 64 GB (FAT32).
+Accept SD_Card from 4 to 64 GB (FAT32).
Note that Windows 10 no longer offers the FAT32 format for the highest sizes of SD_CARD memory.
So you must use an alternative to do, for example: https://www.partitionwizard.com.
Unlike CamelForth FASTFORTH is a "Direct Threaded Code", with an embedded assembler following the standard syntax,
not the one used in the world Forth.
-Its core is fully compliant with the standard ANS.
-
It is optimized for the speed, especially in the interpreter mode, so that you can load an application program written in FORTH/Assembler faster than its binary via MSP430 Flasher.exe.
Everything can be done from your text editor, the preprocessor and a serial terminal.
### the commands
-With the LOAD" pathame" command FastForth loads source files from a SD_CARD memory.
-
-See "SD_TESTS.f", a FORTH program done for example
+With the `LOAD"` pathame" command FastForth loads source files from a SD_CARD memory.
-If you remove the SD memory card reader and then reset, all SD\_IO pins are available except SD_CD.
-Drive letters are always ignored.
+ * LOAD" path\filename.4th" relative path,
- LOAD" path\filename.4th" relative path,
- LOAD" \path\filename.4th" absolute path.
+ * LOAD" \path\filename.4th" absolute path.
The file is interpreted by FORTH in same manner than from the serial terminal.
When EOF is reached, the file is automatically closed.
-A source file can LOAD" another source file, and so on in the limit of 8 handles.
+A source file can `LOAD"` another source file, and so on in the limit of 8 handles.
+
+`LOAD"` may be used as Change Directory command:
-LOAD" may be used as Change Directory command:
+ * LOAD" \misc". \misc becomes the current folder.
- LOAD" \misc". \misc becomes the current folder.
- LOAD" ..\" parent folder becomes the current folder.
- LOAD" \" Root becomes the current folder.
+ * LOAD" ..\" parent folder becomes the current folder.
+ * LOAD" \" Root becomes the current folder.
- READ" filename.ext" reads a file in current directory,
- READ" \filename.ext" reads a file in root directory.
-The first sector of this file is loaded in BUFFER.
-To read next sectors, use the command READ which loads the next sector in the buffer
-and leaves on the stack a true flag when the EOF is reached.
-The file is automatically closed. See tstwords.4th for basic usage.
+To read a file: `READ"` pathname"
+* open it, the first sector is loaded in SD_BUF
+
+The command `READ` sequentially loads the next sector in the buffer and leaves on the stack a true flag when the EOF is reached.
The variable BufferLen keep the count of bytes to be read (1 to 512).
-If you want to anticipate the end, remove the false flag left by the previous READ then use the CLOSE command.
+The file is automatically closed.
+
+If you want to anticipate the end, remove the false flag left by the previous `READ` then use the `CLOSE` command.
+
+To overwrite a file: `WRITE"` path\filename.ext".
- WRITE" path\filename.ext".
+* If the file does not exist, create it
-If the file does not exist, create it else open it, and set the write pointer at the end of the file,
-ready to append chars.
+* set the write pointer at the **beginning** of the file, ready to append chars.
-The command WRITE writes the buffer and increments the current sector.
+To write a file: `APPEND"` path\filename.ext".
-See example of use in \MSP430-FORTH\SD_TEST.f.
+* If the file does not exist, create it
-To overwrite an existing file:
+* set the write pointer at the **end** of the file, ready to append chars.
- DEL" path\filename.ext" (no error issued),
- WRITE" path\filename.ext".
+The command `WRITE` sequentially writes the SD_BUF in SD_CARD and increments the current sector.
-Use CLOSE to close this file.
+Use `CLOSE` to close a WRITE file.
+See examples of use in \MSP430-FORTH\SD_TEST.f.
#### Copy source file to SD_Card
If the system does not restart again, press `SW1+RESET`.
FORTH restarts in the state of its object file.
-Here is the FastForth memory management, one of its major assets, with both hardware events and software equivalent for COLD and WIPE levels:
+Here is the FastForth memory management, one of its major assets, with both hardware events and software equivalent:
* RST_RET
* when you type `RST_RET` the program beyond the last RST_SET is lost.
- * Running a `MARKER` definition will remove it and the program beyond. In addition the user can link it a routine to remove modified configuration in system: vectors, hardware, IOs...
+ * Running a `MARKER` definition will remove it and the program beyond. In addition the user can link it a routine to remove the modified configuration in system: vectors, hardware, I/Os...
-* WARM level : SYS --> WARM display --> SLEEP.
- * when you type `0 SYS`, FORTH interpreter is restarted without program lost, without WARM display.
-
- * when you type `SYS`, FORTH restarts, the program beyond RST_SET is lost, INIT_FORTH and INIT_HARD_APP (INIT_TERM by default) are executed, the WARM display starts by "#1".
+* WARM level : `SYS` -->(no PUC)--> INIT_FORTH --> INIT_HARD --> WARM display --> ABORT --> ACCEPT --> BACKGRND --> SLEEP.
+
+ * when you type `SYS`, FORTH restarts, the WARM display starts by #0.
- * when you type `+n SYS` (n>0, odd), same effects, the WARM display starts by "#+n".
+ * when you type `+n SYS` (n>0, odd), the WARM display starts by #+n.
-* COLD level : PUC --> `SYS` --> WARM display --> SLEEP.
+ * same effect as RST_RET
- * Power ON : the WARM display starts with the SYSRSTIV value "#2".
+ * words ACCEPT, EMIT, KEY are initialised with their default value,
- * SVSHIFG SVSH event (dropout supply) : the WARM display starts with the SYSRSTIV value: "#14".
+ * TIB is initialised with its default value.
+
- * hardware `RST` : the WARM display starts with the SYSRSTIV value "#4".
+* COLD level : `+n SYS` --> PUC --> INIT_FORTH --> INIT_HARD --> WARM display --> ABORT --> ACCEPT --> BACKGRND --> SLEEP.
+
+ * Power ON : the WARM display starts with the SYSRSTIV value #2.
+
+ * hardware `RST` : the WARM display starts with the SYSRSTIV value #6, because RST pin acts as NMI pin.
+ * SVSHIFG SVSH event (supply dropout) : the WARM display starts with the SYSRSTIV value: #14.
+
* PUC on failure : the WARM display starts with the SYSRSTIV value: #n.
- * `+n SYS` (n>0 and even) is the software RESET : the WARM display starts with the SYSRSTIV value "#+n" (even).
+ * other `+n SYS` (n>0 and even) are software RESET : the WARM display starts with the SYSRSTIV value "#+n" (even).
+
+ * same effects as WARM level, plus:
+
+ * performs a PUC.
+
-* WIPE level : PUC --> `-n SYS` --> WARM display --> SLEEP
+* DEEP RESET level:
- * `-n SYS` (n<0) performs the software Deep Reset:
+ * `-n SYS` (n<0) performs the software Deep Reset, WARM display = #-n.
- * INIT_FORTH and INIT_HARD_APP (INIT_TERM by default) are executed,
- * all programs donwloaded from the terminal or from the SD_Card are lost,
- * the default state of COLD_APP, INI_SOFT_APP, INI_HARD_APP and BACKGND_APP is restored,
- * all "defered" words are initialised with their default value,
- * all interrupts vectors also,
+ * hardware `SW1+RESET`, WARM display = #-1.
+
+ * recompiling FastForth, WARM display = #-3.
+
+ * same effects as COLD level, plus:
+
+ * all programs donwloaded from the TERMINAL or from the SD_CARD are lost,
+
+ * COLD_APP, SOFT_APP, HARD_APP and BACKGND_APP default values are restored,
+
+ * all interrupts vectors are initialised with their default value,
+
* SIGNATURES area is FFh full filled.
- * WARM display = #-n.
- * hardware `SW1+RESET` does same effects, WARM display = #-1.
-
- * recompiling FastForth, too, WARM display = #-3.
-* ERROR : ABORT" --> ABORT" display --> SLEEP.
+* ERROR : ABORT" your_text" --> INIT_FORTH --> display = "your_text" --> ABORT --> ACCEPT --> BACKGRND --> SLEEP.
- * when an error occurs, FASTFORTH discards the end of current downloading if any, does same as `SYS` then displays the error message. In this way, any error is followed by the complete erasure of the bad defined word causing this error, and also by discarding the end of downloading of the source file including it.
+ * when an error occurs, FASTFORTH discards the end of current downloading if any. In this way, any error is followed by the complete erasure of the bad defined word causing this error, and also by discarding the end of downloading of the source file including it.
- * It is strongly recommended to end any source file with `RST_SET` to protect it program from any subsequent error.
+Once validate, it is strongly recommended to end any source file with `RST_SET` to protect the resulting program from a subsequent download error.
+As all other FORTH words, `RST_SET` `RST_RET` and` MARKER` definitions may be freely used in compiling mode.
-As all other words FORTH, RST_SET RST_RET and MARKER definitions may be freely used in compiling mode.
+If you have previously set `NOECHO`, there is no WARM display.
-If you have previously set 'NOECHO', there is no WARM, COLD, WIPE display.
+If you don't want to display an ABORT" message, type: `ABORT" "`
-With I2C_FastForth version, WARM display is preceded by the decimal I2C slave address, example: `@18`.
+With I2C_FastForth version, WARM and `ABORT"` displays are preceded by the decimal I2C slave address, example: `@18`.
## VOCABULARY ADD-ON
The CONTEXT stack is 8 word_set sized.
-after typing: WORDSET TRUC \ a new word-set called TRUC is created
+after typing: `WORDSET TRUC` a new word-set called TRUC is created, then:
- TRUC adds the word-set TRUC first in the CONTEXT stack, the interpreter search existing definitions first in TRUC
- PREVIOUS removes TRUC from CONTEXT
+* `TRUC` adds the word-set TRUC first in the CONTEXT stack, the interpreter search existing definitions first in TRUC
- DEFINITIONS adds news definitions in the first word-set in the CONTEXT stack, i.e. TRUC,
- PREVIOUS removes TRUC from CONTEXT but new definitions are still added in TRUC
- DEFINITIONS new definitions are added into the previous first word-set in the CONTEXT stack,
- after `-1 SYS`: the FORTH word-set.
+* `DEFINITIONS` adds news definitions in the first word-set in the CONTEXT stack, i.e. TRUC,
+* `PREVIOUS` removes TRUC from CONTEXT but new definitions are still added in TRUC
+* `DEFINITIONS` new definitions are added into the previous first word-set in the CONTEXT stack,
+* after `-1 SYS`, FORTH is the CONTEXT and the CURRENT word-set.
## EMBEDDED ASSEMBLER
### HOW TO MIX assembly and FORTH ?
-FAST FORTH knows three kinds of definitions :
+FAST FORTH knows two modes of definitions :
* high level FORTH definitions `: <name> ... ;`
-* low level definitions `CODE <name> ... ENDCODE`
+* assembly low level definitions `CODE <name> ... ENDCODE`
+
+there is also some variations of these two modes :
+
+* high level definitions `NONAME: ... ;`
-* low level hidden definitions `HDNCODE <name> ... ENDCODE` which are deliberately hidden because they are not executable by FORTH.
+* low level definitions `CODENNM ... ENDCODE`, low-level equivalent of `NONAME:`
+
+* low level definitions `HDNCODE <name> ... ENDCODE`, these definitions are 'hidden' and can be accessed only from assembly level.
Examples:
ENDCODE
- HDNCODE WDT_INT \ low level hidden definition "WDT_INT" (Watchdog interrupt)
- BIT #8,&TERM_STATW \ break (ALT+b) sent by TERMINAL ?
- 0<> IF \ if yes
- MOV #ABORT,PC \ continue with ABORT (no return)
+ HDNCODE WDT_INT \ low level hidden definition "WDT_INT" (Watchdog interrupt)
+ BIT #8,&TERM_STATW \ break (ALT+b) sent by TERMINAL ?
+ 0<> IF \ if yes
+ MOV #ABORT,PC \ continue with ABORT (no return)
THEN
- \ else return to background task SLEEP
- MOV @RSP+,SR \ restore SR flags
- BIC #%0111_1000,SR \ but force CPU Active Mode, disable all interrupts
- RET \ (instead of RETI)
+ \ else return to background task SLEEP
+ BIC #%0111_1000,0(RSP) \ force CPU Active Mode, disable all interrupts
+ RETI \
ENDCODE
At the end of low level CODE definition, the instruction MOV @IP+,PC jumps to the next definition.
This faster (4 cycles) and shorter (one word) instruction replaces the famous pair of assembly
-instructions : CALL #LABEL ... RET (4+4 cycles, 2+1 words). The register IP is the Interpretative Pointer.
+instructions : CALL #LABEL ... RET (4+4 cycles, 2+1 words).
+The register IP is the Interpretative Pointer.
High level FORTH definitions starts with a boot code "DOCOL" which saves the IP pointer and loads it with the first address
of a list of execution addresses, then performs a postincrement branch to the first one.
and the one of the high level word NOOP :
header \ compiled by the word :
- execution addr
- DOCOL PUSH IP \ boot code "DOCOL"...
+ execution addr PUSH IP \ boot code "DOCOL"...
CALL rDOCOL \ ...compiled by the word :
addr of DUP \ execution addr of DUP
addr of DROP \ execution addr of DROP
REGISTERS correspondence (you can freely use ASM or TI or FASTFORTH registers's names).
- ASM TI FASTFORTH comment
+ REG TI FASTFORTH comment
R0 PC PC Program Counter
R1 SP RSP Return Stack Pointer
`MOV @X+,rDOCON`
`MOV @X,rDOVAR`
-(Search `INIT_DOXXX` in your \inc\device.pat)
+(Search `INIT_DOXXX` in \inc\MSP430xxxx.pat)
If you want to restore only rDODOES, rDOCON and rDOVAR:
`MOV #XDODOES,rDODOES`
`MOV #XDOCON,rDOCON`
-When you use these registers you can't call any FORTH words created by them at the same time!
+When you use these registers you can't call any FORTH words using them at the same time!
don't use R3 and use R2 (SR) only with BIC, BIT, BIS instructions in register mode.
The bits 0-11 of SR register are saved by interrupts and restored by the instruction RETI.
you can use freely UF9 UF10 and UF11 as SR bits 9-11.
-FastForth uses UF9 for double numbers interpreting.
+FastForth uses UF9 for double numbers interpreting and also by TO ... VALUE.
**PARAMETERS STACK**
SUB #2,PSP \ insert a empty 2th cell
MOV TOS,0(PSP) \ fill this 2th cell with first cell
- MOV <what you want>,TOS \ MOV or MOV.B <what you want>,TOS ; i.e. update first cell
+ MOV(.B) <what you want>,TOS \ i.e. update first cell
to pop one cell from the PSP stack :
RETURN-STACK-CELLS = 48 max size of the return stack, in cells
STACK-CELLS = 48 max size of the data stack, in cells
- /COUNTED-STRING = 255 max size of a counted string, in characters
+ /COUNTED-STRING = 255 max size of a counted string, in characters
/HOLD = 34 size of the pictured numeric output string buffer, in characters
/PAD = 84 size of the scratch area pointed to by PAD, in characters
ADDRESS-UNIT-BITS = 16 size of one address unit, in bits
- FLOORED = true true if floored division is the default
+ FLOORED = true true if floored division is the default
MAX-CHAR = 255 max value of any character in the implementation-defined character set
MAX-N = 32767 largest usable signed integer
MAX-U = 65535 largest usable unsigned integer
- MAX-D = 2147483647 largest usable signed double number
+ MAX-D = 2147483647 largest usable signed double number
MAX-UD = 4294967295 largest usable unsigned double number
DeFiNiTiOnS aRe CaSe-InSeNsItIvE they are compiled in their CAPS_ON form.
Words ACCEPT KEY EMIT are DEFERred definitions. ACCEPT doesn't use KEY.
RST_SET defines the bound of the program memory protected against any PUC.
- RST_RET removes all words defined after RST_SET
+ RST_RET removes all words defined after RST_SET.
HI2LO used to switch compilation from high level (FORTH) to low level (assembler).
CODENNM the assembler counterpart of :NONAME.
CODE <name> creates a definition written in assembler.
this defined <name> must be ended with ENDCODE unless COLON or LO2HI use.
- HDNCODE <name> creates a word same as CODE but in the hidden word-set to be visible only in the assembly mode.
+ HDNCODE <name> same as CODE but the definition is in the hidden word-set to be visible only in the assembly mode.
NOECHO disables display on the TERMINAL
ECHO enables display on the TERMINAL
- SYS 0 SYS | SYS restarts the interpreter,
- +n (odd) SYS initializes the hardware and restarts the FORTH engine,
- +n (even) SYS does software RESET, initializes the hardware and restarts the FORTH engine,
+ SYS 0 SYS | SYS executes WARM
+ +n (odd) SYS same,
+ +n (even) SYS does software RESET then executes WARM
-n SYS same as +n (even) SYS, plus resets the program memory to its original state.
-### Other words/addresses which are usable in any generic source_files.f
-
-**All constants, variables and definitions included in \inc\device.pat and \inc\target.pat files are usable by
-the assembler and also by the FORTH interpreter (except the definitions).**
-
- see definitions in forthMSP430FR.asm:
- SLEEP ASM CODE_WITHOUT_RETURN: CPU shutdown
- LIT CODE compiled by LITERAL
- XSQUOTE CODE compiled by S" and S_
- HEREXEC CODE HERE and BEGIN execute address
- QFBRAN CODE compiled by IF UNTIL
- BRAN CODE compiled by ELSE REPEAT AGAIN
- NEXT_ADR CODE NEXT instruction (MOV @IP+,PC)
- MUSMOD ASM 32/16 unsigned division, used by ?NUMBER, UM/MOD
- MDIV1DIV2 ASM input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
- MDIV1 ASM input for 48/16 unsigned division, see DOUBLE M*/
- RET_ADR ASM RET address,
- SETIB CODE Set Input Buffer with org & len values, reset >IN pointer
- REFILL CODE accept one line from input and leave org len of input buffer
- CIB_ORG Current Input Buffer address, default value: TIB_ORG; may be redirected to SDIB_ORG
- XDODOES to restore rDODOES: `MOV #XDODOES,rDODOES`
- XDOCON to restore rDOCON: `MOV #XDOCON,rDOCON`
- XDOVAR to restore rDOVAR: `MOV #XDOVAR,rDOVAR`
- to restore rDOCOL: `MOV &INIT_DOCOL,rDOCOL`
- INIT_FORTH CODE_WITHOUT_RETURN, common part of SYS and QABORT, starts FORTH engine
- QABORT CODE_WITHOUT_RETURN, run-time part of ABORT"
- ABORT ABORT address
- QUIT QUIT address
-
- see definitions in forthMSP430FR_TERM_UART.asm:
- ABORT_TERM CODE_WITHOUT_RETURN, called by QABORT, QREVEAL and INTERPRET
- UART_WARM
- UART_INIT_TERM ASM CODE, content of UART_WARM+2 by default
- UART_COLD_TERM ASM CODE, content of UART_COLD+2 by default
- UART_INIT_SOFT ASM CODE, content of INIT_FORTH+2 by default = RET address
- UART_RXON ASM CODE, content of SLEEP+2 by default
- UART_RXOFF ASM CODE, called by ACCEPT
-
- see definitions in forthMSP430FR_TERM_I2C.asm:
- ABORT_TERM CODE_WITHOUT_RETURN, called by QABORT, QREVEAL and INTERPRET
- I2C_WARM
- I2C_INIT_TERM ASM CODE, content of I2C_WARM+2 by default
- I2C_COLD_TERM ASM CODE, content of I2C_COLD+2 by default = RET address
- I2C_INIT_SOFT ASM CODE, content of INIT_FORTH+2 by default = RET address
- I2C_RXON ASM CODE, content of SLEEP+2 by default
- I2C_CTRL_CH ASM CODE, used as is: MOV.B #CTRL_CHAR,Y
- CALL #I2C_CTRL_CH
+### Other constants/addresses which are usable in any generic source_files.f
+
+**All constants, variables and definitions included in \inc\any.pat files are usable by
+the assembler and also by the FORTH interpreter.**
## MSP430ASSEMBLER word-set (in the hidden word-set)
### SD_CARD_READ_WRITE ADD-ON
-TERM2SD",
-SD_EMIT,
-WRITE,
-READ,
-CLOSE,
-DEL",
-WRITE",
-APPEND",
-READ".
-
- TERM2SD" TERM2SD" SD_TEST.4TH" copy input file to SD_CARD
- (use CopySourceFileToTarget_SD_Card.bat to do)
- SD_EMIT sends output stream at the end of last opened as write file.
+ TERM2SD" TERM2SD" SD_TEST.4TH" copy SD_TEST.4TH file to SD_CARD (use CopySourceFileToTarget_SD_Card.bat to do)
WRITE write sequentially the content of SD_buf to a file
READ read sequentially a file in SD_buf, leave a flag, false when the file is automatically closed.
CLOSE close last opened file.
- DEL" DEL" SD_TEST.4TH" remove this file from SD_CARD.
- WRITE" WRITE" TRUC" create or overwrite a file TRUC ready to write to its beginning.
- APPEND" APPEND" TRUC" open or create a file TRUC ready to write to the end of this file
- READ" READ" TRUC" open TRUC and load its first sector in SD_buf
+ DEL" TRUC" remove the file TRUC from SD_CARD.
+ WRITE" TRUC" create or overwrite a file TRUC ready to write to its beginning.
+ APPEND" TRUC" open or create a file TRUC ready to write to the end of this file
+ READ" TRUC" open TRUC and load its first sector in SD_buf
+ WR_SECT Write SD_BUF in Sector loaded in W=lo:X=hi
+ RD_SECT load Sector W=lo:X=hi into SD_BUF, set BufferPtr=0
## OPTIONNAL ADD-ON
# Documentation at http://www.scintilla.org/SciTEDoc.html\r
\r
# # Globals\r
-# \r
+#\r
# PLAT_WIN=1\r
# PLAT_GTK=0\r
# position.maximize=1\r
-# \r
+#\r
# save.session=1\r
# save.recent=1\r
# save.session=1\r
# session.bookmarks=1\r
-# \r
+#\r
# buffers.zorder.switching=1\r
# properties.directory.enable=1\r
# check.if.already.open=1\r
\r
\r
-# \r
+#\r
# # Window sizes and visibility\r
# if PLAT_WIN\r
# position.left=-1\r
# if PLAT_GTK\r
# position.left=5\r
# position.top=22\r
-# \r
+#\r
# position.width=1000\r
# position.height=768\r
# position.maximize=1\r
# #fileselector.show.hidden=1\r
# magnification=0\r
# output.magnification=-4\r
-# \r
+#\r
# # Sizes and visibility in edit pane\r
# line.margin.visible=1\r
# line.margin.width=4\r
\r
\r
# #Element styles\r
-# \r
+#\r
# #view.eol=1\r
-# #control.char.symbol=. \r
+# #control.char.symbol=.\r
# caret.period=500\r
# view.whitespace=0\r
# view.indentation.whitespace=1\r
# caret.line.back=#222222\r
# calltip.back=#FFF0FE\r
\r
-edge.column=80\r
+edge.column=84\r
edge.mode=1\r
edge.colour=#404040\r
\r
#find.mark=#0000FF\r
#highlight.current.word=1\r
#highlight.current.word.by.style=1\r
-#highlight.current.word.colour=#00D040\r
+#highlight.current.word.colour=#00D040 \r
#indicators.alpha=63\r
#indicators.under=1\r
\r
$(FileNameExt) : $(FileDate) \97 $(FileTime) | $(FileAttr)\r
\r
if PLAT_WIN\r
- command.scite.help=C:\Program Files\SRWare Iron\iron.exe "C:\Program Files\SciTE\SciTEDoc.html"\r
+ command.scite.help=C:\Users\JeanMi\AppData\Local\Yandex\YandexBrowser\Application\browser.exe --allow-file-access --allow-file-access-from-files "https://www.scintilla.org/SciTEDoc.html"\r
command.scite.help.subsystem=2\r
if PLAT_GTK\r
command.print.*=a2ps "$(FileNameExt)"\r
command.scite.help=xdg-open "file://$(SciteDefaultHome)/SciTEDoc.html"\r
- \r
+\r
# # Internationalisation\r
# # Japanese input code page 932 and ShiftJIS character set 128\r
# #code.page=932\r
#Prev File|IDM_PREVFILE|\r
\r
#if PLAT_WIN\r
-import A:\projets\msp430\config\asm\r
-import A:\projets\msp430\config\forth\r
-import A:\projets\msp430\config\fortran\r
-import A:\projets\msp430\config\hex\r
-import A:\projets\msp430\config\others\r
-import Z:\config\asm\r
-import Z:\config\forth\r
-import Z:\config\fortran\r
-import Z:\config\hex\r
-import Z:\config\others\r
+import .\config\asm\r
+import .\config\forth\r
+import .\config\fortran\r
+import .\config\hex\r
+import .\config\others\r
\r
#if PLAT_GTK\r
import /home/thoorens/CloudStation/projets/msp430/config/asm\r
@1800
-80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A0 19
-CA C6 7E C5 84 C5 54 C5 3A C7 28 D7 E0 CF 9A CF
-9A CF B0 C6 6E C7 36 C7 3C 21 E0 20 8E C9 B6 C4
-C4 C4 AA C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5
-3A C7 28 D7 E0 CF 9A CF 9A CF 00 00 00 00 00 00
+80 3E 08 00 A1 F7 18 00 FD FF 90 01 10 00 A8 19
+CC C6 6A C5 70 C5 44 C5 2A C7 0E D7 D8 CF 96 CF
+96 CF 98 C6 5E C7 26 C7 3C 21 E0 20 4C C9 A0 C4
+AE C4 8C C8 20 00 0A 00 00 20 6A C5 70 C5 44 C5
+2A C7 0E D7 D8 CF 96 CF 96 CF 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00
@C400
-92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00
-3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82
-8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63
-30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E
-1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20
-05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69
-08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B
-12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00
-0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21
-3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40
-3C 21 00 00 AF 4F FE FF 2F 83 00 3D 0E 93 3E 4F
-95 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12
-3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D
-92 12 3C 18 3D 41 39 40 22 18 B2 49 AE C6 B2 49
-6C C7 B2 49 34 C7 B2 49 A0 C4 31 49 34 49 35 49
-36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20
-82 43 BC 21 30 40 54 D0 8F 93 02 00 02 20 2F 52
-BF 3F B0 12 3A C7 92 C3 1C 05 18 42 00 18 39 40
-41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23
-B0 12 D0 C4 B4 C8 AC C4 52 C5 7C C7 1E C4 04 1B
-5B 37 6D 00 9E C7 9E C7 1E C4 04 1B 5B 30 6D 00
-9E C7 EA CC B0 12 7E C5 B2 40 81 00 00 05 92 42
-02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02
-92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3
-0A 05 FD 23 30 41 92 12 3E 18 84 12 7C C7 1E C4
-07 0D 0A 1B 5B 37 6D 23 9E C7 02 CA 1E C4 19 46
-61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68
-6F 6F 72 65 6E 73 2C 20 9E C7 0A C4 40 FF 32 C4
-CA C8 CE C9 1E C4 0A 62 79 74 65 73 20 66 72 65
-65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38
-02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E
-08 18 92 12 3A 18 F2 B0 10 00 00 02 02 20 B2 43
-08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0
-10 00 00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40
-E0 20 B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3
-26 02 F2 40 FD 00 22 02 E2 D2 24 02 F2 40 A5 00
-A1 01 F2 40 10 00 A0 01 D2 43 A1 01 B2 40 00 A5
-60 01 B2 D0 10 00 86 01 B2 40 00 02 88 01 F2 C3
-82 01 F2 D0 0A 00 82 01 B2 40 E8 01 84 01 39 40
-80 00 18 42 00 18 18 83 FE 23 19 83 FA 23 39 40
-00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 1E 42
-08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 C4
-86 C5 00 00 0C 41 43 43 45 50 54 00 30 40 B0 C6
-08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40
-0E C7 3C 40 1A C7 5D 15 9B 3E 21 52 3A 17 58 42
-0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 13 00
-0E 05 E2 D2 22 02 30 41 48 9C 06 2C 78 92 11 20
+2F 83 8F 4E 00 00 3E 4D 30 4D 8F 4E FE FF AF 4F
+FC FF 2F 82 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00
+0D 5E 1D B3 0D 63 30 4D 0B 4E 1C 4F 02 00 2E 4F
+0A 43 35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43
+09 43 0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30
+0C 5C 0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40
+A0 C4 8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 43
+BE 21 B2 4F BC 21 82 4E BA 21 3E 4F 30 4D 2F 82
+8F 4E 02 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F
+FE FF 2F 83 FF 3C 0E 93 3E 4F 99 21 2D 4D 30 4D
+2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E 30 4D 2F 83
+8F 4E 00 00 3E 41 2E 4E 30 4D 3D 41 39 40 22 18
+B2 49 96 C6 B2 49 5C C7 B2 49 24 C7 B2 49 8A C4
+31 49 34 49 35 49 36 49 37 49 B2 49 B8 21 B2 49
+B6 21 B2 49 00 20 82 43 B4 21 92 12 3C 18 30 40
+96 D0 8F 93 02 00 02 20 2F 52 BF 3F 30 12 20 C5
+B0 12 2A C7 92 C3 1C 05 18 42 00 18 39 40 41 00
+19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 30 41
+B0 12 BA C4 96 C8 96 C4 42 C5 6C C7 14 C4 04 1B
+5B 37 6D 00 8E C7 8E C7 14 C4 04 1B 5B 30 6D 00
+8E C7 C0 CC B2 40 81 00 00 05 92 42 02 18 06 05
+92 42 04 18 08 05 F2 D0 30 00 0A 02 92 C3 00 05
+92 D3 1A 05 92 C3 30 01 30 41 92 B3 0A 05 FD 23
+30 41 92 12 3E 18 84 12 6C C7 14 C4 07 0D 0A 1B
+5B 37 6D 23 8E C7 C4 C9 14 C4 19 46 61 73 74 46
+6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65
+6E 73 2C 20 8E C7 00 C4 40 FF 46 D5 9E C8 90 C9
+14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 9C C4
+36 C5 00 00 06 53 59 53 92 12 3A 18 0E 93 06 38
+02 24 1E B3 03 24 B0 12 BA C4 72 C5 82 4E 08 18
+F2 B0 10 00 00 02 02 20 B2 43 08 18 B2 40 04 A5
+20 01 92 D3 04 01 B2 D0 10 00 00 01 B2 40 80 5A
+CC 01 3F 40 80 20 31 40 E0 20 B2 43 02 02 B2 D3
+06 02 D2 43 24 02 F2 D3 26 02 F2 40 FD 00 22 02
+E2 D2 24 02 F2 40 A5 00 A1 01 F2 40 10 00 A0 01
+D2 43 A1 01 B2 40 00 A5 60 01 B2 D0 10 00 86 01
+B2 40 00 02 88 01 F2 C3 82 01 F2 D0 0A 00 82 01
+B2 40 E8 01 84 01 39 40 80 00 18 42 00 18 18 83
+FE 23 19 83 FA 23 39 40 00 10 29 83 89 43 00 20
+FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 3E B3
+01 20 0E 49 B0 12 BA C4 72 C5 00 00 0C 41 43 43
+45 50 54 00 30 40 98 C6 08 4E 2E 4F 08 5E 39 40
+0D 00 3A 40 20 00 3B 40 FE C6 3C 40 0A C7 5D 15
+92 12 40 18 12 D2 06 18 FB 3F A2 B3 1C 05 FD 27
+B2 40 13 00 0E 05 E2 D2 22 02 30 41 21 52 3A 17
+58 42 0C 05 48 9C 08 2C 48 9B EF 27 78 92 11 20
2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00
-1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D 10 C7
-2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 92 B3
-1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 06 4B
-45 59 30 40 36 C7 30 12 4C C7 A2 B3 1C 05 FD 27
+1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D 00 C7
+2D 83 92 B3 1C 05 E4 23 FC 3F 92 B3 1C 05 FD 27
+58 42 0C 05 3E 8F 3D 41 48 4C EB 3F 00 00 06 4B
+45 59 30 40 26 C7 30 12 3C C7 A2 B3 1C 05 FD 27
B2 40 11 00 0E 05 E2 C2 22 02 30 41 2F 83 8F 4E
-00 00 92 B3 1C 05 FD 27 B0 12 D6 C6 1E 42 0C 05
-30 4D 00 00 08 45 4D 49 54 00 30 40 6E C7 08 4E
-3E 4F C7 3F 64 C7 08 45 43 48 4F 00 B2 40 C2 48
-08 C7 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40
-30 4D 08 C7 30 4D 00 00 08 54 59 50 45 00 0D 12
-3D 40 AE C7 29 4F 8F 4E 00 00 7E 49 DE 3F B0 C7
-2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D
-86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 71 22
-F9 98 00 00 6E 22 19 53 1C 83 FA 23 2D 53 30 4D
-2F 53 3E 4F 1E 83 65 22 9B 24 2E C7 0D 5B 45 4C
-53 45 5D 00 0D 12 84 12 0A C4 00 00 CE C8 C0 C7
-12 CA CC CC B0 C4 3C C8 14 C4 06 5B 54 48 45 4E
-5D 00 C4 C7 1A C8 E0 C7 FE C7 14 C4 06 5B 45 4C
-53 45 5D 00 C4 C7 2C C8 E0 C7 FC C7 1E C4 04 5B
-49 46 5D 00 C4 C7 FE C7 B2 C4 FC C7 1E C4 05 0D
-6B 6F 20 0A 9E C7 9A C4 84 C4 B2 C4 FE C7 EC C7
-0D 5B 54 48 45 4E 5D 00 30 4D 50 C8 09 5B 49 46
-5D 00 0E 93 3E 4F C6 27 30 4D 5C C8 13 5B 44 45
-46 49 4E 45 44 5D 0D 12 84 12 C0 C7 12 CA 7A CA
-1E CC 8E C9 6C C8 17 5B 55 4E 44 45 46 49 4E 45
-44 5D 0D 12 84 12 C0 C7 12 CA 7A CA 9E C8 3D 41
-2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00
-3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF
-3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53
-30 4D 00 00 02 40 2E 4E 30 4D A4 C6 02 21 BE 4F
-00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F
-01 28 0E F3 30 4D D8 C5 05 53 22 00 82 43 C0 21
-0D 12 84 12 0A C4 1E C4 7C CC 0A C4 22 00 12 CA
-12 C9 B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21
-3E 4F 3D 41 30 4D 86 C7 05 2E 22 00 0D 12 84 12
-FC C8 0A C4 9E C7 7C CC 8E C9 00 00 04 3C 23 00
-B2 40 B2 21 B2 21 30 4D F8 C8 02 23 1B 42 BE 21
-2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 7A 90 0A 00
-02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42
-B2 21 C8 4A 00 00 30 4D 4A C9 04 23 53 00 0D 12
-84 12 4C C9 86 C9 2D 83 09 DE 09 93 E1 23 3D 41
-30 4D 7A C9 04 23 3E 00 9F 42 B2 21 00 00 3E 40
-B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E
-3E 4F DB 3F 94 C9 08 53 49 47 4E 00 0E 93 3E 4F
-7A 40 2D 00 D2 33 30 4D 76 C7 04 55 2E 00 0C 43
-2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3
-00 00 3E E3 9F 53 00 00 0E 63 84 12 40 C9 C0 C7
-AE C9 7E C9 AA C8 BC C9 98 C9 9E C7 8E C9 28 C9
-02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52
-44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C
-09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90
-27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C
-00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90
-61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82
-C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00
-30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40
-CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00
-08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E
-78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23
-1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3
-01 20 1E 83 8F 4C 00 00 30 4D 00 CA 0E 3E 4E 55
-4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82
-82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00
-12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04
-82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63
-1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49
-04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43
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@FF80
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-77 00 10 00 12 00 14 00 16 00 00 00 FA 45 FA 45
-FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45
-FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45
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-FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 0E 46
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+D8 45 D8 45 D8 45 D8 45 D8 45 D8 45 B4 46 D8 45
+D8 45 D8 45 D8 45 D8 45 D8 45 D8 45 D8 45 E8 45
q
@set PortCOM=%2
-@if 1%PortCOM% == 1 CALL %~d1\config\Select.bat SelectPortCOM
+@if 1%PortCOM% == 1 CALL %~dp1..\config\Select.bat SelectPortCOM
-@%~d1\prog\BSL-Scripter.exe --log --quiet --initComm [INVOKE,%PortCOM%,UART,9600,PARITY] --device FRxx --erase ERASE_ALL --exit [RESET]
-@%~d1\prog\BSL-Scripter.exe --log --initComm [INVOKE,%PortCOM%,UART,9600,PARITY] --device FRxx --speed FAST --bslPwd %~dp1binaries\pass32_default.txt -w %~dp1binaries\%~nx1 --exit [RESET]
+@%~dp1..\prog\BSL-Scripter.exe --log --quiet --initComm [INVOKE,%PortCOM%,UART,9600,PARITY] --device FRxx --erase ERASE_ALL --exit [RESET]
+@%~dp1..\prog\BSL-Scripter.exe --log --initComm [INVOKE,%PortCOM%,UART,9600,PARITY] --device FRxx --speed FAST --bslPwd %~dp1binaries\pass32_default.txt -w %~dp1binaries\%~nx1 --exit [RESET]
@pause
:send4th
-start %~d1\config\SendSource.bat %1 NOECHO
+start %~dp1..\config\SendSource.bat %1 NOECHO
::PAUSE > NUL
exit
:sendF
-call %~d1\config\Select.bat SelectTemplate
+call %~dp1..\config\Select.bat SelectTemplate
-@start %~d1\config\CopyTo_SD_Card.bat %1 %~dp1inc\%template% %2
+@start %~dp1..\config\CopyTo_SD_Card.bat %1 %~dp1..\inc\%template% %2
::PAUSE > NUL
exit
:preprocessF
@%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~dp1..\inc\%~n2.pat %~dpn1.f %~dpn1.4TH
-@call %~d1\config\Select.bat SelectDeviceId %~dp1..\inc\%~n2.pat
+@call %~dp1..\config\Select.bat SelectDeviceId %~dp1..\inc\%~n2.pat
:DownloadF
@taskkill /F /IM ttermpro.exe 1> NUL 2>&1
:win32F
-@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\SendToSD.ttl %~dpn1.4TH /C %deviceid% 1> NUL 2>&1
+@"C:\Program Files\teraterm\ttpmacro.exe" /V %~dp1..\config\SendToSD.ttl %~dpn1.4TH /C %deviceid% 1> NUL 2>&1
@IF NOT ERRORLEVEL 1 GOTO EndF
:win64F
-@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\SendToSD.ttl %~dpn1.4TH /C %deviceid%
+@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~dp1..\config\SendToSD.ttl %~dpn1.4TH /C %deviceid%
:EndF
MOVE "%~dpn1.4TH" "%~dp1\LAST.4TH" > NUL
::@echo off
-@if F%1==F (
- @echo no file to do that!
+set target=%~n1
+IF EXIST config\Select.bat (
+:: used by scite commands Ctrl+1 or Ctrl+4
+ call config\Select.bat SelectDevice %%target%%
+ IF EXIST %~dp1binaries\%~n1.txt (
+ call %~dp1prog\msp430flasher -s -m SBW2 -u -n %%device%% -v -w %~dp1binaries\%~n1.txt -z [RESET,VCC]
+ ) else (
+:: hex files generate error 60: verify error
+ IF EXIST %~dp1binaries\%~n1.hex (
+ call %~dp1prog\msp430flasher -s -m SBW2 -u -n %%device%% -v -w %~dp1binaries\%~n1.hex -z [RESET,VCC]
+ )
+ )
) else (
- @call %~d1\config\Select.bat SelectDevice %1
- @IF EXIST %~dp1binaries\%~n1.txt GOTO progtxt
- @IF EXIST %~dp1binaries\%~n1.hex GOTO proghex
+ IF EXIST %~dp1..\config\Select.bat (
+:: used by drag n drop on \binaries\FET_prog.bat
+ call %~dp1..\config\Select.bat SelectDevice %%target%%
+ IF EXIST %~n1.txt (
+ call %~dp1..\prog\msp430flasher -s -m SBW2 -u -n %%device%% -v -w %~n1.txt -z [RESET,VCC]
+ ) else (
+:: hex files generate error 60: verify error
+ IF EXIST %~n1.hex (
+ call %~dp1..\prog\msp430flasher -s -m SBW2 -u -n %%device%% -v -w %~n1.hex -z [RESET,VCC]
+ )
+ )
+ )
)
+::pause
@exit
-:progtxt
-%~d1\prog\msp430flasher -s -m SBW2 -u -n %device% -v -w %~dp1binaries\%~n1.txt -z [RESET,VCC]
-@exit
-
-:proghex
-%~d1\prog\msp430flasher -s -m SBW2 -u -n %device% -v -w %~dp1binaries\%~n1.hex -z [RESET,VCC]
-@exit
-
-:: your git copy must be the root of a virtual drive
-
:: %n1 = filename of file to flash
-:: %nx1 = filename.ext of file to flash
:: -s : force update
:: -m : select SBW2 mode
:: -u : Unlocks locked flash memory (INFOA) for writing.
+++ /dev/null
-@1800
-80 3E 12 00 00 00 F8 00 00 00 35 01 10 00 E0 43
-56 41 B8 5C 44 41 76 5B DC 42 1A 4C 96 65 62 4C
-CA 42 4E 43 2A 43 3C 1D E0 1C E2 45 B6 40 C4 40
-F8 44 20 00 0A 00 00 1C 1A 4C 1A 4C 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
-q
::Preprocess.bat
::used by PreprocessSourceFile.bat or by scite editor Tools menu
-@ECHO OFF
+::@ECHO OFF
::echo %2
::echo %~dp1..\inc\%~n2.pat
:preprocess
-%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~dp1..\inc\%~n2.pat %~dpn1.f %~dp1LAST.4TH
-
-call %~d1\config\Select.bat SelectDevice %~dp1..\inc\%~n2.pat
+%~dp1..\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~dp1..\inc\%~n2.pat %~dpn1.f %~dp1LAST.4TH
+set target=%~n2
+call %~dp1..\config\Select.bat SelectDevice %%target%%
if not exist %~dp1SD_%device:~3% MD %~dp1SD_%device:~3% > NUL
COPY /y %~dp1LAST.4TH %~dp1SD_%device:~3%\%~n1.4TH > NUL
+::pause
exit
:: %~dpn1.f is the symbolic source file
-:: %~d1\inc\%~n2.pat is the pattern file for preprocessor gema.exe
+:: %~dp1..\inc\%~n2.pat is the pattern file for preprocessor gema.exe
:: %~dp1LAST.4TH is the output source file (ready to send to the target)
:: %~d1 is the drive of arg %1
:: %~n2 is your selected template by SelectTarget.bat or your scite $(1)
::PreProcessSourceFile.bat
::used as link in any folder to drag and drop file.f on it.
-::@call SelectTarget.bat
-@call %~d1\config\Select.bat SelectTemplate
-@start %~d1\config\Preprocess.bat %1 %~dp1..\inc\%template% %2
-exit
+
:: %1 is file.f to be preprocessed
-:: %2 is used by Preprocess.bat as an unexpected third parameter
+:: %2 is used by Preprocess.bat as error : "unexpected third parameter"
+
+call ..\config\Select.bat SelectTemplate
+call ..\config\Preprocess.bat %1 ..\inc\%template% %2
+pause
+exit
@exit /b
:SelectDevice
-::%1 = "SelectDevice"
-::%2 = file.pat name
-
-@set device=%~n2
-@if /I %device:~0,16% == MSP_EXP430FR5739 set device=MSP430FR5739
-@if /I %device:~0,16% == MSP_EXP430FR5969 set device=MSP430FR5969
-@if /I %device:~0,16% == MSP_EXP430FR5994 set device=MSP430FR5994
-@if /I %device:~0,16% == MSP_EXP430FR6989 set device=MSP430FR6989
-@if /I %device:~0,16% == MSP_EXP430FR4133 set device=MSP430FR4133
-@if /I %device:~0,16% == MSP_EXP430FR2433 set device=MSP430FR2433
-@if /I %device:~0,16% == CHIPSTICK_FR2433 set device=MSP430FR2433
-@if /I %device:~0,16% == MSP_EXP430FR2355 set device=MSP430FR2355
-@if /I %device:~0,15% == LP_EXP430FR2476 set device=MSP430FR2476
+:: fonction called by FET_prog.bat and preprocess.bat with variable %target%
+@if /I %target:~0,16% == MSP_EXP430FR5739 set device=MSP430FR5739
+@if /I %target:~0,16% == MSP_EXP430FR5969 set device=MSP430FR5969
+@if /I %target:~0,16% == MSP_EXP430FR5994 set device=MSP430FR5994
+@if /I %target:~0,16% == MSP_EXP430FR6989 set device=MSP430FR6989
+@if /I %target:~0,16% == MSP_EXP430FR4133 set device=MSP430FR4133
+@if /I %target:~0,16% == MSP_EXP430FR2433 set device=MSP430FR2433
+@if /I %target:~0,16% == CHIPSTICK_FR2433 set device=MSP430FR2433
+@if /I %target:~0,16% == MSP_EXP430FR2355 set device=MSP430FR2355
+@if /I %target:~0,15% == LP_MSP430FR2476 set device=MSP430FR2476
+
+::pause
@exit /b
:: fonction called by SendSource.bat
::echo %~n2
-@set deviceid=%~n2
-@if /I %deviceid:~0,16% == MSP_EXP430FR5739 set deviceid=$8103
-@if /I %deviceid:~0,16% == MSP_EXP430FR5969 set deviceid=$8169
-@if /I %deviceid:~0,16% == MSP_EXP430FR5994 set deviceid=$82A1
-@if /I %deviceid:~0,16% == MSP_EXP430FR6989 set deviceid=$81A8
-@if /I %deviceid:~0,16% == MSP_EXP430FR4133 set deviceid=$81F0
-@if /I %deviceid:~0,16% == MSP_EXP430FR2433 set deviceid=$8240
-@if /I %deviceid:~0,16% == CHIPSTICK_FR2433 set deviceid=$8240
-@if /I %deviceid:~0,16% == MSP_EXP430FR2355 set deviceid=$830C
-@if /I %deviceid:~0,15% == LP_EXP430FR2476 set deviceid=$832A
+@set target=%~n2
+@if /I %target:~0,16% == MSP_EXP430FR5739 set deviceid=$8103
+@if /I %target:~0,16% == MSP_EXP430FR5969 set deviceid=$8169
+@if /I %target:~0,16% == MSP_EXP430FR5994 set deviceid=$82A1
+@if /I %target:~0,16% == MSP_EXP430FR6989 set deviceid=$81A8
+@if /I %target:~0,16% == MSP_EXP430FR4133 set deviceid=$81F0
+@if /I %target:~0,16% == MSP_EXP430FR2433 set deviceid=$8240
+@if /I %target:~0,16% == CHIPSTICK_FR2433 set deviceid=$8240
+@if /I %target:~0,16% == MSP_EXP430FR2355 set deviceid=$830C
+@if /I %target:~0,15% == LP_MSP430FR2476 set deviceid=$832A
::echo %deviceid%
::%1 = "SelectDevice"
uptime timeend ; stops chrono...
diff = timeend - timestart
+;sprintf2 resultat " %s download and execute: %d msec" param2 diff
+filestat param2 size
+KBds = 10 * size / diff
+sprintf2 resultat " %s download compile execute: %d msec (%d kBds eff.)" param2 diff KBds
+
showtt 1 ; display teraterm window
-sprintf2 resultat " %s download and execute: %d msec" param2 diff
messagebox resultat "teraterm.exe"
;logclose
-unlink
+;unlink
;end
::echo %2
::echo %~dp1..\inc\%~n2.pat
-@ECHO OFF
+::@ECHO OFF
::first select part .4TH or .f
:preprocessF
-@%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~dp1..\inc\%~n2.pat %~dpn1.f %~dpn1.4TH
-@call %~d1\config\Select.bat SelectDeviceId %~dp1..\inc\%~n2.pat
+%~dp1..\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~dp1..\inc\%~n2.pat %~dpn1.f %~dpn1.4TH
+call %~dp1..\config\Select.bat SelectDeviceId %~dp1..\inc\%~n2.pat
:DownloadF
-@taskkill /F /IM ttermpro.exe 1> NUL 2>&1
+taskkill /F /IM ttermpro.exe 1> NUL 2>&1
:Win32F
-@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\SendFile.ttl %~dpn1.4TH /C %3 %deviceid% 1> NUL 2>&1
-@IF NOT ERRORLEVEL 1 GOTO EndF
+"C:\Program Files\teraterm\ttpmacro.exe" /V %~dp1..\config\SendFile.ttl %~dpn1.4TH /C %3 %deviceid% 1> NUL 2>&1
+IF NOT ERRORLEVEL 1 GOTO EndF
:Win64F
-@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\SendFile.ttl %~dpn1.4TH /C %3 %deviceid%
+"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~dp1..\config\SendFile.ttl %~dpn1.4TH /C %3 %deviceid%
:EndF
-@MOVE "%~dpn1.4TH" "%~dp1LAST.4TH" > NUL
-call %~d1\config\Select.bat SelectDevice %~dp1..\inc\%~n2.pat
+MOVE "%~dpn1.4TH" "%~dp1LAST.4TH" > NUL
+call %~dp1..\config\Select.bat SelectDevice %~dp1..\inc\%~n2.pat
if not exist %~dp1SD_%device:~3% MD %~dp1SD_%device:~3% > NUL
COPY /y %~dp1LAST.4TH %~dp1SD_%device:~3%\%~n1.4TH > NUL
exit
:Download4th
-@taskkill /F /IM ttermpro.exe 1> NUL 2>&1
+taskkill /F /IM ttermpro.exe 1> NUL 2>&1
:Win324th
-@"C:\Program Files\teraterm\ttpmacro.exe" /V %~d1\config\SendFile.ttl %~dpn1.4TH /C %2 0 1> NUL 2>&1
-@IF NOT ERRORLEVEL 1 GOTO End4th
+"C:\Program Files\teraterm\ttpmacro.exe" /V %~dp1..\config\SendFile.ttl %~dpn1.4TH /C %2 0 1> NUL 2>&1
+IF NOT ERRORLEVEL 1 GOTO End4th
:Win644th
-@"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\SendFile.ttl %~dpn1.4TH /C %2 0
+"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~dp1..\config\SendFile.ttl %~dpn1.4TH /C %2 0
:End4th
-@COPY "%~dpn1.4TH" "%~dp1LAST.4TH" > NUL
+::@COPY "%~dpn1.4TH" "%~dp1LAST.4TH" > NUL
exit
::SendSourceFileToTarget.bat
::used as link in any folder to drag and drop file.f or file.4th on it.
-@ECHO OFF
+:: %1 is file.f to be send
+
+::@ECHO OFF
IF /I "%~x1" == ".f" goto sendF
:send4th
-start %~d1\config\SendSource.bat %1 ECHO
+start %~dp1..\config\SendSource.bat %1 ECHO
::PAUSE > NUL
exit
:sendF
-call %~d1\config\Select.bat SelectTemplate
+call %~dp1..\config\Select.bat SelectTemplate
-start %~d1\config\SendSource.bat %1 %~dp1..\inc\%template% ECHO
+start %~dp1..\config\SendSource.bat %1 %~dp1..\inc\%template% ECHO
::PAUSE > NUL
exit
-:: %1 is file.f to be send
sendln param4 ' ?ID ECHO' ; send: %deviceID% ?ID
sendln 'NOBOOT' ;
-sendln 'TERM2SD" ' inputstr '"' ; send to FastForth the command TERM2SD" \file.4TH" ...with optionnal path added in inputbox
+sendln 'TERM2SD" ' inputstr '"' ; send to FastForth the command 'TERM2SD" \file.4TH"' ...with optionnal path added in inputbox
uptime timestart ; starts chrono...
-sendfile param2 0 ; binary flag = 0 to send text file
+sendfile param2 0 ; binary flag = 0 to send text file (enabling software XON/XOFF)
sendln #4 ; send ETX to ask TERM2SD" to close file
position.maximize=1
# Define SciTE settings for MACROASSEMBLER AS for MSP430
-file.patterns.asm=*.asm;*.inc;*.lst;*.mac
+file.patterns.asm=*.asm;*.inc;*.lst;*.mac;*.pat
# add '*.inc;*.asm;' to 'source.files' variable in 'SciTEGlobal.properties'
# if you want to include these file patterns into default source file list
# the star at the start of this command line is to display the parameters box
# $(1) = target, example : MSP_EXP430FR5969
# $(2) = extension, example : _8MHz
-
+# $(3) = "COMx"
+#command.subsystem.4.*.asm=2
if PLAT_WIN
command.name.0.*.asm=Assemble 1:[target]
command.0.*.asm=*.\config\build.bat $(FileNameExt) $(1)$(2)
command.name.1.*.asm=FET Prog 1:[target]
- command.1.*.asm=*\config\FET_prog.bat $(1)$(2)
+ command.1.*.asm=*.\config\FET_prog.bat $(1)$(2)
-# $(3) = "COMx"
command.name.2.*.asm=BSL Prog 1:[target] with 3:[COMx]
- command.2.*.asm=*\config\BSL_prog.bat $(1)$(2) $(3)
+ command.2.*.asm=*.\config\BSL_prog.bat $(1)$(2) $(3)
command.name.3.*.asm=Assemble target CurrentSelection
- command.3.*.asm=\config\build.bat $(FileNameExt) $(CurrentSelection)
+ command.3.*.asm=.\config\build.bat $(FileNameExt) $(CurrentSelection)
command.name.4.*.asm=FET Prog target CurrentSelection
- command.4.*.asm=\config\FET_prog.bat $(CurrentSelection)
+ command.4.*.asm=.\config\FET_prog.bat $(CurrentSelection)
command.name.5.*.asm=BSL Prog target CurrentSelection with 3:[COMx]
- command.5.*.asm=*\config\BSL_prog.bat $(CurrentSelection) $(3)
+ command.5.*.asm=*.\config\BSL_prog.bat $(CurrentSelection) $(3)
if PLAT_GTK
# variable $FF = /home/thoorens/CloudStation/projets/msp430 is defined in my ~.profile
::@ECHO OFF
-%~d1\prog\asw -x -q -L -i %~dp1inc %1 -o %~dp1binaries\%2.p
-%~d1\prog\p2hex %~dp1binaries\%2.p -r 0x0000-0xffff
-%~d1\prog\srec_cat -contradictory-bytes=warning %~dp1binaries\%2.hex -intel -output %~dp1binaries\%2.txt -ti-txt
+%~dp1prog\asw -x -q -L -i %~dp1inc %1 -o %~dp1binaries\%2.p
+%~dp1prog\p2hex %~dp1binaries\%2.p -r 0x0000-0xffff
+%~dp1prog\srec_cat -contradictory-bytes=warning %~dp1binaries\%2.hex -intel -output %~dp1binaries\%2.txt -ti-txt
del %~dp1binaries\%2.p
-::del %~dp1binaries\%2.hex
+del %~dp1binaries\%2.hex
+::pause
exit
-rem your git copy must be the root of a virtual drive
-
rem %1 is the input file.asm
rem %2 is the target name
# defwords
keywords3.$(file.patterns.forth)=\
code hdncode endcode : ; immediate :noname codennm \
-lo2hi hi2lo colon \
+lo2hi hi2lo colon [if] [else] [then] [undefined] [defined] \
# MSP430 assembly words & MSP430_instructions
keywords4.$(file.patterns.forth)=\
# string words
keywords6.$(file.patterns.forth)=\
-s" ." c" abort" ( .( read" write" del" load"
+s" ." c" abort" ( .( read" write" append" del" load"
if PLAT_WIN
command.name.0.*.f=preprocess file.f with 1:[target].pat then download file.4TH
- command.0.*.f=*\config\SendSource.bat $(FileDir)\$(FileName).f $(1)$(2) NOECHO
+ command.0.*.f=*..\config\SendSource.bat $(FileDir)\$(FileName).f $(1)$(2) NOECHO
command.name.1.*.f=preprocess file.f with 1:[target].pat then download file.4TH with ECHO
- command.1.*.f=*\config\SendSource.bat $(FileDir)\$(FileName).f $(1)$(2) ECHO
+ command.1.*.f=*..\config\SendSource.bat $(FileDir)\$(FileName).f $(1)$(2) ECHO
command.name.2.*.f=preprocess file.f with 1:[target].pat then download file.4th HALFDUPLEX
- command.2.*.f=*\config\SendSource.bat $(FileDir)/$(FileName).f $(1)$(2) HALF
+ command.2.*.f=*..\config\SendSource.bat $(FileDir)/$(FileName).f $(1)$(2) HALF
command.name.3.*.f=preprocess file.f with 1:[target].pat then download file.4TH to target SD_CARD
- command.3.*.f=*\config\CopyTo_SD_Card.bat $(FileDir)\$(FileName).f $(1)$(2)
+ command.3.*.f=*..\config\CopyTo_SD_Card.bat $(FileDir)\$(FileName).f $(1)$(2)
command.name.4.*.f=preprocess file.f with 1:[target].pat to LAST.4th (for debug)
- command.4.*.f=*\config\Preprocess.bat $(FileDir)\$(FileName).f $(1)$(2)
+ command.4.*.f=*..\config\Preprocess.bat $(FileDir)\$(FileName).f $(1)$(2)
command.name.5.*.f=preprocess file.f with target CurrentSelection then download
- command.5.*.f=\config\SendSource.bat $(FileDir)\$(FileName).f $(CurrentSelection) NOECHO
+ command.5.*.f=..\config\SendSource.bat $(FileDir)\$(FileName).f $(CurrentSelection) NOECHO
command.name.6.*.f=preprocess file.f with target CurrentSelection then download with ECHO
- command.6.*.f=\config\SendSource.bat $(FileDir)\$(FileName).f $(CurrentSelection) ECHO
+ command.6.*.f=..\config\SendSource.bat $(FileDir)\$(FileName).f $(CurrentSelection) ECHO
command.name.7.*.f=preprocess file.f with target CurrentSelection then download HALFDUPLEX
- command.7.*.f=\config\SendSource.bat $(FileDir)\$(FileName).f $(CurrentSelection) HALF
+ command.7.*.f=..\config\SendSource.bat $(FileDir)\$(FileName).f $(CurrentSelection) HALF
command.name.8.*.f=preprocess file.f with target CurrentSelection then download file.4th to target SD_CARD
- command.8.*.f=\config\CopyTo_SD_Card.bat $(FileDir)\$(FileName).f $(CurrentSelection)
+ command.8.*.f=..\config\CopyTo_SD_Card.bat $(FileDir)\$(FileName).f $(CurrentSelection)
command.name.9.*.f=preprocess file.f with target CurrentSelection to LAST.4th (for debug)
- command.9.*.f=\config\Preprocess.bat $(FileDir)\$(FileName).f $(CurrentSelection)
+ command.9.*.f=..\config\Preprocess.bat $(FileDir)\$(FileName).f $(CurrentSelection)
command.name.10.*.f=convert FORTH registers to TI's ones
- command.10.*.f=\prog\gema -line -t -f \inc\FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt)
+ command.10.*.f=..\prog\gema -line -t -f \inc\FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt)
command.name.11.*.f=convert TI registers to FORTH's ones
- command.11.*.f=\prog\gema -line -t -f \inc\TiREGtoFastForth.pat $(FileNameExt) $(FileNameExt)
+ command.11.*.f=..\prog\gema -line -t -f \inc\TiREGtoFastForth.pat $(FileNameExt) $(FileNameExt)
command.name.0.*.4th=send file.4th to target
- command.0.*.4th=\config\SendSource.bat $(FileDir)\$(FileName).4TH NOECHO
+ command.0.*.4th=..\config\SendSource.bat $(FileDir)\$(FileName).4TH NOECHO
command.name.1.*.4th=send file.4th to target with ECHO
- command.1.*.4th=\config\SendSource.bat $(FileDir)\$(FileName).4TH ECHO
+ command.1.*.4th=..\config\SendSource.bat $(FileDir)\$(FileName).4TH ECHO
command.name.2.*.4th=send file.4th to target with HALFDUPLEX
- command.2.*.4th=\config\SendSource.bat $(FileDir)/$(FileName).4th HALF
+ command.2.*.4th=..\config\SendSource.bat $(FileDir)/$(FileName).4th HALF
command.name.3.*.4th=send file.4th to target SD_CARD
- command.3.*.4th=\config\CopyTo_SD_Card.bat $(FileDir)\$(FileName).4TH
+ command.3.*.4th=..\config\CopyTo_SD_Card.bat $(FileDir)\$(FileName).4TH
command.name.4.*.4th=convert TI registers to FORTH's ones
- command.4.*.4th=\prog\gema -line -t -f \inc\TiREGtoFastForth.pat $(FileNameExt) $(FileNameExt)
+ command.4.*.4th=..\prog\gema -line -t -f \inc\TiREGtoFastForth.pat $(FileNameExt) $(FileNameExt)
command.name.5.*.4th=convert FORTH registers to TI's ones
- command.5.*.4th=\prog\gema -line -t -f \inc\FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt)
+ command.5.*.4th=..\prog\gema -line -t -f \inc\FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt)
if PLAT_GTK
# variable $FF = /media/jeanmi/DATA/CloudStation is defined in my ~.profile
+++ /dev/null
-# Define SciTE settings for Fortran files.
-
-#filter.fortran=Fortran (f for f90 f95 f2k)|*.f;*.for;*.f90;*.f95;*.f2k|
-filter.fortran=Fortran (for f90 f95 f2k)|*.for;*.f90;*.f95;*.f2k|
-
-#file.patterns.f95=*.f90;*.f95;*.f2k
-file.patterns.f95=*.f90;*.f95;*.f2k;*.pat
-#file.patterns.f77=*.f;*.for
-file.patterns.f77=*.for
-file.patterns.fortran=$(file.patterns.f95);$(file.patterns.f77)
-
-lexer.$(file.patterns.f95)=fortran
-lexer.$(file.patterns.f77)=f77
-
-# keywords and input/output specifiers
-keywordclass.fortran=access action advance allocatable allocate \
-apostrophe assign assignment associate asynchronous backspace \
-bind blank blockdata call case character class close common \
-complex contains continue cycle data deallocate decimal delim \
-default dimension direct do dowhile double doubleprecision else \
-elseif elsewhere encoding end endassociate endblockdata enddo \
-endfile endforall endfunction endif endinterface endmodule endprogram \
-endselect endsubroutine endtype endwhere entry eor equivalence \
-err errmsg exist exit external file flush fmt forall form format \
-formatted function go goto id if implicit in include inout \
-integer inquire intent interface intrinsic iomsg iolength \
-iostat kind len logical module name named namelist nextrec nml \
-none nullify number only open opened operator optional out pad \
-parameter pass pause pending pointer pos position precision \
-print private program protected public quote read readwrite \
-real rec recl recursive result return rewind save select \
-selectcase selecttype sequential sign size stat status stop stream \
-subroutine target then to type unformatted unit use value \
-volatile wait where while write
-
-keywords.$(file.patterns.f95)=$(keywordclass.fortran)
-keywords.$(file.patterns.f77)=$(keywordclass.fortran)
-
-# keywords2 is for highlighting intrinsic and extended functions
-keywords2.$(file.patterns.fortran)=abs achar acos acosd adjustl adjustr \
-aimag aimax0 aimin0 aint ajmax0 ajmin0 akmax0 akmin0 all allocated alog \
-alog10 amax0 amax1 amin0 amin1 amod anint any asin asind associated \
-atan atan2 atan2d atand bitest bitl bitlr bitrl bjtest bit_size bktest break \
-btest cabs ccos cdabs cdcos cdexp cdlog cdsin cdsqrt ceiling cexp char \
-clog cmplx conjg cos cosd cosh count cpu_time cshift csin csqrt dabs \
-dacos dacosd dasin dasind datan datan2 datan2d datand date \
-date_and_time dble dcmplx dconjg dcos dcosd dcosh dcotan ddim dexp \
-dfloat dflotk dfloti dflotj digits dim dimag dint dlog dlog10 dmax1 dmin1 \
-dmod dnint dot_product dprod dreal dsign dsin dsind dsinh dsqrt dtan dtand \
-dtanh eoshift epsilon errsns exp exponent float floati floatj floatk floor fraction \
-free huge iabs iachar iand ibclr ibits ibset ichar idate idim idint idnint ieor ifix \
-iiabs iiand iibclr iibits iibset iidim iidint iidnnt iieor iifix iint iior iiqint iiqnnt iishft \
-iishftc iisign ilen imax0 imax1 imin0 imin1 imod index inint inot int int1 int2 int4 \
-int8 iqint iqnint ior ishft ishftc isign isnan izext jiand jibclr jibits jibset jidim jidint \
-jidnnt jieor jifix jint jior jiqint jiqnnt jishft jishftc jisign jmax0 jmax1 jmin0 jmin1 \
-jmod jnint jnot jzext kiabs kiand kibclr kibits kibset kidim kidint kidnnt kieor kifix \
-kind kint kior kishft kishftc kisign kmax0 kmax1 kmin0 kmin1 kmod knint knot kzext \
-lbound leadz len len_trim lenlge lge lgt lle llt log log10 logical lshift malloc matmul \
-max max0 max1 maxexponent maxloc maxval merge min min0 min1 minexponent minloc \
-minval mod modulo mvbits nearest nint not nworkers number_of_processors pack popcnt \
-poppar precision present product radix random random_number random_seed range real \
-repeat reshape rrspacing rshift scale scan secnds selected_int_kind \
-selected_real_kind set_exponent shape sign sin sind sinh size sizeof sngl snglq spacing \
-spread sqrt sum system_clock tan tand tanh tiny transfer transpose trim ubound unpack verify
-
-# keywords3 are nonstardard, extended and user defined functions
-keywords3.$(file.patterns.fortran)=cdabs cdcos cdexp cdlog cdsin cdsqrt cotan cotand \
-dcmplx dconjg dcotan dcotand decode dimag dll_export dll_import doublecomplex dreal \
-dvchk encode find flen flush getarg getcharqq getcl getdat getenv gettim hfix ibchng \
-identifier imag int1 int2 int4 intc intrup invalop iostat_msg isha ishc ishl jfix \
-lacfar locking locnear map nargs nbreak ndperr ndpexc offset ovefl peekcharqq precfill \
-prompt qabs qacos qacosd qasin qasind qatan qatand qatan2 qcmplx qconjg qcos qcosd \
-qcosh qdim qexp qext qextd qfloat qimag qlog qlog10 qmax1 qmin1 qmod qreal qsign qsin \
-qsind qsinh qsqrt qtan qtand qtanh ran rand randu rewrite segment setdat settim system \
-timer undfl unlock union val virtual volatile zabs zcos zexp zlog zsin zsqrt
-
-#fold.comment.fortran=1
-#fold.quotes.fortran=1
-
-comment.block.fortran=!~
-
-# These setting do not work very well for FORTRAN, uncoment to use it
-# statement.indent.$(file.patterns.fortran)=8 associate block blockdata case do enum \
-# function interface module program subroutine then type where
-# statement.end.$(file.patterns.fortran)=10 end
-
-# Fortran styles
-# Default
-style.fortran.0=fore:#808080
-style.f77.0=fore:#808080
-style.fortran.32=
-style.f77.32=
-# Comment
-style.fortran.1=$(colour.code.comment.line),$(font.code.comment.line)
-style.f77.1=$(colour.code.comment.line),$(font.code.comment.line)
-# Number
-style.fortran.2=$(colour.number)
-style.f77.2=$(colour.number)
-# Single quoted string
-style.fortran.3=$(colour.string)
-style.f77.3=$(colour.string)
-# Double quoted string
-style.fortran.4=$(colour.string)
-style.f77.4=$(colour.string)
-# End of line where string is not closed
-style.fortran.5=fore:#000000,back:#E0C0E0,eolfilled
-style.f77.5=fore:#000000,back:#E0C0E0,eolfilled
-# Operators
-style.fortran.6=$(colour.operator),bold
-style.f77.6=$(colour.operator),bold
-# Identifiers
-style.fortran.7=
-style.f77.7=
-# Keywords
-style.fortran.8=$(colour.keyword),case:u
-style.f77.8=$(colour.keyword),case:u
-# Keywords2
-style.fortran.9=fore:#B00040
-style.f77.9=fore:#B00040
-# Keywords3
-style.fortran.10=fore:#B04080
-style.f77.10=fore:#B04080
-# Preprocessor
-style.fortran.11=$(colour.preproc)
-style.f77.11=$(colour.preproc)
-# Operators in .NAME. format
-#style.fortran.12=$(colour.operator),bold
-#style.f77.12=$(colour.operator),bold
-style.fortran.12=$(colour.operator)
-style.f77.12=$(colour.operator)
-# Labels
-style.fortran.13=fore:#E0C0E0
-style.f77.13=fore:#E0C0E0
-# Continuation
-style.fortran.14=fore:#000000,back:#F0E080
-style.f77.14=fore:#000000,back:#F0E080
-# Braces are matched in all cases
-braces.fortran.style=0
-
-if PLAT_WIN
- fc77=lf95 $(FileNameExt) -c -fix
- fc90=lf95 $(FileNameExt) -c
- g95=g95 $(FileNameExt) -o $(FileName).exe
-if PLAT_GTK
- fc77=f77 -c -o $(FileName).o $(FileNameExt)
- fc90=f90 -c -o $(FileName).o $(FileNameExt)
- g95=g95 $(FileNameExt) -o $(FileName).exe
-command.compile.*.f=$(g95)
-command.build.*.f=make
-command.go.*.f=$(FileName)
-
-command.compile.*.for=$(g95)
-command.build.*.for=make
-command.go.*.for=$(FileName)
-
-command.compile.*.f90=$(g95)
-command.build.*.f90=make
-command.go.*.f90=$(FileName)
-
-command.compile.*.f95=$(g95)
-command.build.*.f95=make
-command.go.*.f95=$(FileName)
-
-if PLAT_WIN
- api.$(file.patterns.fortran)=$(SciteDefaultHome)\fortran.api
-
-autocomplete.fortran.ignorecase=1
-autocomplete.f77.ignorecase=1
-calltip.fortran.ignorecase=1
-calltip.f77.ignorecase=1
\ No newline at end of file
+++ /dev/null
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-q
.PAGE 0 ; listing without pagination
;-------------------------------------------------------------------------------
-VER .equ "V309" ; FORTH version
+VER .equ "V400" ; FORTH version
;===============================================================================
; before assembling or programming you must set TARGET in scite param1 (SHIFT+F8)
;LP_MSP430FR2476 ; compile for LP_MSP430FR2476 launchpad
;CHIPSTICK_FR2433 ; compile for "CHIPSTICK" of M. Ken BOAK
-; choose DTC model (Direct Threaded Code); if you don't know, choose 2, because DOCOL routine without using scratch register
+; choose DTC model (Direct Threaded Code); if you don't know, choose 2
DTC .equ 2 ; DTC model 1 : DOCOL = CALL rDOCOL 14 cycles 1 word shortest DTC model
; DTC model 2 : DOCOL = PUSH IP, CALL rEXIT 13 cycles 2 words best compromize to mix FORTH/ASM code
- ; DTC model 3 : inlined DOCOL 9 cycles 4 words fastest
+ ; DTC model 3 : inlined DOCOL (and LO2HI) 9 cycles 4 words fastest
THREADS .equ 16 ; 1, 2 , 4 , 8 , 16, 32 search entries in word-set.
; +0, +28, +48, +56, +90, +154 bytes, usefull to speed up compilation;
; the FORTH interpreter is speed up by about a square root factor of THREADS.
-FREQUENCY .equ 16 ; fully tested at 1,2,4,8,16 MHz, plus 24 MHz for MSP430FR57xx,MSP430FR2355
-
-; ============================================================================
-TERMINAL_I2C ; - 12 bytes; uncomment to select I2C_Master TERMINAL instead of UART TERMINAL
-; ============================================================================
- .IFDEF TERMINAL_I2C
-MYSLAVEADR .equ 18
-; ============================================================================
- .ELSE ; UART TERMINAL
-; ============================================================================
-TERMINALBAUDRATE .equ 4000000 ; choose value considering the frequency, see explanations below.
-; ----------------------------------------------------------------------------
-TERMINAL3WIRES ; ; + 18 bytes enable 3 wires XON/XOFF software flow control
-TERMINAL4WIRES ; ; + 12 bytes enable 4 wires RTS hardware flow control
+FREQUENCY .equ 8 ; fully tested at 1,2,4,8,16 MHz, plus 24 MHz for MSP430FR57xx,MSP430FR2355
+
+
+; ==============================================================================
+;UART_TERMINAL ; COMMENT TO SWITCH FROM UART TO I2C TERMINAL
+; ==============================================================================
+ .IFDEF UART_TERMINAL
+TERMINALBAUDRATE .equ 4000000
+TERMINAL3WIRES ;; + 18 bytes enable 3 wires XON/XOFF software flow control
+TERMINAL4WIRES ;; + 12 bytes enable 4 wires RTS hardware flow control
;TERMINAL5WIRES ; + 10 bytes enable 5 wires RTS/CTS hardware flow control
-; ----------------------------------------------------------------------------
;HALFDUPLEX ; switch to UART half duplex TERMINAL input
-; ============================================================================
+ .ELSE
+I2C_TERM_ADR .equ 18 ; I2C_TERMINAL_Slave_Address << 1
.ENDIF
;===============================================================================
;===============================================================================
DOUBLE_INPUT ;; + 60 bytes : adds the interpretation engine for double numbers (numbers with dot)
FIXPOINT_INPUT ;; + 68 bytes : adds the interpretation engine for Q15.16 numbers (numbers with comma)
+VOCABULARY_SET ;; + 194 bytes : adds words: WORDSET FORTH hidden PREVIOUS ONLY DEFINITIONS
SD_CARD_LOADER ;; + 1582 bytes : to load source files from SD_card
BOOTLOADER ;; + 82 bytes : includes in WARM process the bootloader SD_CARD\BOOT.4TH.
SD_CARD_READ_WRITE ;; + 1168 bytes : to read, create, write and del files + copy text files from PC to target SD_Card
-;EXTENDED_MEM ; + 506 bytes : allows assembler to execute code up to 1MB (LARGE_CODE).
-;EXTENDED_ASM ; + 1212 bytes : extended assembler to 20 bits datas (LARGE_DATA + LARGE_CODE).
-;VOCABULARY_SET ; + 162 bytes : adds words: WORDSET FORTH hidden PREVIOUS ONLY DEFINITIONS
-;PROMPT ; + 18 bytes : to display prompt "ok ", for FORTH addicts.
+LARGE_CODE ;; + 506 bytes : allows assembler to execute code up to 1MB.
+LARGE_DATA ;; + 1212 bytes : extended assembler to 20 bits addresses and datas.
+;PROMPT ; + 18 bytes : to display the prompt "ok ", (obsolete).
;===============================================================================
+
+;-------------------------------------------------------------------------------
+; OPTIONS that can be added later by downloading their source file >------------------------------------+
+; however, added here, they are protected against WIPE and Deep Reset. |
+;------------------------------------------------------------------------------- v
+;CORE_COMPLEMENT ; + 2304 bytes, if you want a conventional FORTH ANS94 compliant CORE_ANS.f
+;FIXPOINT ; + 422/528 bytes add HOLDS F+ F- F/ F* F#S F. S>F FIXPOINT.f
+;UTILITY ; + 434/524 bytes (1/16threads) : add .S .RS WORDS U.R DUMP ? UTILITY.f
+;SD_TOOLS ; + 142 bytes for trivial DIR, FAT, CLUSTR. and SECTOR. view, (adds UTILITY) SD_TOOLS.f
+;DOUBLE ; DOUBLE word set DOUBLE.f
.save
.listing off
;===============================================================================
; DTCforthMSP430FR5xxx program (FRAM) memory
;-------------------------------------------------------------------------------
; here we place the FORTH primitives without name.
-; Users can access them via declarations made in \inc\MSP430FRxxxx.pat
-;
-;###############################################################################
-; here, FAST FORTH sleeps, waiting any interrupt. With LPM4, supply current is below 1uA.
-; IP,S,T,W,X,Y registers (R13 to R8) are free...
-; ...and so TOS, PSP and RSP stacks within their rules of use.
-;
-; ; remember: to force SLEEP execution, you must end any interrupt routine with :
-; ; BIC #%0_1111_000,0(RSP) ; 4~
-; ; RETI ; 5~ 4 words
-; ;
-; remember: to force SLEEP execution, you must end any interrupt routine with :
-; MOV @RSP+,SR ; 2~
-; BIC #%0_1111_000,SR ; 2~
-; RET ; 3~ 4 words
-;
-; or faster (but SR flags will be lost):
-; ADD #2 RSP ; 1~
-; RET ; 3~ 2 words
-;
-SLEEP CALL &SLEEP_APP ; BACKGND_DEF = UART_RXON/I2C_ACCEPT as default BACKGND_APP; value set by DEEP.
- BIS &LPM_MODE,SR ;2 enter in LPMx mode with GIE=1
- JMP SLEEP ;2 return off any interrupts else TERMINAL_INT
-;
-;###############################################################################
-
+; User can access them via declarations made in \inc\MSP430FRxxxx.pat
; ------------------------------------------------------------------------------
; COMPILING OPERATORS
; ------------------------------------------------------------------------------
-; Primitive lit; compiled by LITERAL
-; lit -- x fetch inline literal to stack
+; Primitive LIT; compiled by LITERAL
+; LIT -- x fetch inline literal to stack
; This is the run-time code of LITERAL.
-lit SUB #2,PSP ; 1 save old TOS..
+LIT SUB #2,PSP ; 1 save old TOS..
MOV TOS,0(PSP) ; 3 ..onto stack
MOV @IP+,TOS ; 2 fetch new TOS value
MOV @IP+,PC ; 4 NEXT
-TWODUP_XSQUOTE ; used by [ELSE]
+TWODUP_XSQUOTE ; see [ELSE]
MOV TOS,-2(PSP) ; 3
MOV @PSP,-4(PSP) ; 4
SUB #4,PSP ; 1
MOV TOS,2(PSP) ; 3 and reserve one cell on stack
MOV.B @IP+,TOS ; 2 -- ? u u = lenght of string
MOV IP,0(PSP) ; 3 -- addr u IP is odd...
- ADD TOS,IP ; 1 -- addr u IP=addr+u=addr(end_of_string)
- BIT #1,IP ; 1 -- addr u IP=addr+u Carry set/clear if odd/even
- ADDC #0,IP ; 1 -- addr u IP=addr+u aligned
+ ADD TOS,IP ; 1 IP=addr+u=addr(end_of_string)
+ BIT #1,IP ; 1 IP=addr+u Carry set/clear if odd/even
+ ADDC #0,IP ; 1 IP=addr+u aligned
MOV @IP+,PC ; 4 16~
-; https://forth-standard.org/standard/core/HERE
-; HERE -- addr returns memory program ptr
-HEREXEC SUB #2,PSP
- MOV TOS,0(PSP)
- MOV &DP,TOS
- MOV @IP+,PC
-
; primitive MU/MOD; used by ?NUMBER UM/MOD, and M*/ in DOUBLE word set
; MU/MOD UDVDlo UDVDhi UDIVlo -- UREMlo UQUOTlo UQUOThi
;-------------------------------------------------------------------------------
; : SETIB SOURCE 2! 0 >IN ! ;
; SETIB org len -- set Input Buffer, shared by INTERPRET and [ELSE]
-SETIB MOV TOS,&SOURCE_LEN ; -- org len
- MOV @PSP+,&SOURCE_ORG ; -- len
- MOV #0,&TOIN ;
-DROP MOV @PSP+,TOS ; --
- MOV @IP+,PC ;
+SETIB MOV #0,&TOIN ;3
+ MOV @PSP+,&SOURCE_ORG ;4 -- len
+ MOV TOS,&SOURCE_LEN ;3 -- len
+DROP MOV @PSP+,TOS ;2 --
+ MOV @IP+,PC ;4
; REFILL accept one line to input buffer and leave org len' of the filled input buffer
; as it has no more host OS and as waiting command is done by ACCEPT, REFILL's flag is useless
MOV @TOS,TOS ;+2 TOS = CONSTANT value
MOV @IP+,PC ;+4 = 16~ = ITC+4
-;-----------------------------------;
-INIT_FORTH ; common part of QABORT|WARM|PUC
-;-----------------------------------;
- CALL &SOFT_APP ; init SOFT_APP
- MOV @RSP+,IP ; init IP with CALLER next address
-; ;
- MOV #PUC_ABORT_ORG,X ; FRAM INFO FRAM MAIN
-; ; --------- ---------
- MOV @X+,&PFAACCEPT ; BODYACCEPT --> PFAACCEPT
- MOV @X+,&PFAEMIT ; BODYEMIT --> PFAEMIT
- MOV @X+,&PFAKEY ; BODYKEY --> PFAKEY
- MOV @X+,&CIB_ORG ; TIB_ORG --> CIB_ORG
-; ;
-; ; FRAM INFO REG|RAM
-; ; --------- -------
- MOV @X+,RSP ; INIT_RSTACK --> R1=RSP
- MOV @X+,rDOCOL ; INIT_DTC --> R4=rDOCOL
- MOV @X+,rDODOES ; INIT_DODOES --> R5=rDODOES
- MOV @X+,rDOCON ; INIT_DOCON --> R6=rDOCON
- MOV @X+,rDOVAR ; INIT_RFROM --> R7=rDOVAR
- MOV @X+,&CAPS ; INIT_CAPS --> RAM CAPS init CAPS ON
- MOV @X+,&BASEADR ; INIT_BASE --> RAM BASE init decimal base
- MOV @X+,&LEAVEPTR ; INIT_LEAVE --> RAM LEAVEPTR
- MOV #0,&STATE ; 0 --> RAM STATE
- MOV #SEL_RST_DEP,PC ; goto PUC 7 to select the user's choice from TOS value: RST_RET|DEEP_RESET
-;-----------------------------------;
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
.include "forthMSP430FR_TERM_I2C.asm"
.ELSE
.IFDEF HALFDUPLEX
;https://forth-standard.org/standard/core/TYPE
;C TYPE adr u -- type string to terminal
TYPE PUSH IP ;3
- MOV #TYPE_NEXT,IP ;2
-; PUSHM #2,X ;4 push X Y
- MOV @PSP,X ;2 -- adr len X = adr
-TYPELOOP MOV TOS,0(PSP) ;3 -- len len
+ MOV #TYPE_NEXT+2,IP ;2 because SUB #2,IP
+ MOV @PSP+,X ;2 -- len X = adr
+TYPELOOP SUB #2,IP ;1 [IP] = TYPE_NEXT
+ SUB #2,PSP ;1 -- x len
+ MOV TOS,0(PSP) ;3 -- len len
MOV.B @X+,TOS ;2 -- len char
- JMP EMIT ;2 ~17, S T W regs are free
+ JMP EMIT ;22 S T W regs are free
TYPE_NEXT mNEXTADR ; -- len
- SUB #2,IP ;1 [IP] = TYPE_NEXT
- SUB #2,PSP ;1 -- x len
- SUB.B #1,TOS ;1 -- x len-1 byte operation, according to the /COUNTED-STRING value
- JNZ TYPELOOP ;2 29~ EMIT loop
-; POPM #2,X ;4 pop Y X
- MOV @RSP+,IP ;2 -- x 0
-TWODROP ADD #2,PSP ;1 -- 0
- MOV @PSP+,TOS ;2 --
- MOV @IP+,PC ;4
-
-BL CALL rDOCON
- .word 20h
+ SUB.B #1,TOS ;1 -- len-1 byte operation, according to the /COUNTED-STRING value
+ JNZ TYPELOOP ;2 32~/19~ EMIT loop 312/526 kBds/MHz --> 7.5MBds @ 24 MHz
+ JZ DROPEXIT ;2
; ------------------------------------------------------------------------------
; forthMSP430FR : CONDITIONNAL COMPILATION, 114/109 words
; ------------------------------------------------------------------------------
+; goal: speed up the false conditionnal to reach true|false equal time: reached!
+; ------------------------------------------------------------------------------
+
+ FORTHWORDIMM "[THEN]" ; does nothing
+; https://forth-standard.org/standard/tools/BracketTHEN
+ MOV @IP+,PC
+
+; ------------------------------------------------------------------------------
; BRanch if BAD strings COMParaison, [COMPARE ZEROEQUAL QFBRAN] replacement
-BRBADCOMP ; -- addr1 u1 addr2 u2
+QBRBADCOMP ; addr1 u1 addr2 u2 --
MOV TOS,S ;1 S = u2
MOV @PSP+,Y ;2 Y = addr2
CMP @PSP+,S ;2 u1 = u2 ?
JNZ BRAN ;2 -- branch if u1<>u2, 11+6 cycles
COMPLOOP CMP.B @Y+,0(X) ;4
JNZ BRAN ;2 -- if char1<>char2; branch on first char <> in 17+6 cycles
- ADD #1,X ;1 addr1+1
- SUB #1,S ;1 u2-1
+ ADD #1,X ;1 addr+1
+ SUB #1,S ;1 u-1
JNZ COMPLOOP ;2 10 cycles char comp loop
SKIPBRANCH ADD #2,IP ;1
MOV @IP+,PC ;4
; [TWODROP ONEMINUS ?DUP ZEROEQUAL QFBRAN next_comp EXIT] replacement
-BRNEXTCMP ; -- cnt addr u
- ADD #2,PSP ;1 -- cnt addr TWODROP
- MOV @PSP+,TOS ;2 -- cnt
+QBRNEXTCMP ; -- cnt addr u
+ ADD #2,PSP ;1 -- cnt addr NIP
+ MOV @PSP+,TOS ;2 -- cnt + DROP = TWODROP
SUB #1,TOS ;3 -- cnt-1 ONEMINUS
JNZ BRAN ;2 -- cnt-1 branch to next comparaison if <> 0
- JZ DROPEXIT ;19w else DROP EXIT
+DROPEXIT MOV @PSP+,TOS ;2 --
+ MOV @RSP+,IP ;2
+ MOV @IP+,PC ;4
FORTHWORDIMM "[ELSE]"
; https://forth-standard.org/standard/tools/BracketELSE
-; [ELSE] a small and fast definition
;Compilation:
;Perform the execution semantics given below.
;Execution:
;including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN],
;until the word [THEN] has been parsed and discarded.
;If the parse area becomes exhausted, it is refilled as with REFILL.
-BRACKETELSE
- mDOCOL
- .word lit,0 ; -- 0
-BRACKETELSE0
- .word ONEPLUS ; -- cnt+1
-BRACKETELSE1 ;
- .word BL,WORDD,COUNT ; -- cnt addr u Z=1 if U=0
- .word ZBRAN,BRACKETELSE5 ; u = 0 if end of line --> refill buffer then loop back
- .word TWODUP_XSQUOTE ; oui je sais, c'est pas beau mais c'est efficace....
- .byte 6,"[THEN]" ; -- cnt addr u addr u addr2 u2
- .word BRBADCOMP,BRACKETELSE2 ; -- cnt addr u if bad string comparaison, jump for next comparaison
- .word BRNEXTCMP,BRACKETELSE1 ; 2DROP, count-1, loop back if count <> 0, else DROP EXIT
-BRACKETELSE2 ;
- .word TWODUP_XSQUOTE ;
- .byte 6,"[ELSE]" ;
- .word BRBADCOMP,BRACKETELSE3 ; if bad string comparaison, jump for next comparaison
- .word BRNEXTCMP,BRACKETELSE0 ; 2DROP, count-1, loop back with count+1 if count <> 0, else DROP EXIT
-BRACKETELSE3 ;
- .word XSQUOTE ;
- .byte 4,"[IF]" ;
- .word BRBADCOMP,BRACKETELSE1 ; if bad string comparaison, loop back
- .word BRAN,BRACKETELSE0 ; else loop back with count+1
-BRACKETELSE5 ;
-;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^;
-; OPTION ; +5 words option
-;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;
- .word XSQUOTE ;
- .byte 5,13,"ko ",10 ;
- .word TYPE ; CR ." ko " LF to show false branch of conditionnal compilation
-;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^;
- .word TWODROP_REFILL ; REFILL Input Buffer with next line
- .word SETIB ; SET Input Buffer pointers SOURCE_LEN, SOURCE_ORG and clear >IN
- .word BRAN,BRACKETELSE1 ; then loop back 45/40 words with/without option
-
- FORTHWORDIMM "[THEN]" ; do nothing
-; https://forth-standard.org/standard/tools/BracketTHEN
-; [THEN]
-BRACKETTHEN MOV @IP+,PC
+;the loop back from BRACKTELSE1 to BRACKTELSE0 is shorten
+BRACKETELSE mDOCOL
+ .word LIT,1 ; -- cnt
+ .word BRAN,BRACKTELSE1 ; 6~ versus 5~ for ONEPLUS
+BRACKTELSE0 .word XSQUOTE ; end of skiped line
+ .byte 5,13,"ko ",10 ; send CR + "ko " + LF
+ .word TYPE ; CR ." ko " LF
+ .word TWODROP_REFILL ; REFILL Input Buffer with next line
+ .word SETIB ; SET Input Buffer pointers SOURCE_LEN, SOURCE_ORG and clear >IN
+BRACKTELSE1 .word BL_WORD,COUNT ; -- cnt addr u Z = 1 if u = 0
+ .word ZBRAN,BRACKTELSE0 ; -- cnt addr 0 Z = 1 --> end of line, -6~
+ .word TWODUP_XSQUOTE ; 24 ~
+ .byte 6,"[THEN]" ; -- cnt addr u addr1 u1 addr2 u2
+ .word QBRBADCOMP,BRACKTELSE2 ; -- cnt addr u if [THEN] not found, jump for next comparaison
+ .word QBRNEXTCMP,BRACKTELSE1 ; if found, 2DROP, count-1, loop back if count <> 0 | DROP EXIT if count = 0
+BRACKTELSE2 .word TWODUP_XSQUOTE ;
+ .byte 6,"[ELSE]" ; -- cnt addr u addr1 u1 addr2 u2
+ .word QBRBADCOMP,BRACKTELSE3 ; -- cnt addr u if [ELSE] not found, jump for next comparaison
+ .word QBRNEXTCMP,BRACKTELSE4 ; if found, 2DROP, count-1, loop back if count <> 0
+BRACKTELSE3 .word XSQUOTE ; 16 ~
+ .byte 4,"[IF]" ; -- cnt addr1 u1 addr2 u2
+ .word QBRBADCOMP,BRACKTELSE1 ; -- cnt if [IF] not found, loop back for next word comparaison
+BRACKTELSE4 .word ONEPLUS ; -- cnt+1 if found, same loop back with count+1
+ .word BRAN,BRACKTELSE1 ;
FORTHWORDIMM "[IF]" ; flag --
; https://forth-standard.org/standard/tools/BracketIF
-; [IF]
;Compilation:
;Perform the execution semantics given below.
;Execution: ;( flag | flag "<spaces>name ..." -- )
JZ BRACKETELSE ; if false flag output
MOV @IP+,PC ; if true flag output
- FORTHWORDIMM "[DEFINED]"
-; https://forth-standard.org/standard/tools/BracketDEFINED
-; [DEFINED]
-;Compilation:
-;Perform the execution semantics given below.
-;Execution:
-;( "<spaces>name ..." -- flag )
-;Skip leading space delimiters. Parse name delimited by a space.
-;Return a true flag if name is the name of a word that can be found,
-;otherwise return a false flag. [DEFINED] is an immediate word.
-DEFINED mDOCOL
- .word BL,WORDD,FIND
- .word NIP,EXIT
-
-
FORTHWORDIMM "[UNDEFINED]"
; https://forth-standard.org/standard/tools/BracketUNDEFINED
-; [UNDEFINED]
;Compilation:
;Perform the execution semantics given below.
;Execution: ( "<spaces>name ..." -- flag )
;Return a false flag if name is the name of a word that can be found,
;otherwise return a true flag.
mDOCOL
- .word BL,WORDD,FIND
+ .word BL_WORD,FIND
mNEXTADR
- MOV @RSP+,IP
- ADD #2,PSP ; NIP
-; https://forth-standard.org/standard/core/ZeroEqual
-; 0= n/u -- flag return true if TOS=0
-ZEROEQUAL SUB #1,TOS ;1 borrow (clear cy) if TOS was 0
+ SUB #1,TOS ;1 borrow if TOS was 0
SUBC TOS,TOS ;1 TOS=-1 if borrow was set
+NIP_EXIT MOV @RSP+,IP
+NIP ADD #2,PSP ;1
MOV @IP+,PC ;4
+ FORTHWORDIMM "[DEFINED]"
+; https://forth-standard.org/standard/tools/BracketDEFINED
+;Compilation:
+;Perform the execution semantics given below.
+;Execution:
+;( "<spaces>name ..." -- flag )
+;Skip leading space delimiters. Parse name delimited by a space.
+;Return a true flag if name is the name of a word that can be found,
+;otherwise return a false flag. [DEFINED] is an immediate word.
+DEFINED mDOCOL
+ .word BL_WORD,FIND
+ .word NIP_EXIT
+
;-------------------------------------------------------------------------------
; STACK OPERATIONS
;-------------------------------------------------------------------------------
; https://forth-standard.org/standard/core/DUP
; DUP x -- x x duplicate top of stack
-DUP MOV TOS,-2(PSP) ; 3
-POSTDECR SUB #2,PSP ; 1 post decrement stack...
+DUP SUB #2,PSP ; 1
+ MOV TOS,0(PSP) ; 3
MOV @IP+,PC ; 4
-; https://forth-standard.org/standard/core/DEPTH
-; DEPTH -- +n number of items on stack, must leave 0 if stack empty
-DEPTH MOV TOS,-2(PSP)
- MOV #PSTACK,TOS
- SUB PSP,TOS ; PSP-S0--> TOS
- RRA TOS ; TOS/2 --> TOS
- JMP POSTDECR
-
;-------------------------------------------------------------------------------
; ARITHMETIC OPERATIONS
;-------------------------------------------------------------------------------
MOV @PSP+,TOS ;2
MOV @IP+,PC ;4
-;-------------------------------------------------------------------------------
-; COMPARAISON OPERATIONS
-;-------------------------------------------------------------------------------
-; https://forth-standard.org/standard/core/Zeroless
-; 0< n -- flag true if TOS negative
-ZEROLESS ADD TOS,TOS ;1 set carry if TOS negative
- SUBC TOS,TOS ;1 TOS=-1 if carry was clear
-INVERT XOR #-1,TOS ;1 TOS=-1 if carry was set
- MOV @IP+,PC ;
-
-; FORTHWORD "U>"
-; https://forth-standard.org/standard/core/Umore
-; U> n1 n2 -- flag
-UMORE SUB @PSP+,TOS ;2
- JNC UMOREEND ; 2 flag = true, Z = 0
- AND #0,TOS ; 1 flag = false,Z = 1
-UMOREEND MOV @IP+,PC ; 4
-
; ------------------------------------------------------------------------------
; STRINGS PROCESSING
; ------------------------------------------------------------------------------
+
+; use SQUOTE+10 to enable separator select
+
FORTHWORDIMM "S\34" ; immediate
; https://forth-standard.org/standard/core/Sq
; S" -- compile in-line string
-SQUOTE MOV #0,&CAPS ; CAPS OFF
- mDOCOL
- .word lit,XSQUOTE,COMMA
- .word lit,'"',WORDD ; -- c-addr = HERE W=Count_of_chars
+SQUOTE SUB #2,PSP ; first choose separator
+ MOV TOS,0(PSP)
+ MOV #'"',TOS ; separator = '"'
+; SQUOTE+10 address ;
+ MOV #0,T ; volatile CAPS OFF, only for WORDD+4 below
+ mDOCOL
+ .word LIT,XSQUOTE,COMMA ; obviously use not T register...
+ .word WORDD+4 ; -- c-addr = DP, W=Count_of_chars
mNEXTADR ;
- MOV #20h,&CAPS ; restore CAPS ON
- ADD #1,W ;
- BIT #1,W ;1 C = /Z
- ADDC W,&DP ; DP is aligned
-DROPEXIT MOV @PSP+,TOS ; --
- MOV @RSP+,IP
- MOV @IP+,PC
-
+ ADD #1,W ; to include count of chars
+ BIT #1,W ; C = /Z
+ ADDC W,&DP ; -- addr new DP is aligned
+ JMP DROPEXIT ;
+
FORTHWORDIMM ".\34" ; immediate
; https://forth-standard.org/standard/core/Dotq
; ." -- compile string to print
DOTQUOTE mDOCOL
.word SQUOTE
- .word lit,TYPE,COMMA
+ .word LIT,TYPE,COMMA
.word EXIT
;-------------------------------------------------------------------------------
JN HOLDW ; jump if 0<
MOV @IP+,PC
+BL CALL rDOCON
+ .word 20h
+
FORTHWORD "U."
; https://forth-standard.org/standard/core/Ud
; U. u -- display u (unsigned)
-; note: DDOT = UDOT + 10
-; use enhanced MUSMOD with 16 bits dividend instead of 32.
+; note: DDOT = UDOT + 10 (see DOUBLE.f)
UDOT MOV #0,S ; 1 -- hi=0
-DOTTODDOT SUB #2,PSP ; 1 convert n|u to d|ud with Y = -1|0
+ SUB #2,PSP ; 1 convert n|u to d|ud with Y = -1|0
MOV TOS,0(PSP) ; 3 -- lo lo
MOV S,TOS ; 1 -- lo hi
-DDOT PUSHM #2,IP ; 4 R-- IP sign
+DDOT PUSHM #2,IP ; 4 R-- IP S=sign
AND #-1,TOS ; clear V, set N
JGE DDOTNEXT ; if hi positive (N=0)
XOR #-1,0(PSP) ;4
DOT CMP #0,TOS
JGE UDOT
MOV #-1,S
- JMP DOTTODDOT
+ JMP UDOT+2
;-------------------------------------------------------------------------------
; INTERPRETER
;-------------------------------------------------------------------------------
- FORTHWORD "WORD"
+
; https://forth-standard.org/standard/core/WORD
; WORD char -- addr Z=1 if len=0
-; parse a word delimited by char separator
-; if CAPS is ON, this word is CAPITALIZED unless 'char' input.
+; parse a word delimited by char separator.
+; the resulting c-string is left at HERE.
+; if CAPS is ON, this word is CAPITALIZED unless for a 'char' input.
; notice that the average lenght of all CORE definitions is about 4.
-WORDD MOV #SOURCE_LEN,S ;2 -- sep
+ FORTHWORD "WORD"
+ JMP WORDD ;2
+;-------------------------------;
+BL_WORD SUB #2,PSP ;1 )
+ MOV TOS,0(PSP) ;3 > 6~ instead of 16~ for CONSTANT BL runtime
+ MOV #' ',TOS ;2 -- BL )
+WORDD MOV &CAPS,T ;3 CAPS OFF = 0, CAPS ON = $20.
+ MOV #SOURCE_LEN,S ;2 -- WORDD+4 address
MOV @S+,X ;2 X = src_len
MOV @S+,Y ;2 Y = src_org
ADD Y,X ;1 X = src_len + src_org = src_end
ADD @S+,Y ;2 Y = >IN + src_org = src_ptr
MOV @S,W ;2 W = HERE = dst_ptr
-SKIPCHARLOO CMP Y,X ;1 src_ptr = src_end ?
- JZ SKIPCHAREND ;2 if yes : End Of Line !
+;-------------------------------;
+SKIPSEPLOOP CMP X,Y ;1 src_ptr >= src_end ?
+ JC SKIPSEPEND ;2 if yes : End Of Line !
CMP.B @Y+,TOS ;2 does char = separator ?
- JZ SKIPCHARLOO ;2 if yes; 7~ loop
+ JZ SKIPSEPLOOP ;2 if yes; 7~ loop
+;-------------------------------;
SUB #1,Y ;1 decrement the post incremented src_ptr
-QSCANTICK MOV &CAPS,T ;3 CAPS OFF = 0, CAPS ON = $20.
- CMP.B #"'",0(Y) ;4 first char = TICK ?
- JNZ SCANWORDLOO ;2 no
- CMP.B @Y,2(Y) ;3 third char = TICK ?
- JNZ SCANWORDLOO ;2 no
- MOV #0,T ;1 don't change to upper case for 'char' input
-SCANWORDLOO MOV.B S,0(W) ;3 first, S makes room in dst for word length; next, put char.
- CMP Y,X ;1 src_ptr = src_end ?
- JZ SCANWORDEND ;2 if yes
+SCANTICK CMP.B #"'",2(Y) ;4 third char = TICK ? (allow ' as first char for a defined word)
+ JNZ SCANWRDLOOP ;2 no
+ MOV #0,T ;1 don't change to upper case for a 'char' input
+;-------------------------------;
+SCANWRDLOOP MOV.B S,0(W) ;3 first, S makes room in dst for word length; next, put char here.
+ CMP X,Y ;1 src_ptr = src_end ?
+ JZ SCANWRDEND ;2 if yes
MOV.B @Y+,S ;2 S=char
CMP.B S,TOS ;1 -- sep does char = separator ?
- JZ SCANWORDEND ;2 if yes
- ADD #1,W ;1 increment dst just before test loop
+ JZ SCANWRDEND ;2 if yes
+ ADD #1,W ;1 increment dst
CMP.B #'a',S ;2 char U< 'a' ? this condition is tested at each loop
- JNC SCANWORDLOO ;2 16~ upper case char loop
+ JNC SCANWRDLOOP ;2 16~ upper case char loop
CMP.B #'z'+1,S ;2 char U>= 'z'+1 ?
- JC SCANWORDLOO ;2 U>= loopback if yes
+ JC SCANWRDLOOP ;2 U>= loopback if yes
SUB.B T,S ;1 convert a...z to A...Z if CAPS ON (T=$20)
- JMP SCANWORDLOO ;2 23~ lower case char loop
-SCANWORDEND
-SKIPCHAREND SUB &SOURCE_ORG,Y ;3 -- sep Y=src_ptr - src_org = new >IN (first char separator next)
- MOV Y,&TOIN ;3 update >IN
- MOV &DP,TOS ;3 -- c-addr
- SUB TOS,W ;1 W=Word_Length
- MOV.B W,0(TOS) ;3
- MOV @IP+,PC ;4 -- c-addr 48 words Z=1 <==> lenght=0 <==> EOL, Z is tested by INTERPRET
+ JMP SCANWRDLOOP ;2 23~ lower case char loop
+SCANWRDEND SUB &SOURCE_ORG,Y ;3 -- sep Y=src_ptr - src_org = new >IN (first char separator next)
+ MOV Y,&TOIN ;3 update >IN for next word search in this input stream
+SKIPSEPEND MOV &DP,TOS ;3 -- addr TOS = HERE
+ SUB TOS,W ;1 W = Word_Length >= 0
+ MOV.B W,0(TOS) ;3 -- c-addr
+ MOV @IP+,PC ;4 Z=1 <==> Word_Length = 0 <==> EOL, tested by INTERPRET
FORTHWORD "FIND" ;
; https://forth-standard.org/standard/core/FIND
-; FIND c-addr -- c-addr 0 if not found ; flag Z=1 c-addr at transient RAM area (HERE)
+; FIND addr -- c-addr 0 if not found ; flag Z=1 c-addr at transient RAM area (HERE)
; CFA -1 if found ; flag Z=0
; CFA 1 if immediate ; flag Z=0
; compare WORD at c-addr (HERE) with each of words in each of listed vocabularies in CONTEXT
-; FIND to WORDLOOP : 10/17 cycles,
-; mismatch word loop: 14 cycles on len, 21 cycles on first char,
+; start of FIND : 5 cycles
+; VOCLOOP : 5/12 cycles,
+; mismatch word loop: +14 cycles on len,
+; +7 cycles on first char,
; +10 cycles char loop,
-; WORDFOUND to end : 16 cycles.
+; WORDFOUND to end : 15/16 cycles.
; note: with 16 threads vocabularies, FIND takes only! 75% of CORETEST.4th processing time
FIND SUB #2,PSP ;1 -- ???? c-addr reserve one cell, not at FINDEND which would kill the Z flag
MOV TOS,S ;1 S=c-addr
MOV #CONTEXT,T ;2 T = first cell addr of CONTEXT stack
VOCLOOP MOV @T+,TOS ;2 -- ???? VOC_PFA T=CTXT+2
- CMP #0,TOS ;1 no more vocabulary in CONTEXT ?
+ CMP #0,TOS ;1 TOS = BODY = voclink; no more vocabulary in CONTEXT ?
JZ FINDEND ;2 -- ???? 0 yes ==> exit; Z=1
.SWITCH THREADS
.CASE 1 ; nothing to do
.ENDCASE
ADD #2,TOS ;1 -- ???? VOC_PFAx+2
WORDLOOP MOV -2(TOS),TOS ;3 -- ???? NFA -2(TOS) = [VOC_PFAx] first, then [LFA]
- CMP #0,TOS ;1 -- ???? NFA no more word in the thread ?
- JZ VOCLOOP ;2 -- ???? NFA yes ==> search next voc in context
+ CMP #0,TOS ;1 no more word in the thread ?
+ JZ VOCLOOP ;2 yes ==> search next voc in context
MOV TOS,X ;1
MOV.B @X+,Y ;2 TOS = NFA, X= NFA+1, Y = NFA_first_byte = cnt<<2+i (i= immediate flag)
RRA.B Y ;1 remove immediate flag, the remainder is the count of the definition name.
LENCOMP CMP.B @S,Y ;2 compare lenght
- JNZ WORDLOOP ;2 -- ???? NFA 14~ word loop on lenght mismatch
+ JNZ WORDLOOP ;2 14~ word loop on lenght mismatch
MOV S,W ;1 S=W=c-addr
CHARCOMP CMP.B @X+,1(W) ;4 compare chars
- JNZ WORDLOOP ;2 -- ???? NFA 21~ word loop on first char mismatch
+ JNZ WORDLOOP ;2 21~ word loop on first char mismatch
ADD #1,W ;1
SUB.B #1,Y ;1 decr count
- JNZ CHARCOMP ;2 -- ???? NFA 10~ char loop
+ JNZ CHARCOMP ;2 10~ char loop
WORDFOUND BIT #1,X ;1
ADDC #0,X ;1
MOV X,S ;1 S=aligned CFA
- MOV.B @TOS,TOS ;2 -- ???? NFA_1st_byte
+ MOV.B @TOS,TOS ;2 -- ???? NFA_1st_byte
AND #1,TOS ;1 -- ???? 0|1 test immediate flag
JNZ FINDEND ;2 -- ???? 1 jump if bit 1 is set, as immediate bit
SUB #1,TOS ;1 -- ???? -1
-FINDEND MOV S,0(PSP) ;3 not found: -- c-addr 0 flag Z=1
- MOV @IP+,PC ;4 34/40 words
+FINDEND MOV S,0(PSP) ;3 -- xt -1/0/1 if not found: -- c-addr 0 flag Z=1
+ MOV @IP+,PC ;4 34/40 words return to interpreter
+
+; FORTHWORD "FIND" ;
+; ; https://forth-standard.org/standard/core/FIND
+; ; FIND addr -- c-addr 0 if not found ; flag Z=1 c-addr at transient RAM area (HERE)
+; ; CFA -1 if found ; flag Z=0
+; ; CFA 1 if immediate ; flag Z=0
+; ; compare WORD at c-addr (HERE) with each of words in each of listed vocabularies in CONTEXT
+; ; start of FIND : 4/11 cycles
+; ; VOCLOOP : 6 cycles,
+; ; mismatch word loop: +14 cycles on len,
+; ; +7 cycles on first char,
+; ; +10 cycles char loop,
+; ; WORDFOUND to end : 15/17 cycles.
+; ; note: with 16 threads vocabularies, FIND takes only! 75% of CORETEST.4th processing time
+; FIND ;
+; .SWITCH THREADS ;
+; .CASE 1 ; nothing to do
+; .ELSECASE ; searching thread adds 7 cycles & 6 words
+; MOV.B 1(TOS),rDOCON ;3 S=c-addr rDOCON=first char of c-addr string
+; AND.B #(THREADS-1),rDOCON;2 rDOCON=thread_x
+; ADD rDOCON,rDOCON ;1 rDOCON=thread_offset_x
+; ADD #2,rDOCON ;1 rDOCON=thread_offset_x+2
+; .ENDCASE
+; SUB #2,PSP ;1 -- ???? c-addr reserve one cell, not at FINDEND which would kill the Z flag
+; MOV TOS,S ;1 S=c-addr
+; MOV #CONTEXT,T ;2 T = first cell addr of CONTEXT stack
+; VOCLOOP MOV @T+,TOS ;2 -- ???? VOC_PFA T=CTXT+2
+; CMP #0,TOS ;1 no more vocabulary in CONTEXT ?
+; JZ FINDEND ;2 -- ???? 0 yes ==> exit; Z=1
+; .SWITCH THREADS
+; .CASE 1 ; nothing to do
+; ADD #2,TOS ;1 -- ???? VOC_PFAx+2
+; .ELSECASE ; searching thread adds 7 cycles & 6 words
+; ADD rDOCON,TOS ;1 -- ???? VOC_PFAx+2 TOS = words set entry
+; .ENDCASE
+; WORDLOOP MOV -2(TOS),TOS ;3 -- ???? NFA -2(TOS) = [VOC_PFAx] first, then [LFA]
+; CMP #0,TOS ;1 no more word in the thread ?
+; JZ VOCLOOP ;2 yes ==> search next voc in context
+; MOV TOS,X ;1
+; MOV.B @X+,Y ;2 TOS = NFA, X= NFA+1, Y = NFA_first_byte = cnt<<2+i (i= immediate flag)
+; RRA.B Y ;1 remove immediate flag, the remainder is the count of the definition name.
+; LENCOMP CMP.B @S,Y ;2 compare lenght
+; JNZ WORDLOOP ;2 14~ word loop on lenght mismatch
+; MOV S,W ;1 S=W=c-addr
+; CHARCOMP CMP.B @X+,1(W) ;4 compare chars
+; JNZ WORDLOOP ;2 21~ word loop on first char mismatch
+; ADD #1,W ;1
+; SUB.B #1,Y ;1 decr count
+; JNZ CHARCOMP ;2 10~ char loop
+; WORDFOUND BIT #1,X ;1
+; ADDC #0,X ;1
+; MOV X,S ;1 S=aligned CFA
+; MOV.B @TOS,TOS ;2 -- ???? NFA_1st_byte
+; AND #1,TOS ;1 -- ???? 0|1 test immediate flag
+; JNZ FINDEND ;2 -- ???? 1 jump if bit 1 is set, as immediate bit
+; SUB #1,TOS ;1 -- ???? -1
+; FINDEND
+; .CASE 1 ; nothing to do
+; .ELSECASE ; searching thread adds 7 cycles & 6 words
+; MOV #XDOCON,rDOCON ;2
+; .ENDCASE
+; MOV S,0(PSP) ;3 -- xt -1/0/1 if not found: -- c-addr 0 flag Z=1
+; MOV @IP+,PC ;4 34/40 words return to interpreter
.IFDEF MPY_32 ; if 32 bits hardware multiplier
MOV @PSP+,Y ;2 -- ud1lo cnt1 Y = ud1hi
MOV @PSP,X ;2 -- x cnt1 X = ud1lo
SUB #4,PSP ;1 -- x x x cnt1
-TONUMLD_OP1 MOV T,&MPY ;3 base = MPY OP1 loaded out of TONUMLOOP
+TONUMLD_OP1 MOV T,&MPY ;3 base = MPY = OP1 loaded out of TONUMLOOP
TONUMLOOP MOV.B @S,W ;2 -- x x x cnt S=adr, T=base, W=char, X=udlo, Y=udhi
-DDIGITQ SUB.B #3Ah,W ;2 all Ctrl_Chars < '0' and all chars '0' to '9' become negative
+DDIGITQ SUB.B #':',W ;2 all Ctrl_Chars < '0' and all chars '0' to '9' become negative
JNC DDIGITQNEXT ;2 accept all chars U< ':' (accept $0 up to $39)
- SUB.B #7,W ;2 W = char - ($3A + $07 = 'A')
+ SUB.B #7,W ;2 W = char - (':' + $07 = 'A')
JNC TONUMEND ;2 -- x x x cnt reject all Ctrl_Chars U< 'A', (with Z flag = 0)
DDIGITQNEXT ADD.B #0Ah,W ;2 restore digit value: 0 to 15 (and beyond)
CMP T,W ;1 digit-base (U>= comparaison rejects all Ctrl_Chars)
BIC #Z,SR ;1 reset Z before return to QNUMBER because else
JC TONUMEND ;2 to avoid QNUMBER conversion true with digit=base :-(
-UDSTAR MOV X,&OP2L ;3 Load 2nd operand (ud1lo)
+ MOV X,&OP2L ;3 Load 2nd operand (ud1lo)
MOV Y,&OP2H ;3 Load 2nd operand (ud1hi)
MOV &RES0,X ;3 lo result in X (ud2lo)
MOV &RES1,Y ;3 hi result in Y (ud2hi)
-MPLUS ADD W,X ;1 ud2lo + digit
+ ADD W,X ;1 ud2lo + digit
ADDC #0,Y ;1 ud2hi + carry
TONUMPLUS ADD #1,S ;1 adr+1
SUB #1,TOS ;1 -- x x x cnt cnt-1
- JNZ TONUMLOOP ;2 if count <>0 33~ loop
+ JNZ TONUMLOOP ;2 if count <>0 34~ digit loop
TONUMEND MOV S,0(PSP) ;3 -- x x addr2 cnt2
MOV Y,2(PSP) ;3 -- x ud2hi addr2 cnt2
MOV X,4(PSP) ;3 -- ud2lo ud2hi addr2 cnt2
QHEXA MOV #16,T ;2 preset base 16
CMP.B #1,W ;1 hex '$' prefix ? '#' + 1 = '$'
JZ PREFIXNEXT ;2 yes
-QTICK CMP.B #4,W ;1 prefix = ' ? '#' + 4 = "'"
- JNZ QNUMNEXT ;2 -- addr x x x cnt no, abort because prefix not recognized
+QTICK CMP.B #4,W ;1 ' prefix ? '#' + 4 = "'"
+ JNZ QNUMNEXT ;2 -- addr x x x cnt no, abort because other prefixes not recognized
CMP #3,TOS ;2 count = 3 ?
JNZ QNUMNEXT ;2 no, abort
- CMP.B @S+,1(S) ;4 -- addr x x x 3 3rd char = 1st char = "'" ?
+ CMP.B @S+,1(S) ;4 -- addr x x x 3 3rd char = 1st char ?
MOV.B @S,S ;2 does byte to word conversion
- MOV S,4(PSP) ;3 -- addr ud2lo x x x ud2lo = ASCII code of 'char'
- JMP QNUMNEXT ;2 -- addr ud2lo x x x with happy end if 3rd char = 1st char
+ MOV S,4(PSP) ;3 -- addr ud2lo x x 3 ud2lo = ASCII code of 'char'
+ JMP QNUMNEXT ;2 -- addr ud2lo x x 3 with happy end only if 3rd char = 1st char = "'"
QNUMMINUS MOV #-1,2(RSP) ;3 R-- sign IP set sign flag
PREFIXNEXT SUB #1,TOS ;1 -- addr x x x cnt-1 TOS=count-1
CMP.B @S+,0(S) ;4 S=adr+1; same prefix ?
; ------------------------------;
QNUMNEXT POPM #2,TOS ;4 -- addr ud2lo-hi x sign R: -- POPM IP,TOS TOS = sign flag = {-1;0}
JZ QNUMOK ;2 -- addr ud2lo-hi x sign conversion OK if Z=1
-QNUMKO
- .IFDEF DOUBLE_NUMBERS ;
- BIC #UF9,SR ;2 reset flag UF9, before next use as double number flag
- .ENDIF
- ADD #6,PSP ;2 -- addr sign
+; ------------------------------;
+QNUMKO ADD #6,PSP ;2 -- addr sign
AND #0,TOS ;1 -- addr ff TOS=0 and Z=1 ==> conversion ko
MOV @IP+,PC ;4
; ------------------------------;
ADD #1,2(PSP) ;3
ADDC #0,0(PSP) ;3
QDOUBLE BIT #UF9,SR ;2 -- dlo dhi tf decimal point or comma fixpoint ?
- JNZ QNUMEND ;2 leave double
-NIP ADD #2,PSP ;1 -- n tf leave number
+ JZ NIP ;2 no, goto leave number
QNUMEND MOV @IP+,PC ;4 TOS<>0 and Z=0 ==> conversion ok
.ELSE
QNUMOK ADD #4,PSP ;1 -- addr ud2lo sign
XOR #-1,TOS ;1 -- udlo udhi sign
QNEGATE XOR #-1,2(PSP) ;3
ADD #1,2(PSP) ;3 -- n u tf
-QNUMEND
-NIP ADD #2,PSP ;1 -- n tf
+QNUMEND ADD #2,PSP ;1 -- n tf
MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok
.ENDIF ; DOUBLE_NUMBERS ;
MOV #UMSTARNEXT2,IP ;2
UMSTARTWO JMP UMSTAR1 ;2 -- ud1lo ud1hi x ud4hi X=ud4lo
UMSTARNEXT2 mNEXTADR ; -- ud1lo ud1hi x ud4hi
-MPLUS ADD @RSP+,X ;2 -- ud1lo ud1hi x ud4hi X=ud4lo+digit=ud2lo r-- IP adr count base ud3lo
+ ADD @RSP+,X ;2 -- ud1lo ud1hi x ud4hi X=ud4lo+digit=ud2lo r-- IP adr count base ud3lo
ADDC @RSP+,TOS ;2 -- ud1lo ud1hi x ud2hi TOS=ud4hi+ud3lo+carry=ud2hi r-- IP adr count base
MOV X,4(PSP) ;3 -- ud2lo ud1hi x ud2hi
MOV TOS,2(PSP) ;3 -- ud2lo ud2hi x x r-- IP adr count base
CMP.B #1,Y ;1 hex prefix ? '$' = '#' + 1
JZ PREFIXNEXT ;2 yes
QTICK CMP.B #4,Y ;1 prefix = ' ? "'" = '#' + 4
- JNZ QNUMNEXT ;2 -- addr x x x cnt abort if not recognized prefix
+ JNZ QNUMNEXT ;2 -- addr x x x cnt no, abort because other prefixes not recognized
CMP #3,TOS ;
JNZ QNUMNEXT ;
CMP.B @S+,1(S) ;4 compare 3rd with first char '
MOV.B @S,S ;2 does char to word conversion
- MOV S,4(PSP) ;5 -- addr ud2lo 0 x x ud2lo = ASCII code of 'char'
+ MOV S,4(PSP) ;5 -- addr ud2lo x x 3 ud2lo = ASCII code of 'char'
JMP QNUMNEXT ;2 with happy end if flag Z = 1
QNUMMINUS MOV #-1,2(RSP) ;3 R-- sign IP set sign flag
PREFIXNEXT SUB #1,T ;1 T=count-1
; ------------------------------;97
QNUMNEXT POPM #2,TOS ;4 -- addr ud2lo-hi x sign R: -- POPM IP,TOS TOS = sign flag = {-1;0}
JZ QNUMOK ;2 -- addr ud2lo-hi x sign conversion OK if Z=1
-QNUMKO ; flag Z=0
- .IFDEF DOUBLE_NUMBERS
- BIC #UF9,SR
- .ENDIF
- ADD #6,PSP ;1 -- addr sign
+; ------------------------------;
+QNUMKO ADD #6,PSP ;1 -- addr sign
AND #0,TOS ;1 -- addr ff TOS=0 and Z=1 ==> conversion ko
MOV @IP+,PC ;4
; ------------------------------;
ADD #1,2(PSP) ;3
ADDC #0,0(PSP) ;3 -- dlo dhi tf
QDOUBLE BIT #UF9,SR ;2 -- dlo dhi tf decimal point added ?
- JNZ QNUMEND ;2 -- dlo dhi tf leave double
-NIP ADD #2,PSP ;1 -- dlo tf leave number, Z=0
+ JZ NIP ; no, goto leave number, Z=0
QNUMEND MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok
.ELSE
QNUMOK ADD #4,PSP ;1 -- addr ud2lo sign
XOR #-1,TOS ;1 -- udlo udlo tf TOS=-1 and Z=0
QNEGATE XOR #-1,2(PSP) ;3
ADD #1,2(PSP) ;3 -- n udlo tf
-QNUMEND
-NIP ADD #2,PSP ;1
+QNUMEND ADD #2,PSP ;1
MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok
.ENDIF ; DOUBLE_NUMBERS
.ENDIF ; of Hardware/Software MPY
BACKSLASH MOV &SOURCE_LEN,&TOIN ;
MOV @IP+,PC
+; ------------------------------;
+; INTERPRET = BACKSLASH + 8 ;
+; ------------------------------;
; INTERPRET i*x addr u -- j*x interpret given buffer
; This is the common factor of EVALUATE and QUIT.
; set addr u as input buffer then parse it word by word
INTERPRET mDOCOL ; INTERPRET = BACKSLASH + 8
.word SETIB ; -- set input buffer pointers
-INTLOOP .word BL,WORDD ; -- c-addr fl flag Z = 1 <=> End Of Line
- .word ZBRAN,FDROPEXIT; BRANch to DROPEXIT if Z = 1
- .word FIND
+INTLOOP .word BL_WORD ; -- c-addr flag Z = 1 <=> End Of Line
+ .word ZBRAN,FDROPEXIT; early return if End of Line
+ .word FIND ;
mNEXTADR ; -- xt|c-addr|xt -1|0|+1 Z=1 --> not found
MOV TOS,W ; W = flag = (-1|0|+1) as (not_immediate|not_found|immediate)
MOV @PSP+,TOS ; -- xt|c-addr|xt
- MOV #INTQNUMNEXT,IP ;2 INTQNUMNEXT is the continuation of QNUMBER
+ MOV #INTQNUMNEXT,IP ;2 INTQNUMNEXT is the next of QNUMBER
JZ QNUMBER ;2 if Z=1 --> not found, search a number
MOV #INTLOOP,IP ;2 INTLOOP is the continuation of EXECUTE|COMMA
XOR &STATE,W ;3
MOV @PSP+,TOS ;2 -- n|c-addr
MOV #INTLOOP,IP ;2 INTLOOP is the continuation of LITERAL.
JNZ LITERAL ;2 n -- Z = 0 --> is a number, execute LITERAL then loop back to INTLOOP
-NotFoundexe ADD.B #1,0(TOS) ;3 c-addr -- Z = 1 --> Not a Number : incr string count to add '?'
+NOTFOUND MOV #FABORT_TERM,IP ;2 ABORT_TERM becomes the end of INTERPRET
+ ADD.B #1,0(TOS) ;3 c-addr -- Z = 1 --> Not a Number : incr string count to add '?'
MOV.B @TOS,Y ;2 Y=count+1
ADD TOS,Y ;1 Y=end of string addr
MOV.B #'?',0(Y) ;5 add '?' to end of string
- MOV #FABORT_TERM,IP ;2 ABORT_TERM is the continuation of COUNT
- JMP COUNT ;2 -- addr len 37 words
-
-;-------------------------------------------------------------------------------
-; DICTIONARY MANAGEMENT
-;-------------------------------------------------------------------------------
- FORTHWORD ","
-; https://forth-standard.org/standard/core/Comma
-; , x -- append cell to dict
-COMMA ADD #2,&DP ;3
- MOV &DP,W ;3
- MOV TOS,-2(W) ;3
- MOV @PSP+,TOS ;2
- MOV @IP+,PC ;4 15~ W = DP
+ JMP COUNT ;2 -- addr len return to ABORT_TERM
+FDROPEXIT .word DROPEXIT
FORTHWORDIMM "LITERAL" ; immediate
+ .IFDEF DOUBLE_NUMBERS ; are recognized
; https://forth-standard.org/standard/core/LITERAL
; LITERAL n -- append single numeric literal if compiling state
; d -- append two numeric literals if compiling state and UF9<>0 (not ANS)
- .IFDEF DOUBLE_NUMBERS ; are recognized
LITERAL CMP #0,&STATE ;3
- JZ LITERALNEXT ;2 if interpreting state, does nothing else clear UF9 flag
+ JZ LITERALNEXT ;2 if interpreting state, does nothing else to clear UF9 flag
MOV TOS,X ;1 X = n|dhi
LITERALLOOP MOV &DP,W ;3
ADD #4,&DP ;3
- MOV #lit,0(W) ;4
+ MOV #LIT,0(W) ;4
MOV X,2(W) ;3 pass 1: compile n, if pass 2: compile dhi
MOV @PSP+,TOS ;2
BIT #UF9,SR ;2 double number ?
JMP LITERALLOOP ;2
LITERALEND MOV @IP+,PC ;4
.ELSE
+; https://forth-standard.org/standard/core/LITERAL
+; LITERAL n -- append single numeric literal if compiling state
LITERAL CMP #0,&STATE ;3
JZ LITERALEND ;2 if interpreting state, does nothing
MOV &DP,W ;3
ADD #4,&DP ;3
- MOV #lit,0(W) ;4
+ MOV #LIT,0(W) ;4
MOV TOS,2(W) ;3
MOV @PSP+,TOS ;2
LITERALEND MOV @IP+,PC ;4
.ENDIF
+; https://forth-standard.org/standard/core/DEPTH
+; DEPTH -- +n number of items on stack, must leave 0 if stack empty
+QDEPTH MOV TOS,-2(PSP) ; 3
+ MOV #PSTACK,TOS ; 2
+ SUB PSP,TOS ; 1 PSP-S0--> TOS
+ RRA TOS ; 1 TOS/2 --> TOS
+ SUB #2,PSP ; 1
+; https://forth-standard.org/standard/core/Zeroless
+; 0< n -- flag true if TOS negative
+ZEROLESS ADD TOS,TOS ;1 set carry if TOS negative
+ SUBC TOS,TOS ;1 TOS=-1 if carry was clear
+INVERT XOR #-1,TOS ;1 TOS=-1 if carry was set
+ MOV @IP+,PC ;4
+
FORTHWORD "COUNT"
; https://forth-standard.org/standard/core/COUNT
; COUNT c-addr1 -- adr len counted->adr/len
MOV.B @TOS+,W ;2
MOV TOS,0(PSP) ;3
MOV W,TOS ;1
- AND #-1,TOS ; Z is set if u=0
- MOV @IP+,PC ;4 14~
+ AND #-1,TOS ;1 Z is set if u=0
+ MOV @IP+,PC ;4 12~
+
+QFRAM_FULL SUB #2,PSP ; 2
+ MOV TOS,0(PSP) ; 3
+ MOV #0,TOS ; 1
+ CMP #FRAM_FULL,&DP ; 4
+ JC INVERT ; 2
+ MOV @IP+,PC ; 4 16~
FORTHWORD "ALLOT"
; https://forth-standard.org/standard/core/ALLOT
MOV @PSP+,TOS
MOV @IP+,PC
+; ----------------------------------;
+; ABORT = ALLOT + $08 ;
+; QUIT = ALLOT + $0E ;
+; ----------------------------------;
; FORTHWORD "ABORT"
; https://forth-standard.org/standard/core/ABORT
; Empty the data stack and perform the function of QUIT,
; which includes emptying the return stack, without displaying a message.
; ABORT is the common next of WARM and ABORT"
-ABORT MOV #PSTACK,PSP ; ABORT = ALLOT + 8
- MOV #0,TOS ; and clear TOS for SYS use.
+ABORT MOV #PSTACK,PSP ; clear Parameter stack
+ MOV #0,TOS ; clear TOS for SYS use.
; https://forth-standard.org/standard/core/QUIT
; QUIT -- interpret line by line the input stream
-QUIT mASM2FORTH ; QUIT = ALLOT + 14
+QUIT mASM2FORTH ; QUIT is the level 0 of Return stack
.IFDEF PROMPT
-QUIT1 .word XSQUOTE ; lower interpret loop
- .byte 5,13,10,"ok " ; CR + LF + Forth prompt
+QUIT1 .word XSQUOTE ;
+ .byte 5,13,10,"ok " ; CR+LF + Forth prompt
QUIT2
.ELSE
-QUIT2 .word XSQUOTE
+QUIT2 .word XSQUOTE ; 16~
.byte 2,13,10 ; CR+LF
.ENDIF
- .word TYPE ;
- .word REFILL ; -- org len refill input buffer from ACCEPT (one line)
-QUIT4 .word INTERPRET ; interpret input buffer|string
-QUIT5 .word DEPTH,ZEROLESS ; stack empty test
- .word XSQUOTE ; ABORT" stack empty! "
+ .word TYPE ; 79~
+ .word REFILL ; -- org len refill the input line buffer from ACCEPT
+QUIT4 .word INTERPRET ; interpret it
+QUIT5 .word QDEPTH ; 15~ stack empty test
+ .word XSQUOTE ; 16~ ABORT" stack empty"
.byte 11,"stack empty";
- .word QABORT ; see QABORT in forthMSP430FR_TERM_xxx.asm
- .word HEREXEC ; )
- .word lit,FRAM_FULL ; > FRAM full test
- .word UMORE ; )
- .word XSQUOTE ; ABORT" FRAM full! "
- .byte 9,"FRAM full" ;
- .word QABORT ; see QABORT in forthMSP430FR_TERM_xxx.asm
+ .word QABORT ; 14~ see QABORT in forthMSP430FR_TERM_xxx.asm
+ .word QFRAM_FULL ; 16~ FRAM full test
+ .word XSQUOTE ; 16~ ABORT" MAIN full"
+ .byte 9,"MAIN full" ;
+ .word QABORT ; 14~
.IFDEF PROMPT
- .word lit,STATE,FETCH ; STATE @
+ .word LIT,STATE,FETCH ; STATE @
.word QFBRAN,QUIT1 ; 0= case of interpretion state
.word XSQUOTE ; 0<> case of compilation state
.byte 5,13,10," " ; CR+LF + 3 spaces
.ENDIF
- .word BRAN,QUIT2
+ .word BRAN,QUIT2 ; 6~
FORTHWORDIMM "ABORT\34"
-; ; ABORT" is enabled in interpretation mode (+ 17 words) :
+; ; ABORT" is enabled in interpretation mode (+ 11 words) :
+; PUSH IP
; CMP #0,&STATE
-; JNZ CMPL_QABORT
-; MOV #0,&CAPS ; CAPS OFF
-; EXEC_QABORT mDOCOL
-; .word LIT,'"',WORDD,COUNT,QABORT
-; .word BL,LIT,CAPS,STORE
-; .word EXIT
+; JNZ COMP_QABORT
+; EXEC_QABORT MOV #0,T ; CAPS OFF
+; mASM2FORTH
+; .word LIT,'"',WORDD+4,COUNT,QABORT
+; .word DROPEXIT
+;COMP_QABORT mASM2FORTH
+; .word SQUOTE
+; .word LIT,QABORT,COMMA ; see QABORT in forthMSP430FR_TERM_xxx.asm
+;FEXIT .word EXIT
; https://forth-standard.org/standard/core/ABORTq
; ABORT" " (empty string) displays nothing
; ABORT" i*x flag -- i*x R: j*x -- j*x flag=0
; i*x flag -- R: j*x -- flag<>0
-CMPL_QABORT mDOCOL
+ mDOCOL
.word SQUOTE
- .word lit,QABORT,COMMA ; see QABORT in forthMSP430FR_TERM_xxx.asm
- .word EXIT
+ .word LIT,QABORT,COMMA ; see QABORT in forthMSP430FR_TERM_xxx.asm
+FEXIT .word EXIT
-;-------------------------------------------------------------------------------
-; COMPILER
-;-------------------------------------------------------------------------------
FORTHWORD "'"
; https://forth-standard.org/standard/core/Tick
-; ' -- xt find word in dictionary and leave on stack its execution address
+; ' -- xt find word in dictionary and leave on stack its execution address if exist else error.
TICK mDOCOL
- .word BL,WORDD,FIND
- .word ZBRAN,NotFound ; BRANch to NotFound if Z = 1
-FDROPEXIT .word DROPEXIT
-NotFound .word NotFoundExe ; see INTERPRET
-
+ .word BL_WORD,FIND
+ .word QFBRAN,FNOTFOUND;
+ .word EXIT
+FNOTFOUND .word NOTFOUND ; see INTERPRET
FORTHWORDIMM "[']" ; immediate word, i.e. word executed during compilation
; https://forth-standard.org/standard/core/BracketTick
; ['] <name> -- find word & compile it as literal
BRACTICK mDOCOL
.word TICK ; get xt of <name>
- .word lit,lit,COMMA ; append lit action
+ .word LIT,LIT,COMMA ; append LIT action
.word COMMA,EXIT ; append xt literal
FORTHWORDIMM "[" ; immediate
; https://forth-standard.org/standard/core/Bracket
; [ -- enter interpretative state
-LEFTBRACKET
- MOV #0,&STATE
+LEFTBRACKET MOV #0,&STATE
MOV @IP+,PC
FORTHWORD "]"
; https://forth-standard.org/standard/core/right-bracket
; ] -- enter compiling state
-RIGHTBRACKET
MOV #-1,&STATE
MOV @IP+,PC
+;-------------------------------------------------------------------------------
+; COMPILER
+;-------------------------------------------------------------------------------
+ FORTHWORD ","
+; https://forth-standard.org/standard/core/Comma
+; , x -- append cell to dict
+COMMA ADD #2,&DP ;3
+ MOV &DP,W ;3
+ MOV TOS,-2(W) ;3
+ MOV @PSP+,TOS ;2
+ MOV @IP+,PC ;4 15~ W = DP
+
FORTHWORDIMM "POSTPONE"
; https://forth-standard.org/standard/core/POSTPONE
POSTPONE mDOCOL
- .word BL,WORDD,FIND
- .word ZBRAN,NotFound ; BRANch to NotFound if Z = 1
+ .word BL_WORD,FIND
+ .word ZBRAN,FNOTFOUND ; BRANch to FNOTFOUND if Z = 1
.word ZEROLESS ; immediate word ?
.word QFBRAN,POST1 ; if immediate
- .word lit,lit,COMMA ; else compile lit
+ .word LIT,LIT,COMMA ; else compile LIT
.word COMMA ; compile xt
- .word lit,COMMA ; CFA of COMMA
+ .word LIT,COMMA ; CFA of COMMA
POST1 .word COMMA,EXIT ; then compile xt of word found if immediate else CFA of COMMA
FORTHWORD ":"
HEADER BIT #1,&DP ;3 carry set if odd
ADDC #2,&DP ;4 align and make room for LFA
mDOCOL ;
- .word BL,WORDD ; W=Count_of_chars
+ .word BL_WORD ; W = Count_of_chars, up to 127 for definitions
mNEXTADR ; -- HERE HERE is the NFA of this new word
MOV @RSP+,IP ;
BIS.B #1,W ; W=count is always odd
ADD TOS,W ; W=Aligned_CFA
MOV &CURRENT,X ; X=VOC_BODY of CURRENT
MOV TOS,Y ; Y=NFA
+ ADD.B @TOS+,-1(TOS) ; shift left once NFA_1st_byte (make room for immediate flag, clear it)
.SWITCH THREADS ;
.CASE 1 ; nothing to do
.ELSECASE ; multithreading add 5~ 4words
- MOV.B 1(TOS),TOS ; -- char TOS=first CHAR of new word
- AND #(THREADS-1),TOS ; -- offset TOS= thread_offset
- ADD TOS,TOS ; TOS= thread_offset * 2
+ MOV.B @TOS,TOS ; -- char TOS=first CHAR of new word
+ AND #(THREADS-1),TOS ; -- offset TOS= thread_offset in words
+ ADD TOS,TOS ; TOS= thread_offset in bytes
ADD TOS,X ; X=VOC_PFAx = thread x of VOC_PFA of CURRENT
.ENDCASE ;
MOV @PSP+,TOS ; --
- ADD.B @Y,0(Y) ; shift left once NFA_1st_byte (make room for immediate flag)
HEADEREND MOV Y,&LAST_NFA ; NFA --> LAST_NFA used by QREVEAL, IMMEDIATE
MOV X,&LAST_THREAD ; VOC_PFAx --> LAST_THREAD used by QREVEAL
MOV W,&LAST_CFA ; HERE=CFA --> LAST_CFA used by DOES>, RECURSE
MOV PSP,&LAST_PSP ; save PSP for check compiling, used by QREVEAL
- ADD #4,W ; by default make room for two words...
+ ADD #4,W ; W = BODY of created word...
MOV W,&DP ;
MOV @RSP+,PC ; RET W is the new DP value )
- ; X is LAST_THREAD > used by compiling words: CREATE, DEFER, :...
+;-----------------------------------; X is LAST_THREAD > used by compiling words: CREATE DEFER : CODE ...
COLONNEXT ; Y is NFA )
- .SWITCH DTC ; Direct Threaded Code select
- .CASE 1 ;
- MOV #DOCOL,-4(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = XDOCOL)
- SUB #2,&DP ;
- .CASE 2 ;
- MOV #120Dh,-4(W) ; compile PUSH IP 3~
- MOV #DOCOL,-2(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = EXIT)
- .CASE 3 ;
- MOV #120Dh,-4(W) ; compile PUSH IP 3~
- MOV #400Dh,-2(W) ; compile MOV PC,IP 1~
- MOV #522Dh,0(W) ; compile ADD #4,IP 1~
- MOV #4D30h,+2(W) ; compile MOV @IP+,PC 4~
- ADD #4,&DP ;
+ .SWITCH DTC ; Direct Threaded Code select:
+ .CASE 1 ; [rDOCOL] = XDOCOL
+ MOV #DOCOL,-4(W) ; compile CALL R4 = rDOCOL
+ SUB #2,&DP ; adjust DP
+ .CASE 2 ; [rDOCOL] = EXIT
+ MOV #120Dh,-4(W) ; compile PUSH IP 3~
+ MOV #DOCOL,-2(W) ; compile CALL R4 = rDOCOL
+ .CASE 3 ; [rDOCOL] = ???
+ MOV #120Dh,-4(W) ; compile PUSH IP 3~
+ MOV #400Dh,-2(W) ; compile MOV PC,IP 1~
+ MOV #522Dh,0(W) ; compile ADD #4,IP 1~
+ MOV #4D30h,+2(W) ; compile MOV @IP+,PC 4~
+ ADD #4,&DP ; adjust DP
.ENDCASE ;
MOV #-1,&STATE ; enter compiling state
MOV @IP+,PC ;
;-----------------------------------;
;;Z ?REVEAL -- if no stack mismatch, link this new word in the CURRENT vocabulary
-QREVEAL CMP PSP,&LAST_PSP ; Check SP with its saved value by :, :NONAME, CODE...
- JZ LINK_NFA ; see MARKER
+QREVEAL CMP PSP,&LAST_PSP ; Check SP with its saved value by , :NONAME CODE...
+ JNZ BAD_CSP ;
+ JZ LINK_NFA ;
BAD_CSP mASM2FORTH ; if stack mismatch.
.word XSQUOTE
.byte 15,"stack mismatch!"
FABORT_TERM .word ABORT_TERM
+LINK_NFA MOV &LAST_NFA,Y ; if no error, link this definition in its thread
+ MOV &LAST_THREAD,X ;
+REVEAL MOV @X,-2(Y) ; [LAST_THREAD] --> LFA (for NONAME: LFA --> 210h unused PA reg)
+ MOV Y,0(X) ; LAST_NFA --> [LAST_THREAD] (for NONAME: [LAST_THREAD] --> 212h unused PA reg)
+ MOV @IP+,PC
FORTHWORDIMM ";"
; https://forth-standard.org/standard/core/Semi
SEMICOLON CMP #0,&STATE ; if interpret mode, semicolon becomes a comment identifier
JZ BACKSLASH ; tip: ";" is transparent to the preprocessor, so semicolon comments are kept in file.4th
mDOCOL ; compile mode
- .word lit,EXIT,COMMA
+ .word LIT,EXIT,COMMA
.word QREVEAL,LEFTBRACKET,EXIT
FORTHWORD "IMMEDIATE"
; https://forth-standard.org/standard/core/IMMEDIATE
; IMMEDIATE -- make last definition immediate
-IMMEDIATE MOV &LAST_NFA,Y ; Y = NFA|unused_PA_reg (as lure for :NONAME)
- BIS.B #1,0(Y) ;4 FIND process more easier with bit0 than bit7
+IMMEDIATE MOV &LAST_NFA,Y ;3
+ BIS.B #1,0(Y) ;4 FIND process more easier with bit0 for IMMEDIATE flag than bit7
MOV @IP+,PC
FORTHWORD "CREATE"
CREATE CALL #HEADER ; -- W = DP
MOV #DOCON,-4(W) ;4 -4(W) = CFA = CALL rDOCON
MOV W,-2(W) ;3 -2(W) = PFA = W = next address
- JMP REVEAL ; to link the definition in vocabulary
+CREATENEXT JMP REVEAL ; to link the definition in vocabulary
FORTHWORD "DOES>"
; https://forth-standard.org/standard/core/DOES
MOV #DODOES,0(W) ; replace CALL rDOCON of CREATE by new CFA: CALL rDODOES
MOV IP,2(W) ; replace PFA by the address after DOES> as execution address
MOV @RSP+,IP ; which ends the..
- MOV @IP+,PC ; ..of a CREATE definition.
+NEXT_ADR MOV @IP+,PC ; ..of a CREATE definition.
FORTHWORD ":NONAME"
; https://forth-standard.org/standard/core/ColonNONAME
; Y is the LAST_NFA lure value for REVEAL and IMMEDIATE
; ...because we don't want to modify the word set !
PUSH #COLONNEXT ; define COLONNEXT as HEADEREND RET
-HEADERLESS SUB #2,PSP ; common part of :NONAME and CODENNM
+HEADERLESS SUB #2,PSP ; -- TOS common part of :NONAME and CODENNM
MOV TOS,0(PSP) ;
MOV &DP,W ;
BIT #1,W ;
ADDC #0,W ; W = aligned CFA
MOV W,TOS ; -- xt aligned CFA of :NONAME | CODENNM
- MOV #212h,X ; MOV @X,-2(Y) writes to 210h = unused PA register address (lure for REVEAL and IMMEDIATE)
- MOV X,Y ; MOV Y,0(X) writes to 212h = unused PA register address (lure for REVEAL)
+ MOV #212h,X ; MOV Y,0(X) writes to 212h = unused PA register address (lure for REVEAL)
+ MOV X,Y ; MOV @X,-2(Y) writes to 210h = unused PA register address (lure for REVEAL and IMMEDIATE)
JMP HEADEREND ;
;; https://forth-standard.org/standard/core/DEFER
; MOV #NEXT_ADR,-2(W) ;3 second CELL = ...mNEXT : do nothing by default
; JMP REVEAL ; to link created word in vocabulary
-; IS <name> xt --
-
; used like this (high level defn.):
; DEFER DISPLAY create a "do nothing" definition (2 CELLS)
; inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY
; or in a definition : ... ['] U. IS DISPLAY ... ;
-; KEY, EMIT, ACCEPT are examples of DEFERred words
+; KEY, EMIT, CR, ACCEPT are examples of DEFERred words
+
+; IS <name> xt --
FORTHWORDIMM "IS" ; immediate
IS PUSH IP
CMP #0,&STATE
DEFERSTORE MOV @PSP+,2(TOS) ; -- CFA_DEFERed_WORD xt --> [PFA_DEFERed_WORD]
MOV @PSP+,TOS ; --
MOV @IP+,PC ;
-
IS_COMPILE mASM2FORTH
- .word BRACTICK ; find the word, compile its CFA as literal
- .word lit,DEFERSTORE,COMMA ; compile DEFERSTORE
- .word EXIT
+ .word BRACTICK ; find the word, compile its CFA as literal
+ .word LIT,DEFERSTORE ; compile DEFERSTORE
+ .word COMMA,EXIT
+;-------------------------------------------------------------------------------
+; ASSEMBLER building definitions
+;-------------------------------------------------------------------------------
FORTHWORD "CODE" ; a CODE word must be finished with ENDCODE
ASMCODE CALL #HEADER ; (that sets CFA and PFA)
-ASMCODE1 SUB #4,&DP ; remove default CFA and PFA
-ASMCODE2
- .IFDEF EXTENDED_ASM
- MOV #0,&RPT_WORD ; clear RPT instruction
- .ENDIF
- JMP ASSEMBLER ; add ASSEMBLER in CONTEXT stack
+ASMCODE1 SUB #4,&DP ; remove default room for CFA + PFA
+ .IFDEF VOCABULARY_SET ; if VOCABULARY_SET
+ JMP hidden ; add hidden word set in CONTEXT stack
+ .ELSE ;
+hidden MOV &CONTEXT,&CONTEXT+2 ; add hidden word set in CONTEXT stack
+ MOV #BODYhidden,&CONTEXT;
+ MOV @IP+,PC ;
+ .ENDIF
; HDNCODE (hidden CODE) is used to define a CODE word which must not to be executed by FORTH interpreter
-; i.e. typically an assembler word called by CALL and ended by RET, or an interrupt routine ended by RETI.
-; HDNCODE words are only usable in ASSEMBLER definitions.
+; i.e. typically the case of an assembler definition called by CALL and ended by RET, or an interrupt routine.
+; HDNCODE words are only usable in ASSEMBLER CONTEXT.
FORTHWORD "HDNCODE"
- MOV #BODYASSEMBLER,&CURRENT ; select ASSEMBLER word set to link this HDNCODE definition
- JMP ASMCODE
-
- asmword "ENDCODE" ; test PSP balancing then restore previous CONTEXT
-ENDCODE mDOCOL ; and set CURRENT = CONTEXT (to also terminate HDNCODE definitions)
- .word QREVEAL
+ PUSH &CURRENT ; save CURRENT
+ MOV #BODYhidden,&CURRENT; select hidden word set as CURRENT to link HDNCODE definition
+ mDOCOL
+ .word ASMCODE
mNEXTADR
MOV @RSP+,IP
-ENDCODEND MOV &CONTEXT+2,&CURRENT ;5 to do DEFINITIONS (before previous)
- JMP PREVIOUS ;
+ MOV @RSP+,&CURRENT ; restore CURRENT
+ MOV @IP+,PC ;
FORTHWORD "CODENNM" ; CODENoNaMe is the assembly counterpart of :NONAME
CODENNM PUSH #ASMCODE1 ; define HEADERLESS return
JMP HEADERLESS ; that makes room for CFA and PFA
+ asmword "ENDCODE" ;
+ENDCODE MOV IP,T ; T is unused by QREVEAL
+ mASM2FORTH ;
+ .word QREVEAL
+ mNEXTADR
+ MOV T,IP
+ .IFDEF VOCABULARY_SET
+ JMP PREVIOUS ; remove hidden word set from CONTEXT stack
+ .ELSE ;
+PREVIOUS MOV #BODYFORTH,&CONTEXT ; remove hidden word set from CONTEXT stack
+ MOV #0,&CONTEXT+2 ;
+ MOV @IP+,PC
+ .ENDIF
+
; here are 3 words used to switch FORTH <--> ASSEMBLER
-; COLON -- compile DOCOL, remove ASSEMBLER from CONTEXT and CURRENT, switch to compilation state
+; COLON -- compile DOCOL, remove ASSEMBLER from CONTEXT stack, switch to compilation state
asmword "COLON"
MOV &DP,W
.SWITCH DTC
MOV #DOCOL,0(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = XDOCOL)
ADD #2,&DP
.CASE 2
- MOV #120Dh,0(W) ; compile PUSH IP
-COLON1 MOV #DOCOL,2(W) ; compile CALL R4 = rDOCOL
+ MOV #120Dh,0(W) ; compile PUSH IP
+COLON1 MOV #DOCOL,2(W) ; compile CALL R4 = rDOCOL
ADD #4,&DP
.CASE 3 ; inlined DOCOL
- MOV #120Dh,0(W) ; compile PUSH IP
-COLON1 MOV #400Dh,2(W) ; compile MOV PC,IP
+ MOV #120Dh,0(W) ; compile PUSH IP
+COLON1 MOV #400Dh,2(W) ; compile MOV PC,IP
MOV #522Dh,4(W) ; compile ADD #4,IP
MOV #4D30h,6(W) ; compile MOV @IP+,PC
ADD #8,&DP ;
.ENDCASE ; DTC
-COLON2 MOV #-1,&STATE ;3 enter in compile state
- JMP ENDCODEND ;2 to do PREVIOUS DEFINITIONS
+COLON2 MOV #-1,&STATE ; enter in compile state
+ JMP PREVIOUS ; to restore CONTEXT
; LO2HI -- same as COLON but without saving IP
asmword "LO2HI"
MOV &DP,W ; W = HERE+2
MOV W,-2(W) ; compile HERE+2 to HERE
MOV #0,&STATE ; LEFTBRACKET
- JMP ASMCODE2 ; add ASSEMBLER in context
+ JMP hidden ; to save CURRENT and add ASSEMBLER in context
;-------------------------------------------------------------------------------
; WORDS SET for VOCABULARY, not ANS compliant,
;-------------------------------------------------------------------------------
.IFDEF VOCABULARY_SET
+
FORTHWORD "WORDSET"
;X VOCABULARY -- create a new word_set
VOCABULARY mDOCOL
.word CREATE
+ mNEXTADR ; W = BODY
.SWITCH THREADS
.CASE 1
- .word lit,0,COMMA ; W = DP
- mNEXTADR ;
+ MOV #0,0(W) ; W = BODY, init thread with 0
+ ADD #2,W ;
.ELSECASE
- mNEXTADR ; W = DP
MOV #THREADS,X ; count
-VOCABULOOP MOV #0,0(W) ; DP = BODY first
+VOCABULOOP MOV #0,0(W) ; init threads area with 0
ADD #2,W
SUB #1,X
JNZ VOCABULOOP
- .ENDCASE ; W = DP
- MOV &LASTVOC,0(W)
+ .ENDCASE ; W = BODY + THREADS*2
+ MOV &LASTVOC,0(W) ; link LASTVOC
MOV W,&LASTVOC
- ADD #2,W
- MOV W,&DP ; update DP
- mASM2FORTH
- .word DOES
- .ENDIF ; VOCABULARY_SET
+ ADD #2,W ; update DP
+ MOV W,&DP ;
+ mASM2FORTH ;
+ .word DOES ;
+;-----------------------------------;
VOCDOES mNEXTADR ; adds WORD-SET first in context stack
- .IFDEF VOCABULARY_SET
-ALSO MOV #14,X ;2 -- move up 7 words, first word in last
+ALSO MOV #14,X ;2 -- move up 7 words, first word in last
ALSOLOOP SUB #2,X
MOV CONTEXT(X),CONTEXT+2(X) ; X=src < Y=dst copy W bytes beginning with the end
JNZ ALSOLOOP
- .ELSE ; VOCABULARY_SET off ; VOCDOES is used only by the assembler to switch from HIlevel to LOlevel environments
- MOV #BODYFORTH,&CONTEXT+2;4 copy BODYFORTH --> 2th cell of CONTEXT
- .ENDIF ; VOCABULARY_SET
- MOV TOS,&CONTEXT ;3 copy word-set BODY --> first cell of CONTEXT
+ MOV TOS,CONTEXT(X) ;3 copy word-set BODY --> first cell of CONTEXT
MOV #DROPEXIT,PC
- .IFDEF VOCABULARY_SET
- FORTHWORD "FORTH"
- .ENDIF
-;X FORTH -- ; add FORTH as first context word-set
-FORTH ; leave BODYFORTH on the stack and run VOCDOES
- CALL rDODOES ; Code Field Address (CFA) of FORTH
-PFAFORTH .word VOCDOES ; Parameter Field Address (PFA) of FORTH
+ FORTHWORD "DEFINITIONS"
+;X DEFINITIONS -- set last context vocabulary as entry for further defining words
+DEFINITIONS MOV &CONTEXT,&CURRENT
+ MOV @IP+,PC
+
+ FORTHWORD "ONLY"
+;X ONLY -- fill the context stack with 0 to access only the first word-set, ex.: FORTH ONLY
+ MOV #8,T
+ MOV #0,X
+ONLY_LOOP ADD #2,X
+ MOV #0,CONTEXT(X)
+ SUB #1,T
+ JNZ ONLY_LOOP
+ MOV @IP+,PC
+
+ FORTHWORD "PREVIOUS"
+;X PREVIOUS -- pop first word-set out of context stack
+PREVIOUS MOV #8,Y ;1 move down 8 words, first with CONTEXT+2 addr, last with NULL_WORD one
+ MOV #CONTEXT+2,X ;2 X = org = CONTEXT+2, X-2 = dst = CONTEXT
+ CMP #0,0(X) ;3 [org] = 0 ?
+ JZ PREVIOUSEND ;2 to avoid scratch of the first CONTEXT cell by human mistake
+PREVIOUSLOO MOV @X+,-4(X) ;4
+ SUB #1,Y ;1
+ JNZ PREVIOUSLOO ;2 8~ loop * 8 = 64 ~
+PREVIOUSEND MOV @IP+,PC ;4
+
+ FORTHWORD "FORTH" ; add FORTH as first context word-set
+ CALL rDODOES
+ .word VOCDOES
+
+ .ENDIF ; VOCABULARY_SET
+
BODYFORTH .word lastforthword ; BODY of FORTH
.SWITCH THREADS
.CASE 2
voclink .set $-2
.IFDEF VOCABULARY_SET
-; FORTHWORD "ASSEMBLER"
FORTHWORD "hidden" ; cannot be found by FORTH interpreter because the string is not capitalized
- .ENDIF
-;X ASSEMBLER -- ; add ASSEMBLER as first context word-set
-ASSEMBLER CALL rDODOES ; leave BODYASSEMBLER on the stack and run VOCDOES
+hidden CALL rDODOES
.word VOCDOES
-BODYASSEMBLER .word lastasmword
+ .ENDIF
+BODYhidden .word lastasmword ; BODY of hidden words
.SWITCH THREADS
.CASE 2
.word lastasmword1
.word voclink
voclink .set $-2
- .IFDEF VOCABULARY_SET
- FORTHWORD "PREVIOUS"
-;X PREVIOUS -- pop first word-set out of context stack
-PREVIOUS MOV #8,Y ;1 move down 8 words, first with CONTEXT+2 addr, end when NULL_WORD is moved
- MOV #CONTEXT+2,X ;2 X = CONTEXT+2 = org, X-2 = CONTEXT = dst
-PREVIOUSLOO CMP #0,0(X) ;3 [org] = 0 ?
- JZ PREVIOUSEND ;2 to avoid scratch of the first CONTEXT cell by human mistake, then to skip useless loops
- MOV @X+,-4(X) ;4
- SUB #1,Y ;1
- JNZ PREVIOUSLOO ;2 7~ loop * 8 = 56 ~
-PREVIOUSEND MOV @IP+,PC ;4
- .ELSE ;
-PREVIOUS MOV #BODYFORTH,&CONTEXT
-ONLY MOV #0,&CONTEXT+2 ; then execute ONLY
- MOV @IP+,PC
- .ENDIF ; VOCABULARY_SET
-
- .IFDEF VOCABULARY_SET
- FORTHWORD "ONLY"
-;X ONLY -- cut the context stack to access only the first word-set, ex.: FORTH ONLY
-ONLY MOV #0,&CONTEXT+2
- MOV @IP+,PC
-
- FORTHWORD "DEFINITIONS"
-;X DEFINITIONS -- set last context vocabulary as entry for further defining words
-DEFINITIONS MOV &CONTEXT,&CURRENT
- MOV @IP+,PC
- .ENDIF ; VOCABULARY_SET
-
;-------------------------------------------------------------------------------
-; FASTFORTH environment management: DP, LASTVOC, CURRENT, CONTEXT and THREADS
+; FASTFORTH environment management: RST_SET RST_RET MARKER
;-------------------------------------------------------------------------------
-ENV_COPY
+ENV_COPY ; mini MOVE T words from X to W
.IFDEF VOCABULARY_SET
- MOV #24,T ; bytes count of extended RST environment: DP,LASTVOC,CURRENT,CONTEXT(8),null_word
+ MOV #12,T ; words count for extended environment: DP,LASTVOC,CURRENT,CONTEXT(8),NULL_WORD
.ELSE
- MOV #10,T ; bytes count of RST environment: DP,LASTVOC,CURRENT,CONTEXT(2)
+ MOV #4,T ; words count for basic environment: DP,LASTVOC,CURRENT,CONTEXT
.ENDIF
-ENV_LOOP MOV @X+,0(W)
- ADD #2,W
- SUB #2,T ; words-1
- JNZ ENV_LOOP
+MOV_WORDS MOV @X+,0(W) ; 4 X = src, W = dst, T = words count
+ ADD #2,W ; 1
+ SUB #1,T ; 1 words count -1
+ JNZ MOV_WORDS ; 2
MOV @RSP+,PC
FORTHWORD "RST_SET" ; define actual environment as new RESET environment
FORTHWORD "RST_RET" ; init / return_to_previous RESET or MARKER environment
RST_RET MOV #RST_DP,X ; org = FRAM value (first RST_DP), see \inc\ThingsInFirst.inc
- MOV @X,S ; S = restored DP, used below for comparaison with NFAs
MOV #DP,W ; dst = RAM value (first DP)
+ MOV @X,S ; S = restored DP, used below for comparaison with NFAs below
CALL #ENV_COPY ; copy environment FRAM RST --> RAM, use T,W,X
-;-----------------------------------;
- MOV &LASTVOC,W ; W = init/restored LASTVOC
- .SWITCH THREADS ; init/restore THREAD(s) with NFAs value < init/restored DP, for all word set
+ MOV &LASTVOC,W ; W = init/restored LASTVOC in RAM
+ .SWITCH THREADS ; init/restore THREAD(s) with NFAs value < DP value, for all word set
.CASE 1 ; mono thread word-set
MARKALLVOC MOV W,Y ; W=VLK Y = VLK
-MRKWORDLOOP MOV -2(Y),Y ; W=VLK Y = [THD_n] then [LFA] = NFA
+MRKWORDLOOP MOV -2(Y),Y ; W=VLK Y = [THD] then [LFA] = NFA
CMP Y,S ; Y=NFA S=DP CMP = S-Y : OLD_DP-NFA
JNC MRKWORDLOOP ; loop back if S<Y : OLD_DP<NFA
MOV Y,-2(W) ; W=VLK X=THD Y=NFA refresh thread with good NFA
JNZ MARKALLVOC ; W=VLK-1 no : loopback
MOV @IP+,PC ;
-;-------------------------------------------------------------------------------
-; PUC 7 : SELECT RST_RET|DEEP_RESET <== INIT_FORTH <== (PUC,SYS,QABORT)
-;-------------------------------------------------------------------------------
-SEL_RST_DEP CMP #0,TOS ;
- JGE RST_RET ; if TOS >= 0
-;-----------------------------------;
-; DEEP RESET ; if TOS < 0
-;-----------------------------------;
-; DEEP INIT SIGNATURES AREA ;
-;-----------------------------------;
- MOV #16,X ; max known SIGNATURES length = 12 bytes
-SIGNATLOOP SUB #2,X ;
- MOV #-1,SIGNATURES(X) ; reset signatures; WARNING ! DON'T CHANGE IMMEDIATE VALUE !
- JNZ SIGNATLOOP ;
-;-----------------------------------;
-; DEEP INIT VECTORS INT ; X = 0 ;-)
-;-----------------------------------;
- MOV #RESET,-2(X) ; write RESET at addr X-2 = FFFEh
-INIVECLOOP SUB #2,X ;
- MOV #COLD,-2(X) ; -2(X) = FFFCh first
- CMP #0FFACh+2,X ; init 41 vectors, FFFCh down to 0FFACh
- JNZ INIVECLOOP ; all vectors are initialised to execute COLD routine
-;-----------------------------------;
-; DEEP INIT Terminal Int vector ;
-;-----------------------------------;
- MOV #DEEP_ORG,X ; DEEP_ORG values are in FRAM INFO, see \inc\ThingsInFirst.inc
- MOV @X+,&TERM_VEC ; TERMINAL_INT as default vector --> FRAM TERM_VEC
-;-----------------------------------;
-; DEEP INIT FRAM RST values ; 8 word values
-;-----------------------------------;
- MOV #RST_LEN,T ; bytes count
- MOV #RST_ORG,W ; W = dst, X = org
- CALL #ENV_LOOP ;
- MOV #0,&RST_CONTEXT+2 ; to do FORTH ONLY
-;-----------------------------------;
-; WARM INIT threads of all word set ;
-;-----------------------------------;
- JMP RST_RET ; then go to DUP|PUCNEXT, resp. in QABORT|RESET
-;-----------------------------------;
-
; https://forth-standard.org/standard/core/MARKER
; MARKER
;name Execution: ( -- )
;definition of name. Remove the definition of name and all subsequent definitions. Restoration
;of any structures still existing that could refer to deleted definitions or deallocated data space is
;not necessarily provided. No other contextual information such as numeric base is affected.
-
-; FastForth provides all that is necessary for a real time application with MARKER definition,
-; by adding a call to a custom subroutine to restore all user environment.
; the FORTH environment is it automaticaly restored.
-MARKER_DOES ; restores RST environment saved by MARKER defn.,
- ; executes user defined subroutine (RET_ADR by default),
- ; then executes RST_RET.
+; FastForth provides all that is necessary for a real time application,
+; by adding a call to a custom asm subroutine to restore all user environment.
+
+MARKER_DOES ; execution part of MARKER definition
mNEXTADR ; -- BODY
.IFDEF VOCABULARY_SET
- MOV TOS,X ; X = org (first : BODY=MARKER_DP)
+ MOV TOS,X ; X = org (first : BODY = MARKER_DP)
MOV #RST_DP,W ; W = dst (first : RST_DP), see \inc\ThingsInFirst.inc
- CALL #ENV_COPY ; copy FORTH environment FRAM MARKER --> FRAM RST
- MOV X,TOS ; -- RET_ADR by default
+ CALL #ENV_COPY ; restore previous FORTH environment from FRAM MARKER to FRAM RST
+ MOV X,TOS ; -- USER_DOES RET_ADR by default
.ELSE
- MOV @TOS+,&RST_DP ;
+ MOV @TOS+,&RST_DP ; -- USER_DOES only RST_DP is restored
.ENDIF
- CALL @TOS+ ; -- USER_BODY executes user defined asm subroutine (RET_ADR by default), IP and TOS are free
+ CALL @TOS+ ; -- USER_PARAM executes defined USER_DOES subroutine (RET_ADR by default),
+ ; IP is free, TOS is the address of first USER parameter
MOV @PSP+,TOS ; --
MOV @RSP+,IP ;
- JMP RST_RET ; then performs RST_RET
+ JMP RST_RET ; which restores previous FORTH environment in RAM
FORTHWORD "MARKER" ; definition part
;( "<spaces>name" -- )
;Skip leading space delimiters. Parse name delimited by a space. Create a definition for name
;with the execution semantics defined above.
;-------------------------------------------------------------------------------
-;before that, it execute DOES part of previous definition if already exists.
- PUSH &TOIN
+; before that, if already defined, "name" executes its MARKER_DOES part.
+; i.e. does: [DEFINED] <name> [IF] <name> [THEN]
+; MARKER <name>
+;-------------------------------------------------------------------------------
+ PUSH &TOIN ; -- save >IN
mDOCOL
- .word BL,WORDD,FIND
- .word QFBRAN,MARKER_NEXT
- .word DUP,EXECUTE
-MARKER_NEXT mNEXTADR
- MOV @PSP+,TOS ;
- MOV @RSP+,IP
- MOV @RSP+,&TOIN
+ .word BL_WORD,FIND ; -- addr flag
+ .word QFBRAN,MARKER_NEXT; -- addr if not found
+ .word DUP,EXECUTE ; -- MARKER_DOES execute it
+MARKER_NEXT mNEXTADR ; -- addr|MARKER_DOES
+ MOV @PSP+,TOS ; --
+ MOV @RSP+,IP ;
+ MOV @RSP+,&TOIN ; restore >IN for HEADER
;-------------------------------------------------------------------------------
- CALL #HEADER ;4 W = DP, Y = NFA,
+ CALL #HEADER ;4 W = BODY, Y = NFA,
MOV #1285h,-4(W) ;4 CFA = CALL rDODOES
MOV #MARKER_DOES,-2(W) ;4 PFA = MARKER_DOES
SUB #2,Y ;1 Y = NFA-2 = LFA = DP to be restored, W = FRAM MARKER_DDP
MOV Y,&DP ; Y = previous DP (just before MARKER definition)
MOV #DP,X ; X = org = RAM DP, W = dst = MARKER_BODY
CALL #ENV_COPY ; copy environment RAM --> FRAM MARKER
- MOV #RET_ADR,0(W) ;4 user defined subroutine by default = RET_ADR
+ MOV #RET_ADR,0(W) ;4 USER_DOES default subroutine = RET_ADR
ADD #2,W ;1
MOV W,&DP ;4 set new RAM DP (after the end of MARKER definition)
.ELSE
MOV Y,0(W) ; DP to be restored
- MOV #RET_ADR,2(W) ; MARKER subroutine
+ MOV #RET_ADR,2(W) ; USER_DOES default subroutine = RET_ADR
ADD #4,&DP ;
.ENDIF
-LINK_NFA MOV &LAST_NFA,Y ; if no error, link this definition in its thread
- MOV &LAST_THREAD,X ;
-REVEAL MOV @X,-2(Y) ; [LAST_THREAD] --> LFA (for NONAME: LFA --> 210h unused PA reg)
- MOV Y,0(X) ; LAST_NFA --> [LAST_THREAD] (for NONAME: [LAST_THREAD] --> 212h unused PA reg)
-REVEAL_END MOV @IP+,PC
+ JMP LINK_NFA ; then NEXT
+
+;-------------------------------------------------------------------------------
+; PUC 7 : SELECT RST_RET|DEEP_RESET <== INIT_FORTH <== (PUC,SYS,QABORT)
+;-------------------------------------------------------------------------------
+SEL_RST CMP #0,TOS ;
+ JGE RST_RET ; RST_RET if TOS >= 0
+;-----------------------------------;
+; DEEP RESET ; DEEP_RESET if TOS < 0
+;-----------------------------------;
+; DEEP INIT SIGNATURES AREA ;
+;-----------------------------------;
+ MOV #16,X ; max known SIGNATURES length = 12 bytes
+SIGNATLOOP SUB #2,X ;
+ MOV #-1,SIGNATURES(X) ; reset signatures; WARNING ! DON'T CHANGE IMMEDIATE VALUE !
+ JNZ SIGNATLOOP ;
+;-----------------------------------;
+; DEEP INIT VECTORS INT ; X = 0 ;-)
+;-----------------------------------;
+ MOV #RESET,-2(X) ; write RESET at addr X-2 = FFFEh
+INIVECLOOP SUB #2,X ;
+ MOV #COLD,-2(X) ; -2(X) = FFFCh first
+ CMP #0FFACh+2,X ; init 41 vectors, FFFCh down to 0FFACh
+ JNZ INIVECLOOP ; all vectors are initialised to execute COLD routine
+;-----------------------------------;
+; DEEP INIT Terminal Int vector ;
+;-----------------------------------;
+ MOV #DEEP_ORG,X ; DEEP_ORG values are in FRAM INFO, see \inc\ThingsInFirst.inc
+ MOV @X+,&TERM_VEC ; TERMINAL_INT as default vector --> FRAM TERM_VEC
+;-----------------------------------;
+; DEEP INIT FRAM RST values ; [COLD,SOFT,HARD,BACKGRND]_APP + RST_[DP,LASTVOC,CURRENT,CONTEXT]
+;-----------------------------------;
+ MOV #RST_LEN/2,T ; T = words count
+ MOV #RST_ORG,W ; W = dst, X = org
+ CALL #MOV_WORDS ;
+ MOV #0,&RST_CONTEXT+2 ; to do FORTH ONLY
+;-----------------------------------;
+ .IFDEF BOOTLOADER ; does NOBOOT:
+ MOV #WARM,&PUCNEXT ; removes XBOOT from PUC chain.
+ .ENDIF
+;-----------------------------------;
+; WARM INIT threads of all word set ;
+;-----------------------------------;
+ JMP RST_RET ; then go to DUP|PUCNEXT, resp. in QABORT|RESET
+;-----------------------------------;
;===============================================================================
-; ASSEMBLER OPTION
+; ASSEMBLER KERNEL OPTION
;===============================================================================
- .IFDEF EXTENDED_ASM
+ .IFDEF LARGE_DATA
.include "forthMSP430FR_EXTD_ASM.asm"
.ELSE
.include "forthMSP430FR_ASM.asm"
.ENDIF
.IFDEF SD_CARD_LOADER
-;-------------------------------------------------------------------------------
-; SD CARD OPTIONS
-;-------------------------------------------------------------------------------
+;===============================================================================
+; SD CARD KERNEL OPTIONS
+;===============================================================================
.include "forthMSP430FR_SD_LowLvl.asm" ; SD primitives
.include "forthMSP430FR_SD_INIT.asm" ; return to INIT_TERM; without use of IP,TOS
.include "forthMSP430FR_SD_LOAD.asm" ; SD LOAD driver
-; .include "forthMSP430FR_SD_LOAD_next.asm" ; SD LOAD driver
.IFDEF SD_CARD_READ_WRITE
.include "forthMSP430FR_SD_RW.asm" ; SD Read/Write driver
-; .include "forthMSP430FR_SD_RW_next.asm" ; SD Read/Write driver
.ENDIF
.ENDIF
+
+;===============================================================================
+; ADDONS OPTIONS; if included here they will be protected against Deep_RST
+;===============================================================================
+ .IFDEF CORE_COMPLEMENT
+;-------------------------------------------------------------------------------
+; COMPLEMENT of definitions to pass ANS94 CORETEST
+;-------------------------------------------------------------------------------
+ .include "ADDON/CORE_ANS.asm"
+ .ENDIF
+
+ .IFDEF UTILITY
;-------------------------------------------------------------------------------
-; ADD HERE YOUR CODE TO BE INTEGRATED IN KERNEL (protected against Deep_RST)
+; UTILITY WORDS
+;-------------------------------------------------------------------------------
+ .include "ADDON/UTILITY.asm"
+ .ENDIF
+
+ .IFDEF FIXPOINT
+;-------------------------------------------------------------------------------
+; FIXED POINT OPERATORS
+;-------------------------------------------------------------------------------
+ .include "ADDON/FIXPOINT.asm"
+ .ENDIF
+
+ .IFDEF DOUBLE
+;-------------------------------------------------------------------------------
+; DOUBLE word set
+;-------------------------------------------------------------------------------
+ .include "ADDON/DOUBLE.asm"
+ .ENDIF
+
+ .IFDEF SD_CARD_LOADER
+ .IFDEF SD_TOOLS
+;-------------------------------------------------------------------------------
+; BASIC SD TOOLS
+;-------------------------------------------------------------------------------
+ .include "ADDON/SD_TOOLS.asm"
+ .ENDIF
+ .ENDIF
+
+;-------------------------------------------------------------------------------
+; ADD HERE YOUR CODE TO BE INTEGRATED IN KERNEL and protected against Deep_RST
;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
-;
-; .include "\ADDON\CORE_ANS.asm"
-; .include "\ADDON\UTILITY.asm"
-; .include "\ADDON\FIXPOINT.asm"
; .include "YOUR_CODE.asm"
-;
;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
; ADD HERE YOUR CODE TO BE INTEGRATED IN KERNEL (protected against Deep_RST)
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
-; RESOLVE ASSEMBLY PTR, init interrupt Vectors
+; RESOLVE ASSEMBLY pointers, init interrupt Vectors
;-------------------------------------------------------------------------------
.include "ThingsInLast.inc"
; ----------------------------------------------------------------------
; MOV(.B) SR,dst is coded as follow : MOV(.B) R2,dst ; 1 cycle, one word AS=00 (register mode)
; MOV(.B) #0,dst is coded as follow : MOV(.B) R3,dst ; 1 cycle, one word AS=00 (register mode)
-; MOV(.B) &EDE,dst is coded as follow : MOV(.B) EDE(R2),dst ; 3 cycles, two words AS=01 ( x(reg) mode)
; MOV(.B) #1,dst is coded as follow : MOV(.B) (R3),dst ; 1 cycle, one word AS=01 ( x(reg) mode)
; MOV(.B) #4,dst is coded as follow : MOV(.B) @R2,dst ; 1 cycle, one word AS=10 ( @reg mode)
; MOV(.B) #2,dst is coded as follow : MOV(.B) @R3,dst ; 1 cycle, one word AS=10 ( @reg mode)
; MOV(.B) #8,dst is coded as follow : MOV(.B) @R2+,dst ; 1 cycle, one word AS=11 ( @reg+ mode)
; MOV(.B) #-1,dst is coded as follow : MOV(.B) @R3+,dst ; 1 cycle, one word AS=11 ( @reg+ mode)
; ----------------------------------------------------------------------
+; MOV(.B) &EDE,dst is coded as follow : MOV(.B) EDE(R2),dst ; 3 cycles, two words AS=01 ( x(reg) mode)
; MOV(.B) #xxxx,dst is coded as follow: MOV(.B) @PC+,dst ; 2 cycles, two words AS=11 ( @reg+ mode)
; ----------------------------------------------------------------------
-; PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC
-; PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
+; PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rDOVAR,rDOCON,rDODOES, rDOCOL, R3, SR,RSP, PC
+; PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0
; example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack
;
-; POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP
-; POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
+; POPM order : PC,RSP, SR, R3, rDOCOL,rDODOES,rDOCON,rDOVAR, Y, X, W, T, S, IP,TOS,PSP
+; POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15
; example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack
; common code for maxi 3 successive SearchARG: SearchARG, SearchARG+Offset, SearchARG-offset
; leave PFA of VARIABLE, [PFA] of CONSTANT, User_Parameter_Field_Address of MARKER_DOES, CFA for all others.
; if the ARGument is not found after those three SearchARg, the 'not found' error is issued by SrchOfst.
+; ----------------------------------;
SearchARGn PUSH &TOIN ; push TOIN, for next SearchARGn if any
mASM2FORTH ; -- sep sep = ','|'('|' '
.word WORDD,FIND ; -- addr search string name first
- .word QFBRAN,SrchArgNum ; -- addr if string name not found
+ .word QFBRAN,SRCHARGNUM ; -- addr if string name not found
COMPUTEARG mNEXTADR ; -- CFA of named definition
MOV @TOS+,S ; -- PFA S=DOxxx
QDOVAR SUB #1287h,S ; CFA = DOxxx = 1287h = CALL R7 = rDOVAR
QMARKER CMP #MARKER_DOES,0(TOS) ; -- PFA search if PFA = [MARKER_DOES]
JNZ ISOTHER ; -- PFA
.IFDEF VOCABULARY_SET ; -- PFA
- ADD #30,TOS ; -- UPFA+2 skip room for DP, CURRENT, CONTEXT(8), null_word, LASTVOC, RET_ADR 2+(2+2+16+2+2+2) +2 bytes
+ISMARKER ADD #30,TOS ; -- UPFA+2 skip room for DP, CURRENT, CONTEXT(8), null_word, LASTVOC, RET_ADR 2+(2+2+16+2+2+2) +2 bytes
.ELSE ;
- ADD #8,TOS ; -- UPFA+2 skip room for DP, RET_ADR 2+(2+2) +2 bytes
+ISMARKER ADD #8,TOS ; -- UPFA+2 skip room for DP, RET_ADR 2+(2+2) +2 bytes
.ENDIF ;
ISOTHER SUB #2,TOS ; -- CFA|UPFA UPFA = MARKER_DOES User_Parameter_Field_Address
ARGFOUND ADD #2,RSP ; remove TOIN
SEARCHRET MOV @RSP+,PC ;24 SR(Z)=0 if ARG found
-SrchArgNum .word QNUMBER ;
- .word QFBRAN,ARGNOTFOUND; -- addr with SR(Z)=1
- .word ARGFOUND ; -- value no return
+SRCHARGNUM .word QNUMBER ;
+ .word QFBRAN,ARGNOTFOUND; -- addr
+ .word ARGFOUND ; -- value
ARGNOTFOUND mNEXTADR ; -- x
MOV @RSP+,&TOIN ; restore TOIN
MOV @RSP+,PC ;32 SR(Z)=1 if ARG not found
+; ----------------------------------;
+; ----------------------------------;
SearchIndex
-; Search index of "xxxx(REG)," ; <== ComputeIDXpREG <== PARAM13
-; Search index of ",xxxx(REG)" ; <== ComputeIDXpREG <== PARAM21
+; Search index of "xxxx(REG)," ; <== ComputeIDXpREG <== PARAM1IDX
+; Search index of ",xxxx(REG)" ; <== ComputeIDXpREG <== PARAM2IDX
+; Search index of "xxxx(REG)," ; <== CALLA, MOVA
+; Search index of ",xxxx(REG)" ; <== MOVA
SUB #1,&TOIN ; move >IN back one (unskip 'R')
MOV #'(',TOS ; addr -- "(" as WORD separator to find xxxx of "xxxx(REG),"
SearchARG ; sep -- n|d or abort" not found"
-; Search ARG of "#xxxx," ; <== PARAM101
-; Search ARG of "&xxxx," ; <== PARAM111
-; Search ARG of ",&xxxx" ; <== PARAM111 <== PARAM201
- MOV TOS,W
+; Search ARG of "#xxxx," ; <== PARAM1SHARP
+; Search ARG of "&xxxx," ; <== PARAMXAMP
+; Search ARG of ",&xxxx" ; <== PARAMXAMP <== PARAM2AMP
+ MOV TOS,W ;
PUSHM #4,IP ; -- sep PUSHM IP,S,T,W as IP_RET,OPCODE,OPCODEADR,sep
CALL #SearchARGn ; first search argument without offset
JNZ SrchEnd ; -- ARG if ARG found
-SearchArgPo MOV #'+',TOS ; -- '+'
+SearchArgPl MOV #'+',TOS ; -- '+'
CALL #SearchARGn ; 2th search argument with '+' as separator
JNZ ArgPlusOfst ; -- ARG if ARG of ARG+offset found
-SearchArgMo MOV #'-',TOS ; -- '-'
+SearchArgMi MOV #'-',TOS ; -- '-'
CALL #SearchARGn ; 3th search argument with '-' as separator
SUB #1,&TOIN ; to handle offset with its minus sign
ArgPlusOfst PUSH TOS ; -- ARG save ARG on stack
MOV 2(RSP),TOS ; -- sep reload offset sep
SrchOfst mASM2FORTH ;
.word WORDD,QNUMBER ; -- Ofst|c-addr flag
- .word QFBRAN,NotFound ; -- c-addr no return, see INTERPRET
+ .word QFBRAN,FNOTFOUND ; -- c-addr no return, see INTERPRET
mNEXTADR ; -- Ofst
ADD @RSP+,TOS ; -- Arg+Ofst
SrchEnd POPM #4,IP ; POPM W,T,S,IP common return for SearchARG and SearchRn
; ----------------------------------------------------------------------
; DTCforthMSP430FR5xxx ASSEMBLER : search REG
; ----------------------------------------------------------------------
-; compute index of "xxxx(REG)," ; <== PARAM13, sep=','
-; compute index of ",xxxx(REG)" ; <== PARAM210, sep=' '
+; compute index of "xxxx(REG)," ; <== PARAM1IDX, sep=','
+; compute index of ",xxxx(REG)" ; <== PARAM2IDX, sep=' '
ComputeIDXpREG ; addr -- Rn|addr
CALL #SearchIndex ; -- xxxx aborted if not found
MOV &DP,X
MOV #')',TOS ; -- ")" prepare separator to search REG of "xxxx(REG)"
; search REG of "xxxx(REG)," separator = ')'
; search REG of ",xxxx(REG)" separator = ')'
-; search REG of "@REG," separator = ',' <== PARAM120
-; search REG of "@REG+," separator = '+' <== PARAM121
+; search REG of "@REG," separator = ',' <== PARAM1AT
+; search REG of "@REG+," separator = '+' <== PARAM1ATPL
SkipRSearchRn
ADD #1,&TOIN ; skip "R" in input buffer
-; search REG of "REG," separator = ',' <== PARAM13
-; search REG of ",REG" separator = BL <== PARAM21
+; search REG of "REG," separator = ',' <== PARAM1REG
+; search REG of ",REG" separator = ' ' <== PARAM2REG
SearchRn MOV &TOIN,W ;
PUSHM #4,IP ; PUSHM IP,S,T,W as IP_RET,OPCODE,OPCODEADR,TOIN
mASM2FORTH ; search xx of Rxx
mNEXTADR ; -- Rn number is found
CMP #16,TOS ; -- Rn
JNC SrchEnd ; -- Rn SR(Z)=0, Rn found,
- JC BOUNDERROR ; abort if Rn out of bounds
+ JC REGNUM_ERR ; abort if Rn out of bounds
REGNOTFOUND mNEXTADR ; -- addr SR(Z)=1, (case of @REG not found),
MOV @RSP,&TOIN ; -- addr restore TOIN, ready for next SearchRn
; DTCforthMSP430FR5xxx ASSEMBLER : INTERPRET FIRST OPERAND
; ----------------------------------------------------------------------
; PARAM1 separator -- ; parse input buffer until separator and compute first operand of opcode
- ; sep is comma for src and space for dst .
-PARAM1 JNZ PARAM10 ; -- sep if prefix <> 'R'
- CALL #SearchRn ; case of "REG,"
- JMP PARAM123 ; -- 000R REG of "REG," found, S=OPCODE=0
+ ; sep is "," for src TYPE II and " " for dst (TYPE II).
+PARAM1 JNZ QPARAM1SHARP ; -- sep if prefix <> 'R'
+PARAM1REG CALL #SearchRn ; case of "REG,"
+ JNZ REGSHFT8L ; -- 000R REG of "REG," found, S=OPCODE=0
; ----------------------------------;
-PARAM10 CMP.B #'#',W ; -- sep W=first char
- JNE PARAM11
-PARAM101 CALL #SearchARG ; -- xxxx abort if not found
+QPARAM1SHARP CMP.B #'#',W ; -- sep W=first char
+ JNE QPARAM1AMP
+PARAM1SHARP CALL #SearchARG ; -- xxxx abort if not found
MOV #0300h,S ; OPCODE = 0300h : MOV #0,dst is coded MOV R3,dst
CMP #0,TOS ; -- xxxx #0 ?
JZ PARAMENDOF
CMP #-1,TOS ; -- xxxx #-1 ?
JZ PARAMENDOF
MOV #0030h,S ; -- xxxx for all other cases : MOV @PC+,dst
-; endcase of "&xxxx," ; <== PARAM111
-; endcase of ",&xxxx" ; <== PARAM111 <== PARAM201
+; endcase of "&xxxx," ; <== PARAM1AMP
+; endcase of ",&xxxx" ; <== PARAMXAMP <== PARAM2AMP
StoreArg MOV &DP,X ;
ADD #2,&DP ; cell allot for arg
MOV TOS,0(X) ; compile arg
-; endcase of all "#xxxx," ;
-; endcase of all "&xxxx" ;
-; endcase of all "xxxx(REG)"|"@REG"|"@REG+" <== PARAM124
-PARAMENDOF MOV @PSP+,TOS ; --
- MOV @IP+,PC ; -- S=OPCODE,T=OPCODEADR
+ JMP PARAMENDOF
; ----------------------------------;
-PARAM11 CMP.B #'&',W ; -- sep
- JNE PARAM12
-; case of "&xxxx," ; -- sep search for "&xxxx,"
-PARAM110 MOV #0210h,S ; -- sep set code type : xxxx(R2) with AS=0b01 ==> x210h
-; case of "&xxxx,"|",&xxxx" ; <== PARAM201
-PARAM111 CALL #SearchARG ; -- arg abort if not found
- JMP StoreArg ; -- then ret
+QPARAM1AMP CMP.B #'&',W ; -- sep
+ JNE QPARAM1AT
+; case of "&xxxx," ; search for "&xxxx,"
+PARAM1AMP MOV #0210h,S ; set code type : xxxx(R2) with AS=0b01 ==> x210h
+; case of "&xxxx,"|",&xxxx" ; <== PARAM2AMP
+PARAMXAMP CALL #SearchARG ; -- sep
+ JMP StoreArg ; -- arg abort if not found
; ----------------------------------;
-PARAM12 CMP.B #'@',W ; -- sep
- JNE PARAM13
+QPARAM1AT CMP.B #'@',W ; -- sep
+ JNE PARAM1IDX
; case of "@REG,"|"@REG+,"
-PARAM120 MOV #0020h,S ; -- sep init OPCODE with indirect code type : AS=0b10
+PARAM1AT MOV #0020h,S ; -- sep init OPCODE with indirect code type : AS=0b10
CALL #SkipRSearchRn ; Z = not found
- JNZ PARAM123 ; -- Rn REG of "@REG," found
+ JNZ REGSHFT8L ; -- Rn REG of "@REG," found
; case of "@REG+," ; -- addr search REG of "@REG+"
-PARAM121 BIS #0010h,S ; change OPCODE from @REG to @REG+ type
+PARAM1ATPL BIS #0010h,S ; change OPCODE from @REG to @REG+ type
MOV #'+',TOS ; -- sep
- CALL #SearchRn ; -- Rn
-; case of "@REG+,"|"xxxx(REG)," ; <== PARAM13
-PARAM122 ; case of double separator: +, and ),
- CMP &SOURCE_LEN,&TOIN ; test OPCODE II parameter ending by REG+ or (REG) without comma,
- JZ PARAM123 ; i.e. >IN = SOURCE_LEN : don't skip char CR !
- ADD #1,&TOIN ; -- 000R skip "," ready for the second operand search
-; case of "@REG+,"|"xxxx(REG)," ;
-; case of "@REG," ; -- 000R <== PARAM120
-; case of "REG," ; -- 000R <== PARAM1
-PARAM123 SWPB TOS ; -- 0R00 swap bytes because it's not a dst REG typeI (not a 2 ops inst.)
-; case of ",REG" ; -- 000R <== PARAM2 (dst REG typeI)
-; case of ",xxxx(REG)" ; -- 000R <== PARAM21 (dst REG typeI)
-PARAM124 ADD TOS,S ; -- 0R00|000R
- JMP PARAMENDOF
-; ----------------------------------;
+ CALL #SearchRn ;
+ JNZ QSKIPCOMMA ; -- Rn REG found
+; ----------------------------------; REG not found
; case of "xxxx(REG)," ; -- sep
-PARAM13 BIS #0010h,S ; AS=0b01 for indexing address
- CALL #ComputeIDXpREG ; compile index xxxx and search REG of "(REG)"
- JMP PARAM122 ; -- Rn
+PARAM1IDX BIS #0010h,S ; AS=0b01 for indexing address
+ CALL #ComputeIDXpREG ; compile index xxxx and search REG of "(REG)", abort if xxxx not found
+; case of "@REG+,"|"xxxx(REG)," ; <== PARAM1ATPL
+QSKIPCOMMA CMP &SOURCE_LEN,&TOIN ; test OPCODE II parameter ending by REG+ or (REG) without comma,
+ JZ REGSHFT8L ; i.e. >IN = SOURCE_LEN : don't skip char CR !
+SKIPCOMMA ADD #1,&TOIN ; -- 000R with OPCODE I, skip "," ready for the second operand search
+; endcase of "@REG," ; -- 000R <== PARAM1AT
+; endcase of "REG," ; -- 000R <== PARAM1REG
+REGSHFT8L SWPB TOS ; -- 0R00 swap bytes because it's not a dst REG typeI (not a 2 ops inst.)
+; endcase of ",REG" ; -- 000R <== PARAM2REG (dst REG typeI)
+; endcase of ",xxxx(REG)" ; -- 000R <== PARAM2IDX (dst REG typeI)
+OPCODEPLREG ADD TOS,S ; -- 0R00|000R
+; endcase of all ; <== PARAM1SHARP PARAM1AMP PARAM2AMP
+PARAMENDOF MOV @PSP+,TOS ; --
+ MOV @IP+,PC ; -- S=OPCODE,T=OPCODEADR
; ----------------------------------;
; ----------------------------------------------------------------------
; DTCforthMSP430FR5xxx ASSEMBLER : INTERPRET 2th OPERAND
; ----------------------------------------------------------------------
-PARAM2 JNZ PARAM20 ; -- sep if prefix <> 'R'
- CALL #SearchRn ; -- sep case of ",REG"
- JMP PARAM124 ; -- 000R REG of ",REG" found
+PARAM2 JNZ QPARAM2AMP ; -- sep if prefix <> 'R'
+PARAM2REG CALL #SearchRn ; -- sep case of ",REG"
+ JNZ OPCODEPLREG ; -- 000R REG of ",REG" found
; ----------------------------------;
-PARAM20 CMP.B #'&',W ;
- JNZ PARAM21 ; '&' not found
+QPARAM2AMP CMP.B #'&',W ;
+ JNZ PARAM2IDX ; '&' not found
; case of ",&xxxx" ;
-PARAM201 BIS #0082h,S ; change OPCODE : AD=1, dst = R2
- JMP PARAM111 ; -- ' '
+PARAM2AMP BIS #0082h,S ; change OPCODE : AD=1, dst = R2
+ JMP PARAMXAMP ; -- ' '
; ----------------------------------;
; case of ",xxxx(REG) ; -- sep
-PARAM21 BIS #0080h,S ; set AD=1
- CALL #ComputeIDXpREG ; compile index xxxx and search REG of ",xxxx(REG)"
- JMP PARAM124 ; -- 000R REG of ",xxxx(REG) found
+PARAM2IDX BIS #0080h,S ; set AD=1
+ CALL #ComputeIDXpREG ; compile index xxxx and search REG of ",xxxx(REG)", abort if xxxx not found
+ JNZ OPCODEPLREG ; -- 000R if REG found
+ MOV #NOTFOUND,PC ; does ABORT" ?"
+; ----------------------------------;
; ----------------------------------------------------------------------------------------
; DTCforthMSP430FR5xxx ASSEMBLER: reset OPCODE in S reg, set OPCODE addr in T reg,
; TYPE1DOES -- BODYDOES search and compute PARAM1 & PARAM2 as src and dst operands then compile instruction
TYPE1DOES .word lit,','
.word InitAndSkipPrfx ; init S=0, T=DP, DP=DP+2 then skip prefix, SR(Z)=1 if prefix = 'R'
- .word PARAM1 ; -- BODYDOES
+ .word PARAM1 ; -- BODYDOES S=OPCODE,T=OPCODEADR
.word BL,SkipPrfx ; SR(Z)=1 if prefix = 'R'
- .word PARAM2 ; -- BODYDOES
+ .word PARAM2 ; -- BODYDOES S=OPCODE,T=OPCODEADR
mNEXTADR ;
MAKEOPCODE MOV @RSP+,IP
BIS @TOS,S ; -- opcode generic opcode + customized S
- MOV S,0(T) ; -- opcode store completed opcode
+ MOV S,0(T) ; -- opcode store complete opcode
JMP PARAMENDOF ; -- then EXIT
asmword "MOV"
TYPE2DOES ; -- BODYDOES
.word BL ; -- BODYDOES ' '
.word InitAndSkipPrfx ;
- .word PARAM1 ; -- BODYDOES
+ .word PARAM1 ; -- BODYDOES S=OPCODE,T=OPCODEADR
mNEXTADR ;
MOV S,W ;
AND #0070h,S ; keep B/W & AS infos in OPCODE
CALL rDODOES
.word TYPE2DOES,1280h
-BOUNDERRWM1 ADD #1,W ; <== RRAM|RRUM|RRCM|RLAM error
-BOUNDERRORW MOV W,TOS ; <== PUSHM|POPM|ASM_branch error
-BOUNDERROR ; <== REG number error
+; ----------------------------------------------------------------------
+; errors output
+; ----------------------------------------------------------------------
+
+MUL_REG_ERR ADD #1,W ; <== PUSHM|POPM|RRAM|RRUM|RRCM|RLAM error
+BRANCH_ERR MOV W,TOS ; <== ASM_branch error
+REGNUM_ERR ; <== REG number error
mASM2FORTH ; -- n n = value out of bounds
.word DOT,XSQUOTE
.byte 13,"out of bounds"
ASM_THEN1 MOV @PSP+,TOS ; --
MOV Y,X ;
ADD #2,X ; -- Y=@OPCODE W=dst X=src+2
- SUB X,W ; -- Y=@OPCODE W=dst-src+2=displacement*2 (bytes)
+ SUB X,W ; -- Y=@OPCODE W=dst-src+2=displacement (bytes)
+ CMP #1023,W
+ JC BRANCH_ERR ; (JHS) unsigned branch if displ. > 1022 bytes
RRA W ; -- Y=@OPCODE W=displacement (words)
- CMP #512,W
- JC BOUNDERRORW ; (JHS) unsigned branch if u> 511
- BIS W,0(Y) ; -- [@OPCODE]=OPCODE completed
+ BIS W,0(Y) ; -- [@OPCODE]=OPCODE completed
MOV @IP+,PC
; ELSE @OPCODE1 -- @OPCODE2 branch for IF..ELSE
; BEGIN -- BEGINadr initialize backward branch
asmword "BEGIN"
- MOV #HEREXEC,PC
+HERE SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV &DP,TOS
+ MOV @IP+,PC
; UNTIL @BEGIN OPCODE -- resolve conditional backward branch
asmword "UNTIL"
MOV &DP,X ; -- Y=OPCODE X=HERE W=dst
SUB #2,W ; -- Y=OPCODE X=HERE W=dst-2
SUB X,W ; -- Y=OPCODE X=src W=src-dst-2=displacement (bytes)
+ CMP #-1024,W ;
+ JL BRANCH_ERR ; signed branch if displ. < -1024 bytes
RRA W ; -- Y=OPCODE X=HERE W=displacement (words)
- CMP #-512,W
- JL BOUNDERRORW ; signed branch if < -512
AND #3FFh,W ; -- Y=OPCODE X=HERE W=troncated negative displacement (words)
BIS W,Y ; -- Y=OPCODE (completed)
MOV Y,0(X)
; DTCforthMSP430FR5xxx ASSEMBLER : branch up to 3 backward labels and up to 3 forward labels
; ------------------------------------------------------------------------------------------
; used for non canonical branchs, as BASIC language: "goto line x"
-; labels BWx and FWx must be respectively set and used at the beginning of line (>IN < 8).
-; FWx at the beginning of a line can resolve only one previous GOTO|?GOTO FWx.
-; BWx at the beginning of a line can be resolved by any subsequent GOTO|?GOTO BWx.
-
-;BACKWDOES FORTHtoASM
-; MOV @RSP+,IP
-; MOV @TOS,TOS
-; MOV @TOS,Y ; Y = ASMBWx
-; MOV @PSP+,TOS ;
-; MOV @Y,W ; W = [BWx]
-; CMP #8,&TOIN ; are we colon 8 or more ?
-;BACKWUSE JHS ASM_UNTIL1 ; yes, use this label
-;BACKWSET MOV &DP,0(Y) ; no, set LABEL = DP
-; mNEXT
-
-;; backward label 1
-; asmword "BW1"
-; mdodoes
-; .word BACKWDOES
-; .word ASMBW1 ; in RAM
+; labels BWx and FWx must be set at the beginning of line (>IN < 8).
+; FWx can resolve only one previous GOTO|?GOTO FWx.
+; BWx can resolve any subsequent GOTO|?GOTO BWx.
BACKWDOES mNEXTADR
MOV @RSP+,IP ;
+ MOV @TOS,TOS
MOV TOS,Y ; -- BODY Y = BWx addr
MOV @PSP+,TOS ; --
MOV @Y,W ; W = LABEL
asmword "BW1"
CALL rDODOES ; CFA
.word BACKWDOES ; PFA
- .word 0 ; BODY
+ .word ASMBW1 ; in RAM
; backward label 2
asmword "BW2"
CALL rDODOES
.word BACKWDOES
- .word 0
+ .word ASMBW2 ; in RAM
; backward label 3
asmword "BW3"
CALL rDODOES
.word BACKWDOES
- .word 0
-
-;FORWDOES mNEXTADR
-; MOV @RSP+,IP
-; MOV &DP,W ;
-; MOV @TOS,TOS
-; MOV @TOS,Y ; -- BODY Y=@OPCODE of FWx
-; MOV #0,0(TOS) ; V3.9: clear @OPCODE of FWx to erratic 2th resolution
-; CMP #8,&TOIN ; are we colon 8 or more ?
-;FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DP, Y=@OPCODE
-;FORWSET MOV @PSP+,0(W) ; yes compile incomplete opcode
-; ADD #2,&DP ; increment DP
-; MOV W,0(TOS) ; store @OPCODE into ASMFWx
-; MOV @PSP+,TOS ; --
-; MOV @IP+,PC
-;
-;; forward label 1
-; asmword "FW1"
-; CALL rDODOES ; CFA
-; .word FORWDOES ;
-; .word ASMFW1 ; in RAM
+ .word ASMBW3 ; in RAM
FORWDOES mNEXTADR
MOV @RSP+,IP
MOV &DP,W ;
+ MOV @TOS,TOS
MOV @TOS,Y ; -- BODY Y=@OPCODE of FWx
MOV #0,0(TOS) ; V3.9: clear @OPCODE of FWx to avoid jmp resolution without label
CMP #8,&TOIN ; are we colon 8 or more ?
asmword "FW1"
CALL rDODOES ; CFA
.word FORWDOES ; PFA
- .word 0 ; BODY
+ .word ASMFW1 ; in RAM
; forward label 2
asmword "FW2"
CALL rDODOES
.word FORWDOES
- .word 0
+ .word ASMFW3 ; in RAM
; forward label 3
asmword "FW3"
CALL rDODOES
.word FORWDOES
- .word 0
+ .word ASMFW3 ; in RAM
;ASM GOTO <label> -- unconditionnal branch to label
asmword "GOTO"
; RxxM syntax: RxxM #n,REG with 0 < n < 5
TYPE3DOES ; -- BODYDOES
- .word SkipPrfx ;
.word LIT,',' ; -- BODYDOES ','
+ .word SkipPrfx ;
.word WORDD,QNUMBER ;
- .word QFBRAN,NotFound ; see INTERPRET
+ .word QFBRAN,FNOTFOUND; see INTERPRET
.word BL ; -- BODYDOES n ' '
.word InitAndSkipPrfx ; -- BODYDOES n ' '
.word PARAM2 ; -- BODYDOES n S=OPCODE = 0x000R
MOV TOS,W ; -- BODYDOES n W = n
MOV @PSP+,TOS ; -- BODYDOES
SUB #1,W ; W = n floored to 0
- JN BOUNDERRWM1
+ JN MUL_REG_ERR
MOV @TOS,X ; X=OPCODE
RLAM #4,X ; OPCODE bit 1000h --> C
JNC RxxMINSTRU ; if bit 1000h = 0
POPMINSTRU SUB W,S ; to make POPM opcode, compute first REG to POP; TI is complicated....
PUSHMINSTRU SUB W,Y ; Y=REG-(n-1)
CMP #16,Y
- JC BOUNDERRWM1 ; JC=JHS (U>=)
+ JC MUL_REG_ERR ; JC=JHS (U>=)
RLAM #4,W ; W = n << 4
JMP BIS_ASMTYPE ; BODYDOES --
RxxMINSTRU CMP #4,W ;
- JC BOUNDERRWM1 ; JC=JHS (U>=)
+ JC MUL_REG_ERR ; JC=JHS (U>=)
SWPB W ; W = n << 8
RLAM #2,W ; W = N << 10
JMP BIS_ASMTYPE ; BODYDOES --
CALL rDODOES
.word TYPE3DOES,1700h
-
- .IFDEF EXTENDED_MEM
+ .IFDEF LARGE_CODE
asmword "RRCM.A"
CALL rDODOES
.word TYPE3DOES,0040h
asmword "SUBA"
CALL rDODOES
.word TYPE4DOES,00F0h
- .ENDIF ; EXTENDED_MEM
+ .ENDIF ; LARGE_CODE
-; -*- coding: utf-8 -*-
+ ; -*- coding: utf-8 -*-
;
; ----------------------------------------------------------------------
;forthMSP430FR_EXTD_ASM.asm
.ENDIF ;
ISOTHER SUB #2,TOS ; -- CFA|UPFA UPFA = MARKER_DOES User_Parameter_Field_Address
ARGFOUND ADD #2,RSP ; remove TOIN
-SEARCHRET MOV @RSP+,PC ;24 SR(Z)=0 ARG found
+SEARCHRET MOV @RSP+,PC ;24 SR(Z)=0 if ARG found
SRCHARGNUM .word QNUMBER ;
- .word QFBRAN,ARGNOTFOUND; -- addr if ARG not found SR(Z)=1
+ .word QFBRAN,ARGNOTFOUND; -- addr
.word ARGFOUND ; -- value
ARGNOTFOUND mNEXTADR ; -- x
MOV @RSP+,&TOIN ; restore TOIN
- MOV @RSP+,PC ;32 SR(Z)=1 ARG not found
+ MOV @RSP+,PC ;32 SR(Z)=1 if ARG not found
+; ----------------------------------;
+; ----------------------------------;
SearchIndex
-; Search index of "xxxx(REG)," ; <== ComputeIDXpREG <== PARAM13
-; Search index of ",xxxx(REG)" ; <== ComputeIDXpREG <== PARAM21
- SUB #1,&TOIN ; move >IN back one
- MOV #'(',TOS ; addr -- "(" as WORD separator to find xxxx of "xxxx(REG),"
-SearchARG ; sep -- n|d or abort" not found"
-; Search ARG of "#xxxx," ; <== PARAM101
-; Search ARG of "&xxxx," ; <== PARAM111
-; Search ARG of ",&xxxx" ; <== PARAM111 <== PARAM201
+; Search index of "xxxx(REG)," ; <== ComputeIDXpREG <== PARAM1IDX
+; Search index of ",xxxx(REG)" ; <== ComputeIDXpREG <== PARAM2IDX
+ MOV #'(',TOS ; addr -- "(" as WORD separator to find xxxx of "xxxx(REG),"
+ SUB #1,&TOIN ; move >IN back one (unskip 'R')
+SearchARG ; sep -- n|d or abort" not found"
+; Search ARG of "#xxxx," ; <== PARAM1SHARP
+; Search ARG of "&xxxx," ; <== PARAMXAMP
+; Search ARG of ",&xxxx" ; <== PARAMXAMP <== PARAM2AMP
MOV TOS,W
- PUSHM #4,IP ; -- sep PUSHM IP, S,T,W as IP_RET,OPCODE,OPCODEADR,sep
- CALL #SearchARGn ; first search argument without offset
- JNZ SrchEnd ; -- ARG if ARG found goto SrchPopEnd
-SearchArgPo MOV #'+',TOS ; -- '+'
- CALL #SearchARGn ; 2th search argument with '+' as separator
- JNZ ArgPlusOfst ; -- ARG if ARG of ARG+offset found
-SearchArgMo MOV #'-',TOS ; -- '-'
- CALL #SearchARGn ; 3th search argument with '-' as separator
- SUB #1,&TOIN ; to handle offset with its minus sign
-ArgPlusOfst PUSH TOS ; -- ARG save ARG on stack
- MOV 2(RSP),TOS ; -- sep reload offset sep
+ PUSHM #4,IP ; -- sep PUSHM IP,S,T,W as IP_RET,OPCODE,OPCODEADR,sep
+ CALL #SearchARGn ; first search argument without offset
+ JNZ SrchEnd ; -- ARG if ARG found
+SearchArgPl MOV #'+',TOS ; -- '+'
+ CALL #SearchARGn ; 2th search argument with '+' as separator
+ JNZ ArgPlusOfst ; -- ARG if ARG of ARG+offset found
+SearchArgMi MOV #'-',TOS ; -- '-'
+ CALL #SearchARGn ; 3th search argument with '-' as separator
+ SUB #1,&TOIN ; to handle offset with its minus sign
+ArgPlusOfst PUSH TOS ; -- ARG save ARG on stack
+ MOV 2(RSP),TOS ; -- sep reload offset sep
SrchOfst mASM2FORTH ;
.word WORDD,QNUMBER ; -- Ofst|c-addr flag
- .word QFBRAN,NotFound ; -- c-addr no return, see INTERPRET
+ .word QFBRAN,FNOTFOUND ; -- c-addr no return, see INTERPRET
mNEXTADR ; -- Ofst
ADD @RSP+,TOS ; -- Arg+Ofst
SrchEnd POPM #4,IP ; POPM W,T,S,IP common return for SearchARG and SearchRn
; ----------------------------------------------------------------------
; DTCforthMSP430FR5xxx ASSEMBLER : search REG
; ----------------------------------------------------------------------
-; compute arg of "xxxx(REG)," ; <== PARAM130, sep=','
-; compute arg of ",xxxx(REG)" ; <== PARAM210, sep=' '
+; compute index of "xxxx(REG)," ; <== PARAM1IDX, sep=','
+; compute index of ",xxxx(REG)" ; <== PARAM2IDX, sep=' '
ComputeIDXpREG ; addr -- Rn|addr
CALL #SearchIndex ; -- xxxx aborted if not found
CALL #ARGD2S ; skip arg_hi if DOUBLE
MOV #')',TOS ; -- ")" prepare separator to search REG of "xxxx(REG)"
; search REG of "xxxx(REG)," separator = ')'
; search REG of ",xxxx(REG)" separator = ')'
-; search REG of "@REG," separator = ',' <== PARAM120
-; search REG of "@REG+," separator = '+' <== PARAM121
+; search REG of "@REG," separator = ',' <== PARAM1AT
+; search REG of "@REG+," separator = '+' <== PARAM1ATPL
SkipRSearchRn
ADD #1,&TOIN ; skip "R" in input buffer
-; search REG of "REG," separator = ',' <== PARAM13
-; search REG of ",REG" separator = BL <== PARAM21
+; search REG of "REG," separator = ',' <== PARAM1REG
+; search REG of ",REG" separator = ' ' <== PARAM2REG
SearchRn MOV &TOIN,W ;
- PUSHM #4,IP ; PUSHM IP, S,T,W as IP_RET,OPCODE,OPCODEADR,TOIN
+ PUSHM #4,IP ; PUSHM IP,S,T,W as IP_RET,OPCODE,OPCODEADR,TOIN
mASM2FORTH ; search xx of Rxx
.word WORDD,QNUMBER ;
- .word QFBRAN,REGNOTFOUND; -- xxxx if Not a Number, SR(Z)=1
+ .word QFBRAN,REGNOTFOUND; -- xxxx SR(Z)=1 if Not a Number
mNEXTADR ; -- Rn number is found
CMP #16,TOS ; -- Rn
- JNC SrchEnd ; -- Rn Rn is valid, remove TOIN then SrchEnd
+ JNC SrchEnd ; -- Rn SR(Z)=0, Rn found,
JC BOUNDERROR ; abort if Rn out of bounds
-REGNOTFOUND mNEXTADR ; -- addr SR(Z)=1, case of @REG not found,
- MOV @RSP,&TOIN ; -- addr restore TOIN (to point after prefix 'R')
+REGNOTFOUND mNEXTADR ; -- addr SR(Z)=1, (case of @REG not found),
+ MOV @RSP,&TOIN ; -- addr restore TOIN, ready for next SearchRn
JMP SrchEnd ; -- addr SR(Z)=1 ==> not a register
; ----------------------------------------------------------------------
; DTCforthMSP430FR5xxx ASSEMBLER : INTERPRET FIRST OPERAND
; ----------------------------------------------------------------------
; PARAM1 separator -- ; parse input buffer until separator and compute first operand of opcode
- ; sep is comma for src and space for dst .
-PARAM1 JNZ PARAM10 ; -- sep if prefix <> 'R'
- CALL #SearchRn ; case of "REG,"
- JMP PARAM123 ; -- 000R REG of "REG," found, S=OPCODE=0
+ ; sep is "," for src TYPE II and " " for dst (TYPE II).
+PARAM1 JNZ QPARAM1SHARP ; -- sep if prefix <> 'R'
+PARAM1REG CALL #SearchRn ; case of "REG,"
+ JNZ REGSHFT8L ; -- 000R REG of "REG," found, S=OPCODE=0
; ----------------------------------;
-PARAM10 CMP.B #'#',W ; -- sep W=first char
- JNE PARAM11
-PARAM101 CALL #SearchARG ; -- xxxx abort if not found
+QPARAM1SHARP CMP.B #'#',W ; -- sep W=first char
+ JNE QPARAM1AMP
+PARAM1SHARP CALL #SearchARG ; -- xxxx abort if not found
CALL #ARGD2S ; skip arg_hi of OPCODE type V
MOV #0300h,S ; OPCODE = 0300h : MOV #0,dst is coded MOV R3,dst
CMP #0,TOS ; -- xxxx #0 ?
CMP #-1,TOS ; -- xxxx #-1 ?
JZ PARAMENDOF
MOV #0030h,S ; -- xxxx for all other cases : MOV @PC+,dst
-StoreArg MOV &DP,X ;
- ADD #2,&DP ; cell allot for arg
+; endcase of "&xxxx," ; <== PARAM1AMP
+; endcase of ",&xxxx" ; <== PARAMXAMP <== PARAM2AMP
+StoreArg MOV &DP,X ;
+ ADD #2,&DP ; cell allot for arg
MOV TOS,0(X) ; compile arg
-; case of "&xxxx," ; <== PARAM111
-; case of ",&xxxx" ; <== PARAM110 <== PARAM201
-; endcase of all "&xxxx" ;
-; endcase of all "#xxxx" ; <== PARAM101,102,104,108,10M1
-; endcase of all "REG"|"@REG"|"@REG+" <== PARAM124
-PARAMENDOF MOV @PSP+,TOS ; --
- MOV @IP+,PC ; -- S=OPCODE,T=OPCODEADR
+ JMP PARAMENDOF
; ----------------------------------;
-PARAM11 CMP.B #'&',W ; -- sep
- JNE PARAM12
-; case of "&xxxx," ; -- sep search for "&xxxx,"
-PARAM110 MOV #0210h,S ; -- sep set code type : xxxx(SR) with AS=0b01 ==> x210h (and SR=0 !)
-; case of ",&xxxx" ; <== PARAM201
-PARAM111 CALL #SearchARG ; -- arg abort if not found
+QPARAM1AMP CMP.B #'&',W ; -- sep
+ JNE QPARAM1AT
+; case of "&xxxx," ; search for "&xxxx,"
+PARAM1AMP MOV #0210h,S ; set code type : xxxx(R2) with AS=0b01 ==> x210h
+; case of "&xxxx,"|",&xxxx" ; <== PARAM2AMP
+PARAMXAMP CALL #SearchARG ; -- sep
CALL #ARGD2S ; skip arg_hi of OPCODE type V
JMP StoreArg ; -- then ret
; ----------------------------------;
-PARAM12 CMP.B #'@',W ; -- sep
- JNE PARAM13
+QPARAM1AT CMP.B #'@',W ; -- sep
+ JNE PARAM1IDX
; case of "@REG,"|"@REG+,"
-PARAM120 MOV #0020h,S ; -- sep init OPCODE with indirect code type : AS=0b10
+PARAM1AT MOV #0020h,S ; -- sep init OPCODE with indirect code type : AS=0b10
CALL #SkipRSearchRn ; Z = not found
- JNZ PARAM123 ; -- Rn REG of "@REG," found
+ JNZ REGSHFT8L ; -- Rn REG of "@REG," found
; case of "@REG+," ; -- addr search REG of "@REG+"
-PARAM121 BIS #0010h,S ; change OPCODE from @REG to @REG+ type
+PARAM1ATPL BIS #0010h,S ; change OPCODE from @REG to @REG+ type
MOV #'+',TOS ; -- sep
- CALL #SearchRn ; -- Rn
-; case of "xxxx(REG)," ; <== PARAM13
-PARAM122 ; case of double separator: +, and ),
- CMP &SOURCE_LEN,&TOIN ; test OPCODE II parameter ending by REG+ or (REG) without comma,
- JZ PARAM123 ; i.e. >IN = SOURCE_LEN : don't skip char CR !
- ADD #1,&TOIN ; -- 000R skip "," ready for the second operand search
-; case of "@REG," ; -- 000R <== PARAM120
-; case of "REG," ; -- 000R <== PARAM1
-PARAM123 SWPB TOS ; -- 0R00 swap bytes because it's not a dst REG typeI (not a 2 ops inst.)
-; case of ",REG" ; -- 000R <== PARAM2 (dst REG typeI)
-; case of ",xxxx(REG)" ; -- 000R <== PARAM21 (dst REG typeI)
-PARAM124 ADD TOS,S ; -- 0R00|000R
- JMP PARAMENDOF
-; ----------------------------------;
+ CALL #SearchRn ;
+ JNZ QSKIPCOMMA ; -- Rn REG found
+; ----------------------------------; REG not found
; case of "xxxx(REG)," ; -- sep
-PARAM13 BIS #0010h,S ; AS=0b01 for indexing address
- CALL #ComputeIDXpREG ; compile index xxxx and search REG of "(REG)"
- JMP PARAM122 ; -- Rn
+PARAM1IDX BIS #0010h,S ; AS=0b01 for indexing address
+ CALL #ComputeIDXpREG ; compile index xxxx and search REG of "(REG)", abort if xxxx not found
+; case of "@REG+,"|"xxxx(REG)," ; <== PARAM1ATPL
+QSKIPCOMMA CMP &SOURCE_LEN,&TOIN ; test OPCODE II parameter ending by REG+ or (REG) without comma,
+ JZ REGSHFT8L ; i.e. >IN = SOURCE_LEN : don't skip char CR !
+SKIPCOMMA ADD #1,&TOIN ; -- 000R with OPCODE I, skip "," ready for the second operand search
+; endcase of "@REG," ; -- 000R <== PARAM1AT
+; endcase of "REG," ; -- 000R <== PARAM1REG
+REGSHFT8L SWPB TOS ; -- 0R00 swap bytes because it's not a dst REG typeI (not a 2 ops inst.)
+; endcase of ",REG" ; -- 000R <== PARAM2REG (dst REG typeI)
+; endcase of ",xxxx(REG)" ; -- 000R <== PARAM2IDX (dst REG typeI)
+OPCODEPLREG ADD TOS,S ; -- 0R00|000R
+; endcase of all ; <== PARAM1SHARP PARAM1AMP PARAM2AMP
+PARAMENDOF MOV @PSP+,TOS ; --
+ MOV @IP+,PC ; -- S=OPCODE,T=OPCODEADR
; ----------------------------------;
; ----------------------------------------------------------------------
; DTCforthMSP430FR5xxx ASSEMBLER : INTERPRET 2th OPERAND
; ----------------------------------------------------------------------
-PARAM2 JNZ PARAM20 ; -- sep if prefix <> 'R'
- CALL #SearchRn ; -- sep case of ",REG"
- JMP PARAM124 ; -- 000R REG of ",REG" found
+PARAM2 JNZ QPARAM2AMP ; -- sep if prefix <> 'R'
+PARAM2REG CALL #SearchRn ; -- sep case of ",REG"
+ JNZ OPCODEPLREG ; -- 000R REG of ",REG" found
; ----------------------------------;
-PARAM20 CMP.B #'&',W ;
- JNE PARAM21 ; '&' not found
+QPARAM2AMP CMP.B #'&',W ;
+ JNZ PARAM2IDX ; '&' not found
; case of ",&xxxx" ;
-PARAM201 BIS #0082h,S ; change OPCODE : AD=1, dst = R2
- JMP PARAM111 ; -- ' '
+PARAM2AMP BIS #0082h,S ; change OPCODE : AD=1, dst = R2
+ JMP PARAMXAMP ; -- ' '
; ----------------------------------;
; case of ",xxxx(REG) ; -- sep
-PARAM21 BIS #0080h,S ; set AD=1
- CALL #ComputeIDXpREG ; compile index xxxx and search REG of ",xxxx(REG)"
- JMP PARAM124 ; -- 000R REG of ",xxxx(REG) found
+PARAM2IDX BIS #0080h,S ; set AD=1
+ CALL #ComputeIDXpREG ; compile index xxxx and search REG of ",xxxx(REG)", abort if xxxx not found
+ JNZ OPCODEPLREG ; -- 000R if REG found
+ MOV #NOTFOUND,PC ; does ABORT" ?"
+; ----------------------------------;
; ----------------------------------------------------------------------------------------
; DTCforthMSP430FR5xxx ASSEMBLER: reset OPCODE in S reg, set OPCODE addr in T reg,
; ----------------------------------------------------------------------------------------
InitAndSkipPrfx
MOV #0,S ; reset OPCODE
- MOV &DP,T ; HERE --> OPCODEADR
- ADD #2,&DP ; cell allot for opcode
+ MOV &DP,T ; HERE --> OPCODEADR
+ ADD #2,&DP ; cell allot for opcode
; SkipPrfx ; -- skip all occurring char 'BL' plus one prefix
SkipPrfx MOV #20h,W ; -- W=BL
MOV &TOIN,X ; --
MOV @IP+,PC ; 4
; ----------------------------------------------------------------------
-; DTCforthMSP430FR5xxx ASSEMBLER: OPCODE TYPE 0 : zero operand f:-)
+; DTCforthMSP430FR5xxx ASSEMBLER: OPCODE TYPE 0 : zero operand :-)
; ----------------------------------------------------------------------
asmword "RETI"
mDOCOL
; TYPE1DOES -- BODYDOES search and compute PARAM1 & PARAM2 as src and dst operands then compile instruction
TYPE1DOES .word lit,','
.word InitAndSkipPrfx ; init S=0, T=DP, DP=DP+2 then skip prefix, SR(Z)=1 if prefix = 'R'
- .word PARAM1 ; -- BODYDOES
+ .word PARAM1 ; -- BODYDOES S=OPCODE,T=OPCODEADR
.word BL,SkipPrfx ; SR(Z)=1 if prefix = 'R'
- .word PARAM2 ; -- BODYDOES
+ .word PARAM2 ; -- BODYDOES S=OPCODE,T=OPCODEADR
mNEXTADR ;
MAKEOPCODE MOV @RSP+,IP
BIS @TOS,S ; -- opcode generic opcode + customized S
- MOV S,0(T) ; -- opcode store completed opcode
+ MOV S,0(T) ; -- opcode store complete opcode
JMP PARAMENDOF ; -- then EXIT
asmword "MOV"
TYPE2DOES ; -- BODYDOES
.word BL ; -- BODYDOES ' '
.word InitAndSkipPrfx ;
- .word PARAM1 ; -- BODYDOES
+ .word PARAM1 ; -- BODYDOES S=OPCODE,T=OPCODEADR
mNEXTADR ;
MOV S,W ;
AND #0070h,S ; keep B/W & AS infos in OPCODE
asmword "S>=" ; if >= assertion (opposite of jump if < )
CALL rDOCON
- .word 3800h
+ .word 3800h ; JL
asmword "S<" ; if < assertion
CALL rDOCON
- .word 3400h
+ .word 3400h ; JGE
asmword "0>=" ; if 0>= assertion ; use only with IF UNTIL WHILE !
CALL rDOCON
- .word 3000h
+ .word 3000h ; JN
asmword "0<" ; jump if 0< ; use only with ?GOTO !
CALL rDOCON
- .word 3000h
+ .word 3000h ; JN
asmword "U<" ; if U< assertion
CALL rDOCON
- .word 2C00h
+ .word 2C00h ;
asmword "U>=" ; if U>= assertion
CALL rDOCON
;ASM THEN @OPCODE -- resolve forward branch
asmword "THEN"
-ASM_THEN MOV &DP,W ; -- @OPCODE W=dst
+ASM_THEN MOV &DP,W ; -- @OPCODE W=dst
MOV TOS,Y ; Y=@OPCODE
ASM_THEN1 MOV @PSP+,TOS ; --
MOV Y,X ;
ADD #2,X ; -- Y=@OPCODE W=dst X=src+2
SUB X,W ; -- Y=@OPCODE W=dst-src+2=displacement*2 (bytes)
+ CMP #1023,W
+ JC BOUNDERRORW ; (JHS) unsigned branch if displ. > 1022 bytes
RRA W ; -- Y=@OPCODE W=displacement (words)
- CMP #512,W
- JC BOUNDERRORW ; (JHS) unsigned branch if u> 511
- BIS W,0(Y) ; -- [@OPCODE]=OPCODE completed
+ BIS W,0(Y) ; -- [@OPCODE]=OPCODE completed
MOV @IP+,PC
;C ELSE @OPCODE1 -- @OPCODE2 branch for IF..ELSE
asmword "ELSE"
-ASM_ELSE MOV &DP,W ; -- W=HERE
+ASM_ELSE MOV &DP,W ; -- W=HERE
MOV #3C00h,0(W) ; compile unconditionnal branch
- ADD #2,&DP ; -- DP+2
+ ADD #2,&DP ; -- DP+2
SUB #2,PSP
MOV W,0(PSP) ; -- @OPCODE2 @OPCODE1
JMP ASM_THEN ; -- @OPCODE2
; BEGIN -- BEGINadr initialize backward branch
asmword "BEGIN"
- MOV #HEREXEC,PC
+HERE SUB #2,PSP
+ MOV TOS,0(PSP)
+ MOV &DP,TOS
+ MOV @IP+,PC
; UNTIL @BEGIN OPCODE -- resolve conditional backward branch
asmword "UNTIL"
ASM_UNTIL MOV @PSP+,W ; -- OPCODE W=@BEGIN
ASM_UNTIL1 MOV TOS,Y ; Y=OPCODE W=@BEGIN
ASM_UNTIL2 MOV @PSP+,TOS ; --
- MOV &DP,X ; -- Y=OPCODE X=HERE W=dst
+ MOV &DP,X ; -- Y=OPCODE X=HERE W=dst
SUB #2,W ; -- Y=OPCODE X=HERE W=dst-2
SUB X,W ; -- Y=OPCODE X=src W=src-dst-2=displacement (bytes)
+ CMP #-1024,W ;
+ JL BOUNDERRORW ; signed branch if displ. < -1024 bytes
RRA W ; -- Y=OPCODE X=HERE W=displacement (words)
- CMP #-512,W
- JL BOUNDERRORW ; signed branch if < -512
AND #3FFh,W ; -- Y=OPCODE X=HERE W=troncated negative displacement (words)
BIS W,Y ; -- Y=OPCODE (completed)
MOV Y,0(X)
; FWx at the beginning of a line can resolve only one previous GOTO|?GOTO FWx.
; BWx at the beginning of a line can be resolved by any subsequent GOTO|?GOTO BWx.
-;BACKWDOES FORTHtoASM
-; MOV @RSP+,IP
-; MOV @TOS,TOS
-; MOV TOS,Y ; Y = ASMBWx
-; MOV @PSP+,TOS ;
-; MOV @Y,W ; W = [BWx]
-; CMP #8,&TOIN ; are we colon 8 or more ?
-;BACKWUSE JHS ASM_UNTIL1 ; yes, use this label
-;BACKWSET MOV &DP,0(Y) ; no, set LABEL = DP
-; mNEXT
-
-;; backward label 1
-; asmword "BW1"
-; mdodoes
-; .word BACKWDOES
-; .word ASMBW1 ; in RAM
-
BACKWDOES mNEXTADR
MOV @RSP+,IP ;
- MOV TOS,Y ; -- BODY Y = ASMBWx addr
+ MOV @TOS,TOS
+ MOV TOS,Y ; -- BODY Y = BWx addr
MOV @PSP+,TOS ; --
MOV @Y,W ; W = LABEL
CMP #8,&TOIN ; are we colon 8 or more ?
BACKWUSE JC ASM_UNTIL1 ; yes, use this label
-BACKWSET MOV &DP,0(Y) ; no, set LABEL = DP
+BACKWSET MOV &DP,0(Y) ; no, set LABEL = DP
MOV @IP+,PC
; backward label 1
asmword "BW1"
- CALL rDODOES
- .word BACKWDOES
- .word 0
+ CALL rDODOES ; CFA
+ .word BACKWDOES ; PFA
+ .word ASMBW1 ; in RAM
; backward label 2
asmword "BW2"
CALL rDODOES
.word BACKWDOES
- .word 0
+ .word ASMBW2 ; in RAM
; backward label 3
asmword "BW3"
CALL rDODOES
.word BACKWDOES
- .word 0
-
-;FORWDOES mNEXTADR
-; MOV @RSP+,IP
-; MOV &DP,W ;
-; MOV @TOS,TOS
-; MOV @TOS,Y ; -- BODY Y=@OPCODE of FWx
-; MOV #0,0(TOS) ; clear @OPCODE of FWx to erratic 2th resolution
-; CMP #8,&TOIN ; are we colon 8 or more ?
-;FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DP, Y=@OPCODE
-;FORWSET MOV @PSP+,0(W) ; yes compile incomplete opcode
-; ADD #2,&DP ; increment DP
-; MOV W,0(TOS) ; store @OPCODE into ASMFWx
-; MOV @PSP+,TOS ; --
-; MOV @IP+,PC
-;
-;; forward label 1
-; asmword "FW1"
-; CALL rDODOES ; CFA
-; .word FORWDOES ;
-; .word ASMFW1 ; in RAM
+ .word ASMBW3 ; in RAM
FORWDOES mNEXTADR
MOV @RSP+,IP
- MOV &DP,W ;
+ MOV &DP,W ;
+ MOV @TOS,TOS
MOV @TOS,Y ; -- BODY Y=@OPCODE of FWx
- MOV #0,0(TOS) ; clear @OPCODE of FWx to avoid erratic 2th resolution
+ MOV #0,0(TOS) ; V3.9: clear @OPCODE of FWx to avoid jmp resolution without label
CMP #8,&TOIN ; are we colon 8 or more ?
FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DP, Y=@OPCODE
FORWSET MOV @PSP+,0(W) ; yes compile opcode (without displacement)
- ADD #2,&DP ; increment DP
+ ADD #2,&DP ; increment DP
MOV W,0(TOS) ; store @OPCODE into BODY of FWx
MOV @PSP+,TOS ; --
MOV @IP+,PC
; forward label 1
asmword "FW1"
- CALL rDODOES
- .word FORWDOES
- .word 0
+ CALL rDODOES ; CFA
+ .word FORWDOES ; PFA
+ .word ASMFW1 ; in RAM
; forward label 2
asmword "FW2"
CALL rDODOES
.word FORWDOES
- .word 0
+ .word ASMFW3 ; in RAM
; forward label 3
asmword "FW3"
CALL rDODOES
.word FORWDOES
- .word 0
+ .word ASMFW3 ; in RAM
;ASM GOTO <label> -- unconditionnal branch to label
asmword "GOTO"
; RxxM syntax: RxxM #n,REG with 0 < n < 5
TYPE3DOES ; -- BODYDOES
- .word SkipPrfx ;
.word LIT,',' ; -- BODYDOES ','
+ .word SkipPrfx ;
.word WORDD,QNUMBER ;
- .word QFBRAN,NotFound ; see INTERPRET
+ .word QFBRAN,FNOTFOUND; see INTERPRET
.word BL ; -- BODYDOES n ' '
.word InitAndSkipPrfx ; -- BODYDOES n ' '
.word PARAM2 ; -- BODYDOES n S=OPCODE = 0x000R
MOV #'+',TOS ; -- sep
JMP CALLA01 ;
;-----------------------------------;
-CALLA2 ADD #2,&DP ; -- sep make room for xxxx of #$x.xxxx|&$x.xxxx|$xxxx(REG)
+CALLA2 ADD #2,&DP ; -- sep make room for xxxx of #$x.xxxx|&$x.xxxx|$xxxx(REG)
CMP.B #'#',W ;
JNZ CALLA3
MOV #13Bh,S ; 13Bh<<4 = opcode for CALLA #$x.xxxx
ACMS11 CMP.B #'#',W ; -- sep X=addr
JNE MOVA12 ;
BIC #40h,S ; set #opcode
-ACMS111 ADD #2,&DP ; make room for low #$xxxx|&$xxxx|$xxxx(REG)
+ACMS111 ADD #2,&DP ; make room for low #$xxxx|&$xxxx|$xxxx(REG)
CALL #SearchARG ; -- Lo Hi
MOV @PSP+,2(T) ; -- Hi store $xxxx of #$x.xxxx|&$x.xxxx|$xxxx(REG)
AND #0Fh,TOS ; -- Hi sel Hi src
JMP ACMS102 ;
;-----------------------------------;
MOVA14 BIS #0030h,S ; -- sep set xxxx(REG), opcode
- ADD #2,&DP ; make room for first $xxxx of $xxxx(REG),
+ ADD #2,&DP ; make room for first $xxxx of $xxxx(REG),
CALL #SearchIndex ; -- n
MOV TOS,2(T) ; -- n store $xxxx as 2th word
MOV #')',TOS ; -- ')'
JMP ACMS103 ;
;-----------------------------------;
MOVA22 BIC #0F0h,S ; -- sep
- ADD #2,&DP ; make room for $xxxx
+ ADD #2,&DP ; make room for $xxxx
CMP.B #'&',W ;
JNZ MOVA23 ;
BIS #060h,S ; set ,&$x.xxxx opcode
PRMX102 MOV S,TOS ; -- EW init|update Extended word
PRMX103 MOV @IP+,PC ; -- Ext_Word
;-----------------------------------;
-PRMX11 MOV #0,&RPT_WORD ; clear RPT
- CMP.B #'#',W ; -- sep
+PRMX11 CMP.B #'#',W ; -- sep
JNZ PRMX12
PRMX111 CALL #SearchARG ; -- Lo Hi search $x.xxxx of #x.xxxx,
ADD #2,PSP ; -- Hi pop unused low word
;-----------------------------------;
PRMX20 JZ PRMX102 ; -- sep if prefix <> 'R'
;-----------------------------------;
-PRMX21 MOV #0,&RPT_WORD ;
- CMP.B #'&',W ;
+PRMX21 CMP.B #'&',W ;
JNZ PRMX22 ;
PRMX211 CALL #SearchARG ; -- Lo Hi
PRMX213 ADD #2,PSP ; -- hi pop low word
;-----------------------------------;
UPDATE_XW ; BODYDOES >IN Extended_Word -- BODYDOES+2
MOV @PSP+,&TOIN ; -- BODYDOES EW restore >IN at the start of instruction string
- MOV &DP,T ;
- ADD #2,&DP ; make room for extended word
+ MOV &DP,T ;
+ ADD #2,&DP ; make room for extended word
MOV TOS,S ; S = Extended_Word
MOV @PSP+,TOS ;
BIS &RPT_WORD,S ; update Extended_word with RPT_WORD
- MOV #0,&RPT_WORD ; clear RPT before next instruction
+ MOV #0,&RPT_WORD ; clear RPT_WORD
BIS @TOS+,S ; -- BODYDOES+2 update Extended_word with [BODYDOES] = A/L bit
MOV S,0(T) ; store extended word
MOV @IP+,PC ;
SDA_MoveChar ;
; ----------------------------------;
CMP TOS,X ; 1 len = SDIB_len ?
- JZ YEMIT ; 2 yes, don't move char to dst
+ JZ QYEMIT ; 2 yes, don't move char to dst
MOV.B Y,0(W) ; 3 move char to dst
ADD #1,W ; 1 increment SDIB_ptr
ADD #1,TOS ; 1 increment len of moved chars
- JMP YEMIT ; 9/6~ send echo to terminal if ECHO, do nothing if NOECHO
+ JMP QYEMIT ; 9/6~ send echo to terminal if ECHO, do nothing if NOECHO
; ----------------------------------; 29/26~ char loop, add 14~ for readsectorW one char ==> 43/40~ ==> 186/200 kbytes/s @ 8MHz
SDA_GetFileNextSect ; -- SDIB_org len
; ----------------------------------;
; ===========================================================
; ===========================================================
-; Init SD_Card software, called by INIT_FORTH(INIT_SOFT_APP)
+; Init SD_Card software, called by INIT_FORTH(SOFT_APP)
; ===========================================================
;-----------------------------------;
INIT_SOFT_SD ; called by INI_FORTH common part of ?ABORT|RST
;-----------------------------------;
-; CMP #0,TOS ; USERSYS = 0 ?
-; JZ INIT_HSD_END ; no hardware init if USERSYS = 0 SYS
; MOV #HandlesLen,X ; clear all handles
;ClearHandle SUB #2,X ; 1
; MOV #0,FirstHandle(X) ; 3
; JNZ ClearHandle ; 2
MOV #0,&CurrentHdl ;
- MOV #INIT_SOFT_TERM,PC ; link to previous INI_SOFT_APP then RET
+ MOV #INIT_SOFT,PC ; link to previous INI_SOFT_APP then RET
;-----------------------------------;
; ===========================================================
-; Init hardware SD_Card, called by WARM(INIT_HARD_APP)
+; Init hardware SD_Card, called by WARM(HARD_APP)
; ===========================================================
; web search: "SDA simplified specifications"
;-----------------------------------;
-INIT_HARD_SD CALL @PC+ ; link to previous INI_HARD_APP
- .word INIT_TERM ; which activates all previous I/O settings and set TOS = RSTIV_MEM.
+INIT_HARD_SD CALL @PC+ ; link to previous HARD_APP first, because used by ERROR outputs
+ .word INIT_TERM ; which activates all previous I/O settings.
;-----------------------------------;
BIT.B #CD_SD,&SD_CDIN ; SD_memory in SD_Card module ?
JNZ INIT_HSD_END ; no
MOV #0,SD_ORG(X) ; 3
JNZ ClearSDdata ; 2
;-----------------------------------;
-SD_POWER_ON
-; ----------------------------------;
- MOV #8,X ; send 8*8 = 64 clk on SPI
- CALL #SPI_X_GET ;
BIC.B #CS_SD,&SD_CSOUT ; preset Chip Select output low to switch in SPI mode
; ----------------------------------;
-INIT_CMD0 ; SD_CMD_FRM+2 is already cleared...
+INIT_CMD0 ; SD_CMD_FRM is zero fullfilled...
; ----------------------------------;
MOV #4,S ; preset error 4R1 for CMD0
MOV #0095h,&SD_CMD_FRM ; $(95 00 00 00 00 00)
+ MOV #0,&SD_CMD_FRM+2 ;
MOV #4000h,&SD_CMD_FRM+4 ; $(95 00 00 00 00 40) = CMD0
+ MOV #8,Y ; CMD0 necessary loop, not documented in "SDA simplified specifications"
; ----------------------------------;
-SEND_CMD0 ; GO_IDLE_STATE, expected SPI_R1 response = 1 = idle state
+SEND_CMD0 ; GO_IDLE_STATE (software reset), expected SPI_R1 response = 1 = idle state
; ----------------------------------;
CALL #sendCommandIdleRet ;X send command (does little to big endian conversion), see forthMSP430FR_SD_lowLvl.asm
- JZ INIT_CMD8 ; if idle state
+ JZ INIT_CMD8 ; if idle state reached (W=1)
+ SUB #1,Y ;
+ JNZ SEND_CMD0 ; else loop back 8 times, because init time of SD_Card can be long...
SD_INIT_ERROR ;
- MOV #SD_CARD_ERROR,PC ; ReturnError = $04R1, case of defectuous card (or insufficient SD_POWER_ON clk)
+ JMP SD_CARD_ERROR ; ReturnError = $04R1, case of defectuous card (or insufficient SD_POWER_ON clk)
; ----------------------------------; see forthMSP430FR_SD_lowLvl.asm
INIT_CMD8 ; mandatory if SD_Card >= V2.x [11:8]supply voltage(VHS)
; ----------------------------------;
- CALL #SPI_GET ; (needed to pass SanDisk ultra 8GB "HC I")
- CMP.B #-1,W ; FFh expected value <==> MISO = high level
- JNE INIT_CMD8 ; loop back while yet busy
MOV #0AA87h,&SD_CMD_FRM ; $(87 AA ...) (CRC:CHECK PATTERN)
MOV #1,&SD_CMD_FRM+2 ; $(87 AA 01 00 ...) (CRC:CHECK PATTERN:VHS set as 2.7to3.6V:0)
MOV #4800h,&SD_CMD_FRM+4 ; $(87 AA 01 00 00 48)
; ----------------------------------;
MOV #1,&SD_CMD_FRM ; $(01 00 ... set stop bit
MOV #0,&SD_CMD_FRM+2 ; $(01 00 00 00 ...
-; MOV.B #16,Y ; init 16 * ACMD41 repeats (fails with SanDisk ultra 8GB "HC I" and Transcend 2GB)
-; MOV.B #32,Y ; init 32 * ACMD41 repeats ==> ~400ms time out
MOV.B #-1,Y ; init 255 * ACMD41 repeats ==> ~3 s time out
MOV #8,S ; preset error 8R1 for ACMD41
; ----------------------------------;
SEND_CMD41 ; CMD41 = APP OPERATING CONDITION
MOV #6940h,&SD_CMD_FRM+4 ; $(01 00 00 00 40 69) (30th bit = HCS = High Capacity Support request)
CALL #WaitIdleBeforeSendCMD ; wait until idle (needed to pass SanDisk ultra 8GB "HC I") then send Command CMD41
- JZ SetBLockLength ; if SD_Card ready (R1=0)
+ JZ SwitchSPIhighSpeed ; if SD_Card ready (R1=0)
SUB.B #1,Y ; else decr time out delay
JNZ INIT_CMD55 ; then loop back while count of repeat not reached
- JMP SD_INIT_ERROR ; ReturnError on time out : unusable card (or insufficient Vdd SD)
-; ----------------------------------;
-setBLockLength ; set block = 512 bytes (buffer size), usefull only for FAT16 SD Cards
-; ----------------------------------;
- ADD S,S ; preset error $10 for CMD16
-SEND_CMD16 ; CMD16 = SET_BLOCKLEN
- MOV #02h,&SD_CMD_FRM+2 ; $(01 00 02 00 ...)
- MOV #5000h,&SD_CMD_FRM+4 ; $(01 00 02 00 00 50)
- CALL #WaitIdleBeforeSendCMD ; wait until idle then send CMD16
- JNZ SD_INIT_ERROR ; if W = R1 <> 0, ReturnError = $20R1 ; send command ko
+ JMP SD_CARD_ERROR ; ReturnError on time out : unusable card (or insufficient Vdd SD)
; ----------------------------------; W = R1 = 0
SwitchSPIhighSpeed ; end of SD init ==> SD_CLK = SMCLK
; ----------------------------------;
; ----------------------------------;
MOV #0,W ;
MOV #0,X ;
- CALL #readSectorWX ; read physical first sector, W=0
+ CALL #ReadSectorWX ; read physical first sector, W=0
MOV #SD_BUF,Y ;
- MOV 454(Y),&BS_FirstSectorL ; so, from here, sectors become logical
- MOV 456(Y),&BS_FirstSectorH ;
- MOV.B 450(Y),S ; S = partition ID
+; ----------------------------------;
+ CMP #0AA55h,1FEh(Y) ; valid boot sector ?
+ JZ SetMBR ;
+ MOV #1000h,S ; error Boot Sector
+ JMP SD_CARD_INIT_ERROR ;
+; ----------------------------------;
+SetMBR ;
+; ----------------------------------;
+ MOV 1C6h(Y),&BS_FirstSectorL; logical sector = physical sector + BS_FirstSector
+ MOV 1C8h(Y),&BS_FirstSectorH;
; ----------------------------------;
TestPartitionID ;
; ----------------------------------;
+ MOV.B 1C2h(Y),S ; S = partition ID
SUB.B #0Ch,S ; ID=0Ch Partition FAT32 using LBA ?
JZ Read_MBR_FirstSector ;
ADD.B #1,S ; ID=0Bh Partition FAT32 using CHS & LBA ?
JZ Read_MBR_FirstSector ;
- ADD.B #4,S ; ID=07h assigned to FAT 32 by MiniTools Partition Wizard....
+ ADD.B #4,S ; ID=07h assigned to FAT32 by MiniTools Partition Wizard....
JZ Read_MBR_FirstSector ;
- ADD #02007h,S ; set ReturnError = $20 & restore ID value
- MOV #SD_CARD_ID_ERROR,PC ; see: https://en.wikipedia.org/wiki/Partition_type
+ ADD #01007h,S ; set ReturnError = $10 & restore ID value
+ JMP SD_CARD_INIT_ERROR ; see: https://en.wikipedia.org/wiki/Partition_type
; ----------------------------------;
Read_MBR_FirstSector ; read first logical sector
; ----------------------------------;
MOV #0,X ; W = 0
- CALL #readSectorWX ; ...with the good CMD17 bytes/sectors frame ! (good switch FAT16/FAT32)
-; ----------------------------------;
-FATxx_SetFileSystem ;
+ CALL #ReadSectorWX ;
; ----------------------------------;
-; MOV 44(Y),&DIRClusterL ; init DIRcluster as FAT32 RootDIR
- MOV #2,&DIRClusterL ; init DIRcluster as FAT32 RootDIR
+FAT32_SetFileSystem ;
; ----------------------------------;
- MOV 14(Y),X ;3 X = BPB_RsvdSecCnt (05FEh=1534)
+ MOV 0Eh(Y),X ;3 X = BPB_RsvdSecCnt (05FEh=1534)
MOV X,&OrgFAT1 ;3 set OrgFAT1
; ----------------------------------;
- MOV 36(Y),W ; no set W = BPB_FATSz32 (1D01h=7425)
+ MOV 24h(Y),W ; no set W = BPB_FATSz32 (1D01h=7425)
MOV W,&FATSize ; limited to 32767 sectors....
; ----------------------------------;
ADD W,X ;
- MOV X,&OrgFAT2 ; X = OrgFAT1 + FATsize = OrgFAT2 (8959)
+ MOV X,&OrgFAT2 ; X = OrgFAT1 + FATsize = OrgFAT32 (8959)
; ----------------------------------;
ADD W,X ; X = OrgFAT2 + FATsize = FAT32 OrgDatas (16384)
FATxx_SetFileSystemNext ;
- MOV.B 13(Y),Y ; Logical sectors per cluster (8)
+ MOV.B 0Dh(Y),Y ; Logical sectors per cluster (8)
MOV Y,&SecPerClus ;
SUB Y,X ; OrgDatas - SecPerClus*2 = OrgClusters
SUB Y,X ; no borrow expected
MOV X,&OrgClusters ; X = virtual cluster 0 address (clusters 0 and 1 don't exist)
+ MOV #2,&DIRClusterL ; init DIRcluster as FAT32 RootDIR
+ MOV #0,&DIRClusterH ;
INIT_HSD_END ;
MOV @RSP+,PC ; RET
;-----------------------------------;
-
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
-
; used variables : BufferPtr, BufferLen
;-----------------------------------------------------------------------
; ==================================;
ADD &OrgFAT1,W ;
MOV #0,X ; FAT1_SectorHI = 0
- JMP ReadSectorWX ;SWX read FAT1SectorW
+ JMP ReadSectorWX ;SWX read FAT1SectorW, W = 0
; ----------------------------------;
.IFDEF SD_CARD_READ_WRITE
; X = SectorH, (RTC) DATE
; Y = BufferPtr, (DIR) DIREntryOfst
-
; ==================================;
HDLcurClus2FATsecWofstY ;WXY Input: T=Handle, HDL_CurClustHL Output: ClusterHL, FATsector, W = FATsector, Y = FAToffset
; ==================================;
MOV @RSP+,PC ;
; ----------------------------------;
-
; ==================================;
HDLCurClusPlsOfst2sectorHL ;SWX input: HDL (CurClust, ClustOfst) output: SectorHL
; ==================================;
MOV @RSP+,PC ;
; ----------------------------------;
-
; if first open_load token, save DefaultInputStream
; if other open_load token, decrement token, save previous context
; ==================================; input : Cluster, DIREntryOfst
GetFreeHandle ;STWXY init handle(HDLL_DIRsect,HDLW_DIRofst,HDLL_FirstClus = HDLL_CurClust,HDLL_CurSize)
; ==================================; output : T = new CurrentHdl
- MOV #8,S ; prepare file already open error
+ MOV #4,S ; prepare file already open error
MOV #FirstHandle,T ;
MOV #0,X ; X = init previous handle as 0
; ----------------------------------;
CMP &ClusterH,HDLH_FirstClus(T);
JNE SearchNextHandle ;
CMP &ClusterL,HDLL_FirstClus(T);
- JZ OPEN_Error ; error 8: Already Open abort ===>
+ JZ OPEN_Error ; error 4: Already Open abort ===>
SearchNextHandle ;
MOV T,X ; handle is occupied, keep it in X as previous handle
ADD #HandleLenght,T ;
CMP #HandleEnd,T ;
JNZ SearchHandleLoop ;
- ADD S,S ;
- JMP OPEN_Error ; error 16 = no more handle error, abort ===>
+ MOV #8,S ;
+ JMP OPEN_Error ; error 8 = no more handle error, abort ===>
; ----------------------------------;
FreeHandleFound ; T = new handle, X = previous handle
; ----------------------------------;
; ==================================;
MOV &SectorL,W ; Low
MOV &SectorH,X ; High
- JMP ReadSectorWX ; SWX then RET
+ JMP ReadSectorWX ; SWX then RET with W = 0
; ----------------------------------;
-; ----------------------------------;
-CloseHandleT ;
-; ----------------------------------;
- MOV.B #0,HDLB_Token(T) ; release the handle
- MOV @T,T ; T = previous handle
- MOV T,&CurrentHdl ; becomes current handle
- CMP #0,T ;
- JZ CloseHandleRet ; if no more handle
-; ----------------------------------;
-RestorePreviousLoadedBuffer ;
-; ----------------------------------;
- MOV HDLW_BUFofst(T),&BufferPtr ; restore previous BufferPtr
- CALL #SetBufLenLoadCurSector ; then reload previous buffer
- BIC #Z,SR ;
-; ----------------------------------;
-CloseHandleRet ;
- MOV @RSP+,PC ; Z = 1 if no more handle
-; ----------------------------------;
-
; ==================================;
CloseHandle ; <== CLOSE, Read_File, TERM2SD", OPEN_DEL
; ==================================;
; ----------------------------------;
MOV HDLL_DIRsect(T),W ;
MOV HDLH_DIRsect(T),X ;
- CALL #readSectorWX ;SWX SD_buffer = DIRsector
+ CALL #ReadSectorWX ;SWX SD_buffer = DIRsector
MOV HDLW_DIRofst(T),Y ; Y = DirEntryOffset
CALL #GetYMDHMSforDIR ; X=DATE, W=TIME
MOV X,SD_BUF+18(Y) ; access date
ADD #6,RSP ; R-- QUIT3 empties return stack
MOV @RSP+,IP ; skip return to SD_ACCEPT
; ----------------------------------;
- CALL #CloseHandleT ; Z = 1 if no more handle
+ PUSH #CheckFirstLoadedFile ; defines the RETurn of CloseHandleT
+; ----------------------------------;
+CloseHandleT ;
+; ----------------------------------;
+ MOV.B #0,HDLB_Token(T) ; release the handle
+ MOV @T,T ; T = previous handle
+ MOV T,&CurrentHdl ; becomes current handle
+ CMP #0,T ;
+ JZ CloseHandleRet ; if no more handle
+; ----------------------------------;
+RestorePreviousLoadedBuffer ;
+; ----------------------------------;
+ MOV HDLW_BUFofst(T),&BufferPtr ; restore previous BufferPtr
+ CALL #SetBufLenLoadCurSector ; then reload previous buffer
+ BIC #Z,SR ;
+; ----------------------------------;
+CloseHandleRet ;
+ MOV @RSP+,PC ; Z = 1 if no more handle, then RET
; ----------------------------------;
-CheckFirstLoadedFileIsClosed ;
+CheckFirstLoadedFile ;
; ----------------------------------;
JZ RestoreDefaultACCEPT ;
MOV #NOECHO,PC ; -- org len if return to SD_ACCEPT
MOV #ECHO,PC ; -- org len if return to Terminal ACCEPT
; ----------------------------------;
-
-; ==================================; input : X = countdown_of_spaces, Y = DIRsector_buffer ptr
-ParseEntryNameSpaces ;XY
-; ==================================; output: Z flag, Y is set after the last space char
- CMP #0,X ;
- JZ PENSL_END ;
-; ----------------------------------;
-ParseEntryNameSpacesLoop ;
-; ----------------------------------;
- CMP.B #32,SD_BUF(Y) ; SPACE ?
- JNZ PENSL_END ; no: RET
- ADD #1,Y ;
- SUB #1,X ;
- JNZ ParseEntryNameSpacesLoop;
-PENSL_END ;
- MOV @RSP+,PC ;
-; ----------------------------------;
-
.IFDEF SD_CARD_READ_WRITE
; ==================================;
; compile state : compile OpenType, compile SQUOTE and the string of provided pathname
; exec state : open a file from SD card via its pathname
; convert counted string found at HERE in a String then parse it
-; media identifiers "A:", "B:" ... are ignored (only one SD_Card),
; char "\" as first one initializes rootDir as SearchDir.
; if file found, if not already open and if free handle...
; ...open the file as read and return the handle in CurrentHdl.
OPEN_EXEC ;
mDOCOL ; if exec state
.word lit,'"',WORDD,COUNT ; -- open_type addr cnt
- .word $+2 ;
+ mNEXTADR ;
MOV @RSP+,IP ;
; ----------------------------------;
ParenOpen ; -- open_type addr cnt
; ----------------------------------;
- MOV @PSP+,rDOCON ; rDOCON = addr = pathname PTR
- ADD rDOCON,TOS ; TOS = EOS (End Of String) = pathname end
+ MOV #0,S ;
+Q_SD_present ;
+ BIT.B #CD_SD,&SD_CDIN ; SD_memory in SD_Card module ?
+ JZ Q_SD_not_init ; yes
+ BIC #BUS_SD,&SD_SEL ; no, hide SIMO, SOMI & SCK pins (SD not initialized memory)
+Q_SD_not_init ;
+ BIT #BUS_SD,&SD_SEL ; is SD init by SYS ?
+ JNZ OPEN_LetUsGo ; no --> with TOS = -1 does abort
+ MOV #NO_SD_CARD,PC ; S = 0 --> error 0
+; ----------------------------------;
+OPEN_LetUsGo ;
+; ----------------------------------;
+ MOV #1,S ; error 1
+ CMP #0,TOS ; cnt = 0 ?
+ JZ OPEN_Error ; yes: error 1 ===>
+ MOV @PSP+,rDOCON ; -- open_type cnt rDOCON = addr = pathname PTR
+ ADD rDOCON,TOS ; -- open_type EOS TOS = EOS (End Of String) = pathname end
.IFDEF SD_CARD_READ_WRITE ;
MOV TOS,&PathName_END ; for WRITE CREATE part
.ENDIF
+ MOV &DIRClusterL,&ClusterL ; set DIR cluster
+ MOV &DIRClusterH,&ClusterH ;
; ----------------------------------;
-;OPN_PathName ;
-; ----------------------------------;
- MOV #2,&ClusterL ; set root DIR cluster
- MOV #0,&ClusterH ;
- MOV #1,S ; error 1
- CMP rDOCON,TOS ; PTR = EOS ? (end of pathname ?)
- JZ OPEN_Error ; yes: error 1 ===>
+OPN_AntiSlashFirstTest ;
; ----------------------------------;
- CMP.B #':',1(rDOCON) ; A: B: C: ... in pathname ?
- JNZ OPN_AntiSlashStartTest ; no
- ADD #2,rDOCON ; yes : skip drive because not used, only one SD_card
-; ----------------------------------;
-OPN_AntiSlashStartTest ;
CMP.B #'\\',0(rDOCON) ; "\" as first char ?
- JNZ OPN_SearchDirSector ; no
+ JNZ OPN_SearchInDIR ; no
ADD #1,rDOCON ; yes : skip '\' char
+ MOV #0,&ClusterH ;
+ JMP OPN_AntiSlashFirstNext ;
; ----------------------------------;
-OPN_EndOfStringTest ;
-; ----------------------------------;
- CMP rDOCON,TOS ; PTR = EOS ? (end of pathname ?)
- JZ OPN_SetCurrentDIR ; if pathname ptr = end of string
-; ----------------------------------;
-OPN_SearchDirSector ; <=== dir found in path
+OPN_SearchInDIR ; <=== dir found in path
; ----------------------------------;
MOV rDOCON,&PathName_PTR ; save Pathname ptr
- CALL #ClusterHLtoFrstSectorHL; output: SectorHL
- MOV &SecPerClus,rDODOES ; DIR sectors = one cluster sectors
; ----------------------------------;
-OPN_LoadDIRsector ; <=== Dir Sector loopback
+OPN_LoadDIRcluster ; <=== next DIR cluster loopback
; ----------------------------------;
- CALL #ReadSectorHL ;SWX
+ CALL #ClusterHLtoFrstSectorHL; output: first Sector of this cluster
+ MOV &SecPerClus,rDODOES ; set sectors count down
; ----------------------------------;
- MOV #2,S ; prepare no such file error
- MOV #0,W ; init entries count
+OPN_LoadDIRsector ; <=== next DIR Sector loopback
; ----------------------------------;
-OPN_SearchDIRentry ; <=== DIR Entry loopback
+ CALL #ReadSectorHL ;SWX,
+ MOV #2,S ; prepare error 2
+; ----------------------------------; W = 0 = DIREntryOfst
+OPN_SearchDIRentry ; <=== next DIR_Entry loopback
; ----------------------------------;
- MOV W,Y ; 1
- RLAM #4,Y ; --> * 16
- ADD Y,Y ; 1 --> * 2
- MOV Y,&DIREntryOfst ; DIREntryOfst
- CMP.B #0,SD_BUF(Y) ; free entry ? (end of entries in DIR)
- JZ OPN_NoSuchFile ; error 2 NoSuchFile, used by create ===>
+ MOV W,&DIREntryOfst ; update DIREntryOfst
+ CMP.B #0,SD_BUF(W) ; free entry ?
+ JZ OPN_NoSuchFile ; NoSuchFile error = 2 ===>
+ MOV W,Y ; 1 W = DIREntryOfst, Y = Entry_name pointer
MOV #8,X ; count of chars in entry name
; ----------------------------------;
-OPN_CompareName8chars ;
+OPN_CompareName ;
; ----------------------------------;
- CMP.B @rDOCON+,SD_BUF(Y) ; compare Pathname(char) with DirEntry(char)
- JNZ OPN_FirstCharMismatch ;
+ MOV.B @rDOCON+,T ;
+ CMP.B T,SD_BUF(Y) ; compare Pathname with DirEntry1to8, char by char
+ JNZ OPN_CompareNameNext ;
ADD #1,Y ;
SUB #1,X ;
- JNZ OPN_CompareName8chars ; loopback if chars 1 to 7 of string and DirEntry are equal
- ADD #1,rDOCON ; 9th char of Pathname is always a dot
+ JNZ OPN_CompareName ;
+ MOV.B @rDOCON+,T ; 9th char of Pathname should be '.'
+ JZ OPN_CompareNameDone ; if X = 0
; ----------------------------------;
-OPN_FirstCharMismatch ;
+OPN_CompareNameNext ; remainder of 8 chars of DIR_entry name must be spaces
; ----------------------------------;
- CMP.B #'.',-1(rDOCON) ; FirstNotEqualChar of Pathname = dot ?
- JZ OPN_DotFound ;
+ CMP.B #32,SD_BUF(Y) ; parse DIR entry up to 8th chars
+ JNZ OPN_DIRentryMismatch ; if a char of DIR entry name <> space
+ ADD #1,Y ;
+ SUB #1,X ;
+ JNZ OPN_CompareNameNext ;
; ----------------------------------;
-OPN_DotNotFound ;
+OPN_CompareNameDone ; T = "." or FirstNotEqualChar
; ----------------------------------;
- ADD #3,X ; for next cases not equal chars of DIRentry until 11 must be spaces
- CALL #ParseEntryNameSpaces ; for X + 3 chars
- JNZ OPN_DIRentryMismatch ; if a char entry <> space
- CMP.B #'\\',-1(rDOCON) ; FirstNotEqualChar of Pathname = "\" ?
+ CMP.B #'\\',T ; FirstNotEqualChar of Pathname = "\" ?
JZ OPN_EntryFound ;
- CMP rDOCON,TOS ; EOS exceeded ?
- JNC OPN_EntryFound ; yes
+; ----------------------------------;
+ MOV #3,X ; to compare 3 char extension
+ CMP.B #'.',T ; FirstNotEqualChar of Pathname = dot ?
+ JNZ OPN_CompExtensionNext ; if not
+; ----------------------------------;
+OPN_CompareExtension ;
+; ----------------------------------;
+ CMP.B @rDOCON+,SD_BUF(Y) ; compare Pathname_ext(char) with DirEntry9to11(char)
+ JNZ OPN_CompExtensionNext ;
+ ADD #1,Y ;
+ SUB #1,X ;
+ JNZ OPN_CompareExtension ;
+ JZ OPN_CompExtensionDone ;
+; ----------------------------------;
+OPN_CompExtensionNext ; remainder of 8 chars of DIR_entry extension must be spaces
+; ----------------------------------;
+ CMP.B #32,SD_BUF(Y) ; parse DIR entry up to 11th chars
+ JNZ OPN_DIRentryMismatch ; if a char of DIR entry extension <> space
+ ADD #1,Y ;
+ SUB #1,X ;
+ JNZ OPN_CompExtensionNext ;
+; ----------------------------------;
+OPN_CompExtensionDone ;
+; ----------------------------------;
+ CMP.B #'.',-2(rDOCON) ; LastCharEqual = dot ? (case of Pathname = "..\" which matches with first DIR entry = ".")
+ JZ OPN_DIRentryMismatch ; to compare with 2th DIR entry, the good one.
+ CMP TOS,rDOCON ; EOS reached ?
+ JC OPN_EntryFound ; yes
; ----------------------------------;
OPN_DIRentryMismatch ;
; ----------------------------------;
- MOV &PathName_PTR,rDOCON ; reload PathName_PTR as it was at last OPN_SearchDirSector
- ADD #1,W ; inc entry
- CMP #16,W ; 16 entries in a sector
- JNZ OPN_SearchDIRentry ; ===> loopback for search next DIR entry
+ MOV &PathName_PTR,rDOCON ; reload PathName_PTR as it was at last OPN_SearchInDIR
+ ADD #32,W ; W = DIREntryOfst + DIRentrySize
+ CMP #512,W ; out of sector bound ?
+ JNZ OPN_SearchDIRentry ; no, loopback for search next DIR entry in same sector
; ----------------------------------;
ADD #1,&SectorL ;
ADDC #0,&SectorH ;
- SUB #1,rDODOES ; dec count of Dir sectors
- JNZ OPN_LoadDIRsector ; ===> loopback for search next DIR sector
+ SUB #1,rDODOES ; count of Dir sectors reached ?
+ JNZ OPN_LoadDIRsector ; no, loopback to load next DIR sector in same cluster
; ----------------------------------;
- MOV #4,S ;
- JMP OPEN_Error ; ENd of DIR error 4 ===>
+ CALL #ClusterHLtoFAT1sectWofstY ; load FATsector in SD_Buffer, set Y = FAToffset
+ CMP #-1,0(Y) ; last DIR cluster ?
+ JNZ OPN_SetNextDIRcluster ;
+ CMP #0FFFh,2(Y) ;
+ .IFNDEF SD_CARD_READ_WRITE ;
+ JZ OPN_NoSuchFile ; yes, NoSuchFile error = 2 ===>
+ .ELSE ;
+ JNZ OPN_SetNextDIRcluster ; no
+OPN_QcreateDIRentry ; -- open_type EOS
+ CMP #4,0(PSP) ; open type = WRITE" or APPEND" ?
+ JNC OPN_NoSuchFile ; no: NoSuchFile error = 2 ===>
+OPN_AddDIRcluster ; yes
+ PUSH #OPN_LoadDIRcluster ; as RETurn of GetNewCluster: ===> loopback to load this new DIR cluster
+; ==================================;
+GetNewCluster ; called by Write_File
+; ==================================;
+ PUSH Y ; push previous FAToffset
+ PUSH W ; push previous FATsector
+ CALL #SearchMarkNewClusterHL ;SWXY input: W = FATsector Y = FAToffset, output: ClusterHL, W = FATsector of New cluster
+ CMP @RSP,W ; previous and new clusters are in same FATsector?
+ JZ LinkClusters ; yes
; ----------------------------------;
-
+UpdateNewClusterFATs ;
; ----------------------------------;
-OPN_DotFound ; not equal chars of entry name until 8 must be spaces
+ MOV @RSP,W ; W = previous FATsector
+ CALL #ReadFAT1SectorW ;SWX reload previous FATsector in buffer to link clusters
; ----------------------------------;
- CMP.B #'.',-2(rDOCON) ; LastCharEqual = dot ?
- JZ OPN_DIRentryMismatch ; case of first DIR entry = "." and Pathname = "..\"
- CALL #ParseEntryNameSpaces ; parse X spaces, X{0,...,7}
- JNZ OPN_DIRentryMismatch ; if a char entry <> space
- MOV #3,X ;
+LinkClusters ;
; ----------------------------------;
-OPN_CompareExt3chars ;
+ MOV @RSP+,W ; W = previous FATsector
+ MOV @RSP+,Y ; Y = previous FAToffset
+ MOV &ClusterL,SD_BUF(Y) ; store new cluster to current cluster address in previous FATsector buffer
+ MOV &ClusterH,SD_BUF+2(Y) ;
+ JMP SaveSectorWtoFATs ;SWXY update FATs from SD_BUF to W = previous FATsector, then RET
+; ==================================;
+ .ENDIF ; SD_CARD_READ_WRITE ;
; ----------------------------------;
- CMP.B @rDOCON+,SD_BUF(Y) ; compare string(char) with DirEntry(char)
- JNZ OPN_ExtNotEqualChar ;
- ADD #1,Y ;
- SUB #1,X ;
- JNZ OPN_CompareExt3chars ; nothing to do if chars equal
- JMP OPN_EntryFound ;
-OPN_ExtNotEqualChar ;
- CMP rDOCON,TOS ; EOS exceeded ?
- JC OPN_DIRentryMismatch ; no, loop back
- CMP.B #'\\',-1(rDOCON) ; FirstNotEqualChar = "\" ?
- JNZ OPN_DIRentryMismatch ;
- CALL #ParseEntryNameSpaces ; parse X spaces, X{0,...,3}
- JNZ OPN_DIRentryMismatch ; if a char entry <> space, loop back
+OPN_SetNextDIRcluster ;
+; ----------------------------------;
+ MOV @Y+,&ClusterL ;
+ MOV @Y,&ClusterH ;
+ JMP OPN_LoadDIRcluster ; ===> loop back to load this new DIR cluster
+; ----------------------------------;
+
; ----------------------------------;
OPN_EntryFound ; Y points on the file attribute (11th byte of entry)
; ----------------------------------;
- MOV &DIREntryOfst,Y ; reload DIRentry
- MOV SD_BUF+26(Y),&ClusterL ; first clusterL of file
- MOV SD_BUF+20(Y),&ClusterH ; first clusterH of file
+; MOV W,&DIREntryOfst ;
+ MOV SD_BUF+14H(W),&ClusterH ; first clusterH of file
+ MOV SD_BUF+1Ah(W),&ClusterL ; first clusterL of file
OPN_EntryFoundNext
- BIT.B #10h,SD_BUF+11(Y) ; test if Directory or File
+ BIT.B #10h,SD_BUF+0Bh(W) ; test if Directory or File
JZ OPN_FileFound ; is a file
; ----------------------------------;
OPN_DIRfound ; entry is a DIRECTORY
JNZ OPN_DIRfoundNext ;
CMP #0,&ClusterL ; case of ".." entry, when parent directory is root
JNZ OPN_DIRfoundNext ;
- MOV #2,&ClusterL ; set cluster as RootDIR cluster
+OPN_AntiSlashFirstNext
+ MOV #2,&ClusterL ; set clusterL as RootDIR cluster
OPN_DIRfoundNext ;
- CMP rDOCON,TOS ; EOS reached ?
- JNZ OPN_SearchDirSector ; no: (we presume that FirstNotEqualChar = "\") ==> loop back
+ CMP TOS,rDOCON ; EOS reached ?
+ JNC OPN_SearchInDIR ; no: (rDOCON points after "\") ==> loop back
; ----------------------------------;
OPN_SetCurrentDIR ; -- open_type ptr PathName_PTR is set on name of this DIR
; ----------------------------------;
MOV &ClusterL,&DIRClusterL ;
MOV &ClusterH,&DIRclusterH ;
- MOV #0,0(PSP) ; -- open_type ptr open_type = 0
+ MOV #0,0(PSP) ; -- open_type ptr set open_type = 0 = DIR
JMP OPN_Dir
; ----------------------------------;
OPN_FileFound ; -- open_type ptr PathName_PTR is set on name of file
OPEN_QDIR ;
; ----------------------------------;
CMP #0,W ;
- JZ OPEN_LOAD_END ; nothing to do
+ JNZ OPEN_QLOAD ; nothing else to do
+ MOV @IP+,PC ;
; ----------------------------------;
OPEN_QLOAD ;
; ----------------------------------;
; ----------------------------------;
; Error 1 : PathNameNotFound ; S = error 1
; Error 2 : NoSuchFile ; S = error 2
-; Error 4 : DIRisFull ; S = error 4
-; Error 8 : alreadyOpen ; S = error 8
-; Error 16 : NomoreHandle ; S = error 16
+; Error 4 : alreadyOpen ; S = error 4
+; Error 8 : NomoreHandle ; S = error 8
; ----------------------------------;
- mDOCOL ; set ECHO, type Pathname, type #error, type "< OpenError"; no return
- .word ECHO ;
- .word XSQUOTE ; don't use S register
- .byte 11,"< OpenError" ;
- .word BRAN,ABORT_SD ; to insert S error as flag, no return
+ MOV #SD_CARD_FILE_ERROR,PC ;
; ----------------------------------;
.IFDEF BOOTLOADER
; here we are after INIT_FORTH
; performs bootstrap from SD_CARD\BOOT.4th file, ready to test SYSRSTIV|USERSYS value
XBOOT CALL &HARD_APP ; WARM first calls HARD_APP (which includes INIT_HARD_SD)
- BIT.B #CD_SD,&SD_CDIN ; SD_memory in SD_Card socket ?
- JZ BOOT_YES ; if yes
-AbortBoot MOV #WARM+4,PC ; if no, resume with WARM+4, without return
-; ----------------------------------;
-BOOT_YES MOV #PSTACK-2,PSP ; preserve SYSRSTIV|USERSYS in TOS for BOOT.4TH tests
- MOV #0,0(PSP) ; set 0 for next SYS use
- mDOCOL ;
- .word XSQUOTE ; -- SYSRSTIV|USERSYS addr u
- .byte 15,"LOAD\34 BOOT.4TH\34" ; LOAD" BOOT.4TH" issues error 2 if no such file...
-; .byte 22,"NOECHO LOAD\34 BOOT.4TH\34" ; LOAD" BOOT.4TH" issues error 2 if no such file...
- .word BRAN,QUIT4 ; to interpret this string, then loop back to QUIT
+ MOV #PSTACK-2,PSP ; preserve SYSRSTIV|USERSYS in TOS for BOOT.4TH tests
+ MOV #0,0(PSP) ; set TOS = 0 for the next of XBOOT
+ mASM2FORTH ;
+ .word XSQUOTE ; -- SYSRSTIV|USERSYS addr u
+ .byte 15,"LOAD\34 BOOT.4TH\34" ; LOAD" BOOT.4TH" issues error 2 if no such file...
+ .word BRAN,QUIT4 ; to interpret this string, then loop back to QUIT1/QUIT2
; ----------------------------------;
; ==================================;
; ==================================;
FORTHWORD "NOBOOT" ; to disable BOOT
; ==================================;
- MOV #WARM,&PUCNEXT ; removes XBOOT from PUC chain.
+NOBOOT MOV #WARM,&PUCNEXT ; removes XBOOT from PUC chain.
MOV @IP+,PC ;
.ENDIF
RW_Sector_CMD ;WX <=== CMD17 or CMD24 (read or write Sector CMD)
; ==================================;
BIC.B #CS_SD,&SD_CSOUT ; set Chip Select low
- BIT.B #CD_SD,&SD_CDIN ; test Card Detect: memory card present ?
- JZ ComputePhysicalSector ; yes
- MOV #COLD,PC ; no: force COLD
; ----------------------------------;
ComputePhysicalSector ; input = logical sector...
; ----------------------------------;
MOV @RSP+,PC ;4
; ----------------------------------;
- ASMWORD "R_SECT_WX" ; Read SECTor W=lo, X=Hi
+ .IFDEF SD_CARD_READ_WRITE
+ ASMWORD "RD_SECT" ; ReaD SECTor W=lo, X=Hi
+ .ENDIF ; SD_CARD_READ_WRITE
; ==================================;
ReadSectorWX ; SWX read a logical sector
; ==================================;
.IFDEF SD_CARD_READ_WRITE
- ASMWORD "W_SECT_WX" ; Write SECTor W=lo, X=Hi
+ ASMWORD "WR_SECT" ; WRite SECTor W=lo, X=Hi
; ==================================;
WriteSectorWX ; write a logical sector
; ==================================;
.ENDIF ; SD_CARD_READ_WRITE
-; SD Error n°
-; High byte
+; ----------------------------------;
+; SD ERRORS
+; ----------------------------------;
+; 0 = NO SD_CARD
+; ----------------------------------;
+;
+; ----------------------------------;
+; High byte = 0 : FILE level error
+; ----------------------------------;
+; low byte
+; $1 = PathNameNotFound
+; $2 = NoSuchFile
+; $4 = alreadyOpen
+; $8 = NomoreHandle
+; $10 = InvalidPathname
+; $20 = DiskFull
+;
+; ----------------------------------;
+; High byte <> 0 : SD_CARD level error
+; ----------------------------------;
; 1 = CMD17 read error
; 2 = CMD24 write error
; 4 = CMD0 time out (GO_IDLE_STATE)
; 8 = ACMD41 time out (APP_SEND_OP_COND)
-; $10 = CMD16 time out (SET_BLOCKLEN)
-; $20 = not FAT32 media, low byte = partition ID
-
-; low byte, if CMD R1 response : %0xxx_xxxx
-; 1th bit = In Idle state
-; 2th bit = Erase reset
-; 3th bit = Illegal command
-; 4th bit = Command CRC error
-; 5th bit = erase sequence error
-; 6th bit = address error
-; 7th bit = parameter error
+; $10 = partition error, low byte = partition ID <> FAT32
+;
+; low byte, if CMD R1 response:
+; bit0 = In Idle state
+; bit1 = Erase reset
+; bit2 = Illegal command
+; bit3 = Command CRC error
+; bit4 = erase sequence error
+; bit5 = address error
+; bit6 = parameter error
-; Data Response Token
-; Every data block written to the card will be acknowledged by a data response token.
-; It is one byte long and has the following format:
-; %xxxx_sss0 with bits(3-1) = Status
-;The meaning of the status bits is defined as follows:
-;'010' - Data accepted.
-;'101' - Data rejected due to a CRC error.
-;'110' - Data Rejected due to a Write Error
+; low byte if Data Response Token
+; Every data block written to the card will be acknowledged by a data response token.
+; It is one byte long and has the following format:
+; %xxxx_sss0 with bits(3-1) = Status
+; The meaning of the status bits is defined as follows:
+; '010' - Data accepted.
+; '101' - Data rejected due to a CRC error.
+; '110' - Data Rejected due to a Write Error
-; ----------------------------------;
-SD_CARD_ERROR ; <=== SD_INIT errors 4,8,$10 from forthMSP430FR_SD_INIT.asm
-; ----------------------------------;
- SWPB S ; High Level error in High byte
- ADD &SD_RXBUF,S ; add SPI(GET) return value as low byte error
-SD_CARD_ID_ERROR ; <=== SD_INIT error $20 from forthMSP430FR_SD_INIT.asm
- BIS.B #CS_SD,&SD_CSOUT ; Chip Select high
- mASM2FORTH ;
- .word ECHO
- .word XSQUOTE ; don't use S register
- .byte 11,"< SD Error!" ;
-; ----------------------------------;
-ABORT_SD ; <=== OPEN file errors from forthMSP430FR_SD_LOAD.asm
-; ----------------------------------;
- mNEXTADR ;
- SUB #2,PSP ;
- MOV TOS,0(PSP) ;
- MOV #10h,&BASEADR ; select hex
- MOV S,TOS ;
- mASM2FORTH ;
- .word UDOT,ABORT_TERM ; no return...
-; ----------------------------------;
+; ------------------------------;
+SD_CARD_ERROR ; <=== SD_INIT errors 4,8,$10 from forthMSP430FR_SD_INIT.asm
+; ------------------------------;
+ SWPB S ; High Level error in High byte
+ BIS &SD_RXBUF,S ; add SPI(GET) return value as low byte error
+SD_CARD_INIT_ERROR ; <=== from forthMSP430FR_SD_INIT.asm
+SD_CARD_FILE_ERROR ; <=== from forthMSP430FR_SD_LOAD.asm, forthMSP430FR_SD_RW.asm
+NO_SD_CARD ; from forthMSP430FR_SD_LOAD(Open_File)
+ MOV S,TOS ;
+ CALL #ABORT_TERM+4 ;
+ CALL #INIT_FORTH ;
+ .IFDEF BOOTLOADER ;
+ .word NOBOOT ;
+ .ENDIF
+ .word ECHO ;
+ .word XSQUOTE ;
+ .byte 4,27,"[7m" ;
+ .word TYPE ;
+ .word XSQUOTE ;
+ .byte 10,"SD_ERROR $" ;
+ .word TYPE ;
+ .word LIT,10h ;
+ .word LIT,BASEADR,STORE;
+ .word UDOT ;
+ .word LIT,10 ;
+ .word LIT,BASEADR,STORE;
+ .word BRAN,SDABORT_END; to set normal video display then goto ABORT
+; ------------------------------;
; and only for FR5xxx and FR6xxx with RTC_B or RTC_C hardware if you want write file with date and time.
-; Tested with MSP-EXP430FR5969 launchpad
-; Copyright (C) <2015> <J.M. THOORENS>
-;
-; This program is free software: you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation, either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program. If not, see <http://www.gnu.org/licenses/>.
-
; ======================================================================
; READ" primitive as part of OpenPathName
; input from open: S = OpenError, W = open_type, SectorHL = DIRsectorHL,
; sequentially read a file opened by READ".
; sectors are loaded in SD_BUF and BufferLen leave the count of loaded bytes.
; when the last sector of file is loaded in buffer, the handle is automatically closed and flag is true (<>0).
+; to call Read_File in assembly : CALL &READ+$0C
; ==================================;
FORTHWORD "READ" ; -- fl closed flag
; ==================================;
-READ
SUB #2,PSP ;
MOV TOS,0(PSP) ;
MOV &CurrentHdl,TOS ;
CALL #Read_File ;SWX
- SUB &CurrentHdl,TOS ; -- fl if fl<>0 (if Z=0) handle is closed
+ SUB &CurrentHdl,TOS ; -- fl if true (if Z=0) handle is closed
MOV @IP+,PC ;
; ----------------------------------;
; ==================================;
SearchMarkNewClusterHL ;SWXY <== WRITE_FILE, OPEN_WRITE_CREATE, OPEN_OVERWRITE
; ==================================;
- MOV #8,S ; preset disk full return error
+ MOV #20h,S ; preset disk full return error
PUSH W ;3 R-- FATsector
; ----------------------------------;
LoadFATsectorLoop ;
MOV @RSP+,PC ; RET
; ----------------------------------;
-
-; ----------------------------------;
-
-
; ======================================================================
; DEL" primitive as part of OpenPathName
-; All "DEL"eted clusters are freed
+;;;; All "DEL"eted clusters are freed
; input from open: S = OpenError, W = open_type, SectorHL = DIRsectorHL,
; Buffer = [DIRsector], ClusterHL = FirstClusterHL
; from open(GetFreeHandle): Y = DIRentry, T = CurrentHdl
; ----------------------------------;
; 2- Delete DIR entry ;
; ----------------------------------;
- MOV.B #0E5h,SD_BUF(Y) ;
- CALL #WriteSectorHL ;SWX write SectorHL=DIRsector
-; ----------------------------------;
-; 3- free all file clusters ;
-; ----------------------------------;
- CALL #FreeAllClusters ;SWXY input: HDLL_FirstClus(T), output: FATS are updated
+ MOV.B #0E5h,SD_BUF(Y) ; mark DIRentry as deleted
+ CALL #WriteSectorHL ;SWX update SectorHL=DIRsector
+;; ----------------------------------;
+;; 3- free all file clusters ;
+;; ----------------------------------;
+; CALL #FreeAllClusters ;SWXY input: HDLL_FirstClus(T), output: FATS are updated
; ----------------------------------;
; 4- Close Handle ;
; ----------------------------------;
;-----------------------------------------------------------------------
-
; FAT16/32 format for date and time in a DIR entry
; create time : offset 0Dh = 0 to 200 centiseconds, not used.
; offset 0Eh = 0bhhhhhmmmmmmsssss, with : s=seconds*2, m=minutes, h=hours
GetYMDHMSforDIR ; output: X=date, W=TIME
; ==================================;
.IFDEF LF_XTAL ;
- .IFNDEF RTC ; RTC_B or RTC_C select
+ .IFNDEF RTC ; select RTC_B or RTC_C, not RTC
; ----------------------------------;
BIT.B #RTCHOLD,&RTCCTL1 ; rtc is running ?
JNZ SD_RW_RET ; no
; ----------------------------------;
;-----------------------------------------------------------------------
-; WRITE" subroutines
+; WRITE subroutines
;-----------------------------------------------------------------------
-; write sequentially the buffer in the post incremented SectorHL.
-; The first time, SectorHL is initialized by WRITE".
+;Z WRITE --
+; write sequentially the SD_buffer in the post incremented SectorHL.
+; The first SectorHL is initialized by WRITE".
+; the last sector will be processed by CLOSE
; All used registers must be initialized.
+; to call Write_File in assembly : CALL #WRITE+4
+
+; ==================================;
+ FORTHWORD "WRITE" ; encapsulate Write_File
+; ==================================;
+ PUSH #WRITE_END ;
+; ----------------------------------;
+
; ==================================;
-Write_File ;STWXY <== WRITE, SD_EMIT, TERM2SD"
+Write_File ;STWXY <== WRITE, SD_EMIT, TERM2SD", BUT NOT CLOSE !
; ==================================;
- MOV #BytsPerSec,&BufferPtr ; write always all the buffer
+ MOV #BytsPerSec,&BufferPtr ; write always all the buffer, the last written buffer will be processed directly by CloseHandle
MOV &CurrentHdl,T ;
CALL #WriteSD_Buf ;SWX write SD_BUF and update Handle informations only for DIRentry update
MOV #0,&BufferPtr ; reset buffer pointer
JNC Write_File_End ; no,
; ----------------------------------;
CALL #HDLcurClus2FATsecWofstY;WXY Output: FATsector W=FATsector, Y=FAToffset
- PUSH Y ; push previous FAToffset
- PUSH W ; push previous FATsector
-; ----------------------------------;
-GetNewCluster ; input : T=CurrentHdl
-; ----------------------------------;
- CALL #SearchMarkNewClusterHL ;SWXY input: W = FATsector Y = FAToffset, output: ClusterHL, W = FATsector of New cluster
- CMP @RSP,W ; previous and new clusters are in same FATsector?
- JZ LinkClusters ; yes
-; ----------------------------------;
-UpdateNewClusterFATs ;
-; ----------------------------------;
- MOV @RSP,W ; W = previous FATsector
- CALL #ReadFAT1SectorW ;SWX reload previous FATsector in buffer to link clusters
-; ----------------------------------;
-LinkClusters ;
-; ----------------------------------;
- MOV @RSP+,W ; W = previous FATsector
- MOV @RSP+,Y ; Y = previous FAToffset
- MOV &ClusterL,SD_BUF(Y) ; store new cluster to current cluster address in previous FATsector buffer
- MOV &ClusterH,SD_BUF+2(Y) ;
- CALL #SaveSectorWtoFATs ;SWXY update FATs from SD_BUF to W = previous FATsector
+ CALL #GetNewCluster ;
; ==================================;
HDLSetCurClustSetFrstSect ;
; ==================================;
+ MOV.B #0,HDLB_ClustOfst(T) ; clear current Cluster offset
MOV #4,HDLB_Token(T) ; and clear ClustOfst
; ==================================;
HDLSetCurClustSetCurSect ;
; ==================================;
MOV &ClusterL,HDLL_CurClust(T) ; update handle with new cluster
MOV &ClusterH,HDLH_CurClust(T) ;
-Write_File_End
- MOV #ClusterHL2sectorHL,PC ;W set current SectorHL to be written
+; ----------------------------------;
+Write_File_End ;
+ MOV #ClusterHL2sectorHL,PC ;W set current SectorHL to be written, then RET
; ----------------------------------;
-;Z WRITE --
-; sequentially write the entire SD_BUF in a file opened by WRITE"
-; ==================================;
- FORTHWORD "WRITE" ; in assembly : CALL #WRITE,X CALL 2(X)
-; ==================================;
- CALL #Write_File ;STWXY
+; ----------------------------------;
+WRITE_END
MOV @IP+,PC ;
; ----------------------------------;
; ----------------------------------;
CMP #2,S ; "no such file" error ?
JZ OPEN_WRITE_CREATE ; yes, Handle is to be created !
- CMP #0,S ; well opened file ?
+ CMP #0,S ; already opened file ?
JZ OPEN_OVERWRITE ; yes, handle is created
; ----------------------------------;
OPWC_Write_Errors ;
-; ----------------------------------;
-OPWC_InvalidPathname ; S = 4
-OPWC_DiskFull ; S = 8
+OPWC_InvalidPathname ; S = $10
+OPWC_DiskFull ; S = $20
; ----------------------------------;
OPW_Error ; set ECHO, type Pathname, type #error, type "< WriteError"; no return
- mDOCOL ;
- .word XSQUOTE ;
- .byte 12,"< WriteError",0 ;
- .word BRAN,ABORT_SD ; to insert S error as flag, no return
+ MOV #SD_CARD_FILE_ERROR,PC ;
; ----------------------------------;
; ======================================================================
; output: nothing (no message if open error)
; ======================================================================
-
; ==================================;
OPEN_WRITE_CREATE ; a new Handle is to be created
; ==================================;
; ----------------------------------;
CALL #ReadSectorHL ; reload DIRsector
MOV &DIREntryOfst,Y ; Y = entry offset (first free entry in DIR)
- MOV.B #20h,SD_BUF+11(Y) ; file attribute = file
+ MOV.B #20h,SD_BUF+0Bh(Y) ; file attribute = file
CALL #GetYMDHMSforDIR ;WX X=DATE, W=TIME
- MOV #0,SD_BUF+12(Y) ; nt reserved = 0 and centiseconds are 0
- MOV W,SD_BUF+14(Y) ; time of creation
- MOV X,SD_BUF+16(Y) ; date of creation 20/08/2001
-; MOV X,SD_BUF+18(Y) ; date of access 20/08/2001
- MOV &ClusterH,SD_BUF+20(Y) ; as first Cluster Hi
- MOV &ClusterL,SD_BUF+26(Y) ; as first cluster LO
- MOV #0,SD_BUF+28(Y) ; set file_sizeLO = 0
- MOV #0,SD_BUF+30(Y) ; set file_sizeHI = 0
+ MOV W,SD_BUF+0Eh(Y) ; time of creation
+ MOV X,SD_BUF+10h(Y) ; date of creation 20/08/2001
+ MOV &ClusterH,SD_BUF+14h(Y) ; as first Cluster Hi
+ MOV &ClusterL,SD_BUF+1Ah(Y) ; as first cluster LO
+ MOV #0,SD_BUF+1Ch(Y) ; set file_sizeLO = 0
+ MOV #0,SD_BUF+1Eh(Y) ; set file_sizeHI = 0
; ----------------------------------;
; 4 create DIRentryName ; file name format "xxxxxxxx.yyy"
; ----------------------------------;
- MOV #4,S ; preset pathname error
+ MOV #10h,S ; preset pathname error
MOV &PathName_PTR,T ; here, PathName_PTR is set to file name
CMP T,&PathName_END ; end of string reached ?
- JZ OPWC_InvalidPathname ; yes write error 1
+ JZ OPWC_InvalidPathname ; yes write error $10
CMP.B #'.',0(T) ; forbidden "." in first
- JZ OPWC_InvalidPathname ; write error 1
+ JZ OPWC_InvalidPathname ; write error $10
MOV #11,X ; X=countdown of chars entry
CALL #FillDIRentryName ;STWXY
; ----------------------------------;
MOV @IP+,PC ; --
; ----------------------------------;
-
; ======================================================================
; APPEND" primitive as part of OpenPathName
; input from open: SectorHL = DIRsectorHL,
OPEN_8W ;
CMP #2,S ; "no such file" error ?
JZ OPEN_WRITE_CREATE ; if yes, handle is to be created
- CMP #0,S ; well opened file ?
+ CMP #0,S ; already opened file ?
JNZ OPWC_Write_Errors ; no
; ==================================;
OPEN_WRITE_APPEND ; yes, handle is already created
; ----------------------------------;
- .IFNDEF TERMINAL_I2C ; if UART_TERMINAL
+ .IFDEF TERMINALBAUDRATE ; if UART_TERMINAL
; first TERATERM sends the command TERM2SD" file.ext" to FastForth which returns XOFF at the end of the line.
; then when XON is sent below, TERATERM sends "file.ext" up to XOFF sent by TERM2SD" (slices of 512 bytes),
FORTHWORD "TERM2SD\34" ;
; ==================================;
mDOCOL ;
- .word WRITEDQ ; if already exist FreeAllClusters else create it as WRITE file
+ .word WRITEDQ ; if already exist Free All Clusters else create it as WRITE file
mNEXTADR ;
; ----------------------------------;
T2S_GetSliceLoop ; tranfert by slices of 512 bytes from terminal input to file on SD_CARD via SD_BUF
; ----------------------------------;
- MOV #0,W ;1 reset W = BufferPtr
- CALL #RXON ; use no registers
+ MOV #0,W ;1 clear W = BufferPtr
+ CALL #UART_RXON ; use no registers
; ----------------------------------;
T2S_Get_a_Char_Loop ;
; ----------------------------------;
; ----------------------------------;
T2S_XOFF ; 27 cycles between XON and XOFF
; ----------------------------------;
- CALL #RXOFF ;4 use no registers
+ CALL #UART_RXOFF ;4 use no registers
JMP T2S_Get_a_Char_Loop ;2 loop back once to get char sent by TERMINAL during XOFF time
; ----------------------------------;
T2S_End_Of_File ; wait CR before sending XOFF
CMP.B #0Dh,&TERM_RXBUF ; also clears RX_IFG !
JZ T2S_Wait_CR ; wait CR
; ----------------------------------;
- CALL #RXOFF ;4 use no registers
+ CALL #UART_RXOFF ;4 use no registers
; ----------------------------------;
T2S_Wait_LF ; warning! EOT must be followed by CR+LF (TERM2SD" used with I2C_FastForth)
; ----------------------------------;
FORTHWORD "TERM2SD\34" ; here, I2C_Master is reSTARTed in RX mode
; ==================================;
mDOCOL ;
+ .word WRITEDQ ; if already exist FreeAllClusters else create it as WRITE file
; ----------------------------------;
.word NOECHO ; comment this line to echo chars
; ----------------------------------;
- .word WRITEDQ ; if already exist FreeAllClusters else create it as WRITE file
mNEXTADR ;
; ----------------------------------;
- MOV #0,W ; reset W = SD_Buf_Ptr
+ MOV #0,W ; clear W = SD_Buf_Ptr
MOV.B #0Ah,IP ; IP = char 'LF'
; ----------------------------------;
T2S_GetLineLoop ; tranfert line by line from terminal input to SD_BUF
; ----------------------------------;
- CALL #RXON ; use Y reg; send I2C Ctrl_Char $00 to request I2C_Master to switch from RX to TX
+ CALL #I2C_ACCEPT ; use Y reg; send I2C Ctrl_Char $00 to request I2C_Master to switch from RX to TX
; ----------------------------------;
T2S_Get_a_Char_Loop ;
; ----------------------------------;
; ----------------------------------;
T2S_Q_EOF ;
; ----------------------------------;
- CMP.B #4,X ;1 EOF sent by TERMINAL (teraterm.exe) ?
+ CMP.B #4,X ;1 EOT sent by TERMINAL (teraterm.exe) ?
JZ T2S_End_Of_File ;2 yes
MOV.B X,SD_BUF(W) ;3
ADD #1,W ;1
JNZ T2S_Wait_LF ;
; ----------------------------------; here I2C_Master switches from TX to RX
MOV W,&BufferPtr ; to add it to HDLL_CurSize
- CALL #CloseHandle ; tranfert SD_BUF to last sector of opened file in SD_CARD then close it
+ CALL #CloseHandle ; tranfert SD_BUF to last sector of opened file in SD_CARD then close it
; ----------------------------------;
MOV @RSP+,IP ;
MOV #ECHO,PC ;
; LP_MSP430FR2476 P1.4 P1.5 P6.1
;
;-------------------------------------------------------------------------------
-; UART TERMINAL: QABORT COLD_TERM INIT_TERM RXON RXOFF
+; UART TERMINAL: QABORT ABORT_TERM INIT_BACKGRND RXON INIT_FORTH INIT_TERM INIT_COLD INIT_SOFT
;-------------------------------------------------------------------------------
-; define run-time part of ABORT" ; if f is true display msg. then abort current process
-QABORT CMP #0,2(PSP) ; -- f c-addr u test flag f
- JNZ ABORT_TERM ; see forthMSP430FR_TERM_xxxx.asm below
-THREEDROP ADD #4,PSP ; -- u
+;-----------------------------------;
+INIT_FORTH ; common ABORT_TERM|WARM subroutine, to init DEFERed definitions + INIT_FORTH
+;-----------------------------------;
+ MOV @RSP+,IP ; init IP with CALLER next address
+; ;
+ MOV #PUC_ABORT_ORG,X ; FRAM INFO FRAM MAIN
+; ; --------- ---------
+ MOV @X+,&PFAACCEPT ; BODYACCEPT --> PFAACCEPT
+ MOV @X+,&PFAEMIT ; BODYEMIT --> PFAEMIT
+ MOV @X+,&PFAKEY ; BODYKEY --> PFAKEY
+ MOV @X+,&CIB_ORG ; TIB_ORG --> CIB_ORG
+; ;
+; ; FRAM INFO REG|RAM
+; ; --------- -------
+ MOV @X+,RSP ; INIT_RSTACK --> R1=RSP
+ MOV @X+,rDOCOL ; EXIT --> R4=rDOCOL (if DTC=2)
+ MOV @X+,rDODOES ; XDODOES --> R5=rDODOES
+ MOV @X+,rDOCON ; XDOCON --> R6=rDOCON
+ MOV @X+,rDOVAR ; RFROM --> R7=rDOVAR
+ MOV @X+,&CAPS ; INIT_CAPS --> RAM CAPS init CAPS ON
+ MOV @X+,&BASEADR ; INIT_BASE --> RAM BASE init decimal base
+ MOV @X+,&LEAVEPTR ; INIT_LEAVE --> RAM LEAVEPTR
+ MOV #0,&STATE ; 0 --> RAM STATE
+ CALL &SOFT_APP ; default SOFT_APP = INIT_SOFT = RET_ADR, value set by DEEP_RESET.
+ MOV #SEL_RST,PC ; goto PUC 7 to select the user's choice from TOS value: RST_RET|DEEP_RESET
+;-----------------------------------;
+
+; ?ABORT defines the run-time part of ABORT"
+;-----------------------------------;
+QABORT CMP #0,2(PSP) ; -- f addr cnt if f is true abort current process then display ABORT" msg.
+ JNZ ABORT_TERM ;
+THREEDROP ADD #4,PSP ; -- cnt
JMP DROP ;
+ABORT_TERM PUSH #ABORT_INIT ; called by INTERPRET, QREVEAL, TYPE2DOES
; ----------------------------------;
-UART_ABORT_TERM ; exit from downloading then reinit some variables via INIT_FORTH
+UART_ABORT CALL #UART_RXON ;
; ----------------------------------;
-ABORT_TERM CALL #RXON ; resume downloading source file if any
A_UART_LOOP BIC #RX_TERM,&TERM_IFG ; clear RX_TERM
- MOV &FREQ_KHZ,Y ; 1000, 2000, 4000, 8000, 16000, 240000
+ MOV &FREQ_KHZ,Y ; 1000, 2000, 4000, 8000, 16000, 24000
A_USB_LOOPJ MOV #65,X ; 2~ <-------+ linux with minicom seems very very slow...
-A_USB_LOOPI SUB #1,X ; 1~ <---+ | ==> ((65*3)+5)*1000 = 200ms delay
- JNZ A_USB_LOOPI ; 2~ 3~ loop ---+ | to refill its USB buffer
+A_USB_LOOPI SUB #1,X ; 1~ <---+ | ...to refill its USB buffer
+ JNZ A_USB_LOOPI ; 2~ 3~ loop ---+ | ==> ((65*3)+5)*1000 = 200ms delay
SUB #1,Y ; 1~ |
JNZ A_USB_LOOPJ ; 2~ 200~ loop -----+
- BIT #RX_TERM,&TERM_IFG ; 4 new char in TERMRXBUF after A_USB_LOOPJ delay ?
+ BIT #RX_TERM,&TERM_IFG ; 4 new char in TERMRXBUF after 200ms delay ?
JNZ A_UART_LOOP ; 2 yes, the input stream is still active: loop back
- CALL #INIT_FORTH ; common ?ABORT|PUC subroutine to init DEFERed definitions
- ; cnt is a byte, always positive. If cnt = 0 no RST_RET.
- .word DUP ;
- .word QFBRAN,ABORT_END; display nothing, don't force ECHO if ABORT" empty string
- .word ECHO ; force ECHO
+ MOV @RSP+,PC
+; ----------------------------------;
+ABORT_INIT CALL #INIT_FORTH ; common ?ABORT|PUC subroutine
+ .word DUP ; -- f addr cnt cnt
+ .word QFBRAN,ABORT_END; -- f addr 0 don't force ECHO, no display if ABORT" is an empty string
+ .word ECHO ; -- f addr cnt force ECHO
.word XSQUOTE ;
.byte 4,27,"[7m" ;
- .word TYPE ; type ESC [7m (set reverse video)
+ .word TYPE ; ESC [7m = set reverse video
; ----------------------------------;
-; Display QABORT|WARM message ; <== WARM jumps here
+; Display QABORT|WARM message ; -- addr cnt <== WARM jumps here
; ----------------------------------;
-ABORT_TYPE .word TYPE ; -- f type QABORT|WARM message
- .word XSQUOTE ; -- f c-addr u
+ABORT_TYPE .word TYPE ; -- f type QABORT|WARM message
+SDABORT_END .word XSQUOTE ; set normal video Display then goto ABORT
.byte 4,27,"[0m" ;
- .word TYPE ; -- f set normal video
-ABORT_END .word ABORT ; -- f no return
+ .word TYPE ; ESC [0m = set normal video
+ABORT_END .word ABORT ; -- f no return
; ----------------------------------;
;-------------------------------------------------------------------------------
; INIT TERMinal then enable I/O ;
;-------------------------------------------------------------------------------
-UART_INIT_TERM ; see MSP430FRxxxx.pat file
+INIT_HARD ;
; ----------------------------------;
-INIT_TERM ; TOS = USERSYS, don't change it
- CALL #COLD_TERM ; wait while TERM_UART is busy
- MOV #0081h,&TERM_CTLW0 ; UC SWRST + UCLK = SMCLK
- MOV &TERMBRW_RST,&TERM_BRW ; init value in FRAM
- MOV &TERMMCTLW_RST,&TERM_MCTLW ; init value in FRAM
+INIT_TERM ; default content of HARD_APP called by WARM
+; ----------------------------------;
+ MOV #0081h,&TERM_CTLW0 ; 8 bits, UC SWRST + UCLK = SMCLK, max 6MBds @24MHz
+ MOV &TERMBRW_RST,&TERM_BRW ; init value in FRAM INFO
+ MOV &TERMMCTLW_RST,&TERM_MCTLW ; init value in FRAM INFO
BIS.B #BUS_TERM,&TERM_SEL ; Configure pins TERM_UART|TERM_I2C
BIC #1,&TERM_CTLW0 ; release UC_TERM from reset...
BIS #WAKE_UP,&TERM_IE ; then enable interrupt for wake up on terminal input
; ----------------------------------;
; ----------------------------------;
-UART_COLD_TERM ; default STOP_APP: wait TERMINAL idle
-; ----------------------------------;
-WAIT_UART_IDLE
-COLD_TERM BIT #1,&TERM_STATW ;3 uart busy ?
- JNZ COLD_TERM ;2 loop back while TERM_UART is busy
+INIT_STOP ; default STOP_APP, called by SYS: wait end of TX to TERMINAL
; ----------------------------------;
-UART_INIT_SOFT ;
+TX_IDLE BIT #1,&TERM_STATW ;3 uart busy ?
+ JNZ TX_IDLE ;2 loop back while TERM_UART is busy
; ----------------------------------;
-INIT_SOFT_TERM
- MOV @RSP+,PC ; does nothing by default
+INIT_SOFT MOV @RSP+,PC ;
; ----------------------------------;
;-------------------------------------------------------------------------------
-; UART TERMINAL : WARM SYS COLD
+; UART TERMINAL : SYS COLD RESET WARM
;-------------------------------------------------------------------------------
-; ----------------------------------; thanks to INIT_FORTH, WARM implements the choice
-UART_WARM ; made by the user with SYS|hardwareRST|DEEP_reset
-;-----------------------------------; regarding the state of the software.
-WARM CALL &HARD_APP ;
- mASM2FORTH ;
- .word ECHO ;
- .word XSQUOTE
- .byte 7,13,10,27,"[7m#" ; CR + cmd "reverse video" + #
- .word TYPE
- .word DOT ; display TOS = USERSYS value
- .word XSQUOTE
- .byte 25,"FastForth ",169,"J.M.Thoorens, "
- .word TYPE
- .word LIT,FRAM_FULL
- .word HEREXEC,MINUS,UDOT
- .word XSQUOTE
- .byte 10,"bytes free"
- .word BRAN,ABORT_TYPE ; without return!
+
+;-----------------------------------;
+UART_WARM ; (n) --
+;-----------------------------------;
+WARM CALL &HARD_APP ; default HARD_APP = INIT_TERM, value set by DEEP_RESET.
+ mASM2FORTH ;
+ .word ECHO ;
+ .word XSQUOTE ;
+ .byte 7,13,10,27,"[7m#" ; CR + cmd "reverse video" + #
+ .word TYPE ;
+ .word DOT ; display TOS = USERSYS value
+ .word XSQUOTE ;
+ .byte 25,"FastForth ",169 ;
+ .byte "J.M.Thoorens, " ;
+ .word TYPE ;
+ .word LIT,FRAM_FULL ;
+ .word HERE,MINUS,UDOT ;
+ .word XSQUOTE ;
+ .byte 10,"bytes free" ;
+ .word BRAN,ABORT_TYPE ; without return
;-----------------------------------;
;-----------------------------------;
- FORTHWORD "SYS" ; n -- software RST, DEEP_RST, COLD, WARM
+ FORTHWORD "SYS" ; n -- select COLD, DEEP_COLD, WARM (as software RST,DEEP_RST,WARM)
;-----------------------------------;
+SYS CALL &STOP_APP ; default STOP_APP = INIT_STOP, set by DEEP_RESET.
CMP #0,TOS ;
- JL SYSEND ; if -n SYS ==> COLD + DEEP_RESET
- JZ NOPUC ; if [0] SYS
+ JL TOS2COLD ; if -n SYS --> COLD --> PUC --> INIT_FORTH --> DEEP_RESET --> WARM
+ JZ TOS2WARM ; if [0] SYS --> INIT_FORTH --> WARM
BIT #1,TOS ;
- JNC SYSEND ; if +n SYS (+n even)
-NOPUC PUSH #WARM ;
- PUSH RSP ; Push address of WARM address
- JMP INIT_FORTH ; if +n SYS (+n odd) ==> INIT_FORTH --> WARM --> WARM display
-SYSEND MOV TOS,&USERSYS ; ==> COLD --> PUC --> INIT_FORTH --> WARM --> WARM display
-;===============================================================================
-COLD ; <--- USER_NMI vector <--- <RESET> and <RESET> + <SW1> (DEEP_RESET)
-;===============================================================================
-; as pin RST is replaced by pin NMI, RESET by pin activation is redirected here via USER NMI vector
+ JZ TOS2COLD ; if +n SYS (+n even)--> COLD --> PUC --> INIT_FORTH --> WARM
+TOS2WARM CALL #INIT_FORTH ; if +n SYS (+n odd) --> INIT_FORTH --> WARM
+FWARM .word WARM ; no return
+TOS2COLD MOV TOS,&USERSYS ;
+;*******************************************************************************
+COLD ; <--- USER_NMI vector <------------------------ <RESET> | <RESET+SW1>
+;*******************************************************************************
+; as pin RST is replaced by pin NMI, hardware RESET is redirected here via USER NMI vector
; that allows actions to be performed before executing software BOR.
- CALL &COLD_APP ; to stop APPlication before reset
BIT.B #SW1,&SW1_IN ; <SW1> pressed ?
- JNZ COLDEXE ; no
+ JNZ DO_BOR ; no
MOV #-1,&USERSYS ; yes, set negative value to force DEEP_RESET
-COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR ------------------------+
-;=============================================================================== |
-RESET ; <-- RST vect. <-- SYS_failures PUC POR BOR <--+
-;===============================================================================
+DO_BOR MOV #0A504h,&PMMCTL0 ; ---------------------------> software_BOR --->+
+;******************************************************************************* |
+;******************************************************************************* v
+RESET ; <--- RST vector <----------- PUC <--- POR <---+<--- BOR <--- SYS_failures
+;*******************************************************************************
+;*******************************************************************************
; PUC 1: replace pin RESET by pin NMI, stops WDT_RESET
;-------------------------------------------------------------------------------
- BIS #3,&SFRRPCR ; pin RST becomes pin NMI with falling edge, so SYSRSTIV = 4
- BIS #10h,&SFRIE1 ; enable NMI interrupt ==> hardware RESET is redirected to COLD.
+ BIS #1,&SFRRPCR ; pin RST becomes pin NMI with rising edge, SYSRSTIV = 6, hardware RESET is redirected to COLD
+ BIS #10h,&SFRIE1 ; enable NMI pin interrupt.
MOV #5A80h,&WDTCTL ; disable WDT RESET
;-------------------------------------------------------------------------------
; PUC 2: INIT STACK
MOV #0,RAM_ORG(X) ; 3
JNZ INITRAMLOOP ; 2 6 cycles loop !
;-------------------------------------------------------------------------------
-; PUC 5: GET SYSRSTIV and SYS_USER ; X = 0
+; PUC 5: GET SYSRSTIV and USERSYS
;-------------------------------------------------------------------------------
MOV &SYSRSTIV,X ; X <-- SYSRSTIV <-- 0
- MOV &USERSYS,TOS ; TOS = USERSYS
- MOV #0,&USERSYS ; clear USERSYS
- AND #-1,TOS ;
+ MOV &USERSYS,TOS ; TOS = FRAM USERSYS
+ MOV #0,&USERSYS ; clear FRAM USERSYS
+ BIT #-1,TOS ;
JNZ PUC6 ; if TOS <> 0, keep USERSYS value
- MOV X,TOS ; TOS <-- SYSRSTIV
+ MOV X,TOS ; else TOS <-- SYSRSTIV
;-------------------------------------------------------------------------------
-; PUC 6: START FORTH engine
+; PUC 6: START FORTH engine: WARM (BOOT)
;-------------------------------------------------------------------------------
PUC6 CALL #INIT_FORTH ; common part of QABORT|PUC
-PUCNEXT .WORD WARM ; no return. May be redirected by BOOT.
+PUCNEXT .word WARM ; no return. May be redirected by BOOT.
;-----------------------------------;
;-------------------------------------------------------------------------------
-; INTERPRETER INPUT: ACCEPT KEY EMIT ECHO NOECHO
+; INTERPRETER INPUT: ACCEPT RXOFF KEY EMIT ECHO NOECHO
;-------------------------------------------------------------------------------
- FORTHWORD "ACCEPT"
+ FORTHWORD "ACCEPT" ;
;-----------------------------------;
;https://forth-standard.org/standard/core/ACCEPT
;C ACCEPT addr addr len -- addr len' get line at addr to interpret len' chars
MOV IP,S ; S = ACCEPT_ret
MOV #CR_NEXT,IP ;2 IP = XOFF_ret
PUSHM #5,IP ;5 PUSHM IP,S,T,W,X r-- XOFF_ret ACCEPT_ret BL CR buf_end
- JMP SLEEP ;2
-; ----------------------------------;
+ NOP ; to do same BACKGRND offset
+
+; here, FAST FORTH sleeps, waiting any interrupt.
+; IP,S,T,W,X,Y registers (R13 to R8) are free...
+; ...and also TOS, PSP and RSP stacks within their rules of use.
+;###################################################################################
+BACKGRND CALL &BACKGRND_APP ; default BACKGRND_APP = UART_RXON, value set by DEEP_RESET.
+ BIS &LPM_MODE,SR ;2 enter in LPM0 mode with GIE=1
+ JMP BACKGRND ;2 return for all interrupts.
+;###################################################################################
-; **********************************;
-TERMINAL_INT ; <--- TEMR RX interrupt vector, delayed by the LPMx wake up time
-; **********************************; if wake up time increases, max bauds rate decreases...
-; (ACCEPT) part II under interrupt ; Org Ptr -- len'
-; ----------------------------------;
- ADD #4,RSP ;1 remove SR and PC from stack, SR flags are lost (unused by FORTH interpreter)
- POPM #3,IP ;6 POPM W=buffer_bound, T=0Dh, S=20h, IP=ACCEPT_RET r-- XOFF_ret
-; ----------------------------------;
-AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read character into Y, RX_TERM is cleared
-; ----------------------------------;
- CMP.B T,Y ;1 CR ?
- JNZ AKEYRDNNEXT ;2 no
-; ----------------------------------;
-RXOFF ; Software|hardware flow control to stop RX UART r-- ACCEPT_ret CR_NEXT
; ----------------------------------;
+UART_RXOFF ; Software|hardware flow control to stop RX UART
+; ----------------------------------; RXOFF is sent while LF char is received...
.IFDEF TERMINAL3WIRES ; first software flow control
RXOFF_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char
JZ RXOFF_LOOP ;2
BIS.B #RTS,&HANDSHAKOUT ;3 set RTS high
.ENDIF ;
MOV @RSP+,PC ;4 to CR_NEXT
+; ----------------------------------; RXOFF is sent while LF char is received...
+
+; **********************************;
+TERMINAL_INT ; <--- TEMR RX interrupt vector, delayed by the LPM0 wake up time
+; **********************************; if wake up time increases, max bauds rate decreases...
+; ACCEPT part II under interrupt ; Org Ptr -- len' all SR flags are cleared
; ----------------------------------;
-AKEYRDNNEXT CMP.B S,Y ;1 printable char ?
+ ADD #4,RSP ;1 remove PC and SR from stack
+ POPM #4,IP ;6 POPM W=BUF_end, T='CR', S='BL', IP=ACCEPT_ret r-- XOFF_ret
+; ----------------------------------;
+AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read character into Y, RX_TERM is cleared
+; ----------------------------------;
+ CMP.B S,Y ;1 printable char ?
JC ASTORETEST ;2 yes
; ----------------------------------;
+ CMP.B T,Y ;1 CR ?
+ JZ UART_RXOFF ;2 yes
+; ----------------------------------;
CMP.B #8,Y ;1 char = BS ?
JNE WAITaKEY ;2 case of other control chars
; ----------------------------------;
; end of backspace ;
; ----------------------------------;
ASTORETEST CMP W,TOS ; 1 Bound is reached ?
- JC YEMIT ; 2 yes: don't store char @ Ptr, don't increment TOS
+ JC WAITaKEY ; 2 yes: don't store char @ Ptr, don't increment TOS
MOV.B Y,0(TOS) ; 3 no: store char @ Ptr
ADD #1,TOS ; 1 increment Ptr
; ----------------------------------;
WAITaKEY BIT #RX_TERM,&TERM_IFG ; 3 new char in TERMRXBUF ?
- JNZ AKEYREAD ; 2 yes
+ JNZ AKEYREAD ; 2 yes, loop = 21~ by char ==> 476 kBds/MHz
JZ WAITaKEY ; 2 no
; ----------------------------------;
; return of RXOFF
; ----------------------------------;
-CR_NEXT SUB @PSP+,TOS ; -- len'
-WAITLF BIT #RX_TERM,&TERM_IFG ; char 'LF' is received ?
- JZ WAITLF ; no
- MOV.B &TERM_RXBUF,Y ; yes, clear RX_int flag after LF received
+CR_NEXT BIT #RX_TERM,&TERM_IFG ; char 'LF' is received ?
+ JZ CR_NEXT ; no
+ MOV.B &TERM_RXBUF,Y ; yes, clear RX_IFG flag after LF received
; ----------------------------------;
-ACCEPT_EOL MOV S,Y ; output a BL on TERMINAL (for the case of error occuring)
- JMP YEMIT ; before return to ABORT to interpret line
-; **********************************; UF9 to UF11 are reset.
+ SUB @PSP+,TOS ; -- len' R-- ACCEPT_NEXT
+ MOV @RSP+,IP ; R--
+ACCEPT_EOL MOV.B S,Y ; output a BL on TERMINAL (for the case of error occuring)
+ JMP QYEMIT ; before return to QUIT to interpret line
+; **********************************; UF9 to UF11 will be resetted.
-; ------------------------------------------------------------------------------
-; TERMINAL I/O, input part
-; ------------------------------------------------------------------------------
+;-----------------------------------;
FORTHWORD "KEY"
+;-----------------------------------;
; https://forth-standard.org/standard/core/KEY
; KEY -- c wait character from input device ; primary DEFERred word
KEY MOV @PC+,PC ;4 Code Field Address (CFA) of KEY
PFAKEY .word BODYKEY ; Parameter Field Address (PFA) of KEY, with default value
BODYKEY PUSH #KEYNEXT ;
; ----------------------------------;
-RXON ; default BACKGND_APP
+INIT_BACKGRND ; default content of BACKGRND_APP called by BACKGRND
+; ----------------------------------;
+UART_RXON ;
; ----------------------------------;
.IFDEF TERMINAL3WIRES ; first software flow control
-RXON_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char, useless at high baudrates
- JZ RXON_LOOP ;2
+ BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char, useless at high baudrates
+ JZ UART_RXON ;2
MOV #17,&TERM_TXBUF ;4 move char XON into TX_buf
.ENDIF ;
.IFDEF TERMINAL4WIRES ; and hardware flow control after
BIC.B #RTS,&HANDSHAKOUT ;3 set RTS low
.ENDIF ;
- MOV @RSP+,PC ;4 to BACKGND (End of file download or quiet input) or AKEYREAD...
-; ----------------------------------; ... (get next line of file downloading), or user defined
+ MOV @RSP+,PC ;4
+; ----------------------------------;
KEYNEXT SUB #2,PSP ;1 push old TOS..
MOV TOS,0(PSP) ;3 ..onto stack
KEYLOOP BIT #RX_TERM,&TERM_IFG ; loop if bit0 = 0 in interupt flag register
JZ KEYLOOP ;
+ CALL #UART_RXOFF ;
MOV &TERM_RXBUF,TOS ;
- CALL #RXOFF ;
MOV @IP+,PC
+;-----------------------------------;
-; ------------------------------------------------------------------------------
-; TERMINAL I/O, output part
-; ------------------------------------------------------------------------------
+;-----------------------------------;
FORTHWORD "EMIT"
+;-----------------------------------;
; https://forth-standard.org/standard/core/EMIT
; EMIT c -- output character to the selected output device ; primary DEFERred word
EMIT MOV @PC+,PC ;4 Code Field Address (CFA) of EMIT
PFAEMIT .word BODYEMIT ; Parameter Field Address (PFA) of EMIT, with its default value
BODYEMIT MOV TOS,Y ;1 output character to the default output: TERMINAL
MOV @PSP+,TOS ;2
-YEMIT BIT #TX_TERM,&TERM_IFG ; 3 wait the sending end of previous char, useless at high baudrates
- JZ YEMIT ; 2
+QYEMIT BIT #TX_TERM,&TERM_IFG ; 3 NOECHO stores here : MOV @IP+,PC, ECHO store here the first word of: BIT #TX_TERM,&TERM_IFG
+ JZ QYEMIT ; 2
.IFDEF TERMINAL5WIRES ;
-YEMIT1 BIT.B #CTS,&HANDSHAKIN ;
- JNZ YEMIT1
+QYEMIT1 BIT.B #CTS,&HANDSHAKIN ;
+ JNZ QYEMIT1 ;
.ENDIF
-QYEMIT MOV.B Y,&TERM_TXBUF ; 3 may be replaced by MOV @IP+,PC with NOECHO
+ MOV.B Y,&TERM_TXBUF ; 3
MOV @IP+,PC ;
- FORTHWORD "ECHO"
-;Z ECHO -- connect terminal output (default)
-ECHO MOV #48C2h,&QYEMIT ; 48C2h = MOV.B Y,&<next_adr>
- MOV @IP+,PC
-
- FORTHWORD "NOECHO"
-;Z NOECHO -- disconnect terminal output
-NOECHO MOV #NEXT,&QYEMIT ; NEXT = 4030h = MOV @IP+,PC
- MOV @IP+,PC
+;-----------------------------------;
+ FORTHWORD "ECHO" ; -- connect EMIT to TERMINAL (default)
+;-----------------------------------;
+ECHO MOV #0B3A2h,&QYEMIT ; MOV #'BIT #TX_TERM,0(PC)',&QYEMIT
+ MOV @IP+,PC ;
+;-----------------------------------;
+;-----------------------------------;
+ FORTHWORD "NOECHO" ; -- disconnect TERMINAL from EMIT
+;-----------------------------------;
+NOECHO MOV #4D30h,&QYEMIT ; MOV #'MOV @IP+,PC',&QYEMIT
+ MOV @IP+,PC ;
+;-----------------------------------;
; -*- coding: utf-8 -*-
;
-; ---------------------------------------------------
-; TERMINAL driver for I2CFastForth target (I2C Slave)
-; ---------------------------------------------------
-; |
-; | GND------------------------------GND
-; | Vcc-------------o---o------------Vcc
-; | | |
-; | 3 3
-; | k k
-; v 3 3
+; --------------------------------------------------- ---------------------------
+; TERMINAL driver for I2CFastForth target (I2C Slave) see MSP430-FORTH/UARTI2CS.f
+; --------------------------------------------------- ---------------------------
+; | |
+; | GND------------------------------GND |
+; | Vcc-------------o---o------------Vcc |
+; | | | |
+; | 3 3 |
+; | k k |
+; v 3 3 v
; I2C_FastForth | | UARTI2C +---------------------------------------+
; hardware +--------------|---o-------------+ Software | +-----------------------------+ |
; I2C Slave | +-------o----------+ | I2C Master | | +------(option)-----+ | |
; don't forget to link 3V3 and GND on each side and to add 3k3 pullup resistors on SDA and SCL.
;
;-------------------------------------------------------------------------------
-; I2C TERMINAL: QABORT ABORT_TERM INIT_TERM COLD_TERM RXON I2C_CTRL_CH
+; I2C TERMINAL: QABORT ABORT_TERM INIT_FORTH INIT_TERM COLD_TERM RXON I2C_CTRL_CH
;-------------------------------------------------------------------------------
-; ?ABORT defines run-time part of ABORT"
+;-----------------------------------;
+INIT_FORTH ; common ABORT_TERM|WARM subroutine, to init DEFERed definitions + INIT_FORTH
+;-----------------------------------;
+ MOV @RSP+,IP ; init IP with CALLER next address
+; ;
+ MOV #PUC_ABORT_ORG,X ; FRAM INFO FRAM MAIN
+; ; --------- ---------
+ MOV @X+,&PFAACCEPT ; BODYACCEPT --> PFAACCEPT
+ MOV @X+,&PFAEMIT ; BODYEMIT --> PFAEMIT
+ MOV @X+,&PFAKEY ; BODYKEY --> PFAKEY
+ MOV @X+,&CIB_ORG ; TIB_ORG --> CIB_ORG
+; ;
+; ; FRAM INFO REG|RAM
+; ; --------- -------
+ MOV @X+,RSP ; INIT_RSTACK --> R1=RSP
+ MOV @X+,rDOCOL ; EXIT --> R4=rDOCOL (if DTC=2)
+ MOV @X+,rDODOES ; XDODOES --> R5=rDODOES
+ MOV @X+,rDOCON ; XDOCON --> R6=rDOCON
+ MOV @X+,rDOVAR ; RFROM --> R7=rDOVAR
+ MOV @X+,&CAPS ; INIT_CAPS --> RAM CAPS init CAPS ON
+ MOV @X+,&BASEADR ; INIT_BASE --> RAM BASE init decimal base
+ MOV @X+,&LEAVEPTR ; INIT_LEAVE --> RAM LEAVEPTR
+ MOV #0,&STATE ; 0 --> RAM STATE
+ CALL &SOFT_APP ; default SOFT_APP = INIT_SOFT = RET_ADR, value set by DEEP_RESET.
+ MOV #SEL_RST,PC ; goto PUC 7 to select the user's choice from TOS value: RST_RET|DEEP_RESET
+;-----------------------------------;
+
+; ?ABORT defines the run-time part of ABORT"
+;-----------------------------------;
QABORT CMP #0,2(PSP) ; -- f addr cnt if f is true abort current process then display ABORT" msg.
- JNZ ABORT_TERM ; see forthMSP430FR_TERM_xxxx.asm below
+ JNZ ABORT_TERM ;
THREEDROP ADD #4,PSP ; -- cnt
JMP DROP ;
; ----------------------------------;
-I2C_ABORT_TERM ; exit from downloading then reinit FORTH variables via INIT_FORTH
+ABORT_TERM PUSH #ABORT_INIT ; called by INTERPRET, QREVEAL, TYPE2DOES
; ----------------------------------;
-ABORT_TERM MOV #2,Y ; send $02 as Ctrl_Char ?ABORT
- CALL #I2C_CTRL_CH ;
- CALL #INIT_FORTH ; common ?ABORT|PUC subroutine to init DEFERed definitions + INIT_FORTH
- .word DUP ; -- f addr cnt cnt
+I2C_ABORT MOV.B #-1,Y ; send $FF (ABORT_TERM Ctrl_Char) to UARTtoI2C bridge (I2C Master)
+ JMP I2C_CTRL_CH ;
+ABORT_INIT CALL #INIT_FORTH ; common ?ABORT|PUC subroutine
+A_TERM_END .word DUP ; -- f addr cnt cnt
.word QFBRAN,ABORT_END; -- f addr 0 if cnt = 0 display nothing
- .word ECHO ; force ECHO
+ .word ECHO ; -- f addr cnt force ECHO
.word XSQUOTE ;
.byte 5,27,"[7m",'@' ;
.word TYPE ; cmd "reverse video" + displays "@"
; Display ABORT|WARM message ; -- f addr cnt <== WARM jumps here
; ----------------------------------;
ABORT_TYPE .word TYPE ; -- f display QABORT|WARM message
- .word XSQUOTE ;
+SDABORT_END .word XSQUOTE ; set normal video Display then goto ABORT
.byte 4,27,"[0m" ;
.word TYPE ; set normal video
ABORT_END .word ABORT ; -- f|f addr 0 no return
; ----------------------------------;
-RXON ; called by SLEEP before CPU sleeping down.
-; ----------------------------------;
-I2C_ACCEPT MOV.B #0,Y ; ACCEPT request Ctrl_Char = $00
-; ----------------------------------;
-I2C_CTRL_CH BIT #TX_TERM,&TERM_IFG ; send it to I2C_Master_RX to restart it in TX mode
- JZ I2C_CTRL_CH ; wait TX buffer empty
- MOV.B Y,&TERM_TXBUF ; send Ctrl_Char
-; ----------------------------------;
-I2C_COLD_TERM
; ----------------------------------;
-COLD_TERM ; does nothing by default
+INIT_BACKGRND ; default content of BACKGRND_APP called by BACKGRND
; ----------------------------------;
-I2C_INIT_SOFT ;
+I2C_INIT_BACKGRND ;
; ----------------------------------;
-INIT_SOFT_TERM
- MOV @RSP+,PC ; does nothing by default
+I2C_ACCEPT MOV.B #0,Y ; ACCEPT request Ctrl_Char = $00
+ JMP I2C_CTRL_CH ;
; ----------------------------------;
;-------------------------------------------------------------------------------
; INIT TERMinal then enable I/O
;-------------------------------------------------------------------------------
-; ----------------------------------;
-I2C_INIT_TERM ;
-; ----------------------------------;
-INIT_TERM ; TOS = USERSYS, don't change
+INIT_TERM ; default content of HARD_APP called by WARM
+; ----------------------------------; TOS = USERSYS, don't change
BIS #07C0h,&TERM_CTLW0 ; set I2C_Slave in RX mode to receive I2C_address
- MOV &I2CSLAVEADR,Y ; init value found in FRAM INFO
- RRA Y ; I2C Slave address without R/W bit
+ MOV &I2CSLAVEADR,Y ; I2C_Slave_address<<1 value found in FRAM INFO
+ RRA Y ; shift it right one
BIS #400h,Y ; enable I2COA0 Slave address
MOV Y,&TERM_I2COA0 ;
BIS.B #BUS_TERM,&TERM_SEL ; Configure pins TERM_I2C
BIC #1,&TERM_CTLW0 ; release UC_TERM from reset...
- BIS #WAKE_UP,&TERM_IE ; then enable interrupt for wake up on START
- BIC #LOCKLPM5,&PM5CTL0 ; activate all previous I/O settings.
- MOV @RSP+,PC ;
+ BIS #WAKE_UP,&TERM_IE ; ...enable interrupt for wake up on START
+ BIC #LOCKLPM5,&PM5CTL0 ; then activate all previous I/O settings.
+; ----------------------------------;
+INIT_STOP ; default content of STOP_APP called by SYS, does nothing
+; ----------------------------------;
+INIT_SOFT MOV @RSP+,PC ; default content of SOFT_APP called by INIT_FORTH, does nothing
; ----------------------------------;
;-------------------------------------------------------------------------------
-; I2C TERMINAL : WARM SYS COLD
+; I2C TERMINAL : SYS COLD RESET WARM
;-------------------------------------------------------------------------------
;-----------------------------------;
-; FORTHWORD "WARM" ; (n) --
+WARM ; (n) --
;-----------------------------------;
-I2C_WARM ;
-;-----------------------------------;
-WARM CALL &HARD_APP ; init HARD_APP, i.e. UART_TERMinal then unlock IO's
- mASM2FORTH ; display a message then goto QUIT (without return):
- .word ECHO ;
- .word XSQUOTE
- .byte 7,13,10,27,"[7m@" ; CR+LF + cmd "reverse video" + @
- .word TYPE
- .word LIT,I2CSLAVEADR,FETCH
- .word DOT ; display decimal I2C_address<<1
- .word LIT,'#',EMIT
- .word DOT ; display signed USERSYS
- .word XSQUOTE
- .byte 25,"FastForth ",169,"J.M.Thoorens, "
- .word TYPE
- .word LIT,FRAM_FULL
- .word HEREXEC,MINUS,UDOT ; number of...
- .word XSQUOTE
- .byte 10,"bytes free" ; bytes free
- .word BRAN,ABORT_TYPE ; no return
+ CALL &HARD_APP ; init HARD_APP, i.e. I2C_TERMinal then unlock IO's
+ mASM2FORTH ;
+ .word ECHO ;
+ .word XSQUOTE ;
+ .byte 7,13,10,27,"[7m@" ; CR+LF + cmd "reverse video" + @
+ .word TYPE ;
+ .word LIT,I2CSLAVEADR ;
+ .word FETCH,DOT ; display decimal I2C_address<<1
+ .word LIT,'#',EMIT ;
+ .word DOT ; display signed USERSYS
+ .word XSQUOTE ;
+ .byte 25,"FastForth ",169 ;
+ .byte "J.M.Thoorens, " ;
+ .word TYPE ;
+ .word LIT,FRAM_FULL ;
+ .word HERE,MINUS,UDOT ;
+ .word XSQUOTE ;
+ .byte 10,"bytes free" ; bytes free
+ .word BRAN,ABORT_TYPE ; no return
;-----------------------------------;
;-----------------------------------;
- FORTHWORD "SYS" ; n -- software RST, DEEP_RST, COLD, WARM
+ FORTHWORD "SYS" ; n -- select COLD, DEEP_COLD, WARM (as software RST,DEEP_RST,WARM)
;-----------------------------------;
+SYS CALL &STOP_APP ; default STOP_APP = INIT_STOP, set by DEEP_RESET.
CMP #0,TOS ;
- JL SYSEND ; if -n SYS ==> COLD + DEEP_RESET
- JZ NOPUC ; if [0] SYS
+ JL TOS2COLD ; if -n SYS --> COLD --> PUC --> INIT_FORTH --> DEEP_RESET --> WARM
+ JZ TOS2WARM ; if [0] SYS --> INIT_FORTH --> WARM
BIT #1,TOS ;
- JNC SYSEND ; if +n SYS (+n even)
-NOPUC PUSH #WARM ; push WARM address
- PUSH RSP ; Push address of WARM address
- JMP INIT_FORTH ; if +n SYS (+n odd) ==> INIT_FORTH --> WARM --> WARM display
-SYSEND MOV TOS,&USERSYS ; ==> COLD --> PUC --> INIT_FORTH --> WARM --> WARM display
-;===============================================================================
+ JZ TOS2COLD ; if +n SYS (+n even)--> COLD --> PUC --> INIT_FORTH --> WARM
+TOS2WARM CALL #INIT_FORTH ; if +n SYS (+n odd) --> INIT_FORTH --> WARM
+FWARM .word WARM ; no return
+TOS2COLD MOV TOS,&USERSYS ;
+;*******************************************************************************
COLD ; <--- USER_NMI vector <--- <RESET> and <RESET> + <SW1> (DEEP_RESET)
-;===============================================================================
-; as pin RST is replaced by pin NMI by RESET below, hardware RESET is redirected here via USER NMI vector
-; that allows specific actions before executing software BOR:
- CALL &COLD_APP ; to stop APPlication before reset
+;*******************************************************************************
+; as pin RST is replaced by pin NMI, RESET by pin activation is redirected here via USER NMI vector
+; that allows actions to be performed before executing software BOR.
BIT.B #SW1,&SW1_IN ; <SW1> pressed ?
- JNZ COLDEXE ; no
- MOV #-1,&USERSYS ; yes, force USERSYS negative value to do DEEP_RESET
-COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR ------------------------+
-;=============================================================================== |
+ JNZ DO_BOR ; no
+ MOV #-1,&USERSYS ; yes, set negative value to force DEEP_RESET
+DO_BOR MOV #0A504h,&PMMCTL0 ; ---------------------------> software_BOR --->+
+;******************************************************************************* |
RESET ; <-- RST vect. <-- SYS_failures PUC POR BOR <--+
-;===============================================================================
+;*******************************************************************************
; PUC 1: replace pin RESET by pin NMI, stops WDT_RESET
;-------------------------------------------------------------------------------
- BIS #3,&SFRRPCR ; pin RST becomes pin NMI with falling edge, so SYSRSTIV = 4
+ BIS #1,&SFRRPCR ; pin RST becomes pin NMI with rising edge, so SYSRSTIV = 6
BIS #10h,&SFRIE1 ; enable NMI interrupt ==> hardware RESET is redirected to COLD.
MOV #5A80h,&WDTCTL ; disable WDT RESET
;-------------------------------------------------------------------------------
MOV #0,RAM_ORG(X) ; 3
JNZ INITRAMLOOP ; 2 6 cycles loop !
;-------------------------------------------------------------------------------
-; PUC 5: GET SYSRSTIV and SYS_USER
+; PUC 5: GET SYSRSTIV and USERSYS
;-------------------------------------------------------------------------------
- MOV &USERSYS,TOS ; TOS = USERSYS
- MOV #0,&USERSYS ; clear USERSYS
- AND #-1,TOS ;
- JNZ PUC6 ; if TOS <> 0, keep USERSYS value
- MOV &SYSRSTIV,TOS ; TOS <-- SYSRSTIV <-- 0
+ MOV &SYSRSTIV,X ; X <-- SYSRSTIV <-- 0
+ MOV &USERSYS,TOS ; TOS = USERSYS (FRAM)
+ MOV #0,&USERSYS ; and clear USERSYS
+ BIT.B #-1,TOS ; high byte reserved use
+ JNZ PUC6 ; if TOS <> 0, keep this USERSYS value
+ MOV X,TOS ; else TOS = SYSRSTIV
;-------------------------------------------------------------------------------
-; PUC 6: START FORTH engine
+; PUC 6: START FORTH engine: WARM (BOOT)
;-------------------------------------------------------------------------------
PUC6 CALL #INIT_FORTH ; common part of QABORT|PUC
-PUCNEXT .WORD WARM ; no return. May be replaced by XBOOT.
+PUCNEXT .word WARM ; no return. May be replaced by XBOOT by BOOT ;-)
;-----------------------------------;
;-------------------------------------------------------------------------------
FORTHWORD "ACCEPT" ;
; ----------------------------------;
;https://forth-standard.org/standard/core/ACCEPT
-;C ACCEPT addr addr len -- addr len' get line at addr to interpret len' chars
+;C ACCEPT addr addr len -- addr len' get a line from TERMINAL
ACCEPT MOV @PC+,PC ;3 Code Field Address (CFA) of ACCEPT
PFAACCEPT .word BODYACCEPT ; Parameter Field Address (PFA) of ACCEPT
-BODYACCEPT ; BODY of ACCEPT = default execution of ACCEPT
; ----------------------------------;
; ACCEPT part I prepare TERMINAL_INT;
; ----------------------------------;
- MOV TOS,W ;1 -- org len W=len
+BODYACCEPT MOV TOS,W ;1 -- org len W=len
MOV @PSP,TOS ;2 -- org ptr )
ADD TOS,W ;1 -- org ptr W=buf_end )
MOV #0Ah,T ;2 T = 'LF' to speed up char loop in part II > prepare stack and registers for TERMINAL_INT use
MOV #20h,S ;2 S = 'BL' to speed up char loop in part II )
PUSHM #4,IP ;6 PUSH IP,S,T,W R-- IP, 'BL', 'LF', buf_end )
- JMP SLEEP ;2
-; ----------------------------------;
+
+; here, FAST FORTH sleeps, waiting any interrupt. With LPM4, supply current is below 1uA.
+; IP,S,T,W,X,Y registers (R13 to R8) are free...
+; ...and also TOS, PSP and RSP stacks within their rules of use.
+;###################################################################################
+BACKGRND CALL &BACKGRND_APP ; default BACKGRND_APP = INIT_BACKGRND = I2C_ACCEPT, value set by DEEP_RESET.
+ BIS &LPM_MODE,SR ;2 enter in LPM4 mode with GIE=1
+ JMP BACKGRND ;2 return for all interrupts.
+;###################################################################################
; As TI says nothing about the reset of the UCSTTIFG flag by the I2C_Slave,
; it is assumed that it clears it as soon as the first byte has been exchanged.
; **********************************;
-TERMINAL_INT ; down to LPM4 <--- START interrupt vector, bus is stalled, waiting ACK first char by I2C_Slave RX
+TERMINAL_INT ; <--- 80us <--- START interrupt vector, bus is stalled, I2C_Master waits ACK on address
; **********************************;
-; (ACCEPT) part II under interrupt ; Org Ptr --
+; ACCEPT part II wake on TERM_INT ; Org Ptr --
; ----------------------------------;
ADD #4,RSP ;1 remove SR and PC from stack, SR flags are lost (unused by FORTH interpreter)
- BIC #WAKE_UP,&TERM_IFG ; clear UCSTTIFG before return to SLEEP (instead of RXBUF access to clear it)
+ BIC #WAKE_UP,&TERM_IFG ; clear UCSTTIFG before return to BACKGRND if any (here, UCSTTIFG is not yet cleared !)
BIT #10h,&TERM_CTLW0 ;4 test UCTR
- JNZ SLEEP ; if I2C_Master RX, loop back to SLEEP
- POPM #4,IP ;6 POPM IP=ret_IP,W=src_end,T=0Ah,S=20h
+ JNZ BACKGRND ; if Master RX loop back to BACKGRND
+ACCEPT_YES POPM #4,IP ;6 POPM S=20h, T=0Ah, W=src_end, IP=ret_IP
QNEWCHAR BIT #RX_TERM,&TERM_IFG ;3 test RX BUF IFG
JZ QNEWCHAR ;2 wait RX BUF full
; ----------------------------------;
AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read char into Y, RX_IFG is cleared, bus unstalled by I2C_Slave
; ----------------------------------;
- CMP.B T,Y ;1 char = LF ?
- JZ LF_NEXT ;2 jump if char = LF
CMP.B S,Y ;1 printable char ?
JC ASTORETEST ;2 jump if char U>= BL
+ CMP.B T,Y ;1 char = LF ?
+ JZ LF_NEXT ;2 jump if char = LF
; ----------------------------------;
CMP.B #8,Y ; char = BS ?
- JNZ QNEWCHAR ; case of all other control chars: skip it
+ JNZ QNEWCHAR ; case of all other control chars: skip them
; ----------------------------------;
; case of backspace ; made only by an human
; ----------------------------------;
CMP @PSP,TOS ; Ptr = Org ?
- JZ QNEWCHAR ; yes: do nothing else
+ JZ QNEWCHAR ; yes: does nothing
SUB #1,TOS ; no : dec Ptr
JMP QNEWCHAR ;
; ----------------------------------;
ADD #1,TOS ; 1 increment dst_Ptr
JMP QNEWCHAR ;
; ----------------------------------;
-LF_NEXT SUB @PSP+,TOS ; -- len'
+LF_NEXT BIT #10h,&TERM_CTLW0 ;4 test UCTR, instead of BUS idle because a ReSTART perhaps used by Master
+ JZ LF_NEXT ; wait until Master switched from TX to RX
+; ----------------------------------;
+ SUB @PSP+,TOS ; -- len'
ACCEPT_EOL MOV S,Y ; output a BL on TERMINAL (for the case of error occuring)
- JMP YEMIT ; before line interpreting
+ JMP QYEMIT ; before going to INTERPRET
; **********************************;
; ----------------------------------;
; KEY -- c wait character from input device ; primary DEFERred word
KEY MOV @PC+,PC ; Code Field Address (CFA) of KEY
PFAKEY .word BODYKEY ; Param Field Address (PFA) of KEY, with its default value
-BODYKEY MOV.B #1,Y ; KEY request Ctrl_Char = $01
- CALL #I2C_CTRL_CH ; send it to I2C_Master to restart its UART in RX mode
- SUB #2,PSP ; push old TOS..
+BODYKEY PUSH #KEYNEXT ;
+ MOV.B #1,Y ; KEY request Ctrl_Char = $01
+; ----------------------------------;
+I2C_CTRL_CH BIT #TX_TERM,&TERM_IFG ; send it to I2C_Master_RX to restart it in TX mode
+ JZ I2C_CTRL_CH ; wait TX buffer empty
+ MOV.B Y,&TERM_TXBUF ; send Ctrl_Char
+ MOV @RSP+,PC ;
+; ----------------------------------;
+KEYNEXT SUB #2,PSP ;1 push old TOS..
MOV TOS,0(PSP) ; ..onto stack
BKEYLOOP BIT #RX_TERM,&TERM_IFG ; received char ?
JZ BKEYLOOP ; wait char received
MOV &TERM_RXBUF,TOS ; -- char
- CALL #RXON ; send Ctrl_Char $00 to I2C_Master to restart its UART in TX mode
+ CALL #I2C_ACCEPT ; send Ctrl_Char $00 to I2C_Master to restart its UART in TX mode
BKEYEND MOV @IP+,PC ; -- char
; ----------------------------------;
; EMIT c -- output character to an output device ; primary DEFERred word
EMIT MOV @PC+,PC ;3 Code Field Address (CFA) of EMIT
PFAEMIT .word BODYEMIT ; Parameter Field Address (PFA) of EMIT, with its default value
-BODYEMIT
- MOV TOS,Y ;1 sends character to the default output TERMINAL
+BODYEMIT MOV TOS,Y ;1 sends character to the default output TERMINAL
MOV @PSP+,TOS ;2
-YEMIT BIT #TX_TERM,&TERM_IFG ;3
- JZ YEMIT ;2 wait TX buffer empty
-QYEMIT MOV.B Y,&TERM_TXBUF ;3 may be replaced by MOV @IP+,PC with NOECHO
-YEMITEND MOV @IP+,PC ;4 11 words
+QYEMIT BIT #TX_TERM,&TERM_IFG ;3 NOECHO stores here : MOV @IP+,PC, ECHO store here the first word of: BIT #TX_TERM,&TERM_IFG
+ JZ QYEMIT ;2 wait TX buffer empty
+ MOV.B Y,&TERM_TXBUF ;3
+ MOV @IP+,PC ;4 11 words
; ----------------------------------;
-; ----------------------------------;
- FORTHWORD "ECHO" ; connect EMIT to TERMINAL (default)
-; ----------------------------------;
-ECHO MOV #48C2h,&QYEMIT ; 48C2h = MOV.B Y,&<next_adr>
- MOV #5,Y ; ECHO request Ctrl_Char = $05
+;-----------------------------------;
+ FORTHWORD "ECHO" ; -- connect EMIT to TERMINAL (default)
+;-----------------------------------;
+ECHO MOV #0B3A2h,&QYEMIT ; MOV #'BIT #TX_TERM,0(PC)',&QYEMIT
+ MOV.B #5,Y ; ECHO request Ctrl_Char = $05
ECHOEND CALL #I2C_CTRL_CH ;
MOV @IP+,PC ;
; ----------------------------------;
-; ----------------------------------;
- FORTHWORD "NOECHO" ; disconnect EMIT to TERMINAL
-; ----------------------------------;
-NOECHO MOV #4D30h,&QYEMIT ; NEXT = 4D30h = MOV @IP+,PC
- MOV #4,Y ; NOECHO request Ctrl_Char = $04
+;-----------------------------------;
+ FORTHWORD "NOECHO" ; -- disconnect TERMINAL from EMIT
+;-----------------------------------;
+NOECHO MOV #4D30h,&QYEMIT ; MOV #'MOV @IP+,PC',&QYEMIT
+ MOV.B #4,Y ; NOECHO request Ctrl_Char = $04
JMP ECHOEND ;
; ----------------------------------;
-
; LP_MSP430FR2476 P1.4 P1.5 P6.1
;
;-------------------------------------------------------------------------------
-; UART TERMINAL: QABORT INIT_TERM COLD_TERM
+; UART TERMINAL: QABORT ABORT_TERM INIT_BACKGRND RXON INIT_FORTH INIT_TERM INIT_COLD INIT_SOFT
;-------------------------------------------------------------------------------
+;
+;-----------------------------------;
+; modifying TOs is forbidden here ! ;
+;-----------------------------------;
+INIT_FORTH ; common ABORT_TERM|WARM subroutine, to init DEFERed definitions + INIT_FORTH
+;-----------------------------------;
+ MOV @RSP+,IP ; init IP with CALLER next address
+; ;
+ MOV #PUC_ABORT_ORG,X ; FRAM INFO FRAM MAIN
+; ; --------- ---------
+ MOV @X+,&PFAACCEPT ; BODYACCEPT --> PFAACCEPT
+ MOV @X+,&PFAEMIT ; BODYEMIT --> PFAEMIT
+ MOV @X+,&PFAKEY ; BODYKEY --> PFAKEY
+ MOV @X+,&CIB_ORG ; TIB_ORG --> CIB_ORG TIB = Terminal Input Buffer, CIB = Current Input Buffer
+; ;
+; ; FRAM INFO REG|RAM
+; ; --------- -------
+ MOV @X+,RSP ; INIT_RSTACK --> R1=RSP PSP is initialised with ABORT
+ MOV @X+,rDOCOL ; EXIT --> R4=rDOCOL (if DTC=2)
+ MOV @X+,rDODOES ; XDODOES --> R5=rDODOES
+ MOV @X+,rDOCON ; XDOCON --> R6=rDOCON
+ MOV @X+,rDOVAR ; RFROM --> R7=rDOVAR
+ MOV @X+,&CAPS ; INIT_CAPS --> RAM CAPS init CAPS ON
+ MOV @X+,&BASEADR ; INIT_BASE --> RAM BASE init decimal base
+ MOV @X+,&LEAVEPTR ; INIT_LEAVE --> RAM LEAVEPTR
+ MOV #0,&STATE ; 0 --> RAM STATE
+ CALL &SOFT_APP ; default SOFT_APP = INIT_SOFT = RET_ADR, value set by DEEP_RESET.
+ MOV #SEL_RST,PC ; goto PUC 7 to select the user's choice from TOS value: RST_RET|DEEP_RESET
+;-----------------------------------;
-; this define run-time part of ABORT" if f is true display msg. then abort current process
-QABORT CMP #0,2(PSP) ; -- f addr cnt test flag f
- JNZ ABORT_TERM ; see forthMSP430FR_TERM_xxxx.asm below
+; ?ABORT defines the run-time part of ABORT"
+;-----------------------------------;
+QABORT CMP #0,2(PSP) ; -- f addr cnt if f is true abort current process then display ABORT" msg.
+ JNZ ABORT_TERM ;
THREEDROP ADD #4,PSP ; -- cnt
JMP DROP ;
+ABORT_TERM PUSH #ABORT_INIT ; ABORT_TERM is called by INTERPRET, QREVEAL, TYPE2DOES
; ----------------------------------;
-UART_ABORT_TERM ; exit from downloading, execute INIT_FORTH then display message if any
+UART_ABORT CALL #UART_RXON ;
; ----------------------------------;
-ABORT_TERM CALL #RXON ; resume downloading source file if any
A_UART_LOOP BIC #RX_TERM,&TERM_IFG ; clear RX_TERM
MOV &FREQ_KHZ,Y ; 1000, 2000, 4000, 8000, 16000, 24000
-A_USB_LOOPJ MOV #65,X ; 2~ <----+ linux with minicom seems very very slow...
-A_USB_LOOPI SUB #1,X ; 1~ <--+ | to refill its USB buffer
- JNZ A_USB_LOOPI ; 2~ 3~ loop ---+ |
+A_USB_LOOPJ MOV #65,X ; 2~ <-------+ linux with minicom seems very very slow...
+A_USB_LOOPI SUB #1,X ; 1~ <---+ | ...to refill its USB buffer
+ JNZ A_USB_LOOPI ; 2~ 3~ loop ---+ | ==> ((65*3)+5)*1000 = 200ms delay
SUB #1,Y ; 1~ |
- JNZ A_USB_LOOPJ ; 2~ 200~ loop -----+ ((65*3)+5)*1000 = 200ms delay
+ JNZ A_USB_LOOPJ ; 2~ 200~ loop -----+
BIT #RX_TERM,&TERM_IFG ; 4 new char in TERMRXBUF after 200ms delay ?
JNZ A_UART_LOOP ; 2 yes, the input stream is still active: loop back
- CALL #INIT_FORTH ; common ?ABORT|PUC subroutine
- ; TOS = cnt (byte), always positive. No RST_RET if cnt = 0.
+ MOV @RSP+,PC
+; ----------------------------------;
+ABORT_INIT CALL #INIT_FORTH ; common ?ABORT|PUC subroutine
.word DUP ; -- f addr cnt cnt
- .word QFBRAN,ABORT_END; -- f addr 0 don't force ECHO if ABORT" is an empty string
+ .word QFBRAN,ABORT_END; -- f addr 0 don't force ECHO, no display if ABORT" is an empty string
.word ECHO ; -- f addr cnt force ECHO
.word XSQUOTE ;
.byte 4,27,"[7m" ;
.word TYPE ; ESC [7m = set reverse video
; ----------------------------------;
-; Display QABORT|WARM message ; <== WARM jumps here
+; Display QABORT|WARM message ; -- addr cnt <== WARM jumps here
; ----------------------------------;
ABORT_TYPE .word TYPE ; -- f type QABORT|WARM message
- .word XSQUOTE ;
+SDABORT_END .word XSQUOTE ; set normal video Display then goto ABORT
.byte 4,27,"[0m" ;
.word TYPE ; ESC [0m = set normal video
ABORT_END .word ABORT ; -- f no return
; ----------------------------------;
;-------------------------------------------------------------------------------
-; INIT TERMinal then enable I/O
+; INIT TERMinal then enable I/O ;
;-------------------------------------------------------------------------------
-
+INIT_HARD ;
; ----------------------------------;
-UART_INIT_TERM ;
+INIT_TERM ; default content of HARD_APP called by WARM
; ----------------------------------;
-INIT_TERM
- CALL #WAIT_UART_IDLE ; wait while TERM_UART is busy
- MOV #0081h,&TERM_CTLW0 ; 8 bits, UC SWRST + UCLK = SMCLK, max 6MBds
-; MOV #1081h,&TERM_CTLW0 ; 7 bits, UC SWRST + UCLK = SMCLK, max 4MBds
+ MOV #0081h,&TERM_CTLW0 ; 8 bits, UC SWRST + UCLK = SMCLK, max 6MBds @24MHz
MOV &TERMBRW_RST,&TERM_BRW ; init value in FRAM INFO
MOV &TERMMCTLW_RST,&TERM_MCTLW ; init value in FRAM INFO
BIS.B #BUS_TERM,&TERM_SEL ; Configure pins TERM_UART|TERM_I2C
; ----------------------------------;
; ----------------------------------;
-UART_COLD_TERM ; default STOP_APP: wait TERMINAL idle
+INIT_STOP ; default STOP_APP, called by SYS: wait end of TX to TERMINAL
; ----------------------------------;
-WAIT_UART_IDLE
-COLD_TERM BIT #1,&TERM_STATW ;3 uart busy ?
- JNZ COLD_TERM ;2 loop back while TERM_UART is busy
+TX_IDLE BIT #1,&TERM_STATW ;3 uart busy ?
+ JNZ TX_IDLE ;2 loop back while TERM_UART is busy
; ----------------------------------;
-UART_INIT_SOFT ;
-; ----------------------------------;
-INIT_SOFT_TERM
- MOV @RSP+,PC ; does nothing
+INIT_SOFT MOV @RSP+,PC ;
; ----------------------------------;
;-------------------------------------------------------------------------------
-; UART TERMINAL : WARM SYS COLD RESET
+; UART TERMINAL : SYS COLD RESET WARM
;-------------------------------------------------------------------------------
;-----------------------------------;
-; FORTHWORD "WARM" ; (n) --
-;-----------------------------------; thanks to INIT_FORTH, WARM implements the choice
-UART_WARM ; made by the user with SYS|hardwareRST|DEEP_reset
-;-----------------------------------; regarding the state of the software.
-WARM CALL &HARD_APP ;
- mASM2FORTH ;
- .word ECHO ;
- .word XSQUOTE
- .byte 7,13,10,27,"[7m#" ; CR + cmd "reverse video" + #
- .word TYPE
- .word DOT ; display TOS = USERSYS value
- .word XSQUOTE
- .byte 25,"FastForth ",169,"J.M.Thoorens, "
- .word TYPE
- .word LIT,FRAM_FULL
- .word HEREXEC,MINUS,UDOT
- .word XSQUOTE
- .byte 10,"bytes free"
- .word BRAN,ABORT_TYPE ; without return
+UART_WARM ; (n) --
+;-----------------------------------;
+WARM CALL &HARD_APP ; default HARD_APP = INIT_TERM, value set by DEEP_RESET.
+ mASM2FORTH ;
+ .word ECHO ;
+ .word XSQUOTE ;
+ .byte 7,13,10,27,"[7m#" ; CR + cmd "reverse video" + #
+ .word TYPE ;
+ .word DOT ; display TOS = USERSYS value
+ .word XSQUOTE ;
+ .byte 25,"FastForth ",169 ;
+ .byte "J.M.Thoorens, " ;
+ .word TYPE ;
+ .word LIT,FRAM_FULL ;
+ .word HERE,MINUS,UDOT ;
+ .word XSQUOTE ;
+ .byte 10,"bytes free" ;
+ .word BRAN,ABORT_TYPE ; no return
;-----------------------------------;
;-----------------------------------;
- FORTHWORD "SYS" ; n -- software RST, DEEP_RST, COLD, WARM
+ FORTHWORD "SYS" ; n -- select COLD, DEEP_COLD, WARM (as software RST,DEEP_RST,WARM)
;-----------------------------------;
+SYS CALL &STOP_APP ; default STOP_APP = INIT_STOP, set by DEEP_RESET.
CMP #0,TOS ;
- JL SYSEND ; if -n SYS ==> COLD + DEEP_RESET
- JZ NOPUC ; if [0] SYS ==> INIT_FORTH --> WARM --> WARM display
+ JL TOS2COLD ; if -n SYS --> COLD --> PUC --> INIT_FORTH --> DEEP_RESET --> WARM
+ JZ TOS2WARM ; if [0] SYS --> INIT_FORTH --> WARM
BIT #1,TOS ;
- JNC SYSEND ; if +n SYS (+n even)
-NOPUC PUSH #WARM ;
- PUSH RSP ; Push address of WARM address
- JMP INIT_FORTH ; if +n SYS (+n odd) ==> INIT_FORTH --> WARM --> WARM display
-SYSEND MOV TOS,&USERSYS ; ==> COLD --> PUC --> INIT_FORTH --> WARM --> WARM display
-;===============================================================================
-COLD ; <--- USER_NMI vector <--- <RESET> and <RESET> + <SW1> (DEEP_RESET)
-;===============================================================================
-; as pin RST is replaced by pin NMI, RESET by pin activation is redirected here via USER NMI vector
+ JZ TOS2COLD ; if +n SYS (+n even)--> COLD --> PUC --> INIT_FORTH --> WARM
+TOS2WARM CALL #INIT_FORTH ; if +n SYS (+n odd) --> INIT_FORTH --> WARM
+FWARM .word WARM ; no return
+TOS2COLD MOV TOS,&USERSYS ;
+;*******************************************************************************
+COLD ; <--- USER_NMI vector <------------------------ <RESET> | <RESET+SW1>
+;*******************************************************************************
+; as pin RST is replaced by pin NMI, hardware RESET is redirected here via USER NMI vector
; that allows actions to be performed before executing software BOR.
- CALL &COLD_APP ; to stop APPlication before reset
BIT.B #SW1,&SW1_IN ; <SW1> pressed ?
- JNZ COLDEXE ; no
+ JNZ DO_BOR ; no
MOV #-1,&USERSYS ; yes, set negative value to force DEEP_RESET
-COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR ------------------------+
-;=============================================================================== |
-RESET ; <-- RST vect. <-- SYS_failures PUC POR BOR <--+
-;===============================================================================
+DO_BOR MOV #0A504h,&PMMCTL0 ; ---------------------------> software_BOR --->+
+;******************************************************************************* |
+;******************************************************************************* v
+RESET ; <--- RST vector <----------- PUC <--- POR <---+<--- BOR <--- SYS_failures
+;*******************************************************************************
+;*******************************************************************************
; PUC 1: replace pin RESET by pin NMI, stops WDT_RESET
;-------------------------------------------------------------------------------
- BIS #3,&SFRRPCR ; pin NMI with falling edge replaces pin RST, so SYSRSTIV = 4
- BIS #10h,&SFRIE1 ; enable NMI pin interrupt ==> hardware RESET is redirected to COLD.
+ BIS #1,&SFRRPCR ; pin RST becomes pin NMI with rising edge, SYSRSTIV = 6, hardware RESET is redirected to COLD
+ BIS #10h,&SFRIE1 ; enable NMI pin interrupt.
MOV #5A80h,&WDTCTL ; disable WDT RESET
;-------------------------------------------------------------------------------
; PUC 2: INIT STACK
;-------------------------------------------------------------------------------
; PUC 4: init RAM to 0
;-------------------------------------------------------------------------------
- MOV #RAM_LEN,X ; 2 RAM_LEN must be even and > 1, obviously.
+ MOV #RAM_LEN,X ; 2 RAM_LEN must be even and > 0, obviously.
INITRAMLOOP SUB #2,X ; 1
MOV #0,RAM_ORG(X) ; 3
JNZ INITRAMLOOP ; 2 6 cycles loop !
;-------------------------------------------------------------------------------
-; PUC 5: GET SYSRSTIV and SYS_USER
+; PUC 5: GET SYSRSTIV and USERSYS
;-------------------------------------------------------------------------------
MOV &SYSRSTIV,X ; X <-- SYSRSTIV <-- 0
- MOV &USERSYS,TOS ; TOS = USERSYS
- MOV #0,&USERSYS ; clear USERSYS
- AND #-1,TOS ;
+ MOV &USERSYS,TOS ; TOS = FRAM USERSYS
+ MOV #0,&USERSYS ; clear FRAM USERSYS
+ BIT #-1,TOS ;
JNZ PUC6 ; if TOS <> 0, keep USERSYS value
- MOV X,TOS ; TOS <-- SYSRSTIV
+ MOV X,TOS ; else TOS <-- SYSRSTIV
;-------------------------------------------------------------------------------
-; PUC 6: START FORTH engine
+; PUC 6: START FORTH engine: WARM (BOOT)
;-------------------------------------------------------------------------------
PUC6 CALL #INIT_FORTH ; common part of QABORT|PUC
-PUCNEXT .WORD WARM ; no return. May be redirected by BOOT.
+PUCNEXT .word WARM ; no return. May be redirected by BOOT.
;-----------------------------------;
;-------------------------------------------------------------------------------
ADD TOS,Y ;1 -- org ptr Y = buf_end
MOV #0Dh,X ;2 X = 'CR' to speed up char loop in part II
MOV #20h,W ;2 W = 'BL' to speed up char loop in part II
- MOV #YEMIT_NEXT,T ;2 T = return for QYEMIT
- MOV #CR_NEXT,S ;2 S = CR_NEXT
- PUSHM #6,IP ;8 PUSHM IP,S,T,W,X,Y r-- ACCEPT_ret CR_NEXT YEMIT_NEXT BL CR buf_end
- JMP SLEEP ;2 send RXON then shut down to LPM0 sleeping mode
-; ----------------------------------;
+ MOV #YEMIT_NEXT,T ;2 T = YEMIT_ret
+ MOV #CR_NEXT,S ;2 S = XOFF_ret
+ PUSHM #6,IP ;8 PUSHM IP,S,T,W,X,Y r-- ACCEPT_ret XOFF_ret YEMIT_ret BL CR buf_end
+
+;###################################################################################
+BACKGRND CALL &BACKGRND_APP ; default BACKGRND_APP = UART_INIT_BACKGRND = UART_RXON, value set by DEEP_RESET.
+ BIS &LPM_MODE,SR ;2 enter in LPM0 mode with GIE=1
+; here, FAST FORTH sleeps, awaiting any interrupt.
+; IP,S,T,W,X,Y registers (R13 to R8) are free...
+; ...and also TOS, PSP and RSP stacks within their rules of use.
+ JMP BACKGRND ;2 return for all interrupts.
+;###################################################################################
-; **********************************;
-TERMINAL_INT ; <--- TERM RX buffer full interrupt vector, delayed by the LPM0 wake up time
-; **********************************; if wake up time increases, max bauds rate decreases...
-; ACCEPT part II under interrupt ; Org Ptr -- len' all SR flags are cleared
-; ----------------------------------;
- ADD #4,RSP ;1 remove SR and PC from stack
- POPM #4,IP ;6 POPM W=buffer_bound, T=0Dh, S=20h, IP=YEMIT_NEXT r-- ACCEPT_ret CR_NEXT
-; ----------------------------------;
-AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read character into Y, RX_TERM is cleared
-; ----------------------------------;
- CMP.B T,Y ;1 CR ?
- JNZ AKEYRDNNEXT ;2 no
-; ----------------------------------;
-RXOFF ; Software|hardware flow control to stop RX UART r-- ACCEPT_ret CR_NEXT
; ----------------------------------;
+UART_RXOFF ; Software|hardware flow control to stop RX UART
+; ----------------------------------; RXOFF is sent while LF char is received...
.IFDEF TERMINAL3WIRES ; first software flow control
RXOFF_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char
JZ RXOFF_LOOP ;2
BIS.B #RTS,&HANDSHAKOUT ;3 set RTS high
.ENDIF ;
MOV @RSP+,PC ;4 to CR_NEXT
+; ----------------------------------; RXOFF is sent while LF char is received...
+
+; **********************************;
+TERMINAL_INT ; <--- TERM RX interrupt vector, delayed by the LPM0 wake up time
+; **********************************; if wake up time increases, max baudrate decreases...
+; ACCEPT part II under interrupt ; Org Ptr -- len' all SR flags are cleared
; ----------------------------------;
-AKEYRDNNEXT CMP.B S,Y ;1 printable char ?
+ ADD #4,RSP ;1 remove SR and PC from stack
+ POPM #4,IP ;6 POPM W=BUF_end, T='CR', S='BL', IP=YEMIT_ret r-- ACCEPT_ret XOFF_ret
+; ----------------------------------;
+AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read character into Y, RX_TERM is cleared
+; ----------------------------------;
+ CMP.B S,Y ;1 printable char ?
JC ASTORETEST ;2 yes
; ----------------------------------;
+ CMP.B T,Y ;1 CR ?
+ JZ UART_RXOFF ;2 yes
+; ----------------------------------;
CMP.B #8,Y ;1 char = BS ?
- JNE WAITaKEY ;2 case of other control chars
+ JNZ WAITaKEY ;2 case of other control chars
; ----------------------------------;
; start of backspace ; made only by an human
; ----------------------------------;
CMP @PSP,TOS ; Ptr = Org ?
JZ WAITaKEY ; yes: do nothing
SUB #1,TOS ; no : dec Ptr
- JMP YEMIT ; don't store BS, return to YEMIT_NEXT
+ JMP QYEMIT ; don't store BS, return to YEMIT_NEXT
+; ----------------------------------;
+; end of backspace ;
; ----------------------------------;
ASTORETEST CMP W,TOS ; 1 Bound is reached ?
- JC YEMIT ; 2 yes: don't store char @ Ptr, don't increment TOS
+ JC QYEMIT ; 2 yes: don't store char @ Ptr, don't increment TOS
MOV.B Y,0(TOS) ; 3 no: store char @ Ptr
ADD #1,TOS ; 1 increment Ptr
; ----------------------------------;
-YEMIT BIT #TX_TERM,&TERM_IFG ; 3 wait the sending end of previous char, useless at high baudrates,
- JZ YEMIT ; 2 but there's no point in wanting to save time here:
- .IFDEF TERMINAL5WIRES ;
-YEMIT1 BIT.B #CTS,&HANDSHAKIN ; 3 CTS is pulled low if unwired.
- JNZ YEMIT1 ; 2
+QYEMIT BIT #TX_TERM,&TERM_IFG ; 3 NOECHO stores here : MOV @IP+,PC, ECHO store here the first word of: BIT #TX_TERM,&TERM_IFG
+ JZ QYEMIT ; 2 but there's no point in wanting to save time here:
+ .IFDEF TERMINAL5WIRES ; then decrease BAUDRATE !
+QYEMIT1 BIT.B #CTS,&HANDSHAKIN ; 3 CTS is pulled low if unwired.
+ JNZ QYEMIT1 ; 2
.ENDIF ;
-QYEMIT MOV.B Y,&TERM_TXBUF ; 3 may be replaced by MOV @IP+,PC with NOECHO
+ MOV.B Y,&TERM_TXBUF ; 3
MOV @IP+,PC ; 4
; ----------------------------------;
-YEMIT_NEXT .word $+2 ; 0 YEMII NEXT address
+YEMIT_NEXT .word $+2 ; 0 YEMIT NEXT address
SUB #2,IP ; 1 restore YEMIT_NEXT
; ----------------------------------;
WAITaKEY BIT #RX_TERM,&TERM_IFG ; 3 new char in TERMRXBUF ?
- JNZ AKEYREAD ; 2 yes, loop = 34~/31~ by char (with/without echo) ==> 294/322 kBds/MHz
+ JNZ AKEYREAD ; 2 yes, loop = 34~/26~ by char (with/without echo) ==> 294/384 kBds/MHz
JMP WAITaKEY ; 2 no
; ----------------------------------;
-; return of RXOFF ; --- Org Ptr R-- ACCEPT_NEXT
+; return of RXOFF ; --- Org Ptr
; ----------------------------------;
-CR_NEXT SUB @PSP+,TOS ; -- len'
- MOV @RSP+,IP ; R--
-WAITLF BIT #RX_TERM,&TERM_IFG ; char 'LF' is received ?
- JZ WAITLF ; no
+CR_NEXT BIT #RX_TERM,&TERM_IFG ; char 'LF' is received ?
+ JZ CR_NEXT ; no
MOV.B &TERM_RXBUF,Y ; yes, clear RX_IFG flag after LF received
; ----------------------------------;
-ACCEPT_EOL MOV S,Y ; output a BL on TERMINAL (for the case of error occuring)
- JMP YEMIT ; before return to QUIT to interpret line
+ SUB @PSP+,TOS ; -- len' R-- ACCEPT_NEXT
+ MOV @RSP+,IP ; R--
+ACCEPT_EOL MOV.B S,Y ; output a BL on TERMINAL (for the case of error occuring)
+ JMP QYEMIT ; before return to QUIT to interpret line
; **********************************; UF9 to UF11 will be resetted.
;-----------------------------------;
PFAKEY .word BODYKEY ; Parameter Field Address (PFA) of KEY, with default value
BODYKEY PUSH #KEYNEXT ;
; ----------------------------------;
-RXON ; default BACKGND_APP
+INIT_BACKGRND ; default content of BACKGRND_APP called by BACKGRND
+; ----------------------------------;
+UART_RXON ;
; ----------------------------------;
.IFDEF TERMINAL3WIRES ; first software flow control
-RXON_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char, useless at high baudrates
- JZ RXON_LOOP ;2
+ BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char, useless at high baudrates
+ JZ UART_RXON ;2
MOV #17,&TERM_TXBUF ;4 move char XON into TX_buf
.ENDIF ;
.IFDEF TERMINAL4WIRES ; and hardware flow control after
BIC.B #RTS,&HANDSHAKOUT ;3 set RTS low
.ENDIF ;
- MOV @RSP+,PC ;4 to BACKGND (End of file download or quiet input) or AKEYREAD...
-; ----------------------------------; ... (get next line of file downloading), or user defined
+ MOV @RSP+,PC ;4
+; ----------------------------------;
KEYNEXT SUB #2,PSP ;1 push old TOS..
MOV TOS,0(PSP) ;3 ..onto stack
KEYLOOP BIT #RX_TERM,&TERM_IFG ; loop if bit0 = 0 in interupt flag register
JZ KEYLOOP ;
- CALL #RXOFF ;
+ CALL #UART_RXOFF ;
MOV &TERM_RXBUF,TOS ;
MOV @IP+,PC
+;-----------------------------------;
;-----------------------------------;
- FORTHWORD "EMIT"
+ FORTHWORD "EMIT" ; save X before use if used
;-----------------------------------;
; https://forth-standard.org/standard/core/EMIT
; EMIT c -- output character to the selected output device ; primary DEFERred word
-EMIT MOV @PC+,PC ;4 Code Field Address (CFA) of EMIT
+EMIT MOV @PC+,PC ;3 Code Field Address (CFA) of EMIT
PFAEMIT .word BODYEMIT ; Parameter Field Address (PFA) of EMIT, with its default value
BODYEMIT MOV TOS,Y ;1 output character to the default output: TERMINAL
MOV @PSP+,TOS ;2
- JMP YEMIT ;2 + 12~
+ JMP QYEMIT ;2 + 12~
+;-----------------------------------;
;-----------------------------------;
- FORTHWORD "ECHO"
+ FORTHWORD "ECHO" ; -- connect ACCEPT and EMIT to TERMINAL input (default)
+;-----------------------------------;
+ECHO MOV #0B3A2h,&QYEMIT ; MOV #'BIT #TX_TERM,0(PC)',&QYEMIT
+ MOV @IP+,PC ;
;-----------------------------------;
-;Z ECHO -- connect terminal output (default)
-ECHO MOV #48C2h,&QYEMIT ; 48C2h = MOV.B Y,&<next_adr>
- MOV @IP+,PC
;-----------------------------------;
- FORTHWORD "NOECHO"
+ FORTHWORD "NOECHO" ; -- disconnect ACCEPT and EMIT from TERMINAL input
+;-----------------------------------;
+NOECHO MOV #4D30h,&QYEMIT ; MOV #'MOV @IP+,PC',&QYEMIT
+ MOV @IP+,PC ;
;-----------------------------------;
-;Z NOECHO -- disconnect terminal output
-NOECHO MOV #4D30h,&QYEMIT ; NEXT = 4D30h = MOV @IP+,PC
- MOV @IP+,PC
-
-! -*- coding: utf-8 -*-
-! ChipStick_FR2433.pat
-!
-\.f=\.4th for ChipStick_FR2433! to change file type
-!
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! tell GEMA to replace default Comment separator '!' by ';'
+; ChipStick_FR2433.pat
+;
+\.f=\.4th for ChipStick_FR2433; to change file type
+; ========================
+; remove comments
+; ========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! MSP430FR2433 Config
-! ======================================================================
+; ======================================================================
+; MSP430FR2433 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR2433.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR2xxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-! ---------------------------------------------------
-! CHIPSTICK_FR2433 <--> OUTPUT WORLD
-! ---------------------------------------------------
-! P3.1 - LED1
-!
-! P2.1 - PL2.2 - SW1
-! P2.0 - PL2.3 - SW2
-!
-! +--4k7-< DeepRST <-- GND
-! |
-! P1.4 - UCA0 TXD PL1.4 - <-+-> RX UARTtoUSB bridge
-! P1.5 - UCA0 RXD PL1.3 - <---- TX UARTtoUSB bridge
-! P3.2 - RTS PL1.2 - ----> CTS UARTtoUSB bridge (if TERMINALCTSRTS option)
-! -
-! P3.0 - PL1.7 - ----> /CS SPI_RAM
-! P1.1 - UCB0 CLK PL1.9 - ----> CLK SPI_RAM
-! P1.2 - UCB0 SIMO PL1.10 - ----> SI SPI_RAM
-! P1.3 - UCB0 SOMI PL2.10 - <---- S0 SPI_RAM
-!
-!
-! P1.1 - UCB0 CLK PL1.9 - ----> SD_CLK
-! P1.2 - UCB0 SIMO PL1.10 - ----> SD_SDI
-! P1.3 - UCB0 SOMI PL2.10 - <---- SD_SDO
-! P2.3 - PL1.6 - <---- SD_CD (Card Detect)
-! P2.2 - PL2.9 - ----> SD_CS (Card Select)
-!
-! P1.2 - UCB0 SDA PL1.10 - <---> SDA I2C Slave
-! P1.3 - UCB0 SCL PL2.10 - ----> SCL I2C Slave
-!
-! P2.2 - PL2.9 - ----> SCL I2C SoftMaster
-! P2.0 - PL2.3 - <---> SDA I2C SoftMaster
-!
-! P1.0 - UCB0 STE PL1.8 - <---- TSSOP32236 (IR RC5)
-
-
-! ============================================
-! FORTH I/O :
-! ============================================
-!TERMINAL
-BUS_TERM=\$30! ; P1.4 = TX, P1.5 = RX
-
-TERM_IN=\$200!
-TERM_REN=\$206!
-TERM_SEL=\$20A! \SEL0
-
-TERM_VEC=\$FFE4! \ UCA0
-WAKE_UP=1! \ RX int
-
-TERM_CTLW0=\$500! \ eUSCI_A control word 0
-TERM_CTLW1=\$502! \ eUSCI_A control word 1
-TERM_BRW=\$506!
-TERM_BR0=\$506! \ eUSCI_A baud rate 0
-TERM_BR1=\$507! \ eUSCI_A baud rate 1
-TERM_MCTLW=\$508! \ eUSCI_A modulation control
-TERM_STATW=\$50A! \ eUSCI_A status
-TERM_RXBUF=\$50C! \ eUSCI_A receive buffer
-TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer
-TERM_ABCTL=\$510! \ eUSCI_A LIN control
-TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control
-TERM_IE=\$51A! \ eUSCI_A interrupt enable
-TERM_IFG=\$51C! \ eUSCI_A interrupt flags
-TERM_IV=\$51E! \ eUSCI_A interrupt vector word
-
-RTS=4! ; P3.2
-CTS=1! ; P3.0
-HANDSHAKIN=\$220!
-HANDSHAKOUT=\$222!
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-LED1_OUT=\$222!
-LED1=\$02! P3.1
-
-SW1_IN=\$201!
-SW1=\$02! P2.1
-
-WIPE_IN=\$201!
-IO_WIPE=\$02! P2.1
-
-SW2_IN=\$201!
-SW2=\$01! P2.0
-
-
-IR_IN=\$200!
-IR_OUT=\$202!
-IR_DIR=\$204!
-IR_REN=\$208!
-IR_IES=\$218!
-IR_IE=\$21A!
-IR_IFG=\$21C!
-IR_VEC=\$FFDC! P1 int
-RC5_=RC5_!
-RC5=\$01! P1.0
-
-I2CSM_IN=\$201!
-I2CSM_OUT=\$203!
-I2CSM_DIR=\$205!
-I2CSM_REN=\$207!
-SMSDA=\$01! P2.0
-SMSCL=\$04! P2.2
-SM_BUS=\$05!
-
-I2CSMM_IN=\$201!
-I2CSMM_OUT=\$203!
-I2CSMM_DIR=\$205!
-I2CSMM_REN=\$207!
-SMMSDA=\$01! P2.0
-SMMSCL=\$04! P2.2
-SMM_BUS=\$05!
-
-I2CMM_IN=\$200!
-I2CMM_OUT=\$202!
-I2CMM_DIR=\$204!
-I2CMM_REN=\$206!
-I2CMM_SEL=\$20A! SEL0
-I2CMM_VEC=\$FFE0!
-MMSDA=\$04! P1.2
-MMSCL=\$08! P1.3
-MM_BUS=\$0C!
-
-I2CM_IN=\$200!
-I2CM_OUT=\$202!
-I2CM_DIR=\$204!
-I2CM_REN=\$206!
-I2CM_SEL=\$20A! SEL0
-I2CM_VEC=\$FFE0!
-MSDA=\$04! P1.2
-MSCL=\$08! P1.3
-M_BUS=\$0C!
-
-I2CS_IN=\$200!
-I2CS_OUT=\$202!
-I2CS_DIR=\$204!
-I2CS_REN=\$206!
-I2CS_SEL=\$20A! SEL0
-I2CS_VEC=\$FFE0!
-SSDA=\$40! P1.2
-SSCL=\$80! P1.3
-S_BUS=\$C0!
-
-
-CD_SD=8! ; P2.3 as Card Detect
-SD_CDIN=\$201!
-
-CS_SD=4! ; P2.2 as Card Select
-SD_CSOUT=\$203!
-SD_CSDIR=\$205!
-
-BUS_SD=\$0E! ; pins P1.1 as UCB0CLK, P1.2 as UCB0SIMO & P1.3 as UCB0SOMI
-SD_SEL=\$20A! ; PASEL0 to configure UCB0
-SD_REN=\$206! ; to configure pullup resistors
+; ---------------------------------------------------
+; CHIPSTICK_FR2433 <--> OUTPUT WORLD
+; ---------------------------------------------------
+; P3.1 - LED1
+;
+; P2.1 - PL2.2 - SW1
+; P2.0 - PL2.3 - SW2
+;
+; +--4k7-< DeepRST <-- GND
+; |
+; P1.4 - UCA0 TXD PL1.4 - <-+-> RX UARTtoUSB bridge
+; P1.5 - UCA0 RXD PL1.3 - <---- TX UARTtoUSB bridge
+; P3.2 - RTS PL1.2 - ----> CTS UARTtoUSB bridge (option)
+; -
+; P3.0 - PL1.7 - ----> /CS SPI_RAM
+; P1.1 - UCB0 CLK PL1.9 - ----> CLK SPI_RAM
+; P1.2 - UCB0 SIMO PL1.10 - ----> SI SPI_RAM
+; P1.3 - UCB0 SOMI PL2.10 - <---- S0 SPI_RAM
+;
+;
+; P1.1 - UCB0 CLK PL1.9 - ----> SD_CLK
+; P1.2 - UCB0 SIMO PL1.10 - ----> SD_SDI
+; P1.3 - UCB0 SOMI PL2.10 - <---- SD_SDO
+; P2.3 - PL1.6 - <---- SD_CD (Card Detect)
+; P2.2 - PL2.9 - ----> SD_CS (Card Select)
+;
+; P1.2 - UCB0 SDA PL1.10 - <---> SDA I2C Slave
+; P1.3 - UCB0 SCL PL2.10 - ----> SCL I2C Slave
+;
+; P2.2 - PL2.9 - ----> SCL I2C SoftMaster
+; P2.0 - PL2.3 - <---> SDA I2C SoftMaster
+;
+; P1.0 - UCB0 STE PL1.8 - <---- TSSOP32236 (IR RC5)
+
+
+; ============================================
+; FORTH I/O :
+; ============================================
+;TERMINAL
+BUS_TERM=\$30; ; P1.4 = TX, P1.5 = RX
+
+TERM_IN=\$200;
+TERM_REN=\$206;
+TERM_SEL=\$20A; \SEL0
+
+TERM_VEC=\$FFE4; \ UCA0
+WAKE_UP=1; \ RX int
+
+TERM_CTLW0=\$500; \ eUSCI_A control word 0
+TERM_CTLW1=\$502; \ eUSCI_A control word 1
+TERM_BRW=\$506;
+TERM_BR0=\$506; \ eUSCI_A baud rate 0
+TERM_BR1=\$507; \ eUSCI_A baud rate 1
+TERM_MCTLW=\$508; \ eUSCI_A modulation control
+TERM_STATW=\$50A; \ eUSCI_A status
+TERM_RXBUF=\$50C; \ eUSCI_A receive buffer
+TERM_TXBUF=\$50E; \ eUSCI_A transmit buffer
+TERM_ABCTL=\$510; \ eUSCI_A LIN control
+TERM_IRTCTL=\$512; \ eUSCI_A IrDA transmit control
+TERM_IRRCTL=\$513; \ eUSCI_A IrDA receive control
+TERM_IE=\$51A; \ eUSCI_A interrupt enable
+TERM_IFG=\$51C; \ eUSCI_A interrupt flags
+TERM_IV=\$51E; \ eUSCI_A interrupt vector word
+
+RTS=4; ; P3.2
+CTS=1; ; P3.0
+HANDSHAKIN=\$220;
+HANDSHAKOUT=\$222;
+
+; ============================================
+; APPLICATION I/O :
+; ============================================
+LED1_OUT=\$222;
+LED1=\$02; P3.1
+
+SW1_IN=\$201;
+SW1=\$02; P2.1
+
+WIPE_IN=\$201;
+IO_WIPE=\$02; P2.1
+
+SW2_IN=\$201;
+SW2=\$01; P2.0
+
+
+IR_IN=\$200;
+IR_OUT=\$202;
+IR_DIR=\$204;
+IR_REN=\$208;
+IR_IES=\$218;
+IR_IE=\$21A;
+IR_IFG=\$21C;
+IR_VEC=\$FFDC; P1 int
+RC5_=RC5_;
+RC5=\$01; P1.0
+
+I2CSM_IN=\$201;
+I2CSM_OUT=\$203;
+I2CSM_DIR=\$205;
+I2CSM_REN=\$207;
+SMSDA=\$01; P2.0
+SMSCL=\$04; P2.2
+SM_BUS=\$05;
+
+I2CSMM_IN=\$201;
+I2CSMM_OUT=\$203;
+I2CSMM_DIR=\$205;
+I2CSMM_REN=\$207;
+SMMSDA=\$01; P2.0
+SMMSCL=\$04; P2.2
+SMM_BUS=\$05;
+
+I2CMM_IN=\$200;
+I2CMM_OUT=\$202;
+I2CMM_DIR=\$204;
+I2CMM_REN=\$206;
+I2CMM_SEL=\$20A; SEL0
+I2CMM_VEC=\$FFE0;
+MMSDA=\$04; P1.2
+MMSCL=\$08; P1.3
+MM_BUS=\$0C;
+
+I2CM_IN=\$200;
+I2CM_OUT=\$202;
+I2CM_DIR=\$204;
+I2CM_REN=\$206;
+I2CM_SEL=\$20A; SEL0
+I2CM_VEC=\$FFE0;
+MSDA=\$04; P1.2
+MSCL=\$08; P1.3
+M_BUS=\$0C;
+
+I2CS_IN=\$200;
+I2CS_OUT=\$202;
+I2CS_DIR=\$204;
+I2CS_REN=\$206;
+I2CS_SEL=\$20A; SEL0
+I2CS_VEC=\$FFE0;
+SSDA=\$40; P1.2
+SSCL=\$80; P1.3
+S_BUS=\$C0;
+
+
+CD_SD=8; ; P2.3 as Card Detect
+SD_CDIN=\$201;
+
+CS_SD=4; ; P2.2 as Card Select
+SD_CSOUT=\$203;
+SD_CSDIR=\$205;
+
+BUS_SD=\$0E; ; pins P1.1 as UCB0CLK, P1.2 as UCB0SIMO & P1.3 as UCB0SOMI
+SD_SEL=\$20A; ; PASEL0 to configure UCB0
+SD_REN=\$206; ; to configure pullup resistors
-!FastForthREGtoTI.pat
-! ============================================
-! translate Forth registers to TI's ones
-! ============================================
-
-PC=R0!
-SP=R1!
-RSP=R1!
-SR=R2!
-CG1=R2!
-CG2=R3!
-rDOCOL=R4!
-rDODOES=R5!
-rDOCON=R6!
-rDOVAR=R7!
-R=R4!
-Q=R5!
-P=R6!
-M=R7!
-Y=R8!
-X=R9!
-W=R10!
-T=R11!
-S=R12!
-IP=R13!
-TOS=R14!
-PSP=R15!
-
-! forth words filter
-\"\s*\"=\"\s*\"! ." xxxx" filter
-S\"\s*\"=S\"\s*\"! S" xxxx" filter
-s\"\s*\"=S\"\s*\"! s" xxxx" filter
-\(\s*\)=\(\s*\)! ( xxxx) and .( xxxx) filter
-abort\"\s*\"=ABORT\"\s*\"! abort" xxxx" filter
-ABORT\"\s*\"=ABORT\"\s*\"! ABORT" xxxx" filter
-!
-D\.R=D\.R!
-!
-M\*=M\*!
-M\+=M\+!
-!
-R\>=R\>!
-R\@=R\@!
-\>R=\>R!
-!
-S\>=S\>!
-\>S=\>S!
-S\<=S\<!
-S\>\==S\>\=!
-\.S=\.S!
-\s\_=\S\_! s_ filter
-\S\_=\S\_! S_ filter
-!
-\<\#=\<\#!
-\#S=\#S!
-\#\>=\#\>!
-!
-T\{=T\{!
-\}T=\}T!
-!
-U\.R=U\.R!
-!
-! ASCII numbers interpreter complement
-'NUL'=\$00!
-'SOH'=\$01!
-'STX'=\$02!
-'ETX'=\$03!
-'EOT'=\$04!
-'ENQ'=\$05!
-'ACK'=\$06!
-'BEL'=\$07!
-'BS'=\$08! Backspace
-'HT'=\$09! Horizontal Tabulation
-'LF'=\$0A!
-'VT'=\$0B!
-'FF'=\$0C!
-'CR'=\$0D!
-'SO'=\$0E!
-'SI'=\$0F!
-'DLE'=\$10!
-'DC1'=\$11!
-'XON'=\$11!
-'DC2'=\$12!
-'DC3'=\$13!
-'XOFF'=\$13!
-'DC4'=\$14!
-'NAK'=\$15!
-'SYN'=\$16!
-'ETB'=\$17!
-'CAN'=\$18!
-'EM'=\$19!
-'SUB'=\$1A!
-'ESC'=\$1B! escape char
-'FS'=\$1C!
-'GS'=\$1D!
-'RS'=\$1E!
-'US'=\$1F!
-'SP'=\$20!
-'DEL'=\$7F!
-'R'='R'!
-'Q'='Q'!
-'P'='P'!
-'M'='M'!
-'Y'='Y'!
-'X'='X'!
-'W'='W'!
-'T'='T'!
-'S'='S'!
-(SW1)=(SW1)!
-(SW2)=(SW2)!
-(RST)=(RST)!
-\/RTS=\/RTS!
-\/CTS=\/CTS!
-XON\/XOFF=XON\/XOFF!
-
-! ============================================
-! SR bits :
-! ============================================
-\#C=\#1! = SR(0) Carry flag
-\#Z=\#2! = SR(1) Zero flag
-\#N=\#4! = SR(2) Negative flag
-\#V=\#\$100! = SR(8) oVerflow flag
-GIE=8! = SR(3) Enable Int
-CPUOFF=\$10! = SR(4) CPUOFF
-OSCOFF=\$20! = SR(5) OSCOFF
-SCG0=\$40! = SR(6) SCG0
-SCG1=\$80! = SR(7) SCG1
-UF9=\$200! = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
-UF10=\$400! = SR(10) User Flag 2
-UF11=\$800! = SR(11) User Flag 3
-
-LPM4=\$F0! SR(LPM4)
-LPM3=\$D0! SR(LPM3)
-LPM2=\$90! SR(LPM2)
-LPM1=\$50! SR(LPM1)
-LPM0=\$10! SR(LPM0)
-
-! ============================================
-! PORTx, Reg bits :
-! ============================================
-BIT0=1!
-BIT1=2!
-BIT2=4!
-BIT3=8!
-BIT4=\$10!
-BIT5=\$20!
-BIT6=\$40!
-BIT7=\$80!
-BIT8=\$100!
-BIT9=\$200!
-BIT10=\$400!
-BIT11=\$800!
-BIT12=\$1000!
-BIT13=\$2000!
-BIT14=\$4000!
-BIT15=\$8000!
-
-! ============================================
-! symbolic codes :
-! ============================================
-RET=MOV \@R1+,R0! \ MOV @RSP+,PC
-RETA=MOVA \@R1+,R0! \ MOVA @RSP+,PC
-NOP=MOV \#0,R3! \ one word one cycle
-NOP2=\$3C00 ,! \ compile JMP 0 one word two cycles
-NOP3=MOV R0,R0! \ MOV PC,PC one word three cycles
-NEXT=MOV \@R13+,R0! \ MOV @IP+,PC
-\'\ \\=\'\ \\! \ to compile INTERPRET in CORE_ANS.f
-DODOES=\$1285!
-DOCON=\$1286!
-DOVAR=\$1287!
-
-! ============================================
-! ADD-ON flags :
-! ============================================
-FLOORED=\$8000!
-LF_XTAL=\$4000!
-HMPY=1!
\ No newline at end of file
+
+@set-syntax{C;\;}! tell GEMA to replace Comment separator '!' by ';'
+; ============================================
+;FastForthREGtoTI.pat
+; ============================================
+; translate Forth registers to TI's ones
+; ============================================
+PC=R0
+SP=R1
+RSP=R1
+SR=R2
+CG1=R2
+CG2=R3
+rDOCOL=R4
+rDODOES=R5
+rDOCON=R6
+rDOVAR=R7
+R=R4
+Q=R5
+P=R6
+M=R7
+Y=R8
+X=R9
+W=R10
+T=R11
+S=R12
+IP=R13
+TOS=R14
+PSP=R15
+
+; forth words filter
+\"\s*\"=\"\s*\"; "; ." xxxx" filter
+S\"\s*\"=S\"\s*\"; "; S" xxxx" filter
+s\"\s*\"=S\"\s*\"; "; s" xxxx" filter
+\(\s*\)=\(\s*\); ( xxxx) and .( xxxx) filter
+abort\"\s*\"=ABORT\"\s*\"; "; abort" xxxx" filter
+ABORT\"\s*\"=ABORT\"\s*\"; "; ABORT" xxxx" filter
+
+D\.R=D\.R
+
+FLOORED\/SYMETRIC=FLOORED\/SYMETRIC
+
+M\*=M\*
+M\+=M\+
+
+R\>=R\>
+R\@=R\@
+\>R=\>R
+
+S\>=S\>
+\>S=\>S
+S\<=S\<
+S\>\==S\>\=
+S\?=S\?
+\.S=\.S
+
+\<\#=\<\#
+\#S=\#S
+\#\>=\#\>
+\#\\=\#\\
+\#\!=\#\!
+\#\@=\#\@
+
+T\{=T\{; CORETEST filter
+\}T=\}T; CORETEST filter
+
+U\.R=U\.R
+
+; ASCII numbers interpreter complement
+'NUL'=\$00
+'SOH'=\$01
+'STX'=\$02
+'ETX'=\$03
+'EOT'=\$04
+'ENQ'=\$05
+'ACK'=\$06
+'BEL'=\$07
+'BS'=\$08; Backspace
+'HT'=\$09; Horizontal Tabulation
+'LF'=\$0A
+'VT'=\$0B
+'FF'=\$0C
+'CR'=\$0D
+'SO'=\$0E
+'SI'=\$0F
+'DLE'=\$10
+'DC1'=\$11
+'XON'=\$11
+'DC2'=\$12
+'DC3'=\$13
+'XOFF'=\$13
+'DC4'=\$14
+'NAK'=\$15
+'SYN'=\$16
+'ETB'=\$17
+'CAN'=\$18
+'EM'=\$19
+'SUB'=\$1A
+'ESC'=\$1B; escape char
+'FS'=\$1C
+'GS'=\$1D
+'RS'=\$1E
+'US'=\$1F
+'SP'=\$20
+'DEL'=\$7F
+'R'='R'
+'Q'='Q'
+'P'='P'
+'M'='M'
+'Y'='Y'
+'X'='X'
+'W'='W'
+'T'='T'
+'S'='S'
+(SW1)=(SW1)
+(SW2)=(SW2)
+(RST)=(RST)
+\/RTS=\/RTS
+\/CTS=\/CTS
+XON\/XOFF=XON\/XOFF
+
+; ============================================
+; SR bits :
+; ============================================
+\#C=\#1; = SR(0) Carry flag
+\#Z=\#2; = SR(1) Zero flag
+\#N=\#4; = SR(2) Negative flag
+\#V=\#\$100; = SR(8) oVerflow flag
+
+GIE=8; = SR(3) Enable Int
+CPUOFF=\$10; = SR(4) CPUOFF
+OSCOFF=\$20; = SR(5) OSCOFF
+SCG0=\$40; = SR(6) SCG0
+SCG1=\$80; = SR(7) SCG1
+LPM4=\$F0; = SR(LPM4)
+LPM3=\$D0; = SR(LPM3)
+LPM2=\$90; = SR(LPM2)
+LPM1=\$50; = SR(LPM1)
+LPM0=\$10; = SR(LPM0)
+
+UF9=\$200; = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use.
+UF10=\$400; = SR(10) User Flag 2
+UF11=\$800; = SR(11) User Flag 3
+
+; ============================================
+; PORTx, Reg bits :
+; ============================================
+\#BIT0=\#1
+\#BIT1=\#2
+\#BIT2=\#4
+\#BIT3=\#8
+\#BIT4=\#\$10
+\#BIT5=\#\$20
+\#BIT6=\#\$40
+\#BIT7=\#\$80
+\#BIT8=\#\$100
+\#BIT9=\#\$200
+\#BIT10=\#\$400
+\#BIT11=\#\$800
+\#BIT12=\#\$1000
+\#BIT13=\#\$2000
+\#BIT14=\#\$4000
+\#BIT15=\#\$8000
+
+; ============================================
+; symbolic codes :
+; ============================================
+RET=MOV \@R1+,R0; MOV @RSP+,PC
+RETA=MOVA \@R1+,R0; MOVA @RSP+,PC
+NOP=MOV \#0,R3; one word one cycle
+NOP2=\$3C00 ,; compile JMP 0 one word two cycles
+NOP3=MOV R0,R0; MOV PC,PC one word three cycles
+NEXT=MOV \@R13+,R0; MOV @IP+,PC
+DODOES=\$1285;
+DOCON=\$1286;
+DOVAR=\$1287;
-! -*- coding: utf-8 -*-
-! LP_MSP430FR2476.pat
-!
-\.f=\.4th for LP_MSP430FR2476! to change file type
-!
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! replace ! by semicolon
+; LP_MSP430FR2476.pat
+;
+\.f=\.4th for LP_MSP430FR2476; to change file type
+; ========================
+; remove comments
+; ========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! LP_MSP430FR2476 Config
-! ======================================================================
+; ======================================================================
+; LP_MSP430FR2476 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR2476.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR2xxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-
-! ======================================================================
-! LP_MSP430FR2476 board
-! ======================================================================
-!
-! ===================================================================================
-! in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
-! ===================================================================================
-!
-! J101 Target J101 eZ-FET UARTtoUSB
-!
-! DVSS 14 o--o 13 GND
-! 5V0 12 o--o 11 5V0
-! DVCC 10 o--o 9 3V3
-! P1.5 UCA0_RX 8 o--o 7 <------------ TX UARTtoUSB
-! P1.4 UCA0_TX 6 o--o 5 <---------+-> RX UARTtoUSB
-! SBWTDIO/RST 4 o--o 3 | _
-! SBWTCK/TST 2 o--o 1 +--4k7---o o-- GND
-! DeepRST
-! J1 - left ext.
-! 3v3
-! P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
-! P2.5/UCA1RXD/UCA1SOMI/CAP1.2
-! P2.6/UCA1TXD/UCA1SIMO/CAP1.3
-! P2.2/SYNC/ACLK/COMP0.1
-! P5.4/UCB1STE/TA3CLK/A11
-! P3.5/UCB1CLK/TB0TRG/CAP3.1
-! P4.5/UCB0SOMI/UCB0SCL/TA3.2
-! P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
-! P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/VEREF-
-!
-!
-! J3 - left int.
-! 5V
-! GND
-! P1.7/UCA0STE/SMCLK/TDO/A7
-! P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8
-! P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9
-! P5.3/UCB1CLK/TA3.0/A10
-! P1.0/UCB0STE/TA0CLK/A0/VEREF+ - J7 - LED1
-! P1.1/UCB0CLK/TA0.1/COMP0.0/A1 - TEMPERATURE SENSOR
-! P5.7/TA2.1/COMP0.2
-! P3.7/TA3.2/CAP2.0
-!
-! J4 - right int.
-! P5.2/UCA0TXD/UCA0SIMO/TB0.4
-! P5.1/UCA0RXD/UCA0SOMI/TB0.3 - J8 - LED2R
-! P5.0/UCA0CLK/TB0.2 - J8 - LED2G
-! P4.7/UCA0STE/TB0.1 - J8 - LED2B
-! P6.0/TA2.2/COMP0.3
-! P3.3/TA2.1/CAP0.1
-! P6.1/TB0CLK
-! P6.2/TB0.0
-! P4.1/TA3.0/CAP2.2
-! P3.1/UCA1STE/CAP1.0
-!
-! J2 - right ext.
-! GND
-! P4.6/UCB0SIMO/UCB0SDA/TA3.1
-! P2.1/XIN
-! P2.0/XOUT
-! /RST
-! P3.2/UCB1SIMO/UCB1SDA/CAP3.2
-! P3.6/UCB1SOMI/UCB1SCL/CAP3.3
-! P4.2/TA3CLK/CAP2.3
-! P2.7/UCB1STE/CAP3.0
-! P2.4/UCA1CLK/CAP1.1
-!
-! switch-keys:
-! P4.0/TA3.1/CAP2.1 - S1
-! P2.3/TA2.0/CAP0.2 - S2
-! /RST - S3
-!
-! XTAL LF 32768 Hz
-! P2.0/XOUT
-! P2.1/XIN
-!
-!
-! Clocks:
-! 8 MHz DCO intern
-!
-!
-!
-! ===================================================================================
-! in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
-! ===================================================================================
-!
-! -----------------------------------------------
-! MSP430FR5969 LAUNCHPAD <--> OUTPUT WORLD
-! -----------------------------------------------
-!
-! ----------------------------------------
-! Temperature sensor : jumper J9 removed !
-! ----------------------------------------
-!
-! P4.0 - Switch S1 <--- LCD contrast + (finger :-)
-! P2.3 - Switch S2 <--- LCD contrast - (finger ;-)
-!
-! GND - <-------+---0V0----------> 1 LCD_Vss
-! VCC - >------ | --3V6-----+----> 2 LCD_Vdd
-! | |
-! |___ 470n ---
-! ^ | ---
-! / \ BAT54 |
-! --- |
-! 100n | 2k2 |
-! P4.7 - TB0.1 J4 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! P5.0 - J4 ----------orange---------> 4 LCD_RS
-! P5.1 - J4 ----------blue-----------> 5 LCD_R/W
-! P5.2 - J4 ----------black----------> 6 LCD_EN
-! P1.0 - J3 <---------brown----------> 11 LCD_DB4
-! P1.1 - J3 <---------red------------> 12 LCD_DB5
-! P1.2 - J1 <---------orange---------> 13 LCD_DB5
-! P1.3 - J1 <---------yellow---------> 14 LCD_DB7
-!
-! +--4k7-< DeepRST <-- GND
-! |
-! P1.4 - UCA0 TXD J101.8 <-+->white--> RX UARTtoUSB bridge
-! P1.5 - UCA0 RXD J101.10 <----green--- TX UARTtoUSB bridge
-! VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
-! GND - J101.20 <---> GND
-! P6.1 - RTS J4 ----blue----> CTS UARTtoUSB bridge (optional hardware control flow)
-! P6.2 - CTS J4 ---yellow---> RTS UARTtoUSB bridge (optional hardware control flow)
-!
-!
-! VCC - ----> VCC SD_CardAdapter
-! GND - <---> GND SD_CardAdapter
-! P2.4 - UCA1 CLK J2 ----> CLK SD_CardAdapter (SCK)
-! P2.6 - UCA1 TXD/SIMO J1 ----> SDI SD_CardAdapter (MOSI)
-! P2.5 - UCA1 RXD/SOMI J1 <---- SDO SD_CardAdapter (MISO)
-! P1.6 - J4 ----> CS SD_CardAdapter (Card Select)
-! P1.7 - J4 <---- CD SD_CardAdapter (Card Detect)
-!
-!
-! P2.2 - J3.10 <---- OUT IR_Receiver (1 TSOP32236) ───┐
-! └┌───┐
-! VCC - ----> VCC IR_Receiver (2 TSOP32236) ────| O |
-! ┌└───┘
-! GND - <---> GND IR_Receiver (3 TSOP32236) ───┘
-!
-! P4.3 - UCB1 SCL/SOMI J3 ----> SCL I2C MASTER/SLAVE
-! P4.4 - UCB1 SDA/SIMO J3 <---> SDA I2C MASTER/SLAVE
-
-! P3.3 - J4 ----> SCL SOFTWARE I2C MASTER
-! P3.2 - J2 <---> SDA SOFTWARE I2C MASTER
-
-
-
-! ============================================
-! FORTH I/O :
-! ============================================
-!TERMINAL
-BUS_TERM=\$30! ; P1.4 = TX, P1.5 = RX
-
-TERM_IN=\$200!
-TERM_REN=\$206!
-TERM_SEL=\$20A! \SEL0
-
-TERM_VEC=\$FFE4! \ UCA0
-WAKE_UP=1! \ RX int
-
-TERM_CTLW0=\$500! \ eUSCI_A control word 0
-TERM_CTLW1=\$502! \ eUSCI_A control word 1
-TERM_BRW=\$506!
-TERM_BR0=\$506! \ eUSCI_A baud rate 0
-TERM_BR1=\$507! \ eUSCI_A baud rate 1
-TERM_MCTLW=\$508! \ eUSCI_A modulation control
-TERM_STATW=\$50A! \ eUSCI_A status
-TERM_RXBUF=\$50C! \ eUSCI_A receive buffer
-TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer
-TERM_ABCTL=\$510! \ eUSCI_A LIN control
-TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control
-TERM_IE=\$51A! \ eUSCI_A interrupt enable
-TERM_IFG=\$51C! \ eUSCI_A interrupt flags
-TERM_IV=\$51E! \ eUSCI_A interrupt vector word
-
-RTS=2! P6.1
-CTS=4! P6.2
-HANDSHAKIN=\$241!
-HANDSHAKOUT=\$243!
-
-CD_SD=\$80! P1.7 as Card Detect
-SD_CDIN=\$200!
-
-CS_SD=\$40! P1.6 as Card Select
-SD_CSOUT=\$202!
-SD_CSDIR=\$204!
-
-BUS_SD=\$7000! pins P2.4 as UCA1CLK, P2.6 as UCA1SIMO & P2.5 as UCA1SOMI
-SD_SEL=\$20A! PASEL0 to configure UCA1
-SD_REN=\$206! PAREN to configure pullup resistors
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-LED2_OUT=\$202!
-LED2_DIR=\$204!
-LED2=1! P1.0 green led
-
-LED1_OUT=\$242!
-LED1_DIR=\$244!
-LED1=2! P5.1 red led
-
-SW1_IN=\$221!
-SW1=1! P4.0 = S1
-WIPE_IN\$221!
-IO_WIPE=1! P4.0 = S1 = FORTH Deep_RST pin
-
-SW2_IN=\$201!
-SW2=8! P2.3 S2
-
-
-!LCD_Vo PWM
-LCDVo_DIR=\$225! P4
-LCDVo_SEL=\$22D! SEL1
-LCDVo=\$80! P4.7 as TB0.1
-!LCD command bus
-LCD_CMD_IN=\$240! P5
+; ======================================================================
+; LP_MSP430FR2476 board
+; ======================================================================
+;
+; ===================================================================================
+; in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
+; ===================================================================================
+;
+; J101 Target J101 eZ-FET UARTtoUSB
+;
+; DVSS 14 o--o 13 GND
+; 5V0 12 o--o 11 5V0
+; DVCC 10 o--o 9 3V3
+; P1.5 UCA0_RX 8 o--o 7 <------------ TX UARTtoUSB
+; P1.4 UCA0_TX 6 o--o 5 <---------+-> RX UARTtoUSB
+; SBWTDIO/RST 4 o--o 3 | _
+; SBWTCK/TST 2 o--o 1 +--4k7---o o-- GND
+; DeepRST
+; J1 - left ext.
+; 3v3
+; P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6
+; P2.5/UCA1RXD/UCA1SOMI/CAP1.2
+; P2.6/UCA1TXD/UCA1SIMO/CAP1.3
+; P2.2/SYNC/ACLK/COMP0.1
+; P5.4/UCB1STE/TA3CLK/A11
+; P3.5/UCB1CLK/TB0TRG/CAP3.1
+; P4.5/UCB0SOMI/UCB0SCL/TA3.2
+; P1.3/UCB0SOMI/UCB0SCL/MCLK/A3
+; P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/VEREF-
+;
+;
+; J3 - left int.
+; 5V
+; GND
+; P1.7/UCA0STE/SMCLK/TDO/A7
+; P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8
+; P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9
+; P5.3/UCB1CLK/TA3.0/A10
+; P1.0/UCB0STE/TA0CLK/A0/VEREF+ - J7 - LED1
+; P1.1/UCB0CLK/TA0.1/COMP0.0/A1 - TEMPERATURE SENSOR
+; P5.7/TA2.1/COMP0.2
+; P3.7/TA3.2/CAP2.0
+;
+; J4 - right int.
+; P5.2/UCA0TXD/UCA0SIMO/TB0.4
+; P5.1/UCA0RXD/UCA0SOMI/TB0.3 - J8 - LED2R
+; P5.0/UCA0CLK/TB0.2 - J8 - LED2G
+; P4.7/UCA0STE/TB0.1 - J8 - LED2B
+; P6.0/TA2.2/COMP0.3
+; P3.3/TA2.1/CAP0.1
+; P6.1/TB0CLK
+; P6.2/TB0.0
+; P4.1/TA3.0/CAP2.2
+; P3.1/UCA1STE/CAP1.0
+;
+; J2 - right ext.
+; GND
+; P4.6/UCB0SIMO/UCB0SDA/TA3.1
+; P2.1/XIN
+; P2.0/XOUT
+; /RST
+; P3.2/UCB1SIMO/UCB1SDA/CAP3.2
+; P3.6/UCB1SOMI/UCB1SCL/CAP3.3
+; P4.2/TA3CLK/CAP2.3
+; P2.7/UCB1STE/CAP3.0
+; P2.4/UCA1CLK/CAP1.1
+;
+; switch-keys:
+; P4.0/TA3.1/CAP2.1 - S1
+; P2.3/TA2.0/CAP0.2 - S2
+; /RST - S3
+;
+; XTAL LF 32768 Hz
+; P2.0/XOUT
+; P2.1/XIN
+;
+;
+; Clocks:
+; 8 MHz DCO intern
+;
+;
+;
+; ===================================================================================
+; in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
+; ===================================================================================
+;
+; -----------------------------------------------
+; MSP430FR5969 LAUNCHPAD <--> OUTPUT WORLD
+; -----------------------------------------------
+;
+; ----------------------------------------
+; Temperature sensor : jumper J9 removed ;
+; ----------------------------------------
+;
+; P4.0 - Switch S1 <--- LCD contrast + (finger :-)
+; P2.3 - Switch S2 <--- LCD contrast - (finger ;-)
+;
+; GND - <-------+---0V0----------> 1 LCD_Vss
+; VCC - >------ | --3V6-----+----> 2 LCD_Vdd
+; | |
+; |___ 470n ---
+; ^ | ---
+; / \ BAT54 |
+; --- |
+; 100n | 2k2 |
+; P4.7 - TB0.1 J4 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; P5.0 - J4 ----------orange---------> 4 LCD_RS
+; P5.1 - J4 ----------blue-----------> 5 LCD_R/W
+; P5.2 - J4 ----------black----------> 6 LCD_EN
+; P1.0 - J3 <---------brown----------> 11 LCD_DB4
+; P1.1 - J3 <---------red------------> 12 LCD_DB5
+; P1.2 - J1 <---------orange---------> 13 LCD_DB5
+; P1.3 - J1 <---------yellow---------> 14 LCD_DB7
+;
+; +--4k7-< DeepRST <-- GND
+; |
+; P1.4 - UCA0 TXD J101.8 <-+->white--> RX UARTtoUSB bridge
+; P1.5 - UCA0 RXD J101.10 <----green--- TX UARTtoUSB bridge
+; VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ; 3.3V !)
+; GND - J101.20 <---> GND
+; P6.1 - RTS J4 ----blue----> CTS UARTtoUSB bridge (optional hardware control flow)
+; P6.2 - CTS J4 ---yellow---> RTS UARTtoUSB bridge (optional hardware control flow)
+;
+;
+; VCC - ----> VCC SD_CardAdapter
+; GND - <---> GND SD_CardAdapter
+; P2.4 - UCA1 CLK J2 ----> CLK SD_CardAdapter (SCK)
+; P2.6 - UCA1 TXD/SIMO J1 ----> SDI SD_CardAdapter (MOSI)
+; P2.5 - UCA1 RXD/SOMI J1 <---- SDO SD_CardAdapter (MISO)
+; P1.6 - J4 ----> CS SD_CardAdapter (Card Select)
+; P1.7 - J4 <---- CD SD_CardAdapter (Card Detect)
+;
+;
+; P2.2 - J3.10 <---- OUT IR_Receiver (1 TSOP32236) ───┐
+; └┌───┐
+; VCC - ----> VCC IR_Receiver (2 TSOP32236) ────| O |
+; ┌└───┘
+; GND - <---> GND IR_Receiver (3 TSOP32236) ───┘
+;
+; P4.3 - UCB1 SCL/SOMI J3 ----> SCL I2C MASTER/SLAVE
+; P4.4 - UCB1 SDA/SIMO J3 <---> SDA I2C MASTER/SLAVE
+
+; P3.3 - J4 ----> SCL SOFTWARE I2C MASTER
+; P3.2 - J2 <---> SDA SOFTWARE I2C MASTER
+
+
+
+; ----------------------------------------------------------------------
+; MSP430FR2476 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;SYS_SFR .equ 0140h ; SYS
+;CS_SFR .equ 0180h ; Clock System
+;FRAM_SFR .equ 01A0h ; FRAM control
+;CRC16_SFR .equ 01C0h
+;WDT_A_SFR .equ 01CCh ; Watchdog
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3/4
+;PC_SFR .equ 0240h ; PORT5/6
+;RTC_SFR .equ 0300h
+;TA0_SFR .equ 0380h
+;TA1_SFR .equ 03C0h
+;TA2_SFR .equ 0400h
+;TA3_SFR .equ 0440h
+;TB0_SFR .equ 0480h
+;MPY_SFR .equ 04C0h
+;eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
+;eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
+;eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
+;eUSCI_B1_SFR .equ 0580h ; eUSCI_B1
+;BACK_MEM_SFR .equ 0660h
+;ADC10_B_SFR .equ 0700h
+;eCOMP_SFR .equ 08F0h
+
+;ECOMP0_VEC=\$FFCA;
+;P6_VEC=\$FFCC;
+;P5_VEC=\$FFCE;
+;P4_VEC=\$FFD0;
+;P3_VEC=\$FFD2;
+;P2_VEC=\$FFD4;
+;P1_VEC=\$FFD6;
+;ADC10_B_VEC=\$FFD8;
+;EUSCI_B1_VEC=\$FFDA;
+;EUSCI_B0_VEC=\$FFDC;
+;EUSCI_A1_VEC=\$FFDE;
+;EUSCI_A0_VEC=\$FFE0;
+;WDT_VEC=\$FFE2;
+;RTC_VEC=\$FFE4;
+;TB0_X_VEC=\$FFE6;
+;TB0_0_VEC=\$FFE8;
+;TA3_X_VEC=\$FFEA;
+;TA3_0_VEC=\$FFEC;
+;TA2_X_VEC=\$FFEE;
+;TA2_0_VEC=\$FFF0;
+;TA1_X_VEC=\$FFF2;
+;TA1_0_VEC=\$FFF4;
+;TA0_X_VEC=\$FFF6;
+;TA0_0_VEC=\$FFF8;
+;U_NMI_VEC=\$FFFA;
+;S_NMI_VEC=\$FFFC;
+;RST_VEC=\$FFFE;
+
+; ============================================
+; FAST FORTH configuration :
+; ============================================
+;TERMINAL
+BUS_TERM=\$30; ; P1.4 = TX, P1.5 = RX
+
+TERM_IN=\$200;
+TERM_REN=\$206;
+TERM_SEL=\$20A; \SEL0
+
+TERM_VEC=\$FFE4; \ UCA0
+UCSWRST=1; eUSCI Software Reset
+WAKE_UP=1; \ RX int
+RX=1; RX flag IFG
+TX=2; Tx flag IFG
+
+TERM_CTLW0=\$500; \ eUSCI_A control word 0
+TERM_CTLW1=\$502; \ eUSCI_A control word 1
+TERM_BRW=\$506;
+TERM_BR0=\$506; \ eUSCI_A baud rate 0
+TERM_BR1=\$507; \ eUSCI_A baud rate 1
+TERM_MCTLW=\$508; \ eUSCI_A modulation control
+TERM_STATW=\$50A; \ eUSCI_A status
+TERM_RXBUF=\$50C; \ eUSCI_A receive buffer
+TERM_TXBUF=\$50E; \ eUSCI_A transmit buffer
+TERM_ABCTL=\$510; \ eUSCI_A LIN control
+TERM_IRTCTL=\$512; \ eUSCI_A IrDA transmit control
+TERM_IRRCTL=\$513; \ eUSCI_A IrDA receive control
+TERM_IE=\$51A; \ eUSCI_A interrupt enable
+TERM_IFG=\$51C; \ eUSCI_A interrupt flags
+TERM_IV=\$51E; \ eUSCI_A interrupt vector word
+
+RTS=2; P6.1
+CTS=4; P6.2
+HANDSHAKIN=\$241;
+HANDSHAKOUT=\$243;
+
+CD_SD=\$80; P1.7 as Card Detect
+SD_CDIN=\$200;
+
+CS_SD=\$40; P1.6 as Card Select
+SD_CSOUT=\$202;
+SD_CSDIR=\$204;
+
+BUS_SD=\$7000; pins P2.4 as UCA1CLK, P2.6 as UCA1SIMO & P2.5 as UCA1SOMI
+SD_SEL=\$20A; PASEL0 to configure UCA1
+SD_REN=\$206; PAREN to configure pullup resistors
+
+LFXT_OUT=\$203; P2
+LFXT_DIR=\$205; P2
+LFXT_SEL=\$20B; P2SEL0
+LFXIN=\$2; P2.1
+LFXOUT=\$1; P2.0
+
+; FAST FORTH I/O :
+LED2_OUT=\$202;
+LED2_DIR=\$204;
+LED2=1; P1.0 green led
+LED1_OUT=\$242;
+LED1_DIR=\$244;
+LED1=2; P5.1 red led
+
+SW1_IN=\$221;
+SW1=1; P4.0 = S1
+SW2_IN=\$201;
+SW2=8; P2.3 S2
+
+; ============================================
+; COMMON UARTI2CS & RC5toLCD APPLICATIONs
+; ============================================
+;Software I2C_Master
+I2CSM_IN=\$220;
+I2CSM_OUT=\$222;
+I2CSM_DIR=\$224;
+I2CSM_REN=\$226;
+SM_SDA=4; P3.2
+SM_SCL=8; P3.3
+SM_BUS=\$0C;
+
+; ============================================
+; UARTI2CS APPLICATION
+; ============================================
+;500_ms_INT TIMER
+TIM_CTL=\$380; TA0
+TIM_CCTL2=\$386;
+TIM_CCR0=\$392;
+TIM_CCR2=\$396;
+T_OUT2=4; P1.2 <--- TA0.2
+T_OUT2_DIR=\$204; P1DIR
+T_OUT2_SEL=\$20C; P1SEL1
+INT_IN=2; P1.1
+INT_IN_IE=\$21A; P1IE
+INT_IN_IFG=\$21C; P1IFG
+INT_IN_VEC=\$FFD6; P1VEC
+
+;local variables
+UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+TIMER_CONF=\{UARTI2CS\}\+12; <-- TIM_CTL configuration
+COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+; ============================================
+; RC5toLCD APPLICATION
+; ============================================
+;LCD_Vo PWM
+LCDVo_DIR=\$225; P4
+LCDVo_SEL=\$22D; SEL1
+LCDVo=\$80; P4.7 as TB0.1
+;LCD command bus
+LCD_CMD_IN=\$240; P5
LCD_CMD_OUT=\$242
LCD_CMD_DIR=\$244
LCD_CMD_REN=\$246
-LCD_RS=1! P5.0
-LCD_RW=2! P5.1
-LCD_EN=4! P5.2
-LCD_CMD=\$32!
-!LCD data bus
-LCD_DB_IN=\$200! P1
-LCD_DB_OUT=\$202!
-LCD_DB_DIR=\$204!
-LCD_DB_REN=\$206!
-LCD_DB=\$0F! P1.3210
-!LCD timer
-LCD_TIM_CTL=\$480! TB0CTL
-LCD_TIM_CCTLn=\$484! TB0CCTL1
-LCD_TIM_CCR0=\$492! TB0CCR0
-LCD_TIM_CCRn=\$494! TB0CCR1
-LCD_TIM_EX0=\$4A0! TB0EX0
-
-
-!WATCHDOG timer
-WDT_TIM_CTL=\$380! TA0CTL
-WDT_TIM_CCTL0=\$382! TA0CCTL0
-WDT_TIM_CCR0=\$392! TA0CCR0
-WDT_TIM_EX0=\$3A0! TA0EX0
-WDT_TIM_0_VEC=\$FFF8! TA0_0_VEC
-
-
-!IR_RC5
-RC5_=RC5_!
-IR_IN=\$201!
-IR_OUT=\$203!
-IR_DIR=\$205!
-IR_REN=\$209!
-IR_IES=\$219!
-IR_IE=\$21B!
-IR_IFG=\$21D!
-IR_VEC=\$FFD4! P2 int
-RC5=4! P2.2
-!IR_RC5 timer
-RC5_TIM_CTL=\$3C0! TA1CTL
-RC5_TIM_R=\$3D0! TA1R
-RC5_TIM_EX0=\$3E0! TA1EX0
-
-!Software I2C_Master
-I2CSM_IN=\$220!
-I2CSM_OUT=\$222!
-I2CSM_DIR=\$224!
-I2CSM_REN=\$226!
-SMSDA=4! P3.2
-SMSCL=8! P3.3
-SM_BUS=\$0C!
-
-!Software I2C_Multi_Master
-I2CSMM_IN=\$220!
-I2CSMM_OUT=\$222!
-I2CSMM_DIR=\$224!
-I2CSMM_REN=\$226!
-SMMSDA=4! P3.2
-SMMSCL=8! P3.3
-SMM_BUS=\$0C!
-
-!hardware I2C_Multi_Master
-I2CMM_IN=\$221!
-I2CMM_OUT=\$223!
-I2CMM_DIR=\$225!
-I2CMM_REN=\$227!
-I2CMM_SEL=\$22B! SEL0
-I2CMM_VEC=\$FFDA! UCB1
-MMSCL=8! P4.3
-MMSDA=\$10! P4.4
-MM_BUS=\$18!
-
-!hardware I2C_Master
-I2CM_IN=\$221!
-I2CM_OUT=\$223!
-I2CM_DIR=\$225!
-I2CM_REN=\$227!
-I2CM_SEL=\$22B! SEL0
-I2CM_VEC=\$FFDA! UCB1
-MSCL=8! P4.3
-MSDA=\$10! P4.4
-M_BUS=\$18!
-
-!hardware I2C_Slave
-I2CS_IN=\$221!
-I2CS_OUT=\$223!
-I2CS_DIR=\$225!
-I2CS_REN=\$227!
-I2CS_SEL=\$22B! SEL0
-I2CS_VEC=\$FFDA! UCB1
-SSCL=8! P4.3
-SSDA=\$10! P4.4
-S_BUS=\$18!
-
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
-
-I2CM_CTLW0=\$580! USCI_B1 Control Word Register 0
-I2CM_CTLW1=\$582! USCI_B1 Control Word Register 1
-I2CM_BRW=\$586! USCI_B1 Baud Word Rate 0
-I2CM_STATW=\$588! USCI_B1 status word
-I2CM_TBCNT=\$58A! USCI_B1 byte counter threshold
-I2CM_RXBUF=\$58C! USCI_B1 Receive Buffer 8
-I2CM_TXBUF=\$58E! USCI_B1 Transmit Buffer 8
-I2CM_I2COA0=\$594! USCI_B1 I2C Own Address 0
-I2CM_ADDRX=\$59C! USCI_B1 Received Address Register
-I2CM_I2CSA=\$5A0! USCI_B1 I2C Slave Address
-I2CM_IE=\$5AA! USCI_B1 Interrupt Enable
-I2CM_IFG=\$5AC! USCI_B1 Interrupt Flags Register
-
-I2CS_CTLW0=\$580! USCI_B1 Control Word Register 0
-I2CS_CTLW1=\$582! USCI_B1 Control Word Register 1
-I2CS_BRW=\$586! USCI_B1 Baud Word Rate 0
-I2CS_STATW=\$588! USCI_B1 status word
-I2CS_TBCNT=\$58A! USCI_B1 byte counter threshold
-I2CS_RXBUF=\$58C! USCI_B1 Receive Buffer 8
-I2CS_TXBUF=\$58E! USCI_B1 Transmit Buffer 8
-I2CS_I2COA0=\$594! USCI_B1 I2C Own Address 0
-I2CS_ADDRX=\$59C! USCI_B1 Received Address Register
-I2CS_I2CSA=\$5A0! USCI_B1 I2C Slave Address
-I2CS_IE=\$5AA! USCI_B1 Interrupt Enable
-I2CS_IFG=\$5AC! USCI_B1 Interrupt Flags Register
+LCD_RS=1; P5.0
+LCD_RW=2; P5.1
+LCD_EN=4; P5.2
+LCD_CMD=\$32;
+;LCD data bus
+LCD_DB_IN=\$200; P1
+LCD_DB_OUT=\$202;
+LCD_DB_DIR=\$204;
+LCD_DB_REN=\$206;
+LCD_DB=\$0F; P1.3210
+;LCD timer
+LCD_TIM_CTL=\$480; TB0CTL
+LCD_TIM_CCTLn=\$484; TB0CCTL1
+LCD_TIM_CCR0=\$492; TB0CCR0
+LCD_TIM_CCRn=\$494; TB0CCR1
+LCD_TIM_EX0=\$4A0; TB0EX0
+;WATCHDOG timer
+WDT_TIM_CTL=\$380; TA0CTL
+WDT_TIM_CCTL0=\$382; TA0CCTL0
+WDT_TIM_CCR0=\$392; TA0CCR0
+WDT_TIM_EX0=\$3A0; TA0EX0
+WDT_TIM_0_VEC=\$FFF8; TA0_0_VEC
+;IR_RC5
+RC5_=RC5_;
+IR_IN=\$201;
+IR_OUT=\$203;
+IR_DIR=\$205;
+IR_REN=\$209;
+IR_IES=\$219;
+IR_IE=\$21B;
+IR_IFG=\$21D;
+IR_VEC=\$FFD4; P2 int
+RC5=4; P2.2
+;IR_RC5 timer
+RC5_TIM_CTL=\$3C0; TA1CTL
+RC5_TIM_R=\$3D0; TA1R
+RC5_TIM_EX0=\$3E0; TA1EX0
+; --------------------------------------------
+
+;Software I2C_Multi_Master
+I2CSMM_IN=\$220;
+I2CSMM_OUT=\$222;
+I2CSMM_DIR=\$224;
+I2CSMM_REN=\$226;
+SMMSDA=4; P3.2
+SMMSCL=8; P3.3
+SMM_BUS=\$0C;
+
+;hardware I2C_Multi_Master
+I2CMM_IN=\$221;
+I2CMM_OUT=\$223;
+I2CMM_DIR=\$225;
+I2CMM_REN=\$227;
+I2CMM_SEL=\$22B; SEL0
+I2CMM_VEC=\$FFDA; UCB1
+MMSCL=8; P4.3
+MMSDA=\$10; P4.4
+MM_BUS=\$18;
+
+;hardware I2C_Master
+I2CM_IN=\$221;
+I2CM_OUT=\$223;
+I2CM_DIR=\$225;
+I2CM_REN=\$227;
+I2CM_SEL=\$22B; SEL0
+I2CM_VEC=\$FFDA; UCB1
+MSCL=8; P4.3
+MSDA=\$10; P4.4
+M_BUS=\$18;
+
+;hardware I2C_Slave
+I2CS_IN=\$221;
+I2CS_OUT=\$223;
+I2CS_DIR=\$225;
+I2CS_REN=\$227;
+I2CS_SEL=\$22B; SEL0
+I2CS_VEC=\$FFDA; UCB1
+SSCL=8; P4.3
+SSDA=\$10; P4.4
+S_BUS=\$18;
+
+I2CM_CTLW0=\$580; USCI_B1 Control Word Register 0
+I2CM_CTLW1=\$582; USCI_B1 Control Word Register 1
+I2CM_BRW=\$586; USCI_B1 Baud Word Rate 0
+I2CM_STATW=\$588; USCI_B1 status word
+I2CM_TBCNT=\$58A; USCI_B1 byte counter threshold
+I2CM_RXBUF=\$58C; USCI_B1 Receive Buffer 8
+I2CM_TXBUF=\$58E; USCI_B1 Transmit Buffer 8
+I2CM_I2COA0=\$594; USCI_B1 I2C Own Address 0
+I2CM_ADDRX=\$59C; USCI_B1 Received Address Register
+I2CM_I2CSA=\$5A0; USCI_B1 I2C Slave Address
+I2CM_IE=\$5AA; USCI_B1 Interrupt Enable
+I2CM_IFG=\$5AC; USCI_B1 Interrupt Flags Register
+
+I2CS_CTLW0=\$580; USCI_B1 Control Word Register 0
+I2CS_CTLW1=\$582; USCI_B1 Control Word Register 1
+I2CS_BRW=\$586; USCI_B1 Baud Word Rate 0
+I2CS_STATW=\$588; USCI_B1 status word
+I2CS_TBCNT=\$58A; USCI_B1 byte counter threshold
+I2CS_RXBUF=\$58C; USCI_B1 Receive Buffer 8
+I2CS_TXBUF=\$58E; USCI_B1 Transmit Buffer 8
+I2CS_I2COA0=\$594; USCI_B1 I2C Own Address 0
+I2CS_ADDRX=\$59C; USCI_B1 Received Address Register
+I2CS_I2CSA=\$5A0; USCI_B1 I2C Slave Address
+I2CS_IE=\$5AA; USCI_B1 Interrupt Enable
+I2CS_IFG=\$5AC; USCI_B1 Interrupt Flags Register
DEVICE = "MSP430FR2355"
FR2_FAMILY
-
+HMPY ; hardware
+FLL ; Frequency Locked Loop CLOCK
; ----------------------------------------------
; MSP430FR2355 MEMORY MAP
; ----------------------------------------------
-!MSP430FR2355.pat
-
-! ----------------------------------------------
-! MSP430FR2355 MEMORY MAP
-! ----------------------------------------------
-! 0000-0005 = reserved
-! 0006-001F = tiny RAM
-! 0020-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL1 (2k)
-! 1800-19FF = information memory (FRAM 512 B)
-! 1A00-1A31 = TLV device descriptor info (FRAM 128 B)
-! 1A80-1FFF = unused
-! 2000-2FFF = RAM (4 KB)
-! 2800-7FFF = unused
-! 8000-FF7F = code memory (FRAM 15232 B)
-! FF80-FFFF = interrupt vectors (FRAM 128 B)
-! FFC00-FFFFF = BSL2 (2k)
-! ----------------------------------------------
-! MSP430FR2355 DEVICE ID
-! ----------------------------------------------
-! 1A04 = 0C, 1A05 = 83
-! ----------------------------------------------
-PAGESIZE=512! ; MPU unit
-
-
-! ============================================
-! TINY RAM
-! ============================================
-TINYRAM_ORG=\$6!
-TINYRAM_LEN=\$1A!
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-BSL2=\$FFC00!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO addresses
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-!
-INIT_DOXXX=\$182C! MOV #INIT_DOXXX,X \ te restore DOxxx registers
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-!
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0032!
-DEVICEID=\$1A04!
-!
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$2000!
-RAM_LEN=\$1000!
-!
-! ----------------------------------------------
-! FORTH RAM areas :
-! ----------------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-!
-! ----------------------------------------------
-! FastForth RAM memory map (>= 1k):
-! ----------------------------------------------
-LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT
-LSATCK=\$2000! leave stack, grow up
-PSTACK=\$2080! parameter stack, grow down
-RSTACK=\$20E0! Return stack, grow down
-!
-PAD_I2CADR=\$20E0! RX I2C address
-PAD_I2CCNT=\$20E2! count max
-PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$2138! TX I2C address
-TIB_I2CCNT=\$213A! count of bytes
-TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$2190! base address for HOLDS
-HOLD_BASE=\$21B2! BASE HOLD area, grow down
-!
-HP=\$21B2! HOLD ptr
-LAST_NFA=\$21B4!
-LAST_THREAD=\$21B6!
-LAST_CFA=\$21B8!
-LAST_PSP=\$21BA!
-!
-STATEADR=\$21BC! Interpreter state
-BASEADR=\$21BE!
-CAPS=\$21C0 !
-!
-SOURCE_LEN=\$21C2! len of input stream
-SOURCE_ORG=\$21C4! adr of input stream
-TOIN=\$21C6! >IN
-DP=\$21C8! dictionary ptr
-!
-LASTVOC=\$21CA! keep VOC-LINK
-CURRENT=\$21CC! CURRENT dictionnary ptr
-CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!21E0! 28 RAM bytes free
-! ---------------------------------------
-!
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$21FC!
-SD_BUF_I2CNT=\$21FE!
-SD_BUF=\$2200! \ SD_Card buffer
-SD_BUF_END=\$2400!
-!
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2402!
-BS_FirstSectorL=\$2404!
-BS_FirstSectorH=\$2406!
-OrgFAT1=\$2408!
-FATSize=\$240A!
-OrgFAT2=\$240C!
-OrgRootDir=\$240E!
-OrgClusters=\$2410! Sector of Cluster 0
-SecPerClus=\$2412!
-!
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2414! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2414! CRC:ll word access
-SD_CMD_FRM1=\$2415! ll byte access
-SD_CMD_FRM2=\$2416! LL:hh word access
-SD_CMD_FRM3=\$2417! hh byte access
-SD_CMD_FRM4=\$2418! HH:CMD word access
-SD_CMD_FRM5=\$2419! CMD byte access
-SectorL=\$241A! 2 words
-SectorH=\$241C!
-!
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$241E!
-BufferLen=\$2420!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2422! 16 bits wide (FAT16)
-ClusterH=\$2424! 16 bits wide (FAT16)
-LastFATsector=\$2426! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2428! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$242A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$242C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$242E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2430!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2432! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2434!
-EndOfPath=\$2436!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! SD BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! CIB LEN of previous handle
-HDLW_PrevORG=26! CIB ORG of previous handle
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2438!
-HandleEnd=\$2518!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2518!
-SDIB_I2CCNT=\$251A!
-SDIB_ORG=\$251C!
-
-SD_END=\$2570!
-SD_LEN=\$16E!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$8000! Code space start
-! ----------------------------------------------
-SLEEP=\$8000! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$800A! CODE compiled by LITERAL
-XSQUOTE=\$801E! CODE compiled by S" and S_
-HEREXEC=\$8032! CODE HERE and BEGIN execute address
-MUSMOD=\$803E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$8050! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$8058! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$8082! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$8084! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$8094! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$80A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$80AC! CODE compiled by IF UNTIL
-BRAN=\$80B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$80B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$80B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$80C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$80D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$8108! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$8112! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$8154! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$817E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$8184! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL &SOFT_APP)
-UART_WARM=\$8186! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$8144! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$8146! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$8150! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$8150! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$8152! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$817A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR2355
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW ! reset by -1 SYS and by S1+<reset>
-JTAG_SIG2=\$FF82! if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-BSL_CONF_SIG=\$FF88!
-BSL_CONF=\$FF8A!
-BSL_I2C_ADRE=\$FFA0!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFCE! FFCE-FFFF : 24 vectors + reset
-VECT_LEN=\$32!
-! ----------------------------------------------
-P4_VEC=\$FFCE!
-P3_VEC=\$FFD0!
-P2_VEC=\$FFD2!
-P1_VEC=\$FFD4!
-SAC1SAC3_VEC=\$FFD6!
-SAC0SAC2_VEC=\$FFD8!
-ECOMPX_VEC=\$FFDA!
-ADC12_VEC=\$FFDC!
-EUSCI_B1_VEC=\$FFDE!
-EUSCI_B0_VEC=\$FFE0!
-EUSCI_A1_VEC=\$FFE2!
-EUSCI_A0_VEC=\$FFE4!
-WDT_VEC=\$FFE6!
-RTC_VEC=\$FFE8!
-TB3_X_VEC=\$FFEA!
-TB3_0_VEC=\$FFEC!
-TB2_X_VEC=\$FFEE!
-TB2_0_VEC=\$FFF0!
-TB1_X_VEC=\$FFF2!
-TB1_0_VEC=\$FFF4!
-TB0_X_VEC=\$FFF6!
-TB0_0_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-
-
-! ----------------------------------------------------------------------
-! MSP430FR2355 Peripheral File Map
-! ----------------------------------------------------------------------
-!SFR_SFR .equ 0100h ; Special function
-!PMM_SFR .equ 0120h ; PMM
-!SYS_SFR .equ 0140h ; SYS
-!CS_SFR .equ 0180h ; Clock System
-!FRAM_SFR .equ 01A0h ; FRAM control
-!CRC16_SFR .equ 01C0h
-!WDT_A_SFR .equ 01CCh ; Watchdog
-!PA_SFR .equ 0200h ; PORT1/2
-!PB_SFR .equ 0220h ; PORT3/4
-!PC_SFR .equ 0240h ; PORT5/6
-!RTC_SFR .equ 0300h
-!TB0_SFR .equ 0380h
-!TB1_SFR .equ 03C0h
-!TB2_SFR .equ 0400h
-!TB3_SFR .equ 0440h
-!MPY_SFR .equ 04C0h
-!eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
-!eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
-!eUSCI_A1_SFR .equ 0580h ; eUSCI_A1
-!eUSCI_B1_SFR .equ 05C0h ; eUSCI_B1
-!BACK_MEM_SFR .equ 0660h
-!ICC_SFR .equ 06C0h
-!ADC10_B_SFR .equ 0700h
-!eCOMP0_SFR .equ 08E0h
-!eCOMP1_SFR .equ 0900h
-!SAC0_SFR .equ 0C80h
-!SAC1_SFR .equ 0C90h
-!SAC2_SFR .equ 0CA0h
-!SAC3_SFR .equ 0CB0h
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMCTL1=\$122! \ PMM Control 0
-PMMCTL2=\$124! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-SYSCTL=\$140! \ System control
-SYSBSLC=\$142! \ Bootstrap loader configuration area
-SYSJMBC=\$146! \ JTAG mailbox control
-SYSJMBI0=\$148! \ JTAG mailbox input 0
-SYSJMBI1=\$14A! \ JTAG mailbox input 1
-SYSJMBO0=\$14C! \ JTAG mailbox output 0
-SYSJMBO1=\$14E! \ JTAG mailbox output 1
-SYSUNIV=\$15A! \ User NMI vector generator
-SYSSNIV=\$15C! \ System NMI vector generator
-SYSRSTIV=\$15E! \ Reset vector generator
-SYSCFG0=\$160! \ System configuration 0
-SYSCFG1=\$162! \ System configuration 1
-SYSCFG2=\$164! \ System configuration 2
-SYSCFG3=\$166! \ System configuration 3
-
-CSCTL0=\$180! \ CS control 0
-CSCTL1=\$182! \ CS control 1
-CSCTL2=\$184! \ CS control 2
-CSCTL3=\$186! \ CS control 3
-CSCTL4=\$188! \ CS control 4
-CSCTL5=\$18A! \ CS control 5
-CSCTL6=\$18C! \ CS control 6
-CSCTL7=\$18E! \ CS control 7
-CSCTL8=\$190! \ CS control 8
-
-
-FRCTLCTL0=\$1A0! \ FRAM control 0
-FRCTLCTL0_H=\$1A1! \ FRAM control 0_H: FRAM password byte = $A5
-GCCTL0=\$1A4! \ General control 0
-GCCTL1=\$1A6! \ General control 1
-
-CRC16DI=\$1C0! \ CRC data input
-CRCDIRB=\$1C2! \ CRC data input reverse byte
-CRCINIRES=\$1C4! \ CRC initialization and result
-CRCRESR=\$1C6! \ CRC result reverse byte
-
-WDTCTL=\$1CC! \ WDT control register
-
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-PBIN=\$220!
-PBOUT=\$222!
-PBDIR=\$224!
-PBREN=\$226!
-PBSEL0=\$22A!
-PBSEL1=\$22C!
-PBIES=\$238!
-PBIE=\$23A!
-PBIFG=\$23C!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-P3IV=\$22E!
-P3IES=\$238!
-P3IE=\$23A!
-P3IFG=\$23C!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-P4SEL1=\$22D!
-P4IES=\$239!
-P4IE=\$23B!
-P4IFG=\$23D!
-P4IV=\$23E!
-
-PCIN=\$240!
-PCOUT=\$242!
-PCDIR=\$244!
-PCREN=\$246!
-PCSEL0=\$24A!
-PCSEL1=\$24C!
-
-P5IN=\$240!
-P5OUT=\$242!
-P5DIR=\$244!
-P5REN=\$246!
-P5SEL0=\$24A!
-P5SEL1=\$24C!
-
-P6IN=\$241!
-P6OUT=\$243!
-P6DIR=\$245!
-P6REN=\$247!
-P6SEL0=\$249!
-P6SEL1=\$24B!
-
-
-RTCCTL=\$300! \ RTC control
-RTCIV=\$304! \ RTC interrupt vector word
-RTCMOD=\$308! \ RTC modulo
-RTCCNT=\$30C! \ RTC counter register
-
-
-TBCLR=4!
-TBIFG=1!
-CCIFG=1!
-
-TB0CTL=\$380! \ TB0 control
-TB0CCTL0=\$382! \ Capture/compare control 0
-TB0CCTL1=\$384! \ Capture/compare control 1
-TB0CCTL2=\$386! \ Capture/compare control 2
-TB0R=\$390! \ TB0 counter register
-TB0CCR0=\$392! \ Capture/compare register 0
-TB0CCR1=\$394! \ Capture/compare register 1
-TB0CCR2=\$396! \ Capture/compare register 2
-TB0EX0=\$3A0! \ TB0 expansion register 0
-TB0IV=\$3AE! \ TB0 interrupt vector
-
-TB1CTL=\$3C0! \ TB1 control
-TB1CCTL0=\$3C2! \ Capture/compare control 0
-TB1CCTL1=\$3C4! \ Capture/compare control 1
-TB1CCTL2=\$3C6! \ Capture/compare control 2
-TB1R=\$3D0! \ TB0 counter register
-TB1CCR0=\$3D2! \ Capture/compare register 0
-TB1CCR1=\$3D4! \ Capture/compare register 1
-TB1CCR2=\$3D6! \ Capture/compare register 2
-TB1EX0=\$3E0! \ TB0 expansion register 0
-TB1IV=\$3EE! \ TB0 interrupt vector
-
-TB2CTL=\$400! \ TB2 control
-TB2CCTL0=\$402! \ Capture/compare control 0
-TB2CCTL1=\$404! \ Capture/compare control 1
-TB2CCTL2=\$406! \ Capture/compare control 2
-TB2R=\$410! \ TB0 counter register
-TB2CCR0=\$412! \ Capture/compare register 0
-TB2CCR1=\$414! \ Capture/compare register 1
-TB2CCR2=\$416! \ Capture/compare register 2
-TB2EX0=\$420! \ TB0 expansion register 0
-TB2IV=\$42E! \ TB0 interrupt vector
-
-TB3CTL=\$440! \ TB3 control
-TB3CCTL0=\$442! \ Capture/compare control 0
-TB3CCTL1=\$444! \ Capture/compare control 1
-TB3CCTL2=\$446! \ Capture/compare control 2
-TB3CCTL3=\$448! \ Capture/compare control 3
-TB3CCTL4=\$44A! \ Capture/compare control 4
-TB3CCTL6=\$44C! \ Capture/compare control 5
-TB3CCTL6=\$44E! \ Capture/compare control 6
-TB3R=\$450! \ TB0 counter register
-TB3CCR0=\$452! \ Capture/compare register 0
-TB3CCR1=\$454! \ Capture/compare register 1
-TB3CCR2=\$456! \ Capture/compare register 2
-TB3CCR3=\$456! \ Capture/compare register 3
-TB3CCR4=\$456! \ Capture/compare register 4
-TB3CCR5=\$456! \ Capture/compare register 5
-TB3CCR6=\$456! \ Capture/compare register 6
-TB3EX0=\$460! \ TB0 expansion register 0
-TB3IV=\$46E! \ TB0 interrupt vector
-
-
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-
-
-UCA0CTLW0=\$500! \ eUSCI_A control word 0
-UCA0CTLW1=\$502! \ eUSCI_A control word 1
-UCA0BRW=\$506!
-UCA0BR0=\$506! \ eUSCI_A baud rate 0
-UCA0BR1=\$507! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$508! \ eUSCI_A modulation control
-UCA0STAT=\$50A! \ eUSCI_A status
-UCA0RXBUF=\$50C! \ eUSCI_A receive buffer
-UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$510! \ eUSCI_A LIN control
-UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control
-UCA0IE=\$51A! \ eUSCI_A interrupt enable
-UCA0IFG=\$51C! \ eUSCI_A interrupt flags
-UCA0IV=\$51E! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$580! \ eUSCI_A control word 0
-UCA1CTLW1=\$582! \ eUSCI_A control word 1
-UCA1BRW=\$586!
-UCA1BR0=\$586! \ eUSCI_A baud rate 0
-UCA1BR1=\$587! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$588! \ eUSCI_A modulation control
-UCA1STAT=\$58A! \ eUSCI_A status
-UCA1RXBUF=\$58C! \ eUSCI_A receive buffer
-UCA1TXBUF=\$58E! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$590! \ eUSCI_A LIN control
-UCA1IRTCTL=\$592! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$593! \ eUSCI_A IrDA receive control
-UCA1IE=\$59A! \ eUSCI_A interrupt enable
-UCA1IFG=\$59C! \ eUSCI_A interrupt flags
-UCA1IV=\$59E! \ eUSCI_A interrupt vector word
-
-
-UCB0CTLW0=\$540! \ eUSCI_B control word 0
-UCB0CTLW1=\$542! \ eUSCI_B control word 1
-UCB0BRW=\$546!
-UCB0BR0=\$546! \ eUSCI_B bit rate 0
-UCB0BR1=\$547! \ eUSCI_B bit rate 1
-UCB0STATW=\$548! \ eUSCI_B status word
-UCBCNT0=\$549! \ eUSCI_B hardware count
-UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$54C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$55C! \ eUSCI_B received address
-UCB0ADDMASK=\$55E! \ eUSCI_B address mask
-UCB0I2CSA=\$560! \ eUSCI I2C slave address
-UCB0IE=\$56A! \ eUSCI interrupt enable
-UCB0IFG=\$56C! \ eUSCI interrupt flags
-UCB0IV=\$56E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-UCB1CTLW0=\$5C0! \ eUSCI_B control word 0
-UCB1CTLW1=\$5C2! \ eUSCI_B control word 1
-UCB1BRW=\$5C6!
-UCB1BR0=\$5C6! \ eUSCI_B bit rate 0
-UCB1BR1=\$5C7! \ eUSCI_B bit rate 1
-UCB1STATW=\$5C8! \ eUSCI_B status word
-UCB1NT0=\$5C9! \ eUSCI_B hardware count
-UCB1TBCNT=\$5CA! \ eUSCI_B byte counter threshold
-UCB1RXBUF=\$5CC! \ eUSCI_B receive buffer
-UCB1TXBUF=\$5CE! \ eUSCI_B transmit buffer
-UCB1I2COA0=\$5D4! \ eUSCI_B I2C own address 0
-UCB1I2COA1=\$5D6! \ eUSCI_B I2C own address 1
-UCB1I2COA2=\$5D8! \ eUSCI_B I2C own address 2
-UCB1I2COA3=\$5DA! \ eUSCI_B I2C own address 3
-UCB1ADDRX=\$5DC! \ eUSCI_B received address
-UCB1ADDMASK=\$5DE! \ eUSCI_B address mask
-UCB1I2CSA=\$5E0! \ eUSCI I2C slave address
-UCB1IE=\$5EA! \ eUSCI interrupt enable
-UCB1IFG=\$5EC! \ eUSCI interrupt flags
-UCB1IV=\$5EE! \ eUSCI interrupt vector word
-
-BAKMEM0=\$660! \ Backup Memory 0
-BAKMEM1=\$662! \ Backup Memory 1
-BAKMEM2=\$664! \ Backup Memory 2
-BAKMEM3=\$666! \ Backup Memory 3
-BAKMEM4=\$668! \ Backup Memory 4
-BAKMEM5=\$66A! \ Backup Memory 5
-BAKMEM6=\$66C! \ Backup Memory 6
-BAKMEM7=\$66E! \ Backup Memory 7
-BAKMEM8=\$670! \ Backup Memory 8
-BAKMEM9=\$672! \ Backup Memory 9
-BAKMEM10=\$674! \ Backup Memory 10
-BAKMEM11=\$676! \ Backup Memory 11
-BAKMEM12=\$678! \ Backup Memory 12
-BAKMEM13=\$67A! \ Backup Memory 13
-BAKMEM14=\$67C! \ Backup Memory 14
-BAKMEM15=\$67E! \ Backup Memory 15
-
-ICCSC=\$6C00! \ Interrupt Compare Controller Status and Control Register
-ICCMVS=\$6C02! \ Interrupt Compare Controller Mask Virtual Stack Register
-ICCILSR0=\$6C04! \ Interrupt Compare Controller Interrupt Level Setting Register 0
-ICCILSR1=\$6C06! \ Interrupt Compare Controller Interrupt Level Setting Register 1
-ICCILSR2=\$6C08! \ Interrupt Compare Controller Interrupt Level Setting Register 2
-ICCILSR3=\$6C0A! \ Interrupt Compare Controller Interrupt Level Setting Register 3
-ICCILSR4=\$6C0C! \ Interrupt Compare Controller Interrupt Level Setting Register 4
-ICCILSR5=\$6C0E! \ Interrupt Compare Controller Interrupt Level Setting Register 5
-ICCILSR6=\$6C10! \ Interrupt Compare Controller Interrupt Level Setting Register 6
-ICCILSR7=\$6C12! \ Interrupt Compare Controller Interrupt Level Setting Register 7
-
-
-
-ADC12CTL0=\$700! \ ADC12_B Control register 0
-ADC12CTL1=\$702! \ ADC12_B Control register 1
-ADC12CTL2=\$704! \ ADC12_B Control register 2
-ADC12LO=\$706! \ ADC12_B Window Comparator Low Threshold
-ADC12HI=\$708! \ ADC12_B Window Comparator High Threshold
-ADC12MCTL0=\$70A! \ ADC12_B Memory Control Register 0
-ADC12MEM0=\$712! \ ADC12_B Conversion Memory Register
-ADC12IE=\$71A! \ ADC12_B Interrupt Enable
-ADC12IFG=\$71C! \ ADC12_B Interrupt Flags
-ADC12IV=\$71E! \ ADC12_B Interrupt Vector Word
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-
-
-CP0CTL0=\$8E0! \ Comparator control 0
-CP0CTL1=\$8E2! \ Comparator control 1
-CP0INT=\$8E6! \ Comparator interrupt
-CP0IV=\$8E8! \ Comparator interrupt vector
-CP0DACCTL=\$8EA! \ Comparator built-in DAC control
-CP0DACDATA=\$8EC! \ Comparator built-in DAC data
-
-CP1CTL0=\$900! \ Comparator control 0
-CP1CTL1=\$902! \ Comparator control 1
-CP1INT=\$906! \ Comparator interrupt
-CP1IV=\$908! \ Comparator interrupt vector
-CP1DACCTL=\$90A! \ Comparator built-in DAC control
-CP1DACDATA=\$90C! \ Comparator built-in DAC data
-
-SAC0OA=\$0C80! SAC0 OA control
-SAC0PGA=\$0C82! SAC0 PGA control
-SAC0DAC=\$0C84! SAC0 DAC control
-SAC0DAT=\$0C86! SAC0 DAC data
-SAC0DATSTS=\$0C88! SAC0 DAC status
-SAC0IV=\$0C8A! SAC0 interrupt vector
-
-SAC1OA=\$0C90! SAC1 OA control
-SAC1PGA=\$0C92! SAC1 PGA control
-SAC1DAC=\$0C94! SAC1 DAC control
-SAC1DAT=\$0C96! SAC1 DAC data
-SAC1DATSTS=\$0C98! SAC1 DAC status
-SAC1IV=\$0C9A! SAC1 interrupt vector
-
-SAC2OA=\$0CA0! SAC2 OA control
-SAC2PGA=\$0CA2! SAC2 PGA control
-SAC2DAC=\$0CA4! SAC2 DAC control
-SAC2DAT=\$0CA6! SAC2 DAC data
-SAC2DATSTS=\$0CA8! SAC2 DAC status
-SAC2IV=\$0CAA! SAC2 interrupt vector
-
-SAC3OA=\$0CB0! SAC3 OA control
-SAC3PGA=\$0CB2! SAC3 PGA control
-SAC3DAC=\$0CB4! SAC3 DAC control
-SAC3DAT=\$0CB6! SAC3 DAC data
-SAC3DATSTS=\$0CB8! SAC3 DAC status
-SAC3IV=\$0CBA! SAC3 interrupt vector
+
+@set-syntax{C;\;}! tell GEMA to replace default Comment separator '!' by ';'
+; ========================
+;MSP430FR2355.pat
+; ========================
+; ----------------------------------------------
+; MSP430FR2355 MEMORY MAP
+; ----------------------------------------------
+; 0000-0005 = reserved
+; 0006-001F = tiny RAM
+; 0020-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL1 (2k)
+; 1800-19FF = information memory (FRAM 512 B)
+; 1A00-1A31 = TLV device descriptor info (FRAM 128 B)
+; 1A80-1FFF = unused
+; 2000-2FFF = RAM (4 KB)
+; 2800-7FFF = unused
+; 8000-FF7F = code memory (FRAM 15232 B)
+; FF80-FFFF = interrupt vectors (FRAM 128 B)
+; FFC00-FFFFF = BSL2 (2k)
+; ----------------------------------------------
+; MSP430FR2355 DEVICE ID
+; ----------------------------------------------
+; 1A04 = 0C, 1A05 = 83
+; ----------------------------------------------
+;PAGESIZE=512; ; MPU unit
+
+; ============================================
+; TINY RAM
+; ============================================
+TINYRAM_ORG=\$6;
+TINYRAM_LEN=\$1A;
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+BSL2=\$FFC00;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM area cleared by any PUC event
+; ============================================
+RAM_ORG=\$2000;
+RAM_LEN=\$1000;
+;
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FR2xxx.pat
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$8000; Code space start
+; ----------------------------------------------
+\#LIT=\#\$8000; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$8014; asm CODE run time of QUOTE
+\#MUSMOD=\#\$8028; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$803A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$8042; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$806C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$806E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$807E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$808A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$8096; CODE compiled by IF UNTIL
+\#BRAN=\#\$809C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$809E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$80A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$80AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$80BA;
+\#ABORT_TERM=\#\$8100; CALL to discard pending download
+\#UART_WARM=\#\$8172; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$815C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for defined addresses from FORTH definitions
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR2355
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW ; reset by -1 SYS and by S1+<reset>
+JTAG_SIG2=\$FF82; if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+BSL_CONF_SIG=\$FF88;
+BSL_CONF=\$FF8A;
+BSL_I2C_ADRE=\$FFA0;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFCE; FFCE-FFFF : 24 vectors + reset
+VECT_LEN=\$32;
+; ----------------------------------------------
+P4_VEC=\$FFCE;
+P3_VEC=\$FFD0;
+P2_VEC=\$FFD2;
+P1_VEC=\$FFD4;
+SAC1SAC3_VEC=\$FFD6;
+SAC0SAC2_VEC=\$FFD8;
+ECOMPX_VEC=\$FFDA;
+ADC12_VEC=\$FFDC;
+EUSCI_B1_VEC=\$FFDE;
+EUSCI_B0_VEC=\$FFE0;
+EUSCI_A1_VEC=\$FFE2;
+EUSCI_A0_VEC=\$FFE4;
+WDT_VEC=\$FFE6;
+RTC_VEC=\$FFE8;
+TB3_X_VEC=\$FFEA;
+TB3_0_VEC=\$FFEC;
+TB2_X_VEC=\$FFEE;
+TB2_0_VEC=\$FFF0;
+TB1_X_VEC=\$FFF2;
+TB1_0_VEC=\$FFF4;
+TB0_X_VEC=\$FFF6;
+TB0_0_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+
+
+; ----------------------------------------------------------------------
+; MSP430FR2355 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;SYS_SFR .equ 0140h ; SYS
+;CS_SFR .equ 0180h ; Clock System
+;FRAM_SFR .equ 01A0h ; FRAM control
+;CRC16_SFR .equ 01C0h
+;WDT_A_SFR .equ 01CCh ; Watchdog
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3/4
+;PC_SFR .equ 0240h ; PORT5/6
+;RTC_SFR .equ 0300h
+;TB0_SFR .equ 0380h
+;TB1_SFR .equ 03C0h
+;TB2_SFR .equ 0400h
+;TB3_SFR .equ 0440h
+;MPY_SFR .equ 04C0h
+;eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
+;eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
+;eUSCI_A1_SFR .equ 0580h ; eUSCI_A1
+;eUSCI_B1_SFR .equ 05C0h ; eUSCI_B1
+;BACK_MEM_SFR .equ 0660h
+;ICC_SFR .equ 06C0h
+;ADC10_B_SFR .equ 0700h
+;eCOMP0_SFR .equ 08E0h
+;eCOMP1_SFR .equ 0900h
+;SAC0_SFR .equ 0C80h
+;SAC1_SFR .equ 0C90h
+;SAC2_SFR .equ 0CA0h
+;SAC3_SFR .equ 0CB0h
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMCTL1=\$122; \ PMM Control 0
+PMMCTL2=\$124; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+SYSCTL=\$140; \ System control
+SYSBSLC=\$142; \ Bootstrap loader configuration area
+SYSJMBC=\$146; \ JTAG mailbox control
+SYSJMBI0=\$148; \ JTAG mailbox input 0
+SYSJMBI1=\$14A; \ JTAG mailbox input 1
+SYSJMBO0=\$14C; \ JTAG mailbox output 0
+SYSJMBO1=\$14E; \ JTAG mailbox output 1
+SYSUNIV=\$15A; \ User NMI vector generator
+SYSSNIV=\$15C; \ System NMI vector generator
+SYSRSTIV=\$15E; \ Reset vector generator
+SYSCFG0=\$160; \ System configuration 0
+SYSCFG1=\$162; \ System configuration 1
+SYSCFG2=\$164; \ System configuration 2
+SYSCFG3=\$166; \ System configuration 3
+
+CSCTL0=\$180; \ CS control 0
+CSCTL1=\$182; \ CS control 1
+CSCTL2=\$184; \ CS control 2
+CSCTL3=\$186; \ CS control 3
+CSCTL4=\$188; \ CS control 4
+CSCTL5=\$18A; \ CS control 5
+CSCTL6=\$18C; \ CS control 6
+CSCTL7=\$18E; \ CS control 7
+CSCTL8=\$190; \ CS control 8
+
+
+FRCTLCTL0=\$1A0; \ FRAM control 0
+FRCTLCTL0_H=\$1A1; \ FRAM control 0_H: FRAM password byte = $A5
+GCCTL0=\$1A4; \ General control 0
+GCCTL1=\$1A6; \ General control 1
+
+CRC16DI=\$1C0; \ CRC data input
+CRCDIRB=\$1C2; \ CRC data input reverse byte
+CRCINIRES=\$1C4; \ CRC initialization and result
+CRCRESR=\$1C6; \ CRC result reverse byte
+
+WDTCTL=\$1CC; \ WDT control register
+
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+PBIN=\$220;
+PBOUT=\$222;
+PBDIR=\$224;
+PBREN=\$226;
+PBSEL0=\$22A;
+PBSEL1=\$22C;
+PBIES=\$238;
+PBIE=\$23A;
+PBIFG=\$23C;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+P3IV=\$22E;
+P3IES=\$238;
+P3IE=\$23A;
+P3IFG=\$23C;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+P4SEL1=\$22D;
+P4IES=\$239;
+P4IE=\$23B;
+P4IFG=\$23D;
+P4IV=\$23E;
+
+PCIN=\$240;
+PCOUT=\$242;
+PCDIR=\$244;
+PCREN=\$246;
+PCSEL0=\$24A;
+PCSEL1=\$24C;
+
+P5IN=\$240;
+P5OUT=\$242;
+P5DIR=\$244;
+P5REN=\$246;
+P5SEL0=\$24A;
+P5SEL1=\$24C;
+
+P6IN=\$241;
+P6OUT=\$243;
+P6DIR=\$245;
+P6REN=\$247;
+P6SEL0=\$249;
+P6SEL1=\$24B;
+
+
+RTCCTL=\$300; \ RTC control
+RTCIV=\$304; \ RTC interrupt vector word
+RTCMOD=\$308; \ RTC modulo
+RTCCNT=\$30C; \ RTC counter register
+
+
+TBCLR=4;
+TBIFG=1;
+CCIFG=1;
+
+TB0CTL=\$380; \ TB0 control
+TB0CCTL0=\$382; \ Capture/compare control 0
+TB0CCTL1=\$384; \ Capture/compare control 1
+TB0CCTL2=\$386; \ Capture/compare control 2
+TB0R=\$390; \ TB0 counter register
+TB0CCR0=\$392; \ Capture/compare register 0
+TB0CCR1=\$394; \ Capture/compare register 1
+TB0CCR2=\$396; \ Capture/compare register 2
+TB0EX0=\$3A0; \ TB0 expansion register 0
+TB0IV=\$3AE; \ TB0 interrupt vector
+
+TB1CTL=\$3C0; \ TB1 control
+TB1CCTL0=\$3C2; \ Capture/compare control 0
+TB1CCTL1=\$3C4; \ Capture/compare control 1
+TB1CCTL2=\$3C6; \ Capture/compare control 2
+TB1R=\$3D0; \ TB0 counter register
+TB1CCR0=\$3D2; \ Capture/compare register 0
+TB1CCR1=\$3D4; \ Capture/compare register 1
+TB1CCR2=\$3D6; \ Capture/compare register 2
+TB1EX0=\$3E0; \ TB0 expansion register 0
+TB1IV=\$3EE; \ TB0 interrupt vector
+
+TB2CTL=\$400; \ TB2 control
+TB2CCTL0=\$402; \ Capture/compare control 0
+TB2CCTL1=\$404; \ Capture/compare control 1
+TB2CCTL2=\$406; \ Capture/compare control 2
+TB2R=\$410; \ TB0 counter register
+TB2CCR0=\$412; \ Capture/compare register 0
+TB2CCR1=\$414; \ Capture/compare register 1
+TB2CCR2=\$416; \ Capture/compare register 2
+TB2EX0=\$420; \ TB0 expansion register 0
+TB2IV=\$42E; \ TB0 interrupt vector
+
+TB3CTL=\$440; \ TB3 control
+TB3CCTL0=\$442; \ Capture/compare control 0
+TB3CCTL1=\$444; \ Capture/compare control 1
+TB3CCTL2=\$446; \ Capture/compare control 2
+TB3CCTL3=\$448; \ Capture/compare control 3
+TB3CCTL4=\$44A; \ Capture/compare control 4
+TB3CCTL6=\$44C; \ Capture/compare control 5
+TB3CCTL6=\$44E; \ Capture/compare control 6
+TB3R=\$450; \ TB0 counter register
+TB3CCR0=\$452; \ Capture/compare register 0
+TB3CCR1=\$454; \ Capture/compare register 1
+TB3CCR2=\$456; \ Capture/compare register 2
+TB3CCR3=\$456; \ Capture/compare register 3
+TB3CCR4=\$456; \ Capture/compare register 4
+TB3CCR5=\$456; \ Capture/compare register 5
+TB3CCR6=\$456; \ Capture/compare register 6
+TB3EX0=\$460; \ TB0 expansion register 0
+TB3IV=\$46E; \ TB0 interrupt vector
+
+
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+
+
+UCA0CTLW0=\$500; \ eUSCI_A control word 0
+UCA0CTLW1=\$502; \ eUSCI_A control word 1
+UCA0BRW=\$506;
+UCA0BR0=\$506; \ eUSCI_A baud rate 0
+UCA0BR1=\$507; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$508; \ eUSCI_A modulation control
+UCA0STAT=\$50A; \ eUSCI_A status
+UCA0RXBUF=\$50C; \ eUSCI_A receive buffer
+UCA0TXBUF=\$50E; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$510; \ eUSCI_A LIN control
+UCA0IRTCTL=\$512; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$513; \ eUSCI_A IrDA receive control
+UCA0IE=\$51A; \ eUSCI_A interrupt enable
+UCA0IFG=\$51C; \ eUSCI_A interrupt flags
+UCA0IV=\$51E; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$580; \ eUSCI_A control word 0
+UCA1CTLW1=\$582; \ eUSCI_A control word 1
+UCA1BRW=\$586;
+UCA1BR0=\$586; \ eUSCI_A baud rate 0
+UCA1BR1=\$587; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$588; \ eUSCI_A modulation control
+UCA1STAT=\$58A; \ eUSCI_A status
+UCA1RXBUF=\$58C; \ eUSCI_A receive buffer
+UCA1TXBUF=\$58E; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$590; \ eUSCI_A LIN control
+UCA1IRTCTL=\$592; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$593; \ eUSCI_A IrDA receive control
+UCA1IE=\$59A; \ eUSCI_A interrupt enable
+UCA1IFG=\$59C; \ eUSCI_A interrupt flags
+UCA1IV=\$59E; \ eUSCI_A interrupt vector word
+
+
+UCB0CTLW0=\$540; \ eUSCI_B control word 0
+UCB0CTLW1=\$542; \ eUSCI_B control word 1
+UCB0BRW=\$546;
+UCB0BR0=\$546; \ eUSCI_B bit rate 0
+UCB0BR1=\$547; \ eUSCI_B bit rate 1
+UCB0STATW=\$548; \ eUSCI_B status word
+UCBCNT0=\$549; \ eUSCI_B hardware count
+UCB0TBCNT=\$54A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$54C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$54E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$554; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$556; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$558; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$55A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$55C; \ eUSCI_B received address
+UCB0ADDMASK=\$55E; \ eUSCI_B address mask
+UCB0I2CSA=\$560; \ eUSCI I2C slave address
+UCB0IE=\$56A; \ eUSCI interrupt enable
+UCB0IFG=\$56C; \ eUSCI interrupt flags
+UCB0IV=\$56E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+UCB1CTLW0=\$5C0; \ eUSCI_B control word 0
+UCB1CTLW1=\$5C2; \ eUSCI_B control word 1
+UCB1BRW=\$5C6;
+UCB1BR0=\$5C6; \ eUSCI_B bit rate 0
+UCB1BR1=\$5C7; \ eUSCI_B bit rate 1
+UCB1STATW=\$5C8; \ eUSCI_B status word
+UCB1NT0=\$5C9; \ eUSCI_B hardware count
+UCB1TBCNT=\$5CA; \ eUSCI_B byte counter threshold
+UCB1RXBUF=\$5CC; \ eUSCI_B receive buffer
+UCB1TXBUF=\$5CE; \ eUSCI_B transmit buffer
+UCB1I2COA0=\$5D4; \ eUSCI_B I2C own address 0
+UCB1I2COA1=\$5D6; \ eUSCI_B I2C own address 1
+UCB1I2COA2=\$5D8; \ eUSCI_B I2C own address 2
+UCB1I2COA3=\$5DA; \ eUSCI_B I2C own address 3
+UCB1ADDRX=\$5DC; \ eUSCI_B received address
+UCB1ADDMASK=\$5DE; \ eUSCI_B address mask
+UCB1I2CSA=\$5E0; \ eUSCI I2C slave address
+UCB1IE=\$5EA; \ eUSCI interrupt enable
+UCB1IFG=\$5EC; \ eUSCI interrupt flags
+UCB1IV=\$5EE; \ eUSCI interrupt vector word
+
+BAKMEM0=\$660; \ Backup Memory 0
+BAKMEM1=\$662; \ Backup Memory 1
+BAKMEM2=\$664; \ Backup Memory 2
+BAKMEM3=\$666; \ Backup Memory 3
+BAKMEM4=\$668; \ Backup Memory 4
+BAKMEM5=\$66A; \ Backup Memory 5
+BAKMEM6=\$66C; \ Backup Memory 6
+BAKMEM7=\$66E; \ Backup Memory 7
+BAKMEM8=\$670; \ Backup Memory 8
+BAKMEM9=\$672; \ Backup Memory 9
+BAKMEM10=\$674; \ Backup Memory 10
+BAKMEM11=\$676; \ Backup Memory 11
+BAKMEM12=\$678; \ Backup Memory 12
+BAKMEM13=\$67A; \ Backup Memory 13
+BAKMEM14=\$67C; \ Backup Memory 14
+BAKMEM15=\$67E; \ Backup Memory 15
+
+ICCSC=\$6C00; \ Interrupt Compare Controller Status and Control Register
+ICCMVS=\$6C02; \ Interrupt Compare Controller Mask Virtual Stack Register
+ICCILSR0=\$6C04; \ Interrupt Compare Controller Interrupt Level Setting Register 0
+ICCILSR1=\$6C06; \ Interrupt Compare Controller Interrupt Level Setting Register 1
+ICCILSR2=\$6C08; \ Interrupt Compare Controller Interrupt Level Setting Register 2
+ICCILSR3=\$6C0A; \ Interrupt Compare Controller Interrupt Level Setting Register 3
+ICCILSR4=\$6C0C; \ Interrupt Compare Controller Interrupt Level Setting Register 4
+ICCILSR5=\$6C0E; \ Interrupt Compare Controller Interrupt Level Setting Register 5
+ICCILSR6=\$6C10; \ Interrupt Compare Controller Interrupt Level Setting Register 6
+ICCILSR7=\$6C12; \ Interrupt Compare Controller Interrupt Level Setting Register 7
+
+
+
+ADC12CTL0=\$700; \ ADC12_B Control register 0
+ADC12CTL1=\$702; \ ADC12_B Control register 1
+ADC12CTL2=\$704; \ ADC12_B Control register 2
+ADC12LO=\$706; \ ADC12_B Window Comparator Low Threshold
+ADC12HI=\$708; \ ADC12_B Window Comparator High Threshold
+ADC12MCTL0=\$70A; \ ADC12_B Memory Control Register 0
+ADC12MEM0=\$712; \ ADC12_B Conversion Memory Register
+ADC12IE=\$71A; \ ADC12_B Interrupt Enable
+ADC12IFG=\$71C; \ ADC12_B Interrupt Flags
+ADC12IV=\$71E; \ ADC12_B Interrupt Vector Word
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CP0CTL0=\$8E0; \ Comparator control 0
+CP0CTL1=\$8E2; \ Comparator control 1
+CP0INT=\$8E6; \ Comparator interrupt
+CP0IV=\$8E8; \ Comparator interrupt vector
+CP0DACCTL=\$8EA; \ Comparator built-in DAC control
+CP0DACDATA=\$8EC; \ Comparator built-in DAC data
+
+CP1CTL0=\$900; \ Comparator control 0
+CP1CTL1=\$902; \ Comparator control 1
+CP1INT=\$906; \ Comparator interrupt
+CP1IV=\$908; \ Comparator interrupt vector
+CP1DACCTL=\$90A; \ Comparator built-in DAC control
+CP1DACDATA=\$90C; \ Comparator built-in DAC data
+
+SAC0OA=\$0C80; SAC0 OA control
+SAC0PGA=\$0C82; SAC0 PGA control
+SAC0DAC=\$0C84; SAC0 DAC control
+SAC0DAT=\$0C86; SAC0 DAC data
+SAC0DATSTS=\$0C88; SAC0 DAC status
+SAC0IV=\$0C8A; SAC0 interrupt vector
+
+SAC1OA=\$0C90; SAC1 OA control
+SAC1PGA=\$0C92; SAC1 PGA control
+SAC1DAC=\$0C94; SAC1 DAC control
+SAC1DAT=\$0C96; SAC1 DAC data
+SAC1DATSTS=\$0C98; SAC1 DAC status
+SAC1IV=\$0C9A; SAC1 interrupt vector
+
+SAC2OA=\$0CA0; SAC2 OA control
+SAC2PGA=\$0CA2; SAC2 PGA control
+SAC2DAC=\$0CA4; SAC2 DAC control
+SAC2DAT=\$0CA6; SAC2 DAC data
+SAC2DATSTS=\$0CA8; SAC2 DAC status
+SAC2IV=\$0CAA; SAC2 interrupt vector
+
+SAC3OA=\$0CB0; SAC3 OA control
+SAC3PGA=\$0CB2; SAC3 PGA control
+SAC3DAC=\$0CB4; SAC3 DAC control
+SAC3DAT=\$0CB6; SAC3 DAC data
+SAC3DATSTS=\$0CB8; SAC3 DAC status
+SAC3IV=\$0CBA; SAC3 interrupt vector
DEVICE = "MSP430FR2433"
FR2_FAMILY
-
+HMPY ; hardware multiplier
+FLL ; Frequency Locked Loop CLOCK
; ----------------------------------------------
; MSP430FR2433 MEMORY MAP
; ----------------------------------------------
-!MSP430FR2433.pat
-
-! ----------------------------------------------
-! MSP430FR2433 MEMORY MAP
-! ----------------------------------------------
-! 0000-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL1 (2k)
-! 1800-19FF = info B (FRAM 512 B)
-! 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
-! 2000-2FFF = RAM (4 KB)
-! C400-FF7F = code memory (FRAM 15232 B)
-! FF80-FFFF = interrupt vectors (FRAM 128 B)
-! FFC00-FFFFF = BSL2 (2k)
-! ----------------------------------------------
-!PAGESIZE .equ 512 ; MPU unit
-
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-BSL2=\$FFC00!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG =\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO addresses
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0080!
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$2000!
-RAM_LEN=\$1000!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ---------------------------------------
-! FastForth RAM memory map (>= 1k):
-! ---------------------------------------
-LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT
-LSATCK=\$2000! leave stack, grow up
-PSTACK=\$2080! parameter stack, grow down
-RSTACK=\$20E0! Return stack, grow down
-!
-PAD_I2CADR=\$20E0! RX I2C address
-PAD_I2CCNT=\$20E2! count max
-PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$2138! TX I2C address
-TIB_I2CCNT=\$213A! count of bytes
-TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$2190! base address for HOLDS
-HOLD_BASE=\$21B2! BASE HOLD area, grow down
-!
-HP=\$21B2! HOLD ptr
-LAST_NFA=\$21B4!
-LAST_THREAD=\$21B6!
-LAST_CFA=\$21B8!
-LAST_PSP=\$21BA!
-!
-STATEADR=\$21BC! Interpreter state
-BASEADR=\$21BE!
-CAPS=\$21C0 !
-!
-SOURCE_LEN=\$21C2! len of input stream
-SOURCE_ORG=\$21C4! adr of input stream
-TOIN=\$21C6! >IN
-DP=\$21C8! dictionary ptr
-!
-LASTVOC=\$21CA! keep VOC-LINK
-CURRENT=\$21CC! CURRENT dictionnary ptr
-CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!21E0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$21FC!
-SD_BUF_I2CNT=\$21FE!
-SD_BUF=\$2200! \ SD_Card buffer
-BUFEND=\$2400!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2402!
-BS_FirstSectorL=\$2404!
-BS_FirstSectorH=\$2406!
-OrgFAT1=\$2408!
-FATSize=\$240A!
-OrgFAT2=\$240C!
-OrgRootDir=\$240E!
-OrgClusters=\$2410! Sector of Cluster 0
-SecPerClus=\$2412!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2414! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2414! CRC:ll word access
-SD_CMD_FRM1=\$2415! ll byte access
-SD_CMD_FRM2=\$2416! LL:hh word access
-SD_CMD_FRM3=\$2417! hh byte access
-SD_CMD_FRM4=\$2418! HH:CMD word access
-SD_CMD_FRM5=\$2419! CMD byte access
-SectorL=\$241A! 2 words
-SectorH=\$241C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$241E!
-BufferLen=\$2420!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2422! 16 bits wide (FAT16)
-ClusterH=\$2424! 16 bits wide (FAT16)
-LastFATsector=\$2426! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2428! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$242A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$242C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$242E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2430!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2432! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2434!
-EndOfPath=\$2436!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2438!
-HandleEnd=\$2518!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2518!
-SDIB_I2CCNT=\$251A!
-SDIB_ORG=\$251C!
-
-SD_END=\$2570!
-SD_LEN=\$16E!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$C400! Code space start
-
-SLEEP=\$C400! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$C40A! CODE compiled by LITERAL
-XSQUOTE=\$C41E! CODE compiled by S" and S_
-HEREXEC=\$C432! CODE HERE and BEGIN execute address
-MUSMOD=\$C43E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$C450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$C458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$C482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$C484! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$C494! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$C4A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$C4AC! CODE compiled by IF UNTIL
-BRAN=\$C4B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$C4B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$C4B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$C4C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$C4D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$C508! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$C512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$C554! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$C57E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$C584! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$C586! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$C544! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$C546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$C550! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$C550! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$C552! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$C57A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR2433
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
-JTAG_SIG2=\$FF82! if JTAG_SIG <> |\$FFFFFFFF, \$00000000|, SBW and JTAG are locked
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFDA! FFDA-FFFF
-VECT_LEN=\$26!
-! ----------------------------------------------
-
-P2_VEC=\$FFDA!
-P1_VEC=\$FFDC!
-ADC10_B_VEC=\$FFDE!
-EUSCI_B0_VEC=\$FFE0!
-EUSCI_A1_VEC=\$FFE2!
-EUSCI_A0_VEC=\$FFE4!
-WDT_VEC=\$FFE6!
-RTC_VEC=\$FFE8!
-TA3_X_VEC=\$FFEA!
-TA3_0_VEC=\$FFEC!
-TA2_X_VEC=\$FFEE!
-TA2_0_VEC=\$FFF0!
-TA1_X_VEC=\$FFF2!
-TA1_0_VEC=\$FFF4!
-TA0_X_VEC=\$FFF6!
-TA0_0_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-
-
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-
-
-
-! ----------------------------------------------------------------------
-! MSP430FR2433 Peripheral File Map
-! ----------------------------------------------------------------------
-!SFR_SFR .equ 0100h ; Special function
-!PMM_SFR .equ 0120h ; PMM
-!SYS_SFR .equ 0140h ; SYS
-!CS_SFR .equ 0180h ; Clock System
-!FRAM_SFR .equ 01A0h ; FRAM control
-!CRC16_SFR .equ 01C0h
-!WDT_A_SFR .equ 01CCh ; Watchdog
-!PA_SFR .equ 0200h ; PORT1/2
-!PB_SFR .equ 0220h ; PORT3
-!RTC_SFR .equ 0300h
-!TA0_SFR .equ 0380h
-!TA1_SFR .equ 03C0h
-!TA2_SFR .equ 0400h
-!TA3_SFR .equ 0440h
-!MPY_SFR .equ 04C0h
-!eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
-!eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
-!eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
-!BACK_MEM_SFR .equ 0660h
-!ADC10_B_SFR .equ 0700h
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMCTL1=\$122! \ PMM Control 0
-PMMCTL2=\$124! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-SYSCTL=\$140! \ System control
-SYSBSLC=\$142! \ Bootstrap loader configuration area
-SYSJMBC=\$146! \ JTAG mailbox control
-SYSJMBI0=\$148! \ JTAG mailbox input 0
-SYSJMBI1=\$14A! \ JTAG mailbox input 1
-SYSJMBO0=\$14C! \ JTAG mailbox output 0
-SYSJMBO1=\$14E! \ JTAG mailbox output 1
-SYSUNIV=\$15A! \ User NMI vector generator
-SYSSNIV=\$15C! \ System NMI vector generator
-SYSRSTIV=\$15E! \ Reset vector generator
-SYSCFG0=\$160! \ System configuration 0
-SYSCFG1=\$162! \ System configuration 1
-SYSCFG2=\$164! \ System configuration 2
-
-CSCTL0=\$180! \ CS control 0
-CSCTL1=\$182! \ CS control 1
-CSCTL2=\$184! \ CS control 2
-CSCTL3=\$186! \ CS control 3
-CSCTL4=\$188! \ CS control 4
-CSCTL5=\$18A! \ CS control 5
-CSCTL6=\$18C! \ CS control 6
-CSCTL7=\$18E! \ CS control 7
-CSCTL8=\$190! \ CS control 8
-
-FRCTLCTL0=\$1A0! \ FRAM control 0
-GCCTL0=\$1A4! \ General control 0
-GCCTL1=\$1A6! \ General control 1
-
-CRC16DI=\$1C0! \ CRC data input
-CRCDIRB=\$1C2! \ CRC data input reverse byte
-CRCINIRES=\$1C4! \ CRC initialization and result
-CRCRESR=\$1C6! \ CRC result reverse byte
-
-WDTCTL=\$1CC! \ WDT control register
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-
-RTCCTL=\$300! \ RTC control
-RTCIV=\$304! \ RTC interrupt vector word
-RTCMOD=\$308! \ RTC modulo
-RTCCNT=\$30C! \ RTC counter register
-
-TACLR=4!
-TAIFG=1!
-CCIFG=1!
-
-TA0CTL=\$380! \ TA0 control
-TA0CCTL0=\$382! \ Capture/compare control 0
-TA0CCTL1=\$384! \ Capture/compare control 1
-TA0CCTL2=\$386! \ Capture/compare control 2
-TA0R=\$390! \ TA0 counter register
-TA0CCR0=\$392! \ Capture/compare register 0
-TA0CCR1=\$394! \ Capture/compare register 1
-TA0CCR2=\$396! \ Capture/compare register 2
-TA0EX0=\$3A0! \ TA0 expansion register 0
-TA0IV=\$3AE! \ TA0 interrupt vector
-
-TA1CTL=\$3C0! \ TA1 control
-TA1CCTL0=\$3C2! \ Capture/compare control 0
-TA1CCTL1=\$3C4! \ Capture/compare control 1
-TA1CCTL2=\$3C6! \ Capture/compare control 2
-TA1R=\$3D0! \ TA1 counter register
-TA1CCR0=\$3D2! \ Capture/compare register 0
-TA1CCR1=\$3D4! \ Capture/compare register 1
-TA1CCR2=\$3D6! \ Capture/compare register 2
-TA1EX0=\$3E0! \ TA1 expansion register 0
-TA1IV=\$3EE! \ TA1 interrupt vector
-
-TA2CTL=\$400! \ TA2 control
-TA2CCTL0=\$402! \ Capture/compare control 0
-TA2CCTL1=\$404! \ Capture/compare control 1
-TA2R=\$410! \ TA2 counter register
-TA2CCR0=\$412! \ Capture/compare register 0
-TA2CCR1=\$414! \ Capture/compare register 1
-TA2EX0=\$420! \ TA2 expansion register 0
-TA2IV=\$42E! \ TA2 interrupt vector
-
-TA3CTL=\$440! \ TA3 control
-TA3CCTL0=\$442! \ Capture/compare control 0
-TA3CCTL1=\$444! \ Capture/compare control 1
-TA3R=\$450! \ TA3 counter register
-TA3CCR0=\$452! \ Capture/compare register 0
-TA3CCR1=\$454! \ Capture/compare register 1
-TA3EX0=\$460! \ TA3 expansion register 0
-TA3IV=\$46E! \ TA3 interrupt vector
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-
-UCA0CTLW0=\$500! \ eUSCI_A control word 0
-UCA0CTLW1=\$502! \ eUSCI_A control word 1
-UCA0BRW=\$506!
-UCA0BR0=\$506! \ eUSCI_A baud rate 0
-UCA0BR1=\$507! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$508! \ eUSCI_A modulation control
-UCA0STAT=\$50A! \ eUSCI_A status
-UCA0RXBUF=\$50C! \ eUSCI_A receive buffer
-UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$510! \ eUSCI_A LIN control
-UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control
-UCA0IE=\$51A! \ eUSCI_A interrupt enable
-UCA0IFG=\$51C! \ eUSCI_A interrupt flags
-UCA0IV=\$51E! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$520! \ eUSCI_A control word 0
-UCA1CTLW1=\$522! \ eUSCI_A control word 1
-UCA1BRW=\$526!
-UCA1BR0=\$526! \ eUSCI_A baud rate 0
-UCA1BR1=\$527! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$528! \ eUSCI_A modulation control
-UCA1STAT=\$52A! \ eUSCI_A status
-UCA1RXBUF=\$52C! \ eUSCI_A receive buffer
-UCA1TXBUF=\$52E! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$530! \ eUSCI_A LIN control
-UCA1IRTCTL=\$532! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$533! \ eUSCI_A IrDA receive control
-UCA1IE=\$53A! \ eUSCI_A interrupt enable
-UCA1IFG=\$53C! \ eUSCI_A interrupt flags
-UCA1IV=\$53E! \ eUSCI_A interrupt vector word
-
-UCB0CTLW0=\$540! \ eUSCI_B control word 0
-UCB0CTLW1=\$542! \ eUSCI_B control word 1
-UCB0BRW=\$546!
-UCB0BR0=\$546! \ eUSCI_B bit rate 0
-UCB0BR1=\$547! \ eUSCI_B bit rate 1
-UCB0STATW=\$548! \ eUSCI_B status word
-UCBCNT0=\$549! \ eUSCI_B hardware count
-UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$54C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$55C! \ eUSCI_B received address
-UCB0ADDMASK=\$55E! \ eUSCI_B address mask
-UCB0I2CSA=\$560! \ eUSCI I2C slave address
-UCB0IE=\$56A! \ eUSCI interrupt enable
-UCB0IFG=\$56C! \ eUSCI interrupt flags
-UCB0IV=\$56E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-BAKMEM0=\$660! \ Backup Memory 0
-BAKMEM1=\$662! \ Backup Memory 1
-BAKMEM2=\$664! \ Backup Memory 2
-BAKMEM3=\$666! \ Backup Memory 3
-BAKMEM4=\$668! \ Backup Memory 4
-BAKMEM5=\$66A! \ Backup Memory 5
-BAKMEM6=\$66C! \ Backup Memory 6
-BAKMEM7=\$66E! \ Backup Memory 7
-BAKMEM8=\$670! \ Backup Memory 8
-BAKMEM9=\$672! \ Backup Memory 9
-BAKMEM10=\$674! \ Backup Memory 10
-BAKMEM11=\$676! \ Backup Memory 11
-BAKMEM12=\$678! \ Backup Memory 12
-BAKMEM13=\$67A! \ Backup Memory 13
-BAKMEM14=\$67C! \ Backup Memory 14
-BAKMEM15=\$67E! \ Backup Memory 15
-
-ADC10CTL0=\$700! \ ADC10_B Control register 0
-ADC10CTL1=\$702! \ ADC10_B Control register 1
-ADC10CTL2=\$704! \ ADC10_B Control register 2
-ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold
-ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold
-ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0
-ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register
-ADC10IE=\$71A! \ ADC10_B Interrupt Enable
-ADC10IFG=\$71C! \ ADC10_B Interrupt Flags
-ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word
-
-ADCON=\$10!
-ADCSTART=\$03!
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430FR2433.pat
+
+; ----------------------------------------------
+; MSP430FR2433 MEMORY MAP
+; ----------------------------------------------
+; 0000-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL1 (2k)
+; 1800-19FF = info B (FRAM 512 B)
+; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
+; 2000-2FFF = RAM (4 KB)
+; C400-FF7F = code memory (FRAM 15232 B)
+; FF80-FFFF = interrupt vectors (FRAM 128 B)
+; FFC00-FFFFF = BSL2 (2k)
+; ----------------------------------------------
+;PAGESIZE .equ 512 ; MPU unit
+
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+BSL2=\$FFC00;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG =\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$2000;
+RAM_LEN=\$1000;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ---------------------------------------
+; FastForth RAM memory map (>= 1k):
+; ---------------------------------------
+LEAVEPTR=\$2000; Leave-stack pointer, init by QUIT
+LSATCK=\$2000; leave stack, grow up
+PSTACK=\$2080; parameter stack, grow down
+RSTACK=\$20E0; Return stack, grow down
+;
+PAD_I2CADR=\$20E0; RX I2C address
+PAD_I2CCNT=\$20E2; count max
+PAD_ORG=\$20E4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$2138; TX I2C address
+TIB_I2CCNT=\$213A; count of bytes
+TIB_ORG=\$213C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$2190; base address for HOLDS
+HOLD_BASE=\$21B2; BASE HOLD area, grow down
+;
+HP=\$21B2; HOLD ptr
+STATEADR=\$21B4; Interpreter state
+BASEADR=\$21B6; base
+CAPS=\$21B8; CAPS ON/OFF
+SOURCE_LEN=\$21BA; len of input stream
+SOURCE_ORG=\$21BC; adr of input stream
+TOIN=\$21BE; >IN
+;
+DP=\$21C0; dictionary ptr
+LASTVOC=\$21C2; keep VOC-LINK
+CURRENT=\$21C4; CURRENT dictionnary ptr
+CONTEXT=\$21C6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$21D8;
+LAST_THREAD=\$21DA;
+LAST_CFA=\$21DC;
+LAST_PSP=\$21DE;
+ASMBW1=\$21E0; 3 backward labels
+ASMBW2=\$21E2;
+ASMBW3=\$21E4;
+ASMFW1=\$21E6; 3 forward labels
+ASMFW2=\$21E8;
+ASMFW3=\$21EA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$21FC;
+SD_BUF_I2CNT=\$21FE;
+SD_BUF=\$2200; \ SD_Card buffer
+BUFEND=\$2400;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2402;
+BS_FirstSectorL=\$2404;
+BS_FirstSectorH=\$2406;
+OrgFAT1=\$2408;
+FATSize=\$240A;
+OrgFAT2=\$240C;
+OrgRootDir=\$240E;
+OrgClusters=\$2410; Sector of Cluster 0
+SecPerClus=\$2412;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2414; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2414; CRC:ll word access
+SD_CMD_FRM1=\$2415; ll byte access
+SD_CMD_FRM2=\$2416; LL:hh word access
+SD_CMD_FRM3=\$2417; hh byte access
+SD_CMD_FRM4=\$2418; HH:CMD word access
+SD_CMD_FRM5=\$2419; CMD byte access
+SectorL=\$241A; 2 words
+SectorH=\$241C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$241E;
+BufferLen=\$2420;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2422; 16 bits wide (FAT16)
+ClusterH=\$2424; 16 bits wide (FAT16)
+LastFATsector=\$2426; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2428; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$242A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$242C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$242E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2430;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2432; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2434;
+EndOfPath=\$2436;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2438;
+HandleEnd=\$2518;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2518;
+SDIB_I2CCNT=\$251A;
+SDIB_ORG=\$251C;
+
+SD_END=\$2570;
+SD_LEN=\$16E;
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$C400; Code space start
+; ----------------------------------------------
+\#LIT=\#\$C400; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$C414; asm CODE run time of QUOTE
+\#MUSMOD=\#\$C428; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$C43A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$C442; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$C46C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$C46E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$C47E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$C48A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$C496; CODE compiled by IF UNTIL
+\#BRAN=\#\$C49C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$C49E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$C4A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$C4AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$C4BA;
+\#ABORT_TERM=\#\$C500; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$C572; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$C55C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR2433
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
+JTAG_SIG2=\$FF82; if JTAG_SIG <> $FFFF_FFFF|$0000_0000, SBW and JTAG are locked
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFDA; FFDA-FFFF
+VECT_LEN=\$26;
+; ----------------------------------------------
+
+P2_VEC=\$FFDA;
+P1_VEC=\$FFDC;
+ADC10_B_VEC=\$FFDE;
+EUSCI_B0_VEC=\$FFE0;
+EUSCI_A1_VEC=\$FFE2;
+EUSCI_A0_VEC=\$FFE4;
+WDT_VEC=\$FFE6;
+RTC_VEC=\$FFE8;
+TA3_X_VEC=\$FFEA;
+TA3_0_VEC=\$FFEC;
+TA2_X_VEC=\$FFEE;
+TA2_0_VEC=\$FFF0;
+TA1_X_VEC=\$FFF2;
+TA1_0_VEC=\$FFF4;
+TA0_X_VEC=\$FFF6;
+TA0_0_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+
+
+
+; You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
+; those addresses are usable with the symbolic assembler
+
+
+
+; ----------------------------------------------------------------------
+; MSP430FR2433 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;SYS_SFR .equ 0140h ; SYS
+;CS_SFR .equ 0180h ; Clock System
+;FRAM_SFR .equ 01A0h ; FRAM control
+;CRC16_SFR .equ 01C0h
+;WDT_A_SFR .equ 01CCh ; Watchdog
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3
+;RTC_SFR .equ 0300h
+;TA0_SFR .equ 0380h
+;TA1_SFR .equ 03C0h
+;TA2_SFR .equ 0400h
+;TA3_SFR .equ 0440h
+;MPY_SFR .equ 04C0h
+;eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
+;eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
+;eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
+;BACK_MEM_SFR .equ 0660h
+;ADC10_B_SFR .equ 0700h
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMCTL1=\$122; \ PMM Control 0
+PMMCTL2=\$124; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+SYSCTL=\$140; \ System control
+SYSBSLC=\$142; \ Bootstrap loader configuration area
+SYSJMBC=\$146; \ JTAG mailbox control
+SYSJMBI0=\$148; \ JTAG mailbox input 0
+SYSJMBI1=\$14A; \ JTAG mailbox input 1
+SYSJMBO0=\$14C; \ JTAG mailbox output 0
+SYSJMBO1=\$14E; \ JTAG mailbox output 1
+SYSUNIV=\$15A; \ User NMI vector generator
+SYSSNIV=\$15C; \ System NMI vector generator
+SYSRSTIV=\$15E; \ Reset vector generator
+SYSCFG0=\$160; \ System configuration 0
+SYSCFG1=\$162; \ System configuration 1
+SYSCFG2=\$164; \ System configuration 2
+
+CSCTL0=\$180; \ CS control 0
+CSCTL1=\$182; \ CS control 1
+CSCTL2=\$184; \ CS control 2
+CSCTL3=\$186; \ CS control 3
+CSCTL4=\$188; \ CS control 4
+CSCTL5=\$18A; \ CS control 5
+CSCTL6=\$18C; \ CS control 6
+CSCTL7=\$18E; \ CS control 7
+CSCTL8=\$190; \ CS control 8
+
+FRCTLCTL0=\$1A0; \ FRAM control 0
+GCCTL0=\$1A4; \ General control 0
+GCCTL1=\$1A6; \ General control 1
+
+CRC16DI=\$1C0; \ CRC data input
+CRCDIRB=\$1C2; \ CRC data input reverse byte
+CRCINIRES=\$1C4; \ CRC initialization and result
+CRCRESR=\$1C6; \ CRC result reverse byte
+
+WDTCTL=\$1CC; \ WDT control register
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+
+RTCCTL=\$300; \ RTC control
+RTCIV=\$304; \ RTC interrupt vector word
+RTCMOD=\$308; \ RTC modulo
+RTCCNT=\$30C; \ RTC counter register
+
+TACLR=4;
+TAIFG=1;
+CCIFG=1;
+
+TA0CTL=\$380; \ TA0 control
+TA0CCTL0=\$382; \ Capture/compare control 0
+TA0CCTL1=\$384; \ Capture/compare control 1
+TA0CCTL2=\$386; \ Capture/compare control 2
+TA0R=\$390; \ TA0 counter register
+TA0CCR0=\$392; \ Capture/compare register 0
+TA0CCR1=\$394; \ Capture/compare register 1
+TA0CCR2=\$396; \ Capture/compare register 2
+TA0EX0=\$3A0; \ TA0 expansion register 0
+TA0IV=\$3AE; \ TA0 interrupt vector
+
+TA1CTL=\$3C0; \ TA1 control
+TA1CCTL0=\$3C2; \ Capture/compare control 0
+TA1CCTL1=\$3C4; \ Capture/compare control 1
+TA1CCTL2=\$3C6; \ Capture/compare control 2
+TA1R=\$3D0; \ TA1 counter register
+TA1CCR0=\$3D2; \ Capture/compare register 0
+TA1CCR1=\$3D4; \ Capture/compare register 1
+TA1CCR2=\$3D6; \ Capture/compare register 2
+TA1EX0=\$3E0; \ TA1 expansion register 0
+TA1IV=\$3EE; \ TA1 interrupt vector
+
+TA2CTL=\$400; \ TA2 control
+TA2CCTL0=\$402; \ Capture/compare control 0
+TA2CCTL1=\$404; \ Capture/compare control 1
+TA2R=\$410; \ TA2 counter register
+TA2CCR0=\$412; \ Capture/compare register 0
+TA2CCR1=\$414; \ Capture/compare register 1
+TA2EX0=\$420; \ TA2 expansion register 0
+TA2IV=\$42E; \ TA2 interrupt vector
+
+TA3CTL=\$440; \ TA3 control
+TA3CCTL0=\$442; \ Capture/compare control 0
+TA3CCTL1=\$444; \ Capture/compare control 1
+TA3R=\$450; \ TA3 counter register
+TA3CCR0=\$452; \ Capture/compare register 0
+TA3CCR1=\$454; \ Capture/compare register 1
+TA3EX0=\$460; \ TA3 expansion register 0
+TA3IV=\$46E; \ TA3 interrupt vector
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+
+UCA0CTLW0=\$500; \ eUSCI_A control word 0
+UCA0CTLW1=\$502; \ eUSCI_A control word 1
+UCA0BRW=\$506;
+UCA0BR0=\$506; \ eUSCI_A baud rate 0
+UCA0BR1=\$507; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$508; \ eUSCI_A modulation control
+UCA0STAT=\$50A; \ eUSCI_A status
+UCA0RXBUF=\$50C; \ eUSCI_A receive buffer
+UCA0TXBUF=\$50E; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$510; \ eUSCI_A LIN control
+UCA0IRTCTL=\$512; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$513; \ eUSCI_A IrDA receive control
+UCA0IE=\$51A; \ eUSCI_A interrupt enable
+UCA0IFG=\$51C; \ eUSCI_A interrupt flags
+UCA0IV=\$51E; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$520; \ eUSCI_A control word 0
+UCA1CTLW1=\$522; \ eUSCI_A control word 1
+UCA1BRW=\$526;
+UCA1BR0=\$526; \ eUSCI_A baud rate 0
+UCA1BR1=\$527; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$528; \ eUSCI_A modulation control
+UCA1STAT=\$52A; \ eUSCI_A status
+UCA1RXBUF=\$52C; \ eUSCI_A receive buffer
+UCA1TXBUF=\$52E; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$530; \ eUSCI_A LIN control
+UCA1IRTCTL=\$532; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$533; \ eUSCI_A IrDA receive control
+UCA1IE=\$53A; \ eUSCI_A interrupt enable
+UCA1IFG=\$53C; \ eUSCI_A interrupt flags
+UCA1IV=\$53E; \ eUSCI_A interrupt vector word
+
+UCB0CTLW0=\$540; \ eUSCI_B control word 0
+UCB0CTLW1=\$542; \ eUSCI_B control word 1
+UCB0BRW=\$546;
+UCB0BR0=\$546; \ eUSCI_B bit rate 0
+UCB0BR1=\$547; \ eUSCI_B bit rate 1
+UCB0STATW=\$548; \ eUSCI_B status word
+UCBCNT0=\$549; \ eUSCI_B hardware count
+UCB0TBCNT=\$54A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$54C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$54E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$554; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$556; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$558; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$55A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$55C; \ eUSCI_B received address
+UCB0ADDMASK=\$55E; \ eUSCI_B address mask
+UCB0I2CSA=\$560; \ eUSCI I2C slave address
+UCB0IE=\$56A; \ eUSCI interrupt enable
+UCB0IFG=\$56C; \ eUSCI interrupt flags
+UCB0IV=\$56E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+BAKMEM0=\$660; \ Backup Memory 0
+BAKMEM1=\$662; \ Backup Memory 1
+BAKMEM2=\$664; \ Backup Memory 2
+BAKMEM3=\$666; \ Backup Memory 3
+BAKMEM4=\$668; \ Backup Memory 4
+BAKMEM5=\$66A; \ Backup Memory 5
+BAKMEM6=\$66C; \ Backup Memory 6
+BAKMEM7=\$66E; \ Backup Memory 7
+BAKMEM8=\$670; \ Backup Memory 8
+BAKMEM9=\$672; \ Backup Memory 9
+BAKMEM10=\$674; \ Backup Memory 10
+BAKMEM11=\$676; \ Backup Memory 11
+BAKMEM12=\$678; \ Backup Memory 12
+BAKMEM13=\$67A; \ Backup Memory 13
+BAKMEM14=\$67C; \ Backup Memory 14
+BAKMEM15=\$67E; \ Backup Memory 15
+
+ADC10CTL0=\$700; \ ADC10_B Control register 0
+ADC10CTL1=\$702; \ ADC10_B Control register 1
+ADC10CTL2=\$704; \ ADC10_B Control register 2
+ADC10LO=\$706; \ ADC10_B Window Comparator Low Threshold
+ADC10HI=\$708; \ ADC10_B Window Comparator High Threshold
+ADC10MCTL0=\$70A; \ ADC10_B Memory Control Register 0
+ADC10MEM0=\$712; \ ADC10_B Conversion Memory Register
+ADC10IE=\$71A; \ ADC10_B Interrupt Enable
+ADC10IFG=\$71C; \ ADC10_B Interrupt Flags
+ADC10IV=\$71E; \ ADC10_B Interrupt Vector Word
+
+ADCON=\$10;
+ADCSTART=\$03;
DEVICE = "MSP430FR2476"
FR2_FAMILY
-
+HMPY ; hardware multiplier
+FLL ; Frequency Locked Loop CLOCK
; ----------------------------------------------
; MSP430FR2476 MEMORY MAP
; ----------------------------------------------
-!MSP430FR2476.pat
-
-! ----------------------------------------------
-! MSP430FR2476 MEMORY MAP
-! ----------------------------------------------
-! 0000-0005 = reserved
-! 0006-001F = TinyRAM
-! 0020-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL1 (2k)
-! 1800-19FF = info B (FRAM 512 B)
-! 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
-! 1A80-1FFF = unused
-! 2000-3FFF = RAM (8 KB)
-! 4000-7FFF = unused
-! 8000-17FFF = code memory (FRAM 64 kB)
-! FF80-FFFF = interrupt vectors (FRAM 128 B)
-! C0000-C3FFF = CapTivate lib
-! FFC00-FFFFF = BSL2 (2k)
-! ----------------------------------------------
-!PAGESIZE .equ 512 ; MPU unit
-
-
-! ============================================
-! TINY RAM
-! ============================================
-TinyRAM_ORG=\$06!
-TinyRAM_LEN=\$1A!
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000! to $17FF (2k)
-BSL2=\$FFC00! to $FFFFFF (1k)
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO(DCBA) memory map (256 bytes):
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! to $1A31 Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0080!
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$2000!
-RAM_LEN=\$2000!
-
-! ----------------------------------------------
-! FORTH RAM areas :
-! ----------------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ----------------------------------------------
-! FastForth RAM memory map (>= 1k):
-! ----------------------------------------------
-LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT
-LSATCK=\$2000! leave stack, grow up
-PSTACK=\$2080! parameter stack, grow down
-RSTACK=\$20E0! Return stack, grow down
-!
-PAD_I2CADR=\$20E0! RX I2C address
-PAD_I2CCNT=\$20E2! count max
-PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$2138! TX I2C address
-TIB_I2CCNT=\$213A! count of bytes
-TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$2190! base address for HOLDS
-HOLD_BASE=\$21B2! BASE HOLD area, grow down
-!
-HP=\$21B2! HOLD ptr
-LAST_NFA=\$21B4!
-LAST_THREAD=\$21B6!
-LAST_CFA=\$21B8!
-LAST_PSP=\$21BA!
-!
-STATEADR=\$21BC! Interpreter state
-BASEADR=\$21BE!
-CAPS=\$21C0 !
-!
-SOURCE_LEN=\$21C2! len of input stream
-SOURCE_ORG=\$21C4! adr of input stream
-TOIN=\$21C6! >IN
-DP=\$21C8! dictionary ptr
-!
-LASTVOC=\$21CA! keep VOC-LINK
-CURRENT=\$21CC! CURRENT dictionnary ptr
-CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!21E0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$21FC!
-SD_BUF_I2CNT=\$21FE!
-SD_BUF=\$2200! \ SD_Card buffer
-BUFEND=\$2400!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2402!
-BS_FirstSectorL=\$2404!
-BS_FirstSectorH=\$2406!
-OrgFAT1=\$2408!
-FATSize=\$240A!
-OrgFAT2=\$240C!
-OrgRootDir=\$240E!
-OrgClusters=\$2410! Sector of Cluster 0
-SecPerClus=\$2412!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2414! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2414! CRC:ll word access
-SD_CMD_FRM1=\$2415! ll byte access
-SD_CMD_FRM2=\$2416! LL:hh word access
-SD_CMD_FRM3=\$2417! hh byte access
-SD_CMD_FRM4=\$2418! HH:CMD word access
-SD_CMD_FRM5=\$2419! CMD byte access
-SectorL=\$241A! 2 words
-SectorH=\$241C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$241E!
-BufferLen=\$2420!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2422! 16 bits wide (FAT16)
-ClusterH=\$2424! 16 bits wide (FAT16)
-LastFATsector=\$2426! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2428! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$242A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$242C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$242E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2430!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2432! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2434!
-EndOfPath=\$2436!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2438!
-HandleEnd=\$2518!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2518!
-SDIB_I2CCNT=\$251A!
-SDIB_ORG=\$251C!
-
-SD_END=\$2570!
-SD_LEN=\$16E!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$8000! Code space start
-
-SLEEP=\$8000! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$800A! CODE compiled by LITERAL
-XSQUOTE=\$801E! CODE compiled by S" and S_
-HEREXEC=\$8032! CODE HERE and BEGIN execute address
-MUSMOD=\$803E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$8050! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$8058! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$8082! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$8084! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$8094! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$80A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$80AC! CODE compiled by IF UNTIL
-BRAN=\$80B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$80B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$80B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$80C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$80D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$8108! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$8112! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$8154! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$817E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$8184! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL &SOFT_APP)
-UART_WARM=\$8186! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$8144! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$8146! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$8150! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$8150! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$8152! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$817A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR2476
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
-JTAG_SIG2=\$FF82! if JTAG_SIG <> |\$FFFFFFFF, \$00000000|, SBW and JTAG are locked
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-BSL_I2C_ADRE=\$FFA0!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFDA! FFDA-FFFF
-VECT_LEN=\$38!
-! ----------------------------------------------
-ECOMP0_VEC=\$FFCA!
-P6_VEC=\$FFCC!
-P5_VEC=\$FFCE!
-P4_VEC=\$FFD0!
-P3_VEC=\$FFD2!
-P2_VEC=\$FFD4!
-P1_VEC=\$FFD6!
-ADC10_B_VEC=\$FFD8!
-EUSCI_B1_VEC=\$FFDA!
-EUSCI_B0_VEC=\$FFDC!
-EUSCI_A1_VEC=\$FFDE!
-EUSCI_A0_VEC=\$FFE0!
-WDT_VEC=\$FFE2!
-RTC_VEC=\$FFE4!
-TB0_X_VEC=\$FFE6!
-TB0_0_VEC=\$FFE8!
-TA3_X_VEC=\$FFEA!
-TA3_0_VEC=\$FFEC!
-TA2_X_VEC=\$FFEE!
-TA2_0_VEC=\$FFF0!
-TA1_X_VEC=\$FFF2!
-TA1_0_VEC=\$FFF4!
-TA0_X_VEC=\$FFF6!
-TA0_0_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ----------------------------------------------------------------------
-! MSP430FR2433 Peripheral File Map
-! ----------------------------------------------------------------------
-!SFR_SFR .equ 0100h ; Special function
-!PMM_SFR .equ 0120h ; PMM
-!SYS_SFR .equ 0140h ; SYS
-!CS_SFR .equ 0180h ; Clock System
-!FRAM_SFR .equ 01A0h ; FRAM control
-!CRC16_SFR .equ 01C0h
-!WDT_A_SFR .equ 01CCh ; Watchdog
-!PA_SFR .equ 0200h ; PORT1/2
-!PB_SFR .equ 0220h ; PORT3
-!RTC_SFR .equ 0300h
-!TA0_SFR .equ 0380h
-!TA1_SFR .equ 03C0h
-!TA2_SFR .equ 0400h
-!TA3_SFR .equ 0440h
-!TB0_SFR .equ 0480h
-!MPY_SFR .equ 04C0h
-!eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
-!eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
-!eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
-!BACK_MEM_SFR .equ 0660h
-!ADC10_B_SFR .equ 0700h
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMCTL1=\$122! \ PMM Control 0
-PMMCTL2=\$124! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-SYSCTL=\$140! \ System control
-SYSBSLC=\$142! \ Bootstrap loader configuration area
-SYSJMBC=\$146! \ JTAG mailbox control
-SYSJMBI0=\$148! \ JTAG mailbox input 0
-SYSJMBI1=\$14A! \ JTAG mailbox input 1
-SYSJMBO0=\$14C! \ JTAG mailbox output 0
-SYSJMBO1=\$14E! \ JTAG mailbox output 1
-SYSUNIV=\$15A! \ User NMI vector generator
-SYSSNIV=\$15C! \ System NMI vector generator
-SYSRSTIV=\$15E! \ Reset vector generator
-SYSCFG0=\$160! \ System configuration 0
-SYSCFG1=\$162! \ System configuration 1
-SYSCFG2=\$164! \ System configuration 2
-
-CSCTL0=\$180! \ CS control 0
-CSCTL1=\$182! \ CS control 1
-CSCTL2=\$184! \ CS control 2
-CSCTL3=\$186! \ CS control 3
-CSCTL4=\$188! \ CS control 4
-CSCTL5=\$18A! \ CS control 5
-CSCTL6=\$18C! \ CS control 6
-CSCTL7=\$18E! \ CS control 7
-CSCTL8=\$190! \ CS control 8
-
-FRCTLCTL0=\$1A0! \ FRAM control 0
-GCCTL0=\$1A4! \ General control 0
-GCCTL1=\$1A6! \ General control 1
-
-CRC16DI=\$1C0! \ CRC data input
-CRCDIRB=\$1C2! \ CRC data input reverse byte
-CRCINIRES=\$1C4! \ CRC initialization and result
-CRCRESR=\$1C6! \ CRC result reverse byte
-
-WDTCTL=\$1CC! \ WDT control register
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-P3IV=\$22E!
-P3SELC=\$236!
-P3IES=\$238!
-P3IE=\$23A!
-P3IFG=\$23C!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-P4SEL1=\$22D!
-P4SELC=\$237!
-P4IES=\$239!
-P4IE=\$23B!
-P4IFG=\$23D!
-P4IV=\$23E!
-
-PCIN=\$240!
-PCOUT=\$242!
-PCDIR=\$244!
-PCREN=\$246!
-PCSEL0=\$24A!
-PCSEL1=\$24C!
-PCSELC=\$256!
-PCIES=\$258!
-PCIE=\$25A!
-PCIFG=\$25C!
-
-P5IN=\$240!
-P5OUT=\$242!
-P5DIR=\$244!
-P5REN=\$246!
-P5SEL0=\$24A!
-P5SEL1=\$24C!
-P5IV=\$24E!
-P5SELC=\$256!
-P5IES=\$258!
-P5IE=\$25A!
-P5IFG=\$25C!
-
-P6IN=\$241!
-P6OUT=\$243!
-P6DIR=\$245!
-P6REN=\$247!
-P6SEL0=\$24B!
-P6SEL1=\$24D!
-P6SELC=\$257!
-P6IES=\$259!
-P6IE=\$25B!
-P6IFG=\$25D!
-P6IV=\$25E!
-
-RTCCTL=\$300! \ RTC control
-RTCIV=\$304! \ RTC interrupt vector word
-RTCMOD=\$308! \ RTC modulo
-RTCCNT=\$30C! \ RTC counter register
-
-TACLR=4!
-TAIFG=1!
-CCIFG=1!
-
-TA0CTL=\$380! \ TA0 control
-TA0CCTL0=\$382! \ Capture/compare control 0
-TA0CCTL1=\$384! \ Capture/compare control 1
-TA0CCTL2=\$386! \ Capture/compare control 2
-TA0R=\$390! \ TA0 counter register
-TA0CCR0=\$392! \ Capture/compare register 0
-TA0CCR1=\$394! \ Capture/compare register 1
-TA0CCR2=\$396! \ Capture/compare register 2
-TA0EX0=\$3A0! \ TA0 expansion register 0
-TA0IV=\$3AE! \ TA0 interrupt vector
-
-TA1CTL=\$3C0! \ TA1 control
-TA1CCTL0=\$3C2! \ Capture/compare control 0
-TA1CCTL1=\$3C4! \ Capture/compare control 1
-TA1CCTL2=\$3C6! \ Capture/compare control 2
-TA1R=\$3D0! \ TA1 counter register
-TA1CCR0=\$3D2! \ Capture/compare register 0
-TA1CCR1=\$3D4! \ Capture/compare register 1
-TA1CCR2=\$3D6! \ Capture/compare register 2
-TA1EX0=\$3E0! \ TA1 expansion register 0
-TA1IV=\$3EE! \ TA1 interrupt vector
-
-TA2CTL=\$400! \ TA2 control
-TA2CCTL0=\$402! \ Capture/compare control 0
-TA2CCTL1=\$404! \ Capture/compare control 1
-TA2CCTL2=\$406! \ Capture/compare control 2
-TA2R=\$410! \ TA2 counter register
-TA2CCR0=\$412! \ Capture/compare register 0
-TA2CCR1=\$414! \ Capture/compare register 1
-TA2CCR1=\$416! \ Capture/compare register 2
-TA2EX0=\$420! \ TA2 expansion register 0
-TA2IV=\$42E! \ TA2 interrupt vector
-
-TA3CTL=\$440! \ TA3 control
-TA3CCTL0=\$442! \ Capture/compare control 0
-TA3CCTL1=\$444! \ Capture/compare control 1
-TA3CCTL1=\$446! \ Capture/compare control 2
-TA3R=\$450! \ TA3 counter register
-TA3CCR0=\$452! \ Capture/compare register 0
-TA3CCR1=\$454! \ Capture/compare register 1
-TA3CCR1=\$456! \ Capture/compare register 2
-TA3EX0=\$460! \ TA3 expansion register 0
-TA3IV=\$46E! \ TA3 interrupt vector
-
-TB0CTL=\$480! \ TB0 control
-TB0CCTL0=\$482! \ Capture/compare control 0
-TB0CCTL1=\$484! \ Capture/compare control 1
-TB0CCTL2=\$486! \ Capture/compare control 2
-TB0CCTL3=\$488! \ Capture/compare control 3
-TB0CCTL4=\$48A! \ Capture/compare control 4
-TB0CCTL5=\$48C! \ Capture/compare control 5
-TB0CCTL6=\$48E! \ Capture/compare control 6
-TB0R=\$490! \ TB0 counter register
-TB0CCR0=\$492! \ Capture/compare register 0
-TB0CCR1=\$494! \ Capture/compare register 1
-TB0CCR2=\$496! \ Capture/compare register 2
-TB0CCR3=\$498! \ Capture/compare register 3
-TB0CCR5=\$49A! \ Capture/compare register 4
-TB0CCR5=\$49C! \ Capture/compare register 5
-TB0CCR6=\$49E! \ Capture/compare register 6
-TB0EX0=\$4A0! \ TB0 expansion register 0
-TB0IV=\$4AE! \ TB0 interrupt vector
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-
-UCA0CTLW0=\$500! \ eUSCI_A control word 0
-UCA0CTLW1=\$502! \ eUSCI_A control word 1
-UCA0BRW=\$506!
-UCA0BR0=\$506! \ eUSCI_A baud rate 0
-UCA0BR1=\$507! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$508! \ eUSCI_A modulation control
-UCA0STAT=\$50A! \ eUSCI_A status
-UCA0RXBUF=\$50C! \ eUSCI_A receive buffer
-UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$510! \ eUSCI_A LIN control
-UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control
-UCA0IE=\$51A! \ eUSCI_A interrupt enable
-UCA0IFG=\$51C! \ eUSCI_A interrupt flags
-UCA0IV=\$51E! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$520! \ eUSCI_A control word 0
-UCA1CTLW1=\$522! \ eUSCI_A control word 1
-UCA1BRW=\$526!
-UCA1BR0=\$526! \ eUSCI_A baud rate 0
-UCA1BR1=\$527! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$528! \ eUSCI_A modulation control
-UCA1STAT=\$52A! \ eUSCI_A status
-UCA1RXBUF=\$52C! \ eUSCI_A receive buffer
-UCA1TXBUF=\$52E! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$530! \ eUSCI_A LIN control
-UCA1IRTCTL=\$532! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$533! \ eUSCI_A IrDA receive control
-UCA1IE=\$53A! \ eUSCI_A interrupt enable
-UCA1IFG=\$53C! \ eUSCI_A interrupt flags
-UCA1IV=\$53E! \ eUSCI_A interrupt vector word
-
-UCB0CTLW0=\$540! \ eUSCI_B control word 0
-UCB0CTLW1=\$542! \ eUSCI_B control word 1
-UCB0BRW=\$546!
-UCB0BR0=\$546! \ eUSCI_B bit rate 0
-UCB0BR1=\$547! \ eUSCI_B bit rate 1
-UCB0STATW=\$548! \ eUSCI_B status word
-UCBCNT0=\$549! \ eUSCI_B hardware count
-UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$54C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$55C! \ eUSCI_B received address
-UCB0ADDMASK=\$55E! \ eUSCI_B address mask
-UCB0I2CSA=\$560! \ eUSCI I2C slave address
-UCB0IE=\$56A! \ eUSCI interrupt enable
-UCB0IFG=\$56C! \ eUSCI interrupt flags
-UCB0IV=\$56E! \ eUSCI interrupt vector word
-
-UCB1CTLW0=\$580! \ eUSCI_B control word 0
-UCB1CTLW1=\$582! \ eUSCI_B control word 1
-UCB1BRW=\$586!
-UCB1BR0=\$586! \ eUSCI_B bit rate 0
-UCB1BR1=\$587! \ eUSCI_B bit rate 1
-UCB1STATW=\$588! \ eUSCI_B status word
-UCB1NT0=\$589! \ eUSCI_B hardware count
-UCB1TBCNT=\$58A! \ eUSCI_B byte counter threshold
-UCB1RXBUF=\$58C! \ eUSCI_B receive buffer
-UCB1TXBUF=\$58E! \ eUSCI_B transmit buffer
-UCB1I2COA0=\$594! \ eUSCI_B I2C own address 0
-UCB1I2COA1=\$596! \ eUSCI_B I2C own address 1
-UCB1I2COA2=\$598! \ eUSCI_B I2C own address 2
-UCB1I2COA3=\$59A! \ eUSCI_B I2C own address 3
-UCB1ADDRX=\$59C! \ eUSCI_B received address
-UCB1ADDMASK=\$59E! \ eUSCI_B address mask
-UCB1I2CSA=\$5A0! \ eUSCI I2C slave address
-UCB1IE=\$5AA! \ eUSCI interrupt enable
-UCB1IFG=\$5AC! \ eUSCI interrupt flags
-UCB1IV=\$5AE! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-BAKMEM0=\$660! \ Backup Memory 0
-BAKMEM1=\$662! \ Backup Memory 1
-BAKMEM2=\$664! \ Backup Memory 2
-BAKMEM3=\$666! \ Backup Memory 3
-BAKMEM4=\$668! \ Backup Memory 4
-BAKMEM5=\$66A! \ Backup Memory 5
-BAKMEM6=\$66C! \ Backup Memory 6
-BAKMEM7=\$66E! \ Backup Memory 7
-BAKMEM8=\$670! \ Backup Memory 8
-BAKMEM9=\$672! \ Backup Memory 9
-BAKMEM10=\$674! \ Backup Memory 10
-BAKMEM11=\$676! \ Backup Memory 11
-BAKMEM12=\$678! \ Backup Memory 12
-BAKMEM13=\$67A! \ Backup Memory 13
-BAKMEM14=\$67C! \ Backup Memory 14
-BAKMEM15=\$67E! \ Backup Memory 15
-
-ADC10CTL0=\$700! \ ADC10_B Control register 0
-ADC10CTL1=\$702! \ ADC10_B Control register 1
-ADC10CTL2=\$704! \ ADC10_B Control register 2
-ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold
-ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold
-ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0
-ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register
-ADC10IE=\$71A! \ ADC10_B Interrupt Enable
-ADC10IFG=\$71C! \ ADC10_B Interrupt Flags
-ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-CP0CTL0=\$8E0! \ Comparator control 0
-CP0CTL1=\$8E2! \ Comparator control 1
-CP0INT=\$8E6! \ Comparator interrupt
-CP0IV=\$8E8! \ Comparator interrupt vector
-CP0DACCTL=\$8EA! \ Comparator built-in DAC control
-CP0DACDATA=\$8EC! \ Comparator built-in DAC data
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430FR2476.pat
+
+; ----------------------------------------------
+; MSP430FR2476 MEMORY MAP
+; ----------------------------------------------
+; 0000-0005 = reserved
+; 0006-001F = TinyRAM
+; 0020-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL1 (2k)
+; 1800-19FF = info B (FRAM 512 B)
+; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
+; 1A80-1FFF = unused
+; 2000-3FFF = RAM (8 KB)
+; 4000-7FFF = unused
+; 8000-17FFF = code memory (FRAM 64 kB)
+; FF80-FFFF = interrupt vectors (FRAM 128 B)
+; C0000-C3FFF = CapTivate lib
+; FFC00-FFFFF = BSL2 (2k)
+; ----------------------------------------------
+;PAGESIZE .equ 512 ; MPU unit
+
+
+; ============================================
+; TINY RAM
+; ============================================
+TinyRAM_ORG=\$06;
+TinyRAM_LEN=\$1A;
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000; to $17FF (2k)
+BSL2=\$FFC00; to $FFFFFF (1k)
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$2000;
+RAM_LEN=\$2000;
+
+; ----------------------------------------------
+; FORTH RAM areas :
+; ----------------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ----------------------------------------------
+; FastForth RAM memory map (>= 1k):
+; ----------------------------------------------
+LEAVEPTR=\$2000; Leave-stack pointer, init by QUIT
+LSATCK=\$2000; leave stack, grow up
+PSTACK=\$2080; parameter stack, grow down
+RSTACK=\$20E0; Return stack, grow down
+;
+PAD_I2CADR=\$20E0; RX I2C address
+PAD_I2CCNT=\$20E2; count max
+PAD_ORG=\$20E4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$2138; TX I2C address
+TIB_I2CCNT=\$213A; count of bytes
+TIB_ORG=\$213C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$2190; base address for HOLDS
+HOLD_BASE=\$21B2; BASE HOLD area, grow down
+;
+HP=\$21B2; HOLD ptr
+STATEADR=\$21B4; Interpreter state
+BASEADR=\$21B6; base
+CAPS=\$21B8; CAPS ON/OFF
+SOURCE_LEN=\$21BA; len of input stream
+SOURCE_ORG=\$21BC; adr of input stream
+TOIN=\$21BE; >IN
+;
+DP=\$21C0; dictionary ptr
+LASTVOC=\$21C2; keep VOC-LINK
+CURRENT=\$21C4; CURRENT dictionnary ptr
+CONTEXT=\$21C6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$21D8;
+LAST_THREAD=\$21DA;
+LAST_CFA=\$21DC;
+LAST_PSP=\$21DE;
+ASMBW1=\$21E0; 3 backward labels
+ASMBW2=\$21E2;
+ASMBW3=\$21E4;
+ASMFW1=\$21E6; 3 forward labels
+ASMFW2=\$21E8;
+ASMFW3=\$21EA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$21FC;
+SD_BUF_I2CNT=\$21FE;
+SD_BUF=\$2200; \ SD_Card buffer
+BUFEND=\$2400;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2402;
+BS_FirstSectorL=\$2404;
+BS_FirstSectorH=\$2406;
+OrgFAT1=\$2408;
+FATSize=\$240A;
+OrgFAT2=\$240C;
+OrgRootDir=\$240E;
+OrgClusters=\$2410; Sector of Cluster 0
+SecPerClus=\$2412;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2414; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2414; CRC:ll word access
+SD_CMD_FRM1=\$2415; ll byte access
+SD_CMD_FRM2=\$2416; LL:hh word access
+SD_CMD_FRM3=\$2417; hh byte access
+SD_CMD_FRM4=\$2418; HH:CMD word access
+SD_CMD_FRM5=\$2419; CMD byte access
+SectorL=\$241A; 2 words
+SectorH=\$241C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$241E;
+BufferLen=\$2420;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2422; 16 bits wide (FAT16)
+ClusterH=\$2424; 16 bits wide (FAT16)
+LastFATsector=\$2426; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2428; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$242A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$242C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$242E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2430;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2432; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2434;
+EndOfPath=\$2436;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2438;
+HandleEnd=\$2518;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2518;
+SDIB_I2CCNT=\$251A;
+SDIB_ORG=\$251C;
+
+SD_END=\$2570;
+SD_LEN=\$16E;
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$8000; Code space start
+; ----------------------------------------------
+\#LIT=\#\$8000; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$8014; asm CODE run time of QUOTE
+\#MUSMOD=\#\$8028; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$803A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$8042; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$806C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$806E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$807E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$808A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$8096; CODE compiled by IF UNTIL
+\#BRAN=\#\$809C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$809E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$80A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$80AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$80BA;
+\#ABORT_TERM=\#\$8100; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$8172; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$815C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for defined addresses from FORTH definitions
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR2476
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset>
+JTAG_SIG2=\$FF82; if JTAG_SIG <> |\$FFFFFFFF, \$00000000|, SBW and JTAG are locked
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+BSL_I2C_ADRE=\$FFA0;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFDA; FFDA-FFFF
+VECT_LEN=\$38;
+; ----------------------------------------------
+ECOMP0_VEC=\$FFCA;
+P6_VEC=\$FFCC;
+P5_VEC=\$FFCE;
+P4_VEC=\$FFD0;
+P3_VEC=\$FFD2;
+P2_VEC=\$FFD4;
+P1_VEC=\$FFD6;
+ADC10_B_VEC=\$FFD8;
+EUSCI_B1_VEC=\$FFDA;
+EUSCI_B0_VEC=\$FFDC;
+EUSCI_A1_VEC=\$FFDE;
+EUSCI_A0_VEC=\$FFE0;
+WDT_VEC=\$FFE2;
+RTC_VEC=\$FFE4;
+TB0_X_VEC=\$FFE6;
+TB0_0_VEC=\$FFE8;
+TA3_X_VEC=\$FFEA;
+TA3_0_VEC=\$FFEC;
+TA2_X_VEC=\$FFEE;
+TA2_0_VEC=\$FFF0;
+TA1_X_VEC=\$FFF2;
+TA1_0_VEC=\$FFF4;
+TA0_X_VEC=\$FFF6;
+TA0_0_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ----------------------------------------------------------------------
+; MSP430FR2476 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;SYS_SFR .equ 0140h ; SYS
+;CS_SFR .equ 0180h ; Clock System
+;FRAM_SFR .equ 01A0h ; FRAM control
+;CRC16_SFR .equ 01C0h
+;WDT_A_SFR .equ 01CCh ; Watchdog
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3/4
+;PC_SFR .equ 0240h ; PORT5/6
+;RTC_SFR .equ 0300h
+;TA0_SFR .equ 0380h
+;TA1_SFR .equ 03C0h
+;TA2_SFR .equ 0400h
+;TA3_SFR .equ 0440h
+;TB0_SFR .equ 0480h
+;MPY_SFR .equ 04C0h
+;eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
+;eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
+;eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
+;eUSCI_B1_SFR .equ 0580h ; eUSCI_B1
+;BACK_MEM_SFR .equ 0660h
+;ADC10_B_SFR .equ 0700h
+;eCOMP_SFR .equ 08F0h
+
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMCTL1=\$122; \ PMM Control 0
+PMMCTL2=\$124; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+SYSCTL=\$140; \ System control
+SYSBSLC=\$142; \ Bootstrap loader configuration area
+SYSJMBC=\$146; \ JTAG mailbox control
+SYSJMBI0=\$148; \ JTAG mailbox input 0
+SYSJMBI1=\$14A; \ JTAG mailbox input 1
+SYSJMBO0=\$14C; \ JTAG mailbox output 0
+SYSJMBO1=\$14E; \ JTAG mailbox output 1
+SYSUNIV=\$15A; \ User NMI vector generator
+SYSSNIV=\$15C; \ System NMI vector generator
+SYSRSTIV=\$15E; \ Reset vector generator
+SYSCFG0=\$160; \ System configuration 0
+SYSCFG1=\$162; \ System configuration 1
+SYSCFG2=\$164; \ System configuration 2
+
+CSCTL0=\$180; \ CS control 0
+CSCTL1=\$182; \ CS control 1
+CSCTL2=\$184; \ CS control 2
+CSCTL3=\$186; \ CS control 3
+CSCTL4=\$188; \ CS control 4
+CSCTL5=\$18A; \ CS control 5
+CSCTL6=\$18C; \ CS control 6
+CSCTL7=\$18E; \ CS control 7
+CSCTL8=\$190; \ CS control 8
+
+FRCTLCTL0=\$1A0; \ FRAM control 0
+GCCTL0=\$1A4; \ General control 0
+GCCTL1=\$1A6; \ General control 1
+
+CRC16DI=\$1C0; \ CRC data input
+CRCDIRB=\$1C2; \ CRC data input reverse byte
+CRCINIRES=\$1C4; \ CRC initialization and result
+CRCRESR=\$1C6; \ CRC result reverse byte
+
+WDTCTL=\$1CC; \ WDT control register
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+P3IV=\$22E;
+P3SELC=\$236;
+P3IES=\$238;
+P3IE=\$23A;
+P3IFG=\$23C;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+P4SEL1=\$22D;
+P4SELC=\$237;
+P4IES=\$239;
+P4IE=\$23B;
+P4IFG=\$23D;
+P4IV=\$23E;
+
+PCIN=\$240;
+PCOUT=\$242;
+PCDIR=\$244;
+PCREN=\$246;
+PCSEL0=\$24A;
+PCSEL1=\$24C;
+PCSELC=\$256;
+PCIES=\$258;
+PCIE=\$25A;
+PCIFG=\$25C;
+
+P5IN=\$240;
+P5OUT=\$242;
+P5DIR=\$244;
+P5REN=\$246;
+P5SEL0=\$24A;
+P5SEL1=\$24C;
+P5IV=\$24E;
+P5SELC=\$256;
+P5IES=\$258;
+P5IE=\$25A;
+P5IFG=\$25C;
+
+P6IN=\$241;
+P6OUT=\$243;
+P6DIR=\$245;
+P6REN=\$247;
+P6SEL0=\$24B;
+P6SEL1=\$24D;
+P6SELC=\$257;
+P6IES=\$259;
+P6IE=\$25B;
+P6IFG=\$25D;
+P6IV=\$25E;
+
+RTCCTL=\$300; \ RTC control
+RTCIV=\$304; \ RTC interrupt vector word
+RTCMOD=\$308; \ RTC modulo
+RTCCNT=\$30C; \ RTC counter register
+
+TACLR=4;
+TAIFG=1;
+CCIFG=1;
+
+TA0CTL=\$380; \ TA0 control
+TA0CCTL0=\$382; \ Capture/compare control 0
+TA0CCTL1=\$384; \ Capture/compare control 1
+TA0CCTL2=\$386; \ Capture/compare control 2
+TA0R=\$390; \ TA0 counter register
+TA0CCR0=\$392; \ Capture/compare register 0
+TA0CCR1=\$394; \ Capture/compare register 1
+TA0CCR2=\$396; \ Capture/compare register 2
+TA0EX0=\$3A0; \ TA0 expansion register 0
+TA0IV=\$3AE; \ TA0 interrupt vector
+
+TA1CTL=\$3C0; \ TA1 control
+TA1CCTL0=\$3C2; \ Capture/compare control 0
+TA1CCTL1=\$3C4; \ Capture/compare control 1
+TA1CCTL2=\$3C6; \ Capture/compare control 2
+TA1R=\$3D0; \ TA1 counter register
+TA1CCR0=\$3D2; \ Capture/compare register 0
+TA1CCR1=\$3D4; \ Capture/compare register 1
+TA1CCR2=\$3D6; \ Capture/compare register 2
+TA1EX0=\$3E0; \ TA1 expansion register 0
+TA1IV=\$3EE; \ TA1 interrupt vector
+
+TA2CTL=\$400; \ TA2 control
+TA2CCTL0=\$402; \ Capture/compare control 0
+TA2CCTL1=\$404; \ Capture/compare control 1
+TA2CCTL2=\$406; \ Capture/compare control 2
+TA2R=\$410; \ TA2 counter register
+TA2CCR0=\$412; \ Capture/compare register 0
+TA2CCR1=\$414; \ Capture/compare register 1
+TA2CCR1=\$416; \ Capture/compare register 2
+TA2EX0=\$420; \ TA2 expansion register 0
+TA2IV=\$42E; \ TA2 interrupt vector
+
+TA3CTL=\$440; \ TA3 control
+TA3CCTL0=\$442; \ Capture/compare control 0
+TA3CCTL1=\$444; \ Capture/compare control 1
+TA3CCTL1=\$446; \ Capture/compare control 2
+TA3R=\$450; \ TA3 counter register
+TA3CCR0=\$452; \ Capture/compare register 0
+TA3CCR1=\$454; \ Capture/compare register 1
+TA3CCR1=\$456; \ Capture/compare register 2
+TA3EX0=\$460; \ TA3 expansion register 0
+TA3IV=\$46E; \ TA3 interrupt vector
+
+TB0CTL=\$480; \ TB0 control
+TB0CCTL0=\$482; \ Capture/compare control 0
+TB0CCTL1=\$484; \ Capture/compare control 1
+TB0CCTL2=\$486; \ Capture/compare control 2
+TB0CCTL3=\$488; \ Capture/compare control 3
+TB0CCTL4=\$48A; \ Capture/compare control 4
+TB0CCTL5=\$48C; \ Capture/compare control 5
+TB0CCTL6=\$48E; \ Capture/compare control 6
+TB0R=\$490; \ TB0 counter register
+TB0CCR0=\$492; \ Capture/compare register 0
+TB0CCR1=\$494; \ Capture/compare register 1
+TB0CCR2=\$496; \ Capture/compare register 2
+TB0CCR3=\$498; \ Capture/compare register 3
+TB0CCR5=\$49A; \ Capture/compare register 4
+TB0CCR5=\$49C; \ Capture/compare register 5
+TB0CCR6=\$49E; \ Capture/compare register 6
+TB0EX0=\$4A0; \ TB0 expansion register 0
+TB0IV=\$4AE; \ TB0 interrupt vector
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+
+UCA0CTLW0=\$500; \ eUSCI_A control word 0
+UCA0CTLW1=\$502; \ eUSCI_A control word 1
+UCA0BRW=\$506;
+UCA0BR0=\$506; \ eUSCI_A baud rate 0
+UCA0BR1=\$507; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$508; \ eUSCI_A modulation control
+UCA0STAT=\$50A; \ eUSCI_A status
+UCA0RXBUF=\$50C; \ eUSCI_A receive buffer
+UCA0TXBUF=\$50E; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$510; \ eUSCI_A LIN control
+UCA0IRTCTL=\$512; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$513; \ eUSCI_A IrDA receive control
+UCA0IE=\$51A; \ eUSCI_A interrupt enable
+UCA0IFG=\$51C; \ eUSCI_A interrupt flags
+UCA0IV=\$51E; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$520; \ eUSCI_A control word 0
+UCA1CTLW1=\$522; \ eUSCI_A control word 1
+UCA1BRW=\$526;
+UCA1BR0=\$526; \ eUSCI_A baud rate 0
+UCA1BR1=\$527; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$528; \ eUSCI_A modulation control
+UCA1STAT=\$52A; \ eUSCI_A status
+UCA1RXBUF=\$52C; \ eUSCI_A receive buffer
+UCA1TXBUF=\$52E; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$530; \ eUSCI_A LIN control
+UCA1IRTCTL=\$532; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$533; \ eUSCI_A IrDA receive control
+UCA1IE=\$53A; \ eUSCI_A interrupt enable
+UCA1IFG=\$53C; \ eUSCI_A interrupt flags
+UCA1IV=\$53E; \ eUSCI_A interrupt vector word
+
+UCB0CTLW0=\$540; \ eUSCI_B control word 0
+UCB0CTLW1=\$542; \ eUSCI_B control word 1
+UCB0BRW=\$546;
+UCB0BR0=\$546; \ eUSCI_B bit rate 0
+UCB0BR1=\$547; \ eUSCI_B bit rate 1
+UCB0STATW=\$548; \ eUSCI_B status word
+UCBCNT0=\$549; \ eUSCI_B hardware count
+UCB0TBCNT=\$54A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$54C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$54E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$554; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$556; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$558; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$55A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$55C; \ eUSCI_B received address
+UCB0ADDMASK=\$55E; \ eUSCI_B address mask
+UCB0I2CSA=\$560; \ eUSCI I2C slave address
+UCB0IE=\$56A; \ eUSCI interrupt enable
+UCB0IFG=\$56C; \ eUSCI interrupt flags
+UCB0IV=\$56E; \ eUSCI interrupt vector word
+
+UCB1CTLW0=\$580; \ eUSCI_B control word 0
+UCB1CTLW1=\$582; \ eUSCI_B control word 1
+UCB1BRW=\$586;
+UCB1BR0=\$586; \ eUSCI_B bit rate 0
+UCB1BR1=\$587; \ eUSCI_B bit rate 1
+UCB1STATW=\$588; \ eUSCI_B status word
+UCB1NT0=\$589; \ eUSCI_B hardware count
+UCB1TBCNT=\$58A; \ eUSCI_B byte counter threshold
+UCB1RXBUF=\$58C; \ eUSCI_B receive buffer
+UCB1TXBUF=\$58E; \ eUSCI_B transmit buffer
+UCB1I2COA0=\$594; \ eUSCI_B I2C own address 0
+UCB1I2COA1=\$596; \ eUSCI_B I2C own address 1
+UCB1I2COA2=\$598; \ eUSCI_B I2C own address 2
+UCB1I2COA3=\$59A; \ eUSCI_B I2C own address 3
+UCB1ADDRX=\$59C; \ eUSCI_B received address
+UCB1ADDMASK=\$59E; \ eUSCI_B address mask
+UCB1I2CSA=\$5A0; \ eUSCI I2C slave address
+UCB1IE=\$5AA; \ eUSCI interrupt enable
+UCB1IFG=\$5AC; \ eUSCI interrupt flags
+UCB1IV=\$5AE; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+BAKMEM0=\$660; \ Backup Memory 0
+BAKMEM1=\$662; \ Backup Memory 1
+BAKMEM2=\$664; \ Backup Memory 2
+BAKMEM3=\$666; \ Backup Memory 3
+BAKMEM4=\$668; \ Backup Memory 4
+BAKMEM5=\$66A; \ Backup Memory 5
+BAKMEM6=\$66C; \ Backup Memory 6
+BAKMEM7=\$66E; \ Backup Memory 7
+BAKMEM8=\$670; \ Backup Memory 8
+BAKMEM9=\$672; \ Backup Memory 9
+BAKMEM10=\$674; \ Backup Memory 10
+BAKMEM11=\$676; \ Backup Memory 11
+BAKMEM12=\$678; \ Backup Memory 12
+BAKMEM13=\$67A; \ Backup Memory 13
+BAKMEM14=\$67C; \ Backup Memory 14
+BAKMEM15=\$67E; \ Backup Memory 15
+
+ADC10CTL0=\$700; \ ADC10_B Control register 0
+ADC10CTL1=\$702; \ ADC10_B Control register 1
+ADC10CTL2=\$704; \ ADC10_B Control register 2
+ADC10LO=\$706; \ ADC10_B Window Comparator Low Threshold
+ADC10HI=\$708; \ ADC10_B Window Comparator High Threshold
+ADC10MCTL0=\$70A; \ ADC10_B Memory Control Register 0
+ADC10MEM0=\$712; \ ADC10_B Conversion Memory Register
+ADC10IE=\$71A; \ ADC10_B Interrupt Enable
+ADC10IFG=\$71C; \ ADC10_B Interrupt Flags
+ADC10IV=\$71E; \ ADC10_B Interrupt Vector Word
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CP0CTL0=\$8E0; \ Comparator control 0
+CP0CTL1=\$8E2; \ Comparator control 1
+CP0INT=\$8E6; \ Comparator interrupt
+CP0IV=\$8E8; \ Comparator interrupt vector
+CP0DACCTL=\$8EA; \ Comparator built-in DAC control
+CP0DACDATA=\$8EC; \ Comparator built-in DAC data
-!MSP430FR2633.pat
-
-! ----------------------------------------------
-! MSP430FR2633 MEMORY MAP
-! ----------------------------------------------
-! 0000-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL1 (4x512 B)
-! 1800-19FF = info B (FRAM 512 B)
-! 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
-! 2000-2FFF = RAM (4 KB)
-! 4000-6FFF = ROM captivate (12 k)
-! C400-FF7F = code memory (FRAM 15232 B)
-! FF80-FFFF = interrupt vectors (FRAM 128 B)
-! FFC00-FFFFF = BSL2 (2k)
-! ----------------------------------------------
-!PAGESIZE .equ 512 ; MPU unit
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-BSL2=\$FFC00!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG =\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0080!
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$2000!
-RAM_LEN=\$1000!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ---------------------------------------
-! FastForth RAM memory map (>= 1k):
-! ---------------------------------------
-LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT
-LSATCK=\$2000! leave stack, grow up
-PSTACK=\$2080! parameter stack, grow down
-RSTACK=\$20E0! Return stack, grow down
-!
-PAD_I2CADR=\$20E0! RX I2C address
-PAD_I2CCNT=\$20E2! count max
-PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$2138! TX I2C address
-TIB_I2CCNT=\$213A! count of bytes
-TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$2190! base address for HOLDS
-HOLD_BASE=\$21B2! BASE HOLD area, grow down
-!
-HP=\$21B2! HOLD ptr
-LAST_NFA=\$21B4!
-LAST_THREAD=\$21B6!
-LAST_CFA=\$21B8!
-LAST_PSP=\$21BA!
-!
-STATEADR=\$21BC! Interpreter state
-BASEADR=\$21BE!
-CAPS=\$21C0 !
-!
-SOURCE_LEN=\$21C2! len of input stream
-SOURCE_ORG=\$21C4! adr of input stream
-TOIN=\$21C6! >IN
-DP=\$21C8! dictionary ptr
-!
-LASTVOC=\$21CA! keep VOC-LINK
-CURRENT=\$21CC! CURRENT dictionnary ptr
-CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!21E0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$21FC!
-SD_BUF_I2CNT=\$21FE!
-SD_BUF=\$2200! \ SD_Card buffer
-BUFEND=\$2400!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2402!
-BS_FirstSectorL=\$2404!
-BS_FirstSectorH=\$2406!
-OrgFAT1=\$2408!
-FATSize=\$240A!
-OrgFAT2=\$240C!
-OrgRootDir=\$240E!
-OrgClusters=\$2410! Sector of Cluster 0
-SecPerClus=\$2412!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2414! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2414! CRC:ll word access
-SD_CMD_FRM1=\$2415! ll byte access
-SD_CMD_FRM2=\$2416! LL:hh word access
-SD_CMD_FRM3=\$2417! hh byte access
-SD_CMD_FRM4=\$2418! HH:CMD word access
-SD_CMD_FRM5=\$2419! CMD byte access
-SectorL=\$241A! 2 words
-SectorH=\$241C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$241E!
-BufferLen=\$2420!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2422! 16 bits wide (FAT16)
-ClusterH=\$2424! 16 bits wide (FAT16)
-LastFATsector=\$2426! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2428! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$242A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$242C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$242E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2430!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2432! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2434!
-EndOfPath=\$2436!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2438!
-HandleEnd=\$2518!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2518!
-SDIB_I2CCNT=\$251A!
-SDIB_ORG=\$251C!
-
-SD_END=\$2570!
-SD_LEN=\$16E!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$C400! Code space start
-
-SLEEP=\$C400! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$C40A! CODE compiled by LITERAL
-XSQUOTE=\$C41E! CODE compiled by S" and S_
-HEREXEC=\$C432! CODE HERE and BEGIN execute address
-MUSMOD=\$C43E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$C450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$C458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$C482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$C484! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$C494! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$C4A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$C4AC! CODE compiled by IF UNTIL
-BRAN=\$C4B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$C4B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$C4B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$C4C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$C4D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$C508! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$C512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$C554! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$C57E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$C584! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$C586! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$C544! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$C546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$C550! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$C550! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$C552! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$C57A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR2633
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFD8! FFD8-FFFF
-VECT_LEN=\$28!
-
-CAPTIVATE_VEC=\$FFD8!
-P2_VEC=\$FFDA!
-P1_VEC=\$FFDC!
-ADC10_B_VEC=\$FFDE!
-EUSCI_B0_VEC=\$FFE0!
-EUSCI_A1_VEC=\$FFE2!
-EUSCI_A0_VEC=\$FFE4!
-WDT_VEC=\$FFE6!
-RTC_VEC=\$FFE8!
-TA3_X_VEC=\$FFEA!
-TA3_0_VEC=\$FFEC!
-TA2_X_VEC=\$FFEE!
-TA2_0_VEC=\$FFF0!
-TA1_X_VEC=\$FFF2!
-TA1_0_VEC=\$FFF4!
-TA0_X_VEC=\$FFF6!
-TA0_0_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMCTL1=\$122! \ PMM Control 0
-PMMCTL2=\$124! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-SYSCTL=\$140! \ System control
-SYSBSLC=\$142! \ Bootstrap loader configuration area
-SYSJMBC=\$146! \ JTAG mailbox control
-SYSJMBI0=\$148! \ JTAG mailbox input 0
-SYSJMBI1=\$14A! \ JTAG mailbox input 1
-SYSJMBO0=\$14C! \ JTAG mailbox output 0
-SYSJMBO1=\$14E! \ JTAG mailbox output 1
-SYSUNIV=\$15A! \ User NMI vector generator
-SYSSNIV=\$15C! \ System NMI vector generator
-SYSRSTIV=\$15E! \ Reset vector generator
-SYSCFG0=\$160! \ System configuration 0
-SYSCFG1=\$162! \ System configuration 1
-SYSCFG2=\$164! \ System configuration 2
-
-CSCTL0=\$180! \ CS control 0
-CSCTL1=\$182! \ CS control 1
-CSCTL2=\$184! \ CS control 2
-CSCTL3=\$186! \ CS control 3
-CSCTL4=\$188! \ CS control 4
-CSCTL5=\$18A! \ CS control 5
-CSCTL6=\$18C! \ CS control 6
-CSCTL7=\$18E! \ CS control 7
-CSCTL8=\$190! \ CS control 8
-
-
-FRCTLCTL0=\$1A0! \ FRAM control 0
-GCCTL0=\$1A4! \ General control 0
-GCCTL1=\$1A6! \ General control 1
-
-CRC16DI=\$1C0! \ CRC data input
-CRCDIRB=\$1C2! \ CRC data input reverse byte
-CRCINIRES=\$1C4! \ CRC initialization and result
-CRCRESR=\$1C6! \ CRC result reverse byte
-
-WDTCTL=\$1CC! \ WDT control register
-
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-
-
-RTCCTL=\$300! \ RTC control
-RTCIV=\$304! \ RTC interrupt vector word
-RTCMOD=\$308! \ RTC modulo
-RTCCNT=\$30C! \ RTC counter register
-
-
-TACLR=4!
-TAIFG=1!
-CCIFG=1!
-
-TA0CTL=\$380! \ TA0 control
-TA0CCTL0=\$382! \ Capture/compare control 0
-TA0CCTL1=\$384! \ Capture/compare control 1
-TA0CCTL2=\$386! \ Capture/compare control 2
-TA0R=\$390! \ TA0 counter register
-TA0CCR0=\$392! \ Capture/compare register 0
-TA0CCR1=\$394! \ Capture/compare register 1
-TA0CCR2=\$396! \ Capture/compare register 2
-TA0EX0=\$3A0! \ TA0 expansion register 0
-TA0IV=\$3AE! \ TA0 interrupt vector
-
-TA1CTL=\$3C0! \ TA1 control
-TA1CCTL0=\$3C2! \ Capture/compare control 0
-TA1CCTL1=\$3C4! \ Capture/compare control 1
-TA1CCTL2=\$3C6! \ Capture/compare control 2
-TA1R=\$3D0! \ TA1 counter register
-TA1CCR0=\$3D2! \ Capture/compare register 0
-TA1CCR1=\$3D4! \ Capture/compare register 1
-TA1CCR2=\$3D6! \ Capture/compare register 2
-TA1EX0=\$3E0! \ TA1 expansion register 0
-TA1IV=\$3EE! \ TA1 interrupt vector
-
-TA2CTL=\$400! \ TA2 control
-TA2CCTL0=\$402! \ Capture/compare control 0
-TA2CCTL1=\$404! \ Capture/compare control 1
-TA2R=\$410! \ TA2 counter register
-TA2CCR0=\$412! \ Capture/compare register 0
-TA2CCR1=\$414! \ Capture/compare register 1
-TA2EX0=\$420! \ TA2 expansion register 0
-TA2IV=\$42E! \ TA2 interrupt vector
-
-TA3CTL=\$440! \ TA3 control
-TA3CCTL0=\$442! \ Capture/compare control 0
-TA3CCTL1=\$444! \ Capture/compare control 1
-TA3R=\$450! \ TA3 counter register
-TA3CCR0=\$452! \ Capture/compare register 0
-TA3CCR1=\$454! \ Capture/compare register 1
-TA3EX0=\$460! \ TA3 expansion register 0
-TA3IV=\$46E! \ TA3 interrupt vector
-
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-
-
-UCA0CTLW0=\$500! \ eUSCI_A control word 0
-UCA0CTLW1=\$502! \ eUSCI_A control word 1
-UCA0BRW=\$506!
-UCA0BR0=\$506! \ eUSCI_A baud rate 0
-UCA0BR1=\$507! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$508! \ eUSCI_A modulation control
-UCA0STAT=\$50A! \ eUSCI_A status
-UCA0RXBUF=\$50C! \ eUSCI_A receive buffer
-UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$510! \ eUSCI_A LIN control
-UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control
-UCA0IE=\$51A! \ eUSCI_A interrupt enable
-UCA0IFG=\$51C! \ eUSCI_A interrupt flags
-UCA0IV=\$51E! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$520! \ eUSCI_A control word 0
-UCA1CTLW1=\$522! \ eUSCI_A control word 1
-UCA1BRW=\$526!
-UCA1BR0=\$526! \ eUSCI_A baud rate 0
-UCA1BR1=\$527! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$528! \ eUSCI_A modulation control
-UCA1STAT=\$52A! \ eUSCI_A status
-UCA1RXBUF=\$52C! \ eUSCI_A receive buffer
-UCA1TXBUF=\$52E! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$530! \ eUSCI_A LIN control
-UCA1IRTCTL=\$532! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$533! \ eUSCI_A IrDA receive control
-UCA1IE=\$53A! \ eUSCI_A interrupt enable
-UCA1IFG=\$53C! \ eUSCI_A interrupt flags
-UCA1IV=\$53E! \ eUSCI_A interrupt vector word
-
-
-UCB0CTLW0=\$540! \ eUSCI_B control word 0
-UCB0CTLW1=\$542! \ eUSCI_B control word 1
-UCB0BRW=\$546!
-UCB0BR0=\$546! \ eUSCI_B bit rate 0
-UCB0BR1=\$547! \ eUSCI_B bit rate 1
-UCB0STATW=\$548! \ eUSCI_B status word
-UCBCNT0=\$549! \ eUSCI_B hardware count
-UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$54C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$55C! \ eUSCI_B received address
-UCB0ADDMASK=\$55E! \ eUSCI_B address mask
-UCB0I2CSA=\$560! \ eUSCI I2C slave address
-UCB0IE=\$56A! \ eUSCI interrupt enable
-UCB0IFG=\$56C! \ eUSCI interrupt flags
-UCB0IV=\$56E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-
-BAKMEM0=\$660! \ Backup Memory 0
-BAKMEM1=\$662! \ Backup Memory 1
-BAKMEM2=\$664! \ Backup Memory 2
-BAKMEM3=\$666! \ Backup Memory 3
-BAKMEM4=\$668! \ Backup Memory 4
-BAKMEM5=\$66A! \ Backup Memory 5
-BAKMEM6=\$66C! \ Backup Memory 6
-BAKMEM7=\$66E! \ Backup Memory 7
-BAKMEM8=\$670! \ Backup Memory 8
-BAKMEM9=\$672! \ Backup Memory 9
-BAKMEM10=\$674! \ Backup Memory 10
-BAKMEM11=\$676! \ Backup Memory 11
-BAKMEM12=\$678! \ Backup Memory 12
-BAKMEM13=\$67A! \ Backup Memory 13
-BAKMEM14=\$67C! \ Backup Memory 14
-BAKMEM15=\$67E! \ Backup Memory 15
-
-
-ADC10CTL0=\$700! \ ADC10_B Control register 0
-ADC10CTL1=\$702! \ ADC10_B Control register 1
-ADC10CTL2=\$704! \ ADC10_B Control register 2
-ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold
-ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold
-ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0
-ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register
-ADC10IE=\$71A! \ ADC10_B Interrupt Enable
-ADC10IFG=\$71C! \ ADC10_B Interrupt Flags
-ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word
-
-ADCON=\$10!
-ADCSTART=\$03!
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430FR2633.pat
+
+; ----------------------------------------------
+; MSP430FR2633 MEMORY MAP
+; ----------------------------------------------
+; 0000-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL1 (4x512 B)
+; 1800-19FF = info B (FRAM 512 B)
+; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
+; 2000-2FFF = RAM (4 KB)
+; 4000-6FFF = ROM captivate (12 k)
+; C400-FF7F = code memory (FRAM 15232 B)
+; FF80-FFFF = interrupt vectors (FRAM 128 B)
+; FFC00-FFFFF = BSL2 (2k)
+; ----------------------------------------------
+;PAGESIZE .equ 512 ; MPU unit
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+BSL2=\$FFC00;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG =\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$2000;
+RAM_LEN=\$1000;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ---------------------------------------
+; FastForth RAM memory map (>= 1k):
+; ---------------------------------------
+LEAVEPTR=\$2000; Leave-stack pointer, init by QUIT
+LSATCK=\$2000; leave stack, grow up
+PSTACK=\$2080; parameter stack, grow down
+RSTACK=\$20E0; Return stack, grow down
+;
+PAD_I2CADR=\$20E0; RX I2C address
+PAD_I2CCNT=\$20E2; count max
+PAD_ORG=\$20E4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$2138; TX I2C address
+TIB_I2CCNT=\$213A; count of bytes
+TIB_ORG=\$213C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$2190; base address for HOLDS
+HOLD_BASE=\$21B2; BASE HOLD area, grow down
+;
+HP=\$21B2; HOLD ptr
+STATEADR=\$21B4; Interpreter state
+BASEADR=\$21B6; base
+CAPS=\$21B8; CAPS ON/OFF
+SOURCE_LEN=\$21BA; len of input stream
+SOURCE_ORG=\$21BC; adr of input stream
+TOIN=\$21BE; >IN
+;
+DP=\$21C0; dictionary ptr
+LASTVOC=\$21C2; keep VOC-LINK
+CURRENT=\$21C4; CURRENT dictionnary ptr
+CONTEXT=\$21C6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$21D8;
+LAST_THREAD=\$21DA;
+LAST_CFA=\$21DC;
+LAST_PSP=\$21DE;
+ASMBW1=\$21E0; 3 backward labels
+ASMBW2=\$21E2;
+ASMBW3=\$21E4;
+ASMFW1=\$21E6; 3 forward labels
+ASMFW2=\$21E8;
+ASMFW3=\$21EA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$21FC;
+SD_BUF_I2CNT=\$21FE;
+SD_BUF=\$2200; \ SD_Card buffer
+BUFEND=\$2400;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2402;
+BS_FirstSectorL=\$2404;
+BS_FirstSectorH=\$2406;
+OrgFAT1=\$2408;
+FATSize=\$240A;
+OrgFAT2=\$240C;
+OrgRootDir=\$240E;
+OrgClusters=\$2410; Sector of Cluster 0
+SecPerClus=\$2412;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2414; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2414; CRC:ll word access
+SD_CMD_FRM1=\$2415; ll byte access
+SD_CMD_FRM2=\$2416; LL:hh word access
+SD_CMD_FRM3=\$2417; hh byte access
+SD_CMD_FRM4=\$2418; HH:CMD word access
+SD_CMD_FRM5=\$2419; CMD byte access
+SectorL=\$241A; 2 words
+SectorH=\$241C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$241E;
+BufferLen=\$2420;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2422; 16 bits wide (FAT16)
+ClusterH=\$2424; 16 bits wide (FAT16)
+LastFATsector=\$2426; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2428; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$242A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$242C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$242E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2430;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2432; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2434;
+EndOfPath=\$2436;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2438;
+HandleEnd=\$2518;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2518;
+SDIB_I2CCNT=\$251A;
+SDIB_ORG=\$251C;
+
+SD_END=\$2570;
+SD_LEN=\$16E;
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$C400; Code space start
+; ----------------------------------------------
+\#LIT=\#\$C400; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$C414; asm CODE run time of QUOTE
+\#MUSMOD=\#\$C428; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$C43A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$C442; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$C46C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$C46E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$C47E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$C48A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$C496; CODE compiled by IF UNTIL
+\#BRAN=\#\$C49C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$C49E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$C4A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$C4AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$C4BA;
+\#ABORT_TERM=\#\$C500; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$C572; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$C55C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR2633
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFD8; FFD8-FFFF
+VECT_LEN=\$28;
+
+CAPTIVATE_VEC=\$FFD8;
+P2_VEC=\$FFDA;
+P1_VEC=\$FFDC;
+ADC10_B_VEC=\$FFDE;
+EUSCI_B0_VEC=\$FFE0;
+EUSCI_A1_VEC=\$FFE2;
+EUSCI_A0_VEC=\$FFE4;
+WDT_VEC=\$FFE6;
+RTC_VEC=\$FFE8;
+TA3_X_VEC=\$FFEA;
+TA3_0_VEC=\$FFEC;
+TA2_X_VEC=\$FFEE;
+TA2_0_VEC=\$FFF0;
+TA1_X_VEC=\$FFF2;
+TA1_0_VEC=\$FFF4;
+TA0_X_VEC=\$FFF6;
+TA0_0_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMCTL1=\$122; \ PMM Control 0
+PMMCTL2=\$124; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+SYSCTL=\$140; \ System control
+SYSBSLC=\$142; \ Bootstrap loader configuration area
+SYSJMBC=\$146; \ JTAG mailbox control
+SYSJMBI0=\$148; \ JTAG mailbox input 0
+SYSJMBI1=\$14A; \ JTAG mailbox input 1
+SYSJMBO0=\$14C; \ JTAG mailbox output 0
+SYSJMBO1=\$14E; \ JTAG mailbox output 1
+SYSUNIV=\$15A; \ User NMI vector generator
+SYSSNIV=\$15C; \ System NMI vector generator
+SYSRSTIV=\$15E; \ Reset vector generator
+SYSCFG0=\$160; \ System configuration 0
+SYSCFG1=\$162; \ System configuration 1
+SYSCFG2=\$164; \ System configuration 2
+
+CSCTL0=\$180; \ CS control 0
+CSCTL1=\$182; \ CS control 1
+CSCTL2=\$184; \ CS control 2
+CSCTL3=\$186; \ CS control 3
+CSCTL4=\$188; \ CS control 4
+CSCTL5=\$18A; \ CS control 5
+CSCTL6=\$18C; \ CS control 6
+CSCTL7=\$18E; \ CS control 7
+CSCTL8=\$190; \ CS control 8
+
+
+FRCTLCTL0=\$1A0; \ FRAM control 0
+GCCTL0=\$1A4; \ General control 0
+GCCTL1=\$1A6; \ General control 1
+
+CRC16DI=\$1C0; \ CRC data input
+CRCDIRB=\$1C2; \ CRC data input reverse byte
+CRCINIRES=\$1C4; \ CRC initialization and result
+CRCRESR=\$1C6; \ CRC result reverse byte
+
+WDTCTL=\$1CC; \ WDT control register
+
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+
+
+RTCCTL=\$300; \ RTC control
+RTCIV=\$304; \ RTC interrupt vector word
+RTCMOD=\$308; \ RTC modulo
+RTCCNT=\$30C; \ RTC counter register
+
+
+TACLR=4;
+TAIFG=1;
+CCIFG=1;
+
+TA0CTL=\$380; \ TA0 control
+TA0CCTL0=\$382; \ Capture/compare control 0
+TA0CCTL1=\$384; \ Capture/compare control 1
+TA0CCTL2=\$386; \ Capture/compare control 2
+TA0R=\$390; \ TA0 counter register
+TA0CCR0=\$392; \ Capture/compare register 0
+TA0CCR1=\$394; \ Capture/compare register 1
+TA0CCR2=\$396; \ Capture/compare register 2
+TA0EX0=\$3A0; \ TA0 expansion register 0
+TA0IV=\$3AE; \ TA0 interrupt vector
+
+TA1CTL=\$3C0; \ TA1 control
+TA1CCTL0=\$3C2; \ Capture/compare control 0
+TA1CCTL1=\$3C4; \ Capture/compare control 1
+TA1CCTL2=\$3C6; \ Capture/compare control 2
+TA1R=\$3D0; \ TA1 counter register
+TA1CCR0=\$3D2; \ Capture/compare register 0
+TA1CCR1=\$3D4; \ Capture/compare register 1
+TA1CCR2=\$3D6; \ Capture/compare register 2
+TA1EX0=\$3E0; \ TA1 expansion register 0
+TA1IV=\$3EE; \ TA1 interrupt vector
+
+TA2CTL=\$400; \ TA2 control
+TA2CCTL0=\$402; \ Capture/compare control 0
+TA2CCTL1=\$404; \ Capture/compare control 1
+TA2R=\$410; \ TA2 counter register
+TA2CCR0=\$412; \ Capture/compare register 0
+TA2CCR1=\$414; \ Capture/compare register 1
+TA2EX0=\$420; \ TA2 expansion register 0
+TA2IV=\$42E; \ TA2 interrupt vector
+
+TA3CTL=\$440; \ TA3 control
+TA3CCTL0=\$442; \ Capture/compare control 0
+TA3CCTL1=\$444; \ Capture/compare control 1
+TA3R=\$450; \ TA3 counter register
+TA3CCR0=\$452; \ Capture/compare register 0
+TA3CCR1=\$454; \ Capture/compare register 1
+TA3EX0=\$460; \ TA3 expansion register 0
+TA3IV=\$46E; \ TA3 interrupt vector
+
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+
+
+UCA0CTLW0=\$500; \ eUSCI_A control word 0
+UCA0CTLW1=\$502; \ eUSCI_A control word 1
+UCA0BRW=\$506;
+UCA0BR0=\$506; \ eUSCI_A baud rate 0
+UCA0BR1=\$507; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$508; \ eUSCI_A modulation control
+UCA0STAT=\$50A; \ eUSCI_A status
+UCA0RXBUF=\$50C; \ eUSCI_A receive buffer
+UCA0TXBUF=\$50E; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$510; \ eUSCI_A LIN control
+UCA0IRTCTL=\$512; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$513; \ eUSCI_A IrDA receive control
+UCA0IE=\$51A; \ eUSCI_A interrupt enable
+UCA0IFG=\$51C; \ eUSCI_A interrupt flags
+UCA0IV=\$51E; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$520; \ eUSCI_A control word 0
+UCA1CTLW1=\$522; \ eUSCI_A control word 1
+UCA1BRW=\$526;
+UCA1BR0=\$526; \ eUSCI_A baud rate 0
+UCA1BR1=\$527; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$528; \ eUSCI_A modulation control
+UCA1STAT=\$52A; \ eUSCI_A status
+UCA1RXBUF=\$52C; \ eUSCI_A receive buffer
+UCA1TXBUF=\$52E; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$530; \ eUSCI_A LIN control
+UCA1IRTCTL=\$532; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$533; \ eUSCI_A IrDA receive control
+UCA1IE=\$53A; \ eUSCI_A interrupt enable
+UCA1IFG=\$53C; \ eUSCI_A interrupt flags
+UCA1IV=\$53E; \ eUSCI_A interrupt vector word
+
+
+UCB0CTLW0=\$540; \ eUSCI_B control word 0
+UCB0CTLW1=\$542; \ eUSCI_B control word 1
+UCB0BRW=\$546;
+UCB0BR0=\$546; \ eUSCI_B bit rate 0
+UCB0BR1=\$547; \ eUSCI_B bit rate 1
+UCB0STATW=\$548; \ eUSCI_B status word
+UCBCNT0=\$549; \ eUSCI_B hardware count
+UCB0TBCNT=\$54A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$54C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$54E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$554; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$556; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$558; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$55A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$55C; \ eUSCI_B received address
+UCB0ADDMASK=\$55E; \ eUSCI_B address mask
+UCB0I2CSA=\$560; \ eUSCI I2C slave address
+UCB0IE=\$56A; \ eUSCI interrupt enable
+UCB0IFG=\$56C; \ eUSCI interrupt flags
+UCB0IV=\$56E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+
+BAKMEM0=\$660; \ Backup Memory 0
+BAKMEM1=\$662; \ Backup Memory 1
+BAKMEM2=\$664; \ Backup Memory 2
+BAKMEM3=\$666; \ Backup Memory 3
+BAKMEM4=\$668; \ Backup Memory 4
+BAKMEM5=\$66A; \ Backup Memory 5
+BAKMEM6=\$66C; \ Backup Memory 6
+BAKMEM7=\$66E; \ Backup Memory 7
+BAKMEM8=\$670; \ Backup Memory 8
+BAKMEM9=\$672; \ Backup Memory 9
+BAKMEM10=\$674; \ Backup Memory 10
+BAKMEM11=\$676; \ Backup Memory 11
+BAKMEM12=\$678; \ Backup Memory 12
+BAKMEM13=\$67A; \ Backup Memory 13
+BAKMEM14=\$67C; \ Backup Memory 14
+BAKMEM15=\$67E; \ Backup Memory 15
+
+
+ADC10CTL0=\$700; \ ADC10_B Control register 0
+ADC10CTL1=\$702; \ ADC10_B Control register 1
+ADC10CTL2=\$704; \ ADC10_B Control register 2
+ADC10LO=\$706; \ ADC10_B Window Comparator Low Threshold
+ADC10HI=\$708; \ ADC10_B Window Comparator High Threshold
+ADC10MCTL0=\$70A; \ ADC10_B Memory Control Register 0
+ADC10MEM0=\$712; \ ADC10_B Conversion Memory Register
+ADC10IE=\$71A; \ ADC10_B Interrupt Enable
+ADC10IFG=\$71C; \ ADC10_B Interrupt Flags
+ADC10IV=\$71E; \ ADC10_B Interrupt Vector Word
+
+ADCON=\$10;
+ADCSTART=\$03;
--- /dev/null
+
+@set-syntax{C;\;}! tell GEMA to replace default Comment separator '!' by ';'
+;MSP430fr2xxx.pat
+; ============================================
+; RAM area cleared by any PUC event
+; ============================================
+; RAM_ORG=\$2000;
+;
+; ----------------------------------------------
+; FastForth RAM memory map:
+; ----------------------------------------------
+LEAVEPTR=\$2000; Leave-stack pointer, init by QUIT
+LSATCK=\$2000; leave stack, grow up
+PSTACK=\$2080; parameter stack, grow down
+RSTACK=\$20E0; Return stack, grow down
+;
+PAD_I2CADR=\$20E0; RX I2C address
+PAD_I2CCNT=\$20E2; count max
+PAD_ORG=\$20E4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$2138; TX I2C address
+TIB_I2CCNT=\$213A; count of bytes
+TIB_ORG=\$213C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$2190; base address for HOLDS
+HOLD_BASE=\$21B2; BASE HOLD area, grow down
+;
+HP=\$21B2; HOLD ptr
+STATEADR=\$21B4; Interpreter state
+BASEADR=\$21B6; base
+CAPS=\$21B8; CAPS ON/OFF
+SOURCE_LEN=\$21BA; len of input stream
+SOURCE_ORG=\$21BC; adr of input stream
+TOIN=\$21BE; >IN
+;
+DP=\$21C0; dictionary ptr
+LASTVOC=\$21C2; keep VOC-LINK
+CURRENT=\$21C4; CURRENT dictionnary ptr
+CONTEXT=\$21C6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$21D8;
+LAST_THREAD=\$21DA;
+LAST_CFA=\$21DC;
+LAST_PSP=\$21DE;
+ASMBW1=\$21E0; 3 backward labels
+ASMBW2=\$21E2;
+ASMBW3=\$21E4;
+ASMFW1=\$21E6; 3 forward labels
+ASMFW2=\$21E8;
+ASMFW3=\$21EA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$21FC;
+SD_BUF_I2CNT=\$21FE;
+SD_BUF=\$2200; \ SD_Card buffer
+SD_BUF_END=\$2400;
+;
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2402;
+BS_FirstSectorL=\$2404;
+BS_FirstSectorH=\$2406;
+OrgFAT1=\$2408;
+FATSize=\$240A;
+OrgFAT2=\$240C;
+OrgRootDir=\$240E;
+OrgClusters=\$2410; Sector of Cluster 0
+SecPerClus=\$2412;
+;
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2414; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2414; CRC:ll word access
+SD_CMD_FRM1=\$2415; ll byte access
+SD_CMD_FRM2=\$2416; LL:hh word access
+SD_CMD_FRM3=\$2417; hh byte access
+SD_CMD_FRM4=\$2418; HH:CMD word access
+SD_CMD_FRM5=\$2419; CMD byte access
+SectorL=\$241A; 2 words
+SectorH=\$241C;
+;
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$241E;
+BufferLen=\$2420;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2422; 16 bits wide (FAT16)
+ClusterH=\$2424; 16 bits wide (FAT16)
+LastFATsector=\$2426; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2428; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$242A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$242C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$242E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2430;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2432; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2434;
+EndOfPath=\$2436;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; SD BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; CIB LEN of previous handle
+HDLW_PrevORG=26; CIB ORG of previous handle
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2438;
+HandleEnd=\$2518;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2518;
+SDIB_I2CCNT=\$251A;
+SDIB_ORG=\$251C;
+
+SD_END=\$2570;
+SD_LEN=\$16E;
+
DEVICE = "MSP430FR4133"
FR2_FAMILY
-
+FLL ; Frequency Locked Loop CLOCK
; ----------------------------------------------
; MSP430FR4133 MEMORY MAP
; ----------------------------------------------
-!MSP430FR4133.pat
-
-! ----------------------------------------------
-! MSP430FR4133 MEMORY MAP
-! ----------------------------------------------
-! 0000-0FFF = peripherals (4 KB)
-! 1000-13FF = ROM bootstrap loader BSL0.1 (2x512 B)
-! 1800-19FF = INFO 512 B
-! 1A00-1A23 = TLV device descriptor info (FRAM 35 B)
-! 2000-27FF = RAM (2 KB)
-! C400-FF7F = code memory (FRAM 15232 B)
-! FF80-FFFF = interrupt vectors (FRAM 127 B)
-! ----------------------------------------------
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG =\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! ! Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0080! !
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$2000!
-RAM_LEN=\$0800!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ---------------------------------------
-! FastForth RAM memory map (>= 1k):
-! ---------------------------------------
-LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT
-LSATCK=\$2000! leave stack, grow up
-PSTACK=\$2080! parameter stack, grow down
-RSTACK=\$20E0! Return stack, grow down
-!
-PAD_I2CADR=\$20E0! RX I2C address
-PAD_I2CCNT=\$20E2! count max
-PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$2138! TX I2C address
-TIB_I2CCNT=\$213A! count of bytes
-TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$2190! base address for HOLDS
-HOLD_BASE=\$21B2! BASE HOLD area, grow down
-!
-HP=\$21B2! HOLD ptr
-LAST_NFA=\$21B4!
-LAST_THREAD=\$21B6!
-LAST_CFA=\$21B8!
-LAST_PSP=\$21BA!
-!
-STATEADR=\$21BC! Interpreter state
-BASEADR=\$21BE!
-CAPS=\$21C0 !
-!
-SOURCE_LEN=\$21C2! len of input stream
-SOURCE_ORG=\$21C4! adr of input stream
-TOIN=\$21C6! >IN
-DP=\$21C8! dictionary ptr
-!
-LASTVOC=\$21CA! keep VOC-LINK
-CURRENT=\$21CC! CURRENT dictionnary ptr
-CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!21E0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$21FC!
-SD_BUF_I2CNT=\$21FE!
-SD_BUF=\$2200! \ SD_Card buffer
-BUFEND=\$2400!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2402!
-BS_FirstSectorL=\$2404!
-BS_FirstSectorH=\$2406!
-OrgFAT1=\$2408!
-FATSize=\$240A!
-OrgFAT2=\$240C!
-OrgRootDir=\$240E!
-OrgClusters=\$2410! Sector of Cluster 0
-SecPerClus=\$2412!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2414! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2414! CRC:ll word access
-SD_CMD_FRM1=\$2415! ll byte access
-SD_CMD_FRM2=\$2416! LL:hh word access
-SD_CMD_FRM3=\$2417! hh byte access
-SD_CMD_FRM4=\$2418! HH:CMD word access
-SD_CMD_FRM5=\$2419! CMD byte access
-SectorL=\$241A! 2 words
-SectorH=\$241C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$241E!
-BufferLen=\$2420!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2422! 16 bits wide (FAT16)
-ClusterH=\$2424! 16 bits wide (FAT16)
-LastFATsector=\$2426! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2428! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$242A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$242C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$242E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2430!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2432! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2434!
-EndOfPath=\$2436!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2438!
-HandleEnd=\$2518!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2518!
-SDIB_I2CCNT=\$251A!
-SDIB_ORG=\$251C!
-
-SD_END=\$2570!
-SD_LEN=\$16E!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$C400! Code space start
-
-SLEEP=\$C400! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$C40A! CODE compiled by LITERAL
-XSQUOTE=\$C41E! CODE compiled by S" and S_
-HEREXEC=\$C432! CODE HERE and BEGIN execute address
-MUSMOD=\$C43E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$C450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$C458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$C482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$C484! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$C494! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$C4A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$C4AC! CODE compiled by IF UNTIL
-BRAN=\$C4B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$C4B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$C4B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$C4C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$C4D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$C508! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$C512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$C554! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$C57E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$C584! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$C586! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$C544! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$C546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$C550! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$C550! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$C552! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$C57A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR4133
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFE2! FFE2-FFFF
-VECT_LEN=\$1E!
-
-LCD_VEC=\$FFE2!
-P2_VEC=\$FFE4!
-P1_VEC=\$FFE6!
-ADC10_B_VEC=\$FFE8!
-EUSCI_B0_VEC=\$FFEA!
-EUSCI_A0_VEC=\$FFEC!
-WDT_VEC=\$FFEE!
-RTC_VEC=\$FFF0!
-TA1_X_VEC=\$FFF2!
-TA1_0_VEC=\$FFF4!
-TA0_X_VEC=\$FFF6!
-TA0_0_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMCTL1=\$122! \ PMM Control 0
-PMMCTL2=\$124! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-SYSCTL=\$140! \ System control
-SYSBSLC=\$142! \ Bootstrap loader configuration area
-SYSJMBC=\$146! \ JTAG mailbox control
-SYSJMBI0=\$148! \ JTAG mailbox input 0
-SYSJMBI1=\$14A! \ JTAG mailbox input 1
-SYSJMBO0=\$14C! \ JTAG mailbox output 0
-SYSJMBO1=\$14E! \ JTAG mailbox output 1
-SYSUNIV=\$15A! \ User NMI vector generator
-SYSSNIV=\$15C! \ System NMI vector generator
-SYSRSTIV=\$15E! \ Reset vector generator
-SYSCFG0=\$160! \ System configuration 0
-SYSCFG1=\$162! \ System configuration 1
-SYSCFG2=\$164! \ System configuration 2
-
-CSCTL0=\$180! \ CS control 0
-CSCTL1=\$182! \ CS control 1
-CSCTL2=\$184! \ CS control 2
-CSCTL3=\$186! \ CS control 3
-CSCTL4=\$188! \ CS control 4
-CSCTL5=\$18A! \ CS control 5
-CSCTL6=\$18C! \ CS control 6
-CSCTL7=\$18E! \ CS control 7
-CSCTL8=\$190! \ CS control 8
-
-
-FRCTLCTL0=\$1A0! \ FRAM control 0
-GCCTL0=\$1A4! \ General control 0
-GCCTL1=\$1A6! \ General control 1
-
-CRC16DI=\$1C0! \ CRC data input
-CRCDIRB=\$1C2! \ CRC data input reverse byte
-CRCINIRES=\$1C4! \ CRC initialization and result
-CRCRESR=\$1C6! \ CRC result reverse byte
-
-WDTCTL=\$1CC! \ WDT control register
-
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-PBIN=\$220!
-PBOUT=\$222!
-PBDIR=\$224!
-PBREN=\$226!
-PBSEL0=\$22A!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-
-PCIN=\$240!
-PCOUT=\$242!
-PCDIR=\$244!
-PCREN=\$246!
-PCSEL0=\$24A!
-PCSEL1=\$24C!
-
-P5IN=\$240!
-P5OUT=\$242!
-P5DIR=\$244!
-P5REN=\$246!
-P5SEL0=\$24A!
-
-P6IN=\$241!
-P6OUT=\$243!
-P6DIR=\$245!
-P6REN=\$247!
-
-PDIN=\$260!
-PDOUT=\$262!
-PDDIR=\$264!
-PDREN=\$266!
-PDSEL0=\$26A!
-
-P7IN=\$260!
-P7OUT=\$262!
-P7DIR=\$264!
-P7REN=\$266!
-
-P8IN=\$261!
-P8OUT=\$263!
-P8DIR=\$265!
-P8REN=\$267!
-P8SEL0=\$26B!
-
-CAPTIO0CTL=\$2EE! \ Capacitive Touch IO 0 control
-
-
-
-TACLR=4!
-TAIFG=1!
-CCIFG=1!
-
-TA0CTL=\$300! \ TA0 control
-TA0CCTL0=\$302! \ Capture/compare control 0
-TA0CCTL1=\$304! \ Capture/compare control 1
-TA0CCTL2=\$306! \ Capture/compare control 2
-TA0R=\$310! \ TA0 counter register
-TA0CCR0=\$312! \ Capture/compare register 0
-TA0CCR1=\$314! \ Capture/compare register 1
-TA0CCR2=\$316! \ Capture/compare register 2
-TA0EX0=\$320! \ TA0 expansion register 0
-TA0IV=\$32E! \ TA0 interrupt vector
-
-TA1CTL=\$340! \ TA1 control
-TA1CCTL0=\$342! \ Capture/compare control 0
-TA1CCTL1=\$344! \ Capture/compare control 1
-TA1CCTL2=\$346! \ Capture/compare control 2
-TA1R=\$350! \ TA1 counter register
-TA1CCR0=\$352! \ Capture/compare register 0
-TA1CCR1=\$354! \ Capture/compare register 1
-TA1CCR2=\$356! \ Capture/compare register 2
-TA1EX0=\$360! \ TA1 expansion register 0
-TA1IV=\$36E! \ TA1 interrupt vector
-
-RTCCTL=\$3C0! \ RTC control
-RTCIV=\$3C4! \ RTC interrupt vector word
-RTCMOD=\$3C8! \ RTC modulo
-RTCCNT=\$3CC! \ RTC counter register
-
-
-UCA0CTLW0=\$500! \ eUSCI_A control word 0
-UCA0CTLW1=\$502! \ eUSCI_A control word 1
-UCA0BRW=\$506!
-UCA0BR0=\$506! \ eUSCI_A baud rate 0
-UCA0BR1=\$507! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$508! \ eUSCI_A modulation control
-UCA0STAT=\$50A! \ eUSCI_A status
-UCA0RXBUF=\$50C! \ eUSCI_A receive buffer
-UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$510! \ eUSCI_A LIN control
-UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control
-UCA0IE=\$51A! \ eUSCI_A interrupt enable
-UCA0IFG=\$51C! \ eUSCI_A interrupt flags
-UCA0IV=\$51E! \ eUSCI_A interrupt vector word
-
-
-UCB0CTLW0=\$540! \ eUSCI_B control word 0
-UCB0CTLW1=\$542! \ eUSCI_B control word 1
-UCB0BRW=\$546!
-UCB0BR0=\$546! \ eUSCI_B bit rate 0
-UCB0BR1=\$547! \ eUSCI_B bit rate 1
-UCB0STATW=\$548! \ eUSCI_B status word
-UCBCNT0=\$549! \ eUSCI_B hardware count
-UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$54C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$55C! \ eUSCI_B received address
-UCB0ADDMASK=\$55E! \ eUSCI_B address mask
-UCB0I2CSA=\$560! \ eUSCI I2C slave address
-UCB0IE=\$56A! \ eUSCI interrupt enable
-UCB0IFG=\$56C! \ eUSCI interrupt flags
-UCB0IV=\$56E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-LCDCTL0=\$600! \ LCD control register 0
-LCDCTL1=\$602! \ LCD control register 1
-LCDBLKCTL=\$604! \ LCD blink control register
-LCDMEMCTL=\$606! \ LCD memory control register
-LCDVCTL=\$608! \ LCD voltage control register
-LCDPCTL0=\$60A! \ LCD port control 0
-LCDPCTL1=\$60C! \ LCD port control 1
-LCDPCTL2=\$60E! \ LCD port control 2
-LCDCSS0=\$614! \ LCD COM/SEG select register
-LCDCSS1=\$616! \ LCD COM/SEG select register
-LCDCSS2=\$618! \ LCD COM/SEG select register
-LCDIV=\$61E! \ LCD interrupt vector
-LCDM0=\$620! \ LCD memory 0
-LCDM1=\$621! \ LCD memory 1
-LCDM2=\$622! \ LCD memory 2
-LCDM3=\$623! \ LCD memory 3
-LCDM4=\$624! \ LCD memory 4
-LCDM5=\$625! \ LCD memory 5
-LCDM6=\$626! \ LCD memory 6
-LCDM7=\$627! \ LCD memory 7
-LCDM8=\$628! \ LCD memory 8
-LCDM9=\$629! \ LCD memory 9
-LCDM10=\$62A! \ LCD memory 10
-LCDM11=\$62B! \ LCD memory 11
-LCDM12=\$62C! \ LCD memory 12
-LCDM13=\$62D! \ LCD memory 13
-LCDM14=\$62E! \ LCD memory 14
-LCDM15=\$62F! \ LCD memory 15
-LCDM16=\$630! \ LCD memory 16
-LCDM17=\$631! \ LCD memory 17
-LCDM18=\$632! \ LCD memory 18
-LCDM19=\$633! \ LCD memory 19
-LCDM20=\$634! \ LCD memory 20
-LCDM21=\$635! \ LCD memory 21
-LCDM22=\$636! \ LCD memory 22
-LCDM23=\$637! \ LCD memory 23
-LCDM24=\$638! \ LCD memory 24
-LCDM25=\$639! \ LCD memory 25
-LCDM26=\$63A! \ LCD memory 26
-LCDM27=\$63B! \ LCD memory 27
-LCDM28=\$63C! \ LCD memory 28
-LCDM29=\$63D! \ LCD memory 29
-LCDM30=\$63E! \ LCD memory 30
-LCDM31=\$63F! \ LCD memory 31
-LCDM32=\$640! \ LCD memory 32
-LCDM33=\$641! \ LCD memory 33
-LCDM34=\$642! \ LCD memory 34
-LCDM35=\$643! \ LCD memory 35
-LCDM36=\$644! \ LCD memory 36
-LCDM37=\$645! \ LCD memory 37
-LCDM38=\$646! \ LCD memory 38
-LCDM39=\$647! \ LCD memory 39
-LCDBM0=\$640! \ LCD blinking memory 0
-LCDBM1=\$641! \ LCD blinking memory 1
-LCDBM2=\$642! \ LCD blinking memory 2
-LCDBM3=\$643! \ LCD blinking memory 3
-LCDBM4=\$644! \ LCD blinking memory 4
-LCDBM5=\$645! \ LCD blinking memory 5
-LCDBM6=\$646! \ LCD blinking memory 6
-LCDBM7=\$647! \ LCD blinking memory 7
-LCDBM8=\$648! \ LCD blinking memory 8
-LCDBM9=\$649! \ LCD blinking memory 9
-LCDBM10=\$64A! \ LCD blinking memory 10
-LCDBM11=\$64B! \ LCD blinking memory 11
-LCDBM12=\$64C! \ LCD blinking memory 12
-LCDBM13=\$64D! \ LCD blinking memory 13
-LCDBM14=\$64E! \ LCD blinking memory 14
-LCDBM15=\$64F! \ LCD blinking memory 15
-LCDBM16=\$650! \ LCD blinking memory 16
-LCDBM17=\$651! \ LCD blinking memory 17
-LCDBM18=\$652! \ LCD blinking memory 18
-LCDBM19=\$653! \ LCD blinking memory 19
-
-
-BAKMEM0=\$660! \ Backup Memory 0
-BAKMEM1=\$662! \ Backup Memory 1
-BAKMEM2=\$664! \ Backup Memory 2
-BAKMEM3=\$666! \ Backup Memory 3
-BAKMEM4=\$668! \ Backup Memory 4
-BAKMEM5=\$66A! \ Backup Memory 5
-BAKMEM6=\$66C! \ Backup Memory 6
-BAKMEM7=\$66E! \ Backup Memory 7
-BAKMEM8=\$670! \ Backup Memory 8
-BAKMEM9=\$672! \ Backup Memory 9
-BAKMEM10=\$674! \ Backup Memory 10
-BAKMEM11=\$676! \ Backup Memory 11
-BAKMEM12=\$678! \ Backup Memory 12
-BAKMEM13=\$67A! \ Backup Memory 13
-BAKMEM14=\$67C! \ Backup Memory 14
-BAKMEM15=\$67E! \ Backup Memory 15
-
-
-
-ADC10CTL0=\$700! \ ADC10_B Control register 0
-ADC10CTL1=\$702! \ ADC10_B Control register 1
-ADC10CTL2=\$704! \ ADC10_B Control register 2
-ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold
-ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold
-ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0
-ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register
-ADC10IE=\$71A! \ ADC10_B Interrupt Enable
-ADC10IFG=\$71C! \ ADC10_B Interrupt Flags
-ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word
-
-ADCON=\$10!
-ADCSTART=\$03!
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430FR4133.pat
+
+; ----------------------------------------------
+; MSP430FR4133 MEMORY MAP
+; ----------------------------------------------
+; 0000-0FFF = peripherals (4 KB)
+; 1000-13FF = ROM bootstrap loader BSL0.1 (2x512 B)
+; 1800-19FF = INFO 512 B
+; 1A00-1A23 = TLV device descriptor info (FRAM 35 B)
+; 2000-27FF = RAM (2 KB)
+; C400-FF7F = code memory (FRAM 15232 B)
+; FF80-FFFF = interrupt vectors (FRAM 127 B)
+; ----------------------------------------------
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG =\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$2000;
+RAM_LEN=\$0800;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ---------------------------------------
+; FastForth RAM memory map (>= 1k):
+; ---------------------------------------
+LEAVEPTR=\$2000; Leave-stack pointer, init by QUIT
+LSATCK=\$2000; leave stack, grow up
+PSTACK=\$2080; parameter stack, grow down
+RSTACK=\$20E0; Return stack, grow down
+;
+PAD_I2CADR=\$20E0; RX I2C address
+PAD_I2CCNT=\$20E2; count max
+PAD_ORG=\$20E4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$2138; TX I2C address
+TIB_I2CCNT=\$213A; count of bytes
+TIB_ORG=\$213C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$2190; base address for HOLDS
+HOLD_BASE=\$21B2; BASE HOLD area, grow down
+;
+HP=\$21B2; HOLD ptr
+STATEADR=\$21B4; Interpreter state
+BASEADR=\$21B6; base
+CAPS=\$21B8; CAPS ON/OFF
+SOURCE_LEN=\$21BA; len of input stream
+SOURCE_ORG=\$21BC; adr of input stream
+TOIN=\$21BE; >IN
+;
+DP=\$21C0; dictionary ptr
+LASTVOC=\$21C2; keep VOC-LINK
+CURRENT=\$21C4; CURRENT dictionnary ptr
+CONTEXT=\$21C6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$21D8;
+LAST_THREAD=\$21DA;
+LAST_CFA=\$21DC;
+LAST_PSP=\$21DE;
+ASMBW1=\$21E0; 3 backward labels
+ASMBW2=\$21E2;
+ASMBW3=\$21E4;
+ASMFW1=\$21E6; 3 forward labels
+ASMFW2=\$21E8;
+ASMFW3=\$21EA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$21FC;
+SD_BUF_I2CNT=\$21FE;
+SD_BUF=\$2200; \ SD_Card buffer
+BUFEND=\$2400;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2402;
+BS_FirstSectorL=\$2404;
+BS_FirstSectorH=\$2406;
+OrgFAT1=\$2408;
+FATSize=\$240A;
+OrgFAT2=\$240C;
+OrgRootDir=\$240E;
+OrgClusters=\$2410; Sector of Cluster 0
+SecPerClus=\$2412;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2414; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2414; CRC:ll word access
+SD_CMD_FRM1=\$2415; ll byte access
+SD_CMD_FRM2=\$2416; LL:hh word access
+SD_CMD_FRM3=\$2417; hh byte access
+SD_CMD_FRM4=\$2418; HH:CMD word access
+SD_CMD_FRM5=\$2419; CMD byte access
+SectorL=\$241A; 2 words
+SectorH=\$241C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$241E;
+BufferLen=\$2420;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2422; 16 bits wide (FAT16)
+ClusterH=\$2424; 16 bits wide (FAT16)
+LastFATsector=\$2426; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2428; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$242A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$242C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$242E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2430;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2432; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2434;
+EndOfPath=\$2436;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2438;
+HandleEnd=\$2518;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2518;
+SDIB_I2CCNT=\$251A;
+SDIB_ORG=\$251C;
+
+SD_END=\$2570;
+SD_LEN=\$16E;
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$C400; Code space start
+; ----------------------------------------------
+\#LIT=\#\$C400; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$C414; asm CODE run time of QUOTE
+\#MUSMOD=\#\$C428; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$C43A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$C442; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$C46C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$C46E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$C47E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$C48A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$C496; CODE compiled by IF UNTIL
+\#BRAN=\#\$C49C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$C49E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$C4A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$C4AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$C4BA;
+\#ABORT_TERM=\#\$C500; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$C572; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$C55C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR4133
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFE2; FFE2-FFFF
+VECT_LEN=\$1E;
+
+LCD_VEC=\$FFE2;
+P2_VEC=\$FFE4;
+P1_VEC=\$FFE6;
+ADC10_B_VEC=\$FFE8;
+EUSCI_B0_VEC=\$FFEA;
+EUSCI_A0_VEC=\$FFEC;
+WDT_VEC=\$FFEE;
+RTC_VEC=\$FFF0;
+TA1_X_VEC=\$FFF2;
+TA1_0_VEC=\$FFF4;
+TA0_X_VEC=\$FFF6;
+TA0_0_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMCTL1=\$122; \ PMM Control 0
+PMMCTL2=\$124; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+SYSCTL=\$140; \ System control
+SYSBSLC=\$142; \ Bootstrap loader configuration area
+SYSJMBC=\$146; \ JTAG mailbox control
+SYSJMBI0=\$148; \ JTAG mailbox input 0
+SYSJMBI1=\$14A; \ JTAG mailbox input 1
+SYSJMBO0=\$14C; \ JTAG mailbox output 0
+SYSJMBO1=\$14E; \ JTAG mailbox output 1
+SYSUNIV=\$15A; \ User NMI vector generator
+SYSSNIV=\$15C; \ System NMI vector generator
+SYSRSTIV=\$15E; \ Reset vector generator
+SYSCFG0=\$160; \ System configuration 0
+SYSCFG1=\$162; \ System configuration 1
+SYSCFG2=\$164; \ System configuration 2
+
+CSCTL0=\$180; \ CS control 0
+CSCTL1=\$182; \ CS control 1
+CSCTL2=\$184; \ CS control 2
+CSCTL3=\$186; \ CS control 3
+CSCTL4=\$188; \ CS control 4
+CSCTL5=\$18A; \ CS control 5
+CSCTL6=\$18C; \ CS control 6
+CSCTL7=\$18E; \ CS control 7
+CSCTL8=\$190; \ CS control 8
+
+
+FRCTLCTL0=\$1A0; \ FRAM control 0
+GCCTL0=\$1A4; \ General control 0
+GCCTL1=\$1A6; \ General control 1
+
+CRC16DI=\$1C0; \ CRC data input
+CRCDIRB=\$1C2; \ CRC data input reverse byte
+CRCINIRES=\$1C4; \ CRC initialization and result
+CRCRESR=\$1C6; \ CRC result reverse byte
+
+WDTCTL=\$1CC; \ WDT control register
+
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+PBIN=\$220;
+PBOUT=\$222;
+PBDIR=\$224;
+PBREN=\$226;
+PBSEL0=\$22A;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+
+PCIN=\$240;
+PCOUT=\$242;
+PCDIR=\$244;
+PCREN=\$246;
+PCSEL0=\$24A;
+PCSEL1=\$24C;
+
+P5IN=\$240;
+P5OUT=\$242;
+P5DIR=\$244;
+P5REN=\$246;
+P5SEL0=\$24A;
+
+P6IN=\$241;
+P6OUT=\$243;
+P6DIR=\$245;
+P6REN=\$247;
+
+PDIN=\$260;
+PDOUT=\$262;
+PDDIR=\$264;
+PDREN=\$266;
+PDSEL0=\$26A;
+
+P7IN=\$260;
+P7OUT=\$262;
+P7DIR=\$264;
+P7REN=\$266;
+
+P8IN=\$261;
+P8OUT=\$263;
+P8DIR=\$265;
+P8REN=\$267;
+P8SEL0=\$26B;
+
+CAPTIO0CTL=\$2EE; \ Capacitive Touch IO 0 control
+
+
+
+TACLR=4;
+TAIFG=1;
+CCIFG=1;
+
+TA0CTL=\$300; \ TA0 control
+TA0CCTL0=\$302; \ Capture/compare control 0
+TA0CCTL1=\$304; \ Capture/compare control 1
+TA0CCTL2=\$306; \ Capture/compare control 2
+TA0R=\$310; \ TA0 counter register
+TA0CCR0=\$312; \ Capture/compare register 0
+TA0CCR1=\$314; \ Capture/compare register 1
+TA0CCR2=\$316; \ Capture/compare register 2
+TA0EX0=\$320; \ TA0 expansion register 0
+TA0IV=\$32E; \ TA0 interrupt vector
+
+TA1CTL=\$340; \ TA1 control
+TA1CCTL0=\$342; \ Capture/compare control 0
+TA1CCTL1=\$344; \ Capture/compare control 1
+TA1CCTL2=\$346; \ Capture/compare control 2
+TA1R=\$350; \ TA1 counter register
+TA1CCR0=\$352; \ Capture/compare register 0
+TA1CCR1=\$354; \ Capture/compare register 1
+TA1CCR2=\$356; \ Capture/compare register 2
+TA1EX0=\$360; \ TA1 expansion register 0
+TA1IV=\$36E; \ TA1 interrupt vector
+
+RTCCTL=\$3C0; \ RTC control
+RTCIV=\$3C4; \ RTC interrupt vector word
+RTCMOD=\$3C8; \ RTC modulo
+RTCCNT=\$3CC; \ RTC counter register
+
+
+UCA0CTLW0=\$500; \ eUSCI_A control word 0
+UCA0CTLW1=\$502; \ eUSCI_A control word 1
+UCA0BRW=\$506;
+UCA0BR0=\$506; \ eUSCI_A baud rate 0
+UCA0BR1=\$507; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$508; \ eUSCI_A modulation control
+UCA0STAT=\$50A; \ eUSCI_A status
+UCA0RXBUF=\$50C; \ eUSCI_A receive buffer
+UCA0TXBUF=\$50E; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$510; \ eUSCI_A LIN control
+UCA0IRTCTL=\$512; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$513; \ eUSCI_A IrDA receive control
+UCA0IE=\$51A; \ eUSCI_A interrupt enable
+UCA0IFG=\$51C; \ eUSCI_A interrupt flags
+UCA0IV=\$51E; \ eUSCI_A interrupt vector word
+
+
+UCB0CTLW0=\$540; \ eUSCI_B control word 0
+UCB0CTLW1=\$542; \ eUSCI_B control word 1
+UCB0BRW=\$546;
+UCB0BR0=\$546; \ eUSCI_B bit rate 0
+UCB0BR1=\$547; \ eUSCI_B bit rate 1
+UCB0STATW=\$548; \ eUSCI_B status word
+UCBCNT0=\$549; \ eUSCI_B hardware count
+UCB0TBCNT=\$54A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$54C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$54E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$554; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$556; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$558; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$55A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$55C; \ eUSCI_B received address
+UCB0ADDMASK=\$55E; \ eUSCI_B address mask
+UCB0I2CSA=\$560; \ eUSCI I2C slave address
+UCB0IE=\$56A; \ eUSCI interrupt enable
+UCB0IFG=\$56C; \ eUSCI interrupt flags
+UCB0IV=\$56E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+LCDCTL0=\$600; \ LCD control register 0
+LCDCTL1=\$602; \ LCD control register 1
+LCDBLKCTL=\$604; \ LCD blink control register
+LCDMEMCTL=\$606; \ LCD memory control register
+LCDVCTL=\$608; \ LCD voltage control register
+LCDPCTL0=\$60A; \ LCD port control 0
+LCDPCTL1=\$60C; \ LCD port control 1
+LCDPCTL2=\$60E; \ LCD port control 2
+LCDCSS0=\$614; \ LCD COM/SEG select register
+LCDCSS1=\$616; \ LCD COM/SEG select register
+LCDCSS2=\$618; \ LCD COM/SEG select register
+LCDIV=\$61E; \ LCD interrupt vector
+LCDM0=\$620; \ LCD memory 0
+LCDM1=\$621; \ LCD memory 1
+LCDM2=\$622; \ LCD memory 2
+LCDM3=\$623; \ LCD memory 3
+LCDM4=\$624; \ LCD memory 4
+LCDM5=\$625; \ LCD memory 5
+LCDM6=\$626; \ LCD memory 6
+LCDM7=\$627; \ LCD memory 7
+LCDM8=\$628; \ LCD memory 8
+LCDM9=\$629; \ LCD memory 9
+LCDM10=\$62A; \ LCD memory 10
+LCDM11=\$62B; \ LCD memory 11
+LCDM12=\$62C; \ LCD memory 12
+LCDM13=\$62D; \ LCD memory 13
+LCDM14=\$62E; \ LCD memory 14
+LCDM15=\$62F; \ LCD memory 15
+LCDM16=\$630; \ LCD memory 16
+LCDM17=\$631; \ LCD memory 17
+LCDM18=\$632; \ LCD memory 18
+LCDM19=\$633; \ LCD memory 19
+LCDM20=\$634; \ LCD memory 20
+LCDM21=\$635; \ LCD memory 21
+LCDM22=\$636; \ LCD memory 22
+LCDM23=\$637; \ LCD memory 23
+LCDM24=\$638; \ LCD memory 24
+LCDM25=\$639; \ LCD memory 25
+LCDM26=\$63A; \ LCD memory 26
+LCDM27=\$63B; \ LCD memory 27
+LCDM28=\$63C; \ LCD memory 28
+LCDM29=\$63D; \ LCD memory 29
+LCDM30=\$63E; \ LCD memory 30
+LCDM31=\$63F; \ LCD memory 31
+LCDM32=\$640; \ LCD memory 32
+LCDM33=\$641; \ LCD memory 33
+LCDM34=\$642; \ LCD memory 34
+LCDM35=\$643; \ LCD memory 35
+LCDM36=\$644; \ LCD memory 36
+LCDM37=\$645; \ LCD memory 37
+LCDM38=\$646; \ LCD memory 38
+LCDM39=\$647; \ LCD memory 39
+LCDBM0=\$640; \ LCD blinking memory 0
+LCDBM1=\$641; \ LCD blinking memory 1
+LCDBM2=\$642; \ LCD blinking memory 2
+LCDBM3=\$643; \ LCD blinking memory 3
+LCDBM4=\$644; \ LCD blinking memory 4
+LCDBM5=\$645; \ LCD blinking memory 5
+LCDBM6=\$646; \ LCD blinking memory 6
+LCDBM7=\$647; \ LCD blinking memory 7
+LCDBM8=\$648; \ LCD blinking memory 8
+LCDBM9=\$649; \ LCD blinking memory 9
+LCDBM10=\$64A; \ LCD blinking memory 10
+LCDBM11=\$64B; \ LCD blinking memory 11
+LCDBM12=\$64C; \ LCD blinking memory 12
+LCDBM13=\$64D; \ LCD blinking memory 13
+LCDBM14=\$64E; \ LCD blinking memory 14
+LCDBM15=\$64F; \ LCD blinking memory 15
+LCDBM16=\$650; \ LCD blinking memory 16
+LCDBM17=\$651; \ LCD blinking memory 17
+LCDBM18=\$652; \ LCD blinking memory 18
+LCDBM19=\$653; \ LCD blinking memory 19
+
+
+BAKMEM0=\$660; \ Backup Memory 0
+BAKMEM1=\$662; \ Backup Memory 1
+BAKMEM2=\$664; \ Backup Memory 2
+BAKMEM3=\$666; \ Backup Memory 3
+BAKMEM4=\$668; \ Backup Memory 4
+BAKMEM5=\$66A; \ Backup Memory 5
+BAKMEM6=\$66C; \ Backup Memory 6
+BAKMEM7=\$66E; \ Backup Memory 7
+BAKMEM8=\$670; \ Backup Memory 8
+BAKMEM9=\$672; \ Backup Memory 9
+BAKMEM10=\$674; \ Backup Memory 10
+BAKMEM11=\$676; \ Backup Memory 11
+BAKMEM12=\$678; \ Backup Memory 12
+BAKMEM13=\$67A; \ Backup Memory 13
+BAKMEM14=\$67C; \ Backup Memory 14
+BAKMEM15=\$67E; \ Backup Memory 15
+
+
+
+ADC10CTL0=\$700; \ ADC10_B Control register 0
+ADC10CTL1=\$702; \ ADC10_B Control register 1
+ADC10CTL2=\$704; \ ADC10_B Control register 2
+ADC10LO=\$706; \ ADC10_B Window Comparator Low Threshold
+ADC10HI=\$708; \ ADC10_B Window Comparator High Threshold
+ADC10MCTL0=\$70A; \ ADC10_B Memory Control Register 0
+ADC10MEM0=\$712; \ ADC10_B Conversion Memory Register
+ADC10IE=\$71A; \ ADC10_B Interrupt Enable
+ADC10IFG=\$71C; \ ADC10_B Interrupt Flags
+ADC10IV=\$71E; \ ADC10_B Interrupt Vector Word
+
+ADCON=\$10;
+ADCSTART=\$03;
.listing off
DEVICE = "MSP430FR5738"
-
+HMPY ; hardware multiplier
; ----------------------------------------------
; MSP430FR5738 MEMORY MAP
; ----------------------------------------------
-!MSP430fr5738.pat
-
-! ----------------------------------------------
-! MSP430FR5738 MEMORY MAP
-! ----------------------------------------------
-! 0000-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
-! 1800-187F = info B (FRAM 128 B)
-! 1880-18FF = info A (FRAM 128 B)
-! 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
-! 1C00-1FFF = RAM (1 KB)
-! C200-FF7F = code memory (FRAM 15743 B)
-! FF80-FFFF = interrupt vectors (FRAM 127 B)
-! ----------------------------------------------
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0100!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$185A!
-BS_FirstSectorL=\$185C!
-BS_FirstSectorH=\$185E!
-OrgFAT1=\$1860!
-FATSize=\$1862!
-OrgFAT2=\$1864!
-OrgRootDir=\$1866!
-OrgClusters=\$1868! Sector of Cluster 0
-SecPerClus=\$186A!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$186C! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$186C! CRC:ll word access
-SD_CMD_FRM1=\$186D! ll byte access
-SD_CMD_FRM2=\$186E! LL:hh word access
-SD_CMD_FRM3=\$186F! hh byte access
-SD_CMD_FRM4=\$1870! HH:CMD word access
-SD_CMD_FRM5=\$1871! CMD byte access
-SectorL=\$1872! 2 words
-SectorH=\$1874!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$1876!
-BufferLen=\$1878!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$187A! 16 bits wide (FAT16)
-ClusterH=\$187C! 16 bits wide (FAT16)
-LastFATsector=\$187E! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$1880! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$1882! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$1884! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$1886! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$1888!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$188A! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$188C! address of pathname string
-EndOfPath=\$188E!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=4!
-HandleLenght=28!
-FirstHandle=\$1890!
-HandleEnd=\$1900!
-
-SD_END=\$1900!
-SD_LEN=\$A6!
-
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0080!
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$1C00!
-RAM_LEN=\$0400!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-!SD_card Input Buffer = PAD
-SDIB_I2CADR=\$1CE0!
-SDIB_I2CCNT=\$1CE2!
-SDIB_ORG=\$1CE4!
-SDIB_LEN=\$54!
-
-! ---------------------------------------
-! FastForth RAM memory map (= 1k)
-! ---------------------------------------
-LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT
-LSATCK=\$1C00! leave stack, grow up
-PSTACK=\$1C80! parameter stack, grow down
-RSTACK=\$1CE0! Return stack, grow down
-!
-PAD_I2CADR=\$1CE0! RX I2C address
-PAD_I2CCNT=\$1CE2! count max
-PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$1D38! TX I2C address
-TIB_I2CCNT=\$1D3A! count of bytes
-TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$1D90! base address for HOLDS
-HOLD_BASE=\$1DB2! BASE HOLD area, grow down
-!
-HP=\$1DB2! HOLD ptr
-LAST_NFA=\$1DB4!
-LAST_THREAD=\$1DB6!
-LAST_CFA=\$1DB8!
-LAST_PSP=\$1DBA!
-!
-STATEADR=\$1DBC! Interpreter state
-BASEADR=\$1DBE! base
-CAPS=\$1DC0! CAPS ON/OFF
-!
-SOURCE_LEN=\$1DC2! len of input stream
-SOURCE_ORG=\$1DC4! adr of input stream
-TOIN=\$1DC6! >IN
-DP=\$1DC8! dictionary ptr
-!
-LASTVOC=\$1DCA! keep VOC-LINK
-CURRENT=\$1DCC! CURRENT dictionnary ptr
-CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS)
-
-! ---------------------------------------
-!1DE0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$1DFC!
-SD_BUF_I2CNT=\$1DFE!
-SD_BUF=\$1E00! \ SD_Card buffer
-BUFEND=\$2000!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$C200! Code space start
-MAIN_LEN=\$3E00! 15.5 k FRAM
-! ----------------------------------------------
-
-SLEEP=\$C200! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$C20A! CODE compiled by LITERAL
-XSQUOTE=\$C21E! CODE compiled by S" and S_
-HEREXEC=\$C232! CODE HERE and BEGIN execute address
-MUSMOD=\$C23E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$C250! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$C258! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$C282! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$C284! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$C294! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$C2A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$C2AC! CODE compiled by IF UNTIL
-BRAN=\$C2B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$C2B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$C2B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$C2C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$C2D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$C308! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$C312! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$C354! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$C37E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$C384! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$C386! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$C344! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$C346! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$C350! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$C350! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$C352! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$C37A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR5738
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFCE! FFCE-FFFF
-VECT_LEN=\$32!
-
-
-RTC_VEC=\$FFCE!
-P4_VEC=\$FFD0!
-P3_VEC=\$FFD2!
-TB2_X_VEC=\$FFD4! All others
-TB2_0_VEC=\$FFD6! only CCIFG0
-P2_VEC=\$FFD8!
-TB1_X_VEC=\$FFDA! All others
-TB1_0_VEC=\$FFDC! only CCIFG0
-P1_VEC=\$FFDE!
-TA1_X_VEC=\$FFE0! All others
-TA1_0_VEC=\$FFE2! only CCIFG0
-DMA_VEC=\$FFE4!
-!EUSCI_A1_VEC=\$FFE6!
-TA0_X_VEC=\$FFE8! All others
-TA0_0_VEC=\$FFEA! only CCIFG0
-ADC10_B_VEC=\$FFEC!
-EUSCI_B0_VEC=\$FFEE!
-EUSCI_A0_VEC=\$FFF0!
-WDT_VEC=\$FFF2!
-TB0_X_VEC=\$FFF4! All others
-TB0_0_VEC=\$FFF6! only CCIFG0
-COMP_D_VEC=\$FFF8!
-USER_NMI_VEC=\$FFFA!
-SYS_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-FRCTLCTL0=\$140! \ FRAM control 0
-GCCTL0=\$144! \ General control 0
-GCCTL1=\$146! \ General control 1
-
-CRC16DI=\$150! \ CRC data input
-CRCDIRB=\$152! \ CRC data input reverse byte
-CRCINIRES=\$154! \ CRC initialization and result
-CRCRESR=\$156! \ CRC result reverse byte
-
-WDTCTL=\$15C! \ WDT control register
-
-CSCTL0=\$160! \ CS control 0
-CSCTL0_H=\$161! \
-CSCTL1=\$162! \ CS control 1
-CSCTL2=\$164! \ CS control 2
-CSCTL3=\$166! \ CS control 3
-CSCTL4=\$168! \ CS control 4
-CSCTL5=\$16A! \ CS control 5
-CSCTL6=\$16C! \ CS control 6
-
-SYSCTL=\$180! \ System control
-SYSJMBC=\$186! \ JTAG mailbox control
-SYSJMBI0=\$188! \ JTAG mailbox input 0
-SYSJMBI1=\$18A! \ JTAG mailbox input 1
-SYSJMBO0=\$18C! \ JTAG mailbox output 0
-SYSJMBO1=\$18E! \ JTAG mailbox output 1
-SYSBERRIV=\$198! \ Bus Error vector generator
-SYSUNIV=\$19A! \ User NMI vector generator
-SYSSNIV=\$19C! \ System NMI vector generator
-SYSRSTIV=\$19E! \ Reset vector generator
-
-REFCTL=\$1b0! \ Shared reference control
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PASELC=\$216!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1SELC=\$216!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2SELC=\$217!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-
-PJIN=\$320!
-PJOUT=\$322!
-PJDIR=\$324!
-PJREN=\$326!
-PJSEL0=\$32A!
-PJSEL1=\$32C!
-PJSELC=\$336!
-
-
-TACLR=4!
-TAIFG=1!
-TBCLR=4!
-TBIFG=1!
-CCIFG=1!
-
-TA0CTL=\$340! \ TA0 control
-TA0CCTL0=\$342! \ Capture/compare control 0
-TA0CCTL1=\$344! \ Capture/compare control 1
-TA0CCTL2=\$346! \ Capture/compare control 2
-TA0R=\$350! \ TA0 counter register
-TA0CCR0=\$352! \ Capture/compare register 0
-TA0CCR1=\$354! \ Capture/compare register 1
-TA0CCR2=\$356! \ Capture/compare register 2
-TA0EX0=\$360! \ TA0 expansion register 0
-TA0IV=\$36E! \ TA0 interrupt vector
-
-TA1CTL=\$380! \ TA1 control
-TA1CCTL0=\$382! \ Capture/compare control 0
-TA1CCTL1=\$384! \ Capture/compare control 1
-TA1CCTL2=\$386! \ Capture/compare control 2
-TA1R=\$390! \ TA1 counter register
-TA1CCR0=\$392! \ Capture/compare register 0
-TA1CCR1=\$394! \ Capture/compare register 1
-TA1CCR2=\$396! \ Capture/compare register 2
-TA1EX0=\$3A0! \ TA1 expansion register 0
-TA1IV=\$3AE! \ TA1 interrupt vector
-
-TB0CTL=\$3C0! \ TB0 control
-TB0CCTL0=\$3C2! \ Capture/compare control 0
-TB0CCTL1=\$3C4! \ Capture/compare control 1
-TB0CCTL2=\$3C6! \ Capture/compare control 2
-TB0R=\$3D0! \ TB0 counter register
-TB0CCR0=\$3D2! \ Capture/compare register 0
-TB0CCR1=\$3D4! \ Capture/compare register 1
-TB0CCR2=\$3D6! \ Capture/compare register 2
-TB0EX0=\$3E0! \ TB0 expansion register 0
-TB0IV=\$3EE! \ TB0 interrupt vector
-
-
-TB1CTL=\$400! \ TB1 control
-TB1CCTL0=\$402! \ Capture/compare control 0
-TB1CCTL1=\$404! \ Capture/compare control 1
-TB1CCTL2=\$406! \ Capture/compare control 2
-TB1R=\$410! \ TB1 counter register
-TB1CCR0=\$412! \ Capture/compare register 0
-TB1CCR1=\$414! \ Capture/compare register 1
-TB1CCR2=\$416! \ Capture/compare register 2
-TB1EX0=\$420! \ TB1 expansion register 0
-TB1IV=\$42E! \ TB1 interrupt vector
-
-TB2CTL=\$440! \ TB2 control
-TB2CCTL0=\$442! \ Capture/compare control 0
-TB2CCTL1=\$444! \ Capture/compare control 1
-TB2CCTL2=\$446! \ Capture/compare control 2
-TB2R=\$450! \ TB2 counter register
-TB2CCR0=\$452! \ Capture/compare register 0
-TB2CCR1=\$454! \ Capture/compare register 1
-TB2CCR2=\$456! \ Capture/compare register 2
-TB2EX0=\$460! \ TB2 expansion register 0
-TB2IV=\$46E! \ TB2 interrupt vector
-
-! RTC_B
-RTCCTL0=\$4A0! \ RTC control 0
-RTCCTL1=\$4A1! \ RTC control 1
-RTCCTL2=\$4A2! \ RTC control 2
-RTCCTL3=\$4A3! \ RTC control 3
-RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
-RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
-RTCPS0=\$4AC! \ RTC prescaler 0
-RTCPS1=\$4AD! \ RTC prescaler 1
-RTCIV=\$4AE! \ RTC interrupt vector word
-RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
-RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
-RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
-RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
-RTCDAY=\$4B4! \ RTC days
-RTCMON=\$4B5! \ RTC month
-RTCYEAR=\$4B6!
-RTCYEARL=\$4B6! \ RTC year low
-RTCYEARH=\$4B7! \ RTC year high
-RTCAMIN=\$4B8! \ RTC alarm minutes
-RTCAHOUR=\$4B9! \ RTC alarm hours
-RTCADOW=\$4BA! \ RTC alarm day of week
-RTCADAY=\$4BB! \ RTC alarm days
-BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
-BCD2BIN=\$4BE! \ BCD-to-binary conversion register
-RTCHOLD=\$40!
-RTCRDY=\$10!
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-DMAIFG=8!
-
-DMA0CTL=\$500! \ DMA channel 0 control
-DMA0SAL=\$502! \ DMA channel 0 source address low
-DMA0SAH=\$504! \ DMA channel 0 source address high
-DMA0DAL=\$506! \ DMA channel 0 destination address low
-DMA0DAH=\$508! \ DMA channel 0 destination address high
-DMA0SZ=\$50A! \ DMA channel 0 transfer size
-DMA1CTL=\$510! \ DMA channel 1 control
-DMA1SAL=\$512! \ DMA channel 1 source address low
-DMA1SAH=\$514! \ DMA channel 1 source address high
-DMA1DAL=\$516! \ DMA channel 1 destination address low
-DMA1DAH=\$518! \ DMA channel 1 destination address high
-DMA1SZ=\$51A! \ DMA channel 1 transfer size
-DMA2CTL=\$520! \ DMA channel 2 control
-DMA2SAL=\$522! \ DMA channel 2 source address low
-DMA2SAH=\$524! \ DMA channel 2 source address high
-DMA2DAL=\$526! \ DMA channel 2 destination address low
-DMA2DAH=\$528! \ DMA channel 2 destination address high
-DMA2SZ=\$52A! \ DMA channel 2 transfer size
-DMACTL0=\$530! \ DMA module control 0
-DMACTL1=\$532! \ DMA module control 1
-DMACTL2=\$534! \ DMA module control 2
-DMACTL3=\$536! \ DMA module control 3
-DMACTL4=\$538! \ DMA module control 4
-DMAIV=\$53A! \ DMA interrupt vector
-
-MPUCTL0=\$5A0! \ MPU control 0
-MPUCTL1=\$5A2! \ MPU control 1
-MPUSEG=\$5A4! \ MPU Segmentation Register
-MPUSAM=\$5A6! \ MPU access management
-
-UCA0CTLW0=\$5C0! \ eUSCI_A control word 0
-UCA0CTLW1=\$5C2! \ eUSCI_A control word 1
-UCA0BRW=\$5C6!
-UCA0BR0=\$5C6! \ eUSCI_A baud rate 0
-UCA0BR1=\$5C7! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$5C8! \ eUSCI_A modulation control
-UCA0STATW=\$5CA! \ eUSCI_A status
-UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer
-UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$5D0! \ eUSCI_A LIN control
-UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-UCA0IE=\$5DA! \ eUSCI_A interrupt enable
-UCA0IFG=\$5DC! \ eUSCI_A interrupt flags
-UCA0IV=\$5DE! \ eUSCI_A interrupt vector word
-
-UCB0CTLW0=\$640! \ eUSCI_B control word 0
-UCB0CTLW1=\$642! \ eUSCI_B control word 1
-UCB0BRW=\$646!
-UCB0BR0=\$646! \ eUSCI_B bit rate 0
-UCB0BR1=\$647! \ eUSCI_B bit rate 1
-UCB0STATW=\$648! \ eUSCI_B status word
-UCB0BCNT=\$649! \ eUSCI_B Byte Count !WARNING! byte access!
-UCB0TBCNT=\$64A! \ eUSCI_B Byte Count Threshold
-UCB0RXBUF=\$64C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$65C! \ eUSCI_B received address
-UCB0ADDMASK=\$65E! \ eUSCI_B address mask
-UCB0I2CSA=\$660! \ eUSCI I2C slave address
-UCB0IE=\$66A! \ eUSCI interrupt enable
-UCB0IFG=\$66C! \ eUSCI interrupt flags
-UCB0IV=\$66E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-ADC10CTL0=\$700! \ ADC10_B Control register 0
-ADC10CTL1=\$702! \ ADC10_B Control register 1
-ADC10CTL2=\$704! \ ADC10_B Control register 2
-ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold
-ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold
-ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0
-ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register
-ADC10IE=\$71A! \ ADC10_B Interrupt Enable
-ADC10IFG=\$71C! \ ADC10_B Interrupt Flags
-ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-CDIFG=1!
-CDIIFG=2!
-
-CDCTL0=\$8C0! \ Comparator_D control register 0
-CDCTL1=\$8C2! \ Comparator_D control register 1
-CDCTL2=\$8C4! \ Comparator_D control register 2
-CDCTL3=\$8C6! \ Comparator_D control register 3
-CDINT=\$8CC! \ Comparator_D interrupt register
-CDIV=\$8CE! \ Comparator_D interrupt vector word
+
+@set-syntax{C;\;}! replace ! by semicolon
+
+; ----------------------------------------------
+;MSP430fr5738.pat
+; ----------------------------------------------
+
+; ----------------------------------------------
+; MSP430FR5738 MEMORY MAP
+; ----------------------------------------------
+; 0000-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
+; 1800-187F = info B (FRAM 128 B)
+; 1880-18FF = info A (FRAM 128 B)
+; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
+; 1C00-1FFF = RAM (1 KB)
+; C200-FF7F = code memory (FRAM 15743 B)
+; FF80-FFFF = interrupt vectors (FRAM 127 B)
+; ----------------------------------------------
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0100;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$1C00;
+RAM_LEN=\$0400;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FR57xx.pat
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$C200; Code space start
+MAIN_LEN=\$3E00; 15.5 k FRAM
+; ----------------------------------------------
+\#LIT=\#\$C200; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$C214; asm CODE run time of QUOTE
+\#MUSMOD=\#\$C228; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$C23A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$C242; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$C26C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$C26E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$C27E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$C28A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$C296; CODE compiled by IF UNTIL
+\#BRAN=\#\$C29C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$C29E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$C2A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$C2AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$C2BA;
+\#ABORT_TERM=\#\$4300; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$C372; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$C35C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR5738
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFCE; FFCE-FFFF
+VECT_LEN=\$32;
+
+
+RTC_VEC=\$FFCE;
+P4_VEC=\$FFD0;
+P3_VEC=\$FFD2;
+TB2_X_VEC=\$FFD4; All others
+TB2_0_VEC=\$FFD6; only CCIFG0
+P2_VEC=\$FFD8;
+TB1_X_VEC=\$FFDA; All others
+TB1_0_VEC=\$FFDC; only CCIFG0
+P1_VEC=\$FFDE;
+TA1_X_VEC=\$FFE0; All others
+TA1_0_VEC=\$FFE2; only CCIFG0
+DMA_VEC=\$FFE4;
+;EUSCI_A1_VEC=\$FFE6;
+TA0_X_VEC=\$FFE8; All others
+TA0_0_VEC=\$FFEA; only CCIFG0
+ADC10_B_VEC=\$FFEC;
+EUSCI_B0_VEC=\$FFEE;
+EUSCI_A0_VEC=\$FFF0;
+WDT_VEC=\$FFF2;
+TB0_X_VEC=\$FFF4; All others
+TB0_0_VEC=\$FFF6; only CCIFG0
+COMP_D_VEC=\$FFF8;
+USER_NMI_VEC=\$FFFA;
+SYS_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+FRCTLCTL0=\$140; \ FRAM control 0
+GCCTL0=\$144; \ General control 0
+GCCTL1=\$146; \ General control 1
+
+CRC16DI=\$150; \ CRC data input
+CRCDIRB=\$152; \ CRC data input reverse byte
+CRCINIRES=\$154; \ CRC initialization and result
+CRCRESR=\$156; \ CRC result reverse byte
+
+WDTCTL=\$15C; \ WDT control register
+
+CSCTL0=\$160; \ CS control 0
+CSCTL0_H=\$161; \
+CSCTL1=\$162; \ CS control 1
+CSCTL2=\$164; \ CS control 2
+CSCTL3=\$166; \ CS control 3
+CSCTL4=\$168; \ CS control 4
+CSCTL5=\$16A; \ CS control 5
+CSCTL6=\$16C; \ CS control 6
+
+SYSCTL=\$180; \ System control
+SYSJMBC=\$186; \ JTAG mailbox control
+SYSJMBI0=\$188; \ JTAG mailbox input 0
+SYSJMBI1=\$18A; \ JTAG mailbox input 1
+SYSJMBO0=\$18C; \ JTAG mailbox output 0
+SYSJMBO1=\$18E; \ JTAG mailbox output 1
+SYSBERRIV=\$198; \ Bus Error vector generator
+SYSUNIV=\$19A; \ User NMI vector generator
+SYSSNIV=\$19C; \ System NMI vector generator
+SYSRSTIV=\$19E; \ Reset vector generator
+
+REFCTL=\$1b0; \ Shared reference control
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PASELC=\$216;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1SELC=\$216;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2SELC=\$217;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+
+PJIN=\$320;
+PJOUT=\$322;
+PJDIR=\$324;
+PJREN=\$326;
+PJSEL0=\$32A;
+PJSEL1=\$32C;
+PJSELC=\$336;
+
+
+TACLR=4;
+TAIFG=1;
+TBCLR=4;
+TBIFG=1;
+CCIFG=1;
+
+TA0CTL=\$340; \ TA0 control
+TA0CCTL0=\$342; \ Capture/compare control 0
+TA0CCTL1=\$344; \ Capture/compare control 1
+TA0CCTL2=\$346; \ Capture/compare control 2
+TA0R=\$350; \ TA0 counter register
+TA0CCR0=\$352; \ Capture/compare register 0
+TA0CCR1=\$354; \ Capture/compare register 1
+TA0CCR2=\$356; \ Capture/compare register 2
+TA0EX0=\$360; \ TA0 expansion register 0
+TA0IV=\$36E; \ TA0 interrupt vector
+
+TA1CTL=\$380; \ TA1 control
+TA1CCTL0=\$382; \ Capture/compare control 0
+TA1CCTL1=\$384; \ Capture/compare control 1
+TA1CCTL2=\$386; \ Capture/compare control 2
+TA1R=\$390; \ TA1 counter register
+TA1CCR0=\$392; \ Capture/compare register 0
+TA1CCR1=\$394; \ Capture/compare register 1
+TA1CCR2=\$396; \ Capture/compare register 2
+TA1EX0=\$3A0; \ TA1 expansion register 0
+TA1IV=\$3AE; \ TA1 interrupt vector
+
+TB0CTL=\$3C0; \ TB0 control
+TB0CCTL0=\$3C2; \ Capture/compare control 0
+TB0CCTL1=\$3C4; \ Capture/compare control 1
+TB0CCTL2=\$3C6; \ Capture/compare control 2
+TB0R=\$3D0; \ TB0 counter register
+TB0CCR0=\$3D2; \ Capture/compare register 0
+TB0CCR1=\$3D4; \ Capture/compare register 1
+TB0CCR2=\$3D6; \ Capture/compare register 2
+TB0EX0=\$3E0; \ TB0 expansion register 0
+TB0IV=\$3EE; \ TB0 interrupt vector
+
+
+TB1CTL=\$400; \ TB1 control
+TB1CCTL0=\$402; \ Capture/compare control 0
+TB1CCTL1=\$404; \ Capture/compare control 1
+TB1CCTL2=\$406; \ Capture/compare control 2
+TB1R=\$410; \ TB1 counter register
+TB1CCR0=\$412; \ Capture/compare register 0
+TB1CCR1=\$414; \ Capture/compare register 1
+TB1CCR2=\$416; \ Capture/compare register 2
+TB1EX0=\$420; \ TB1 expansion register 0
+TB1IV=\$42E; \ TB1 interrupt vector
+
+TB2CTL=\$440; \ TB2 control
+TB2CCTL0=\$442; \ Capture/compare control 0
+TB2CCTL1=\$444; \ Capture/compare control 1
+TB2CCTL2=\$446; \ Capture/compare control 2
+TB2R=\$450; \ TB2 counter register
+TB2CCR0=\$452; \ Capture/compare register 0
+TB2CCR1=\$454; \ Capture/compare register 1
+TB2CCR2=\$456; \ Capture/compare register 2
+TB2EX0=\$460; \ TB2 expansion register 0
+TB2IV=\$46E; \ TB2 interrupt vector
+
+; RTC_B
+RTCCTL0=\$4A0; \ RTC control 0
+RTCCTL1=\$4A1; \ RTC control 1
+RTCCTL2=\$4A2; \ RTC control 2
+RTCCTL3=\$4A3; \ RTC control 3
+RTCPS0CTL=\$4A8; \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA; \ RTC prescaler 1 control
+RTCPS0=\$4AC; \ RTC prescaler 0
+RTCPS1=\$4AD; \ RTC prescaler 1
+RTCIV=\$4AE; \ RTC interrupt vector word
+RTCSEC=\$4B0; \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCMIN=\$4B1; \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCHOUR=\$4B2; \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCDOW=\$4B3; \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCDAY=\$4B4; \ RTC days
+RTCMON=\$4B5; \ RTC month
+RTCYEAR=\$4B6;
+RTCYEARL=\$4B6; \ RTC year low
+RTCYEARH=\$4B7; \ RTC year high
+RTCAMIN=\$4B8; \ RTC alarm minutes
+RTCAHOUR=\$4B9; \ RTC alarm hours
+RTCADOW=\$4BA; \ RTC alarm day of week
+RTCADAY=\$4BB; \ RTC alarm days
+BIN2BCD=\$4BC; \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE; \ BCD-to-binary conversion register
+RTCHOLD=\$40;
+RTCRDY=\$10;
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+DMAIFG=8;
+
+DMA0CTL=\$500; \ DMA channel 0 control
+DMA0SAL=\$502; \ DMA channel 0 source address low
+DMA0SAH=\$504; \ DMA channel 0 source address high
+DMA0DAL=\$506; \ DMA channel 0 destination address low
+DMA0DAH=\$508; \ DMA channel 0 destination address high
+DMA0SZ=\$50A; \ DMA channel 0 transfer size
+DMA1CTL=\$510; \ DMA channel 1 control
+DMA1SAL=\$512; \ DMA channel 1 source address low
+DMA1SAH=\$514; \ DMA channel 1 source address high
+DMA1DAL=\$516; \ DMA channel 1 destination address low
+DMA1DAH=\$518; \ DMA channel 1 destination address high
+DMA1SZ=\$51A; \ DMA channel 1 transfer size
+DMA2CTL=\$520; \ DMA channel 2 control
+DMA2SAL=\$522; \ DMA channel 2 source address low
+DMA2SAH=\$524; \ DMA channel 2 source address high
+DMA2DAL=\$526; \ DMA channel 2 destination address low
+DMA2DAH=\$528; \ DMA channel 2 destination address high
+DMA2SZ=\$52A; \ DMA channel 2 transfer size
+DMACTL0=\$530; \ DMA module control 0
+DMACTL1=\$532; \ DMA module control 1
+DMACTL2=\$534; \ DMA module control 2
+DMACTL3=\$536; \ DMA module control 3
+DMACTL4=\$538; \ DMA module control 4
+DMAIV=\$53A; \ DMA interrupt vector
+
+MPUCTL0=\$5A0; \ MPU control 0
+MPUCTL1=\$5A2; \ MPU control 1
+MPUSEG=\$5A4; \ MPU Segmentation Register
+MPUSAM=\$5A6; \ MPU access management
+
+UCA0CTLW0=\$5C0; \ eUSCI_A control word 0
+UCA0CTLW1=\$5C2; \ eUSCI_A control word 1
+UCA0BRW=\$5C6;
+UCA0BR0=\$5C6; \ eUSCI_A baud rate 0
+UCA0BR1=\$5C7; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$5C8; \ eUSCI_A modulation control
+UCA0STATW=\$5CA; \ eUSCI_A status
+UCA0RXBUF=\$5CC; \ eUSCI_A receive buffer
+UCA0TXBUF=\$5CE; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$5D0; \ eUSCI_A LIN control
+UCA0IRTCTL=\$5D2; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$5D3; \ eUSCI_A IrDA receive control
+UCA0IE=\$5DA; \ eUSCI_A interrupt enable
+UCA0IFG=\$5DC; \ eUSCI_A interrupt flags
+UCA0IV=\$5DE; \ eUSCI_A interrupt vector word
+
+UCB0CTLW0=\$640; \ eUSCI_B control word 0
+UCB0CTLW1=\$642; \ eUSCI_B control word 1
+UCB0BRW=\$646;
+UCB0BR0=\$646; \ eUSCI_B bit rate 0
+UCB0BR1=\$647; \ eUSCI_B bit rate 1
+UCB0STATW=\$648; \ eUSCI_B status word
+UCB0BCNT=\$649; \ eUSCI_B Byte Count ;WARNING; byte access;
+UCB0TBCNT=\$64A; \ eUSCI_B Byte Count Threshold
+UCB0RXBUF=\$64C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$64E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$654; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$656; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$658; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$65A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$65C; \ eUSCI_B received address
+UCB0ADDMASK=\$65E; \ eUSCI_B address mask
+UCB0I2CSA=\$660; \ eUSCI I2C slave address
+UCB0IE=\$66A; \ eUSCI interrupt enable
+UCB0IFG=\$66C; \ eUSCI interrupt flags
+UCB0IV=\$66E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+ADC10CTL0=\$700; \ ADC10_B Control register 0
+ADC10CTL1=\$702; \ ADC10_B Control register 1
+ADC10CTL2=\$704; \ ADC10_B Control register 2
+ADC10LO=\$706; \ ADC10_B Window Comparator Low Threshold
+ADC10HI=\$708; \ ADC10_B Window Comparator High Threshold
+ADC10MCTL0=\$70A; \ ADC10_B Memory Control Register 0
+ADC10MEM0=\$712; \ ADC10_B Conversion Memory Register
+ADC10IE=\$71A; \ ADC10_B Interrupt Enable
+ADC10IFG=\$71C; \ ADC10_B Interrupt Flags
+ADC10IV=\$71E; \ ADC10_B Interrupt Vector Word
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CDIFG=1;
+CDIIFG=2;
+
+CDCTL0=\$8C0; \ Comparator_D control register 0
+CDCTL1=\$8C2; \ Comparator_D control register 1
+CDCTL2=\$8C4; \ Comparator_D control register 2
+CDCTL3=\$8C6; \ Comparator_D control register 3
+CDINT=\$8CC; \ Comparator_D interrupt register
+CDIV=\$8CE; \ Comparator_D interrupt vector word
.listing off
DEVICE = "MSP430FR5739"
-
+HMPY ; hardware multiplier
; ----------------------------------------------
; MSP430FR5739 MEMORY MAP
-!MSP430fr5739.pat
-
-! ----------------------------------------------
-! MSP430FR5739 MEMORY MAP
-! ----------------------------------------------
-! 0000-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
-! 1800-187F = info B (FRAM 128 B)
-! 1880-18FF = info A (FRAM 128 B)
-! 1900-19FF = N/A (mirrored into info A/B)
-! 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
-! 1A80-1BFF = unused (385 B)
-! 1C00-1FFF = RAM (1 KB)
-! 2000-C1FF = unused (41472 B)
-! C200-FF7F = code memory (FRAM 15743 B)
-! FF80-FFFF = interrupt vectors (FRAM 127 B)
-! ----------------------------------------------
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0100!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-
-! ============================================
-! FastForth INFO(DCBA) memory map (256 bytes):
-! ============================================
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$185A!
-BS_FirstSectorL=\$185C!
-BS_FirstSectorH=\$185E!
-OrgFAT1=\$1860!
-FATSize=\$1862!
-OrgFAT2=\$1864!
-OrgRootDir=\$1866!
-OrgClusters=\$1868! Sector of Cluster 0
-SecPerClus=\$186A!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$186C! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$186C! CRC:ll word access
-SD_CMD_FRM1=\$186D! ll byte access
-SD_CMD_FRM2=\$186E! LL:hh word access
-SD_CMD_FRM3=\$186F! hh byte access
-SD_CMD_FRM4=\$1870! HH:CMD word access
-SD_CMD_FRM5=\$1871! CMD byte access
-SectorL=\$1872! 2 words
-SectorH=\$1874!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$1876!
-BufferLen=\$1878!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$187A! 16 bits wide (FAT16)
-ClusterH=\$187C! 16 bits wide (FAT16)
-LastFATsector=\$187E! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$1880! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$1882! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$1884! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$1886! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$1888!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$188A! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$188C! address of pathname string
-EndOfPath=\$188E!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=4!
-HandleLenght=28!
-FirstHandle=\$1890!
-HandleEnd=\$1900!
-
-SD_END=\$1900!
-SD_LEN=\$A6!
-
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0080!
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$1C00!
-RAM_LEN=\$0400!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-!SD_card Input Buffer = PAD
-SDIB_I2CADR=\$1CE0!
-SDIB_I2CCNT=\$1CE2!
-SDIB_ORG=\$1CE4!
-SDIB_LEN=\$54!
-
-! ----------------------------------------------
-! FastForth RAM memory map (= 1k):
-! ----------------------------------------------
-LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT
-LSATCK=\$1C00! leave stack, grow up
-PSTACK=\$1C80! parameter stack, grow down
-RSTACK=\$1CE0! Return stack, grow down
-!
-PAD_I2CADR=\$1CE0! RX I2C address
-PAD_I2CCNT=\$1CE2! count max
-PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$1D38! TX I2C address
-TIB_I2CCNT=\$1D3A! count of bytes
-TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$1D90! base address for HOLDS
-HOLD_BASE=\$1DB2! BASE HOLD area, grow down
-!
-HP=\$1DB2! HOLD ptr
-LAST_NFA=\$1DB4!
-LAST_THREAD=\$1DB6!
-LAST_CFA=\$1DB8!
-LAST_PSP=\$1DBA!
-!
-STATEADR=\$1DBC! Interpreter state
-BASEADR=\$1DBE! base
-CAPS=\$1DC0! CAPS ON/OFF
-!
-SOURCE_LEN=\$1DC2! len of input stream
-SOURCE_ORG=\$1DC4! adr of input stream
-TOIN=\$1DC6! >IN
-DP=\$1DC8! dictionary ptr
-!
-LASTVOC=\$1DCA! keep VOC-LINK
-CURRENT=\$1DCC! CURRENT dictionnary ptr
-CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!1DE0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$1DFC!
-SD_BUF_I2CNT=\$1DFE!
-SD_BUF=\$1E00! \ SD_Card buffer
-BUFEND=\$2000!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$C200! Code space start
-MAIN_LEN=\$3E00! 15.5 k FRAM
-! ----------------------------------------------
-
-SLEEP=\$C200! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$C20A! CODE compiled by LITERAL
-XSQUOTE=\$C21E! CODE compiled by S" and S_
-HEREXEC=\$C232! CODE HERE and BEGIN execute address
-MUSMOD=\$C23E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$C250! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$C258! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$C282! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$C284! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$C294! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$C2A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$C2AC! CODE compiled by IF UNTIL
-BRAN=\$C2B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$C2B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$C2B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$C2C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$C2D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$C308! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$C312! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$C354! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$C37E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$C384! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$C386! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$C344! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$C346! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$C350! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$C350! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$C352! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$C37A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR5739
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFCE! FFCE-FFFF
-VECT_LEN=\$32!
-
-
-RTC_VEC=\$FFCE!
-P4_VEC=\$FFD0!
-P3_VEC=\$FFD2!
-TB2_X_VEC=\$FFD4!
-TB2_0_VEC=\$FFD6!
-P2_VEC=\$FFD8!
-TB1_X_VEC=\$FFDA!
-TB1_0_VEC=\$FFDC!
-P1_VEC=\$FFDE!
-TA1_X_VEC=\$FFE0!
-TA1_0_VEC=\$FFE2!
-DMA_VEC=\$FFE4!
-EUSCI_A1_VEC=\$FFE6!
-TA0_X_VEC=\$FFE8!
-TA0_0_VEC=\$FFEA!
-ADC10_B_VEC=\$FFEC!
-EUSCI_B0_VEC=\$FFEE!
-EUSCI_A0_VEC=\$FFF0!
-WDT_VEC=\$FFF2!
-TB0_X_VEC=\$FFF4!
-TB0_0_VEC=\$FFF6!
-COMP_D_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-FRCTLCTL0=\$140! \ FRAM control 0
-GCCTL0=\$144! \ General control 0
-GCCTL1=\$146! \ General control 1
-
-CRC16DI=\$150! \ CRC data input
-CRCDIRB=\$152! \ CRC data input reverse byte
-CRCINIRES=\$154! \ CRC initialization and result
-CRCRESR=\$156! \ CRC result reverse byte
-
-WDTCTL=\$15C! \ WDT control register
-
-CSCTL0=\$160! \ CS control 0
-CSCTL0_H=\$161! \
-CSCTL1=\$162! \ CS control 1
-CSCTL2=\$164! \ CS control 2
-CSCTL3=\$166! \ CS control 3
-CSCTL4=\$168! \ CS control 4
-CSCTL5=\$16A! \ CS control 5
-CSCTL6=\$16C! \ CS control 6
-
-SYSCTL=\$180! \ System control
-SYSJMBC=\$186! \ JTAG mailbox control
-SYSJMBI0=\$188! \ JTAG mailbox input 0
-SYSJMBI1=\$18A! \ JTAG mailbox input 1
-SYSJMBO0=\$18C! \ JTAG mailbox output 0
-SYSJMBO1=\$18E! \ JTAG mailbox output 1
-SYSBERRIV=\$198! \ Bus Error vector generator
-SYSUNIV=\$19A! \ User NMI vector generator
-SYSSNIV=\$19C! \ System NMI vector generator
-SYSRSTIV=\$19E! \ Reset vector generator
-
-REFCTL=\$1b0! \ Shared reference control
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PASELC=\$216!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1SELC=\$216!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2SELC=\$217!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-PBIN=\$220!
-PBOUT=\$222!
-PBDIR=\$224!
-PBREN=\$226!
-PBSEL0=\$22A!
-PBSEL1=\$22C!
-PBSELC=\$236!
-PBIES=\$238!
-PBIE=\$23A!
-PBIFG=\$23C!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-P3IV=\$22E!
-P3SELC=\$236!
-P3IES=\$238!
-P3IE=\$23A!
-P3IFG=\$23C!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-P4SEL1=\$22D!
-P4SELC=\$237!
-P4IES=\$239!
-P4IE=\$23B!
-P4IFG=\$23D!
-P4IV=\$23E!
-
-PJIN=\$320!
-PJOUT=\$322!
-PJDIR=\$324!
-PJREN=\$326!
-PJSEL0=\$32A!
-PJSEL1=\$32C!
-PJSELC=\$336!
-
-
-TACLR=4!
-TAIFG=1!
-TBCLR=4!
-TBIFG=1!
-CCIFG=1!
-
-TA0CTL=\$340! \ TA0 control
-TA0CCTL0=\$342! \ Capture/compare control 0
-TA0CCTL1=\$344! \ Capture/compare control 1
-TA0CCTL2=\$346! \ Capture/compare control 2
-TA0R=\$350! \ TA0 counter register
-TA0CCR0=\$352! \ Capture/compare register 0
-TA0CCR1=\$354! \ Capture/compare register 1
-TA0CCR2=\$356! \ Capture/compare register 2
-TA0EX0=\$360! \ TA0 expansion register 0
-TA0IV=\$36E! \ TA0 interrupt vector
-
-TA1CTL=\$380! \ TA1 control
-TA1CCTL0=\$382! \ Capture/compare control 0
-TA1CCTL1=\$384! \ Capture/compare control 1
-TA1CCTL2=\$386! \ Capture/compare control 2
-TA1R=\$390! \ TA1 counter register
-TA1CCR0=\$392! \ Capture/compare register 0
-TA1CCR1=\$394! \ Capture/compare register 1
-TA1CCR2=\$396! \ Capture/compare register 2
-TA1EX0=\$3A0! \ TA1 expansion register 0
-TA1IV=\$3AE! \ TA1 interrupt vector
-
-TB0CTL=\$3C0! \ TB0 control
-TB0CCTL0=\$3C2! \ Capture/compare control 0
-TB0CCTL1=\$3C4! \ Capture/compare control 1
-TB0CCTL2=\$3C6! \ Capture/compare control 2
-TB0R=\$3D0! \ TB0 counter register
-TB0CCR0=\$3D2! \ Capture/compare register 0
-TB0CCR1=\$3D4! \ Capture/compare register 1
-TB0CCR2=\$3D6! \ Capture/compare register 2
-TB0EX0=\$3E0! \ TB0 expansion register 0
-TB0IV=\$3EE! \ TB0 interrupt vector
-
-TB1CTL=\$400! \ TB1 control
-TB1CCTL0=\$402! \ Capture/compare control 0
-TB1CCTL1=\$404! \ Capture/compare control 1
-TB1CCTL2=\$406! \ Capture/compare control 2
-TB1R=\$410! \ TB1 counter register
-TB1CCR0=\$412! \ Capture/compare register 0
-TB1CCR1=\$414! \ Capture/compare register 1
-TB1CCR2=\$416! \ Capture/compare register 2
-TB1EX0=\$420! \ TB1 expansion register 0
-TB1IV=\$42E! \ TB1 interrupt vector
-
-TB2CTL=\$440! \ TB2 control
-TB2CCTL0=\$442! \ Capture/compare control 0
-TB2CCTL1=\$444! \ Capture/compare control 1
-TB2CCTL2=\$446! \ Capture/compare control 2
-TB2R=\$450! \ TB2 counter register
-TB2CCR0=\$452! \ Capture/compare register 0
-TB2CCR1=\$454! \ Capture/compare register 1
-TB2CCR2=\$456! \ Capture/compare register 2
-TB2EX0=\$460! \ TB2 expansion register 0
-TB2IV=\$46E! \ TB2 interrupt vector
-
-! RTC_B
-RTCCTL0=\$4A0! \ RTC control 0
-RTCCTL1=\$4A1! \ RTC control 1
-RTCCTL2=\$4A2! \ RTC control 2
-RTCCTL3=\$4A3! \ RTC control 3
-RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
-RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
-RTCPS0=\$4AC! \ RTC prescaler 0
-RTCPS1=\$4AD! \ RTC prescaler 1
-RTCIV=\$4AE! \ RTC interrupt vector word
-RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
-RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
-RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
-RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
-RTCDAY=\$4B4! \ RTC days
-RTCMON=\$4B5! \ RTC month
-RTCYEAR=\$4B6!
-RTCYEARL=\$4B6! \ RTC year low
-RTCYEARH=\$4B7! \ RTC year high
-RTCAMIN=\$4B8! \ RTC alarm minutes
-RTCAHOUR=\$4B9! \ RTC alarm hours
-RTCADOW=\$4BA! \ RTC alarm day of week
-RTCADAY=\$4BB! \ RTC alarm days
-BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
-BCD2BIN=\$4BE! \ BCD-to-binary conversion register
-RTCHOLD=\$40!
-RTCRDY=\$10!
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-DMAIFG=8!
-
-DMA0CTL=\$500! \ DMA channel 0 control
-DMA0SAL=\$502! \ DMA channel 0 source address low
-DMA0SAH=\$504! \ DMA channel 0 source address high
-DMA0DAL=\$506! \ DMA channel 0 destination address low
-DMA0DAH=\$508! \ DMA channel 0 destination address high
-DMA0SZ=\$50A! \ DMA channel 0 transfer size
-DMA1CTL=\$510! \ DMA channel 1 control
-DMA1SAL=\$512! \ DMA channel 1 source address low
-DMA1SAH=\$514! \ DMA channel 1 source address high
-DMA1DAL=\$516! \ DMA channel 1 destination address low
-DMA1DAH=\$518! \ DMA channel 1 destination address high
-DMA1SZ=\$51A! \ DMA channel 1 transfer size
-DMA2CTL=\$520! \ DMA channel 2 control
-DMA2SAL=\$522! \ DMA channel 2 source address low
-DMA2SAH=\$524! \ DMA channel 2 source address high
-DMA2DAL=\$526! \ DMA channel 2 destination address low
-DMA2DAH=\$528! \ DMA channel 2 destination address high
-DMA2SZ=\$52A! \ DMA channel 2 transfer size
-DMACTL0=\$530! \ DMA module control 0
-DMACTL1=\$532! \ DMA module control 1
-DMACTL2=\$534! \ DMA module control 2
-DMACTL3=\$536! \ DMA module control 3
-DMACTL4=\$538! \ DMA module control 4
-DMAIV=\$53A! \ DMA interrupt vector
-
-MPUCTL0=\$5A0! \ MPU control 0
-MPUCTL1=\$5A2! \ MPU control 1
-MPUSEG=\$5A4! \ MPU Segmentation Register
-MPUSAM=\$5A6! \ MPU access management
-
-UCA0CTLW0=\$5C0! \ eUSCI_A control word 0
-UCA0CTLW1=\$5C2! \ eUSCI_A control word 1
-UCA0BRW=\$5C6!
-UCA0BR0=\$5C6! \ eUSCI_A baud rate 0
-UCA0BR1=\$5C7! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$5C8! \ eUSCI_A modulation control
-UCA0STAT=\$5CA! \ eUSCI_A status
-UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer
-UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$5D0! \ eUSCI_A LIN control
-UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-UCA0IE=\$5DA! \ eUSCI_A interrupt enable
-UCA0IFG=\$5DC! \ eUSCI_A interrupt flags
-UCA0IV=\$5DE! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$5E0! \ eUSCI_A control word 0
-UCA1CTLW1=\$5E2! \ eUSCI_A control word 1
-UCA1BRW=\$5E6!
-UCA1BR0=\$5E6! \ eUSCI_A baud rate 0
-UCA1BR1=\$5E7! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$5E8! \ eUSCI_A modulation control
-UCA1STAT=\$5EA! \ eUSCI_A status
-UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer
-UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$5F0! \ eUSCI_A LIN control
-UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control
-UCA1IE=\$5FA! \ eUSCI_A interrupt enable
-UCA1IFG=\$5FC! \ eUSCI_A interrupt flags
-UCA1IV=\$5FE! \ eUSCI_A interrupt vector word
-
-UCB0CTLW0=\$640! \ eUSCI_B control word 0
-UCB0CTLW1=\$642! \ eUSCI_B control word 1
-UCB0BRW=\$646!
-UCB0BR0=\$646! \ eUSCI_B bit rate 0
-UCB0BR1=\$647! \ eUSCI_B bit rate 1
-UCB0STATW=\$648! \ eUSCI_B status word
-UCBCNT0=\$649! \ eUSCI_B hardware count
-UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$64C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$65C! \ eUSCI_B received address
-UCB0ADDMASK=\$65E! \ eUSCI_B address mask
-UCB0I2CSA=\$660! \ eUSCI I2C slave address
-UCB0IE=\$66A! \ eUSCI interrupt enable
-UCB0IFG=\$66C! \ eUSCI interrupt flags
-UCB0IV=\$66E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-ADC10CTL0=\$700! \ ADC10_B Control register 0
-ADC10CTL1=\$702! \ ADC10_B Control register 1
-ADC10CTL2=\$704! \ ADC10_B Control register 2
-ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold
-ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold
-ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0
-ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register
-ADC10IE=\$71A! \ ADC10_B Interrupt Enable
-ADC10IFG=\$71C! \ ADC10_B Interrupt Flags
-ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-CDIFG=1!
-CDIIFG=2!
-
-CDCTL0=\$8C0! \ Comparator_D control register 0
-CDCTL1=\$8C2! \ Comparator_D control register 1
-CDCTL2=\$8C4! \ Comparator_D control register 2
-CDCTL3=\$8C6! \ Comparator_D control register 3
-CDINT=\$8CC! \ Comparator_D interrupt register
-CDIV=\$8CE! \ Comparator_D interrupt vector word
+
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430fr5739.pat
+
+; ----------------------------------------------
+; MSP430FR5739 MEMORY MAP
+; ----------------------------------------------
+; 0000-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
+; 1800-187F = info B (FRAM 128 B)
+; 1880-18FF = info A (FRAM 128 B)
+; 1900-19FF = N/A (mirrored into info A/B)
+; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
+; 1A80-1BFF = unused (385 B)
+; 1C00-1FFF = RAM (1 KB)
+; 2000-C1FF = unused (41472 B)
+; C200-FF7F = code memory (FRAM 15743 B)
+; FF80-FFFF = interrupt vectors (FRAM 127 B)
+; ----------------------------------------------
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0100;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$1C00;
+RAM_LEN=\$0400;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FR57xx.pat
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$C200; Code space start
+MAIN_LEN=\$3E00; 15.5 k FRAM
+; ----------------------------------------------
+\#LIT=\#\$C200; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$C214; asm CODE run time of QUOTE
+\#MUSMOD=\#\$C228; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$C23A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$C242; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$C26C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$C26E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$C27E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$C28A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$C296; CODE compiled by IF UNTIL
+\#BRAN=\#\$C29C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$C29E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$C2A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$C2AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$C2BA;
+\#ABORT_TERM=\#\$4300; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$C372; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$C35C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR5739
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFCE; FFCE-FFFF
+VECT_LEN=\$32;
+
+
+RTC_VEC=\$FFCE;
+P4_VEC=\$FFD0;
+P3_VEC=\$FFD2;
+TB2_X_VEC=\$FFD4;
+TB2_0_VEC=\$FFD6;
+P2_VEC=\$FFD8;
+TB1_X_VEC=\$FFDA;
+TB1_0_VEC=\$FFDC;
+P1_VEC=\$FFDE;
+TA1_X_VEC=\$FFE0;
+TA1_0_VEC=\$FFE2;
+DMA_VEC=\$FFE4;
+EUSCI_A1_VEC=\$FFE6;
+TA0_X_VEC=\$FFE8;
+TA0_0_VEC=\$FFEA;
+ADC10_B_VEC=\$FFEC;
+EUSCI_B0_VEC=\$FFEE;
+EUSCI_A0_VEC=\$FFF0;
+WDT_VEC=\$FFF2;
+TB0_X_VEC=\$FFF4;
+TB0_0_VEC=\$FFF6;
+COMP_D_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+FRCTLCTL0=\$140; \ FRAM control 0
+GCCTL0=\$144; \ General control 0
+GCCTL1=\$146; \ General control 1
+
+CRC16DI=\$150; \ CRC data input
+CRCDIRB=\$152; \ CRC data input reverse byte
+CRCINIRES=\$154; \ CRC initialization and result
+CRCRESR=\$156; \ CRC result reverse byte
+
+WDTCTL=\$15C; \ WDT control register
+
+CSCTL0=\$160; \ CS control 0
+CSCTL0_H=\$161; \
+CSCTL1=\$162; \ CS control 1
+CSCTL2=\$164; \ CS control 2
+CSCTL3=\$166; \ CS control 3
+CSCTL4=\$168; \ CS control 4
+CSCTL5=\$16A; \ CS control 5
+CSCTL6=\$16C; \ CS control 6
+
+SYSCTL=\$180; \ System control
+SYSJMBC=\$186; \ JTAG mailbox control
+SYSJMBI0=\$188; \ JTAG mailbox input 0
+SYSJMBI1=\$18A; \ JTAG mailbox input 1
+SYSJMBO0=\$18C; \ JTAG mailbox output 0
+SYSJMBO1=\$18E; \ JTAG mailbox output 1
+SYSBERRIV=\$198; \ Bus Error vector generator
+SYSUNIV=\$19A; \ User NMI vector generator
+SYSSNIV=\$19C; \ System NMI vector generator
+SYSRSTIV=\$19E; \ Reset vector generator
+
+REFCTL=\$1b0; \ Shared reference control
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PASELC=\$216;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1SELC=\$216;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2SELC=\$217;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+PBIN=\$220;
+PBOUT=\$222;
+PBDIR=\$224;
+PBREN=\$226;
+PBSEL0=\$22A;
+PBSEL1=\$22C;
+PBSELC=\$236;
+PBIES=\$238;
+PBIE=\$23A;
+PBIFG=\$23C;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+P3IV=\$22E;
+P3SELC=\$236;
+P3IES=\$238;
+P3IE=\$23A;
+P3IFG=\$23C;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+P4SEL1=\$22D;
+P4SELC=\$237;
+P4IES=\$239;
+P4IE=\$23B;
+P4IFG=\$23D;
+P4IV=\$23E;
+
+PJIN=\$320;
+PJOUT=\$322;
+PJDIR=\$324;
+PJREN=\$326;
+PJSEL0=\$32A;
+PJSEL1=\$32C;
+PJSELC=\$336;
+
+
+TACLR=4;
+TAIFG=1;
+TBCLR=4;
+TBIFG=1;
+CCIFG=1;
+
+TA0CTL=\$340; \ TA0 control
+TA0CCTL0=\$342; \ Capture/compare control 0
+TA0CCTL1=\$344; \ Capture/compare control 1
+TA0CCTL2=\$346; \ Capture/compare control 2
+TA0R=\$350; \ TA0 counter register
+TA0CCR0=\$352; \ Capture/compare register 0
+TA0CCR1=\$354; \ Capture/compare register 1
+TA0CCR2=\$356; \ Capture/compare register 2
+TA0EX0=\$360; \ TA0 expansion register 0
+TA0IV=\$36E; \ TA0 interrupt vector
+
+TA1CTL=\$380; \ TA1 control
+TA1CCTL0=\$382; \ Capture/compare control 0
+TA1CCTL1=\$384; \ Capture/compare control 1
+TA1CCTL2=\$386; \ Capture/compare control 2
+TA1R=\$390; \ TA1 counter register
+TA1CCR0=\$392; \ Capture/compare register 0
+TA1CCR1=\$394; \ Capture/compare register 1
+TA1CCR2=\$396; \ Capture/compare register 2
+TA1EX0=\$3A0; \ TA1 expansion register 0
+TA1IV=\$3AE; \ TA1 interrupt vector
+
+TB0CTL=\$3C0; \ TB0 control
+TB0CCTL0=\$3C2; \ Capture/compare control 0
+TB0CCTL1=\$3C4; \ Capture/compare control 1
+TB0CCTL2=\$3C6; \ Capture/compare control 2
+TB0R=\$3D0; \ TB0 counter register
+TB0CCR0=\$3D2; \ Capture/compare register 0
+TB0CCR1=\$3D4; \ Capture/compare register 1
+TB0CCR2=\$3D6; \ Capture/compare register 2
+TB0EX0=\$3E0; \ TB0 expansion register 0
+TB0IV=\$3EE; \ TB0 interrupt vector
+
+TB1CTL=\$400; \ TB1 control
+TB1CCTL0=\$402; \ Capture/compare control 0
+TB1CCTL1=\$404; \ Capture/compare control 1
+TB1CCTL2=\$406; \ Capture/compare control 2
+TB1R=\$410; \ TB1 counter register
+TB1CCR0=\$412; \ Capture/compare register 0
+TB1CCR1=\$414; \ Capture/compare register 1
+TB1CCR2=\$416; \ Capture/compare register 2
+TB1EX0=\$420; \ TB1 expansion register 0
+TB1IV=\$42E; \ TB1 interrupt vector
+
+TB2CTL=\$440; \ TB2 control
+TB2CCTL0=\$442; \ Capture/compare control 0
+TB2CCTL1=\$444; \ Capture/compare control 1
+TB2CCTL2=\$446; \ Capture/compare control 2
+TB2R=\$450; \ TB2 counter register
+TB2CCR0=\$452; \ Capture/compare register 0
+TB2CCR1=\$454; \ Capture/compare register 1
+TB2CCR2=\$456; \ Capture/compare register 2
+TB2EX0=\$460; \ TB2 expansion register 0
+TB2IV=\$46E; \ TB2 interrupt vector
+
+; RTC_B
+RTCCTL0=\$4A0; \ RTC control 0
+RTCCTL1=\$4A1; \ RTC control 1
+RTCCTL2=\$4A2; \ RTC control 2
+RTCCTL3=\$4A3; \ RTC control 3
+RTCPS0CTL=\$4A8; \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA; \ RTC prescaler 1 control
+RTCPS0=\$4AC; \ RTC prescaler 0
+RTCPS1=\$4AD; \ RTC prescaler 1
+RTCIV=\$4AE; \ RTC interrupt vector word
+RTCSEC=\$4B0; \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCMIN=\$4B1; \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCHOUR=\$4B2; \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCDOW=\$4B3; \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCDAY=\$4B4; \ RTC days
+RTCMON=\$4B5; \ RTC month
+RTCYEAR=\$4B6;
+RTCYEARL=\$4B6; \ RTC year low
+RTCYEARH=\$4B7; \ RTC year high
+RTCAMIN=\$4B8; \ RTC alarm minutes
+RTCAHOUR=\$4B9; \ RTC alarm hours
+RTCADOW=\$4BA; \ RTC alarm day of week
+RTCADAY=\$4BB; \ RTC alarm days
+BIN2BCD=\$4BC; \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE; \ BCD-to-binary conversion register
+RTCHOLD=\$40;
+RTCRDY=\$10;
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+DMAIFG=8;
+
+DMA0CTL=\$500; \ DMA channel 0 control
+DMA0SAL=\$502; \ DMA channel 0 source address low
+DMA0SAH=\$504; \ DMA channel 0 source address high
+DMA0DAL=\$506; \ DMA channel 0 destination address low
+DMA0DAH=\$508; \ DMA channel 0 destination address high
+DMA0SZ=\$50A; \ DMA channel 0 transfer size
+DMA1CTL=\$510; \ DMA channel 1 control
+DMA1SAL=\$512; \ DMA channel 1 source address low
+DMA1SAH=\$514; \ DMA channel 1 source address high
+DMA1DAL=\$516; \ DMA channel 1 destination address low
+DMA1DAH=\$518; \ DMA channel 1 destination address high
+DMA1SZ=\$51A; \ DMA channel 1 transfer size
+DMA2CTL=\$520; \ DMA channel 2 control
+DMA2SAL=\$522; \ DMA channel 2 source address low
+DMA2SAH=\$524; \ DMA channel 2 source address high
+DMA2DAL=\$526; \ DMA channel 2 destination address low
+DMA2DAH=\$528; \ DMA channel 2 destination address high
+DMA2SZ=\$52A; \ DMA channel 2 transfer size
+DMACTL0=\$530; \ DMA module control 0
+DMACTL1=\$532; \ DMA module control 1
+DMACTL2=\$534; \ DMA module control 2
+DMACTL3=\$536; \ DMA module control 3
+DMACTL4=\$538; \ DMA module control 4
+DMAIV=\$53A; \ DMA interrupt vector
+
+MPUCTL0=\$5A0; \ MPU control 0
+MPUCTL1=\$5A2; \ MPU control 1
+MPUSEG=\$5A4; \ MPU Segmentation Register
+MPUSAM=\$5A6; \ MPU access management
+
+UCA0CTLW0=\$5C0; \ eUSCI_A control word 0
+UCA0CTLW1=\$5C2; \ eUSCI_A control word 1
+UCA0BRW=\$5C6;
+UCA0BR0=\$5C6; \ eUSCI_A baud rate 0
+UCA0BR1=\$5C7; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$5C8; \ eUSCI_A modulation control
+UCA0STAT=\$5CA; \ eUSCI_A status
+UCA0RXBUF=\$5CC; \ eUSCI_A receive buffer
+UCA0TXBUF=\$5CE; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$5D0; \ eUSCI_A LIN control
+UCA0IRTCTL=\$5D2; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$5D3; \ eUSCI_A IrDA receive control
+UCA0IE=\$5DA; \ eUSCI_A interrupt enable
+UCA0IFG=\$5DC; \ eUSCI_A interrupt flags
+UCA0IV=\$5DE; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$5E0; \ eUSCI_A control word 0
+UCA1CTLW1=\$5E2; \ eUSCI_A control word 1
+UCA1BRW=\$5E6;
+UCA1BR0=\$5E6; \ eUSCI_A baud rate 0
+UCA1BR1=\$5E7; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$5E8; \ eUSCI_A modulation control
+UCA1STAT=\$5EA; \ eUSCI_A status
+UCA1RXBUF=\$5EC; \ eUSCI_A receive buffer
+UCA1TXBUF=\$5EE; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$5F0; \ eUSCI_A LIN control
+UCA1IRTCTL=\$5F2; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$5F3; \ eUSCI_A IrDA receive control
+UCA1IE=\$5FA; \ eUSCI_A interrupt enable
+UCA1IFG=\$5FC; \ eUSCI_A interrupt flags
+UCA1IV=\$5FE; \ eUSCI_A interrupt vector word
+
+UCB0CTLW0=\$640; \ eUSCI_B control word 0
+UCB0CTLW1=\$642; \ eUSCI_B control word 1
+UCB0BRW=\$646;
+UCB0BR0=\$646; \ eUSCI_B bit rate 0
+UCB0BR1=\$647; \ eUSCI_B bit rate 1
+UCB0STATW=\$648; \ eUSCI_B status word
+UCBCNT0=\$649; \ eUSCI_B hardware count
+UCB0TBCNT=\$64A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$64C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$64E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$654; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$656; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$658; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$65A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$65C; \ eUSCI_B received address
+UCB0ADDMASK=\$65E; \ eUSCI_B address mask
+UCB0I2CSA=\$660; \ eUSCI I2C slave address
+UCB0IE=\$66A; \ eUSCI interrupt enable
+UCB0IFG=\$66C; \ eUSCI interrupt flags
+UCB0IV=\$66E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+ADC10CTL0=\$700; \ ADC10_B Control register 0
+ADC10CTL1=\$702; \ ADC10_B Control register 1
+ADC10CTL2=\$704; \ ADC10_B Control register 2
+ADC10LO=\$706; \ ADC10_B Window Comparator Low Threshold
+ADC10HI=\$708; \ ADC10_B Window Comparator High Threshold
+ADC10MCTL0=\$70A; \ ADC10_B Memory Control Register 0
+ADC10MEM0=\$712; \ ADC10_B Conversion Memory Register
+ADC10IE=\$71A; \ ADC10_B Interrupt Enable
+ADC10IFG=\$71C; \ ADC10_B Interrupt Flags
+ADC10IV=\$71E; \ ADC10_B Interrupt Vector Word
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CDIFG=1;
+CDIIFG=2;
+
+CDCTL0=\$8C0; \ Comparator_D control register 0
+CDCTL1=\$8C2; \ Comparator_D control register 1
+CDCTL2=\$8C4; \ Comparator_D control register 2
+CDCTL3=\$8C6; \ Comparator_D control register 3
+CDINT=\$8CC; \ Comparator_D interrupt register
+CDIV=\$8CE; \ Comparator_D interrupt vector word
--- /dev/null
+
+@set-syntax{C;\;}! tell GEMA to replace default Comment separator '!' by ';'
+;MSP430FR57xx.pat
+
+; ----------------------------------------------
+; FastForth RAM memory map (= 1k):
+; ----------------------------------------------
+LEAVEPTR=\$1C00; Leave-stack pointer, init by QUIT
+LSATCK=\$1C00; leave stack, grow up
+PSTACK=\$1C80; parameter stack, grow down
+RSTACK=\$1CE0; Return stack, grow down
+;
+PAD_I2CADR=\$1CE0; RX I2C address
+PAD_I2CCNT=\$1CE2; count max
+PAD_ORG=\$1CE4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$1D38; TX I2C address
+TIB_I2CCNT=\$1D3A; count of bytes
+TIB_ORG=\$1D3C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$1D90; base address for HOLDS
+HOLD_BASE=\$1DB2; BASE HOLD area, grow down
+;
+HP=\$1DB2; HOLD ptr
+STATEADR=\$1DB4; Interpreter state
+BASEADR=\$1DB6; base
+CAPS=\$1DB8; CAPS ON/OFF
+SOURCE_LEN=\$1DBA; len of input stream
+SOURCE_ORG=\$1DBC; adr of input stream
+TOIN=\$1DBE; >IN
+;
+DP=\$1DC0; dictionary ptr
+LASTVOC=\$1DC2; keep VOC-LINK
+CURRENT=\$1DC4; CURRENT dictionnary ptr
+CONTEXT=\$1DC6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1DD8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$1DD8;
+LAST_THREAD=\$1DDA;
+LAST_CFA=\$1DDC;
+LAST_PSP=\$1DDE;
+ASMBW1=\$1DE0; 3 backward labels
+ASMBW2=\$1DE2;
+ASMBW3=\$1DE4;
+ASMFW1=\$1DE6; 3 forward labels
+ASMFW2=\$1DE8;
+ASMFW3=\$1DEA;
+;
+; ---------------------------------------
+; RAM_ORG + $1DEC RAM free
+; ---------------------------------------
+;
.listing off
DEVICE = "MSP430FR5948"
-
+HMPY ; hardware multiplier
; ----------------------------------------------
; MSP430FR5948 MEMORY MAP
; ----------------------------------------------
-!MSP430fr5948.pat
-
-! ----------------------------------------------
-! MSP430fr5948 MEMORY MAP
-! ----------------------------------------------
-! 0000-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
-! 1800-19FF = INFO 512 B FRAM
-! 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
-! 1C00-23FF = RAM 2 KB
-! 4400-FF7F = MAIN FRAM
-! FF80-FFFF = interrupt vectors (FRAM 128 B)
-! ----------------------------------------------
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! ; Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0100! ;
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$1C00!
-RAM_LEN=\$0800!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ---------------------------------------
-! FastForth RAM memory map (>= 1k)
-! ---------------------------------------
-LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT
-LSATCK=\$1C00! leave stack, grow up
-PSTACK=\$1C80! parameter stack, grow down
-RSTACK=\$1CE0! Return stack, grow down
-!
-PAD_I2CADR=\$1CE0! RX I2C address
-PAD_I2CCNT=\$1CE2! count max
-PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$1D38! TX I2C address
-TIB_I2CCNT=\$1D3A! count of bytes
-TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$1D90! base address for HOLDS
-HOLD_BASE=\$1DB2! BASE HOLD area, grow down
-!
-HP=\$1DB2! HOLD ptr
-LAST_NFA=\$1DB4!
-LAST_THREAD=\$1DB6!
-LAST_CFA=\$1DB8!
-LAST_PSP=\$1DBA!
-!
-STATEADR=\$1DBC! Interpreter state
-BASEADR=\$1DBE! base
-CAPS=\$1DC0! CAPS ON/OFF
-!
-SOURCE_LEN=\$1DC2! len of input stream
-SOURCE_ORG=\$1DC4! adr of input stream
-TOIN=\$1DC6! >IN
-DP=\$1DC8! dictionary ptr
-!
-LASTVOC=\$1DCA! keep VOC-LINK
-CURRENT=\$1DCC! CURRENT dictionnary ptr
-CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!1DE0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$1DFC!
-SD_BUF_I2CNT=\$1DFE!
-SD_BUF=\$1E00! \ SD_Card buffer
-BUFEND=\$2000!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2002!
-BS_FirstSectorL=\$2004!
-BS_FirstSectorH=\$2006!
-OrgFAT1=\$2008!
-FATSize=\$200A!
-OrgFAT2=\$200C!
-OrgRootDir=\$200E!
-OrgClusters=\$2010! Sector of Cluster 0
-SecPerClus=\$2012!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2014! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2014! CRC:ll word access
-SD_CMD_FRM1=\$2015! ll byte access
-SD_CMD_FRM2=\$2016! LL:hh word access
-SD_CMD_FRM3=\$2017! hh byte access
-SD_CMD_FRM4=\$2018! HH:CMD word access
-SD_CMD_FRM5=\$2019! CMD byte access
-SectorL=\$201A! 2 words
-SectorH=\$201C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$201E!
-BufferLen=\$2020!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2022! 16 bits wide (FAT16)
-ClusterH=\$2024! 16 bits wide (FAT16)
-LastFATsector=\$2026! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2028! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$202A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$202C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$202E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2030!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2032! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2034!
-EndOfPath=\$2036!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2038!
-HandleEnd=\$2118!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2118!
-SDIB_I2CCNT=\$211A!
-SDIB_ORG=\$251C!
-SDIB_LEN=\$54!
-
-SD_END=\$2170!
-SD_LEN=\$16E!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$4400! Code space start
-MAIN_LEN=\$BC00! 47 k FRAM
-! ----------------------------------------------
-
-SLEEP=\$4400! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$440A! CODE compiled by LITERAL
-XSQUOTE=\$441E! CODE compiled by S" and S_
-HEREXEC=\$4432! CODE HERE and BEGIN execute address
-MUSMOD=\$443E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$4450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$4458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$4482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$4484! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$4494! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$44A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$44AC! CODE compiled by IF UNTIL
-BRAN=\$44B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$44B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$44B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$44C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$44D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$4508! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$4512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$4554! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$457E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$4584! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$4586! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$4544! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$4546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$4550! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$4550! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$4552! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$457A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR5948
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFCC! FFCC-FFFF
-VECT_LEN=\$34!
-
-
-AES_VEC=\$FFCC!
-RTC_VEC=\$FFCE!
-P4_VEC=\$FFD0!
-P3_VEC=\$FFD2!
-TB2_X_VEC=\$FFD4!
-TB2_0_VEC=\$FFD6!
-P2_VEC=\$FFD8!
-TB1_X_VEC=\$FFDA!
-TB1_0_VEC=\$FFDC!
-P1_VEC=\$FFDE!
-TA1_X_VEC=\$FFE0!
-TA1_0_VEC=\$FFE2!
-DMA_VEC=\$FFE4!
-EUSCI_A1_VEC=\$FFE6!
-TA0_X_VEC=\$FFE8!
-TA0_0_VEC=\$FFEA!
-ADC12_B_VEC=\$FFEC!
-EUSCI_B0_VEC=\$FFEE!
-EUSCI_A0_VEC=\$FFF0!
-WDT_VEC=\$FFF2!
-TB0_X_VEC=\$FFF4!
-TB0_0_VEC=\$FFF6!
-COMP_D_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-FRCTLCTL0=\$140! \ FRAM control 0
-GCCTL0=\$144! \ General control 0
-GCCTL1=\$146! \ General control 1
-
-CRC16DI=\$150! \ CRC data input
-CRCDIRB=\$152! \ CRC data input reverse byte
-CRCINIRES=\$154! \ CRC initialization and result
-CRCRESR=\$156! \ CRC result reverse byte
-
-WDTCTL=\$15C! \ WDT control register
-
-CSCTL0=\$160! \ CS control 0
-CSCTL1=\$162! \ CS control 1
-CSCTL2=\$164! \ CS control 2
-CSCTL3=\$166! \ CS control 3
-CSCTL4=\$168! \ CS control 4
-CSCTL5=\$16A! \ CS control 5
-CSCTL6=\$16C! \ CS control 6
-
-SYSCTL=\$180! \ System control
-SYSJMBC=\$186! \ JTAG mailbox control
-SYSJMBI0=\$188! \ JTAG mailbox input 0
-SYSJMBI1=\$18A! \ JTAG mailbox input 1
-SYSJMBO0=\$18C! \ JTAG mailbox output 0
-SYSJMBO1=\$18E! \ JTAG mailbox output 1
-SYSUNIV=\$19A! \ User NMI vector generator
-SYSSNIV=\$19C! \ System NMI vector generator
-SYSRSTIV=\$19E! \ Reset vector generator
-
-REFCTL=\$1B0! \ Shared reference control
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PASELC=\$216!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1SELC=\$216!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2SELC=\$217!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-PBIN=\$220!
-PBOUT=\$222!
-PBDIR=\$224!
-PBREN=\$226!
-PBSEL0=\$22A!
-PBSEL1=\$22C!
-PBSELC=\$236!
-PBIES=\$238!
-PBIE=\$23A!
-PBIFG=\$23C!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-P3IV=\$22E!
-P3SELC=\$236!
-P3IES=\$238!
-P3IE=\$23A!
-P3IFG=\$23C!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-P4SEL1=\$22D!
-P4SELC=\$237!
-P4IES=\$239!
-P4IE=\$23B!
-P4IFG=\$23D!
-P4IV=\$23E!
-
-PJIN=\$320!
-PJOUT=\$322!
-PJDIR=\$324!
-PJREN=\$326!
-PJSEL0=\$32A!
-PJSEL1=\$32C!
-PJSELC=\$336!
-
-
-TACLR=4!
-TAIFG=1!
-TBCLR=2!
-TBIFG=1!
-CCIFG=1!
-
-TA0CTL=\$340! \ TA0 control
-TA0CCTL0=\$342! \ Capture/compare control 0
-TA0CCTL1=\$344! \ Capture/compare control 1
-TA0CCTL2=\$346! \ Capture/compare control 2
-TA0R=\$350! \ TA0 counter register
-TA0CCR0=\$352! \ Capture/compare register 0
-TA0CCR1=\$354! \ Capture/compare register 1
-TA0CCR2=\$356! \ Capture/compare register 2
-TA0EX0=\$360! \ TA0 expansion register 0
-TA0IV=\$36E! \ TA0 interrupt vector
-
-TA1CTL=\$380! \ TA1 control
-TA1CCTL0=\$382! \ Capture/compare control 0
-TA1CCTL1=\$384! \ Capture/compare control 1
-TA1CCTL2=\$386! \ Capture/compare control 2
-TA1R=\$390! \ TA1 counter register
-TA1CCR0=\$392! \ Capture/compare register 0
-TA1CCR1=\$394! \ Capture/compare register 1
-TA1CCR2=\$396! \ Capture/compare register 2
-TA1EX0=\$3A0! \ TA1 expansion register 0
-TA1IV=\$3AE! \ TA1 interrupt vector
-
-TB0CTL=\$3C0! \ TB0 control
-TB0CCTL0=\$3C2! \ Capture/compare control 0
-TB0CCTL1=\$3C4! \ Capture/compare control 1
-TB0CCTL2=\$3C6! \ Capture/compare control 2
-TB0CCTL3=\$3C8! \ Capture/compare control 3
-TB0CCTL4=\$3CA! \ Capture/compare control 4
-TB0CCTL5=\$3CC! \ Capture/compare control 5
-TB0CCTL6=\$3CE! \ Capture/compare control 6
-TB0R=\$3D0! \ TB0 counter register
-TB0CCR0=\$3D2! \ Capture/compare register 0
-TB0CCR1=\$3D4! \ Capture/compare register 1
-TB0CCR2=\$3D6! \ Capture/compare register 2
-TB0CCR3=\$3D8! \ Capture/compare register 3
-TB0CCR5=\$3DA! \ Capture/compare register 4
-TB0CCR5=\$3DC! \ Capture/compare register 5
-TB0CCR6=\$3DE! \ Capture/compare register 6
-TB0EX0=\$3E0! \ TB0 expansion register 0
-TB0IV=\$3EE! \ TB0 interrupt vector
-
-TA2CTL=\$400! \ TA2 control
-TA2CCTL0=\$402! \ Capture/compare control 0
-TA2CCTL1=\$404! \ Capture/compare control 1
-TA2R=\$410! \ TA2 counter register
-TA2CCR0=\$412! \ Capture/compare register 0
-TA2CCR1=\$414! \ Capture/compare register 1
-TA2EX0=\$420! \ TA2 expansion register 0
-TA2IV=\$42E! \ TA2 interrupt vector
-
-TA3CTL=\$440! \ TA3 control
-TA3CCTL0=\$442! \ Capture/compare control 0
-TA3CCTL1=\$444! \ Capture/compare control 1
-TA3R=\$450! \ TA3 counter register
-TA3CCR0=\$452! \ Capture/compare register 0
-TA3CCR1=\$454! \ Capture/compare register 1
-TA3EX0=\$460! \ TA3 expansion register 0
-TA3IV=\$46E! \ TA3 interrupt vector
-
-! \ RTC_B
-RTCCTL0=\$4A0! \ RTC control 0
-RTCCTL1=\$4A1! \ RTC control 1
-RTCCTL2=\$4A2! \ RTC control 2
-RTCCTL3=\$4A3! \ RTC control 3
-RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
-RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
-RTCPS0=\$4AC! \ RTC prescaler 0
-RTCPS1=\$4AD! \ RTC prescaler 1
-RTCIV=\$4AE! \ RTC interrupt vector word
-RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
-RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
-RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
-RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
-RTCDAY=\$4B4! \ RTC days
-RTCMON=\$4B5! \ RTC month
-RTCYEAR=\$4B6!
-RTCYEARL=\$4B6! \ RTC year low
-RTCYEARH=\$4B7! \ RTC year high
-RTCAMIN=\$4B8! \ RTC alarm minutes
-RTCAHOUR=\$4B9! \ RTC alarm hours
-RTCADOW=\$4BA! \ RTC alarm day of week
-RTCADAY=\$4BB! \ RTC alarm days
-BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
-BCD2BIN=\$4BE! \ BCD-to-binary conversion register
-RTCHOLD=\$40!
-RTCRDY=\$10!
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-DMAIFG=8!
-
-DMACTL0=\$500! \ DMA module control 0
-DMACTL1=\$502! \ DMA module control 1
-DMACTL2=\$504! \ DMA module control 2
-DMACTL3=\$506! \ DMA module control 3
-DMACTL4=\$508! \ DMA module control 4
-DMAIV=\$50A! \ DMA interrupt vector
-
-DMA0CTL=\$510! \ DMA channel 0 control
-DMA0SAL=\$512! \ DMA channel 0 source address low
-DMA0SAH=\$514! \ DMA channel 0 source address high
-DMA0DAL=\$516! \ DMA channel 0 destination address low
-DMA0DAH=\$518! \ DMA channel 0 destination address high
-DMA0SZ=\$51A! \ DMA channel 0 transfer size
-
-DMA1CTL=\$520! \ DMA channel 1 control
-DMA1SAL=\$522! \ DMA channel 1 source address low
-DMA1SAH=\$524! \ DMA channel 1 source address high
-DMA1DAL=\$526! \ DMA channel 1 destination address low
-DMA1DAH=\$528! \ DMA channel 1 destination address high
-DMA1SZ=\$52A! \ DMA channel 1 transfer size
-
-DMA2CTL=\$530! \ DMA channel 2 control
-DMA2SAL=\$532! \ DMA channel 2 source address low
-DMA2SAH=\$534! \ DMA channel 2 source address high
-DMA2DAL=\$536! \ DMA channel 2 destination address low
-DMA2DAH=\$538! \ DMA channel 2 destination address high
-DMA2SZ=\$53A! \ DMA channel 2 transfer size
-
-
-MPUCTL0=\$5A0! \ MPU control 0
-MPUCTL1=\$5A2! \ MPU control 1
-MPUSEGB2=\$5A4! \ MPU Segmentation Border2
-MPUSEGB1=\$5A6! \ MPU Segmentation Border1
-MPUSAM=\$5A8! \ MPU access management
-MPUIPC0=\$5AA! \ MPU IP control 0
-MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2
-MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1
-
-UCA0CTLW0=\$5C0! \ eUSCI_A control word 0
-UCA0CTLW1=\$5C2! \ eUSCI_A control word 1
-UCA0BRW=\$5C6!
-UCA0BR0=\$5C6! \ eUSCI_A baud rate 0
-UCA0BR1=\$5C7! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$5C8! \ eUSCI_A modulation control
-UCA0STAT=\$5CA! \ eUSCI_A status
-UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer
-UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$5D0! \ eUSCI_A LIN control
-UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-UCA0IE=\$5DA! \ eUSCI_A interrupt enable
-UCA0IFG=\$5DC! \ eUSCI_A interrupt flags
-UCA0IV=\$5DE! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$5E0! \ eUSCI_A control word 0
-UCA1CTLW1=\$5E2! \ eUSCI_A control word 1
-UCA1BRW=\$5E6!
-UCA1BR0=\$5E6! \ eUSCI_A baud rate 0
-UCA1BR1=\$5E7! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$5E8! \ eUSCI_A modulation control
-UCA1STAT=\$5EA! \ eUSCI_A status
-UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer
-UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$5F0! \ eUSCI_A LIN control
-UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control
-UCA1IE=\$5FA! \ eUSCI_A interrupt enable
-UCA1IFG=\$5FC! \ eUSCI_A interrupt flags
-UCA1IV=\$5FE! \ eUSCI_A interrupt vector word
-
-UCB0CTLW0=\$640! \ eUSCI_B control word 0
-UCB0CTLW1=\$642! \ eUSCI_B control word 1
-UCB0BRW=\$646!
-UCB0BR0=\$646! \ eUSCI_B bit rate 0
-UCB0BR1=\$647! \ eUSCI_B bit rate 1
-UCB0STATW=\$648! \ eUSCI_B status word
-UCBCNT0=\$649! \ eUSCI_B hardware count
-UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$64C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$65C! \ eUSCI_B received address
-UCB0ADDMASK=\$65E! \ eUSCI_B address mask
-UCB0I2CSA=\$660! \ eUSCI I2C slave address
-UCB0IE=\$66A! \ eUSCI interrupt enable
-UCB0IFG=\$66C! \ eUSCI interrupt flags
-UCB0IV=\$66E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-
-ADC12CTL0=\$800! \ ADC12_B Control 0
-ADC12CTL1=\$802! \ ADC12_B Control 1
-ADC12CTL2=\$804! \ ADC12_B Control 2
-ADC12CTL3=\$806! \ ADC12_B Control 3
-ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register
-ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register
-ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0
-ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1
-ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2
-ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0
-ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1
-ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2
-ADC12IV=\$818! \ ADC12_B Interrupt Vector
-ADC12MCTL0=\$820! \ ADC12_B Memory Control 0
-ADC12MCTL1=\$822! \ ADC12_B Memory Control 1
-ADC12MCTL2=\$824! \ ADC12_B Memory Control 2
-ADC12MCTL3=\$826! \ ADC12_B Memory Control 3
-ADC12MCTL4=\$828! \ ADC12_B Memory Control 4
-ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5
-ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6
-ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7
-ADC12MCTL8=\$830! \ ADC12_B Memory Control 8
-ADC12MCTL9=\$832! \ ADC12_B Memory Control 9
-ADC12MCTL10=\$834! \ ADC12_B Memory Control 10
-ADC12MCTL11=\$836! \ ADC12_B Memory Control 11
-ADC12MCTL12=\$838! \ ADC12_B Memory Control 12
-ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13
-ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14
-ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15
-ADC12MCTL16=\$840! \ ADC12_B Memory Control 16
-ADC12MCTL17=\$842! \ ADC12_B Memory Control 17
-ADC12MCTL18=\$844! \ ADC12_B Memory Control 18
-ADC12MCTL19=\$846! \ ADC12_B Memory Control 19
-ADC12MCTL20=\$848! \ ADC12_B Memory Control 20
-ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21
-ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22
-ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23
-ADC12MCTL24=\$850! \ ADC12_B Memory Control 24
-ADC12MCTL25=\$852! \ ADC12_B Memory Control 25
-ADC12MCTL26=\$854! \ ADC12_B Memory Control 26
-ADC12MCTL27=\$856! \ ADC12_B Memory Control 27
-ADC12MCTL28=\$858! \ ADC12_B Memory Control 28
-ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29
-ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30
-ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31
-ADC12MEM0=\$860! \ ADC12_B Memory 0
-ADC12MEM1=\$862! \ ADC12_B Memory 1
-ADC12MEM2=\$864! \ ADC12_B Memory 2
-ADC12MEM3=\$866! \ ADC12_B Memory 3
-ADC12MEM4=\$868! \ ADC12_B Memory 4
-ADC12MEM5=\$86A! \ ADC12_B Memory 5
-ADC12MEM6=\$86C! \ ADC12_B Memory 6
-ADC12MEM7=\$86E! \ ADC12_B Memory 7
-ADC12MEM8=\$870! \ ADC12_B Memory 8
-ADC12MEM9=\$872! \ ADC12_B Memory 9
-ADC12MEM10=\$874! \ ADC12_B Memory 10
-ADC12MEM11=\$876! \ ADC12_B Memory 11
-ADC12MEM12=\$878! \ ADC12_B Memory 12
-ADC12MEM13=\$87A! \ ADC12_B Memory 13
-ADC12MEM14=\$87C! \ ADC12_B Memory 14
-ADC12MEM15=\$87E! \ ADC12_B Memory 15
-ADC12MEM16=\$880! \ ADC12_B Memory 16
-ADC12MEM17=\$882! \ ADC12_B Memory 17
-ADC12MEM18=\$884! \ ADC12_B Memory 18
-ADC12MEM19=\$886! \ ADC12_B Memory 19
-ADC12MEM20=\$888! \ ADC12_B Memory 20
-ADC12MEM21=\$88A! \ ADC12_B Memory 21
-ADC12MEM22=\$88C! \ ADC12_B Memory 22
-ADC12MEM23=\$88E! \ ADC12_B Memory 23
-ADC12MEM24=\$890! \ ADC12_B Memory 24
-ADC12MEM25=\$892! \ ADC12_B Memory 25
-ADC12MEM26=\$894! \ ADC12_B Memory 26
-ADC12MEM27=\$896! \ ADC12_B Memory 27
-ADC12MEM28=\$898! \ ADC12_B Memory 28
-ADC12MEM29=\$89A! \ ADC12_B Memory 29
-ADC12MEM30=\$89C! \ ADC12_B Memory 30
-ADC12MEM31=\$89E! \ ADC12_B Memory 31
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-CDIFG=1!
-CDIIFG=2!
-
-CDCTL0=\$8C0! \ Comparator_E control register 0
-CDCTL1=\$8C2! \ Comparator_E control register 1
-CDCTL2=\$8C4! \ Comparator_E control register 2
-CDCTL3=\$8C6! \ Comparator_E control register 3
-CDINT=\$8CC! \ Comparator_E interrupt register
-CDIV=\$8CE! \ Comparator_E interrupt vector word
-
-
-AESACTL0=\$9C0! \ AES accelerator control register 0
-AESASTAT=\$9C4! \ AES accelerator status register
-AESAKEY=\$9C6! \ AES accelerator key register
-AESADIN=\$9C8! \ AES accelerator data in register
-AESADOUT=\$9CA! \ AES accelerator data out register
-AESAXDIN=\$9CC! \ AES accelerator XORed data in register
-AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger)
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430fr5948.pat
+
+; ----------------------------------------------
+; MSP430fr5948 MEMORY MAP
+; ----------------------------------------------
+; 0000-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
+; 1800-19FF = INFO 512 B FRAM
+; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
+; 1C00-23FF = RAM 2 KB
+; 4400-FF7F = MAIN FRAM
+; FF80-FFFF = interrupt vectors (FRAM 128 B)
+; ----------------------------------------------
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$1C00;
+RAM_LEN=\$0800;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ---------------------------------------
+; FastForth RAM memory map (>= 1k)
+; ---------------------------------------
+LEAVEPTR=\$1C00; Leave-stack pointer, init by QUIT
+LSATCK=\$1C00; leave stack, grow up
+PSTACK=\$1C80; parameter stack, grow down
+RSTACK=\$1CE0; Return stack, grow down
+;
+PAD_I2CADR=\$1CE0; RX I2C address
+PAD_I2CCNT=\$1CE2; count max
+PAD_ORG=\$1CE4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$1D38; TX I2C address
+TIB_I2CCNT=\$1D3A; count of bytes
+TIB_ORG=\$1D3C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$1D90; base address for HOLDS
+HOLD_BASE=\$1DB2; BASE HOLD area, grow down
+;
+HP=\$1DB2; HOLD ptr
+STATEADR=\$1DB4; Interpreter state
+BASEADR=\$1DB6; base
+CAPS=\$1DB8; CAPS ON/OFF
+SOURCE_LEN=\$1DBA; len of input stream
+SOURCE_ORG=\$1DBC; adr of input stream
+TOIN=\$1DBE; >IN
+;
+DP=\$1DC0; dictionary ptr
+LASTVOC=\$1DC2; keep VOC-LINK
+CURRENT=\$1DC4; CURRENT dictionnary ptr
+CONTEXT=\$1DC6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$1DD8;
+LAST_THREAD=\$1DDA;
+LAST_CFA=\$1DDC;
+LAST_PSP=\$1DDE;
+ASM_CURR=\$1DE0; CODE saves CURRENT, ENDCODE restores CURRENT
+ASMBW1=\$1DE2; 3 backward labels
+ASMBW2=\$1DE4;
+ASMBW3=\$1DE6;
+ASMFW1=\$1DE8; 3 forward labels
+ASMFW2=\$1DEA;
+ASMFW3=\$1DEC;
+;
+; ---------------------------------------
+; RAM_ORG + $1EE RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$1DFC;
+SD_BUF_I2CNT=\$1DFE;
+SD_BUF=\$1E00; \ SD_Card buffer
+BUFEND=\$2000;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2002;
+BS_FirstSectorL=\$2004;
+BS_FirstSectorH=\$2006;
+OrgFAT1=\$2008;
+FATSize=\$200A;
+OrgFAT2=\$200C;
+OrgRootDir=\$200E;
+OrgClusters=\$2010; Sector of Cluster 0
+SecPerClus=\$2012;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2014; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2014; CRC:ll word access
+SD_CMD_FRM1=\$2015; ll byte access
+SD_CMD_FRM2=\$2016; LL:hh word access
+SD_CMD_FRM3=\$2017; hh byte access
+SD_CMD_FRM4=\$2018; HH:CMD word access
+SD_CMD_FRM5=\$2019; CMD byte access
+SectorL=\$201A; 2 words
+SectorH=\$201C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$201E;
+BufferLen=\$2020;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2022; 16 bits wide (FAT16)
+ClusterH=\$2024; 16 bits wide (FAT16)
+LastFATsector=\$2026; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2028; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$202A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$202C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$202E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2030;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2032; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2034;
+EndOfPath=\$2036;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2038;
+HandleEnd=\$2118;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2118;
+SDIB_I2CCNT=\$211A;
+SDIB_ORG=\$251C;
+SDIB_LEN=\$54;
+
+SD_END=\$2170;
+SD_LEN=\$16E;
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$4400; Code space start
+MAIN_LEN=\$BC00; 47 k FRAM
+; ----------------------------------------------
+\#LIT=\#\$4400; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$4414; asm CODE run time of QUOTE
+\#MUSMOD=\#\$4428; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$443A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$4442; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$446C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$446E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$447E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$448A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$4496; CODE compiled by IF UNTIL
+\#BRAN=\#\$449C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$449E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$44A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$44AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$44BA;
+\#ABORT_TERM=\#\$4500; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$4572; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$455C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR5948
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFCC; FFCC-FFFF
+VECT_LEN=\$34;
+
+
+AES_VEC=\$FFCC;
+RTC_VEC=\$FFCE;
+P4_VEC=\$FFD0;
+P3_VEC=\$FFD2;
+TB2_X_VEC=\$FFD4;
+TB2_0_VEC=\$FFD6;
+P2_VEC=\$FFD8;
+TB1_X_VEC=\$FFDA;
+TB1_0_VEC=\$FFDC;
+P1_VEC=\$FFDE;
+TA1_X_VEC=\$FFE0;
+TA1_0_VEC=\$FFE2;
+DMA_VEC=\$FFE4;
+EUSCI_A1_VEC=\$FFE6;
+TA0_X_VEC=\$FFE8;
+TA0_0_VEC=\$FFEA;
+ADC12_B_VEC=\$FFEC;
+EUSCI_B0_VEC=\$FFEE;
+EUSCI_A0_VEC=\$FFF0;
+WDT_VEC=\$FFF2;
+TB0_X_VEC=\$FFF4;
+TB0_0_VEC=\$FFF6;
+COMP_D_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+FRCTLCTL0=\$140; \ FRAM control 0
+GCCTL0=\$144; \ General control 0
+GCCTL1=\$146; \ General control 1
+
+CRC16DI=\$150; \ CRC data input
+CRCDIRB=\$152; \ CRC data input reverse byte
+CRCINIRES=\$154; \ CRC initialization and result
+CRCRESR=\$156; \ CRC result reverse byte
+
+WDTCTL=\$15C; \ WDT control register
+
+CSCTL0=\$160; \ CS control 0
+CSCTL1=\$162; \ CS control 1
+CSCTL2=\$164; \ CS control 2
+CSCTL3=\$166; \ CS control 3
+CSCTL4=\$168; \ CS control 4
+CSCTL5=\$16A; \ CS control 5
+CSCTL6=\$16C; \ CS control 6
+
+SYSCTL=\$180; \ System control
+SYSJMBC=\$186; \ JTAG mailbox control
+SYSJMBI0=\$188; \ JTAG mailbox input 0
+SYSJMBI1=\$18A; \ JTAG mailbox input 1
+SYSJMBO0=\$18C; \ JTAG mailbox output 0
+SYSJMBO1=\$18E; \ JTAG mailbox output 1
+SYSUNIV=\$19A; \ User NMI vector generator
+SYSSNIV=\$19C; \ System NMI vector generator
+SYSRSTIV=\$19E; \ Reset vector generator
+
+REFCTL=\$1B0; \ Shared reference control
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PASELC=\$216;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1SELC=\$216;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2SELC=\$217;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+PBIN=\$220;
+PBOUT=\$222;
+PBDIR=\$224;
+PBREN=\$226;
+PBSEL0=\$22A;
+PBSEL1=\$22C;
+PBSELC=\$236;
+PBIES=\$238;
+PBIE=\$23A;
+PBIFG=\$23C;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+P3IV=\$22E;
+P3SELC=\$236;
+P3IES=\$238;
+P3IE=\$23A;
+P3IFG=\$23C;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+P4SEL1=\$22D;
+P4SELC=\$237;
+P4IES=\$239;
+P4IE=\$23B;
+P4IFG=\$23D;
+P4IV=\$23E;
+
+PJIN=\$320;
+PJOUT=\$322;
+PJDIR=\$324;
+PJREN=\$326;
+PJSEL0=\$32A;
+PJSEL1=\$32C;
+PJSELC=\$336;
+
+
+TACLR=4;
+TAIFG=1;
+TBCLR=2;
+TBIFG=1;
+CCIFG=1;
+
+TA0CTL=\$340; \ TA0 control
+TA0CCTL0=\$342; \ Capture/compare control 0
+TA0CCTL1=\$344; \ Capture/compare control 1
+TA0CCTL2=\$346; \ Capture/compare control 2
+TA0R=\$350; \ TA0 counter register
+TA0CCR0=\$352; \ Capture/compare register 0
+TA0CCR1=\$354; \ Capture/compare register 1
+TA0CCR2=\$356; \ Capture/compare register 2
+TA0EX0=\$360; \ TA0 expansion register 0
+TA0IV=\$36E; \ TA0 interrupt vector
+
+TA1CTL=\$380; \ TA1 control
+TA1CCTL0=\$382; \ Capture/compare control 0
+TA1CCTL1=\$384; \ Capture/compare control 1
+TA1CCTL2=\$386; \ Capture/compare control 2
+TA1R=\$390; \ TA1 counter register
+TA1CCR0=\$392; \ Capture/compare register 0
+TA1CCR1=\$394; \ Capture/compare register 1
+TA1CCR2=\$396; \ Capture/compare register 2
+TA1EX0=\$3A0; \ TA1 expansion register 0
+TA1IV=\$3AE; \ TA1 interrupt vector
+
+TB0CTL=\$3C0; \ TB0 control
+TB0CCTL0=\$3C2; \ Capture/compare control 0
+TB0CCTL1=\$3C4; \ Capture/compare control 1
+TB0CCTL2=\$3C6; \ Capture/compare control 2
+TB0CCTL3=\$3C8; \ Capture/compare control 3
+TB0CCTL4=\$3CA; \ Capture/compare control 4
+TB0CCTL5=\$3CC; \ Capture/compare control 5
+TB0CCTL6=\$3CE; \ Capture/compare control 6
+TB0R=\$3D0; \ TB0 counter register
+TB0CCR0=\$3D2; \ Capture/compare register 0
+TB0CCR1=\$3D4; \ Capture/compare register 1
+TB0CCR2=\$3D6; \ Capture/compare register 2
+TB0CCR3=\$3D8; \ Capture/compare register 3
+TB0CCR5=\$3DA; \ Capture/compare register 4
+TB0CCR5=\$3DC; \ Capture/compare register 5
+TB0CCR6=\$3DE; \ Capture/compare register 6
+TB0EX0=\$3E0; \ TB0 expansion register 0
+TB0IV=\$3EE; \ TB0 interrupt vector
+
+TA2CTL=\$400; \ TA2 control
+TA2CCTL0=\$402; \ Capture/compare control 0
+TA2CCTL1=\$404; \ Capture/compare control 1
+TA2R=\$410; \ TA2 counter register
+TA2CCR0=\$412; \ Capture/compare register 0
+TA2CCR1=\$414; \ Capture/compare register 1
+TA2EX0=\$420; \ TA2 expansion register 0
+TA2IV=\$42E; \ TA2 interrupt vector
+
+TA3CTL=\$440; \ TA3 control
+TA3CCTL0=\$442; \ Capture/compare control 0
+TA3CCTL1=\$444; \ Capture/compare control 1
+TA3R=\$450; \ TA3 counter register
+TA3CCR0=\$452; \ Capture/compare register 0
+TA3CCR1=\$454; \ Capture/compare register 1
+TA3EX0=\$460; \ TA3 expansion register 0
+TA3IV=\$46E; \ TA3 interrupt vector
+
+; \ RTC_B
+RTCCTL0=\$4A0; \ RTC control 0
+RTCCTL1=\$4A1; \ RTC control 1
+RTCCTL2=\$4A2; \ RTC control 2
+RTCCTL3=\$4A3; \ RTC control 3
+RTCPS0CTL=\$4A8; \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA; \ RTC prescaler 1 control
+RTCPS0=\$4AC; \ RTC prescaler 0
+RTCPS1=\$4AD; \ RTC prescaler 1
+RTCIV=\$4AE; \ RTC interrupt vector word
+RTCSEC=\$4B0; \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCMIN=\$4B1; \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCHOUR=\$4B2; \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCDOW=\$4B3; \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCDAY=\$4B4; \ RTC days
+RTCMON=\$4B5; \ RTC month
+RTCYEAR=\$4B6;
+RTCYEARL=\$4B6; \ RTC year low
+RTCYEARH=\$4B7; \ RTC year high
+RTCAMIN=\$4B8; \ RTC alarm minutes
+RTCAHOUR=\$4B9; \ RTC alarm hours
+RTCADOW=\$4BA; \ RTC alarm day of week
+RTCADAY=\$4BB; \ RTC alarm days
+BIN2BCD=\$4BC; \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE; \ BCD-to-binary conversion register
+RTCHOLD=\$40;
+RTCRDY=\$10;
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+DMAIFG=8;
+
+DMACTL0=\$500; \ DMA module control 0
+DMACTL1=\$502; \ DMA module control 1
+DMACTL2=\$504; \ DMA module control 2
+DMACTL3=\$506; \ DMA module control 3
+DMACTL4=\$508; \ DMA module control 4
+DMAIV=\$50A; \ DMA interrupt vector
+
+DMA0CTL=\$510; \ DMA channel 0 control
+DMA0SAL=\$512; \ DMA channel 0 source address low
+DMA0SAH=\$514; \ DMA channel 0 source address high
+DMA0DAL=\$516; \ DMA channel 0 destination address low
+DMA0DAH=\$518; \ DMA channel 0 destination address high
+DMA0SZ=\$51A; \ DMA channel 0 transfer size
+
+DMA1CTL=\$520; \ DMA channel 1 control
+DMA1SAL=\$522; \ DMA channel 1 source address low
+DMA1SAH=\$524; \ DMA channel 1 source address high
+DMA1DAL=\$526; \ DMA channel 1 destination address low
+DMA1DAH=\$528; \ DMA channel 1 destination address high
+DMA1SZ=\$52A; \ DMA channel 1 transfer size
+
+DMA2CTL=\$530; \ DMA channel 2 control
+DMA2SAL=\$532; \ DMA channel 2 source address low
+DMA2SAH=\$534; \ DMA channel 2 source address high
+DMA2DAL=\$536; \ DMA channel 2 destination address low
+DMA2DAH=\$538; \ DMA channel 2 destination address high
+DMA2SZ=\$53A; \ DMA channel 2 transfer size
+
+
+MPUCTL0=\$5A0; \ MPU control 0
+MPUCTL1=\$5A2; \ MPU control 1
+MPUSEGB2=\$5A4; \ MPU Segmentation Border2
+MPUSEGB1=\$5A6; \ MPU Segmentation Border1
+MPUSAM=\$5A8; \ MPU access management
+MPUIPC0=\$5AA; \ MPU IP control 0
+MPUIPSEGB2=\$5AC; \ MPU IP Encapsulation Segment Border 2
+MPUIPSEGB1=\$5AE; \ MPU IP Encapsulation Segment Border 1
+
+UCA0CTLW0=\$5C0; \ eUSCI_A control word 0
+UCA0CTLW1=\$5C2; \ eUSCI_A control word 1
+UCA0BRW=\$5C6;
+UCA0BR0=\$5C6; \ eUSCI_A baud rate 0
+UCA0BR1=\$5C7; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$5C8; \ eUSCI_A modulation control
+UCA0STAT=\$5CA; \ eUSCI_A status
+UCA0RXBUF=\$5CC; \ eUSCI_A receive buffer
+UCA0TXBUF=\$5CE; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$5D0; \ eUSCI_A LIN control
+UCA0IRTCTL=\$5D2; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$5D3; \ eUSCI_A IrDA receive control
+UCA0IE=\$5DA; \ eUSCI_A interrupt enable
+UCA0IFG=\$5DC; \ eUSCI_A interrupt flags
+UCA0IV=\$5DE; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$5E0; \ eUSCI_A control word 0
+UCA1CTLW1=\$5E2; \ eUSCI_A control word 1
+UCA1BRW=\$5E6;
+UCA1BR0=\$5E6; \ eUSCI_A baud rate 0
+UCA1BR1=\$5E7; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$5E8; \ eUSCI_A modulation control
+UCA1STAT=\$5EA; \ eUSCI_A status
+UCA1RXBUF=\$5EC; \ eUSCI_A receive buffer
+UCA1TXBUF=\$5EE; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$5F0; \ eUSCI_A LIN control
+UCA1IRTCTL=\$5F2; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$5F3; \ eUSCI_A IrDA receive control
+UCA1IE=\$5FA; \ eUSCI_A interrupt enable
+UCA1IFG=\$5FC; \ eUSCI_A interrupt flags
+UCA1IV=\$5FE; \ eUSCI_A interrupt vector word
+
+UCB0CTLW0=\$640; \ eUSCI_B control word 0
+UCB0CTLW1=\$642; \ eUSCI_B control word 1
+UCB0BRW=\$646;
+UCB0BR0=\$646; \ eUSCI_B bit rate 0
+UCB0BR1=\$647; \ eUSCI_B bit rate 1
+UCB0STATW=\$648; \ eUSCI_B status word
+UCBCNT0=\$649; \ eUSCI_B hardware count
+UCB0TBCNT=\$64A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$64C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$64E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$654; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$656; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$658; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$65A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$65C; \ eUSCI_B received address
+UCB0ADDMASK=\$65E; \ eUSCI_B address mask
+UCB0I2CSA=\$660; \ eUSCI I2C slave address
+UCB0IE=\$66A; \ eUSCI interrupt enable
+UCB0IFG=\$66C; \ eUSCI interrupt flags
+UCB0IV=\$66E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+
+ADC12CTL0=\$800; \ ADC12_B Control 0
+ADC12CTL1=\$802; \ ADC12_B Control 1
+ADC12CTL2=\$804; \ ADC12_B Control 2
+ADC12CTL3=\$806; \ ADC12_B Control 3
+ADC12LO=\$808; \ ADC12_B Window Comparator Low Threshold Register
+ADC12HI=\$80A; \ ADC12_B Window Comparator High Threshold Register
+ADC12IFGR0=\$80C; \ ADC12_B Interrupt Flag Register 0
+ADC12IFGR1=\$80E; \ ADC12_B Interrupt Flag Register 1
+ADC12IFGR2=\$810; \ ADC12_B Interrupt Flag Register 2
+ADC12IER0=\$812; \ ADC12_B Interrupt Enable Register 0
+ADC12IER1=\$814; \ ADC12_B Interrupt Enable Register 1
+ADC12IER2=\$816; \ ADC12_B Interrupt Enable Register 2
+ADC12IV=\$818; \ ADC12_B Interrupt Vector
+ADC12MCTL0=\$820; \ ADC12_B Memory Control 0
+ADC12MCTL1=\$822; \ ADC12_B Memory Control 1
+ADC12MCTL2=\$824; \ ADC12_B Memory Control 2
+ADC12MCTL3=\$826; \ ADC12_B Memory Control 3
+ADC12MCTL4=\$828; \ ADC12_B Memory Control 4
+ADC12MCTL5=\$82A; \ ADC12_B Memory Control 5
+ADC12MCTL6=\$82C; \ ADC12_B Memory Control 6
+ADC12MCTL7=\$82E; \ ADC12_B Memory Control 7
+ADC12MCTL8=\$830; \ ADC12_B Memory Control 8
+ADC12MCTL9=\$832; \ ADC12_B Memory Control 9
+ADC12MCTL10=\$834; \ ADC12_B Memory Control 10
+ADC12MCTL11=\$836; \ ADC12_B Memory Control 11
+ADC12MCTL12=\$838; \ ADC12_B Memory Control 12
+ADC12MCTL13=\$83A; \ ADC12_B Memory Control 13
+ADC12MCTL14=\$83C; \ ADC12_B Memory Control 14
+ADC12MCTL15=\$83E; \ ADC12_B Memory Control 15
+ADC12MCTL16=\$840; \ ADC12_B Memory Control 16
+ADC12MCTL17=\$842; \ ADC12_B Memory Control 17
+ADC12MCTL18=\$844; \ ADC12_B Memory Control 18
+ADC12MCTL19=\$846; \ ADC12_B Memory Control 19
+ADC12MCTL20=\$848; \ ADC12_B Memory Control 20
+ADC12MCTL21=\$84A; \ ADC12_B Memory Control 21
+ADC12MCTL22=\$84C; \ ADC12_B Memory Control 22
+ADC12MCTL23=\$84E; \ ADC12_B Memory Control 23
+ADC12MCTL24=\$850; \ ADC12_B Memory Control 24
+ADC12MCTL25=\$852; \ ADC12_B Memory Control 25
+ADC12MCTL26=\$854; \ ADC12_B Memory Control 26
+ADC12MCTL27=\$856; \ ADC12_B Memory Control 27
+ADC12MCTL28=\$858; \ ADC12_B Memory Control 28
+ADC12MCTL29=\$85A; \ ADC12_B Memory Control 29
+ADC12MCTL30=\$85C; \ ADC12_B Memory Control 30
+ADC12MCTL31=\$85E; \ ADC12_B Memory Control 31
+ADC12MEM0=\$860; \ ADC12_B Memory 0
+ADC12MEM1=\$862; \ ADC12_B Memory 1
+ADC12MEM2=\$864; \ ADC12_B Memory 2
+ADC12MEM3=\$866; \ ADC12_B Memory 3
+ADC12MEM4=\$868; \ ADC12_B Memory 4
+ADC12MEM5=\$86A; \ ADC12_B Memory 5
+ADC12MEM6=\$86C; \ ADC12_B Memory 6
+ADC12MEM7=\$86E; \ ADC12_B Memory 7
+ADC12MEM8=\$870; \ ADC12_B Memory 8
+ADC12MEM9=\$872; \ ADC12_B Memory 9
+ADC12MEM10=\$874; \ ADC12_B Memory 10
+ADC12MEM11=\$876; \ ADC12_B Memory 11
+ADC12MEM12=\$878; \ ADC12_B Memory 12
+ADC12MEM13=\$87A; \ ADC12_B Memory 13
+ADC12MEM14=\$87C; \ ADC12_B Memory 14
+ADC12MEM15=\$87E; \ ADC12_B Memory 15
+ADC12MEM16=\$880; \ ADC12_B Memory 16
+ADC12MEM17=\$882; \ ADC12_B Memory 17
+ADC12MEM18=\$884; \ ADC12_B Memory 18
+ADC12MEM19=\$886; \ ADC12_B Memory 19
+ADC12MEM20=\$888; \ ADC12_B Memory 20
+ADC12MEM21=\$88A; \ ADC12_B Memory 21
+ADC12MEM22=\$88C; \ ADC12_B Memory 22
+ADC12MEM23=\$88E; \ ADC12_B Memory 23
+ADC12MEM24=\$890; \ ADC12_B Memory 24
+ADC12MEM25=\$892; \ ADC12_B Memory 25
+ADC12MEM26=\$894; \ ADC12_B Memory 26
+ADC12MEM27=\$896; \ ADC12_B Memory 27
+ADC12MEM28=\$898; \ ADC12_B Memory 28
+ADC12MEM29=\$89A; \ ADC12_B Memory 29
+ADC12MEM30=\$89C; \ ADC12_B Memory 30
+ADC12MEM31=\$89E; \ ADC12_B Memory 31
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CDIFG=1;
+CDIIFG=2;
+
+CDCTL0=\$8C0; \ Comparator_E control register 0
+CDCTL1=\$8C2; \ Comparator_E control register 1
+CDCTL2=\$8C4; \ Comparator_E control register 2
+CDCTL3=\$8C6; \ Comparator_E control register 3
+CDINT=\$8CC; \ Comparator_E interrupt register
+CDIV=\$8CE; \ Comparator_E interrupt vector word
+
+
+AESACTL0=\$9C0; \ AES accelerator control register 0
+AESASTAT=\$9C4; \ AES accelerator status register
+AESAKEY=\$9C6; \ AES accelerator key register
+AESADIN=\$9C8; \ AES accelerator data in register
+AESADOUT=\$9CA; \ AES accelerator data out register
+AESAXDIN=\$9CC; \ AES accelerator XORed data in register
+AESAXIN =\$9CE; \ AES accelerator XORed data in register (no trigger)
.listing off
DEVICE = "MSP430FR5969"
-
+HMPY ; hardware multiplier
; ----------------------------------------------
; MSP430FR5969 MEMORY MAP
; ----------------------------------------------
-!MSP430fr5969.pat
-
-! ----------------------------------------------
-! MSP430FR5969 MEMORY MAP
-! ----------------------------------------------
-! 0000-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
-! 1800-19FF = FRAM INFO 512 B
-! 1A00-1AFF = TLV device descriptor info (FRAM 256 B)
-! 1C00-23FF = RAM (2 KB)
-! 4400-FF7F = MAIN (FRAM 47 kB)
-! FF80-FFFF = interrupt vectors (FRAM 127 B)
-! ----------------------------------------------
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! ; Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0100! ;
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$1C00!
-RAM_LEN=\$0800!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ---------------------------------------
-! FastForth RAM memory map (>= 1k)
-! ---------------------------------------
-LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT
-LSATCK=\$1C00! leave stack, grow up
-PSTACK=\$1C80! parameter stack, grow down
-RSTACK=\$1CE0! Return stack, grow down
-!
-PAD_I2CADR=\$1CE0! RX I2C address
-PAD_I2CCNT=\$1CE2! count max
-PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$1D38! TX I2C address
-TIB_I2CCNT=\$1D3A! count of bytes
-TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$1D90! base address for HOLDS
-HOLD_BASE=\$1DB2! BASE HOLD area, grow down
-!
-HP=\$1DB2! HOLD ptr
-LAST_NFA=\$1DB4!
-LAST_THREAD=\$1DB6!
-LAST_CFA=\$1DB8!
-LAST_PSP=\$1DBA!
-!
-STATEADR=\$1DBC! Interpreter state
-BASEADR=\$1DBE! base
-CAPS=\$1DC0! CAPS ON/OFF
-!
-SOURCE_LEN=\$1DC2! len of input stream
-SOURCE_ORG=\$1DC4! adr of input stream
-TOIN=\$1DC6! >IN
-DP=\$1DC8! dictionary ptr
-!
-LASTVOC=\$1DCA! keep VOC-LINK
-CURRENT=\$1DCC! CURRENT dictionnary ptr
-CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!1DE0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$1DFC!
-SD_BUF_I2CNT=\$1DFE!
-SD_BUF=\$1E00! \ SD_Card buffer
-BUFEND=\$2000!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2002!
-BS_FirstSectorL=\$2004!
-BS_FirstSectorH=\$2006!
-OrgFAT1=\$2008!
-FATSize=\$200A!
-OrgFAT2=\$200C!
-OrgRootDir=\$200E!
-OrgClusters=\$2010! Sector of Cluster 0
-SecPerClus=\$2012!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2014! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2014! CRC:ll word access
-SD_CMD_FRM1=\$2015! ll byte access
-SD_CMD_FRM2=\$2016! LL:hh word access
-SD_CMD_FRM3=\$2017! hh byte access
-SD_CMD_FRM4=\$2018! HH:CMD word access
-SD_CMD_FRM5=\$2019! CMD byte access
-SectorL=\$201A! 2 words
-SectorH=\$201C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$201E!
-BufferLen=\$2020!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2022! 16 bits wide (FAT16)
-ClusterH=\$2024! 16 bits wide (FAT16)
-LastFATsector=\$2026! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2028! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$202A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$202C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$202E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2030!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2032! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2034!
-EndOfPath=\$2036!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2038!
-HandleEnd=\$2118!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2118!
-SDIB_I2CCNT=\$211A!
-SDIB_ORG=\$251C!
-SDIB_LEN=\$54!
-
-SD_END=\$2170!
-SD_LEN=\$16E!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$4400! Code space start
-MAIN_LEN=\$BC00! 47 k FRAM
-! ----------------------------------------------
-
-SLEEP=\$4400! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$440A! CODE compiled by LITERAL
-XSQUOTE=\$441E! CODE compiled by S" and S_
-HEREXEC=\$4432! CODE HERE and BEGIN execute address
-MUSMOD=\$443E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$4450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$4458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$4482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$4484! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$4494! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$44A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$44AC! CODE compiled by IF UNTIL
-BRAN=\$44B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$44B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$44B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$44C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$44D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$4508! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$4512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$4554! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$457E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$4584! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$4586! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$4544! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$4546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$4550! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$4550! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$4552! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$457A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR5969
-! ----------------------------------------------
-MAIN_LEN=\$FC00! 63k FRAM
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFCC! FFCC-FFFF
-VECT_LEN=\$34!
-
-AES_VEC=\$FFCC!
-RTC_VEC=\$FFCE!
-P4_VEC=\$FFD0!
-P3_VEC=\$FFD2!
-TA3_X_VEC=\$FFD4!
-TA3_0_VEC=\$FFD6!
-P2_VEC=\$FFD8!
-TA2_X_VEC=\$FFDA!
-TA2_0_VEC=\$FFDC!
-P1_VEC=\$FFDE!
-TA1_X_VEC=\$FFE0!
-TA1_0_VEC=\$FFE2!
-DMA_VEC=\$FFE4!
-EUSCI_A1_VEC=\$FFE6!
-TA0_X_VEC=\$FFE8!
-TA0_0_VEC=\$FFEA!
-ADC12_B_VEC=\$FFEC!
-EUSCI_B0_VEC=\$FFEE!
-EUSCI_A0_VEC=\$FFF0!
-WDT_VEC=\$FFF2!
-TB0_X_VEC=\$FFF4!
-TB0_0_VEC=\$FFF6!
-COMP_D_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-FRCTLCTL0=\$140! \ FRAM control 0
-GCCTL0=\$144! \ General control 0
-GCCTL1=\$146! \ General control 1
-
-CRC16DI=\$150! \ CRC data input
-CRCDIRB=\$152! \ CRC data input reverse byte
-CRCINIRES=\$154! \ CRC initialization and result
-CRCRESR=\$156! \ CRC result reverse byte
-
-WDTCTL=\$15C! \ WDT control register
-
-CSCTL0=\$160! \ CS control 0
-CSCTL1=\$162! \ CS control 1
-CSCTL2=\$164! \ CS control 2
-CSCTL3=\$166! \ CS control 3
-CSCTL4=\$168! \ CS control 4
-CSCTL5=\$16A! \ CS control 5
-CSCTL6=\$16C! \ CS control 6
-
-SYSCTL=\$180! \ System control
-SYSJMBC=\$186! \ JTAG mailbox control
-SYSJMBI0=\$188! \ JTAG mailbox input 0
-SYSJMBI1=\$18A! \ JTAG mailbox input 1
-SYSJMBO0=\$18C! \ JTAG mailbox output 0
-SYSJMBO1=\$18E! \ JTAG mailbox output 1
-SYSUNIV=\$19A! \ User NMI vector generator
-SYSSNIV=\$19C! \ System NMI vector generator
-SYSRSTIV=\$19E! \ Reset vector generator
-
-REFCTL=\$1B0! \ Shared reference control
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PASELC=\$216!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1SELC=\$216!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2SELC=\$217!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-PBIN=\$220!
-PBOUT=\$222!
-PBDIR=\$224!
-PBREN=\$226!
-PBSEL0=\$22A!
-PBSEL1=\$22C!
-PBSELC=\$236!
-PBIES=\$238!
-PBIE=\$23A!
-PBIFG=\$23C!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-P3IV=\$22E!
-P3SELC=\$236!
-P3IES=\$238!
-P3IE=\$23A!
-P3IFG=\$23C!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-P4SEL1=\$22D!
-P4SELC=\$237!
-P4IES=\$239!
-P4IE=\$23B!
-P4IFG=\$23D!
-P4IV=\$23E!
-
-PJIN=\$320!
-PJOUT=\$322!
-PJDIR=\$324!
-PJREN=\$326!
-PJSEL0=\$32A!
-PJSEL1=\$32C!
-PJSELC=\$336!
-
-
-TACLR=4!
-TAIFG=1!
-TBCLR=2!
-TBIFG=1!
-CCIFG=1!
-
-TA0CTL=\$340! \ TA0 control
-TA0CCTL0=\$342! \ Capture/compare control 0
-TA0CCTL1=\$344! \ Capture/compare control 1
-TA0CCTL2=\$346! \ Capture/compare control 2
-TA0R=\$350! \ TA0 counter register
-TA0CCR0=\$352! \ Capture/compare register 0
-TA0CCR1=\$354! \ Capture/compare register 1
-TA0CCR2=\$356! \ Capture/compare register 2
-TA0EX0=\$360! \ TA0 expansion register 0
-TA0IV=\$36E! \ TA0 interrupt vector
-
-TA1CTL=\$380! \ TA1 control
-TA1CCTL0=\$382! \ Capture/compare control 0
-TA1CCTL1=\$384! \ Capture/compare control 1
-TA1CCTL2=\$386! \ Capture/compare control 2
-TA1R=\$390! \ TA1 counter register
-TA1CCR0=\$392! \ Capture/compare register 0
-TA1CCR1=\$394! \ Capture/compare register 1
-TA1CCR2=\$396! \ Capture/compare register 2
-TA1EX0=\$3A0! \ TA1 expansion register 0
-TA1IV=\$3AE! \ TA1 interrupt vector
-
-TB0CTL=\$3C0! \ TB0 control
-TB0CCTL0=\$3C2! \ Capture/compare control 0
-TB0CCTL1=\$3C4! \ Capture/compare control 1
-TB0CCTL2=\$3C6! \ Capture/compare control 2
-TB0CCTL3=\$3C8! \ Capture/compare control 3
-TB0CCTL4=\$3CA! \ Capture/compare control 4
-TB0CCTL5=\$3CC! \ Capture/compare control 5
-TB0CCTL6=\$3CE! \ Capture/compare control 6
-TB0R=\$3D0! \ TB0 counter register
-TB0CCR0=\$3D2! \ Capture/compare register 0
-TB0CCR1=\$3D4! \ Capture/compare register 1
-TB0CCR2=\$3D6! \ Capture/compare register 2
-TB0CCR3=\$3D8! \ Capture/compare register 3
-TB0CCR5=\$3DA! \ Capture/compare register 4
-TB0CCR5=\$3DC! \ Capture/compare register 5
-TB0CCR6=\$3DE! \ Capture/compare register 6
-TB0EX0=\$3E0! \ TB0 expansion register 0
-TB0IV=\$3EE! \ TB0 interrupt vector
-
-TA2CTL=\$400! \ TA2 control
-TA2CCTL0=\$402! \ Capture/compare control 0
-TA2CCTL1=\$404! \ Capture/compare control 1
-TA2R=\$410! \ TA2 counter register
-TA2CCR0=\$412! \ Capture/compare register 0
-TA2CCR1=\$414! \ Capture/compare register 1
-TA2EX0=\$420! \ TA2 expansion register 0
-TA2IV=\$42E! \ TA2 interrupt vector
-
-TA3CTL=\$440! \ TA3 control
-TA3CCTL0=\$442! \ Capture/compare control 0
-TA3CCTL1=\$444! \ Capture/compare control 1
-TA3R=\$450! \ TA3 counter register
-TA3CCR0=\$452! \ Capture/compare register 0
-TA3CCR1=\$454! \ Capture/compare register 1
-TA3EX0=\$460! \ TA3 expansion register 0
-TA3IV=\$46E! \ TA3 interrupt vector
-
-! \ RTC_B
-RTCCTL0=\$4A0! \ RTC control 0
-RTCCTL1=\$4A1! \ RTC control 1
-RTCCTL2=\$4A2! \ RTC control 2
-RTCCTL3=\$4A3! \ RTC control 3
-RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
-RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
-RTCPS0=\$4AC! \ RTC prescaler 0
-RTCPS1=\$4AD! \ RTC prescaler 1
-RTCIV=\$4AE! \ RTC interrupt vector word
-RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
-RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
-RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
-RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
-RTCDAY=\$4B4! \ RTC days
-RTCMON=\$4B5! \ RTC month
-RTCYEAR=\$4B6!
-RTCYEARL=\$4B6! \ RTC year low
-RTCYEARH=\$4B7! \ RTC year high
-RTCAMIN=\$4B8! \ RTC alarm minutes
-RTCAHOUR=\$4B9! \ RTC alarm hours
-RTCADOW=\$4BA! \ RTC alarm day of week
-RTCADAY=\$4BB! \ RTC alarm days
-BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
-BCD2BIN=\$4BE! \ BCD-to-binary conversion register
-RTCHOLD=\$40!
-RTCRDY=\$10!
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-DMAIFG=8!
-
-DMACTL0=\$500! \ DMA module control 0
-DMACTL1=\$502! \ DMA module control 1
-DMACTL2=\$504! \ DMA module control 2
-DMACTL3=\$506! \ DMA module control 3
-DMACTL4=\$508! \ DMA module control 4
-DMAIV=\$50A! \ DMA interrupt vector
-
-DMA0CTL=\$510! \ DMA channel 0 control
-DMA0SAL=\$512! \ DMA channel 0 source address low
-DMA0SAH=\$514! \ DMA channel 0 source address high
-DMA0DAL=\$516! \ DMA channel 0 destination address low
-DMA0DAH=\$518! \ DMA channel 0 destination address high
-DMA0SZ=\$51A! \ DMA channel 0 transfer size
-
-DMA1CTL=\$520! \ DMA channel 1 control
-DMA1SAL=\$522! \ DMA channel 1 source address low
-DMA1SAH=\$524! \ DMA channel 1 source address high
-DMA1DAL=\$526! \ DMA channel 1 destination address low
-DMA1DAH=\$528! \ DMA channel 1 destination address high
-DMA1SZ=\$52A! \ DMA channel 1 transfer size
-
-DMA2CTL=\$530! \ DMA channel 2 control
-DMA2SAL=\$532! \ DMA channel 2 source address low
-DMA2SAH=\$534! \ DMA channel 2 source address high
-DMA2DAL=\$536! \ DMA channel 2 destination address low
-DMA2DAH=\$538! \ DMA channel 2 destination address high
-DMA2SZ=\$53A! \ DMA channel 2 transfer size
-
-
-MPUCTL0=\$5A0! \ MPU control 0
-MPUCTL1=\$5A2! \ MPU control 1
-MPUSEGB2=\$5A4! \ MPU Segmentation Border2
-MPUSEGB1=\$5A6! \ MPU Segmentation Border1
-MPUSAM=\$5A8! \ MPU access management
-MPUIPC0=\$5AA! \ MPU IP control 0
-MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2
-MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1
-
-UCA0CTLW0=\$5C0! \ eUSCI_A control word 0
-UCA0CTLW1=\$5C2! \ eUSCI_A control word 1
-UCA0BRW=\$5C6!
-UCA0BR0=\$5C6! \ eUSCI_A baud rate 0
-UCA0BR1=\$5C7! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$5C8! \ eUSCI_A modulation control
-UCA0STAT=\$5CA! \ eUSCI_A status
-UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer
-UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$5D0! \ eUSCI_A LIN control
-UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-UCA0IE=\$5DA! \ eUSCI_A interrupt enable
-UCA0IFG=\$5DC! \ eUSCI_A interrupt flags
-UCA0IV=\$5DE! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$5E0! \ eUSCI_A control word 0
-UCA1CTLW1=\$5E2! \ eUSCI_A control word 1
-UCA1BRW=\$5E6!
-UCA1BR0=\$5E6! \ eUSCI_A baud rate 0
-UCA1BR1=\$5E7! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$5E8! \ eUSCI_A modulation control
-UCA1STAT=\$5EA! \ eUSCI_A status
-UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer
-UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$5F0! \ eUSCI_A LIN control
-UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control
-UCA1IE=\$5FA! \ eUSCI_A interrupt enable
-UCA1IFG=\$5FC! \ eUSCI_A interrupt flags
-UCA1IV=\$5FE! \ eUSCI_A interrupt vector word
-
-UCB0CTLW0=\$640! \ eUSCI_B control word 0
-UCB0CTLW1=\$642! \ eUSCI_B control word 1
-UCB0BRW=\$646!
-UCB0BR0=\$646! \ eUSCI_B bit rate 0
-UCB0BR1=\$647! \ eUSCI_B bit rate 1
-UCB0STATW=\$648! \ eUSCI_B status word
-UCBCNT0=\$649! \ eUSCI_B hardware count
-UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$64C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$65C! \ eUSCI_B received address
-UCB0ADDMASK=\$65E! \ eUSCI_B address mask
-UCB0I2CSA=\$660! \ eUSCI I2C slave address
-UCB0IE=\$66A! \ eUSCI interrupt enable
-UCB0IFG=\$66C! \ eUSCI interrupt flags
-UCB0IV=\$66E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-
-ADC12CTL0=\$800! \ ADC12_B Control 0
-ADC12CTL1=\$802! \ ADC12_B Control 1
-ADC12CTL2=\$804! \ ADC12_B Control 2
-ADC12CTL3=\$806! \ ADC12_B Control 3
-ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register
-ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register
-ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0
-ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1
-ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2
-ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0
-ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1
-ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2
-ADC12IV=\$818! \ ADC12_B Interrupt Vector
-ADC12MCTL0=\$820! \ ADC12_B Memory Control 0
-ADC12MCTL1=\$822! \ ADC12_B Memory Control 1
-ADC12MCTL2=\$824! \ ADC12_B Memory Control 2
-ADC12MCTL3=\$826! \ ADC12_B Memory Control 3
-ADC12MCTL4=\$828! \ ADC12_B Memory Control 4
-ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5
-ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6
-ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7
-ADC12MCTL8=\$830! \ ADC12_B Memory Control 8
-ADC12MCTL9=\$832! \ ADC12_B Memory Control 9
-ADC12MCTL10=\$834! \ ADC12_B Memory Control 10
-ADC12MCTL11=\$836! \ ADC12_B Memory Control 11
-ADC12MCTL12=\$838! \ ADC12_B Memory Control 12
-ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13
-ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14
-ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15
-ADC12MCTL16=\$840! \ ADC12_B Memory Control 16
-ADC12MCTL17=\$842! \ ADC12_B Memory Control 17
-ADC12MCTL18=\$844! \ ADC12_B Memory Control 18
-ADC12MCTL19=\$846! \ ADC12_B Memory Control 19
-ADC12MCTL20=\$848! \ ADC12_B Memory Control 20
-ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21
-ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22
-ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23
-ADC12MCTL24=\$850! \ ADC12_B Memory Control 24
-ADC12MCTL25=\$852! \ ADC12_B Memory Control 25
-ADC12MCTL26=\$854! \ ADC12_B Memory Control 26
-ADC12MCTL27=\$856! \ ADC12_B Memory Control 27
-ADC12MCTL28=\$858! \ ADC12_B Memory Control 28
-ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29
-ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30
-ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31
-ADC12MEM0=\$860! \ ADC12_B Memory 0
-ADC12MEM1=\$862! \ ADC12_B Memory 1
-ADC12MEM2=\$864! \ ADC12_B Memory 2
-ADC12MEM3=\$866! \ ADC12_B Memory 3
-ADC12MEM4=\$868! \ ADC12_B Memory 4
-ADC12MEM5=\$86A! \ ADC12_B Memory 5
-ADC12MEM6=\$86C! \ ADC12_B Memory 6
-ADC12MEM7=\$86E! \ ADC12_B Memory 7
-ADC12MEM8=\$870! \ ADC12_B Memory 8
-ADC12MEM9=\$872! \ ADC12_B Memory 9
-ADC12MEM10=\$874! \ ADC12_B Memory 10
-ADC12MEM11=\$876! \ ADC12_B Memory 11
-ADC12MEM12=\$878! \ ADC12_B Memory 12
-ADC12MEM13=\$87A! \ ADC12_B Memory 13
-ADC12MEM14=\$87C! \ ADC12_B Memory 14
-ADC12MEM15=\$87E! \ ADC12_B Memory 15
-ADC12MEM16=\$880! \ ADC12_B Memory 16
-ADC12MEM17=\$882! \ ADC12_B Memory 17
-ADC12MEM18=\$884! \ ADC12_B Memory 18
-ADC12MEM19=\$886! \ ADC12_B Memory 19
-ADC12MEM20=\$888! \ ADC12_B Memory 20
-ADC12MEM21=\$88A! \ ADC12_B Memory 21
-ADC12MEM22=\$88C! \ ADC12_B Memory 22
-ADC12MEM23=\$88E! \ ADC12_B Memory 23
-ADC12MEM24=\$890! \ ADC12_B Memory 24
-ADC12MEM25=\$892! \ ADC12_B Memory 25
-ADC12MEM26=\$894! \ ADC12_B Memory 26
-ADC12MEM27=\$896! \ ADC12_B Memory 27
-ADC12MEM28=\$898! \ ADC12_B Memory 28
-ADC12MEM29=\$89A! \ ADC12_B Memory 29
-ADC12MEM30=\$89C! \ ADC12_B Memory 30
-ADC12MEM31=\$89E! \ ADC12_B Memory 31
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-CDIFG=1!
-CDIIFG=2!
-
-CDCTL0=\$8C0! \ Comparator_E control register 0
-CDCTL1=\$8C2! \ Comparator_E control register 1
-CDCTL2=\$8C4! \ Comparator_E control register 2
-CDCTL3=\$8C6! \ Comparator_E control register 3
-CDINT=\$8CC! \ Comparator_E interrupt register
-CDIV=\$8CE! \ Comparator_E interrupt vector word
-
-
-AESACTL0=\$9C0! \ AES accelerator control register 0
-AESASTAT=\$9C4! \ AES accelerator status register
-AESAKEY=\$9C6! \ AES accelerator key register
-AESADIN=\$9C8! \ AES accelerator data in register
-AESADOUT=\$9CA! \ AES accelerator data out register
-AESAXDIN=\$9CC! \ AES accelerator XORed data in register
-AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger)
+
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430fr5969.pat
+
+; ----------------------------------------------
+; MSP430FR5969 MEMORY MAP
+; ----------------------------------------------
+; 0000-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
+; 1800-19FF = FRAM INFO 512 B
+; 1A00-1AFF = TLV device descriptor info (FRAM 256 B)
+; 1C00-23FF = RAM (2 KB)
+; 4400-FF7F = MAIN (FRAM 47 kB)
+; FF80-FFFF = interrupt vectors (FRAM 127 B)
+; ----------------------------------------------
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0200;
+
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$1C00;
+RAM_LEN=\$0800;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ---------------------------------------
+; FastForth RAM memory map (>= 1k)
+; ---------------------------------------
+LEAVEPTR=\$1C00; Leave-stack pointer, init by QUIT
+LSATCK=\$1C00; leave stack, grow up
+PSTACK=\$1C80; parameter stack, grow down
+RSTACK=\$1CE0; Return stack, grow down
+;
+PAD_I2CADR=\$1CE0; RX I2C address
+PAD_I2CCNT=\$1CE2; count max
+PAD_ORG=\$1CE4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$1D38; TX I2C address
+TIB_I2CCNT=\$1D3A; count of bytes
+TIB_ORG=\$1D3C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$1D90; base address for HOLDS
+HOLD_BASE=\$1DB2; BASE HOLD area, grow down
+;
+HP=\$1DB2; HOLD ptr
+STATEADR=\$1DB4; Interpreter state
+BASEADR=\$1DB6; base
+CAPS=\$1DB8; CAPS ON/OFF
+SOURCE_LEN=\$1DBA; len of input stream
+SOURCE_ORG=\$1DBC; adr of input stream
+TOIN=\$1DBE; >IN
+;
+DP=\$1DC0; dictionary ptr
+LASTVOC=\$1DC2; keep VOC-LINK
+CURRENT=\$1DC4; CURRENT dictionnary ptr
+CONTEXT=\$1DC6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$1DD8;
+LAST_THREAD=\$1DDA;
+LAST_CFA=\$1DDC;
+LAST_PSP=\$1DDE;
+ASMBW1=\$1DE0; 3 backward labels
+ASMBW2=\$1DE2;
+ASMBW3=\$1DE4;
+ASMFW1=\$1DE6; 3 forward labels
+ASMFW2=\$1DE8;
+ASMFW3=\$1DEA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$1DFC;
+SD_BUF_I2CNT=\$1DFE;
+SD_BUF=\$1E00; \ SD_Card buffer
+BUFEND=\$2000;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2002;
+BS_FirstSectorL=\$2004;
+BS_FirstSectorH=\$2006;
+OrgFAT1=\$2008;
+FATSize=\$200A;
+OrgFAT2=\$200C;
+OrgRootDir=\$200E;
+OrgClusters=\$2010; Sector of Cluster 0
+SecPerClus=\$2012;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2014; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2014; CRC:ll word access
+SD_CMD_FRM1=\$2015; ll byte access
+SD_CMD_FRM2=\$2016; LL:hh word access
+SD_CMD_FRM3=\$2017; hh byte access
+SD_CMD_FRM4=\$2018; HH:CMD word access
+SD_CMD_FRM5=\$2019; CMD byte access
+SectorL=\$201A; 2 words
+SectorH=\$201C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$201E;
+BufferLen=\$2020;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2022; 16 bits wide (FAT16)
+ClusterH=\$2024; 16 bits wide (FAT16)
+LastFATsector=\$2026; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2028; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$202A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$202C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$202E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2030;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2032; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2034;
+EndOfPath=\$2036;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2038;
+HandleEnd=\$2118;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2118;
+SDIB_I2CCNT=\$211A;
+SDIB_ORG=\$251C;
+SDIB_LEN=\$54;
+
+SD_END=\$2170;
+SD_LEN=\$16E;
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$4400; Code space start
+MAIN_LEN=\$BC00; 47 k FRAM
+; ----------------------------------------------
+\#LIT=\#\$4400; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$4414; asm CODE run time of QUOTE
+\#MUSMOD=\#\$4428; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$443A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$4442; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$446C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$446E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$447E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$448A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$4496; CODE compiled by IF UNTIL
+\#BRAN=\#\$449C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$449E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$44A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$44AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$44BA;
+\#ABORT_TERM=\#\$4500; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$4572; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$455C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR5969
+; ----------------------------------------------
+MAIN_LEN=\$FC00; 63k FRAM
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFCC; FFCC-FFFF
+VECT_LEN=\$34;
+
+AES_VEC=\$FFCC;
+RTC_VEC=\$FFCE;
+P4_VEC=\$FFD0;
+P3_VEC=\$FFD2;
+TA3_X_VEC=\$FFD4;
+TA3_0_VEC=\$FFD6;
+P2_VEC=\$FFD8;
+TA2_X_VEC=\$FFDA;
+TA2_0_VEC=\$FFDC;
+P1_VEC=\$FFDE;
+TA1_X_VEC=\$FFE0;
+TA1_0_VEC=\$FFE2;
+DMA_VEC=\$FFE4;
+EUSCI_A1_VEC=\$FFE6;
+TA0_X_VEC=\$FFE8;
+TA0_0_VEC=\$FFEA;
+ADC12_B_VEC=\$FFEC;
+EUSCI_B0_VEC=\$FFEE;
+EUSCI_A0_VEC=\$FFF0;
+WDT_VEC=\$FFF2;
+TB0_X_VEC=\$FFF4;
+TB0_0_VEC=\$FFF6;
+COMP_D_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+FRCTLCTL0=\$140; \ FRAM control 0
+GCCTL0=\$144; \ General control 0
+GCCTL1=\$146; \ General control 1
+
+CRC16DI=\$150; \ CRC data input
+CRCDIRB=\$152; \ CRC data input reverse byte
+CRCINIRES=\$154; \ CRC initialization and result
+CRCRESR=\$156; \ CRC result reverse byte
+
+WDTCTL=\$15C; \ WDT control register
+
+CSCTL0=\$160; \ CS control 0
+CSCTL1=\$162; \ CS control 1
+CSCTL2=\$164; \ CS control 2
+CSCTL3=\$166; \ CS control 3
+CSCTL4=\$168; \ CS control 4
+CSCTL5=\$16A; \ CS control 5
+CSCTL6=\$16C; \ CS control 6
+
+SYSCTL=\$180; \ System control
+SYSJMBC=\$186; \ JTAG mailbox control
+SYSJMBI0=\$188; \ JTAG mailbox input 0
+SYSJMBI1=\$18A; \ JTAG mailbox input 1
+SYSJMBO0=\$18C; \ JTAG mailbox output 0
+SYSJMBO1=\$18E; \ JTAG mailbox output 1
+SYSUNIV=\$19A; \ User NMI vector generator
+SYSSNIV=\$19C; \ System NMI vector generator
+SYSRSTIV=\$19E; \ Reset vector generator
+
+REFCTL=\$1B0; \ Shared reference control
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PASELC=\$216;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1SELC=\$216;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2SELC=\$217;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+PBIN=\$220;
+PBOUT=\$222;
+PBDIR=\$224;
+PBREN=\$226;
+PBSEL0=\$22A;
+PBSEL1=\$22C;
+PBSELC=\$236;
+PBIES=\$238;
+PBIE=\$23A;
+PBIFG=\$23C;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+P3IV=\$22E;
+P3SELC=\$236;
+P3IES=\$238;
+P3IE=\$23A;
+P3IFG=\$23C;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+P4SEL1=\$22D;
+P4SELC=\$237;
+P4IES=\$239;
+P4IE=\$23B;
+P4IFG=\$23D;
+P4IV=\$23E;
+
+PJIN=\$320;
+PJOUT=\$322;
+PJDIR=\$324;
+PJREN=\$326;
+PJSEL0=\$32A;
+PJSEL1=\$32C;
+PJSELC=\$336;
+
+
+TACLR=4;
+TAIFG=1;
+TBCLR=2;
+TBIFG=1;
+CCIFG=1;
+
+TA0CTL=\$340; \ TA0 control
+TA0CCTL0=\$342; \ Capture/compare control 0
+TA0CCTL1=\$344; \ Capture/compare control 1
+TA0CCTL2=\$346; \ Capture/compare control 2
+TA0R=\$350; \ TA0 counter register
+TA0CCR0=\$352; \ Capture/compare register 0
+TA0CCR1=\$354; \ Capture/compare register 1
+TA0CCR2=\$356; \ Capture/compare register 2
+TA0EX0=\$360; \ TA0 expansion register 0
+TA0IV=\$36E; \ TA0 interrupt vector
+
+TA1CTL=\$380; \ TA1 control
+TA1CCTL0=\$382; \ Capture/compare control 0
+TA1CCTL1=\$384; \ Capture/compare control 1
+TA1CCTL2=\$386; \ Capture/compare control 2
+TA1R=\$390; \ TA1 counter register
+TA1CCR0=\$392; \ Capture/compare register 0
+TA1CCR1=\$394; \ Capture/compare register 1
+TA1CCR2=\$396; \ Capture/compare register 2
+TA1EX0=\$3A0; \ TA1 expansion register 0
+TA1IV=\$3AE; \ TA1 interrupt vector
+
+TB0CTL=\$3C0; \ TB0 control
+TB0CCTL0=\$3C2; \ Capture/compare control 0
+TB0CCTL1=\$3C4; \ Capture/compare control 1
+TB0CCTL2=\$3C6; \ Capture/compare control 2
+TB0CCTL3=\$3C8; \ Capture/compare control 3
+TB0CCTL4=\$3CA; \ Capture/compare control 4
+TB0CCTL5=\$3CC; \ Capture/compare control 5
+TB0CCTL6=\$3CE; \ Capture/compare control 6
+TB0R=\$3D0; \ TB0 counter register
+TB0CCR0=\$3D2; \ Capture/compare register 0
+TB0CCR1=\$3D4; \ Capture/compare register 1
+TB0CCR2=\$3D6; \ Capture/compare register 2
+TB0CCR3=\$3D8; \ Capture/compare register 3
+TB0CCR5=\$3DA; \ Capture/compare register 4
+TB0CCR5=\$3DC; \ Capture/compare register 5
+TB0CCR6=\$3DE; \ Capture/compare register 6
+TB0EX0=\$3E0; \ TB0 expansion register 0
+TB0IV=\$3EE; \ TB0 interrupt vector
+
+TA2CTL=\$400; \ TA2 control
+TA2CCTL0=\$402; \ Capture/compare control 0
+TA2CCTL1=\$404; \ Capture/compare control 1
+TA2R=\$410; \ TA2 counter register
+TA2CCR0=\$412; \ Capture/compare register 0
+TA2CCR1=\$414; \ Capture/compare register 1
+TA2EX0=\$420; \ TA2 expansion register 0
+TA2IV=\$42E; \ TA2 interrupt vector
+
+TA3CTL=\$440; \ TA3 control
+TA3CCTL0=\$442; \ Capture/compare control 0
+TA3CCTL1=\$444; \ Capture/compare control 1
+TA3R=\$450; \ TA3 counter register
+TA3CCR0=\$452; \ Capture/compare register 0
+TA3CCR1=\$454; \ Capture/compare register 1
+TA3EX0=\$460; \ TA3 expansion register 0
+TA3IV=\$46E; \ TA3 interrupt vector
+
+; \ RTC_B
+RTCCTL0=\$4A0; \ RTC control 0
+RTCCTL1=\$4A1; \ RTC control 1
+RTCCTL2=\$4A2; \ RTC control 2
+RTCCTL3=\$4A3; \ RTC control 3
+RTCPS0CTL=\$4A8; \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA; \ RTC prescaler 1 control
+RTCPS0=\$4AC; \ RTC prescaler 0
+RTCPS1=\$4AD; \ RTC prescaler 1
+RTCIV=\$4AE; \ RTC interrupt vector word
+RTCSEC=\$4B0; \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCMIN=\$4B1; \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCHOUR=\$4B2; \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCDOW=\$4B3; \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCDAY=\$4B4; \ RTC days
+RTCMON=\$4B5; \ RTC month
+RTCYEAR=\$4B6;
+RTCYEARL=\$4B6; \ RTC year low
+RTCYEARH=\$4B7; \ RTC year high
+RTCAMIN=\$4B8; \ RTC alarm minutes
+RTCAHOUR=\$4B9; \ RTC alarm hours
+RTCADOW=\$4BA; \ RTC alarm day of week
+RTCADAY=\$4BB; \ RTC alarm days
+BIN2BCD=\$4BC; \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE; \ BCD-to-binary conversion register
+RTCHOLD=\$40;
+RTCRDY=\$10;
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+DMAIFG=8;
+
+DMACTL0=\$500; \ DMA module control 0
+DMACTL1=\$502; \ DMA module control 1
+DMACTL2=\$504; \ DMA module control 2
+DMACTL3=\$506; \ DMA module control 3
+DMACTL4=\$508; \ DMA module control 4
+DMAIV=\$50A; \ DMA interrupt vector
+
+DMA0CTL=\$510; \ DMA channel 0 control
+DMA0SAL=\$512; \ DMA channel 0 source address low
+DMA0SAH=\$514; \ DMA channel 0 source address high
+DMA0DAL=\$516; \ DMA channel 0 destination address low
+DMA0DAH=\$518; \ DMA channel 0 destination address high
+DMA0SZ=\$51A; \ DMA channel 0 transfer size
+
+DMA1CTL=\$520; \ DMA channel 1 control
+DMA1SAL=\$522; \ DMA channel 1 source address low
+DMA1SAH=\$524; \ DMA channel 1 source address high
+DMA1DAL=\$526; \ DMA channel 1 destination address low
+DMA1DAH=\$528; \ DMA channel 1 destination address high
+DMA1SZ=\$52A; \ DMA channel 1 transfer size
+
+DMA2CTL=\$530; \ DMA channel 2 control
+DMA2SAL=\$532; \ DMA channel 2 source address low
+DMA2SAH=\$534; \ DMA channel 2 source address high
+DMA2DAL=\$536; \ DMA channel 2 destination address low
+DMA2DAH=\$538; \ DMA channel 2 destination address high
+DMA2SZ=\$53A; \ DMA channel 2 transfer size
+
+
+MPUCTL0=\$5A0; \ MPU control 0
+MPUCTL1=\$5A2; \ MPU control 1
+MPUSEGB2=\$5A4; \ MPU Segmentation Border2
+MPUSEGB1=\$5A6; \ MPU Segmentation Border1
+MPUSAM=\$5A8; \ MPU access management
+MPUIPC0=\$5AA; \ MPU IP control 0
+MPUIPSEGB2=\$5AC; \ MPU IP Encapsulation Segment Border 2
+MPUIPSEGB1=\$5AE; \ MPU IP Encapsulation Segment Border 1
+
+UCA0CTLW0=\$5C0; \ eUSCI_A control word 0
+UCA0CTLW1=\$5C2; \ eUSCI_A control word 1
+UCA0BRW=\$5C6;
+UCA0BR0=\$5C6; \ eUSCI_A baud rate 0
+UCA0BR1=\$5C7; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$5C8; \ eUSCI_A modulation control
+UCA0STAT=\$5CA; \ eUSCI_A status
+UCA0RXBUF=\$5CC; \ eUSCI_A receive buffer
+UCA0TXBUF=\$5CE; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$5D0; \ eUSCI_A LIN control
+UCA0IRTCTL=\$5D2; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$5D3; \ eUSCI_A IrDA receive control
+UCA0IE=\$5DA; \ eUSCI_A interrupt enable
+UCA0IFG=\$5DC; \ eUSCI_A interrupt flags
+UCA0IV=\$5DE; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$5E0; \ eUSCI_A control word 0
+UCA1CTLW1=\$5E2; \ eUSCI_A control word 1
+UCA1BRW=\$5E6;
+UCA1BR0=\$5E6; \ eUSCI_A baud rate 0
+UCA1BR1=\$5E7; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$5E8; \ eUSCI_A modulation control
+UCA1STAT=\$5EA; \ eUSCI_A status
+UCA1RXBUF=\$5EC; \ eUSCI_A receive buffer
+UCA1TXBUF=\$5EE; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$5F0; \ eUSCI_A LIN control
+UCA1IRTCTL=\$5F2; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$5F3; \ eUSCI_A IrDA receive control
+UCA1IE=\$5FA; \ eUSCI_A interrupt enable
+UCA1IFG=\$5FC; \ eUSCI_A interrupt flags
+UCA1IV=\$5FE; \ eUSCI_A interrupt vector word
+
+UCB0CTLW0=\$640; \ eUSCI_B control word 0
+UCB0CTLW1=\$642; \ eUSCI_B control word 1
+UCB0BRW=\$646;
+UCB0BR0=\$646; \ eUSCI_B bit rate 0
+UCB0BR1=\$647; \ eUSCI_B bit rate 1
+UCB0STATW=\$648; \ eUSCI_B status word
+UCBCNT0=\$649; \ eUSCI_B hardware count
+UCB0TBCNT=\$64A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$64C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$64E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$654; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$656; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$658; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$65A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$65C; \ eUSCI_B received address
+UCB0ADDMASK=\$65E; \ eUSCI_B address mask
+UCB0I2CSA=\$660; \ eUSCI I2C slave address
+UCB0IE=\$66A; \ eUSCI interrupt enable
+UCB0IFG=\$66C; \ eUSCI interrupt flags
+UCB0IV=\$66E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+
+ADC12CTL0=\$800; \ ADC12_B Control 0
+ADC12CTL1=\$802; \ ADC12_B Control 1
+ADC12CTL2=\$804; \ ADC12_B Control 2
+ADC12CTL3=\$806; \ ADC12_B Control 3
+ADC12LO=\$808; \ ADC12_B Window Comparator Low Threshold Register
+ADC12HI=\$80A; \ ADC12_B Window Comparator High Threshold Register
+ADC12IFGR0=\$80C; \ ADC12_B Interrupt Flag Register 0
+ADC12IFGR1=\$80E; \ ADC12_B Interrupt Flag Register 1
+ADC12IFGR2=\$810; \ ADC12_B Interrupt Flag Register 2
+ADC12IER0=\$812; \ ADC12_B Interrupt Enable Register 0
+ADC12IER1=\$814; \ ADC12_B Interrupt Enable Register 1
+ADC12IER2=\$816; \ ADC12_B Interrupt Enable Register 2
+ADC12IV=\$818; \ ADC12_B Interrupt Vector
+ADC12MCTL0=\$820; \ ADC12_B Memory Control 0
+ADC12MCTL1=\$822; \ ADC12_B Memory Control 1
+ADC12MCTL2=\$824; \ ADC12_B Memory Control 2
+ADC12MCTL3=\$826; \ ADC12_B Memory Control 3
+ADC12MCTL4=\$828; \ ADC12_B Memory Control 4
+ADC12MCTL5=\$82A; \ ADC12_B Memory Control 5
+ADC12MCTL6=\$82C; \ ADC12_B Memory Control 6
+ADC12MCTL7=\$82E; \ ADC12_B Memory Control 7
+ADC12MCTL8=\$830; \ ADC12_B Memory Control 8
+ADC12MCTL9=\$832; \ ADC12_B Memory Control 9
+ADC12MCTL10=\$834; \ ADC12_B Memory Control 10
+ADC12MCTL11=\$836; \ ADC12_B Memory Control 11
+ADC12MCTL12=\$838; \ ADC12_B Memory Control 12
+ADC12MCTL13=\$83A; \ ADC12_B Memory Control 13
+ADC12MCTL14=\$83C; \ ADC12_B Memory Control 14
+ADC12MCTL15=\$83E; \ ADC12_B Memory Control 15
+ADC12MCTL16=\$840; \ ADC12_B Memory Control 16
+ADC12MCTL17=\$842; \ ADC12_B Memory Control 17
+ADC12MCTL18=\$844; \ ADC12_B Memory Control 18
+ADC12MCTL19=\$846; \ ADC12_B Memory Control 19
+ADC12MCTL20=\$848; \ ADC12_B Memory Control 20
+ADC12MCTL21=\$84A; \ ADC12_B Memory Control 21
+ADC12MCTL22=\$84C; \ ADC12_B Memory Control 22
+ADC12MCTL23=\$84E; \ ADC12_B Memory Control 23
+ADC12MCTL24=\$850; \ ADC12_B Memory Control 24
+ADC12MCTL25=\$852; \ ADC12_B Memory Control 25
+ADC12MCTL26=\$854; \ ADC12_B Memory Control 26
+ADC12MCTL27=\$856; \ ADC12_B Memory Control 27
+ADC12MCTL28=\$858; \ ADC12_B Memory Control 28
+ADC12MCTL29=\$85A; \ ADC12_B Memory Control 29
+ADC12MCTL30=\$85C; \ ADC12_B Memory Control 30
+ADC12MCTL31=\$85E; \ ADC12_B Memory Control 31
+ADC12MEM0=\$860; \ ADC12_B Memory 0
+ADC12MEM1=\$862; \ ADC12_B Memory 1
+ADC12MEM2=\$864; \ ADC12_B Memory 2
+ADC12MEM3=\$866; \ ADC12_B Memory 3
+ADC12MEM4=\$868; \ ADC12_B Memory 4
+ADC12MEM5=\$86A; \ ADC12_B Memory 5
+ADC12MEM6=\$86C; \ ADC12_B Memory 6
+ADC12MEM7=\$86E; \ ADC12_B Memory 7
+ADC12MEM8=\$870; \ ADC12_B Memory 8
+ADC12MEM9=\$872; \ ADC12_B Memory 9
+ADC12MEM10=\$874; \ ADC12_B Memory 10
+ADC12MEM11=\$876; \ ADC12_B Memory 11
+ADC12MEM12=\$878; \ ADC12_B Memory 12
+ADC12MEM13=\$87A; \ ADC12_B Memory 13
+ADC12MEM14=\$87C; \ ADC12_B Memory 14
+ADC12MEM15=\$87E; \ ADC12_B Memory 15
+ADC12MEM16=\$880; \ ADC12_B Memory 16
+ADC12MEM17=\$882; \ ADC12_B Memory 17
+ADC12MEM18=\$884; \ ADC12_B Memory 18
+ADC12MEM19=\$886; \ ADC12_B Memory 19
+ADC12MEM20=\$888; \ ADC12_B Memory 20
+ADC12MEM21=\$88A; \ ADC12_B Memory 21
+ADC12MEM22=\$88C; \ ADC12_B Memory 22
+ADC12MEM23=\$88E; \ ADC12_B Memory 23
+ADC12MEM24=\$890; \ ADC12_B Memory 24
+ADC12MEM25=\$892; \ ADC12_B Memory 25
+ADC12MEM26=\$894; \ ADC12_B Memory 26
+ADC12MEM27=\$896; \ ADC12_B Memory 27
+ADC12MEM28=\$898; \ ADC12_B Memory 28
+ADC12MEM29=\$89A; \ ADC12_B Memory 29
+ADC12MEM30=\$89C; \ ADC12_B Memory 30
+ADC12MEM31=\$89E; \ ADC12_B Memory 31
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CDIFG=1;
+CDIIFG=2;
+
+CDCTL0=\$8C0; \ Comparator_E control register 0
+CDCTL1=\$8C2; \ Comparator_E control register 1
+CDCTL2=\$8C4; \ Comparator_E control register 2
+CDCTL3=\$8C6; \ Comparator_E control register 3
+CDINT=\$8CC; \ Comparator_E interrupt register
+CDIV=\$8CE; \ Comparator_E interrupt vector word
+
+
+AESACTL0=\$9C0; \ AES accelerator control register 0
+AESASTAT=\$9C4; \ AES accelerator status register
+AESAKEY=\$9C6; \ AES accelerator key register
+AESADIN=\$9C8; \ AES accelerator data in register
+AESADOUT=\$9CA; \ AES accelerator data out register
+AESAXDIN=\$9CC; \ AES accelerator XORed data in register
+AESAXIN =\$9CE; \ AES accelerator XORed data in register (no trigger)
.listing off
DEVICE = "MSP430FR5972"
-
+HMPY ; hardware multiplier
; ----------------------------------------------
; MSP430FR5972 MEMORY MAP
-!MSP430FR5972.pat, duplicated from MSP430fr6989.pat
-
-! ----------------------------------------------
-! MSP430FR5972 MEMORY MAP
-! ----------------------------------------------
-! 0000-0005 = reserved ROM
-! 0006-001F = tiny RAM 26 bytes
-! 0020-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
-! 1800-19FF = FRAM INFO 512 B
-! 1A00-1AFF = TLV device descriptor info (FRAM 256 B)
-! 1B00-1BFF = ROM boot memory
-! 1C00-23FF = RAM (2 KB)
-! 4400-FF7F = code memory (FRAM 48 kB)
-! FF80-FFFF = interrupt vectors (FRAM 127 B)
-! ----------------------------------------------
-
-
-! ============================================
-! TINY RAM
-! ============================================
-TinyRAM_ORG=\$06!
-TinyRAM_LEN=\$20!
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! ; Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0100! ;
-DEVICEID=\$1A04!
-
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$1C00!
-RAM_LEN=\$0800!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ----------------------------------------------
-! FastForth RAM memory map (>= 1k):
-! ----------------------------------------------
-LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT
-LSATCK=\$1C00! leave stack, grow up
-PSTACK=\$1C80! parameter stack, grow down
-RSTACK=\$1CE0! Return stack, grow down
-!
-PAD_I2CADR=\$1CE0! RX I2C address
-PAD_I2CCNT=\$1CE2! count max
-PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$1D38! TX I2C address
-TIB_I2CCNT=\$1D3A! count of bytes
-TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$1D90! base address for HOLDS
-HOLD_BASE=\$1DB2! BASE HOLD area, grow down
-!
-HP=\$1DB2! HOLD ptr
-LAST_NFA=\$1DB4!
-LAST_THREAD=\$1DB6!
-LAST_CFA=\$1DB8!
-LAST_PSP=\$1DBA!
-!
-STATEADR=\$1DBC! Interpreter state
-BASEADR=\$1DBE! base
-CAPS=\$1DC0! CAPS ON/OFF
-!
-SOURCE_LEN=\$1DC2! len of input stream
-SOURCE_ORG=\$1DC4! adr of input stream
-TOIN=\$1DC6! >IN
-DP=\$1DC8! dictionary ptr
-!
-LASTVOC=\$1DCA! keep VOC-LINK
-CURRENT=\$1DCC! CURRENT dictionnary ptr
-CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!1DE0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$1DFC!
-SD_BUF_I2CNT=\$1DFE!
-SD_BUF=\$1E00! \ SD_Card buffer
-BUFEND=\$2000!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2002!
-BS_FirstSectorL=\$2004!
-BS_FirstSectorH=\$2006!
-OrgFAT1=\$2008!
-FATSize=\$200A!
-OrgFAT2=\$200C!
-OrgRootDir=\$200E!
-OrgClusters=\$2010! Sector of Cluster 0
-SecPerClus=\$2012!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2014! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2014! CRC:ll word access
-SD_CMD_FRM1=\$2015! ll byte access
-SD_CMD_FRM2=\$2016! LL:hh word access
-SD_CMD_FRM3=\$2017! hh byte access
-SD_CMD_FRM4=\$2018! HH:CMD word access
-SD_CMD_FRM5=\$2019! CMD byte access
-SectorL=\$201A! 2 words
-SectorH=\$201C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$201E!
-BufferLen=\$2020!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2022! 16 bits wide (FAT16)
-ClusterH=\$2024! 16 bits wide (FAT16)
-LastFATsector=\$2026! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2028! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$202A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$202C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$202E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2030!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2032! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2034!
-EndOfPath=\$2036!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2038!
-HandleEnd=\$2118!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2118!
-SDIB_I2CCNT=\$211A!
-SDIB_ORG=\$211C!
-SDIB_LEN=\$54!
-
-SD_END=\$2170!
-SD_LEN=\$16E!
-
-! ----------------------------------------------
-! FRAM
-! ----------------------------------------------
-MAIN_ORG=\$4400! Code space start
-MAIN_LEN=\$24000! 127 k FRAM
-! ----------------------------------------------
-
-SLEEP=\$4400! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$440A! CODE compiled by LITERAL
-XSQUOTE=\$441E! CODE compiled by S" and S_
-HEREXEC=\$4432! CODE HERE and BEGIN execute address
-MUSMOD=\$443E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$4450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$4458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$4482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$4484! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$4494! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$44A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$44AC! CODE compiled by IF UNTIL
-BRAN=\$44B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$44B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$44B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$44C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$44D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$4508! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$4512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$4554! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$457E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$4584! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$4586! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$4544! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$4546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$4550! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$4550! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$4552! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$457A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR6989
-! ----------------------------------------------
-MAIN_LEN=\$1FC00! 127 k FRAM
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFC6! FFC6-FFFF
-VECT_LEN=\$3A!
-
-
-AES_VEC=\$FFC6!
-RTC_VEC=\$FFC8!
-P4_VEC=\$FFCC!
-P3_VEC=\$FFCE!
-TA3_X_VEC=\$FFD0!
-TA3_0_VEC=\$FFD2!
-P2_VEC=\$FFD4!
-TA2_X_VEC=\$FFD6!
-TA2_0_VEC=\$FFD8!
-P1_VEC=\$FFDA!
-TA1_X_VEC=\$FFDC!
-TA1_0_VEC=\$FFDE!
-DMA_VEC=\$FFE0!
-EUSCI_B1_VEC=\$FFE2!
-EUSCI_A1_VEC=\$FFE4!
-TA0_X_VEC=\$FFE6!
-TA0_0_VEC=\$FFE8!
-ADC12_B_VEC=\$FFEA!
-EUSCI_B0_VEC=\$FFEC!
-EUSCI_A0_VEC=\$FFEE!
-WDT_VEC=\$FFF2!
-TB0_X_VEC=\$FFF4!
-TB0_0_VEC=\$FFF6!
-COMP_E_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-FRCTLCTL0=\$140! \ FRAM control 0
-GCCTL0=\$144! \ General control 0
-GCCTL1=\$146! \ General control 1
-
-CRC16DI=\$150! \ CRC data input
-CRCDIRB=\$152! \ CRC data input reverse byte
-CRCINIRES=\$154! \ CRC initialization and result
-CRCRESR=\$156! \ CRC result reverse byte
-
-RCCTL0=\$158! \ RAM controller control 0
-
-WDTCTL=\$15C! \ WDT control register
-
-CSCTL0=\$160! \ CS control 0
-CSCTL1=\$162! \ CS control 1
-CSCTL2=\$164! \ CS control 2
-CSCTL3=\$166! \ CS control 3
-CSCTL4=\$168! \ CS control 4
-CSCTL5=\$16A! \ CS control 5
-CSCTL6=\$16C! \ CS control 6
-
-SYSCTL=\$180! \ System control
-SYSJMBC=\$186! \ JTAG mailbox control
-SYSJMBI0=\$188! \ JTAG mailbox input 0
-SYSJMBI1=\$18A! \ JTAG mailbox input 1
-SYSJMBO0=\$18C! \ JTAG mailbox output 0
-SYSJMBO1=\$18E! \ JTAG mailbox output 1
-SYSUNIV=\$19A! \ User NMI vector generator
-SYSSNIV=\$19C! \ System NMI vector generator
-SYSRSTIV=\$19E! \ Reset vector generator
-
-REFCTL=\$1B0! \ Shared reference control
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PASELC=\$216!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1SELC=\$216!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2SELC=\$217!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-PBIN=\$220!
-PBOUT=\$222!
-PBDIR=\$224!
-PBREN=\$226!
-PBSEL0=\$22A!
-PBSEL1=\$22C!
-PBSELC=\$236!
-PBIES=\$238!
-PBIE=\$23A!
-PBIFG=\$23C!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-P3IV=\$22E!
-P3SELC=\$236!
-P3IES=\$238!
-P3IE=\$23A!
-P3IFG=\$23C!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-P4SEL1=\$22D!
-P4SELC=\$237!
-P4IES=\$239!
-P4IE=\$23B!
-P4IFG=\$23D!
-P4IV=\$23E!
-
-PCIN=\$240!
-PCOUT=\$242!
-PCDIR=\$244!
-PCREN=\$246!
-PCSEL0=\$24A!
-PCSEL1=\$24C!
-PCSELC=\$256!
-
-P5IN=\$240!
-P5OUT=\$242!
-P5DIR=\$244!
-P5REN=\$246!
-P5SEL0=\$24A!
-P5SEL1=\$24C!
-P5SELC=\$256!
-
-P6IN=\$241!
-P6OUT=\$243!
-P6DIR=\$245!
-P6REN=\$247!
-P6SEL0=\$24B!
-P6SEL1=\$24D!
-P6SELC=\$257!
-
-P7IN=\$260!
-P7OUT=\$262!
-P7DIR=\$264!
-P7REN=\$266!
-P7SEL0=\$26A!
-P7SEL1=\$26C!
-P7SELC=\$276!
-
-P9IN=\$280!
-P9OUT=\$282!
-P9DIR=\$284!
-P9REN=\$286!
-P9SEL0=\$28A!
-P9SEL1=\$28C!
-P9SELC=\$296!
-
-PJIN=\$320!
-PJOUT=\$322!
-PJDIR=\$324!
-PJREN=\$326!
-PJSEL0=\$32A!
-PJSEL1=\$32C!
-PJSELC=\$336!
-
-
-TACLR=4!
-TAIFG=1!
-TBCLR=2!
-TBIFG=1!
-CCIFG=1!
-
-TA0CTL=\$340! \ TA0 control
-TA0CCTL0=\$342! \ Capture/compare control 0
-TA0CCTL1=\$344! \ Capture/compare control 1
-TA0CCTL2=\$346! \ Capture/compare control 2
-TA0CCTL3=\$348! \ Capture/compare control 3
-TA0CCTL4=\$34A! \ Capture/compare control 4
-TA0R=\$350! \ TA0 counter register
-TA0CCR0=\$352! \ Capture/compare register 0
-TA0CCR1=\$354! \ Capture/compare register 1
-TA0CCR2=\$356! \ Capture/compare register 2
-TA0CCR2=\$358! \ Capture/compare register 3
-TA0CCR2=\$35A! \ Capture/compare register 4
-TA0EX0=\$360! \ TA0 expansion register 0
-TA0IV=\$36E! \ TA0 interrupt vector
-
-TA1CTL=\$380! \ TA1 control
-TA1CCTL0=\$382! \ Capture/compare control 0
-TA1CCTL1=\$384! \ Capture/compare control 1
-TA1CCTL2=\$386! \ Capture/compare control 2
-TA1R=\$390! \ TA1 counter register
-TA1CCR0=\$392! \ Capture/compare register 0
-TA1CCR1=\$394! \ Capture/compare register 1
-TA1CCR2=\$396! \ Capture/compare register 2
-TA1EX0=\$3A0! \ TA1 expansion register 0
-TA1IV=\$3AE! \ TA1 interrupt vector
-
-TB0CTL=\$3C0! \ TB0 control
-TB0CCTL0=\$3C2! \ Capture/compare control 0
-TB0CCTL1=\$3C4! \ Capture/compare control 1
-TB0CCTL2=\$3C6! \ Capture/compare control 2
-TB0CCTL3=\$3C8! \ Capture/compare control 3
-TB0CCTL4=\$3CA! \ Capture/compare control 4
-TB0CCTL5=\$3CC! \ Capture/compare control 5
-TB0CCTL6=\$3CE! \ Capture/compare control 6
-TB0R=\$3D0! \ TB0 counter register
-TB0CCR0=\$3D2! \ Capture/compare register 0
-TB0CCR1=\$3D4! \ Capture/compare register 1
-TB0CCR2=\$3D6! \ Capture/compare register 2
-TB0CCR3=\$3D8! \ Capture/compare register 3
-TB0CCR5=\$3DA! \ Capture/compare register 4
-TB0CCR5=\$3DC! \ Capture/compare register 5
-TB0CCR6=\$3DE! \ Capture/compare register 6
-TB0EX0=\$3E0! \ TB0 expansion register 0
-TB0IV=\$3EE! \ TB0 interrupt vector
-
-TA2CTL=\$400! \ TA2 control
-TA2CCTL0=\$402! \ Capture/compare control 0
-TA2CCTL1=\$404! \ Capture/compare control 1
-TA2R=\$410! \ TA2 counter register
-TA2CCR0=\$412! \ Capture/compare register 0
-TA2CCR1=\$414! \ Capture/compare register 1
-TA2EX0=\$420! \ TA2 expansion register 0
-TA2IV=\$42E! \ TA2 interrupt vector
-
-CAPTIO0CTL=\$43E! \ Capacitive Touch IO 0 control
-
-TA3CTL=\$440! \ TA3 control
-TA3CCTL0=\$442! \ Capture/compare control 0
-TA3CCTL1=\$444! \ Capture/compare control 1
-TA3CCTL2=\$446! \ Capture/compare control 2
-TA3CCTL3=\$448! \ Capture/compare control 3
-TA3CCTL4=\$44A! \ Capture/compare control 4
-TA3R=\$450! \ TA3 counter register
-TA3CCR0=\$452! \ Capture/compare register 0
-TA3CCR1=\$454! \ Capture/compare register 1
-TA3CCR2=\$456! \ Capture/compare register 2
-TA3CCR3=\$458! \ Capture/compare register 3
-TA3CCR4=\$45A! \ Capture/compare register 4
-TA3EX0=\$460! \ TA3 expansion register 0
-TA3IV=\$46E! \ TA3 interrupt vector
-
-CAPTIO1CTL=\$47E! \ Capacitive Touch IO 1 control
-
-! \ RTC_C
-RTCCTL0_L=\$4A0! \ RTCCTL0_L
-RTCCTL0_H=\$4A1! \ RTCCTL0_H
-RTCCTL1=\$4A2! \ RTCCTL1
-RTCCTL3=\$4A3! \ RTCCTL3
-RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
-RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
-RTCPS=\$4AC! \ RTC prescaler
-RT0PS=\$4AC! \ RTC prescaler 0
-RT1PS=\$4AD! \ RTC prescaler 1
-RTCIV=\$4AE! \ RTC interrupt vector word
-RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
-RTCCNT1=\$4B0! \ Real-Time Counter 1
-RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
-RTCCNT2=\$4B1! \ Real-Time Counter 2
-RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
-RTCCNT3=\$4B2! \ Real-Time Counter 3
-RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
-RTCCNT4=\$4B3! \ Real-Time Counter 4
-RTCDAY=\$4B4! \ RTC days
-RTCMON=\$4B5! \ RTC month
-RTCYEAR=\$4B6!
-RTCYEARL=\$4B6! \ RTC year low
-RTCYEARH=\$4B7! \ RTC year high
-RTCAMIN=\$4B8! \ RTC alarm minutes
-RTCAHOUR=\$4B9! \ RTC alarm hours
-RTCADOW=\$4BA! \ RTC alarm day of week
-RTCADAY=\$4BB! \ RTC alarm days
-BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
-BCD2BIN=\$4BE! \ BCD-to-binary conversion register
-
-RTCHOLD=\$40!
-RTCRDY=\$10!
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-DMAIFG=8!
-
-DMACTL0=\$500! \ DMA module control 0
-DMACTL1=\$502! \ DMA module control 1
-DMACTL2=\$504! \ DMA module control 2
-DMACTL3=\$506! \ DMA module control 3
-DMACTL4=\$508! \ DMA module control 4
-DMAIV=\$50A! \ DMA interrupt vector
-
-DMA0CTL=\$510! \ DMA channel 0 control
-DMA0SAL=\$512! \ DMA channel 0 source address low
-DMA0SAH=\$514! \ DMA channel 0 source address high
-DMA0DAL=\$516! \ DMA channel 0 destination address low
-DMA0DAH=\$518! \ DMA channel 0 destination address high
-DMA0SZ=\$51A! \ DMA channel 0 transfer size
-
-DMA1CTL=\$520! \ DMA channel 1 control
-DMA1SAL=\$522! \ DMA channel 1 source address low
-DMA1SAH=\$524! \ DMA channel 1 source address high
-DMA1DAL=\$526! \ DMA channel 1 destination address low
-DMA1DAH=\$528! \ DMA channel 1 destination address high
-DMA1SZ=\$52A! \ DMA channel 1 transfer size
-
-DMA2CTL=\$530! \ DMA channel 2 control
-DMA2SAL=\$532! \ DMA channel 2 source address low
-DMA2SAH=\$534! \ DMA channel 2 source address high
-DMA2DAL=\$536! \ DMA channel 2 destination address low
-DMA2DAH=\$538! \ DMA channel 2 destination address high
-DMA2SZ=\$53A! \ DMA channel 2 transfer size
-
-
-MPUCTL0=\$5A0! \ MPU control 0
-MPUCTL1=\$5A2! \ MPU control 1
-MPUSEGB2=\$5A4! \ MPU Segmentation Border2
-MPUSEGB1=\$5A6! \ MPU Segmentation Border1
-MPUSAM=\$5A8! \ MPU access management
-MPUIPC0=\$5AA! \ MPU IP control 0
-MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2
-MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1
-
-UCA0CTLW0=\$5C0! \ eUSCI_A control word 0
-UCA0CTLW1=\$5C2! \ eUSCI_A control word 1
-UCA0BRW=\$5C6!
-UCA0BR0=\$5C6! \ eUSCI_A baud rate 0
-UCA0BR1=\$5C7! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$5C8! \ eUSCI_A modulation control
-UCA0STAT=\$5CA! \ eUSCI_A status
-UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer
-UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$5D0! \ eUSCI_A LIN control
-UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-UCA0IE=\$5DA! \ eUSCI_A interrupt enable
-UCA0IFG=\$5DC! \ eUSCI_A interrupt flags
-UCA0IV=\$5DE! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$5E0! \ eUSCI_A control word 0
-UCA1CTLW1=\$5E2! \ eUSCI_A control word 1
-UCA1BRW=\$5E6!
-UCA1BR0=\$5E6! \ eUSCI_A baud rate 0
-UCA1BR1=\$5E7! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$5E8! \ eUSCI_A modulation control
-UCA1STAT=\$5EA! \ eUSCI_A status
-UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer
-UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$5F0! \ eUSCI_A LIN control
-UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control
-UCA1IE=\$5FA! \ eUSCI_A interrupt enable
-UCA1IFG=\$5FC! \ eUSCI_A interrupt flags
-UCA1IV=\$5FE! \ eUSCI_A interrupt vector word
-
-
-UCB0CTLW0=\$640! \ eUSCI_B control word 0
-UCB0CTLW1=\$642! \ eUSCI_B control word 1
-UCB0BRW=\$646!
-UCB0BR0=\$646! \ eUSCI_B bit rate 0
-UCB0BR1=\$647! \ eUSCI_B bit rate 1
-UCB0STATW=\$648! \ eUSCI_B status word
-UCBCNT0=\$649! \ eUSCI_B hardware count
-UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$64C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$65C! \ eUSCI_B received address
-UCB0ADDMASK=\$65E! \ eUSCI_B address mask
-UCB0I2CSA=\$660! \ eUSCI I2C slave address
-UCB0IE=\$66A! \ eUSCI interrupt enable
-UCB0IFG=\$66C! \ eUSCI interrupt flags
-UCB0IV=\$66E! \ eUSCI interrupt vector word
-
-UCB1CTLW0=\$680! \ eUSCI_B control word 0
-UCB1CTLW1=\$682! \ eUSCI_B control word 1
-UCB1BRW=\$686!
-UCB1BR0=\$686! \ eUSCI_B bit rate 0
-UCB1BR1=\$687! \ eUSCI_B bit rate 1
-UCB1STATW=\$688! \ eUSCI_B status word
-UCB1NT0=\$689! \ eUSCI_B hardware count
-UCB1TBCNT=\$68A! \ eUSCI_B byte counter threshold
-UCB1RXBUF=\$68C! \ eUSCI_B receive buffer
-UCB1TXBUF=\$68E! \ eUSCI_B transmit buffer
-UCB1I2COA0=\$694! \ eUSCI_B I2C own address 0
-UCB1I2COA1=\$696! \ eUSCI_B I2C own address 1
-UCB1I2COA2=\$698! \ eUSCI_B I2C own address 2
-UCB1I2COA3=\$69A! \ eUSCI_B I2C own address 3
-UCB1ADDRX=\$69C! \ eUSCI_B received address
-UCB1ADDMASK=\$69E! \ eUSCI_B address mask
-UCB1I2CSA=\$6A0! \ eUSCI I2C slave address
-UCB1IE=\$6AA! \ eUSCI interrupt enable
-UCB1IFG=\$6AC! \ eUSCI interrupt flags
-UCB1IV=\$6AE! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-
-ADC12CTL0=\$800! \ ADC12_B Control 0
-ADC12CTL1=\$802! \ ADC12_B Control 1
-ADC12CTL2=\$804! \ ADC12_B Control 2
-ADC12CTL3=\$806! \ ADC12_B Control 3
-ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register
-ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register
-ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0
-ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1
-ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2
-ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0
-ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1
-ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2
-ADC12IV=\$818! \ ADC12_B Interrupt Vector
-ADC12MCTL0=\$820! \ ADC12_B Memory Control 0
-ADC12MCTL1=\$822! \ ADC12_B Memory Control 1
-ADC12MCTL2=\$824! \ ADC12_B Memory Control 2
-ADC12MCTL3=\$826! \ ADC12_B Memory Control 3
-ADC12MCTL4=\$828! \ ADC12_B Memory Control 4
-ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5
-ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6
-ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7
-ADC12MCTL8=\$830! \ ADC12_B Memory Control 8
-ADC12MCTL9=\$832! \ ADC12_B Memory Control 9
-ADC12MCTL10=\$834! \ ADC12_B Memory Control 10
-ADC12MCTL11=\$836! \ ADC12_B Memory Control 11
-ADC12MCTL12=\$838! \ ADC12_B Memory Control 12
-ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13
-ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14
-ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15
-ADC12MCTL16=\$840! \ ADC12_B Memory Control 16
-ADC12MCTL17=\$842! \ ADC12_B Memory Control 17
-ADC12MCTL18=\$844! \ ADC12_B Memory Control 18
-ADC12MCTL19=\$846! \ ADC12_B Memory Control 19
-ADC12MCTL20=\$848! \ ADC12_B Memory Control 20
-ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21
-ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22
-ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23
-ADC12MCTL24=\$850! \ ADC12_B Memory Control 24
-ADC12MCTL25=\$852! \ ADC12_B Memory Control 25
-ADC12MCTL26=\$854! \ ADC12_B Memory Control 26
-ADC12MCTL27=\$856! \ ADC12_B Memory Control 27
-ADC12MCTL28=\$858! \ ADC12_B Memory Control 28
-ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29
-ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30
-ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31
-ADC12MEM0=\$860! \ ADC12_B Memory 0
-ADC12MEM1=\$862! \ ADC12_B Memory 1
-ADC12MEM2=\$864! \ ADC12_B Memory 2
-ADC12MEM3=\$866! \ ADC12_B Memory 3
-ADC12MEM4=\$868! \ ADC12_B Memory 4
-ADC12MEM5=\$86A! \ ADC12_B Memory 5
-ADC12MEM6=\$86C! \ ADC12_B Memory 6
-ADC12MEM7=\$86E! \ ADC12_B Memory 7
-ADC12MEM8=\$870! \ ADC12_B Memory 8
-ADC12MEM9=\$872! \ ADC12_B Memory 9
-ADC12MEM10=\$874! \ ADC12_B Memory 10
-ADC12MEM11=\$876! \ ADC12_B Memory 11
-ADC12MEM12=\$878! \ ADC12_B Memory 12
-ADC12MEM13=\$87A! \ ADC12_B Memory 13
-ADC12MEM14=\$87C! \ ADC12_B Memory 14
-ADC12MEM15=\$87E! \ ADC12_B Memory 15
-ADC12MEM16=\$880! \ ADC12_B Memory 16
-ADC12MEM17=\$882! \ ADC12_B Memory 17
-ADC12MEM18=\$884! \ ADC12_B Memory 18
-ADC12MEM19=\$886! \ ADC12_B Memory 19
-ADC12MEM20=\$888! \ ADC12_B Memory 20
-ADC12MEM21=\$88A! \ ADC12_B Memory 21
-ADC12MEM22=\$88C! \ ADC12_B Memory 22
-ADC12MEM23=\$88E! \ ADC12_B Memory 23
-ADC12MEM24=\$890! \ ADC12_B Memory 24
-ADC12MEM25=\$892! \ ADC12_B Memory 25
-ADC12MEM26=\$894! \ ADC12_B Memory 26
-ADC12MEM27=\$896! \ ADC12_B Memory 27
-ADC12MEM28=\$898! \ ADC12_B Memory 28
-ADC12MEM29=\$89A! \ ADC12_B Memory 29
-ADC12MEM30=\$89C! \ ADC12_B Memory 30
-ADC12MEM31=\$89E! \ ADC12_B Memory 31
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-CDIFG=1!
-CDIIFG=2!
-
-CDCTL0=\$8C0! \ Comparator_E control register 0
-CDCTL1=\$8C2! \ Comparator_E control register 1
-CDCTL2=\$8C4! \ Comparator_E control register 2
-CDCTL3=\$8C6! \ Comparator_E control register 3
-CDINT=\$8CC! \ Comparator_E interrupt register
-CDIV=\$8CE! \ Comparator_E interrupt vector word
-
-CRC32DIW0=\$980! \ CRC32 data input
-CRC32DIRBW0=\$986! \ CRC32 data input reverse
-CRC32INIRESW0=\$988! \ CRC32 initialization and result word 0
-CRC32INIRESW1=\$98A! \ CRC32 initialization and result word 1
-CRC32RESRW1=\$98! \ CRC32 result reverse word 1
-CRC32RESRW1=\$98E! \ CRC32 result reverse word 0
-CRC16DIW0=\$990! \ CRC16 data input
-CRC16DIRBW0=\$996! \ CRC16 data input reverse
-CRC16INIRESW0=\$998! \ CRC16 initialization and result word 0
-CRC16RESRW1=\$99E! \ CRC16 result reverse word 0
-
-
-AESACTL0=\$9C0! \ AES accelerator control register 0
-AESASTAT=\$9C4! \ AES accelerator status register
-AESAKEY=\$9C6! \ AES accelerator key register
-AESADIN=\$9C8! \ AES accelerator data in register
-AESADOUT=\$9CA! \ AES accelerator data out register
-AESAXDIN=\$9CC! \ AES accelerator XORed data in register
-AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger)
+
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430FR5972.pat, duplicated from MSP430fr6989.pat
+
+; ----------------------------------------------
+; MSP430FR5972 MEMORY MAP
+; ----------------------------------------------
+; 0000-0005 = reserved ROM
+; 0006-001F = tiny RAM 26 bytes
+; 0020-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
+; 1800-19FF = FRAM INFO 512 B
+; 1A00-1AFF = TLV device descriptor info (FRAM 256 B)
+; 1B00-1BFF = ROM boot memory
+; 1C00-23FF = RAM (2 KB)
+; 4400-FF7F = code memory (FRAM 48 kB)
+; FF80-FFFF = interrupt vectors (FRAM 127 B)
+; ----------------------------------------------
+
+
+; ============================================
+; TINY RAM
+; ============================================
+TinyRAM_ORG=\$06;
+TinyRAM_LEN=\$20;
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$1C00;
+RAM_LEN=\$0800;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ----------------------------------------------
+; FastForth RAM memory map (>= 1k):
+; ----------------------------------------------
+LEAVEPTR=\$1C00; Leave-stack pointer, init by QUIT
+LSATCK=\$1C00; leave stack, grow up
+PSTACK=\$1C80; parameter stack, grow down
+RSTACK=\$1CE0; Return stack, grow down
+;
+PAD_I2CADR=\$1CE0; RX I2C address
+PAD_I2CCNT=\$1CE2; count max
+PAD_ORG=\$1CE4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$1D38; TX I2C address
+TIB_I2CCNT=\$1D3A; count of bytes
+TIB_ORG=\$1D3C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$1D90; base address for HOLDS
+HOLD_BASE=\$1DB2; BASE HOLD area, grow down
+;
+HP=\$1DB2; HOLD ptr
+STATEADR=\$1DB4; Interpreter state
+BASEADR=\$1DB6; base
+CAPS=\$1DB8; CAPS ON/OFF
+SOURCE_LEN=\$1DBA; len of input stream
+SOURCE_ORG=\$1DBC; adr of input stream
+TOIN=\$1DBE; >IN
+;
+DP=\$1DC0; dictionary ptr
+LASTVOC=\$1DC2; keep VOC-LINK
+CURRENT=\$1DC4; CURRENT dictionnary ptr
+CONTEXT=\$1DC6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$1DD8;
+LAST_THREAD=\$1DDA;
+LAST_CFA=\$1DDC;
+LAST_PSP=\$1DDE;
+ASMBW1=\$1DE0; 3 backward labels
+ASMBW2=\$1DE2;
+ASMBW3=\$1DE4;
+ASMFW1=\$1DE6; 3 forward labels
+ASMFW2=\$1DE8;
+ASMFW3=\$1DEA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$1DFC;
+SD_BUF_I2CNT=\$1DFE;
+SD_BUF=\$1E00; \ SD_Card buffer
+BUFEND=\$2000;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2002;
+BS_FirstSectorL=\$2004;
+BS_FirstSectorH=\$2006;
+OrgFAT1=\$2008;
+FATSize=\$200A;
+OrgFAT2=\$200C;
+OrgRootDir=\$200E;
+OrgClusters=\$2010; Sector of Cluster 0
+SecPerClus=\$2012;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2014; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2014; CRC:ll word access
+SD_CMD_FRM1=\$2015; ll byte access
+SD_CMD_FRM2=\$2016; LL:hh word access
+SD_CMD_FRM3=\$2017; hh byte access
+SD_CMD_FRM4=\$2018; HH:CMD word access
+SD_CMD_FRM5=\$2019; CMD byte access
+SectorL=\$201A; 2 words
+SectorH=\$201C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$201E;
+BufferLen=\$2020;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2022; 16 bits wide (FAT16)
+ClusterH=\$2024; 16 bits wide (FAT16)
+LastFATsector=\$2026; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2028; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$202A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$202C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$202E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2030;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2032; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2034;
+EndOfPath=\$2036;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2038;
+HandleEnd=\$2118;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2118;
+SDIB_I2CCNT=\$211A;
+SDIB_ORG=\$211C;
+SDIB_LEN=\$54;
+
+SD_END=\$2170;
+SD_LEN=\$16E;
+
+; ----------------------------------------------
+; FRAM
+; ----------------------------------------------
+MAIN_ORG=\$4400; Code space start
+MAIN_LEN=\$24000; 127 k FRAM
+; ----------------------------------------------
+\#LIT=\#\$4400; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$4414; asm CODE run time of QUOTE
+\#MUSMOD=\#\$4428; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$443A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$4442; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$446C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$446E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$447E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$448A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$4496; CODE compiled by IF UNTIL
+\#BRAN=\#\$449C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$449E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$44A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$44AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$44BA;
+\#ABORT_TERM=\#\$4500; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$4572; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$455C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR6989
+; ----------------------------------------------
+MAIN_LEN=\$1FC00; 127 k FRAM
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFC6; FFC6-FFFF
+VECT_LEN=\$3A;
+
+
+AES_VEC=\$FFC6;
+RTC_VEC=\$FFC8;
+P4_VEC=\$FFCC;
+P3_VEC=\$FFCE;
+TA3_X_VEC=\$FFD0;
+TA3_0_VEC=\$FFD2;
+P2_VEC=\$FFD4;
+TA2_X_VEC=\$FFD6;
+TA2_0_VEC=\$FFD8;
+P1_VEC=\$FFDA;
+TA1_X_VEC=\$FFDC;
+TA1_0_VEC=\$FFDE;
+DMA_VEC=\$FFE0;
+EUSCI_B1_VEC=\$FFE2;
+EUSCI_A1_VEC=\$FFE4;
+TA0_X_VEC=\$FFE6;
+TA0_0_VEC=\$FFE8;
+ADC12_B_VEC=\$FFEA;
+EUSCI_B0_VEC=\$FFEC;
+EUSCI_A0_VEC=\$FFEE;
+WDT_VEC=\$FFF2;
+TB0_X_VEC=\$FFF4;
+TB0_0_VEC=\$FFF6;
+COMP_E_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+FRCTLCTL0=\$140; \ FRAM control 0
+GCCTL0=\$144; \ General control 0
+GCCTL1=\$146; \ General control 1
+
+CRC16DI=\$150; \ CRC data input
+CRCDIRB=\$152; \ CRC data input reverse byte
+CRCINIRES=\$154; \ CRC initialization and result
+CRCRESR=\$156; \ CRC result reverse byte
+
+RCCTL0=\$158; \ RAM controller control 0
+
+WDTCTL=\$15C; \ WDT control register
+
+CSCTL0=\$160; \ CS control 0
+CSCTL1=\$162; \ CS control 1
+CSCTL2=\$164; \ CS control 2
+CSCTL3=\$166; \ CS control 3
+CSCTL4=\$168; \ CS control 4
+CSCTL5=\$16A; \ CS control 5
+CSCTL6=\$16C; \ CS control 6
+
+SYSCTL=\$180; \ System control
+SYSJMBC=\$186; \ JTAG mailbox control
+SYSJMBI0=\$188; \ JTAG mailbox input 0
+SYSJMBI1=\$18A; \ JTAG mailbox input 1
+SYSJMBO0=\$18C; \ JTAG mailbox output 0
+SYSJMBO1=\$18E; \ JTAG mailbox output 1
+SYSUNIV=\$19A; \ User NMI vector generator
+SYSSNIV=\$19C; \ System NMI vector generator
+SYSRSTIV=\$19E; \ Reset vector generator
+
+REFCTL=\$1B0; \ Shared reference control
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PASELC=\$216;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1SELC=\$216;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2SELC=\$217;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+PBIN=\$220;
+PBOUT=\$222;
+PBDIR=\$224;
+PBREN=\$226;
+PBSEL0=\$22A;
+PBSEL1=\$22C;
+PBSELC=\$236;
+PBIES=\$238;
+PBIE=\$23A;
+PBIFG=\$23C;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+P3IV=\$22E;
+P3SELC=\$236;
+P3IES=\$238;
+P3IE=\$23A;
+P3IFG=\$23C;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+P4SEL1=\$22D;
+P4SELC=\$237;
+P4IES=\$239;
+P4IE=\$23B;
+P4IFG=\$23D;
+P4IV=\$23E;
+
+PCIN=\$240;
+PCOUT=\$242;
+PCDIR=\$244;
+PCREN=\$246;
+PCSEL0=\$24A;
+PCSEL1=\$24C;
+PCSELC=\$256;
+
+P5IN=\$240;
+P5OUT=\$242;
+P5DIR=\$244;
+P5REN=\$246;
+P5SEL0=\$24A;
+P5SEL1=\$24C;
+P5SELC=\$256;
+
+P6IN=\$241;
+P6OUT=\$243;
+P6DIR=\$245;
+P6REN=\$247;
+P6SEL0=\$24B;
+P6SEL1=\$24D;
+P6SELC=\$257;
+
+P7IN=\$260;
+P7OUT=\$262;
+P7DIR=\$264;
+P7REN=\$266;
+P7SEL0=\$26A;
+P7SEL1=\$26C;
+P7SELC=\$276;
+
+P9IN=\$280;
+P9OUT=\$282;
+P9DIR=\$284;
+P9REN=\$286;
+P9SEL0=\$28A;
+P9SEL1=\$28C;
+P9SELC=\$296;
+
+PJIN=\$320;
+PJOUT=\$322;
+PJDIR=\$324;
+PJREN=\$326;
+PJSEL0=\$32A;
+PJSEL1=\$32C;
+PJSELC=\$336;
+
+
+TACLR=4;
+TAIFG=1;
+TBCLR=2;
+TBIFG=1;
+CCIFG=1;
+
+TA0CTL=\$340; \ TA0 control
+TA0CCTL0=\$342; \ Capture/compare control 0
+TA0CCTL1=\$344; \ Capture/compare control 1
+TA0CCTL2=\$346; \ Capture/compare control 2
+TA0CCTL3=\$348; \ Capture/compare control 3
+TA0CCTL4=\$34A; \ Capture/compare control 4
+TA0R=\$350; \ TA0 counter register
+TA0CCR0=\$352; \ Capture/compare register 0
+TA0CCR1=\$354; \ Capture/compare register 1
+TA0CCR2=\$356; \ Capture/compare register 2
+TA0CCR2=\$358; \ Capture/compare register 3
+TA0CCR2=\$35A; \ Capture/compare register 4
+TA0EX0=\$360; \ TA0 expansion register 0
+TA0IV=\$36E; \ TA0 interrupt vector
+
+TA1CTL=\$380; \ TA1 control
+TA1CCTL0=\$382; \ Capture/compare control 0
+TA1CCTL1=\$384; \ Capture/compare control 1
+TA1CCTL2=\$386; \ Capture/compare control 2
+TA1R=\$390; \ TA1 counter register
+TA1CCR0=\$392; \ Capture/compare register 0
+TA1CCR1=\$394; \ Capture/compare register 1
+TA1CCR2=\$396; \ Capture/compare register 2
+TA1EX0=\$3A0; \ TA1 expansion register 0
+TA1IV=\$3AE; \ TA1 interrupt vector
+
+TB0CTL=\$3C0; \ TB0 control
+TB0CCTL0=\$3C2; \ Capture/compare control 0
+TB0CCTL1=\$3C4; \ Capture/compare control 1
+TB0CCTL2=\$3C6; \ Capture/compare control 2
+TB0CCTL3=\$3C8; \ Capture/compare control 3
+TB0CCTL4=\$3CA; \ Capture/compare control 4
+TB0CCTL5=\$3CC; \ Capture/compare control 5
+TB0CCTL6=\$3CE; \ Capture/compare control 6
+TB0R=\$3D0; \ TB0 counter register
+TB0CCR0=\$3D2; \ Capture/compare register 0
+TB0CCR1=\$3D4; \ Capture/compare register 1
+TB0CCR2=\$3D6; \ Capture/compare register 2
+TB0CCR3=\$3D8; \ Capture/compare register 3
+TB0CCR5=\$3DA; \ Capture/compare register 4
+TB0CCR5=\$3DC; \ Capture/compare register 5
+TB0CCR6=\$3DE; \ Capture/compare register 6
+TB0EX0=\$3E0; \ TB0 expansion register 0
+TB0IV=\$3EE; \ TB0 interrupt vector
+
+TA2CTL=\$400; \ TA2 control
+TA2CCTL0=\$402; \ Capture/compare control 0
+TA2CCTL1=\$404; \ Capture/compare control 1
+TA2R=\$410; \ TA2 counter register
+TA2CCR0=\$412; \ Capture/compare register 0
+TA2CCR1=\$414; \ Capture/compare register 1
+TA2EX0=\$420; \ TA2 expansion register 0
+TA2IV=\$42E; \ TA2 interrupt vector
+
+CAPTIO0CTL=\$43E; \ Capacitive Touch IO 0 control
+
+TA3CTL=\$440; \ TA3 control
+TA3CCTL0=\$442; \ Capture/compare control 0
+TA3CCTL1=\$444; \ Capture/compare control 1
+TA3CCTL2=\$446; \ Capture/compare control 2
+TA3CCTL3=\$448; \ Capture/compare control 3
+TA3CCTL4=\$44A; \ Capture/compare control 4
+TA3R=\$450; \ TA3 counter register
+TA3CCR0=\$452; \ Capture/compare register 0
+TA3CCR1=\$454; \ Capture/compare register 1
+TA3CCR2=\$456; \ Capture/compare register 2
+TA3CCR3=\$458; \ Capture/compare register 3
+TA3CCR4=\$45A; \ Capture/compare register 4
+TA3EX0=\$460; \ TA3 expansion register 0
+TA3IV=\$46E; \ TA3 interrupt vector
+
+CAPTIO1CTL=\$47E; \ Capacitive Touch IO 1 control
+
+; \ RTC_C
+RTCCTL0_L=\$4A0; \ RTCCTL0_L
+RTCCTL0_H=\$4A1; \ RTCCTL0_H
+RTCCTL1=\$4A2; \ RTCCTL1
+RTCCTL3=\$4A3; \ RTCCTL3
+RTCPS0CTL=\$4A8; \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA; \ RTC prescaler 1 control
+RTCPS=\$4AC; \ RTC prescaler
+RT0PS=\$4AC; \ RTC prescaler 0
+RT1PS=\$4AD; \ RTC prescaler 1
+RTCIV=\$4AE; \ RTC interrupt vector word
+RTCSEC=\$4B0; \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCCNT1=\$4B0; \ Real-Time Counter 1
+RTCMIN=\$4B1; \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCCNT2=\$4B1; \ Real-Time Counter 2
+RTCHOUR=\$4B2; \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCCNT3=\$4B2; \ Real-Time Counter 3
+RTCDOW=\$4B3; \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCCNT4=\$4B3; \ Real-Time Counter 4
+RTCDAY=\$4B4; \ RTC days
+RTCMON=\$4B5; \ RTC month
+RTCYEAR=\$4B6;
+RTCYEARL=\$4B6; \ RTC year low
+RTCYEARH=\$4B7; \ RTC year high
+RTCAMIN=\$4B8; \ RTC alarm minutes
+RTCAHOUR=\$4B9; \ RTC alarm hours
+RTCADOW=\$4BA; \ RTC alarm day of week
+RTCADAY=\$4BB; \ RTC alarm days
+BIN2BCD=\$4BC; \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE; \ BCD-to-binary conversion register
+
+RTCHOLD=\$40;
+RTCRDY=\$10;
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+DMAIFG=8;
+
+DMACTL0=\$500; \ DMA module control 0
+DMACTL1=\$502; \ DMA module control 1
+DMACTL2=\$504; \ DMA module control 2
+DMACTL3=\$506; \ DMA module control 3
+DMACTL4=\$508; \ DMA module control 4
+DMAIV=\$50A; \ DMA interrupt vector
+
+DMA0CTL=\$510; \ DMA channel 0 control
+DMA0SAL=\$512; \ DMA channel 0 source address low
+DMA0SAH=\$514; \ DMA channel 0 source address high
+DMA0DAL=\$516; \ DMA channel 0 destination address low
+DMA0DAH=\$518; \ DMA channel 0 destination address high
+DMA0SZ=\$51A; \ DMA channel 0 transfer size
+
+DMA1CTL=\$520; \ DMA channel 1 control
+DMA1SAL=\$522; \ DMA channel 1 source address low
+DMA1SAH=\$524; \ DMA channel 1 source address high
+DMA1DAL=\$526; \ DMA channel 1 destination address low
+DMA1DAH=\$528; \ DMA channel 1 destination address high
+DMA1SZ=\$52A; \ DMA channel 1 transfer size
+
+DMA2CTL=\$530; \ DMA channel 2 control
+DMA2SAL=\$532; \ DMA channel 2 source address low
+DMA2SAH=\$534; \ DMA channel 2 source address high
+DMA2DAL=\$536; \ DMA channel 2 destination address low
+DMA2DAH=\$538; \ DMA channel 2 destination address high
+DMA2SZ=\$53A; \ DMA channel 2 transfer size
+
+
+MPUCTL0=\$5A0; \ MPU control 0
+MPUCTL1=\$5A2; \ MPU control 1
+MPUSEGB2=\$5A4; \ MPU Segmentation Border2
+MPUSEGB1=\$5A6; \ MPU Segmentation Border1
+MPUSAM=\$5A8; \ MPU access management
+MPUIPC0=\$5AA; \ MPU IP control 0
+MPUIPSEGB2=\$5AC; \ MPU IP Encapsulation Segment Border 2
+MPUIPSEGB1=\$5AE; \ MPU IP Encapsulation Segment Border 1
+
+UCA0CTLW0=\$5C0; \ eUSCI_A control word 0
+UCA0CTLW1=\$5C2; \ eUSCI_A control word 1
+UCA0BRW=\$5C6;
+UCA0BR0=\$5C6; \ eUSCI_A baud rate 0
+UCA0BR1=\$5C7; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$5C8; \ eUSCI_A modulation control
+UCA0STAT=\$5CA; \ eUSCI_A status
+UCA0RXBUF=\$5CC; \ eUSCI_A receive buffer
+UCA0TXBUF=\$5CE; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$5D0; \ eUSCI_A LIN control
+UCA0IRTCTL=\$5D2; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$5D3; \ eUSCI_A IrDA receive control
+UCA0IE=\$5DA; \ eUSCI_A interrupt enable
+UCA0IFG=\$5DC; \ eUSCI_A interrupt flags
+UCA0IV=\$5DE; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$5E0; \ eUSCI_A control word 0
+UCA1CTLW1=\$5E2; \ eUSCI_A control word 1
+UCA1BRW=\$5E6;
+UCA1BR0=\$5E6; \ eUSCI_A baud rate 0
+UCA1BR1=\$5E7; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$5E8; \ eUSCI_A modulation control
+UCA1STAT=\$5EA; \ eUSCI_A status
+UCA1RXBUF=\$5EC; \ eUSCI_A receive buffer
+UCA1TXBUF=\$5EE; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$5F0; \ eUSCI_A LIN control
+UCA1IRTCTL=\$5F2; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$5F3; \ eUSCI_A IrDA receive control
+UCA1IE=\$5FA; \ eUSCI_A interrupt enable
+UCA1IFG=\$5FC; \ eUSCI_A interrupt flags
+UCA1IV=\$5FE; \ eUSCI_A interrupt vector word
+
+
+UCB0CTLW0=\$640; \ eUSCI_B control word 0
+UCB0CTLW1=\$642; \ eUSCI_B control word 1
+UCB0BRW=\$646;
+UCB0BR0=\$646; \ eUSCI_B bit rate 0
+UCB0BR1=\$647; \ eUSCI_B bit rate 1
+UCB0STATW=\$648; \ eUSCI_B status word
+UCBCNT0=\$649; \ eUSCI_B hardware count
+UCB0TBCNT=\$64A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$64C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$64E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$654; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$656; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$658; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$65A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$65C; \ eUSCI_B received address
+UCB0ADDMASK=\$65E; \ eUSCI_B address mask
+UCB0I2CSA=\$660; \ eUSCI I2C slave address
+UCB0IE=\$66A; \ eUSCI interrupt enable
+UCB0IFG=\$66C; \ eUSCI interrupt flags
+UCB0IV=\$66E; \ eUSCI interrupt vector word
+
+UCB1CTLW0=\$680; \ eUSCI_B control word 0
+UCB1CTLW1=\$682; \ eUSCI_B control word 1
+UCB1BRW=\$686;
+UCB1BR0=\$686; \ eUSCI_B bit rate 0
+UCB1BR1=\$687; \ eUSCI_B bit rate 1
+UCB1STATW=\$688; \ eUSCI_B status word
+UCB1NT0=\$689; \ eUSCI_B hardware count
+UCB1TBCNT=\$68A; \ eUSCI_B byte counter threshold
+UCB1RXBUF=\$68C; \ eUSCI_B receive buffer
+UCB1TXBUF=\$68E; \ eUSCI_B transmit buffer
+UCB1I2COA0=\$694; \ eUSCI_B I2C own address 0
+UCB1I2COA1=\$696; \ eUSCI_B I2C own address 1
+UCB1I2COA2=\$698; \ eUSCI_B I2C own address 2
+UCB1I2COA3=\$69A; \ eUSCI_B I2C own address 3
+UCB1ADDRX=\$69C; \ eUSCI_B received address
+UCB1ADDMASK=\$69E; \ eUSCI_B address mask
+UCB1I2CSA=\$6A0; \ eUSCI I2C slave address
+UCB1IE=\$6AA; \ eUSCI interrupt enable
+UCB1IFG=\$6AC; \ eUSCI interrupt flags
+UCB1IV=\$6AE; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+
+ADC12CTL0=\$800; \ ADC12_B Control 0
+ADC12CTL1=\$802; \ ADC12_B Control 1
+ADC12CTL2=\$804; \ ADC12_B Control 2
+ADC12CTL3=\$806; \ ADC12_B Control 3
+ADC12LO=\$808; \ ADC12_B Window Comparator Low Threshold Register
+ADC12HI=\$80A; \ ADC12_B Window Comparator High Threshold Register
+ADC12IFGR0=\$80C; \ ADC12_B Interrupt Flag Register 0
+ADC12IFGR1=\$80E; \ ADC12_B Interrupt Flag Register 1
+ADC12IFGR2=\$810; \ ADC12_B Interrupt Flag Register 2
+ADC12IER0=\$812; \ ADC12_B Interrupt Enable Register 0
+ADC12IER1=\$814; \ ADC12_B Interrupt Enable Register 1
+ADC12IER2=\$816; \ ADC12_B Interrupt Enable Register 2
+ADC12IV=\$818; \ ADC12_B Interrupt Vector
+ADC12MCTL0=\$820; \ ADC12_B Memory Control 0
+ADC12MCTL1=\$822; \ ADC12_B Memory Control 1
+ADC12MCTL2=\$824; \ ADC12_B Memory Control 2
+ADC12MCTL3=\$826; \ ADC12_B Memory Control 3
+ADC12MCTL4=\$828; \ ADC12_B Memory Control 4
+ADC12MCTL5=\$82A; \ ADC12_B Memory Control 5
+ADC12MCTL6=\$82C; \ ADC12_B Memory Control 6
+ADC12MCTL7=\$82E; \ ADC12_B Memory Control 7
+ADC12MCTL8=\$830; \ ADC12_B Memory Control 8
+ADC12MCTL9=\$832; \ ADC12_B Memory Control 9
+ADC12MCTL10=\$834; \ ADC12_B Memory Control 10
+ADC12MCTL11=\$836; \ ADC12_B Memory Control 11
+ADC12MCTL12=\$838; \ ADC12_B Memory Control 12
+ADC12MCTL13=\$83A; \ ADC12_B Memory Control 13
+ADC12MCTL14=\$83C; \ ADC12_B Memory Control 14
+ADC12MCTL15=\$83E; \ ADC12_B Memory Control 15
+ADC12MCTL16=\$840; \ ADC12_B Memory Control 16
+ADC12MCTL17=\$842; \ ADC12_B Memory Control 17
+ADC12MCTL18=\$844; \ ADC12_B Memory Control 18
+ADC12MCTL19=\$846; \ ADC12_B Memory Control 19
+ADC12MCTL20=\$848; \ ADC12_B Memory Control 20
+ADC12MCTL21=\$84A; \ ADC12_B Memory Control 21
+ADC12MCTL22=\$84C; \ ADC12_B Memory Control 22
+ADC12MCTL23=\$84E; \ ADC12_B Memory Control 23
+ADC12MCTL24=\$850; \ ADC12_B Memory Control 24
+ADC12MCTL25=\$852; \ ADC12_B Memory Control 25
+ADC12MCTL26=\$854; \ ADC12_B Memory Control 26
+ADC12MCTL27=\$856; \ ADC12_B Memory Control 27
+ADC12MCTL28=\$858; \ ADC12_B Memory Control 28
+ADC12MCTL29=\$85A; \ ADC12_B Memory Control 29
+ADC12MCTL30=\$85C; \ ADC12_B Memory Control 30
+ADC12MCTL31=\$85E; \ ADC12_B Memory Control 31
+ADC12MEM0=\$860; \ ADC12_B Memory 0
+ADC12MEM1=\$862; \ ADC12_B Memory 1
+ADC12MEM2=\$864; \ ADC12_B Memory 2
+ADC12MEM3=\$866; \ ADC12_B Memory 3
+ADC12MEM4=\$868; \ ADC12_B Memory 4
+ADC12MEM5=\$86A; \ ADC12_B Memory 5
+ADC12MEM6=\$86C; \ ADC12_B Memory 6
+ADC12MEM7=\$86E; \ ADC12_B Memory 7
+ADC12MEM8=\$870; \ ADC12_B Memory 8
+ADC12MEM9=\$872; \ ADC12_B Memory 9
+ADC12MEM10=\$874; \ ADC12_B Memory 10
+ADC12MEM11=\$876; \ ADC12_B Memory 11
+ADC12MEM12=\$878; \ ADC12_B Memory 12
+ADC12MEM13=\$87A; \ ADC12_B Memory 13
+ADC12MEM14=\$87C; \ ADC12_B Memory 14
+ADC12MEM15=\$87E; \ ADC12_B Memory 15
+ADC12MEM16=\$880; \ ADC12_B Memory 16
+ADC12MEM17=\$882; \ ADC12_B Memory 17
+ADC12MEM18=\$884; \ ADC12_B Memory 18
+ADC12MEM19=\$886; \ ADC12_B Memory 19
+ADC12MEM20=\$888; \ ADC12_B Memory 20
+ADC12MEM21=\$88A; \ ADC12_B Memory 21
+ADC12MEM22=\$88C; \ ADC12_B Memory 22
+ADC12MEM23=\$88E; \ ADC12_B Memory 23
+ADC12MEM24=\$890; \ ADC12_B Memory 24
+ADC12MEM25=\$892; \ ADC12_B Memory 25
+ADC12MEM26=\$894; \ ADC12_B Memory 26
+ADC12MEM27=\$896; \ ADC12_B Memory 27
+ADC12MEM28=\$898; \ ADC12_B Memory 28
+ADC12MEM29=\$89A; \ ADC12_B Memory 29
+ADC12MEM30=\$89C; \ ADC12_B Memory 30
+ADC12MEM31=\$89E; \ ADC12_B Memory 31
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CDIFG=1;
+CDIIFG=2;
+
+CDCTL0=\$8C0; \ Comparator_E control register 0
+CDCTL1=\$8C2; \ Comparator_E control register 1
+CDCTL2=\$8C4; \ Comparator_E control register 2
+CDCTL3=\$8C6; \ Comparator_E control register 3
+CDINT=\$8CC; \ Comparator_E interrupt register
+CDIV=\$8CE; \ Comparator_E interrupt vector word
+
+CRC32DIW0=\$980; \ CRC32 data input
+CRC32DIRBW0=\$986; \ CRC32 data input reverse
+CRC32INIRESW0=\$988; \ CRC32 initialization and result word 0
+CRC32INIRESW1=\$98A; \ CRC32 initialization and result word 1
+CRC32RESRW1=\$98; \ CRC32 result reverse word 1
+CRC32RESRW1=\$98E; \ CRC32 result reverse word 0
+CRC16DIW0=\$990; \ CRC16 data input
+CRC16DIRBW0=\$996; \ CRC16 data input reverse
+CRC16INIRESW0=\$998; \ CRC16 initialization and result word 0
+CRC16RESRW1=\$99E; \ CRC16 result reverse word 0
+
+
+AESACTL0=\$9C0; \ AES accelerator control register 0
+AESASTAT=\$9C4; \ AES accelerator status register
+AESAKEY=\$9C6; \ AES accelerator key register
+AESADIN=\$9C8; \ AES accelerator data in register
+AESADOUT=\$9CA; \ AES accelerator data out register
+AESAXDIN=\$9CC; \ AES accelerator XORed data in register
+AESAXIN =\$9CE; \ AES accelerator XORed data in register (no trigger)
.listing off
DEVICE = "MSP430FR5994"
-
+HMPY ; hardware multiplier
; ----------------------------------------------
; MSP430FR5994 MEMORY MAP
-!MSP430fr5994.pat
-
-! ----------------------------------------------
-! MSP430FR5994 MEMORY MAP
-! ----------------------------------------------
-! 000A-001F = tiny RAM
-! 0020-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
-! 1800-19FF = FRAM INFO 512 B
-! 1A00-1AFF = FRAM TLV device descriptor info (256 B)
-! 1C00-2BFF = RAM (4KB)
-! 2C00-3BFF = sharedRAM (4kB)
-! 4000-FF7F = FRAM MAIN
-! FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
-! 10000-
-! ----------------------------------------------
-! PAGESIZE .equ 512 ; MPU unit
-
-
-! ============================================
-! TINY RAM
-! ============================================
-TinyRAM_ORG=\$0A!
-TinyRAM_LEN=\$16!
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO addresses
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-!
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0100!
-DEVICEID=\$1A04!
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$1C00!
-RAM_LEN=\$1000!
-SharedRAM_ORG=\$2C00!
-SharedRAM_LEN=\$1000!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ----------------------------------------------
-! FastForth RAM memory map (>= 1k):
-! ----------------------------------------------
-LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT
-LSATCK=\$1C00! leave stack, grow up
-PSTACK=\$1C80! parameter stack, grow down
-RSTACK=\$1CE0! Return stack, grow down
-!
-PAD_I2CADR=\$1CE0! RX I2C address
-PAD_I2CCNT=\$1CE2! count max
-PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$1D38! TX I2C address
-TIB_I2CCNT=\$1D3A! count of bytes
-TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$1D90! base address for HOLDS
-HOLD_BASE=\$1DB2! BASE HOLD area, grow down
-!
-HP=\$1DB2! HOLD ptr
-LAST_NFA=\$1DB4!
-LAST_THREAD=\$1DB6!
-LAST_CFA=\$1DB8!
-LAST_PSP=\$1DBA!
-!
-STATEADR=\$1DBC! Interpreter state
-BASEADR=\$1DBE! base
-CAPS=\$1DC0! CAPS ON/OFF
-!
-SOURCE_LEN=\$1DC2! len of input stream
-SOURCE_ORG=\$1DC4! adr of input stream
-TOIN=\$1DC6! >IN
-DP=\$1DC8! dictionary ptr
-!
-LASTVOC=\$1DCA! keep VOC-LINK
-CURRENT=\$1DCC! CURRENT dictionnary ptr
-CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!1DE0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$1DFC!
-SD_BUF_I2CNT=\$1DFE!
-SD_BUF=\$1E00! \ SD_Card buffer
-BUFEND=\$2000!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2002!
-BS_FirstSectorL=\$2004!
-BS_FirstSectorH=\$2006!
-OrgFAT1=\$2008!
-FATSize=\$200A!
-OrgFAT2=\$200C!
-OrgRootDir=\$200E!
-OrgClusters=\$2010! Sector of Cluster 0
-SecPerClus=\$2012!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2014! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2014! CRC:ll word access
-SD_CMD_FRM1=\$2015! ll byte access
-SD_CMD_FRM2=\$2016! LL:hh word access
-SD_CMD_FRM3=\$2017! hh byte access
-SD_CMD_FRM4=\$2018! HH:CMD word access
-SD_CMD_FRM5=\$2019! CMD byte access
-SectorL=\$201A! 2 words
-SectorH=\$201C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$201E!
-BufferLen=\$2020!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2022! 16 bits wide (FAT16)
-ClusterH=\$2024! 16 bits wide (FAT16)
-LastFATsector=\$2026! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2028! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$202A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$202C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$202E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2030!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2032! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2034!
-EndOfPath=\$2036!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2038!
-HandleEnd=\$2118!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2118!
-SDIB_I2CCNT=\$211A!
-SDIB_ORG=\$211C!
-SDIB_LEN=\$54!
-
-SD_END=\$2170!
-SD_LEN=\$16E!
-
-SPI_X_GET=SPI_GET+2!
-SPI_PUT=SPI_GET+4!
-SD_CARD_ID_ERROR=SD_ERROR+6!
-ReadSectorWX=READ_SECT+8!
-WriteSectorWX=WRITE_SECT+8!
-
-! ============================================
-! FRAM MAIN
-! ============================================
-MAIN_ORG=\$4000! Code space start
-MAIN_LEN=\$40000! 240 kb FRAM
-! ----------------------------------------------
-SLEEP=\$4000! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$400A! CODE compiled by LITERAL
-XSQUOTE=\$401E! CODE compiled by S" and S_
-HEREXEC=\$4032! CODE HERE and BEGIN execute address
-MUSMOD=\$403E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$4050! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$4058! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$4082! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$4084! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$4094! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$40A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$40AC! CODE compiled by IF UNTIL
-BRAN=\$40B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$40B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$40B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$40C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$40D0! asm CODE common part of SYS and QABORT, starts FORTH engine
-QABORT=\$4108! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$4112! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$4154! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$417E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$4184! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL &SOFT_APP)
-UART_WARM=\$4186! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$4144! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$4146! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$4150! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$4150! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$4152! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$417A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR5994
-! ----------------------------------------------
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0, enable JTAG/SBW
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits max
-IPE_SIG_VALID=\$FF88! one word
-IPE_STR_PTR_SRC=\$FF8A! one word
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\0FFB4! FFB4-FFFF
-VECT_LEN=\$4C!
-
-
-LEA_VEC=\$FFB4!
-P8_VEC=\$FFB6!
-P7_VEC=\$FFB8!
-EUSCI_B3_VEC=\$FFBA!
-EUSCI_B2_VEC=\$FFBC!
-EUSCI_B1_VEC=\$FFBE!
-EUSCI_A3_VEC=\$FFC0!
-EUSCI_A2_VEC=\$FFC2!
-P6_VEC=\$FFC4!
-P5_VEC=\$FFC6!
-TA4_X_VEC=\$FFC8!
-TA4_0_VEC=\$FFCA!
-AES_VEC=\$FFCC!
-RTC_C_VEC=\$FFCE!
-P4_VEC=\$FFD0!
-P3_VEC=\$FFD2!
-TA3_X_VEC=\$FFD4!
-TA3_0_VEC=\$FFD6!
-P2_VEC=\$FFD8!
-TA2_X_VEC=\$FFDA!
-TA2_0_VEC=\$FFDC!
-P1_VEC=\$FFDE!
-TA1_X_VEC=\$FFE0!
-TA1_0_VEC=\$FFE2!
-DMA_VEC=\$FFE4!
-EUSCI_A1_VEC=\$FFE6!
-TA0_X_VEC=\$FFE8!
-TA0_0_VEC=\$FFEA!
-ADC12_B_VEC=\$FFEC!
-EUSCI_B0_VEC=\$FFEE!
-EUSCI_A0_VEC=\$FFF0!
-WDT_VEC=\$FFF2!
-TB0_X_VEC=\$FFF4!
-TB0_0_VEC=\$FFF6!
-COMP_E_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-FRCTLCTL0=\$140! \ FRAM control 0
-GCCTL0=\$144! \ General control 0
-GCCTL1=\$146! \ General control 1
-
-CRC16DI=\$150! \ CRC data input
-CRCDIRB=\$152! \ CRC data input reverse byte
-CRCINIRES=\$154! \ CRC initialization and result
-CRCRESR=\$156! \ CRC result reverse byte
-
-
-RCCTL0=\$158! \ RAM controller control 0
-
-
-WDTCTL=\$15C! \ WDT control register
-
-CSCTL0=\$160! \ CS control 0
-CSCTL1=\$162! \ CS control 1
-CSCTL2=\$164! \ CS control 2
-CSCTL3=\$166! \ CS control 3
-CSCTL4=\$168! \ CS control 4
-CSCTL5=\$16A! \ CS control 5
-CSCTL6=\$16C! \ CS control 6
-
-SYSCTL=\$180! \ System control
-SYSJMBC=\$186! \ JTAG mailbox control
-SYSJMBI0=\$188! \ JTAG mailbox input 0
-SYSJMBI1=\$18A! \ JTAG mailbox input 1
-SYSJMBO0=\$18C! \ JTAG mailbox output 0
-SYSJMBO1=\$18E! \ JTAG mailbox output 1
-SYSUNIV=\$19A! \ User NMI vector generator
-SYSSNIV=\$19C! \ System NMI vector generator
-SYSRSTIV=\$19E! \ Reset vector generator
-
-REFCTL=\$1B0! \ Shared reference control
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PASELC=\$216!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1SELC=\$216!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2SELC=\$217!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-PBIN=\$220!
-PBOUT=\$222!
-PBDIR=\$224!
-PBREN=\$226!
-PBSEL0=\$22A!
-PBSEL1=\$22C!
-PBSELC=\$236!
-PBIES=\$238!
-PBIE=\$23A!
-PBIFG=\$23C!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-P3IV=\$22E!
-P3SELC=\$236!
-P3IES=\$238!
-P3IE=\$23A!
-P3IFG=\$23C!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-P4SEL1=\$22D!
-P4SELC=\$237!
-P4IES=\$239!
-P4IE=\$23B!
-P4IFG=\$23D!
-P4IV=\$23E!
-
-PCIN=\$240!
-PCOUT=\$242!
-PCDIR=\$244!
-PCREN=\$246!
-PCSEL0=\$24A!
-PCSEL1=\$24C!
-PCSELC=\$256!
-PCIES=\$258!
-PCIE=\$25A!
-PCIFG=\$25C!
-
-P5IN=\$240!
-P5OUT=\$242!
-P5DIR=\$244!
-P5REN=\$246!
-P5SEL0=\$24A!
-P5SEL1=\$24C!
-P5IV=\$24E!
-P5SELC=\$256!
-P5IES=\$258!
-P5IE=\$25A!
-P5IFG=\$25C!
-
-P6IN=\$241!
-P6OUT=\$243!
-P6DIR=\$245!
-P6REN=\$247!
-P6SEL0=\$24B!
-P6SEL1=\$24D!
-P6SELC=\$257!
-P6IES=\$259!
-P6IE=\$25B!
-P6IFG=\$25D!
-P6IV=\$25E!
-
-PDIN=\$260!
-PDOUT=\$262!
-PDDIR=\$264!
-PDREN=\$266!
-PDSEL0=\$26A!
-PDSEL1=\$26C!
-PDSELC=\$276!
-PDIES=\$278!
-PDIE=\$27A!
-PDIFG=\$27C!
-
-P7IN=\$260!
-P7OUT=\$262!
-P7DIR=\$264!
-P7REN=\$266!
-P7SEL0=\$26A!
-P7SEL1=\$26C!
-P7IV=\$26E!
-P7SELC=\$276!
-P7IES=\$278!
-P7IE=\$27A!
-P7IFG=\$27C!
-
-P8IN=\$261!
-P8OUT=\$263!
-P8DIR=\$265!
-P8REN=\$267!
-P8SEL0=\$26B!
-P8SEL1=\$26D!
-P8SELC=\$277!
-P8IES=\$279!
-P8IE=\$27B!
-P8IFG=\$27D!
-P8IV=\$27E!
-
-PJIN=\$320!
-PJOUT=\$322!
-PJDIR=\$324!
-PJREN=\$326!
-PJSEL0=\$32A!
-PJSEL1=\$32C!
-PJSELC=\$336!
-
-
-TACLR=4!
-TAIFG=1!
-TBCLR=2!
-TBIFG=1!
-CCIFG=1!
-
-TA0CTL=\$340! \ TA0 control
-TA0CCTL0=\$342! \ Capture/compare control 0
-TA0CCTL1=\$344! \ Capture/compare control 1
-TA0CCTL2=\$346! \ Capture/compare control 2
-TA0R=\$350! \ TA0 counter register
-TA0CCR0=\$352! \ Capture/compare register 0
-TA0CCR1=\$354! \ Capture/compare register 1
-TA0CCR2=\$356! \ Capture/compare register 2
-TA0EX0=\$360! \ TA0 expansion register 0
-TA0IV=\$36E! \ TA0 interrupt vector
-
-TA1CTL=\$380! \ TA1 control
-TA1CCTL0=\$382! \ Capture/compare control 0
-TA1CCTL1=\$384! \ Capture/compare control 1
-TA1CCTL2=\$386! \ Capture/compare control 2
-TA1R=\$390! \ TA1 counter register
-TA1CCR0=\$392! \ Capture/compare register 0
-TA1CCR1=\$394! \ Capture/compare register 1
-TA1CCR2=\$396! \ Capture/compare register 2
-TA1EX0=\$3A0! \ TA1 expansion register 0
-TA1IV=\$3AE! \ TA1 interrupt vector
-
-TB0CTL=\$3C0! \ TB0 control
-TB0CCTL0=\$3C2! \ Capture/compare control 0
-TB0CCTL1=\$3C4! \ Capture/compare control 1
-TB0CCTL2=\$3C6! \ Capture/compare control 2
-TB0CCTL3=\$3C8! \ Capture/compare control 3
-TB0CCTL4=\$3CA! \ Capture/compare control 4
-TB0CCTL5=\$3CC! \ Capture/compare control 5
-TB0CCTL6=\$3CE! \ Capture/compare control 6
-TB0R=\$3D0! \ TB0 counter register
-TB0CCR0=\$3D2! \ Capture/compare register 0
-TB0CCR1=\$3D4! \ Capture/compare register 1
-TB0CCR2=\$3D6! \ Capture/compare register 2
-TB0CCR3=\$3D8! \ Capture/compare register 3
-TB0CCR5=\$3DA! \ Capture/compare register 4
-TB0CCR5=\$3DC! \ Capture/compare register 5
-TB0CCR6=\$3DE! \ Capture/compare register 6
-TB0EX0=\$3E0! \ TB0 expansion register 0
-TB0IV=\$3EE! \ TB0 interrupt vector
-
-TA2CTL=\$400! \ TA2 control
-TA2CCTL0=\$402! \ Capture/compare control 0
-TA2CCTL1=\$404! \ Capture/compare control 1
-TA2R=\$410! \ TA2 counter register
-TA2CCR0=\$412! \ Capture/compare register 0
-TA2CCR1=\$414! \ Capture/compare register 1
-TA2EX0=\$420! \ TA2 expansion register 0
-TA2IV=\$42E! \ TA2 interrupt vector
-
-CAPTIO0CTL=\$43E! \ Capacitive Touch IO 0 control
-
-TA3CTL=\$440! \ TA3 control
-TA3CCTL0=\$442! \ Capture/compare control 0
-TA3CCTL1=\$444! \ Capture/compare control 1
-TA3R=\$450! \ TA3 counter register
-TA3CCR0=\$452! \ Capture/compare register 0
-TA3CCR1=\$454! \ Capture/compare register 1
-TA3EX0=\$460! \ TA3 expansion register 0
-TA3IV=\$46E! \ TA3 interrupt vector
-
-CAPTIO1CTL=\$47E! \ Capacitive Touch IO 1 control
-
-! \ RTC_C
-RTCCTL0_L=\$4A0! \ RTCCTL0_L
-RTCCTL0_H=\$4A1! \ RTCCTL0_H
-RTCCTL1=\$4A2! \ RTCCTL1
-RTCCTL3=\$4A3! \ RTCCTL3
-RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
-RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
-RTCPS=\$4AC! \ RTC prescaler
-RT0PS=\$4AC! \ RTC prescaler 0
-RT1PS=\$4AD! \ RTC prescaler 1
-RTCIV=\$4AE! \ RTC interrupt vector word
-RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
-RTCCNT1=\$4B0! \ Real-Time Counter 1
-RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
-RTCCNT2=\$4B1! \ Real-Time Counter 2
-RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
-RTCCNT3=\$4B2! \ Real-Time Counter 3
-RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
-RTCCNT4=\$4B3! \ Real-Time Counter 4
-RTCDAY=\$4B4! \ RTC days
-RTCMON=\$4B5! \ RTC month
-RTCYEAR=\$4B6!
-RTCYEARL=\$4B6! \ RTC year low
-RTCYEARH=\$4B7! \ RTC year high
-RTCAMIN=\$4B8! \ RTC alarm minutes
-RTCAHOUR=\$4B9! \ RTC alarm hours
-RTCADOW=\$4BA! \ RTC alarm day of week
-RTCADAY=\$4BB! \ RTC alarm days
-BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
-BCD2BIN=\$4BE! \ BCD-to-binary conversion register
-
-RTCHOLD=\$40!
-RTCRDY=\$10!
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-DMAIFG=8!
-
-DMACTL0=\$500! \ DMA module control 0
-DMACTL1=\$502! \ DMA module control 1
-DMACTL2=\$504! \ DMA module control 2
-DMACTL3=\$506! \ DMA module control 3
-DMACTL4=\$508! \ DMA module control 4
-DMAIV=\$50A! \ DMA interrupt vector
-
-DMA0CTL=\$510! \ DMA channel 0 control
-DMA0SAL=\$512! \ DMA channel 0 source address low
-DMA0SAH=\$514! \ DMA channel 0 source address high
-DMA0DAL=\$516! \ DMA channel 0 destination address low
-DMA0DAH=\$518! \ DMA channel 0 destination address high
-DMA0SZ=\$51A! \ DMA channel 0 transfer size
-
-DMA1CTL=\$520! \ DMA channel 1 control
-DMA1SAL=\$522! \ DMA channel 1 source address low
-DMA1SAH=\$524! \ DMA channel 1 source address high
-DMA1DAL=\$526! \ DMA channel 1 destination address low
-DMA1DAH=\$528! \ DMA channel 1 destination address high
-DMA1SZ=\$52A! \ DMA channel 1 transfer size
-
-DMA2CTL=\$530! \ DMA channel 2 control
-DMA2SAL=\$532! \ DMA channel 2 source address low
-DMA2SAH=\$534! \ DMA channel 2 source address high
-DMA2DAL=\$536! \ DMA channel 2 destination address low
-DMA2DAH=\$538! \ DMA channel 2 destination address high
-DMA2SZ=\$53A! \ DMA channel 2 transfer size
-
-DMA3CTL=\$540! \ DMA channel 3 control
-DMA3SAL=\$542! \ DMA channel 3 source address low
-DMA3SAH=\$544! \ DMA channel 3 source address high
-DMA3DAL=\$546! \ DMA channel 3 destination address low
-DMA3DAH=\$548! \ DMA channel 3 destination address high
-DMA3SZ=\$54A! \ DMA channel 3 transfer size
-
-DMA4CTL=\$550! \ DMA channel 4 control
-DMA4SAL=\$552! \ DMA channel 4 source address low
-DMA4SAH=\$554! \ DMA channel 4 source address high
-DMA4DAL=\$556! \ DMA channel 4 destination address low
-DMA4DAH=\$558! \ DMA channel 4 destination address high
-DMA4SZ=\$55A! \ DMA channel 4 transfer size
-
-DMA5CTL=\$560! \ DMA channel 5 control
-DMA5SAL=\$562! \ DMA channel 5 source address low
-DMA5SAH=\$564! \ DMA channel 5 source address high
-DMA5DAL=\$566! \ DMA channel 5 destination address low
-DMA5DAH=\$568! \ DMA channel 5 destination address high
-DMA5SZ=\$56A! \ DMA channel 5 transfer size
-
-MPUCTL0=\$5A0! \ MPU control 0
-MPUCTL1=\$5A2! \ MPU control 1
-MPUSEGB2=\$5A4! \ MPU Segmentation Border2
-MPUSEGB1=\$5A6! \ MPU Segmentation Border1
-MPUSAM=\$5A8! \ MPU access management
-MPUIPC0=\$5AA! \ MPU IP control 0
-MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2
-MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1
-
-UCA0CTLW0=\$5C0! \ eUSCI_A control word 0
-UCA0CTLW1=\$5C2! \ eUSCI_A control word 1
-UCA0BRW=\$5C6!
-UCA0BR0=\$5C6! \ eUSCI_A baud rate 0
-UCA0BR1=\$5C7! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$5C8! \ eUSCI_A modulation control
-UCA0STAT=\$5CA! \ eUSCI_A status
-UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer
-UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$5D0! \ eUSCI_A LIN control
-UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-UCA0IE=\$5DA! \ eUSCI_A interrupt enable
-UCA0IFG=\$5DC! \ eUSCI_A interrupt flags
-UCA0IV=\$5DE! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$5E0! \ eUSCI_A control word 0
-UCA1CTLW1=\$5E2! \ eUSCI_A control word 1
-UCA1BRW=\$5E6!
-UCA1BR0=\$5E6! \ eUSCI_A baud rate 0
-UCA1BR1=\$5E7! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$5E8! \ eUSCI_A modulation control
-UCA1STAT=\$5EA! \ eUSCI_A status
-UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer
-UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$5F0! \ eUSCI_A LIN control
-UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control
-UCA1IE=\$5FA! \ eUSCI_A interrupt enable
-UCA1IFG=\$5FC! \ eUSCI_A interrupt flags
-UCA1IV=\$5FE! \ eUSCI_A interrupt vector word
-
-UCA2CTLW0=\$600! \ eUSCI_A control word 0
-UCA2CTLW1=\$602! \ eUSCI_A control word 1
-UCA2BRW=\$606!
-UCA2BR0=\$606! \ eUSCI_A baud rate 0
-UCA2BR1=\$607! \ eUSCI_A baud rate 1
-UCA2MCTLW=\$608! \ eUSCI_A modulation control
-UCA2STAT=\$60A! \ eUSCI_A status
-UCA2RXBUF=\$60C! \ eUSCI_A receive buffer
-UCA2TXBUF=\$60E! \ eUSCI_A transmit buffer
-UCA2ABCTL=\$610! \ eUSCI_A LIN control
-UCA2IRTCTL=\$612! \ eUSCI_A IrDA transmit control
-UCA2IRRCTL=\$613! \ eUSCI_A IrDA receive control
-UCA2IE=\$61A! \ eUSCI_A interrupt enable
-UCA2IFG=\$61C! \ eUSCI_A interrupt flags
-UCA2IV=\$61E! \ eUSCI_A interrupt vector word
-
-UCA3CTLW0=\$620! \ eUSCI_A control word 0
-UCA3CTLW1=\$622! \ eUSCI_A control word 1
-UCA3BRW=\$626!
-UCA3BR0=\$626! \ eUSCI_A baud rate 0
-UCA3BR1=\$627! \ eUSCI_A baud rate 1
-UCA3MCTLW=\$628! \ eUSCI_A modulation control
-UCA3STAT=\$62A! \ eUSCI_A status
-UCA3RXBUF=\$62C! \ eUSCI_A receive buffer
-UCA3TXBUF=\$62E! \ eUSCI_A transmit buffer
-UCA3ABCTL=\$630! \ eUSCI_A LIN control
-UCA3IRTCTL=\$632! \ eUSCI_A IrDA transmit control
-UCA3IRRCTL=\$633! \ eUSCI_A IrDA receive control
-UCA3IE=\$63A! \ eUSCI_A interrupt enable
-UCA3IFG=\$63C! \ eUSCI_A interrupt flags
-UCA3IV=\$63E! \ eUSCI_A interrupt vector word
-
-UCB0CTLW0=\$640! \ eUSCI_B control word 0
-UCB0CTLW1=\$642! \ eUSCI_B control word 1
-UCB0BRW=\$646!
-UCB0BR0=\$646! \ eUSCI_B bit rate 0
-UCB0BR1=\$647! \ eUSCI_B bit rate 1
-UCB0STATW=\$648! \ eUSCI_B status word
-UCBCNT0=\$649! \ eUSCI_B hardware count
-UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$64C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$65C! \ eUSCI_B received address
-UCB0ADDMASK=\$65E! \ eUSCI_B address mask
-UCB0I2CSA=\$660! \ eUSCI I2C slave address
-UCB0IE=\$66A! \ eUSCI interrupt enable
-UCB0IFG=\$66C! \ eUSCI interrupt flags
-UCB0IV=\$66E! \ eUSCI interrupt vector word
-
-UCB1CTLW0=\$680! \ eUSCI_B control word 0
-UCB1CTLW1=\$682! \ eUSCI_B control word 1
-UCB1BRW=\$686!
-UCB1BR0=\$686! \ eUSCI_B bit rate 0
-UCB1BR1=\$687! \ eUSCI_B bit rate 1
-UCB1STATW=\$688! \ eUSCI_B status word
-UCB1NT0=\$689! \ eUSCI_B hardware count
-UCB1TBCNT=\$68A! \ eUSCI_B byte counter threshold
-UCB1RXBUF=\$68C! \ eUSCI_B receive buffer
-UCB1TXBUF=\$68E! \ eUSCI_B transmit buffer
-UCB1I2COA0=\$694! \ eUSCI_B I2C own address 0
-UCB1I2COA1=\$696! \ eUSCI_B I2C own address 1
-UCB1I2COA2=\$698! \ eUSCI_B I2C own address 2
-UCB1I2COA3=\$69A! \ eUSCI_B I2C own address 3
-UCB1ADDRX=\$69C! \ eUSCI_B received address
-UCB1ADDMASK=\$69E! \ eUSCI_B address mask
-UCB1I2CSA=\$6A0! \ eUSCI I2C slave address
-UCB1IE=\$6AA! \ eUSCI interrupt enable
-UCB1IFG=\$6AC! \ eUSCI interrupt flags
-UCB1IV=\$6AE! \ eUSCI interrupt vector word
-
-UCB2CTLW0=\$6C0! \ eUSCI_B control word 0
-UCB2CTLW1=\$6C2! \ eUSCI_B control word 1
-UCB2BRW=\$6C6!
-UCB2BR0=\$6C6! \ eUSCI_B bit rate 0
-UCB2BR1=\$6C7! \ eUSCI_B bit rate 1
-UCB2STATW=\$6C8! \ eUSCI_B status word
-UCB2NT0=\$6C9! \ eUSCI_B hardware count
-UCB2TBCNT=\$6CA! \ eUSCI_B byte counter threshold
-UCB2RXBUF=\$6CC! \ eUSCI_B receive buffer
-UCB2TXBUF=\$6CE! \ eUSCI_B transmit buffer
-UCB2I2COA0=\$6D4! \ eUSCI_B I2C own address 0
-UCB2I2COA1=\$6D6! \ eUSCI_B I2C own address 1
-UCB2I2COA2=\$6D8! \ eUSCI_B I2C own address 2
-UCB2I2COA3=\$6DA! \ eUSCI_B I2C own address 3
-UCB2ADDRX=\$6DC! \ eUSCI_B received address
-UCB2ADDMASK=\$6DE! \ eUSCI_B address mask
-UCB2I2CSA=\$6E0! \ eUSCI I2C slave address
-UCB2IE=\$6EA! \ eUSCI interrupt enable
-UCB2IFG=\$6EC! \ eUSCI interrupt flags
-UCB2IV=\$6EE! \ eUSCI interrupt vector word
-
-UCB3CTLW0=\$700! \ eUSCI_B control word 0
-UCB3CTLW1=\$702! \ eUSCI_B control word 1
-UCB3BRW=\$706!
-UCB3BR0=\$706! \ eUSCI_B bit rate 0
-UCB3BR1=\$707! \ eUSCI_B bit rate 1
-UCB3STATW=\$708! \ eUSCI_B status word
-UCB3NT0=\$709! \ eUSCI_B hardware count
-UCB3TBCNT=\$70A! \ eUSCI_B byte counter threshold
-UCB3RXBUF=\$70C! \ eUSCI_B receive buffer
-UCB3TXBUF=\$70E! \ eUSCI_B transmit buffer
-UCB3I2COA0=\$714! \ eUSCI_B I2C own address 0
-UCB3I2COA1=\$716! \ eUSCI_B I2C own address 1
-UCB3I2COA2=\$718! \ eUSCI_B I2C own address 2
-UCB3I2COA3=\$71A! \ eUSCI_B I2C own address 3
-UCB3ADDRX=\$71C! \ eUSCI_B received address
-UCB3ADDMASK=\$71E! \ eUSCI_B address mask
-UCB3I2CSA=\$720! \ eUSCI I2C slave address
-UCB3IE=\$72A! \ eUSCI interrupt enable
-UCB3IFG=\$72C! \ eUSCI interrupt flags
-UCB3IV=\$72E! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-TA4CTL=\$7C0! \ TA4 control
-TA4CCTL0=\$7C2! \ Capture/compare control 0
-TA4CCTL1=\$7C4! \ Capture/compare control 1
-TA4R=\$7D0! \ TA4 counter register
-TA4CCR0=\$7D2! \ Capture/compare register 0
-TA4CCR1=\$7D4! \ Capture/compare register 1
-TA4EX0=\$7E0! \ TA4 expansion register 0
-TA4IV=\$7EE! \ TA4 interrupt vector
-
-
-ADC12CTL0=\$800! \ ADC12_B Control 0
-ADC12CTL1=\$802! \ ADC12_B Control 1
-ADC12CTL2=\$804! \ ADC12_B Control 2
-ADC12CTL3=\$806! \ ADC12_B Control 3
-ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register
-ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register
-ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0
-ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1
-ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2
-ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0
-ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1
-ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2
-ADC12IV=\$818! \ ADC12_B Interrupt Vector
-ADC12MCTL0=\$820! \ ADC12_B Memory Control 0
-ADC12MCTL1=\$822! \ ADC12_B Memory Control 1
-ADC12MCTL2=\$824! \ ADC12_B Memory Control 2
-ADC12MCTL3=\$826! \ ADC12_B Memory Control 3
-ADC12MCTL4=\$828! \ ADC12_B Memory Control 4
-ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5
-ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6
-ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7
-ADC12MCTL8=\$830! \ ADC12_B Memory Control 8
-ADC12MCTL9=\$832! \ ADC12_B Memory Control 9
-ADC12MCTL10=\$834! \ ADC12_B Memory Control 10
-ADC12MCTL11=\$836! \ ADC12_B Memory Control 11
-ADC12MCTL12=\$838! \ ADC12_B Memory Control 12
-ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13
-ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14
-ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15
-ADC12MCTL16=\$840! \ ADC12_B Memory Control 16
-ADC12MCTL17=\$842! \ ADC12_B Memory Control 17
-ADC12MCTL18=\$844! \ ADC12_B Memory Control 18
-ADC12MCTL19=\$846! \ ADC12_B Memory Control 19
-ADC12MCTL20=\$848! \ ADC12_B Memory Control 20
-ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21
-ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22
-ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23
-ADC12MCTL24=\$850! \ ADC12_B Memory Control 24
-ADC12MCTL25=\$852! \ ADC12_B Memory Control 25
-ADC12MCTL26=\$854! \ ADC12_B Memory Control 26
-ADC12MCTL27=\$856! \ ADC12_B Memory Control 27
-ADC12MCTL28=\$858! \ ADC12_B Memory Control 28
-ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29
-ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30
-ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31
-ADC12MEM0=\$860! \ ADC12_B Memory 0
-ADC12MEM1=\$862! \ ADC12_B Memory 1
-ADC12MEM2=\$864! \ ADC12_B Memory 2
-ADC12MEM3=\$866! \ ADC12_B Memory 3
-ADC12MEM4=\$868! \ ADC12_B Memory 4
-ADC12MEM5=\$86A! \ ADC12_B Memory 5
-ADC12MEM6=\$86C! \ ADC12_B Memory 6
-ADC12MEM7=\$86E! \ ADC12_B Memory 7
-ADC12MEM8=\$870! \ ADC12_B Memory 8
-ADC12MEM9=\$872! \ ADC12_B Memory 9
-ADC12MEM10=\$874! \ ADC12_B Memory 10
-ADC12MEM11=\$876! \ ADC12_B Memory 11
-ADC12MEM12=\$878! \ ADC12_B Memory 12
-ADC12MEM13=\$87A! \ ADC12_B Memory 13
-ADC12MEM14=\$87C! \ ADC12_B Memory 14
-ADC12MEM15=\$87E! \ ADC12_B Memory 15
-ADC12MEM16=\$880! \ ADC12_B Memory 16
-ADC12MEM17=\$882! \ ADC12_B Memory 17
-ADC12MEM18=\$884! \ ADC12_B Memory 18
-ADC12MEM19=\$886! \ ADC12_B Memory 19
-ADC12MEM20=\$888! \ ADC12_B Memory 20
-ADC12MEM21=\$88A! \ ADC12_B Memory 21
-ADC12MEM22=\$88C! \ ADC12_B Memory 22
-ADC12MEM23=\$88E! \ ADC12_B Memory 23
-ADC12MEM24=\$890! \ ADC12_B Memory 24
-ADC12MEM25=\$892! \ ADC12_B Memory 25
-ADC12MEM26=\$894! \ ADC12_B Memory 26
-ADC12MEM27=\$896! \ ADC12_B Memory 27
-ADC12MEM28=\$898! \ ADC12_B Memory 28
-ADC12MEM29=\$89A! \ ADC12_B Memory 29
-ADC12MEM30=\$89C! \ ADC12_B Memory 30
-ADC12MEM31=\$89E! \ ADC12_B Memory 31
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-CDIFG=1!
-CDIIFG=2!
-
-CDCTL0=\$8C0! \ Comparator_E control register 0
-CDCTL1=\$8C2! \ Comparator_E control register 1
-CDCTL2=\$8C4! \ Comparator_E control register 2
-CDCTL3=\$8C6! \ Comparator_E control register 3
-CDINT=\$8CC! \ Comparator_E interrupt register
-CDIV=\$8CE! \ Comparator_E interrupt vector word
-
-CRC32DIW0=\$980! \ CRC32 data input
-CRC32DIRBW0=\$986! \ CRC32 data input reverse
-CRC32INIRESW0=\$988! \ CRC32 initialization and result word 0
-CRC32INIRESW1=\$98A! \ CRC32 initialization and result word 1
-CRC32RESRW1=\$98! \ CRC32 result reverse word 1
-CRC32RESRW1=\$98E! \ CRC32 result reverse word 0
-CRC16DIW0=\$990! \ CRC16 data input
-CRC16DIRBW0=\$996! \ CRC16 data input reverse
-CRC16INIRESW0=\$998! \ CRC16 initialization and result word 0
-CRC16RESRW1=\$99E! \ CRC16 result reverse word 0
-
-
-AESACTL0=\$9C0! \ AES accelerator control register 0
-AESASTAT=\$9C4! \ AES accelerator status register
-AESAKEY=\$9C6! \ AES accelerator key register
-AESADIN=\$9C8! \ AES accelerator data in register
-AESADOUT=\$9CA! \ AES accelerator data out register
-AESAXDIN=\$9CC! \ AES accelerator XORed data in register
-AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger)
-
-LEASCCAP=\$A80! \ LEASC capability
-LEASCCNF0=\$A84! \ Configuration 0
-LEASCCNF1=\$A88! \ Configuration 1
-LEASCCNF2=\$A8C! \ Configuration 2
-LEASCMB=\$A90! \ Memory bottom
-LEASCMT=\$A94! \ Memory top
-LEASCCMA=\$A98! \ Code memory access
-LEASCCMCTL=\$A9C! \ Code memory control
-LEASSCMDSTAT=\$AA8! \ LEA command status
-LEASCS1STAT=\$AAC! \ LEA source 1 status
-LEASCS0STAT=\$AB0! \ LEA source 0 status
-LEASCDSTSTAT=\$AB4! \ LEA result status
-LEASCPMCTL=\$AC0! \ Control
-LEASCPMDST=\$AC4! \ Result
-LEASCPMS1=\$AC8! \ Source 1
-LEASCPMS0=\$ACC! \ Source 0
-LEASCPMCB=\$AD0! \ Command buffer
-LEASCIFGSET=\$AF0! \ Interrupt flag and set
-LEASCIE=\$AF4! \ Interrupt enable
-LEASCIFG=\$AF8! \ Interrupt flag and clr
-LEASCIV=\$AFC! \ Interrupt vector
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430fr5994.pat
+
+; ----------------------------------------------
+; MSP430FR5994 MEMORY MAP
+; ----------------------------------------------
+; 000A-001F = tiny RAM
+; 0020-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
+; 1800-19FF = FRAM INFO 512 B
+; 1A00-1AFF = FRAM TLV device descriptor info (256 B)
+; 1C00-2BFF = RAM (4KB)
+; 2C00-3BFF = sharedRAM (4kB)
+; 4000-FF7F = FRAM MAIN
+; FF80-FFFF = FRAM interrupt vectors and signatures (FRAM)
+; 10000-
+; ----------------------------------------------
+; PAGESIZE .equ 512 ; MPU unit
+
+
+; ============================================
+; TINY RAM
+; ============================================
+TinyRAM_ORG=\$0A;
+TinyRAM_LEN=\$16;
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$1C00;
+RAM_LEN=\$1000;
+SharedRAM_ORG=\$2C00;
+SharedRAM_LEN=\$1000;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ----------------------------------------------
+; FastForth RAM memory map (>= 1k):
+; ----------------------------------------------
+LEAVEPTR=\$1C00; Leave-stack pointer, init by QUIT
+LSATCK=\$1C00; leave stack, grow up
+PSTACK=\$1C80; parameter stack, grow down
+RSTACK=\$1CE0; Return stack, grow down
+;
+PAD_I2CADR=\$1CE0; RX I2C address
+PAD_I2CCNT=\$1CE2; count max
+PAD_ORG=\$1CE4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$1D38; TX I2C address
+TIB_I2CCNT=\$1D3A; count of bytes
+TIB_ORG=\$1D3C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$1D90; base address for HOLDS
+HOLD_BASE=\$1DB2; BASE HOLD area, grow down
+;
+HP=\$1DB2; HOLD ptr
+STATEADR=\$1DB4; Interpreter state
+BASEADR=\$1DB6; base
+CAPS=\$1DB8; CAPS ON/OFF
+SOURCE_LEN=\$1DBA; len of input stream
+SOURCE_ORG=\$1DBC; adr of input stream
+TOIN=\$1DBE; >IN
+;
+DP=\$1DC0; dictionary ptr
+LASTVOC=\$1DC2; keep VOC-LINK
+CURRENT=\$1DC4; CURRENT dictionnary ptr
+CONTEXT=\$1DC6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$1DD8;
+LAST_THREAD=\$1DDA;
+LAST_CFA=\$1DDC;
+LAST_PSP=\$1DDE;
+ASMBW1=\$1DE0; 3 backward labels
+ASMBW2=\$1DE2;
+ASMBW3=\$1DE4;
+ASMFW1=\$1DE6; 3 forward labels
+ASMFW2=\$1DE8;
+ASMFW3=\$1DEA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$1DFC;
+SD_BUF_I2CNT=\$1DFE;
+SD_BUF=\$1E00; \ SD_Card buffer
+BUFEND=\$2000;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2002;
+BS_FirstSectorL=\$2004;
+BS_FirstSectorH=\$2006;
+OrgFAT1=\$2008;
+FATSize=\$200A;
+OrgFAT2=\$200C;
+OrgRootDir=\$200E;
+OrgClusters=\$2010; Sector of Cluster 0
+SecPerClus=\$2012;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2014; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2014; CRC:ll word access
+SD_CMD_FRM1=\$2015; ll byte access
+SD_CMD_FRM2=\$2016; LL:hh word access
+SD_CMD_FRM3=\$2017; hh byte access
+SD_CMD_FRM4=\$2018; HH:CMD word access
+SD_CMD_FRM5=\$2019; CMD byte access
+SectorL=\$201A; 2 words
+SectorH=\$201C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$201E;
+BufferLen=\$2020;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2022; 16 bits wide (FAT16)
+ClusterH=\$2024; 16 bits wide (FAT16)
+LastFATsector=\$2026; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2028; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$202A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$202C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$202E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2030;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2032; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2034;
+EndOfPath=\$2036;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2038;
+HandleEnd=\$2118;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2118;
+SDIB_I2CCNT=\$211A;
+SDIB_ORG=\$211C;
+SDIB_LEN=\$54;
+
+SD_END=\$2170;
+SD_LEN=\$16E;
+
+; ============================================
+; FRAM MAIN
+; ============================================
+MAIN_ORG=\$4000; Code space start
+MAIN_LEN=\$40000; 240 kb FRAM
+; ----------------------------------------------
+\#LIT=\#\$4000; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$4014; asm CODE run time of QUOTE
+\#MUSMOD=\#\$4028; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$403A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$4042; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$406C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$406E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$407E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$408A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$4096; CODE compiled by IF UNTIL
+\#BRAN=\#\$409C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$409E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$40A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$40AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$40BA;
+\#ABORT_TERM=\#\$4100; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$4172; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$415C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for defined addresses from FORTH definitions
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR5994
+; ----------------------------------------------
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0, enable JTAG/SBW
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits max
+IPE_SIG_VALID=\$FF88; one word
+IPE_STR_PTR_SRC=\$FF8A; one word
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\0FFB4; FFB4-FFFF
+VECT_LEN=\$4C;
+
+
+LEA_VEC=\$FFB4;
+P8_VEC=\$FFB6;
+P7_VEC=\$FFB8;
+EUSCI_B3_VEC=\$FFBA;
+EUSCI_B2_VEC=\$FFBC;
+EUSCI_B1_VEC=\$FFBE;
+EUSCI_A3_VEC=\$FFC0;
+EUSCI_A2_VEC=\$FFC2;
+P6_VEC=\$FFC4;
+P5_VEC=\$FFC6;
+TA4_X_VEC=\$FFC8;
+TA4_0_VEC=\$FFCA;
+AES_VEC=\$FFCC;
+RTC_C_VEC=\$FFCE;
+P4_VEC=\$FFD0;
+P3_VEC=\$FFD2;
+TA3_X_VEC=\$FFD4;
+TA3_0_VEC=\$FFD6;
+P2_VEC=\$FFD8;
+TA2_X_VEC=\$FFDA;
+TA2_0_VEC=\$FFDC;
+P1_VEC=\$FFDE;
+TA1_X_VEC=\$FFE0;
+TA1_0_VEC=\$FFE2;
+DMA_VEC=\$FFE4;
+EUSCI_A1_VEC=\$FFE6;
+TA0_X_VEC=\$FFE8;
+TA0_0_VEC=\$FFEA;
+ADC12_B_VEC=\$FFEC;
+EUSCI_B0_VEC=\$FFEE;
+EUSCI_A0_VEC=\$FFF0;
+WDT_VEC=\$FFF2;
+TB0_X_VEC=\$FFF4;
+TB0_0_VEC=\$FFF6;
+COMP_E_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+FRCTLCTL0=\$140; \ FRAM control 0
+GCCTL0=\$144; \ General control 0
+GCCTL1=\$146; \ General control 1
+
+CRC16DI=\$150; \ CRC data input
+CRCDIRB=\$152; \ CRC data input reverse byte
+CRCINIRES=\$154; \ CRC initialization and result
+CRCRESR=\$156; \ CRC result reverse byte
+
+
+RCCTL0=\$158; \ RAM controller control 0
+
+
+WDTCTL=\$15C; \ WDT control register
+
+CSCTL0=\$160; \ CS control 0
+CSCTL1=\$162; \ CS control 1
+CSCTL2=\$164; \ CS control 2
+CSCTL3=\$166; \ CS control 3
+CSCTL4=\$168; \ CS control 4
+CSCTL5=\$16A; \ CS control 5
+CSCTL6=\$16C; \ CS control 6
+
+SYSCTL=\$180; \ System control
+SYSJMBC=\$186; \ JTAG mailbox control
+SYSJMBI0=\$188; \ JTAG mailbox input 0
+SYSJMBI1=\$18A; \ JTAG mailbox input 1
+SYSJMBO0=\$18C; \ JTAG mailbox output 0
+SYSJMBO1=\$18E; \ JTAG mailbox output 1
+SYSUNIV=\$19A; \ User NMI vector generator
+SYSSNIV=\$19C; \ System NMI vector generator
+SYSRSTIV=\$19E; \ Reset vector generator
+
+REFCTL=\$1B0; \ Shared reference control
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PASELC=\$216;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1SELC=\$216;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2SELC=\$217;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+PBIN=\$220;
+PBOUT=\$222;
+PBDIR=\$224;
+PBREN=\$226;
+PBSEL0=\$22A;
+PBSEL1=\$22C;
+PBSELC=\$236;
+PBIES=\$238;
+PBIE=\$23A;
+PBIFG=\$23C;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+P3IV=\$22E;
+P3SELC=\$236;
+P3IES=\$238;
+P3IE=\$23A;
+P3IFG=\$23C;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+P4SEL1=\$22D;
+P4SELC=\$237;
+P4IES=\$239;
+P4IE=\$23B;
+P4IFG=\$23D;
+P4IV=\$23E;
+
+PCIN=\$240;
+PCOUT=\$242;
+PCDIR=\$244;
+PCREN=\$246;
+PCSEL0=\$24A;
+PCSEL1=\$24C;
+PCSELC=\$256;
+PCIES=\$258;
+PCIE=\$25A;
+PCIFG=\$25C;
+
+P5IN=\$240;
+P5OUT=\$242;
+P5DIR=\$244;
+P5REN=\$246;
+P5SEL0=\$24A;
+P5SEL1=\$24C;
+P5IV=\$24E;
+P5SELC=\$256;
+P5IES=\$258;
+P5IE=\$25A;
+P5IFG=\$25C;
+
+P6IN=\$241;
+P6OUT=\$243;
+P6DIR=\$245;
+P6REN=\$247;
+P6SEL0=\$24B;
+P6SEL1=\$24D;
+P6SELC=\$257;
+P6IES=\$259;
+P6IE=\$25B;
+P6IFG=\$25D;
+P6IV=\$25E;
+
+PDIN=\$260;
+PDOUT=\$262;
+PDDIR=\$264;
+PDREN=\$266;
+PDSEL0=\$26A;
+PDSEL1=\$26C;
+PDSELC=\$276;
+PDIES=\$278;
+PDIE=\$27A;
+PDIFG=\$27C;
+
+P7IN=\$260;
+P7OUT=\$262;
+P7DIR=\$264;
+P7REN=\$266;
+P7SEL0=\$26A;
+P7SEL1=\$26C;
+P7IV=\$26E;
+P7SELC=\$276;
+P7IES=\$278;
+P7IE=\$27A;
+P7IFG=\$27C;
+
+P8IN=\$261;
+P8OUT=\$263;
+P8DIR=\$265;
+P8REN=\$267;
+P8SEL0=\$26B;
+P8SEL1=\$26D;
+P8SELC=\$277;
+P8IES=\$279;
+P8IE=\$27B;
+P8IFG=\$27D;
+P8IV=\$27E;
+
+PJIN=\$320;
+PJOUT=\$322;
+PJDIR=\$324;
+PJREN=\$326;
+PJSEL0=\$32A;
+PJSEL1=\$32C;
+PJSELC=\$336;
+
+
+TACLR=4;
+TAIFG=1;
+TBCLR=2;
+TBIFG=1;
+CCIFG=1;
+
+TA0CTL=\$340; \ TA0 control
+TA0CCTL0=\$342; \ Capture/compare control 0
+TA0CCTL1=\$344; \ Capture/compare control 1
+TA0CCTL2=\$346; \ Capture/compare control 2
+TA0R=\$350; \ TA0 counter register
+TA0CCR0=\$352; \ Capture/compare register 0
+TA0CCR1=\$354; \ Capture/compare register 1
+TA0CCR2=\$356; \ Capture/compare register 2
+TA0EX0=\$360; \ TA0 expansion register 0
+TA0IV=\$36E; \ TA0 interrupt vector
+
+TA1CTL=\$380; \ TA1 control
+TA1CCTL0=\$382; \ Capture/compare control 0
+TA1CCTL1=\$384; \ Capture/compare control 1
+TA1CCTL2=\$386; \ Capture/compare control 2
+TA1R=\$390; \ TA1 counter register
+TA1CCR0=\$392; \ Capture/compare register 0
+TA1CCR1=\$394; \ Capture/compare register 1
+TA1CCR2=\$396; \ Capture/compare register 2
+TA1EX0=\$3A0; \ TA1 expansion register 0
+TA1IV=\$3AE; \ TA1 interrupt vector
+
+TB0CTL=\$3C0; \ TB0 control
+TB0CCTL0=\$3C2; \ Capture/compare control 0
+TB0CCTL1=\$3C4; \ Capture/compare control 1
+TB0CCTL2=\$3C6; \ Capture/compare control 2
+TB0CCTL3=\$3C8; \ Capture/compare control 3
+TB0CCTL4=\$3CA; \ Capture/compare control 4
+TB0CCTL5=\$3CC; \ Capture/compare control 5
+TB0CCTL6=\$3CE; \ Capture/compare control 6
+TB0R=\$3D0; \ TB0 counter register
+TB0CCR0=\$3D2; \ Capture/compare register 0
+TB0CCR1=\$3D4; \ Capture/compare register 1
+TB0CCR2=\$3D6; \ Capture/compare register 2
+TB0CCR3=\$3D8; \ Capture/compare register 3
+TB0CCR5=\$3DA; \ Capture/compare register 4
+TB0CCR5=\$3DC; \ Capture/compare register 5
+TB0CCR6=\$3DE; \ Capture/compare register 6
+TB0EX0=\$3E0; \ TB0 expansion register 0
+TB0IV=\$3EE; \ TB0 interrupt vector
+
+TA2CTL=\$400; \ TA2 control
+TA2CCTL0=\$402; \ Capture/compare control 0
+TA2CCTL1=\$404; \ Capture/compare control 1
+TA2R=\$410; \ TA2 counter register
+TA2CCR0=\$412; \ Capture/compare register 0
+TA2CCR1=\$414; \ Capture/compare register 1
+TA2EX0=\$420; \ TA2 expansion register 0
+TA2IV=\$42E; \ TA2 interrupt vector
+
+CAPTIO0CTL=\$43E; \ Capacitive Touch IO 0 control
+
+TA3CTL=\$440; \ TA3 control
+TA3CCTL0=\$442; \ Capture/compare control 0
+TA3CCTL1=\$444; \ Capture/compare control 1
+TA3R=\$450; \ TA3 counter register
+TA3CCR0=\$452; \ Capture/compare register 0
+TA3CCR1=\$454; \ Capture/compare register 1
+TA3EX0=\$460; \ TA3 expansion register 0
+TA3IV=\$46E; \ TA3 interrupt vector
+
+CAPTIO1CTL=\$47E; \ Capacitive Touch IO 1 control
+
+; \ RTC_C
+RTCCTL0_L=\$4A0; \ RTCCTL0_L
+RTCCTL0_H=\$4A1; \ RTCCTL0_H
+RTCCTL1=\$4A2; \ RTCCTL1
+RTCCTL3=\$4A3; \ RTCCTL3
+RTCPS0CTL=\$4A8; \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA; \ RTC prescaler 1 control
+RTCPS=\$4AC; \ RTC prescaler
+RT0PS=\$4AC; \ RTC prescaler 0
+RT1PS=\$4AD; \ RTC prescaler 1
+RTCIV=\$4AE; \ RTC interrupt vector word
+RTCSEC=\$4B0; \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCCNT1=\$4B0; \ Real-Time Counter 1
+RTCMIN=\$4B1; \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCCNT2=\$4B1; \ Real-Time Counter 2
+RTCHOUR=\$4B2; \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCCNT3=\$4B2; \ Real-Time Counter 3
+RTCDOW=\$4B3; \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCCNT4=\$4B3; \ Real-Time Counter 4
+RTCDAY=\$4B4; \ RTC days
+RTCMON=\$4B5; \ RTC month
+RTCYEAR=\$4B6;
+RTCYEARL=\$4B6; \ RTC year low
+RTCYEARH=\$4B7; \ RTC year high
+RTCAMIN=\$4B8; \ RTC alarm minutes
+RTCAHOUR=\$4B9; \ RTC alarm hours
+RTCADOW=\$4BA; \ RTC alarm day of week
+RTCADAY=\$4BB; \ RTC alarm days
+BIN2BCD=\$4BC; \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE; \ BCD-to-binary conversion register
+
+RTCHOLD=\$40;
+RTCRDY=\$10;
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+DMAIFG=8;
+
+DMACTL0=\$500; \ DMA module control 0
+DMACTL1=\$502; \ DMA module control 1
+DMACTL2=\$504; \ DMA module control 2
+DMACTL3=\$506; \ DMA module control 3
+DMACTL4=\$508; \ DMA module control 4
+DMAIV=\$50A; \ DMA interrupt vector
+
+DMA0CTL=\$510; \ DMA channel 0 control
+DMA0SAL=\$512; \ DMA channel 0 source address low
+DMA0SAH=\$514; \ DMA channel 0 source address high
+DMA0DAL=\$516; \ DMA channel 0 destination address low
+DMA0DAH=\$518; \ DMA channel 0 destination address high
+DMA0SZ=\$51A; \ DMA channel 0 transfer size
+
+DMA1CTL=\$520; \ DMA channel 1 control
+DMA1SAL=\$522; \ DMA channel 1 source address low
+DMA1SAH=\$524; \ DMA channel 1 source address high
+DMA1DAL=\$526; \ DMA channel 1 destination address low
+DMA1DAH=\$528; \ DMA channel 1 destination address high
+DMA1SZ=\$52A; \ DMA channel 1 transfer size
+
+DMA2CTL=\$530; \ DMA channel 2 control
+DMA2SAL=\$532; \ DMA channel 2 source address low
+DMA2SAH=\$534; \ DMA channel 2 source address high
+DMA2DAL=\$536; \ DMA channel 2 destination address low
+DMA2DAH=\$538; \ DMA channel 2 destination address high
+DMA2SZ=\$53A; \ DMA channel 2 transfer size
+
+DMA3CTL=\$540; \ DMA channel 3 control
+DMA3SAL=\$542; \ DMA channel 3 source address low
+DMA3SAH=\$544; \ DMA channel 3 source address high
+DMA3DAL=\$546; \ DMA channel 3 destination address low
+DMA3DAH=\$548; \ DMA channel 3 destination address high
+DMA3SZ=\$54A; \ DMA channel 3 transfer size
+
+DMA4CTL=\$550; \ DMA channel 4 control
+DMA4SAL=\$552; \ DMA channel 4 source address low
+DMA4SAH=\$554; \ DMA channel 4 source address high
+DMA4DAL=\$556; \ DMA channel 4 destination address low
+DMA4DAH=\$558; \ DMA channel 4 destination address high
+DMA4SZ=\$55A; \ DMA channel 4 transfer size
+
+DMA5CTL=\$560; \ DMA channel 5 control
+DMA5SAL=\$562; \ DMA channel 5 source address low
+DMA5SAH=\$564; \ DMA channel 5 source address high
+DMA5DAL=\$566; \ DMA channel 5 destination address low
+DMA5DAH=\$568; \ DMA channel 5 destination address high
+DMA5SZ=\$56A; \ DMA channel 5 transfer size
+
+MPUCTL0=\$5A0; \ MPU control 0
+MPUCTL1=\$5A2; \ MPU control 1
+MPUSEGB2=\$5A4; \ MPU Segmentation Border2
+MPUSEGB1=\$5A6; \ MPU Segmentation Border1
+MPUSAM=\$5A8; \ MPU access management
+MPUIPC0=\$5AA; \ MPU IP control 0
+MPUIPSEGB2=\$5AC; \ MPU IP Encapsulation Segment Border 2
+MPUIPSEGB1=\$5AE; \ MPU IP Encapsulation Segment Border 1
+
+UCA0CTLW0=\$5C0; \ eUSCI_A control word 0
+UCA0CTLW1=\$5C2; \ eUSCI_A control word 1
+UCA0BRW=\$5C6;
+UCA0BR0=\$5C6; \ eUSCI_A baud rate 0
+UCA0BR1=\$5C7; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$5C8; \ eUSCI_A modulation control
+UCA0STAT=\$5CA; \ eUSCI_A status
+UCA0RXBUF=\$5CC; \ eUSCI_A receive buffer
+UCA0TXBUF=\$5CE; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$5D0; \ eUSCI_A LIN control
+UCA0IRTCTL=\$5D2; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$5D3; \ eUSCI_A IrDA receive control
+UCA0IE=\$5DA; \ eUSCI_A interrupt enable
+UCA0IFG=\$5DC; \ eUSCI_A interrupt flags
+UCA0IV=\$5DE; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$5E0; \ eUSCI_A control word 0
+UCA1CTLW1=\$5E2; \ eUSCI_A control word 1
+UCA1BRW=\$5E6;
+UCA1BR0=\$5E6; \ eUSCI_A baud rate 0
+UCA1BR1=\$5E7; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$5E8; \ eUSCI_A modulation control
+UCA1STAT=\$5EA; \ eUSCI_A status
+UCA1RXBUF=\$5EC; \ eUSCI_A receive buffer
+UCA1TXBUF=\$5EE; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$5F0; \ eUSCI_A LIN control
+UCA1IRTCTL=\$5F2; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$5F3; \ eUSCI_A IrDA receive control
+UCA1IE=\$5FA; \ eUSCI_A interrupt enable
+UCA1IFG=\$5FC; \ eUSCI_A interrupt flags
+UCA1IV=\$5FE; \ eUSCI_A interrupt vector word
+
+UCA2CTLW0=\$600; \ eUSCI_A control word 0
+UCA2CTLW1=\$602; \ eUSCI_A control word 1
+UCA2BRW=\$606;
+UCA2BR0=\$606; \ eUSCI_A baud rate 0
+UCA2BR1=\$607; \ eUSCI_A baud rate 1
+UCA2MCTLW=\$608; \ eUSCI_A modulation control
+UCA2STAT=\$60A; \ eUSCI_A status
+UCA2RXBUF=\$60C; \ eUSCI_A receive buffer
+UCA2TXBUF=\$60E; \ eUSCI_A transmit buffer
+UCA2ABCTL=\$610; \ eUSCI_A LIN control
+UCA2IRTCTL=\$612; \ eUSCI_A IrDA transmit control
+UCA2IRRCTL=\$613; \ eUSCI_A IrDA receive control
+UCA2IE=\$61A; \ eUSCI_A interrupt enable
+UCA2IFG=\$61C; \ eUSCI_A interrupt flags
+UCA2IV=\$61E; \ eUSCI_A interrupt vector word
+
+UCA3CTLW0=\$620; \ eUSCI_A control word 0
+UCA3CTLW1=\$622; \ eUSCI_A control word 1
+UCA3BRW=\$626;
+UCA3BR0=\$626; \ eUSCI_A baud rate 0
+UCA3BR1=\$627; \ eUSCI_A baud rate 1
+UCA3MCTLW=\$628; \ eUSCI_A modulation control
+UCA3STAT=\$62A; \ eUSCI_A status
+UCA3RXBUF=\$62C; \ eUSCI_A receive buffer
+UCA3TXBUF=\$62E; \ eUSCI_A transmit buffer
+UCA3ABCTL=\$630; \ eUSCI_A LIN control
+UCA3IRTCTL=\$632; \ eUSCI_A IrDA transmit control
+UCA3IRRCTL=\$633; \ eUSCI_A IrDA receive control
+UCA3IE=\$63A; \ eUSCI_A interrupt enable
+UCA3IFG=\$63C; \ eUSCI_A interrupt flags
+UCA3IV=\$63E; \ eUSCI_A interrupt vector word
+
+UCB0CTLW0=\$640; \ eUSCI_B control word 0
+UCB0CTLW1=\$642; \ eUSCI_B control word 1
+UCB0BRW=\$646;
+UCB0BR0=\$646; \ eUSCI_B bit rate 0
+UCB0BR1=\$647; \ eUSCI_B bit rate 1
+UCB0STATW=\$648; \ eUSCI_B status word
+UCBCNT0=\$649; \ eUSCI_B hardware count
+UCB0TBCNT=\$64A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$64C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$64E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$654; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$656; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$658; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$65A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$65C; \ eUSCI_B received address
+UCB0ADDMASK=\$65E; \ eUSCI_B address mask
+UCB0I2CSA=\$660; \ eUSCI I2C slave address
+UCB0IE=\$66A; \ eUSCI interrupt enable
+UCB0IFG=\$66C; \ eUSCI interrupt flags
+UCB0IV=\$66E; \ eUSCI interrupt vector word
+
+UCB1CTLW0=\$680; \ eUSCI_B control word 0
+UCB1CTLW1=\$682; \ eUSCI_B control word 1
+UCB1BRW=\$686;
+UCB1BR0=\$686; \ eUSCI_B bit rate 0
+UCB1BR1=\$687; \ eUSCI_B bit rate 1
+UCB1STATW=\$688; \ eUSCI_B status word
+UCB1NT0=\$689; \ eUSCI_B hardware count
+UCB1TBCNT=\$68A; \ eUSCI_B byte counter threshold
+UCB1RXBUF=\$68C; \ eUSCI_B receive buffer
+UCB1TXBUF=\$68E; \ eUSCI_B transmit buffer
+UCB1I2COA0=\$694; \ eUSCI_B I2C own address 0
+UCB1I2COA1=\$696; \ eUSCI_B I2C own address 1
+UCB1I2COA2=\$698; \ eUSCI_B I2C own address 2
+UCB1I2COA3=\$69A; \ eUSCI_B I2C own address 3
+UCB1ADDRX=\$69C; \ eUSCI_B received address
+UCB1ADDMASK=\$69E; \ eUSCI_B address mask
+UCB1I2CSA=\$6A0; \ eUSCI I2C slave address
+UCB1IE=\$6AA; \ eUSCI interrupt enable
+UCB1IFG=\$6AC; \ eUSCI interrupt flags
+UCB1IV=\$6AE; \ eUSCI interrupt vector word
+
+UCB2CTLW0=\$6C0; \ eUSCI_B control word 0
+UCB2CTLW1=\$6C2; \ eUSCI_B control word 1
+UCB2BRW=\$6C6;
+UCB2BR0=\$6C6; \ eUSCI_B bit rate 0
+UCB2BR1=\$6C7; \ eUSCI_B bit rate 1
+UCB2STATW=\$6C8; \ eUSCI_B status word
+UCB2NT0=\$6C9; \ eUSCI_B hardware count
+UCB2TBCNT=\$6CA; \ eUSCI_B byte counter threshold
+UCB2RXBUF=\$6CC; \ eUSCI_B receive buffer
+UCB2TXBUF=\$6CE; \ eUSCI_B transmit buffer
+UCB2I2COA0=\$6D4; \ eUSCI_B I2C own address 0
+UCB2I2COA1=\$6D6; \ eUSCI_B I2C own address 1
+UCB2I2COA2=\$6D8; \ eUSCI_B I2C own address 2
+UCB2I2COA3=\$6DA; \ eUSCI_B I2C own address 3
+UCB2ADDRX=\$6DC; \ eUSCI_B received address
+UCB2ADDMASK=\$6DE; \ eUSCI_B address mask
+UCB2I2CSA=\$6E0; \ eUSCI I2C slave address
+UCB2IE=\$6EA; \ eUSCI interrupt enable
+UCB2IFG=\$6EC; \ eUSCI interrupt flags
+UCB2IV=\$6EE; \ eUSCI interrupt vector word
+
+UCB3CTLW0=\$700; \ eUSCI_B control word 0
+UCB3CTLW1=\$702; \ eUSCI_B control word 1
+UCB3BRW=\$706;
+UCB3BR0=\$706; \ eUSCI_B bit rate 0
+UCB3BR1=\$707; \ eUSCI_B bit rate 1
+UCB3STATW=\$708; \ eUSCI_B status word
+UCB3NT0=\$709; \ eUSCI_B hardware count
+UCB3TBCNT=\$70A; \ eUSCI_B byte counter threshold
+UCB3RXBUF=\$70C; \ eUSCI_B receive buffer
+UCB3TXBUF=\$70E; \ eUSCI_B transmit buffer
+UCB3I2COA0=\$714; \ eUSCI_B I2C own address 0
+UCB3I2COA1=\$716; \ eUSCI_B I2C own address 1
+UCB3I2COA2=\$718; \ eUSCI_B I2C own address 2
+UCB3I2COA3=\$71A; \ eUSCI_B I2C own address 3
+UCB3ADDRX=\$71C; \ eUSCI_B received address
+UCB3ADDMASK=\$71E; \ eUSCI_B address mask
+UCB3I2CSA=\$720; \ eUSCI I2C slave address
+UCB3IE=\$72A; \ eUSCI interrupt enable
+UCB3IFG=\$72C; \ eUSCI interrupt flags
+UCB3IV=\$72E; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+TA4CTL=\$7C0; \ TA4 control
+TA4CCTL0=\$7C2; \ Capture/compare control 0
+TA4CCTL1=\$7C4; \ Capture/compare control 1
+TA4R=\$7D0; \ TA4 counter register
+TA4CCR0=\$7D2; \ Capture/compare register 0
+TA4CCR1=\$7D4; \ Capture/compare register 1
+TA4EX0=\$7E0; \ TA4 expansion register 0
+TA4IV=\$7EE; \ TA4 interrupt vector
+
+
+ADC12CTL0=\$800; \ ADC12_B Control 0
+ADC12CTL1=\$802; \ ADC12_B Control 1
+ADC12CTL2=\$804; \ ADC12_B Control 2
+ADC12CTL3=\$806; \ ADC12_B Control 3
+ADC12LO=\$808; \ ADC12_B Window Comparator Low Threshold Register
+ADC12HI=\$80A; \ ADC12_B Window Comparator High Threshold Register
+ADC12IFGR0=\$80C; \ ADC12_B Interrupt Flag Register 0
+ADC12IFGR1=\$80E; \ ADC12_B Interrupt Flag Register 1
+ADC12IFGR2=\$810; \ ADC12_B Interrupt Flag Register 2
+ADC12IER0=\$812; \ ADC12_B Interrupt Enable Register 0
+ADC12IER1=\$814; \ ADC12_B Interrupt Enable Register 1
+ADC12IER2=\$816; \ ADC12_B Interrupt Enable Register 2
+ADC12IV=\$818; \ ADC12_B Interrupt Vector
+ADC12MCTL0=\$820; \ ADC12_B Memory Control 0
+ADC12MCTL1=\$822; \ ADC12_B Memory Control 1
+ADC12MCTL2=\$824; \ ADC12_B Memory Control 2
+ADC12MCTL3=\$826; \ ADC12_B Memory Control 3
+ADC12MCTL4=\$828; \ ADC12_B Memory Control 4
+ADC12MCTL5=\$82A; \ ADC12_B Memory Control 5
+ADC12MCTL6=\$82C; \ ADC12_B Memory Control 6
+ADC12MCTL7=\$82E; \ ADC12_B Memory Control 7
+ADC12MCTL8=\$830; \ ADC12_B Memory Control 8
+ADC12MCTL9=\$832; \ ADC12_B Memory Control 9
+ADC12MCTL10=\$834; \ ADC12_B Memory Control 10
+ADC12MCTL11=\$836; \ ADC12_B Memory Control 11
+ADC12MCTL12=\$838; \ ADC12_B Memory Control 12
+ADC12MCTL13=\$83A; \ ADC12_B Memory Control 13
+ADC12MCTL14=\$83C; \ ADC12_B Memory Control 14
+ADC12MCTL15=\$83E; \ ADC12_B Memory Control 15
+ADC12MCTL16=\$840; \ ADC12_B Memory Control 16
+ADC12MCTL17=\$842; \ ADC12_B Memory Control 17
+ADC12MCTL18=\$844; \ ADC12_B Memory Control 18
+ADC12MCTL19=\$846; \ ADC12_B Memory Control 19
+ADC12MCTL20=\$848; \ ADC12_B Memory Control 20
+ADC12MCTL21=\$84A; \ ADC12_B Memory Control 21
+ADC12MCTL22=\$84C; \ ADC12_B Memory Control 22
+ADC12MCTL23=\$84E; \ ADC12_B Memory Control 23
+ADC12MCTL24=\$850; \ ADC12_B Memory Control 24
+ADC12MCTL25=\$852; \ ADC12_B Memory Control 25
+ADC12MCTL26=\$854; \ ADC12_B Memory Control 26
+ADC12MCTL27=\$856; \ ADC12_B Memory Control 27
+ADC12MCTL28=\$858; \ ADC12_B Memory Control 28
+ADC12MCTL29=\$85A; \ ADC12_B Memory Control 29
+ADC12MCTL30=\$85C; \ ADC12_B Memory Control 30
+ADC12MCTL31=\$85E; \ ADC12_B Memory Control 31
+ADC12MEM0=\$860; \ ADC12_B Memory 0
+ADC12MEM1=\$862; \ ADC12_B Memory 1
+ADC12MEM2=\$864; \ ADC12_B Memory 2
+ADC12MEM3=\$866; \ ADC12_B Memory 3
+ADC12MEM4=\$868; \ ADC12_B Memory 4
+ADC12MEM5=\$86A; \ ADC12_B Memory 5
+ADC12MEM6=\$86C; \ ADC12_B Memory 6
+ADC12MEM7=\$86E; \ ADC12_B Memory 7
+ADC12MEM8=\$870; \ ADC12_B Memory 8
+ADC12MEM9=\$872; \ ADC12_B Memory 9
+ADC12MEM10=\$874; \ ADC12_B Memory 10
+ADC12MEM11=\$876; \ ADC12_B Memory 11
+ADC12MEM12=\$878; \ ADC12_B Memory 12
+ADC12MEM13=\$87A; \ ADC12_B Memory 13
+ADC12MEM14=\$87C; \ ADC12_B Memory 14
+ADC12MEM15=\$87E; \ ADC12_B Memory 15
+ADC12MEM16=\$880; \ ADC12_B Memory 16
+ADC12MEM17=\$882; \ ADC12_B Memory 17
+ADC12MEM18=\$884; \ ADC12_B Memory 18
+ADC12MEM19=\$886; \ ADC12_B Memory 19
+ADC12MEM20=\$888; \ ADC12_B Memory 20
+ADC12MEM21=\$88A; \ ADC12_B Memory 21
+ADC12MEM22=\$88C; \ ADC12_B Memory 22
+ADC12MEM23=\$88E; \ ADC12_B Memory 23
+ADC12MEM24=\$890; \ ADC12_B Memory 24
+ADC12MEM25=\$892; \ ADC12_B Memory 25
+ADC12MEM26=\$894; \ ADC12_B Memory 26
+ADC12MEM27=\$896; \ ADC12_B Memory 27
+ADC12MEM28=\$898; \ ADC12_B Memory 28
+ADC12MEM29=\$89A; \ ADC12_B Memory 29
+ADC12MEM30=\$89C; \ ADC12_B Memory 30
+ADC12MEM31=\$89E; \ ADC12_B Memory 31
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CDIFG=1;
+CDIIFG=2;
+
+CDCTL0=\$8C0; \ Comparator_E control register 0
+CDCTL1=\$8C2; \ Comparator_E control register 1
+CDCTL2=\$8C4; \ Comparator_E control register 2
+CDCTL3=\$8C6; \ Comparator_E control register 3
+CDINT=\$8CC; \ Comparator_E interrupt register
+CDIV=\$8CE; \ Comparator_E interrupt vector word
+
+CRC32DIW0=\$980; \ CRC32 data input
+CRC32DIRBW0=\$986; \ CRC32 data input reverse
+CRC32INIRESW0=\$988; \ CRC32 initialization and result word 0
+CRC32INIRESW1=\$98A; \ CRC32 initialization and result word 1
+CRC32RESRW1=\$98; \ CRC32 result reverse word 1
+CRC32RESRW1=\$98E; \ CRC32 result reverse word 0
+CRC16DIW0=\$990; \ CRC16 data input
+CRC16DIRBW0=\$996; \ CRC16 data input reverse
+CRC16INIRESW0=\$998; \ CRC16 initialization and result word 0
+CRC16RESRW1=\$99E; \ CRC16 result reverse word 0
+
+
+AESACTL0=\$9C0; \ AES accelerator control register 0
+AESASTAT=\$9C4; \ AES accelerator status register
+AESAKEY=\$9C6; \ AES accelerator key register
+AESADIN=\$9C8; \ AES accelerator data in register
+AESADOUT=\$9CA; \ AES accelerator data out register
+AESAXDIN=\$9CC; \ AES accelerator XORed data in register
+AESAXIN =\$9CE; \ AES accelerator XORed data in register (no trigger)
+
+LEASCCAP=\$A80; \ LEASC capability
+LEASCCNF0=\$A84; \ Configuration 0
+LEASCCNF1=\$A88; \ Configuration 1
+LEASCCNF2=\$A8C; \ Configuration 2
+LEASCMB=\$A90; \ Memory bottom
+LEASCMT=\$A94; \ Memory top
+LEASCCMA=\$A98; \ Code memory access
+LEASCCMCTL=\$A9C; \ Code memory control
+LEASSCMDSTAT=\$AA8; \ LEA command status
+LEASCS1STAT=\$AAC; \ LEA source 1 status
+LEASCS0STAT=\$AB0; \ LEA source 0 status
+LEASCDSTSTAT=\$AB4; \ LEA result status
+LEASCPMCTL=\$AC0; \ Control
+LEASCPMDST=\$AC4; \ Result
+LEASCPMS1=\$AC8; \ Source 1
+LEASCPMS0=\$ACC; \ Source 0
+LEASCPMCB=\$AD0; \ Command buffer
+LEASCIFGSET=\$AF0; \ Interrupt flag and set
+LEASCIE=\$AF4; \ Interrupt enable
+LEASCIFG=\$AF8; \ Interrupt flag and clr
+LEASCIV=\$AFC; \ Interrupt vector
--- /dev/null
+@set-syntax{C;\;}! replace ! by semicolon
+
+;MSP430fr5xxx.pat
+
+; ============================================
+; RAM
+; ============================================
+;RAM_ORG=\$1C00;
+
+; ----------------------------------------------
+; FastForth RAM memory map (>= 1k):
+; ----------------------------------------------
+LEAVEPTR=\$1C00; Leave-stack pointer, init by QUIT
+LSATCK=\$1C00; leave stack, grow up
+PSTACK=\$1C80; parameter stack, grow down
+RSTACK=\$1CE0; Return stack, grow down
+;
+PAD_I2CADR=\$1CE0; RX I2C address
+PAD_I2CCNT=\$1CE2; count max
+PAD_ORG=\$1CE4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$1D38; TX I2C address
+TIB_I2CCNT=\$1D3A; count of bytes
+TIB_ORG=\$1D3C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$1D90; base address for HOLDS
+HOLD_BASE=\$1DB2; BASE HOLD area, grow down
+;
+HP=\$1DB2; HOLD ptr
+STATEADR=\$1DB4; Interpreter state
+BASEADR=\$1DB6; base
+CAPS=\$1DB8; CAPS ON/OFF
+SOURCE_LEN=\$1DBA; len of input stream
+SOURCE_ORG=\$1DBC; adr of input stream
+TOIN=\$1DBE; >IN
+;
+DP=\$1DC0; dictionary ptr
+LASTVOC=\$1DC2; keep VOC-LINK
+CURRENT=\$1DC4; CURRENT dictionnary ptr
+CONTEXT=\$1DC6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$1DD8;
+LAST_THREAD=\$1DDA;
+LAST_CFA=\$1DDC;
+LAST_PSP=\$1DDE;
+ASMBW1=\$1DE0; 3 backward labels
+ASMBW2=\$1DE2;
+ASMBW3=\$1DE4;
+ASMFW1=\$1DE6; 3 forward labels
+ASMFW2=\$1DE8;
+ASMFW3=\$1DEA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$1DFC;
+SD_BUF_I2CNT=\$1DFE;
+SD_BUF=\$1E00; \ SD_Card buffer
+BUFEND=\$2000;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2002;
+BS_FirstSectorL=\$2004;
+BS_FirstSectorH=\$2006;
+OrgFAT1=\$2008;
+FATSize=\$200A;
+OrgFAT2=\$200C;
+OrgRootDir=\$200E;
+OrgClusters=\$2010; Sector of Cluster 0
+SecPerClus=\$2012;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2014; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2014; CRC:ll word access
+SD_CMD_FRM1=\$2015; ll byte access
+SD_CMD_FRM2=\$2016; LL:hh word access
+SD_CMD_FRM3=\$2017; hh byte access
+SD_CMD_FRM4=\$2018; HH:CMD word access
+SD_CMD_FRM5=\$2019; CMD byte access
+SectorL=\$201A; 2 words
+SectorH=\$201C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$201E;
+BufferLen=\$2020;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2022; 16 bits wide (FAT16)
+ClusterH=\$2024; 16 bits wide (FAT16)
+LastFATsector=\$2026; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2028; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$202A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$202C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$202E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2030;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2032; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2034;
+EndOfPath=\$2036;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2038;
+HandleEnd=\$2118;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2118;
+SDIB_I2CCNT=\$211A;
+SDIB_ORG=\$211C;
+SDIB_LEN=\$54;
+
+SD_END=\$2170;
+SD_LEN=\$16E;
+
.listing off
DEVICE = "MSP430FR6989"
-
+HMPY ; hardware multiplier
; ----------------------------------------------
; MSP430FR6989 MEMORY MAP
-!MSP430fr6989.pat
-
-! ----------------------------------------------
-! MSP430FR6989 MEMORY MAP
-! ----------------------------------------------
-! 0000-0005 = reserved ROM
-! 0006-001F = tiny RAM 26 bytes
-! 0020-0FFF = peripherals (4 KB)
-! 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
-! 1800-19FF = FRAM INFO 512 B
-! 1A00-1AFF = TLV device descriptor info (FRAM 256 B)
-! 1B00-1BFF = ROM boot memory
-! 1C00-23FF = RAM (2 KB)
-! 4400-FF7F = code memory (FRAM 48 kB)
-! FF80-FFFF = interrupt vectors (FRAM 127 B)
-! ----------------------------------------------
-
-
-! ============================================
-! TINY RAM
-! ============================================
-TinyRAM_ORG=\$06!
-TinyRAM_LEN=\$20!
-
-! ============================================
-! BSL
-! ============================================
-BSL1=\$1000!
-
-! ============================================
-! FRAM INFO
-! ============================================
-INFO_ORG=\$1800!
-INFO_LEN=\$0200!
-
-! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
-! those addresses are usable with the symbolic assembler
-! ----------------------------------------------
-! FastForth INFO
-! ----------------------------------------------
-FREQ_KHZ=\$1800! FREQUENCY (in kHz)
-TERMBRW_RST=\$1802! TERMBRW_RST
-TERMMCTLW_RST=\$1804! TERMMCTLW_RST
-I2CSLAVEADR=\$1802! I2C_SLAVE address
-I2CSLAVEADR1=\$1804!
-LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value
-USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
-VERSION=\$180A!
-THREADS=\$180C! THREADS
-KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION
-! BIT14=LF_XTAL
-! BIT13=UART CTS
-! BIT12=UART RTS
-! BIT11=UART XON/XOFF
-! BIT10=UART half duplex
-! BIT9=I2C_TERMINAL
-! BIT8=Q15.16 input
-! BIT7=DOUBLE input
-! BIT6=assembler 20 bits
-! BIT5=assembler 16 bits
-! BIT4=assembler 16 bits with 20 bits addr
-! BIT3=vocabulary set
-! BIT2=
-! BIT1=
-! BIT0=
-!
-DEEP_ORG=\$1810! MOV #DEEP_ORG,X
-DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector
-DEEP_COLD=\$1812! to DEEP_INIT COLD_APP
-DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP
-DEEP_HARD=\$1816! to DEEP_INIT HARD_APP
-DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP
-DEEP_DP=\$181A! to DEEP_INIT RST_DP
-DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC
-DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT
-DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT
-!
-PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X
-INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT
-INIT_EMIT=\$1824! to INIT PFA_EMIT
-INIT_KEY=\$1826! to INIT PFA_KEY
-INIT_CIB=\$1828! to INIT CIB_ORG
-FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words
-INIT_RSP=\$182A! to INIT RSP
-INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_DODOES=\$182E! to INIT rDODOES (R5)
-INIT_DOCON=\$1830! to INIT rDOCON (R6)
-INIT_DOVAR=\$1832! to INIT rDOVAR (R7)
-INIT_CAPS=\$1834! to INIT CAPS
-INIT_BASE=\$1836! to INIT BASE
-INIT_LEAVE=\$1838! to INIT LEAVEPTR
-!
-RST_ORG=\$183A!
-RST_LEN=\$10!
-COLD_APP=\$183A! COLD_APP
-SOFT_APP=\$183C! SOFT_APP
-HARD_APP=\$183E! HARD_APP
-SLEEP_APP=\$1840! SLEEP_APP
-RST_DP=\$1842! RST_RET value for (RAM) DDP
-RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC
-RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT
-RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS)
-!
-! $185A = free EPROM
-!
-! ============================================
-! FRAM TLV
-! ============================================
-TLV_ORG=\$1A00! ; Device Descriptor Info (Tag-Lenght-Value)
-TLV_LEN=\$0100! ;
-DEVICEID=\$1A04!
-
-
-! ============================================
-! RAM
-! ============================================
-RAM_ORG=\$1C00!
-RAM_LEN=\$0800!
-
-! ---------------------------------------
-! FORTH RAM areas :
-! ---------------------------------------
-LSTACK_SIZE=\#16! words
-PSTACK_SIZE=\#48! words
-RSTACK_SIZE=\#48! words
-PAD_LEN=\#84! bytes
-CIB_LEN=\#84! bytes
-HOLD_SIZE=\#34! bytes
-
-! ----------------------------------------------
-! FastForth RAM memory map (>= 1k):
-! ----------------------------------------------
-LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT
-LSATCK=\$1C00! leave stack, grow up
-PSTACK=\$1C80! parameter stack, grow down
-RSTACK=\$1CE0! Return stack, grow down
-!
-PAD_I2CADR=\$1CE0! RX I2C address
-PAD_I2CCNT=\$1CE2! count max
-PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up
-!
-TIB_I2CADR=\$1D38! TX I2C address
-TIB_I2CCNT=\$1D3A! count of bytes
-TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up
-!
-HOLDS_ORG=\$1D90! base address for HOLDS
-HOLD_BASE=\$1DB2! BASE HOLD area, grow down
-!
-HP=\$1DB2! HOLD ptr
-LAST_NFA=\$1DB4!
-LAST_THREAD=\$1DB6!
-LAST_CFA=\$1DB8!
-LAST_PSP=\$1DBA!
-!
-STATEADR=\$1DBC! Interpreter state
-BASEADR=\$1DBE! base
-CAPS=\$1DC0! CAPS ON/OFF
-!
-SOURCE_LEN=\$1DC2! len of input stream
-SOURCE_ORG=\$1DC4! adr of input stream
-TOIN=\$1DC6! >IN
-DP=\$1DC8! dictionary ptr
-!
-LASTVOC=\$1DCA! keep VOC-LINK
-CURRENT=\$1DCC! CURRENT dictionnary ptr
-CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS)
-!
-! ---------------------------------------
-!1DE0! 28 RAM bytes free
-! ---------------------------------------
-
-! ---------------------------------------
-! SD buffer
-! ---------------------------------------
-SD_BUF_I2ADR=\$1DFC!
-SD_BUF_I2CNT=\$1DFE!
-SD_BUF=\$1E00! \ SD_Card buffer
-BUFEND=\$2000!
-
-! ---------------------------------------
-! FAT16 FileSystemInfos
-! ---------------------------------------
-FATtype=\$2002!
-BS_FirstSectorL=\$2004!
-BS_FirstSectorH=\$2006!
-OrgFAT1=\$2008!
-FATSize=\$200A!
-OrgFAT2=\$200C!
-OrgRootDir=\$200E!
-OrgClusters=\$2010! Sector of Cluster 0
-SecPerClus=\$2012!
-
-! ---------------------------------------
-! SD command
-! ---------------------------------------
-SD_CMD_FRM=\$2014! 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
-SD_CMD_FRM0=\$2014! CRC:ll word access
-SD_CMD_FRM1=\$2015! ll byte access
-SD_CMD_FRM2=\$2016! LL:hh word access
-SD_CMD_FRM3=\$2017! hh byte access
-SD_CMD_FRM4=\$2018! HH:CMD word access
-SD_CMD_FRM5=\$2019! CMD byte access
-SectorL=\$201A! 2 words
-SectorH=\$201C!
-
-! ---------------------------------------
-! BUFFER management
-! ---------------------------------------
-BufferPtr=\$201E!
-BufferLen=\$2020!
-
-! ---------------------------------------
-! FAT entry
-! ---------------------------------------
-ClusterL=\$2022! 16 bits wide (FAT16)
-ClusterH=\$2024! 16 bits wide (FAT16)
-LastFATsector=\$2026! Set by FreeAllClusters, used by OPEN_OVERWRITE
-LastFAToffset=\$2028! Set by FreeAllClusters, used by OPEN_OVERWRITE
-FATsector=\$202A! used by APPEND"
-
-! ---------------------------------------
-! DIR entry
-! ---------------------------------------
-DIRclusterL=\$202C! contains the Cluster of current directory ; 1 if FAT16 root directory
-DIRclusterH=\$202E! contains the Cluster of current directory ; 1 if FAT16 root directory
-EntryOfst=\$2030!
-
-! ---------------------------------------
-! Handle Pointer
-! ---------------------------------------
-CurrentHdl=\$2032! contains the address of the last opened file structure, or 0
-
-! ---------------------------------------
-! Load file operation
-! ---------------------------------------
-pathname=\$2034!
-EndOfPath=\$2036!
-
-! ---------------------------------------
-! Handle structure
-! ---------------------------------------
-! three handle tokens :
-! token = 0 : free handle
-! token = 1 : file to read
-! token = 2 : file updated (write)
-! token =-1 : LOAD"ed file (source file)
-
-! offset values
-HDLW_PrevHDL=0! previous handle ; used by LOAD"
-HDLB_Token=2! token
-HDLB_ClustOfst=3! Current sector offset in current cluster (Byte)
-HDLL_DIRsect=4! Dir SectorL (Long)
-HDLH_DIRsect=6!
-HDLW_DIRofst=8! BUFFER offset of Dir entry
-HDLL_FirstClus=10! File First ClusterLo (identify the file)
-HDLH_FirstClus=12! File First ClusterHi (byte)
-HDLL_CurClust=14! Current ClusterLo
-HDLH_CurClust=16! Current ClusterHi (T as 3Th byte)
-HDLL_CurSize=18! written size / not yet read size (Long)
-HDLH_CurSize=20! written size / not yet read size (Long)
-HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE"
-HDLW_PrevLEN=24! previous LEN
-HDLW_PrevORG=26! previous ORG
-
-
-!OpenedFirstFile ; "openedFile" structure
-HandleMax=8!
-HandleLenght=28!
-FirstHandle=\$2038!
-HandleEnd=\$2118!
-
-!SD_card Input Buffer
-SDIB_I2CADR=\$2118!
-SDIB_I2CCNT=\$211A!
-SDIB_ORG=\$211C!
-SDIB_LEN=\$54!
-
-SD_END=\$2170!
-SD_LEN=\$16E!
-
-! ----------------------------------------------
-! FRAM
-! ----------------------------------------------
-MAIN_ORG=\$4400! Code space start
-MAIN_LEN=\$24000! 127 k FRAM
-! ----------------------------------------------
-
-SLEEP=\$4400! CODE_WITHOUT_RETURN, CPU shutdown
-LIT=\$440A! CODE compiled by LITERAL
-XSQUOTE=\$441E! CODE compiled by S" and S_
-HEREXEC=\$4432! CODE HERE and BEGIN execute address
-MUSMOD=\$443E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
-MDIV1DIV2=\$4450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
-MDIV1=\$4458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/
-RET_ADR=\$4482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
-SETIB=\$4484! CODE Set Input Buffer with org & len values, reset >IN pointer
-REFILL=\$4494! CODE accept one line from input and leave org len of input buffer
-CIB_ORG=\$44A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
-QFBRAN=\$44AC! CODE compiled by IF UNTIL
-BRAN=\$44B2! CODE compiled by ELSE REPEAT AGAIN
-NEXT_ADR=\$44B4! CODE NEXT instruction (MOV @IP+,PC)
-XDODOES=\$44B6! to restore rDODOES: MOV #XDODOES,rDODOES
-XDOCON=\$44C4! to restore rDOCON: MOV #XDOCON,rDOCON
-! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
-! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
-INIT_FORTH=\$44D0! asm CODE common part of RST and QABORT, starts FORTH engine
-QABORT=\$4508! CODE_WITHOUT_RETURN run-time part of ABORT"
-ABORT_TERM=\$4512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET
-!-------------------------------------------------------------------------------
-! UART FASTFORTH
-!-------------------------------------------------------------------------------
-UART_INIT_TERM=\$4554! asm CODE, content of WARM+2 by default (WARM starts with: CALL &HARD_APP)
-UART_COLD_TERM=\$457E! asm CODE, content of COLD+2 by default (COLD starts with: CALL &STOP_APP)
-UART_INIT_SOFT=\$4584! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SOFT_APP)
-UART_WARM=\$4586! WARM address
-UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL &SLEEP_APP)
-UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'.
-!-------------------------------------------------------------------------------
-! I2C FASTFORTH
-!-------------------------------------------------------------------------------
-I2C_ACCEPT=\$4544! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP)
-I2C_CTRL_CH=\$4546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y
-! CALL #I2C_CTRL_CH
-I2C_COLD_TERM=\$4550! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP)
-I2C_INIT_SOFT=\$4550! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP)
-I2C_INIT_TERM=\$4552! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP)
-I2C_WARM=\$457A! WARM address
-!-------------------------------------------------------------------------------
-NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 +
-COLD=SYS\+\$16! COLD address ' SYS 22 +
-ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 +
-QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 +
-
-! ----------------------------------------------
-! Interrupt Vectors and signatures - MSP430FR6989
-! ----------------------------------------------
-MAIN_LEN=\$1FC00! 127 k FRAM
-FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use.
-SIGNATURES=\$FF80! JTAG/BSL signatures
-JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
-JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
-BSL_SIG1=\$FF84!
-BSL_SIG2=\$FF86!
-I2CSLA0=\$FFA2! UCBxI2COA0 default value address
-I2CSLA1=\$FFA4! UCBxI2COA1 default value address
-I2CSLA2=\$FFA6! UCBxI2COA2 default value address
-I2CSLA3=\$FFA8! UCBxI2COA3 default value address
-JTAG_PASSWORD=\$FF88! 256 bits
-BSL_PASSWORD=\$FFE0! 256 bits
-VECT_ORG=\$FFC6! FFC6-FFFF
-VECT_LEN=\$3A!
-
-
-AES_VEC=\$FFC6!
-RTC_VEC=\$FFC8!
-LCD_VEC=\$FFCA!
-P4_VEC=\$FFCC!
-P3_VEC=\$FFCE!
-TA3_X_VEC=\$FFD0!
-TA3_0_VEC=\$FFD2!
-P2_VEC=\$FFD4!
-TA2_X_VEC=\$FFD6!
-TA2_0_VEC=\$FFD8!
-P1_VEC=\$FFDA!
-TA1_X_VEC=\$FFDC!
-TA1_0_VEC=\$FFDE!
-DMA_VEC=\$FFE0!
-EUSCI_B1_VEC=\$FFE2!
-EUSCI_A1_VEC=\$FFE4!
-TA0_X_VEC=\$FFE6!
-TA0_0_VEC=\$FFE8!
-ADC12_B_VEC=\$FFEA!
-EUSCI_B0_VEC=\$FFEC!
-EUSCI_A0_VEC=\$FFEE!
-ESI_VEC=\$FFF0!
-WDT_VEC=\$FFF2!
-TB0_X_VEC=\$FFF4!
-TB0_0_VEC=\$FFF6!
-COMP_E_VEC=\$FFF8!
-U_NMI_VEC=\$FFFA!
-S_NMI_VEC=\$FFFC!
-RST_VEC=\$FFFE!
-
-! ============================================
-! Special Fonction Registers (SFR)
-! ============================================
-
-SFRIE1=\$100! \ SFR enable register
-SFRIFG1=\$102! \ SFR flag register
-SFRRPCR=\$104! \ SFR reset pin control
-
-PMMCTL0=\$120! \ PMM Control 0
-PMMIFG=\$12A! \ PMM interrupt flags
-PM5CTL0=\$130! \ PM5 Control 0
-
-FRCTLCTL0=\$140! \ FRAM control 0
-GCCTL0=\$144! \ General control 0
-GCCTL1=\$146! \ General control 1
-
-CRC16DI=\$150! \ CRC data input
-CRCDIRB=\$152! \ CRC data input reverse byte
-CRCINIRES=\$154! \ CRC initialization and result
-CRCRESR=\$156! \ CRC result reverse byte
-
-RCCTL0=\$158! \ RAM controller control 0
-
-WDTCTL=\$15C! \ WDT control register
-
-CSCTL0=\$160! \ CS control 0
-CSCTL1=\$162! \ CS control 1
-CSCTL2=\$164! \ CS control 2
-CSCTL3=\$166! \ CS control 3
-CSCTL4=\$168! \ CS control 4
-CSCTL5=\$16A! \ CS control 5
-CSCTL6=\$16C! \ CS control 6
-
-SYSCTL=\$180! \ System control
-SYSJMBC=\$186! \ JTAG mailbox control
-SYSJMBI0=\$188! \ JTAG mailbox input 0
-SYSJMBI1=\$18A! \ JTAG mailbox input 1
-SYSJMBO0=\$18C! \ JTAG mailbox output 0
-SYSJMBO1=\$18E! \ JTAG mailbox output 1
-SYSUNIV=\$19A! \ User NMI vector generator
-SYSSNIV=\$19C! \ System NMI vector generator
-SYSRSTIV=\$19E! \ Reset vector generator
-
-REFCTL=\$1B0! \ Shared reference control
-
-PAIN=\$200!
-PAOUT=\$202!
-PADIR=\$204!
-PAREN=\$206!
-PASEL0=\$20A!
-PASEL1=\$20C!
-PASELC=\$216!
-PAIES=\$218!
-PAIE=\$21A!
-PAIFG=\$21C!
-
-P1IN=\$200!
-P1OUT=\$202!
-P1DIR=\$204!
-P1REN=\$206!
-P1SEL0=\$20A!
-P1SEL1=\$20C!
-P1IV=\$20E!
-P1SELC=\$216!
-P1IES=\$218!
-P1IE=\$21A!
-P1IFG=\$21C!
-
-P2IN=\$201!
-P2OUT=\$203!
-P2DIR=\$205!
-P2REN=\$207!
-P2SEL0=\$20B!
-P2SEL1=\$20D!
-P2SELC=\$217!
-P2IES=\$219!
-P2IE=\$21B!
-P2IFG=\$21D!
-P2IV=\$21E!
-
-PBIN=\$220!
-PBOUT=\$222!
-PBDIR=\$224!
-PBREN=\$226!
-PBSEL0=\$22A!
-PBSEL1=\$22C!
-PBSELC=\$236!
-PBIES=\$238!
-PBIE=\$23A!
-PBIFG=\$23C!
-
-P3IN=\$220!
-P3OUT=\$222!
-P3DIR=\$224!
-P3REN=\$226!
-P3SEL0=\$22A!
-P3SEL1=\$22C!
-P3IV=\$22E!
-P3SELC=\$236!
-P3IES=\$238!
-P3IE=\$23A!
-P3IFG=\$23C!
-
-P4IN=\$221!
-P4OUT=\$223!
-P4DIR=\$225!
-P4REN=\$227!
-P4SEL0=\$22B!
-P4SEL1=\$22D!
-P4SELC=\$237!
-P4IES=\$239!
-P4IE=\$23B!
-P4IFG=\$23D!
-P4IV=\$23E!
-
-PCIN=\$240!
-PCOUT=\$242!
-PCDIR=\$244!
-PCREN=\$246!
-PCSEL0=\$24A!
-PCSEL1=\$24C!
-PCSELC=\$256!
-
-P5IN=\$240!
-P5OUT=\$242!
-P5DIR=\$244!
-P5REN=\$246!
-P5SEL0=\$24A!
-P5SEL1=\$24C!
-P5SELC=\$256!
-
-P6IN=\$241!
-P6OUT=\$243!
-P6DIR=\$245!
-P6REN=\$247!
-P6SEL0=\$24B!
-P6SEL1=\$24D!
-P6SELC=\$257!
-
-PDIN=\$260!
-PDOUT=\$262!
-PDDIR=\$264!
-PDREN=\$266!
-PDSEL0=\$26A!
-PDSEL1=\$26C!
-PDSELC=\$276!
-
-P7IN=\$260!
-P7OUT=\$262!
-P7DIR=\$264!
-P7REN=\$266!
-P7SEL0=\$26A!
-P7SEL1=\$26C!
-P7SELC=\$276!
-
-P8IN=\$261!
-P8OUT=\$263!
-P8DIR=\$265!
-P8REN=\$267!
-P8SEL0=\$26B!
-P8SEL1=\$26D!
-P8SELC=\$277!
-
-PEIN=\$280!
-PEOUT=\$282!
-PEDIR=\$284!
-PEREN=\$286!
-PESEL0=\$28A!
-PESEL1=\$28C!
-PESELC=\$296!
-
-P9IN=\$280!
-P9OUT=\$282!
-P9DIR=\$284!
-P9REN=\$286!
-P9SEL0=\$28A!
-P9SEL1=\$28C!
-P9SELC=\$296!
-
-P10IN=\$281!
-P10OUT=\$283!
-P10DIR=\$285!
-P10REN=\$287!
-P10SEL0=\$28B!
-P10SEL1=\$28D!
-P10SELC=\$297!
-
-PJIN=\$320!
-PJOUT=\$322!
-PJDIR=\$324!
-PJREN=\$326!
-PJSEL0=\$32A!
-PJSEL1=\$32C!
-PJSELC=\$336!
-
-
-TACLR=4!
-TAIFG=1!
-TBCLR=2!
-TBIFG=1!
-CCIFG=1!
-
-TA0CTL=\$340! \ TA0 control
-TA0CCTL0=\$342! \ Capture/compare control 0
-TA0CCTL1=\$344! \ Capture/compare control 1
-TA0CCTL2=\$346! \ Capture/compare control 2
-TA0CCTL3=\$348! \ Capture/compare control 3
-TA0CCTL4=\$34A! \ Capture/compare control 4
-TA0R=\$350! \ TA0 counter register
-TA0CCR0=\$352! \ Capture/compare register 0
-TA0CCR1=\$354! \ Capture/compare register 1
-TA0CCR2=\$356! \ Capture/compare register 2
-TA0CCR2=\$358! \ Capture/compare register 3
-TA0CCR2=\$35A! \ Capture/compare register 4
-TA0EX0=\$360! \ TA0 expansion register 0
-TA0IV=\$36E! \ TA0 interrupt vector
-
-TA1CTL=\$380! \ TA1 control
-TA1CCTL0=\$382! \ Capture/compare control 0
-TA1CCTL1=\$384! \ Capture/compare control 1
-TA1CCTL2=\$386! \ Capture/compare control 2
-TA1R=\$390! \ TA1 counter register
-TA1CCR0=\$392! \ Capture/compare register 0
-TA1CCR1=\$394! \ Capture/compare register 1
-TA1CCR2=\$396! \ Capture/compare register 2
-TA1EX0=\$3A0! \ TA1 expansion register 0
-TA1IV=\$3AE! \ TA1 interrupt vector
-
-TB0CTL=\$3C0! \ TB0 control
-TB0CCTL0=\$3C2! \ Capture/compare control 0
-TB0CCTL1=\$3C4! \ Capture/compare control 1
-TB0CCTL2=\$3C6! \ Capture/compare control 2
-TB0CCTL3=\$3C8! \ Capture/compare control 3
-TB0CCTL4=\$3CA! \ Capture/compare control 4
-TB0CCTL5=\$3CC! \ Capture/compare control 5
-TB0CCTL6=\$3CE! \ Capture/compare control 6
-TB0R=\$3D0! \ TB0 counter register
-TB0CCR0=\$3D2! \ Capture/compare register 0
-TB0CCR1=\$3D4! \ Capture/compare register 1
-TB0CCR2=\$3D6! \ Capture/compare register 2
-TB0CCR3=\$3D8! \ Capture/compare register 3
-TB0CCR5=\$3DA! \ Capture/compare register 4
-TB0CCR5=\$3DC! \ Capture/compare register 5
-TB0CCR6=\$3DE! \ Capture/compare register 6
-TB0EX0=\$3E0! \ TB0 expansion register 0
-TB0IV=\$3EE! \ TB0 interrupt vector
-
-TA2CTL=\$400! \ TA2 control
-TA2CCTL0=\$402! \ Capture/compare control 0
-TA2CCTL1=\$404! \ Capture/compare control 1
-TA2R=\$410! \ TA2 counter register
-TA2CCR0=\$412! \ Capture/compare register 0
-TA2CCR1=\$414! \ Capture/compare register 1
-TA2EX0=\$420! \ TA2 expansion register 0
-TA2IV=\$42E! \ TA2 interrupt vector
-
-CAPTIO0CTL=\$43E! \ Capacitive Touch IO 0 control
-
-TA3CTL=\$440! \ TA3 control
-TA3CCTL0=\$442! \ Capture/compare control 0
-TA3CCTL1=\$444! \ Capture/compare control 1
-TA3CCTL2=\$446! \ Capture/compare control 2
-TA3CCTL3=\$448! \ Capture/compare control 3
-TA3CCTL4=\$44A! \ Capture/compare control 4
-TA3R=\$450! \ TA3 counter register
-TA3CCR0=\$452! \ Capture/compare register 0
-TA3CCR1=\$454! \ Capture/compare register 1
-TA3CCR2=\$456! \ Capture/compare register 2
-TA3CCR3=\$458! \ Capture/compare register 3
-TA3CCR4=\$45A! \ Capture/compare register 4
-TA3EX0=\$460! \ TA3 expansion register 0
-TA3IV=\$46E! \ TA3 interrupt vector
-
-CAPTIO1CTL=\$47E! \ Capacitive Touch IO 1 control
-
-! \ RTC_C
-RTCCTL0_L=\$4A0! \ RTCCTL0_L
-RTCCTL0_H=\$4A1! \ RTCCTL0_H
-RTCCTL1=\$4A2! \ RTCCTL1
-RTCCTL3=\$4A3! \ RTCCTL3
-RTCPS0CTL=\$4A8! \ RTC prescaler 0 control
-RTCPS1CTL=\$4AA! \ RTC prescaler 1 control
-RTCPS=\$4AC! \ RTC prescaler
-RT0PS=\$4AC! \ RTC prescaler 0
-RT1PS=\$4AD! \ RTC prescaler 1
-RTCIV=\$4AE! \ RTC interrupt vector word
-RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC,
-RTCCNT1=\$4B0! \ Real-Time Counter 1
-RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN,
-RTCCNT2=\$4B1! \ Real-Time Counter 2
-RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR,
-RTCCNT3=\$4B2! \ Real-Time Counter 3
-RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW,
-RTCCNT4=\$4B3! \ Real-Time Counter 4
-RTCDAY=\$4B4! \ RTC days
-RTCMON=\$4B5! \ RTC month
-RTCYEAR=\$4B6!
-RTCYEARL=\$4B6! \ RTC year low
-RTCYEARH=\$4B7! \ RTC year high
-RTCAMIN=\$4B8! \ RTC alarm minutes
-RTCAHOUR=\$4B9! \ RTC alarm hours
-RTCADOW=\$4BA! \ RTC alarm day of week
-RTCADAY=\$4BB! \ RTC alarm days
-BIN2BCD=\$4BC! \ Binary-to-BCD conversion register
-BCD2BIN=\$4BE! \ BCD-to-binary conversion register
-
-RTCHOLD=\$40!
-RTCRDY=\$10!
-
-MPY=\$4C0! \ 16-bit operand 1 - multiply
-MPYS=\$4C2! \ 16-bit operand 1 - signed multiply
-MAC=\$4C4! \ 16-bit operand 1 - multiply accumulate
-MACS=\$4C6! \ 16-bit operand 1 - signed multiply accumulate
-OP2=\$4C8! \ 16-bit operand 2
-RESLO=\$4CA! \ 16 x 16 result low word
-RESHI=\$4CC! \ 16 x 16 result high word
-SUMEXT=\$4CE! \ 16 x 16 sum extension register
-MPY32L=\$4D0! \ 32-bit operand 1 - multiply low word
-MPY32H=\$4D2! \ 32-bit operand 1 - multiply high word
-MPYS32L=\$4D4! \ 32-bit operand 1 - signed multiply low word
-MPYS32H=\$4D6! \ 32-bit operand 1 - signed multiply high word
-MAC32L=\$4D8! \ 32-bit operand 1 - multiply accumulate low word
-MAC32H=\$4DA! \ 32-bit operand 1 - multiply accumulate high word
-MACS32L=\$4DC! \ 32-bit operand 1 - signed multiply accumulate low word
-MACS32H=\$4DE! \ 32-bit operand 1 - signed multiply accumulate high word
-OP2L=\$4E0! \ 32-bit operand 2 - low word
-OP2H=\$4E2! \ 32-bit operand 2 - high word
-RES0=\$4E4! \ 32 x 32 result 0 - least significant word
-RES1=\$4E6! \ 32 x 32 result 1
-RES2=\$4E8! \ 32 x 32 result 2
-RES3=\$4EA! \ 32 x 32 result 3 - most significant word
-MPY32CTL0=\$4EC! \ MPY32 control register 0
-
-DMAIFG=8!
-
-DMACTL0=\$500! \ DMA module control 0
-DMACTL1=\$502! \ DMA module control 1
-DMACTL2=\$504! \ DMA module control 2
-DMACTL3=\$506! \ DMA module control 3
-DMACTL4=\$508! \ DMA module control 4
-DMAIV=\$50A! \ DMA interrupt vector
-
-DMA0CTL=\$510! \ DMA channel 0 control
-DMA0SAL=\$512! \ DMA channel 0 source address low
-DMA0SAH=\$514! \ DMA channel 0 source address high
-DMA0DAL=\$516! \ DMA channel 0 destination address low
-DMA0DAH=\$518! \ DMA channel 0 destination address high
-DMA0SZ=\$51A! \ DMA channel 0 transfer size
-
-DMA1CTL=\$520! \ DMA channel 1 control
-DMA1SAL=\$522! \ DMA channel 1 source address low
-DMA1SAH=\$524! \ DMA channel 1 source address high
-DMA1DAL=\$526! \ DMA channel 1 destination address low
-DMA1DAH=\$528! \ DMA channel 1 destination address high
-DMA1SZ=\$52A! \ DMA channel 1 transfer size
-
-DMA2CTL=\$530! \ DMA channel 2 control
-DMA2SAL=\$532! \ DMA channel 2 source address low
-DMA2SAH=\$534! \ DMA channel 2 source address high
-DMA2DAL=\$536! \ DMA channel 2 destination address low
-DMA2DAH=\$538! \ DMA channel 2 destination address high
-DMA2SZ=\$53A! \ DMA channel 2 transfer size
-
-
-MPUCTL0=\$5A0! \ MPU control 0
-MPUCTL1=\$5A2! \ MPU control 1
-MPUSEGB2=\$5A4! \ MPU Segmentation Border2
-MPUSEGB1=\$5A6! \ MPU Segmentation Border1
-MPUSAM=\$5A8! \ MPU access management
-MPUIPC0=\$5AA! \ MPU IP control 0
-MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2
-MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1
-
-UCA0CTLW0=\$5C0! \ eUSCI_A control word 0
-UCA0CTLW1=\$5C2! \ eUSCI_A control word 1
-UCA0BRW=\$5C6!
-UCA0BR0=\$5C6! \ eUSCI_A baud rate 0
-UCA0BR1=\$5C7! \ eUSCI_A baud rate 1
-UCA0MCTLW=\$5C8! \ eUSCI_A modulation control
-UCA0STAT=\$5CA! \ eUSCI_A status
-UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer
-UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer
-UCA0ABCTL=\$5D0! \ eUSCI_A LIN control
-UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-UCA0IE=\$5DA! \ eUSCI_A interrupt enable
-UCA0IFG=\$5DC! \ eUSCI_A interrupt flags
-UCA0IV=\$5DE! \ eUSCI_A interrupt vector word
-
-UCA1CTLW0=\$5E0! \ eUSCI_A control word 0
-UCA1CTLW1=\$5E2! \ eUSCI_A control word 1
-UCA1BRW=\$5E6!
-UCA1BR0=\$5E6! \ eUSCI_A baud rate 0
-UCA1BR1=\$5E7! \ eUSCI_A baud rate 1
-UCA1MCTLW=\$5E8! \ eUSCI_A modulation control
-UCA1STAT=\$5EA! \ eUSCI_A status
-UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer
-UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer
-UCA1ABCTL=\$5F0! \ eUSCI_A LIN control
-UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control
-UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control
-UCA1IE=\$5FA! \ eUSCI_A interrupt enable
-UCA1IFG=\$5FC! \ eUSCI_A interrupt flags
-UCA1IV=\$5FE! \ eUSCI_A interrupt vector word
-
-
-UCB0CTLW0=\$640! \ eUSCI_B control word 0
-UCB0CTLW1=\$642! \ eUSCI_B control word 1
-UCB0BRW=\$646!
-UCB0BR0=\$646! \ eUSCI_B bit rate 0
-UCB0BR1=\$647! \ eUSCI_B bit rate 1
-UCB0STATW=\$648! \ eUSCI_B status word
-UCBCNT0=\$649! \ eUSCI_B hardware count
-UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold
-UCB0RXBUF=\$64C! \ eUSCI_B receive buffer
-UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer
-UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0
-UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1
-UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2
-UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3
-UCB0ADDRX=\$65C! \ eUSCI_B received address
-UCB0ADDMASK=\$65E! \ eUSCI_B address mask
-UCB0I2CSA=\$660! \ eUSCI I2C slave address
-UCB0IE=\$66A! \ eUSCI interrupt enable
-UCB0IFG=\$66C! \ eUSCI interrupt flags
-UCB0IV=\$66E! \ eUSCI interrupt vector word
-
-UCB1CTLW0=\$680! \ eUSCI_B control word 0
-UCB1CTLW1=\$682! \ eUSCI_B control word 1
-UCB1BRW=\$686!
-UCB1BR0=\$686! \ eUSCI_B bit rate 0
-UCB1BR1=\$687! \ eUSCI_B bit rate 1
-UCB1STATW=\$688! \ eUSCI_B status word
-UCB1NT0=\$689! \ eUSCI_B hardware count
-UCB1TBCNT=\$68A! \ eUSCI_B byte counter threshold
-UCB1RXBUF=\$68C! \ eUSCI_B receive buffer
-UCB1TXBUF=\$68E! \ eUSCI_B transmit buffer
-UCB1I2COA0=\$694! \ eUSCI_B I2C own address 0
-UCB1I2COA1=\$696! \ eUSCI_B I2C own address 1
-UCB1I2COA2=\$698! \ eUSCI_B I2C own address 2
-UCB1I2COA3=\$69A! \ eUSCI_B I2C own address 3
-UCB1ADDRX=\$69C! \ eUSCI_B received address
-UCB1ADDMASK=\$69E! \ eUSCI_B address mask
-UCB1I2CSA=\$6A0! \ eUSCI I2C slave address
-UCB1IE=\$6AA! \ eUSCI interrupt enable
-UCB1IFG=\$6AC! \ eUSCI interrupt flags
-UCB1IV=\$6AE! \ eUSCI interrupt vector word
-
-UCTXACK=\$20!
-UCTR=\$10!
-
-
-ADC12CTL0=\$800! \ ADC12_B Control 0
-ADC12CTL1=\$802! \ ADC12_B Control 1
-ADC12CTL2=\$804! \ ADC12_B Control 2
-ADC12CTL3=\$806! \ ADC12_B Control 3
-ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register
-ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register
-ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0
-ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1
-ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2
-ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0
-ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1
-ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2
-ADC12IV=\$818! \ ADC12_B Interrupt Vector
-ADC12MCTL0=\$820! \ ADC12_B Memory Control 0
-ADC12MCTL1=\$822! \ ADC12_B Memory Control 1
-ADC12MCTL2=\$824! \ ADC12_B Memory Control 2
-ADC12MCTL3=\$826! \ ADC12_B Memory Control 3
-ADC12MCTL4=\$828! \ ADC12_B Memory Control 4
-ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5
-ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6
-ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7
-ADC12MCTL8=\$830! \ ADC12_B Memory Control 8
-ADC12MCTL9=\$832! \ ADC12_B Memory Control 9
-ADC12MCTL10=\$834! \ ADC12_B Memory Control 10
-ADC12MCTL11=\$836! \ ADC12_B Memory Control 11
-ADC12MCTL12=\$838! \ ADC12_B Memory Control 12
-ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13
-ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14
-ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15
-ADC12MCTL16=\$840! \ ADC12_B Memory Control 16
-ADC12MCTL17=\$842! \ ADC12_B Memory Control 17
-ADC12MCTL18=\$844! \ ADC12_B Memory Control 18
-ADC12MCTL19=\$846! \ ADC12_B Memory Control 19
-ADC12MCTL20=\$848! \ ADC12_B Memory Control 20
-ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21
-ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22
-ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23
-ADC12MCTL24=\$850! \ ADC12_B Memory Control 24
-ADC12MCTL25=\$852! \ ADC12_B Memory Control 25
-ADC12MCTL26=\$854! \ ADC12_B Memory Control 26
-ADC12MCTL27=\$856! \ ADC12_B Memory Control 27
-ADC12MCTL28=\$858! \ ADC12_B Memory Control 28
-ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29
-ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30
-ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31
-ADC12MEM0=\$860! \ ADC12_B Memory 0
-ADC12MEM1=\$862! \ ADC12_B Memory 1
-ADC12MEM2=\$864! \ ADC12_B Memory 2
-ADC12MEM3=\$866! \ ADC12_B Memory 3
-ADC12MEM4=\$868! \ ADC12_B Memory 4
-ADC12MEM5=\$86A! \ ADC12_B Memory 5
-ADC12MEM6=\$86C! \ ADC12_B Memory 6
-ADC12MEM7=\$86E! \ ADC12_B Memory 7
-ADC12MEM8=\$870! \ ADC12_B Memory 8
-ADC12MEM9=\$872! \ ADC12_B Memory 9
-ADC12MEM10=\$874! \ ADC12_B Memory 10
-ADC12MEM11=\$876! \ ADC12_B Memory 11
-ADC12MEM12=\$878! \ ADC12_B Memory 12
-ADC12MEM13=\$87A! \ ADC12_B Memory 13
-ADC12MEM14=\$87C! \ ADC12_B Memory 14
-ADC12MEM15=\$87E! \ ADC12_B Memory 15
-ADC12MEM16=\$880! \ ADC12_B Memory 16
-ADC12MEM17=\$882! \ ADC12_B Memory 17
-ADC12MEM18=\$884! \ ADC12_B Memory 18
-ADC12MEM19=\$886! \ ADC12_B Memory 19
-ADC12MEM20=\$888! \ ADC12_B Memory 20
-ADC12MEM21=\$88A! \ ADC12_B Memory 21
-ADC12MEM22=\$88C! \ ADC12_B Memory 22
-ADC12MEM23=\$88E! \ ADC12_B Memory 23
-ADC12MEM24=\$890! \ ADC12_B Memory 24
-ADC12MEM25=\$892! \ ADC12_B Memory 25
-ADC12MEM26=\$894! \ ADC12_B Memory 26
-ADC12MEM27=\$896! \ ADC12_B Memory 27
-ADC12MEM28=\$898! \ ADC12_B Memory 28
-ADC12MEM29=\$89A! \ ADC12_B Memory 29
-ADC12MEM30=\$89C! \ ADC12_B Memory 30
-ADC12MEM31=\$89E! \ ADC12_B Memory 31
-
-ADCON=\$10!
-ADCSTART=\$03!
-
-CDIFG=1!
-CDIIFG=2!
-
-CDCTL0=\$8C0! \ Comparator_E control register 0
-CDCTL1=\$8C2! \ Comparator_E control register 1
-CDCTL2=\$8C4! \ Comparator_E control register 2
-CDCTL3=\$8C6! \ Comparator_E control register 3
-CDINT=\$8CC! \ Comparator_E interrupt register
-CDIV=\$8CE! \ Comparator_E interrupt vector word
-
-CRC32DIW0=\$980! \ CRC32 data input
-CRC32DIRBW0=\$986! \ CRC32 data input reverse
-CRC32INIRESW0=\$988! \ CRC32 initialization and result word 0
-CRC32INIRESW1=\$98A! \ CRC32 initialization and result word 1
-CRC32RESRW1=\$98! \ CRC32 result reverse word 1
-CRC32RESRW1=\$98E! \ CRC32 result reverse word 0
-CRC16DIW0=\$990! \ CRC16 data input
-CRC16DIRBW0=\$996! \ CRC16 data input reverse
-CRC16INIRESW0=\$998! \ CRC16 initialization and result word 0
-CRC16RESRW1=\$99E! \ CRC16 result reverse word 0
-
-
-AESACTL0=\$9C0! \ AES accelerator control register 0
-AESASTAT=\$9C4! \ AES accelerator status register
-AESAKEY=\$9C6! \ AES accelerator key register
-AESADIN=\$9C8! \ AES accelerator data in register
-AESADOUT=\$9CA! \ AES accelerator data out register
-AESAXDIN=\$9CC! \ AES accelerator XORed data in register
-AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger)
-
-
-LCDCCTL0=\$A00! \ LCD_C control register 0
-LCDCCTL1=\$A02! \ LCD_C control register 1
-LCDCBLKCTL=\$A04! \ LCD_C blinking control register
-LCDCMEMCTL=\$A06! \ LCD_C memory control register
-LCDCVCTL=\$A08! \ LCD_C voltage control register
-LCDCPCTL0=\$A0A! \ LCD_C port control 0
-LCDCPCTL1=\$A0C! \ LCD_C port control 1
-LCDCPCTL2=\$A0E! \ LCD_C port control 2
-LCDCCPCTL=\$A12! \ LCD_C charge pump ctrl register
-LCDCIV=\$A1E! \ LCD_C interrupt vector
-LCDM1=\$A20! \ LCD_C memory 1
-LCDM2=\$A21! \ LCD_C memory 2
-LCDM3=\$A22! \ LCD_C memory 3
-LCDM4=\$A23! \ LCD_C memory 4
-LCDM5=\$A24! \ LCD_C memory 5
-LCDM6=\$A25! \ LCD_C memory 6
-LCDM7=\$A26! \ LCD_C memory 7
-LCDM8=\$A27! \ LCD_C memory 8
-LCDM9=\$A28! \ LCD_C memory 9
-LCDM10=\$A29! \ LCD_C memory 10
-LCDM11=\$A2A! \ LCD_C memory 11
-LCDM12=\$A2B! \ LCD_C memory 12
-LCDM13=\$A2C! \ LCD_C memory 13
-LCDM14=\$A2D! \ LCD_C memory 14
-LCDM15=\$A2E! \ LCD_C memory 15
-LCDM16=\$A2F! \ LCD_C memory 16
-LCDM17=\$A30! \ LCD_C memory 17
-LCDM18=\$A31! \ LCD_C memory 18
-LCDM19=\$A32! \ LCD_C memory 19
-LCDM20=\$A33! \ LCD_C memory 20
-LCDM21=\$A34! \ LCD_C memory 21
-LCDM22=\$A35! \ LCD_C memory 22
-LCDM23=\$A36! \ LCD_C memory 23
-LCDM24=\$A37! \ LCD_C memory 24
-LCDM25=\$A38! \ LCD_C memory 25
-LCDM26=\$A39! \ LCD_C memory 26
-LCDM27=\$A3A! \ LCD_C memory 27
-LCDM28=\$A3B! \ LCD_C memory 28
-LCDM29=\$A3C! \ LCD_C memory 29
-LCDM30=\$A3D! \ LCD_C memory 30
-LCDM31=\$A3E! \ LCD_C memory 31
-LCDM32=\$A3F! \ LCD_C memory 32
-LCDM33=\$A40! \ LCD_C memory 33
-LCDM34=\$A41! \ LCD_C memory 34
-LCDM35=\$A42! \ LCD_C memory 35
-LCDM36=\$A43! \ LCD_C memory 36
-LCDM37=\$A44! \ LCD_C memory 37
-LCDM38=\$A45! \ LCD_C memory 38
-LCDM39=\$A46! \ LCD_C memory 39
-LCDM40=\$A47! \ LCD_C memory 40
-LCDM41=\$A48! \ LCD_C memory 41
-LCDM42=\$A49! \ LCD_C memory 42
-LCDM43=\$A4A! \ LCD_C memory 43
-LCDBM1=\$A40! \ LCD_C blinking memory 1
-LCDBM2=\$A41! \ LCD_C blinking memory 2
-LCDBM3=\$A42! \ LCD_C blinking memory 3
-LCDBM4=\$A43! \ LCD_C blinking memory 4
-LCDBM5=\$A44! \ LCD_C blinking memory 5
-LCDBM6=\$A45! \ LCD_C blinking memory 6
-LCDBM7=\$A46! \ LCD_C blinking memory 7
-LCDBM8=\$A47! \ LCD_C blinking memory 8
-LCDBM9=\$A48! \ LCD_C blinking memory 9
-LCDBM10=\$A49! \ LCD_C blinking memory 10
-LCDBM11=\$A4A! \ LCD_C blinking memory 11
-LCDBM12=\$A4B! \ LCD_C blinking memory 12
-LCDBM13=\$A4C! \ LCD_C blinking memory 13
-LCDBM14=\$A4D! \ LCD_C blinking memory 14
-LCDBM15=\$A4E! \ LCD_C blinking memory 15
-LCDBM16=\$A4F! \ LCD_C blinking memory 16
-LCDBM17=\$A50! \ LCD_C blinking memory 17
-LCDBM18=\$A51! \ LCD_C blinking memory 18
-LCDBM19=\$A52! \ LCD_C blinking memory 19
-LCDBM20=\$A53! \ LCD_C blinking memory 20
-LCDBM21=\$A54! \ LCD_C blinking memory 21
-LCDBM22=\$A55! \ LCD_C blinking memory 22
-
-
-ESIDEBUG1=\$D00! \ ESI debug register 1
-ESIDEBUG2=\$D02! \ ESI debug register 2
-ESIDEBUG3=\$D04! \ ESI debug register 3
-ESIDEBUG4=\$D06! \ ESI debug register 4
-ESIDEBUG5=\$D08! \ ESI debug register 5
-ESICNT0=\$D10! \ ESI PSM counter 0
-ESICNT1=\$D12! \ ESI PSM counter 1
-ESICNT2=\$D14! \ ESI PSM counter 2
-ESICNT3=\$D16! \ ESI oscillator counter register
-ESIIV=\$D1A! \ ESI interrupt vector
-ESIINT1=\$D1C! \ ESI interrupt register 1
-ESIINT2=\$D1E! \ ESI interrupt register 2
-ESIAFE=\$D20! \ ESI AFE control register
-ESIPPU=\$D22! \ ESI PPU control register
-ESITSM=\$D24! \ ESI TSM control register
-ESIPSM=\$D26! \ ESI PSM control register
-ESIOSC=\$D28! \ ESI oscillator control register
-ESICTL=\$D2A! \ ESI control register
-ESITHR1=\$D2C! \ ESI PSM counter threshold register 1
-ESITHR2=\$D2E! \ ESI PSM counter threshold register 2
-ESIADMEM1=\$D30! \ ESI A/D conversion memory 1
-ESIADMEM2=\$D32! \ ESI A/D conversion memory 2
-ESIADMEM3=\$D34! \ ESI A/D conversion memory 3
-ESIADMEM4=\$D36! \ ESI A/D conversion memory 4
-ESIDAC1R0=\$D40! \ ESI DAC1 register 0
-ESIDAC1R1=\$D42! \ ESI DAC1 register 1
-ESIDAC1R2=\$D44! \ ESI DAC1 register 2
-ESIDAC1R3=\$D46! \ ESI DAC1 register 3
-ESIDAC1R4=\$D48! \ ESI DAC1 register 4
-ESIDAC1R5=\$D4A! \ ESI DAC1 register 5
-ESIDAC1R6=\$D4C! \ ESI DAC1 register 6
-ESIDAC1R7=\$D4E! \ ESI DAC1 register 7
-ESIDAC2R0=\$D50! \ ESI DAC2 register 0
-ESIDAC2R1=\$D52! \ ESI DAC2 register 1
-ESIDAC2R2=\$D54! \ ESI DAC2 register 2
-ESIDAC2R3=\$D56! \ ESI DAC2 register 3
-ESIDAC2R4=\$D58! \ ESI DAC2 register 4
-ESIDAC2R5=\$D5A! \ ESI DAC2 register 5
-ESIDAC2R6=\$D5C! \ ESI DAC2 register 6
-ESIDAC2R7=\$D5E! \ ESI DAC2 register 7
-ESITSM0=\$D60! \ ESI TSM 0
-ESITSM1=\$D62! \ ESI TSM 1
-ESITSM2=\$D64! \ ESI TSM 2
-ESITSM3=\$D66! \ ESI TSM 3
-ESITSM4=\$D68! \ ESI TSM 4
-ESITSM5=\$D6A! \ ESI TSM 5
-ESITSM6=\$D6C! \ ESI TSM 6
-ESITSM7=\$D6E! \ ESI TSM 7
-ESITSM8=\$D70! \ ESI TSM 8
-ESITSM9=\$D72! \ ESI TSM 9
-ESITSM10=\$D74! \ ESI TSM 10
-ESITSM11=\$D76! \ ESI TSM 11
-ESITSM12=\$D78! \ ESI TSM 12
-ESITSM13=\$D7A! \ ESI TSM 13
-ESITSM14=\$D7C! \ ESI TSM 14
-ESITSM15=\$D7E! \ ESI TSM 15
-ESITSM16=\$D80! \ ESI TSM 16
-ESITSM17=\$D82! \ ESI TSM 17
-ESITSM18=\$D84! \ ESI TSM 18
-ESITSM19=\$D86! \ ESI TSM 19
-ESITSM20=\$D88! \ ESI TSM 20
-ESITSM21=\$D8A! \ ESI TSM 21
-ESITSM22=\$D8C! \ ESI TSM 22
-ESITSM23=\$D8E! \ ESI TSM 23
-ESITSM24=\$D90! \ ESI TSM 24
-ESITSM25=\$D92! \ ESI TSM 25
-ESITSM26=\$D94! \ ESI TSM 26
-ESITSM27=\$D96! \ ESI TSM 27
-ESITSM28=\$D98! \ ESI TSM 28
-ESITSM29=\$D9A! \ ESI TSM 29
-ESITSM30=\$D9C! \ ESI TSM 30
-ESITSM31=\$D9E! \ ESI TSM 31
-
-
-ESI_RAM=\$E00!
+
+@set-syntax{C;\;}! replace ! by semicolon
+;MSP430fr6989.pat
+
+; ----------------------------------------------
+; MSP430FR6989 MEMORY MAP
+; ----------------------------------------------
+; 0000-0005 = reserved ROM
+; 0006-001F = tiny RAM 26 bytes
+; 0020-0FFF = peripherals (4 KB)
+; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
+; 1800-19FF = FRAM INFO 512 B
+; 1A00-1AFF = TLV device descriptor info (FRAM 256 B)
+; 1B00-1BFF = ROM boot memory
+; 1C00-23FF = RAM (2 KB)
+; 4400-FF7F = code memory (FRAM 48 kB)
+; FF80-FFFF = interrupt vectors (FRAM 127 B)
+; ----------------------------------------------
+
+
+; ============================================
+; TINY RAM
+; ============================================
+TinyRAM_ORG=\$06;
+TinyRAM_LEN=\$20;
+
+; ============================================
+; BSL
+; ============================================
+BSL1=\$1000;
+
+; ============================================
+; FRAM INFO
+; ============================================
+INFO_ORG=\$1800;
+INFO_LEN=\$0200;
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; FRAM TLV
+; ============================================
+
+; See MSP430FRxxxx.pat
+
+; ============================================
+; RAM
+; ============================================
+RAM_ORG=\$1C00;
+RAM_LEN=\$0800;
+
+; ---------------------------------------
+; FORTH RAM areas :
+; ---------------------------------------
+
+; See MSP430FRxxxx.pat
+
+; ----------------------------------------------
+; FastForth RAM memory map (>= 1k):
+; ----------------------------------------------
+LEAVEPTR=\$1C00; Leave-stack pointer, init by QUIT
+LSATCK=\$1C00; leave stack, grow up
+PSTACK=\$1C80; parameter stack, grow down
+RSTACK=\$1CE0; Return stack, grow down
+;
+PAD_I2CADR=\$1CE0; RX I2C address
+PAD_I2CCNT=\$1CE2; count max
+PAD_ORG=\$1CE4; user scratch pad buffer, 84 bytes, grow up
+;
+TIB_I2CADR=\$1D38; TX I2C address
+TIB_I2CCNT=\$1D3A; count of bytes
+TIB_ORG=\$1D3C; Terminal input buffer, 84 bytes, grow up
+;
+HOLDS_ORG=\$1D90; base address for HOLDS
+HOLD_BASE=\$1DB2; BASE HOLD area, grow down
+;
+HP=\$1DB2; HOLD ptr
+STATEADR=\$1DB4; Interpreter state
+BASEADR=\$1DB6; base
+CAPS=\$1DB8; CAPS ON/OFF
+SOURCE_LEN=\$1DBA; len of input stream
+SOURCE_ORG=\$1DBC; adr of input stream
+TOIN=\$1DBE; >IN
+;
+DP=\$1DC0; dictionary ptr
+LASTVOC=\$1DC2; keep VOC-LINK
+CURRENT=\$1DC4; CURRENT dictionnary ptr
+CONTEXT=\$1DC6; CONTEXT dictionnary space (8 + Null CELLS)
+;
+; ---------------------------------------
+; RAM_ORG + $1D8 : may be shared between FORTH compiler and user application
+; ---------------------------------------
+LAST_NFA=\$1DD8;
+LAST_THREAD=\$1DDA;
+LAST_CFA=\$1DDC;
+LAST_PSP=\$1DDE;
+ASMBW1=\$1DE0; 3 backward labels
+ASMBW2=\$1DE2;
+ASMBW3=\$1DE4;
+ASMFW1=\$1DE6; 3 forward labels
+ASMFW2=\$1DE8;
+ASMFW3=\$1DEA;
+;
+; ---------------------------------------
+; RAM_ORG + $1EC RAM free
+; ---------------------------------------
+;
+; ---------------------------------------
+; RAM_ORG + $1FC: SD buffer
+; ---------------------------------------
+SD_BUF_I2ADR=\$1DFC;
+SD_BUF_I2CNT=\$1DFE;
+SD_BUF=\$1E00; \ SD_Card buffer
+BUFEND=\$2000;
+
+; ---------------------------------------
+; FAT16 FileSystemInfos
+; ---------------------------------------
+FATtype=\$2002;
+BS_FirstSectorL=\$2004;
+BS_FirstSectorH=\$2006;
+OrgFAT1=\$2008;
+FATSize=\$200A;
+OrgFAT2=\$200C;
+OrgRootDir=\$200E;
+OrgClusters=\$2010; Sector of Cluster 0
+SecPerClus=\$2012;
+
+; ---------------------------------------
+; SD command
+; ---------------------------------------
+SD_CMD_FRM=\$2014; 6 bytes SD_CMDx inverted frame \${CRC,ll,LL,hh,HH,CMD}
+SD_CMD_FRM0=\$2014; CRC:ll word access
+SD_CMD_FRM1=\$2015; ll byte access
+SD_CMD_FRM2=\$2016; LL:hh word access
+SD_CMD_FRM3=\$2017; hh byte access
+SD_CMD_FRM4=\$2018; HH:CMD word access
+SD_CMD_FRM5=\$2019; CMD byte access
+SectorL=\$201A; 2 words
+SectorH=\$201C;
+
+; ---------------------------------------
+; BUFFER management
+; ---------------------------------------
+BufferPtr=\$201E;
+BufferLen=\$2020;
+
+; ---------------------------------------
+; FAT entry
+; ---------------------------------------
+ClusterL=\$2022; 16 bits wide (FAT16)
+ClusterH=\$2024; 16 bits wide (FAT16)
+LastFATsector=\$2026; Set by FreeAllClusters, used by OPEN_OVERWRITE
+LastFAToffset=\$2028; Set by FreeAllClusters, used by OPEN_OVERWRITE
+FATsector=\$202A; used by APPEND"
+
+; ---------------------------------------
+; DIR entry
+; ---------------------------------------
+DIRclusterL=\$202C; contains the Cluster of current directory ; 1 if FAT16 root directory
+DIRclusterH=\$202E; contains the Cluster of current directory ; 1 if FAT16 root directory
+EntryOfst=\$2030;
+
+; ---------------------------------------
+; Handle Pointer
+; ---------------------------------------
+CurrentHdl=\$2032; contains the address of the last opened file structure, or 0
+
+; ---------------------------------------
+; Load file operation
+; ---------------------------------------
+pathname=\$2034;
+EndOfPath=\$2036;
+
+; ---------------------------------------
+; Handle structure
+; ---------------------------------------
+; three handle tokens :
+; token = 0 : free handle
+; token = 1 : file to read
+; token = 2 : file updated (write)
+; token =-1 : LOAD"ed file (source file)
+
+; offset values
+HDLW_PrevHDL=0; previous handle ; used by LOAD"
+HDLB_Token=2; token
+HDLB_ClustOfst=3; Current sector offset in current cluster (Byte)
+HDLL_DIRsect=4; Dir SectorL (Long)
+HDLH_DIRsect=6;
+HDLW_DIRofst=8; BUFFER offset of Dir entry
+HDLL_FirstClus=10; File First ClusterLo (identify the file)
+HDLH_FirstClus=12; File First ClusterHi (byte)
+HDLL_CurClust=14; Current ClusterLo
+HDLH_CurClust=16; Current ClusterHi (T as 3Th byte)
+HDLL_CurSize=18; written size / not yet read size (Long)
+HDLH_CurSize=20; written size / not yet read size (Long)
+HDLW_BUFofst=22; BUFFER offset ; used by LOAD" and by WRITE"
+HDLW_PrevLEN=24; previous LEN
+HDLW_PrevORG=26; previous ORG
+
+
+;OpenedFirstFile ; "openedFile" structure
+HandleMax=8;
+HandleLenght=28;
+FirstHandle=\$2038;
+HandleEnd=\$2118;
+
+;SD_card Input Buffer
+SDIB_I2CADR=\$2118;
+SDIB_I2CCNT=\$211A;
+SDIB_ORG=\$211C;
+SDIB_LEN=\$54;
+
+SD_END=\$2170;
+SD_LEN=\$16E;
+
+; ----------------------------------------------
+; FRAM
+; ----------------------------------------------
+MAIN_ORG=\$4400; Code space start
+MAIN_LEN=\$24000; 127 k FRAM
+; ----------------------------------------------
+\#LIT=\#\$4400; asm CODE run time of LITERAL
+\#XSQUOTE=\#\$4414; asm CODE run time of QUOTE
+\#MUSMOD=\#\$4428; asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD
+\#MDIV1DIV2=\#\$443A; asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/
+\#MDIV1=\#\$4442; asm CODE input for 48/16 unsigned division, see DOUBLE M*/
+\#RET_ADR=\#\$446C; asm CODE of INIT_SOFT_PFA and MARKER+8 definitions,
+\#SETIB=\#\$446E; CODE Set Input Buffer with org & len values, reset >IN pointer
+\#REFILL=\#\$447E; CODE accept one line from input and leave org len of input buffer
+\#CIB_ORG=\#\$448A; [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG
+\#QFBRAN=\#\$4496; CODE compiled by IF UNTIL
+\#BRAN=\#\$449C; CODE compiled by ELSE REPEAT AGAIN
+\#NEXT_ADR=\#\$449E; CODE NEXT instruction (MOV @IP+,PC)
+\#XDODOES=\#\$44A0; to restore rDODOES: MOV #XDODOES,rDODOES
+\#XDOCON=\#\$44AE; to restore rDOCON: MOV #XDOCON,rDOCON
+; to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR
+; to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+\#INIT_FORTH=\#\$44BA;
+\#ABORT_TERM=\#\$4500; CALL #ABORT_TERM to discard pending download
+\#UART_WARM=\#\$4572; WARM address for UART TERMINAL
+\#I2C_WARM=\#\$455C; WARM address for I2C TERMINAL
+
+; See MSP430FRxxxx.pat for other addresses
+
+; ----------------------------------------------
+; Interrupt Vectors and signatures - MSP430FR6989
+; ----------------------------------------------
+MAIN_LEN=\$1FC00; 127 k FRAM
+FRAM_FULL=\$FF40; 64 bytes are sufficient considering what can be compiled in one line and WORD use.
+SIGNATURES=\$FF80; JTAG/BSL signatures
+JTAG_SIG1=\$FF80; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
+JTAG_SIG2=\$FF82; if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD
+BSL_SIG1=\$FF84;
+BSL_SIG2=\$FF86;
+I2CSLA0=\$FFA2; UCBxI2COA0 default value address
+I2CSLA1=\$FFA4; UCBxI2COA1 default value address
+I2CSLA2=\$FFA6; UCBxI2COA2 default value address
+I2CSLA3=\$FFA8; UCBxI2COA3 default value address
+JTAG_PASSWORD=\$FF88; 256 bits
+BSL_PASSWORD=\$FFE0; 256 bits
+VECT_ORG=\$FFC6; FFC6-FFFF
+VECT_LEN=\$3A;
+
+
+AES_VEC=\$FFC6;
+RTC_VEC=\$FFC8;
+LCD_VEC=\$FFCA;
+P4_VEC=\$FFCC;
+P3_VEC=\$FFCE;
+TA3_X_VEC=\$FFD0;
+TA3_0_VEC=\$FFD2;
+P2_VEC=\$FFD4;
+TA2_X_VEC=\$FFD6;
+TA2_0_VEC=\$FFD8;
+P1_VEC=\$FFDA;
+TA1_X_VEC=\$FFDC;
+TA1_0_VEC=\$FFDE;
+DMA_VEC=\$FFE0;
+EUSCI_B1_VEC=\$FFE2;
+EUSCI_A1_VEC=\$FFE4;
+TA0_X_VEC=\$FFE6;
+TA0_0_VEC=\$FFE8;
+ADC12_B_VEC=\$FFEA;
+EUSCI_B0_VEC=\$FFEC;
+EUSCI_A0_VEC=\$FFEE;
+ESI_VEC=\$FFF0;
+WDT_VEC=\$FFF2;
+TB0_X_VEC=\$FFF4;
+TB0_0_VEC=\$FFF6;
+COMP_E_VEC=\$FFF8;
+U_NMI_VEC=\$FFFA;
+S_NMI_VEC=\$FFFC;
+RST_VEC=\$FFFE;
+
+; ============================================
+; Special Fonction Registers (SFR)
+; ============================================
+
+SFRIE1=\$100; \ SFR enable register
+SFRIFG1=\$102; \ SFR flag register
+SFRRPCR=\$104; \ SFR reset pin control
+
+PMMCTL0=\$120; \ PMM Control 0
+PMMIFG=\$12A; \ PMM interrupt flags
+PM5CTL0=\$130; \ PM5 Control 0
+
+FRCTLCTL0=\$140; \ FRAM control 0
+GCCTL0=\$144; \ General control 0
+GCCTL1=\$146; \ General control 1
+
+CRC16DI=\$150; \ CRC data input
+CRCDIRB=\$152; \ CRC data input reverse byte
+CRCINIRES=\$154; \ CRC initialization and result
+CRCRESR=\$156; \ CRC result reverse byte
+
+RCCTL0=\$158; \ RAM controller control 0
+
+WDTCTL=\$15C; \ WDT control register
+
+CSCTL0=\$160; \ CS control 0
+CSCTL1=\$162; \ CS control 1
+CSCTL2=\$164; \ CS control 2
+CSCTL3=\$166; \ CS control 3
+CSCTL4=\$168; \ CS control 4
+CSCTL5=\$16A; \ CS control 5
+CSCTL6=\$16C; \ CS control 6
+
+SYSCTL=\$180; \ System control
+SYSJMBC=\$186; \ JTAG mailbox control
+SYSJMBI0=\$188; \ JTAG mailbox input 0
+SYSJMBI1=\$18A; \ JTAG mailbox input 1
+SYSJMBO0=\$18C; \ JTAG mailbox output 0
+SYSJMBO1=\$18E; \ JTAG mailbox output 1
+SYSUNIV=\$19A; \ User NMI vector generator
+SYSSNIV=\$19C; \ System NMI vector generator
+SYSRSTIV=\$19E; \ Reset vector generator
+
+REFCTL=\$1B0; \ Shared reference control
+
+PAIN=\$200;
+PAOUT=\$202;
+PADIR=\$204;
+PAREN=\$206;
+PASEL0=\$20A;
+PASEL1=\$20C;
+PASELC=\$216;
+PAIES=\$218;
+PAIE=\$21A;
+PAIFG=\$21C;
+
+P1IN=\$200;
+P1OUT=\$202;
+P1DIR=\$204;
+P1REN=\$206;
+P1SEL0=\$20A;
+P1SEL1=\$20C;
+P1IV=\$20E;
+P1SELC=\$216;
+P1IES=\$218;
+P1IE=\$21A;
+P1IFG=\$21C;
+
+P2IN=\$201;
+P2OUT=\$203;
+P2DIR=\$205;
+P2REN=\$207;
+P2SEL0=\$20B;
+P2SEL1=\$20D;
+P2SELC=\$217;
+P2IES=\$219;
+P2IE=\$21B;
+P2IFG=\$21D;
+P2IV=\$21E;
+
+PBIN=\$220;
+PBOUT=\$222;
+PBDIR=\$224;
+PBREN=\$226;
+PBSEL0=\$22A;
+PBSEL1=\$22C;
+PBSELC=\$236;
+PBIES=\$238;
+PBIE=\$23A;
+PBIFG=\$23C;
+
+P3IN=\$220;
+P3OUT=\$222;
+P3DIR=\$224;
+P3REN=\$226;
+P3SEL0=\$22A;
+P3SEL1=\$22C;
+P3IV=\$22E;
+P3SELC=\$236;
+P3IES=\$238;
+P3IE=\$23A;
+P3IFG=\$23C;
+
+P4IN=\$221;
+P4OUT=\$223;
+P4DIR=\$225;
+P4REN=\$227;
+P4SEL0=\$22B;
+P4SEL1=\$22D;
+P4SELC=\$237;
+P4IES=\$239;
+P4IE=\$23B;
+P4IFG=\$23D;
+P4IV=\$23E;
+
+PCIN=\$240;
+PCOUT=\$242;
+PCDIR=\$244;
+PCREN=\$246;
+PCSEL0=\$24A;
+PCSEL1=\$24C;
+PCSELC=\$256;
+
+P5IN=\$240;
+P5OUT=\$242;
+P5DIR=\$244;
+P5REN=\$246;
+P5SEL0=\$24A;
+P5SEL1=\$24C;
+P5SELC=\$256;
+
+P6IN=\$241;
+P6OUT=\$243;
+P6DIR=\$245;
+P6REN=\$247;
+P6SEL0=\$24B;
+P6SEL1=\$24D;
+P6SELC=\$257;
+
+PDIN=\$260;
+PDOUT=\$262;
+PDDIR=\$264;
+PDREN=\$266;
+PDSEL0=\$26A;
+PDSEL1=\$26C;
+PDSELC=\$276;
+
+P7IN=\$260;
+P7OUT=\$262;
+P7DIR=\$264;
+P7REN=\$266;
+P7SEL0=\$26A;
+P7SEL1=\$26C;
+P7SELC=\$276;
+
+P8IN=\$261;
+P8OUT=\$263;
+P8DIR=\$265;
+P8REN=\$267;
+P8SEL0=\$26B;
+P8SEL1=\$26D;
+P8SELC=\$277;
+
+PEIN=\$280;
+PEOUT=\$282;
+PEDIR=\$284;
+PEREN=\$286;
+PESEL0=\$28A;
+PESEL1=\$28C;
+PESELC=\$296;
+
+P9IN=\$280;
+P9OUT=\$282;
+P9DIR=\$284;
+P9REN=\$286;
+P9SEL0=\$28A;
+P9SEL1=\$28C;
+P9SELC=\$296;
+
+P10IN=\$281;
+P10OUT=\$283;
+P10DIR=\$285;
+P10REN=\$287;
+P10SEL0=\$28B;
+P10SEL1=\$28D;
+P10SELC=\$297;
+
+PJIN=\$320;
+PJOUT=\$322;
+PJDIR=\$324;
+PJREN=\$326;
+PJSEL0=\$32A;
+PJSEL1=\$32C;
+PJSELC=\$336;
+
+
+TACLR=4;
+TAIFG=1;
+TBCLR=2;
+TBIFG=1;
+CCIFG=1;
+
+TA0CTL=\$340; \ TA0 control
+TA0CCTL0=\$342; \ Capture/compare control 0
+TA0CCTL1=\$344; \ Capture/compare control 1
+TA0CCTL2=\$346; \ Capture/compare control 2
+TA0CCTL3=\$348; \ Capture/compare control 3
+TA0CCTL4=\$34A; \ Capture/compare control 4
+TA0R=\$350; \ TA0 counter register
+TA0CCR0=\$352; \ Capture/compare register 0
+TA0CCR1=\$354; \ Capture/compare register 1
+TA0CCR2=\$356; \ Capture/compare register 2
+TA0CCR2=\$358; \ Capture/compare register 3
+TA0CCR2=\$35A; \ Capture/compare register 4
+TA0EX0=\$360; \ TA0 expansion register 0
+TA0IV=\$36E; \ TA0 interrupt vector
+
+TA1CTL=\$380; \ TA1 control
+TA1CCTL0=\$382; \ Capture/compare control 0
+TA1CCTL1=\$384; \ Capture/compare control 1
+TA1CCTL2=\$386; \ Capture/compare control 2
+TA1R=\$390; \ TA1 counter register
+TA1CCR0=\$392; \ Capture/compare register 0
+TA1CCR1=\$394; \ Capture/compare register 1
+TA1CCR2=\$396; \ Capture/compare register 2
+TA1EX0=\$3A0; \ TA1 expansion register 0
+TA1IV=\$3AE; \ TA1 interrupt vector
+
+TB0CTL=\$3C0; \ TB0 control
+TB0CCTL0=\$3C2; \ Capture/compare control 0
+TB0CCTL1=\$3C4; \ Capture/compare control 1
+TB0CCTL2=\$3C6; \ Capture/compare control 2
+TB0CCTL3=\$3C8; \ Capture/compare control 3
+TB0CCTL4=\$3CA; \ Capture/compare control 4
+TB0CCTL5=\$3CC; \ Capture/compare control 5
+TB0CCTL6=\$3CE; \ Capture/compare control 6
+TB0R=\$3D0; \ TB0 counter register
+TB0CCR0=\$3D2; \ Capture/compare register 0
+TB0CCR1=\$3D4; \ Capture/compare register 1
+TB0CCR2=\$3D6; \ Capture/compare register 2
+TB0CCR3=\$3D8; \ Capture/compare register 3
+TB0CCR5=\$3DA; \ Capture/compare register 4
+TB0CCR5=\$3DC; \ Capture/compare register 5
+TB0CCR6=\$3DE; \ Capture/compare register 6
+TB0EX0=\$3E0; \ TB0 expansion register 0
+TB0IV=\$3EE; \ TB0 interrupt vector
+
+TA2CTL=\$400; \ TA2 control
+TA2CCTL0=\$402; \ Capture/compare control 0
+TA2CCTL1=\$404; \ Capture/compare control 1
+TA2R=\$410; \ TA2 counter register
+TA2CCR0=\$412; \ Capture/compare register 0
+TA2CCR1=\$414; \ Capture/compare register 1
+TA2EX0=\$420; \ TA2 expansion register 0
+TA2IV=\$42E; \ TA2 interrupt vector
+
+CAPTIO0CTL=\$43E; \ Capacitive Touch IO 0 control
+
+TA3CTL=\$440; \ TA3 control
+TA3CCTL0=\$442; \ Capture/compare control 0
+TA3CCTL1=\$444; \ Capture/compare control 1
+TA3CCTL2=\$446; \ Capture/compare control 2
+TA3CCTL3=\$448; \ Capture/compare control 3
+TA3CCTL4=\$44A; \ Capture/compare control 4
+TA3R=\$450; \ TA3 counter register
+TA3CCR0=\$452; \ Capture/compare register 0
+TA3CCR1=\$454; \ Capture/compare register 1
+TA3CCR2=\$456; \ Capture/compare register 2
+TA3CCR3=\$458; \ Capture/compare register 3
+TA3CCR4=\$45A; \ Capture/compare register 4
+TA3EX0=\$460; \ TA3 expansion register 0
+TA3IV=\$46E; \ TA3 interrupt vector
+
+CAPTIO1CTL=\$47E; \ Capacitive Touch IO 1 control
+
+; \ RTC_C
+RTCCTL0_L=\$4A0; \ RTCCTL0_L
+RTCCTL0_H=\$4A1; \ RTCCTL0_H
+RTCCTL1=\$4A2; \ RTCCTL1
+RTCCTL3=\$4A3; \ RTCCTL3
+RTCPS0CTL=\$4A8; \ RTC prescaler 0 control
+RTCPS1CTL=\$4AA; \ RTC prescaler 1 control
+RTCPS=\$4AC; \ RTC prescaler
+RT0PS=\$4AC; \ RTC prescaler 0
+RT1PS=\$4AD; \ RTC prescaler 1
+RTCIV=\$4AE; \ RTC interrupt vector word
+RTCSEC=\$4B0; \ RTC seconds, RTC counter register 1 RTCSEC,
+RTCCNT1=\$4B0; \ Real-Time Counter 1
+RTCMIN=\$4B1; \ RTC minutes, RTC counter register 2 RTCMIN,
+RTCCNT2=\$4B1; \ Real-Time Counter 2
+RTCHOUR=\$4B2; \ RTC hours, RTC counter register 3 RTCHOUR,
+RTCCNT3=\$4B2; \ Real-Time Counter 3
+RTCDOW=\$4B3; \ RTC day of week, RTC counter register 4 RTCDOW,
+RTCCNT4=\$4B3; \ Real-Time Counter 4
+RTCDAY=\$4B4; \ RTC days
+RTCMON=\$4B5; \ RTC month
+RTCYEAR=\$4B6;
+RTCYEARL=\$4B6; \ RTC year low
+RTCYEARH=\$4B7; \ RTC year high
+RTCAMIN=\$4B8; \ RTC alarm minutes
+RTCAHOUR=\$4B9; \ RTC alarm hours
+RTCADOW=\$4BA; \ RTC alarm day of week
+RTCADAY=\$4BB; \ RTC alarm days
+BIN2BCD=\$4BC; \ Binary-to-BCD conversion register
+BCD2BIN=\$4BE; \ BCD-to-binary conversion register
+
+RTCHOLD=\$40;
+RTCRDY=\$10;
+
+MPY=\$4C0; \ 16-bit operand 1 - multiply
+MPYS=\$4C2; \ 16-bit operand 1 - signed multiply
+MAC=\$4C4; \ 16-bit operand 1 - multiply accumulate
+MACS=\$4C6; \ 16-bit operand 1 - signed multiply accumulate
+OP2=\$4C8; \ 16-bit operand 2
+RESLO=\$4CA; \ 16 x 16 result low word
+RESHI=\$4CC; \ 16 x 16 result high word
+SUMEXT=\$4CE; \ 16 x 16 sum extension register
+MPY32L=\$4D0; \ 32-bit operand 1 - multiply low word
+MPY32H=\$4D2; \ 32-bit operand 1 - multiply high word
+MPYS32L=\$4D4; \ 32-bit operand 1 - signed multiply low word
+MPYS32H=\$4D6; \ 32-bit operand 1 - signed multiply high word
+MAC32L=\$4D8; \ 32-bit operand 1 - multiply accumulate low word
+MAC32H=\$4DA; \ 32-bit operand 1 - multiply accumulate high word
+MACS32L=\$4DC; \ 32-bit operand 1 - signed multiply accumulate low word
+MACS32H=\$4DE; \ 32-bit operand 1 - signed multiply accumulate high word
+OP2L=\$4E0; \ 32-bit operand 2 - low word
+OP2H=\$4E2; \ 32-bit operand 2 - high word
+RES0=\$4E4; \ 32 x 32 result 0 - least significant word
+RES1=\$4E6; \ 32 x 32 result 1
+RES2=\$4E8; \ 32 x 32 result 2
+RES3=\$4EA; \ 32 x 32 result 3 - most significant word
+MPY32CTL0=\$4EC; \ MPY32 control register 0
+
+DMAIFG=8;
+
+DMACTL0=\$500; \ DMA module control 0
+DMACTL1=\$502; \ DMA module control 1
+DMACTL2=\$504; \ DMA module control 2
+DMACTL3=\$506; \ DMA module control 3
+DMACTL4=\$508; \ DMA module control 4
+DMAIV=\$50A; \ DMA interrupt vector
+
+DMA0CTL=\$510; \ DMA channel 0 control
+DMA0SAL=\$512; \ DMA channel 0 source address low
+DMA0SAH=\$514; \ DMA channel 0 source address high
+DMA0DAL=\$516; \ DMA channel 0 destination address low
+DMA0DAH=\$518; \ DMA channel 0 destination address high
+DMA0SZ=\$51A; \ DMA channel 0 transfer size
+
+DMA1CTL=\$520; \ DMA channel 1 control
+DMA1SAL=\$522; \ DMA channel 1 source address low
+DMA1SAH=\$524; \ DMA channel 1 source address high
+DMA1DAL=\$526; \ DMA channel 1 destination address low
+DMA1DAH=\$528; \ DMA channel 1 destination address high
+DMA1SZ=\$52A; \ DMA channel 1 transfer size
+
+DMA2CTL=\$530; \ DMA channel 2 control
+DMA2SAL=\$532; \ DMA channel 2 source address low
+DMA2SAH=\$534; \ DMA channel 2 source address high
+DMA2DAL=\$536; \ DMA channel 2 destination address low
+DMA2DAH=\$538; \ DMA channel 2 destination address high
+DMA2SZ=\$53A; \ DMA channel 2 transfer size
+
+
+MPUCTL0=\$5A0; \ MPU control 0
+MPUCTL1=\$5A2; \ MPU control 1
+MPUSEGB2=\$5A4; \ MPU Segmentation Border2
+MPUSEGB1=\$5A6; \ MPU Segmentation Border1
+MPUSAM=\$5A8; \ MPU access management
+MPUIPC0=\$5AA; \ MPU IP control 0
+MPUIPSEGB2=\$5AC; \ MPU IP Encapsulation Segment Border 2
+MPUIPSEGB1=\$5AE; \ MPU IP Encapsulation Segment Border 1
+
+UCA0CTLW0=\$5C0; \ eUSCI_A control word 0
+UCA0CTLW1=\$5C2; \ eUSCI_A control word 1
+UCA0BRW=\$5C6;
+UCA0BR0=\$5C6; \ eUSCI_A baud rate 0
+UCA0BR1=\$5C7; \ eUSCI_A baud rate 1
+UCA0MCTLW=\$5C8; \ eUSCI_A modulation control
+UCA0STAT=\$5CA; \ eUSCI_A status
+UCA0RXBUF=\$5CC; \ eUSCI_A receive buffer
+UCA0TXBUF=\$5CE; \ eUSCI_A transmit buffer
+UCA0ABCTL=\$5D0; \ eUSCI_A LIN control
+UCA0IRTCTL=\$5D2; \ eUSCI_A IrDA transmit control
+UCA0IRRCTL=\$5D3; \ eUSCI_A IrDA receive control
+UCA0IE=\$5DA; \ eUSCI_A interrupt enable
+UCA0IFG=\$5DC; \ eUSCI_A interrupt flags
+UCA0IV=\$5DE; \ eUSCI_A interrupt vector word
+
+UCA1CTLW0=\$5E0; \ eUSCI_A control word 0
+UCA1CTLW1=\$5E2; \ eUSCI_A control word 1
+UCA1BRW=\$5E6;
+UCA1BR0=\$5E6; \ eUSCI_A baud rate 0
+UCA1BR1=\$5E7; \ eUSCI_A baud rate 1
+UCA1MCTLW=\$5E8; \ eUSCI_A modulation control
+UCA1STAT=\$5EA; \ eUSCI_A status
+UCA1RXBUF=\$5EC; \ eUSCI_A receive buffer
+UCA1TXBUF=\$5EE; \ eUSCI_A transmit buffer
+UCA1ABCTL=\$5F0; \ eUSCI_A LIN control
+UCA1IRTCTL=\$5F2; \ eUSCI_A IrDA transmit control
+UCA1IRRCTL=\$5F3; \ eUSCI_A IrDA receive control
+UCA1IE=\$5FA; \ eUSCI_A interrupt enable
+UCA1IFG=\$5FC; \ eUSCI_A interrupt flags
+UCA1IV=\$5FE; \ eUSCI_A interrupt vector word
+
+
+UCB0CTLW0=\$640; \ eUSCI_B control word 0
+UCB0CTLW1=\$642; \ eUSCI_B control word 1
+UCB0BRW=\$646;
+UCB0BR0=\$646; \ eUSCI_B bit rate 0
+UCB0BR1=\$647; \ eUSCI_B bit rate 1
+UCB0STATW=\$648; \ eUSCI_B status word
+UCBCNT0=\$649; \ eUSCI_B hardware count
+UCB0TBCNT=\$64A; \ eUSCI_B byte counter threshold
+UCB0RXBUF=\$64C; \ eUSCI_B receive buffer
+UCB0TXBUF=\$64E; \ eUSCI_B transmit buffer
+UCB0I2COA0=\$654; \ eUSCI_B I2C own address 0
+UCB0I2COA1=\$656; \ eUSCI_B I2C own address 1
+UCB0I2COA2=\$658; \ eUSCI_B I2C own address 2
+UCB0I2COA3=\$65A; \ eUSCI_B I2C own address 3
+UCB0ADDRX=\$65C; \ eUSCI_B received address
+UCB0ADDMASK=\$65E; \ eUSCI_B address mask
+UCB0I2CSA=\$660; \ eUSCI I2C slave address
+UCB0IE=\$66A; \ eUSCI interrupt enable
+UCB0IFG=\$66C; \ eUSCI interrupt flags
+UCB0IV=\$66E; \ eUSCI interrupt vector word
+
+UCB1CTLW0=\$680; \ eUSCI_B control word 0
+UCB1CTLW1=\$682; \ eUSCI_B control word 1
+UCB1BRW=\$686;
+UCB1BR0=\$686; \ eUSCI_B bit rate 0
+UCB1BR1=\$687; \ eUSCI_B bit rate 1
+UCB1STATW=\$688; \ eUSCI_B status word
+UCB1NT0=\$689; \ eUSCI_B hardware count
+UCB1TBCNT=\$68A; \ eUSCI_B byte counter threshold
+UCB1RXBUF=\$68C; \ eUSCI_B receive buffer
+UCB1TXBUF=\$68E; \ eUSCI_B transmit buffer
+UCB1I2COA0=\$694; \ eUSCI_B I2C own address 0
+UCB1I2COA1=\$696; \ eUSCI_B I2C own address 1
+UCB1I2COA2=\$698; \ eUSCI_B I2C own address 2
+UCB1I2COA3=\$69A; \ eUSCI_B I2C own address 3
+UCB1ADDRX=\$69C; \ eUSCI_B received address
+UCB1ADDMASK=\$69E; \ eUSCI_B address mask
+UCB1I2CSA=\$6A0; \ eUSCI I2C slave address
+UCB1IE=\$6AA; \ eUSCI interrupt enable
+UCB1IFG=\$6AC; \ eUSCI interrupt flags
+UCB1IV=\$6AE; \ eUSCI interrupt vector word
+
+UCTXACK=\$20;
+UCTR=\$10;
+
+
+ADC12CTL0=\$800; \ ADC12_B Control 0
+ADC12CTL1=\$802; \ ADC12_B Control 1
+ADC12CTL2=\$804; \ ADC12_B Control 2
+ADC12CTL3=\$806; \ ADC12_B Control 3
+ADC12LO=\$808; \ ADC12_B Window Comparator Low Threshold Register
+ADC12HI=\$80A; \ ADC12_B Window Comparator High Threshold Register
+ADC12IFGR0=\$80C; \ ADC12_B Interrupt Flag Register 0
+ADC12IFGR1=\$80E; \ ADC12_B Interrupt Flag Register 1
+ADC12IFGR2=\$810; \ ADC12_B Interrupt Flag Register 2
+ADC12IER0=\$812; \ ADC12_B Interrupt Enable Register 0
+ADC12IER1=\$814; \ ADC12_B Interrupt Enable Register 1
+ADC12IER2=\$816; \ ADC12_B Interrupt Enable Register 2
+ADC12IV=\$818; \ ADC12_B Interrupt Vector
+ADC12MCTL0=\$820; \ ADC12_B Memory Control 0
+ADC12MCTL1=\$822; \ ADC12_B Memory Control 1
+ADC12MCTL2=\$824; \ ADC12_B Memory Control 2
+ADC12MCTL3=\$826; \ ADC12_B Memory Control 3
+ADC12MCTL4=\$828; \ ADC12_B Memory Control 4
+ADC12MCTL5=\$82A; \ ADC12_B Memory Control 5
+ADC12MCTL6=\$82C; \ ADC12_B Memory Control 6
+ADC12MCTL7=\$82E; \ ADC12_B Memory Control 7
+ADC12MCTL8=\$830; \ ADC12_B Memory Control 8
+ADC12MCTL9=\$832; \ ADC12_B Memory Control 9
+ADC12MCTL10=\$834; \ ADC12_B Memory Control 10
+ADC12MCTL11=\$836; \ ADC12_B Memory Control 11
+ADC12MCTL12=\$838; \ ADC12_B Memory Control 12
+ADC12MCTL13=\$83A; \ ADC12_B Memory Control 13
+ADC12MCTL14=\$83C; \ ADC12_B Memory Control 14
+ADC12MCTL15=\$83E; \ ADC12_B Memory Control 15
+ADC12MCTL16=\$840; \ ADC12_B Memory Control 16
+ADC12MCTL17=\$842; \ ADC12_B Memory Control 17
+ADC12MCTL18=\$844; \ ADC12_B Memory Control 18
+ADC12MCTL19=\$846; \ ADC12_B Memory Control 19
+ADC12MCTL20=\$848; \ ADC12_B Memory Control 20
+ADC12MCTL21=\$84A; \ ADC12_B Memory Control 21
+ADC12MCTL22=\$84C; \ ADC12_B Memory Control 22
+ADC12MCTL23=\$84E; \ ADC12_B Memory Control 23
+ADC12MCTL24=\$850; \ ADC12_B Memory Control 24
+ADC12MCTL25=\$852; \ ADC12_B Memory Control 25
+ADC12MCTL26=\$854; \ ADC12_B Memory Control 26
+ADC12MCTL27=\$856; \ ADC12_B Memory Control 27
+ADC12MCTL28=\$858; \ ADC12_B Memory Control 28
+ADC12MCTL29=\$85A; \ ADC12_B Memory Control 29
+ADC12MCTL30=\$85C; \ ADC12_B Memory Control 30
+ADC12MCTL31=\$85E; \ ADC12_B Memory Control 31
+ADC12MEM0=\$860; \ ADC12_B Memory 0
+ADC12MEM1=\$862; \ ADC12_B Memory 1
+ADC12MEM2=\$864; \ ADC12_B Memory 2
+ADC12MEM3=\$866; \ ADC12_B Memory 3
+ADC12MEM4=\$868; \ ADC12_B Memory 4
+ADC12MEM5=\$86A; \ ADC12_B Memory 5
+ADC12MEM6=\$86C; \ ADC12_B Memory 6
+ADC12MEM7=\$86E; \ ADC12_B Memory 7
+ADC12MEM8=\$870; \ ADC12_B Memory 8
+ADC12MEM9=\$872; \ ADC12_B Memory 9
+ADC12MEM10=\$874; \ ADC12_B Memory 10
+ADC12MEM11=\$876; \ ADC12_B Memory 11
+ADC12MEM12=\$878; \ ADC12_B Memory 12
+ADC12MEM13=\$87A; \ ADC12_B Memory 13
+ADC12MEM14=\$87C; \ ADC12_B Memory 14
+ADC12MEM15=\$87E; \ ADC12_B Memory 15
+ADC12MEM16=\$880; \ ADC12_B Memory 16
+ADC12MEM17=\$882; \ ADC12_B Memory 17
+ADC12MEM18=\$884; \ ADC12_B Memory 18
+ADC12MEM19=\$886; \ ADC12_B Memory 19
+ADC12MEM20=\$888; \ ADC12_B Memory 20
+ADC12MEM21=\$88A; \ ADC12_B Memory 21
+ADC12MEM22=\$88C; \ ADC12_B Memory 22
+ADC12MEM23=\$88E; \ ADC12_B Memory 23
+ADC12MEM24=\$890; \ ADC12_B Memory 24
+ADC12MEM25=\$892; \ ADC12_B Memory 25
+ADC12MEM26=\$894; \ ADC12_B Memory 26
+ADC12MEM27=\$896; \ ADC12_B Memory 27
+ADC12MEM28=\$898; \ ADC12_B Memory 28
+ADC12MEM29=\$89A; \ ADC12_B Memory 29
+ADC12MEM30=\$89C; \ ADC12_B Memory 30
+ADC12MEM31=\$89E; \ ADC12_B Memory 31
+
+ADCON=\$10;
+ADCSTART=\$03;
+
+CDIFG=1;
+CDIIFG=2;
+
+CDCTL0=\$8C0; \ Comparator_E control register 0
+CDCTL1=\$8C2; \ Comparator_E control register 1
+CDCTL2=\$8C4; \ Comparator_E control register 2
+CDCTL3=\$8C6; \ Comparator_E control register 3
+CDINT=\$8CC; \ Comparator_E interrupt register
+CDIV=\$8CE; \ Comparator_E interrupt vector word
+
+CRC32DIW0=\$980; \ CRC32 data input
+CRC32DIRBW0=\$986; \ CRC32 data input reverse
+CRC32INIRESW0=\$988; \ CRC32 initialization and result word 0
+CRC32INIRESW1=\$98A; \ CRC32 initialization and result word 1
+CRC32RESRW1=\$98; \ CRC32 result reverse word 1
+CRC32RESRW1=\$98E; \ CRC32 result reverse word 0
+CRC16DIW0=\$990; \ CRC16 data input
+CRC16DIRBW0=\$996; \ CRC16 data input reverse
+CRC16INIRESW0=\$998; \ CRC16 initialization and result word 0
+CRC16RESRW1=\$99E; \ CRC16 result reverse word 0
+
+
+AESACTL0=\$9C0; \ AES accelerator control register 0
+AESASTAT=\$9C4; \ AES accelerator status register
+AESAKEY=\$9C6; \ AES accelerator key register
+AESADIN=\$9C8; \ AES accelerator data in register
+AESADOUT=\$9CA; \ AES accelerator data out register
+AESAXDIN=\$9CC; \ AES accelerator XORed data in register
+AESAXIN =\$9CE; \ AES accelerator XORed data in register (no trigger)
+
+
+LCDCCTL0=\$A00; \ LCD_C control register 0
+LCDCCTL1=\$A02; \ LCD_C control register 1
+LCDCBLKCTL=\$A04; \ LCD_C blinking control register
+LCDCMEMCTL=\$A06; \ LCD_C memory control register
+LCDCVCTL=\$A08; \ LCD_C voltage control register
+LCDCPCTL0=\$A0A; \ LCD_C port control 0
+LCDCPCTL1=\$A0C; \ LCD_C port control 1
+LCDCPCTL2=\$A0E; \ LCD_C port control 2
+LCDCCPCTL=\$A12; \ LCD_C charge pump ctrl register
+LCDCIV=\$A1E; \ LCD_C interrupt vector
+LCDM1=\$A20; \ LCD_C memory 1
+LCDM2=\$A21; \ LCD_C memory 2
+LCDM3=\$A22; \ LCD_C memory 3
+LCDM4=\$A23; \ LCD_C memory 4
+LCDM5=\$A24; \ LCD_C memory 5
+LCDM6=\$A25; \ LCD_C memory 6
+LCDM7=\$A26; \ LCD_C memory 7
+LCDM8=\$A27; \ LCD_C memory 8
+LCDM9=\$A28; \ LCD_C memory 9
+LCDM10=\$A29; \ LCD_C memory 10
+LCDM11=\$A2A; \ LCD_C memory 11
+LCDM12=\$A2B; \ LCD_C memory 12
+LCDM13=\$A2C; \ LCD_C memory 13
+LCDM14=\$A2D; \ LCD_C memory 14
+LCDM15=\$A2E; \ LCD_C memory 15
+LCDM16=\$A2F; \ LCD_C memory 16
+LCDM17=\$A30; \ LCD_C memory 17
+LCDM18=\$A31; \ LCD_C memory 18
+LCDM19=\$A32; \ LCD_C memory 19
+LCDM20=\$A33; \ LCD_C memory 20
+LCDM21=\$A34; \ LCD_C memory 21
+LCDM22=\$A35; \ LCD_C memory 22
+LCDM23=\$A36; \ LCD_C memory 23
+LCDM24=\$A37; \ LCD_C memory 24
+LCDM25=\$A38; \ LCD_C memory 25
+LCDM26=\$A39; \ LCD_C memory 26
+LCDM27=\$A3A; \ LCD_C memory 27
+LCDM28=\$A3B; \ LCD_C memory 28
+LCDM29=\$A3C; \ LCD_C memory 29
+LCDM30=\$A3D; \ LCD_C memory 30
+LCDM31=\$A3E; \ LCD_C memory 31
+LCDM32=\$A3F; \ LCD_C memory 32
+LCDM33=\$A40; \ LCD_C memory 33
+LCDM34=\$A41; \ LCD_C memory 34
+LCDM35=\$A42; \ LCD_C memory 35
+LCDM36=\$A43; \ LCD_C memory 36
+LCDM37=\$A44; \ LCD_C memory 37
+LCDM38=\$A45; \ LCD_C memory 38
+LCDM39=\$A46; \ LCD_C memory 39
+LCDM40=\$A47; \ LCD_C memory 40
+LCDM41=\$A48; \ LCD_C memory 41
+LCDM42=\$A49; \ LCD_C memory 42
+LCDM43=\$A4A; \ LCD_C memory 43
+LCDBM1=\$A40; \ LCD_C blinking memory 1
+LCDBM2=\$A41; \ LCD_C blinking memory 2
+LCDBM3=\$A42; \ LCD_C blinking memory 3
+LCDBM4=\$A43; \ LCD_C blinking memory 4
+LCDBM5=\$A44; \ LCD_C blinking memory 5
+LCDBM6=\$A45; \ LCD_C blinking memory 6
+LCDBM7=\$A46; \ LCD_C blinking memory 7
+LCDBM8=\$A47; \ LCD_C blinking memory 8
+LCDBM9=\$A48; \ LCD_C blinking memory 9
+LCDBM10=\$A49; \ LCD_C blinking memory 10
+LCDBM11=\$A4A; \ LCD_C blinking memory 11
+LCDBM12=\$A4B; \ LCD_C blinking memory 12
+LCDBM13=\$A4C; \ LCD_C blinking memory 13
+LCDBM14=\$A4D; \ LCD_C blinking memory 14
+LCDBM15=\$A4E; \ LCD_C blinking memory 15
+LCDBM16=\$A4F; \ LCD_C blinking memory 16
+LCDBM17=\$A50; \ LCD_C blinking memory 17
+LCDBM18=\$A51; \ LCD_C blinking memory 18
+LCDBM19=\$A52; \ LCD_C blinking memory 19
+LCDBM20=\$A53; \ LCD_C blinking memory 20
+LCDBM21=\$A54; \ LCD_C blinking memory 21
+LCDBM22=\$A55; \ LCD_C blinking memory 22
+
+
+ESIDEBUG1=\$D00; \ ESI debug register 1
+ESIDEBUG2=\$D02; \ ESI debug register 2
+ESIDEBUG3=\$D04; \ ESI debug register 3
+ESIDEBUG4=\$D06; \ ESI debug register 4
+ESIDEBUG5=\$D08; \ ESI debug register 5
+ESICNT0=\$D10; \ ESI PSM counter 0
+ESICNT1=\$D12; \ ESI PSM counter 1
+ESICNT2=\$D14; \ ESI PSM counter 2
+ESICNT3=\$D16; \ ESI oscillator counter register
+ESIIV=\$D1A; \ ESI interrupt vector
+ESIINT1=\$D1C; \ ESI interrupt register 1
+ESIINT2=\$D1E; \ ESI interrupt register 2
+ESIAFE=\$D20; \ ESI AFE control register
+ESIPPU=\$D22; \ ESI PPU control register
+ESITSM=\$D24; \ ESI TSM control register
+ESIPSM=\$D26; \ ESI PSM control register
+ESIOSC=\$D28; \ ESI oscillator control register
+ESICTL=\$D2A; \ ESI control register
+ESITHR1=\$D2C; \ ESI PSM counter threshold register 1
+ESITHR2=\$D2E; \ ESI PSM counter threshold register 2
+ESIADMEM1=\$D30; \ ESI A/D conversion memory 1
+ESIADMEM2=\$D32; \ ESI A/D conversion memory 2
+ESIADMEM3=\$D34; \ ESI A/D conversion memory 3
+ESIADMEM4=\$D36; \ ESI A/D conversion memory 4
+ESIDAC1R0=\$D40; \ ESI DAC1 register 0
+ESIDAC1R1=\$D42; \ ESI DAC1 register 1
+ESIDAC1R2=\$D44; \ ESI DAC1 register 2
+ESIDAC1R3=\$D46; \ ESI DAC1 register 3
+ESIDAC1R4=\$D48; \ ESI DAC1 register 4
+ESIDAC1R5=\$D4A; \ ESI DAC1 register 5
+ESIDAC1R6=\$D4C; \ ESI DAC1 register 6
+ESIDAC1R7=\$D4E; \ ESI DAC1 register 7
+ESIDAC2R0=\$D50; \ ESI DAC2 register 0
+ESIDAC2R1=\$D52; \ ESI DAC2 register 1
+ESIDAC2R2=\$D54; \ ESI DAC2 register 2
+ESIDAC2R3=\$D56; \ ESI DAC2 register 3
+ESIDAC2R4=\$D58; \ ESI DAC2 register 4
+ESIDAC2R5=\$D5A; \ ESI DAC2 register 5
+ESIDAC2R6=\$D5C; \ ESI DAC2 register 6
+ESIDAC2R7=\$D5E; \ ESI DAC2 register 7
+ESITSM0=\$D60; \ ESI TSM 0
+ESITSM1=\$D62; \ ESI TSM 1
+ESITSM2=\$D64; \ ESI TSM 2
+ESITSM3=\$D66; \ ESI TSM 3
+ESITSM4=\$D68; \ ESI TSM 4
+ESITSM5=\$D6A; \ ESI TSM 5
+ESITSM6=\$D6C; \ ESI TSM 6
+ESITSM7=\$D6E; \ ESI TSM 7
+ESITSM8=\$D70; \ ESI TSM 8
+ESITSM9=\$D72; \ ESI TSM 9
+ESITSM10=\$D74; \ ESI TSM 10
+ESITSM11=\$D76; \ ESI TSM 11
+ESITSM12=\$D78; \ ESI TSM 12
+ESITSM13=\$D7A; \ ESI TSM 13
+ESITSM14=\$D7C; \ ESI TSM 14
+ESITSM15=\$D7E; \ ESI TSM 15
+ESITSM16=\$D80; \ ESI TSM 16
+ESITSM17=\$D82; \ ESI TSM 17
+ESITSM18=\$D84; \ ESI TSM 18
+ESITSM19=\$D86; \ ESI TSM 19
+ESITSM20=\$D88; \ ESI TSM 20
+ESITSM21=\$D8A; \ ESI TSM 21
+ESITSM22=\$D8C; \ ESI TSM 22
+ESITSM23=\$D8E; \ ESI TSM 23
+ESITSM24=\$D90; \ ESI TSM 24
+ESITSM25=\$D92; \ ESI TSM 25
+ESITSM26=\$D94; \ ESI TSM 26
+ESITSM27=\$D96; \ ESI TSM 27
+ESITSM28=\$D98; \ ESI TSM 28
+ESITSM29=\$D9A; \ ESI TSM 29
+ESITSM30=\$D9C; \ ESI TSM 30
+ESITSM31=\$D9E; \ ESI TSM 31
+
+
+ESI_RAM=\$E00;
--- /dev/null
+
+@set-syntax{C;\;}! tell GEMA to replace default Comment separator '!' by ';'
+;MSP430FRxxxx.pat
+
+; ============================================
+; FRAM INFO
+; ============================================
+; INFO_ORG=\$1800;
+
+; You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst
+; those addresses are usable with the symbolic assembler
+
+FREQ_KHZ=\$1800; FREQUENCY (in kHz)
+TERMBRW_RST=\$1802; TERMBRW_RST
+TERMMCTLW_RST=\$1804; TERMMCTLW_RST
+I2CSLAVEADR=\$1802; I2C_SLAVE address
+I2CSLAVEADR1=\$1804;
+LPM_MODE=\$1806; LPM_MODE value, LPM0+GIE is the default value
+USERSYS=\$1808; user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc.
+VERSION=\$180A;
+THREADS=\$180C; THREADS
+; ---------------------------------------------
+KERNEL_ADDON=\$180E;
+; ---------------------------------------------
+FLOORED=\$8000; BIT15=FLOORED DIVISION
+LF_XTAL=\$4000; BIT14=LF_XTAL
+; BIT13=UART CTS
+; BIT12=UART RTS
+; BIT11=UART XON/XOFF
+; BIT10=UART half duplex
+; BIT9=I2C_TERMINAL
+; BIT8=Q15.16 input
+; BIT7=DOUBLE input
+; BIT6=assembler 20 bits
+; BIT5=assembler 16 bits
+; BIT4=assembler 16 bits with 20 bits addr
+HMPY=8; BIT3=hardware MPY
+; BIT2=
+; BIT1=
+; BIT0=
+; ----------------------------------------------
+DEEP_ORG=\$1810; MOV #DEEP_ORG,X
+; ----------------------------------------------
+DEEP_TERM_VEC=\$1810; address of default TERMINAL vector
+DEEP_STOP=\$1812; address of default STOP_APP
+DEEP_SOFT=\$1814; address of default SOFT_APP
+DEEP_HARD=\$1816; address of default HARD_APP
+DEEP_BACKGRND=\$1818; address of default BACKGRND_APP
+DEEP_DP=\$181A; to DEEP_INIT RST_DP
+DEEP_LASTVOC=\$181C; to DEEP_INIT RST_LASTVOC
+DEEP_CURRENT=\$181E; to DEEP_INIT RST_CURRENT
+DEEP_CONTEXT=\$1820; to DEEP_INIT RST_CONTEXT
+;
+; ----------------------------------------------
+PUC_ABORT_ORG=\$1822; MOV #PUC_ABORT_ORG,X
+; ----------------------------------------------
+INIT_ACCEPT=\$1822; to INIT PFA_ACCEPT
+INIT_EMIT=\$1824; to INIT PFA_EMIT
+INIT_KEY=\$1826; to INIT PFA_KEY
+INIT_CIB=\$1828; to INIT CIB_ORG
+;
+; ----------------------------------------------
+FORTH_ORG=\$182A; MOV #FORTH_ORG,X \to preserve the state of DEFERed words
+; ----------------------------------------------
+INIT_RSP=\$182A; to INIT RSP
+; ----------------------------------------------
+INIT_DOXXX=\$182C; MOV #INIT_DOXXX,X \ to restore DOxxx registers
+; ----------------------------------------------
+INIT_DOCOL=\$182C; to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL
+INIT_DODOES=\$182E; to INIT rDODOES (R5)
+INIT_DOCON=\$1830; to INIT rDOCON (R6)
+INIT_DOVAR=\$1832; to INIT rDOVAR (R7)
+INIT_CAPS=\$1834; to INIT CAPS
+INIT_BASE=\$1836; to INIT BASE
+INIT_LEAVE=\$1838; to INIT LEAVEPTR
+;
+; ----------------------------------------------
+RST_ORG=\$183A;
+RST_LEN=\$10; 16 bytes
+; ----------------------------------------------
+STOP_APP=\$183A; address of current STOP_APP
+SOFT_APP=\$183C; address of current SOFT_APP
+HARD_APP=\$183E; address of current HARD_APP
+BACKGRND_APP=\$1840; address of current BACKGRND_APP
+RST_DP=\$1842; RST_RET value for (RAM) DDP
+RST_LASTVOC=\$1844; RST_RET value for (RAM) LASTVOC
+RST_CURRENT=\$1846; RST_RET value for (RAM) CURRENT
+RST_CONTEXT=\$1848; RST_RET value for (RAM) CONTEXT (8 CELLS)
+;
+; ===============================================
+; FAST FORTH V 4.0: FRAM usage, INFO space free from $185A to $19FF
+; ===============================================
+;
+; ============================================
+; FRAM TLV
+; ============================================
+TLV_ORG=\$1A00; Device Descriptor Info (Tag-Lenght-Value)
+TLV_LEN=\$0100;
+DEVICEID=\$1A04;
+
+; ============================================
+; FORTH RAM areas :
+; ============================================
+LSTACK_SIZE=\#16; words
+PSTACK_SIZE=\#48; words
+RSTACK_SIZE=\#48; words
+PAD_LEN=\#84; bytes
+CIB_LEN=\#84; bytes
+HOLD_SIZE=\#34; bytes
+
+; ============================================
+; FRAM MAIN
+; ============================================
+; to use in ASSEMBLER mode
+; see device.pat for other addresses
+
+I2C_CTRL=KEY\+\$0A; used as is: MOV.B #<CTRL_CHAR>,Y
+; CALL #I2C_CTRL
+\#UART_RXON=\#KEY\+8; CALL #UART_RXON
+\#UART_RXOFF=\#ACCEPT\+\$26; CALL #UART_RXOFF
+\#BACKGRND=\#ACCEPT\+\$1C; MOV #BACKGRND,PC
+\#STOP_APP=\&SYS\+2; CALL #STOP_APP
+\#TOS2WARM=\#SYS\+\$0E; CALL #TOS2WARM WARM with TOS value
+\#TOS2COLD=\#SYS\+\$14; CALL #TOS2COLD COLD with TOS value
+INTERPRET=\\+\$08; address used in CORE_ANS.f
+\#ABORT=\#ALLOT\+\$08; MOV #ABORT,PC used in CORE_ANS.f
+\#QUIT=\#ALLOT\+\$0E; MOV #QUIT,PC used in CORE_ANS.f
+\#D\.=\#U\.+\$0A; MOV #D.,PC used in DOUBLE.f
+\#Read_File=\&READ\+\$0C; CALL #Read_File, sequentially load a sector in SD_BUF
+\#Write_File=\#WRITE\+4; CALL #Write_File, sequentially write SD_BUF in a sector
-! -*- coding: utf-8 -*-
-! MSP_EXP430FR2355.pat
-!
-\.f=\.4th for MSP_EXP430FR2355! to change file type
-!
-!========================
-! remove comments
-!========================
-\\*\n=! entire comment lines
-\s\\*\n=\n! comments at end of line
-! ======================================================================
-! MSP430FR2355 Config
-! ======================================================================
-@define{@read{@mergepath{@inpath{};MSP430FR2355.pat;}}}
+
+@set-syntax{C;\;}! tell GEMA to replace default Comment separator '!' by ';'
+; ========================
+; MSP_EXP430FR2355.pat
+; ========================
+\.f=\.4th for MSP_EXP430FR2355; to change file type from generic to targeted
+
+; ========================
+; remove comments
+; ========================
+\\*\n=; remove entire commented lines
+\s\\*\n=\n; remove comments at end of line
+
+; ======================================================================
+; MSP430FR2355 Config
+; ======================================================================
+@reset-syntax{}; enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR2xxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR2355.pat;}}}
-! ======================================================================
-! INIT MSP-EXP430FR2355 board
-! ======================================================================
-!
-! J101 (7xjumper)
-! "SBWTCK" ---> TEST
-! "SBWTDIO" ---> RST
-! "TXD" <--- P4.3 == UCA0TXD <-- UCA0TXDBUf
-! "RXD" ---> P4.2 == UCA0RXD --> UCA0RXDBUF
-! "3V3" <--> 3V3
-! "5V0" <--> 5V0
-! "GND" <--> GND
-!
-!
-! SW1 -- P4.1
-! SW2 -- P2.3
-!
-! LED1 - P1.0 (red)
-! LED2 - P6.6 (green)
-!
-! I/O pins on J1:
-! J1.1 - 3V3
-! J1.2 - P1.5
-! J1.3 - P1.6
-! J1.4 - P1.7
-! J1.5 - P3.6
-! J1.6 - P5.2
-! J1.7 - P4.5
-! J1.8 - P3.4
-! J1.9 - P1.3
-! J1.10 - P1.2
-!
-! I/O pins on J3:
-! J3.21 - 5V0
-! J3.22 - GND
-! J3.23 - P1.4 A4 SEED
-! J3.24 - P5.3 A11
-! J3.25 - P5.1 A9
-! J3.26 - P5.0 A8
-! J3.27 - P5.4
-! J3.28 - P1.1 A1 SEED
-! J3.29 - P3.5 OA3O
-! J3.30 - P3.1 OA2O
-!
-!
-! I/O pins on J2:
-! J2.11 - P3.0
-! J2.12 - P2.5
-! J2.13 - P4.4
-! J2.14 - P4.7
-! J2.15 - P4.6
-! J2.16 - RST
-! J2.17 - P4.0
-! J2.18 - P2.2
-! J2.19 - P2.0
-! J2.20 - GND
-!
-! I/O pins on J4:
-! J2.31 - P3.2
-! J2.32 - P3.3
-! J2.33 - P2.4
-! J2.34 - P3.7
-! J2.35 - P6.4
-! J2.36 - P6.3
-! J2.37 - P6.2
-! J2.38 - P6.1
-! J2.39 - P6.0
-! J2.40 - 2.1
-!
-! LFXTAL XOUT- P2.6
-! LFXTAL XIN - P2.7
-
-
-!
-! ======================================================================
-! MSP_EXP430FR2355 LAUNCHPAD <--> OUTPUT WORLD
-! ======================================================================
-!
-! +--4k7-< DeepRST switch <-- GND
-! |
-! P4.3 - UCA1 TXD J101.6 - <-+-> RX UARTtoUSB bridge
-! P4.2 - UCA1 RXD J101.8 - <---- TX UARTtoUSB bridge
-! P2.0 - RTS J2.19 - ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
-! P2.1 - CTS J4.40 - <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
-!
-! P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Master_Slave
-! P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Master_Slave
-!
-! P2.2 - J2.18 - <---- TSSOP32236 (IR RC5)
-!
-! P2.5 - J2.12 - ----> SD_CS (Card Select)
-! P4.4 - J2.13 - <---- SD_CD (Card Detect)
-! P4.5 - UCB1 CLK J1.7 - ----> SD_CLK
-! P4.7 - UCB1 SOMI J2.14 - <---- SD_SDO
-! P4.6 - UCB1 SIMO J2.15 - ----> SD_SDI
-!
-! P3.2 - J4.38 - <---> SDA I2C Soft_Master
-! P3.3 - J4.39 - ----> SCL I2C Soft_Master
-
-! GND <-------+---0V0----------> 1 LCD_Vss
-! VCC <------ | --3V6-----+----> 2 LCD_Vdd
-! | |
-! |___ 470n ---
-! ^ | ---
-! / \ BAT54 |
-! --- |
-! 100n | 2k2 |
-! P1.7 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! P1.5 >------------------------> 4 LCD_RS
-! P1.4 >------------------------> 5 LCD_R/W
-! P1.1 >------------------------> 6 LCD_EN
-
-! P6.0 <------------------------> 11 LCD_DB4
-! P6.1 <------------------------> 12 LCD_DB5
-! P6.2 <------------------------> 13 LCD_DB5
-! P6.3 <------------------------> 14 LCD_DB7
-
-! P4.1 ---> S2 LCD contrast +
-! P2.3 ---> S1 LCD contrast -
-
-
-! ============================================
-! FORTH TERMINAL I/O :
-! ============================================
-!TERMINAL
-BUS_TERM=\$0C! P4.2 = RX, P4.3 = TX
-
-TERM_IN=\$221! P4
-TERM_REN=\$227!
-TERM_SEL=\$22B! SEL0
-
-RTS=1! P2.0
-CTS=2! P2.1
-HANDSHAKIN=\$201!
-HANDSHAKOUT=\$203!
-
-XT1_OUT=\$203! P2
-XT1_DIR=\$205! P2
-XT1_SEL=\$20D! P2SEL1
-XIN=\$80!
-XOUT=\$40!
-
-! ============================================
-! FORTH TERMINAL hardware
-! ============================================
-TERM_CTLW0=\$580! \ eUSCI_A1 control word 0
-TERM_CTLW1=\$582! \ eUSCI_A1 control word 1
-TERM_BRW=\$586!
-TERM_BR0=\$586! \ eUSCI_A1 baud rate 0
-TERM_BR1=\$587! \ eUSCI_A1 baud rate 1
-TERM_MCTLW=\$588! \ eUSCI_A1 modulation control
-TERM_STATW=\$58A! \ eUSCI_A1 status
-TERM_RXBUF=\$58C! \ eUSCI_A1 receive buffer
-TERM_TXBUF=\$58E! \ eUSCI_A1 transmit buffer
-TERM_ABCTL=\$590! \ eUSCI_A1 LIN control
-TERM_IRTCTL=\$592! \ eUSCI_A1 IrDA transmit control
-TERM_IRRCTL=\$593! \ eUSCI_A1 IrDA receive control
-TERM_IE=\$59A! \ eUSCI_A1 interrupt enable
-TERM_IFG=\$59C! \ eUSCI_A1 interrupt flags
-TERM_IV=\$59E! \ eUSCI_A1 interrupt vector word
-
-WAKE_UP=1! UART RX interrupt
-RX_TERM=1! RX flag ifg
-TX_TERM=2! Tx flag ifg
-
-! ============================================
-! FRAM MAIN
-! ============================================
-TERM_VEC=\$FFE2! vector for eUSCI_A1
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-LED1_OUT=\$202!
-LED1_DIR=\$204!
-LED1=1! P1.0 LED1 red
-
-LED2_OUT=\$243!
-LED2_DIR=\$245!
-LED2=\$40! P6.6 LED2 green
-
-SW1_IN=\$221!
-SW1=2! P4.1 = S1
-
-WIPE_IN=\$221!
-WIPE=2! P4.1 = S1 = FORTH Deep_RST pin
-
-SW2_IN=\$201!
-SW2=8! P2.3
-
-
-!LCD_Vo PWM
-LCDVo_DIR=\$204! P1
-LCDVo_SEL=\$20C! SEL1
-LCDVo=\$80! P1.7 as TB0.2
-!LCD command bus
-LCD_CMD_IN=\$200! P1
+; ======================================================================
+; INIT MSP-EXP430FR2355 board
+; ======================================================================
+;
+; J101 (7xjumper)
+; "SBWTCK" ---> TEST
+; "SBWTDIO" ---> RST
+; "TXD" <--- P4.3 == UCA0TXD <-- UCA0TXDBUf
+; "RXD" ---> P4.2 == UCA0RXD --> UCA0RXDBUF
+; "3V3" <--> 3V3
+; "5V0" <--> 5V0
+; "GND" <--> GND
+;
+;
+; SW1 -- P4.1
+; SW2 -- P2.3
+;
+; LED1 - P1.0 (red)
+; LED2 - P6.6 (green)
+;
+; I/O pins on J1:
+; J1.1 - 3V3
+; J1.2 - P1.5
+; J1.3 - P1.6
+; J1.4 - P1.7
+; J1.5 - P3.6
+; J1.6 - P5.2
+; J1.7 - P4.5
+; J1.8 - P3.4
+; J1.9 - P1.3
+; J1.10 - P1.2
+;
+; I/O pins on J3:
+; J3.21 - 5V0
+; J3.22 - GND
+; J3.23 - P1.4 A4 SEED
+; J3.24 - P5.3 A11
+; J3.25 - P5.1 A9
+; J3.26 - P5.0 A8
+; J3.27 - P5.4
+; J3.28 - P1.1 A1 SEED
+; J3.29 - P3.5 OA3O
+; J3.30 - P3.1 OA2O
+;
+;
+; I/O pins on J2:
+; J2.11 - P3.0
+; J2.12 - P2.5
+; J2.13 - P4.4
+; J2.14 - P4.7
+; J2.15 - P4.6
+; J2.16 - RST
+; J2.17 - P4.0
+; J2.18 - P2.2
+; J2.19 - P2.0
+; J2.20 - GND
+;
+; I/O pins on J4:
+; J2.31 - P3.2
+; J2.32 - P3.3
+; J2.33 - P2.4
+; J2.34 - P3.7
+; J2.35 - P6.4
+; J2.36 - P6.3
+; J2.37 - P6.2
+; J2.38 - P6.1
+; J2.39 - P6.0
+; J2.40 - 2.1
+;
+; LFXTAL XOUT- P2.6
+; LFXTAL XIN - P2.7
+
+
+;
+; ======================================================================
+; MSP_EXP430FR2355 LAUNCHPAD <--> OUTPUT WORLD
+; ======================================================================
+;
+; +--4k7-< DeepRST switch <-- GND
+; |
+; P4.3 - UCA1 TXD J101.6 - <-+-> RX UARTtoUSB bridge
+; P4.2 - UCA1 RXD J101.8 - <---- TX UARTtoUSB bridge
+; P2.0 - RTS J2.19 - ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
+; P2.1 - CTS J4.40 - <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
+;
+; P1.2 - UCB0 SDA J1.10 - <---> SDA I2C hardware Slave
+; P1.3 - UCB0 SCL J1.9 - ----> SCL I2C hardware Slave
+;
+; P2.2 - J2.18 - <---- TSSOP32236 (IR RC5)
+;
+; P2.5 - J2.12 - ----> SD_CS (Card Select)
+; P4.4 - J2.13 - <---- SD_CD (Card Detect)
+; P4.5 - UCB1 CLK J1.7 - ----> SD_CLK
+; P4.7 - UCB1 SOMI J2.14 - <---- SD_SDO
+; P4.6 - UCB1 SIMO J2.15 - ----> SD_SDI
+;
+; P3.2 - J4.38 - <---> SDA I2C Soft_Master
+; P3.3 - J4.39 - ----> SCL I2C Soft_Master
+
+; GND <-------+---0V0----------> 1 LCD_Vss
+; VCC <------ | --3V6-----+----> 2 LCD_Vdd
+; | |
+; |___ 470n ---
+; ^ | ---
+; / \ BAT54 |
+; --- |
+; 100n | 2k2 |
+; P1.7 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; P1.5 >------------------------> 4 LCD_RS
+; P1.4 >------------------------> 5 LCD_R/W
+; P1.1 >------------------------> 6 LCD_EN
+
+; P6.0 <------------------------> 11 LCD_DB4
+; P6.1 <------------------------> 12 LCD_DB5
+; P6.2 <------------------------> 13 LCD_DB5
+; P6.3 <------------------------> 14 LCD_DB7
+
+; P4.1 ---> S2 LCD contrast +
+; P2.3 ---> S1 LCD contrast -
+
+
+; ----------------------------------------------------------------------
+; MSP430FR2355 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;SYS_SFR .equ 0140h ; SYS
+;CS_SFR .equ 0180h ; Clock System
+;FRAM_SFR .equ 01A0h ; FRAM control
+;CRC16_SFR .equ 01C0h
+;WDT_A_SFR .equ 01CCh ; Watchdog
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3/4
+;PC_SFR .equ 0240h ; PORT5/6
+;RTC_SFR .equ 0300h
+;TB0_SFR .equ 0380h
+;TB1_SFR .equ 03C0h
+;TB2_SFR .equ 0400h
+;TB3_SFR .equ 0440h
+;MPY_SFR .equ 04C0h
+;eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
+;eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
+;eUSCI_A1_SFR .equ 0580h ; eUSCI_A1
+;eUSCI_B1_SFR .equ 05C0h ; eUSCI_B1
+;BACK_MEM_SFR .equ 0660h
+;ICC_SFR .equ 06C0h
+;ADC10_B_SFR .equ 0700h
+;eCOMP0_SFR .equ 08E0h
+;eCOMP1_SFR .equ 0900h
+;SAC0_SFR .equ 0C80h
+;SAC1_SFR .equ 0C90h
+;SAC2_SFR .equ 0CA0h
+;SAC3_SFR .equ 0CB0h
+
+;P4_VEC=\$FFCE;
+;P3_VEC=\$FFD0;
+;P2_VEC=\$FFD2;
+;P1_VEC=\$FFD4;
+;SAC1SAC3_VEC=\$FFD6;
+;SAC0SAC2_VEC=\$FFD8;
+;ECOMPX_VEC=\$FFDA;
+;ADC12_VEC=\$FFDC;
+;EUSCI_B1_VEC=\$FFDE;
+;EUSCI_B0_VEC=\$FFE0;
+;EUSCI_A1_VEC=\$FFE2;
+;EUSCI_A0_VEC=\$FFE4;
+;WDT_VEC=\$FFE6;
+;RTC_VEC=\$FFE8;
+;TB3_X_VEC=\$FFEA;
+;TB3_0_VEC=\$FFEC;
+;TB2_X_VEC=\$FFEE;
+;TB2_0_VEC=\$FFF0;
+;TB1_X_VEC=\$FFF2;
+;TB1_0_VEC=\$FFF4;
+;TB0_X_VEC=\$FFF6;
+;TB0_0_VEC=\$FFF8;
+;U_NMI_VEC=\$FFFA;
+;S_NMI_VEC=\$FFFC;
+;RST_VEC=\$FFFE;
+
+; ============================================
+; FAST FORTH configuration :
+; ============================================
+;TERMINAL P4.2 = RX, P4.3 = TX
+BUS_TERM=\$0C
+TERM_IN=\$221; P4
+TERM_REN=\$227
+TERM_SEL=\$22B; SEL0
+
+TERM_VEC=\$FFE2; vector for eUSCI_A1
+UCSWRST=1; eUSCI Software Reset
+WAKE_UP=1; UART RX interrupt
+RX=1; RX flag IE|IFG
+TX=2; Tx flag IE|IFG
+
+RTS=1; P2.0
+CTS=2; P2.1
+HANDSHAKIN=\$201
+HANDSHAKOUT=\$203
+
+TERM_CTLW0=\$580; eUSCI_A1 control word 0
+TERM_CTLW1=\$582; eUSCI_A1 control word 1
+TERM_BRW=\$586; eUSCI_A1 baud rate
+TERM_MCTLW=\$588; eUSCI_A1 modulation control
+TERM_STATW=\$58A; eUSCI_A1 status
+TERM_RXBUF=\$58C; eUSCI_A1 receive buffer
+TERM_TXBUF=\$58E; eUSCI_A1 transmit buffer
+TERM_IE=\$59A; eUSCI_A1 interrupt enable
+TERM_IFG=\$59C; eUSCI_A1 interrupt flags
+TERM_IV=\$59E; eUSCI_A1 interrupt vector word
+
+LFXT_OUT=\$203; P2
+LFXT_DIR=\$205; P2
+LFXT_SEL=\$20D; P2SEL1
+LFXIN=\$80; P2.7
+LFXOUT=\$40; P2.6
+
+; FAST FORTH I/O :
+LED1_OUT=\$202
+LED1_DIR=\$204
+LED1=1; P1.0 LED1 red
+LED2_OUT=\$243
+LED2_DIR=\$245
+LED2=\$40; P6.6 LED2 green
+
+SW1_IN=\$221
+SW1=2; P4.1 = S1
+SW2_IN=\$201
+SW2=8; P2.3 = S2
+
+; ============================================
+; COMMON UARTI2CS & RC5toLCD APPLICATIONs
+; ============================================
+;Software I2C_Master
+I2CSM_IN=\$220
+I2CSM_OUT=\$222
+I2CSM_DIR=\$224
+I2CSM_REN=\$226
+I2CSM_IES=\$238
+I2CSM_IFG=\$23C
+SM_SDA=4; P3.2
+SM_SCL=8; P3.3
+SM_BUS=\$0C
+
+; ============================================
+; UARTI2CS APPLICATION
+; ============================================
+;500_ms_INT TIMER = TB0
+TIM_CTL=\$380
+TIM_CCTL2=\$386
+TIM_CCR0=\$392
+TIM_CCR2=\$396
+T_OUT2=\$80; P1.7 <--- TB0.2
+T_OUT2_DIR=\$204; P1DIR
+T_OUT2_SEL=\$20C; P1SEL1
+INT_IN=\$40; P1.6
+INT_IN_IE=\$21A; P1IE
+INT_IN_IFG=\$21C; P1IFG
+INT_IN_VEC=\$FFD4; P1VEC
+
+;local variables
+UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+TIMER_CONF=\{UARTI2CS\}\+12; <-- TIM_CTL configuration
+COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+; ============================================
+; RC5toLCD APPLICATION
+; ============================================
+;LCD_Vo PWM P1
+LCDVo_DIR=\$204
+LCDVo_SEL=\$20C; SEL1
+LCDVo=\$80; P1.7 as TB0.2
+
+;LCD command bus P1
+LCD_CMD_IN=\$200
LCD_CMD_OUT=\$202
LCD_CMD_DIR=\$204
LCD_CMD_REN=\$206
-LCD_RS=\$20! P1.5
-LCD_RW=\$10! P1.4
-LCD_EN=2! P1.1
-LCD_CMD=\$32!
-!LCD data bus
-LCD_DB_IN=\$341! P6
+LCD_RS=\$20; P1.5
+LCD_RW=\$10; P1.4
+LCD_EN=2; P1.1
+LCD_CMD=\$32;
+;LCD data bus P6
+LCD_DB_IN=\$341
LCD_DB_OUT=\$343
LCD_DB_DIR=\$345
LCD_DB_REN=\$347
-LCD_DB=\$0F! P6.3210
-!LCD timer
-LCD_TIM_CTL=\$380! TB0CTL
-LCD_TIM_CCTLn=\$386! TB0CCTL2
-LCD_TIM_CCR0=\$392! TB0CCR0
-LCD_TIM_CCRn=\$396! TB0CCR2
-LCD_TIM_EX0=\$3A0! TB0EX0
-
-
-!WATCHDOG timer
-WDT_TIM_CTL=\$3C2! TB1CTL
-WDT_TIM_CCTL0=\$3C2! TB1CCTL0
-WDT_TIM_CCR0=\$3D2! TB1CCR0
-WDT_TIM_EX0=\$3E0! TB1EX0
-WDT_TIM_0_VEC=\$FFF4! TB1_0_VEC
-
-
-!IR_RC5
-RC5_=RC5_!
-IR_IN=\$201!
-IR_OUT=\$203!
-IR_DIR=\$205!
-IR_REN=\$209!
-IR_IES=\$219!
-IR_IE=\$21B!
-IR_IFG=\$21D!
-IR_VEC=\$FFD2! P2 int
-RC5=4! P2.2
-!IR_RC5 timer
-RC5_TIM_CTL=\$400! TB2CTL
-RC5_TIM_R=\$410! TB2R
-RC5_TIM_EX0=\$420! TB2EX0
-
-!Software I2C_Master
-I2CSM_IN=\$220!
-I2CSM_OUT=\$222!
-I2CSM_DIR=\$224!
-I2CSM_REN=\$226!
-I2CSM_IES=\$238!
-I2CSM_IFG=\$23C!
-SM_SDA=4! P3.2
-SM_SCL=8! P3.3
-SM_BUS=\$0C!
-
-!Software I2C_Multi_Master
-I2CSMM_IN=\$220!
-I2CSMM_OUT=\$222!
-I2CSMM_DIR=\$224!
-I2CSMM_REN=\$226!
-I2CSMM_IES=\$238!
-I2CSMM_IFG=\$23C!
-SMM_SDA=4! P3.2
-SMM_SCL=8! P3.3
-SMM_BUS=\$0C!
-
-!hardware I2C_Multi_Master
-I2CMM_IN=\$200!
-I2CMM_OUT=\$202!
-I2CMM_DIR=\$204!
-I2CMM_REN=\$206!
-I2CMM_SEL=\$20A! SEL0
-I2CMM_VEC=\$FFE0! UCB0
-MM_SDA=4! P1.2
-MM_SCL=8! P1.3
-MM_BUS=\$0C!
-
-!hardware I2C_Master
-I2CM_IN=\$200!
-I2CM_OUT=\$202!
-I2CM_DIR=\$204!
-I2CM_REN=\$206!
-I2CM_SEL=\$20A! SEL0
-I2CM_VEC=\$FFE0! UCB0
-M_SDA=4! P1.2
-M_SCL=8! P1.3
-M_BUS=\$0C!
-
-!hardware I2C_Slave
-I2CS_IN=\$200!
-I2CS_OUT=\$202!
-I2CS_DIR=\$204!
-I2CS_REN=\$206!
-I2CS_SEL=\$20A! SEL0
-I2CS_VEC=\$FFE0! UCB0
-S_SDA=4! P1.2
-S_SCL=8! P1.3
-S_BUS=\$0C!
-I2CMM_VEC=\$FFE0! UCB0
-
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
-
-I2CM_CTLW0=\$540! USCI_B0 Control Word Register 0
-I2CM_CTLW1=\$542! USCI_B0 Control Word Register 1
-I2CM_BRW=\$546! USCI_B0 Baud Word Rate 0
-I2CM_STATW=\$548! USCI_B0 status word
-I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold
-I2CM_RXBUF=\$54C! USCI_B0 Receive Buffer 8
-I2CM_TXBUF=\$54E! USCI_B0 Transmit Buffer 8
-I2CM_I2COA0=\$554! USCI_B0 I2C Own Address 0
-I2CM_ADDRX=\$55C! USCI_B0 Received Address Register
-I2CM_I2CSA=\$560! USCI_B0 I2C Slave Address
-I2CM_IE=\$56A! USCI_B0 Interrupt Enable
-I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register
-
-I2CS_CTLW0=\$540! USCI_B0 Control Word Register 0
-I2CS_CTLW1=\$542! USCI_B0 Control Word Register 1
-I2CS_BRW=\$546! USCI_B0 Baud Word Rate 0
-I2CS_STATW=\$548! USCI_B0 status word
-I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold
-I2CS_RXBUF=\$54C! USCI_B0 Receive Buffer 8
-I2CS_TXBUF=\$54E! USCI_B0 Transmit Buffer 8
-I2CS_I2COA0=\$554! USCI_B0 I2C Own Address 0
-I2CS_ADDRX=\$55C! USCI_B0 Received Address Register
-I2CS_I2CSA=\$560! USCI_B0 I2C Slave Address
-I2CS_IE=\$56A! USCI_B0 Interrupt Enable
-I2CS_IFG=\$56C! USCI_B0 Interrupt Flags Register
-
-CD_SD=\$10! P4.4 as Card Detect
-SD_CDIN=\$221!
-
-CS_SD=\$20! P2.5 as Card Select
-SD_CSOUT=\$203!
-SD_CSDIR=\$205!
-
-BUS_SD=\$7000! pins P4.5 as UCB1CLK, P4.6 as UCB1SIMO & P4.7 as UCB1SOMI
-SD_SEL=\$22B! P4SEL0 to configure UCB1
-SD_REN=\$227! P4REN to configure pullup resistors
+LCD_DB=\$0F; P6.3210
+;LCD timer TB0
+LCD_TIM_CTL=\$380
+LCD_TIM_CCTLn=\$386; TB0CCTL2
+LCD_TIM_CCR0=\$392
+LCD_TIM_CCRn=\$396; TB0CCR2
+LCD_TIM_EX0=\$3A0
+;WATCHDOG timer TB1
+WDT_TIM_CTL=\$3C2
+WDT_TIM_CCTL0=\$3C2
+WDT_TIM_CCR0=\$3D2
+WDT_TIM_EX0=\$3E0
+WDT_TIM_0_VEC=\$FFF4; TB1_0_VEC
+;IR_RC5
+RC5_=RC5_;
+IR_IN=\$201;
+IR_OUT=\$203;
+IR_DIR=\$205;
+IR_REN=\$209;
+IR_IES=\$219;
+IR_IE=\$21B;
+IR_IFG=\$21D;
+IR_VEC=\$FFD2; P2 int
+RC5=4; P2.2
+;IR_RC5 timer
+RC5_TIM_CTL=\$400; TB2CTL
+RC5_TIM_R=\$410; TB2R
+RC5_TIM_EX0=\$420; TB2EX0
+; --------------------------------------------
+
+;Software I2C_Multi_Master
+I2CSMM_IN=\$220;
+I2CSMM_OUT=\$222;
+I2CSMM_DIR=\$224;
+I2CSMM_REN=\$226;
+I2CSMM_IES=\$238;
+I2CSMM_IFG=\$23C;
+SMM_SDA=4; P3.2
+SMM_SCL=8; P3.3
+SMM_BUS=\$0C;
+
+;hardware I2C_Multi_Master
+I2CMM_IN=\$200;
+I2CMM_OUT=\$202;
+I2CMM_DIR=\$204;
+I2CMM_REN=\$206;
+I2CMM_SEL=\$20A; SEL0
+I2CMM_VEC=\$FFE0; UCB0
+MM_SDA=4; P1.2
+MM_SCL=8; P1.3
+MM_BUS=\$0C;
+
+;hardware I2C_Master
+I2CM_IN=\$200;
+I2CM_OUT=\$202;
+I2CM_DIR=\$204;
+I2CM_REN=\$206;
+I2CM_SEL=\$20A; SEL0
+I2CM_VEC=\$FFE0; UCB0
+M_SDA=4; P1.2
+M_SCL=8; P1.3
+M_BUS=\$0C;
+
+;hardware I2C_Slave
+I2CS_IN=\$200;
+I2CS_OUT=\$202;
+I2CS_DIR=\$204;
+I2CS_REN=\$206;
+I2CS_SEL=\$20A; SEL0
+I2CS_VEC=\$FFE0; UCB0
+S_SDA=4; P1.2
+S_SCL=8; P1.3
+S_BUS=\$0C;
+I2CMM_VEC=\$FFE0; UCB0
+
+I2CM_CTLW0=\$540; USCI_B0 Control Word Register 0
+I2CM_CTLW1=\$542; USCI_B0 Control Word Register 1
+I2CM_BRW=\$546; USCI_B0 Baud Word Rate 0
+I2CM_STATW=\$548; USCI_B0 status word
+I2CM_TBCNT=\$54A; USCI_B0 byte counter threshold
+I2CM_RXBUF=\$54C; USCI_B0 Receive Buffer 8
+I2CM_TXBUF=\$54E; USCI_B0 Transmit Buffer 8
+I2CM_I2COA0=\$554; USCI_B0 I2C Own Address 0
+I2CM_ADDRX=\$55C; USCI_B0 Received Address Register
+I2CM_I2CSA=\$560; USCI_B0 I2C Slave Address
+I2CM_IE=\$56A; USCI_B0 Interrupt Enable
+I2CM_IFG=\$56C; USCI_B0 Interrupt Flags Register
+
+I2CS_CTLW0=\$540; USCI_B0 Control Word Register 0
+I2CS_CTLW1=\$542; USCI_B0 Control Word Register 1
+I2CS_BRW=\$546; USCI_B0 Baud Word Rate 0
+I2CS_STATW=\$548; USCI_B0 status word
+I2CS_TBCNT=\$54A; USCI_B0 byte counter threshold
+I2CS_RXBUF=\$54C; USCI_B0 Receive Buffer 8
+I2CS_TXBUF=\$54E; USCI_B0 Transmit Buffer 8
+I2CS_I2COA0=\$554; USCI_B0 I2C Own Address 0
+I2CS_ADDRX=\$55C; USCI_B0 Received Address Register
+I2CS_I2CSA=\$560; USCI_B0 I2C Slave Address
+I2CS_IE=\$56A; USCI_B0 Interrupt Enable
+I2CS_IFG=\$56C; USCI_B0 Interrupt Flags Register
+
+CD_SD=\$10; P4.4 as Card Detect
+SD_CDIN=\$221;
+
+CS_SD=\$20; P2.5 as Card Select
+SD_CSOUT=\$203;
+SD_CSDIR=\$205;
+
+BUS_SD=\$7000; pins P4.5 as UCB1CLK, P4.6 as UCB1SIMO & P4.7 as UCB1SOMI
+SD_SEL=\$22B; P4SEL0 to configure UCB1
+SD_REN=\$227; P4REN to configure pullup resistors
-! -*- coding: utf-8 -*-
-! MSP_EXP430FR2433.pat
-!
-\.f=\.4th for MSP_EXP430FR2433! to change file type
-!
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! replace ! by semicolon
+; MSP_EXP430FR2433.pat
+;
+\.f=\.4th for MSP_EXP430FR2433; to change file type
+;
+; ========================
+; remove comments
+; ========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! MSP430FR2433 Config
-! ======================================================================
+; ======================================================================
+; MSP430FR2433 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR2433.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR2xxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-! ======================================================================
-! INIT MSP-EXP430FR2433 board
-! ======================================================================
-!
-! J101 (7xjumper)
-! "SBWTCK" ---> TEST
-! "SBWTDIO" ---> RST
-! "TXD" <--- P1.4 == UCA0TXD <-- UCA0TXDBUf
-! "RXD" ---> P1.5 == UCA0RXD --> UCA0RXDBUF
-! "3V3" <--> 3V3
-! "5V0" <--> 5V0
-! "GND" <--> GND
-!
-!
-! SW1 -- P2.3
-! SW2 -- P2.7
-!
-! LED1 - P1.0
-! LED2 - P1.1
-!
-! I/O pins on J1:
-! J1.1 - 3V3
-! J1.2 - P1.0
-! J1.3 - P1.5
-! J1.4 - P1.4
-! J1.5 - P1.6
-! J1.6 - P1.7
-! J1.7 - P2.4
-! J1.8 - P2.7
-! J1.9 - P1.3
-! J1.10- P1.2
-!
-! I/O pins on J2:
-! J2.11 - P2.0
-! J2.12 - P2.1
-! J2.13 - P3.1
-! J2.14 - P2.5
-! J2.15 - P2.6
-! J2.16 - RST
-! J2.17 - P3.2
-! J2.18 - P2.2
-! J2.19 - P1.1
-! J2.20 - GND
-!
-!
-! ======================================================================
-! MSP-EXP430FR2433 LAUNCHPAD <--> OUTPUT WORLD
-! ======================================================================
-!
-! +--4k7-< DeepRST switch <-- GND
-! |
-! P1.4 - UCA0 TXD J101.6 - <-+-> RX UARTtoUSB bridge
-! P1.5 - UCA0 RXD J101.8 - <---- TX UARTtoUSB bridge
-! P1.0 - RTS J1.2 - ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
-! P1.1 - CTS J2.19 - <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
-!
-!
-! P2.4 - UCA1 CLK J1.7 - ----> SD_CLK
-! P2.6 - UCA1 SIMO J2.15 - ----> SD_SDI
-! P2.5 - UCA1 SOMI J2.14 - <---- SD_SDO
-! P2.1 - J2.12 - <---- SD_CD (Card Detect)
-! P2.0 - J2.11 - ----> SD_CS (Card Select)
-!
-! P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Slave
-! P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Slave
-!
-! P3.1 - J2.13 - ----> SCL I2C SoftMaster
-! P3.2 - J2.17 - <---> SDA I2C SoftMaster
-!
-! P2.2 - ACLK J2.18 - <---- TSSOP32236 (IR RC5)
-
-
-
-! ============================================
-! FORTH I/O :
-! ============================================
-!TERMINAL
-BUS_TERM=\$30! ; P1.4 = TX, P1.5 = RX
-
-TERM_IN=\$200!
-TERM_REN=\$206!
-TERM_SEL=\$20A! \SEL0
-
-TERM_VEC=\$FFE4! \ UCA0
-WAKE_UP=1! \ RX int
-
-TERM_CTLW0=\$500! \ eUSCI_A control word 0
-TERM_CTLW1=\$502! \ eUSCI_A control word 1
-TERM_BRW=\$506!
-TERM_BR0=\$506! \ eUSCI_A baud rate 0
-TERM_BR1=\$507! \ eUSCI_A baud rate 1
-TERM_MCTLW=\$508! \ eUSCI_A modulation control
-TERM_STATW=\$50A! \ eUSCI_A status
-TERM_RXBUF=\$50C! \ eUSCI_A receive buffer
-TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer
-TERM_ABCTL=\$510! \ eUSCI_A LIN control
-TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control
-TERM_IE=\$51A! \ eUSCI_A interrupt enable
-TERM_IFG=\$51C! \ eUSCI_A interrupt flags
-TERM_IV=\$51E! \ eUSCI_A interrupt vector word
-
-RTS=1! P1.0
-CTS=2! P1.1
-HANDSHAKIN=\$200!
-HANDSHAKOUT=\$202!
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-LED1_OUT=\$202!
-LED1_DIR=\$204!
-LED1=1! P1.0 LED1 red
-
-LED2_OUT=\$202!
-LED2_DIR=\$204!
-LED2=2! P1.1 LED2 green
-
-SW1_IN=\$201!
-SW1=8! P2.3 = S1
-
-WIPE_IN=\$201!
-IO_WIPE=8! P2.3 = S1 = FORTH Deep_RST pin
-
-SW2_IN=\$201!
-SW2=\$80! P2.7
-
-
-!IR_RC5
-IR_IN=\$201!
-IR_OUT=\$203!
-IR_DIR=\$205!
-IR_REN=\$209!
-IR_IES=\$219!
-IR_IE=\$21B!
-IR_IFG=\$21D!
-IR_VEC=\$FFDA! P2 int
-RC5_=RC5_!
-RC5=4! P2.2
-
-!I2C_Soft_Master
-I2CSM_IN=\$220!
-I2CSM_OUT=\$222!
-I2CSM_DIR=\$224!
-I2CSM_REN=\$226!
-SM_SDA=4! P3.2
-SM_SCL=2! P3.1
-SM_BUS=\$06!
-
-!I2C_Soft_Multi_Master
-I2CSMM_IN=\$220!
-I2CSMM_OUT=\$222!
-I2CSMM_DIR=\$224!
-I2CSMM_REN=\$226!
-SMM_SDA=4! P3.2
-SMM_SCL=2! P3.1
-SMM_BUS=\$06!
-
-!I2C_Multi_Master
-I2CMM_IN=\$200!
-I2CMM_OUT=\$202!
-I2CMM_DIR=\$204!
-I2CMM_REN=\$206!
-I2CMM_SEL=\$20A! SEL0
-I2CMM_VEC=\$FFE0! UCB0_VEC
-MM_SDA=\$04! P1.2
-MM_SCL=\$08! P1.3
-MM_BUS=\$0C!
-
-!I2C_Master
-I2CM_IN=\$200!
-I2CM_OUT=\$202!
-I2CM_DIR=\$204!
-I2CM_REN=\$206!
-I2CM_SEL=\$20A! SEL0
-I2CM_VEC=\$FFE0! UCB0_VEC
-M_SDA=\$04! P1.2
-M_SCL=\$08! P1.3
-M_BUS=\$0C!
-
-!I2C_Slave
-I2CS_IN=\$200!
-I2CS_OUT=\$202!
-I2CS_DIR=\$204!
-I2CS_REN=\$206!
-I2CS_SEL=\$20A! SEL0
-I2CS_VEC=\$FFE0! UCB0_VEC
-S_SDA=\$04! P1.2
-S_SCL=\$08! P1.3
-S_BUS=\$0C!
-
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
-
-I2CM_CTLW0=\$540! USCI_B0 Control Word Register 0
-I2CM_CTLW1=\$542! USCI_B0 Control Word Register 1
-I2CM_BRW=\$546! USCI_B0 Baud Word Rate 0
-I2CM_STATW=\$548! USCI_B0 status word
-I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold
-I2CM_RXBUF=\$54C! USCI_B0 Receive Buffer 8
-I2CM_TXBUF=\$54E! USCI_B0 Transmit Buffer 8
-I2CM_I2COA0=\$554! USCI_B0 I2C Own Address 0
-I2CM_ADDRX=\$55C! USCI_B0 Received Address Register
-I2CM_I2CSA=\$560! USCI_B0 I2C Slave Address
-I2CM_IE=\$56A! USCI_B0 Interrupt Enable
-I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register
-
-I2CS_CTLW0=\$540! USCI_B0 Control Word Register 0
-I2CS_CTLW1=\$542! USCI_B0 Control Word Register 1
-I2CS_BRW=\$546! USCI_B0 Baud Word Rate 0
-I2CS_STATW=\$548! USCI_B0 status word
-I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold
-I2CS_RXBUF=\$54C! USCI_B0 Receive Buffer 8
-I2CS_TXBUF=\$54E! USCI_B0 Transmit Buffer 8
-I2CS_I2COA0=\$554! USCI_B0 I2C Own Address 0
-I2CS_ADDRX=\$55C! USCI_B0 Received Address Register
-I2CS_I2CSA=\$560! USCI_B0 I2C Slave Address
-I2CS_IE=\$56A! USCI_B0 Interrupt Enable
-I2CS_IFG=\$56C! USCI_B0 Interrupt Flags Register
-
-CD_SD=2! ; P2.1 as Card Detect
-SD_CDIN=\$201!
-
-CS_SD=1! ; P2.0 as Card Select
-SD_CSOUT=\$203!
-SD_CSDIR=\$205!
-
-BUS_SD=\$7000! ; pins P2.4 as UCB0CLK, P2.6 as UCB0SIMO & P25 as UCB0SOMI
-SD_SEL=\$20A! ; PASEL0 to configure UCB0
-SD_REN=\$206! ; PAREN to configure pullup resistors
+; ======================================================================
+; INIT MSP-EXP430FR2433 board
+; ======================================================================
+;
+; J101 (7xjumper)
+; "SBWTCK" ---> TEST
+; "SBWTDIO" ---> RST
+; "TXD" <--- P1.4 == UCA0TXD <-- UCA0TXDBUf
+; "RXD" ---> P1.5 == UCA0RXD --> UCA0RXDBUF
+; "3V3" <--> 3V3
+; "5V0" <--> 5V0
+; "GND" <--> GND
+;
+;
+; SW1 -- P2.3
+; SW2 -- P2.7
+;
+; LED1 - P1.0
+; LED2 - P1.1
+;
+; I/O pins on J1:
+; J1.1 - 3V3
+; J1.2 - P1.0
+; J1.3 - P1.5
+; J1.4 - P1.4
+; J1.5 - P1.6
+; J1.6 - P1.7
+; J1.7 - P2.4
+; J1.8 - P2.7
+; J1.9 - P1.3
+; J1.10- P1.2
+;
+; I/O pins on J2:
+; J2.11 - P2.0
+; J2.12 - P2.1
+; J2.13 - P3.1
+; J2.14 - P2.5
+; J2.15 - P2.6
+; J2.16 - RST
+; J2.17 - P3.2
+; J2.18 - P2.2
+; J2.19 - P1.1
+; J2.20 - GND
+;
+;
+; ======================================================================
+; MSP-EXP430FR2433 LAUNCHPAD <--> OUTPUT WORLD
+; ======================================================================
+;
+; +--4k7-< DeepRST switch <-- GND
+; |
+; P1.4 - UCA0 TXD J101.6 - <-+-> RX UARTtoUSB bridge
+; P1.5 - UCA0 RXD J101.8 - <---- TX UARTtoUSB bridge
+; P1.0 - RTS J1.2 - ----> CTS UARTtoUSB bridge (TERMINAL4WIRES)
+; P1.1 - CTS J2.19 - <---- RTS UARTtoUSB bridge (TERMINAL5WIRES)
+;
+;
+; P2.4 - UCA1 CLK J1.7 - ----> SD_CLK
+; P2.6 - UCA1 SIMO J2.15 - ----> SD_SDI
+; P2.5 - UCA1 SOMI J2.14 - <---- SD_SDO
+; P2.1 - J2.12 - <---- SD_CD (Card Detect)
+; P2.0 - J2.11 - ----> SD_CS (Card Select)
+;
+; P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Slave
+; P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Slave
+;
+; P3.1 - J2.13 - ----> SCL I2C SoftMaster
+; P3.2 - J2.17 - <---> SDA I2C SoftMaster
+;
+; P2.2 - ACLK J2.18 - <---- TSSOP32236 (IR RC5)
+
+
+
+;P2_VEC=\$FFDA;
+;P1_VEC=\$FFDC;
+;ADC10_B_VEC=\$FFDE;
+;EUSCI_B0_VEC=\$FFE0;
+;EUSCI_A1_VEC=\$FFE2;
+;EUSCI_A0_VEC=\$FFE4;
+;WDT_VEC=\$FFE6;
+;RTC_VEC=\$FFE8;
+;TA3_X_VEC=\$FFEA;
+;TA3_0_VEC=\$FFEC;
+;TA2_X_VEC=\$FFEE;
+;TA2_0_VEC=\$FFF0;
+;TA1_X_VEC=\$FFF2;
+;TA1_0_VEC=\$FFF4;
+;TA0_X_VEC=\$FFF6;
+;TA0_0_VEC=\$FFF8;
+;U_NMI_VEC=\$FFFA;
+;S_NMI_VEC=\$FFFC;
+;RST_VEC=\$FFFE;
+
+; ----------------------------------------------------------------------
+; MSP430FR2433 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;SYS_SFR .equ 0140h ; SYS
+;CS_SFR .equ 0180h ; Clock System
+;FRAM_SFR .equ 01A0h ; FRAM control
+;CRC16_SFR .equ 01C0h
+;WDT_A_SFR .equ 01CCh ; Watchdog
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3
+;RTC_SFR .equ 0300h
+;TA0_SFR .equ 0380h
+;TA1_SFR .equ 03C0h
+;TA2_SFR .equ 0400h
+;TA3_SFR .equ 0440h
+;MPY_SFR .equ 04C0h
+;eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
+;eUSCI_A1_SFR .equ 0520h ; eUSCI_A1
+;eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
+;BACK_MEM_SFR .equ 0660h
+;ADC10_B_SFR .equ 0700h
+; ============================================
+; FAST FORTH configuration :
+; ============================================
+;TERMINAL
+BUS_TERM=\$30; ; P1.4 = TX, P1.5 = RX
+
+TERM_IN=\$200;
+TERM_REN=\$206;
+TERM_SEL=\$20A; \SEL0
+
+TERM_VEC=\$FFE4; \ UCA0
+UCSWRST=1; eUSCI Software Reset
+WAKE_UP=1; \ RX int
+RX=1; RX flag IFG
+TX=2; Tx flag IFG
+
+TERM_CTLW0=\$500; \ eUSCI_A control word 0
+TERM_CTLW1=\$502; \ eUSCI_A control word 1
+TERM_BRW=\$506;
+TERM_BR0=\$506; \ eUSCI_A baud rate 0
+TERM_BR1=\$507; \ eUSCI_A baud rate 1
+TERM_MCTLW=\$508; \ eUSCI_A modulation control
+TERM_STATW=\$50A; \ eUSCI_A status
+TERM_RXBUF=\$50C; \ eUSCI_A receive buffer
+TERM_TXBUF=\$50E; \ eUSCI_A transmit buffer
+TERM_IE=\$51A; \ eUSCI_A interrupt enable
+TERM_IFG=\$51C; \ eUSCI_A interrupt flags
+TERM_IV=\$51E; \ eUSCI_A interrupt vector word
+
+RTS=1; P1.0
+CTS=2; P1.1
+HANDSHAKIN=\$200;
+HANDSHAKOUT=\$202;
+
+LFXT_OUT=\$203; P2
+LFXT_DIR=\$205; P2
+LFXT_SEL=\$20B; P2SEL0
+LFXIN=\$2; P2.1
+LFXOUT=\$1; P2.0
+
+; FORTH I/O :
+LED1_OUT=\$202;
+LED1_DIR=\$204;
+LED1=1; P1.0 LED1 red
+LED2_OUT=\$202;
+LED2_DIR=\$204;
+LED2=2; P1.1 LED2 green
+
+SW1_IN=\$201;
+SW1=8; P2.3 = S1
+SW2_IN=\$201;
+SW2=\$80; P2.7
+
+;IR_RC5
+IR_IN=\$201;
+IR_OUT=\$203;
+IR_DIR=\$205;
+IR_REN=\$209;
+IR_IES=\$219;
+IR_IE=\$21B;
+IR_IFG=\$21D;
+IR_VEC=\$FFDA; P2 int
+RC5_=RC5_;
+RC5=4; P2.2
+
+; ============================================
+; UARTI2CS APPLICATION
+; ============================================
+;I2C_Soft_Master
+I2CSM_IN=\$220;
+I2CSM_OUT=\$222;
+I2CSM_DIR=\$224;
+I2CSM_REN=\$226;
+SM_SDA=4; P3.2
+SM_SCL=2; P3.1
+SM_BUS=\$06;
+
+;500_ms_INT TIMER
+TIM_CTL=\$380; TA0
+TIM_CCTL2=\$386;
+TIM_CCR0=\$392;
+TIM_CCR2=\$396;
+T_OUT2=4; P1.2 <--- TA0.2
+T_OUT2_DIR=\$204; P1DIR
+T_OUT2_SEL=\$20C; P1SEL1
+INT_IN=8; P1.3
+INT_IN_IE=\$21A; P1IE
+INT_IN_IFG=\$21C; P1IFG
+INT_IN_VEC=\$FFDC; P1VEC
+
+;local variables
+UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+TIMER_CONF=\{UARTI2CS\}\+12; <-- TIM_CTL configuration
+COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+; --------------------------------------------
+
+;I2C_Soft_Multi_Master
+I2CSMM_IN=\$220;
+I2CSMM_OUT=\$222;
+I2CSMM_DIR=\$224;
+I2CSMM_REN=\$226;
+SMM_SDA=4; P3.2
+SMM_SCL=2; P3.1
+SMM_BUS=\$06;
+
+;I2C_Multi_Master
+I2CMM_IN=\$200;
+I2CMM_OUT=\$202;
+I2CMM_DIR=\$204;
+I2CMM_REN=\$206;
+I2CMM_SEL=\$20A; SEL0
+I2CMM_VEC=\$FFE0; UCB0_VEC
+MM_SDA=\$04; P1.2
+MM_SCL=\$08; P1.3
+MM_BUS=\$0C;
+
+;I2C_Master
+I2CM_IN=\$200;
+I2CM_OUT=\$202;
+I2CM_DIR=\$204;
+I2CM_REN=\$206;
+I2CM_SEL=\$20A; SEL0
+I2CM_VEC=\$FFE0; UCB0_VEC
+M_SDA=\$04; P1.2
+M_SCL=\$08; P1.3
+M_BUS=\$0C;
+
+;I2C_Slave
+I2CS_IN=\$200;
+I2CS_OUT=\$202;
+I2CS_DIR=\$204;
+I2CS_REN=\$206;
+I2CS_SEL=\$20A; SEL0
+I2CS_VEC=\$FFE0; UCB0_VEC
+S_SDA=\$04; P1.2
+S_SCL=\$08; P1.3
+S_BUS=\$0C;
+
+I2CM_CTLW0=\$540; USCI_B0 Control Word Register 0
+I2CM_CTLW1=\$542; USCI_B0 Control Word Register 1
+I2CM_BRW=\$546; USCI_B0 Baud Word Rate 0
+I2CM_STATW=\$548; USCI_B0 status word
+I2CM_TBCNT=\$54A; USCI_B0 byte counter threshold
+I2CM_RXBUF=\$54C; USCI_B0 Receive Buffer 8
+I2CM_TXBUF=\$54E; USCI_B0 Transmit Buffer 8
+I2CM_I2COA0=\$554; USCI_B0 I2C Own Address 0
+I2CM_ADDRX=\$55C; USCI_B0 Received Address Register
+I2CM_I2CSA=\$560; USCI_B0 I2C Slave Address
+I2CM_IE=\$56A; USCI_B0 Interrupt Enable
+I2CM_IFG=\$56C; USCI_B0 Interrupt Flags Register
+
+I2CS_CTLW0=\$540; USCI_B0 Control Word Register 0
+I2CS_CTLW1=\$542; USCI_B0 Control Word Register 1
+I2CS_BRW=\$546; USCI_B0 Baud Word Rate 0
+I2CS_STATW=\$548; USCI_B0 status word
+I2CS_TBCNT=\$54A; USCI_B0 byte counter threshold
+I2CS_RXBUF=\$54C; USCI_B0 Receive Buffer 8
+I2CS_TXBUF=\$54E; USCI_B0 Transmit Buffer 8
+I2CS_I2COA0=\$554; USCI_B0 I2C Own Address 0
+I2CS_ADDRX=\$55C; USCI_B0 Received Address Register
+I2CS_I2CSA=\$560; USCI_B0 I2C Slave Address
+I2CS_IE=\$56A; USCI_B0 Interrupt Enable
+I2CS_IFG=\$56C; USCI_B0 Interrupt Flags Register
+
+CD_SD=2; ; P2.1 as Card Detect
+SD_CDIN=\$201;
+
+CS_SD=1; ; P2.0 as Card Select
+SD_CSOUT=\$203;
+SD_CSDIR=\$205;
+
+BUS_SD=\$7000; ; pins P2.4 as UCB0CLK, P2.6 as UCB0SIMO & P25 as UCB0SOMI
+SD_SEL=\$20A; ; PASEL0 to configure UCB0
+SD_REN=\$206; ; PAREN to configure pullup resistors
-! -*- coding: utf-8 -*-
-! MSP_EXP430FR4133.pat
-!
-\.f=\.4th for MSP_EXP430FR4133! to change file type
-!
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! replace ! by semicolon
+; MSP_EXP430FR4133.pat
+;
+\.f=\.4th for MSP_EXP430FR4133; to change file type
+; ========================
+; remove comments
+; ========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! MSP430FR4133 Config
-! ======================================================================
+; ======================================================================
+; MSP430FR4133 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR4133.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR2xxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-! ======================================================================
-! MSP_EXP430FR4133 board
-! ======================================================================
-!
-! J101 eZ-FET <-> target
-! -----------------------
-! P1 <-> P2 - NC
-! P3 <-> P4 - TEST - TEST
-! P5 <-> P6 - RST - RST
-! P7 <-> P8 - TX1 - P1.0 UCA0 TXD ---> RX UARTtoUSB module
-! P9 <->P10 - RX1 - P1.1 UCA0 RXD <--- TX UARTtoUSB module
-! P11<->P12 - CTS - P2.4
-! P13<->P14 - RTS - P2.3
-! P15<->P16 - VCC - 3V3
-! P17<->P18 - 5V
-! P19<->P20 - GND - VSS
-!
-! Launchpad Header Left J1
-! ------------------------
-! P1 - 3V3
-! P2 - P8.1 ACLK/A9
-! P3 - P1.1 UCA0 RXD
-! P4 - P1.0 UCA0 TXD
-! P5 - P2.7
-! P6 - P8.0 SMCLK/A8
-! P7 - P5.1 UCB0 CLK
-! P8 - P2.5
-! P9 - P8.2 TA1CLK
-! P10- P8.3 TA1.2
-!
-! Launchpad Header Right J2
-! -------------------------
-! P1 - GND
-! P2 - P1.7 TA0.1/TDO/A7
-! P3 - P1.6 TA0.2/TDI/TCLK/A6
-! P4 - P5.0 UCB0STE
-! P5 - RST
-! P6 - P5.2 UCB0SIMO/UCB0SDA
-! P7 - P5.3 UCB0SOMI/UCB0SCL
-! P8 - P1.3 UCA0STE/A3
-! P9 - P1.4 MCLK/TCK/A4
-! P10- P1.5 TA0CLK/TMS/A5
-!
-! switch-keys:
-! S1 - P1.2
-! S2 - P2.6
-! S3 - RST
-!
-! LEDS:
-! LED1 - P1.0/TXD
-! LED2 - P4.0
-!
-! XTAL LF 32768 Hz
-! Y4 - P4.1 XIN
-! Y4 - P4.2 XOUT
-!
-! LCD
-! L0 - P7.0
-! L1 - P7.1
-! L2 - P7.2
-! L3 - P7.3
-! L4 - P7.4
-! L5 - P7.5
-! L6 - P7.6
-! L7 - P7.7
-! L8 - P3.0
-! L9 - P3.1
-! L10 - P3.2
-! L11 - P3.3
-! L12 - P3.4
-! L13 - P3.5
-! L14 - P3.6
-! L15 - P3.7
-! L16 - P6.0
-! L17 - P6.1
-! L18 - P6.2
-! L19 - P6.3
-! L20 - P6.4
-! L21 - P6.5
-! L22 - P6.6
-! L23 - P6.7
-! L24 - P2.0
-! L25 - P2.1
-! L26 - P2.2
-! L36 - P5.4
-! L37 - P5.5
-! L38 - P5.6
-! L39 - P5.7
-!
-!
-!
-!
-!
-!
-! ===================================================================================
-! in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
-! then wire VCC and GND of bridge onto J13 connector
-! ===================================================================================
-!
-! ---------------------------------------------------
-! MSP - MSP-EXP430FR4133 LAUNCHPAD <--> OUTPUT WORLD
-! ---------------------------------------------------
-!
-! +-4k7-< DeepRST <-- GND
-! |
-! P1.0 - UCA0 TXD J101.8 --+-> RX UARTtoUSB bridge
-! P1.1 - UCA0 RXD J101.10 <---- TX UARTtoUSB bridge
-! P2.3 - RTS J101.14 ----> CTS UARTtoUSB bridge (if TERMINALCTSRTS option)
-! VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
-! GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge)
-!
-! P1.0 - STRAP JP1 MUST BE REMOVED (LED red)
-! =========================
-!
-! P4.0 - LED green
-!
-! P1.2 - Switch SW1 <--- LCD contrast + (finger :-)
-! P2.6 - Switch SW2 <--- LCD contrast - (finger ;-)
-!
-!
-! GND - J2.1 <-------+---0V0----------> 1 LCD_Vss
-! VCC - J1.1 >------ | --3V6-----+----> 2 LCD_Vdd
-! | |
-! ___ 470n ---
-! ^ ---
-! / \ 1n4148 |
-! --- |
-! 100n | 2k2 |
-! P1.6 - TA0.2 J2.18 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! P1.3 - J2.13 -------------------------> 4 LCD_RS
-! P1.4 - J2.12 -------------------------> 5 LCD_R/W
-! P1.5 - J2.11 -------------------------> 6 LCD_EN
-! P5.0 - J2.17 <------------------------> 11 LCD_DB4
-! P5.1 - J1.7 <------------------------> 12 LCD_DB5
-! P5.2 - J2.15 <------------------------> 13 LCD_DB5
-! P5.3 - J2.14 <------------------------> 14 LCD_DB7
-!
-!
-! P1.7 - J2.19 <---- OUT IR_Receiver (1 TSOP32236)
-!
-! P4.1 - LFXIN 32768Hz quartz
-! P4.2 - LFXOUT 32768Hz quartz
-!
-! VCC - J1.1 ----> VCC SD_CardAdapter
-! GND - J2.1 <---> GND SD_CardAdapter
-! P5.1 - UCB0 CLK J1.7 ----> CLK SD_CardAdapter (SCK)
-! P8.1 - J1.2 ----> CS SD_CardAdapter (Card Select)
-! P5.2 - UCB0 TXD/SIMO J2.15 ----> SDI SD_CardAdapter (MOSI)
-! P5.3 - UCB0 RXD/SOMI J2.14 <---- SDO SD_CardAdapter (MISO)
-! P8.0 - J1.6 <---- CD SD_CardAdapter (Card Detect)
-!
-!
-!
-! P8.2 - Soft I2C_Master J1.9 ----> SDA software I2C Master
-! P8.3 - Soft I2C_Master J1.10 <---> SCL software I2C Master
-
-
-! ============================================
-! FORTH I/O :
-! ============================================
-!TERMINAL
-BUS_TERM=3! ; P1.0 = TX, P1.1 = RX
-
-TERM_IN=\$200!
-TERM_REN=\$206!
-TERM_SEL=\$20A! \ SEL0
+; ======================================================================
+; MSP_EXP430FR4133 board
+; ======================================================================
+;
+; J101 eZ-FET <-> target
+; -----------------------
+; P1 <-> P2 - NC
+; P3 <-> P4 - TEST - TEST
+; P5 <-> P6 - RST - RST
+; P7 <-> P8 - TX1 - P1.0 UCA0 TXD ---> RX UARTtoUSB module
+; P9 <->P10 - RX1 - P1.1 UCA0 RXD <--- TX UARTtoUSB module
+; P11<->P12 - CTS - P2.4
+; P13<->P14 - RTS - P2.3
+; P15<->P16 - VCC - 3V3
+; P17<->P18 - 5V
+; P19<->P20 - GND - VSS
+;
+; Launchpad Header Left J1
+; ------------------------
+; P1 - 3V3
+; P2 - P8.1 ACLK/A9
+; P3 - P1.1 UCA0 RXD
+; P4 - P1.0 UCA0 TXD
+; P5 - P2.7
+; P6 - P8.0 SMCLK/A8
+; P7 - P5.1 UCB0 CLK
+; P8 - P2.5
+; P9 - P8.2 TA1CLK
+; P10- P8.3 TA1.2
+;
+; Launchpad Header Right J2
+; -------------------------
+; P1 - GND
+; P2 - P1.7 TA0.1/TDO/A7
+; P3 - P1.6 TA0.2/TDI/TCLK/A6
+; P4 - P5.0 UCB0STE
+; P5 - RST
+; P6 - P5.2 UCB0SIMO/UCB0SDA
+; P7 - P5.3 UCB0SOMI/UCB0SCL
+; P8 - P1.3 UCA0STE/A3
+; P9 - P1.4 MCLK/TCK/A4
+; P10- P1.5 TA0CLK/TMS/A5
+;
+; switch-keys:
+; S1 - P1.2
+; S2 - P2.6
+; S3 - RST
+;
+; LEDS:
+; LED1 - P1.0/TXD
+; LED2 - P4.0
+;
+; XTAL LF 32768 Hz
+; Y4 - P4.1 XIN
+; Y4 - P4.2 XOUT
+;
+; LCD
+; L0 - P7.0
+; L1 - P7.1
+; L2 - P7.2
+; L3 - P7.3
+; L4 - P7.4
+; L5 - P7.5
+; L6 - P7.6
+; L7 - P7.7
+; L8 - P3.0
+; L9 - P3.1
+; L10 - P3.2
+; L11 - P3.3
+; L12 - P3.4
+; L13 - P3.5
+; L14 - P3.6
+; L15 - P3.7
+; L16 - P6.0
+; L17 - P6.1
+; L18 - P6.2
+; L19 - P6.3
+; L20 - P6.4
+; L21 - P6.5
+; L22 - P6.6
+; L23 - P6.7
+; L24 - P2.0
+; L25 - P2.1
+; L26 - P2.2
+; L36 - P5.4
+; L37 - P5.5
+; L38 - P5.6
+; L39 - P5.7
+;
+;
+;
+;
+;
+;
+; ===================================================================================
+; in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
+; then wire VCC and GND of bridge onto J13 connector
+; ===================================================================================
+;
+; ---------------------------------------------------
+; MSP - MSP-EXP430FR4133 LAUNCHPAD <--> OUTPUT WORLD
+; ---------------------------------------------------
+;
+; +-4k7-< DeepRST <-- GND
+; |
+; P1.0 - UCA0 TXD J101.8 --+-> RX UARTtoUSB bridge
+; P1.1 - UCA0 RXD J101.10 <---- TX UARTtoUSB bridge
+; P2.3 - RTS J101.14 ----> CTS UARTtoUSB bridge (if TERMINALCTSRTS option)
+; VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ; 3.3V !)
+; GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge)
+;
+; P1.0 - STRAP JP1 MUST BE REMOVED (LED red)
+; =========================
+;
+; P4.0 - LED green
+;
+; P1.2 - Switch SW1 <--- LCD contrast + (finger :-)
+; P2.6 - Switch SW2 <--- LCD contrast - (finger ;-)
+;
+;
+; GND - J2.1 <-------+---0V0----------> 1 LCD_Vss
+; VCC - J1.1 >------ | --3V6-----+----> 2 LCD_Vdd
+; | |
+; ___ 470n ---
+; ^ ---
+; / \ 1n4148 |
+; --- |
+; 100n | 2k2 |
+; P1.6 - TA0.2 J2.18 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; P1.3 - J2.13 -------------------------> 4 LCD_RS
+; P1.4 - J2.12 -------------------------> 5 LCD_R/W
+; P1.5 - J2.11 -------------------------> 6 LCD_EN
+; P5.0 - J2.17 <------------------------> 11 LCD_DB4
+; P5.1 - J1.7 <------------------------> 12 LCD_DB5
+; P5.2 - J2.15 <------------------------> 13 LCD_DB5
+; P5.3 - J2.14 <------------------------> 14 LCD_DB7
+;
+;
+; P1.7 - J2.19 <---- OUT IR_Receiver (1 TSOP32236)
+;
+; P4.1 - LFXIN 32768Hz quartz
+; P4.2 - LFXOUT 32768Hz quartz
+;
+; VCC - J1.1 ----> VCC SD_CardAdapter
+; GND - J2.1 <---> GND SD_CardAdapter
+; P5.1 - UCB0 CLK J1.7 ----> CLK SD_CardAdapter (SCK)
+; P8.1 - J1.2 ----> CS SD_CardAdapter (Card Select)
+; P5.2 - UCB0 TXD/SIMO J2.15 ----> SDI SD_CardAdapter (MOSI)
+; P5.3 - UCB0 RXD/SOMI J2.14 <---- SDO SD_CardAdapter (MISO)
+; P8.0 - J1.6 <---- CD SD_CardAdapter (Card Detect)
+;
+;
+;
+; P8.2 - Soft I2C_Master J1.9 ----> SDA software I2C Master
+; P8.3 - Soft I2C_Master J1.10 <---> SCL software I2C Master
-TERM_VEC=\$FFEC! \ UCA0
-WAKE_UP=1! \ RX int
-TERM_CTLW0=\$500! \ eUSCI_A control word 0
-TERM_CTLW1=\$502! \ eUSCI_A control word 1
-TERM_BRW=\$506!
-TERM_BR0=\$506! \ eUSCI_A baud rate 0
-TERM_BR1=\$507! \ eUSCI_A baud rate 1
-TERM_MCTLW=\$508! \ eUSCI_A modulation control
-TERM_STATW=\$50A! \ eUSCI_A status
-TERM_RXBUF=\$50C! \ eUSCI_A receive buffer
-TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer
-TERM_ABCTL=\$510! \ eUSCI_A LIN control
-TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control
-TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control
-TERM_IE=\$51A! \ eUSCI_A interrupt enable
-TERM_IFG=\$51C! \ eUSCI_A interrupt flags
-TERM_IV=\$51E! \ eUSCI_A interrupt vector word
+; ----------------------------------------------------------------------
+; EXP430FR4133 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;SYS_SFR .equ 0140h ; SYS
+;CS_SFR .equ 0180h ; Clock System
+;FRAM_SFR .equ 01A0h ; FRAM control
+;CRC16_SFR .equ 01C0h
+;WDT_A_SFR .equ 01CCh ; Watchdog
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3/4
+;PC_SFR .equ 0240h ; PORT5/6
+;PD_SFR .equ 0260h ; PORT7/8
+;CTIO0_SFR .equ 02E0h ; Capacitive Touch IO
+;TA0_SFR .equ 0300h
+;TA1_SFR .equ 0340h
+;RTC_SFR .equ 03C0h
+;eUSCI_A0_SFR .equ 0500h ; eUSCI_A0
+;eUSCI_B0_SFR .equ 0540h ; eUSCI_B0
+;LCD_SFR .equ 0600h
+;BACK_MEM_SFR .equ 0660h
+;ADC10_B_SFR .equ 0700h
-RTS=8! ; P2.3
-CTS=\$10! ; P2.4
-HANDSHAKIN=\$201!
-HANDSHAKOUT=\$203!
+;LCD_VEC=\$FFE2;
+;P2_VEC=\$FFE4;
+;P1_VEC=\$FFE6;
+;ADC10_B_VEC=\$FFE8;
+;EUSCI_B0_VEC=\$FFEA;
+;EUSCI_A0_VEC=\$FFEC;
+;WDT_VEC=\$FFEE;
+;RTC_VEC=\$FFF0;
+;TA1_X_VEC=\$FFF2;
+;TA1_0_VEC=\$FFF4;
+;TA0_X_VEC=\$FFF6;
+;TA0_0_VEC=\$FFF8;
+;U_NMI_VEC=\$FFFA;
+;S_NMI_VEC=\$FFFC;
+;RST_VEC=\$FFFE;
+; ============================================
+; FAST FORTH configuration :
+; ============================================
+;TERMINAL
+BUS_TERM=3; ; P1.0 = TX, P1.1 = RX
+TERM_IN=\$200;
+TERM_REN=\$206;
+TERM_SEL=\$20A; \ SEL0
-! ============================================
-! APPLICATION I/O :
-! ============================================
-!LEDs
-!----
-invert LED numbers because LED1=TXD !
-LED2_OUT=\$202!
-LED2_DIR=\$204!
-LED2=\$01! P1.0 red LED
-LED1_OUT=\$223!
-LED1_DIR=\$225!
-LED1=\$01! P4.0 green LED, warning ! wired with UART RX !
+TERM_VEC=\$FFEC; \ UCA0
+UCSWRST=1; eUSCI Software Reset
+WAKE_UP=1; \ RX int
+RX=1; RX flag IFG
+TX=2; Tx flag IFG
-!switches
-!--------
-SW1_IN=\$200!
-SW1=\$04! P1.2 = S1
-WIPE_IN=\$200!
-IO_WIPE=\$04! P1.2 = S1 = FORTH Deep_RST pin
-SW2_IN=\$201!
-SW2=\$40! P2.6 = S2
+TERM_CTLW0=\$500; \ eUSCI_A control word 0
+TERM_CTLW1=\$502; \ eUSCI_A control word 1
+TERM_BRW=\$506;
+TERM_BR0=\$506; \ eUSCI_A baud rate 0
+TERM_BR1=\$507; \ eUSCI_A baud rate 1
+TERM_MCTLW=\$508; \ eUSCI_A modulation control
+TERM_STATW=\$50A; \ eUSCI_A status
+TERM_RXBUF=\$50C; \ eUSCI_A receive buffer
+TERM_TXBUF=\$50E; \ eUSCI_A transmit buffer
+TERM_IE=\$51A; \ eUSCI_A interrupt enable
+TERM_IFG=\$51C; \ eUSCI_A interrupt flags
+TERM_IV=\$51E; \ eUSCI_A interrupt vector word
-!LCD Vo driver
-!-------------
-LCDVo_DIR=\$204! P1.6 = LCDVo
-LCDVo_SEL=\$20A! SEL0
-LCDVo=\$40!
-!LCD timer
-LCD_TIM_CTL=\$300! TA0CTL
-LCD_TIM_CCTLn=\$306! TA0CCTL2
-LCD_TIM_CCR0=\$312! TA0CCR0
-LCD_TIM_CCRn=\$316! TA0CCR2
-LCD_TIM_EX0=\$320! TA0EX0
+RTS=8; ; P2.3
+CTS=\$10; ; P2.4
+HANDSHAKIN=\$201;
+HANDSHAKOUT=\$203;
-!LCD command bus
-!---------------
-LCD_CMD_IN=\$200!
-LCD_CMD_OUT=\$202!
-LCD_CMD_DIR=\$204!
-LCD_CMD_REN=\$206!
-LCD_RS=\$08! P1.3 LCD_RS
-LCD_RW=\$10! P1.4 LCD_RW
-LCD_EN=\$20! P1.5 LCD_EN
-LCD_CMD=\$38!
+LFXT_OUT=\$223; P4
+LFXT_DIR=\$225; P4
+LFXT_SEL=\$22B; P4SEL0
+LFXIN=\$2; P4.1
+LFXOUT=\$4; P4.2
-!LCD data bus
-!------------
-LCD_DB_IN=\$240!
-LCD_DB_OUT=\$242!
-LCD_DB_DIR=\$244!
-LCD_DB_REN=\$246!
-LCD_DB=\$0F! P5.0-3 LCD_DATA_BUS
+;LEDs
+; ----
+invert LED numbers because LED1=TXD ;
+LED2_OUT=\$202;
+LED2_DIR=\$204;
+LED2=\$01; P1.0 red LED
+LED1_OUT=\$223;
+LED1_DIR=\$225;
+LED1=\$01; P4.0 green LED, warning ; wired with UART RX ;
-!IR_RC5 input
-!------------
-IR_IN=\$200!
-IR_OUT=\$202!
-IR_DIR=\$204!
-IR_REN=\$206!
-IR_IES=\$218!
-IR_IE=\$21A!
-IR_IFG=\$21C!
-IR_VEC=\$FFE6! P1 int
-RC5=\$80! P1.7 IR_RC5
+;switches
+ ;--------
+SW1_IN=\$200;
+SW1=\$04; P1.2 = S1
+SW2_IN=\$201;
+SW2=\$40; P2.6 = S2
-!IR_RC5 timer
-IR_TIM_CTL=\$340! TA1CTL
-IR_TIM_CCTLn=\$346! TA1CCTL2
-IR_TIM_R=\$350! TA1R
-IR_TIM_CCR0=\$352! TA1CCR0
-IR_TIM_CCRn=\$356! TA1CCR2
-IR_TIM_EX0=\$360! TA1EX0
+; ============================================
+; UARTI2CS APPLICATION
+; ============================================
+I2CSM_IN=\$261;
+I2CSM_OUT=\$263;
+I2CSM_DIR=\$265;
+I2CSM_REN=\$267;
+SM_SDA=\$04; P8.2 SDA software MASTER
+SM_SCL=\$08; P8.3 SCL software MASTER
+SM_BUS=\$0C;
+;500_ms_INT TIMER
+TIM_CTL=\$300; TA0
+TIM_CCTL2=\$306;
+TIM_CCR0=\$312;
+TIM_CCR2=\$316;
+T_OUT2=\$40; P1.6 <--- TA0.2
+T_OUT2_DIR=\$204; P1DIR
+T_OUT2_SEL=\$20C; P1SEL1
+INT_IN=\$80; P1.7
+INT_IN_IE=\$21A; P1IE
+INT_IN_IFG=\$21C; P1IFG
+INT_IN_VEC=\$FFE6; P1VEC
-I2CSM_IN=\$261!
-I2CSM_OUT=\$263!
-I2CSM_DIR=\$265!
-I2CSM_REN=\$267!
-SM_SDA=\$04! P8.2 SDA software MASTER
-SM_SCL=\$08! P8.3 SCL software MASTER
-SM_BUS=\$0C!
+;local variables
+UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+TIMER_CONF=\{UARTI2CS\}\+12; <-- TIM_CTL configuration
+COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+; --------------------------------------------
-I2CSMM_IN=\$261!
-I2CSMM_OUT=\$263!
-I2CSMM_DIR=\$265!
-I2CSMM_REN=\$267!
-SMM_SDA=\$04! P8.2 SDA software MULTI_MASTER
-SMM_SCL=\$08! P8.3 SCL software MULTI_MASTER
-SMM_BUS=\$0C!
+; ============================================
+; RC5toLCD APPLICATION
+; ============================================
+;LCD Vo driver
+; -------------
+LCDVo_DIR=\$204; P1.6 = LCDVo
+LCDVo_SEL=\$20A; SEL0
+LCDVo=\$40;
+;LCD timer
+LCD_TIM_CTL=\$300; TA0CTL
+LCD_TIM_CCTLn=\$306; TA0CCTL2
+LCD_TIM_CCR0=\$312; TA0CCR0
+LCD_TIM_CCRn=\$316; TA0CCR2
+LCD_TIM_EX0=\$320; TA0EX0
+;LCD command bus
+ ;---------------
+LCD_CMD_IN=\$200;
+LCD_CMD_OUT=\$202;
+LCD_CMD_DIR=\$204;
+LCD_CMD_REN=\$206;
+LCD_RS=\$08; P1.3 LCD_RS
+LCD_RW=\$10; P1.4 LCD_RW
+LCD_EN=\$20; P1.5 LCD_EN
+LCD_CMD=\$38;
+;LCD data bus
+; ------------
+LCD_DB_IN=\$240;
+LCD_DB_OUT=\$242;
+LCD_DB_DIR=\$244;
+LCD_DB_REN=\$246;
+LCD_DB=\$0F; P5.0-3 LCD_DATA_BUS
+;IR_RC5 input
+; ------------
+IR_IN=\$200;
+IR_OUT=\$202;
+IR_DIR=\$204;
+IR_REN=\$206;
+IR_IES=\$218;
+IR_IE=\$21A;
+IR_IFG=\$21C;
+IR_VEC=\$FFE6; P1 int
+RC5=\$80; P1.7 IR_RC5
+;IR_RC5 timer
+IR_TIM_CTL=\$340; TA1CTL
+IR_TIM_CCTLn=\$346; TA1CCTL2
+IR_TIM_R=\$350; TA1R
+IR_TIM_CCR0=\$352; TA1CCR0
+IR_TIM_CCRn=\$356; TA1CCR2
+IR_TIM_EX0=\$360; TA1EX0
+; --------------------------------------------
-I2CMM_IN=\$240!
-I2CMM_OUT=\$242!
-I2CMM_DIR=\$244!
-I2CMM_REN=\$246!
-I2CMM_SEL=\$24A! SEL0
-I2CMM_VEC=\$FFEA! UCB0_VEC
-MM_SDA=\$04! P5.2 SDA hadware MULTI_MASTER
-MM_SCL=\$08! P5.3 SCL hadware MULTI_MASTER
-MM_BUS=\$0C!
+I2CSMM_IN=\$261;
+I2CSMM_OUT=\$263;
+I2CSMM_DIR=\$265;
+I2CSMM_REN=\$267;
+SMM_SDA=\$04; P8.2 SDA software MULTI_MASTER
+SMM_SCL=\$08; P8.3 SCL software MULTI_MASTER
+SMM_BUS=\$0C;
-I2CM_IN=\$240!
-I2CM_OUT=\$242!
-I2CM_DIR=\$244!
-I2CM_REN=\$246!
-I2CM_SEL=\$24A! SEL0
-I2CM_VEC=\$FFEA! UCB0_VEC
-M_SDA=\$04! P5.2 SDA hadware MASTER
-M_SCL=\$08! P5.3 SCL hadware MASTER
-M_BUS=\$0C!
+I2CMM_IN=\$240;
+I2CMM_OUT=\$242;
+I2CMM_DIR=\$244;
+I2CMM_REN=\$246;
+I2CMM_SEL=\$24A; SEL0
+I2CMM_VEC=\$FFEA; UCB0_VEC
+MM_SDA=\$04; P5.2 SDA hadware MULTI_MASTER
+MM_SCL=\$08; P5.3 SCL hadware MULTI_MASTER
+MM_BUS=\$0C;
-I2CS_IN=\$240!
-I2CS_OUT=\$242!
-I2CS_DIR=\$244!
-I2CS_REN=\$246!
-I2CS_SEL=\$24A! SEL0
-I2CS_VEC=\$FFEA! UCB0_VEC
-S_SDA=\$04! P5.2 SDA hadware SLAVE
-S_SCL=\$08! P5.3 SCL hadware SLAVE
-S_BUS=\$0C!
+I2CM_IN=\$240;
+I2CM_OUT=\$242;
+I2CM_DIR=\$244;
+I2CM_REN=\$246;
+I2CM_SEL=\$24A; SEL0
+I2CM_VEC=\$FFEA; UCB0_VEC
+M_SDA=\$04; P5.2 SDA hadware MASTER
+M_SCL=\$08; P5.3 SCL hadware MASTER
+M_BUS=\$0C;
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
+I2CS_IN=\$240;
+I2CS_OUT=\$242;
+I2CS_DIR=\$244;
+I2CS_REN=\$246;
+I2CS_SEL=\$24A; SEL0
+I2CS_VEC=\$FFEA; UCB0_VEC
+S_SDA=\$04; P5.2 SDA hadware SLAVE
+S_SCL=\$08; P5.3 SCL hadware SLAVE
+S_BUS=\$0C;
-I2CM_CTLW0=\$540! USCI_B0 Control Word Register 0
-I2CM_CTLW1=\$542! USCI_B0 Control Word Register 1
-I2CM_BRW=\$546! USCI_B0 Baud Word Rate 0
-I2CM_STATW=\$548! USCI_B0 status word
-I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold
-I2CM_RXBUF=\$54C! USCI_B0 Receive Buffer 8
-I2CM_TXBUF=\$54E! USCI_B0 Transmit Buffer 8
-I2CM_I2COA0=\$554! USCI_B0 I2C Own Address 0
-I2CM_ADDRX=\$55C! USCI_B0 Received Address Register
-I2CM_I2CSA=\$560! USCI_B0 I2C Slave Address
-I2CM_IE=\$56A! USCI_B0 Interrupt Enable
-I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register
+I2CM_CTLW0=\$540; USCI_B0 Control Word Register 0
+I2CM_CTLW1=\$542; USCI_B0 Control Word Register 1
+I2CM_BRW=\$546; USCI_B0 Baud Word Rate 0
+I2CM_STATW=\$548; USCI_B0 status word
+I2CM_TBCNT=\$54A; USCI_B0 byte counter threshold
+I2CM_RXBUF=\$54C; USCI_B0 Receive Buffer 8
+I2CM_TXBUF=\$54E; USCI_B0 Transmit Buffer 8
+I2CM_I2COA0=\$554; USCI_B0 I2C Own Address 0
+I2CM_ADDRX=\$55C; USCI_B0 Received Address Register
+I2CM_I2CSA=\$560; USCI_B0 I2C Slave Address
+I2CM_IE=\$56A; USCI_B0 Interrupt Enable
+I2CM_IFG=\$56C; USCI_B0 Interrupt Flags Register
-I2CS_CTLW0=\$540! USCI_B0 Control Word Register 0
-I2CS_CTLW1=\$542! USCI_B0 Control Word Register 1
-I2CS_BRW=\$546! USCI_B0 Baud Word Rate 0
-I2CS_STATW=\$548! USCI_B0 status word
-I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold
-I2CS_RXBUF=\$54C! USCI_B0 Receive Buffer 8
-I2CS_TXBUF=\$54E! USCI_B0 Transmit Buffer 8
-I2CS_I2COA0=\$554! USCI_B0 I2C Own Address 0
-I2CS_ADDRX=\$55C! USCI_B0 Received Address Register
-I2CS_I2CSA=\$560! USCI_B0 I2C Slave Address
-I2CS_IE=\$56A! USCI_B0 Interrupt Enable
-I2CS_IFG=\$56C! USCI_B0 Interrupt Flags Register
+I2CS_CTLW0=\$540; USCI_B0 Control Word Register 0
+I2CS_CTLW1=\$542; USCI_B0 Control Word Register 1
+I2CS_BRW=\$546; USCI_B0 Baud Word Rate 0
+I2CS_STATW=\$548; USCI_B0 status word
+I2CS_TBCNT=\$54A; USCI_B0 byte counter threshold
+I2CS_RXBUF=\$54C; USCI_B0 Receive Buffer 8
+I2CS_TXBUF=\$54E; USCI_B0 Transmit Buffer 8
+I2CS_I2COA0=\$554; USCI_B0 I2C Own Address 0
+I2CS_ADDRX=\$55C; USCI_B0 Received Address Register
+I2CS_I2CSA=\$560; USCI_B0 I2C Slave Address
+I2CS_IE=\$56A; USCI_B0 Interrupt Enable
+I2CS_IFG=\$56C; USCI_B0 Interrupt Flags Register
-CD_SD=2! ; P8.1 as Card Detect
-SD_CDIN=\$261!
+CD_SD=2; ; P8.1 as Card Detect
+SD_CDIN=\$261;
-CS_SD=1! ; P8.0 as Card Select
-SD_CSOUT=\$263!
-SD_CSDIR=\$265!
+CS_SD=1; ; P8.0 as Card Select
+SD_CSOUT=\$263;
+SD_CSDIR=\$265;
-BUS_SD=\$000E! ; pins P5.1 as UCB0CLK, P5.2 as UCB0SIMO & P5.3 as UCB0SOMI
-SD_SEL=\$24A! ; PCSEL0 to configure UCB0
-SD_REN=\$246! ; PCREN to configure pullup resistors
+BUS_SD=\$000E; ; pins P5.1 as UCB0CLK, P5.2 as UCB0SIMO & P5.3 as UCB0SOMI
+SD_SEL=\$24A; ; PCSEL0 to configure UCB0
+SD_REN=\$246; ; PCREN to configure pullup resistors
-! -*- coding: utf-8 -*-
-! MSP_EXP430FR5739.pat
-!
-\.f=\.4th for MSP_EXP430FR5739! to change file type
-
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! replace ! by semicolon
+; MSP_EXP430FR5739.pat
+;
+\.f=\.4th for MSP_EXP430FR5739; to change file type
+
+; ========================
+; remove comments
+; ========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! MSP430FR5739 Config
-! ======================================================================
+; ======================================================================
+; MSP430FR5739 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR5739.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR57xx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-!
-! ======================================================================
-! MSP_EXP430FR5739 board
-! ======================================================================
-
-! blue LEDs (Px.y ---> resistor ---> LED ---> GND)
-! PJ.0 - LED1
-! PJ.1 - LED2
-! PJ.2 - LED3
-! PJ.3 - LED4
-! P3.4 - LED5
-! P3.5 - LED6
-! P3.6 - LED7
-! P3.7 - LED8
-!
-! I/O pins on SV1:
-! P1.0 - SV1.1
-! P1.1 - SV1.2
-! P1.2 - SV1.3
-! P3.0 - SV1.4
-! P3.1 - SV1.5
-! P3.2 - SV1.6
-! P3.3 - SV1.7
-! P1.3 - SV1.8
-! P1.4 - SV1.9
-! P1.5 - SV1.10
-! P4.0 - SV1.11
-! GND - SV1.12
-!
-! I/O pins on SV2:
-! P1.7 - SV2.1
-! P1.6 - SV2.2
-! P3.7 - SV2.3
-! P3.6 - SV2.4
-! P3.5 - SV2.5
-! P3.4 - SV2.6
-! P2.2 - SV2.7
-! P2.1 - SV2.8
-! P2.6 - SV2.9
-! P2.5 - SV2.10
-! P2.0 - SV2.11
-! VCC - SV2.12
-!
-! I/O pins on RF:
-! GND - RF.1
-! VCC - RF.2
-! P2.0 - RF.3
-! P1.0 - RF.4
-! P2.6 - RF.5
-! P1.1 - RF.6
-! P2.5 - RF.7
-! P1.2 - RF.8
-! P2.7 - RF.9
-! P2.3 - RF.10
-! P4.0 - RF.11
-! GND - RF.12
-! P4.1 - RF.13
-! P2.4 - RF.14
-! P1.7 - RF.15
-! P2.2 - RF.16
-! P1.3 - RF.17
-! P1.6 - RF.18
-!
-! Accelerometer:
-! P2.7 - VS
-! P3.0 - XOUT
-! P3.1 - YOUT
-! P3.2 - ZOUT
-!
-! LDR and NTC:
-! P2.7 - VS
-! P3.3 - LDR
-! P1.4 - NTC
-!
-! RST - reset
-!
-! ======================================================================
-! MSP-EXP430FR5739 LAUNCHPAD <--> OUTPUT WORLD
-! ======================================================================
-!
-! P4.0 - Switch S1 <--- LCD contrast + (finger :-)
-! P4.1 - Switch S2 <--- LCD contrast - (finger :-)
-!
-! GND <-------+---0V0----------> 1 LCD_Vss
-! VCC >------ | --3V6-----+----> 2 LCD_Vdd
-! | |
-! |___ 470n ---
-! ^ | ---
-! / \ BAT54 |
-! --- |
-! 100n | 2k2 |
-! P1.5 - UCB0 CLK TB0.2 SV1.10 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! P3.4 - SV2.6 -------------------------> 4 LCD_RS
-! P3.5 - SV2.5 -------------------------> 5 LCD_R/W
-! P3.6 - SV2.4 -------------------------> 6 LCD_EN
-! P1.0 - SV1.1 <------------------------> 11 LCD_DB4
-! P1.1 - SV1.2 <------------------------> 12 LCD_DB5
-! P1.2 - SV1.3 <------------------------> 13 LCD_DB5
-! P1.3 - SV1.8 <------------------------> 14 LCD_DB7
-!
-! PJ.4 - LFXI 32768Hz quartz
-! PJ.5 - LFXO 32768Hz quartz
-! PJ.6 - HFXI
-! PJ.7 - HFXO
-! +--4k7-< DeepRST <-- GND
-! |
-! P2.0 - UCA0 TXD SV2.11 --+-> RX UARTtoUSB bridge
-! P2.1 - UCA0 RXD SV2.8 <---- TX UARTtoUSB bridge
-! VCC - <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
-! GND - <---> GND (optional supply from UARTtoUSB bridge)
-!
-! VCC - RF.2
-! VSS - RF.1
-! P2.2 - RF.16 <---- CD SD_CardAdapter (Card Detect)
-! P2.3 - RF.10 ----> CS SD_CardAdapter (Card Select)
-! P2.4 - UCA1 CLK RF.14 ----> CLK SD_CardAdapter (SCK)
-! P2.5 - UCA1 TXD/SIMO RF.7 ----> SDI SD_CardAdapter (MOSI)
-! P2.6 - UCA1 RXD/SOMI RF.5 <---- SDO SD_CardAdapter (MISO)
-!
-! P2.7 - RF.9 <---- OUT IR_Receiver (1 TSOP32236)
-!
-! P1.7 - UCB0 SCL/SOMI SV2.1 <---> SCL I2C MASTER/SLAVE
-! P1.6 - UCB0 SDA/SIMO SV2.2 <---> SDA I2C MASTER/SLAVE
-
-! ============================================
-! FORTH I/O :
-! ============================================
-!TERMINAL
-BUS_TERM=3! \ P2.0 = TX, P2.1 = RX
-
-TERM_IN=\$201!
-TERM_REN=\$207!
-TERM_SEL=\$20D!
-
-TERM_VEC=\$FFF0! \ UCA0
-WAKE_UP=1! \ RX int
-
-TERM_CTLW0=\$5C0! \ eUSCI_A control word 0
-TERM_CTLW1=\$5C2! \ eUSCI_A control word 1
-TERM_BRW=\$5C6!
-TERM_BR0=\$5C6! \ eUSCI_A baud rate 0
-TERM_BR1=\$5C7! \ eUSCI_A baud rate 1
-TERM_MCTLW=\$5C8! \ eUSCI_A modulation control
-TERM_STATW=\$5CA! \ eUSCI_A status
-TERM_RXBUF=\$5CC! \ eUSCI_A receive buffer
-TERM_TXBUF=\$5CE! \ eUSCI_A transmit buffer
-TERM_ABCTL=\$5D0! \ eUSCI_A LIN control
-TERM_IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-TERM_IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-TERM_IE=\$5DA! \ eUSCI_A interrupt enable
-TERM_IFG=\$5DC! \ eUSCI_A interrupt flags
-TERM_IV=\$5DE! \ eUSCI_A interrupt vector word
-
-RTS=4!
-CTS=8!
-HANDSHAKIN=\$201!
-HANDSHAKOUT=\$203!
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-LED1_OUT=\$322!
-LED1=\$01! PJ.0
-
-LED2_OUT=\$322!
-LED2=\$02! PJ.1
-
-SW1_IN=\$221!
-SW1=\$01! P4.0 = S1
-
-WIPE_IN=\$221!
-IO_WIPE=\$01! P4.0 = S1 = = FORTH Deep_RST pin
-
-SW2_IN=\$221!
-SW2=\$02! P4.1 = S2
-
-LCDVo_DIR=\$204!
-LCDVo_SEL=\$20A! SEL0
-LCDVo=\$20! P1.5
-
-LCD_CMD_IN=\$220!
-LCD_CMD_OUT=\$222!
-LCD_CMD_DIR=\$224!
-LCD_CMD_REN=\$226!
-LCD_RS=\$10! P3.4
-LCD_RW=\$20! P3.5
-LCD_EN=\$40! P3.6
-LCD_CMD=\$70!
-
-LCD_DB_IN=\$200!
-LCD_DB_OUT=\$202!
-LCD_DB_DIR=\$204!
-LCD_DB_REN=\$206!
-LCD_DB=\$0F! P1.0-3
-!LCD timer
-LCD_TIM_CTL=\$3C0! TB0CTL
-LCD_TIM_CCTLn=\$3C6! TB0CCTL2
-LCD_TIM_CCR0=\$3D2! TB0CCR0
-LCD_TIM_CCRn=\$3D6! TB0CCR2
-LCD_TIM_EX0=\$3E0! TB0EX0
-
-
-!WATCHDOG timer
-WDT_TIM_CTL=\$340! TA0CTL
-WDT_TIM_CCTL0=\$342! TA0CCTL0
-WDT_TIM_CCR0=\$352! TA0CCR0
-WDT_TIM_EX0=\$360! TA0EX0
-WDT_TIM_0_VEC=\$FFEA! TA0_0_VEC
-
-IR_IN=\$201!
-IR_OUT=\$203!
-IR_DIR=\$205!
-IR_REN=\$207!
-IR_IES=\$219!
-IR_IE=\$21B!
-IR_IFG=\$21D!
-RC5_=RC5_!
-RC5=\$40! P2.6
-IR_VEC=\$FFD8! P2 int
-!IR_RC5 timer
-RC5_TIM_CTL=\$380! TA1CTL
-RC5_TIM_R=\$390! TA1R
-RC5_TIM_EX0=\$3A0! TA1EX0
-
-I2CSM_IN=\$221!
-I2CSM_OUT=\$223!
-I2CSM_DIR=\$225!
-I2CSM_REN=\$207!
-SM_SDA=1! P4.0
-SM_SCL=2! P4.1
-SM_BUS=3!
-
-I2CSMM_IN=\$221!
-I2CSMM_OUT=\$223!
-I2CSMM_DIR=\$225!
-I2CSMM_REN=\$227!
-SMM_SDA=1! P4.0
-SMM_SCL=2! P4.1
-SMM_BUS=3!
+;
+; ======================================================================
+; MSP_EXP430FR5739 board
+; ======================================================================
+
+; blue LEDs (Px.y ---> resistor ---> LED ---> GND)
+; PJ.0 - LED1
+; PJ.1 - LED2
+; PJ.2 - LED3
+; PJ.3 - LED4
+; P3.4 - LED5
+; P3.5 - LED6
+; P3.6 - LED7
+; P3.7 - LED8
+;
+; I/O pins on SV1:
+; P1.0 - SV1.1
+; P1.1 - SV1.2
+; P1.2 - SV1.3
+; P3.0 - SV1.4
+; P3.1 - SV1.5
+; P3.2 - SV1.6
+; P3.3 - SV1.7
+; P1.3 - SV1.8
+; P1.4 - SV1.9
+; P1.5 - SV1.10
+; P4.0 - SV1.11
+; GND - SV1.12
+;
+; I/O pins on SV2:
+; P1.7 - SV2.1
+; P1.6 - SV2.2
+; P3.7 - SV2.3
+; P3.6 - SV2.4
+; P3.5 - SV2.5
+; P3.4 - SV2.6
+; P2.2 - SV2.7
+; P2.1 - SV2.8
+; P2.6 - SV2.9
+; P2.5 - SV2.10
+; P2.0 - SV2.11
+; VCC - SV2.12
+;
+; I/O pins on RF:
+; GND - RF.1
+; VCC - RF.2
+; P2.0 - RF.3
+; P1.0 - RF.4
+; P2.6 - RF.5
+; P1.1 - RF.6
+; P2.5 - RF.7
+; P1.2 - RF.8
+; P2.7 - RF.9
+; P2.3 - RF.10
+; P4.0 - RF.11
+; GND - RF.12
+; P4.1 - RF.13
+; P2.4 - RF.14
+; P1.7 - RF.15
+; P2.2 - RF.16
+; P1.3 - RF.17
+; P1.6 - RF.18
+;
+; Accelerometer:
+; P2.7 - VS
+; P3.0 - XOUT
+; P3.1 - YOUT
+; P3.2 - ZOUT
+;
+; LDR and NTC:
+; P2.7 - VS
+; P3.3 - LDR
+; P1.4 - NTC
+;
+; RST - reset
+;
+; ======================================================================
+; MSP-EXP430FR5739 LAUNCHPAD <--> OUTPUT WORLD
+; ======================================================================
+;
+; P4.0 - Switch S1 <--- LCD contrast + (finger :-)
+; P4.1 - Switch S2 <--- LCD contrast - (finger :-)
+;
+; GND <-------+---0V0----------> 1 LCD_Vss
+; VCC >------ | --3V6-----+----> 2 LCD_Vdd
+; | |
+; |___ 470n ---
+; ^ | ---
+; / \ BAT54 |
+; --- |
+; 100n | 2k2 |
+; P1.5 - UCB0 CLK TB0.2 SV1.10 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; P3.4 - SV2.6 -------------------------> 4 LCD_RS
+; P3.5 - SV2.5 -------------------------> 5 LCD_R/W
+; P3.6 - SV2.4 -------------------------> 6 LCD_EN
+; P1.0 - SV1.1 <------------------------> 11 LCD_DB4
+; P1.1 - SV1.2 <------------------------> 12 LCD_DB5
+; P1.2 - SV1.3 <------------------------> 13 LCD_DB5
+; P1.3 - SV1.8 <------------------------> 14 LCD_DB7
+;
+; PJ.4 - LFXI 32768Hz quartz
+; PJ.5 - LFXO 32768Hz quartz
+; PJ.6 - HFXI
+; PJ.7 - HFXO
+; +--4k7-< DeepRST <-- GND
+; |
+; P2.0 - UCA0 TXD SV2.11 --+-> RX UARTtoUSB bridge
+; P2.1 - UCA0 RXD SV2.8 <---- TX UARTtoUSB bridge
+; VCC - <---- VCC (optional supply from UARTtoUSB bridge - WARNING ; 3.3V !)
+; GND - <---> GND (optional supply from UARTtoUSB bridge)
+;
+; VCC - RF.2
+; VSS - RF.1
+; P2.2 - RF.16 <---- CD SD_CardAdapter (Card Detect)
+; P2.3 - RF.10 ----> CS SD_CardAdapter (Card Select)
+; P2.4 - UCA1 CLK RF.14 ----> CLK SD_CardAdapter (SCK)
+; P2.5 - UCA1 TXD/SIMO RF.7 ----> SDI SD_CardAdapter (MOSI)
+; P2.6 - UCA1 RXD/SOMI RF.5 <---- SDO SD_CardAdapter (MISO)
+;
+; P2.7 - RF.9 <---- OUT IR_Receiver (1 TSOP32236)
+;
+; P1.7 - UCB0 SCL/SOMI SV2.1 <---> SCL I2C MASTER/SLAVE
+; P1.6 - UCB0 SDA/SIMO SV2.2 <---> SDA I2C MASTER/SLAVE
+
+; ----------------------------------------------------------------------
+; MSP430FR5739 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;FRAM_SFR .equ 0140h ; FRAM control
+;CRC16_SFR .equ 0150h
+;WDT_A_SFR .equ 015Ch ; Watchdog
+;CS_SFR .equ 0160h
+;SYS_SFR .equ 0180h ; SYS
+;REF_SFR .equ 01B0h ; REF
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3/4
+;PJ_SFR .equ 0320h ; PORTJ
+;TA0_SFR .equ 0340h
+;TA1_SFR .equ 0380h
+;TB0_SFR .equ 03C0h
+;TB1_SFR .equ 0400h
+;TB2_SFR .equ 0440h
+;RTC_B_SFR .equ 04A0h
+;MPY_SFR .equ 04C0h
+;DMA_CTRL_SFR .equ 0500h
+;DMA_CHN0_SFR .equ 0510h
+;DMA_CHN1_SFR .equ 0520h
+;DMA_CHN2_SFR .equ 0530h
+;MPU_SFR .equ 05A0h ; memory protect unit
+;eUSCI_A0_SFR .equ 05C0h ; eUSCI_A0
+;eUSCI_A1_SFR .equ 05E0h ; eUSCI_A1
+;eUSCI_B0_SFR .equ 0640h ; eUSCI_B0
+;ADC10_B_SFR .equ 0700h
+;COMP_D_SFR .equ 08C0h
+
+; ----------------------------------------------
+; Interrupt Vectors - MSP430FR57xx
+; ----------------------------------------------
+; FFCE-FFFF 24 vectors + reset
+; 0FFCEh - RTC_B
+; 0FFD0h - I/O Port 4
+; 0FFD2h - I/O Port 3
+; 0FFD4h - TB2_1
+; 0FFD6h - TB2_0
+; 0FFD8h - I/O Port 2
+; 0FFDAh - TB1_1
+; 0FFDCh - TB1_0
+; 0FFDEh - I/O Port 1
+; 0FFE0h - TA1_1
+; 0FFE2h - TA1_0
+; 0FFE4h - DMA
+; 0FFE6h - eUSCI_A1
+; 0FFE8h - TA0_1
+; 0FFEAh - TA0_0
+; 0FFECh - ADC10_B
+; 0FFEEh - eUSCI_B0
+; 0FFF0h - eUSCI_A0
+; 0FFF2h - Watchdog
+; 0FFF4h - TB0_1
+; 0FFF6h - TB0_0
+; 0FFF8h - COMP_D
+; 0FFFAh - userNMI
+; 0FFFCh - sysNMI
+; 0FFFEh - reset
+
+; ============================================
+; FAST FORTH configuration :
+; ============================================
+;TERMINAL
+BUS_TERM=3; \ P2.0 = TX, P2.1 = RX
+TERM_IN=\$201;
+TERM_REN=\$207;
+TERM_SEL=\$20D;
+
+TERM_VEC=\$FFF0; \ UCA0
+WAKE_UP=1; \ RX int
+RX=1; RX flag IFG
+TX=2; Tx flag IFG
+
+TERM_CTLW0=\$5C0; \ eUSCI_A control word 0
+TERM_CTLW1=\$5C2; \ eUSCI_A control word 1
+TERM_BRW=\$5C6;
+TERM_BR0=\$5C6; \ eUSCI_A baud rate 0
+TERM_BR1=\$5C7; \ eUSCI_A baud rate 1
+TERM_MCTLW=\$5C8; \ eUSCI_A modulation control
+TERM_STATW=\$5CA; \ eUSCI_A status
+TERM_RXBUF=\$5CC; \ eUSCI_A receive buffer
+TERM_TXBUF=\$5CE; \ eUSCI_A transmit buffer
+TERM_ABCTL=\$5D0; \ eUSCI_A LIN control
+TERM_IRTCTL=\$5D2; \ eUSCI_A IrDA transmit control
+TERM_IRRCTL=\$5D3; \ eUSCI_A IrDA receive control
+TERM_IE=\$5DA; \ eUSCI_A interrupt enable
+TERM_IFG=\$5DC; \ eUSCI_A interrupt flags
+TERM_IV=\$5DE; \ eUSCI_A interrupt vector word
+
+RTS=4;
+CTS=8;
+HANDSHAKIN=\$201;
+HANDSHAKOUT=\$203;
+
+LFXT_OUT=\$322; PJ
+LFXT_DIR=\$324; PJ
+LFXT_SEL=\$32A; PJSEL0
+LFXIN=\$10; PJ.4
+LFXOUT=\$20; PJ.5
+
+; FAST FORTH I/O :
+LED1_OUT=\$322;
+LED1_DIR=\$324;
+LED1=\$01; PJ.0
+LED2_OUT=\$322;
+LED2_DIR=\$324;
+LED2=\$02; PJ.1
+
+SW1_IN=\$221;
+SW1=\$01; P4.0 = S1
+SW2_IN=\$221;
+SW2=\$02; P4.1 = S2
+
+; ============================================
+; UARTI2CS APPLICATION
+; ============================================
+I2CSM_IN=\$221;
+I2CSM_OUT=\$223;
+I2CSM_DIR=\$225;
+I2CSM_REN=\$207;
+SM_SDA=1; P4.0
+SM_SCL=2; P4.1
+SM_BUS=3;
+
+;500_ms_INT TIMER
+TIM_CTL=\$340; TA0
+TIM_CCTL2=\$346;
+TIM_CCR0=\$352;
+TIM_CCR2=\$356;
+T_OUT2=2; P1.1 <--- TA0.2
+T_OUT2_DIR=\$204; P1DIR
+T_OUT2_SEL=\$20C; P1SEL1
+INT_IN=1; P1.0
+INT_IN_IE=\$21A; P1IE
+INT_IN_IFG=\$21C; P1IFG
+INT_IN_VEC=\$FFDE; P1VEC
+
+;local variables
+UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+TIMER_CONF=\{UARTI2CS\}\+12; <-- TIM_CTL configuration
+COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+; ============================================
+; RC5toLCD APPLICATION
+; ============================================
+LCDVo_DIR=\$204;
+LCDVo_SEL=\$20A; SEL0
+LCDVo=\$20; P1.5
+;LCD command bus
+LCD_CMD_IN=\$220;
+LCD_CMD_OUT=\$222;
+LCD_CMD_DIR=\$224;
+LCD_CMD_REN=\$226;
+LCD_RS=\$10; P3.4
+LCD_RW=\$20; P3.5
+LCD_EN=\$40; P3.6
+LCD_CMD=\$70;
+;LCD command bus
+LCD_DB_IN=\$200;
+LCD_DB_OUT=\$202;
+LCD_DB_DIR=\$204;
+LCD_DB_REN=\$206;
+LCD_DB=\$0F; P1.0-3
+;LCD timer
+LCD_TIM_CTL=\$3C0; TB0CTL
+LCD_TIM_CCTLn=\$3C6; TB0CCTL2
+LCD_TIM_CCR0=\$3D2; TB0CCR0
+LCD_TIM_CCRn=\$3D6; TB0CCR2
+LCD_TIM_EX0=\$3E0; TB0EX0
+;WATCHDOG timer
+WDT_TIM_CTL=\$340; TA0CTL
+WDT_TIM_CCTL0=\$342; TA0CCTL0
+WDT_TIM_CCR0=\$352; TA0CCR0
+WDT_TIM_EX0=\$360; TA0EX0
+WDT_TIM_0_VEC=\$FFEA; TA0_0_VEC
+;IR_RC5
+IR_IN=\$201;
+IR_OUT=\$203;
+IR_DIR=\$205;
+IR_REN=\$207;
+IR_IES=\$219;
+IR_IE=\$21B;
+IR_IFG=\$21D;
+RC5_=RC5_;
+RC5=\$40; P2.6
+IR_VEC=\$FFD8; P2 int
+;IR_RC5 timer
+RC5_TIM_CTL=\$380; TA1CTL
+RC5_TIM_R=\$390; TA1R
+RC5_TIM_EX0=\$3A0; TA1EX0
+; --------------------------------------------
+
+I2CSMM_IN=\$221;
+I2CSMM_OUT=\$223;
+I2CSMM_DIR=\$225;
+I2CSMM_REN=\$227;
+SMM_SDA=1; P4.0
+SMM_SCL=2; P4.1
+SMM_BUS=3;
I2CMM_IN=\$200
I2CMM_OUT=\$202
I2CMM_DIR=\$204
I2CMM_REN=\$206
-I2CMM_SEL=\$20C! SEL1
-I2CMM_VEC=\$FFEE! eUSCIB0_INT
-MM_SDA=\$40! P1.6
-MM_SCL=\$80! P1.7
+I2CMM_SEL=\$20C; SEL1
+I2CMM_VEC=\$FFEE; eUSCIB0_INT
+MM_SDA=\$40; P1.6
+MM_SCL=\$80; P1.7
MM_BUS=\$C0
I2CM_IN=\$200
I2CM_OUT=\$202
I2CM_DIR=\$204
I2CM_REN=\$206
-I2CM_SEL=\$20C! SEL1
-I2CM_VEC=\$FFEE! eUSCIB0_INT
-M_SDA=\$40! P1.6
-M_SCL=\$80! P1.7
+I2CM_SEL=\$20C; SEL1
+I2CM_VEC=\$FFEE; eUSCIB0_INT
+M_SDA=\$40; P1.6
+M_SCL=\$80; P1.7
M_BUS=\$C0
I2CS_IN=\$200
I2CS_OUT=\$202
I2CS_DIR=\$204
I2CS_REN=\$206
-I2CS_SEL=\$20C! SEL1
-I2CS_VEC=\$FFEE! eUSCIB0_INT
-S_SDA=\$40! P1.6
-S_SCL=\$80! P1.7
+I2CS_SEL=\$20C; SEL1
+I2CS_VEC=\$FFEE; eUSCIB0_INT
+S_SDA=\$40; P1.6
+S_SCL=\$80; P1.7
S_BUS=\$C0
-LED1_OUT=\$322!
-LED1_DIR=\$324!
-LED1=1! PJ.0 LED1 BLUE
-
-LED2_OUT=\$322!
-LED2_DIR=\$324!
-LED2=2! PJ.1 LED2 BLUE
-
-
-
-
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
-
-I2CM_CTLW0=\$640! USCI_B0 Control Word Register 0
-I2CM_CTLW1=\$642! USCI_B0 Control Word Register 1
-I2CM_BRW=\$646! USCI_B0 Baud Word Rate 0
-I2CM_STATW=\$648! USCI_B0 status word
-I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold
-I2CM_RXBUF=\$64C! USCI_B0 Receive Buffer 8
-I2CM_TXBUF=\$64E! USCI_B0 Transmit Buffer 8
-I2CM_I2COA0=\$654! USCI_B0 I2C Own Address 0
-I2CM_ADDRX=\$65C! USCI_B0 Received Address Register
-I2CM_I2CSA=\$660! USCI_B0 I2C Slave Address
-I2CM_IE=\$66A! USCI_B0 Interrupt Enable
-I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register
-
-I2CS_CTLW0=\$640! USCI_B0 Control Word Register 0
-I2CS_CTLW1=\$642! USCI_B0 Control Word Register 1
-I2CS_BRW=\$646! USCI_B0 Baud Word Rate 0
-I2CS_STATW=\$648! USCI_B0 status word
-I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold
-I2CS_RXBUF=\$64C! USCI_B0 Receive Buffer 8
-I2CS_TXBUF=\$64E! USCI_B0 Transmit Buffer 8
-I2CS_I2COA0=\$654! USCI_B0 I2C Own Address 0
-I2CS_ADDRX=\$65C! USCI_B0 Received Address Register
-I2CS_I2CSA=\$660! USCI_B0 I2C Slave Address
-I2CS_IE=\$66A! USCI_B0 Interrupt Enable
-I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register
-
-
-CD_SD=4! P2.2 as Card Detect
-SD_CDIN=\$201!
-
-CS_SD=8! P2.3 as Card Select
-SD_CSOUT=\$203!
-SD_CSDIR=\$205!
-
-BUS_SD=\$70! pins P2.4 as UCB0CLK, P2.5 as UCB0SIMO & P2.6 as UCB0SOMI
-SD_SEL=\$20D! to configure UCB0
-SD_REN=\$207! to configure pullup resistors
+LED1_OUT=\$322;
+LED1_DIR=\$324;
+LED1=1; PJ.0 LED1 BLUE
+
+LED2_OUT=\$322;
+LED2_DIR=\$324;
+LED2=2; PJ.1 LED2 BLUE
+
+
+
+
+UCSWRST=1; eUSCI Software Reset
+UCTXIE=2; eUSCI Transmit Interrupt Enable
+UCRXIE=1; eUSCI Receive Interrupt Enable
+UCTXIFG=2; eUSCI Transmit Interrupt Flag
+UCRXIFG=1; eUSCI Receive Interrupt Flag
+UCTXIE0=2; eUSCI_B Transmit Interrupt Enable
+UCRXIE0=1; eUSCI_B Receive Interrupt Enable
+UCTXIFG0=2; eUSCI_B Transmit Interrupt Flag
+UCRXIFG0=1; eUSCI_B Receive Interrupt Flag
+
+I2CM_CTLW0=\$640; USCI_B0 Control Word Register 0
+I2CM_CTLW1=\$642; USCI_B0 Control Word Register 1
+I2CM_BRW=\$646; USCI_B0 Baud Word Rate 0
+I2CM_STATW=\$648; USCI_B0 status word
+I2CM_TBCNT=\$64A; USCI_B0 byte counter threshold
+I2CM_RXBUF=\$64C; USCI_B0 Receive Buffer 8
+I2CM_TXBUF=\$64E; USCI_B0 Transmit Buffer 8
+I2CM_I2COA0=\$654; USCI_B0 I2C Own Address 0
+I2CM_ADDRX=\$65C; USCI_B0 Received Address Register
+I2CM_I2CSA=\$660; USCI_B0 I2C Slave Address
+I2CM_IE=\$66A; USCI_B0 Interrupt Enable
+I2CM_IFG=\$66C; USCI_B0 Interrupt Flags Register
+
+I2CS_CTLW0=\$640; USCI_B0 Control Word Register 0
+I2CS_CTLW1=\$642; USCI_B0 Control Word Register 1
+I2CS_BRW=\$646; USCI_B0 Baud Word Rate 0
+I2CS_STATW=\$648; USCI_B0 status word
+I2CS_TBCNT=\$64A; USCI_B0 byte counter threshold
+I2CS_RXBUF=\$64C; USCI_B0 Receive Buffer 8
+I2CS_TXBUF=\$64E; USCI_B0 Transmit Buffer 8
+I2CS_I2COA0=\$654; USCI_B0 I2C Own Address 0
+I2CS_ADDRX=\$65C; USCI_B0 Received Address Register
+I2CS_I2CSA=\$660; USCI_B0 I2C Slave Address
+I2CS_IE=\$66A; USCI_B0 Interrupt Enable
+I2CS_IFG=\$66C; USCI_B0 Interrupt Flags Register
+
+
+CD_SD=4; P2.2 as Card Detect
+SD_CDIN=\$201;
+
+CS_SD=8; P2.3 as Card Select
+SD_CSOUT=\$203;
+SD_CSDIR=\$205;
+
+BUS_SD=\$70; pins P2.4 as UCB0CLK, P2.5 as UCB0SIMO & P2.6 as UCB0SOMI
+SD_SEL=\$20D; to configure UCB0
+SD_REN=\$207; to configure pullup resistors
-! -*- coding: utf-8 -*-
-! MSP_EXP430FR5969.pat
-!
-\.f=\.4th for MSP_EXP430FR5969! to change file type
-!
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! replace ! by semicolon
+; MSP_EXP430FR5969.pat
+;
+\.f=\.4th for MSP_EXP430FR5969; to change file type
+; ========================
+; remove comments
+; ========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! MSP430FR5969 Config
-! ======================================================================
+; ======================================================================
+; MSP430FR5969 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR5969.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR5xxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-! ======================================================================
-! MSP_EXP430FR5969 board
-! ======================================================================
-
-! J3: JTAG
-! --------
-! P1 - TDO - PJ.0
-! P2 - V_debug
-! P3 - TDI - PJ.1
-! P4 - V_ext
-! P5 - TMS - PJ.2
-! P6 - NC
-! P7 - TCK - PJ.3
-! P8 - TEST - TEST
-! P9 - GND
-! P10- CTS - P4.0
-! P11- RST - RESET
-! P12- TX0 - P2.0
-! P13- RTS - P4.1
-! P14- RX0 - P2.1
-
-! Launchpad Header Left J4
-! ------------------------
-! P1 - VCC
-! P2 - P4.2
-! P3 - P2.6 UCA1 RX/SOMI
-! P4 - P2.5 UCA1 TX/SIMO
-! P5 - P4.3
-! P6 - P2.4 UCA1 CLK
-! P7 - P2.2 TB0.2 UCB0CLK
-! P8 - P3.4
-! P9 - P3.5
-! P10- P3.6
-
-! Launchpad Header Right J5
-! -------------------------
-! P11- P1.3
-! P12- P1.4
-! P13- P1.5
-! P14- P1.6 UCB0 SIMO/SDA
-! P15- P1.7 UCB0 SOMI/SCL
-! P16- RST
-! P17- NC
-! P18- P3.0
-! P19- P1.2
-! P20- GND
-
-! J13 eZ-FET <=> target
-! ---------------------------
-! P1 P2 NC NC
-! P3 <-> P4 TEST <-> TEST
-! P5 <-> P6 RST <-> RST
-! P7 P8 TX0 P2.0 (no strap)
-! P9 P10 RX0 P2.1 (no strap)
-! P11 P12 CTS P4.0 (no strap)
-! P13 P14 RTS P4.1 (no strap)
-! P15<->P16 V+ <-> VCC
-! P17 P18 5V (no strap)
-! P19---P20 GND-----VSS
-
-! J21 : external target
-! ---------------------
-! P1 - RX0 - P2.1
-! P2 - VCC
-! P3 - TEST - TEST
-! P4 - RST - RST
-! P5 - GND
-! P6 - TX0 - P2.0
-
-
-! -----------------------------------------------
-! MSP430FR5969 LAUNCHPAD <--> OUTPUT WORLD
-! -----------------------------------------------
-
-! J13 jumpers : device <-> eZ-FET
-! -------------------------------
-! P2 P1 NC NC
-! P4<->P3 TEST <-> TEST
-! P6<->P5 RST <-> RST
-! P8 P7 P2.0 TX0 (no jumper)
-! P10 P9 P2.1 RX0 (no jumper)
-! P12 P11 P4.0 CTS (no jumper)
-! P14 P13 P4.1 RTS (no jumper)
-! P16<->P15 VCC <-> V+
-! P18 P17 5V 5V (no jumper)
-! P20---P19 VSS-----GND
-
-! P4.6 - J6 - LED1 red
-! P1.0 - LED2 green
-!
-! P4.5 - Switch S1 <--- LCD contrast + (finger :-)
-! P1.1 - Switch S2 <--- LCD contrast - (finger ;-)
-!
-! GND - J1.2 <-------+---0V0----------> 1 LCD_Vss
-! VCC - J1.3 >------ | --3V6-----+----> 2 LCD_Vdd
-! | |
-! ___ 470n ---
-! ^ ---
-! / \ 1n4148 |
-! --- |
-! 100n | 2k2 |
-! P2.2 - UCB0 CLK TB0.2 J4.7 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! P3.4 - J4.8 -------------------------> 4 LCD_RS
-! P3.5 - J4.9 -------------------------> 5 LCD_R/W
-! P3.6 - J4.10 -------------------------> 6 LCD_EN
-! PJ.0 - J3.1 <------------------------> 11 LCD_DB4
-! PJ.1 - J3.3 <------------------------> 12 LCD_DB5
-! PJ.2 - J3.5 <------------------------> 13 LCD_DB6
-! PJ.3 - J3.7 <------------------------> 14 LCD_DB7
-!
-! +--4k7-< DeepRST <-- GND
-! |
-! P2.0 - UCA0 TXD J13.8 <-+-> RX UARTtoUSB bridge
-! P2.1 - UCA0 RXD J13.10 <---- TX UARTtoUSB bridge
-! P4.1 - RTS J13.14 ----> CTS UARTtoUSB bridge (optional hardware control flow)
-! VCC - J13.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
-! GND - J13.20 <---> GND (optional supply from UARTtoUSB bridge)
-!
-! VCC - J11.1 ----> VCC SD_CardAdapter
-! GND - J12.3 <---> GND SD_CardAdapter
-! P2.4 - UCA1 CLK J4.6 ----> CLK SD_CardAdapter (SCK)
-! P4.3 - J4.5 ----> CS SD_CardAdapter (Card Select)
-! P2.5 - UCA1 TXD/SIMO J4.4 ----> SDI SD_CardAdapter (MOSI)
-! P2.6 - UCA1 RXD/SOMI J4.3 <---- SDO SD_CardAdapter (MISO)
-! P4.2 - J4.2 <---- CD SD_CardAdapter (Card Detect)
-!
-! P4.0 - J3.10 <---- OUT IR_Receiver (1 TSOP32236) ----┌───┐
-! VCC - J3.2 ----> VCC IR_Receiver (2 TSOP32236) ----│ ○ │
-! GND - J3.9 <---> GND IR_Receiver (3 TSOP32236) ----└───┘
-!
-! P1.2 - J5.19 <---> SDA I2C SOFTWARE MASTER
-! P1.3 - J5.11 <---> SCL I2C SOFTWARE MASTER
-! P1.4 - TB0.1 J5.12 <---> free
-! P1.5 - UCA0 CLK TB0.2 J5.13 <---> free
-! P1.7 - UCB0 SCL/SOMI J5.14 ----> SCL I2C MASTER/SLAVE
-! P1.6 - UCB0 SDA/SIMO J5.15 <---> SDA I2C MASTER/SLAVE
-! P3.0 - J5.7 <---- free
-!
-! PJ.4 - LFXI 32768Hz quartz
-! PJ.5 - LFXO 32768Hz quartz
-! PJ.6 - HFXI
-! PJ.7 - HFXO
-!
-! P2.3 - NC
-! P2.7 - NC
-! P3.1 - NC
-! P3.2 - NC
-! P3.3 - NC
-! P3.7 - NC
-! P4.4 - NC
-! P4.7 - NC
-
-! -------------+------+------+------+------++---+---+---+---+---------+
-! SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current | @ 8MHz
-! -------------+------+------+------+------++---+---+---+---+---------+
-! LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 160uA | default mode
-! LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | 115uA |
-! LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 0.9uA | 32768Hz XTAL is running
-! LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 0.6uA | 32768Hz XTAL is running
-! LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 0.5uA |
-! -------------+------+------+------+------++---+---+---+---+---------+
-
-! ============================================
-! FORTH I/O :
-! ============================================
-!TERMINAL
-BUS_TERM=3! \ P2.0 = TX, P2.1 = RX
-
-TERM_IN=\$201!
-TERM_REN=\$207!
-TERM_SEL=\$20D!
-
-TERM_VEC=\$FFF0! \ UCA0
-WAKE_UP=1! \ RX int
-
-TERM_CTLW0=\$5C0! \ eUSCI_A control word 0
-TERM_CTLW1=\$5C2! \ eUSCI_A control word 1
-TERM_BRW=\$5C6!
-TERM_BR0=\$5C6! \ eUSCI_A baud rate 0
-TERM_BR1=\$5C7! \ eUSCI_A baud rate 1
-TERM_MCTLW=\$5C8! \ eUSCI_A modulation control
-TERM_STAT=\$5CA! \ eUSCI_A status
-TERM_RXBUF=\$5CC! \ eUSCI_A receive buffer
-TERM_TXBUF=\$5CE! \ eUSCI_A transmit buffer
-TERM_ABCTL=\$5D0! \ eUSCI_A LIN control
-TERM_IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control
-TERM_IRRCTL=\$5D3! \ eUSCI_A IrDA receive control
-TERM_IE=\$5DA! \ eUSCI_A interrupt enable
-TERM_IFG=\$5DC! \ eUSCI_A interrupt flags
-TERM_IV=\$5DE! \ eUSCI_A interrupt vector word
-
-RTS=2! ; P4.1
-CTS=1! ; P4.0
-HANDSHAKIN=\$221!
-HANDSHAKOUT=\$223!
-
-CD_SD=4! P4.2 as Card Detect
-SD_CDIN=\$221!
-
-CS_SD=8! P4.3 as Card Select
-SD_CSOUT=\$223!
-SD_CSDIR=\$225!
-
-BUS_SD=\$70! ; pins P2.4 as UCB0CLK, P2.5 as UCB0SIMO & P2.6 as UCB0SOMI
-SD_SEL=\$20D! ; to configure UCB0
-SD_REN=\$207! ; to configure pullup resistors
-
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-! init state : output low
+; ======================================================================
+; MSP_EXP430FR5969 board
+; ======================================================================
+
+; J3: JTAG
+; --------
+; P1 - TDO - PJ.0
+; P2 - V_debug
+; P3 - TDI - PJ.1
+; P4 - V_ext
+; P5 - TMS - PJ.2
+; P6 - NC
+; P7 - TCK - PJ.3
+; P8 - TEST - TEST
+; P9 - GND
+; P10- CTS - P4.0
+; P11- RST - RESET
+; P12- TX0 - P2.0
+; P13- RTS - P4.1
+; P14- RX0 - P2.1
+
+; Launchpad Header Left J4
+; ------------------------
+; P1 - VCC
+; P2 - P4.2
+; P3 - P2.6 UCA1 RX/SOMI
+; P4 - P2.5 UCA1 TX/SIMO
+; P5 - P4.3
+; P6 - P2.4 UCA1 CLK
+; P7 - P2.2 TB0.2 UCB0CLK
+; P8 - P3.4
+; P9 - P3.5
+; P10- P3.6
+
+; Launchpad Header Right J5
+; -------------------------
+; P11- P1.3
+; P12- P1.4
+; P13- P1.5
+; P14- P1.6 UCB0 SIMO/SDA
+; P15- P1.7 UCB0 SOMI/SCL
+; P16- RST
+; P17- NC
+; P18- P3.0
+; P19- P1.2
+; P20- GND
+
+; J13 eZ-FET <=> target
+; ---------------------------
+; P1 P2 NC NC
+; P3 <-> P4 TEST <-> TEST
+; P5 <-> P6 RST <-> RST
+; P7 P8 TX0 P2.0 (no strap)
+; P9 P10 RX0 P2.1 (no strap)
+; P11 P12 CTS P4.0 (no strap)
+; P13 P14 RTS P4.1 (no strap)
+; P15<->P16 V+ <-> VCC
+; P17 P18 5V (no strap)
+; P19---P20 GND-----VSS
+
+; J21 : external target
+; ---------------------
+; P1 - RX0 - P2.1
+; P2 - VCC
+; P3 - TEST - TEST
+; P4 - RST - RST
+; P5 - GND
+; P6 - TX0 - P2.0
+
+
+; -----------------------------------------------
+; MSP430FR5969 LAUNCHPAD <--> OUTPUT WORLD
+; -----------------------------------------------
+
+; J13 jumpers : device <-> eZ-FET
+; -------------------------------
+; P2 P1 NC NC
+; P4<->P3 TEST <-> TEST
+; P6<->P5 RST <-> RST
+; P8 P7 P2.0 TX0 (no jumper)
+; P10 P9 P2.1 RX0 (no jumper)
+; P12 P11 P4.0 CTS (no jumper)
+; P14 P13 P4.1 RTS (no jumper)
+; P16<->P15 VCC <-> V+
+; P18 P17 5V 5V (no jumper)
+; P20---P19 VSS-----GND
+
+; P4.6 - J6 - LED1 red
+; P1.0 - LED2 green
+;
+; P4.5 - Switch S1 <--- LCD contrast + (finger :-)
+; P1.1 - Switch S2 <--- LCD contrast - (finger ;-)
+;
+; GND - J1.2 <-------+---0V0----------> 1 LCD_Vss
+; VCC - J1.3 >------ | --3V6-----+----> 2 LCD_Vdd
+; | |
+; ___ 470n ---
+; ^ ---
+; / \ 1n4148 |
+; --- |
+; 100n | 2k2 |
+; P2.2 - UCB0 CLK TB0.2 J4.7 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; P3.4 - J4.8 -------------------------> 4 LCD_RS
+; P3.5 - J4.9 -------------------------> 5 LCD_R/W
+; P3.6 - J4.10 -------------------------> 6 LCD_EN
+; PJ.0 - J3.1 <------------------------> 11 LCD_DB4
+; PJ.1 - J3.3 <------------------------> 12 LCD_DB5
+; PJ.2 - J3.5 <------------------------> 13 LCD_DB6
+; PJ.3 - J3.7 <------------------------> 14 LCD_DB7
+;
+; +--4k7-< DeepRST <-- GND
+; |
+; P2.0 - UCA0 TXD J13.8 <-+-> RX UARTtoUSB bridge
+; P2.1 - UCA0 RXD J13.10 <---- TX UARTtoUSB bridge
+; P4.1 - RTS J13.14 ----> CTS UARTtoUSB bridge (optional hardware control flow)
+; VCC - J13.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ; 3.3V !)
+; GND - J13.20 <---> GND (optional supply from UARTtoUSB bridge)
+;
+; VCC - J11.1 ----> VCC SD_CardAdapter
+; GND - J12.3 <---> GND SD_CardAdapter
+; P2.4 - UCA1 CLK J4.6 ----> CLK SD_CardAdapter (SCK)
+; P4.3 - J4.5 ----> CS SD_CardAdapter (Card Select)
+; P2.5 - UCA1 TXD/SIMO J4.4 ----> SDI SD_CardAdapter (MOSI)
+; P2.6 - UCA1 RXD/SOMI J4.3 <---- SDO SD_CardAdapter (MISO)
+; P4.2 - J4.2 <---- CD SD_CardAdapter (Card Detect)
+;
+; P4.0 - J3.10 <---- OUT IR_Receiver (1 TSOP32236) ----┌───┐
+; VCC - J3.2 ----> VCC IR_Receiver (2 TSOP32236) ----│ ○ │
+; GND - J3.9 <---> GND IR_Receiver (3 TSOP32236) ----└───┘
+;
+; P1.2 - J5.19 <---> SDA I2C SOFTWARE MASTER
+; P1.3 - J5.11 <---> SCL I2C SOFTWARE MASTER
+; P1.4 - TB0.1 J5.12 <---> free
+; P1.5 - UCA0 CLK TB0.2 J5.13 <---> free
+; P1.7 - UCB0 SCL/SOMI J5.14 ----> SCL I2C MASTER/SLAVE
+; P1.6 - UCB0 SDA/SIMO J5.15 <---> SDA I2C MASTER/SLAVE
+; P3.0 - J5.7 <---- free
+;
+; PJ.4 - LFXI 32768Hz quartz
+; PJ.5 - LFXO 32768Hz quartz
+; PJ.6 - HFXI
+; PJ.7 - HFXO
+;
+; P2.3 - NC
+; P2.7 - NC
+; P3.1 - NC
+; P3.2 - NC
+; P3.3 - NC
+; P3.7 - NC
+; P4.4 - NC
+; P4.7 - NC
+
+; -------------+------+------+------+------++---+---+---+---+---------+
+; SR(low byte) | SCG1 | SCG0 |OSCOFF|CPUOFF||GIE| N | Z | C | current | @ 8MHz
+; -------------+------+------+------+------++---+---+---+---+---------+
+; LPM0 = $18 | 0 | 0 | 0 | 1 || 1 | x | x | x | 160uA | default mode
+; LPM1 = $58 | 0 | 1 | 0 | 1 || 1 | x | x | x | 115uA |
+; LPM2 = $98 | 1 | 0 | 0 | 1 || 1 | x | x | x | 0.9uA | 32768Hz XTAL is running
+; LPM3 = $D8 | 1 | 1 | 0 | 1 || 1 | x | x | x | 0.6uA | 32768Hz XTAL is running
+; LPM4 = $F8 | 1 | 1 | 1 | 1 || 1 | x | x | x | 0.5uA |
+; -------------+------+------+------+------++---+---+---+---+---------+
+
+; FFCC-FFFF 25 vectors + reset
+; 0FFCCh - AES
+; 0FFCEh - RTC_B
+; 0FFD0h - I/O Port 4
+; 0FFD2h - I/O Port 3
+; 0FFD4h - TB2_1
+; 0FFD6h - TB2_0
+; 0FFD8h - I/O Port P2
+; 0FFDAh - TB1_1
+; 0FFDCh - TB1_0
+; 0FFDEh - I/O Port P1
+; 0FFE0h - TA1_1
+; 0FFE2h - TA1_0
+; 0FFE4h - DMA
+; 0FFE6h - eUSCI_A1
+; 0FFE8h - TA0_1
+; 0FFEAh - TA0_0
+; 0FFECh - ADC12_B
+; 0FFEEh - eUSCI_B0
+; 0FFF0h - eUSCI_A0
+; 0FFF2h - Watchdog
+; 0FFF4h - TB0_1
+; 0FFF6h - TB0_0
+; 0FFF8h - COMP_D
+; 0FFFAh - userNMI
+; 0FFFCh - sysNMI
+; 0FFFEh - reset
+
+; ----------------------------------------------------------------------
+; MSP430FR5969 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .set 0100h ; Special function
+;PMM_SFR .set 0120h ; PMM
+;FRAM_SFR .set 0140h ; FRAM control
+;CRC16_SFR .set 0150h
+;WDT_A_SFR .set 015Ch ; Watchdog
+;CS_SFR .set 0160h ; Clock System
+;SYS_SFR .set 0180h ; SYS
+;REF_SFR .set 01B0h ; REF
+;PA_SFR .set 0200h ; PORT1/2
+;PB_SFR .set 0220h ; PORT3/4
+;PJ_SFR .set 0320h ; PORTJ
+;TA0_SFR .set 0340h
+;TA1_SFR .set 0380h
+;TB0_SFR .set 03C0h
+;TA2_SFR .set 0400h
+;CTIO0_SFR .set 0430h ; Capacitive Touch IO
+;TA3_SFR .set 0440h
+;CTIO1_SFR .set 0470h ; Capacitive Touch IO
+;RTC_B_SFR .set 04A0h
+;MPY_SFR .set 04C0h
+;DMA_CTRL_SFR .set 0500h
+;DMA_CHN0_SFR .set 0510h
+;DMA_CHN1_SFR .set 0520h
+;DMA_CHN2_SFR .set 0530h
+;MPU_SFR .set 05A0h ; memory protect unit
+;eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
+;eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
+;eUSCI_B0_SFR .set 0640h ; eUSCI_B0
+;ADC12_B_SFR .set 0800h
+;COMP_E_SFR .set 08C0h
+;AES_SFR .set 09C0h
+
+; ============================================
+; FAST FORTH configuration :
+; ============================================
+;TERMINAL
+BUS_TERM=3; \ P2.0 = TX, P2.1 = RX
+
+TERM_IN=\$201;
+TERM_REN=\$207;
+TERM_SEL=\$20D;
+
+TERM_VEC=\$FFF0; \ UCA0
+UCSWRST=1; eUSCI Software Reset
+WAKE_UP=1; \ RX int
+RX=1; RX flag IFG
+TX=2; Tx flag IFG
+
+TERM_CTLW0=\$5C0; \ eUSCI_A control word 0
+TERM_CTLW1=\$5C2; \ eUSCI_A control word 1
+TERM_BRW=\$5C6;
+TERM_BR0=\$5C6; \ eUSCI_A baud rate 0
+TERM_BR1=\$5C7; \ eUSCI_A baud rate 1
+TERM_MCTLW=\$5C8; \ eUSCI_A modulation control
+TERM_STAT=\$5CA; \ eUSCI_A status
+TERM_RXBUF=\$5CC; \ eUSCI_A receive buffer
+TERM_TXBUF=\$5CE; \ eUSCI_A transmit buffer
+TERM_IE=\$5DA; \ eUSCI_A interrupt enable
+TERM_IFG=\$5DC; \ eUSCI_A interrupt flags
+TERM_IV=\$5DE; \ eUSCI_A interrupt vector word
+
+RTS=2; ; P4.1
+CTS=1; ; P4.0
+HANDSHAKIN=\$221;
+HANDSHAKOUT=\$223;
+
+CD_SD=4; P4.2 as Card Detect
+SD_CDIN=\$221;
+
+CS_SD=8; P4.3 as Card Select
+SD_CSOUT=\$223;
+SD_CSDIR=\$225;
+
+BUS_SD=\$70; ; pins P2.4 as UCB0CLK, P2.5 as UCB0SIMO & P2.6 as UCB0SOMI
+SD_SEL=\$20D; ; to configure UCB0
+SD_REN=\$207; ; to configure pullup resistors
+
+
+LFXT_OUT=\$322; PJ
+LFXT_DIR=\$324; PJ
+LFXT_SEL=\$32A; PJSEL0
+LFXIN=\$10; PJ.4
+LFXOUT=\$20; PJ.5
+
+; FAST FORTH I/O :
LED1_OUT=\$223
LED1_DIR=\$225
-LED1=\$40! P4.6
-
-! init state : output low
+LED1=\$40; P4.6
LED2_OUT=\$202
LED2_DIR=\$204
-LED2=\$01! P1.0
+LED2=\$01; P1.0
-! init state : input with pullup resistor
+; init state : input with pullup resistor
SW1_IN=\$221
-SW1=\$20! P4.5 = S1
-
-WIPE_IN=\$221
-IO_WIPE=\$20! P4.5 = S1 = FORTH Deep_RST pin
-
-! init state : input with pullup resistor
+SW1=\$20; P4.5 = S1
SW2_IN=\$200
-SW2=\$02! P1.1 = S2
+SW2=\$02; P1.1 = S2
+
+; ============================================
+; UARTI2CS APPLICATION
+; ============================================
+;I2C_Soft_Master
+I2CSM_IN=\$200;
+I2CSM_OUT=\$202;
+I2CSM_DIR=\$204;
+I2CSM_REN=\$206;
+SM_SDA=\$04; P1.2
+SM_SCL=\$08; P1.3
+SM_BUS=\$0C
-LCDVo_DIR=\$205! P2
-LCDVo_SEL=\$20B! SEL0
+;500_ms_INT TIMER
+TIM_CTL=\$3C0; TB0
+TIM_CCTL2=\$3C6;
+TIM_CCR0=\$3D2;
+TIM_CCR2=\$3D6;
+T_OUT2=4; P2.2 <--- TB0.2
+T_OUT2_DIR=\$205; P2DIR
+T_OUT2_SEL=\$20D; P2SEL1
+INT_IN=\$10; P3.4
+INT_IN_IE=\$23A; P3IE
+INT_IN_IFG=\$23C; P3IFG
+INT_IN_VEC=\$FFD2; P3VEC
+
+;local variables
+UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+TIMER_CONF=\{UARTI2CS\}\+12; <-- TIM_CTL configuration
+COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+; ============================================
+; RC5toLCD APPLICATION
+; ============================================
+LCDVo_DIR=\$205; P2
+LCDVo_SEL=\$20B; SEL0
LCDVo=\$04
-!LCD timer
-LCD_TIM_CTL=\$3C0! TB0CTL
-LCD_TIM_CCTLn=\$3C6! TB0CCTL2
-LCD_TIM_CCR0=\$3D2! TB0CCR0
-LCD_TIM_CCRn=\$3D6! TB0CCR2
-LCD_TIM_EX0=\$3E0! TB0EX0
-
-LCD_CMD_IN=\$220! P3
+;LCD timer
+LCD_TIM_CTL=\$3C0; TB0CTL
+LCD_TIM_CCTLn=\$3C6; TB0CCTL2
+LCD_TIM_CCR0=\$3D2; TB0CCR0
+LCD_TIM_CCRn=\$3D6; TB0CCR2
+LCD_TIM_EX0=\$3E0; TB0EX0
+;LCD command bus
+LCD_CMD_IN=\$220; P3
LCD_CMD_OUT=\$222
LCD_CMD_DIR=\$224
LCD_CMD_REN=\$226
LCD_RW=\$20
LCD_EN=\$40
LCD_CMD=\$70
-
-LCD_DB_IN=\$320! PJ
+;LCD data bus
+LCD_DB_IN=\$320; PJ
LCD_DB_OUT=\$322
LCD_DB_DIR=\$324
LCD_DB_REN=\$326
LCD_DB=\$0F
-
-
-!WATCHDOG timer
-WDT_TIM_CTL=\$340! TA0CTL
-WDT_TIM_CCTL0=\$342! TA0CCTL0
-WDT_TIM_CCR0=\$352! TA0CCR0
-WDT_TIM_EX0=\$360! TA0EX0
-WDT_TIM_0_VEC=\$FFEA! TA0_0_VEC
-
+;WATCHDOG timer
+WDT_TIM_CTL=\$340; TA0CTL
+WDT_TIM_CCTL0=\$342; TA0CCTL0
+WDT_TIM_CCR0=\$352; TA0CCR0
+WDT_TIM_EX0=\$360; TA0EX0
+WDT_TIM_0_VEC=\$FFEA; TA0_0_VEC
+;IR_RC5
IR_IN=\$221
IR_OUT=\$223
IR_DIR=\$225
IR_IES=\$239
IR_IE=\$23B
IR_IFG=\$23D
-IR_VEC=\$FFD0! P4 int
-RC5=\$01! P4.0
-!IR_RC5 timer
-RC5_TIM_CTL=\$380! TA1CTL
-RC5_TIM_R=\$390! TA1R
-RC5_TIM_EX0=\$3A0! TA1EX0
-
-
-I2CSM_IN=\$200
-I2CSM_OUT=\$202
-I2CSM_DIR=\$204
-I2CSM_REN=\$206
-SM_SDA=\$04! P1.2
-SM_SCL=\$08! P1.3
-SM_BUS=\$0C
+IR_VEC=\$FFD0; P4 int
+RC5=\$01; P4.0
+;IR_RC5 timer
+RC5_TIM_CTL=\$380; TA1CTL
+RC5_TIM_R=\$390; TA1R
+RC5_TIM_EX0=\$3A0; TA1EX0
+; --------------------------------------------
I2CSMM_IN=\$200
I2CSMM_OUT=\$202
I2CSMM_DIR=\$204
I2CSMM_REN=\$206
-SMM_SDA=\$04! P1.2
-SMM_SCL=\$08! P1.3
+SMM_SDA=\$04; P1.2
+SMM_SCL=\$08; P1.3
SMM_BUS=\$0C
I2CMM_IN=\$200
I2CMM_OUT=\$202
I2CMM_DIR=\$204
I2CMM_REN=\$206
-I2CMM_SEL=\$20C! SEL1
-I2CMM_VEC=\$FFEE! eUSCIB0_INT
-MM_SDA=\$40! P1.6
-MM_SCL=\$80! P1.7
+I2CMM_SEL=\$20C; SEL1
+I2CMM_VEC=\$FFEE; eUSCIB0_INT
+MM_SDA=\$40; P1.6
+MM_SCL=\$80; P1.7
MM_BUS=\$C0
I2CM_IN=\$200
I2CM_OUT=\$202
I2CM_DIR=\$204
I2CM_REN=\$206
-I2CM_SEL=\$20C! SEL1
-I2CM_VEC=\$FFEE! eUSCIB0_INT
-M_SDA=\$40! P1.6
-M_SCL=\$80! P1.7
+I2CM_SEL=\$20C; SEL1
+I2CM_VEC=\$FFEE; eUSCIB0_INT
+M_SDA=\$40; P1.6
+M_SCL=\$80; P1.7
M_BUS=\$C0
I2CS_IN=\$200
I2CS_OUT=\$202
I2CS_DIR=\$204
I2CS_REN=\$206
-I2CS_SEL=\$20C! SEL1
-I2CS_VEC=\$FFEE! eUSCIB0_INT
-S_SDA=\$40! P1.6
-S_SCL=\$80! P1.7
+I2CS_SEL=\$20C; SEL1
+I2CS_VEC=\$FFEE; eUSCIB0_INT
+S_SDA=\$40; P1.6
+S_SCL=\$80; P1.7
S_BUS=\$C0
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
-
-I2CM_CTLW0=\$640! USCI_B0 Control Word Register 0
-I2CM_CTLW1=\$642! USCI_B0 Control Word Register 1
-I2CM_BRW=\$646! USCI_B0 Baud Word Rate 0
-I2CM_STATW=\$648! USCI_B0 status word
-I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold
-I2CM_RXBUF=\$64C! USCI_B0 Receive Buffer 8
-I2CM_TXBUF=\$64E! USCI_B0 Transmit Buffer 8
-I2CM_I2COA0=\$654! USCI_B0 I2C Own Address 0
-I2CM_ADDRX=\$65C! USCI_B0 Received Address Register
-I2CM_I2CSA=\$660! USCI_B0 I2C Slave Address
-I2CM_IE=\$66A! USCI_B0 Interrupt Enable
-I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register
-
-I2CS_CTLW0=\$640! USCI_B0 Control Word Register 0
-I2CS_CTLW1=\$642! USCI_B0 Control Word Register 1
-I2CS_BRW=\$646! USCI_B0 Baud Word Rate 0
-I2CS_STATW=\$648! USCI_B0 status word
-I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold
-I2CS_RXBUF=\$64C! USCI_B0 Receive Buffer 8
-I2CS_TXBUF=\$64E! USCI_B0 Transmit Buffer 8
-I2CS_I2COA0=\$654! USCI_B0 I2C Own Address 0
-I2CS_ADDRX=\$65C! USCI_B0 Received Address Register
-I2CS_I2CSA=\$660! USCI_B0 I2C Slave Address
-I2CS_IE=\$66A! USCI_B0 Interrupt Enable
-I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register
+I2CM_CTLW0=\$640; USCI_B0 Control Word Register 0
+I2CM_CTLW1=\$642; USCI_B0 Control Word Register 1
+I2CM_BRW=\$646; USCI_B0 Baud Word Rate 0
+I2CM_STATW=\$648; USCI_B0 status word
+I2CM_TBCNT=\$64A; USCI_B0 byte counter threshold
+I2CM_RXBUF=\$64C; USCI_B0 Receive Buffer 8
+I2CM_TXBUF=\$64E; USCI_B0 Transmit Buffer 8
+I2CM_I2COA0=\$654; USCI_B0 I2C Own Address 0
+I2CM_ADDRX=\$65C; USCI_B0 Received Address Register
+I2CM_I2CSA=\$660; USCI_B0 I2C Slave Address
+I2CM_IE=\$66A; USCI_B0 Interrupt Enable
+I2CM_IFG=\$66C; USCI_B0 Interrupt Flags Register
+
+I2CS_CTLW0=\$640; USCI_B0 Control Word Register 0
+I2CS_CTLW1=\$642; USCI_B0 Control Word Register 1
+I2CS_BRW=\$646; USCI_B0 Baud Word Rate 0
+I2CS_STATW=\$648; USCI_B0 status word
+I2CS_TBCNT=\$64A; USCI_B0 byte counter threshold
+I2CS_RXBUF=\$64C; USCI_B0 Receive Buffer 8
+I2CS_TXBUF=\$64E; USCI_B0 Transmit Buffer 8
+I2CS_I2COA0=\$654; USCI_B0 I2C Own Address 0
+I2CS_ADDRX=\$65C; USCI_B0 Received Address Register
+I2CS_I2CSA=\$660; USCI_B0 I2C Slave Address
+I2CS_IE=\$66A; USCI_B0 Interrupt Enable
+I2CS_IFG=\$66C; USCI_B0 Interrupt Flags Register
-! -*- coding: utf-8 -*-
-! virtual MSP_EXP430FR5972.pat from MSP_EXP430FR6989.pat
-!
-\.f=\.4th for MSP_EXP430FR5972! to change file type
-!
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! replace ! by semicolon
+; virtual MSP_EXP430FR5972.pat from MSP_EXP430FR6989.pat
+;
+\.f=\.4th for MSP_EXP430FR5972; to change file type
+;
+;========================
+; remove comments
+;========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! MSP430FR6989 Config
-! ======================================================================
+; ======================================================================
+; MSP430FR6989 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR5972.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR5xxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-! ======================================================================
-! MSP_EXP430FR5972 board
-! ======================================================================
-
-! ---------------------------------------------------
-! MSP - MSP-EXP430FR5972 virtual LAUNCHPAD <--> OUTPUT WORLD
-! ---------------------------------------------------
-! P1.0 - LED1 red
-! P9.7 - LED2 green
-!
-! P1.1 - Switch S1 <--- LCD contrast + (finger :-)
-! P1.2 - Switch S2 <--- LCD contrast - (finger ;-)
-!
-! GND <-------+---0V0----------> 1 LCD_Vss
-! VCC >------ | --3V3-----+----> 2 LCD_Vdd
-! | |
-! |___ 470n ---
-! ^ | ---
-! / \ BAT54 |
-! --- |
-! 100n | 2k2 |
-! P3.6 - UCA1 CLK TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! P7.0/ <------------------------> 11 LCD_DB4
-! P7.1/ <------------------------> 12 LCD_DB5
-! P7.2/ <------------------------> 13 LCD_DB5
-! P7.3/ <------------------------> 14 LCD_DB7
-! P9.4/A12/C12 -------------------------> 4 LCD_RS
-! P9.5/A13/C13 -------------------------> 5 LCD_R/W
-! P9.6/A14/C14 -------------------------> 6 LCD_EN
-!
-! +--4k7-< DeepRST <-- GND
-! |
-! P3.4 - UCA1 TXD <-+-> RX UARTtoUSB bridge
-! P3.5 - UCA1 RXD <---- TX UARTtoUSB bridge
-! P3.0 - RTS ----> CTS UARTtoUSB bridge (optional hardware control flow)
-! VCC - <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
-! GND - <---> GND (optional supply from UARTtoUSB bridge)
-!
-! VCC - ----> VCC SD_CardAdapter
-! GND - <---> GND SD_CardAdapter
-! P2.2 - UCA0 CLK ----> CLK SD_CardAdapter (SCK)
-! P2.6 - ----> CS SD_CardAdapter (Card Select)
-! P2.0 - UCA0 TXD/SIMO ----> SDI SD_CardAdapter (MOSI)
-! P2.1 - UCA0 RXD/SOMI <---- SDO SD_CardAdapter (MISO)
-! P2.7 - <---- CD SD_CardAdapter (Card Detect)
-!
-! P4.0 - <---- OUT IR_Receiver (1 TSOP32236)
-! VCC - ----> VCC IR_Receiver (2 TSOP32236)
-! GND - <---> GND IR_Receiver (3 TSOP32236)
-!
-! P1.3 - <---> SDA software I2C Master
-! P1.5 - ----> SCL software I2C Master
-!
-! P1.4 -UCB0 CLK TA1.0 <---> free
-!
-! P1.6 -UCB0 SDA/SIMO <---> SDA hardware I2C Master or Slave
-! P1.7 -UCB0 SCL/SOMI ----> SCL hardware I2C Master or Slave
-!
-! P3.0 -UCB1 CLK ----> free (if UARTtoUSB with software control flow)
-! P3.1 -UCB1 SDA/SIMO <---> free
-! P3.2 -UCB1 SCL/SOMI ----> free
-! P3.3 - TA1.1 <---> free
-!
-! PJ.4 - LFXI 32768Hz quartz
-! PJ.5 - LFXO 32768Hz quartz
-! PJ.6 - HFXI
-! PJ.7 - HFXO
-
-
-! ============================================
-! FORTH I/O :
-! ============================================
-BUS_TERM=\$30! \ P3.5 = RX, P3.4 = TX
-
-TERM_IN=\$220!
-TERM_REN=\$226!
-TERM_SEL=\$22C! \ SEL0
-
-TERM_VEC=\$FFE4! \ UCA1
-WAKE_UP=1! \ RX int
-
-TERM_CTLW0=\$5E0! \ eUSCI_A control word 0
-TERM_CTLW1=\$5E2! \ eUSCI_A control word 1
-TERM_BRW=\$5E6!
-TERM_BR0=\$5E6! \ eUSCI_A baud rate 0
-TERM_BR1=\$5E7! \ eUSCI_A baud rate 1
-TERM_MCTLW=\$5E8! \ eUSCI_A modulation control
-TERM_STAT=\$5EA! \ eUSCI_A status
-TERM_RXBUF=\$5EC! \ eUSCI_A receive buffer
-TERM_TXBUF=\$5EE! \ eUSCI_A transmit buffer
-TERM_ABCTL=\$5F0! \ eUSCI_A LIN control
-TERM_IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control
-TERM_IRRCTL=\$5F3! \ eUSCI_A IrDA receive control
-TERM_IE=\$5FA! \ eUSCI_A interrupt enable
-TERM_IFG=\$5FC! \ eUSCI_A interrupt flags
-TERM_IV=\$5FE! \ eUSCI_A interrupt vector word
-
-RTS=1! ; P3.0
-CTS=2! ; P3.1
-HANDSHAKIN=\$220!
-HANDSHAKOUT=\$222!
-
-
-CD_SD=\$80! ; P2.7 as Card Detect
-SD_CDIN=\$201!
-
-CS_SD=\$40! ; P2.6 as Card Select
-SD_CSOUT=\$203!
-SD_CSDIR=\$205!
-
-BUS_SD=\$07! ; pins P2.2 as UCB0CLK, P2.0 as UCB0SIMO & P2.1 as UCB0SOMI
-SD_SEL=\$20C! ; to configure UCB0
-SD_REN=\$206! ; to configure pullup resistors
-
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-LED1_OUT=\$202!
-LED1=1! P1.0
-
-LED2_OUT=\$282!
-LED2=\$80! P9.7
-
-SW1_IN=\$200!
-SW1=2! P1.1
-
-WIPE_IN=\$200! ; pin as FORTH Deep_RST
-IO_WIPE=2! ; P1.1 = S1
-
-SW2_IN=\$200!
-SW2=4! P1.2
-
-LCDVo_DIR=\$224!
-LCDVo_SEL=\$22C! SEL1
-LCDVo=\$40! P3.6
-
-!LCD timer
-LCD_TIM_CTL=\$3C0! TB0CTL
-LCD_TIM_CCTLn=\$3C6! TB0CCTL2
-LCD_TIM_CCR0=\$3D2! TB0CCR0
-LCD_TIM_CCRn=\$3D6! TB0CCR2
-LCD_TIM_EX0=\$3E0! TB0EX0
-
-LCD_CMD_IN=\$221!
-LCD_CMD_OUT=\$223!
-LCD_CMD_DIR=\$225!
-LCD_CMD_REN=\$227!
-LCD_RS=2! P4.1
-LCD_RW=4! P4.2
-LCD_EN=8! P4.3
-LCD_CMD=\$0E!
-
-LCD_DB_IN=\$280!
-LCD_DB_OUT=\$282!
-LCD_DB_DIR=\$284!
-LCD_DB_REN=\$286!
-LCD_DB=\$0F! P9.3-0
-
-
-!WATCHDOG timer
-WDT_TIM_CTL=\$340! TA0CTL
-WDT_TIM_CCTL0=\$342! TA0CCTL0
-WDT_TIM_CCR0=\$352! TA0CCR0
-WDT_TIM_EX0=\$360! TA0EX0
-WDT_TIM_0_Vec=\$FFE8! TA0_0_Vec
-
-IR_IN=\$221!
-IR_OUT=\$223!
-IR_DIR=\$225!
-IR_REN=\$227!
-IR_IES=\$239!
-IR_IE=\$23B!
-IR_IFG=\$23D!
-RC5_=RC5_!
-RC5=1! P4.0
-IR_Vec=\$FFCC! P4 int
-
-I2CSM_IN=\$200!
-I2CSM_OUT=\$202!
-I2CSM_DIR=\$204!
-I2CSM_REN=\$206!
-SM_SDA=8! P1.3
-SM_SCL=\$20! P1.5
-SM_BUS=\$28!
-
-I2CSMM_IN=\$200!
-I2CSMM_OUT=\$202!
-I2CSMM_DIR=\$204!
-I2CSMM_REN=\$206!
-SMM_SDA=8! P1.3
-SMM_SCL=\$20! P1.5
-SMM_BUS=\$28!
-RC5_TIM_CTL=\$380! TA1CTL
-RC5_TIM_R=\$390! TA1R
-RC5_TIM_EX0=\$3A0! TA1EX0
-
-
-I2CMM_IN=\$200!
-I2CMM_OUT=\$202!
-I2CMM_DIR=\$204!
-I2CMM_REN=\$206!
-I2CMM_SEL=\$20A! SEL0
-I2CMM_Vec=\$FFEC! UCBO_Vec
-MM_SDA=\$40! P1.6
-MM_SCL=\$80! P1.7
-MM_BUS=\$C0!
-
-I2CM_IN=\$200!
-I2CM_OUT=\$202!
-I2CM_DIR=\$204!
-I2CM_REN=\$206!
-I2CM_SEL=\$20A! SEL0
-I2CM_Vec=\$FFEC! UCBO_Vec
-M_SDA=\$40! P1.6
-M_SCL=\$80! P1.7
-M_BUS=\$C0!
-
-I2CS_IN=\$200!
-I2CS_OUT=\$202!
-I2CS_DIR=\$204!
-I2CS_REN=\$206!
-I2CS_SEL=\$20A! SEL0
-I2CS_Vec=\$FFEC! UCBO_Vec
-S_SDA=\$40! P1.6
-S_SCL=\$80! P1.7
-S_BUS=\$C0!
-
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
-
-I2CM_CTLW0=\$640! USCI_B0 Control Word Register 0
-I2CM_CTLW1=\$642! USCI_B0 Control Word Register 1
-I2CM_BRW=\$646! USCI_B0 Baud Word Rate 0
-I2CM_STATW=\$648! USCI_B0 status word
-I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold
-I2CM_RXBUF=\$64C! USCI_B0 Receive Buffer 8
-I2CM_TXBUF=\$64E! USCI_B0 Transmit Buffer 8
-I2CM_I2COA0=\$654! USCI_B0 I2C Own Address 0
-I2CM_ADDRX=\$65C! USCI_B0 Received Address Register
-I2CM_I2CSA=\$660! USCI_B0 I2C Slave Address
-I2CM_IE=\$66A! USCI_B0 Interrupt Enable
-I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register
-
-I2CS_CTLW0=\$640! USCI_B0 Control Word Register 0
-I2CS_CTLW1=\$642! USCI_B0 Control Word Register 1
-I2CS_BRW=\$646! USCI_B0 Baud Word Rate 0
-I2CS_STATW=\$648! USCI_B0 status word
-I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold
-I2CS_RXBUF=\$64C! USCI_B0 Receive Buffer 8
-I2CS_TXBUF=\$64E! USCI_B0 Transmit Buffer 8
-I2CS_I2COA0=\$654! USCI_B0 I2C Own Address 0
-I2CS_ADDRX=\$65C! USCI_B0 Received Address Register
-I2CS_I2CSA=\$660! USCI_B0 I2C Slave Address
-I2CS_IE=\$66A! USCI_B0 Interrupt Enable
-I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register
+; ======================================================================
+; MSP_EXP430FR5972 board
+; ======================================================================
+
+; ---------------------------------------------------
+; MSP - MSP-EXP430FR5972 virtual LAUNCHPAD <--> OUTPUT WORLD
+; ---------------------------------------------------
+; P1.0 - LED1 red
+; P9.7 - LED2 green
+;
+; P1.1 - Switch S1 <--- LCD contrast + (finger :-)
+; P1.2 - Switch S2 <--- LCD contrast - (finger ;-)
+;
+; GND <-------+---0V0----------> 1 LCD_Vss
+; VCC >------ | --3V3-----+----> 2 LCD_Vdd
+; | |
+; |___ 470n ---
+; ^ | ---
+; / \ BAT54 |
+; --- |
+; 100n | 2k2 |
+; P3.6 - UCA1 CLK TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; P7.0/ <------------------------> 11 LCD_DB4
+; P7.1/ <------------------------> 12 LCD_DB5
+; P7.2/ <------------------------> 13 LCD_DB5
+; P7.3/ <------------------------> 14 LCD_DB7
+; P9.4/A12/C12 -------------------------> 4 LCD_RS
+; P9.5/A13/C13 -------------------------> 5 LCD_R/W
+; P9.6/A14/C14 -------------------------> 6 LCD_EN
+;
+; +--4k7-< DeepRST <-- GND
+; |
+; P3.4 - UCA1 TXD <-+-> RX UARTtoUSB bridge
+; P3.5 - UCA1 RXD <---- TX UARTtoUSB bridge
+; P3.0 - RTS ----> CTS UARTtoUSB bridge (optional hardware control flow)
+; VCC - <---- VCC (optional supply from UARTtoUSB bridge - WARNING ; 3.3V ;)
+; GND - <---> GND (optional supply from UARTtoUSB bridge)
+;
+; VCC - ----> VCC SD_CardAdapter
+; GND - <---> GND SD_CardAdapter
+; P2.2 - UCA0 CLK ----> CLK SD_CardAdapter (SCK)
+; P2.6 - ----> CS SD_CardAdapter (Card Select)
+; P2.0 - UCA0 TXD/SIMO ----> SDI SD_CardAdapter (MOSI)
+; P2.1 - UCA0 RXD/SOMI <---- SDO SD_CardAdapter (MISO)
+; P2.7 - <---- CD SD_CardAdapter (Card Detect)
+;
+; P4.0 - <---- OUT IR_Receiver (1 TSOP32236)
+; VCC - ----> VCC IR_Receiver (2 TSOP32236)
+; GND - <---> GND IR_Receiver (3 TSOP32236)
+;
+; P1.3 - <---> SDA software I2C Master
+; P1.5 - ----> SCL software I2C Master
+;
+; P1.4 -UCB0 CLK TA1.0 <---> free
+;
+; P1.6 -UCB0 SDA/SIMO <---> SDA hardware I2C Master or Slave
+; P1.7 -UCB0 SCL/SOMI ----> SCL hardware I2C Master or Slave
+;
+; P3.0 -UCB1 CLK ----> free (if UARTtoUSB with software control flow)
+; P3.1 -UCB1 SDA/SIMO <---> free
+; P3.2 -UCB1 SCL/SOMI ----> free
+; P3.3 - TA1.1 <---> free
+;
+; PJ.4 - LFXI 32768Hz quartz
+; PJ.5 - LFXO 32768Hz quartz
+; PJ.6 - HFXI
+; PJ.7 - HFXO
+
+
+; ============================================
+; FORTH I/O :
+; ============================================
+BUS_TERM=\$30; \ P3.5 = RX, P3.4 = TX
+
+TERM_IN=\$220;
+TERM_REN=\$226;
+TERM_SEL=\$22C; \ SEL0
+
+TERM_VEC=\$FFE4; \ UCA1
+WAKE_UP=1; \ RX int
+RX=1; RX flag IFG
+TX=2; Tx flag IFG
+
+TERM_CTLW0=\$5E0; \ eUSCI_A control word 0
+TERM_CTLW1=\$5E2; \ eUSCI_A control word 1
+TERM_BRW=\$5E6;
+TERM_BR0=\$5E6; \ eUSCI_A baud rate 0
+TERM_BR1=\$5E7; \ eUSCI_A baud rate 1
+TERM_MCTLW=\$5E8; \ eUSCI_A modulation control
+TERM_STAT=\$5EA; \ eUSCI_A status
+TERM_RXBUF=\$5EC; \ eUSCI_A receive buffer
+TERM_TXBUF=\$5EE; \ eUSCI_A transmit buffer
+TERM_ABCTL=\$5F0; \ eUSCI_A LIN control
+TERM_IRTCTL=\$5F2; \ eUSCI_A IrDA transmit control
+TERM_IRRCTL=\$5F3; \ eUSCI_A IrDA receive control
+TERM_IE=\$5FA; \ eUSCI_A interrupt enable
+TERM_IFG=\$5FC; \ eUSCI_A interrupt flags
+TERM_IV=\$5FE; \ eUSCI_A interrupt vector word
+
+RTS=1; ; P3.0
+CTS=2; ; P3.1
+HANDSHAKIN=\$220;
+HANDSHAKOUT=\$222;
+
+
+CD_SD=\$80; ; P2.7 as Card Detect
+SD_CDIN=\$201;
+
+CS_SD=\$40; ; P2.6 as Card Select
+SD_CSOUT=\$203;
+SD_CSDIR=\$205;
+
+BUS_SD=\$07; ; pins P2.2 as UCB0CLK, P2.0 as UCB0SIMO & P2.1 as UCB0SOMI
+SD_SEL=\$20C; ; to configure UCB0
+SD_REN=\$206; ; to configure pullup resistors
+
+
+; ============================================
+; APPLICATION I/O :
+; ============================================
+LED1_OUT=\$202;
+LED1=1; P1.0
+
+LED2_OUT=\$282;
+LED2=\$80; P9.7
+
+SW1_IN=\$200;
+SW1=2; P1.1
+
+WIPE_IN=\$200; ; pin as FORTH Deep_RST
+IO_WIPE=2; ; P1.1 = S1
+
+SW2_IN=\$200;
+SW2=4; P1.2
+
+LCDVo_DIR=\$224;
+LCDVo_SEL=\$22C; SEL1
+LCDVo=\$40; P3.6
+
+;LCD timer
+LCD_TIM_CTL=\$3C0; TB0CTL
+LCD_TIM_CCTLn=\$3C6; TB0CCTL2
+LCD_TIM_CCR0=\$3D2; TB0CCR0
+LCD_TIM_CCRn=\$3D6; TB0CCR2
+LCD_TIM_EX0=\$3E0; TB0EX0
+
+LCD_CMD_IN=\$221;
+LCD_CMD_OUT=\$223;
+LCD_CMD_DIR=\$225;
+LCD_CMD_REN=\$227;
+LCD_RS=2; P4.1
+LCD_RW=4; P4.2
+LCD_EN=8; P4.3
+LCD_CMD=\$0E;
+
+LCD_DB_IN=\$280;
+LCD_DB_OUT=\$282;
+LCD_DB_DIR=\$284;
+LCD_DB_REN=\$286;
+LCD_DB=\$0F; P9.3-0
+
+
+;WATCHDOG timer
+WDT_TIM_CTL=\$340; TA0CTL
+WDT_TIM_CCTL0=\$342; TA0CCTL0
+WDT_TIM_CCR0=\$352; TA0CCR0
+WDT_TIM_EX0=\$360; TA0EX0
+WDT_TIM_0_Vec=\$FFE8; TA0_0_Vec
+
+IR_IN=\$221;
+IR_OUT=\$223;
+IR_DIR=\$225;
+IR_REN=\$227;
+IR_IES=\$239;
+IR_IE=\$23B;
+IR_IFG=\$23D;
+RC5_=RC5_;
+RC5=1; P4.0
+IR_Vec=\$FFCC; P4 int
+
+I2CSM_IN=\$200;
+I2CSM_OUT=\$202;
+I2CSM_DIR=\$204;
+I2CSM_REN=\$206;
+SM_SDA=8; P1.3
+SM_SCL=\$20; P1.5
+SM_BUS=\$28;
+
+I2CSMM_IN=\$200;
+I2CSMM_OUT=\$202;
+I2CSMM_DIR=\$204;
+I2CSMM_REN=\$206;
+SMM_SDA=8; P1.3
+SMM_SCL=\$20; P1.5
+SMM_BUS=\$28;
+RC5_TIM_CTL=\$380; TA1CTL
+RC5_TIM_R=\$390; TA1R
+RC5_TIM_EX0=\$3A0; TA1EX0
+
+
+I2CMM_IN=\$200;
+I2CMM_OUT=\$202;
+I2CMM_DIR=\$204;
+I2CMM_REN=\$206;
+I2CMM_SEL=\$20A; SEL0
+I2CMM_Vec=\$FFEC; UCBO_Vec
+MM_SDA=\$40; P1.6
+MM_SCL=\$80; P1.7
+MM_BUS=\$C0;
+
+I2CM_IN=\$200;
+I2CM_OUT=\$202;
+I2CM_DIR=\$204;
+I2CM_REN=\$206;
+I2CM_SEL=\$20A; SEL0
+I2CM_Vec=\$FFEC; UCBO_Vec
+M_SDA=\$40; P1.6
+M_SCL=\$80; P1.7
+M_BUS=\$C0;
+
+I2CS_IN=\$200;
+I2CS_OUT=\$202;
+I2CS_DIR=\$204;
+I2CS_REN=\$206;
+I2CS_SEL=\$20A; SEL0
+I2CS_Vec=\$FFEC; UCBO_Vec
+S_SDA=\$40; P1.6
+S_SCL=\$80; P1.7
+S_BUS=\$C0;
+
+UCSWRST=1; eUSCI Software Reset
+UCTXIE=2; eUSCI Transmit Interrupt Enable
+UCRXIE=1; eUSCI Receive Interrupt Enable
+UCTXIFG=2; eUSCI Transmit Interrupt Flag
+UCRXIFG=1; eUSCI Receive Interrupt Flag
+UCTXIE0=2; eUSCI_B Transmit Interrupt Enable
+UCRXIE0=1; eUSCI_B Receive Interrupt Enable
+UCTXIFG0=2; eUSCI_B Transmit Interrupt Flag
+UCRXIFG0=1; eUSCI_B Receive Interrupt Flag
+
+I2CM_CTLW0=\$640; USCI_B0 Control Word Register 0
+I2CM_CTLW1=\$642; USCI_B0 Control Word Register 1
+I2CM_BRW=\$646; USCI_B0 Baud Word Rate 0
+I2CM_STATW=\$648; USCI_B0 status word
+I2CM_TBCNT=\$64A; USCI_B0 byte counter threshold
+I2CM_RXBUF=\$64C; USCI_B0 Receive Buffer 8
+I2CM_TXBUF=\$64E; USCI_B0 Transmit Buffer 8
+I2CM_I2COA0=\$654; USCI_B0 I2C Own Address 0
+I2CM_ADDRX=\$65C; USCI_B0 Received Address Register
+I2CM_I2CSA=\$660; USCI_B0 I2C Slave Address
+I2CM_IE=\$66A; USCI_B0 Interrupt Enable
+I2CM_IFG=\$66C; USCI_B0 Interrupt Flags Register
+
+I2CS_CTLW0=\$640; USCI_B0 Control Word Register 0
+I2CS_CTLW1=\$642; USCI_B0 Control Word Register 1
+I2CS_BRW=\$646; USCI_B0 Baud Word Rate 0
+I2CS_STATW=\$648; USCI_B0 status word
+I2CS_TBCNT=\$64A; USCI_B0 byte counter threshold
+I2CS_RXBUF=\$64C; USCI_B0 Receive Buffer 8
+I2CS_TXBUF=\$64E; USCI_B0 Transmit Buffer 8
+I2CS_I2COA0=\$654; USCI_B0 I2C Own Address 0
+I2CS_ADDRX=\$65C; USCI_B0 Received Address Register
+I2CS_I2CSA=\$660; USCI_B0 I2C Slave Address
+I2CS_IE=\$66A; USCI_B0 Interrupt Enable
+I2CS_IFG=\$66C; USCI_B0 Interrupt Flags Register
-! -*- coding: utf-8 -*-
-! MSP_EXP430FR5994.pat
-!!
-\.f=\.4th for MSP_EXP430FR5994! to change file type
-
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! replace ! by semicolon
+; MSP_EXP430FR5994.pat
+
+\.f=\.4th for MSP_EXP430FR5994; to change file type
+
+; ========================
+; remove comments
+; ========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! MSP430FR5994 Config
-! ======================================================================
+; ======================================================================
+; MSP430FR5994 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR5994.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR5xxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-! ======================================================================
-! MSP_EXP430FR5994 board
-! ======================================================================
-
-! J101 Target <---> eZ-FET
-! GND 14-13 GND
-! +5V 12-11
-! 3V3 10-9
-! P2.1 UCA0_RX 8-7 <---- TX UARTtoUSB bridge
-! +--4k7-< DeepRST <-- GND
-! |
-! P2.0 UCA0_TX 6-5 <-+-> RX UARTtoUSB bridge
-! /RST 4-3
-! TEST 2-1
-
-
-! P5.6 - sw1 <--- LCD contrast + (finger :-)
-! P5.5 - sw2 <--- LCD contrast - (finger ;-)
-! RST - sw3
-
-! P1.0 - led1 red
-! P1.1 - led2 green
-
-! J1 - left ext.
-! 3v3
-! P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236)
-! P6.1/UCA3RXD/UCA3SOMI -------------------------> 4 LCD_RS
-! P6.0/UCA3TXD/UCA3SIMO -------------------------> 5 LCD_R/W
-! P6.2/UCA3CLK -------------------------> 6 LCD_EN0
-! P1.3/TA1.2/UCB0STE/A3/C3
-! P5.2/UCB1CLK/TA4CLK
-! P6.3/UCA3STE
-! P7.1/UCB2SOMI/UCB2SCL ---> SCL I2C MASTER/SLAVE
-! P7.0/UCB2SIMO/UCB2SDA <--> SDA I2C MASTER/SLAVE
-
-! J3 - left int.
-! 5V
-! GND
-! P3.0/A12/C12 <------------------------> 11 LCD_DB4
-! P3.1/A13/C13 <------------------------> 12 LCD_DB5
-! P3.2/A14/C14 <------------------------> 13 LCD_DB5
-! P3.3/A15/C15 <------------------------> 14 LCD_DB7
-! P1.4/TB0.1/UCA0STE/A4/C4
-! P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! P4.7
-! P8.0
-
-! J4 - right int.
-! P3.7/TB0.6
-! P3.6/TB0.5
-! P3.5/TB0.4/COUT
-! P3.4/TB0.3/SMCLK
-! P7.3/UCB2STE/TA4.1
-! P2.6/TB0.1/UCA1RXD/UCA1SOMI
-! P2.5/TB0.0/UCA1TXD/UCA1SIMO
-! P4.3/A11
-! P4.2/A10 RTS ----> CTS UARTtoUSB bridge (optional hardware control flow)
-! P4.1/A9 CTS <---- RTS UARTtoUSB bridge (optional hardware control flow)
-
-! J2 - right ext.
-! GND
-! P5.7/UCA2STE/TA4.1/MCLK
-! P4.4/TB0.5
-! P5.3/UCB1STE
-! /RST
-! P5.0/UCB1SIMO/UCB1SDA
-! P5.1/UCB1SOMI/UCB1SCL
-! P8.3
-! P8.2 <--> SDA I2C SOFTWARE MASTER
-! P8.1 <--> SCL I2C SOFTWARE MASTER
-
-
-! SD_CARD
-! P7.2/UCB2CLK <--- SD_CD
-! P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 ---> SD_MOSI
-! P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 <--- SD_MISO
-! P4.0/A8 ---> SD_CS
-! P2.2/TB0.2/UCB0CLK ---> SD_CLK
-
-
-
-! XTAL LF 32768 Hz
-! PJ.4/LFXIN
-! PJ.5/LFXOUT
-
-! XTAL HF
-! PJ.6/HFXIN
-! PJ.7/HFXOUT
-
-! -----------------------------------------------
-! LCD config
-! -----------------------------------------------
-
-! <-------+---0V0----------> 1 LCD_Vss
-! >------ | --3V6-----+----> 2 LCD_Vdd
-! | |
-! |___ 470n ---
-! ^ | ---
-! / \ BAT54 |
-! --- |
-! 100n | 2k2 |
-! TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! -------------------------> 4 LCD_RS
-! -------------------------> 5 LCD_R/W
-! -------------------------> 6 LCD_EN0
-! <------------------------> 11 LCD_DB4
-! <------------------------> 12 LCD_DB5
-! <------------------------> 13 LCD_DB5
-! <------------------------> 14 LCD_DB7
-
-
-
-
-! ============================================
-! FORTH I/O :
-! ============================================
-BUS_TERM=3! ; P2.0 = TX, P2.1 = RX
-
-TERM_VEC=\$FFF0! \ UCA0
-WAKE_UP=1! \ RX int
-
-TERM_IN=\$201!
-TERM_REN=\$207!
-TERM_SEL=\$20D! ; SEL1
-
-TERM_CTLW0=\$5C0! \ eUSCI_A0 control word 0
-TERM_CTLW1=\$5C2! \ eUSCI_A0 control word 1
-TERM_BRW=\$5C6!
-TERM_BR0=\$5C6! \ eUSCI_A0 baud rate 0
-TERM_BR1=\$5C7! \ eUSCI_A0 baud rate 1
-TERM_MCTLW=\$5C8! \ eUSCI_A0 modulation control
-TERM_STATW=\$5CA! \ eUSCI_A0 status
-TERM_RXBUF=\$5CC! \ eUSCI_A0 receive buffer
-TERM_TXBUF=\$5CE! \ eUSCI_A0 transmit buffer
-TERM_ABCTL=\$5D0! \ eUSCI_A0 LIN control
-TERM_IRTCTL=\$5D2! \ eUSCI_A0 IrDA transmit control
-TERM_IRRCTL=\$5D3! \ eUSCI_A0 IrDA receive control
-TERM_IE=\$5DA! \ eUSCI_A0 interrupt enable
-TERM_IFG=\$5DC! \ eUSCI_A0 interrupt flags
-TERM_IV=\$5DE! \ eUSCI_A0 interrupt vector word
-
-RTS=4! ; P4.2
-CTS=2! ; P4.1
-HANDSHAKIN=\$221!
-HANDSHAKOUT=\$223!
-
-CD_SD=4! ; P7.2 as Card Detect
-SD_CDIN=\$260!
-
-CS_SD=1! ; P4.0 as Card Select
-SD_CSOUT=\$223!
-SD_CSDIR=\$225!
-
-SD_SEL1=\$20C! ; word access, to configure UCB0
-SD_REN=\$206! ; word access, to configure pullup resistors
-BUS_SD=\$04C0! ; pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0SOMI
-
-SD_CTLW0=\$640! \ eUSCI_B0 control word 0
-SD_CTLW1=\$642! \ eUSCI_B0 control word 1
-SD_BRW=\$646!
-SD_BR0=\$646! \ eUSCI_B0 bit rate 0
-SD_BR1=\$647! \ eUSCI_B0 bit rate 1
-SD_STATW=\$648! \ eUSCI_B0 status word
-SD_NT0=\$649! \ eUSCI_B0 hardware count
-SD_TBCNT=\$64A! \ eUSCI_B0 byte counter threshold
-SD_RXBUF=\$64C! \ eUSCI_B0 receive buffer
-SD_TXBUF=\$64E! \ eUSCI_B0 transmit buffer
-SD_I2COA0=\$654! \ eUSCI_B0 I2C own address 0
-SD_I2COA1=\$656! \ eUSCI_B0 I2C own address 1
-SD_I2COA2=\$658! \ eUSCI_B0 I2C own address 2
-SD_I2COA3=\$65A! \ eUSCI_B0 I2C own address 3
-SD_ADDRX=\$65C! \ eUSCI_B0 received address
-SD_ADDMASK=\$65E! \ eUSCI_B0 address mask
-SD_I2CSA=\$660! \ eUSCI_B0 I2C slave address
-SD_IE=\$66A! \ eUSCI_B0 interrupt enable
-SD_IFG=\$66C! \ eUSCI_B0 interrupt flags
-SD_IV=\$66E! \ eUSCI_B0 interrupt vector word
-
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-LED1_OUT=\$202!
-LED1_DIR=\$204!
-LED1=1! P1.0
-
-LED2_OUT=\$202!
-LED2_DIR=\$204!
-LED2=2! P1.1
-
-SW1_IN=\$240!
-SW1=\$40! P5.6
-
-WIPE_IN=\$240! ; pin as FORTH Deep_RST
-IO_WIPE=\$40! ; P5.6 = S1
-
-SW2_IN=\$240!
-SW2=\$20! P5.5
-
-LCDVo_DIR=\$204!
-LCDVo_SEL=\$20A! SEL0
-LCDVo=\$20! P1.5
-!LCD timer
-LCD_TIM_CTL=\$3C0! TB0CTL
-LCD_TIM_CCTLn=\$3C6! TB0CCTL2
-LCD_TIM_CCR0=\$3D2! TB0CCR0
-LCD_TIM_CCRn=\$3D6! TB0CCR2
-LCD_TIM_EX0=\$3E0! TB0EX0
-
-
-LCD_CMD_IN=\$241!
-LCD_CMD_OUT=\$243!
-LCD_CMD_DIR=\$245!
-LCD_CMD_REN=\$247!
-LCD_RS=2! P6.1
-LCD_RW=1! P6.0
-LCD_EN=4! P6.2
-LCD_CMD=7!
-
-LCD_DB_IN=\$220!
-LCD_DB_OUT=\$222!
-LCD_DB_DIR=\$224!
-LCD_DB_REN=\$226!
-LCD_DB=\$0F! P3.3210
-
-
-!WATCHDOG timer
-WDT_TIM_CTL=\$340! TA0CTL
-WDT_TIM_CCTL0=\$342! TA0CCTL0
-WDT_TIM_CCR0=\$352! TA0CCR0
-WDT_TIM_EX0=\$360! TA0EX0
-WDT_TIM_0_VEC=\$FFEA! TA0_0_VEC
-
-IR_IN=\$200!
-IR_OUT=\$202!
-IR_DIR=\$204!
-IR_REN=\$206!
-IR_IES=\$208!
-IR_IE=\$20A!
-IR_IFG=\$20C!
-IR_VEC=\$FFDE! P1 int
-RC5_=RC5_!
-RC5=4! P1.2
-!IR_RC5 timer
-RC5_TIM_CTL=\$380! TA1CTL
-RC5_TIM_R=\$390! TA1R
-RC5_TIM_EX0=\$3A0! TA1EX0
-
-
-I2CSM_IN=\$261!
-I2CSM_OUT=\$263!
-I2CSM_DIR=\$265!
-I2CSM_REN=\$267!
-SM_SDA=4! P8.2
-SM_SCL=2! P8.1
-SM_BUS=6!
-
-I2CSMM_IN=\$261!
-I2CSMM_OUT=\$263!
-I2CSMM_DIR=\$265!
-I2CSMM_REN=\$267!
-SMM_SDA=4! P8.2
-SMM_SCL=2! P8.1
-SMM_BUS=6!
-
-I2CMM_IN=\$260!
-I2CMM_OUT=\$262!
-I2CMM_DIR=\$264!
-I2CMM_REN=\$266!
-I2CMM_SEL=\$26A! SEL0
-I2CMM_VEC=\$FFBC! UCB2_VEC
-MM_SDA=1! P7.0
-MM_SCL=2! P7.1
-MM_BUS=3!
-
-I2CM_IN=\$260!
-I2CM_OUT=\$262!
-I2CM_DIR=\$264!
-I2CM_REN=\$266!
-I2CM_SEL=\$26A! SEL0
-I2CM_VEC=\$FFBC! UCB2_VEC
-M_SDA=1! P7.0
-M_SCL=2! P7.1
-M_BUS=3!
-
-I2CS_IN=\$260!
-I2CS_OUT=\$262!
-I2CS_DIR=\$264!
-I2CS_REN=\$266!
-I2CS_SEL=\$26A! SEL0
-I2CS_VEC=\$FFBC! UCB2_VEC
-S_SDA=1! P7.0
-S_SCL=2! P7.1
-S_BUS=3!
-
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
-
-I2CM_CTLW0=\$6C0! USCI_B2 Control Word Register 0
-I2CM_CTLW1=\$6C2! USCI_B2 Control Word Register 1
-I2CM_BRW=\$6C6! USCI_B2 Baud Word Rate 0
-I2CM_STATW=\$6C8! USCI_B2 status word
-I2CM_TBCNT=\$6CA! USCI_B2 byte counter threshold
-I2CM_RXBUF=\$6CC! USCI_B2 Receive Buffer 8
-I2CM_TXBUF=\$6CE! USCI_B2 Transmit Buffer 8
-I2CM_I2COA0=\$6D4! USCI_B2 I2C Own Address 0
-I2CM_ADDRX=\$6DC! USCI_B2 Received Address Register
-I2CM_I2CSA=\$6E0! USCI_B2 I2C Slave Address
-I2CM_IE=\$6EA! USCI_B2 Interrupt Enable
-I2CM_IFG=\$6EC! USCI_B2 Interrupt Flags Register
-
-I2CS_CTLW0=\$6C0! USCI_B2 Control Word Register 0
-I2CS_CTLW1=\$6C2! USCI_B2 Control Word Register 1
-I2CS_BRW=\$6C6! USCI_B2 Baud Word Rate 0
-I2CS_STATW=\$6C8! USCI_B2 status word
-I2CS_TBCNT=\$6CA! USCI_B2 byte counter threshold
-I2CS_RXBUF=\$6CC! USCI_B2 Receive Buffer 8
-I2CS_TXBUF=\$6CE! USCI_B2 Transmit Buffer 8
-I2CS_I2COA0=\$6D4! USCI_B2 I2C Own Address 0
-I2CS_ADDRX=\$6DC! USCI_B2 Received Address Register
-I2CS_I2CSA=\$6E0! USCI_B2 I2C Slave Address
-I2CS_IE=\$6EA! USCI_B2 Interrupt Enable
-I2CS_IFG=\$6EC! USCI_B2 Interrupt Flags Register
+; ======================================================================
+; MSP_EXP430FR5994 board
+; ======================================================================
+
+; J101 Target <---> eZ-FET
+; GND 14-13 GND
+; +5V 12-11
+; 3V3 10-9
+; P2.1 UCA0_RX 8-7 <---- TX UARTtoUSB bridge
+; +--4k7-< DeepRST <-- GND
+; |
+; P2.0 UCA0_TX 6-5 <-+-> RX UARTtoUSB bridge
+; /RST 4-3
+; TEST 2-1
+
+
+; P5.6 - sw1 <--- LCD contrast + (finger :-)
+; P5.5 - sw2 <--- LCD contrast - (finger ;-)
+; RST - sw3
+
+; P1.0 - led1 red
+; P1.1 - led2 green
+
+; J1 - left ext.
+; 3v3
+; P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236)
+; P6.1/UCA3RXD/UCA3SOMI -------------------------> 4 LCD_RS
+; P6.0/UCA3TXD/UCA3SIMO -------------------------> 5 LCD_R/W
+; P6.2/UCA3CLK -------------------------> 6 LCD_EN0
+; P1.3/TA1.2/UCB0STE/A3/C3
+; P5.2/UCB1CLK/TA4CLK
+; P6.3/UCA3STE
+; P7.1/UCB2SOMI/UCB2SCL ---> SCL I2C MASTER/SLAVE
+; P7.0/UCB2SIMO/UCB2SDA <--> SDA I2C MASTER/SLAVE
+
+; J3 - left int.
+; 5V
+; GND
+; P3.0/A12/C12 <------------------------> 11 LCD_DB4
+; P3.1/A13/C13 <------------------------> 12 LCD_DB5
+; P3.2/A14/C14 <------------------------> 13 LCD_DB5
+; P3.3/A15/C15 <------------------------> 14 LCD_DB7
+; P1.4/TB0.1/UCA0STE/A4/C4
+; P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; P4.7
+; P8.0
+
+; J4 - right int.
+; P3.7/TB0.6
+; P3.6/TB0.5
+; P3.5/TB0.4/COUT
+; P3.4/TB0.3/SMCLK
+; P7.3/UCB2STE/TA4.1
+; P2.6/TB0.1/UCA1RXD/UCA1SOMI
+; P2.5/TB0.0/UCA1TXD/UCA1SIMO
+; P4.3/A11
+; P4.2/A10 RTS ----> CTS UARTtoUSB bridge (optional hardware control flow)
+; P4.1/A9 CTS <---- RTS UARTtoUSB bridge (optional hardware control flow)
+
+; J2 - right ext.
+; GND
+; P5.7/UCA2STE/TA4.1/MCLK
+; P4.4/TB0.5
+; P5.3/UCB1STE
+; /RST
+; P5.0/UCB1SIMO/UCB1SDA
+; P5.1/UCB1SOMI/UCB1SCL
+; P8.3
+; P8.2 <--> SDA I2C SOFTWARE MASTER
+; P8.1 <--> SCL I2C SOFTWARE MASTER
+
+
+; SD_CARD
+; P7.2/UCB2CLK <--- SD_CD
+; P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 ---> SD_MOSI
+; P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 <--- SD_MISO
+; P4.0/A8 ---> SD_CS
+; P2.2/TB0.2/UCB0CLK ---> SD_CLK
+
+
+
+; XTAL LF 32768 Hz
+; PJ.4/LFXIN
+; PJ.5/LFXOUT
+
+; XTAL HF
+; PJ.6/HFXIN
+; PJ.7/HFXOUT
+
+; -----------------------------------------------
+; LCD config
+; -----------------------------------------------
+
+; <-------+---0V0----------> 1 LCD_Vss
+; >------ | --3V6-----+----> 2 LCD_Vdd
+; | |
+; |___ 470n ---
+; ^ | ---
+; / \ BAT54 |
+; --- |
+; 100n | 2k2 |
+; TB0.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; -------------------------> 4 LCD_RS
+; -------------------------> 5 LCD_R/W
+; -------------------------> 6 LCD_EN0
+; <------------------------> 11 LCD_DB4
+; <------------------------> 12 LCD_DB5
+; <------------------------> 13 LCD_DB5
+; <------------------------> 14 LCD_DB7
+
+
+
+
+; FFB4-FFFF 37 vectors + reset
+; 0FFB4h - LEA_Vec
+; 0FFB6h - P8_Vec
+; 0FFB8h - P7_Vec
+; 0FFBAh - eUSCI_B3_Vec
+; 0FFBCh - eUSCI_B2_Vec
+; 0FFBEh - eUSCI_B1_Vec
+; 0FFC0h - eUSCI_A3_Vec
+; 0FFC2h - eUSCI_A2_Vec
+; 0FFC4h - P6_Vec
+; 0FFC6h - P5_Vec
+; 0FFC8h - TA4_x_Vec
+; 0FFCAh - TA4_0_Vec
+; 0FFCCh - AES_Vec
+; 0FFCEh - RTC_C_Vec
+; 0FFD0h - P4_Vec=
+; 0FFD2h - P3_Vec=
+; 0FFD4h - TA3_x_Vec
+; 0FFD6h - TA3_0_Vec
+; 0FFD8h - P2_Vec
+; 0FFDAh - TA2_x_Vec
+; 0FFDCh - TA2_0_Vec
+; 0FFDEh - P1_Vec=
+; 0FFE0h - TA1_x_Vec
+; 0FFE2h - TA1_0_Vec
+; 0FFE4h - DMA_Vec
+; 0FFE6h - eUSCI_A1_Vec
+; 0FFE8h - TA0_x_Vec
+; 0FFEAh - TA0_0_Vec
+; 0FFECh - ADC12_B_Vec
+; 0FFEEh - eUSCI_B0_Vec
+; 0FFF0h - eUSCI_A0_Vec
+; 0FFF2h - WDT_Vec
+; 0FFF4h - TB0_x_Vec
+; 0FFF6h - TB0_0_Vec
+; 0FFF8h - COMP_E_Vec
+; 0FFFAh - U_NMI_Vec
+; 0FFFCh - S_NMI_Vec
+; 0FFFEh - RST_Vec
+
+
+; ----------------------------------------------------------------------
+; MSP430FR5994 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .equ 0100h ; Special function
+;PMM_SFR .equ 0120h ; PMM
+;FRAM_SFR .equ 0140h ; FRAM control
+;CRC16_SFR .equ 0150h
+;RAM_SFR .equ 0158h
+;WDT_A_SFR .equ 015Ch ; Watchdog
+;CS_SFR .equ 0160h ; Clock System
+;SYS_SFR .equ 0180h ; SYS
+;REF_SFR .equ 01B0h ; REF
+;PA_SFR .equ 0200h ; PORT1/2
+;PB_SFR .equ 0220h ; PORT3/4
+;PC_SFR .equ 0240h ; PORT3/4
+;PD_SFR .equ 0260h ; PORT3/4
+;PJ_SFR .equ 0320h ; PORTJ
+;TA0_SFR .equ 0340h
+;TA1_SFR .equ 0380h
+;TB0_SFR .equ 03C0h
+;TA2_SFR .equ 0400h
+;CTIO0_SFR .equ 0430h ; Capacitive Touch IO
+;TA3_SFR .equ 0440h
+;CTIO1_SFR .equ 0470h ; Capacitive Touch IO
+;RTC_C_SFR .equ 04A0h
+;MPY_SFR .equ 04C0h
+;DMA_CTRL_SFR .equ 0500h
+;DMA_CHN0_SFR .equ 0510h
+;DMA_CHN1_SFR .equ 0520h
+;DMA_CHN2_SFR .equ 0530h
+;DMA_CHN3_SFR .equ 0540h
+;DMA_CHN4_SFR .equ 0550h
+;DMA_CHN5_SFR .equ 0560h
+;MPU_SFR .equ 05A0h ; memory protect unit
+;eUSCI_A0_SFR .equ 05C0h ; eUSCI_A0
+;eUSCI_A1_SFR .equ 05E0h ; eUSCI_A1
+;eUSCI_A2_SFR .equ 0600h ; eUSCI_A1
+;eUSCI_A3_SFR .equ 0620h ; eUSCI_A1
+;eUSCI_B0_SFR .equ 0640h ; eUSCI_B0
+;eUSCI_B1_SFR .equ 0680h ; eUSCI_B1
+;eUSCI_B2_SFR .equ 06C0h ; eUSCI_B2
+;eUSCI_B3_SFR .equ 0700h ; eUSCI_B3
+;TA4_SFR .equ 07C0h
+;ADC12_B_SFR .equ 0800h
+;COMP_E_SFR .equ 08C0h
+;CRC32_SFR .equ 0980h
+;AES_SFR .equ 09C0h
+;LEA_SFR .equ 0A80h
+
+; ============================================
+; FAST FORTH configuration :
+; ============================================
+BUS_TERM=3; ; P2.0 = TX, P2.1 = RX
+
+TERM_VEC=\$FFF0; \ UCA0
+UCSWRST=1; eUSCI Software Reset
+WAKE_UP=1; \ RX int
+RX=1; RX flag IFG
+TX=2; Tx flag IFG
+
+TERM_IN=\$201;
+TERM_REN=\$207;
+TERM_SEL=\$20D; ; SEL1
+
+TERM_CTLW0=\$5C0; \ eUSCI_A0 control word 0
+TERM_CTLW1=\$5C2; \ eUSCI_A0 control word 1
+TERM_BRW=\$5C6;
+TERM_BR0=\$5C6; \ eUSCI_A0 baud rate 0
+TERM_BR1=\$5C7; \ eUSCI_A0 baud rate 1
+TERM_MCTLW=\$5C8; \ eUSCI_A0 modulation control
+TERM_STATW=\$5CA; \ eUSCI_A0 status
+TERM_RXBUF=\$5CC; \ eUSCI_A0 receive buffer
+TERM_TXBUF=\$5CE; \ eUSCI_A0 transmit buffer
+TERM_IE=\$5DA; \ eUSCI_A0 interrupt enable
+TERM_IFG=\$5DC; \ eUSCI_A0 interrupt flags
+TERM_IV=\$5DE; \ eUSCI_A0 interrupt vector word
+
+RTS=4; ; P4.2
+CTS=2; ; P4.1
+HANDSHAKIN=\$221;
+HANDSHAKOUT=\$223;
+
+CD_SD=4; ; P7.2 as Card Detect
+SD_CDIN=\$260;
+
+CS_SD=1; ; P4.0 as Card Select
+SD_CSOUT=\$223;
+SD_CSDIR=\$225;
+
+SD_SEL1=\$20C; ; word access, to configure UCB0
+SD_REN=\$206; ; word access, to configure pullup resistors
+BUS_SD=\$04C0; ; pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0SOMI
+
+SD_CTLW0=\$640; \ eUSCI_B0 control word 0
+SD_CTLW1=\$642; \ eUSCI_B0 control word 1
+SD_BRW=\$646;
+SD_BR0=\$646; \ eUSCI_B0 bit rate 0
+SD_BR1=\$647; \ eUSCI_B0 bit rate 1
+SD_STATW=\$648; \ eUSCI_B0 status word
+SD_NT0=\$649; \ eUSCI_B0 hardware count
+SD_TBCNT=\$64A; \ eUSCI_B0 byte counter threshold
+SD_RXBUF=\$64C; \ eUSCI_B0 receive buffer
+SD_TXBUF=\$64E; \ eUSCI_B0 transmit buffer
+SD_I2COA0=\$654; \ eUSCI_B0 I2C own address 0
+SD_I2COA1=\$656; \ eUSCI_B0 I2C own address 1
+SD_I2COA2=\$658; \ eUSCI_B0 I2C own address 2
+SD_I2COA3=\$65A; \ eUSCI_B0 I2C own address 3
+SD_ADDRX=\$65C; \ eUSCI_B0 received address
+SD_ADDMASK=\$65E; \ eUSCI_B0 address mask
+SD_I2CSA=\$660; \ eUSCI_B0 I2C slave address
+SD_IE=\$66A; \ eUSCI_B0 interrupt enable
+SD_IFG=\$66C; \ eUSCI_B0 interrupt flags
+SD_IV=\$66E; \ eUSCI_B0 interrupt vector word
+
+
+LFXT_OUT=\$322; PJ
+LFXT_DIR=\$324; PJ
+LFXT_SEL=\$32A; PJSEL0
+LFXIN=\$10; PJ.4
+LFXOUT=\$20; PJ.5
+
+; FAST FORTH I/O :
+LED1_OUT=\$202;
+LED1_DIR=\$204;
+LED1=1; P1.0
+LED2_OUT=\$202;
+LED2_DIR=\$204;
+LED2=2; P1.1
+
+SW1_IN=\$240;
+SW1=\$40; P5.6
+SW2_IN=\$240;
+SW2=\$20; P5.5
+
+; ============================================
+; UARTI2CS APPLICATION
+; ============================================
+;I2C_Soft_Master
+I2CSM_IN=\$261;
+I2CSM_OUT=\$263;
+I2CSM_DIR=\$265;
+I2CSM_REN=\$267;
+SM_SDA=4; P8.2
+SM_SCL=2; P8.1
+SM_BUS=6;
+
+;500_ms_INT TIMER
+TIM_CTL=\$3C0; TB0
+TIM_CCTL2=\$3C6;
+TIM_CCR0=\$3D2;
+TIM_CCR2=\$3D6;
+T_OUT2=\$20; P1.5 <--- TB0.2
+T_OUT2_DIR=\$204; P1DIR
+T_OUT2_SEL=\$20C; P1SEL1
+INT_IN=\$10; P1.4
+INT_IN_IE=\$21A; P1IE
+INT_IN_IFG=\$21C; P1IFG
+INT_IN_VEC=\$FFDE; P1VEC
+
+;local variables
+UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+TIMER_CONF=\{UARTI2CS\}\+12; <-- TIM_CTL configuration
+COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+; ============================================
+; RC5toLCD APPLICATION
+; ============================================
+LCDVo_DIR=\$204;
+LCDVo_SEL=\$20A; SEL0
+LCDVo=\$20; P1.5
+;LCD timer
+LCD_TIM_CTL=\$3C0; TB0CTL
+LCD_TIM_CCTLn=\$3C6; TB0CCTL2
+LCD_TIM_CCR0=\$3D2; TB0CCR0
+LCD_TIM_CCRn=\$3D6; TB0CCR2
+LCD_TIM_EX0=\$3E0; TB0EX0
+;LCD command bus
+LCD_CMD_IN=\$241;
+LCD_CMD_OUT=\$243;
+LCD_CMD_DIR=\$245;
+LCD_CMD_REN=\$247;
+LCD_RS=2; P6.1
+LCD_RW=1; P6.0
+LCD_EN=4; P6.2
+LCD_CMD=7;
+;LCD data bus
+LCD_DB_IN=\$220;
+LCD_DB_OUT=\$222;
+LCD_DB_DIR=\$224;
+LCD_DB_REN=\$226;
+LCD_DB=\$0F; P3.3210
+;WATCHDOG timer
+WDT_TIM_CTL=\$340; TA0CTL
+WDT_TIM_CCTL0=\$342; TA0CCTL0
+WDT_TIM_CCR0=\$352; TA0CCR0
+WDT_TIM_EX0=\$360; TA0EX0
+WDT_TIM_0_VEC=\$FFEA; TA0_0_VEC
+;IR_RC5
+IR_IN=\$200;
+IR_OUT=\$202;
+IR_DIR=\$204;
+IR_REN=\$206;
+IR_IES=\$208;
+IR_IE=\$20A;
+IR_IFG=\$20C;
+IR_VEC=\$FFDE; P1 int
+RC5_=RC5_;
+RC5=4; P1.2
+;IR_RC5 timer
+RC5_TIM_CTL=\$380; TA1CTL
+RC5_TIM_R=\$390; TA1R
+RC5_TIM_EX0=\$3A0; TA1EX0
+; --------------------------------------------
+
+I2CSMM_IN=\$261;
+I2CSMM_OUT=\$263;
+I2CSMM_DIR=\$265;
+I2CSMM_REN=\$267;
+SMM_SDA=4; P8.2
+SMM_SCL=2; P8.1
+SMM_BUS=6;
+
+I2CMM_IN=\$260;
+I2CMM_OUT=\$262;
+I2CMM_DIR=\$264;
+I2CMM_REN=\$266;
+I2CMM_SEL=\$26A; SEL0
+I2CMM_VEC=\$FFBC; UCB2_VEC
+MM_SDA=1; P7.0
+MM_SCL=2; P7.1
+MM_BUS=3;
+
+I2CM_IN=\$260;
+I2CM_OUT=\$262;
+I2CM_DIR=\$264;
+I2CM_REN=\$266;
+I2CM_SEL=\$26A; SEL0
+I2CM_VEC=\$FFBC; UCB2_VEC
+M_SDA=1; P7.0
+M_SCL=2; P7.1
+M_BUS=3;
+
+I2CS_IN=\$260;
+I2CS_OUT=\$262;
+I2CS_DIR=\$264;
+I2CS_REN=\$266;
+I2CS_SEL=\$26A; SEL0
+I2CS_VEC=\$FFBC; UCB2_VEC
+S_SDA=1; P7.0
+S_SCL=2; P7.1
+S_BUS=3;
+
+I2CM_CTLW0=\$6C0; USCI_B2 Control Word Register 0
+I2CM_CTLW1=\$6C2; USCI_B2 Control Word Register 1
+I2CM_BRW=\$6C6; USCI_B2 Baud Word Rate 0
+I2CM_STATW=\$6C8; USCI_B2 status word
+I2CM_TBCNT=\$6CA; USCI_B2 byte counter threshold
+I2CM_RXBUF=\$6CC; USCI_B2 Receive Buffer 8
+I2CM_TXBUF=\$6CE; USCI_B2 Transmit Buffer 8
+I2CM_I2COA0=\$6D4; USCI_B2 I2C Own Address 0
+I2CM_ADDRX=\$6DC; USCI_B2 Received Address Register
+I2CM_I2CSA=\$6E0; USCI_B2 I2C Slave Address
+I2CM_IE=\$6EA; USCI_B2 Interrupt Enable
+I2CM_IFG=\$6EC; USCI_B2 Interrupt Flags Register
+
+I2CS_CTLW0=\$6C0; USCI_B2 Control Word Register 0
+I2CS_CTLW1=\$6C2; USCI_B2 Control Word Register 1
+I2CS_BRW=\$6C6; USCI_B2 Baud Word Rate 0
+I2CS_STATW=\$6C8; USCI_B2 status word
+I2CS_TBCNT=\$6CA; USCI_B2 byte counter threshold
+I2CS_RXBUF=\$6CC; USCI_B2 Receive Buffer 8
+I2CS_TXBUF=\$6CE; USCI_B2 Transmit Buffer 8
+I2CS_I2COA0=\$6D4; USCI_B2 I2C Own Address 0
+I2CS_ADDRX=\$6DC; USCI_B2 Received Address Register
+I2CS_I2CSA=\$6E0; USCI_B2 I2C Slave Address
+I2CS_IE=\$6EA; USCI_B2 Interrupt Enable
+I2CS_IFG=\$6EC; USCI_B2 Interrupt Flags Register
-! -*- coding: utf-8 -*-
-! MSP_EXP430FR6989.pat
-!
-\.f=\.4th for MSP_EXP430FR6989! to change file type
-!
-!========================
-! remove comments
-!========================
+
+@set-syntax{C;\;}! replace ! by semicolon
+; MSP_EXP430FR6989.pat
+;
+\.f=\.4th for MSP_EXP430FR6989; to change file type
+; ========================
+; remove comments
+; ========================
\\*\n=
\s\\*\n=\n
-! ======================================================================
-! MSP430FR6989 Config
-! ======================================================================
+; ======================================================================
+; MSP430FR6989 Config
+; ======================================================================
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};MSP430FR6989.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FRxxxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
+@define{@read{@mergepath{@inpath{};MSP430FR5xxx.pat;}}}
+@reset-syntax{}; to enable good interpreting of next line
@define{@read{@mergepath{@inpath{};FastForthREGtoTI.pat;}}}
-! ======================================================================
-! MSP_EXP430FR6989 board
-! ======================================================================
-
-! ---------------------------------------------------
-! MSP - MSP-EXP430FR6989 LAUNCHPAD <--> OUTPUT WORLD
-! ---------------------------------------------------
-! P1.0 - LED1 red
-! P9.7 - LED2 green
-!
-! P1.1 - Switch S1 <--- LCD contrast + (finger :-)
-! P1.2 - Switch S2 <--- LCD contrast - (finger ;-)
-!
-! note : ESI1.1 = lowest left pin
-! note : ESI1.2 is not connected to 3.3V
-! GND J6.2 <-------+---0V0----------> 1 LCD_Vss
-! VCC J6.1 >------ | --3V3-----+----> 2 LCD_Vdd
-! | |
-! |___ 470n ---
-! ^ | ---
-! / \ BAT54 |
-! --- |
-! 100n | 2k2 |
-! P3.6 - UCA1 CLK TB0.2 J4.37 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
-! P9.0/ESICH0 - ESI1.14 <------------------------> 11 LCD_DB4 brown
-! P9.1/ESICH1 - ESI1.13 <------------------------> 12 LCD_DB5 red
-! P9.2/ESICH2 - ESI1.12 <------------------------> 13 LCD_DB5 orange
-! P9.3/ESICH3 - ESI1.11 <------------------------> 14 LCD_DB7 yellow
-! P4.1 -------------------------> 4 LCD_RS yellow
-! P4.2 -------------------------> 5 LCD_R/W green
-! P4.3 -------------------------> 6 LCD_EN blue
-!
-! +--4k7-< DeepRST <-- GND
-! |
-! P3.4 - UCA1 TXD J101.8 <-+-> RX UARTtoUSB bridge
-! P3.5 - UCA1 RXD J101.10 <---- TX UARTtoUSB bridge
-! P3.0 - RTS J101.14 ----> CTS UARTtoUSB bridge (optional hardware control flow)
-! VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
-! GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge)
-!
-! VCC - J1.1 ----> VCC SD_CardAdapter
-! GND - J2.20 <---> GND SD_CardAdapter
-! P2.2 - UCA0 CLK J4.35 ----> CLK SD_CardAdapter (SCK)
-! P2.6 - J4.39 ----> CS SD_CardAdapter (Card Select)
-! P2.0 - UCA0 TXD/SIMO J1.8 ----> SDI SD_CardAdapter (MOSI)
-! P2.1 - UCA0 RXD/SOMI J2.19 <---- SDO SD_CardAdapter (MISO)
-! P2.7 - J4.40 <---- CD SD_CardAdapter (Card Detect)
-!
-! P4.0 - J1.10 <---- OUT IR_Receiver (1 TSOP32236)
-! VCC - J1.1 ----> VCC IR_Receiver (2 TSOP32236)
-! GND - J2.20 <---> GND IR_Receiver (3 TSOP32236)
-!
-! P1.3 - J4.34 <---> SDA software I2C Master
-! P1.5 - J2.18 ----> SCL software I2C Master
-!
-! P1.4 -UCB0 CLK TA1.0 J1.7 <---> free
-!
-! P1.6 -UCB0 SDA/SIMO J2.15 <---> SDA hardware I2C Master or Slave
-! P1.7 -UCB0 SCL/SOMI J2.14 ----> SCL hardware I2C Master or Slave
-!
-! P3.0 -UCB1 CLK J4.33 ----> free (if UARTtoUSB with software control flow)
-! P3.1 -UCB1 SDA/SIMO J4.32 <---> free (if UARTtoUSB with software control flow)
-! P3.2 -UCB1 SCL/SOMI J1.5 ----> free
-! P3.3 - TA1.1 J1.5 <---> free
-!
-! PJ.4 - LFXI 32768Hz quartz
-! PJ.5 - LFXO 32768Hz quartz
-! PJ.6 - HFXI
-! PJ.7 - HFXO
-
-
-! ============================================
-! FORTH I/O :
-! ============================================
-BUS_TERM=\$30! \ P3.5 = RX, P3.4 = TX
-
-TERM_IN=\$220!
-TERM_REN=\$226!
-TERM_SEL=\$22C! \ SEL0
-
-TERM_VEC=\$FFE4! \ UCA1
-WAKE_UP=1! \ RX int
-
-TERM_CTLW0=\$5E0! \ eUSCI_A control word 0
-TERM_CTLW1=\$5E2! \ eUSCI_A control word 1
-TERM_BRW=\$5E6!
-TERM_BR0=\$5E6! \ eUSCI_A baud rate 0
-TERM_BR1=\$5E7! \ eUSCI_A baud rate 1
-TERM_MCTLW=\$5E8! \ eUSCI_A modulation control
-TERM_STAT=\$5EA! \ eUSCI_A status
-TERM_RXBUF=\$5EC! \ eUSCI_A receive buffer
-TERM_TXBUF=\$5EE! \ eUSCI_A transmit buffer
-TERM_ABCTL=\$5F0! \ eUSCI_A LIN control
-TERM_IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control
-TERM_IRRCTL=\$5F3! \ eUSCI_A IrDA receive control
-TERM_IE=\$5FA! \ eUSCI_A interrupt enable
-TERM_IFG=\$5FC! \ eUSCI_A interrupt flags
-TERM_IV=\$5FE! \ eUSCI_A interrupt vector word
-
-RTS=1! ; P3.0
-CTS=2! ; P3.1
-HANDSHAKIN=\$220!
-HANDSHAKOUT=\$222!
-
-
-CD_SD=\$80! ; P2.7 as Card Detect
-SD_CDIN=\$201!
-
-CS_SD=\$40! ; P2.6 as Card Select
-SD_CSOUT=\$203!
-SD_CSDIR=\$205!
-
-BUS_SD=\$07! ; pins P2.2 as UCB0CLK, P2.0 as UCB0SIMO & P2.1 as UCB0SOMI
-SD_SEL=\$20C! ; to configure UCB0
-SD_REN=\$206! ; to configure pullup resistors
-
-
-! ============================================
-! APPLICATION I/O :
-! ============================================
-LED1_OUT=\$202!
-LED1=1! P1.0
-
-LED2_OUT=\$282!
-LED2=\$80! P9.7
-
-SW1_IN=\$200!
-SW1=2! P1.1
-
-WIPE_IN=\$200! ; pin as FORTH Deep_RST
-IO_WIPE=2! ; P1.1 = S1
-
-SW2_IN=\$200!
-SW2=4! P1.2
-
-LCDVo_DIR=\$224!
-LCDVo_SEL=\$22C! SEL1
-LCDVo=\$40! P3.6
-
-!LCD timer
-LCD_TIM_CTL=\$3C0! TB0CTL
-LCD_TIM_CCTLn=\$3C6! TB0CCTL2
-LCD_TIM_CCR0=\$3D2! TB0CCR0
-LCD_TIM_CCRn=\$3D6! TB0CCR2
-LCD_TIM_EX0=\$3E0! TB0EX0
-
-LCD_CMD_IN=\$221!
-LCD_CMD_OUT=\$223!
-LCD_CMD_DIR=\$225!
-LCD_CMD_REN=\$227!
-LCD_RS=2! P4.1
-LCD_RW=4! P4.2
-LCD_EN=8! P4.3
-LCD_CMD=\$0E!
-
-LCD_DB_IN=\$280!
-LCD_DB_OUT=\$282!
-LCD_DB_DIR=\$284!
-LCD_DB_REN=\$286!
-LCD_DB=\$0F! P9.3-0
-
-
-!WATCHDOG timer
-WDT_TIM_CTL=\$340! TA0CTL
-WDT_TIM_CCTL0=\$342! TA0CCTL0
-WDT_TIM_CCR0=\$352! TA0CCR0
-WDT_TIM_EX0=\$360! TA0EX0
-WDT_TIM_0_Vec=\$FFE8! TA0_0_Vec
-
-IR_IN=\$221!
-IR_OUT=\$223!
-IR_DIR=\$225!
-IR_REN=\$227!
-IR_IES=\$239!
-IR_IE=\$23B!
-IR_IFG=\$23D!
-RC5_=RC5_!
-RC5=1! P4.0
-IR_Vec=\$FFCC! P4 int
-
-I2CSM_IN=\$200!
-I2CSM_OUT=\$202!
-I2CSM_DIR=\$204!
-I2CSM_REN=\$206!
-SM_SDA=8! P1.3
-SM_SCL=\$20! P1.5
-SM_BUS=\$28!
-
-I2CSMM_IN=\$200!
-I2CSMM_OUT=\$202!
-I2CSMM_DIR=\$204!
-I2CSMM_REN=\$206!
-SMM_SDA=8! P1.3
-SMM_SCL=\$20! P1.5
-SMM_BUS=\$28!
-RC5_TIM_CTL=\$380! TA1CTL
-RC5_TIM_R=\$390! TA1R
-RC5_TIM_EX0=\$3A0! TA1EX0
-
-
-I2CMM_IN=\$200!
-I2CMM_OUT=\$202!
-I2CMM_DIR=\$204!
-I2CMM_REN=\$206!
-I2CMM_SEL=\$20A! SEL0
-I2CMM_Vec=\$FFEC! UCBO_Vec
-MM_SDA=\$40! P1.6
-MM_SCL=\$80! P1.7
-MM_BUS=\$C0!
-
-I2CM_IN=\$200!
-I2CM_OUT=\$202!
-I2CM_DIR=\$204!
-I2CM_REN=\$206!
-I2CM_SEL=\$20A! SEL0
-I2CM_Vec=\$FFEC! UCBO_Vec
-M_SDA=\$40! P1.6
-M_SCL=\$80! P1.7
-M_BUS=\$C0!
-
-I2CS_IN=\$200!
-I2CS_OUT=\$202!
-I2CS_DIR=\$204!
-I2CS_REN=\$206!
-I2CS_SEL=\$20A! SEL0
-I2CS_Vec=\$FFEC! UCBO_Vec
-S_SDA=\$40! P1.6
-S_SCL=\$80! P1.7
-S_BUS=\$C0!
-
-UCSWRST=1! eUSCI Software Reset
-UCTXIE=2! eUSCI Transmit Interrupt Enable
-UCRXIE=1! eUSCI Receive Interrupt Enable
-UCTXIFG=2! eUSCI Transmit Interrupt Flag
-UCRXIFG=1! eUSCI Receive Interrupt Flag
-UCTXIE0=2! eUSCI_B Transmit Interrupt Enable
-UCRXIE0=1! eUSCI_B Receive Interrupt Enable
-UCTXIFG0=2! eUSCI_B Transmit Interrupt Flag
-UCRXIFG0=1! eUSCI_B Receive Interrupt Flag
-
-I2CM_CTLW0=\$640! USCI_B0 Control Word Register 0
-I2CM_CTLW1=\$642! USCI_B0 Control Word Register 1
-I2CM_BRW=\$646! USCI_B0 Baud Word Rate 0
-I2CM_STATW=\$648! USCI_B0 status word
-I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold
-I2CM_RXBUF=\$64C! USCI_B0 Receive Buffer 8
-I2CM_TXBUF=\$64E! USCI_B0 Transmit Buffer 8
-I2CM_I2COA0=\$654! USCI_B0 I2C Own Address 0
-I2CM_ADDRX=\$65C! USCI_B0 Received Address Register
-I2CM_I2CSA=\$660! USCI_B0 I2C Slave Address
-I2CM_IE=\$66A! USCI_B0 Interrupt Enable
-I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register
-
-I2CS_CTLW0=\$640! USCI_B0 Control Word Register 0
-I2CS_CTLW1=\$642! USCI_B0 Control Word Register 1
-I2CS_BRW=\$646! USCI_B0 Baud Word Rate 0
-I2CS_STATW=\$648! USCI_B0 status word
-I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold
-I2CS_RXBUF=\$64C! USCI_B0 Receive Buffer 8
-I2CS_TXBUF=\$64E! USCI_B0 Transmit Buffer 8
-I2CS_I2COA0=\$654! USCI_B0 I2C Own Address 0
-I2CS_ADDRX=\$65C! USCI_B0 Received Address Register
-I2CS_I2CSA=\$660! USCI_B0 I2C Slave Address
-I2CS_IE=\$66A! USCI_B0 Interrupt Enable
-I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register
+; ======================================================================
+; MSP_EXP430FR6989 board
+; ======================================================================
+
+; ---------------------------------------------------
+; MSP - MSP-EXP430FR6989 LAUNCHPAD <--> OUTPUT WORLD
+; ---------------------------------------------------
+; P1.0 - LED1 red
+; P9.7 - LED2 green
+;
+; P1.1 - Switch S1 <--- LCD contrast + (finger :-)
+; P1.2 - Switch S2 <--- LCD contrast - (finger ;-)
+;
+; note : ESI1.1 = lowest left pin
+; note : ESI1.2 is not connected to 3.3V
+; GND J6.2 <-------+---0V0----------> 1 LCD_Vss
+; VCC J6.1 >------ | --3V3-----+----> 2 LCD_Vdd
+; | |
+; |___ 470n ---
+; ^ | ---
+; / \ BAT54 |
+; --- |
+; 100n | 2k2 |
+; P3.6 - UCA1 CLK TB0.2 J4.37 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
+; P9.0/ESICH0 - ESI1.14 <------------------------> 11 LCD_DB4 brown
+; P9.1/ESICH1 - ESI1.13 <------------------------> 12 LCD_DB5 red
+; P9.2/ESICH2 - ESI1.12 <------------------------> 13 LCD_DB5 orange
+; P9.3/ESICH3 - ESI1.11 <------------------------> 14 LCD_DB7 yellow
+; P4.1 -------------------------> 4 LCD_RS yellow
+; P4.2 -------------------------> 5 LCD_R/W green
+; P4.3 -------------------------> 6 LCD_EN blue
+;
+; +--4k7-< DeepRST <-- GND
+; |
+; P3.4 - UCA1 TXD J101.8 <-+-> RX UARTtoUSB bridge
+; P3.5 - UCA1 RXD J101.10 <---- TX UARTtoUSB bridge
+; P3.0 - RTS J101.14 ----> CTS UARTtoUSB bridge (optional hardware control flow)
+; VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ; 3.3V !)
+; GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge)
+;
+; VCC - J1.1 ----> VCC SD_CardAdapter
+; GND - J2.20 <---> GND SD_CardAdapter
+; P2.2 - UCA0 CLK J4.35 ----> CLK SD_CardAdapter (SCK)
+; P2.6 - J4.39 ----> CS SD_CardAdapter (Card Select)
+; P2.0 - UCA0 TXD/SIMO J1.8 ----> SDI SD_CardAdapter (MOSI)
+; P2.1 - UCA0 RXD/SOMI J2.19 <---- SDO SD_CardAdapter (MISO)
+; P2.7 - J4.40 <---- CD SD_CardAdapter (Card Detect)
+;
+; P4.0 - J1.10 <---- OUT IR_Receiver (1 TSOP32236)
+; VCC - J1.1 ----> VCC IR_Receiver (2 TSOP32236)
+; GND - J2.20 <---> GND IR_Receiver (3 TSOP32236)
+;
+; P1.3 - J4.34 <---> SDA software I2C Master
+; P1.5 - J2.18 ----> SCL software I2C Master
+;
+; P1.4 -UCB0 CLK TA1.0 J1.7 <---> free
+;
+; P1.6 -UCB0 SDA/SIMO J2.15 <---> SDA hardware I2C Master or Slave
+; P1.7 -UCB0 SCL/SOMI J2.14 ----> SCL hardware I2C Master or Slave
+;
+; P3.0 -UCB1 CLK J4.33 ----> free (if UARTtoUSB with software control flow)
+; P3.1 -UCB1 SDA/SIMO J4.32 <---> free (if UARTtoUSB with software control flow)
+; P3.2 -UCB1 SCL/SOMI J1.5 ----> free
+; P3.3 - TA1.1 J1.5 <---> free
+;
+; PJ.4 - LFXI 32768Hz quartz
+; PJ.5 - LFXO 32768Hz quartz
+; PJ.6 - HFXI
+; PJ.7 - HFXO
+
+
+; FFC6-FFFF 28 vectors + reset
+; 0FFC6h - AES
+; 0FFC8h - RTC_C
+; 0FFCAh - LCD_C
+; 0FFCCh - I/O Port 4
+; 0FFCEh - I/O Port 3
+; 0FFD0h - TA3_x
+; 0FFD2h - TA3_0
+; 0FFD4h - I/O Port P2
+; 0FFD6h - TA2_x
+; 0FFD8h - TA2_0
+; 0FFDAh - I/O Port P1
+; 0FFDCh - TA1_x
+; 0FFDEh - TA1_0
+; 0FFE0h - DMA
+; 0FFE2h - eUSCI_B1
+; 0FFE4h - eUSCI_A1
+; 0FFE6h - TA0_x
+; 0FFE8h - TA0_0
+; 0FFEAh - ADC12_B
+; 0FFECh - eUSCI_B0
+; 0FFEEh - eUSCI_A0
+; 0FFF0h - Extended Scan IF
+; 0FFF2h - Watchdog
+; 0FFF4h - TB0_x
+; 0FFF6h - TB0_0
+; 0FFF8h - COMP_E
+; 0FFFAh - userNMI
+; 0FFFCh - sysNMI
+; 0FFFEh - reset
+
+; ----------------------------------------------------------------------
+; EXP430FR6989 Peripheral File Map
+; ----------------------------------------------------------------------
+;SFR_SFR .set 0100h ; Special function
+;PMM_SFR .set 0120h ; PMM
+;FRAM_SFR .set 0140h ; FRAM control
+;CRC16_SFR .set 0150h
+;RAMC_SFR .set 0158h ; RAM controller
+;WDT_A_SFR .set 015Ch ; Watchdog
+;CS_SFR .set 0160h ; Clock System
+;SYS_SFR .set 0180h ; SYS
+;REF_SFR .set 01B0h ; shared REF
+;PA_SFR .set 0200h ; PORT1/2
+;PB_SFR .set 0220h ; PORT3/4
+;PC_SFR .set 0240h ; PORT5/6
+;PD_SFR .set 0260h ; PORT7/8
+;PE_SFR .set 0280h ; PORT9/10
+;PJ_SFR .set 0320h ; PORTJ
+;TA0_SFR .set 0340h
+;TA1_SFR .set 0380h
+;TB0_SFR .set 03C0h
+;TA2_SFR .set 0400h
+;CTIO0_SFR .set 0430h ; Capacitive Touch IO
+;TA3_SFR .set 0440h
+;CTIO1_SFR .set 0470h ; Capacitive Touch IO
+;RTC_C_SFR .set 04A0h
+;MPY_SFR .set 04C0h
+;DMA_CTRL_SFR .set 0500h
+;DMA_CHN0_SFR .set 0510h
+;DMA_CHN1_SFR .set 0520h
+;DMA_CHN2_SFR .set 0530h
+;MPU_SFR .set 05A0h ; memory protect unit
+;eUSCI_A0_SFR .set 05C0h ; eUSCI_A0
+;eUSCI_A1_SFR .set 05E0h ; eUSCI_A1
+;eUSCI_B0_SFR .set 0640h ; eUSCI_B0
+;eUSCI_B1_SFR .set 0680h ; eUSCI_B1
+;ADC12_B_SFR .set 0800h
+;COMP_E_SFR .set 08C0h
+;CRC32_SFR .set 0980h
+;AES_SFR .set 09C0h
+;LCD_SFR .set 0A00h
+;ESI_SFR .set 0D00h
+;ESI_RAM .set 0E00h ; 128 bytes
+
+
+; ============================================
+; FAST FORTH configuration :
+; ============================================
+BUS_TERM=\$30; \ P3.5 = RX, P3.4 = TX
+
+TERM_IN=\$220;
+TERM_REN=\$226;
+TERM_SEL=\$22C; \ SEL0
+
+TERM_VEC=\$FFE4; \ UCA1
+UCSWRST=1; eUSCI Software Reset
+WAKE_UP=1; \ RX int
+RX=1; RX flag IFG
+TX=2; Tx flag IFG
+
+TERM_CTLW0=\$5E0; \ eUSCI_A control word 0
+TERM_CTLW1=\$5E2; \ eUSCI_A control word 1
+TERM_BRW=\$5E6;
+TERM_BR0=\$5E6; \ eUSCI_A baud rate 0
+TERM_BR1=\$5E7; \ eUSCI_A baud rate 1
+TERM_MCTLW=\$5E8; \ eUSCI_A modulation control
+TERM_STAT=\$5EA; \ eUSCI_A status
+TERM_RXBUF=\$5EC; \ eUSCI_A receive buffer
+TERM_TXBUF=\$5EE; \ eUSCI_A transmit buffer
+TERM_ABCTL=\$5F0; \ eUSCI_A LIN control
+TERM_IRTCTL=\$5F2; \ eUSCI_A IrDA transmit control
+TERM_IRRCTL=\$5F3; \ eUSCI_A IrDA receive control
+TERM_IE=\$5FA; \ eUSCI_A interrupt enable
+TERM_IFG=\$5FC; \ eUSCI_A interrupt flags
+TERM_IV=\$5FE; \ eUSCI_A interrupt vector word
+
+RTS=1; ; P3.0
+CTS=2; ; P3.1
+HANDSHAKIN=\$220;
+HANDSHAKOUT=\$222;
+
+CD_SD=\$80; ; P2.7 as Card Detect
+SD_CDIN=\$201;
+
+CS_SD=\$40; ; P2.6 as Card Select
+SD_CSOUT=\$203;
+SD_CSDIR=\$205;
+
+BUS_SD=\$07; ; pins P2.2 as UCB0CLK, P2.0 as UCB0SIMO & P2.1 as UCB0SOMI
+SD_SEL=\$20C; ; to configure UCB0
+SD_REN=\$206; ; to configure pullup resistors
+
+LFXT_OUT=\$322; PJ
+LFXT_DIR=\$324; PJ
+LFXT_SEL=\$32A; PJSEL0
+LFXIN=\$10; PJ.4
+LFXOUT=\$20; PJ.5
+
+; FAST FORTH I/O :
+LED1_OUT=\$202;
+LED1_DIR=\$204;
+LED1=1; P1.0
+LED2_OUT=\$282;
+LED2_DIR=\$287;
+LED2=\$80; P9.7
+
+SW1_IN=\$200;
+SW1=2; P1.1
+SW2_IN=\$200;
+SW2=4; P1.2
+
+; ============================================
+; UARTI2CS APPLICATION
+; ============================================
+;I2C_Soft_Master
+I2CSM_IN=\$200;
+I2CSM_OUT=\$202;
+I2CSM_DIR=\$204;
+I2CSM_REN=\$206;
+SM_SDA=8; P1.3
+SM_SCL=\$20; P1.5
+SM_BUS=\$28;
+
+;500_ms_INT TIMER
+TIM_CTL=\$3C0; TB0
+TIM_CCTL2=\$3C6;
+TIM_CCR0=\$3D2;
+TIM_CCR2=\$3D6;
+T_OUT2=\$40; P3.6 <--- TB0.2
+T_OUT2_DIR=\$224; P3DIR
+T_OUT2_SEL=\$22C; P3SEL1
+INT_IN=\$80; P3.7
+INT_IN_IE=\$23A; P3IE
+INT_IN_IFG=\$23C; P3IFG
+INT_IN_VEC=\$FFCE; P3VEC
+
+;local variables
+UARTI2CS_ADR=\{UARTI2CS\}\+10; <-- I2C_Slave_Addr<<1
+TIMER_CONF=\{UARTI2CS\}\+12; <-- TIM_CTL configuration
+COLLISION_DLY=\{UARTI2CS\}\+14; <-- 20 us resolution delay after I2C collision
+DUPLEX_MODE=\{UARTI2CS\}\+15; <-- flag = 4 --> NOECHO, <> 4 --> ECHO, -1 = I2C link lost
+; ============================================
+; RC5toLCD APPLICATION
+; ============================================
+LCDVo_DIR=\$224;
+LCDVo_SEL=\$22C; SEL1
+LCDVo=\$40; P3.6
+;LCD timer
+LCD_TIM_CTL=\$3C0; TB0CTL
+LCD_TIM_CCTLn=\$3C6; TB0CCTL2
+LCD_TIM_CCR0=\$3D2; TB0CCR0
+LCD_TIM_CCRn=\$3D6; TB0CCR2
+LCD_TIM_EX0=\$3E0; TB0EX0
+;LCD command bus
+LCD_CMD_IN=\$221;
+LCD_CMD_OUT=\$223;
+LCD_CMD_DIR=\$225;
+LCD_CMD_REN=\$227;
+LCD_RS=2; P4.1
+LCD_RW=4; P4.2
+LCD_EN=8; P4.3
+LCD_CMD=\$0E;
+;LCD data bus
+LCD_DB_IN=\$280;
+LCD_DB_OUT=\$282;
+LCD_DB_DIR=\$284;
+LCD_DB_REN=\$286;
+LCD_DB=\$0F; P9.3-0
+;WATCHDOG timer
+WDT_TIM_CTL=\$340; TA0CTL
+WDT_TIM_CCTL0=\$342; TA0CCTL0
+WDT_TIM_CCR0=\$352; TA0CCR0
+WDT_TIM_EX0=\$360; TA0EX0
+WDT_TIM_0_Vec=\$FFE8; TA0_0_Vec
+;IR_RC5
+IR_IN=\$221;
+IR_OUT=\$223;
+IR_DIR=\$225;
+IR_REN=\$227;
+IR_IES=\$239;
+IR_IE=\$23B;
+IR_IFG=\$23D;
+RC5_=RC5_;
+RC5=1; P4.0
+IR_Vec=\$FFCC; P4 int
+; --------------------------------------------
+
+I2CSMM_IN=\$200;
+I2CSMM_OUT=\$202;
+I2CSMM_DIR=\$204;
+I2CSMM_REN=\$206;
+SMM_SDA=8; P1.3
+SMM_SCL=\$20; P1.5
+SMM_BUS=\$28;
+RC5_TIM_CTL=\$380; TA1CTL
+RC5_TIM_R=\$390; TA1R
+RC5_TIM_EX0=\$3A0; TA1EX0
+
+
+I2CMM_IN=\$200;
+I2CMM_OUT=\$202;
+I2CMM_DIR=\$204;
+I2CMM_REN=\$206;
+I2CMM_SEL=\$20A; SEL0
+I2CMM_Vec=\$FFEC; UCBO_Vec
+MM_SDA=\$40; P1.6
+MM_SCL=\$80; P1.7
+MM_BUS=\$C0;
+
+I2CM_IN=\$200;
+I2CM_OUT=\$202;
+I2CM_DIR=\$204;
+I2CM_REN=\$206;
+I2CM_SEL=\$20A; SEL0
+I2CM_Vec=\$FFEC; UCBO_Vec
+M_SDA=\$40; P1.6
+M_SCL=\$80; P1.7
+M_BUS=\$C0;
+
+I2CS_IN=\$200;
+I2CS_OUT=\$202;
+I2CS_DIR=\$204;
+I2CS_REN=\$206;
+I2CS_SEL=\$20A; SEL0
+I2CS_Vec=\$FFEC; UCBO_Vec
+S_SDA=\$40; P1.6
+S_SCL=\$80; P1.7
+S_BUS=\$C0;
+
+I2CM_CTLW0=\$640; USCI_B0 Control Word Register 0
+I2CM_CTLW1=\$642; USCI_B0 Control Word Register 1
+I2CM_BRW=\$646; USCI_B0 Baud Word Rate 0
+I2CM_STATW=\$648; USCI_B0 status word
+I2CM_TBCNT=\$64A; USCI_B0 byte counter threshold
+I2CM_RXBUF=\$64C; USCI_B0 Receive Buffer 8
+I2CM_TXBUF=\$64E; USCI_B0 Transmit Buffer 8
+I2CM_I2COA0=\$654; USCI_B0 I2C Own Address 0
+I2CM_ADDRX=\$65C; USCI_B0 Received Address Register
+I2CM_I2CSA=\$660; USCI_B0 I2C Slave Address
+I2CM_IE=\$66A; USCI_B0 Interrupt Enable
+I2CM_IFG=\$66C; USCI_B0 Interrupt Flags Register
+
+I2CS_CTLW0=\$640; USCI_B0 Control Word Register 0
+I2CS_CTLW1=\$642; USCI_B0 Control Word Register 1
+I2CS_BRW=\$646; USCI_B0 Baud Word Rate 0
+I2CS_STATW=\$648; USCI_B0 status word
+I2CS_TBCNT=\$64A; USCI_B0 byte counter threshold
+I2CS_RXBUF=\$64C; USCI_B0 Receive Buffer 8
+I2CS_TXBUF=\$64E; USCI_B0 Transmit Buffer 8
+I2CS_I2COA0=\$654; USCI_B0 I2C Own Address 0
+I2CS_ADDRX=\$65C; USCI_B0 Received Address Register
+I2CS_I2CSA=\$660; USCI_B0 I2C Slave Address
+I2CS_IE=\$66A; USCI_B0 Interrupt Enable
+I2CS_IFG=\$66C; USCI_B0 Interrupt Flags Register
; TargetInit.asm
; to Init I/O, Clock, FRAM, RTC, ... only for FastForth and SD_options use
.IFDEF MSP_EXP430FR5739
- .include "MSP_EXP430FR5739.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MSP_EXP430FR5739.asm"
.ENDIF
.IFDEF MSP_EXP430FR5969
- .include "MSP_EXP430FR5969.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MSP_EXP430FR5969.asm"
.ENDIF
.IFDEF MSP_EXP430FR5994
- .include "MSP_EXP430FR5994.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MSP_EXP430FR5994.asm"
.ENDIF
.IFDEF MSP_EXP430FR6989
- .INCLUDE "MSP_EXP430FR6989.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .INCLUDE "MSP_EXP430FR6989.asm"
.ENDIF
.IFDEF MSP_EXP430FR4133
- .INCLUDE "MSP_EXP430FR4133.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .INCLUDE "MSP_EXP430FR4133.asm"
.ENDIF
.IFDEF MSP_EXP430FR2433
- .include "MSP_EXP430FR2433.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MSP_EXP430FR2433.asm"
.ENDIF
.IFDEF MSP_EXP430FR2355
- .include "MSP_EXP430FR2355.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MSP_EXP430FR2355.asm"
.ENDIF
.IFDEF LP_MSP430FR2476
- .include "LP_MSP430FR2476.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "LP_MSP430FR2476.asm"
.ENDIF
.IFDEF CHIPSTICK_FR2433
- .include "CHIPSTICK_FR2433.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "CHIPSTICK_FR2433.asm"
.ENDIF
.save
.listing off
;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
.restore
.IFDEF MY_MSP430FR5734
- .include "MY_MSP430FR5734.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5734.asm"
.ENDIF
.IFDEF MY_MSP430FR5738
- .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF MY_MSP430FR5738_1
- .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF MY_MSP430FR5738_2
- .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF MY_MSP430FR5948
- .include "MY_MSP430FR5948.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5948.asm"
.ENDIF
.IFDEF MY_MSP430FR5948_1
- .include "MY_MSP430FR5948_1.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5948_1.asm"
.ENDIF
.IFDEF JMJ_BOX_2021_03_02
- .include "JMJ_BOX_2021_03_02.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "JMJ_BOX_2021_03_02.asm"
.ENDIF
.IFDEF JMJ_BOX_2021_05_04
- .include "JMJ_BOX_2021_05_04.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "JMJ_BOX_2021_05_04.asm"
.ENDIF
.IFDEF JMJ_BOX
- .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF JMJ_BOX_2018_10_29
- .include "JMJ_BOX_2018_10_29.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF JMJ_BOX_2018_08
- .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF JMJ_BOX_GUILLAUME
- .include "MY_MSP430FR5738_2.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF JMJ_BOX_FAVRE
- .include "MY_MSP430FR5738_2.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF PA8_PA_MSP430
- .include "MY_MSP430FR5738_2.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF PA_PA_MSP430
- .include "MY_MSP430FR5738_2.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5738.asm"
.ENDIF
.IFDEF PA_Core_MSP430
- .include "MY_MSP430FR5948_1.asm" ; choose always Px0 to Px3 as RTS pin!!!
+ .include "MY_MSP430FR5948_1.asm"
.ENDIF
; ThingsInFirst.inc
-
- .cpu MSP430X ; define CPU
+ RELAXED ON
BIT0 .equ 1
BIT1 .equ 2
LPM3 .equ SCG1 + SCG0 + CPUOFF
LPM4 .equ SCG1 + SCG0 + OSCOFF + CPUOFF
-;-------------------------------------------------------------------------------
-; DEFINING FORTH REGISTERS - DTC model
-;-------------------------------------------------------------------------------
-RSP .reg R1 ; RSP = Return Stack Pointer (return stack)
-; R2 ; not to be used
-; R3 ; not to be used
-; DOxxx registers ; must be saved before use and restored after use
-rDOCOL .reg R4
-rDODOES .reg r5 ; to restore: MOV #XDODOES,rDODOES
-rDOCON .reg r6 ; to restore: MOV #XDOCON,rDOCON
-rDOVAR .reg r7 ; to restore: MOV #R>,rDOVAR
-; rDOxxx alias
-R .reg r4 ; rDOCOL alias
-Q .reg r5 ; rDODOES alias
-P .reg r6 ; rDOCON alias
-M .reg R7 ; rDOVAR alias
-; Scratch registers
-Y .reg R8
-X .reg R9
-W .reg R10
-T .reg R11
-S .reg R12
-; Forth virtual machine
-IP .reg R13 ; interpretative pointer
-TOS .reg R14 ; first PSP cell
-PSP .reg R15 ; PSP = Parameters Stack Pointer (stack data)
-
-; ----------------------------------------------
-; EXECUTIVE WORDS FOR Direct-Threaded Code (DTC)
-; ----------------------------------------------
-;-------------------------------------------------------------------------------
-; very nice FAST FORTH feature:
-; as IP is always computed from the PC value, we can place low to high level
-; "ASMtoFORTH" or "mDOCOL" switches anywhere in a word, i.e. not only at its
-; beginning as ITC competitors.
-;-------------------------------------------------------------------------------
-DOCOL .equ 1284h ; 1284h = CALL rDOCOL instruction
-DODOES .equ 1285h ; 1285h = CALL rDODOES instruction
-DOCON .equ 1286h ; 1286h = CALL rDOCON instruction
-DOVAR .equ 1287h ; 1287h = CALL rDOVAR instruction
-
-
-
- .SWITCH DTC
-
- .CASE 1 ; DOCOL = CALL rDOCOL, [rDOCOL] = XDOCOL
-mASM2FORTH .MACRO ; compiled by LO2HI
- CALL #EXIT ; 10 cycles
- .ENDM ; 2 words, 10 cycles
- ; LO2HI + HI2LO = 3 words, 10 cycles.
-
-mDOCOL .MACRO ; compiled by : and by colon
- CALL rDOCOL ; 10 [rDOCOL] = XDOCOL
- .ENDM ; 1 word, 14 cycles (CALL included) (ITC+4)
- ; COLON + SEMI = 2 words, 20 cycles (ITC+2)
- .CASE 2 ; DOCOL = PUSH IP + CALL rDOCOL, [rDOCOL] = EXIT
-mASM2FORTH .MACRO ; compiled by LO2HI
- CALL rDOCOL ; 10 [rDOCOL] = EXIT
- .ENDM ; 1 word, 10 cycles.
- ; LO2HI + HI2LO = 2 words, 10 cycles.
-
-mDOCOL .MACRO ; compiled by : and by COLON
- PUSH IP ; 3
- CALL rDOCOL ; 10 [rDOCOL] = EXIT
- .ENDM ; 2 words, 13 cycles (ITC+3)
- ; COLON + SEMI = 3 words, 19 cycles (ITC+1)
- .CASE 3 ; inlined DOCOL
-mASM2FORTH .MACRO ; compiled by LO2HI
- MOV PC,IP ; 1
- ADD #4,IP ; 1
- MOV @IP+,PC ; 4 NEXT
- .ENDM ; 6 cycles, 3 words
- ; LO2HI + HI2LO = 4 words, 6 cycles.
-
-mDOCOL .MACRO ; compiled by : and by COLON
- PUSH IP ; 3
- MOV PC,IP ; 1
- ADD #4,IP ; 1
- MOV @IP+,PC ; 4 NEXT
- .ENDM ; 4 words, 9 cycles (ITC-1)
- ; COLON + SEMI = 5 words, 15 cycles (ITC-3)
- .ENDCASE ; DTC
-
-mNEXTADR .MACRO
- .word $+2
- .ENDM
.save
.listing off
; --------------------------
; COMPUTE BAUDRATE registers = fn(FREQUENCY,BAUDS)
; --------------------------
- .IFNDEF TERMINAL_I2C
+ .IFDEF UART_TERMINAL
.include "TERMINALBAUDRATE.inc"
.ENDIF
;-----------------------------------------------------------------------
FADDON .set 0
.IFDEF MSP_EXP430FR5739
-FADDON .SET FADDON | BIT0 ; hardware MPY
LF_XTAL
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB0_TERM
.ELSE
UCA0_TERM
.ENDIF
-UCA1_SD
.include "MSP430FR5739.inc"
.ENDIF
.IFDEF MSP_EXP430FR5969
-FADDON .SET FADDON | BIT0 ; hardware MPY
;EXTENDED_MEM
LF_XTAL
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB0_TERM
.ELSE
UCA0_TERM
.include "MSP430FR5969.inc"
.ENDIF
.IFDEF MSP_EXP430FR5994
-FADDON .SET FADDON | BIT0 ; hardware MPY
;EXTENDED_MEM
LF_XTAL
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB2_TERM
.ELSE
UCA0_TERM
.include "MSP430FR5994.inc"
.ENDIF
.IFDEF MSP_EXP430FR6989
-FADDON .SET FADDON | BIT0 ; hardware MPY
;EXTENDED_MEM
LF_XTAL
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB0_TERM
.ELSE
UCA1_TERM
.INCLUDE "MSP430FR6989.inc"
.ENDIF
.IFDEF MSP_EXP430FR5972
-FADDON .SET FADDON | BIT0 ; hardware MPY
;EXTENDED_MEM
LF_XTAL
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB0_TERM
.ELSE
UCA1_TERM
.INCLUDE "MSP430FR5972.inc"
.ENDIF
.IFDEF MSP_EXP430FR4133
-FLL
LF_XTAL
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB0_TERM
+UCA0_SD
.ELSE
UCA0_TERM
UCB0_SD
.INCLUDE "MSP430FR4133.inc"
.ENDIF
.IFDEF MSP_EXP430FR2433
-FLL
LF_XTAL
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB0_TERM
.ELSE
UCA0_TERM
.include "MSP430FR2433.inc"
.ENDIF
.IFDEF CHIPSTICK_FR2433
-FLL
; no LF_XTAL to select ACLK = REFOCLK
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB0_TERM
UCA0_SD
.ELSE
.include "MSP430FR2433.inc"
.ENDIF
.IFDEF MSP_EXP430FR2355
-FADDON .SET FADDON | BIT0 ; hardware MPY
-FLL
LF_XTAL
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB0_TERM
.ELSE
UCA1_TERM
.include "MSP430FR2355.inc"
.ENDIF
.IFDEF LP_MSP430FR2476
-FADDON .SET FADDON | BIT0 ; hardware MPY
-FLL
;EXTENDED_MEM
; LF_XTAL ; connect resistors R2=0k, R3=0k before uncomment this line
- .IFDEF TERMINAL_I2C
+ .IFNDEF UART_TERMINAL
UCB1_TERM
.ELSE
UCA0_TERM
; ---------------------------
; compute value of FORTHADDON
; ---------------------------
- .IFDEF FLOORED_DIVISION
-FADDON .SET FADDON | BIT15 ; FLOORED_DIVISION
- .ENDIF
+; .IFDEF FLOORED_DIVISION
+;FADDON .SET FADDON | BIT15 ; FLOORED_DIVISION
+; .ENDIF
.IFDEF LF_XTAL
FADDON .SET FADDON | BIT14 ; LFXTAL = 32768 Hz
.ENDIF
- .IFNDEF TERMINAL_I2C ; if TERMINAL UART...
+ .IFDEF UART_TERMINAL ; if TERMINAL UART...
.IFDEF TERMINAL5WIRES
FADDON .SET FADDON | BIT13 ; UART CTS
.ENDIF
.ENDIF
.ENDIF ; TERMINAL UART
; ---------------------------
- .IFDEF TERMINAL_I2C
-FADDON .SET FADDON | BIT9 ;I2C TERMINAL
+ .IFNDEF UART_TERMINAL
+FADDON .SET FADDON | BIT9 ; I2C TERMINAL
.ENDIF
.IFDEF FIXPOINT_INPUT
FADDON .SET FADDON | BIT8 ; Q15.16 INPUT
FADDON .SET FADDON | BIT4 ; Assembler 16 bits with Address access beyond $FFFF
.ENDIF
.ENDIF
+ .IFDEF HMPY ; see device.inc
+FADDON .SET FADDON | BIT3 ; hardware MPY
+ .ENDIF
+; ---------------------------
+; BIT2 to BIT0 are free
; ---------------------------
-; .IFDEF VOCABULARY_SET ;
-;FADDON .SET FADDON | BIT3 ; vocabulary set
-; .ENDIF ; BIT2 to BIT0 are free
-
;-------------------------------------------------------------------------------
;---------------------------;---------
; name words ; comment
-;---------------------------;---------
+;------------------=====----;---------
;LSTACK = L0 = LEAVEPTR ; ----- RAM_ORG
; |
LSTACK_LEN .equ 16 ; | grows up
;---------------------------;---------
; names bytes ; comments
-;---------------------------;---------
+;------------------=====----;---------
; PAD_I2CADR ; ----- RAM_ORG + $E0
; PAD_I2CCNT ;
; PAD < ----- RAM_ORG + $E4
;
; system variables
;
- ; ----- RAM_ORG + $1E0
+; LAST_NFA ; ----- RAM_ORG + $1D8 : Forth compiler variables
;
- ; 28 bytes free
+ ; 36 free bytes
;
; SD_BUF_I2CADR < ----- RAM_ORG + $1FC
; SD_BUF_I2CCNT ;
; ----------------------------------------------------
; RAM_ORG + $1B2 : RAM VARIABLES
; ----------------------------------------------------
+; FORTH interpreter
+; ----------------------------------------------------
HP .equ HOLD_BASE ; HOLD ptr
+STATE .equ HOLD_BASE+2 ; Interpreter state
+BASEADR .equ HOLD_BASE+4 ; BASE
+CAPS .equ HOLD_BASE+6 ; CAPS
+SOURCE .equ HOLD_BASE+8 ; len, org of input stream
+SOURCE_LEN .equ HOLD_BASE+8 ;
+SOURCE_ORG .equ HOLD_BASE+10 ;
+TOIN .equ HOLD_BASE+12 ; CurrentInputBuffer pointer
; ----------------------------------------------------
-; new definition pointers, generated by HEADER
+; FORTH environment
; ----------------------------------------------------
-LAST_NFA .equ HOLD_BASE+2 ; used by REVEAL, IMMEDIATE
-LAST_THREAD .equ HOLD_BASE+4 ; " REVEAL
-LAST_CFA .equ HOLD_BASE+6 ; " DOES>, RECURSE
-LAST_PSP .equ HOLD_BASE+8 ; " REVEAL
+DP .equ HOLD_BASE+14 ; dictionnary pointer
+LASTVOC .equ HOLD_BASE+16 ;
+CURRENT .equ HOLD_BASE+18 ;
+CONTEXT .equ HOLD_BASE+20 ; 8 words of depth ending
+NULL_WORD .equ HOLD_BASE+36 ; with a null word in addition
; ----------------------------------------------------
-; FORTH interpreter variables
+; FORTH compiler
; ----------------------------------------------------
-STATE .equ HOLD_BASE+10 ; Interpreter state
-BASEADR .equ HOLD_BASE+12 ; BASE
-CAPS .equ HOLD_BASE+14 ; CAPS
+; RAM_ORG + $1D8 : can be shared with APPLICATION needs
; ----------------------------------------------------
-SOURCE .equ HOLD_BASE+16 ; len, org of input stream
-SOURCE_LEN .equ HOLD_BASE+16 ;
-SOURCE_ORG .equ HOLD_BASE+18 ;
-TOIN .equ HOLD_BASE+20 ; CurrentInputBuffer pointer
+LAST_NFA .equ HOLD_BASE+38 ; used by REVEAL, IMMEDIATE
+LAST_THREAD .equ HOLD_BASE+40 ; " REVEAL
+LAST_CFA .equ HOLD_BASE+42 ; " DOES>, RECURSE
+LAST_PSP .equ HOLD_BASE+44 ; " REVEAL
+ASMBW1 .equ HOLD_BASE+46 ;
+ASMBW2 .equ HOLD_BASE+48 ;
+ASMBW3 .equ HOLD_BASE+50 ;
+ASMFW1 .equ HOLD_BASE+52 ;
+ASMFW2 .equ HOLD_BASE+54 ;
+ASMFW3 .equ HOLD_BASE+56 ;
; ----------------------------------------------------
-; FORTH environment
+; RAM_ORG + $1EC : free RAM area
; ----------------------------------------------------
-DP .equ HOLD_BASE+22 ; dictionnary pointer
-LASTVOC .equ HOLD_BASE+24 ;
-CURRENT .equ HOLD_BASE+26 ;
-CONTEXT .equ HOLD_BASE+28 ; 8 words of depth ending
-NULL_WORD .equ HOLD_BASE+44 ; with a null word in addition
-; ----------------------------------;
.IFDEF SD_CARD_LOADER
; --------------------------------------------------
; ---------------------------------------
; FAT FileSystemInfos
; ---------------------------------------
-;FATtype .equ SD_ORG+0
+FATtype .equ SD_ORG+0
BS_FirstSectorL .equ SD_ORG+2 ; init by SD_Init, used by RW_Sector_CMD
BS_FirstSectorH .equ SD_ORG+4 ; init by SD_Init, used by RW_Sector_CMD
OrgFAT1 .equ SD_ORG+6 ; init by SD_Init,
FATSize .equ SD_ORG+8 ; init by SD_Init,
OrgFAT2 .equ SD_ORG+10 ; init by SD_Init,
-;OrgRootDIR .equ SD_ORG+12 ; init by SD_Init,
-OrgClusters .equ SD_ORG+14 ; init by SD_Init, Sector of Cluster 0
+OrgRootDIR .equ SD_ORG+12 ; init by SD_Init, Org Sector of RootDIR
+OrgClusters .equ SD_ORG+14 ; init by SD_Init, Org Sector of Cluster 0
SecPerClus .equ SD_ORG+16 ; init by SD_Init, byte size
; ---------------------------------------
; SD command
LastFAToffset .equ SD_FAT_LEVEL+6 ;
FATsector .equ SD_FAT_LEVEL+8 ; not used
; ---------------------------------------
-; DIR entry
+; DIR entry (RootDIR excluded)
; ---------------------------------------
-DIRClusterL .equ SD_FAT_LEVEL+10 ; contains the Cluster of current directory ; = 1 as FAT16 root directory
-DIRClusterH .equ SD_FAT_LEVEL+12 ; contains the Cluster of current directory ; = 1 as FAT16 root directory
+DIRClusterL .equ SD_FAT_LEVEL+10 ; contains the Cluster of current directory ; = 0 for root directory
+DIRClusterH .equ SD_FAT_LEVEL+12 ; contains the Cluster of current directory ; = 0 for root directory
DIREntryOfst .equ SD_FAT_LEVEL+14
; ---------------------------------------
; Handle Pointer
SD_LEN .equ SD_END-SD_ORG
.ENDIF ; SD_CARD_LOADER
+ .cpu MSP430X ; define CPU
+
+
+;-------------------------------------------------------------------------------
+; DEFINING FORTH REGISTERS - DTC model
+;-------------------------------------------------------------------------------
+RSP .reg R1 ; RSP = Return Stack Pointer (return stack)
+; R2 ; not to be used
+; R3 ; not to be used
+; DOxxx registers ; must be saved before use and restored after use
+rDOCOL .reg R4
+rDODOES .reg r5 ; to restore: MOV #XDODOES,rDODOES
+rDOCON .reg r6 ; to restore: MOV #XDOCON,rDOCON
+rDOVAR .reg r7 ; to restore: MOV #R>,rDOVAR
+; rDOxxx alias
+R .reg r4 ; rDOCOL alias
+Q .reg r5 ; rDODOES alias
+P .reg r6 ; rDOCON alias
+M .reg R7 ; rDOVAR alias
+; Scratch registers
+Y .reg R8
+X .reg R9
+W .reg R10
+T .reg R11
+S .reg R12
+; Forth virtual machine
+IP .reg R13 ; interpretative pointer
+TOS .reg R14 ; first PSP cell
+PSP .reg R15 ; PSP = Parameters Stack Pointer (stack data)
+
+; ----------------------------------------------
+; EXECUTIVE WORDS FOR Direct-Threaded Code (DTC)
+; ----------------------------------------------
+;-------------------------------------------------------------------------------
+; very nice FAST FORTH feature:
+; as IP is always computed from the PC value, we can place low to high level
+; "ASMtoFORTH" or "mDOCOL" switches anywhere in a word, i.e. not only at its
+; beginning as ITC competitors.
+;-------------------------------------------------------------------------------
+DOCOL .equ 1284h ; 1284h = CALL rDOCOL instruction
+DODOES .equ 1285h ; 1285h = CALL rDODOES instruction
+DOCON .equ 1286h ; 1286h = CALL rDOCON instruction
+DOVAR .equ 1287h ; 1287h = CALL rDOVAR instruction
+
+ .SWITCH DTC
+
+ .CASE 1 ; DOCOL = CALL rDOCOL, [rDOCOL] = XDOCOL
+mASM2FORTH .MACRO ; compiled by LO2HI
+ CALL #EXIT ; 10 cycles
+ .ENDM ; 2 words, 10 cycles. LO2HI + HI2LO = 3 words, 10 cycles.
+
+mDOCOL .MACRO ; compiled by : and by colon
+ CALL rDOCOL ; 10 [rDOCOL] = XDOCOL
+ .ENDM ; 1 word, 14 cycles (CALL included) (ITC+4). COLON + SEMI = 2 words, 20 cycles (ITC+2)
+
+ .CASE 2 ; DOCOL = PUSH IP + CALL rDOCOL, [rDOCOL] = EXIT
+mASM2FORTH .MACRO ; compiled by LO2HI
+ CALL rDOCOL ; 10 [rDOCOL] = EXIT
+ .ENDM ; 1 word, 10 cycles. LO2HI + HI2LO = 2 words, 10 cycles.
+
+mDOCOL .MACRO ; compiled by : and by COLON
+ PUSH IP ; 3
+ CALL rDOCOL ; 10 [rDOCOL] = EXIT
+ .ENDM ; 2 words, 13 cycles (ITC+3). COLON + SEMI = 3 words, 19 cycles (ITC+1)
+
+ .CASE 3 ; inlined DOCOL
+mASM2FORTH .MACRO ; compiled by LO2HI
+ MOV PC,IP ; 1
+ ADD #4,IP ; 1
+ MOV @IP+,PC ; 4 NEXT
+ .ENDM ; 3 words, 6 cycles. LO2HI + HI2LO = 4 words, 6 cycles.
+
+mDOCOL .MACRO ; compiled by : and by COLON
+ PUSH IP ; 3
+ MOV PC,IP ; 1
+ ADD #4,IP ; 1
+ MOV @IP+,PC ; 4 NEXT
+ .ENDM ; 4 words, 9 cycles (ITC-1). COLON + SEMI = 5 words, 15 cycles (ITC-3)
+
+ .ENDCASE ; DTC
+
+mNEXTADR .MACRO
+ .word $+2
+ .ENDM
+
.org INFO_ORG
;-------------------------------------------------------------------------------
; INFO(DCBA) >= 256 bytes memory map (FRAM) :
; FRAM INFO: KERNEL INIT CONSTANTS and VARIABLES
; ----------------------------------------------
FREQ_KHZ .word FREQUENCY*1000 ; used to stabilize MCLK before start, see MSP430FRxxxx.asm
- .IFDEF TERMINAL_I2C
-I2CSLAVEADR .word MYSLAVEADR ; on MSP430FR2xxx devices with BSL I2C, Slave address is FFA0h
+ .IFNDEF UART_TERMINAL
+I2CSLAVEADR .word I2C_TERM_ADR ; on MSP430FR2xxx devices with BSL I2C, Slave address is FFA0h
I2CSLAVEADR1 .word 0
LPM_MODE .word GIE+LPM4 ; LPM4 is the default mode for I2C TERMINAL
.ELSE ; TERMINAL_UART
-TERMBRW_RST .word TERMBRW_INI ; set by TERMINALBAUDRATE.inc
-TERMMCTLW_RST .word TERMMCTLW_INI ; set by TERMINALBAUDRATE.inc
+TERMBRW_RST .word TERMBRW_INI ; set by UART_TERMINAL.inc
+TERMMCTLW_RST .word TERMMCTLW_INI ; set by UART_TERMINAL.inc
LPM_MODE .word GIE+LPM0 ; LPM0 is the default mode for UART TERMINAL
.ENDIF
USERSYS .word -3 ; RESET use, value = -3 when compiling new kernel
; --------------------------------------;
DEEP_TERM_VEC .word TERMINAL_INT ; MOV @X+,&TERM_VEC ; TERMINAL_INT --> FRAM TERM_VEC
.IFNDEF SD_CARD_LOADER
-DEEP_COLD .word COLD_TERM ; MOV @X+,&COLD_APP ; COLD_TERM --> FRAM COLD_APP
-DEEP_SOFT .word INIT_SOFT_TERM ; MOV @X+,&SOFT_APP ; INIT_SOFT_TERM --> FRAM SOFT_APP
+DEEP_STOP .word INIT_STOP ; MOV @X+,&STOP_APP ; INIT_STOP --> FRAM STOP_APP
+DEEP_SOFT .word INIT_SOFT ; MOV @X+,&SOFT_APP ; INIT_SOFT_TERM --> FRAM SOFT_APP
DEEP_HARD .word INIT_TERM ; MOV @X+,&HARD_APP ; INIT_TERM --> FRAM HARD_APP
-DEEP_SLEEP .word RXON ; MOV @X+,&SLEEP_APP ; RXON --> FRAM SLEEP_APP
+DEEP_SLEEP .word INIT_BACKGRND ; MOV @X+,&BACKGRND_APP ; INIT_BACKGRND --> FRAM BACKGRND_APP
.ELSE
-DEEP_COLD .word COLD_TERM ; MOV @X+,&COLD_APP ; COLD_TERM --> FRAM COLD_APP
+DEEP_STOP .word INIT_STOP ; MOV @X+,&STOP_APP ; INIT_STOP --> FRAM STOP_APP
DEEP_SOFT .word INIT_SOFT_SD ; MOV @X+,&SOFT_APP ; INIT_SOFT_SD --> FRAM SOFT_APP
DEEP_HARD .word INIT_HARD_SD ; MOV @X+,&HARD_APP ; INIT_HARD_SD --> FRAM HARD_APP
-DEEP_SLEEP .word RXON ; MOV @X+,&SLEEP_APP ; RXON --> FRAM SLEEP_APP
+DEEP_SLEEP .word INIT_BACKGRND ; MOV @X+,&BACKGRND_APP ; INIT_BACKGRND --> FRAM BACKGRND_APP
.ENDIF
DEEP_DP .word ROMDICT ; MOV @X+,&RST_DP ; DEEP_DP --> FRAM RST_DP
DEEP_LASTVOC .word lastvoclink ; MOV @X+,&RST_LASTVOC ; DEEP_LASTVOC --> FRAM RST_LASTVOC
INIT_BASE .word 10 ; MOV @X+,&BASE ; INIT_BASE --> RAM BASE
INIT_LEAVE .word LSTACK ; MOV @X+,&LEAVEPTR ; INIT_LEAVE --> RAM LEAVEPTR
; --------------------------------------;
-; FRAM RST values initialised by -1 SYS ;
+; FRAM RST values initialised by -1 SYS ; from DEEP_ORG+2
; --------------------------------------;
RST_ORG ; make room for RST values of:
RST_LEN .equ 16 ; 16 bytes
; --------------------------------------;
.IFNDEF SD_CARD_LOADER
-COLD_APP .word COLD_TERM ; COLD_APP
-SOFT_APP .word INIT_SOFT_TERM ; SOFT_APP
+STOP_APP .word INIT_STOP ; STOP_APP
+SOFT_APP .word INIT_SOFT ; SOFT_APP
HARD_APP .word INIT_TERM ; HARD_APP
-SLEEP_APP .word RXON ; SLEEP_APP
+BACKGRND_APP .word INIT_BACKGRND ; BACKGRND_APP
.ELSE
-COLD_APP .word COLD_TERM ; COLD_APP
+STOP_APP .word INIT_STOP ; STOP_APP
SOFT_APP .word INIT_SOFT_SD ; SOFT_APP
HARD_APP .word INIT_HARD_SD ; HARD_APP
-SLEEP_APP .word RXON ; SLEEP_APP
+BACKGRND_APP .word INIT_BACKGRND ; BACKGRND_APP
.ENDIF
-; --------------------------------------;
RST_DP .word ROMDICT ; program memory pointer
-; --------------------------------------;
RST_LASTVOC .word lastvoclink ; last vocabulary link
-; --------------------------------------;
RST_CURRENT .word BODYFORTH ; CURRENT word-set ptr
-; --------------------------------------;
RST_CONTEXT .word BODYFORTH ; CONTEXT space (8 CELLS)
.word 0
.word 0
; --------------------------;
; INFO_ORG + $5A : free use ;
-; --------------------------;
\ No newline at end of file
+; --------------------------;
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