reproduce target env stub code added.

diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd
index 0b69795..fb55117 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.vhd
+++ b/de0_cv_nes/de0_cv_nes.vhd
@@ -115,7 +115,7 @@ architecture rtl of de0_cv_nes is
     end component;
 
     component ram\r
-        generic (abus_size : integer := 16; dbus_size : integer := 8);\r
+        generic (abus_size : integer := 16; dbus_size : integer := 8; debug_mem : string := "null-file.bin");\r
         port (\r
                 pi_base_clk     : in std_logic;\r
                 pi_ce_n         : in std_logic;\r
@@ -327,7 +327,7 @@ begin
 \r
     --cpu ram inst.\r
     cpu_ram_inst : ram generic map\r
-        (ram_2k, 8) port map (\r
+        (ram_2k, 8, "mem-before-02b1000000000000.bin") port map (\r
             pi_base_clk,\r
             wr_ram_ce_n,\r
             wr_oe_n,\r

diff --git a/de0_cv_nes/mem/ram.vhd b/de0_cv_nes/mem/ram.vhd
index 594fdfb..70637ed 100644 (file)
--- a/de0_cv_nes/mem/ram.vhd
+++ b/de0_cv_nes/mem/ram.vhd
@@ -9,7 +9,7 @@ use ieee.std_logic_unsigned.conv_integer;
 
 ----SRAM syncronous memory.
 entity ram is
-    generic (abus_size : integer := 16; dbus_size : integer := 8);
+    generic (abus_size : integer := 16; dbus_size : integer := 8; debug_mem : string := "null-file.bin");
     port (
             pi_base_clk     : in std_logic;
             pi_ce_n         : in std_logic;
@@ -25,8 +25,31 @@ architecture rtl of ram is
 subtype ram_data is std_logic_vector (dbus_size -1 downto 0);
 type ram_array is array (0 to 2**abus_size - 1) of ram_data;
 
+function ram_fill return ram_array is 
+use ieee.std_logic_arith.conv_std_logic_vector;
+type binary_file is file of character;
+FILE bin_file : binary_file OPEN read_mode IS debug_mem;
+variable read_data : character;
+variable i : integer;
+variable ret : ram_array;
+begin
+    if (debug_mem = "null-file.bin") then
+        for i in ret'range loop
+            ret(i) := (others => '0');
+        end loop;
+    else
+        for i in ret'range loop
+            read(bin_file, read_data);
+            ret(i) :=
+                conv_std_logic_vector(character'pos(read_data), 8);
+        end loop;
+    end if;
+    return ret;
+end ram_fill;
+
+
 ---ram is initialized with 0.
-signal work_ram : ram_array := (others => (others => '0'));
+signal work_ram : ram_array := ram_fill;
 
 begin
     p_write : process (pi_base_clk)
@@ -74,7 +97,7 @@ end palette_ram;
 
 architecture rtl of palette_ram is
 component ram
-    generic (abus_size : integer := 16; dbus_size : integer := 8);
+    generic (abus_size : integer := 16; dbus_size : integer := 8; debug_mem : string := "null-file.bin");
     port (
             pi_base_clk     : in std_logic;
             pi_ce_n         : in std_logic;

diff --git a/de0_cv_nes/mos6502.vhd b/de0_cv_nes/mos6502.vhd
index 574c33a..07fc5b0 100644 (file)
--- a/de0_cv_nes/mos6502.vhd
+++ b/de0_cv_nes/mos6502.vhd
@@ -238,12 +238,37 @@ signal reg_dma_set      : integer range 0 to 1;
 --debug purpose...\r
 signal reg_exc_cnt          : std_logic_vector (63 downto 0);\r
 \r
+--constant INIT_ACC       : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_X         : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_Y         : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_SP        : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_STATUS    : std_logic_vector (7 downto 0) := "00100000";\r
+--constant INIT_PCL       : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_PCH       : std_logic_vector (7 downto 0) := "00000000";\r
+--constant INIT_EXC_CNT   : std_logic_vector (63 downto 0) := conv_std_logic_vector(16#0#, 64);\r
+\r
+constant INIT_ACC       : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#91#, 8);\r
+constant INIT_X         : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#0d#, 8);\r
+constant INIT_Y         : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#1d#, 8);\r
+constant INIT_SP        : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#fc#, 8);\r
+constant INIT_STATUS    : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#a5#, 8);\r
+constant INIT_PCL       : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#82#, 8);\r
+constant INIT_PCH       : std_logic_vector (7 downto 0) := conv_std_logic_vector(16#80#, 8);\r
+constant INIT_EXC_CNT   : std_logic_vector (63 downto 0) := conv_std_logic_vector(16#02b1#, 16) & conv_std_logic_vector(0, 48);\r
+\r
+constant DEBUG_SW       : integer := 1;\r
+\r
 begin\r
     --state transition process...\r
     set_stat_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
         if (pi_rst_n = '0') then\r
-            reg_main_state <= ST_RS_T0;\r
+            if (DEBUG_SW = 0) then\r
+                reg_main_state <= ST_RS_T0;\r
+            else\r
+                --for test....\r
+                reg_main_state <= ST_NM_T1;\r
+            end if;\r
             reg_sub_state <= ST_SUB00;\r
         elsif (rising_edge(pi_base_clk)) then\r
             reg_main_state <= reg_main_next_state;\r
@@ -336,7 +361,12 @@ begin
             -----idle...\r
             when ST_IDLE =>\r
                 if (pi_rst_n = '0') then\r
-                    reg_main_next_state <= ST_RS_T0;\r
+                    if (DEBUG_SW = 0) then\r
+                        reg_main_next_state <= ST_RS_T0;\r
+                    else\r
+                        --for test....\r
+                        reg_main_next_state <= ST_NM_T1;\r
+                    end if;\r
                 elsif (reg_sub_state = ST_SUB73 and reg_dma_set = 1 and pi_rdy = '1') then\r
                     --ST_CM_T0 is canceled when dma initiated.\r
                     --redo ST_CM_T0.\r
@@ -1114,8 +1144,8 @@ end;
 \r
     begin\r
         if (pi_rst_n = '0') then\r
-            reg_pc_l    <= (others => '0');\r
-            reg_pc_h    <= (others => '0');\r
+            reg_pc_l    <= INIT_PCL;\r
+            reg_pc_h    <= INIT_PCH;\r
             reg_inst    <= (others => '0');\r
             reg_addr    <= (others => 'Z');\r
             reg_d_out   <= (others => 'Z');\r
@@ -1793,7 +1823,7 @@ end;
     sp_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
         if (pi_rst_n = '0') then\r
-            reg_sp <= (others => '0');\r
+            reg_sp <= INIT_SP;\r
         elsif (rising_edge(pi_base_clk)) then\r
             if (reg_main_state = ST_A1_T1) then\r
                 --txs inst.\r
@@ -1871,10 +1901,10 @@ end;
     begin\r
         --Most instructions that explicitly reference memory locations have bit patterns of the form aaabbbcc.\r
         if (pi_rst_n = '0') then\r
-            reg_acc <= (others => '0');\r
-            reg_x <= (others => '0');\r
-            reg_y <= (others => '0');\r
-            reg_status <= "00100000";\r
+            reg_acc <= INIT_ACC;\r
+            reg_x <= INIT_X;\r
+            reg_y <= INIT_Y;\r
+            reg_status <= INIT_STATUS;\r
             reg_tmp_carry <= '0';\r
             reg_tmp_ovf <= '0';\r
             reg_tmp_condition <= '0';\r
@@ -2392,7 +2422,7 @@ end;
     exc_cnt_p : process (pi_rst_n, pi_base_clk)\r
     begin\r
         if (pi_rst_n = '0') then\r
-            reg_exc_cnt <= (others => '0');\r
+            reg_exc_cnt <= INIT_EXC_CNT;\r
         else\r
             if (rising_edge(pi_base_clk)) then\r
                 if (reg_main_state = ST_CM_T0 and reg_sub_state = ST_SUB73) then\r

diff --git a/de0_cv_nes/ppu/render.vhd b/de0_cv_nes/ppu/render.vhd
index 68085df..d5b27d3 100644 (file)
--- a/de0_cv_nes/ppu/render.vhd
+++ b/de0_cv_nes/ppu/render.vhd
@@ -56,7 +56,7 @@ architecture rtl of render is
 \r
 --secondary oam ram.\r
 component ram\r
-    generic (abus_size : integer := 16; dbus_size : integer := 8);\r
+    generic (abus_size : integer := 16; dbus_size : integer := 8; debug_mem : string := "null-file.bin");\r
     port (\r
             pi_base_clk     : in std_logic;\r
             pi_ce_n         : in std_logic;\r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index 4aa1b1a..93e9fb1 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -52,7 +52,7 @@ add wave -label reg_sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/
 add wave -label reg_status -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_status;\r
 \r
 #add wave -divider internal_reg\r
-#add wave -label reg_main_cur_state  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_main_state;\r
+add wave -label reg_main_cur_state  sim:/testbench_motones_sim/sim_board/cpu_inst/reg_main_state;\r
 ##add wave -label reg_sub_cur_state   sim:/testbench_motones_sim/sim_board/cpu_inst/reg_sub_state;\r
 #add wave -label reg_pc_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_pc_l;\r
 #add wave -label reg_pc_h -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/reg_pc_h;\r