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astoria-d [Sun, 10 Jan 2016 07:48:43 +0000 (16:48 +0900)]
regression make file update
astoria-d [Sun, 10 Jan 2016 07:36:58 +0000 (16:36 +0900)]
regression test update
astoria-d [Sun, 10 Jan 2016 06:42:40 +0000 (15:42 +0900)]
dir changed
astoria-d [Sun, 10 Jan 2016 06:40:50 +0000 (15:40 +0900)]
doc dir changed
astoria-d [Sun, 10 Jan 2016 06:38:36 +0000 (15:38 +0900)]
mos 6500 docs added
astoria-d [Sat, 9 Jan 2016 13:50:04 +0000 (22:50 +0900)]
test image update
astoria-d [Sat, 9 Jan 2016 13:47:53 +0000 (22:47 +0900)]
update regression test image
astoria-d [Sun, 3 Jan 2016 02:36:36 +0000 (11:36 +0900)]
image replaced
astoria-d [Sun, 3 Jan 2016 02:34:53 +0000 (11:34 +0900)]
remove pll
astoria-d [Sun, 3 Jan 2016 02:34:37 +0000 (11:34 +0900)]
project file updated
astoria-d [Sun, 3 Jan 2016 01:51:49 +0000 (10:51 +0900)]
latest ver
astoria-d [Sun, 3 Jan 2016 01:37:34 +0000 (10:37 +0900)]
update
astoria-d [Sun, 3 Jan 2016 01:34:09 +0000 (10:34 +0900)]
renamed
astoria-d [Sun, 3 Jan 2016 01:31:41 +0000 (10:31 +0900)]
update
astoria-d [Sun, 3 Jan 2016 01:31:23 +0000 (10:31 +0900)]
clean up
astoria-d [Sun, 3 Jan 2016 01:27:24 +0000 (10:27 +0900)]
dd script update
astoria-d [Sun, 3 Jan 2016 01:23:25 +0000 (10:23 +0900)]
image test added
astoria-d [Sun, 3 Jan 2016 01:16:43 +0000 (10:16 +0900)]
moved file
astoria-d [Sun, 3 Jan 2016 01:16:26 +0000 (10:16 +0900)]
moved file
astoria-d [Sun, 3 Jan 2016 01:13:37 +0000 (10:13 +0900)]
image create script update
astoria-d [Sun, 3 Jan 2016 01:09:56 +0000 (10:09 +0900)]
change for ld65 ver up
astoria-d [Tue, 29 Dec 2015 15:15:22 +0000 (00:15 +0900)]
change
astoria-d [Tue, 29 Dec 2015 14:11:34 +0000 (23:11 +0900)]
more test
astoria-d [Tue, 29 Dec 2015 14:04:42 +0000 (23:04 +0900)]
Merge branch 'master' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga
Conflicts:
.gitignore
astoria-d [Tue, 29 Dec 2015 13:59:51 +0000 (22:59 +0900)]
merged from ppu test branch
astoria-d@office-vm [Thu, 5 Mar 2015 02:35:08 +0000 (11:35 +0900)]
added vga-tools to the main branch
astoria-d [Thu, 5 Mar 2015 01:59:31 +0000 (10:59 +0900)]
gtkwave init script added.
astoria-d@office-vm [Mon, 23 Feb 2015 04:56:59 +0000 (13:56 +0900)]
sprite test code removed to reduce test time
astoria-d@office-vm [Mon, 23 Feb 2015 03:00:02 +0000 (12:00 +0900)]
aligned test app with vhdl test.
astoria-d@office-vm [Mon, 19 Jan 2015 09:56:03 +0000 (18:56 +0900)]
minimum ppu test case added.
astoria-d@office-vm [Thu, 15 Jan 2015 09:47:37 +0000 (18:47 +0900)]
sprite display test code added.
astoria-d@office-vm [Thu, 15 Jan 2015 09:00:15 +0000 (18:00 +0900)]
gtk2-devel memo also added.
astoria-d@office-vm [Thu, 15 Jan 2015 08:58:07 +0000 (17:58 +0900)]
cc65 memo added.
astoria-d@office-vm [Thu, 15 Jan 2015 08:53:11 +0000 (17:53 +0900)]
vga-tool is obsolete. removed.
astoria-d [Thu, 15 Jan 2015 07:08:40 +0000 (16:08 +0900)]
renamed test-image
unknown [Mon, 5 Jan 2015 09:02:08 +0000 (18:02 +0900)]
Merge remote-tracking branch 'origin/simple-reg'
unknown [Mon, 5 Jan 2015 08:34:26 +0000 (17:34 +0900)]
environment adjustments
unknown [Mon, 5 Jan 2015 07:51:52 +0000 (16:51 +0900)]
add documents
unknown [Mon, 5 Jan 2015 04:20:02 +0000 (13:20 +0900)]
test2
unknown [Mon, 5 Jan 2015 04:18:22 +0000 (13:18 +0900)]
test from hp
astoria-d [Wed, 9 Jul 2014 04:51:59 +0000 (13:51 +0900)]
clean up
astoria-d [Tue, 8 Jul 2014 02:31:39 +0000 (11:31 +0900)]
clean up.
some write bug remains, but move forward at this moment...
astoria-d [Wed, 9 Apr 2014 03:07:10 +0000 (12:07 +0900)]
test full 8MB memory.
astoria-d [Fri, 14 Feb 2014 10:32:16 +0000 (19:32 +0900)]
sdram controller OK!!
astoria-d [Fri, 14 Feb 2014 06:34:58 +0000 (15:34 +0900)]
sdram sigtrap2 ok???
astoria-d [Fri, 14 Feb 2014 04:26:01 +0000 (13:26 +0900)]
signal trap ii working...
astoria-d [Fri, 14 Feb 2014 04:09:12 +0000 (13:09 +0900)]
signal trap ii testing...
astoria-d [Thu, 13 Feb 2014 08:56:00 +0000 (17:56 +0900)]
sdram test >> failed...
astoria-d [Thu, 13 Feb 2014 08:19:12 +0000 (17:19 +0900)]
fifo adjustment
astoria-d [Thu, 13 Feb 2014 05:02:54 +0000 (14:02 +0900)]
fifo timing adjustment
astoria-d [Wed, 12 Feb 2014 09:52:54 +0000 (18:52 +0900)]
sdram fifo ready
astoria-d [Wed, 12 Feb 2014 07:14:53 +0000 (16:14 +0900)]
fifo seemingly ok...
astoria-d [Mon, 10 Feb 2014 09:52:27 +0000 (18:52 +0900)]
still working...
astoria-d [Mon, 10 Feb 2014 06:17:19 +0000 (15:17 +0900)]
update
astoria-d [Mon, 10 Feb 2014 04:37:15 +0000 (13:37 +0900)]
change the order again...
astoria-d [Mon, 10 Feb 2014 03:41:46 +0000 (12:41 +0900)]
compile order modified. this is the root cause of the incorrect output??
astoria-d [Mon, 10 Feb 2014 03:12:15 +0000 (12:12 +0900)]
more updates
astoria-d [Mon, 10 Feb 2014 01:31:03 +0000 (10:31 +0900)]
update/fix.
astoria-d [Thu, 2 Jan 2014 10:14:57 +0000 (19:14 +0900)]
restored again due to the stupid compiler!!
astoria-d [Thu, 2 Jan 2014 09:56:25 +0000 (18:56 +0900)]
simulation result broken by the unknown reason..., restored some of the codes.
astoria-d [Thu, 2 Jan 2014 09:42:53 +0000 (18:42 +0900)]
state machine improved
astoria-d [Mon, 23 Dec 2013 04:06:43 +0000 (13:06 +0900)]
sdram io working..
astoria-d [Fri, 20 Dec 2013 08:30:24 +0000 (17:30 +0900)]
- vga sdram access working
- fifo buffer introduced.
astoria-d [Mon, 16 Dec 2013 09:43:46 +0000 (18:43 +0900)]
- signal trap 2 file added
- VGA controller working...
astoria-d [Tue, 3 Dec 2013 06:16:05 +0000 (15:16 +0900)]
update
astoria-d [Thu, 28 Nov 2013 06:19:52 +0000 (15:19 +0900)]
simulation minimum interval changed due to pll simulation
astoria-d [Thu, 28 Nov 2013 05:56:33 +0000 (14:56 +0900)]
- merged latest render module
- render pos timing updated
astoria-d [Fri, 22 Nov 2013 04:33:47 +0000 (13:33 +0900)]
sdram & vga integrated, not displayed though....
astoria-d [Fri, 22 Nov 2013 04:26:47 +0000 (13:26 +0900)]
pll lock signal added
pll frequency changed to 166.666
astoria-d [Fri, 22 Nov 2013 03:29:05 +0000 (12:29 +0900)]
sdram clk singal change
astoria-d [Sat, 9 Nov 2013 23:28:17 +0000 (08:28 +0900)]
page crossing branch instruction supported!!
astoria-d [Sat, 9 Nov 2013 07:41:46 +0000 (16:41 +0900)]
mem clock updated to 160 MHz
astoria-d [Sun, 3 Nov 2013 06:02:35 +0000 (15:02 +0900)]
vga working
astoria-d [Sun, 27 Oct 2013 03:13:18 +0000 (12:13 +0900)]
test image added
astoria-d [Sun, 27 Oct 2013 03:05:08 +0000 (12:05 +0900)]
ppu address reg set timing updated
astoria-d [Sun, 20 Oct 2013 01:41:43 +0000 (10:41 +0900)]
clean up
astoria-d [Sun, 20 Oct 2013 01:37:14 +0000 (10:37 +0900)]
clean up
astoria-d [Sun, 20 Oct 2013 01:21:28 +0000 (10:21 +0900)]
sdram control clean up
astoria-d [Sat, 19 Oct 2013 11:54:59 +0000 (20:54 +0900)]
sdram integration ok
astoria-d [Sat, 19 Oct 2013 04:53:34 +0000 (13:53 +0900)]
sdram controller integration
astoria-d [Mon, 14 Oct 2013 01:31:36 +0000 (10:31 +0900)]
vga work...
astoria-d [Sat, 12 Oct 2013 10:04:35 +0000 (19:04 +0900)]
vga output working...
astoria-d [Sat, 12 Oct 2013 00:49:08 +0000 (09:49 +0900)]
test vga output working...
astoria-d [Sat, 12 Oct 2013 00:32:17 +0000 (09:32 +0900)]
Merge branch 'master' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga
astoria-d [Sat, 12 Oct 2013 00:31:57 +0000 (09:31 +0900)]
vga output ok!!
astoria-d [Tue, 8 Oct 2013 02:32:12 +0000 (11:32 +0900)]
test update
astoria-d [Tue, 8 Oct 2013 02:22:25 +0000 (11:22 +0900)]
jmp (ind) test added.
astoria-d [Tue, 8 Oct 2013 02:10:33 +0000 (11:10 +0900)]
a5 instruction test added.
astoria-d [Mon, 7 Oct 2013 08:27:46 +0000 (17:27 +0900)]
a4 instructions regression test added.
astoria-d [Mon, 7 Oct 2013 06:56:25 +0000 (15:56 +0900)]
a2, a3 instruction test added.
astoria-d [Mon, 7 Oct 2013 03:10:08 +0000 (12:10 +0900)]
tsx instruction supported.
astoria-d [Sun, 6 Oct 2013 04:49:41 +0000 (13:49 +0900)]
vga woring...
astoria-d [Sat, 5 Oct 2013 08:26:36 +0000 (17:26 +0900)]
vga test proj added. still working...
astoria-d [Sat, 5 Oct 2013 01:24:05 +0000 (10:24 +0900)]
ppu render debug pin added but cyclone ii runs short of output pin!
astoria-d [Sat, 5 Oct 2013 01:02:49 +0000 (10:02 +0900)]
oam data read was ok???
previsous changed didn't need. restored.
astoria-d [Sat, 5 Oct 2013 00:36:55 +0000 (09:36 +0900)]
ppu integration and bug fix
astoria-d [Fri, 4 Oct 2013 08:47:42 +0000 (17:47 +0900)]
regression test single byte inst test ok
astoria-d [Fri, 4 Oct 2013 07:32:36 +0000 (16:32 +0900)]
- ppu render ram write timing updated.
- code clean up
astoria-d [Fri, 4 Oct 2013 06:39:30 +0000 (15:39 +0900)]
regression test update
astoria-d [Fri, 4 Oct 2013 05:48:04 +0000 (14:48 +0900)]
regression test update
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