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[motonesfpga/motonesfpga.git] / de0_cv_nes / ppu /
2016-09-14 astoria-dsprite pix processing ok!!! ppu-work-160915
2016-09-14 astoria-d@fcupdate status reg.
2016-09-14 astoria-d@fcsprite display implemented.
2016-09-14 astoria-d@fcsprite pattern shift ok.
2016-09-13 astoria-d@fccleaned up meaningless timing
2016-09-13 astoria-d@fcsprite pattern fetch ok
2016-09-13 astoria-d@fcsprite vram integration
2016-09-13 astoria-d@fcsprite copy ok.
2016-09-12 astoria-dsimplified sprite status.
2016-09-12 astoria-d@fcspr evaluation ok.
2016-09-12 astoria-d@fcoam clear ok
2016-09-12 astoria-d@fcsprite state machine added
2016-09-11 astoria-dbg display ok!!! ppu-work-160911
2016-09-11 astoria-dshift register timing changed.
2016-09-11 astoria-dwrong pattern shift timing.
2016-09-11 astoria-dvram timing update.
2016-09-11 astoria-dbg display not work. dbg counter added.
2016-09-10 astoria-dvga work.
2016-09-10 astoria-dvga ok.
2016-09-10 astoria-dstii debug start. vga display failed!!
2016-09-10 astoria-dwront param name fixed.
2016-09-10 astoria-dbg display done with rtl...
2016-09-10 astoria-dpalette bus separated.
2016-09-10 astoria-dbg pattern ok on rtl.
2016-09-10 astoria-drender working...
2016-09-10 astoria-dvram access cs set ok.
2016-09-10 astoria-dpos work...
2016-09-10 astoria-drender x, y reg set.
2016-09-10 astoria-dvga rendering start.
2016-09-10 astoria-dsprite ram added.
2016-09-10 astoria-dppu source dir created